opcodes/m32r-opc.c

   1 /* Generic opcode table support for targets using CGEN. -*- C -*-
   2    CGEN: Cpu tools GENerator
   3
   4 This file is used to generate m32r-opc.c.
   5
   6 Copyright (C) 1998 Free Software Foundation, Inc.
   7
   8 This file is part of the GNU Binutils and GDB, the GNU debugger.
   9
  10 This program is free software; you can redistribute it and/or modify
  11 it under the terms of the GNU General Public License as published by
  12 the Free Software Foundation; either version 2, or (at your option)
  13 any later version.
  14
  15 This program is distributed in the hope that it will be useful,
  16 but WITHOUT ANY WARRANTY; without even the implied warranty of
  17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  18 GNU General Public License for more details.
  19
  20 You should have received a copy of the GNU General Public License
  21 along with this program; if not, write to the Free Software
  22 Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */
  23
  24 #include "sysdep.h"
  25 #include <stdio.h>
  26 #include "ansidecl.h"
  27 #include "libiberty.h"
  28 #include "bfd.h"
  29 #include "symcat.h"
  30 #include "m32r-opc.h"
  31
  32 /* Look up instruction INSN_VALUE and extract its fields.
  33    If non-null INSN is the insn table entry.
  34    Otherwise INSN_VALUE is examined to compute it.
  35    LENGTH is the bit length of INSN_VALUE if known, otherwise 0.
  36    ALIAS_P is non-zero if alias insns are to be included in the search.
  37    The result a pointer to the insn table entry, or NULL if the instruction
  38    wasn't recognized.  */
  39
  40 const CGEN_INSN *
  41 m32r_cgen_lookup_insn (insn, insn_value, length, fields, alias_p)
  42      const CGEN_INSN *insn;
  43      cgen_insn_t insn_value;
  44      int length;
  45      CGEN_FIELDS *fields;
  46 {
  47   char buf[16];
  48
  49   if (!insn)
  50     {
  51       const CGEN_INSN_LIST *insn_list;
  52
  53 #ifdef CGEN_INT_INSN
  54       switch (length)
  55         {
  56         case 8:
  57           buf[0] = insn_value;
  58           break;
  59         case 16:
  60           if (cgen_current_endian == CGEN_ENDIAN_BIG)
  61             bfd_putb16 (insn_value, buf);
  62           else
  63             bfd_putl16 (insn_value, buf);
  64           break;
  65         case 32:
  66           if (cgen_current_endian == CGEN_ENDIAN_BIG)
  67             bfd_putb32 (insn_value, buf);
  68           else
  69             bfd_putl32 (insn_value, buf);
  70           break;
  71         default:
  72           abort ();
  73         }
  74 #else
  75       abort (); /* FIXME: unfinished */
  76 #endif
  77
  78       /* The instructions are stored in hash lists.
  79          Pick the first one and keep trying until we find the right one.  */
  80
  81       insn_list = CGEN_DIS_LOOKUP_INSN (buf, insn_value);
  82       while (insn_list != NULL)
  83         {
  84           insn = insn_list->insn;
  85
  86           if (alias_p
  87               || ! CGEN_INSN_ATTR (insn, CGEN_INSN_ALIAS))
  88             {
  89               /* Basic bit mask must be correct.  */
  90               /* ??? May wish to allow target to defer this check until the
  91                  extract handler.  */
  92               if ((insn_value & CGEN_INSN_MASK (insn)) == CGEN_INSN_VALUE (insn))
  93                 {
  94                   length = (*CGEN_EXTRACT_FN (insn)) (insn, NULL, insn_value, fields);
  95                   if (length > 0)
  96                     return insn;
  97                 }
  98             }
  99
 100           insn_list = CGEN_DIS_NEXT_INSN (insn_list);
 101         }
 102     }
 103   else
 104     {
 105       /* Sanity check: can't pass an alias insn if ! alias_p.  */
 106       if (! alias_p
 107           && CGEN_INSN_ATTR (insn, CGEN_INSN_ALIAS))
 108         abort ();
 109
 110       length = (*CGEN_EXTRACT_FN (insn)) (insn, NULL, insn_value, fields);
 111       if (length > 0)
 112         return insn;
 113     }
 114
 115   return NULL;
 116 }
 117
 118 /* Fill in the operand instances used by insn INSN_VALUE.
 119    If non-null INS is the insn table entry.
 120    Otherwise INSN_VALUE is examined to compute it.
 121    LENGTH is the number of bits in INSN_VALUE if known, otherwise 0.
 122    INDICES is a pointer to a buffer of MAX_OPERAND_INSTANCES ints to be filled
 123    in.
 124    The result a pointer to the insn table entry, or NULL if the instruction
 125    wasn't recognized.  */
 126
 127 const CGEN_INSN *
 128 m32r_cgen_get_insn_operands (insn, insn_value, length, indices)
 129      const CGEN_INSN *insn;
 130      cgen_insn_t insn_value;
 131      int length;
 132      int *indices;
 133 {
 134   CGEN_FIELDS fields;
 135   const CGEN_OPERAND_INSTANCE *opinst;
 136   int i;
 137
 138   /* FIXME: ALIAS insns are in transition from being record in the insn table
 139      to being recorded separately as macros.  They don't have semantic code
 140      so they can't be used here.  Thus we currently always ignore the INSN
 141      argument.  */
 142   insn = m32r_cgen_lookup_insn (NULL, insn_value, length, &fields, 0);
 143   if (! insn)
 144     return NULL;
 145
 146   for (i = 0, opinst = CGEN_INSN_OPERANDS (insn);
 147        opinst != NULL
 148          && CGEN_OPERAND_INSTANCE_TYPE (opinst) != CGEN_OPERAND_INSTANCE_END;
 149        ++i, ++opinst)
 150     {
 151       const CGEN_OPERAND *op = CGEN_OPERAND_INSTANCE_OPERAND (opinst);
 152       if (op == NULL)
 153         indices[i] = CGEN_OPERAND_INSTANCE_INDEX (opinst);
 154       else
 155         indices[i] = m32r_cgen_get_operand (CGEN_OPERAND_INDEX (op), &fields);
 156     }
 157
 158   return insn;
 159 }
 160 /* Attributes.  */
 161
 162 static const CGEN_ATTR_ENTRY MACH_attr[] =
 163 {
 164   { "m32r", MACH_M32R },
 165 /* start-sanitize-m32rx */
 166   { "m32rx", MACH_M32RX },
 167 /* end-sanitize-m32rx */
 168   { "max", MACH_MAX },
 169   { 0, 0 }
 170 };
 171
 172 /* start-sanitize-m32rx */
 173 static const CGEN_ATTR_ENTRY PIPE_attr[] =
 174 {
 175   { "NONE", PIPE_NONE },
 176   { "O", PIPE_O },
 177   { "S", PIPE_S },
 178   { "OS", PIPE_OS },
 179   { 0, 0 }
 180 };
 181
 182 /* end-sanitize-m32rx */
 183 const CGEN_ATTR_TABLE m32r_cgen_operand_attr_table[] =
 184 {
 185   { "ABS-ADDR", NULL },
 186   { "FAKE", NULL },
 187   { "HASH-PREFIX", NULL },
 188   { "NEGATIVE", NULL },
 189   { "PC", NULL },
 190   { "PCREL-ADDR", NULL },
 191   { "RELAX", NULL },
 192   { "RELOC", NULL },
 193   { "SIGN-OPT", NULL },
 194   { "UNSIGNED", NULL },
 195   { 0, 0 }
 196 };
 197
 198 const CGEN_ATTR_TABLE m32r_cgen_insn_attr_table[] =
 199 {
 200   { "MACH", & MACH_attr[0] },
 201 /* start-sanitize-m32rx */
 202   { "PIPE", & PIPE_attr[0] },
 203 /* end-sanitize-m32rx */
 204   { "ALIAS", NULL },
 205   { "COND-CTI", NULL },
 206   { "FILL-SLOT", NULL },
 207   { "PARALLEL", NULL },
 208   { "RELAX", NULL },
 209   { "RELAXABLE", NULL },
 210   { "UNCOND-CTI", NULL },
 211   { 0, 0 }
 212 };
 213
 214 CGEN_KEYWORD_ENTRY m32r_cgen_opval_h_gr_entries[] =
 215 {
 216   { "fp", 13 },
 217   { "lr", 14 },
 218   { "sp", 15 },
 219   { "r0", 0 },
 220   { "r1", 1 },
 221   { "r2", 2 },
 222   { "r3", 3 },
 223   { "r4", 4 },
 224   { "r5", 5 },
 225   { "r6", 6 },
 226   { "r7", 7 },
 227   { "r8", 8 },
 228   { "r9", 9 },
 229   { "r10", 10 },
 230   { "r11", 11 },
 231   { "r12", 12 },
 232   { "r13", 13 },
 233   { "r14", 14 },
 234   { "r15", 15 }
 235 };
 236
 237 CGEN_KEYWORD m32r_cgen_opval_h_gr =
 238 {
 239   & m32r_cgen_opval_h_gr_entries[0],
 240   19
 241 };
 242
 243 CGEN_KEYWORD_ENTRY m32r_cgen_opval_h_cr_entries[] =
 244 {
 245   { "psw", 0 },
 246   { "cbr", 1 },
 247   { "spi", 2 },
 248   { "spu", 3 },
 249   { "bpc", 6 },
 250   { "cr0", 0 },
 251   { "cr1", 1 },
 252   { "cr2", 2 },
 253   { "cr3", 3 },
 254   { "cr4", 4 },
 255   { "cr5", 5 },
 256   { "cr6", 6 }
 257 };
 258
 259 CGEN_KEYWORD m32r_cgen_opval_h_cr =
 260 {
 261   & m32r_cgen_opval_h_cr_entries[0],
 262   12
 263 };
 264
 265 /* start-sanitize-m32rx */
 266 CGEN_KEYWORD_ENTRY m32r_cgen_opval_h_accums_entries[] =
 267 {
 268   { "a0", 0 },
 269   { "a1", 1 }
 270 };
 271
 272 CGEN_KEYWORD m32r_cgen_opval_h_accums =
 273 {
 274   & m32r_cgen_opval_h_accums_entries[0],
 275   2
 276 };
 277
 278 /* end-sanitize-m32rx */
 279
 280 /* The hardware table.  */
 281
 282 #define HW_ENT(n) m32r_cgen_hw_entries[n]
 283 static const CGEN_HW_ENTRY m32r_cgen_hw_entries[] =
 284 {
 285   { HW_H_PC, & HW_ENT (HW_H_PC + 1), "h-pc", CGEN_ASM_KEYWORD, (PTR) 0 },
 286   { HW_H_MEMORY, & HW_ENT (HW_H_MEMORY + 1), "h-memory", CGEN_ASM_KEYWORD, (PTR) 0 },
 287   { HW_H_SINT, & HW_ENT (HW_H_SINT + 1), "h-sint", CGEN_ASM_KEYWORD, (PTR) 0 },
 288   { HW_H_UINT, & HW_ENT (HW_H_UINT + 1), "h-uint", CGEN_ASM_KEYWORD, (PTR) 0 },
 289   { HW_H_ADDR, & HW_ENT (HW_H_ADDR + 1), "h-addr", CGEN_ASM_KEYWORD, (PTR) 0 },
 290   { HW_H_IADDR, & HW_ENT (HW_H_IADDR + 1), "h-iaddr", CGEN_ASM_KEYWORD, (PTR) 0 },
 291   { HW_H_HI16, & HW_ENT (HW_H_HI16 + 1), "h-hi16", CGEN_ASM_KEYWORD, (PTR) 0 },
 292   { HW_H_SLO16, & HW_ENT (HW_H_SLO16 + 1), "h-slo16", CGEN_ASM_KEYWORD, (PTR) 0 },
 293   { HW_H_ULO16, & HW_ENT (HW_H_ULO16 + 1), "h-ulo16", CGEN_ASM_KEYWORD, (PTR) 0 },
 294   { HW_H_GR, & HW_ENT (HW_H_GR + 1), "h-gr", CGEN_ASM_KEYWORD, (PTR) & m32r_cgen_opval_h_gr },
 295   { HW_H_CR, & HW_ENT (HW_H_CR + 1), "h-cr", CGEN_ASM_KEYWORD, (PTR) & m32r_cgen_opval_h_cr },
 296   { HW_H_ACCUM, & HW_ENT (HW_H_ACCUM + 1), "h-accum", CGEN_ASM_KEYWORD, (PTR) 0 },
 297 /* start-sanitize-m32rx */
 298   { HW_H_ACCUMS, & HW_ENT (HW_H_ACCUMS + 1), "h-accums", CGEN_ASM_KEYWORD, (PTR) & m32r_cgen_opval_h_accums },
 299 /* end-sanitize-m32rx */
 300 /* start-sanitize-m32rx */
 301   { HW_H_ABORT, & HW_ENT (HW_H_ABORT + 1), "h-abort", CGEN_ASM_KEYWORD, (PTR) 0 },
 302 /* end-sanitize-m32rx */
 303   { HW_H_COND, & HW_ENT (HW_H_COND + 1), "h-cond", CGEN_ASM_KEYWORD, (PTR) 0 },
 304   { HW_H_SM, & HW_ENT (HW_H_SM + 1), "h-sm", CGEN_ASM_KEYWORD, (PTR) 0 },
 305   { HW_H_BSM, & HW_ENT (HW_H_BSM + 1), "h-bsm", CGEN_ASM_KEYWORD, (PTR) 0 },
 306   { HW_H_IE, & HW_ENT (HW_H_IE + 1), "h-ie", CGEN_ASM_KEYWORD, (PTR) 0 },
 307   { HW_H_BIE, & HW_ENT (HW_H_BIE + 1), "h-bie", CGEN_ASM_KEYWORD, (PTR) 0 },
 308   { HW_H_BCOND, & HW_ENT (HW_H_BCOND + 1), "h-bcond", CGEN_ASM_KEYWORD, (PTR) 0 },
 309   { HW_H_BPC, & HW_ENT (HW_H_BPC + 1), "h-bpc", CGEN_ASM_KEYWORD, (PTR) 0 },
 310   { HW_H_LOCK, & HW_ENT (HW_H_LOCK + 1), "h-lock", CGEN_ASM_KEYWORD, (PTR) 0 },
 311   { 0 }
 312 };
 313
 314 /* The operand table.  */
 315
 316 #define OPERAND(op) CONCAT2 (M32R_OPERAND_,op)
 317 #define OP_ENT(op) m32r_cgen_operand_table[OPERAND (op)]
 318
 319 const CGEN_OPERAND m32r_cgen_operand_table[MAX_OPERANDS] =
 320 {
 321 /* pc: program counter */
 322   { "pc", & HW_ENT (HW_H_PC), 0, 0,
 323     { 0, 0|(1<<CGEN_OPERAND_FAKE)|(1<<CGEN_OPERAND_PC), { 0 } }  },
 324 /* sr: source register */
 325   { "sr", & HW_ENT (HW_H_GR), 12, 4,
 326     { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } }  },
 327 /* dr: destination register */
 328   { "dr", & HW_ENT (HW_H_GR), 4, 4,
 329     { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } }  },
 330 /* src1: source register 1 */
 331   { "src1", & HW_ENT (HW_H_GR), 4, 4,
 332     { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } }  },
 333 /* src2: source register 2 */
 334   { "src2", & HW_ENT (HW_H_GR), 12, 4,
 335     { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } }  },
 336 /* scr: source control register */
 337   { "scr", & HW_ENT (HW_H_CR), 12, 4,
 338     { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } }  },
 339 /* dcr: destination control register */
 340   { "dcr", & HW_ENT (HW_H_CR), 4, 4,
 341     { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } }  },
 342 /* simm8: 8 bit signed immediate */
 343   { "simm8", & HW_ENT (HW_H_SINT), 8, 8,
 344     { 0, 0|(1<<CGEN_OPERAND_HASH_PREFIX), { 0 } }  },
 345 /* simm16: 16 bit signed immediate */
 346   { "simm16", & HW_ENT (HW_H_SINT), 16, 16,
 347     { 0, 0|(1<<CGEN_OPERAND_HASH_PREFIX), { 0 } }  },
 348 /* uimm4: 4 bit trap number */
 349   { "uimm4", & HW_ENT (HW_H_UINT), 12, 4,
 350     { 0, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_UNSIGNED), { 0 } }  },
 351 /* uimm5: 5 bit shift count */
 352   { "uimm5", & HW_ENT (HW_H_UINT), 11, 5,
 353     { 0, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_UNSIGNED), { 0 } }  },
 354 /* uimm16: 16 bit unsigned immediate */
 355   { "uimm16", & HW_ENT (HW_H_UINT), 16, 16,
 356     { 0, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_UNSIGNED), { 0 } }  },
 357 /* start-sanitize-m32rx */
 358 /* imm1: 1 bit immediate */
 359   { "imm1", & HW_ENT (HW_H_UINT), 15, 1,
 360     { 0, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_UNSIGNED), { 0 } }  },
 361 /* end-sanitize-m32rx */
 362 /* start-sanitize-m32rx */
 363 /* accd: accumulator destination register */
 364   { "accd", & HW_ENT (HW_H_ACCUMS), 4, 2,
 365     { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } }  },
 366 /* end-sanitize-m32rx */
 367 /* start-sanitize-m32rx */
 368 /* accs: accumulator source register */
 369   { "accs", & HW_ENT (HW_H_ACCUMS), 12, 2,
 370     { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } }  },
 371 /* end-sanitize-m32rx */
 372 /* start-sanitize-m32rx */
 373 /* acc: accumulator reg (d) */
 374   { "acc", & HW_ENT (HW_H_ACCUMS), 8, 1,
 375     { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } }  },
 376 /* end-sanitize-m32rx */
 377 /* hash: # prefix */
 378   { "hash", & HW_ENT (HW_H_SINT), 0, 0,
 379     { 0, 0, { 0 } }  },
 380 /* hi16: high 16 bit immediate, sign optional */
 381   { "hi16", & HW_ENT (HW_H_HI16), 16, 16,
 382     { 0, 0|(1<<CGEN_OPERAND_SIGN_OPT)|(1<<CGEN_OPERAND_UNSIGNED), { 0 } }  },
 383 /* slo16: 16 bit signed immediate, for low() */
 384   { "slo16", & HW_ENT (HW_H_SLO16), 16, 16,
 385     { 0, 0, { 0 } }  },
 386 /* ulo16: 16 bit unsigned immediate, for low() */
 387   { "ulo16", & HW_ENT (HW_H_ULO16), 16, 16,
 388     { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } }  },
 389 /* uimm24: 24 bit address */
 390   { "uimm24", & HW_ENT (HW_H_ADDR), 8, 24,
 391     { 0, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_RELOC)|(1<<CGEN_OPERAND_ABS_ADDR)|(1<<CGEN_OPERAND_UNSIGNED), { 0 } }  },
 392 /* disp8: 8 bit displacement */
 393   { "disp8", & HW_ENT (HW_H_IADDR), 8, 8,
 394     { 0, 0|(1<<CGEN_OPERAND_RELAX)|(1<<CGEN_OPERAND_RELOC)|(1<<CGEN_OPERAND_PCREL_ADDR), { 0 } }  },
 395 /* disp16: 16 bit displacement */
 396   { "disp16", & HW_ENT (HW_H_IADDR), 16, 16,
 397     { 0, 0|(1<<CGEN_OPERAND_RELOC)|(1<<CGEN_OPERAND_PCREL_ADDR), { 0 } }  },
 398 /* disp24: 24 bit displacement */
 399   { "disp24", & HW_ENT (HW_H_IADDR), 8, 24,
 400     { 0, 0|(1<<CGEN_OPERAND_RELAX)|(1<<CGEN_OPERAND_RELOC)|(1<<CGEN_OPERAND_PCREL_ADDR), { 0 } }  },
 401 /* condbit: condition bit */
 402   { "condbit", & HW_ENT (HW_H_COND), 0, 0,
 403     { 0, 0|(1<<CGEN_OPERAND_FAKE), { 0 } }  },
 404 /* accum: accumulator */
 405   { "accum", & HW_ENT (HW_H_ACCUM), 0, 0,
 406     { 0, 0|(1<<CGEN_OPERAND_FAKE), { 0 } }  },
 407 };
 408
 409 /* Operand references.  */
 410
 411 #define INPUT CGEN_OPERAND_INSTANCE_INPUT
 412 #define OUTPUT CGEN_OPERAND_INSTANCE_OUTPUT
 413
 414 static const CGEN_OPERAND_INSTANCE fmt_0_add_ops[] = {
 415   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
 416   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
 417   { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
 418   { 0 }
 419 };
 420
 421 static const CGEN_OPERAND_INSTANCE fmt_1_add3_ops[] = {
 422   { INPUT, & HW_ENT (HW_H_SLO16), CGEN_MODE_HI, & OP_ENT (SLO16), 0 },
 423   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
 424   { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
 425   { 0 }
 426 };
 427
 428 static const CGEN_OPERAND_INSTANCE fmt_2_and3_ops[] = {
 429   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
 430   { INPUT, & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (UIMM16), 0 },
 431   { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
 432   { 0 }
 433 };
 434
 435 static const CGEN_OPERAND_INSTANCE fmt_3_or3_ops[] = {
 436   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
 437   { INPUT, & HW_ENT (HW_H_ULO16), CGEN_MODE_UHI, & OP_ENT (ULO16), 0 },
 438   { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
 439   { 0 }
 440 };
 441
 442 static const CGEN_OPERAND_INSTANCE fmt_4_addi_ops[] = {
 443   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
 444   { INPUT, & HW_ENT (HW_H_SINT), CGEN_MODE_SI, & OP_ENT (SIMM8), 0 },
 445   { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
 446   { 0 }
 447 };
 448
 449 static const CGEN_OPERAND_INSTANCE fmt_5_addv_ops[] = {
 450   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
 451   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
 452   { OUTPUT, & HW_ENT (HW_H_COND), CGEN_MODE_UBI, 0, 0 },
 453   { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
 454   { 0 }
 455 };
 456
 457 static const CGEN_OPERAND_INSTANCE fmt_6_addv3_ops[] = {
 458   { INPUT, & HW_ENT (HW_H_SINT), CGEN_MODE_SI, & OP_ENT (SIMM16), 0 },
 459   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
 460   { OUTPUT, & HW_ENT (HW_H_COND), CGEN_MODE_UBI, 0, 0 },
 461   { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
 462   { 0 }
 463 };
 464
 465 static const CGEN_OPERAND_INSTANCE fmt_7_addx_ops[] = {
 466   { INPUT, & HW_ENT (HW_H_COND), CGEN_MODE_UBI, 0, 0 },
 467   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
 468   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
 469   { OUTPUT, & HW_ENT (HW_H_COND), CGEN_MODE_UBI, 0, 0 },
 470   { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
 471   { 0 }
 472 };
 473
 474 static const CGEN_OPERAND_INSTANCE fmt_8_bc8_ops[] = {
 475   { INPUT, & HW_ENT (HW_H_COND), CGEN_MODE_UBI, 0, 0 },
 476   { INPUT, & HW_ENT (HW_H_IADDR), CGEN_MODE_VM, & OP_ENT (DISP8), 0 },
 477   { OUTPUT, & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0 },
 478   { 0 }
 479 };
 480
 481 static const CGEN_OPERAND_INSTANCE fmt_10_bc24_ops[] = {
 482   { INPUT, & HW_ENT (HW_H_COND), CGEN_MODE_UBI, 0, 0 },
 483   { INPUT, & HW_ENT (HW_H_IADDR), CGEN_MODE_VM, & OP_ENT (DISP24), 0 },
 484   { OUTPUT, & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0 },
 485   { 0 }
 486 };
 487
 488 static const CGEN_OPERAND_INSTANCE fmt_12_beq_ops[] = {
 489   { INPUT, & HW_ENT (HW_H_IADDR), CGEN_MODE_VM, & OP_ENT (DISP16), 0 },
 490   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0 },
 491   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0 },
 492   { OUTPUT, & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0 },
 493   { 0 }
 494 };
 495
 496 static const CGEN_OPERAND_INSTANCE fmt_13_beqz_ops[] = {
 497   { INPUT, & HW_ENT (HW_H_IADDR), CGEN_MODE_VM, & OP_ENT (DISP16), 0 },
 498   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0 },
 499   { OUTPUT, & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0 },
 500   { 0 }
 501 };
 502
 503 static const CGEN_OPERAND_INSTANCE fmt_14_bl8_ops[] = {
 504   { INPUT, & HW_ENT (HW_H_IADDR), CGEN_MODE_VM, & OP_ENT (DISP8), 0 },
 505   { INPUT, & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0 },
 506   { OUTPUT, & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0 },
 507   { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 14 },
 508   { 0 }
 509 };
 510
 511 static const CGEN_OPERAND_INSTANCE fmt_15_bl24_ops[] = {
 512   { INPUT, & HW_ENT (HW_H_IADDR), CGEN_MODE_VM, & OP_ENT (DISP24), 0 },
 513   { INPUT, & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0 },
 514   { OUTPUT, & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0 },
 515   { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 14 },
 516   { 0 }
 517 };
 518
 519 static const CGEN_OPERAND_INSTANCE fmt_16_bcl8_ops[] = {
 520   { INPUT, & HW_ENT (HW_H_COND), CGEN_MODE_UBI, 0, 0 },
 521   { INPUT, & HW_ENT (HW_H_IADDR), CGEN_MODE_VM, & OP_ENT (DISP8), 0 },
 522   { INPUT, & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0 },
 523   { OUTPUT, & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0 },
 524   { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 14 },
 525   { 0 }
 526 };
 527
 528 static const CGEN_OPERAND_INSTANCE fmt_17_bcl24_ops[] = {
 529   { INPUT, & HW_ENT (HW_H_COND), CGEN_MODE_UBI, 0, 0 },
 530   { INPUT, & HW_ENT (HW_H_IADDR), CGEN_MODE_VM, & OP_ENT (DISP24), 0 },
 531   { INPUT, & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0 },
 532   { OUTPUT, & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0 },
 533   { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 14 },
 534   { 0 }
 535 };
 536
 537 static const CGEN_OPERAND_INSTANCE fmt_18_bra8_ops[] = {
 538   { INPUT, & HW_ENT (HW_H_IADDR), CGEN_MODE_VM, & OP_ENT (DISP8), 0 },
 539   { OUTPUT, & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0 },
 540   { 0 }
 541 };
 542
 543 static const CGEN_OPERAND_INSTANCE fmt_19_bra24_ops[] = {
 544   { INPUT, & HW_ENT (HW_H_IADDR), CGEN_MODE_VM, & OP_ENT (DISP24), 0 },
 545   { OUTPUT, & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0 },
 546   { 0 }
 547 };
 548
 549 static const CGEN_OPERAND_INSTANCE fmt_20_cmp_ops[] = {
 550   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0 },
 551   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0 },
 552   { OUTPUT, & HW_ENT (HW_H_COND), CGEN_MODE_UBI, 0, 0 },
 553   { 0 }
 554 };
 555
 556 static const CGEN_OPERAND_INSTANCE fmt_21_cmpi_ops[] = {
 557   { INPUT, & HW_ENT (HW_H_SINT), CGEN_MODE_SI, & OP_ENT (SIMM16), 0 },
 558   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0 },
 559   { OUTPUT, & HW_ENT (HW_H_COND), CGEN_MODE_UBI, 0, 0 },
 560   { 0 }
 561 };
 562
 563 static const CGEN_OPERAND_INSTANCE fmt_22_cmpui_ops[] = {
 564   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0 },
 565   { INPUT, & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (UIMM16), 0 },
 566   { OUTPUT, & HW_ENT (HW_H_COND), CGEN_MODE_UBI, 0, 0 },
 567   { 0 }
 568 };
 569
 570 static const CGEN_OPERAND_INSTANCE fmt_23_cmpz_ops[] = {
 571   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0 },
 572   { OUTPUT, & HW_ENT (HW_H_COND), CGEN_MODE_UBI, 0, 0 },
 573   { 0 }
 574 };
 575
 576 static const CGEN_OPERAND_INSTANCE fmt_24_div_ops[] = {
 577   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
 578   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
 579   { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
 580   { 0 }
 581 };
 582
 583 static const CGEN_OPERAND_INSTANCE fmt_25_jc_ops[] = {
 584   { INPUT, & HW_ENT (HW_H_COND), CGEN_MODE_UBI, 0, 0 },
 585   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
 586   { OUTPUT, & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0 },
 587   { 0 }
 588 };
 589
 590 static const CGEN_OPERAND_INSTANCE fmt_26_jl_ops[] = {
 591   { INPUT, & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0 },
 592   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
 593   { OUTPUT, & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0 },
 594   { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 14 },
 595   { 0 }
 596 };
 597
 598 static const CGEN_OPERAND_INSTANCE fmt_27_jmp_ops[] = {
 599   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
 600   { OUTPUT, & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0 },
 601   { 0 }
 602 };
 603
 604 static const CGEN_OPERAND_INSTANCE fmt_28_ld_ops[] = {
 605   { INPUT, & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0 },
 606   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
 607   { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
 608   { 0 }
 609 };
 610
 611 static const CGEN_OPERAND_INSTANCE fmt_30_ld_d_ops[] = {
 612   { INPUT, & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0 },
 613   { INPUT, & HW_ENT (HW_H_SLO16), CGEN_MODE_HI, & OP_ENT (SLO16), 0 },
 614   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
 615   { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
 616   { 0 }
 617 };
 618
 619 static const CGEN_OPERAND_INSTANCE fmt_32_ldb_ops[] = {
 620   { INPUT, & HW_ENT (HW_H_MEMORY), CGEN_MODE_QI, 0, 0 },
 621   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
 622   { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
 623   { 0 }
 624 };
 625
 626 static const CGEN_OPERAND_INSTANCE fmt_33_ldb_d_ops[] = {
 627   { INPUT, & HW_ENT (HW_H_MEMORY), CGEN_MODE_QI, 0, 0 },
 628   { INPUT, & HW_ENT (HW_H_SLO16), CGEN_MODE_HI, & OP_ENT (SLO16), 0 },
 629   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
 630   { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
 631   { 0 }
 632 };
 633
 634 static const CGEN_OPERAND_INSTANCE fmt_34_ldh_ops[] = {
 635   { INPUT, & HW_ENT (HW_H_MEMORY), CGEN_MODE_HI, 0, 0 },
 636   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
 637   { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
 638   { 0 }
 639 };
 640
 641 static const CGEN_OPERAND_INSTANCE fmt_35_ldh_d_ops[] = {
 642   { INPUT, & HW_ENT (HW_H_MEMORY), CGEN_MODE_HI, 0, 0 },
 643   { INPUT, & HW_ENT (HW_H_SLO16), CGEN_MODE_HI, & OP_ENT (SLO16), 0 },
 644   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
 645   { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
 646   { 0 }
 647 };
 648
 649 static const CGEN_OPERAND_INSTANCE fmt_36_ld_plus_ops[] = {
 650   { INPUT, & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0 },
 651   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
 652   { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
 653   { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
 654   { 0 }
 655 };
 656
 657 static const CGEN_OPERAND_INSTANCE fmt_37_ld24_ops[] = {
 658   { INPUT, & HW_ENT (HW_H_ADDR), CGEN_MODE_VM, & OP_ENT (UIMM24), 0 },
 659   { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
 660   { 0 }
 661 };
 662
 663 static const CGEN_OPERAND_INSTANCE fmt_38_ldi8_ops[] = {
 664   { INPUT, & HW_ENT (HW_H_SINT), CGEN_MODE_SI, & OP_ENT (SIMM8), 0 },
 665   { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
 666   { 0 }
 667 };
 668
 669 static const CGEN_OPERAND_INSTANCE fmt_39_ldi16_ops[] = {
 670   { INPUT, & HW_ENT (HW_H_SLO16), CGEN_MODE_HI, & OP_ENT (SLO16), 0 },
 671   { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
 672   { 0 }
 673 };
 674
 675 static const CGEN_OPERAND_INSTANCE fmt_40_lock_ops[] = {
 676   { INPUT, & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0 },
 677   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
 678   { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
 679   { OUTPUT, & HW_ENT (HW_H_LOCK), CGEN_MODE_UBI, 0, 0 },
 680   { 0 }
 681 };
 682
 683 static const CGEN_OPERAND_INSTANCE fmt_41_machi_ops[] = {
 684   { INPUT, & HW_ENT (HW_H_ACCUM), CGEN_MODE_DI, 0, 0 },
 685   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0 },
 686   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0 },
 687   { OUTPUT, & HW_ENT (HW_H_ACCUM), CGEN_MODE_DI, 0, 0 },
 688   { 0 }
 689 };
 690
 691 static const CGEN_OPERAND_INSTANCE fmt_42_machi_a_ops[] = {
 692   { INPUT, & HW_ENT (HW_H_ACCUMS), CGEN_MODE_DI, & OP_ENT (ACC), 0 },
 693   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0 },
 694   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0 },
 695   { OUTPUT, & HW_ENT (HW_H_ACCUMS), CGEN_MODE_DI, & OP_ENT (ACC), 0 },
 696   { 0 }
 697 };
 698
 699 static const CGEN_OPERAND_INSTANCE fmt_43_mulhi_ops[] = {
 700   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0 },
 701   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0 },
 702   { OUTPUT, & HW_ENT (HW_H_ACCUM), CGEN_MODE_DI, 0, 0 },
 703   { 0 }
 704 };
 705
 706 static const CGEN_OPERAND_INSTANCE fmt_44_mulhi_a_ops[] = {
 707   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0 },
 708   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0 },
 709   { OUTPUT, & HW_ENT (HW_H_ACCUMS), CGEN_MODE_DI, & OP_ENT (ACC), 0 },
 710   { 0 }
 711 };
 712
 713 static const CGEN_OPERAND_INSTANCE fmt_45_mv_ops[] = {
 714   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
 715   { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
 716   { 0 }
 717 };
 718
 719 static const CGEN_OPERAND_INSTANCE fmt_46_mvfachi_ops[] = {
 720   { INPUT, & HW_ENT (HW_H_ACCUM), CGEN_MODE_DI, 0, 0 },
 721   { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
 722   { 0 }
 723 };
 724
 725 static const CGEN_OPERAND_INSTANCE fmt_47_mvfachi_a_ops[] = {
 726   { INPUT, & HW_ENT (HW_H_ACCUMS), CGEN_MODE_DI, & OP_ENT (ACCS), 0 },
 727   { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
 728   { 0 }
 729 };
 730
 731 static const CGEN_OPERAND_INSTANCE fmt_48_mvfc_ops[] = {
 732   { INPUT, & HW_ENT (HW_H_CR), CGEN_MODE_USI, & OP_ENT (SCR), 0 },
 733   { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
 734   { 0 }
 735 };
 736
 737 static const CGEN_OPERAND_INSTANCE fmt_49_mvtachi_ops[] = {
 738   { INPUT, & HW_ENT (HW_H_ACCUM), CGEN_MODE_DI, 0, 0 },
 739   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0 },
 740   { OUTPUT, & HW_ENT (HW_H_ACCUM), CGEN_MODE_DI, 0, 0 },
 741   { 0 }
 742 };
 743
 744 static const CGEN_OPERAND_INSTANCE fmt_50_mvtachi_a_ops[] = {
 745   { INPUT, & HW_ENT (HW_H_ACCUMS), CGEN_MODE_DI, & OP_ENT (ACCS), 0 },
 746   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0 },
 747   { OUTPUT, & HW_ENT (HW_H_ACCUMS), CGEN_MODE_DI, & OP_ENT (ACCS), 0 },
 748   { 0 }
 749 };
 750
 751 static const CGEN_OPERAND_INSTANCE fmt_51_mvtc_ops[] = {
 752   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
 753   { OUTPUT, & HW_ENT (HW_H_CR), CGEN_MODE_USI, & OP_ENT (DCR), 0 },
 754   { 0 }
 755 };
 756
 757 static const CGEN_OPERAND_INSTANCE fmt_53_rac_ops[] = {
 758   { INPUT, & HW_ENT (HW_H_ACCUM), CGEN_MODE_DI, 0, 0 },
 759   { OUTPUT, & HW_ENT (HW_H_ACCUM), CGEN_MODE_DI, 0, 0 },
 760   { 0 }
 761 };
 762
 763 static const CGEN_OPERAND_INSTANCE fmt_56_rac_dsi_ops[] = {
 764   { INPUT, & HW_ENT (HW_H_ACCUMS), CGEN_MODE_DI, & OP_ENT (ACCS), 0 },
 765   { INPUT, & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (IMM1), 0 },
 766   { OUTPUT, & HW_ENT (HW_H_ACCUMS), CGEN_MODE_DI, & OP_ENT (ACCD), 0 },
 767   { 0 }
 768 };
 769
 770 static const CGEN_OPERAND_INSTANCE fmt_57_rte_ops[] = {
 771   { INPUT, & HW_ENT (HW_H_BCOND), CGEN_MODE_VM, 0, 0 },
 772   { INPUT, & HW_ENT (HW_H_BIE), CGEN_MODE_VM, 0, 0 },
 773   { INPUT, & HW_ENT (HW_H_BPC), CGEN_MODE_VM, 0, 0 },
 774   { INPUT, & HW_ENT (HW_H_BSM), CGEN_MODE_VM, 0, 0 },
 775   { OUTPUT, & HW_ENT (HW_H_COND), CGEN_MODE_UBI, 0, 0 },
 776   { OUTPUT, & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0 },
 777   { OUTPUT, & HW_ENT (HW_H_IE), CGEN_MODE_VM, 0, 0 },
 778   { OUTPUT, & HW_ENT (HW_H_SM), CGEN_MODE_VM, 0, 0 },
 779   { 0 }
 780 };
 781
 782 static const CGEN_OPERAND_INSTANCE fmt_58_seth_ops[] = {
 783   { INPUT, & HW_ENT (HW_H_HI16), CGEN_MODE_UHI, & OP_ENT (HI16), 0 },
 784   { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
 785   { 0 }
 786 };
 787
 788 static const CGEN_OPERAND_INSTANCE fmt_59_sll3_ops[] = {
 789   { INPUT, & HW_ENT (HW_H_SINT), CGEN_MODE_SI, & OP_ENT (SIMM16), 0 },
 790   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
 791   { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
 792   { 0 }
 793 };
 794
 795 static const CGEN_OPERAND_INSTANCE fmt_60_slli_ops[] = {
 796   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
 797   { INPUT, & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (UIMM5), 0 },
 798   { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
 799   { 0 }
 800 };
 801
 802 static const CGEN_OPERAND_INSTANCE fmt_61_st_ops[] = {
 803   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0 },
 804   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0 },
 805   { OUTPUT, & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0 },
 806   { 0 }
 807 };
 808
 809 static const CGEN_OPERAND_INSTANCE fmt_63_st_d_ops[] = {
 810   { INPUT, & HW_ENT (HW_H_SLO16), CGEN_MODE_HI, & OP_ENT (SLO16), 0 },
 811   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0 },
 812   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0 },
 813   { OUTPUT, & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0 },
 814   { 0 }
 815 };
 816
 817 static const CGEN_OPERAND_INSTANCE fmt_65_stb_ops[] = {
 818   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0 },
 819   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0 },
 820   { OUTPUT, & HW_ENT (HW_H_MEMORY), CGEN_MODE_QI, 0, 0 },
 821   { 0 }
 822 };
 823
 824 static const CGEN_OPERAND_INSTANCE fmt_66_stb_d_ops[] = {
 825   { INPUT, & HW_ENT (HW_H_SLO16), CGEN_MODE_HI, & OP_ENT (SLO16), 0 },
 826   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0 },
 827   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0 },
 828   { OUTPUT, & HW_ENT (HW_H_MEMORY), CGEN_MODE_QI, 0, 0 },
 829   { 0 }
 830 };
 831
 832 static const CGEN_OPERAND_INSTANCE fmt_67_sth_ops[] = {
 833   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0 },
 834   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0 },
 835   { OUTPUT, & HW_ENT (HW_H_MEMORY), CGEN_MODE_HI, 0, 0 },
 836   { 0 }
 837 };
 838
 839 static const CGEN_OPERAND_INSTANCE fmt_68_sth_d_ops[] = {
 840   { INPUT, & HW_ENT (HW_H_SLO16), CGEN_MODE_HI, & OP_ENT (SLO16), 0 },
 841   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0 },
 842   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0 },
 843   { OUTPUT, & HW_ENT (HW_H_MEMORY), CGEN_MODE_HI, 0, 0 },
 844   { 0 }
 845 };
 846
 847 static const CGEN_OPERAND_INSTANCE fmt_69_st_plus_ops[] = {
 848   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0 },
 849   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0 },
 850   { OUTPUT, & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0 },
 851   { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0 },
 852   { 0 }
 853 };
 854
 855 static const CGEN_OPERAND_INSTANCE fmt_70_trap_ops[] = {
 856   { INPUT, & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0 },
 857   { INPUT, & HW_ENT (HW_H_CR), CGEN_MODE_SI, 0, 0 },
 858   { INPUT, & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (UIMM4), 0 },
 859   { OUTPUT, & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0 },
 860   { OUTPUT, & HW_ENT (HW_H_CR), CGEN_MODE_SI, 0, 0 },
 861   { OUTPUT, & HW_ENT (HW_H_CR), CGEN_MODE_SI, 0, 6 },
 862   { 0 }
 863 };
 864
 865 static const CGEN_OPERAND_INSTANCE fmt_71_unlock_ops[] = {
 866   { INPUT, & HW_ENT (HW_H_LOCK), CGEN_MODE_UBI, 0, 0 },
 867   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0 },
 868   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0 },
 869   { OUTPUT, & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0 },
 870   { OUTPUT, & HW_ENT (HW_H_LOCK), CGEN_MODE_UBI, 0, 0 },
 871   { 0 }
 872 };
 873
 874 static const CGEN_OPERAND_INSTANCE fmt_74_satb_ops[] = {
 875   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
 876   { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
 877   { 0 }
 878 };
 879
 880 static const CGEN_OPERAND_INSTANCE fmt_75_sat_ops[] = {
 881   { INPUT, & HW_ENT (HW_H_COND), CGEN_MODE_UBI, 0, 0 },
 882   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
 883   { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
 884   { 0 }
 885 };
 886
 887 static const CGEN_OPERAND_INSTANCE fmt_76_sadd_ops[] = {
 888   { INPUT, & HW_ENT (HW_H_ACCUMS), CGEN_MODE_DI, 0, 0 },
 889   { INPUT, & HW_ENT (HW_H_ACCUMS), CGEN_MODE_DI, 0, 1 },
 890   { OUTPUT, & HW_ENT (HW_H_ACCUMS), CGEN_MODE_DI, 0, 0 },
 891   { 0 }
 892 };
 893
 894 static const CGEN_OPERAND_INSTANCE fmt_77_macwu1_ops[] = {
 895   { INPUT, & HW_ENT (HW_H_ACCUMS), CGEN_MODE_DI, 0, 1 },
 896   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0 },
 897   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0 },
 898   { OUTPUT, & HW_ENT (HW_H_ACCUMS), CGEN_MODE_DI, 0, 1 },
 899   { 0 }
 900 };
 901
 902 static const CGEN_OPERAND_INSTANCE fmt_78_mulwu1_ops[] = {
 903   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0 },
 904   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0 },
 905   { OUTPUT, & HW_ENT (HW_H_ACCUMS), CGEN_MODE_DI, 0, 1 },
 906   { 0 }
 907 };
 908
 909 static const CGEN_OPERAND_INSTANCE fmt_79_sc_ops[] = {
 910   { INPUT, & HW_ENT (HW_H_COND), CGEN_MODE_UBI, 0, 0 },
 911   { 0 }
 912 };
 913
 914 #undef INPUT
 915 #undef OUTPUT
 916
 917 #define A(a) (1 << CONCAT2 (CGEN_INSN_,a))
 918 #define MNEM CGEN_SYNTAX_MNEMONIC /* syntax value for mnemonic */
 919 #define OP(field) CGEN_SYNTAX_MAKE_FIELD (OPERAND (field))
 920
 921 /* The instruction table.  */
 922
 923 const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
 924 {
 925   /* null first entry, end of all hash chains */
 926   { { 0 }, 0 },
 927 /* add $dr,$sr */
 928   {
 929     { 1, 1, 1, 1 },
 930     "add", "add",
 931     { MNEM, ' ', OP (DR), ',', OP (SR), 0 },
 932     { 16, 16, 0xf0f0 }, 0xa0,
 933     & fmt_0_add_ops[0],
 934     { CGEN_INSN_NBOOL_ATTRS, 0|A(PARALLEL), { (1<<MACH_M32R), PIPE_OS } }
 935   },
 936 /* add3 $dr,$sr,$hash$slo16 */
 937   {
 938     { 1, 1, 1, 1 },
 939     "add3", "add3",
 940     { MNEM, ' ', OP (DR), ',', OP (SR), ',', OP (HASH), OP (SLO16), 0 },
 941     { 32, 32, 0xf0f00000 }, 0x80a00000,
 942     & fmt_1_add3_ops[0],
 943     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_NONE } }
 944   },
 945 /* and $dr,$sr */
 946   {
 947     { 1, 1, 1, 1 },
 948     "and", "and",
 949     { MNEM, ' ', OP (DR), ',', OP (SR), 0 },
 950     { 16, 16, 0xf0f0 }, 0xc0,
 951     & fmt_0_add_ops[0],
 952     { CGEN_INSN_NBOOL_ATTRS, 0|A(PARALLEL), { (1<<MACH_M32R), PIPE_OS } }
 953   },
 954 /* and3 $dr,$sr,$uimm16 */
 955   {
 956     { 1, 1, 1, 1 },
 957     "and3", "and3",
 958     { MNEM, ' ', OP (DR), ',', OP (SR), ',', OP (UIMM16), 0 },
 959     { 32, 32, 0xf0f00000 }, 0x80c00000,
 960     & fmt_2_and3_ops[0],
 961     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_NONE } }
 962   },
 963 /* or $dr,$sr */
 964   {
 965     { 1, 1, 1, 1 },
 966     "or", "or",
 967     { MNEM, ' ', OP (DR), ',', OP (SR), 0 },
 968     { 16, 16, 0xf0f0 }, 0xe0,
 969     & fmt_0_add_ops[0],
 970     { CGEN_INSN_NBOOL_ATTRS, 0|A(PARALLEL), { (1<<MACH_M32R), PIPE_OS } }
 971   },
 972 /* or3 $dr,$sr,$hash$ulo16 */
 973   {
 974     { 1, 1, 1, 1 },
 975     "or3", "or3",
 976     { MNEM, ' ', OP (DR), ',', OP (SR), ',', OP (HASH), OP (ULO16), 0 },
 977     { 32, 32, 0xf0f00000 }, 0x80e00000,
 978     & fmt_3_or3_ops[0],
 979     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_NONE } }
 980   },
 981 /* xor $dr,$sr */
 982   {
 983     { 1, 1, 1, 1 },
 984     "xor", "xor",
 985     { MNEM, ' ', OP (DR), ',', OP (SR), 0 },
 986     { 16, 16, 0xf0f0 }, 0xd0,
 987     & fmt_0_add_ops[0],
 988     { CGEN_INSN_NBOOL_ATTRS, 0|A(PARALLEL), { (1<<MACH_M32R), PIPE_OS } }
 989   },
 990 /* xor3 $dr,$sr,$uimm16 */
 991   {
 992     { 1, 1, 1, 1 },
 993     "xor3", "xor3",
 994     { MNEM, ' ', OP (DR), ',', OP (SR), ',', OP (UIMM16), 0 },
 995     { 32, 32, 0xf0f00000 }, 0x80d00000,
 996     & fmt_2_and3_ops[0],
 997     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_NONE } }
 998   },
 999 /* addi $dr,$simm8 */
1000   {
1001     { 1, 1, 1, 1 },
1002     "addi", "addi",
1003     { MNEM, ' ', OP (DR), ',', OP (SIMM8), 0 },
1004     { 16, 16, 0xf000 }, 0x4000,
1005     & fmt_4_addi_ops[0],
1006     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_OS } }
1007   },
1008 /* addv $dr,$sr */
1009   {
1010     { 1, 1, 1, 1 },
1011     "addv", "addv",
1012     { MNEM, ' ', OP (DR), ',', OP (SR), 0 },
1013     { 16, 16, 0xf0f0 }, 0x80,
1014     & fmt_5_addv_ops[0],
1015     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_OS } }
1016   },
1017 /* addv3 $dr,$sr,$simm16 */
1018   {
1019     { 1, 1, 1, 1 },
1020     "addv3", "addv3",
1021     { MNEM, ' ', OP (DR), ',', OP (SR), ',', OP (SIMM16), 0 },
1022     { 32, 32, 0xf0f00000 }, 0x80800000,
1023     & fmt_6_addv3_ops[0],
1024     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_NONE } }
1025   },
1026 /* addx $dr,$sr */
1027   {
1028     { 1, 1, 1, 1 },
1029     "addx", "addx",
1030     { MNEM, ' ', OP (DR), ',', OP (SR), 0 },
1031     { 16, 16, 0xf0f0 }, 0x90,
1032     & fmt_7_addx_ops[0],
1033     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_OS } }
1034   },
1035 /* bc $disp8 */
1036   {
1037     { 1, 1, 1, 1 },
1038     "bc8", "bc",
1039     { MNEM, ' ', OP (DISP8), 0 },
1040     { 16, 16, 0xff00 }, 0x7c00,
1041     & fmt_8_bc8_ops[0],
1042     { CGEN_INSN_NBOOL_ATTRS, 0|A(RELAXABLE)|A(COND_CTI), { (1<<MACH_M32R), PIPE_O } }
1043   },
1044 /* bc.s $disp8 */
1045   {
1046     { 1, 1, 1, 1 },
1047     "bc8.s", "bc.s",
1048     { MNEM, ' ', OP (DISP8), 0 },
1049     { 16, 16, 0xff00 }, 0x7c00,
1050     0,
1051     { CGEN_INSN_NBOOL_ATTRS, 0|A(ALIAS)|A(COND_CTI), { (1<<MACH_M32R), PIPE_O } }
1052   },
1053 /* bc $disp24 */
1054   {
1055     { 1, 1, 1, 1 },
1056     "bc24", "bc",
1057     { MNEM, ' ', OP (DISP24), 0 },
1058     { 32, 32, 0xff000000 }, 0xfc000000,
1059     & fmt_10_bc24_ops[0],
1060     { CGEN_INSN_NBOOL_ATTRS, 0|A(RELAX)|A(COND_CTI), { (1<<MACH_M32R), PIPE_NONE } }
1061   },
1062 /* bc.l $disp24 */
1063   {
1064     { 1, 1, 1, 1 },
1065     "bc24.l", "bc.l",
1066     { MNEM, ' ', OP (DISP24), 0 },
1067     { 32, 32, 0xff000000 }, 0xfc000000,
1068     0,
1069     { CGEN_INSN_NBOOL_ATTRS, 0|A(ALIAS)|A(COND_CTI), { (1<<MACH_M32R), PIPE_NONE } }
1070   },
1071 /* beq $src1,$src2,$disp16 */
1072   {
1073     { 1, 1, 1, 1 },
1074     "beq", "beq",
1075     { MNEM, ' ', OP (SRC1), ',', OP (SRC2), ',', OP (DISP16), 0 },
1076     { 32, 32, 0xf0f00000 }, 0xb0000000,
1077     & fmt_12_beq_ops[0],
1078     { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_M32R), PIPE_NONE } }
1079   },
1080 /* beqz $src2,$disp16 */
1081   {
1082     { 1, 1, 1, 1 },
1083     "beqz", "beqz",
1084     { MNEM, ' ', OP (SRC2), ',', OP (DISP16), 0 },
1085     { 32, 32, 0xfff00000 }, 0xb0800000,
1086     & fmt_13_beqz_ops[0],
1087     { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_M32R), PIPE_NONE } }
1088   },
1089 /* bgez $src2,$disp16 */
1090   {
1091     { 1, 1, 1, 1 },
1092     "bgez", "bgez",
1093     { MNEM, ' ', OP (SRC2), ',', OP (DISP16), 0 },
1094     { 32, 32, 0xfff00000 }, 0xb0b00000,
1095     & fmt_13_beqz_ops[0],
1096     { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_M32R), PIPE_NONE } }
1097   },
1098 /* bgtz $src2,$disp16 */
1099   {
1100     { 1, 1, 1, 1 },
1101     "bgtz", "bgtz",
1102     { MNEM, ' ', OP (SRC2), ',', OP (DISP16), 0 },
1103     { 32, 32, 0xfff00000 }, 0xb0d00000,
1104     & fmt_13_beqz_ops[0],
1105     { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_M32R), PIPE_NONE } }
1106   },
1107 /* blez $src2,$disp16 */
1108   {
1109     { 1, 1, 1, 1 },
1110     "blez", "blez",
1111     { MNEM, ' ', OP (SRC2), ',', OP (DISP16), 0 },
1112     { 32, 32, 0xfff00000 }, 0xb0c00000,
1113     & fmt_13_beqz_ops[0],
1114     { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_M32R), PIPE_NONE } }
1115   },
1116 /* bltz $src2,$disp16 */
1117   {
1118     { 1, 1, 1, 1 },
1119     "bltz", "bltz",
1120     { MNEM, ' ', OP (SRC2), ',', OP (DISP16), 0 },
1121     { 32, 32, 0xfff00000 }, 0xb0a00000,
1122     & fmt_13_beqz_ops[0],
1123     { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_M32R), PIPE_NONE } }
1124   },
1125 /* bnez $src2,$disp16 */
1126   {
1127     { 1, 1, 1, 1 },
1128     "bnez", "bnez",
1129     { MNEM, ' ', OP (SRC2), ',', OP (DISP16), 0 },
1130     { 32, 32, 0xfff00000 }, 0xb0900000,
1131     & fmt_13_beqz_ops[0],
1132     { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_M32R), PIPE_NONE } }
1133   },
1134 /* bl $disp8 */
1135   {
1136     { 1, 1, 1, 1 },
1137     "bl8", "bl",
1138     { MNEM, ' ', OP (DISP8), 0 },
1139     { 16, 16, 0xff00 }, 0x7e00,
1140     & fmt_14_bl8_ops[0],
1141     { CGEN_INSN_NBOOL_ATTRS, 0|A(FILL_SLOT)|A(RELAXABLE)|A(UNCOND_CTI), { (1<<MACH_M32R), PIPE_O } }
1142   },
1143 /* bl.s $disp8 */
1144   {
1145     { 1, 1, 1, 1 },
1146     "bl8.s", "bl.s",
1147     { MNEM, ' ', OP (DISP8), 0 },
1148     { 16, 16, 0xff00 }, 0x7e00,
1149     0,
1150     { CGEN_INSN_NBOOL_ATTRS, 0|A(FILL_SLOT)|A(ALIAS)|A(UNCOND_CTI), { (1<<MACH_M32R), PIPE_O } }
1151   },
1152 /* bl $disp24 */
1153   {
1154     { 1, 1, 1, 1 },
1155     "bl24", "bl",
1156     { MNEM, ' ', OP (DISP24), 0 },
1157     { 32, 32, 0xff000000 }, 0xfe000000,
1158     & fmt_15_bl24_ops[0],
1159     { CGEN_INSN_NBOOL_ATTRS, 0|A(RELAX)|A(UNCOND_CTI), { (1<<MACH_M32R), PIPE_NONE } }
1160   },
1161 /* bl.l $disp24 */
1162   {
1163     { 1, 1, 1, 1 },
1164     "bl24.l", "bl.l",
1165     { MNEM, ' ', OP (DISP24), 0 },
1166     { 32, 32, 0xff000000 }, 0xfe000000,
1167     0,
1168     { CGEN_INSN_NBOOL_ATTRS, 0|A(ALIAS)|A(UNCOND_CTI), { (1<<MACH_M32R), PIPE_NONE } }
1169   },
1170 /* start-sanitize-m32rx */
1171 /* bcl $disp8 */
1172   {
1173     { 1, 1, 1, 1 },
1174     "bcl8", "bcl",
1175     { MNEM, ' ', OP (DISP8), 0 },
1176     { 16, 16, 0xff00 }, 0x7800,
1177     & fmt_16_bcl8_ops[0],
1178     { CGEN_INSN_NBOOL_ATTRS, 0|A(RELAXABLE)|A(COND_CTI), { (1<<MACH_M32RX), PIPE_O } }
1179   },
1180 /* end-sanitize-m32rx */
1181 /* start-sanitize-m32rx */
1182 /* bcl.s $disp8 */
1183   {
1184     { 1, 1, 1, 1 },
1185     "bcl8.s", "bcl.s",
1186     { MNEM, ' ', OP (DISP8), 0 },
1187     { 16, 16, 0xff00 }, 0x7800,
1188     0,
1189     { CGEN_INSN_NBOOL_ATTRS, 0|A(ALIAS)|A(COND_CTI), { (1<<MACH_M32RX), PIPE_O } }
1190   },
1191 /* end-sanitize-m32rx */
1192 /* start-sanitize-m32rx */
1193 /* bcl $disp24 */
1194   {
1195     { 1, 1, 1, 1 },
1196     "bcl24", "bcl",
1197     { MNEM, ' ', OP (DISP24), 0 },
1198     { 32, 32, 0xff000000 }, 0xf8000000,
1199     & fmt_17_bcl24_ops[0],
1200     { CGEN_INSN_NBOOL_ATTRS, 0|A(RELAX)|A(COND_CTI), { (1<<MACH_M32RX), PIPE_NONE } }
1201   },
1202 /* end-sanitize-m32rx */
1203 /* start-sanitize-m32rx */
1204 /* bcl.l $disp24 */
1205   {
1206     { 1, 1, 1, 1 },
1207     "bcl24.l", "bcl.l",
1208     { MNEM, ' ', OP (DISP24), 0 },
1209     { 32, 32, 0xff000000 }, 0xf8000000,
1210     0,
1211     { CGEN_INSN_NBOOL_ATTRS, 0|A(ALIAS)|A(COND_CTI), { (1<<MACH_M32RX), PIPE_NONE } }
1212   },
1213 /* end-sanitize-m32rx */
1214 /* bnc $disp8 */
1215   {
1216     { 1, 1, 1, 1 },
1217     "bnc8", "bnc",
1218     { MNEM, ' ', OP (DISP8), 0 },
1219     { 16, 16, 0xff00 }, 0x7d00,
1220     & fmt_8_bc8_ops[0],
1221     { CGEN_INSN_NBOOL_ATTRS, 0|A(RELAXABLE)|A(COND_CTI), { (1<<MACH_M32R), PIPE_O } }
1222   },
1223 /* bnc.s $disp8 */
1224   {
1225     { 1, 1, 1, 1 },
1226     "bnc8.s", "bnc.s",
1227     { MNEM, ' ', OP (DISP8), 0 },
1228     { 16, 16, 0xff00 }, 0x7d00,
1229     0,
1230     { CGEN_INSN_NBOOL_ATTRS, 0|A(ALIAS)|A(COND_CTI), { (1<<MACH_M32R), PIPE_O } }
1231   },
1232 /* bnc $disp24 */
1233   {
1234     { 1, 1, 1, 1 },
1235     "bnc24", "bnc",
1236     { MNEM, ' ', OP (DISP24), 0 },
1237     { 32, 32, 0xff000000 }, 0xfd000000,
1238     & fmt_10_bc24_ops[0],
1239     { CGEN_INSN_NBOOL_ATTRS, 0|A(RELAX)|A(COND_CTI), { (1<<MACH_M32R), PIPE_NONE } }
1240   },
1241 /* bnc.l $disp24 */
1242   {
1243     { 1, 1, 1, 1 },
1244     "bnc24.l", "bnc.l",
1245     { MNEM, ' ', OP (DISP24), 0 },
1246     { 32, 32, 0xff000000 }, 0xfd000000,
1247     0,
1248     { CGEN_INSN_NBOOL_ATTRS, 0|A(ALIAS)|A(COND_CTI), { (1<<MACH_M32R), PIPE_NONE } }
1249   },
1250 /* bne $src1,$src2,$disp16 */
1251   {
1252     { 1, 1, 1, 1 },
1253     "bne", "bne",
1254     { MNEM, ' ', OP (SRC1), ',', OP (SRC2), ',', OP (DISP16), 0 },
1255     { 32, 32, 0xf0f00000 }, 0xb0100000,
1256     & fmt_12_beq_ops[0],
1257     { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_M32R), PIPE_NONE } }
1258   },
1259 /* bra $disp8 */
1260   {
1261     { 1, 1, 1, 1 },
1262     "bra8", "bra",
1263     { MNEM, ' ', OP (DISP8), 0 },
1264     { 16, 16, 0xff00 }, 0x7f00,
1265     & fmt_18_bra8_ops[0],
1266     { CGEN_INSN_NBOOL_ATTRS, 0|A(FILL_SLOT)|A(RELAXABLE)|A(UNCOND_CTI), { (1<<MACH_M32R), PIPE_O } }
1267   },
1268 /* bra.s $disp8 */
1269   {
1270     { 1, 1, 1, 1 },
1271     "bra8.s", "bra.s",
1272     { MNEM, ' ', OP (DISP8), 0 },
1273     { 16, 16, 0xff00 }, 0x7f00,
1274     0,
1275     { CGEN_INSN_NBOOL_ATTRS, 0|A(ALIAS)|A(UNCOND_CTI), { (1<<MACH_M32R), PIPE_O } }
1276   },
1277 /* bra $disp24 */
1278   {
1279     { 1, 1, 1, 1 },
1280     "bra24", "bra",
1281     { MNEM, ' ', OP (DISP24), 0 },
1282     { 32, 32, 0xff000000 }, 0xff000000,
1283     & fmt_19_bra24_ops[0],
1284     { CGEN_INSN_NBOOL_ATTRS, 0|A(RELAX)|A(UNCOND_CTI), { (1<<MACH_M32R), PIPE_NONE } }
1285   },
1286 /* bra.l $disp24 */
1287   {
1288     { 1, 1, 1, 1 },
1289     "bra24.l", "bra.l",
1290     { MNEM, ' ', OP (DISP24), 0 },
1291     { 32, 32, 0xff000000 }, 0xff000000,
1292     0,
1293     { CGEN_INSN_NBOOL_ATTRS, 0|A(ALIAS)|A(UNCOND_CTI), { (1<<MACH_M32R), PIPE_NONE } }
1294   },
1295 /* start-sanitize-m32rx */
1296 /* bncl $disp8 */
1297   {
1298     { 1, 1, 1, 1 },
1299     "bncl8", "bncl",
1300     { MNEM, ' ', OP (DISP8), 0 },
1301     { 16, 16, 0xff00 }, 0x7900,
1302     & fmt_16_bcl8_ops[0],
1303     { CGEN_INSN_NBOOL_ATTRS, 0|A(RELAXABLE)|A(COND_CTI), { (1<<MACH_M32RX), PIPE_O } }
1304   },
1305 /* end-sanitize-m32rx */
1306 /* start-sanitize-m32rx */
1307 /* bncl.s $disp8 */
1308   {
1309     { 1, 1, 1, 1 },
1310     "bncl8.s", "bncl.s",
1311     { MNEM, ' ', OP (DISP8), 0 },
1312     { 16, 16, 0xff00 }, 0x7900,
1313     0,
1314     { CGEN_INSN_NBOOL_ATTRS, 0|A(ALIAS)|A(COND_CTI), { (1<<MACH_M32RX), PIPE_O } }
1315   },
1316 /* end-sanitize-m32rx */
1317 /* start-sanitize-m32rx */
1318 /* bncl $disp24 */
1319   {
1320     { 1, 1, 1, 1 },
1321     "bncl24", "bncl",
1322     { MNEM, ' ', OP (DISP24), 0 },
1323     { 32, 32, 0xff000000 }, 0xf9000000,
1324     & fmt_17_bcl24_ops[0],
1325     { CGEN_INSN_NBOOL_ATTRS, 0|A(RELAX)|A(COND_CTI), { (1<<MACH_M32RX), PIPE_NONE } }
1326   },
1327 /* end-sanitize-m32rx */
1328 /* start-sanitize-m32rx */
1329 /* bncl.l $disp24 */
1330   {
1331     { 1, 1, 1, 1 },
1332     "bncl24.l", "bncl.l",
1333     { MNEM, ' ', OP (DISP24), 0 },
1334     { 32, 32, 0xff000000 }, 0xf9000000,
1335     0,
1336     { CGEN_INSN_NBOOL_ATTRS, 0|A(ALIAS)|A(COND_CTI), { (1<<MACH_M32RX), PIPE_NONE } }
1337   },
1338 /* end-sanitize-m32rx */
1339 /* cmp $src1,$src2 */
1340   {
1341     { 1, 1, 1, 1 },
1342     "cmp", "cmp",
1343     { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 },
1344     { 16, 16, 0xf0f0 }, 0x40,
1345     & fmt_20_cmp_ops[0],
1346     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_OS } }
1347   },
1348 /* cmpi $src2,$simm16 */
1349   {
1350     { 1, 1, 1, 1 },
1351     "cmpi", "cmpi",
1352     { MNEM, ' ', OP (SRC2), ',', OP (SIMM16), 0 },
1353     { 32, 32, 0xfff00000 }, 0x80400000,
1354     & fmt_21_cmpi_ops[0],
1355     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_NONE } }
1356   },
1357 /* cmpu $src1,$src2 */
1358   {
1359     { 1, 1, 1, 1 },
1360     "cmpu", "cmpu",
1361     { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 },
1362     { 16, 16, 0xf0f0 }, 0x50,
1363     & fmt_20_cmp_ops[0],
1364     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_OS } }
1365   },
1366 /* cmpui $src2,$uimm16 */
1367   {
1368     { 1, 1, 1, 1 },
1369     "cmpui", "cmpui",
1370     { MNEM, ' ', OP (SRC2), ',', OP (UIMM16), 0 },
1371     { 32, 32, 0xfff00000 }, 0x80500000,
1372     & fmt_22_cmpui_ops[0],
1373     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_NONE } }
1374   },
1375 /* start-sanitize-m32rx */
1376 /* cmpeq $src1,$src2 */
1377   {
1378     { 1, 1, 1, 1 },
1379     "cmpeq", "cmpeq",
1380     { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 },
1381     { 16, 16, 0xf0f0 }, 0x60,
1382     & fmt_20_cmp_ops[0],
1383     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_OS } }
1384   },
1385 /* end-sanitize-m32rx */
1386 /* start-sanitize-m32rx */
1387 /* cmpz $src2 */
1388   {
1389     { 1, 1, 1, 1 },
1390     "cmpz", "cmpz",
1391     { MNEM, ' ', OP (SRC2), 0 },
1392     { 16, 16, 0xfff0 }, 0x70,
1393     & fmt_23_cmpz_ops[0],
1394     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_OS } }
1395   },
1396 /* end-sanitize-m32rx */
1397 /* div $dr,$sr */
1398   {
1399     { 1, 1, 1, 1 },
1400     "div", "div",
1401     { MNEM, ' ', OP (DR), ',', OP (SR), 0 },
1402     { 32, 32, 0xf0f0ffff }, 0x90000000,
1403     & fmt_24_div_ops[0],
1404     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_NONE } }
1405   },
1406 /* divu $dr,$sr */
1407   {
1408     { 1, 1, 1, 1 },
1409     "divu", "divu",
1410     { MNEM, ' ', OP (DR), ',', OP (SR), 0 },
1411     { 32, 32, 0xf0f0ffff }, 0x90100000,
1412     & fmt_24_div_ops[0],
1413     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_NONE } }
1414   },
1415 /* rem $dr,$sr */
1416   {
1417     { 1, 1, 1, 1 },
1418     "rem", "rem",
1419     { MNEM, ' ', OP (DR), ',', OP (SR), 0 },
1420     { 32, 32, 0xf0f0ffff }, 0x90200000,
1421     & fmt_24_div_ops[0],
1422     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_NONE } }
1423   },
1424 /* remu $dr,$sr */
1425   {
1426     { 1, 1, 1, 1 },
1427     "remu", "remu",
1428     { MNEM, ' ', OP (DR), ',', OP (SR), 0 },
1429     { 32, 32, 0xf0f0ffff }, 0x90300000,
1430     & fmt_24_div_ops[0],
1431     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_NONE } }
1432   },
1433 /* start-sanitize-m32rx */
1434 /* divh $dr,$sr */
1435   {
1436     { 1, 1, 1, 1 },
1437     "divh", "divh",
1438     { MNEM, ' ', OP (DR), ',', OP (SR), 0 },
1439     { 32, 32, 0xf0f0ffff }, 0x90000010,
1440     & fmt_24_div_ops[0],
1441     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_NONE } }
1442   },
1443 /* end-sanitize-m32rx */
1444 /* start-sanitize-m32rx */
1445 /* jc $sr */
1446   {
1447     { 1, 1, 1, 1 },
1448     "jc", "jc",
1449     { MNEM, ' ', OP (SR), 0 },
1450     { 16, 16, 0xfff0 }, 0x1cc0,
1451     & fmt_25_jc_ops[0],
1452     { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_M32RX), PIPE_O } }
1453   },
1454 /* end-sanitize-m32rx */
1455 /* start-sanitize-m32rx */
1456 /* jnc $sr */
1457   {
1458     { 1, 1, 1, 1 },
1459     "jnc", "jnc",
1460     { MNEM, ' ', OP (SR), 0 },
1461     { 16, 16, 0xfff0 }, 0x1dc0,
1462     & fmt_25_jc_ops[0],
1463     { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_M32RX), PIPE_O } }
1464   },
1465 /* end-sanitize-m32rx */
1466 /* jl $sr */
1467   {
1468     { 1, 1, 1, 1 },
1469     "jl", "jl",
1470     { MNEM, ' ', OP (SR), 0 },
1471     { 16, 16, 0xfff0 }, 0x1ec0,
1472     & fmt_26_jl_ops[0],
1473     { CGEN_INSN_NBOOL_ATTRS, 0|A(FILL_SLOT)|A(UNCOND_CTI), { (1<<MACH_M32R), PIPE_O } }
1474   },
1475 /* jmp $sr */
1476   {
1477     { 1, 1, 1, 1 },
1478     "jmp", "jmp",
1479     { MNEM, ' ', OP (SR), 0 },
1480     { 16, 16, 0xfff0 }, 0x1fc0,
1481     & fmt_27_jmp_ops[0],
1482     { CGEN_INSN_NBOOL_ATTRS, 0|A(UNCOND_CTI), { (1<<MACH_M32R), PIPE_O } }
1483   },
1484 /* ld $dr,@$sr */
1485   {
1486     { 1, 1, 1, 1 },
1487     "ld", "ld",
1488     { MNEM, ' ', OP (DR), ',', '@', OP (SR), 0 },
1489     { 16, 16, 0xf0f0 }, 0x20c0,
1490     & fmt_28_ld_ops[0],
1491     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_O } }
1492   },
1493 /* ld $dr,@($sr) */
1494   {
1495     { 1, 1, 1, 1 },
1496     "ld-2", "ld",
1497     { MNEM, ' ', OP (DR), ',', '@', '(', OP (SR), ')', 0 },
1498     { 16, 16, 0xf0f0 }, 0x20c0,
1499     0,
1500     { CGEN_INSN_NBOOL_ATTRS, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_O } }
1501   },
1502 /* ld $dr,@($slo16,$sr) */
1503   {
1504     { 1, 1, 1, 1 },
1505     "ld-d", "ld",
1506     { MNEM, ' ', OP (DR), ',', '@', '(', OP (SLO16), ',', OP (SR), ')', 0 },
1507     { 32, 32, 0xf0f00000 }, 0xa0c00000,
1508     & fmt_30_ld_d_ops[0],
1509     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_NONE } }
1510   },
1511 /* ld $dr,@($sr,$slo16) */
1512   {
1513     { 1, 1, 1, 1 },
1514     "ld-d2", "ld",
1515     { MNEM, ' ', OP (DR), ',', '@', '(', OP (SR), ',', OP (SLO16), ')', 0 },
1516     { 32, 32, 0xf0f00000 }, 0xa0c00000,
1517     0,
1518     { CGEN_INSN_NBOOL_ATTRS, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE } }
1519   },
1520 /* ldb $dr,@$sr */
1521   {
1522     { 1, 1, 1, 1 },
1523     "ldb", "ldb",
1524     { MNEM, ' ', OP (DR), ',', '@', OP (SR), 0 },
1525     { 16, 16, 0xf0f0 }, 0x2080,
1526     & fmt_32_ldb_ops[0],
1527     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_O } }
1528   },
1529 /* ldb $dr,@($sr) */
1530   {
1531     { 1, 1, 1, 1 },
1532     "ldb-2", "ldb",
1533     { MNEM, ' ', OP (DR), ',', '@', '(', OP (SR), ')', 0 },
1534     { 16, 16, 0xf0f0 }, 0x2080,
1535     0,
1536     { CGEN_INSN_NBOOL_ATTRS, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_O } }
1537   },
1538 /* ldb $dr,@($slo16,$sr) */
1539   {
1540     { 1, 1, 1, 1 },
1541     "ldb-d", "ldb",
1542     { MNEM, ' ', OP (DR), ',', '@', '(', OP (SLO16), ',', OP (SR), ')', 0 },
1543     { 32, 32, 0xf0f00000 }, 0xa0800000,
1544     & fmt_33_ldb_d_ops[0],
1545     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_NONE } }
1546   },
1547 /* ldb $dr,@($sr,$slo16) */
1548   {
1549     { 1, 1, 1, 1 },
1550     "ldb-d2", "ldb",
1551     { MNEM, ' ', OP (DR), ',', '@', '(', OP (SR), ',', OP (SLO16), ')', 0 },
1552     { 32, 32, 0xf0f00000 }, 0xa0800000,
1553     0,
1554     { CGEN_INSN_NBOOL_ATTRS, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE } }
1555   },
1556 /* ldh $dr,@$sr */
1557   {
1558     { 1, 1, 1, 1 },
1559     "ldh", "ldh",
1560     { MNEM, ' ', OP (DR), ',', '@', OP (SR), 0 },
1561     { 16, 16, 0xf0f0 }, 0x20a0,
1562     & fmt_34_ldh_ops[0],
1563     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_O } }
1564   },
1565 /* ldh $dr,@($sr) */
1566   {
1567     { 1, 1, 1, 1 },
1568     "ldh-2", "ldh",
1569     { MNEM, ' ', OP (DR), ',', '@', '(', OP (SR), ')', 0 },
1570     { 16, 16, 0xf0f0 }, 0x20a0,
1571     0,
1572     { CGEN_INSN_NBOOL_ATTRS, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_O } }
1573   },
1574 /* ldh $dr,@($slo16,$sr) */
1575   {
1576     { 1, 1, 1, 1 },
1577     "ldh-d", "ldh",
1578     { MNEM, ' ', OP (DR), ',', '@', '(', OP (SLO16), ',', OP (SR), ')', 0 },
1579     { 32, 32, 0xf0f00000 }, 0xa0a00000,
1580     & fmt_35_ldh_d_ops[0],
1581     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_NONE } }
1582   },
1583 /* ldh $dr,@($sr,$slo16) */
1584   {
1585     { 1, 1, 1, 1 },
1586     "ldh-d2", "ldh",
1587     { MNEM, ' ', OP (DR), ',', '@', '(', OP (SR), ',', OP (SLO16), ')', 0 },
1588     { 32, 32, 0xf0f00000 }, 0xa0a00000,
1589     0,
1590     { CGEN_INSN_NBOOL_ATTRS, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE } }
1591   },
1592 /* ldub $dr,@$sr */
1593   {
1594     { 1, 1, 1, 1 },
1595     "ldub", "ldub",
1596     { MNEM, ' ', OP (DR), ',', '@', OP (SR), 0 },
1597     { 16, 16, 0xf0f0 }, 0x2090,
1598     & fmt_32_ldb_ops[0],
1599     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_O } }
1600   },
1601 /* ldub $dr,@($sr) */
1602   {
1603     { 1, 1, 1, 1 },
1604     "ldub-2", "ldub",
1605     { MNEM, ' ', OP (DR), ',', '@', '(', OP (SR), ')', 0 },
1606     { 16, 16, 0xf0f0 }, 0x2090,
1607     0,
1608     { CGEN_INSN_NBOOL_ATTRS, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_O } }
1609   },
1610 /* ldub $dr,@($slo16,$sr) */
1611   {
1612     { 1, 1, 1, 1 },
1613     "ldub-d", "ldub",
1614     { MNEM, ' ', OP (DR), ',', '@', '(', OP (SLO16), ',', OP (SR), ')', 0 },
1615     { 32, 32, 0xf0f00000 }, 0xa0900000,
1616     & fmt_33_ldb_d_ops[0],
1617     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_NONE } }
1618   },
1619 /* ldub $dr,@($sr,$slo16) */
1620   {
1621     { 1, 1, 1, 1 },
1622     "ldub-d2", "ldub",
1623     { MNEM, ' ', OP (DR), ',', '@', '(', OP (SR), ',', OP (SLO16), ')', 0 },
1624     { 32, 32, 0xf0f00000 }, 0xa0900000,
1625     0,
1626     { CGEN_INSN_NBOOL_ATTRS, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE } }
1627   },
1628 /* lduh $dr,@$sr */
1629   {
1630     { 1, 1, 1, 1 },
1631     "lduh", "lduh",
1632     { MNEM, ' ', OP (DR), ',', '@', OP (SR), 0 },
1633     { 16, 16, 0xf0f0 }, 0x20b0,
1634     & fmt_34_ldh_ops[0],
1635     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_O } }
1636   },
1637 /* lduh $dr,@($sr) */
1638   {
1639     { 1, 1, 1, 1 },
1640     "lduh-2", "lduh",
1641     { MNEM, ' ', OP (DR), ',', '@', '(', OP (SR), ')', 0 },
1642     { 16, 16, 0xf0f0 }, 0x20b0,
1643     0,
1644     { CGEN_INSN_NBOOL_ATTRS, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_O } }
1645   },
1646 /* lduh $dr,@($slo16,$sr) */
1647   {
1648     { 1, 1, 1, 1 },
1649     "lduh-d", "lduh",
1650     { MNEM, ' ', OP (DR), ',', '@', '(', OP (SLO16), ',', OP (SR), ')', 0 },
1651     { 32, 32, 0xf0f00000 }, 0xa0b00000,
1652     & fmt_35_ldh_d_ops[0],
1653     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_NONE } }
1654   },
1655 /* lduh $dr,@($sr,$slo16) */
1656   {
1657     { 1, 1, 1, 1 },
1658     "lduh-d2", "lduh",
1659     { MNEM, ' ', OP (DR), ',', '@', '(', OP (SR), ',', OP (SLO16), ')', 0 },
1660     { 32, 32, 0xf0f00000 }, 0xa0b00000,
1661     0,
1662     { CGEN_INSN_NBOOL_ATTRS, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE } }
1663   },
1664 /* ld $dr,@$sr+ */
1665   {
1666     { 1, 1, 1, 1 },
1667     "ld-plus", "ld",
1668     { MNEM, ' ', OP (DR), ',', '@', OP (SR), '+', 0 },
1669     { 16, 16, 0xf0f0 }, 0x20e0,
1670     & fmt_36_ld_plus_ops[0],
1671     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_O } }
1672   },
1673 /* ld24 $dr,$uimm24 */
1674   {
1675     { 1, 1, 1, 1 },
1676     "ld24", "ld24",
1677     { MNEM, ' ', OP (DR), ',', OP (UIMM24), 0 },
1678     { 32, 32, 0xf0000000 }, 0xe0000000,
1679     & fmt_37_ld24_ops[0],
1680     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_NONE } }
1681   },
1682 /* ldi $dr,$simm8 */
1683   {
1684     { 1, 1, 1, 1 },
1685     "ldi8", "ldi",
1686     { MNEM, ' ', OP (DR), ',', OP (SIMM8), 0 },
1687     { 16, 16, 0xf000 }, 0x6000,
1688     & fmt_38_ldi8_ops[0],
1689     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_OS } }
1690   },
1691 /* ldi8 $dr,$simm8 */
1692   {
1693     { 1, 1, 1, 1 },
1694     "ldi8a", "ldi8",
1695     { MNEM, ' ', OP (DR), ',', OP (SIMM8), 0 },
1696     { 16, 16, 0xf000 }, 0x6000,
1697     & fmt_38_ldi8_ops[0],
1698     { CGEN_INSN_NBOOL_ATTRS, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_OS } }
1699   },
1700 /* ldi $dr,$hash$slo16 */
1701   {
1702     { 1, 1, 1, 1 },
1703     "ldi16", "ldi",
1704     { MNEM, ' ', OP (DR), ',', OP (HASH), OP (SLO16), 0 },
1705     { 32, 32, 0xf0ff0000 }, 0x90f00000,
1706     & fmt_39_ldi16_ops[0],
1707     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_NONE } }
1708   },
1709 /* ldi16 $dr,$hash$slo16 */
1710   {
1711     { 1, 1, 1, 1 },
1712     "ldi16a", "ldi16",
1713     { MNEM, ' ', OP (DR), ',', OP (HASH), OP (SLO16), 0 },
1714     { 32, 32, 0xf0ff0000 }, 0x90f00000,
1715     & fmt_39_ldi16_ops[0],
1716     { CGEN_INSN_NBOOL_ATTRS, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE } }
1717   },
1718 /* lock $dr,@$sr */
1719   {
1720     { 1, 1, 1, 1 },
1721     "lock", "lock",
1722     { MNEM, ' ', OP (DR), ',', '@', OP (SR), 0 },
1723     { 16, 16, 0xf0f0 }, 0x20d0,
1724     & fmt_40_lock_ops[0],
1725     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_O } }
1726   },
1727 /* machi $src1,$src2 */
1728   {
1729     { 1, 1, 1, 1 },
1730     "machi", "machi",
1731     { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 },
1732     { 16, 16, 0xf0f0 }, 0x3040,
1733     & fmt_41_machi_ops[0],
1734     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_S } }
1735   },
1736 /* start-sanitize-m32rx */
1737 /* machi $src1,$src2,$acc */
1738   {
1739     { 1, 1, 1, 1 },
1740     "machi-a", "machi",
1741     { MNEM, ' ', OP (SRC1), ',', OP (SRC2), ',', OP (ACC), 0 },
1742     { 16, 16, 0xf070 }, 0x3040,
1743     & fmt_42_machi_a_ops[0],
1744     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_S } }
1745   },
1746 /* end-sanitize-m32rx */
1747 /* maclo $src1,$src2 */
1748   {
1749     { 1, 1, 1, 1 },
1750     "maclo", "maclo",
1751     { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 },
1752     { 16, 16, 0xf0f0 }, 0x3050,
1753     & fmt_41_machi_ops[0],
1754     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_S } }
1755   },
1756 /* start-sanitize-m32rx */
1757 /* maclo $src1,$src2,$acc */
1758   {
1759     { 1, 1, 1, 1 },
1760     "maclo-a", "maclo",
1761     { MNEM, ' ', OP (SRC1), ',', OP (SRC2), ',', OP (ACC), 0 },
1762     { 16, 16, 0xf070 }, 0x3050,
1763     & fmt_42_machi_a_ops[0],
1764     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_S } }
1765   },
1766 /* end-sanitize-m32rx */
1767 /* macwhi $src1,$src2 */
1768   {
1769     { 1, 1, 1, 1 },
1770     "macwhi", "macwhi",
1771     { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 },
1772     { 16, 16, 0xf0f0 }, 0x3060,
1773     & fmt_41_machi_ops[0],
1774     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_S } }
1775   },
1776 /* macwlo $src1,$src2 */
1777   {
1778     { 1, 1, 1, 1 },
1779     "macwlo", "macwlo",
1780     { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 },
1781     { 16, 16, 0xf0f0 }, 0x3070,
1782     & fmt_41_machi_ops[0],
1783     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_S } }
1784   },
1785 /* mul $dr,$sr */
1786   {
1787     { 1, 1, 1, 1 },
1788     "mul", "mul",
1789     { MNEM, ' ', OP (DR), ',', OP (SR), 0 },
1790     { 16, 16, 0xf0f0 }, 0x1060,
1791     & fmt_0_add_ops[0],
1792     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_S } }
1793   },
1794 /* mulhi $src1,$src2 */
1795   {
1796     { 1, 1, 1, 1 },
1797     "mulhi", "mulhi",
1798     { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 },
1799     { 16, 16, 0xf0f0 }, 0x3000,
1800     & fmt_43_mulhi_ops[0],
1801     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_S } }
1802   },
1803 /* start-sanitize-m32rx */
1804 /* mulhi $src1,$src2,$acc */
1805   {
1806     { 1, 1, 1, 1 },
1807     "mulhi-a", "mulhi",
1808     { MNEM, ' ', OP (SRC1), ',', OP (SRC2), ',', OP (ACC), 0 },
1809     { 16, 16, 0xf070 }, 0x3000,
1810     & fmt_44_mulhi_a_ops[0],
1811     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_S } }
1812   },
1813 /* end-sanitize-m32rx */
1814 /* mullo $src1,$src2 */
1815   {
1816     { 1, 1, 1, 1 },
1817     "mullo", "mullo",
1818     { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 },
1819     { 16, 16, 0xf0f0 }, 0x3010,
1820     & fmt_43_mulhi_ops[0],
1821     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_S } }
1822   },
1823 /* start-sanitize-m32rx */
1824 /* mullo $src1,$src2,$acc */
1825   {
1826     { 1, 1, 1, 1 },
1827     "mullo-a", "mullo",
1828     { MNEM, ' ', OP (SRC1), ',', OP (SRC2), ',', OP (ACC), 0 },
1829     { 16, 16, 0xf070 }, 0x3010,
1830     & fmt_44_mulhi_a_ops[0],
1831     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_S } }
1832   },
1833 /* end-sanitize-m32rx */
1834 /* mulwhi $src1,$src2 */
1835   {
1836     { 1, 1, 1, 1 },
1837     "mulwhi", "mulwhi",
1838     { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 },
1839     { 16, 16, 0xf0f0 }, 0x3020,
1840     & fmt_43_mulhi_ops[0],
1841     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_S } }
1842   },
1843 /* mulwlo $src1,$src2 */
1844   {
1845     { 1, 1, 1, 1 },
1846     "mulwlo", "mulwlo",
1847     { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 },
1848     { 16, 16, 0xf0f0 }, 0x3030,
1849     & fmt_43_mulhi_ops[0],
1850     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_S } }
1851   },
1852 /* mv $dr,$sr */
1853   {
1854     { 1, 1, 1, 1 },
1855     "mv", "mv",
1856     { MNEM, ' ', OP (DR), ',', OP (SR), 0 },
1857     { 16, 16, 0xf0f0 }, 0x1080,
1858     & fmt_45_mv_ops[0],
1859     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_OS } }
1860   },
1861 /* mvfachi $dr */
1862   {
1863     { 1, 1, 1, 1 },
1864     "mvfachi", "mvfachi",
1865     { MNEM, ' ', OP (DR), 0 },
1866     { 16, 16, 0xf0ff }, 0x50f0,
1867     & fmt_46_mvfachi_ops[0],
1868     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_S } }
1869   },
1870 /* start-sanitize-m32rx */
1871 /* mvfachi $dr,$accs */
1872   {
1873     { 1, 1, 1, 1 },
1874     "mvfachi-a", "mvfachi",
1875     { MNEM, ' ', OP (DR), ',', OP (ACCS), 0 },
1876     { 16, 16, 0xf0f3 }, 0x50f0,
1877     & fmt_47_mvfachi_a_ops[0],
1878     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_S } }
1879   },
1880 /* end-sanitize-m32rx */
1881 /* mvfaclo $dr */
1882   {
1883     { 1, 1, 1, 1 },
1884     "mvfaclo", "mvfaclo",
1885     { MNEM, ' ', OP (DR), 0 },
1886     { 16, 16, 0xf0ff }, 0x50f1,
1887     & fmt_46_mvfachi_ops[0],
1888     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_S } }
1889   },
1890 /* start-sanitize-m32rx */
1891 /* mvfaclo $dr,$accs */
1892   {
1893     { 1, 1, 1, 1 },
1894     "mvfaclo-a", "mvfaclo",
1895     { MNEM, ' ', OP (DR), ',', OP (ACCS), 0 },
1896     { 16, 16, 0xf0f3 }, 0x50f1,
1897     & fmt_47_mvfachi_a_ops[0],
1898     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_S } }
1899   },
1900 /* end-sanitize-m32rx */
1901 /* mvfacmi $dr */
1902   {
1903     { 1, 1, 1, 1 },
1904     "mvfacmi", "mvfacmi",
1905     { MNEM, ' ', OP (DR), 0 },
1906     { 16, 16, 0xf0ff }, 0x50f2,
1907     & fmt_46_mvfachi_ops[0],
1908     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_S } }
1909   },
1910 /* start-sanitize-m32rx */
1911 /* mvfacmi $dr,$accs */
1912   {
1913     { 1, 1, 1, 1 },
1914     "mvfacmi-a", "mvfacmi",
1915     { MNEM, ' ', OP (DR), ',', OP (ACCS), 0 },
1916     { 16, 16, 0xf0f3 }, 0x50f2,
1917     & fmt_47_mvfachi_a_ops[0],
1918     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_S } }
1919   },
1920 /* end-sanitize-m32rx */
1921 /* mvfc $dr,$scr */
1922   {
1923     { 1, 1, 1, 1 },
1924     "mvfc", "mvfc",
1925     { MNEM, ' ', OP (DR), ',', OP (SCR), 0 },
1926     { 16, 16, 0xf0f0 }, 0x1090,
1927     & fmt_48_mvfc_ops[0],
1928     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_O } }
1929   },
1930 /* mvtachi $src1 */
1931   {
1932     { 1, 1, 1, 1 },
1933     "mvtachi", "mvtachi",
1934     { MNEM, ' ', OP (SRC1), 0 },
1935     { 16, 16, 0xf0ff }, 0x5070,
1936     & fmt_49_mvtachi_ops[0],
1937     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_S } }
1938   },
1939 /* start-sanitize-m32rx */
1940 /* mvtachi $src1,$accs */
1941   {
1942     { 1, 1, 1, 1 },
1943     "mvtachi-a", "mvtachi",
1944     { MNEM, ' ', OP (SRC1), ',', OP (ACCS), 0 },
1945     { 16, 16, 0xf0f3 }, 0x5070,
1946     & fmt_50_mvtachi_a_ops[0],
1947     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_S } }
1948   },
1949 /* end-sanitize-m32rx */
1950 /* mvtaclo $src1 */
1951   {
1952     { 1, 1, 1, 1 },
1953     "mvtaclo", "mvtaclo",
1954     { MNEM, ' ', OP (SRC1), 0 },
1955     { 16, 16, 0xf0ff }, 0x5071,
1956     & fmt_49_mvtachi_ops[0],
1957     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_S } }
1958   },
1959 /* start-sanitize-m32rx */
1960 /* mvtaclo $src1,$accs */
1961   {
1962     { 1, 1, 1, 1 },
1963     "mvtaclo-a", "mvtaclo",
1964     { MNEM, ' ', OP (SRC1), ',', OP (ACCS), 0 },
1965     { 16, 16, 0xf0f3 }, 0x5071,
1966     & fmt_50_mvtachi_a_ops[0],
1967     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_S } }
1968   },
1969 /* end-sanitize-m32rx */
1970 /* mvtc $sr,$dcr */
1971   {
1972     { 1, 1, 1, 1 },
1973     "mvtc", "mvtc",
1974     { MNEM, ' ', OP (SR), ',', OP (DCR), 0 },
1975     { 16, 16, 0xf0f0 }, 0x10a0,
1976     & fmt_51_mvtc_ops[0],
1977     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_O } }
1978   },
1979 /* neg $dr,$sr */
1980   {
1981     { 1, 1, 1, 1 },
1982     "neg", "neg",
1983     { MNEM, ' ', OP (DR), ',', OP (SR), 0 },
1984     { 16, 16, 0xf0f0 }, 0x30,
1985     & fmt_45_mv_ops[0],
1986     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_OS } }
1987   },
1988 /* nop */
1989   {
1990     { 1, 1, 1, 1 },
1991     "nop", "nop",
1992     { MNEM, 0 },
1993     { 16, 16, 0xffff }, 0x7000,
1994     0,
1995     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_OS } }
1996   },
1997 /* not $dr,$sr */
1998   {
1999     { 1, 1, 1, 1 },
2000     "not", "not",
2001     { MNEM, ' ', OP (DR), ',', OP (SR), 0 },
2002     { 16, 16, 0xf0f0 }, 0xb0,
2003     & fmt_45_mv_ops[0],
2004     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_OS } }
2005   },
2006 /* rac */
2007   {
2008     { 1, 1, 1, 1 },
2009     "rac", "rac",
2010     { MNEM, 0 },
2011     { 16, 16, 0xffff }, 0x5090,
2012     & fmt_53_rac_ops[0],
2013     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_S } }
2014   },
2015 /* start-sanitize-m32rx */
2016 /* rac $accd */
2017   {
2018     { 1, 1, 1, 1 },
2019     "rac-d", "rac",
2020     { MNEM, ' ', OP (ACCD), 0 },
2021     { 16, 16, 0xf3ff }, 0x5090,
2022     0,
2023     { CGEN_INSN_NBOOL_ATTRS, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE } }
2024   },
2025 /* end-sanitize-m32rx */
2026 /* start-sanitize-m32rx */
2027 /* rac $accd,$accs */
2028   {
2029     { 1, 1, 1, 1 },
2030     "rac-ds", "rac",
2031     { MNEM, ' ', OP (ACCD), ',', OP (ACCS), 0 },
2032     { 16, 16, 0xf3f3 }, 0x5090,
2033     0,
2034     { CGEN_INSN_NBOOL_ATTRS, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE } }
2035   },
2036 /* end-sanitize-m32rx */
2037 /* start-sanitize-m32rx */
2038 /* rac $accd,$accs,$imm1 */
2039   {
2040     { 1, 1, 1, 1 },
2041     "rac-dsi", "rac",
2042     { MNEM, ' ', OP (ACCD), ',', OP (ACCS), ',', OP (IMM1), 0 },
2043     { 16, 16, 0xf3f2 }, 0x5090,
2044     & fmt_56_rac_dsi_ops[0],
2045     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_S } }
2046   },
2047 /* end-sanitize-m32rx */
2048 /* rach */
2049   {
2050     { 1, 1, 1, 1 },
2051     "rach", "rach",
2052     { MNEM, 0 },
2053     { 16, 16, 0xffff }, 0x5080,
2054     & fmt_53_rac_ops[0],
2055     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_S } }
2056   },
2057 /* start-sanitize-m32rx */
2058 /* rach $accd */
2059   {
2060     { 1, 1, 1, 1 },
2061     "rach-d", "rach",
2062     { MNEM, ' ', OP (ACCD), 0 },
2063     { 16, 16, 0xf3ff }, 0x5080,
2064     0,
2065     { CGEN_INSN_NBOOL_ATTRS, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE } }
2066   },
2067 /* end-sanitize-m32rx */
2068 /* start-sanitize-m32rx */
2069 /* rach $accd,$accs */
2070   {
2071     { 1, 1, 1, 1 },
2072     "rach-ds", "rach",
2073     { MNEM, ' ', OP (ACCD), ',', OP (ACCS), 0 },
2074     { 16, 16, 0xf3f3 }, 0x5080,
2075     0,
2076     { CGEN_INSN_NBOOL_ATTRS, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE } }
2077   },
2078 /* end-sanitize-m32rx */
2079 /* start-sanitize-m32rx */
2080 /* rach $accd,$accs,$imm1 */
2081   {
2082     { 1, 1, 1, 1 },
2083     "rach-dsi", "rach",
2084     { MNEM, ' ', OP (ACCD), ',', OP (ACCS), ',', OP (IMM1), 0 },
2085     { 16, 16, 0xf3f2 }, 0x5080,
2086     & fmt_56_rac_dsi_ops[0],
2087     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_S } }
2088   },
2089 /* end-sanitize-m32rx */
2090 /* rte */
2091   {
2092     { 1, 1, 1, 1 },
2093     "rte", "rte",
2094     { MNEM, 0 },
2095     { 16, 16, 0xffff }, 0x10d6,
2096     & fmt_57_rte_ops[0],
2097     { CGEN_INSN_NBOOL_ATTRS, 0|A(UNCOND_CTI), { (1<<MACH_M32R), PIPE_O } }
2098   },
2099 /* seth $dr,$hash$hi16 */
2100   {
2101     { 1, 1, 1, 1 },
2102     "seth", "seth",
2103     { MNEM, ' ', OP (DR), ',', OP (HASH), OP (HI16), 0 },
2104     { 32, 32, 0xf0ff0000 }, 0xd0c00000,
2105     & fmt_58_seth_ops[0],
2106     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_NONE } }
2107   },
2108 /* sll $dr,$sr */
2109   {
2110     { 1, 1, 1, 1 },
2111     "sll", "sll",
2112     { MNEM, ' ', OP (DR), ',', OP (SR), 0 },
2113     { 16, 16, 0xf0f0 }, 0x1040,
2114     & fmt_0_add_ops[0],
2115     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_O } }
2116   },
2117 /* sll3 $dr,$sr,$simm16 */
2118   {
2119     { 1, 1, 1, 1 },
2120     "sll3", "sll3",
2121     { MNEM, ' ', OP (DR), ',', OP (SR), ',', OP (SIMM16), 0 },
2122     { 32, 32, 0xf0f00000 }, 0x90c00000,
2123     & fmt_59_sll3_ops[0],
2124     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_NONE } }
2125   },
2126 /* slli $dr,$uimm5 */
2127   {
2128     { 1, 1, 1, 1 },
2129     "slli", "slli",
2130     { MNEM, ' ', OP (DR), ',', OP (UIMM5), 0 },
2131     { 16, 16, 0xf0e0 }, 0x5040,
2132     & fmt_60_slli_ops[0],
2133     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_O } }
2134   },
2135 /* sra $dr,$sr */
2136   {
2137     { 1, 1, 1, 1 },
2138     "sra", "sra",
2139     { MNEM, ' ', OP (DR), ',', OP (SR), 0 },
2140     { 16, 16, 0xf0f0 }, 0x1020,
2141     & fmt_0_add_ops[0],
2142     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_O } }
2143   },
2144 /* sra3 $dr,$sr,$simm16 */
2145   {
2146     { 1, 1, 1, 1 },
2147     "sra3", "sra3",
2148     { MNEM, ' ', OP (DR), ',', OP (SR), ',', OP (SIMM16), 0 },
2149     { 32, 32, 0xf0f00000 }, 0x90a00000,
2150     & fmt_59_sll3_ops[0],
2151     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_NONE } }
2152   },
2153 /* srai $dr,$uimm5 */
2154   {
2155     { 1, 1, 1, 1 },
2156     "srai", "srai",
2157     { MNEM, ' ', OP (DR), ',', OP (UIMM5), 0 },
2158     { 16, 16, 0xf0e0 }, 0x5020,
2159     & fmt_60_slli_ops[0],
2160     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_O } }
2161   },
2162 /* srl $dr,$sr */
2163   {
2164     { 1, 1, 1, 1 },
2165     "srl", "srl",
2166     { MNEM, ' ', OP (DR), ',', OP (SR), 0 },
2167     { 16, 16, 0xf0f0 }, 0x1000,
2168     & fmt_0_add_ops[0],
2169     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_O } }
2170   },
2171 /* srl3 $dr,$sr,$simm16 */
2172   {
2173     { 1, 1, 1, 1 },
2174     "srl3", "srl3",
2175     { MNEM, ' ', OP (DR), ',', OP (SR), ',', OP (SIMM16), 0 },
2176     { 32, 32, 0xf0f00000 }, 0x90800000,
2177     & fmt_59_sll3_ops[0],
2178     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_NONE } }
2179   },
2180 /* srli $dr,$uimm5 */
2181   {
2182     { 1, 1, 1, 1 },
2183     "srli", "srli",
2184     { MNEM, ' ', OP (DR), ',', OP (UIMM5), 0 },
2185     { 16, 16, 0xf0e0 }, 0x5000,
2186     & fmt_60_slli_ops[0],
2187     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_O } }
2188   },
2189 /* st $src1,@$src2 */
2190   {
2191     { 1, 1, 1, 1 },
2192     "st", "st",
2193     { MNEM, ' ', OP (SRC1), ',', '@', OP (SRC2), 0 },
2194     { 16, 16, 0xf0f0 }, 0x2040,
2195     & fmt_61_st_ops[0],
2196     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_O } }
2197   },
2198 /* st $src1,@($src2) */
2199   {
2200     { 1, 1, 1, 1 },
2201     "st-2", "st",
2202     { MNEM, ' ', OP (SRC1), ',', '@', '(', OP (SRC2), ')', 0 },
2203     { 16, 16, 0xf0f0 }, 0x2040,
2204     0,
2205     { CGEN_INSN_NBOOL_ATTRS, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_O } }
2206   },
2207 /* st $src1,@($slo16,$src2) */
2208   {
2209     { 1, 1, 1, 1 },
2210     "st-d", "st",
2211     { MNEM, ' ', OP (SRC1), ',', '@', '(', OP (SLO16), ',', OP (SRC2), ')', 0 },
2212     { 32, 32, 0xf0f00000 }, 0xa0400000,
2213     & fmt_63_st_d_ops[0],
2214     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_NONE } }
2215   },
2216 /* st $src1,@($src2,$slo16) */
2217   {
2218     { 1, 1, 1, 1 },
2219     "st-d2", "st",
2220     { MNEM, ' ', OP (SRC1), ',', '@', '(', OP (SRC2), ',', OP (SLO16), ')', 0 },
2221     { 32, 32, 0xf0f00000 }, 0xa0400000,
2222     0,
2223     { CGEN_INSN_NBOOL_ATTRS, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE } }
2224   },
2225 /* stb $src1,@$src2 */
2226   {
2227     { 1, 1, 1, 1 },
2228     "stb", "stb",
2229     { MNEM, ' ', OP (SRC1), ',', '@', OP (SRC2), 0 },
2230     { 16, 16, 0xf0f0 }, 0x2000,
2231     & fmt_65_stb_ops[0],
2232     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_O } }
2233   },
2234 /* stb $src1,@($src2) */
2235   {
2236     { 1, 1, 1, 1 },
2237     "stb-2", "stb",
2238     { MNEM, ' ', OP (SRC1), ',', '@', '(', OP (SRC2), ')', 0 },
2239     { 16, 16, 0xf0f0 }, 0x2000,
2240     0,
2241     { CGEN_INSN_NBOOL_ATTRS, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_O } }
2242   },
2243 /* stb $src1,@($slo16,$src2) */
2244   {
2245     { 1, 1, 1, 1 },
2246     "stb-d", "stb",
2247     { MNEM, ' ', OP (SRC1), ',', '@', '(', OP (SLO16), ',', OP (SRC2), ')', 0 },
2248     { 32, 32, 0xf0f00000 }, 0xa0000000,
2249     & fmt_66_stb_d_ops[0],
2250     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_NONE } }
2251   },
2252 /* stb $src1,@($src2,$slo16) */
2253   {
2254     { 1, 1, 1, 1 },
2255     "stb-d2", "stb",
2256     { MNEM, ' ', OP (SRC1), ',', '@', '(', OP (SRC2), ',', OP (SLO16), ')', 0 },
2257     { 32, 32, 0xf0f00000 }, 0xa0000000,
2258     0,
2259     { CGEN_INSN_NBOOL_ATTRS, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE } }
2260   },
2261 /* sth $src1,@$src2 */
2262   {
2263     { 1, 1, 1, 1 },
2264     "sth", "sth",
2265     { MNEM, ' ', OP (SRC1), ',', '@', OP (SRC2), 0 },
2266     { 16, 16, 0xf0f0 }, 0x2020,
2267     & fmt_67_sth_ops[0],
2268     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_O } }
2269   },
2270 /* sth $src1,@($src2) */
2271   {
2272     { 1, 1, 1, 1 },
2273     "sth-2", "sth",
2274     { MNEM, ' ', OP (SRC1), ',', '@', '(', OP (SRC2), ')', 0 },
2275     { 16, 16, 0xf0f0 }, 0x2020,
2276     0,
2277     { CGEN_INSN_NBOOL_ATTRS, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_O } }
2278   },
2279 /* sth $src1,@($slo16,$src2) */
2280   {
2281     { 1, 1, 1, 1 },
2282     "sth-d", "sth",
2283     { MNEM, ' ', OP (SRC1), ',', '@', '(', OP (SLO16), ',', OP (SRC2), ')', 0 },
2284     { 32, 32, 0xf0f00000 }, 0xa0200000,
2285     & fmt_68_sth_d_ops[0],
2286     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_NONE } }
2287   },
2288 /* sth $src1,@($src2,$slo16) */
2289   {
2290     { 1, 1, 1, 1 },
2291     "sth-d2", "sth",
2292     { MNEM, ' ', OP (SRC1), ',', '@', '(', OP (SRC2), ',', OP (SLO16), ')', 0 },
2293     { 32, 32, 0xf0f00000 }, 0xa0200000,
2294     0,
2295     { CGEN_INSN_NBOOL_ATTRS, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE } }
2296   },
2297 /* st $src1,@+$src2 */
2298   {
2299     { 1, 1, 1, 1 },
2300     "st-plus", "st",
2301     { MNEM, ' ', OP (SRC1), ',', '@', '+', OP (SRC2), 0 },
2302     { 16, 16, 0xf0f0 }, 0x2060,
2303     & fmt_69_st_plus_ops[0],
2304     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_O } }
2305   },
2306 /* st $src1,@-$src2 */
2307   {
2308     { 1, 1, 1, 1 },
2309     "st-minus", "st",
2310     { MNEM, ' ', OP (SRC1), ',', '@', '-', OP (SRC2), 0 },
2311     { 16, 16, 0xf0f0 }, 0x2070,
2312     & fmt_69_st_plus_ops[0],
2313     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_O } }
2314   },
2315 /* sub $dr,$sr */
2316   {
2317     { 1, 1, 1, 1 },
2318     "sub", "sub",
2319     { MNEM, ' ', OP (DR), ',', OP (SR), 0 },
2320     { 16, 16, 0xf0f0 }, 0x20,
2321     & fmt_0_add_ops[0],
2322     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_OS } }
2323   },
2324 /* subv $dr,$sr */
2325   {
2326     { 1, 1, 1, 1 },
2327     "subv", "subv",
2328     { MNEM, ' ', OP (DR), ',', OP (SR), 0 },
2329     { 16, 16, 0xf0f0 }, 0x0,
2330     & fmt_5_addv_ops[0],
2331     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_OS } }
2332   },
2333 /* subx $dr,$sr */
2334   {
2335     { 1, 1, 1, 1 },
2336     "subx", "subx",
2337     { MNEM, ' ', OP (DR), ',', OP (SR), 0 },
2338     { 16, 16, 0xf0f0 }, 0x10,
2339     & fmt_7_addx_ops[0],
2340     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_OS } }
2341   },
2342 /* trap $uimm4 */
2343   {
2344     { 1, 1, 1, 1 },
2345     "trap", "trap",
2346     { MNEM, ' ', OP (UIMM4), 0 },
2347     { 16, 16, 0xfff0 }, 0x10f0,
2348     & fmt_70_trap_ops[0],
2349     { CGEN_INSN_NBOOL_ATTRS, 0|A(FILL_SLOT)|A(UNCOND_CTI), { (1<<MACH_M32R), PIPE_O } }
2350   },
2351 /* unlock $src1,@$src2 */
2352   {
2353     { 1, 1, 1, 1 },
2354     "unlock", "unlock",
2355     { MNEM, ' ', OP (SRC1), ',', '@', OP (SRC2), 0 },
2356     { 16, 16, 0xf0f0 }, 0x2050,
2357     & fmt_71_unlock_ops[0],
2358     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_O } }
2359   },
2360 /* push $src1 */
2361   {
2362     { 1, 1, 1, 1 },
2363     "push", "push",
2364     { MNEM, ' ', OP (SRC1), 0 },
2365     { 16, 16, 0xf0ff }, 0x207f,
2366     0,
2367     { CGEN_INSN_NBOOL_ATTRS, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE } }
2368   },
2369 /* pop $dr */
2370   {
2371     { 1, 1, 1, 1 },
2372     "pop", "pop",
2373     { MNEM, ' ', OP (DR), 0 },
2374     { 16, 16, 0xf0ff }, 0x20ef,
2375     0,
2376     { CGEN_INSN_NBOOL_ATTRS, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE } }
2377   },
2378 /* start-sanitize-m32rx */
2379 /* satb $dr,$sr */
2380   {
2381     { 1, 1, 1, 1 },
2382     "satb", "satb",
2383     { MNEM, ' ', OP (DR), ',', OP (SR), 0 },
2384     { 32, 32, 0xf0f0ffff }, 0x80000100,
2385     & fmt_74_satb_ops[0],
2386     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_NONE } }
2387   },
2388 /* end-sanitize-m32rx */
2389 /* start-sanitize-m32rx */
2390 /* sath $dr,$sr */
2391   {
2392     { 1, 1, 1, 1 },
2393     "sath", "sath",
2394     { MNEM, ' ', OP (DR), ',', OP (SR), 0 },
2395     { 32, 32, 0xf0f0ffff }, 0x80000200,
2396     & fmt_74_satb_ops[0],
2397     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_NONE } }
2398   },
2399 /* end-sanitize-m32rx */
2400 /* start-sanitize-m32rx */
2401 /* sat $dr,$sr */
2402   {
2403     { 1, 1, 1, 1 },
2404     "sat", "sat",
2405     { MNEM, ' ', OP (DR), ',', OP (SR), 0 },
2406     { 32, 32, 0xf0f0ffff }, 0x80000000,
2407     & fmt_75_sat_ops[0],
2408     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_NONE } }
2409   },
2410 /* end-sanitize-m32rx */
2411 /* start-sanitize-m32rx */
2412 /* pcmpbz $src2 */
2413   {
2414     { 1, 1, 1, 1 },
2415     "pcmpbz", "pcmpbz",
2416     { MNEM, ' ', OP (SRC2), 0 },
2417     { 16, 16, 0xfff0 }, 0x370,
2418     & fmt_23_cmpz_ops[0],
2419     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_OS } }
2420   },
2421 /* end-sanitize-m32rx */
2422 /* start-sanitize-m32rx */
2423 /* sadd */
2424   {
2425     { 1, 1, 1, 1 },
2426     "sadd", "sadd",
2427     { MNEM, 0 },
2428     { 16, 16, 0xffff }, 0x50e4,
2429     & fmt_76_sadd_ops[0],
2430     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_S } }
2431   },
2432 /* end-sanitize-m32rx */
2433 /* start-sanitize-m32rx */
2434 /* macwu1 $src1,$src2 */
2435   {
2436     { 1, 1, 1, 1 },
2437     "macwu1", "macwu1",
2438     { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 },
2439     { 16, 16, 0xf0f0 }, 0x50b0,
2440     & fmt_77_macwu1_ops[0],
2441     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_S } }
2442   },
2443 /* end-sanitize-m32rx */
2444 /* start-sanitize-m32rx */
2445 /* msblo $src1,$src2 */
2446   {
2447     { 1, 1, 1, 1 },
2448     "msblo", "msblo",
2449     { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 },
2450     { 16, 16, 0xf0f0 }, 0x50d0,
2451     & fmt_41_machi_ops[0],
2452     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_S } }
2453   },
2454 /* end-sanitize-m32rx */
2455 /* start-sanitize-m32rx */
2456 /* mulwu1 $src1,$src2 */
2457   {
2458     { 1, 1, 1, 1 },
2459     "mulwu1", "mulwu1",
2460     { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 },
2461     { 16, 16, 0xf0f0 }, 0x50a0,
2462     & fmt_78_mulwu1_ops[0],
2463     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_S } }
2464   },
2465 /* end-sanitize-m32rx */
2466 /* start-sanitize-m32rx */
2467 /* maclh1 $src1,$src2 */
2468   {
2469     { 1, 1, 1, 1 },
2470     "maclh1", "maclh1",
2471     { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 },
2472     { 16, 16, 0xf0f0 }, 0x50c0,
2473     & fmt_77_macwu1_ops[0],
2474     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_S } }
2475   },
2476 /* end-sanitize-m32rx */
2477 /* start-sanitize-m32rx */
2478 /* sc */
2479   {
2480     { 1, 1, 1, 1 },
2481     "sc", "sc",
2482     { MNEM, 0 },
2483     { 16, 16, 0xffff }, 0x7401,
2484     & fmt_79_sc_ops[0],
2485     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_O } }
2486   },
2487 /* end-sanitize-m32rx */
2488 /* start-sanitize-m32rx */
2489 /* snc */
2490   {
2491     { 1, 1, 1, 1 },
2492     "snc", "snc",
2493     { MNEM, 0 },
2494     { 16, 16, 0xffff }, 0x7501,
2495     & fmt_79_sc_ops[0],
2496     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_O } }
2497   },
2498 /* end-sanitize-m32rx */
2499 };
2500
2501 #undef A
2502 #undef MNEM
2503 #undef OP
2504
2505 CGEN_INSN_TABLE m32r_cgen_insn_table =
2506 {
2507   & m32r_cgen_insn_table_entries[0],
2508   sizeof (CGEN_INSN),
2509   MAX_INSNS,
2510   NULL,
2511   m32r_cgen_asm_hash_insn, CGEN_ASM_HASH_SIZE,
2512   m32r_cgen_dis_hash_insn, CGEN_DIS_HASH_SIZE
2513 };
2514
2515 /* The hash functions are recorded here to help keep assembler code out of
2516    the disassembler and vice versa.  */
2517
2518 unsigned int
2519 m32r_cgen_asm_hash_insn (insn)
2520      const char * insn;
2521 {
2522   return CGEN_ASM_HASH (insn);
2523 }
2524
2525 unsigned int
2526 m32r_cgen_dis_hash_insn (buf, value)
2527      const char * buf;
2528      unsigned long value;
2529 {
2530   return CGEN_DIS_HASH (buf, value);
2531 }
2532
2533 CGEN_OPCODE_DATA m32r_cgen_opcode_data =
2534 {
2535   & m32r_cgen_hw_entries[0],
2536   & m32r_cgen_insn_table,
2537 };
2538
2539 void
2540 m32r_cgen_init_tables (mach)
2541     int mach;
2542 {
2543 }
2544
2545 /* Main entry point for stuffing values in cgen_fields.  */
2546
2547 void
2548 m32r_cgen_set_operand (opindex, valuep, fields)
2549      int opindex;
2550      const long * valuep;
2551      CGEN_FIELDS * fields;
2552 {
2553   switch (opindex)
2554     {
2555     case M32R_OPERAND_SR :
2556       fields->f_r2 = * valuep;
2557       break;
2558     case M32R_OPERAND_DR :
2559       fields->f_r1 = * valuep;
2560       break;
2561     case M32R_OPERAND_SRC1 :
2562       fields->f_r1 = * valuep;
2563       break;
2564     case M32R_OPERAND_SRC2 :
2565       fields->f_r2 = * valuep;
2566       break;
2567     case M32R_OPERAND_SCR :
2568       fields->f_r2 = * valuep;
2569       break;
2570     case M32R_OPERAND_DCR :
2571       fields->f_r1 = * valuep;
2572       break;
2573     case M32R_OPERAND_SIMM8 :
2574       fields->f_simm8 = * valuep;
2575       break;
2576     case M32R_OPERAND_SIMM16 :
2577       fields->f_simm16 = * valuep;
2578       break;
2579     case M32R_OPERAND_UIMM4 :
2580       fields->f_uimm4 = * valuep;
2581       break;
2582     case M32R_OPERAND_UIMM5 :
2583       fields->f_uimm5 = * valuep;
2584       break;
2585     case M32R_OPERAND_UIMM16 :
2586       fields->f_uimm16 = * valuep;
2587       break;
2588 /* start-sanitize-m32rx */
2589     case M32R_OPERAND_IMM1 :
2590       fields->f_imm1 = * valuep;
2591       break;
2592 /* end-sanitize-m32rx */
2593 /* start-sanitize-m32rx */
2594     case M32R_OPERAND_ACCD :
2595       fields->f_accd = * valuep;
2596       break;
2597 /* end-sanitize-m32rx */
2598 /* start-sanitize-m32rx */
2599     case M32R_OPERAND_ACCS :
2600       fields->f_accs = * valuep;
2601       break;
2602 /* end-sanitize-m32rx */
2603 /* start-sanitize-m32rx */
2604     case M32R_OPERAND_ACC :
2605       fields->f_acc = * valuep;
2606       break;
2607 /* end-sanitize-m32rx */
2608     case M32R_OPERAND_HASH :
2609       fields->f_nil = * valuep;
2610       break;
2611     case M32R_OPERAND_HI16 :
2612       fields->f_hi16 = * valuep;
2613       break;
2614     case M32R_OPERAND_SLO16 :
2615       fields->f_simm16 = * valuep;
2616       break;
2617     case M32R_OPERAND_ULO16 :
2618       fields->f_uimm16 = * valuep;
2619       break;
2620     case M32R_OPERAND_UIMM24 :
2621       fields->f_uimm24 = * valuep;
2622       break;
2623     case M32R_OPERAND_DISP8 :
2624       fields->f_disp8 = * valuep;
2625       break;
2626     case M32R_OPERAND_DISP16 :
2627       fields->f_disp16 = * valuep;
2628       break;
2629     case M32R_OPERAND_DISP24 :
2630       fields->f_disp24 = * valuep;
2631       break;
2632
2633     default :
2634       fprintf (stderr, "Unrecognized field %d while setting operand.\n",
2635                        opindex);
2636       abort ();
2637   }
2638 }
2639
2640 /* Main entry point for getting values from cgen_fields.  */
2641
2642 long
2643 m32r_cgen_get_operand (opindex, fields)
2644      int opindex;
2645      const CGEN_FIELDS * fields;
2646 {
2647   long value;
2648
2649   switch (opindex)
2650     {
2651     case M32R_OPERAND_SR :
2652       value = fields->f_r2;
2653       break;
2654     case M32R_OPERAND_DR :
2655       value = fields->f_r1;
2656       break;
2657     case M32R_OPERAND_SRC1 :
2658       value = fields->f_r1;
2659       break;
2660     case M32R_OPERAND_SRC2 :
2661       value = fields->f_r2;
2662       break;
2663     case M32R_OPERAND_SCR :
2664       value = fields->f_r2;
2665       break;
2666     case M32R_OPERAND_DCR :
2667       value = fields->f_r1;
2668       break;
2669     case M32R_OPERAND_SIMM8 :
2670       value = fields->f_simm8;
2671       break;
2672     case M32R_OPERAND_SIMM16 :
2673       value = fields->f_simm16;
2674       break;
2675     case M32R_OPERAND_UIMM4 :
2676       value = fields->f_uimm4;
2677       break;
2678     case M32R_OPERAND_UIMM5 :
2679       value = fields->f_uimm5;
2680       break;
2681     case M32R_OPERAND_UIMM16 :
2682       value = fields->f_uimm16;
2683       break;
2684 /* start-sanitize-m32rx */
2685     case M32R_OPERAND_IMM1 :
2686       value = fields->f_imm1;
2687       break;
2688 /* end-sanitize-m32rx */
2689 /* start-sanitize-m32rx */
2690     case M32R_OPERAND_ACCD :
2691       value = fields->f_accd;
2692       break;
2693 /* end-sanitize-m32rx */
2694 /* start-sanitize-m32rx */
2695     case M32R_OPERAND_ACCS :
2696       value = fields->f_accs;
2697       break;
2698 /* end-sanitize-m32rx */
2699 /* start-sanitize-m32rx */
2700     case M32R_OPERAND_ACC :
2701       value = fields->f_acc;
2702       break;
2703 /* end-sanitize-m32rx */
2704     case M32R_OPERAND_HASH :
2705       value = fields->f_nil;
2706       break;
2707     case M32R_OPERAND_HI16 :
2708       value = fields->f_hi16;
2709       break;
2710     case M32R_OPERAND_SLO16 :
2711       value = fields->f_simm16;
2712       break;
2713     case M32R_OPERAND_ULO16 :
2714       value = fields->f_uimm16;
2715       break;
2716     case M32R_OPERAND_UIMM24 :
2717       value = fields->f_uimm24;
2718       break;
2719     case M32R_OPERAND_DISP8 :
2720       value = fields->f_disp8;
2721       break;
2722     case M32R_OPERAND_DISP16 :
2723       value = fields->f_disp16;
2724       break;
2725     case M32R_OPERAND_DISP24 :
2726       value = fields->f_disp24;
2727       break;
2728
2729     default :
2730       fprintf (stderr, "Unrecognized field %d while getting operand.\n",
2731                        opindex);
2732       abort ();
2733   }
2734
2735   return value;
2736 }
2737