opcodes/m32r-opc.c

   1 /* Generic opcode table support for targets using CGEN. -*- C -*-
   2    CGEN: Cpu tools GENerator
   3
   4 This file is used to generate m32r-opc.c.
   5
   6 Copyright (C) 1998 Free Software Foundation, Inc.
   7
   8 This file is part of the GNU Binutils and GDB, the GNU debugger.
   9
  10 This program is free software; you can redistribute it and/or modify
  11 it under the terms of the GNU General Public License as published by
  12 the Free Software Foundation; either version 2, or (at your option)
  13 any later version.
  14
  15 This program is distributed in the hope that it will be useful,
  16 but WITHOUT ANY WARRANTY; without even the implied warranty of
  17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  18 GNU General Public License for more details.
  19
  20 You should have received a copy of the GNU General Public License
  21 along with this program; if not, write to the Free Software
  22 Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */
  23
  24 #include "sysdep.h"
  25 #include <stdio.h>
  26 #include "ansidecl.h"
  27 #include "libiberty.h"
  28 #include "bfd.h"
  29 #include "symcat.h"
  30 #include "m32r-opc.h"
  31
  32 /* Look up instruction INSN_VALUE and extract its fields.
  33    If non-null INSN is the insn table entry.
  34    Otherwise INSN_VALUE is examined to compute it.
  35    LENGTH is the bit length of INSN_VALUE if known, otherwise 0.
  36    ALIAS_P is non-zero if alias insns are to be included in the search.
  37    The result a pointer to the insn table entry, or NULL if the instruction
  38    wasn't recognized.  */
  39
  40 const CGEN_INSN *
  41 m32r_cgen_lookup_insn (insn, insn_value, length, fields, alias_p)
  42      const CGEN_INSN *insn;
  43      cgen_insn_t insn_value;
  44      int length;
  45      CGEN_FIELDS *fields;
  46 {
  47   char buf[16];
  48
  49   if (!insn)
  50     {
  51       const CGEN_INSN_LIST *insn_list;
  52
  53 #ifdef CGEN_INT_INSN
  54       switch (length)
  55         {
  56         case 8:
  57           buf[0] = insn_value;
  58           break;
  59         case 16:
  60           if (cgen_current_endian == CGEN_ENDIAN_BIG)
  61             bfd_putb16 (insn_value, buf);
  62           else
  63             bfd_putl16 (insn_value, buf);
  64           break;
  65         case 32:
  66           if (cgen_current_endian == CGEN_ENDIAN_BIG)
  67             bfd_putb32 (insn_value, buf);
  68           else
  69             bfd_putl32 (insn_value, buf);
  70           break;
  71         default:
  72           abort ();
  73         }
  74 #else
  75       abort (); /* FIXME: unfinished */
  76 #endif
  77
  78       /* The instructions are stored in hash lists.
  79          Pick the first one and keep trying until we find the right one.  */
  80
  81       insn_list = CGEN_DIS_LOOKUP_INSN (buf, insn_value);
  82       while (insn_list != NULL)
  83         {
  84           insn = insn_list->insn;
  85
  86           if (alias_p
  87               || ! CGEN_INSN_ATTR (insn, CGEN_INSN_ALIAS))
  88             {
  89               /* Basic bit mask must be correct.  */
  90               /* ??? May wish to allow target to defer this check until the
  91                  extract handler.  */
  92               if ((insn_value & CGEN_INSN_MASK (insn)) == CGEN_INSN_VALUE (insn))
  93                 {
  94                   length = (*CGEN_EXTRACT_FN (insn)) (insn, NULL, insn_value, fields);
  95                   if (length > 0)
  96                     return insn;
  97                 }
  98             }
  99
 100           insn_list = CGEN_DIS_NEXT_INSN (insn_list);
 101         }
 102     }
 103   else
 104     {
 105       /* Sanity check: can't pass an alias insn if ! alias_p.  */
 106       if (! alias_p
 107           && CGEN_INSN_ATTR (insn, CGEN_INSN_ALIAS))
 108         abort ();
 109
 110       length = (*CGEN_EXTRACT_FN (insn)) (insn, NULL, insn_value, fields);
 111       if (length > 0)
 112         return insn;
 113     }
 114
 115   return NULL;
 116 }
 117
 118 /* Fill in the operand instances used by insn INSN_VALUE.
 119    If non-null INS is the insn table entry.
 120    Otherwise INSN_VALUE is examined to compute it.
 121    LENGTH is the number of bits in INSN_VALUE if known, otherwise 0.
 122    INDICES is a pointer to a buffer of MAX_OPERANDS ints to be filled in.
 123    The result a pointer to the insn table entry, or NULL if the instruction
 124    wasn't recognized.  */
 125
 126 const CGEN_INSN *
 127 m32r_cgen_get_insn_operands (insn, insn_value, length, indices)
 128      const CGEN_INSN *insn;
 129      cgen_insn_t insn_value;
 130      int length;
 131      int *indices;
 132 {
 133   CGEN_FIELDS fields;
 134   const CGEN_OPERAND_INSTANCE *opinst;
 135   int i;
 136
 137   /* FIXME: ALIAS insns are in transition from being record in the insn table
 138      to being recorded separately as macros.  They don't have semantic code
 139      so they can't be used here.  Thus we currently always ignore the INSN
 140      argument.  */
 141   insn = m32r_cgen_lookup_insn (NULL, insn_value, length, &fields, 0);
 142   if (! insn)
 143     return NULL;
 144
 145   for (i = 0, opinst = CGEN_INSN_OPERANDS (insn);
 146        opinst != NULL
 147          && CGEN_OPERAND_INSTANCE_TYPE (opinst) != CGEN_OPERAND_INSTANCE_END;
 148        ++i, ++opinst)
 149     {
 150       const CGEN_OPERAND *op = CGEN_OPERAND_INSTANCE_OPERAND (opinst);
 151       if (op == NULL)
 152         indices[i] = CGEN_OPERAND_INSTANCE_INDEX (opinst);
 153       else
 154         indices[i] = m32r_cgen_get_operand (CGEN_OPERAND_INDEX (op), &fields);
 155     }
 156
 157   return insn;
 158 }
 159 /* Attributes.  */
 160
 161 static const CGEN_ATTR_ENTRY MACH_attr[] =
 162 {
 163   { "m32r", MACH_M32R },
 164 /* start-sanitize-m32rx */
 165   { "m32rx", MACH_M32RX },
 166 /* end-sanitize-m32rx */
 167   { "max", MACH_MAX },
 168   { 0, 0 }
 169 };
 170
 171 /* start-sanitize-m32rx */
 172 static const CGEN_ATTR_ENTRY PIPE_attr[] =
 173 {
 174   { "NONE", PIPE_NONE },
 175   { "O", PIPE_O },
 176   { "S", PIPE_S },
 177   { "OS", PIPE_OS },
 178   { 0, 0 }
 179 };
 180
 181 /* end-sanitize-m32rx */
 182 const CGEN_ATTR_TABLE m32r_cgen_operand_attr_table[] =
 183 {
 184   { "ABS-ADDR", NULL },
 185   { "FAKE", NULL },
 186   { "NEGATIVE", NULL },
 187   { "PC", NULL },
 188   { "PCREL-ADDR", NULL },
 189   { "RELAX", NULL },
 190   { "RELOC", NULL },
 191   { "SIGN-OPT", NULL },
 192   { "UNSIGNED", NULL },
 193   { 0, 0 }
 194 };
 195
 196 const CGEN_ATTR_TABLE m32r_cgen_insn_attr_table[] =
 197 {
 198   { "MACH", & MACH_attr[0] },
 199 /* start-sanitize-m32rx */
 200   { "PIPE", & PIPE_attr[0] },
 201 /* end-sanitize-m32rx */
 202   { "ALIAS", NULL },
 203   { "COND-CTI", NULL },
 204   { "FILL-SLOT", NULL },
 205   { "PARALLEL", NULL },
 206   { "RELAX", NULL },
 207   { "RELAXABLE", NULL },
 208   { "UNCOND-CTI", NULL },
 209   { 0, 0 }
 210 };
 211
 212 CGEN_KEYWORD_ENTRY m32r_cgen_opval_h_gr_entries[] =
 213 {
 214   { "fp", 13 },
 215   { "lr", 14 },
 216   { "sp", 15 },
 217   { "r0", 0 },
 218   { "r1", 1 },
 219   { "r2", 2 },
 220   { "r3", 3 },
 221   { "r4", 4 },
 222   { "r5", 5 },
 223   { "r6", 6 },
 224   { "r7", 7 },
 225   { "r8", 8 },
 226   { "r9", 9 },
 227   { "r10", 10 },
 228   { "r11", 11 },
 229   { "r12", 12 },
 230   { "r13", 13 },
 231   { "r14", 14 },
 232   { "r15", 15 }
 233 };
 234
 235 CGEN_KEYWORD m32r_cgen_opval_h_gr =
 236 {
 237   & m32r_cgen_opval_h_gr_entries[0],
 238   19
 239 };
 240
 241 CGEN_KEYWORD_ENTRY m32r_cgen_opval_h_cr_entries[] =
 242 {
 243   { "psw", 0 },
 244   { "cbr", 1 },
 245   { "spi", 2 },
 246   { "spu", 3 },
 247   { "bpc", 6 },
 248   { "cr0", 0 },
 249   { "cr1", 1 },
 250   { "cr2", 2 },
 251   { "cr3", 3 },
 252   { "cr4", 4 },
 253   { "cr5", 5 },
 254   { "cr6", 6 }
 255 };
 256
 257 CGEN_KEYWORD m32r_cgen_opval_h_cr =
 258 {
 259   & m32r_cgen_opval_h_cr_entries[0],
 260   12
 261 };
 262
 263 /* start-sanitize-m32rx */
 264 CGEN_KEYWORD_ENTRY m32r_cgen_opval_h_accums_entries[] =
 265 {
 266   { "a0", 0 },
 267   { "a1", 1 }
 268 };
 269
 270 CGEN_KEYWORD m32r_cgen_opval_h_accums =
 271 {
 272   & m32r_cgen_opval_h_accums_entries[0],
 273   2
 274 };
 275
 276 /* end-sanitize-m32rx */
 277
 278 /* The hardware table.  */
 279
 280 #define HW_ENT(n) m32r_cgen_hw_entries[n]
 281 static const CGEN_HW_ENTRY m32r_cgen_hw_entries[] =
 282 {
 283   { HW_H_PC, & HW_ENT (HW_H_PC + 1), "h-pc", CGEN_ASM_KEYWORD, (PTR) 0 },
 284   { HW_H_MEMORY, & HW_ENT (HW_H_MEMORY + 1), "h-memory", CGEN_ASM_KEYWORD, (PTR) 0 },
 285   { HW_H_SINT, & HW_ENT (HW_H_SINT + 1), "h-sint", CGEN_ASM_KEYWORD, (PTR) 0 },
 286   { HW_H_UINT, & HW_ENT (HW_H_UINT + 1), "h-uint", CGEN_ASM_KEYWORD, (PTR) 0 },
 287   { HW_H_ADDR, & HW_ENT (HW_H_ADDR + 1), "h-addr", CGEN_ASM_KEYWORD, (PTR) 0 },
 288   { HW_H_IADDR, & HW_ENT (HW_H_IADDR + 1), "h-iaddr", CGEN_ASM_KEYWORD, (PTR) 0 },
 289   { HW_H_HI16, & HW_ENT (HW_H_HI16 + 1), "h-hi16", CGEN_ASM_KEYWORD, (PTR) 0 },
 290   { HW_H_SLO16, & HW_ENT (HW_H_SLO16 + 1), "h-slo16", CGEN_ASM_KEYWORD, (PTR) 0 },
 291   { HW_H_ULO16, & HW_ENT (HW_H_ULO16 + 1), "h-ulo16", CGEN_ASM_KEYWORD, (PTR) 0 },
 292   { HW_H_GR, & HW_ENT (HW_H_GR + 1), "h-gr", CGEN_ASM_KEYWORD, (PTR) & m32r_cgen_opval_h_gr },
 293   { HW_H_CR, & HW_ENT (HW_H_CR + 1), "h-cr", CGEN_ASM_KEYWORD, (PTR) & m32r_cgen_opval_h_cr },
 294   { HW_H_ACCUM, & HW_ENT (HW_H_ACCUM + 1), "h-accum", CGEN_ASM_KEYWORD, (PTR) 0 },
 295 /* start-sanitize-m32rx */
 296   { HW_H_ACCUMS, & HW_ENT (HW_H_ACCUMS + 1), "h-accums", CGEN_ASM_KEYWORD, (PTR) & m32r_cgen_opval_h_accums },
 297 /* end-sanitize-m32rx */
 298 /* start-sanitize-m32rx */
 299   { HW_H_ABORT, & HW_ENT (HW_H_ABORT + 1), "h-abort", CGEN_ASM_KEYWORD, (PTR) 0 },
 300 /* end-sanitize-m32rx */
 301   { HW_H_COND, & HW_ENT (HW_H_COND + 1), "h-cond", CGEN_ASM_KEYWORD, (PTR) 0 },
 302   { HW_H_SM, & HW_ENT (HW_H_SM + 1), "h-sm", CGEN_ASM_KEYWORD, (PTR) 0 },
 303   { HW_H_BSM, & HW_ENT (HW_H_BSM + 1), "h-bsm", CGEN_ASM_KEYWORD, (PTR) 0 },
 304   { HW_H_IE, & HW_ENT (HW_H_IE + 1), "h-ie", CGEN_ASM_KEYWORD, (PTR) 0 },
 305   { HW_H_BIE, & HW_ENT (HW_H_BIE + 1), "h-bie", CGEN_ASM_KEYWORD, (PTR) 0 },
 306   { HW_H_BCOND, & HW_ENT (HW_H_BCOND + 1), "h-bcond", CGEN_ASM_KEYWORD, (PTR) 0 },
 307   { HW_H_BPC, & HW_ENT (HW_H_BPC + 1), "h-bpc", CGEN_ASM_KEYWORD, (PTR) 0 },
 308   { 0 }
 309 };
 310
 311 /* The operand table.  */
 312
 313 #define OP_ENT(op) m32r_cgen_operand_table[CONCAT2 (M32R_OPERAND_,op)]
 314 const CGEN_OPERAND m32r_cgen_operand_table[MAX_OPERANDS] =
 315 {
 316 /* pc: program counter */
 317   { "pc", & HW_ENT (HW_H_PC), 0, 0,
 318     { 0, 0|(1<<CGEN_OPERAND_FAKE)|(1<<CGEN_OPERAND_PC), { 0 } }  },
 319 /* sr: source register */
 320   { "sr", & HW_ENT (HW_H_GR), 12, 4,
 321     { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } }  },
 322 /* dr: destination register */
 323   { "dr", & HW_ENT (HW_H_GR), 4, 4,
 324     { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } }  },
 325 /* src1: source register 1 */
 326   { "src1", & HW_ENT (HW_H_GR), 4, 4,
 327     { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } }  },
 328 /* src2: source register 2 */
 329   { "src2", & HW_ENT (HW_H_GR), 12, 4,
 330     { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } }  },
 331 /* scr: source control register */
 332   { "scr", & HW_ENT (HW_H_CR), 12, 4,
 333     { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } }  },
 334 /* dcr: destination control register */
 335   { "dcr", & HW_ENT (HW_H_CR), 4, 4,
 336     { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } }  },
 337 /* simm8: 8 bit signed immediate */
 338   { "simm8", & HW_ENT (HW_H_SINT), 8, 8,
 339     { 0, 0, { 0 } }  },
 340 /* simm16: 16 bit signed immediate */
 341   { "simm16", & HW_ENT (HW_H_SINT), 16, 16,
 342     { 0, 0, { 0 } }  },
 343 /* uimm4: 4 bit trap number */
 344   { "uimm4", & HW_ENT (HW_H_UINT), 12, 4,
 345     { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } }  },
 346 /* uimm5: 5 bit shift count */
 347   { "uimm5", & HW_ENT (HW_H_UINT), 11, 5,
 348     { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } }  },
 349 /* uimm16: 16 bit unsigned immediate */
 350   { "uimm16", & HW_ENT (HW_H_UINT), 16, 16,
 351     { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } }  },
 352 /* start-sanitize-m32rx */
 353 /* imm1: 1 bit immediate */
 354   { "imm1", & HW_ENT (HW_H_UINT), 15, 1,
 355     { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } }  },
 356 /* end-sanitize-m32rx */
 357 /* start-sanitize-m32rx */
 358 /* accd: accumulator destination register */
 359   { "accd", & HW_ENT (HW_H_ACCUMS), 4, 2,
 360     { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } }  },
 361 /* end-sanitize-m32rx */
 362 /* start-sanitize-m32rx */
 363 /* accs: accumulator source register */
 364   { "accs", & HW_ENT (HW_H_ACCUMS), 12, 2,
 365     { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } }  },
 366 /* end-sanitize-m32rx */
 367 /* start-sanitize-m32rx */
 368 /* acc: accumulator reg (d) */
 369   { "acc", & HW_ENT (HW_H_ACCUMS), 8, 1,
 370     { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } }  },
 371 /* end-sanitize-m32rx */
 372 /* hi16: high 16 bit immediate, sign optional */
 373   { "hi16", & HW_ENT (HW_H_HI16), 16, 16,
 374     { 0, 0|(1<<CGEN_OPERAND_SIGN_OPT)|(1<<CGEN_OPERAND_UNSIGNED), { 0 } }  },
 375 /* slo16: 16 bit signed immediate, for low() */
 376   { "slo16", & HW_ENT (HW_H_SLO16), 16, 16,
 377     { 0, 0, { 0 } }  },
 378 /* ulo16: 16 bit unsigned immediate, for low() */
 379   { "ulo16", & HW_ENT (HW_H_ULO16), 16, 16,
 380     { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } }  },
 381 /* uimm24: 24 bit address */
 382   { "uimm24", & HW_ENT (HW_H_ADDR), 8, 24,
 383     { 0, 0|(1<<CGEN_OPERAND_RELOC)|(1<<CGEN_OPERAND_ABS_ADDR)|(1<<CGEN_OPERAND_UNSIGNED), { 0 } }  },
 384 /* disp8: 8 bit displacement */
 385   { "disp8", & HW_ENT (HW_H_IADDR), 8, 8,
 386     { 0, 0|(1<<CGEN_OPERAND_RELAX)|(1<<CGEN_OPERAND_RELOC)|(1<<CGEN_OPERAND_PCREL_ADDR), { 0 } }  },
 387 /* disp16: 16 bit displacement */
 388   { "disp16", & HW_ENT (HW_H_IADDR), 16, 16,
 389     { 0, 0|(1<<CGEN_OPERAND_RELOC)|(1<<CGEN_OPERAND_PCREL_ADDR), { 0 } }  },
 390 /* disp24: 24 bit displacement */
 391   { "disp24", & HW_ENT (HW_H_IADDR), 8, 24,
 392     { 0, 0|(1<<CGEN_OPERAND_RELAX)|(1<<CGEN_OPERAND_RELOC)|(1<<CGEN_OPERAND_PCREL_ADDR), { 0 } }  },
 393 /* condbit: condition bit */
 394   { "condbit", & HW_ENT (HW_H_COND), 0, 0,
 395     { 0, 0|(1<<CGEN_OPERAND_FAKE), { 0 } }  },
 396 /* accum: accumulator */
 397   { "accum", & HW_ENT (HW_H_ACCUM), 0, 0,
 398     { 0, 0|(1<<CGEN_OPERAND_FAKE), { 0 } }  },
 399 /* start-sanitize-m32rx */
 400 /* abort-parallel-execution: abort parallel execution */
 401   { "abort-parallel-execution", & HW_ENT (HW_H_ABORT), 0, 0,
 402     { 0, 0|(1<<CGEN_OPERAND_FAKE), { 0 } }  },
 403 /* end-sanitize-m32rx */
 404 };
 405
 406 /* Operand references.  */
 407
 408 #define INPUT CGEN_OPERAND_INSTANCE_INPUT
 409 #define OUTPUT CGEN_OPERAND_INSTANCE_OUTPUT
 410
 411 static const CGEN_OPERAND_INSTANCE fmt_0_add_ops[] = {
 412   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
 413   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
 414   { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
 415   { 0 }
 416 };
 417
 418 static const CGEN_OPERAND_INSTANCE fmt_1_add3_ops[] = {
 419   { INPUT, & HW_ENT (HW_H_SLO16), CGEN_MODE_HI, & OP_ENT (SLO16), 0 },
 420   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
 421   { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
 422   { 0 }
 423 };
 424
 425 static const CGEN_OPERAND_INSTANCE fmt_2_and3_ops[] = {
 426   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
 427   { INPUT, & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (UIMM16), 0 },
 428   { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
 429   { 0 }
 430 };
 431
 432 static const CGEN_OPERAND_INSTANCE fmt_3_or3_ops[] = {
 433   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
 434   { INPUT, & HW_ENT (HW_H_ULO16), CGEN_MODE_UHI, & OP_ENT (ULO16), 0 },
 435   { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
 436   { 0 }
 437 };
 438
 439 static const CGEN_OPERAND_INSTANCE fmt_4_addi_ops[] = {
 440   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
 441   { INPUT, & HW_ENT (HW_H_SINT), CGEN_MODE_SI, & OP_ENT (SIMM8), 0 },
 442   { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
 443   { 0 }
 444 };
 445
 446 static const CGEN_OPERAND_INSTANCE fmt_5_addv_ops[] = {
 447   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
 448   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
 449   { OUTPUT, & HW_ENT (HW_H_COND), CGEN_MODE_UBI, 0, 0 },
 450   { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
 451   { 0 }
 452 };
 453
 454 static const CGEN_OPERAND_INSTANCE fmt_6_addv3_ops[] = {
 455   { INPUT, & HW_ENT (HW_H_SINT), CGEN_MODE_SI, & OP_ENT (SIMM16), 0 },
 456   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
 457   { OUTPUT, & HW_ENT (HW_H_COND), CGEN_MODE_UBI, 0, 0 },
 458   { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
 459   { 0 }
 460 };
 461
 462 static const CGEN_OPERAND_INSTANCE fmt_7_addx_ops[] = {
 463   { INPUT, & HW_ENT (HW_H_COND), CGEN_MODE_UBI, 0, 0 },
 464   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
 465   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
 466   { OUTPUT, & HW_ENT (HW_H_COND), CGEN_MODE_UBI, 0, 0 },
 467   { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
 468   { 0 }
 469 };
 470
 471 static const CGEN_OPERAND_INSTANCE fmt_8_bc8_ops[] = {
 472   { INPUT, & HW_ENT (HW_H_COND), CGEN_MODE_UBI, 0, 0 },
 473   { INPUT, & HW_ENT (HW_H_IADDR), CGEN_MODE_VM, & OP_ENT (DISP8), 0 },
 474   { 0 }
 475 };
 476
 477 static const CGEN_OPERAND_INSTANCE fmt_10_bc24_ops[] = {
 478   { INPUT, & HW_ENT (HW_H_COND), CGEN_MODE_UBI, 0, 0 },
 479   { INPUT, & HW_ENT (HW_H_IADDR), CGEN_MODE_VM, & OP_ENT (DISP24), 0 },
 480   { 0 }
 481 };
 482
 483 static const CGEN_OPERAND_INSTANCE fmt_12_beq_ops[] = {
 484   { INPUT, & HW_ENT (HW_H_IADDR), CGEN_MODE_VM, & OP_ENT (DISP16), 0 },
 485   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0 },
 486   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0 },
 487   { 0 }
 488 };
 489
 490 static const CGEN_OPERAND_INSTANCE fmt_13_beqz_ops[] = {
 491   { INPUT, & HW_ENT (HW_H_IADDR), CGEN_MODE_VM, & OP_ENT (DISP16), 0 },
 492   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0 },
 493   { 0 }
 494 };
 495
 496 static const CGEN_OPERAND_INSTANCE fmt_14_bl8_ops[] = {
 497   { INPUT, & HW_ENT (HW_H_IADDR), CGEN_MODE_VM, & OP_ENT (DISP8), 0 },
 498   { INPUT, & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0 },
 499   { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 14 },
 500   { 0 }
 501 };
 502
 503 static const CGEN_OPERAND_INSTANCE fmt_15_bl24_ops[] = {
 504   { INPUT, & HW_ENT (HW_H_IADDR), CGEN_MODE_VM, & OP_ENT (DISP24), 0 },
 505   { INPUT, & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0 },
 506   { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 14 },
 507   { 0 }
 508 };
 509
 510 static const CGEN_OPERAND_INSTANCE fmt_16_bcl8_ops[] = {
 511   { INPUT, & HW_ENT (HW_H_COND), CGEN_MODE_UBI, 0, 0 },
 512   { INPUT, & HW_ENT (HW_H_IADDR), CGEN_MODE_VM, & OP_ENT (DISP8), 0 },
 513   { INPUT, & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0 },
 514   { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 14 },
 515   { 0 }
 516 };
 517
 518 static const CGEN_OPERAND_INSTANCE fmt_17_bcl24_ops[] = {
 519   { INPUT, & HW_ENT (HW_H_COND), CGEN_MODE_UBI, 0, 0 },
 520   { INPUT, & HW_ENT (HW_H_IADDR), CGEN_MODE_VM, & OP_ENT (DISP24), 0 },
 521   { INPUT, & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0 },
 522   { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 14 },
 523   { 0 }
 524 };
 525
 526 static const CGEN_OPERAND_INSTANCE fmt_18_bra8_ops[] = {
 527   { INPUT, & HW_ENT (HW_H_IADDR), CGEN_MODE_VM, & OP_ENT (DISP8), 0 },
 528   { 0 }
 529 };
 530
 531 static const CGEN_OPERAND_INSTANCE fmt_19_bra24_ops[] = {
 532   { INPUT, & HW_ENT (HW_H_IADDR), CGEN_MODE_VM, & OP_ENT (DISP24), 0 },
 533   { 0 }
 534 };
 535
 536 static const CGEN_OPERAND_INSTANCE fmt_20_cmp_ops[] = {
 537   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0 },
 538   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0 },
 539   { OUTPUT, & HW_ENT (HW_H_COND), CGEN_MODE_UBI, 0, 0 },
 540   { 0 }
 541 };
 542
 543 static const CGEN_OPERAND_INSTANCE fmt_21_cmpi_ops[] = {
 544   { INPUT, & HW_ENT (HW_H_SINT), CGEN_MODE_SI, & OP_ENT (SIMM16), 0 },
 545   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0 },
 546   { OUTPUT, & HW_ENT (HW_H_COND), CGEN_MODE_UBI, 0, 0 },
 547   { 0 }
 548 };
 549
 550 static const CGEN_OPERAND_INSTANCE fmt_22_cmpui_ops[] = {
 551   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0 },
 552   { INPUT, & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (UIMM16), 0 },
 553   { OUTPUT, & HW_ENT (HW_H_COND), CGEN_MODE_UBI, 0, 0 },
 554   { 0 }
 555 };
 556
 557 static const CGEN_OPERAND_INSTANCE fmt_23_cmpz_ops[] = {
 558   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0 },
 559   { OUTPUT, & HW_ENT (HW_H_COND), CGEN_MODE_UBI, 0, 0 },
 560   { 0 }
 561 };
 562
 563 static const CGEN_OPERAND_INSTANCE fmt_24_div_ops[] = {
 564   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
 565   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
 566   { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
 567   { 0 }
 568 };
 569
 570 static const CGEN_OPERAND_INSTANCE fmt_25_jc_ops[] = {
 571   { INPUT, & HW_ENT (HW_H_COND), CGEN_MODE_UBI, 0, 0 },
 572   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
 573   { 0 }
 574 };
 575
 576 static const CGEN_OPERAND_INSTANCE fmt_26_jl_ops[] = {
 577   { INPUT, & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0 },
 578   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
 579   { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 14 },
 580   { 0 }
 581 };
 582
 583 static const CGEN_OPERAND_INSTANCE fmt_27_jmp_ops[] = {
 584   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
 585   { 0 }
 586 };
 587
 588 static const CGEN_OPERAND_INSTANCE fmt_28_ld_ops[] = {
 589   { INPUT, & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0 },
 590   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
 591   { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
 592   { 0 }
 593 };
 594
 595 static const CGEN_OPERAND_INSTANCE fmt_30_ld_d_ops[] = {
 596   { INPUT, & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0 },
 597   { INPUT, & HW_ENT (HW_H_SLO16), CGEN_MODE_HI, & OP_ENT (SLO16), 0 },
 598   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
 599   { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
 600   { 0 }
 601 };
 602
 603 static const CGEN_OPERAND_INSTANCE fmt_32_ldb_ops[] = {
 604   { INPUT, & HW_ENT (HW_H_MEMORY), CGEN_MODE_QI, 0, 0 },
 605   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
 606   { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
 607   { 0 }
 608 };
 609
 610 static const CGEN_OPERAND_INSTANCE fmt_33_ldb_d_ops[] = {
 611   { INPUT, & HW_ENT (HW_H_MEMORY), CGEN_MODE_QI, 0, 0 },
 612   { INPUT, & HW_ENT (HW_H_SLO16), CGEN_MODE_HI, & OP_ENT (SLO16), 0 },
 613   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
 614   { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
 615   { 0 }
 616 };
 617
 618 static const CGEN_OPERAND_INSTANCE fmt_34_ldh_ops[] = {
 619   { INPUT, & HW_ENT (HW_H_MEMORY), CGEN_MODE_HI, 0, 0 },
 620   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
 621   { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
 622   { 0 }
 623 };
 624
 625 static const CGEN_OPERAND_INSTANCE fmt_35_ldh_d_ops[] = {
 626   { INPUT, & HW_ENT (HW_H_MEMORY), CGEN_MODE_HI, 0, 0 },
 627   { INPUT, & HW_ENT (HW_H_SLO16), CGEN_MODE_HI, & OP_ENT (SLO16), 0 },
 628   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
 629   { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
 630   { 0 }
 631 };
 632
 633 static const CGEN_OPERAND_INSTANCE fmt_36_ld_plus_ops[] = {
 634   { INPUT, & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0 },
 635   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
 636   { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
 637   { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
 638   { 0 }
 639 };
 640
 641 static const CGEN_OPERAND_INSTANCE fmt_37_ld24_ops[] = {
 642   { INPUT, & HW_ENT (HW_H_ADDR), CGEN_MODE_VM, & OP_ENT (UIMM24), 0 },
 643   { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
 644   { 0 }
 645 };
 646
 647 static const CGEN_OPERAND_INSTANCE fmt_38_ldi8_ops[] = {
 648   { INPUT, & HW_ENT (HW_H_SINT), CGEN_MODE_SI, & OP_ENT (SIMM8), 0 },
 649   { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
 650   { 0 }
 651 };
 652
 653 static const CGEN_OPERAND_INSTANCE fmt_39_ldi16_ops[] = {
 654   { INPUT, & HW_ENT (HW_H_SLO16), CGEN_MODE_HI, & OP_ENT (SLO16), 0 },
 655   { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
 656   { 0 }
 657 };
 658
 659 static const CGEN_OPERAND_INSTANCE fmt_40_lock_ops[] = {
 660   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
 661   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
 662   { 0 }
 663 };
 664
 665 static const CGEN_OPERAND_INSTANCE fmt_41_machi_ops[] = {
 666   { INPUT, & HW_ENT (HW_H_ACCUM), CGEN_MODE_DI, 0, 0 },
 667   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0 },
 668   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0 },
 669   { OUTPUT, & HW_ENT (HW_H_ACCUM), CGEN_MODE_DI, 0, 0 },
 670   { 0 }
 671 };
 672
 673 static const CGEN_OPERAND_INSTANCE fmt_42_machi_a_ops[] = {
 674   { INPUT, & HW_ENT (HW_H_ACCUMS), CGEN_MODE_DI, & OP_ENT (ACC), 0 },
 675   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0 },
 676   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0 },
 677   { OUTPUT, & HW_ENT (HW_H_ACCUMS), CGEN_MODE_DI, & OP_ENT (ACC), 0 },
 678   { 0 }
 679 };
 680
 681 static const CGEN_OPERAND_INSTANCE fmt_43_mulhi_ops[] = {
 682   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0 },
 683   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0 },
 684   { OUTPUT, & HW_ENT (HW_H_ACCUM), CGEN_MODE_DI, 0, 0 },
 685   { 0 }
 686 };
 687
 688 static const CGEN_OPERAND_INSTANCE fmt_44_mulhi_a_ops[] = {
 689   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0 },
 690   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0 },
 691   { OUTPUT, & HW_ENT (HW_H_ACCUMS), CGEN_MODE_DI, & OP_ENT (ACC), 0 },
 692   { 0 }
 693 };
 694
 695 static const CGEN_OPERAND_INSTANCE fmt_45_mv_ops[] = {
 696   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
 697   { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
 698   { 0 }
 699 };
 700
 701 static const CGEN_OPERAND_INSTANCE fmt_46_mvfachi_ops[] = {
 702   { INPUT, & HW_ENT (HW_H_ACCUM), CGEN_MODE_DI, 0, 0 },
 703   { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
 704   { 0 }
 705 };
 706
 707 static const CGEN_OPERAND_INSTANCE fmt_47_mvfachi_a_ops[] = {
 708   { INPUT, & HW_ENT (HW_H_ACCUMS), CGEN_MODE_DI, & OP_ENT (ACCS), 0 },
 709   { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
 710   { 0 }
 711 };
 712
 713 static const CGEN_OPERAND_INSTANCE fmt_48_mvfc_ops[] = {
 714   { INPUT, & HW_ENT (HW_H_CR), CGEN_MODE_SI, & OP_ENT (SCR), 0 },
 715   { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
 716   { 0 }
 717 };
 718
 719 static const CGEN_OPERAND_INSTANCE fmt_49_mvtachi_ops[] = {
 720   { INPUT, & HW_ENT (HW_H_ACCUM), CGEN_MODE_DI, 0, 0 },
 721   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0 },
 722   { OUTPUT, & HW_ENT (HW_H_ACCUM), CGEN_MODE_DI, 0, 0 },
 723   { 0 }
 724 };
 725
 726 static const CGEN_OPERAND_INSTANCE fmt_50_mvtachi_a_ops[] = {
 727   { INPUT, & HW_ENT (HW_H_ACCUMS), CGEN_MODE_DI, & OP_ENT (ACCS), 0 },
 728   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0 },
 729   { OUTPUT, & HW_ENT (HW_H_ACCUMS), CGEN_MODE_DI, & OP_ENT (ACCS), 0 },
 730   { 0 }
 731 };
 732
 733 static const CGEN_OPERAND_INSTANCE fmt_51_mvtc_ops[] = {
 734   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
 735   { OUTPUT, & HW_ENT (HW_H_CR), CGEN_MODE_SI, & OP_ENT (DCR), 0 },
 736   { 0 }
 737 };
 738
 739 static const CGEN_OPERAND_INSTANCE fmt_53_rac_ops[] = {
 740   { INPUT, & HW_ENT (HW_H_ACCUM), CGEN_MODE_DI, 0, 0 },
 741   { OUTPUT, & HW_ENT (HW_H_ACCUM), CGEN_MODE_DI, 0, 0 },
 742   { 0 }
 743 };
 744
 745 static const CGEN_OPERAND_INSTANCE fmt_54_rac_d_ops[] = {
 746   { INPUT, & HW_ENT (HW_H_ACCUM), CGEN_MODE_DI, 0, 0 },
 747   { OUTPUT, & HW_ENT (HW_H_ACCUMS), CGEN_MODE_DI, & OP_ENT (ACCD), 0 },
 748   { 0 }
 749 };
 750
 751 static const CGEN_OPERAND_INSTANCE fmt_55_rac_ds_ops[] = {
 752   { INPUT, & HW_ENT (HW_H_ACCUMS), CGEN_MODE_DI, & OP_ENT (ACCS), 0 },
 753   { OUTPUT, & HW_ENT (HW_H_ACCUMS), CGEN_MODE_DI, & OP_ENT (ACCD), 0 },
 754   { 0 }
 755 };
 756
 757 static const CGEN_OPERAND_INSTANCE fmt_56_rac_dsi_ops[] = {
 758   { INPUT, & HW_ENT (HW_H_ACCUMS), CGEN_MODE_DI, & OP_ENT (ACCS), 0 },
 759   { INPUT, & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (IMM1), 0 },
 760   { OUTPUT, & HW_ENT (HW_H_ACCUMS), CGEN_MODE_DI, & OP_ENT (ACCD), 0 },
 761   { 0 }
 762 };
 763
 764 static const CGEN_OPERAND_INSTANCE fmt_57_rte_ops[] = {
 765   { INPUT, & HW_ENT (HW_H_BCOND), CGEN_MODE_VM, 0, 0 },
 766   { INPUT, & HW_ENT (HW_H_BIE), CGEN_MODE_VM, 0, 0 },
 767   { INPUT, & HW_ENT (HW_H_BPC), CGEN_MODE_VM, 0, 0 },
 768   { INPUT, & HW_ENT (HW_H_BSM), CGEN_MODE_VM, 0, 0 },
 769   { OUTPUT, & HW_ENT (HW_H_COND), CGEN_MODE_UBI, 0, 0 },
 770   { OUTPUT, & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0 },
 771   { OUTPUT, & HW_ENT (HW_H_IE), CGEN_MODE_VM, 0, 0 },
 772   { OUTPUT, & HW_ENT (HW_H_SM), CGEN_MODE_VM, 0, 0 },
 773   { 0 }
 774 };
 775
 776 static const CGEN_OPERAND_INSTANCE fmt_58_seth_ops[] = {
 777   { INPUT, & HW_ENT (HW_H_HI16), CGEN_MODE_UHI, & OP_ENT (HI16), 0 },
 778   { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
 779   { 0 }
 780 };
 781
 782 static const CGEN_OPERAND_INSTANCE fmt_59_sll3_ops[] = {
 783   { INPUT, & HW_ENT (HW_H_SINT), CGEN_MODE_SI, & OP_ENT (SIMM16), 0 },
 784   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
 785   { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
 786   { 0 }
 787 };
 788
 789 static const CGEN_OPERAND_INSTANCE fmt_60_slli_ops[] = {
 790   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
 791   { INPUT, & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (UIMM5), 0 },
 792   { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
 793   { 0 }
 794 };
 795
 796 static const CGEN_OPERAND_INSTANCE fmt_61_st_ops[] = {
 797   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0 },
 798   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0 },
 799   { OUTPUT, & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0 },
 800   { 0 }
 801 };
 802
 803 static const CGEN_OPERAND_INSTANCE fmt_63_st_d_ops[] = {
 804   { INPUT, & HW_ENT (HW_H_SLO16), CGEN_MODE_HI, & OP_ENT (SLO16), 0 },
 805   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0 },
 806   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0 },
 807   { OUTPUT, & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0 },
 808   { 0 }
 809 };
 810
 811 static const CGEN_OPERAND_INSTANCE fmt_65_stb_ops[] = {
 812   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0 },
 813   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0 },
 814   { OUTPUT, & HW_ENT (HW_H_MEMORY), CGEN_MODE_QI, 0, 0 },
 815   { 0 }
 816 };
 817
 818 static const CGEN_OPERAND_INSTANCE fmt_66_stb_d_ops[] = {
 819   { INPUT, & HW_ENT (HW_H_SLO16), CGEN_MODE_HI, & OP_ENT (SLO16), 0 },
 820   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0 },
 821   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0 },
 822   { OUTPUT, & HW_ENT (HW_H_MEMORY), CGEN_MODE_QI, 0, 0 },
 823   { 0 }
 824 };
 825
 826 static const CGEN_OPERAND_INSTANCE fmt_67_sth_ops[] = {
 827   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0 },
 828   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0 },
 829   { OUTPUT, & HW_ENT (HW_H_MEMORY), CGEN_MODE_HI, 0, 0 },
 830   { 0 }
 831 };
 832
 833 static const CGEN_OPERAND_INSTANCE fmt_68_sth_d_ops[] = {
 834   { INPUT, & HW_ENT (HW_H_SLO16), CGEN_MODE_HI, & OP_ENT (SLO16), 0 },
 835   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0 },
 836   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0 },
 837   { OUTPUT, & HW_ENT (HW_H_MEMORY), CGEN_MODE_HI, 0, 0 },
 838   { 0 }
 839 };
 840
 841 static const CGEN_OPERAND_INSTANCE fmt_69_st_plus_ops[] = {
 842   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0 },
 843   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0 },
 844   { OUTPUT, & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0 },
 845   { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0 },
 846   { 0 }
 847 };
 848
 849 static const CGEN_OPERAND_INSTANCE fmt_70_trap_ops[] = {
 850   { INPUT, & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (UIMM4), 0 },
 851   { 0 }
 852 };
 853
 854 static const CGEN_OPERAND_INSTANCE fmt_71_unlock_ops[] = {
 855   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0 },
 856   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0 },
 857   { 0 }
 858 };
 859
 860 static const CGEN_OPERAND_INSTANCE fmt_74_satb_ops[] = {
 861   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0 },
 862   { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
 863   { 0 }
 864 };
 865
 866 static const CGEN_OPERAND_INSTANCE fmt_75_sat_ops[] = {
 867   { INPUT, & HW_ENT (HW_H_COND), CGEN_MODE_UBI, 0, 0 },
 868   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0 },
 869   { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
 870   { 0 }
 871 };
 872
 873 static const CGEN_OPERAND_INSTANCE fmt_76_sadd_ops[] = {
 874   { INPUT, & HW_ENT (HW_H_ACCUMS), CGEN_MODE_DI, 0, 0 },
 875   { INPUT, & HW_ENT (HW_H_ACCUMS), CGEN_MODE_DI, 0, 1 },
 876   { OUTPUT, & HW_ENT (HW_H_ACCUMS), CGEN_MODE_DI, 0, 0 },
 877   { 0 }
 878 };
 879
 880 static const CGEN_OPERAND_INSTANCE fmt_77_macwu1_ops[] = {
 881   { INPUT, & HW_ENT (HW_H_ACCUMS), CGEN_MODE_DI, 0, 1 },
 882   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0 },
 883   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0 },
 884   { OUTPUT, & HW_ENT (HW_H_ACCUMS), CGEN_MODE_DI, 0, 1 },
 885   { 0 }
 886 };
 887
 888 static const CGEN_OPERAND_INSTANCE fmt_78_mulwu1_ops[] = {
 889   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0 },
 890   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0 },
 891   { OUTPUT, & HW_ENT (HW_H_ACCUMS), CGEN_MODE_DI, 0, 1 },
 892   { 0 }
 893 };
 894
 895 static const CGEN_OPERAND_INSTANCE fmt_79_sc_ops[] = {
 896   { INPUT, & HW_ENT (HW_H_COND), CGEN_MODE_UBI, 0, 0 },
 897   { OUTPUT, & HW_ENT (HW_H_ABORT), CGEN_MODE_UBI, 0, 0 },
 898   { 0 }
 899 };
 900
 901 #undef INPUT
 902 #undef OUTPUT
 903
 904 #define OP 1 /* syntax value for mnemonic */
 905
 906 static const CGEN_SYNTAX syntax_table[] =
 907 {
 908 /* <op> $dr,$sr */
 909 /*   0 */  { OP, ' ', 130, ',', 129, 0 },
 910 /* <op> $dr,$sr,#$slo16 */
 911 /*   1 */  { OP, ' ', 130, ',', 129, ',', '#', 145, 0 },
 912 /* <op> $dr,$sr,$slo16 */
 913 /*   2 */  { OP, ' ', 130, ',', 129, ',', 145, 0 },
 914 /* <op> $dr,$sr,#$uimm16 */
 915 /*   3 */  { OP, ' ', 130, ',', 129, ',', '#', 139, 0 },
 916 /* <op> $dr,$sr,$uimm16 */
 917 /*   4 */  { OP, ' ', 130, ',', 129, ',', 139, 0 },
 918 /* <op> $dr,$sr,#$ulo16 */
 919 /*   5 */  { OP, ' ', 130, ',', 129, ',', '#', 146, 0 },
 920 /* <op> $dr,$sr,$ulo16 */
 921 /*   6 */  { OP, ' ', 130, ',', 129, ',', 146, 0 },
 922 /* <op> $dr,#$simm8 */
 923 /*   7 */  { OP, ' ', 130, ',', '#', 135, 0 },
 924 /* <op> $dr,$simm8 */
 925 /*   8 */  { OP, ' ', 130, ',', 135, 0 },
 926 /* <op> $dr,$sr,#$simm16 */
 927 /*   9 */  { OP, ' ', 130, ',', 129, ',', '#', 136, 0 },
 928 /* <op> $dr,$sr,$simm16 */
 929 /*  10 */  { OP, ' ', 130, ',', 129, ',', 136, 0 },
 930 /* <op> $disp8 */
 931 /*  11 */  { OP, ' ', 148, 0 },
 932 /* <op> $disp24 */
 933 /*  12 */  { OP, ' ', 150, 0 },
 934 /* <op> $src1,$src2,$disp16 */
 935 /*  13 */  { OP, ' ', 131, ',', 132, ',', 149, 0 },
 936 /* <op> $src2,$disp16 */
 937 /*  14 */  { OP, ' ', 132, ',', 149, 0 },
 938 /* <op> $src1,$src2 */
 939 /*  15 */  { OP, ' ', 131, ',', 132, 0 },
 940 /* <op> $src2,#$simm16 */
 941 /*  16 */  { OP, ' ', 132, ',', '#', 136, 0 },
 942 /* <op> $src2,$simm16 */
 943 /*  17 */  { OP, ' ', 132, ',', 136, 0 },
 944 /* <op> $src2,#$uimm16 */
 945 /*  18 */  { OP, ' ', 132, ',', '#', 139, 0 },
 946 /* <op> $src2,$uimm16 */
 947 /*  19 */  { OP, ' ', 132, ',', 139, 0 },
 948 /* <op> $src2 */
 949 /*  20 */  { OP, ' ', 132, 0 },
 950 /* <op> $sr */
 951 /*  21 */  { OP, ' ', 129, 0 },
 952 /* <op> $dr,@$sr */
 953 /*  22 */  { OP, ' ', 130, ',', '@', 129, 0 },
 954 /* <op> $dr,@($sr) */
 955 /*  23 */  { OP, ' ', 130, ',', '@', '(', 129, ')', 0 },
 956 /* <op> $dr,@($slo16,$sr) */
 957 /*  24 */  { OP, ' ', 130, ',', '@', '(', 145, ',', 129, ')', 0 },
 958 /* <op> $dr,@($sr,$slo16) */
 959 /*  25 */  { OP, ' ', 130, ',', '@', '(', 129, ',', 145, ')', 0 },
 960 /* <op> $dr,@$sr+ */
 961 /*  26 */  { OP, ' ', 130, ',', '@', 129, '+', 0 },
 962 /* <op> $dr,#$uimm24 */
 963 /*  27 */  { OP, ' ', 130, ',', '#', 147, 0 },
 964 /* <op> $dr,$uimm24 */
 965 /*  28 */  { OP, ' ', 130, ',', 147, 0 },
 966 /* <op> $dr,$slo16 */
 967 /*  29 */  { OP, ' ', 130, ',', 145, 0 },
 968 /* <op> $src1,$src2,$acc */
 969 /*  30 */  { OP, ' ', 131, ',', 132, ',', 143, 0 },
 970 /* <op> $dr */
 971 /*  31 */  { OP, ' ', 130, 0 },
 972 /* <op> $dr,$accs */
 973 /*  32 */  { OP, ' ', 130, ',', 142, 0 },
 974 /* <op> $dr,$scr */
 975 /*  33 */  { OP, ' ', 130, ',', 133, 0 },
 976 /* <op> $src1 */
 977 /*  34 */  { OP, ' ', 131, 0 },
 978 /* <op> $src1,$accs */
 979 /*  35 */  { OP, ' ', 131, ',', 142, 0 },
 980 /* <op> $sr,$dcr */
 981 /*  36 */  { OP, ' ', 129, ',', 134, 0 },
 982 /* <op> */
 983 /*  37 */  { OP, 0 },
 984 /* <op> $accd */
 985 /*  38 */  { OP, ' ', 141, 0 },
 986 /* <op> $accd,$accs */
 987 /*  39 */  { OP, ' ', 141, ',', 142, 0 },
 988 /* <op> $accd,$accs,#$imm1 */
 989 /*  40 */  { OP, ' ', 141, ',', 142, ',', '#', 140, 0 },
 990 /* <op> $dr,#$hi16 */
 991 /*  41 */  { OP, ' ', 130, ',', '#', 144, 0 },
 992 /* <op> $dr,$hi16 */
 993 /*  42 */  { OP, ' ', 130, ',', 144, 0 },
 994 /* <op> $dr,#$uimm5 */
 995 /*  43 */  { OP, ' ', 130, ',', '#', 138, 0 },
 996 /* <op> $dr,$uimm5 */
 997 /*  44 */  { OP, ' ', 130, ',', 138, 0 },
 998 /* <op> $src1,@$src2 */
 999 /*  45 */  { OP, ' ', 131, ',', '@', 132, 0 },
1000 /* <op> $src1,@($src2) */
1001 /*  46 */  { OP, ' ', 131, ',', '@', '(', 132, ')', 0 },
1002 /* <op> $src1,@($slo16,$src2) */
1003 /*  47 */  { OP, ' ', 131, ',', '@', '(', 145, ',', 132, ')', 0 },
1004 /* <op> $src1,@($src2,$slo16) */
1005 /*  48 */  { OP, ' ', 131, ',', '@', '(', 132, ',', 145, ')', 0 },
1006 /* <op> $src1,@+$src2 */
1007 /*  49 */  { OP, ' ', 131, ',', '@', '+', 132, 0 },
1008 /* <op> $src1,@-$src2 */
1009 /*  50 */  { OP, ' ', 131, ',', '@', '-', 132, 0 },
1010 /* <op> #$uimm4 */
1011 /*  51 */  { OP, ' ', '#', 137, 0 },
1012 /* <op> $uimm4 */
1013 /*  52 */  { OP, ' ', 137, 0 },
1014 /* <op> $dr,$src2 */
1015 /*  53 */  { OP, ' ', 130, ',', 132, 0 },
1016 };
1017
1018 #undef OP
1019
1020 static const CGEN_FORMAT format_table[] =
1021 {
1022 /* (f-op1 #)(f-r1 dr)(f-op2 #)(f-r2 sr)(dr SI)(sr SI)(dr SI) */
1023 /*   0 */  { 16, 16, 0xf0f0 },
1024 /* (f-op1 #)(f-r1 dr)(f-op2 #)(f-r2 sr)(f-simm16 slo16)(slo16 HI)(sr SI)(dr SI) */
1025 /*   1 */  { 32, 32, 0xf0f00000 },
1026 /* (f-op1 #)(f-r1 dr)(f-op2 #)(f-r2 sr)(f-uimm16 uimm16)(sr SI)(uimm16 USI)(dr SI) */
1027 /*   2 */  { 32, 32, 0xf0f00000 },
1028 /* (f-op1 #)(f-r1 dr)(f-op2 #)(f-r2 sr)(f-uimm16 ulo16)(sr SI)(ulo16 UHI)(dr SI) */
1029 /*   3 */  { 32, 32, 0xf0f00000 },
1030 /* (f-op1 #)(f-r1 dr)(f-simm8 simm8)(dr SI)(simm8 SI)(dr SI) */
1031 /*   4 */  { 16, 16, 0xf000 },
1032 /* (f-op1 #)(f-r1 dr)(f-op2 #)(f-r2 sr)(dr SI)(sr SI)(condbit UBI)(dr SI) */
1033 /*   5 */  { 16, 16, 0xf0f0 },
1034 /* (f-op1 #)(f-r1 dr)(f-op2 #)(f-r2 sr)(f-simm16 simm16)(simm16 SI)(sr SI)(condbit UBI)(dr SI) */
1035 /*   6 */  { 32, 32, 0xf0f00000 },
1036 /* (f-op1 #)(f-r1 dr)(f-op2 #)(f-r2 sr)(condbit UBI)(dr SI)(sr SI)(condbit UBI)(dr SI) */
1037 /*   7 */  { 16, 16, 0xf0f0 },
1038 /* (f-op1 #)(f-r1 #)(f-disp8 disp8)(condbit UBI)(disp8 VM) */
1039 /*   8 */  { 16, 16, 0xff00 },
1040 /* (f-op1 #)(f-r1 #)(f-disp8 disp8) */
1041 /*   9 */  { 16, 16, 0xff00 },
1042 /* (f-op1 #)(f-r1 #)(f-disp24 disp24)(condbit UBI)(disp24 VM) */
1043 /*  10 */  { 32, 32, 0xff000000 },
1044 /* (f-op1 #)(f-r1 #)(f-disp24 disp24) */
1045 /*  11 */  { 32, 32, 0xff000000 },
1046 /* (f-op1 #)(f-r1 src1)(f-op2 #)(f-r2 src2)(f-disp16 disp16)(disp16 VM)(src1 SI)(src2 SI) */
1047 /*  12 */  { 32, 32, 0xf0f00000 },
1048 /* (f-op1 #)(f-r1 #)(f-op2 #)(f-r2 src2)(f-disp16 disp16)(disp16 VM)(src2 SI) */
1049 /*  13 */  { 32, 32, 0xfff00000 },
1050 /* (f-op1 #)(f-r1 #)(f-disp8 disp8)(disp8 VM)(pc USI)(h-gr-14 SI) */
1051 /*  14 */  { 16, 16, 0xff00 },
1052 /* (f-op1 #)(f-r1 #)(f-disp24 disp24)(disp24 VM)(pc USI)(h-gr-14 SI) */
1053 /*  15 */  { 32, 32, 0xff000000 },
1054 /* (f-op1 #)(f-r1 #)(f-disp8 disp8)(condbit UBI)(disp8 VM)(pc USI)(h-gr-14 SI) */
1055 /*  16 */  { 16, 16, 0xff00 },
1056 /* (f-op1 #)(f-r1 #)(f-disp24 disp24)(condbit UBI)(disp24 VM)(pc USI)(h-gr-14 SI) */
1057 /*  17 */  { 32, 32, 0xff000000 },
1058 /* (f-op1 #)(f-r1 #)(f-disp8 disp8)(disp8 VM) */
1059 /*  18 */  { 16, 16, 0xff00 },
1060 /* (f-op1 #)(f-r1 #)(f-disp24 disp24)(disp24 VM) */
1061 /*  19 */  { 32, 32, 0xff000000 },
1062 /* (f-op1 #)(f-r1 src1)(f-op2 #)(f-r2 src2)(src1 SI)(src2 SI)(condbit UBI) */
1063 /*  20 */  { 16, 16, 0xf0f0 },
1064 /* (f-op1 #)(f-r1 #)(f-op2 #)(f-r2 src2)(f-simm16 simm16)(simm16 SI)(src2 SI)(condbit UBI) */
1065 /*  21 */  { 32, 32, 0xfff00000 },
1066 /* (f-op1 #)(f-r1 #)(f-op2 #)(f-r2 src2)(f-uimm16 uimm16)(src2 SI)(uimm16 USI)(condbit UBI) */
1067 /*  22 */  { 32, 32, 0xfff00000 },
1068 /* (f-op1 #)(f-r1 #)(f-op2 #)(f-r2 src2)(src2 SI)(condbit UBI) */
1069 /*  23 */  { 16, 16, 0xfff0 },
1070 /* (f-op1 #)(f-r1 dr)(f-op2 #)(f-r2 sr)(f-simm16 #)(dr SI)(sr SI)(dr SI) */
1071 /*  24 */  { 32, 32, 0xf0f0ffff },
1072 /* (f-op1 #)(f-r1 #)(f-op2 #)(f-r2 sr)(condbit UBI)(sr SI) */
1073 /*  25 */  { 16, 16, 0xfff0 },
1074 /* (f-op1 #)(f-r1 #)(f-op2 #)(f-r2 sr)(pc USI)(sr SI)(h-gr-14 SI) */
1075 /*  26 */  { 16, 16, 0xfff0 },
1076 /* (f-op1 #)(f-r1 #)(f-op2 #)(f-r2 sr)(sr SI) */
1077 /*  27 */  { 16, 16, 0xfff0 },
1078 /* (f-op1 #)(f-r1 dr)(f-op2 #)(f-r2 sr)(h-memory-sr SI)(sr SI)(dr SI) */
1079 /*  28 */  { 16, 16, 0xf0f0 },
1080 /* (f-op1 #)(f-r1 dr)(f-op2 #)(f-r2 sr) */
1081 /*  29 */  { 16, 16, 0xf0f0 },
1082 /* (f-op1 #)(f-r1 dr)(f-op2 #)(f-r2 sr)(f-simm16 slo16)(h-memory-add-WI-sr-slo16 SI)(slo16 HI)(sr SI)(dr SI) */
1083 /*  30 */  { 32, 32, 0xf0f00000 },
1084 /* (f-op1 #)(f-r1 dr)(f-op2 #)(f-r2 sr)(f-simm16 slo16) */
1085 /*  31 */  { 32, 32, 0xf0f00000 },
1086 /* (f-op1 #)(f-r1 dr)(f-op2 #)(f-r2 sr)(h-memory-sr QI)(sr SI)(dr SI) */
1087 /*  32 */  { 16, 16, 0xf0f0 },
1088 /* (f-op1 #)(f-r1 dr)(f-op2 #)(f-r2 sr)(f-simm16 slo16)(h-memory-add-WI-sr-slo16 QI)(slo16 HI)(sr SI)(dr SI) */
1089 /*  33 */  { 32, 32, 0xf0f00000 },
1090 /* (f-op1 #)(f-r1 dr)(f-op2 #)(f-r2 sr)(h-memory-sr HI)(sr SI)(dr SI) */
1091 /*  34 */  { 16, 16, 0xf0f0 },
1092 /* (f-op1 #)(f-r1 dr)(f-op2 #)(f-r2 sr)(f-simm16 slo16)(h-memory-add-WI-sr-slo16 HI)(slo16 HI)(sr SI)(dr SI) */
1093 /*  35 */  { 32, 32, 0xf0f00000 },
1094 /* (f-op1 #)(f-r1 dr)(f-op2 #)(f-r2 sr)(h-memory-sr SI)(sr SI)(dr SI)(sr SI) */
1095 /*  36 */  { 16, 16, 0xf0f0 },
1096 /* (f-op1 #)(f-r1 dr)(f-uimm24 uimm24)(uimm24 VM)(dr SI) */
1097 /*  37 */  { 32, 32, 0xf0000000 },
1098 /* (f-op1 #)(f-r1 dr)(f-simm8 simm8)(simm8 SI)(dr SI) */
1099 /*  38 */  { 16, 16, 0xf000 },
1100 /* (f-op1 #)(f-r1 dr)(f-op2 #)(f-r2 #)(f-simm16 slo16)(slo16 HI)(dr SI) */
1101 /*  39 */  { 32, 32, 0xf0ff0000 },
1102 /* (f-op1 #)(f-r1 dr)(f-op2 #)(f-r2 sr)(dr SI)(sr SI) */
1103 /*  40 */  { 16, 16, 0xf0f0 },
1104 /* (f-op1 #)(f-r1 src1)(f-op2 #)(f-r2 src2)(accum DI)(src1 SI)(src2 SI)(accum DI) */
1105 /*  41 */  { 16, 16, 0xf0f0 },
1106 /* (f-op1 #)(f-r1 src1)(f-acc acc)(f-op23 #)(f-r2 src2)(acc DI)(src1 SI)(src2 SI)(acc DI) */
1107 /*  42 */  { 16, 16, 0xf070 },
1108 /* (f-op1 #)(f-r1 src1)(f-op2 #)(f-r2 src2)(src1 SI)(src2 SI)(accum DI) */
1109 /*  43 */  { 16, 16, 0xf0f0 },
1110 /* (f-op1 #)(f-r1 src1)(f-acc acc)(f-op23 #)(f-r2 src2)(src1 SI)(src2 SI)(acc DI) */
1111 /*  44 */  { 16, 16, 0xf070 },
1112 /* (f-op1 #)(f-r1 dr)(f-op2 #)(f-r2 sr)(sr SI)(dr SI) */
1113 /*  45 */  { 16, 16, 0xf0f0 },
1114 /* (f-op1 #)(f-r1 dr)(f-op2 #)(f-r2 #)(accum DI)(dr SI) */
1115 /*  46 */  { 16, 16, 0xf0ff },
1116 /* (f-op1 #)(f-r1 dr)(f-op2 #)(f-accs accs)(f-op3 #)(accs DI)(dr SI) */
1117 /*  47 */  { 16, 16, 0xf0f3 },
1118 /* (f-op1 #)(f-r1 dr)(f-op2 #)(f-r2 scr)(scr SI)(dr SI) */
1119 /*  48 */  { 16, 16, 0xf0f0 },
1120 /* (f-op1 #)(f-r1 src1)(f-op2 #)(f-r2 #)(accum DI)(src1 SI)(accum DI) */
1121 /*  49 */  { 16, 16, 0xf0ff },
1122 /* (f-op1 #)(f-r1 src1)(f-op2 #)(f-accs accs)(f-op3 #)(accs DI)(src1 SI)(accs DI) */
1123 /*  50 */  { 16, 16, 0xf0f3 },
1124 /* (f-op1 #)(f-r1 dcr)(f-op2 #)(f-r2 sr)(sr SI)(dcr SI) */
1125 /*  51 */  { 16, 16, 0xf0f0 },
1126 /* (f-op1 #)(f-r1 #)(f-op2 #)(f-r2 #) */
1127 /*  52 */  { 16, 16, 0xffff },
1128 /* (f-op1 #)(f-r1 #)(f-op2 #)(f-r2 #)(accum DI)(accum DI) */
1129 /*  53 */  { 16, 16, 0xffff },
1130 /* (f-op1 #)(f-accd accd)(f-bits67 #)(f-op2 #)(f-accs #)(f-bit14 #)(f-imm1 #)(accum DI)(accd DI) */
1131 /*  54 */  { 16, 16, 0xf3ff },
1132 /* (f-op1 #)(f-accd accd)(f-bits67 #)(f-op2 #)(f-accs accs)(f-bit14 #)(f-imm1 #)(accs DI)(accd DI) */
1133 /*  55 */  { 16, 16, 0xf3f3 },
1134 /* (f-op1 #)(f-accd accd)(f-bits67 #)(f-op2 #)(f-accs accs)(f-bit14 #)(f-imm1 imm1)(accs DI)(imm1 USI)(accd DI) */
1135 /*  56 */  { 16, 16, 0xf3f2 },
1136 /* (f-op1 #)(f-r1 #)(f-op2 #)(f-r2 #)(h-bcond-0 VM)(h-bie-0 VM)(h-bpc-0 VM)(h-bsm-0 VM)(condbit UBI)(pc USI)(h-ie-0 VM)(h-sm-0 VM) */
1137 /*  57 */  { 16, 16, 0xffff },
1138 /* (f-op1 #)(f-r1 dr)(f-op2 #)(f-r2 #)(f-hi16 hi16)(hi16 UHI)(dr SI) */
1139 /*  58 */  { 32, 32, 0xf0ff0000 },
1140 /* (f-op1 #)(f-r1 dr)(f-op2 #)(f-r2 sr)(f-simm16 simm16)(simm16 SI)(sr SI)(dr SI) */
1141 /*  59 */  { 32, 32, 0xf0f00000 },
1142 /* (f-op1 #)(f-r1 dr)(f-shift-op2 #)(f-uimm5 uimm5)(dr SI)(uimm5 USI)(dr SI) */
1143 /*  60 */  { 16, 16, 0xf0e0 },
1144 /* (f-op1 #)(f-r1 src1)(f-op2 #)(f-r2 src2)(src1 SI)(src2 SI)(h-memory-src2 SI) */
1145 /*  61 */  { 16, 16, 0xf0f0 },
1146 /* (f-op1 #)(f-r1 src1)(f-op2 #)(f-r2 src2) */
1147 /*  62 */  { 16, 16, 0xf0f0 },
1148 /* (f-op1 #)(f-r1 src1)(f-op2 #)(f-r2 src2)(f-simm16 slo16)(slo16 HI)(src1 SI)(src2 SI)(h-memory-add-WI-src2-slo16 SI) */
1149 /*  63 */  { 32, 32, 0xf0f00000 },
1150 /* (f-op1 #)(f-r1 src1)(f-op2 #)(f-r2 src2)(f-simm16 slo16) */
1151 /*  64 */  { 32, 32, 0xf0f00000 },
1152 /* (f-op1 #)(f-r1 src1)(f-op2 #)(f-r2 src2)(src1 SI)(src2 SI)(h-memory-src2 QI) */
1153 /*  65 */  { 16, 16, 0xf0f0 },
1154 /* (f-op1 #)(f-r1 src1)(f-op2 #)(f-r2 src2)(f-simm16 slo16)(slo16 HI)(src1 SI)(src2 SI)(h-memory-add-WI-src2-slo16 QI) */
1155 /*  66 */  { 32, 32, 0xf0f00000 },
1156 /* (f-op1 #)(f-r1 src1)(f-op2 #)(f-r2 src2)(src1 SI)(src2 SI)(h-memory-src2 HI) */
1157 /*  67 */  { 16, 16, 0xf0f0 },
1158 /* (f-op1 #)(f-r1 src1)(f-op2 #)(f-r2 src2)(f-simm16 slo16)(slo16 HI)(src1 SI)(src2 SI)(h-memory-add-WI-src2-slo16 HI) */
1159 /*  68 */  { 32, 32, 0xf0f00000 },
1160 /* (f-op1 #)(f-r1 src1)(f-op2 #)(f-r2 src2)(src1 SI)(src2 SI)(h-memory-src2 SI)(src2 SI) */
1161 /*  69 */  { 16, 16, 0xf0f0 },
1162 /* (f-op1 #)(f-r1 #)(f-op2 #)(f-uimm4 uimm4)(uimm4 USI) */
1163 /*  70 */  { 16, 16, 0xfff0 },
1164 /* (f-op1 #)(f-r1 src1)(f-op2 #)(f-r2 src2)(src1 SI)(src2 SI) */
1165 /*  71 */  { 16, 16, 0xf0f0 },
1166 /* (f-op1 #)(f-r1 src1)(f-op2 #)(f-r2 #) */
1167 /*  72 */  { 16, 16, 0xf0ff },
1168 /* (f-op1 #)(f-r1 dr)(f-op2 #)(f-r2 #) */
1169 /*  73 */  { 16, 16, 0xf0ff },
1170 /* (f-op1 #)(f-r1 dr)(f-op2 #)(f-r2 src2)(f-uimm16 #)(src2 SI)(dr SI) */
1171 /*  74 */  { 32, 32, 0xf0f0ffff },
1172 /* (f-op1 #)(f-r1 dr)(f-op2 #)(f-r2 src2)(f-uimm16 #)(condbit UBI)(src2 SI)(dr SI) */
1173 /*  75 */  { 32, 32, 0xf0f0ffff },
1174 /* (f-op1 #)(f-r1 #)(f-op2 #)(f-r2 #)(h-accums-0 DI)(h-accums-1 DI)(h-accums-0 DI) */
1175 /*  76 */  { 16, 16, 0xffff },
1176 /* (f-op1 #)(f-r1 src1)(f-op2 #)(f-r2 src2)(h-accums-1 DI)(src1 SI)(src2 SI)(h-accums-1 DI) */
1177 /*  77 */  { 16, 16, 0xf0f0 },
1178 /* (f-op1 #)(f-r1 src1)(f-op2 #)(f-r2 src2)(src1 SI)(src2 SI)(h-accums-1 DI) */
1179 /*  78 */  { 16, 16, 0xf0f0 },
1180 /* (f-op1 #)(f-r1 #)(f-op2 #)(f-r2 #)(condbit UBI)(abort-parallel-execution UBI) */
1181 /*  79 */  { 16, 16, 0xffff },
1182 };
1183
1184 #define A(a) (1 << CGEN_CAT3 (CGEN_INSN,_,a))
1185 #define SYN(n) (& syntax_table[n])
1186 #define FMT(n) (& format_table[n])
1187
1188 /* The instruction table.  */
1189
1190 const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
1191 {
1192   /* null first entry, end of all hash chains */
1193   { { 0 }, 0 },
1194 /* add $dr,$sr */
1195   {
1196     { 1, 1, 1, 1 },
1197     "add", "add", SYN (0), FMT (0), 0xa0,
1198     & fmt_0_add_ops[0],
1199     { 2, 0|A(PARALLEL), { (1<<MACH_M32R), PIPE_OS } }
1200   },
1201 /* add3 $dr,$sr,#$slo16 */
1202   {
1203     { 1, 1, 1, 1 },
1204     "add3", "add3", SYN (1), FMT (1), 0x80a00000,
1205     & fmt_1_add3_ops[0],
1206     { 2, 0, { (1<<MACH_M32R), PIPE_NONE } }
1207   },
1208 /* add3 $dr,$sr,$slo16 */
1209   {
1210     { 1, 1, 1, 1 },
1211     "add3.a", "add3", SYN (2), FMT (1), 0x80a00000,
1212     & fmt_1_add3_ops[0],
1213     { 2, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE } }
1214   },
1215 /* and $dr,$sr */
1216   {
1217     { 1, 1, 1, 1 },
1218     "and", "and", SYN (0), FMT (0), 0xc0,
1219     & fmt_0_add_ops[0],
1220     { 2, 0|A(PARALLEL), { (1<<MACH_M32R), PIPE_OS } }
1221   },
1222 /* and3 $dr,$sr,#$uimm16 */
1223   {
1224     { 1, 1, 1, 1 },
1225     "and3", "and3", SYN (3), FMT (2), 0x80c00000,
1226     & fmt_2_and3_ops[0],
1227     { 2, 0, { (1<<MACH_M32R), PIPE_NONE } }
1228   },
1229 /* and3 $dr,$sr,$uimm16 */
1230   {
1231     { 1, 1, 1, 1 },
1232     "and3.a", "and3", SYN (4), FMT (2), 0x80c00000,
1233     & fmt_2_and3_ops[0],
1234     { 2, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE } }
1235   },
1236 /* or $dr,$sr */
1237   {
1238     { 1, 1, 1, 1 },
1239     "or", "or", SYN (0), FMT (0), 0xe0,
1240     & fmt_0_add_ops[0],
1241     { 2, 0|A(PARALLEL), { (1<<MACH_M32R), PIPE_OS } }
1242   },
1243 /* or3 $dr,$sr,#$ulo16 */
1244   {
1245     { 1, 1, 1, 1 },
1246     "or3", "or3", SYN (5), FMT (3), 0x80e00000,
1247     & fmt_3_or3_ops[0],
1248     { 2, 0, { (1<<MACH_M32R), PIPE_NONE } }
1249   },
1250 /* or3 $dr,$sr,$ulo16 */
1251   {
1252     { 1, 1, 1, 1 },
1253     "or3.a", "or3", SYN (6), FMT (3), 0x80e00000,
1254     & fmt_3_or3_ops[0],
1255     { 2, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE } }
1256   },
1257 /* xor $dr,$sr */
1258   {
1259     { 1, 1, 1, 1 },
1260     "xor", "xor", SYN (0), FMT (0), 0xd0,
1261     & fmt_0_add_ops[0],
1262     { 2, 0|A(PARALLEL), { (1<<MACH_M32R), PIPE_OS } }
1263   },
1264 /* xor3 $dr,$sr,#$uimm16 */
1265   {
1266     { 1, 1, 1, 1 },
1267     "xor3", "xor3", SYN (3), FMT (2), 0x80d00000,
1268     & fmt_2_and3_ops[0],
1269     { 2, 0, { (1<<MACH_M32R), PIPE_NONE } }
1270   },
1271 /* xor3 $dr,$sr,$uimm16 */
1272   {
1273     { 1, 1, 1, 1 },
1274     "xor3.a", "xor3", SYN (4), FMT (2), 0x80d00000,
1275     & fmt_2_and3_ops[0],
1276     { 2, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE } }
1277   },
1278 /* addi $dr,#$simm8 */
1279   {
1280     { 1, 1, 1, 1 },
1281     "addi", "addi", SYN (7), FMT (4), 0x4000,
1282     & fmt_4_addi_ops[0],
1283     { 2, 0, { (1<<MACH_M32R), PIPE_OS } }
1284   },
1285 /* addi $dr,$simm8 */
1286   {
1287     { 1, 1, 1, 1 },
1288     "addi.a", "addi", SYN (8), FMT (4), 0x4000,
1289     & fmt_4_addi_ops[0],
1290     { 2, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_OS } }
1291   },
1292 /* addv $dr,$sr */
1293   {
1294     { 1, 1, 1, 1 },
1295     "addv", "addv", SYN (0), FMT (5), 0x80,
1296     & fmt_5_addv_ops[0],
1297     { 2, 0, { (1<<MACH_M32R), PIPE_OS } }
1298   },
1299 /* addv3 $dr,$sr,#$simm16 */
1300   {
1301     { 1, 1, 1, 1 },
1302     "addv3", "addv3", SYN (9), FMT (6), 0x80800000,
1303     & fmt_6_addv3_ops[0],
1304     { 2, 0, { (1<<MACH_M32R), PIPE_NONE } }
1305   },
1306 /* addv3 $dr,$sr,$simm16 */
1307   {
1308     { 1, 1, 1, 1 },
1309     "addv3.a", "addv3", SYN (10), FMT (6), 0x80800000,
1310     & fmt_6_addv3_ops[0],
1311     { 2, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE } }
1312   },
1313 /* addx $dr,$sr */
1314   {
1315     { 1, 1, 1, 1 },
1316     "addx", "addx", SYN (0), FMT (7), 0x90,
1317     & fmt_7_addx_ops[0],
1318     { 2, 0, { (1<<MACH_M32R), PIPE_OS } }
1319   },
1320 /* bc $disp8 */
1321   {
1322     { 1, 1, 1, 1 },
1323     "bc8", "bc", SYN (11), FMT (8), 0x7c00,
1324     & fmt_8_bc8_ops[0],
1325     { 2, 0|A(RELAXABLE)|A(COND_CTI), { (1<<MACH_M32R), PIPE_O } }
1326   },
1327 /* bc.s $disp8 */
1328   {
1329     { 1, 1, 1, 1 },
1330     "bc8.s", "bc.s", SYN (11), FMT (9), 0x7c00,
1331     0,
1332     { 2, 0|A(ALIAS)|A(COND_CTI), { (1<<MACH_M32R), PIPE_O } }
1333   },
1334 /* bc $disp24 */
1335   {
1336     { 1, 1, 1, 1 },
1337     "bc24", "bc", SYN (12), FMT (10), 0xfc000000,
1338     & fmt_10_bc24_ops[0],
1339     { 2, 0|A(RELAX)|A(COND_CTI), { (1<<MACH_M32R), PIPE_NONE } }
1340   },
1341 /* bc.l $disp24 */
1342   {
1343     { 1, 1, 1, 1 },
1344     "bc24.l", "bc.l", SYN (12), FMT (11), 0xfc000000,
1345     0,
1346     { 2, 0|A(ALIAS)|A(COND_CTI), { (1<<MACH_M32R), PIPE_NONE } }
1347   },
1348 /* beq $src1,$src2,$disp16 */
1349   {
1350     { 1, 1, 1, 1 },
1351     "beq", "beq", SYN (13), FMT (12), 0xb0000000,
1352     & fmt_12_beq_ops[0],
1353     { 2, 0|A(COND_CTI), { (1<<MACH_M32R), PIPE_NONE } }
1354   },
1355 /* beqz $src2,$disp16 */
1356   {
1357     { 1, 1, 1, 1 },
1358     "beqz", "beqz", SYN (14), FMT (13), 0xb0800000,
1359     & fmt_13_beqz_ops[0],
1360     { 2, 0|A(COND_CTI), { (1<<MACH_M32R), PIPE_NONE } }
1361   },
1362 /* bgez $src2,$disp16 */
1363   {
1364     { 1, 1, 1, 1 },
1365     "bgez", "bgez", SYN (14), FMT (13), 0xb0b00000,
1366     & fmt_13_beqz_ops[0],
1367     { 2, 0|A(COND_CTI), { (1<<MACH_M32R), PIPE_NONE } }
1368   },
1369 /* bgtz $src2,$disp16 */
1370   {
1371     { 1, 1, 1, 1 },
1372     "bgtz", "bgtz", SYN (14), FMT (13), 0xb0d00000,
1373     & fmt_13_beqz_ops[0],
1374     { 2, 0|A(COND_CTI), { (1<<MACH_M32R), PIPE_NONE } }
1375   },
1376 /* blez $src2,$disp16 */
1377   {
1378     { 1, 1, 1, 1 },
1379     "blez", "blez", SYN (14), FMT (13), 0xb0c00000,
1380     & fmt_13_beqz_ops[0],
1381     { 2, 0|A(COND_CTI), { (1<<MACH_M32R), PIPE_NONE } }
1382   },
1383 /* bltz $src2,$disp16 */
1384   {
1385     { 1, 1, 1, 1 },
1386     "bltz", "bltz", SYN (14), FMT (13), 0xb0a00000,
1387     & fmt_13_beqz_ops[0],
1388     { 2, 0|A(COND_CTI), { (1<<MACH_M32R), PIPE_NONE } }
1389   },
1390 /* bnez $src2,$disp16 */
1391   {
1392     { 1, 1, 1, 1 },
1393     "bnez", "bnez", SYN (14), FMT (13), 0xb0900000,
1394     & fmt_13_beqz_ops[0],
1395     { 2, 0|A(COND_CTI), { (1<<MACH_M32R), PIPE_NONE } }
1396   },
1397 /* bl $disp8 */
1398   {
1399     { 1, 1, 1, 1 },
1400     "bl8", "bl", SYN (11), FMT (14), 0x7e00,
1401     & fmt_14_bl8_ops[0],
1402     { 2, 0|A(FILL_SLOT)|A(RELAXABLE)|A(UNCOND_CTI), { (1<<MACH_M32R), PIPE_O } }
1403   },
1404 /* bl.s $disp8 */
1405   {
1406     { 1, 1, 1, 1 },
1407     "bl8.s", "bl.s", SYN (11), FMT (9), 0x7e00,
1408     0,
1409     { 2, 0|A(FILL_SLOT)|A(ALIAS)|A(UNCOND_CTI), { (1<<MACH_M32R), PIPE_O } }
1410   },
1411 /* bl $disp24 */
1412   {
1413     { 1, 1, 1, 1 },
1414     "bl24", "bl", SYN (12), FMT (15), 0xfe000000,
1415     & fmt_15_bl24_ops[0],
1416     { 2, 0|A(RELAX)|A(UNCOND_CTI), { (1<<MACH_M32R), PIPE_NONE } }
1417   },
1418 /* bl.l $disp24 */
1419   {
1420     { 1, 1, 1, 1 },
1421     "bl24.l", "bl.l", SYN (12), FMT (11), 0xfe000000,
1422     0,
1423     { 2, 0|A(ALIAS)|A(UNCOND_CTI), { (1<<MACH_M32R), PIPE_NONE } }
1424   },
1425 /* start-sanitize-m32rx */
1426 /* bcl $disp8 */
1427   {
1428     { 1, 1, 1, 1 },
1429     "bcl8", "bcl", SYN (11), FMT (16), 0x7800,
1430     & fmt_16_bcl8_ops[0],
1431     { 2, 0|A(RELAXABLE)|A(COND_CTI), { (1<<MACH_M32RX), PIPE_O } }
1432   },
1433 /* end-sanitize-m32rx */
1434 /* start-sanitize-m32rx */
1435 /* bcl.s $disp8 */
1436   {
1437     { 1, 1, 1, 1 },
1438     "bcl8.s", "bcl.s", SYN (11), FMT (9), 0x7800,
1439     0,
1440     { 2, 0|A(ALIAS)|A(COND_CTI), { (1<<MACH_M32RX), PIPE_O } }
1441   },
1442 /* end-sanitize-m32rx */
1443 /* start-sanitize-m32rx */
1444 /* bcl $disp24 */
1445   {
1446     { 1, 1, 1, 1 },
1447     "bcl24", "bcl", SYN (12), FMT (17), 0xf8000000,
1448     & fmt_17_bcl24_ops[0],
1449     { 2, 0|A(RELAX)|A(COND_CTI), { (1<<MACH_M32RX), PIPE_NONE } }
1450   },
1451 /* end-sanitize-m32rx */
1452 /* start-sanitize-m32rx */
1453 /* bcl.l $disp24 */
1454   {
1455     { 1, 1, 1, 1 },
1456     "bcl24.l", "bcl.l", SYN (12), FMT (11), 0xf8000000,
1457     0,
1458     { 2, 0|A(ALIAS)|A(COND_CTI), { (1<<MACH_M32RX), PIPE_NONE } }
1459   },
1460 /* end-sanitize-m32rx */
1461 /* bnc $disp8 */
1462   {
1463     { 1, 1, 1, 1 },
1464     "bnc8", "bnc", SYN (11), FMT (8), 0x7d00,
1465     & fmt_8_bc8_ops[0],
1466     { 2, 0|A(RELAXABLE)|A(COND_CTI), { (1<<MACH_M32R), PIPE_O } }
1467   },
1468 /* bnc.s $disp8 */
1469   {
1470     { 1, 1, 1, 1 },
1471     "bnc8.s", "bnc.s", SYN (11), FMT (9), 0x7d00,
1472     0,
1473     { 2, 0|A(ALIAS)|A(COND_CTI), { (1<<MACH_M32R), PIPE_O } }
1474   },
1475 /* bnc $disp24 */
1476   {
1477     { 1, 1, 1, 1 },
1478     "bnc24", "bnc", SYN (12), FMT (10), 0xfd000000,
1479     & fmt_10_bc24_ops[0],
1480     { 2, 0|A(RELAX)|A(COND_CTI), { (1<<MACH_M32R), PIPE_NONE } }
1481   },
1482 /* bnc.l $disp24 */
1483   {
1484     { 1, 1, 1, 1 },
1485     "bnc24.l", "bnc.l", SYN (12), FMT (11), 0xfd000000,
1486     0,
1487     { 2, 0|A(ALIAS)|A(COND_CTI), { (1<<MACH_M32R), PIPE_NONE } }
1488   },
1489 /* bne $src1,$src2,$disp16 */
1490   {
1491     { 1, 1, 1, 1 },
1492     "bne", "bne", SYN (13), FMT (12), 0xb0100000,
1493     & fmt_12_beq_ops[0],
1494     { 2, 0|A(COND_CTI), { (1<<MACH_M32R), PIPE_NONE } }
1495   },
1496 /* bra $disp8 */
1497   {
1498     { 1, 1, 1, 1 },
1499     "bra8", "bra", SYN (11), FMT (18), 0x7f00,
1500     & fmt_18_bra8_ops[0],
1501     { 2, 0|A(FILL_SLOT)|A(RELAXABLE)|A(UNCOND_CTI), { (1<<MACH_M32R), PIPE_O } }
1502   },
1503 /* bra.s $disp8 */
1504   {
1505     { 1, 1, 1, 1 },
1506     "bra8.s", "bra.s", SYN (11), FMT (9), 0x7f00,
1507     0,
1508     { 2, 0|A(ALIAS)|A(UNCOND_CTI), { (1<<MACH_M32R), PIPE_O } }
1509   },
1510 /* bra $disp24 */
1511   {
1512     { 1, 1, 1, 1 },
1513     "bra24", "bra", SYN (12), FMT (19), 0xff000000,
1514     & fmt_19_bra24_ops[0],
1515     { 2, 0|A(RELAX)|A(UNCOND_CTI), { (1<<MACH_M32R), PIPE_NONE } }
1516   },
1517 /* bra.l $disp24 */
1518   {
1519     { 1, 1, 1, 1 },
1520     "bra24.l", "bra.l", SYN (12), FMT (11), 0xff000000,
1521     0,
1522     { 2, 0|A(ALIAS)|A(UNCOND_CTI), { (1<<MACH_M32R), PIPE_NONE } }
1523   },
1524 /* start-sanitize-m32rx */
1525 /* bncl $disp8 */
1526   {
1527     { 1, 1, 1, 1 },
1528     "bncl8", "bncl", SYN (11), FMT (16), 0x7900,
1529     & fmt_16_bcl8_ops[0],
1530     { 2, 0|A(RELAXABLE)|A(COND_CTI), { (1<<MACH_M32RX), PIPE_O } }
1531   },
1532 /* end-sanitize-m32rx */
1533 /* start-sanitize-m32rx */
1534 /* bncl.s $disp8 */
1535   {
1536     { 1, 1, 1, 1 },
1537     "bncl8.s", "bncl.s", SYN (11), FMT (9), 0x7900,
1538     0,
1539     { 2, 0|A(ALIAS)|A(COND_CTI), { (1<<MACH_M32RX), PIPE_O } }
1540   },
1541 /* end-sanitize-m32rx */
1542 /* start-sanitize-m32rx */
1543 /* bncl $disp24 */
1544   {
1545     { 1, 1, 1, 1 },
1546     "bncl24", "bncl", SYN (12), FMT (17), 0xf9000000,
1547     & fmt_17_bcl24_ops[0],
1548     { 2, 0|A(RELAX)|A(COND_CTI), { (1<<MACH_M32RX), PIPE_NONE } }
1549   },
1550 /* end-sanitize-m32rx */
1551 /* start-sanitize-m32rx */
1552 /* bncl.l $disp24 */
1553   {
1554     { 1, 1, 1, 1 },
1555     "bncl24.l", "bncl.l", SYN (12), FMT (11), 0xf9000000,
1556     0,
1557     { 2, 0|A(ALIAS)|A(COND_CTI), { (1<<MACH_M32RX), PIPE_NONE } }
1558   },
1559 /* end-sanitize-m32rx */
1560 /* cmp $src1,$src2 */
1561   {
1562     { 1, 1, 1, 1 },
1563     "cmp", "cmp", SYN (15), FMT (20), 0x40,
1564     & fmt_20_cmp_ops[0],
1565     { 2, 0, { (1<<MACH_M32R), PIPE_OS } }
1566   },
1567 /* cmpi $src2,#$simm16 */
1568   {
1569     { 1, 1, 1, 1 },
1570     "cmpi", "cmpi", SYN (16), FMT (21), 0x80400000,
1571     & fmt_21_cmpi_ops[0],
1572     { 2, 0, { (1<<MACH_M32R), PIPE_NONE } }
1573   },
1574 /* cmpi $src2,$simm16 */
1575   {
1576     { 1, 1, 1, 1 },
1577     "cmpi.a", "cmpi", SYN (17), FMT (21), 0x80400000,
1578     & fmt_21_cmpi_ops[0],
1579     { 2, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE } }
1580   },
1581 /* cmpu $src1,$src2 */
1582   {
1583     { 1, 1, 1, 1 },
1584     "cmpu", "cmpu", SYN (15), FMT (20), 0x50,
1585     & fmt_20_cmp_ops[0],
1586     { 2, 0, { (1<<MACH_M32R), PIPE_OS } }
1587   },
1588 /* cmpui $src2,#$uimm16 */
1589   {
1590     { 1, 1, 1, 1 },
1591     "cmpui", "cmpui", SYN (18), FMT (22), 0x80500000,
1592     & fmt_22_cmpui_ops[0],
1593     { 2, 0, { (1<<MACH_M32R), PIPE_NONE } }
1594   },
1595 /* cmpui $src2,$uimm16 */
1596   {
1597     { 1, 1, 1, 1 },
1598     "cmpui.a", "cmpui", SYN (19), FMT (22), 0x80500000,
1599     & fmt_22_cmpui_ops[0],
1600     { 2, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE } }
1601   },
1602 /* start-sanitize-m32rx */
1603 /* cmpeq $src1,$src2 */
1604   {
1605     { 1, 1, 1, 1 },
1606     "cmpeq", "cmpeq", SYN (15), FMT (20), 0x60,
1607     & fmt_20_cmp_ops[0],
1608     { 2, 0, { (1<<MACH_M32RX), PIPE_OS } }
1609   },
1610 /* end-sanitize-m32rx */
1611 /* start-sanitize-m32rx */
1612 /* cmpz $src2 */
1613   {
1614     { 1, 1, 1, 1 },
1615     "cmpz", "cmpz", SYN (20), FMT (23), 0x70,
1616     & fmt_23_cmpz_ops[0],
1617     { 2, 0, { (1<<MACH_M32RX), PIPE_OS } }
1618   },
1619 /* end-sanitize-m32rx */
1620 /* div $dr,$sr */
1621   {
1622     { 1, 1, 1, 1 },
1623     "div", "div", SYN (0), FMT (24), 0x90000000,
1624     & fmt_24_div_ops[0],
1625     { 2, 0, { (1<<MACH_M32R), PIPE_NONE } }
1626   },
1627 /* divu $dr,$sr */
1628   {
1629     { 1, 1, 1, 1 },
1630     "divu", "divu", SYN (0), FMT (24), 0x90100000,
1631     & fmt_24_div_ops[0],
1632     { 2, 0, { (1<<MACH_M32R), PIPE_NONE } }
1633   },
1634 /* rem $dr,$sr */
1635   {
1636     { 1, 1, 1, 1 },
1637     "rem", "rem", SYN (0), FMT (24), 0x90200000,
1638     & fmt_24_div_ops[0],
1639     { 2, 0, { (1<<MACH_M32R), PIPE_NONE } }
1640   },
1641 /* remu $dr,$sr */
1642   {
1643     { 1, 1, 1, 1 },
1644     "remu", "remu", SYN (0), FMT (24), 0x90300000,
1645     & fmt_24_div_ops[0],
1646     { 2, 0, { (1<<MACH_M32R), PIPE_NONE } }
1647   },
1648 /* start-sanitize-m32rx */
1649 /* divh $dr,$sr */
1650   {
1651     { 1, 1, 1, 1 },
1652     "divh", "divh", SYN (0), FMT (24), 0x90000010,
1653     & fmt_24_div_ops[0],
1654     { 2, 0, { (1<<MACH_M32R), PIPE_NONE } }
1655   },
1656 /* end-sanitize-m32rx */
1657 /* start-sanitize-m32rx */
1658 /* jc $sr */
1659   {
1660     { 1, 1, 1, 1 },
1661     "jc", "jc", SYN (21), FMT (25), 0x1cc0,
1662     & fmt_25_jc_ops[0],
1663     { 2, 0|A(COND_CTI), { (1<<MACH_M32RX), PIPE_O } }
1664   },
1665 /* end-sanitize-m32rx */
1666 /* start-sanitize-m32rx */
1667 /* jnc $sr */
1668   {
1669     { 1, 1, 1, 1 },
1670     "jnc", "jnc", SYN (21), FMT (25), 0x1dc0,
1671     & fmt_25_jc_ops[0],
1672     { 2, 0|A(COND_CTI), { (1<<MACH_M32RX), PIPE_O } }
1673   },
1674 /* end-sanitize-m32rx */
1675 /* jl $sr */
1676   {
1677     { 1, 1, 1, 1 },
1678     "jl", "jl", SYN (21), FMT (26), 0x1ec0,
1679     & fmt_26_jl_ops[0],
1680     { 2, 0|A(FILL_SLOT)|A(UNCOND_CTI), { (1<<MACH_M32R), PIPE_O } }
1681   },
1682 /* jmp $sr */
1683   {
1684     { 1, 1, 1, 1 },
1685     "jmp", "jmp", SYN (21), FMT (27), 0x1fc0,
1686     & fmt_27_jmp_ops[0],
1687     { 2, 0|A(UNCOND_CTI), { (1<<MACH_M32R), PIPE_O } }
1688   },
1689 /* ld $dr,@$sr */
1690   {
1691     { 1, 1, 1, 1 },
1692     "ld", "ld", SYN (22), FMT (28), 0x20c0,
1693     & fmt_28_ld_ops[0],
1694     { 2, 0, { (1<<MACH_M32R), PIPE_O } }
1695   },
1696 /* ld $dr,@($sr) */
1697   {
1698     { 1, 1, 1, 1 },
1699     "ld-2", "ld", SYN (23), FMT (29), 0x20c0,
1700     0,
1701     { 2, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_O } }
1702   },
1703 /* ld $dr,@($slo16,$sr) */
1704   {
1705     { 1, 1, 1, 1 },
1706     "ld-d", "ld", SYN (24), FMT (30), 0xa0c00000,
1707     & fmt_30_ld_d_ops[0],
1708     { 2, 0, { (1<<MACH_M32R), PIPE_NONE } }
1709   },
1710 /* ld $dr,@($sr,$slo16) */
1711   {
1712     { 1, 1, 1, 1 },
1713     "ld-d2", "ld", SYN (25), FMT (31), 0xa0c00000,
1714     0,
1715     { 2, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE } }
1716   },
1717 /* ldb $dr,@$sr */
1718   {
1719     { 1, 1, 1, 1 },
1720     "ldb", "ldb", SYN (22), FMT (32), 0x2080,
1721     & fmt_32_ldb_ops[0],
1722     { 2, 0, { (1<<MACH_M32R), PIPE_O } }
1723   },
1724 /* ldb $dr,@($sr) */
1725   {
1726     { 1, 1, 1, 1 },
1727     "ldb-2", "ldb", SYN (23), FMT (29), 0x2080,
1728     0,
1729     { 2, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_O } }
1730   },
1731 /* ldb $dr,@($slo16,$sr) */
1732   {
1733     { 1, 1, 1, 1 },
1734     "ldb-d", "ldb", SYN (24), FMT (33), 0xa0800000,
1735     & fmt_33_ldb_d_ops[0],
1736     { 2, 0, { (1<<MACH_M32R), PIPE_NONE } }
1737   },
1738 /* ldb $dr,@($sr,$slo16) */
1739   {
1740     { 1, 1, 1, 1 },
1741     "ldb-d2", "ldb", SYN (25), FMT (31), 0xa0800000,
1742     0,
1743     { 2, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE } }
1744   },
1745 /* ldh $dr,@$sr */
1746   {
1747     { 1, 1, 1, 1 },
1748     "ldh", "ldh", SYN (22), FMT (34), 0x20a0,
1749     & fmt_34_ldh_ops[0],
1750     { 2, 0, { (1<<MACH_M32R), PIPE_O } }
1751   },
1752 /* ldh $dr,@($sr) */
1753   {
1754     { 1, 1, 1, 1 },
1755     "ldh-2", "ldh", SYN (23), FMT (29), 0x20a0,
1756     0,
1757     { 2, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_O } }
1758   },
1759 /* ldh $dr,@($slo16,$sr) */
1760   {
1761     { 1, 1, 1, 1 },
1762     "ldh-d", "ldh", SYN (24), FMT (35), 0xa0a00000,
1763     & fmt_35_ldh_d_ops[0],
1764     { 2, 0, { (1<<MACH_M32R), PIPE_NONE } }
1765   },
1766 /* ldh $dr,@($sr,$slo16) */
1767   {
1768     { 1, 1, 1, 1 },
1769     "ldh-d2", "ldh", SYN (25), FMT (31), 0xa0a00000,
1770     0,
1771     { 2, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE } }
1772   },
1773 /* ldub $dr,@$sr */
1774   {
1775     { 1, 1, 1, 1 },
1776     "ldub", "ldub", SYN (22), FMT (32), 0x2090,
1777     & fmt_32_ldb_ops[0],
1778     { 2, 0, { (1<<MACH_M32R), PIPE_O } }
1779   },
1780 /* ldub $dr,@($sr) */
1781   {
1782     { 1, 1, 1, 1 },
1783     "ldub-2", "ldub", SYN (23), FMT (29), 0x2090,
1784     0,
1785     { 2, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_O } }
1786   },
1787 /* ldub $dr,@($slo16,$sr) */
1788   {
1789     { 1, 1, 1, 1 },
1790     "ldub-d", "ldub", SYN (24), FMT (33), 0xa0900000,
1791     & fmt_33_ldb_d_ops[0],
1792     { 2, 0, { (1<<MACH_M32R), PIPE_NONE } }
1793   },
1794 /* ldub $dr,@($sr,$slo16) */
1795   {
1796     { 1, 1, 1, 1 },
1797     "ldub-d2", "ldub", SYN (25), FMT (31), 0xa0900000,
1798     0,
1799     { 2, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE } }
1800   },
1801 /* lduh $dr,@$sr */
1802   {
1803     { 1, 1, 1, 1 },
1804     "lduh", "lduh", SYN (22), FMT (34), 0x20b0,
1805     & fmt_34_ldh_ops[0],
1806     { 2, 0, { (1<<MACH_M32R), PIPE_O } }
1807   },
1808 /* lduh $dr,@($sr) */
1809   {
1810     { 1, 1, 1, 1 },
1811     "lduh-2", "lduh", SYN (23), FMT (29), 0x20b0,
1812     0,
1813     { 2, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_O } }
1814   },
1815 /* lduh $dr,@($slo16,$sr) */
1816   {
1817     { 1, 1, 1, 1 },
1818     "lduh-d", "lduh", SYN (24), FMT (35), 0xa0b00000,
1819     & fmt_35_ldh_d_ops[0],
1820     { 2, 0, { (1<<MACH_M32R), PIPE_NONE } }
1821   },
1822 /* lduh $dr,@($sr,$slo16) */
1823   {
1824     { 1, 1, 1, 1 },
1825     "lduh-d2", "lduh", SYN (25), FMT (31), 0xa0b00000,
1826     0,
1827     { 2, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE } }
1828   },
1829 /* ld $dr,@$sr+ */
1830   {
1831     { 1, 1, 1, 1 },
1832     "ld-plus", "ld", SYN (26), FMT (36), 0x20e0,
1833     & fmt_36_ld_plus_ops[0],
1834     { 2, 0, { (1<<MACH_M32R), PIPE_O } }
1835   },
1836 /* ld24 $dr,#$uimm24 */
1837   {
1838     { 1, 1, 1, 1 },
1839     "ld24", "ld24", SYN (27), FMT (37), 0xe0000000,
1840     & fmt_37_ld24_ops[0],
1841     { 2, 0, { (1<<MACH_M32R), PIPE_NONE } }
1842   },
1843 /* ld24 $dr,$uimm24 */
1844   {
1845     { 1, 1, 1, 1 },
1846     "ld24.a", "ld24", SYN (28), FMT (37), 0xe0000000,
1847     & fmt_37_ld24_ops[0],
1848     { 2, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE } }
1849   },
1850 /* ldi $dr,#$simm8 */
1851   {
1852     { 1, 1, 1, 1 },
1853     "ldi8", "ldi", SYN (7), FMT (38), 0x6000,
1854     & fmt_38_ldi8_ops[0],
1855     { 2, 0, { (1<<MACH_M32R), PIPE_OS } }
1856   },
1857 /* ldi $dr,$simm8 */
1858   {
1859     { 1, 1, 1, 1 },
1860     "ldi8.a", "ldi", SYN (8), FMT (38), 0x6000,
1861     & fmt_38_ldi8_ops[0],
1862     { 2, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_OS } }
1863   },
1864 /* ldi8 $dr,#$simm8 */
1865   {
1866     { 1, 1, 1, 1 },
1867     "ldi8a", "ldi8", SYN (7), FMT (38), 0x6000,
1868     & fmt_38_ldi8_ops[0],
1869     { 2, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_OS } }
1870   },
1871 /* ldi8 $dr,$simm8 */
1872   {
1873     { 1, 1, 1, 1 },
1874     "ldi8a.a", "ldi8", SYN (8), FMT (38), 0x6000,
1875     & fmt_38_ldi8_ops[0],
1876     { 2, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_OS } }
1877   },
1878 /* ldi $dr,$slo16 */
1879   {
1880     { 1, 1, 1, 1 },
1881     "ldi16", "ldi", SYN (29), FMT (39), 0x90f00000,
1882     & fmt_39_ldi16_ops[0],
1883     { 2, 0, { (1<<MACH_M32R), PIPE_NONE } }
1884   },
1885 /* ldi16 $dr,$slo16 */
1886   {
1887     { 1, 1, 1, 1 },
1888     "ldi16a", "ldi16", SYN (29), FMT (39), 0x90f00000,
1889     & fmt_39_ldi16_ops[0],
1890     { 2, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE } }
1891   },
1892 /* lock $dr,@$sr */
1893   {
1894     { 1, 1, 1, 1 },
1895     "lock", "lock", SYN (22), FMT (40), 0x20d0,
1896     & fmt_40_lock_ops[0],
1897     { 2, 0, { (1<<MACH_M32R), PIPE_O } }
1898   },
1899 /* machi $src1,$src2 */
1900   {
1901     { 1, 1, 1, 1 },
1902     "machi", "machi", SYN (15), FMT (41), 0x3040,
1903     & fmt_41_machi_ops[0],
1904     { 2, 0, { (1<<MACH_M32R), PIPE_S } }
1905   },
1906 /* start-sanitize-m32rx */
1907 /* machi $src1,$src2,$acc */
1908   {
1909     { 1, 1, 1, 1 },
1910     "machi-a", "machi", SYN (30), FMT (42), 0x3040,
1911     & fmt_42_machi_a_ops[0],
1912     { 2, 0, { (1<<MACH_M32RX), PIPE_S } }
1913   },
1914 /* end-sanitize-m32rx */
1915 /* maclo $src1,$src2 */
1916   {
1917     { 1, 1, 1, 1 },
1918     "maclo", "maclo", SYN (15), FMT (41), 0x3050,
1919     & fmt_41_machi_ops[0],
1920     { 2, 0, { (1<<MACH_M32R), PIPE_S } }
1921   },
1922 /* start-sanitize-m32rx */
1923 /* maclo $src1,$src2,$acc */
1924   {
1925     { 1, 1, 1, 1 },
1926     "maclo-a", "maclo", SYN (30), FMT (42), 0x3050,
1927     & fmt_42_machi_a_ops[0],
1928     { 2, 0, { (1<<MACH_M32RX), PIPE_S } }
1929   },
1930 /* end-sanitize-m32rx */
1931 /* macwhi $src1,$src2 */
1932   {
1933     { 1, 1, 1, 1 },
1934     "macwhi", "macwhi", SYN (15), FMT (41), 0x3060,
1935     & fmt_41_machi_ops[0],
1936     { 2, 0, { (1<<MACH_M32R), PIPE_S } }
1937   },
1938 /* macwlo $src1,$src2 */
1939   {
1940     { 1, 1, 1, 1 },
1941     "macwlo", "macwlo", SYN (15), FMT (41), 0x3070,
1942     & fmt_41_machi_ops[0],
1943     { 2, 0, { (1<<MACH_M32R), PIPE_S } }
1944   },
1945 /* mul $dr,$sr */
1946   {
1947     { 1, 1, 1, 1 },
1948     "mul", "mul", SYN (0), FMT (0), 0x1060,
1949     & fmt_0_add_ops[0],
1950     { 2, 0, { (1<<MACH_M32R), PIPE_S } }
1951   },
1952 /* mulhi $src1,$src2 */
1953   {
1954     { 1, 1, 1, 1 },
1955     "mulhi", "mulhi", SYN (15), FMT (43), 0x3000,
1956     & fmt_43_mulhi_ops[0],
1957     { 2, 0, { (1<<MACH_M32R), PIPE_S } }
1958   },
1959 /* start-sanitize-m32rx */
1960 /* mulhi $src1,$src2,$acc */
1961   {
1962     { 1, 1, 1, 1 },
1963     "mulhi-a", "mulhi", SYN (30), FMT (44), 0x3000,
1964     & fmt_44_mulhi_a_ops[0],
1965     { 2, 0, { (1<<MACH_M32RX), PIPE_S } }
1966   },
1967 /* end-sanitize-m32rx */
1968 /* mullo $src1,$src2 */
1969   {
1970     { 1, 1, 1, 1 },
1971     "mullo", "mullo", SYN (15), FMT (43), 0x3010,
1972     & fmt_43_mulhi_ops[0],
1973     { 2, 0, { (1<<MACH_M32R), PIPE_S } }
1974   },
1975 /* start-sanitize-m32rx */
1976 /* mullo $src1,$src2,$acc */
1977   {
1978     { 1, 1, 1, 1 },
1979     "mullo-a", "mullo", SYN (30), FMT (44), 0x3010,
1980     & fmt_44_mulhi_a_ops[0],
1981     { 2, 0, { (1<<MACH_M32RX), PIPE_S } }
1982   },
1983 /* end-sanitize-m32rx */
1984 /* mulwhi $src1,$src2 */
1985   {
1986     { 1, 1, 1, 1 },
1987     "mulwhi", "mulwhi", SYN (15), FMT (43), 0x3020,
1988     & fmt_43_mulhi_ops[0],
1989     { 2, 0, { (1<<MACH_M32R), PIPE_S } }
1990   },
1991 /* mulwlo $src1,$src2 */
1992   {
1993     { 1, 1, 1, 1 },
1994     "mulwlo", "mulwlo", SYN (15), FMT (43), 0x3030,
1995     & fmt_43_mulhi_ops[0],
1996     { 2, 0, { (1<<MACH_M32R), PIPE_S } }
1997   },
1998 /* mv $dr,$sr */
1999   {
2000     { 1, 1, 1, 1 },
2001     "mv", "mv", SYN (0), FMT (45), 0x1080,
2002     & fmt_45_mv_ops[0],
2003     { 2, 0, { (1<<MACH_M32R), PIPE_OS } }
2004   },
2005 /* mvfachi $dr */
2006   {
2007     { 1, 1, 1, 1 },
2008     "mvfachi", "mvfachi", SYN (31), FMT (46), 0x50f0,
2009     & fmt_46_mvfachi_ops[0],
2010     { 2, 0, { (1<<MACH_M32R), PIPE_S } }
2011   },
2012 /* start-sanitize-m32rx */
2013 /* mvfachi $dr,$accs */
2014   {
2015     { 1, 1, 1, 1 },
2016     "mvfachi-a", "mvfachi", SYN (32), FMT (47), 0x50f0,
2017     & fmt_47_mvfachi_a_ops[0],
2018     { 2, 0, { (1<<MACH_M32RX), PIPE_S } }
2019   },
2020 /* end-sanitize-m32rx */
2021 /* mvfaclo $dr */
2022   {
2023     { 1, 1, 1, 1 },
2024     "mvfaclo", "mvfaclo", SYN (31), FMT (46), 0x50f1,
2025     & fmt_46_mvfachi_ops[0],
2026     { 2, 0, { (1<<MACH_M32R), PIPE_S } }
2027   },
2028 /* start-sanitize-m32rx */
2029 /* mvfaclo $dr,$accs */
2030   {
2031     { 1, 1, 1, 1 },
2032     "mvfaclo-a", "mvfaclo", SYN (32), FMT (47), 0x50f1,
2033     & fmt_47_mvfachi_a_ops[0],
2034     { 2, 0, { (1<<MACH_M32RX), PIPE_S } }
2035   },
2036 /* end-sanitize-m32rx */
2037 /* mvfacmi $dr */
2038   {
2039     { 1, 1, 1, 1 },
2040     "mvfacmi", "mvfacmi", SYN (31), FMT (46), 0x50f2,
2041     & fmt_46_mvfachi_ops[0],
2042     { 2, 0, { (1<<MACH_M32R), PIPE_S } }
2043   },
2044 /* start-sanitize-m32rx */
2045 /* mvfacmi $dr,$accs */
2046   {
2047     { 1, 1, 1, 1 },
2048     "mvfacmi-a", "mvfacmi", SYN (32), FMT (47), 0x50f2,
2049     & fmt_47_mvfachi_a_ops[0],
2050     { 2, 0, { (1<<MACH_M32RX), PIPE_S } }
2051   },
2052 /* end-sanitize-m32rx */
2053 /* mvfc $dr,$scr */
2054   {
2055     { 1, 1, 1, 1 },
2056     "mvfc", "mvfc", SYN (33), FMT (48), 0x1090,
2057     & fmt_48_mvfc_ops[0],
2058     { 2, 0, { (1<<MACH_M32R), PIPE_O } }
2059   },
2060 /* mvtachi $src1 */
2061   {
2062     { 1, 1, 1, 1 },
2063     "mvtachi", "mvtachi", SYN (34), FMT (49), 0x5070,
2064     & fmt_49_mvtachi_ops[0],
2065     { 2, 0, { (1<<MACH_M32R), PIPE_S } }
2066   },
2067 /* start-sanitize-m32rx */
2068 /* mvtachi $src1,$accs */
2069   {
2070     { 1, 1, 1, 1 },
2071     "mvtachi-a", "mvtachi", SYN (35), FMT (50), 0x5070,
2072     & fmt_50_mvtachi_a_ops[0],
2073     { 2, 0, { (1<<MACH_M32RX), PIPE_S } }
2074   },
2075 /* end-sanitize-m32rx */
2076 /* mvtaclo $src1 */
2077   {
2078     { 1, 1, 1, 1 },
2079     "mvtaclo", "mvtaclo", SYN (34), FMT (49), 0x5071,
2080     & fmt_49_mvtachi_ops[0],
2081     { 2, 0, { (1<<MACH_M32R), PIPE_S } }
2082   },
2083 /* start-sanitize-m32rx */
2084 /* mvtaclo $src1,$accs */
2085   {
2086     { 1, 1, 1, 1 },
2087     "mvtaclo-a", "mvtaclo", SYN (35), FMT (50), 0x5071,
2088     & fmt_50_mvtachi_a_ops[0],
2089     { 2, 0, { (1<<MACH_M32RX), PIPE_S } }
2090   },
2091 /* end-sanitize-m32rx */
2092 /* mvtc $sr,$dcr */
2093   {
2094     { 1, 1, 1, 1 },
2095     "mvtc", "mvtc", SYN (36), FMT (51), 0x10a0,
2096     & fmt_51_mvtc_ops[0],
2097     { 2, 0, { (1<<MACH_M32R), PIPE_O } }
2098   },
2099 /* neg $dr,$sr */
2100   {
2101     { 1, 1, 1, 1 },
2102     "neg", "neg", SYN (0), FMT (45), 0x30,
2103     & fmt_45_mv_ops[0],
2104     { 2, 0, { (1<<MACH_M32R), PIPE_OS } }
2105   },
2106 /* nop */
2107   {
2108     { 1, 1, 1, 1 },
2109     "nop", "nop", SYN (37), FMT (52), 0x7000,
2110     0,
2111     { 2, 0, { (1<<MACH_M32R), PIPE_OS } }
2112   },
2113 /* not $dr,$sr */
2114   {
2115     { 1, 1, 1, 1 },
2116     "not", "not", SYN (0), FMT (45), 0xb0,
2117     & fmt_45_mv_ops[0],
2118     { 2, 0, { (1<<MACH_M32R), PIPE_OS } }
2119   },
2120 /* rac */
2121   {
2122     { 1, 1, 1, 1 },
2123     "rac", "rac", SYN (37), FMT (53), 0x5090,
2124     & fmt_53_rac_ops[0],
2125     { 2, 0, { (1<<MACH_M32R), PIPE_S } }
2126   },
2127 /* start-sanitize-m32rx */
2128 /* rac $accd */
2129   {
2130     { 1, 1, 1, 1 },
2131     "rac-d", "rac", SYN (38), FMT (54), 0x5090,
2132     & fmt_54_rac_d_ops[0],
2133     { 2, 0, { (1<<MACH_M32RX), PIPE_S } }
2134   },
2135 /* end-sanitize-m32rx */
2136 /* start-sanitize-m32rx */
2137 /* rac $accd,$accs */
2138   {
2139     { 1, 1, 1, 1 },
2140     "rac-ds", "rac", SYN (39), FMT (55), 0x5090,
2141     & fmt_55_rac_ds_ops[0],
2142     { 2, 0, { (1<<MACH_M32RX), PIPE_S } }
2143   },
2144 /* end-sanitize-m32rx */
2145 /* start-sanitize-m32rx */
2146 /* rac $accd,$accs,#$imm1 */
2147   {
2148     { 1, 1, 1, 1 },
2149     "rac-dsi", "rac", SYN (40), FMT (56), 0x5090,
2150     & fmt_56_rac_dsi_ops[0],
2151     { 2, 0, { (1<<MACH_M32RX), PIPE_S } }
2152   },
2153 /* end-sanitize-m32rx */
2154 /* rach */
2155   {
2156     { 1, 1, 1, 1 },
2157     "rach", "rach", SYN (37), FMT (53), 0x5080,
2158     & fmt_53_rac_ops[0],
2159     { 2, 0, { (1<<MACH_M32R), PIPE_S } }
2160   },
2161 /* start-sanitize-m32rx */
2162 /* rach $accd */
2163   {
2164     { 1, 1, 1, 1 },
2165     "rach-d", "rach", SYN (38), FMT (54), 0x5080,
2166     & fmt_54_rac_d_ops[0],
2167     { 2, 0, { (1<<MACH_M32RX), PIPE_S } }
2168   },
2169 /* end-sanitize-m32rx */
2170 /* start-sanitize-m32rx */
2171 /* rach $accd,$accs */
2172   {
2173     { 1, 1, 1, 1 },
2174     "rach-ds", "rach", SYN (39), FMT (55), 0x5080,
2175     & fmt_55_rac_ds_ops[0],
2176     { 2, 0, { (1<<MACH_M32RX), PIPE_S } }
2177   },
2178 /* end-sanitize-m32rx */
2179 /* start-sanitize-m32rx */
2180 /* rach $accd,$accs,#$imm1 */
2181   {
2182     { 1, 1, 1, 1 },
2183     "rach-dsi", "rach", SYN (40), FMT (56), 0x5080,
2184     & fmt_56_rac_dsi_ops[0],
2185     { 2, 0, { (1<<MACH_M32RX), PIPE_S } }
2186   },
2187 /* end-sanitize-m32rx */
2188 /* rte */
2189   {
2190     { 1, 1, 1, 1 },
2191     "rte", "rte", SYN (37), FMT (57), 0x10d6,
2192     & fmt_57_rte_ops[0],
2193     { 2, 0|A(UNCOND_CTI), { (1<<MACH_M32R), PIPE_O } }
2194   },
2195 /* seth $dr,#$hi16 */
2196   {
2197     { 1, 1, 1, 1 },
2198     "seth", "seth", SYN (41), FMT (58), 0xd0c00000,
2199     & fmt_58_seth_ops[0],
2200     { 2, 0, { (1<<MACH_M32R), PIPE_NONE } }
2201   },
2202 /* seth $dr,$hi16 */
2203   {
2204     { 1, 1, 1, 1 },
2205     "seth.a", "seth", SYN (42), FMT (58), 0xd0c00000,
2206     & fmt_58_seth_ops[0],
2207     { 2, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE } }
2208   },
2209 /* sll $dr,$sr */
2210   {
2211     { 1, 1, 1, 1 },
2212     "sll", "sll", SYN (0), FMT (0), 0x1040,
2213     & fmt_0_add_ops[0],
2214     { 2, 0, { (1<<MACH_M32R), PIPE_O } }
2215   },
2216 /* sll3 $dr,$sr,#$simm16 */
2217   {
2218     { 1, 1, 1, 1 },
2219     "sll3", "sll3", SYN (9), FMT (59), 0x90c00000,
2220     & fmt_59_sll3_ops[0],
2221     { 2, 0, { (1<<MACH_M32R), PIPE_NONE } }
2222   },
2223 /* sll3 $dr,$sr,$simm16 */
2224   {
2225     { 1, 1, 1, 1 },
2226     "sll3.a", "sll3", SYN (10), FMT (59), 0x90c00000,
2227     & fmt_59_sll3_ops[0],
2228     { 2, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE } }
2229   },
2230 /* slli $dr,#$uimm5 */
2231   {
2232     { 1, 1, 1, 1 },
2233     "slli", "slli", SYN (43), FMT (60), 0x5040,
2234     & fmt_60_slli_ops[0],
2235     { 2, 0, { (1<<MACH_M32R), PIPE_O } }
2236   },
2237 /* slli $dr,$uimm5 */
2238   {
2239     { 1, 1, 1, 1 },
2240     "slli.a", "slli", SYN (44), FMT (60), 0x5040,
2241     & fmt_60_slli_ops[0],
2242     { 2, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_O } }
2243   },
2244 /* sra $dr,$sr */
2245   {
2246     { 1, 1, 1, 1 },
2247     "sra", "sra", SYN (0), FMT (0), 0x1020,
2248     & fmt_0_add_ops[0],
2249     { 2, 0, { (1<<MACH_M32R), PIPE_O } }
2250   },
2251 /* sra3 $dr,$sr,#$simm16 */
2252   {
2253     { 1, 1, 1, 1 },
2254     "sra3", "sra3", SYN (9), FMT (59), 0x90a00000,
2255     & fmt_59_sll3_ops[0],
2256     { 2, 0, { (1<<MACH_M32R), PIPE_NONE } }
2257   },
2258 /* sra3 $dr,$sr,$simm16 */
2259   {
2260     { 1, 1, 1, 1 },
2261     "sra3.a", "sra3", SYN (10), FMT (59), 0x90a00000,
2262     & fmt_59_sll3_ops[0],
2263     { 2, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE } }
2264   },
2265 /* srai $dr,#$uimm5 */
2266   {
2267     { 1, 1, 1, 1 },
2268     "srai", "srai", SYN (43), FMT (60), 0x5020,
2269     & fmt_60_slli_ops[0],
2270     { 2, 0, { (1<<MACH_M32R), PIPE_O } }
2271   },
2272 /* srai $dr,$uimm5 */
2273   {
2274     { 1, 1, 1, 1 },
2275     "srai.a", "srai", SYN (44), FMT (60), 0x5020,
2276     & fmt_60_slli_ops[0],
2277     { 2, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_O } }
2278   },
2279 /* srl $dr,$sr */
2280   {
2281     { 1, 1, 1, 1 },
2282     "srl", "srl", SYN (0), FMT (0), 0x1000,
2283     & fmt_0_add_ops[0],
2284     { 2, 0, { (1<<MACH_M32R), PIPE_O } }
2285   },
2286 /* srl3 $dr,$sr,#$simm16 */
2287   {
2288     { 1, 1, 1, 1 },
2289     "srl3", "srl3", SYN (9), FMT (59), 0x90800000,
2290     & fmt_59_sll3_ops[0],
2291     { 2, 0, { (1<<MACH_M32R), PIPE_NONE } }
2292   },
2293 /* srl3 $dr,$sr,$simm16 */
2294   {
2295     { 1, 1, 1, 1 },
2296     "srl3.a", "srl3", SYN (10), FMT (59), 0x90800000,
2297     & fmt_59_sll3_ops[0],
2298     { 2, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE } }
2299   },
2300 /* srli $dr,#$uimm5 */
2301   {
2302     { 1, 1, 1, 1 },
2303     "srli", "srli", SYN (43), FMT (60), 0x5000,
2304     & fmt_60_slli_ops[0],
2305     { 2, 0, { (1<<MACH_M32R), PIPE_O } }
2306   },
2307 /* srli $dr,$uimm5 */
2308   {
2309     { 1, 1, 1, 1 },
2310     "srli.a", "srli", SYN (44), FMT (60), 0x5000,
2311     & fmt_60_slli_ops[0],
2312     { 2, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_O } }
2313   },
2314 /* st $src1,@$src2 */
2315   {
2316     { 1, 1, 1, 1 },
2317     "st", "st", SYN (45), FMT (61), 0x2040,
2318     & fmt_61_st_ops[0],
2319     { 2, 0, { (1<<MACH_M32R), PIPE_O } }
2320   },
2321 /* st $src1,@($src2) */
2322   {
2323     { 1, 1, 1, 1 },
2324     "st-2", "st", SYN (46), FMT (62), 0x2040,
2325     0,
2326     { 2, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_O } }
2327   },
2328 /* st $src1,@($slo16,$src2) */
2329   {
2330     { 1, 1, 1, 1 },
2331     "st-d", "st", SYN (47), FMT (63), 0xa0400000,
2332     & fmt_63_st_d_ops[0],
2333     { 2, 0, { (1<<MACH_M32R), PIPE_NONE } }
2334   },
2335 /* st $src1,@($src2,$slo16) */
2336   {
2337     { 1, 1, 1, 1 },
2338     "st-d2", "st", SYN (48), FMT (64), 0xa0400000,
2339     0,
2340     { 2, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE } }
2341   },
2342 /* stb $src1,@$src2 */
2343   {
2344     { 1, 1, 1, 1 },
2345     "stb", "stb", SYN (45), FMT (65), 0x2000,
2346     & fmt_65_stb_ops[0],
2347     { 2, 0, { (1<<MACH_M32R), PIPE_O } }
2348   },
2349 /* stb $src1,@($src2) */
2350   {
2351     { 1, 1, 1, 1 },
2352     "stb-2", "stb", SYN (46), FMT (62), 0x2000,
2353     0,
2354     { 2, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_O } }
2355   },
2356 /* stb $src1,@($slo16,$src2) */
2357   {
2358     { 1, 1, 1, 1 },
2359     "stb-d", "stb", SYN (47), FMT (66), 0xa0000000,
2360     & fmt_66_stb_d_ops[0],
2361     { 2, 0, { (1<<MACH_M32R), PIPE_NONE } }
2362   },
2363 /* stb $src1,@($src2,$slo16) */
2364   {
2365     { 1, 1, 1, 1 },
2366     "stb-d2", "stb", SYN (48), FMT (64), 0xa0000000,
2367     0,
2368     { 2, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE } }
2369   },
2370 /* sth $src1,@$src2 */
2371   {
2372     { 1, 1, 1, 1 },
2373     "sth", "sth", SYN (45), FMT (67), 0x2020,
2374     & fmt_67_sth_ops[0],
2375     { 2, 0, { (1<<MACH_M32R), PIPE_O } }
2376   },
2377 /* sth $src1,@($src2) */
2378   {
2379     { 1, 1, 1, 1 },
2380     "sth-2", "sth", SYN (46), FMT (62), 0x2020,
2381     0,
2382     { 2, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_O } }
2383   },
2384 /* sth $src1,@($slo16,$src2) */
2385   {
2386     { 1, 1, 1, 1 },
2387     "sth-d", "sth", SYN (47), FMT (68), 0xa0200000,
2388     & fmt_68_sth_d_ops[0],
2389     { 2, 0, { (1<<MACH_M32R), PIPE_NONE } }
2390   },
2391 /* sth $src1,@($src2,$slo16) */
2392   {
2393     { 1, 1, 1, 1 },
2394     "sth-d2", "sth", SYN (48), FMT (64), 0xa0200000,
2395     0,
2396     { 2, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE } }
2397   },
2398 /* st $src1,@+$src2 */
2399   {
2400     { 1, 1, 1, 1 },
2401     "st-plus", "st", SYN (49), FMT (69), 0x2060,
2402     & fmt_69_st_plus_ops[0],
2403     { 2, 0, { (1<<MACH_M32R), PIPE_O } }
2404   },
2405 /* st $src1,@-$src2 */
2406   {
2407     { 1, 1, 1, 1 },
2408     "st-minus", "st", SYN (50), FMT (69), 0x2070,
2409     & fmt_69_st_plus_ops[0],
2410     { 2, 0, { (1<<MACH_M32R), PIPE_O } }
2411   },
2412 /* sub $dr,$sr */
2413   {
2414     { 1, 1, 1, 1 },
2415     "sub", "sub", SYN (0), FMT (0), 0x20,
2416     & fmt_0_add_ops[0],
2417     { 2, 0, { (1<<MACH_M32R), PIPE_OS } }
2418   },
2419 /* subv $dr,$sr */
2420   {
2421     { 1, 1, 1, 1 },
2422     "subv", "subv", SYN (0), FMT (5), 0x0,
2423     & fmt_5_addv_ops[0],
2424     { 2, 0, { (1<<MACH_M32R), PIPE_OS } }
2425   },
2426 /* subx $dr,$sr */
2427   {
2428     { 1, 1, 1, 1 },
2429     "subx", "subx", SYN (0), FMT (7), 0x10,
2430     & fmt_7_addx_ops[0],
2431     { 2, 0, { (1<<MACH_M32R), PIPE_OS } }
2432   },
2433 /* trap #$uimm4 */
2434   {
2435     { 1, 1, 1, 1 },
2436     "trap", "trap", SYN (51), FMT (70), 0x10f0,
2437     & fmt_70_trap_ops[0],
2438     { 2, 0|A(FILL_SLOT)|A(UNCOND_CTI), { (1<<MACH_M32R), PIPE_O } }
2439   },
2440 /* trap $uimm4 */
2441   {
2442     { 1, 1, 1, 1 },
2443     "trap.a", "trap", SYN (52), FMT (70), 0x10f0,
2444     & fmt_70_trap_ops[0],
2445     { 2, 0|A(ALIAS)|A(FILL_SLOT)|A(UNCOND_CTI), { (1<<MACH_M32R), PIPE_O } }
2446   },
2447 /* unlock $src1,@$src2 */
2448   {
2449     { 1, 1, 1, 1 },
2450     "unlock", "unlock", SYN (45), FMT (71), 0x2050,
2451     & fmt_71_unlock_ops[0],
2452     { 2, 0, { (1<<MACH_M32R), PIPE_O } }
2453   },
2454 /* push $src1 */
2455   {
2456     { 1, 1, 1, 1 },
2457     "push", "push", SYN (34), FMT (72), 0x207f,
2458     0,
2459     { 2, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE } }
2460   },
2461 /* pop $dr */
2462   {
2463     { 1, 1, 1, 1 },
2464     "pop", "pop", SYN (31), FMT (73), 0x20ef,
2465     0,
2466     { 2, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE } }
2467   },
2468 /* start-sanitize-m32rx */
2469 /* satb $dr,$src2 */
2470   {
2471     { 1, 1, 1, 1 },
2472     "satb", "satb", SYN (53), FMT (74), 0x80000100,
2473     & fmt_74_satb_ops[0],
2474     { 2, 0, { (1<<MACH_M32RX), PIPE_NONE } }
2475   },
2476 /* end-sanitize-m32rx */
2477 /* start-sanitize-m32rx */
2478 /* sath $dr,$src2 */
2479   {
2480     { 1, 1, 1, 1 },
2481     "sath", "sath", SYN (53), FMT (74), 0x80000200,
2482     & fmt_74_satb_ops[0],
2483     { 2, 0, { (1<<MACH_M32RX), PIPE_NONE } }
2484   },
2485 /* end-sanitize-m32rx */
2486 /* start-sanitize-m32rx */
2487 /* sat $dr,$src2 */
2488   {
2489     { 1, 1, 1, 1 },
2490     "sat", "sat", SYN (53), FMT (75), 0x80000000,
2491     & fmt_75_sat_ops[0],
2492     { 2, 0, { (1<<MACH_M32RX), PIPE_NONE } }
2493   },
2494 /* end-sanitize-m32rx */
2495 /* start-sanitize-m32rx */
2496 /* pcmpbz $src2 */
2497   {
2498     { 1, 1, 1, 1 },
2499     "pcmpbz", "pcmpbz", SYN (20), FMT (23), 0x370,
2500     & fmt_23_cmpz_ops[0],
2501     { 2, 0, { (1<<MACH_M32RX), PIPE_OS } }
2502   },
2503 /* end-sanitize-m32rx */
2504 /* start-sanitize-m32rx */
2505 /* sadd */
2506   {
2507     { 1, 1, 1, 1 },
2508     "sadd", "sadd", SYN (37), FMT (76), 0x50e4,
2509     & fmt_76_sadd_ops[0],
2510     { 2, 0, { (1<<MACH_M32RX), PIPE_S } }
2511   },
2512 /* end-sanitize-m32rx */
2513 /* start-sanitize-m32rx */
2514 /* macwu1 $src1,$src2 */
2515   {
2516     { 1, 1, 1, 1 },
2517     "macwu1", "macwu1", SYN (15), FMT (77), 0x50b0,
2518     & fmt_77_macwu1_ops[0],
2519     { 2, 0, { (1<<MACH_M32RX), PIPE_S } }
2520   },
2521 /* end-sanitize-m32rx */
2522 /* start-sanitize-m32rx */
2523 /* msblo $src1,$src2 */
2524   {
2525     { 1, 1, 1, 1 },
2526     "msblo", "msblo", SYN (15), FMT (41), 0x50d0,
2527     & fmt_41_machi_ops[0],
2528     { 2, 0, { (1<<MACH_M32RX), PIPE_S } }
2529   },
2530 /* end-sanitize-m32rx */
2531 /* start-sanitize-m32rx */
2532 /* mulwu1 $src1,$src2 */
2533   {
2534     { 1, 1, 1, 1 },
2535     "mulwu1", "mulwu1", SYN (15), FMT (78), 0x50a0,
2536     & fmt_78_mulwu1_ops[0],
2537     { 2, 0, { (1<<MACH_M32RX), PIPE_S } }
2538   },
2539 /* end-sanitize-m32rx */
2540 /* start-sanitize-m32rx */
2541 /* maclh1 $src1,$src2 */
2542   {
2543     { 1, 1, 1, 1 },
2544     "maclh1", "maclh1", SYN (15), FMT (77), 0x50c0,
2545     & fmt_77_macwu1_ops[0],
2546     { 2, 0, { (1<<MACH_M32RX), PIPE_S } }
2547   },
2548 /* end-sanitize-m32rx */
2549 /* start-sanitize-m32rx */
2550 /* sc */
2551   {
2552     { 1, 1, 1, 1 },
2553     "sc", "sc", SYN (37), FMT (79), 0x7401,
2554     & fmt_79_sc_ops[0],
2555     { 2, 0, { (1<<MACH_M32RX), PIPE_O } }
2556   },
2557 /* end-sanitize-m32rx */
2558 /* start-sanitize-m32rx */
2559 /* snc */
2560   {
2561     { 1, 1, 1, 1 },
2562     "snc", "snc", SYN (37), FMT (79), 0x7501,
2563     & fmt_79_sc_ops[0],
2564     { 2, 0, { (1<<MACH_M32RX), PIPE_O } }
2565   },
2566 /* end-sanitize-m32rx */
2567 };
2568
2569 #undef A
2570 #undef SYN
2571 #undef FMT
2572
2573 CGEN_INSN_TABLE m32r_cgen_insn_table =
2574 {
2575   & m32r_cgen_insn_table_entries[0],
2576   sizeof (CGEN_INSN),
2577   MAX_INSNS,
2578   NULL,
2579   m32r_cgen_asm_hash_insn, CGEN_ASM_HASH_SIZE,
2580   m32r_cgen_dis_hash_insn, CGEN_DIS_HASH_SIZE
2581 };
2582
2583 /* The hash functions are recorded here to help keep assembler code out of
2584    the disassembler and vice versa.  */
2585
2586 unsigned int
2587 m32r_cgen_asm_hash_insn (insn)
2588      const char * insn;
2589 {
2590   return CGEN_ASM_HASH (insn);
2591 }
2592
2593 unsigned int
2594 m32r_cgen_dis_hash_insn (buf, value)
2595      const char * buf;
2596      unsigned long value;
2597 {
2598   return CGEN_DIS_HASH (buf, value);
2599 }
2600
2601 CGEN_OPCODE_DATA m32r_cgen_opcode_data =
2602 {
2603   & m32r_cgen_hw_entries[0],
2604   & m32r_cgen_insn_table,
2605 };
2606
2607 void
2608 m32r_cgen_init_tables (mach)
2609     int mach;
2610 {
2611 }
2612
2613 /* Main entry point for stuffing values in cgen_fields.  */
2614
2615 CGEN_INLINE void
2616 m32r_cgen_set_operand (opindex, valuep, fields)
2617      int opindex;
2618      const long * valuep;
2619      CGEN_FIELDS * fields;
2620 {
2621   switch (opindex)
2622     {
2623     case M32R_OPERAND_SR :
2624       fields->f_r2 = * valuep;
2625       break;
2626     case M32R_OPERAND_DR :
2627       fields->f_r1 = * valuep;
2628       break;
2629     case M32R_OPERAND_SRC1 :
2630       fields->f_r1 = * valuep;
2631       break;
2632     case M32R_OPERAND_SRC2 :
2633       fields->f_r2 = * valuep;
2634       break;
2635     case M32R_OPERAND_SCR :
2636       fields->f_r2 = * valuep;
2637       break;
2638     case M32R_OPERAND_DCR :
2639       fields->f_r1 = * valuep;
2640       break;
2641     case M32R_OPERAND_SIMM8 :
2642       fields->f_simm8 = * valuep;
2643       break;
2644     case M32R_OPERAND_SIMM16 :
2645       fields->f_simm16 = * valuep;
2646       break;
2647     case M32R_OPERAND_UIMM4 :
2648       fields->f_uimm4 = * valuep;
2649       break;
2650     case M32R_OPERAND_UIMM5 :
2651       fields->f_uimm5 = * valuep;
2652       break;
2653     case M32R_OPERAND_UIMM16 :
2654       fields->f_uimm16 = * valuep;
2655       break;
2656 /* start-sanitize-m32rx */
2657     case M32R_OPERAND_IMM1 :
2658       fields->f_imm1 = * valuep;
2659       break;
2660 /* end-sanitize-m32rx */
2661 /* start-sanitize-m32rx */
2662     case M32R_OPERAND_ACCD :
2663       fields->f_accd = * valuep;
2664       break;
2665 /* end-sanitize-m32rx */
2666 /* start-sanitize-m32rx */
2667     case M32R_OPERAND_ACCS :
2668       fields->f_accs = * valuep;
2669       break;
2670 /* end-sanitize-m32rx */
2671 /* start-sanitize-m32rx */
2672     case M32R_OPERAND_ACC :
2673       fields->f_acc = * valuep;
2674       break;
2675 /* end-sanitize-m32rx */
2676     case M32R_OPERAND_HI16 :
2677       fields->f_hi16 = * valuep;
2678       break;
2679     case M32R_OPERAND_SLO16 :
2680       fields->f_simm16 = * valuep;
2681       break;
2682     case M32R_OPERAND_ULO16 :
2683       fields->f_uimm16 = * valuep;
2684       break;
2685     case M32R_OPERAND_UIMM24 :
2686       fields->f_uimm24 = * valuep;
2687       break;
2688     case M32R_OPERAND_DISP8 :
2689       fields->f_disp8 = * valuep;
2690       break;
2691     case M32R_OPERAND_DISP16 :
2692       fields->f_disp16 = * valuep;
2693       break;
2694     case M32R_OPERAND_DISP24 :
2695       fields->f_disp24 = * valuep;
2696       break;
2697
2698     default :
2699       fprintf (stderr, "Unrecognized field %d while setting operand.\n",
2700                        opindex);
2701       abort ();
2702   }
2703 }
2704
2705 /* Main entry point for getting values from cgen_fields.  */
2706
2707 CGEN_INLINE long
2708 m32r_cgen_get_operand (opindex, fields)
2709      int opindex;
2710      const CGEN_FIELDS * fields;
2711 {
2712   long value;
2713
2714   switch (opindex)
2715     {
2716     case M32R_OPERAND_SR :
2717       value = fields->f_r2;
2718       break;
2719     case M32R_OPERAND_DR :
2720       value = fields->f_r1;
2721       break;
2722     case M32R_OPERAND_SRC1 :
2723       value = fields->f_r1;
2724       break;
2725     case M32R_OPERAND_SRC2 :
2726       value = fields->f_r2;
2727       break;
2728     case M32R_OPERAND_SCR :
2729       value = fields->f_r2;
2730       break;
2731     case M32R_OPERAND_DCR :
2732       value = fields->f_r1;
2733       break;
2734     case M32R_OPERAND_SIMM8 :
2735       value = fields->f_simm8;
2736       break;
2737     case M32R_OPERAND_SIMM16 :
2738       value = fields->f_simm16;
2739       break;
2740     case M32R_OPERAND_UIMM4 :
2741       value = fields->f_uimm4;
2742       break;
2743     case M32R_OPERAND_UIMM5 :
2744       value = fields->f_uimm5;
2745       break;
2746     case M32R_OPERAND_UIMM16 :
2747       value = fields->f_uimm16;
2748       break;
2749 /* start-sanitize-m32rx */
2750     case M32R_OPERAND_IMM1 :
2751       value = fields->f_imm1;
2752       break;
2753 /* end-sanitize-m32rx */
2754 /* start-sanitize-m32rx */
2755     case M32R_OPERAND_ACCD :
2756       value = fields->f_accd;
2757       break;
2758 /* end-sanitize-m32rx */
2759 /* start-sanitize-m32rx */
2760     case M32R_OPERAND_ACCS :
2761       value = fields->f_accs;
2762       break;
2763 /* end-sanitize-m32rx */
2764 /* start-sanitize-m32rx */
2765     case M32R_OPERAND_ACC :
2766       value = fields->f_acc;
2767       break;
2768 /* end-sanitize-m32rx */
2769     case M32R_OPERAND_HI16 :
2770       value = fields->f_hi16;
2771       break;
2772     case M32R_OPERAND_SLO16 :
2773       value = fields->f_simm16;
2774       break;
2775     case M32R_OPERAND_ULO16 :
2776       value = fields->f_uimm16;
2777       break;
2778     case M32R_OPERAND_UIMM24 :
2779       value = fields->f_uimm24;
2780       break;
2781     case M32R_OPERAND_DISP8 :
2782       value = fields->f_disp8;
2783       break;
2784     case M32R_OPERAND_DISP16 :
2785       value = fields->f_disp16;
2786       break;
2787     case M32R_OPERAND_DISP24 :
2788       value = fields->f_disp24;
2789       break;
2790
2791     default :
2792       fprintf (stderr, "Unrecognized field %d while getting operand.\n",
2793                        opindex);
2794       abort ();
2795   }
2796
2797   return value;
2798 }
2799