opcodes/m32r-opc.h

   1 /* Instruction description for m32r.
   2
   3 THIS FILE IS MACHINE GENERATED WITH CGEN.
   4
   5 Copyright (C) 1996, 1997, 1998 Free Software Foundation, Inc.
   6
   7 This file is part of the GNU Binutils and/or GDB, the GNU debugger.
   8
   9 This program is free software; you can redistribute it and/or modify
  10 it under the terms of the GNU General Public License as published by
  11 the Free Software Foundation; either version 2, or (at your option)
  12 any later version.
  13
  14 This program is distributed in the hope that it will be useful,
  15 but WITHOUT ANY WARRANTY; without even the implied warranty of
  16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17 GNU General Public License for more details.
  18
  19 You should have received a copy of the GNU General Public License along
  20 with this program; if not, write to the Free Software Foundation, Inc.,
  21 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  22
  23 */
  24
  25 #ifndef M32R_OPC_H
  26 #define M32R_OPC_H
  27
  28 #define CGEN_ARCH m32r
  29
  30 /* Given symbol S, return m32r_cgen_<s>.  */
  31 #define CGEN_SYM(s) CONCAT3 (m32r,_cgen_,s)
  32
  33 /* Selected cpu families.  */
  34 #define HAVE_CPU_M32R
  35 /* start-sanitize-m32rx */
  36 #define HAVE_CPU_M32RX
  37 /* end-sanitize-m32rx */
  38
  39 #define CGEN_WORD_BITSIZE 32
  40 #define CGEN_DEFAULT_INSN_BITSIZE 32
  41 #define CGEN_BASE_INSN_BITSIZE 32
  42 #define CGEN_MAX_INSN_BITSIZE 32
  43 #define CGEN_DEFAULT_INSN_SIZE (CGEN_DEFAULT_INSN_BITSIZE / 8)
  44 #define CGEN_BASE_INSN_SIZE (CGEN_BASE_INSN_BITSIZE / 8)
  45 #define CGEN_MAX_INSN_SIZE (CGEN_MAX_INSN_BITSIZE / 8)
  46 #define CGEN_INT_INSN
  47
  48 /* FIXME: Need to compute CGEN_MAX_SYNTAX_BYTES.  */
  49
  50 /* CGEN_MNEMONIC_OPERANDS is defined if mnemonics have operands.
  51    e.g. In "b,a foo" the ",a" is an operand.  If mnemonics have operands
  52    we can't hash on everything up to the space.  */
  53 #define CGEN_MNEMONIC_OPERANDS
  54 /* Maximum number of operands any insn or macro-insn has.  */
  55 #define CGEN_MAX_INSN_OPERANDS 16
  56
  57 /* Enums.  */
  58
  59 /* Enum declaration for insn format enums.  */
  60 typedef enum insn_op1 {
  61   OP1_0, OP1_1, OP1_2, OP1_3
  62  , OP1_4, OP1_5, OP1_6, OP1_7
  63  , OP1_8, OP1_9, OP1_10, OP1_11
  64  , OP1_12, OP1_13, OP1_14, OP1_15
  65 } INSN_OP1;
  66
  67 /* Enum declaration for op2 enums.  */
  68 typedef enum insn_op2 {
  69   OP2_0, OP2_1, OP2_2, OP2_3
  70  , OP2_4, OP2_5, OP2_6, OP2_7
  71  , OP2_8, OP2_9, OP2_10, OP2_11
  72  , OP2_12, OP2_13, OP2_14, OP2_15
  73 } INSN_OP2;
  74
  75 /* Enum declaration for general registers.  */
  76 typedef enum h_gr {
  77   H_GR_FP = 13, H_GR_LR = 14, H_GR_SP = 15, H_GR_R0 = 0
  78  , H_GR_R1 = 1, H_GR_R2 = 2, H_GR_R3 = 3, H_GR_R4 = 4
  79  , H_GR_R5 = 5, H_GR_R6 = 6, H_GR_R7 = 7, H_GR_R8 = 8
  80  , H_GR_R9 = 9, H_GR_R10 = 10, H_GR_R11 = 11, H_GR_R12 = 12
  81  , H_GR_R13 = 13, H_GR_R14 = 14, H_GR_R15 = 15
  82 } H_GR;
  83
  84 /* Enum declaration for control registers.  */
  85 typedef enum h_cr {
  86   H_CR_PSW = 0, H_CR_CBR = 1, H_CR_SPI = 2, H_CR_SPU = 3
  87  , H_CR_BPC = 6, H_CR_CR0 = 0, H_CR_CR1 = 1, H_CR_CR2 = 2
  88  , H_CR_CR3 = 3, H_CR_CR4 = 4, H_CR_CR5 = 5, H_CR_CR6 = 6
  89  , H_CR_CR7 = 7, H_CR_CR8 = 8, H_CR_CR9 = 9, H_CR_CR10 = 10
  90  , H_CR_CR11 = 11, H_CR_CR12 = 12, H_CR_CR13 = 13, H_CR_CR14 = 14
  91  , H_CR_CR15 = 15
  92 } H_CR;
  93
  94 /* start-sanitize-m32rx */
  95 /* Enum declaration for accumulators.  */
  96 typedef enum h_accums {
  97   H_ACCUMS_A0, H_ACCUMS_A1
  98 } H_ACCUMS;
  99
 100 /* end-sanitize-m32rx */
 101 /* Enum declaration for m32r operand types.  */
 102 typedef enum cgen_operand_type {
 103   M32R_OPERAND_PC, M32R_OPERAND_SR, M32R_OPERAND_DR, M32R_OPERAND_SRC1
 104  , M32R_OPERAND_SRC2, M32R_OPERAND_SCR, M32R_OPERAND_DCR, M32R_OPERAND_SIMM8
 105  , M32R_OPERAND_SIMM16, M32R_OPERAND_UIMM4, M32R_OPERAND_UIMM5, M32R_OPERAND_UIMM16
 106 /* start-sanitize-m32rx */
 107  , M32R_OPERAND_IMM1
 108 /* end-sanitize-m32rx */
 109 /* start-sanitize-m32rx */
 110  , M32R_OPERAND_ACCD
 111 /* end-sanitize-m32rx */
 112 /* start-sanitize-m32rx */
 113  , M32R_OPERAND_ACCS
 114 /* end-sanitize-m32rx */
 115 /* start-sanitize-m32rx */
 116  , M32R_OPERAND_ACC
 117 /* end-sanitize-m32rx */
 118  , M32R_OPERAND_HASH, M32R_OPERAND_HI16, M32R_OPERAND_SLO16, M32R_OPERAND_ULO16
 119  , M32R_OPERAND_UIMM24, M32R_OPERAND_DISP8, M32R_OPERAND_DISP16, M32R_OPERAND_DISP24
 120  , M32R_OPERAND_CONDBIT, M32R_OPERAND_ACCUM, M32R_OPERAND_MAX
 121 } CGEN_OPERAND_TYPE;
 122
 123 /* Non-boolean attributes.  */
 124
 125 /* Enum declaration for machine type selection.  */
 126 typedef enum mach_attr {
 127   MACH_M32R
 128 /* start-sanitize-m32rx */
 129  , MACH_M32RX
 130 /* end-sanitize-m32rx */
 131  , MACH_MAX
 132 } MACH_ATTR;
 133
 134 /* start-sanitize-m32rx */
 135 /* Enum declaration for parallel execution pipeline selection.  */
 136 typedef enum pipe_attr {
 137   PIPE_NONE, PIPE_O, PIPE_S, PIPE_OS
 138 } PIPE_ATTR;
 139
 140 /* end-sanitize-m32rx */
 141 /* Number of architecture variants.  */
 142 #define MAX_MACHS ((int) MACH_MAX)
 143
 144 /* Number of operands types.  */
 145 #define MAX_OPERANDS ((int) M32R_OPERAND_MAX)
 146
 147 /* Maximum number of operands referenced by any insn.  */
 148 #define MAX_OPERAND_INSTANCES 8
 149
 150 /* Operand and instruction attribute indices.  */
 151
 152 /* Enum declaration for cgen_operand attrs.  */
 153 typedef enum cgen_operand_attr {
 154   CGEN_OPERAND_ABS_ADDR, CGEN_OPERAND_FAKE, CGEN_OPERAND_HASH_PREFIX, CGEN_OPERAND_NEGATIVE
 155  , CGEN_OPERAND_PC, CGEN_OPERAND_PCREL_ADDR, CGEN_OPERAND_RELAX, CGEN_OPERAND_RELOC
 156  , CGEN_OPERAND_SIGN_OPT, CGEN_OPERAND_UNSIGNED
 157 } CGEN_OPERAND_ATTR;
 158
 159 /* Number of non-boolean elements in cgen_operand.  */
 160 #define CGEN_OPERAND_NBOOL_ATTRS ((int) CGEN_OPERAND_ABS_ADDR)
 161
 162 /* Enum declaration for cgen_insn attrs.  */
 163 typedef enum cgen_insn_attr {
 164   CGEN_INSN_MACH
 165 /* start-sanitize-m32rx */
 166  , CGEN_INSN_PIPE
 167 /* end-sanitize-m32rx */
 168  , CGEN_INSN_ALIAS, CGEN_INSN_COND_CTI, CGEN_INSN_FILL_SLOT, CGEN_INSN_NO_DIS
 169  , CGEN_INSN_PARALLEL, CGEN_INSN_RELAX, CGEN_INSN_RELAXABLE, CGEN_INSN_SPECIAL
 170  , CGEN_INSN_UNCOND_CTI
 171 } CGEN_INSN_ATTR;
 172
 173 /* Number of non-boolean elements in cgen_insn.  */
 174 #define CGEN_INSN_NBOOL_ATTRS ((int) CGEN_INSN_ALIAS)
 175
 176 /* Enum declaration for m32r instruction types.  */
 177 typedef enum cgen_insn_type {
 178   M32R_INSN_ILLEGAL, M32R_INSN_ADD, M32R_INSN_ADD3, M32R_INSN_AND
 179  , M32R_INSN_AND3, M32R_INSN_OR, M32R_INSN_OR3, M32R_INSN_XOR
 180  , M32R_INSN_XOR3, M32R_INSN_ADDI, M32R_INSN_ADDV, M32R_INSN_ADDV3
 181  , M32R_INSN_ADDX, M32R_INSN_BC8, M32R_INSN_BC24, M32R_INSN_BEQ
 182  , M32R_INSN_BEQZ, M32R_INSN_BGEZ, M32R_INSN_BGTZ, M32R_INSN_BLEZ
 183  , M32R_INSN_BLTZ, M32R_INSN_BNEZ, M32R_INSN_BL8, M32R_INSN_BL24
 184 /* start-sanitize-m32rx */
 185  , M32R_INSN_BCL8
 186 /* end-sanitize-m32rx */
 187 /* start-sanitize-m32rx */
 188  , M32R_INSN_BCL24
 189 /* end-sanitize-m32rx */
 190  , M32R_INSN_BNC8, M32R_INSN_BNC24, M32R_INSN_BNE, M32R_INSN_BRA8
 191  , M32R_INSN_BRA24
 192 /* start-sanitize-m32rx */
 193  , M32R_INSN_BNCL8
 194 /* end-sanitize-m32rx */
 195 /* start-sanitize-m32rx */
 196  , M32R_INSN_BNCL24
 197 /* end-sanitize-m32rx */
 198  , M32R_INSN_CMP, M32R_INSN_CMPI, M32R_INSN_CMPU, M32R_INSN_CMPUI
 199 /* start-sanitize-m32rx */
 200  , M32R_INSN_CMPEQ
 201 /* end-sanitize-m32rx */
 202 /* start-sanitize-m32rx */
 203  , M32R_INSN_CMPZ
 204 /* end-sanitize-m32rx */
 205  , M32R_INSN_DIV, M32R_INSN_DIVU, M32R_INSN_REM, M32R_INSN_REMU
 206 /* start-sanitize-m32rx */
 207  , M32R_INSN_DIVH
 208 /* end-sanitize-m32rx */
 209 /* start-sanitize-m32rx */
 210  , M32R_INSN_JC
 211 /* end-sanitize-m32rx */
 212 /* start-sanitize-m32rx */
 213  , M32R_INSN_JNC
 214 /* end-sanitize-m32rx */
 215  , M32R_INSN_JL, M32R_INSN_JMP, M32R_INSN_LD, M32R_INSN_LD_D
 216  , M32R_INSN_LDB, M32R_INSN_LDB_D, M32R_INSN_LDH, M32R_INSN_LDH_D
 217  , M32R_INSN_LDUB, M32R_INSN_LDUB_D, M32R_INSN_LDUH, M32R_INSN_LDUH_D
 218  , M32R_INSN_LD_PLUS, M32R_INSN_LD24, M32R_INSN_LDI8, M32R_INSN_LDI16
 219  , M32R_INSN_LOCK, M32R_INSN_MACHI
 220 /* start-sanitize-m32rx */
 221  , M32R_INSN_MACHI_A
 222 /* end-sanitize-m32rx */
 223  , M32R_INSN_MACLO
 224 /* start-sanitize-m32rx */
 225  , M32R_INSN_MACLO_A
 226 /* end-sanitize-m32rx */
 227  , M32R_INSN_MACWHI, M32R_INSN_MACWLO, M32R_INSN_MUL, M32R_INSN_MULHI
 228 /* start-sanitize-m32rx */
 229  , M32R_INSN_MULHI_A
 230 /* end-sanitize-m32rx */
 231  , M32R_INSN_MULLO
 232 /* start-sanitize-m32rx */
 233  , M32R_INSN_MULLO_A
 234 /* end-sanitize-m32rx */
 235  , M32R_INSN_MULWHI, M32R_INSN_MULWLO, M32R_INSN_MV, M32R_INSN_MVFACHI
 236 /* start-sanitize-m32rx */
 237  , M32R_INSN_MVFACHI_A
 238 /* end-sanitize-m32rx */
 239  , M32R_INSN_MVFACLO
 240 /* start-sanitize-m32rx */
 241  , M32R_INSN_MVFACLO_A
 242 /* end-sanitize-m32rx */
 243  , M32R_INSN_MVFACMI
 244 /* start-sanitize-m32rx */
 245  , M32R_INSN_MVFACMI_A
 246 /* end-sanitize-m32rx */
 247  , M32R_INSN_MVFC, M32R_INSN_MVTACHI
 248 /* start-sanitize-m32rx */
 249  , M32R_INSN_MVTACHI_A
 250 /* end-sanitize-m32rx */
 251  , M32R_INSN_MVTACLO
 252 /* start-sanitize-m32rx */
 253  , M32R_INSN_MVTACLO_A
 254 /* end-sanitize-m32rx */
 255  , M32R_INSN_MVTC, M32R_INSN_NEG, M32R_INSN_NOP, M32R_INSN_NOT
 256  , M32R_INSN_RAC
 257 /* start-sanitize-m32rx */
 258  , M32R_INSN_RAC_DSI
 259 /* end-sanitize-m32rx */
 260  , M32R_INSN_RACH
 261 /* start-sanitize-m32rx */
 262  , M32R_INSN_RACH_DSI
 263 /* end-sanitize-m32rx */
 264  , M32R_INSN_RTE, M32R_INSN_SETH, M32R_INSN_SLL, M32R_INSN_SLL3
 265  , M32R_INSN_SLLI, M32R_INSN_SRA, M32R_INSN_SRA3, M32R_INSN_SRAI
 266  , M32R_INSN_SRL, M32R_INSN_SRL3, M32R_INSN_SRLI, M32R_INSN_ST
 267  , M32R_INSN_ST_D, M32R_INSN_STB, M32R_INSN_STB_D, M32R_INSN_STH
 268  , M32R_INSN_STH_D, M32R_INSN_ST_PLUS, M32R_INSN_ST_MINUS, M32R_INSN_SUB
 269  , M32R_INSN_SUBV, M32R_INSN_SUBX, M32R_INSN_TRAP, M32R_INSN_UNLOCK
 270 /* start-sanitize-m32rx */
 271  , M32R_INSN_SATB
 272 /* end-sanitize-m32rx */
 273 /* start-sanitize-m32rx */
 274  , M32R_INSN_SATH
 275 /* end-sanitize-m32rx */
 276 /* start-sanitize-m32rx */
 277  , M32R_INSN_SAT
 278 /* end-sanitize-m32rx */
 279 /* start-sanitize-m32rx */
 280  , M32R_INSN_PCMPBZ
 281 /* end-sanitize-m32rx */
 282 /* start-sanitize-m32rx */
 283  , M32R_INSN_SADD
 284 /* end-sanitize-m32rx */
 285 /* start-sanitize-m32rx */
 286  , M32R_INSN_MACWU1
 287 /* end-sanitize-m32rx */
 288 /* start-sanitize-m32rx */
 289  , M32R_INSN_MSBLO
 290 /* end-sanitize-m32rx */
 291 /* start-sanitize-m32rx */
 292  , M32R_INSN_MULWU1
 293 /* end-sanitize-m32rx */
 294 /* start-sanitize-m32rx */
 295  , M32R_INSN_MACLH1
 296 /* end-sanitize-m32rx */
 297 /* start-sanitize-m32rx */
 298  , M32R_INSN_SC
 299 /* end-sanitize-m32rx */
 300 /* start-sanitize-m32rx */
 301  , M32R_INSN_SNC
 302 /* end-sanitize-m32rx */
 303  , M32R_INSN_MAX
 304 } CGEN_INSN_TYPE;
 305
 306 /* Index of `illegal' insn place holder.  */
 307 #define CGEN_INSN_ILLEGAL M32R_INSN_ILLEGAL
 308 /* Total number of insns in table.  */
 309 #define MAX_INSNS ((int) M32R_INSN_MAX)
 310
 311 /* cgen.h uses things we just defined.  */
 312 #include "opcode/cgen.h"
 313
 314 /* This struct records data prior to insertion or after extraction.  */
 315 struct cgen_fields
 316 {
 317   long f_nil;
 318   long f_op1;
 319   long f_op2;
 320   long f_cond;
 321   long f_r1;
 322   long f_r2;
 323   long f_simm8;
 324   long f_simm16;
 325   long f_shift_op2;
 326   long f_uimm4;
 327   long f_uimm5;
 328   long f_uimm16;
 329   long f_uimm24;
 330   long f_hi16;
 331   long f_disp8;
 332   long f_disp16;
 333   long f_disp24;
 334 /* start-sanitize-m32rx */
 335   long f_op23;
 336 /* end-sanitize-m32rx */
 337 /* start-sanitize-m32rx */
 338   long f_op3;
 339 /* end-sanitize-m32rx */
 340 /* start-sanitize-m32rx */
 341   long f_acc;
 342 /* end-sanitize-m32rx */
 343 /* start-sanitize-m32rx */
 344   long f_accs;
 345 /* end-sanitize-m32rx */
 346 /* start-sanitize-m32rx */
 347   long f_accd;
 348 /* end-sanitize-m32rx */
 349 /* start-sanitize-m32rx */
 350   long f_bits67;
 351 /* end-sanitize-m32rx */
 352 /* start-sanitize-m32rx */
 353   long f_bit14;
 354 /* end-sanitize-m32rx */
 355 /* start-sanitize-m32rx */
 356   long f_imm1;
 357 /* end-sanitize-m32rx */
 358   int length;
 359 };
 360
 361 /* Attributes.  */
 362 extern const CGEN_ATTR_TABLE m32r_cgen_operand_attr_table[];
 363 extern const CGEN_ATTR_TABLE m32r_cgen_insn_attr_table[];
 364
 365 /* Enum declaration for m32r hardware types.  */
 366 typedef enum hw_type {
 367   HW_H_PC, HW_H_MEMORY, HW_H_SINT, HW_H_UINT
 368  , HW_H_ADDR, HW_H_IADDR, HW_H_HI16, HW_H_SLO16
 369  , HW_H_ULO16, HW_H_GR, HW_H_CR, HW_H_ACCUM
 370 /* start-sanitize-m32rx */
 371  , HW_H_ACCUMS
 372 /* end-sanitize-m32rx */
 373  , HW_H_COND, HW_H_SM, HW_H_BSM, HW_H_IE
 374  , HW_H_BIE, HW_H_BCOND, HW_H_BPC, HW_H_LOCK
 375  , HW_MAX
 376 } HW_TYPE;
 377
 378 #define MAX_HW ((int) HW_MAX)
 379
 380 /* Hardware decls.  */
 381
 382 extern CGEN_KEYWORD m32r_cgen_opval_h_gr;
 383 extern CGEN_KEYWORD m32r_cgen_opval_h_cr;
 384 /* start-sanitize-m32rx */
 385 extern CGEN_KEYWORD m32r_cgen_opval_h_accums;
 386 /* end-sanitize-m32rx */
 387
 388 #define CGEN_INIT_PARSE() \
 389 {\
 390 }
 391 #define CGEN_INIT_INSERT() \
 392 {\
 393 }
 394 #define CGEN_INIT_EXTRACT() \
 395 {\
 396 }
 397 #define CGEN_INIT_PRINT() \
 398 {\
 399 }
 400
 401 /* -- opc.h */
 402
 403 #undef CGEN_DIS_HASH_SIZE
 404 #define CGEN_DIS_HASH_SIZE 256
 405 #undef CGEN_DIS_HASH
 406 #define X(b) (((unsigned char *) (b))[0] & 0xf0)
 407 #define CGEN_DIS_HASH(buffer, value) \
 408 (X (buffer) | \
 409  (X (buffer) == 0x40 || X (buffer) == 0xe0 || X (buffer) == 0x60 || X (buffer) == 0x50 ? 0 \
 410   : X (buffer) == 0x70 || X (buffer) == 0xf0 ? (((unsigned char *) (buffer))[0] & 0xf) \
 411   : X (buffer) == 0x30 ? ((((unsigned char *) (buffer))[1] & 0x70) >> 4) \
 412   : ((((unsigned char *) (buffer))[1] & 0xf0) >> 4)))
 413
 414 /* -- */
 415
 416
 417 #endif /* M32R_OPC_H */