1 /* Print Motorola 68k instructions.
2 Copyright 1986, 1987, 1989, 1991, 1992, 1993 Free Software Foundation, Inc.
4 This file is free software; you can redistribute it and/or modify
5 it under the terms of the GNU General Public License as published by
6 the Free Software Foundation; either version 2 of the License, or
7 (at your option) any later version.
9 This program is distributed in the hope that it will be useful,
10 but WITHOUT ANY WARRANTY; without even the implied warranty of
11 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 GNU General Public License for more details.
14 You should have received a copy of the GNU General Public License
15 along with this program; if not, write to the Free Software
16 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */
19 #include "ieee-float.h"
21 extern CONST
struct ext_format ext_format_68881
;
23 /* Opcode/m68k.h is a massive table. As a kludge, break it up into
24 two pieces. This makes nonportable C -- FIXME -- it assumes that
25 two data items declared near each other will be contiguous in
26 memory. This kludge can be removed, FIXME, when GCC is fixed to not
27 be a hog about initializers. */
30 #define BREAK_UP_BIG_DECL }; \
31 struct m68k_opcode m68k_opcodes_2[] = {
32 #define AND_OTHER_PART sizeof (m68k_opcodes_2)
35 #include "opcode/m68k.h"
38 /* Local function prototypes */
41 fetch_arg
PARAMS ((unsigned char *, int, int, disassemble_info
*));
44 print_base
PARAMS ((int, int, disassemble_info
*));
46 static unsigned char *
47 print_indexed
PARAMS ((int, unsigned char *, bfd_vma
, disassemble_info
*));
49 static unsigned char *
50 print_insn_arg
PARAMS ((char *, unsigned char *, unsigned char *, bfd_vma
,
53 /* Sign-extend an (unsigned char). */
55 #define COERCE_SIGNED_CHAR(ch) ((signed char)(ch))
57 #define COERCE_SIGNED_CHAR(ch) ((int)(((ch) ^ 0x80) & 0xFF) - 128)
60 CONST
char * CONST fpcr_names
[] = {
61 "", "fpiar", "fpsr", "fpiar/fpsr", "fpcr",
62 "fpiar/fpcr", "fpsr/fpcr", "fpiar/fpsr/fpcr"};
64 static char *reg_names
[] = {
65 "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7", "a0",
66 "a1", "a2", "a3", "a4", "a5", "fp", "sp", "ps", "pc"};
68 /* Define accessors for 68K's 1, 2, and 4-byte signed quantities.
69 The _SHIFT values move the quantity to the high order end of an
70 `int' value, so it will sign-extend. Probably a few more casts
71 are needed to make it compile without warnings on finicky systems. */
72 #define BITS_PER_BYTE 8
73 #define WORD_SHIFT (BITS_PER_BYTE * ((sizeof (int)) - 2))
74 #define LONG_SHIFT (BITS_PER_BYTE * ((sizeof (int)) - 4))
76 #define NEXTBYTE(p) (p += 2, FETCH_DATA (info, p), COERCE_SIGNED_CHAR(p[-1]))
79 (p += 2, FETCH_DATA (info, p), \
80 (((int)((p[-2] << 8) + p[-1])) << WORD_SHIFT) >> WORD_SHIFT)
83 (p += 4, FETCH_DATA (info, p), \
84 (((int)((((((p[-4] << 8) + p[-3]) << 8) + p[-2]) << 8) + p[-1])) \
85 << LONG_SHIFT) >> LONG_SHIFT)
87 /* NEXTSINGLE and NEXTDOUBLE handle alignment problems, but not
88 * byte-swapping or other float format differences. FIXME! */
96 #define NEXTSINGLE(val, p) \
97 { int i; union number u;\
98 FETCH_DATA (info, p + sizeof (float));\
99 for (i = 0; i < sizeof(float); i++) u.c[i] = *p++; \
102 #define NEXTDOUBLE(val, p) \
103 { int i; union number u;\
104 FETCH_DATA (info, p + sizeof (double));\
105 for (i = 0; i < sizeof(double); i++) u.c[i] = *p++; \
108 /* Need a function to convert from extended to double precision... */
109 #define NEXTEXTEND(p) \
110 (p += 12, FETCH_DATA (info, p), 0.0)
112 /* Need a function to convert from packed to double
113 precision. Actually, it's easier to print a
114 packed number than a double anyway, so maybe
115 there should be a special case to handle this... */
116 #define NEXTPACKED(p) \
117 (p += 12, FETCH_DATA (info, p), 0.0)
120 /* Maximum length of an instruction. */
127 /* Points to first byte not fetched. */
128 bfd_byte
*max_fetched
;
129 bfd_byte the_buffer
[MAXLEN
];
134 /* Make sure that bytes from INFO->PRIVATE_DATA->BUFFER (inclusive)
135 to ADDR (exclusive) are valid. Returns 1 for success, longjmps
137 #define FETCH_DATA(info, addr) \
138 ((addr) <= ((struct private *)(info->private_data))->max_fetched \
139 ? 1 : fetch_data ((info), (addr)))
142 fetch_data (info
, addr
)
143 struct disassemble_info
*info
;
147 struct private *priv
= (struct private *)info
->private_data
;
148 bfd_vma start
= priv
->insn_start
+ (priv
->max_fetched
- priv
->the_buffer
);
150 status
= (*info
->read_memory_func
) (start
,
152 addr
- priv
->max_fetched
,
156 (*info
->memory_error_func
) (status
, start
, info
);
157 longjmp (priv
->bailout
, 1);
160 priv
->max_fetched
= addr
;
165 m68k_opcode_error(info
, code
, place
)
166 struct disassemble_info
*info
;
169 (*info
->fprintf_func
)(info
->stream
,
170 "<internal error in opcode table: \"%c%c\">",
174 /* Print the m68k instruction at address MEMADDR in debugged memory,
175 on STREAM. Returns length of the instruction, in bytes. */
178 print_insn_m68k (memaddr
, info
)
180 disassemble_info
*info
;
183 register unsigned char *p
;
185 register unsigned long bestmask
;
188 bfd_byte
*buffer
= priv
.the_buffer
;
190 info
->private_data
= (PTR
) &priv
;
191 priv
.max_fetched
= priv
.the_buffer
;
192 priv
.insn_start
= memaddr
;
193 if (setjmp (priv
.bailout
) != 0)
199 FETCH_DATA (info
, buffer
+ 2);
200 for (i
= 0; i
< numopcodes
; i
++)
202 register unsigned long opcode
= m68k_opcodes
[i
].opcode
;
203 register unsigned long match
= m68k_opcodes
[i
].match
;
204 if (((0xff & buffer
[0] & (match
>> 24)) == (0xff & (opcode
>> 24)))
205 && ((0xff & buffer
[1] & (match
>> 16)) == (0xff & (opcode
>> 16)))
206 /* Only fetch the next two bytes if we need to. */
207 && (((0xffff & match
) == 0)
209 (FETCH_DATA (info
, buffer
+ 4)
210 && ((0xff & buffer
[2] & (match
>> 8)) == (0xff & (opcode
>> 8)))
211 && ((0xff & buffer
[3] & match
) == (0xff & opcode
)))
214 /* Don't use for printout the variants of divul and divsl
215 that have the same register number in two places.
216 The more general variants will match instead. */
217 for (d
= m68k_opcodes
[i
].args
; *d
; d
+= 2)
221 /* Don't use for printout the variants of most floating
222 point coprocessor instructions which use the same
223 register number in two places, as above. */
225 for (d
= m68k_opcodes
[i
].args
; *d
; d
+= 2)
229 if (*d
== 0 && match
> bestmask
)
237 /* Handle undefined instructions. */
240 (*info
->fprintf_func
) (info
->stream
, "0%o",
241 (buffer
[0] << 8) + buffer
[1]);
245 (*info
->fprintf_func
) (info
->stream
, "%s", m68k_opcodes
[best
].name
);
247 /* Point at first word of argument data,
248 and at descriptor for first argument. */
251 /* Figure out how long the fixed-size portion of the instruction is.
252 The only place this is stored in the opcode table is
253 in the arguments--look for arguments which specify fields in the 2nd
254 or 3rd words of the instruction. */
255 for (d
= m68k_opcodes
[best
].args
; *d
; d
+= 2)
257 /* I don't think it is necessary to be checking d[0] here; I suspect
258 all this could be moved to the case statement below. */
261 if (d
[1] == 'l' && p
- buffer
< 6)
263 else if (p
- buffer
< 4 && d
[1] != 'C' && d
[1] != '8' )
266 if ((d
[0] == 'L' || d
[0] == 'l') && d
[1] == 'w' && p
- buffer
< 4)
289 /* pflusha is an exception; it takes no arguments but is two words long. */
290 if (buffer
[0] == 0xf0 && buffer
[1] == 0 && buffer
[2] == 0x24 &&
294 FETCH_DATA (info
, p
);
296 d
= m68k_opcodes
[best
].args
;
299 (*info
->fprintf_func
) (info
->stream
, " ");
303 p
= print_insn_arg (d
, buffer
, p
, memaddr
+ p
- buffer
, info
);
305 if (*d
&& *(d
- 2) != 'I' && *d
!= 'k')
306 (*info
->fprintf_func
) (info
->stream
, ",");
311 static unsigned char *
312 print_insn_arg (d
, buffer
, p
, addr
, info
)
314 unsigned char *buffer
;
315 register unsigned char *p
;
316 bfd_vma addr
; /* PC for this arg to be relative to */
317 disassemble_info
*info
;
319 register int val
= 0;
320 register int place
= d
[1];
322 register CONST
char *regname
;
323 register unsigned char *p1
;
329 case 'c': /* cache identifier */
331 static char *cacheFieldName
[] = { "NOP", "dc", "ic", "bc" };
332 val
= fetch_arg (buffer
, place
, 2, info
);
333 (*info
->fprintf_func
) (info
->stream
, cacheFieldName
[val
]);
337 case 'a': /* address register indirect only. Cf. case '+'. */
339 (*info
->fprintf_func
)
342 reg_names
[fetch_arg (buffer
, place
, 3, info
) + 8]);
346 case '_': /* 32-bit absolute address for move16. */
349 (*info
->fprintf_func
) (info
->stream
, "@#");
350 (*info
->print_address_func
) (val
, info
);
355 (*info
->fprintf_func
) (info
->stream
, "ccr");
359 (*info
->fprintf_func
) (info
->stream
, "sr");
363 (*info
->fprintf_func
) (info
->stream
, "usp");
368 static struct { char *name
; int value
; } names
[]
369 = {{"sfc", 0x000}, {"dfc", 0x001}, {"cacr", 0x002},
370 {"tc", 0x003}, {"itt0",0x004}, {"itt1", 0x005},
371 {"dtt0",0x006}, {"dtt1",0x007},
372 {"usp", 0x800}, {"vbr", 0x801}, {"caar", 0x802},
373 {"msp", 0x803}, {"isp", 0x804},
375 /* Should we be calling this psr like we do in case 'Y'? */
378 {"urp", 0x806}, {"srp", 0x807}};
380 val
= fetch_arg (buffer
, place
, 12, info
);
381 for (regno
= sizeof names
/ sizeof names
[0] - 1; regno
>= 0; regno
--)
382 if (names
[regno
].value
== val
)
384 (*info
->fprintf_func
) (info
->stream
, names
[regno
].name
);
388 (*info
->fprintf_func
) (info
->stream
, "%d", val
);
393 val
= fetch_arg (buffer
, place
, 3, info
);
394 /* 0 means 8, except for the bkpt instruction... */
395 if (val
== 0 && d
[1] != 's')
397 (*info
->fprintf_func
) (info
->stream
, "#%d", val
);
401 val
= fetch_arg (buffer
, place
, 8, info
);
404 (*info
->fprintf_func
) (info
->stream
, "#%d", val
);
408 val
= fetch_arg (buffer
, place
, 4, info
);
409 (*info
->fprintf_func
) (info
->stream
, "#%d", val
);
413 (*info
->fprintf_func
) (info
->stream
, "%s",
414 reg_names
[fetch_arg (buffer
, place
, 3, info
)]);
418 (*info
->fprintf_func
)
420 reg_names
[fetch_arg (buffer
, place
, 3, info
) + 010]);
424 (*info
->fprintf_func
)
426 reg_names
[fetch_arg (buffer
, place
, 4, info
)]);
430 (*info
->fprintf_func
)
431 (info
->stream
, "%s@",
432 reg_names
[fetch_arg (buffer
, place
, 4, info
)]);
436 (*info
->fprintf_func
)
437 (info
->stream
, "fp%d",
438 fetch_arg (buffer
, place
, 3, info
));
442 val
= fetch_arg (buffer
, place
, 6, info
);
444 (*info
->fprintf_func
) (info
->stream
, "%s", reg_names
[val
& 7]);
446 (*info
->fprintf_func
) (info
->stream
, "%d", val
);
450 (*info
->fprintf_func
)
451 (info
->stream
, "%s@+",
452 reg_names
[fetch_arg (buffer
, place
, 3, info
) + 8]);
456 (*info
->fprintf_func
)
457 (info
->stream
, "%s@-",
458 reg_names
[fetch_arg (buffer
, place
, 3, info
) + 8]);
463 (*info
->fprintf_func
)
464 (info
->stream
, "{%s}",
465 reg_names
[fetch_arg (buffer
, place
, 3, info
)]);
466 else if (place
== 'C')
468 val
= fetch_arg (buffer
, place
, 7, info
);
469 if ( val
> 63 ) /* This is a signed constant. */
471 (*info
->fprintf_func
) (info
->stream
, "{#%d}", val
);
474 m68k_opcode_error (info
, *d
, place
);
479 p1
= buffer
+ (*d
== '#' ? 2 : 4);
481 val
= fetch_arg (buffer
, place
, 4, info
);
482 else if (place
== 'C')
483 val
= fetch_arg (buffer
, place
, 7, info
);
484 else if (place
== '8')
485 val
= fetch_arg (buffer
, place
, 3, info
);
486 else if (place
== '3')
487 val
= fetch_arg (buffer
, place
, 8, info
);
488 else if (place
== 'b')
490 else if (place
== 'w')
492 else if (place
== 'l')
495 m68k_opcode_error (info
, *d
, place
);
496 (*info
->fprintf_func
) (info
->stream
, "#%d", val
);
502 else if (place
== 'B')
503 val
= COERCE_SIGNED_CHAR(buffer
[1]);
504 else if (place
== 'w' || place
== 'W')
506 else if (place
== 'l' || place
== 'L')
508 else if (place
== 'g')
510 val
= NEXTBYTE (buffer
);
516 else if (place
== 'c')
518 if (buffer
[1] & 0x40) /* If bit six is one, long offset */
524 m68k_opcode_error (info
, *d
, place
);
526 (*info
->print_address_func
) (addr
+ val
, info
);
531 (*info
->fprintf_func
)
532 (info
->stream
, "%s@(%d)",
533 reg_names
[fetch_arg (buffer
, place
, 3, info
)], val
);
537 (*info
->fprintf_func
) (info
->stream
, "%s",
538 fpcr_names
[fetch_arg (buffer
, place
, 3, info
)]);
542 /* Get coprocessor ID... */
543 val
= fetch_arg (buffer
, 'd', 3, info
);
545 if (val
!= 1) /* Unusual coprocessor ID? */
546 (*info
->fprintf_func
) (info
->stream
, "(cpid=%d) ", val
);
548 p
+= 2; /* Skip coprocessor extended operands */
566 val
= fetch_arg (buffer
, 'x', 6, info
);
567 val
= ((val
& 7) << 3) + ((val
>> 3) & 7);
570 val
= fetch_arg (buffer
, 's', 6, info
);
572 /* Get register number assuming address register. */
573 regno
= (val
& 7) + 8;
574 regname
= reg_names
[regno
];
578 (*info
->fprintf_func
) (info
->stream
, "%s", reg_names
[val
]);
582 (*info
->fprintf_func
) (info
->stream
, "%s", regname
);
586 (*info
->fprintf_func
) (info
->stream
, "%s@", regname
);
590 (*info
->fprintf_func
) (info
->stream
, "%s@+", regname
);
594 (*info
->fprintf_func
) (info
->stream
, "%s@-", regname
);
599 (*info
->fprintf_func
) (info
->stream
, "%s@(%d)", regname
, val
);
603 p
= print_indexed (regno
, p
, addr
, info
);
611 (*info
->fprintf_func
) (info
->stream
, "@#");
612 (*info
->print_address_func
) (val
, info
);
617 (*info
->fprintf_func
) (info
->stream
, "@#");
618 (*info
->print_address_func
) (val
, info
);
623 (*info
->print_address_func
) (addr
+ val
, info
);
627 p
= print_indexed (-1, p
, addr
, info
);
631 flt_p
= 1; /* Assume it's a float... */
650 NEXTSINGLE(flval
, p
);
654 NEXTDOUBLE(flval
, p
);
658 ieee_extended_to_double (&ext_format_68881
,
664 flval
= NEXTPACKED(p
);
668 m68k_opcode_error (info
, *d
, place
);
670 if ( flt_p
) /* Print a float? */
671 (*info
->fprintf_func
) (info
->stream
, "#%g", flval
);
673 (*info
->fprintf_func
) (info
->stream
, "#%d", val
);
677 (*info
->fprintf_func
) (info
->stream
,
678 "<invalid address mode 0%o>",
691 /* Move the pointer ahead if this point is farther ahead
696 (*info
->fprintf_func
) (info
->stream
, "#0");
701 register int newval
= 0;
702 for (regno
= 0; regno
< 16; ++regno
)
703 if (val
& (0x8000 >> regno
))
704 newval
|= 1 << regno
;
709 for (regno
= 0; regno
< 16; ++regno
)
710 if (val
& (1 << regno
))
714 (*info
->fprintf_func
) (info
->stream
, "/");
716 (*info
->fprintf_func
) (info
->stream
, "%s", reg_names
[regno
]);
718 while (val
& (1 << (regno
+ 1)))
720 if (regno
> first_regno
)
721 (*info
->fprintf_func
) (info
->stream
, "-%s",
725 else if (place
== '3')
729 val
= fetch_arg (buffer
, place
, 8, info
);
732 (*info
->fprintf_func
) (info
->stream
, "#0");
737 register int newval
= 0;
738 for (regno
= 0; regno
< 8; ++regno
)
739 if (val
& (0x80 >> regno
))
740 newval
|= 1 << regno
;
745 for (regno
= 0; regno
< 8; ++regno
)
746 if (val
& (1 << regno
))
750 (*info
->fprintf_func
) (info
->stream
, "/");
752 (*info
->fprintf_func
) (info
->stream
, "fp%d", regno
);
754 while (val
& (1 << (regno
+ 1)))
756 if (regno
> first_regno
)
757 (*info
->fprintf_func
) (info
->stream
, "-fp%d", regno
);
772 int val
= fetch_arg (buffer
, place
, 5, info
);
776 case 2: name
= "tt0"; break;
777 case 3: name
= "tt1"; break;
778 case 0x10: name
= "tc"; break;
779 case 0x11: name
= "drp"; break;
780 case 0x12: name
= "srp"; break;
781 case 0x13: name
= "crp"; break;
782 case 0x14: name
= "cal"; break;
783 case 0x15: name
= "val"; break;
784 case 0x16: name
= "scc"; break;
785 case 0x17: name
= "ac"; break;
786 case 0x18: name
= "psr"; break;
787 case 0x19: name
= "pcsr"; break;
791 int break_reg
= ((buffer
[3] >> 2) & 7);
792 (*info
->fprintf_func
)
793 (info
->stream
, val
== 0x1c ? "bad%d" : "bac%d",
798 (*info
->fprintf_func
) (info
->stream
, "<mmu register %d>", val
);
801 (*info
->fprintf_func
) (info
->stream
, name
);
807 int fc
= fetch_arg (buffer
, place
, 5, info
);
809 (*info
->fprintf_func
) (info
->stream
, "dfc");
811 (*info
->fprintf_func
) (info
->stream
, "sfc");
813 (*info
->fprintf_func
) (info
->stream
, "<function code %d>", fc
);
818 (*info
->fprintf_func
) (info
->stream
, "val");
823 int level
= fetch_arg (buffer
, place
, 3, info
);
824 (*info
->fprintf_func
) (info
->stream
, "%d", level
);
829 m68k_opcode_error (info
, *d
, ' ');
832 return (unsigned char *) p
;
835 /* Fetch BITS bits from a position in the instruction specified by CODE.
836 CODE is a "place to put an argument", or 'x' for a destination
837 that is a general address (mode and register).
838 BUFFER contains the instruction. */
841 fetch_arg (buffer
, code
, bits
, info
)
842 unsigned char *buffer
;
845 disassemble_info
*info
;
847 register int val
= 0;
854 case 'd': /* Destination, for register or quick. */
855 val
= (buffer
[0] << 8) + buffer
[1];
859 case 'x': /* Destination, for general arg */
860 val
= (buffer
[0] << 8) + buffer
[1];
865 FETCH_DATA (info
, buffer
+ 3);
866 val
= (buffer
[3] >> 4);
870 FETCH_DATA (info
, buffer
+ 3);
875 FETCH_DATA (info
, buffer
+ 3);
876 val
= (buffer
[2] << 8) + buffer
[3];
881 FETCH_DATA (info
, buffer
+ 3);
882 val
= (buffer
[2] << 8) + buffer
[3];
888 FETCH_DATA (info
, buffer
+ 3);
889 val
= (buffer
[2] << 8) + buffer
[3];
893 FETCH_DATA (info
, buffer
+ 5);
894 val
= (buffer
[4] << 8) + buffer
[5];
899 FETCH_DATA (info
, buffer
+ 5);
900 val
= (buffer
[4] << 8) + buffer
[5];
905 FETCH_DATA (info
, buffer
+ 5);
906 val
= (buffer
[4] << 8) + buffer
[5];
910 FETCH_DATA (info
, buffer
+ 3);
911 val
= (buffer
[2] << 8) + buffer
[3];
916 FETCH_DATA (info
, buffer
+ 3);
917 val
= (buffer
[2] << 8) + buffer
[3];
922 FETCH_DATA (info
, buffer
+ 3);
923 val
= (buffer
[2] << 8) + buffer
[3];
928 val
= (buffer
[1] >> 6);
958 /* Print an indexed argument. The base register is BASEREG (-1 for pc).
959 P points to extension word, in buffer.
960 ADDR is the nominal core address of that extension word. */
962 static unsigned char *
963 print_indexed (basereg
, p
, addr
, info
)
967 disassemble_info
*info
;
970 static char *scales
[] = {"", "*2", "*4", "*8"};
971 register int base_disp
;
972 register int outer_disp
;
977 /* Generate the text for the index register.
978 Where this will be output is not yet determined. */
979 sprintf (buf
, "[%s.%c%s]",
980 reg_names
[(word
>> 12) & 0xf],
981 (word
& 0x800) ? 'l' : 'w',
982 scales
[(word
>> 9) & 3]);
984 /* Handle the 68000 style of indexing. */
986 if ((word
& 0x100) == 0)
989 ((word
& 0x80) ? word
| 0xff00 : word
& 0xff)
990 + ((basereg
== -1) ? addr
: 0),
992 (*info
->fprintf_func
) (info
->stream
, "%s", buf
);
996 /* Handle the generalized kind. */
997 /* First, compute the displacement to add to the base register. */
1004 switch ((word
>> 4) & 3)
1007 base_disp
= NEXTWORD (p
);
1010 base_disp
= NEXTLONG (p
);
1015 /* Handle single-level case (not indirect) */
1017 if ((word
& 7) == 0)
1019 print_base (basereg
, base_disp
, info
);
1020 (*info
->fprintf_func
) (info
->stream
, "%s", buf
);
1024 /* Two level. Compute displacement to add after indirection. */
1030 outer_disp
= NEXTWORD (p
);
1033 outer_disp
= NEXTLONG (p
);
1036 (*info
->fprintf_func
) (info
->stream
, "%d(", outer_disp
);
1037 print_base (basereg
, base_disp
, info
);
1039 /* If postindexed, print the closeparen before the index. */
1041 (*info
->fprintf_func
) (info
->stream
, ")%s", buf
);
1042 /* If preindexed, print the closeparen after the index. */
1044 (*info
->fprintf_func
) (info
->stream
, "%s)", buf
);
1049 /* Print a base register REGNO and displacement DISP, on INFO->STREAM.
1050 REGNO = -1 for pc, -2 for none (suppressed). */
1053 print_base (regno
, disp
, info
)
1056 disassemble_info
*info
;
1059 (*info
->fprintf_func
) (info
->stream
, "%d", disp
);
1060 else if (regno
== -1)
1061 (*info
->fprintf_func
) (info
->stream
, "0x%x", (unsigned) disp
);
1063 (*info
->fprintf_func
) (info
->stream
, "%d(%s)", disp
, reg_names
[regno
]);