1 /* Print Motorola 68k instructions.
2 Copyright (C) 1986-2017 Free Software Foundation, Inc.
4 This file is part of the GNU opcodes library.
6 This library is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3, or (at your option)
11 It is distributed in the hope that it will be useful, but WITHOUT
12 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
13 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
14 License for more details.
16 You should have received a copy of the GNU General Public License
17 along with this program; if not, write to the Free Software
18 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
19 MA 02110-1301, USA. */
23 #include "floatformat.h"
24 #include "libiberty.h"
27 #include "opcode/m68k.h"
29 /* Local function prototypes. */
31 const char * const fpcr_names
[] =
33 "", "%fpiar", "%fpsr", "%fpiar/%fpsr", "%fpcr",
34 "%fpiar/%fpcr", "%fpsr/%fpcr", "%fpiar/%fpsr/%fpcr"
37 static char *const reg_names
[] =
39 "%d0", "%d1", "%d2", "%d3", "%d4", "%d5", "%d6", "%d7",
40 "%a0", "%a1", "%a2", "%a3", "%a4", "%a5", "%fp", "%sp",
44 /* Name of register halves for MAC/EMAC.
45 Seperate from reg_names since 'spu', 'fpl' look weird. */
46 static char *const reg_half_names
[] =
48 "%d0", "%d1", "%d2", "%d3", "%d4", "%d5", "%d6", "%d7",
49 "%a0", "%a1", "%a2", "%a3", "%a4", "%a5", "%a6", "%a7",
53 /* Sign-extend an (unsigned char). */
55 #define COERCE_SIGNED_CHAR(ch) ((signed char) (ch))
57 #define COERCE_SIGNED_CHAR(ch) ((int) (((ch) ^ 0x80) & 0xFF) - 128)
60 /* Error code of print_insn_arg's return value. */
62 enum print_insn_arg_error
64 /* An invalid operand is found. */
65 PRINT_INSN_ARG_INVALID_OPERAND
= -1,
67 /* An opcode table error. */
68 PRINT_INSN_ARG_INVALID_OP_TABLE
= -2,
71 PRINT_INSN_ARG_MEMORY_ERROR
= -3,
74 /* Get a 1 byte signed integer. */
75 #define NEXTBYTE(p, val) \
79 if (!FETCH_DATA (info, p)) \
80 return PRINT_INSN_ARG_MEMORY_ERROR; \
81 val = COERCE_SIGNED_CHAR (p[-1]); \
85 /* Get a 2 byte signed integer. */
86 #define COERCE16(x) ((int) (((x) ^ 0x8000) - 0x8000))
88 #define NEXTWORD(p, val, ret_val) \
92 if (!FETCH_DATA (info, p)) \
94 val = COERCE16 ((p[-2] << 8) + p[-1]); \
98 /* Get a 4 byte signed integer. */
99 #define COERCE32(x) ((bfd_signed_vma) ((x) ^ 0x80000000) - 0x80000000)
101 #define NEXTLONG(p, val, ret_val) \
105 if (!FETCH_DATA (info, p)) \
107 val = COERCE32 ((((((p[-4] << 8) + p[-3]) << 8) + p[-2]) << 8) + p[-1]); \
111 /* Get a 4 byte unsigned integer. */
112 #define NEXTULONG(p, val) \
116 if (!FETCH_DATA (info, p)) \
117 return PRINT_INSN_ARG_MEMORY_ERROR; \
118 val = (unsigned int) ((((((p[-4] << 8) + p[-3]) << 8) + p[-2]) << 8) + p[-1]); \
122 /* Get a single precision float. */
123 #define NEXTSINGLE(val, p) \
127 if (!FETCH_DATA (info, p)) \
128 return PRINT_INSN_ARG_MEMORY_ERROR; \
129 floatformat_to_double (& floatformat_ieee_single_big, \
130 (char *) p - 4, & val); \
134 /* Get a double precision float. */
135 #define NEXTDOUBLE(val, p) \
139 if (!FETCH_DATA (info, p)) \
140 return PRINT_INSN_ARG_MEMORY_ERROR; \
141 floatformat_to_double (& floatformat_ieee_double_big, \
142 (char *) p - 8, & val); \
146 /* Get an extended precision float. */
147 #define NEXTEXTEND(val, p) \
151 if (!FETCH_DATA (info, p)) \
152 return PRINT_INSN_ARG_MEMORY_ERROR; \
153 floatformat_to_double (& floatformat_m68881_ext, \
154 (char *) p - 12, & val); \
158 /* Need a function to convert from packed to double
159 precision. Actually, it's easier to print a
160 packed number than a double anyway, so maybe
161 there should be a special case to handle this... */
162 #define NEXTPACKED(p, val) \
166 if (!FETCH_DATA (info, p)) \
167 return PRINT_INSN_ARG_MEMORY_ERROR; \
173 /* Maximum length of an instruction. */
178 /* Points to first byte not fetched. */
179 bfd_byte
*max_fetched
;
180 bfd_byte the_buffer
[MAXLEN
];
184 /* Make sure that bytes from INFO->PRIVATE_DATA->BUFFER (inclusive)
185 to ADDR (exclusive) are valid. Returns 1 for success, 0 on memory
187 #define FETCH_DATA(info, addr) \
188 ((addr) <= ((struct private *) (info->private_data))->max_fetched \
189 ? 1 : fetch_data ((info), (addr)))
192 fetch_data (struct disassemble_info
*info
, bfd_byte
*addr
)
195 struct private *priv
= (struct private *)info
->private_data
;
196 bfd_vma start
= priv
->insn_start
+ (priv
->max_fetched
- priv
->the_buffer
);
198 status
= (*info
->read_memory_func
) (start
,
200 addr
- priv
->max_fetched
,
204 (*info
->memory_error_func
) (status
, start
, info
);
208 priv
->max_fetched
= addr
;
212 /* This function is used to print to the bit-bucket. */
214 dummy_printer (FILE *file ATTRIBUTE_UNUSED
,
215 const char *format ATTRIBUTE_UNUSED
,
222 dummy_print_address (bfd_vma vma ATTRIBUTE_UNUSED
,
223 struct disassemble_info
*info ATTRIBUTE_UNUSED
)
227 /* Fetch BITS bits from a position in the instruction specified by CODE.
228 CODE is a "place to put an argument", or 'x' for a destination
229 that is a general address (mode and register).
230 BUFFER contains the instruction.
231 Returns -1 on failure. */
234 fetch_arg (unsigned char *buffer
,
237 disassemble_info
*info
)
243 case '/': /* MAC/EMAC mask bit. */
244 val
= buffer
[3] >> 5;
247 case 'G': /* EMAC ACC load. */
248 val
= ((buffer
[3] >> 3) & 0x2) | ((~buffer
[1] >> 7) & 0x1);
251 case 'H': /* EMAC ACC !load. */
252 val
= ((buffer
[3] >> 3) & 0x2) | ((buffer
[1] >> 7) & 0x1);
255 case ']': /* EMAC ACCEXT bit. */
256 val
= buffer
[0] >> 2;
259 case 'I': /* MAC/EMAC scale factor. */
260 val
= buffer
[2] >> 1;
263 case 'F': /* EMAC ACCx. */
264 val
= buffer
[0] >> 1;
275 case 'd': /* Destination, for register or quick. */
276 val
= (buffer
[0] << 8) + buffer
[1];
280 case 'x': /* Destination, for general arg. */
281 val
= (buffer
[0] << 8) + buffer
[1];
286 if (! FETCH_DATA (info
, buffer
+ 3))
288 val
= (buffer
[3] >> 4);
292 if (! FETCH_DATA (info
, buffer
+ 3))
298 if (! FETCH_DATA (info
, buffer
+ 3))
300 val
= (buffer
[2] << 8) + buffer
[3];
305 if (! FETCH_DATA (info
, buffer
+ 3))
307 val
= (buffer
[2] << 8) + buffer
[3];
313 if (! FETCH_DATA (info
, buffer
+ 3))
315 val
= (buffer
[2] << 8) + buffer
[3];
319 if (! FETCH_DATA (info
, buffer
+ 5))
321 val
= (buffer
[4] << 8) + buffer
[5];
326 if (! FETCH_DATA (info
, buffer
+ 5))
328 val
= (buffer
[4] << 8) + buffer
[5];
333 if (! FETCH_DATA (info
, buffer
+ 5))
335 val
= (buffer
[4] << 8) + buffer
[5];
339 if (! FETCH_DATA (info
, buffer
+ 3))
341 val
= (buffer
[2] << 8) + buffer
[3];
346 if (! FETCH_DATA (info
, buffer
+ 3))
348 val
= (buffer
[2] << 8) + buffer
[3];
353 if (! FETCH_DATA (info
, buffer
+ 3))
355 val
= (buffer
[2] << 8) + buffer
[3];
360 val
= (buffer
[1] >> 6);
364 if (! FETCH_DATA (info
, buffer
+ 3))
366 val
= (buffer
[2] >> 1);
370 val
= (buffer
[1] & 0x40 ? 0x8 : 0)
371 | ((buffer
[0] >> 1) & 0x7)
372 | (buffer
[3] & 0x80 ? 0x10 : 0);
376 val
= (buffer
[1] & 0x40 ? 0x8 : 0) | ((buffer
[0] >> 1) & 0x7);
380 val
= (buffer
[2] >> 4) | (buffer
[3] & 0x80 ? 0x10 : 0);
384 val
= (buffer
[1] & 0xf) | (buffer
[3] & 0x40 ? 0x10 : 0);
388 val
= (buffer
[3] & 0xf) | (buffer
[3] & 0x40 ? 0x10 : 0);
392 val
= buffer
[2] >> 2;
399 /* bits is never too big. */
400 return val
& ((1 << bits
) - 1);
403 /* Check if an EA is valid for a particular code. This is required
404 for the EMAC instructions since the type of source address determines
405 if it is a EMAC-load instruciton if the EA is mode 2-5, otherwise it
406 is a non-load EMAC instruction and the bits mean register Ry.
407 A similar case exists for the movem instructions where the register
408 mask is interpreted differently for different EAs. */
411 m68k_valid_ea (char code
, int val
)
414 #define M(n0,n1,n2,n3,n4,n5,n6,n70,n71,n72,n73,n74) \
415 (n0 | n1 << 1 | n2 << 2 | n3 << 3 | n4 << 4 | n5 << 5 | n6 << 6 \
416 | n70 << 7 | n71 << 8 | n72 << 9 | n73 << 10 | n74 << 11)
421 mask
= M (1,1,1,1,1,1,1,1,1,1,1,1);
424 mask
= M (0,0,1,1,1,1,1,1,1,0,0,0);
427 mask
= M (1,1,1,1,1,1,1,1,1,0,0,0);
430 mask
= M (1,0,1,1,1,1,1,1,1,1,1,1);
433 mask
= M (1,0,1,1,1,1,1,1,1,1,1,0);
436 mask
= M (0,0,1,0,0,1,1,1,1,1,1,0);
439 mask
= M (0,0,1,0,0,1,1,1,1,0,0,0);
442 mask
= M (1,0,1,1,1,1,1,1,1,0,0,0);
445 mask
= M (1,0,1,0,0,1,1,1,1,0,0,0);
448 mask
= M (1,0,1,0,0,1,1,1,1,1,1,0);
451 mask
= M (0,0,1,0,0,1,1,1,1,1,1,0);
454 mask
= M (0,0,1,0,1,1,1,1,1,0,0,0);
457 mask
= M (0,0,1,1,0,1,1,1,1,1,1,0);
460 mask
= M (1,1,1,1,1,0,0,0,0,0,0,0);
463 mask
= M (0,0,0,0,0,1,0,0,0,1,0,0);
466 mask
= M (0,0,0,0,0,0,1,1,1,0,1,1);
469 mask
= M (1,1,1,1,1,1,0,0,0,0,0,0);
472 mask
= M (1,0,1,1,1,1,0,0,0,0,0,0);
475 mask
= M (1,0,1,1,1,1,0,1,1,0,0,0);
478 mask
= M (1,0,1,1,1,1,0,0,0,1,0,0);
481 mask
= M (0,0,1,1,1,1,0,0,0,1,0,0);
484 mask
= M (0,0,1,0,0,1,0,0,0,0,0,0);
487 mask
= M (0,0,1,0,0,1,0,0,0,1,0,0);
490 mask
= M (0,0,1,1,1,1,0,0,0,0,0,0);
497 mode
= (val
>> 3) & 7;
500 return (mask
& (1 << mode
)) != 0;
503 /* Print a base register REGNO and displacement DISP, on INFO->STREAM.
504 REGNO = -1 for pc, -2 for none (suppressed). */
507 print_base (int regno
, bfd_vma disp
, disassemble_info
*info
)
511 (*info
->fprintf_func
) (info
->stream
, "%%pc@(");
512 (*info
->print_address_func
) (disp
, info
);
519 (*info
->fprintf_func
) (info
->stream
, "@(");
520 else if (regno
== -3)
521 (*info
->fprintf_func
) (info
->stream
, "%%zpc@(");
523 (*info
->fprintf_func
) (info
->stream
, "%s@(", reg_names
[regno
]);
525 sprintf_vma (buf
, disp
);
526 (*info
->fprintf_func
) (info
->stream
, "%s", buf
);
530 /* Print an indexed argument. The base register is BASEREG (-1 for pc).
531 P points to extension word, in buffer.
532 ADDR is the nominal core address of that extension word.
533 Returns NULL upon error. */
535 static unsigned char *
536 print_indexed (int basereg
,
539 disassemble_info
*info
)
542 static char *const scales
[] = { "", ":2", ":4", ":8" };
548 NEXTWORD (p
, word
, NULL
);
550 /* Generate the text for the index register.
551 Where this will be output is not yet determined. */
552 sprintf (buf
, "%s:%c%s",
553 reg_names
[(word
>> 12) & 0xf],
554 (word
& 0x800) ? 'l' : 'w',
555 scales
[(word
>> 9) & 3]);
557 /* Handle the 68000 style of indexing. */
559 if ((word
& 0x100) == 0)
561 base_disp
= word
& 0xff;
562 if ((base_disp
& 0x80) != 0)
566 print_base (basereg
, base_disp
, info
);
567 (*info
->fprintf_func
) (info
->stream
, ",%s)", buf
);
571 /* Handle the generalized kind. */
572 /* First, compute the displacement to add to the base register. */
583 switch ((word
>> 4) & 3)
586 NEXTWORD (p
, base_disp
, NULL
);
589 NEXTLONG (p
, base_disp
, NULL
);
594 /* Handle single-level case (not indirect). */
597 print_base (basereg
, base_disp
, info
);
599 (*info
->fprintf_func
) (info
->stream
, ",%s", buf
);
600 (*info
->fprintf_func
) (info
->stream
, ")");
604 /* Two level. Compute displacement to add after indirection. */
609 NEXTWORD (p
, outer_disp
, NULL
);
612 NEXTLONG (p
, outer_disp
, NULL
);
615 print_base (basereg
, base_disp
, info
);
616 if ((word
& 4) == 0 && buf
[0] != '\0')
618 (*info
->fprintf_func
) (info
->stream
, ",%s", buf
);
621 sprintf_vma (vmabuf
, outer_disp
);
622 (*info
->fprintf_func
) (info
->stream
, ")@(%s", vmabuf
);
624 (*info
->fprintf_func
) (info
->stream
, ",%s", buf
);
625 (*info
->fprintf_func
) (info
->stream
, ")");
630 #define FETCH_ARG(size, val) \
633 val = fetch_arg (buffer, place, size, info); \
635 return PRINT_INSN_ARG_MEMORY_ERROR; \
639 /* Returns number of bytes "eaten" by the operand, or
640 return enum print_insn_arg_error. ADDR is the pc for this arg to be
644 print_insn_arg (const char *d
,
645 unsigned char *buffer
,
648 disassemble_info
*info
)
652 unsigned char *p
= p0
;
663 case 'c': /* Cache identifier. */
665 static char *const cacheFieldName
[] = { "nc", "dc", "ic", "bc" };
667 (*info
->fprintf_func
) (info
->stream
, "%s", cacheFieldName
[val
]);
671 case 'a': /* Address register indirect only. Cf. case '+'. */
674 (*info
->fprintf_func
) (info
->stream
, "%s@", reg_names
[val
+ 8]);
678 case '_': /* 32-bit absolute address for move16. */
681 (*info
->print_address_func
) (uval
, info
);
686 (*info
->fprintf_func
) (info
->stream
, "%%ccr");
690 (*info
->fprintf_func
) (info
->stream
, "%%sr");
694 (*info
->fprintf_func
) (info
->stream
, "%%usp");
698 (*info
->fprintf_func
) (info
->stream
, "%%acc");
702 (*info
->fprintf_func
) (info
->stream
, "%%macsr");
706 (*info
->fprintf_func
) (info
->stream
, "%%mask");
711 /* FIXME: There's a problem here, different m68k processors call the
712 same address different names. The tables below try to get it right
713 using info->mach, but only for v4e. */
714 struct regname
{ char * name
; int value
; };
715 static const struct regname names
[] =
717 {"%sfc", 0x000}, {"%dfc", 0x001}, {"%cacr", 0x002},
718 {"%tc", 0x003}, {"%itt0",0x004}, {"%itt1", 0x005},
719 {"%dtt0",0x006}, {"%dtt1",0x007}, {"%buscr",0x008},
720 {"%rgpiobar", 0x009}, {"%acr4",0x00c},
721 {"%acr5",0x00d}, {"%acr6",0x00e}, {"%acr7", 0x00f},
722 {"%usp", 0x800}, {"%vbr", 0x801}, {"%caar", 0x802},
723 {"%msp", 0x803}, {"%isp", 0x804},
725 /* Reg c04 is sometimes called flashbar or rambar.
726 Reg c05 is also sometimes called rambar. */
727 {"%rambar0", 0xc04}, {"%rambar1", 0xc05},
729 /* reg c0e is sometimes called mbar2 or secmbar.
730 reg c0f is sometimes called mbar. */
731 {"%mbar0", 0xc0e}, {"%mbar1", 0xc0f},
733 /* Should we be calling this psr like we do in case 'Y'? */
736 {"%urp", 0x806}, {"%srp", 0x807}, {"%pcr", 0x808},
738 /* Fido added these. */
739 {"%cac", 0xffe}, {"%mbo", 0xfff}
741 /* Alternate names for v4e (MCF5407/5445x/MCF547x/MCF548x), at least. */
742 static const struct regname names_v4e
[] =
744 {"%asid",0x003}, {"%acr0",0x004}, {"%acr1",0x005},
745 {"%acr2",0x006}, {"%acr3",0x007}, {"%mmubar",0x008},
747 unsigned int arch_mask
;
749 arch_mask
= bfd_m68k_mach_to_features (info
->mach
);
751 if (arch_mask
& (mcfisa_b
| mcfisa_c
))
753 for (regno
= ARRAY_SIZE (names_v4e
); --regno
>= 0;)
754 if (names_v4e
[regno
].value
== val
)
756 (*info
->fprintf_func
) (info
->stream
, "%s", names_v4e
[regno
].name
);
762 for (regno
= ARRAY_SIZE (names
) - 1; regno
>= 0; regno
--)
763 if (names
[regno
].value
== val
)
765 (*info
->fprintf_func
) (info
->stream
, "%s", names
[regno
].name
);
769 (*info
->fprintf_func
) (info
->stream
, "0x%x", val
);
775 /* 0 means 8, except for the bkpt instruction... */
776 if (val
== 0 && d
[1] != 's')
778 (*info
->fprintf_func
) (info
->stream
, "#%d", val
);
786 (*info
->fprintf_func
) (info
->stream
, "#%d", val
);
791 (*info
->fprintf_func
) (info
->stream
, "#%d", val
+1);
796 (*info
->fprintf_func
) (info
->stream
, "#%d", val
);
802 static char *const scalefactor_name
[] = { "<<", ">>" };
805 (*info
->fprintf_func
) (info
->stream
, "%s", scalefactor_name
[val
]);
812 (*info
->fprintf_func
) (info
->stream
, "#%d", val
);
818 (*info
->fprintf_func
) (info
->stream
, "#%d", val
);
823 (*info
->fprintf_func
) (info
->stream
, "%s", reg_names
[val
]);
828 (*info
->fprintf_func
) (info
->stream
, "%s", reg_names
[val
+ 010]);
833 (*info
->fprintf_func
) (info
->stream
, "%s", reg_names
[val
]);
837 FETCH_ARG (4, regno
);
839 (*info
->fprintf_func
) (info
->stream
, "%s@", reg_names
[regno
]);
841 (*info
->fprintf_func
) (info
->stream
, "@(%s)", reg_names
[regno
]);
846 (*info
->fprintf_func
) (info
->stream
, "%%fp%d", val
);
852 (*info
->fprintf_func
) (info
->stream
, "%s", reg_names
[val
& 7]);
854 (*info
->fprintf_func
) (info
->stream
, "%d", val
);
859 (*info
->fprintf_func
) (info
->stream
, "%s@+", reg_names
[val
+ 8]);
864 (*info
->fprintf_func
) (info
->stream
, "%s@-", reg_names
[val
+ 8]);
871 (*info
->fprintf_func
) (info
->stream
, "{%s}", reg_names
[val
]);
873 else if (place
== 'C')
876 if (val
> 63) /* This is a signed constant. */
878 (*info
->fprintf_func
) (info
->stream
, "{#%d}", val
);
881 return PRINT_INSN_ARG_INVALID_OPERAND
;
886 p1
= buffer
+ (*d
== '#' ? 2 : 4);
889 else if (place
== 'C')
891 else if (place
== '8')
893 else if (place
== '3')
895 else if (place
== 'b')
897 else if (place
== 'w' || place
== 'W')
898 NEXTWORD (p1
, val
, PRINT_INSN_ARG_MEMORY_ERROR
);
899 else if (place
== 'l')
900 NEXTLONG (p1
, val
, PRINT_INSN_ARG_MEMORY_ERROR
);
902 return PRINT_INSN_ARG_INVALID_OP_TABLE
;
904 (*info
->fprintf_func
) (info
->stream
, "#%d", val
);
910 else if (place
== 'B')
911 disp
= COERCE_SIGNED_CHAR (buffer
[1]);
912 else if (place
== 'w' || place
== 'W')
913 NEXTWORD (p
, disp
, PRINT_INSN_ARG_MEMORY_ERROR
);
914 else if (place
== 'l' || place
== 'L' || place
== 'C')
915 NEXTLONG (p
, disp
, PRINT_INSN_ARG_MEMORY_ERROR
);
916 else if (place
== 'g')
918 NEXTBYTE (buffer
, disp
);
920 NEXTWORD (p
, disp
, PRINT_INSN_ARG_MEMORY_ERROR
);
922 NEXTLONG (p
, disp
, PRINT_INSN_ARG_MEMORY_ERROR
);
924 else if (place
== 'c')
926 if (buffer
[1] & 0x40) /* If bit six is one, long offset. */
927 NEXTLONG (p
, disp
, PRINT_INSN_ARG_MEMORY_ERROR
);
929 NEXTWORD (p
, disp
, PRINT_INSN_ARG_MEMORY_ERROR
);
932 return PRINT_INSN_ARG_INVALID_OP_TABLE
;
934 (*info
->print_address_func
) (addr
+ disp
, info
);
941 NEXTWORD (p
, val
, PRINT_INSN_ARG_MEMORY_ERROR
);
943 (*info
->fprintf_func
) (info
->stream
, "%s@(%d)", reg_names
[val1
+ 8], val
);
949 (*info
->fprintf_func
) (info
->stream
, "%s", fpcr_names
[val
]);
954 (*info
->fprintf_func
) (info
->stream
, "%%acc%d", val
);
959 (*info
->fprintf_func
) (info
->stream
, "%%accext%s", val
== 0 ? "01" : "23");
965 (*info
->fprintf_func
) (info
->stream
, "<<");
967 (*info
->fprintf_func
) (info
->stream
, ">>");
969 return PRINT_INSN_ARG_INVALID_OPERAND
;
973 /* Get coprocessor ID... */
974 val
= fetch_arg (buffer
, 'd', 3, info
);
976 return PRINT_INSN_ARG_MEMORY_ERROR
;
977 if (val
!= 1) /* Unusual coprocessor ID? */
978 (*info
->fprintf_func
) (info
->stream
, "(cpid=%d) ", val
);
1007 val
= fetch_arg (buffer
, 'x', 6, info
);
1009 return PRINT_INSN_ARG_MEMORY_ERROR
;
1010 val
= ((val
& 7) << 3) + ((val
>> 3) & 7);
1014 val
= fetch_arg (buffer
, 's', 6, info
);
1016 return PRINT_INSN_ARG_MEMORY_ERROR
;
1019 /* If the <ea> is invalid for *d, then reject this match. */
1020 if (!m68k_valid_ea (*d
, val
))
1021 return PRINT_INSN_ARG_INVALID_OPERAND
;
1023 /* Get register number assuming address register. */
1024 regno
= (val
& 7) + 8;
1025 regname
= reg_names
[regno
];
1029 (*info
->fprintf_func
) (info
->stream
, "%s", reg_names
[val
]);
1033 (*info
->fprintf_func
) (info
->stream
, "%s", regname
);
1037 (*info
->fprintf_func
) (info
->stream
, "%s@", regname
);
1041 (*info
->fprintf_func
) (info
->stream
, "%s@+", regname
);
1045 (*info
->fprintf_func
) (info
->stream
, "%s@-", regname
);
1049 NEXTWORD (p
, val
, PRINT_INSN_ARG_MEMORY_ERROR
);
1050 (*info
->fprintf_func
) (info
->stream
, "%s@(%d)", regname
, val
);
1054 p
= print_indexed (regno
, p
, addr
, info
);
1056 return PRINT_INSN_ARG_MEMORY_ERROR
;
1063 NEXTWORD (p
, val
, PRINT_INSN_ARG_MEMORY_ERROR
);
1064 (*info
->print_address_func
) (val
, info
);
1068 NEXTULONG (p
, uval
);
1069 (*info
->print_address_func
) (uval
, info
);
1073 NEXTWORD (p
, val
, PRINT_INSN_ARG_MEMORY_ERROR
);
1074 (*info
->fprintf_func
) (info
->stream
, "%%pc@(");
1075 (*info
->print_address_func
) (addr
+ val
, info
);
1076 (*info
->fprintf_func
) (info
->stream
, ")");
1080 p
= print_indexed (-1, p
, addr
, info
);
1082 return PRINT_INSN_ARG_MEMORY_ERROR
;
1086 flt_p
= 1; /* Assume it's a float... */
1095 NEXTWORD (p
, val
, PRINT_INSN_ARG_MEMORY_ERROR
);
1100 NEXTLONG (p
, val
, PRINT_INSN_ARG_MEMORY_ERROR
);
1105 NEXTSINGLE (flval
, p
);
1109 NEXTDOUBLE (flval
, p
);
1113 NEXTEXTEND (flval
, p
);
1117 NEXTPACKED (p
, flval
);
1121 return PRINT_INSN_ARG_INVALID_OPERAND
;
1123 if (flt_p
) /* Print a float? */
1124 (*info
->fprintf_func
) (info
->stream
, "#0e%g", flval
);
1126 (*info
->fprintf_func
) (info
->stream
, "#%d", val
);
1130 return PRINT_INSN_ARG_INVALID_OPERAND
;
1134 /* If place is '/', then this is the case of the mask bit for
1135 mac/emac loads. Now that the arg has been printed, grab the
1136 mask bit and if set, add a '&' to the arg. */
1141 info
->fprintf_func (info
->stream
, "&");
1151 NEXTWORD (p1
, val
, PRINT_INSN_ARG_MEMORY_ERROR
);
1152 /* Move the pointer ahead if this point is farther ahead
1154 p
= p1
> p
? p1
: p
;
1157 (*info
->fprintf_func
) (info
->stream
, "#0");
1164 for (regno
= 0; regno
< 16; ++regno
)
1165 if (val
& (0x8000 >> regno
))
1166 newval
|= 1 << regno
;
1171 for (regno
= 0; regno
< 16; ++regno
)
1172 if (val
& (1 << regno
))
1177 (*info
->fprintf_func
) (info
->stream
, "/");
1179 (*info
->fprintf_func
) (info
->stream
, "%s", reg_names
[regno
]);
1180 first_regno
= regno
;
1181 while (val
& (1 << (regno
+ 1)))
1183 if (regno
> first_regno
)
1184 (*info
->fprintf_func
) (info
->stream
, "-%s",
1188 else if (place
== '3')
1190 /* `fmovem' insn. */
1196 (*info
->fprintf_func
) (info
->stream
, "#0");
1203 for (regno
= 0; regno
< 8; ++regno
)
1204 if (val
& (0x80 >> regno
))
1205 newval
|= 1 << regno
;
1210 for (regno
= 0; regno
< 8; ++regno
)
1211 if (val
& (1 << regno
))
1215 (*info
->fprintf_func
) (info
->stream
, "/");
1217 (*info
->fprintf_func
) (info
->stream
, "%%fp%d", regno
);
1218 first_regno
= regno
;
1219 while (val
& (1 << (regno
+ 1)))
1221 if (regno
> first_regno
)
1222 (*info
->fprintf_func
) (info
->stream
, "-%%fp%d", regno
);
1225 else if (place
== '8')
1228 /* fmoveml for FP status registers. */
1229 (*info
->fprintf_func
) (info
->stream
, "%s", fpcr_names
[val
]);
1232 return PRINT_INSN_ARG_INVALID_OP_TABLE
;
1251 case 2: name
= "%tt0"; break;
1252 case 3: name
= "%tt1"; break;
1253 case 0x10: name
= "%tc"; break;
1254 case 0x11: name
= "%drp"; break;
1255 case 0x12: name
= "%srp"; break;
1256 case 0x13: name
= "%crp"; break;
1257 case 0x14: name
= "%cal"; break;
1258 case 0x15: name
= "%val"; break;
1259 case 0x16: name
= "%scc"; break;
1260 case 0x17: name
= "%ac"; break;
1261 case 0x18: name
= "%psr"; break;
1262 case 0x19: name
= "%pcsr"; break;
1266 int break_reg
= ((buffer
[3] >> 2) & 7);
1268 (*info
->fprintf_func
)
1269 (info
->stream
, val
== 0x1c ? "%%bad%d" : "%%bac%d",
1274 (*info
->fprintf_func
) (info
->stream
, "<mmu register %d>", val
);
1277 (*info
->fprintf_func
) (info
->stream
, "%s", name
);
1287 (*info
->fprintf_func
) (info
->stream
, "%%dfc");
1289 (*info
->fprintf_func
) (info
->stream
, "%%sfc");
1291 /* xgettext:c-format */
1292 (*info
->fprintf_func
) (info
->stream
, _("<function code %d>"), fc
);
1297 (*info
->fprintf_func
) (info
->stream
, "%%val");
1304 FETCH_ARG (3, level
);
1305 (*info
->fprintf_func
) (info
->stream
, "%d", level
);
1320 (*info
->fprintf_func
) (info
->stream
, "%s%s",
1321 reg_half_names
[reg
],
1322 is_upper
? "u" : "l");
1327 return PRINT_INSN_ARG_INVALID_OP_TABLE
;
1333 /* Try to match the current instruction to best and if so, return the
1334 number of bytes consumed from the instruction stream, else zero. */
1337 match_insn_m68k (bfd_vma memaddr
,
1338 disassemble_info
* info
,
1339 const struct m68k_opcode
* best
)
1341 unsigned char *save_p
;
1344 const char *args
= best
->args
;
1346 struct private *priv
= (struct private *) info
->private_data
;
1347 bfd_byte
*buffer
= priv
->the_buffer
;
1348 fprintf_ftype save_printer
= info
->fprintf_func
;
1349 void (* save_print_address
) (bfd_vma
, struct disassemble_info
*)
1350 = info
->print_address_func
;
1355 /* Point at first word of argument data,
1356 and at descriptor for first argument. */
1359 /* Figure out how long the fixed-size portion of the instruction is.
1360 The only place this is stored in the opcode table is
1361 in the arguments--look for arguments which specify fields in the 2nd
1362 or 3rd words of the instruction. */
1363 for (d
= args
; *d
; d
+= 2)
1365 /* I don't think it is necessary to be checking d[0] here;
1366 I suspect all this could be moved to the case statement below. */
1369 if (d
[1] == 'l' && p
- buffer
< 6)
1371 else if (p
- buffer
< 4 && d
[1] != 'C' && d
[1] != '8')
1375 if ((d
[0] == 'L' || d
[0] == 'l') && d
[1] == 'w' && p
- buffer
< 4)
1401 /* pflusha is an exceptions. It takes no arguments but is two words
1402 long. Recognize it by looking at the lower 16 bits of the mask. */
1403 if (p
- buffer
< 4 && (best
->match
& 0xFFFF) != 0)
1406 /* lpstop is another exception. It takes a one word argument but is
1407 three words long. */
1409 && (best
->match
& 0xffff) == 0xffff
1413 /* Copy the one word argument into the usual location for a one
1414 word argument, to simplify printing it. We can get away with
1415 this because we know exactly what the second word is, and we
1416 aren't going to print anything based on it. */
1418 FETCH_DATA (info
, p
);
1419 buffer
[2] = buffer
[4];
1420 buffer
[3] = buffer
[5];
1423 FETCH_DATA (info
, p
);
1426 info
->print_address_func
= dummy_print_address
;
1427 info
->fprintf_func
= (fprintf_ftype
) dummy_printer
;
1429 /* We scan the operands twice. The first time we don't print anything,
1430 but look for errors. */
1431 for (d
= args
; *d
; d
+= 2)
1433 int eaten
= print_insn_arg (d
, buffer
, p
, memaddr
+ (p
- buffer
), info
);
1437 else if (eaten
== PRINT_INSN_ARG_INVALID_OPERAND
1438 || eaten
== PRINT_INSN_ARG_MEMORY_ERROR
)
1440 info
->fprintf_func
= save_printer
;
1441 info
->print_address_func
= save_print_address
;
1446 /* We must restore the print functions before trying to print the
1448 info
->fprintf_func
= save_printer
;
1449 info
->print_address_func
= save_print_address
;
1450 info
->fprintf_func (info
->stream
,
1451 /* xgettext:c-format */
1452 _("<internal error in opcode table: %s %s>\n"),
1453 best
->name
, best
->args
);
1459 info
->fprintf_func
= save_printer
;
1460 info
->print_address_func
= save_print_address
;
1464 info
->fprintf_func (info
->stream
, "%s", best
->name
);
1467 info
->fprintf_func (info
->stream
, " ");
1471 p
+= print_insn_arg (d
, buffer
, p
, memaddr
+ (p
- buffer
), info
);
1474 if (*d
&& *(d
- 2) != 'I' && *d
!= 'k')
1475 info
->fprintf_func (info
->stream
, ",");
1481 /* Try to interpret the instruction at address MEMADDR as one that
1482 can execute on a processor with the features given by ARCH_MASK.
1483 If successful, print the instruction to INFO->STREAM and return
1484 its length in bytes. Return 0 otherwise. */
1487 m68k_scan_mask (bfd_vma memaddr
, disassemble_info
*info
,
1488 unsigned int arch_mask
)
1492 static const struct m68k_opcode
**opcodes
[16];
1493 static int numopcodes
[16];
1497 struct private *priv
= (struct private *) info
->private_data
;
1498 bfd_byte
*buffer
= priv
->the_buffer
;
1502 /* Speed up the matching by sorting the opcode
1503 table on the upper four bits of the opcode. */
1504 const struct m68k_opcode
**opc_pointer
[16];
1506 /* First count how many opcodes are in each of the sixteen buckets. */
1507 for (i
= 0; i
< m68k_numopcodes
; i
++)
1508 numopcodes
[(m68k_opcodes
[i
].opcode
>> 28) & 15]++;
1510 /* Then create a sorted table of pointers
1511 that point into the unsorted table. */
1512 opc_pointer
[0] = xmalloc (sizeof (struct m68k_opcode
*)
1514 opcodes
[0] = opc_pointer
[0];
1516 for (i
= 1; i
< 16; i
++)
1518 opc_pointer
[i
] = opc_pointer
[i
- 1] + numopcodes
[i
- 1];
1519 opcodes
[i
] = opc_pointer
[i
];
1522 for (i
= 0; i
< m68k_numopcodes
; i
++)
1523 *opc_pointer
[(m68k_opcodes
[i
].opcode
>> 28) & 15]++ = &m68k_opcodes
[i
];
1526 FETCH_DATA (info
, buffer
+ 2);
1527 major_opcode
= (buffer
[0] >> 4) & 15;
1529 for (i
= 0; i
< numopcodes
[major_opcode
]; i
++)
1531 const struct m68k_opcode
*opc
= opcodes
[major_opcode
][i
];
1532 unsigned long opcode
= opc
->opcode
;
1533 unsigned long match
= opc
->match
;
1534 const char *args
= opc
->args
;
1539 if (((0xff & buffer
[0] & (match
>> 24)) == (0xff & (opcode
>> 24)))
1540 && ((0xff & buffer
[1] & (match
>> 16)) == (0xff & (opcode
>> 16)))
1541 /* Only fetch the next two bytes if we need to. */
1542 && (((0xffff & match
) == 0)
1544 (FETCH_DATA (info
, buffer
+ 4)
1545 && ((0xff & buffer
[2] & (match
>> 8)) == (0xff & (opcode
>> 8)))
1546 && ((0xff & buffer
[3] & match
) == (0xff & opcode
)))
1548 && (opc
->arch
& arch_mask
) != 0)
1550 /* Don't use for printout the variants of divul and divsl
1551 that have the same register number in two places.
1552 The more general variants will match instead. */
1553 for (d
= args
; *d
; d
+= 2)
1557 /* Don't use for printout the variants of most floating
1558 point coprocessor instructions which use the same
1559 register number in two places, as above. */
1561 for (d
= args
; *d
; d
+= 2)
1565 /* Don't match fmovel with more than one register;
1566 wait for fmoveml. */
1569 for (d
= args
; *d
; d
+= 2)
1571 if (d
[0] == 's' && d
[1] == '8')
1573 val
= fetch_arg (buffer
, d
[1], 3, info
);
1576 if ((val
& (val
- 1)) != 0)
1582 /* Don't match FPU insns with non-default coprocessor ID. */
1585 for (d
= args
; *d
; d
+= 2)
1589 val
= fetch_arg (buffer
, 'd', 3, info
);
1597 if ((val
= match_insn_m68k (memaddr
, info
, opc
)))
1604 /* Print the m68k instruction at address MEMADDR in debugged memory,
1605 on INFO->STREAM. Returns length of the instruction, in bytes. */
1608 print_insn_m68k (bfd_vma memaddr
, disassemble_info
*info
)
1610 unsigned int arch_mask
;
1611 struct private priv
;
1614 bfd_byte
*buffer
= priv
.the_buffer
;
1616 info
->private_data
= & priv
;
1617 /* Tell objdump to use two bytes per chunk
1618 and six bytes per line for displaying raw data. */
1619 info
->bytes_per_chunk
= 2;
1620 info
->bytes_per_line
= 6;
1621 info
->display_endian
= BFD_ENDIAN_BIG
;
1622 priv
.max_fetched
= priv
.the_buffer
;
1623 priv
.insn_start
= memaddr
;
1625 arch_mask
= bfd_m68k_mach_to_features (info
->mach
);
1628 /* First try printing an m680x0 instruction. Try printing a Coldfire
1629 one if that fails. */
1630 val
= m68k_scan_mask (memaddr
, info
, m68k_mask
);
1632 val
= m68k_scan_mask (memaddr
, info
, mcf_mask
);
1636 val
= m68k_scan_mask (memaddr
, info
, arch_mask
);
1640 /* Handle undefined instructions. */
1641 info
->fprintf_func (info
->stream
, ".short 0x%04x", (buffer
[0] << 8) + buffer
[1]);
1643 return val
? val
: 2;