1 /* Print instructions for the Motorola 88000, for GDB and GNU Binutils.
2 Copyright 1986, 1987, 1988, 1989, 1990, 1991, 1993, 1998, 2000, 2001
3 Free Software Foundation, Inc.
4 Contributed by Data General Corporation, November 1989.
5 Partially derived from an earlier printcmd.c.
7 This file is part of GDB and the GNU Binutils.
9 This program is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 2 of the License, or
12 (at your option) any later version.
14 This program is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with this program; if not, write to the Free Software
21 Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
25 #include "opcode/m88k.h"
27 #include "libiberty.h"
29 typedef struct HASHTAB
{
34 /* Opcode Mnemonic Op 1 Spec Op 2 Spec Op 3 Spec Simflags Next */
36 const INSTAB instructions
[] = {
37 {0xf400c800,"jsr ",{0,5,REG
} ,NO_OPERAND
,NO_OPERAND
, {2,2,NA
,JSR
, 0,0,1,0,0,0,0,1,0,0,0,0} },
38 {0xf400cc00,"jsr.n ",{0,5,REG
} ,NO_OPERAND
,NO_OPERAND
, {1,1,NA
,JSR
, 0,0,1,0,0,0,1,1,0,0,0,0} },
39 {0xf400c000,"jmp ",{0,5,REG
} ,NO_OPERAND
,NO_OPERAND
, {2,2,NA
,JMP
, 0,0,1,0,0,0,0,1,0,0,0,0} },
40 {0xf400c400,"jmp.n ",{0,5,REG
} ,NO_OPERAND
,NO_OPERAND
, {1,1,NA
,JMP
, 0,0,1,0,0,0,1,1,0,0,0,0} },
41 {0xc8000000,"bsr ",{0,26,PCREL
},NO_OPERAND
,NO_OPERAND
, {2,2,NA
,BSR
, i26bit
,0,0,0,0,0,0,1,0,0,0,0} },
42 {0xcc000000,"bsr.n ",{0,26,PCREL
},NO_OPERAND
,NO_OPERAND
, {1,1,NA
,BSR
, i26bit
,0,0,0,0,0,1,1,0,0,0,0} },
43 {0xc0000000,"br ",{0,26,PCREL
},NO_OPERAND
,NO_OPERAND
, {2,2,NA
,BR
, i26bit
,0,0,0,0,0,0,1,0,0,0,0} },
44 {0xc4000000,"br.n ",{0,26,PCREL
},NO_OPERAND
,NO_OPERAND
, {1,1,NA
,BR
, i26bit
,0,0,0,0,0,1,1,0,0,0,0} },
45 {0xd0000000,"bb0 ",{21,5,HEX
} ,{16,5,REG
} ,{0,16,PCREL
},{2,2,NA
,BB0
, i16bit
,0,1,0,0,0,0,1,0,0,0,0} },
46 {0xd4000000,"bb0.n ",{21,5,HEX
} ,{16,5,REG
} ,{0,16,PCREL
},{1,1,NA
,BB0
, i16bit
,0,1,0,0,0,1,1,0,0,0,0} },
47 {0xd8000000,"bb1 ",{21,5,HEX
},{16,5,REG
} ,{0,16,PCREL
},{2,2,NA
,BB1
, i16bit
,0,1,0,0,0,0,1,0,0,0,0} },
48 {0xdc000000,"bb1.n ",{21,5,HEX
},{16,5,REG
} ,{0,16,PCREL
},{1,1,NA
,BB1
, i16bit
,0,1,0,0,0,1,1,0,0,0,0} },
49 {0xf000d000,"tb0 ",{21,5,HEX
} ,{16,5,REG
} ,{0,10,HEX
}, {2,2,NA
,TB0
, i10bit
,0,1,0,0,0,0,1,0,0,0,0} },
50 {0xf000d800,"tb1 ",{21,5,HEX
} ,{16,5,REG
} ,{0,10,HEX
}, {2,2,NA
,TB1
, i10bit
,0,1,0,0,0,0,1,0,0,0,0} },
51 {0xe8000000,"bcnd ",{21,5,CONDMASK
},{16,5,REG
},{0,16,PCREL
},{2,2,NA
,BCND
, i16bit
,0,1,0,0,0,0,1,0,0,0,0} },
52 {0xec000000,"bcnd.n ",{21,5,CONDMASK
},{16,5,REG
},{0,16,PCREL
},{1,1,NA
,BCND
, i16bit
,0,1,0,0,0,1,1,0,0,0,0} },
53 {0xf000e800,"tcnd ",{21,5,CONDMASK
},{16,5,REG
},{0,10,HEX
}, {2,2,NA
,TCND
, i10bit
,0,1,0,0,0,0,1,0,0,0,0} },
54 {0xf8000000,"tbnd ",{16,5,REG
} ,{0,16,HEX
} ,NO_OPERAND
, {2,2,NA
,TBND
, i10bit
,1,0,0,0,0,0,1,0,0,0,0} },
55 {0xf400f800,"tbnd ",{16,5,REG
} ,{0,5,REG
} ,NO_OPERAND
, {2,2,NA
,TBND
, 0,1,1,0,0,0,0,1,0,0,0,0} },
56 {0xf400fc00,"rte ",NO_OPERAND
,NO_OPERAND
,NO_OPERAND
, {2,2,NA
,RTE
, 0,0,0,0,0,0,0,1,0,0,0,0} },
57 {0x1c000000,"ld.b ",{21,5,REG
} ,{16,5,REG
} ,{0,16,HEX
}, {3,1,PMEM
,LDB
,i16bit
,1,0,1,0,0,0,1,0,0,0,0} },
58 {0xf4001c00,"ld.b ",{21,5,REG
} ,{16,5,REG
} ,{0,5,REG
} , {3,1,PMEM
,LDB
, 0,1,1,1,0,0,0,1,0,0,0,0} },
59 {0x0c000000,"ld.bu ",{21,5,REG
} ,{16,5,REG
} ,{0,16,HEX
}, {3,1,PMEM
,LDBU
, i16bit
,1,0,1,0,0,0,1,0,0,0,0} },
60 {0xf4000c00,"ld.bu ",{21,5,REG
} ,{16,5,REG
} ,{0,5,REG
} , {3,1,PMEM
,LDBU
,0,1,1,1,0,0,0,1,0,0,0,0} },
61 {0x18000000,"ld.h ",{21,5,REG
} ,{16,5,REG
} ,{0,16,HEX
}, {3,1,PMEM
,LDH
,i16bit
,1,0,1,0,0,0,1,0,0,0,0} },
62 {0xf4001800,"ld.h ",{21,5,REG
} ,{16,5,REG
} ,{0,5,REG
} , {3,1,PMEM
,LDH
,0,1,1,1,0,0,0,1,0,0,0,0} },
63 {0xf4001a00,"ld.h ",{21,5,REG
} ,{16,5,REG
} ,{0,5,REGSC
},{3,1,PMEM
,LDH
,0,1,1,1,0,0,0,1,0,0,0,1} },
64 {0x08000000,"ld.hu ",{21,5,REG
} ,{16,5,REG
} ,{0,16,HEX
}, {3,1,PMEM
,LDHU
, i16bit
,1,0,1,0,0,0,1,0,0,0,0} },
65 {0xf4000800,"ld.hu ",{21,5,REG
} ,{16,5,REG
} ,{0,5,REG
} , {3,1,PMEM
,LDHU
,0,1,1,1,0,0,0,1,0,0,0,0} },
66 {0xf4000a00,"ld.hu ",{21,5,REG
} ,{16,5,REG
} ,{0,5,REGSC
},{3,1,PMEM
,LDHU
,0,1,1,1,0,0,0,1,0,0,0,1} },
67 {0x14000000,"ld ",{21,5,REG
} ,{16,5,REG
} ,{0,16,HEX
}, {3,1,PMEM
,LD
,i16bit
,1,0,1,0,0,0,1,0,0,0,0} },
68 {0xf4001400,"ld ",{21,5,REG
} ,{16,5,REG
} ,{0,5,REG
} , {3,1,PMEM
,LD
,0,1,1,1,0,0,0,1,0,0,0,0} },
69 {0xf4001600,"ld ",{21,5,REG
} ,{16,5,REG
} ,{0,5,REGSC
},{3,1,PMEM
,LD
,0,1,1,1,0,0,0,1,0,0,0,1} },
70 {0x10000000,"ld.d ",{21,5,REG
} ,{16,5,REG
} ,{0,16,HEX
}, {3,1,PMEM
,LDD
,i16bit
,1,0,1,0,0,0,1,0,0,0,0} },
71 {0xf4001000,"ld.d ",{21,5,REG
} ,{16,5,REG
} ,{0,5,REG
} , {3,1,PMEM
,LDD
,0,1,1,1,0,0,0,1,0,0,0,0} },
72 {0xf4001200,"ld.d ",{21,5,REG
} ,{16,5,REG
} ,{0,5,REGSC
},{3,1,PMEM
,LDD
,0,1,1,1,0,0,0,1,0,0,0,1} },
73 {0xf4001500,"ld.usr ",{21,5,REG
} ,{16,5,REG
} ,{0,5,REG
} , {3,1,PMEM
,LD
,0,1,1,1,0,0,0,1,0,0,0,0} },
74 {0xf4001700,"ld.usr ",{21,5,REG
} ,{16,5,REG
} ,{0,5,REGSC
},{3,1,PMEM
,LD
,0,1,1,1,0,0,0,1,0,0,0,1} },
75 {0x2c000000,"st.b ",{21,5,REG
} ,{16,5,REG
} ,{0,16,HEX
}, {1,1,NA
,STB
,i16bit
,1,0,1,0,0,0,1,0,0,0,0} },
76 {0xf4002c00,"st.b ",{21,5,REG
} ,{16,5,REG
} ,{0,5,REG
} , {1,1,NA
,STB
,0,1,1,1,0,0,0,1,0,0,0,0} },
77 {0x28000000,"st.h ",{21,5,REG
} ,{16,5,REG
} ,{0,16,HEX
}, {1,1,NA
,STH
,i16bit
,1,0,1,0,0,0,1,0,0,0,0} },
78 {0xf4002800,"st.h ",{21,5,REG
} ,{16,5,REG
} ,{0,5,REG
} , {1,1,NA
,STH
,0,1,1,1,0,0,0,1,0,0,0,0} },
79 {0xf4002a00,"st.h ",{21,5,REG
} ,{16,5,REG
} ,{0,5,REGSC
},{1,1,NA
,STH
,0,1,1,1,0,0,0,1,0,0,0,1} },
80 {0x24000000,"st ",{21,5,REG
} ,{16,5,REG
} ,{0,16,HEX
}, {1,1,NA
,ST
,i16bit
,1,0,1,0,0,0,1,0,0,0,0} },
81 {0xf4002400,"st ",{21,5,REG
} ,{16,5,REG
} ,{0,5,REG
} , {1,1,NA
,ST
,0,1,1,1,0,0,0,1,0,0,0,0} },
82 {0xf4002600,"st ",{21,5,REG
} ,{16,5,REG
} ,{0,5,REGSC
},{1,1,NA
,ST
,0,1,1,1,0,0,0,1,0,0,0,1} },
83 {0x20000000,"st.d ",{21,5,REG
} ,{16,5,REG
} ,{0,16,HEX
}, {1,1,NA
,STD
,i16bit
,0,1,0,0,0,0,1,0,0,0,0} },
84 {0xf4002000,"st.d ",{21,5,REG
} ,{16,5,REG
} ,{0,5,REG
} , {1,1,NA
,STD
,0,1,1,1,0,0,0,1,0,0,0,0} },
85 {0xf4002200,"st.d ",{21,5,REG
} ,{16,5,REG
} ,{0,5,REGSC
},{1,1,NA
,STD
,0,1,1,1,0,0,0,1,0,0,0,1} },
86 {0xf4002500,"st.usr ",{21,5,REG
} ,{16,5,REG
} ,{0,5,REG
} , {1,1,NA
,ST
,0,1,1,1,0,0,0,1,0,0,0,0} },
87 {0xf4002700,"st.usr ",{21,5,REG
} ,{16,5,REG
} ,{0,5,REGSC
},{1,1,NA
,ST
,0,1,1,1,0,0,0,1,0,0,0,1} },
89 {0x00000000,"xmem.bu ",{21,5,REG} ,{16,5,REG} ,{0,16,HEX}, {3,1,PMEM,XMEMBU ,i16bit,1,1,1,0,0,0,1,0,0,0,0} },
91 {0xf4000000,"xmem.bu ",{21,5,REG
} ,{16,5,REG
} ,{0,5,REG
} , {3,1,PMEM
,XMEM
,0,1,1,1,0,0,0,1,0,0,0,0} },
93 {0x04000000,"xmem ",{21,5,REG} ,{16,5,REG} ,{0,16,HEX}, {3,1,PMEM,XMEM ,i16bit,1,1,1,0,0,0,1,0,0,0,0} },
95 {0xf4000400,"xmem ",{21,5,REG
} ,{16,5,REG
} ,{0,5,REG
} , {3,1,PMEM
,XMEM
,0,1,1,1,0,0,0,1,0,0,0,0} },
96 {0xf4000600,"xmem ",{21,5,REG
} ,{16,5,REG
} ,{0,5,REGSC
},{3,1,PMEM
,XMEM
,0,1,1,1,0,0,0,1,0,0,0,1} },
97 {0xf4000500,"xmem.usr ",{21,5,REG
} ,{16,5,REG
} ,{0,5,REG
} , {3,1,PMEM
,XMEM
,0,1,1,1,0,0,0,1,0,0,0,0} },
98 {0xf4000700,"xmem.usr ",{21,5,REG
} ,{16,5,REG
} ,{0,5,REGSC
},{3,1,PMEM
,XMEM
,0,1,1,1,0,0,0,1,0,0,0,1} },
100 {0xf4003e00,"lda.b ",{21,5,REG} ,{16,5,REG} ,{0,5,REGSC},{1,1,PINT,LDAH, 0,1,1,1,0,0,0,0,0,0,0,1} },
102 {0xf4003e00,"lda.x ",{21,5,REG
} ,{16,5,REG
} ,{0,5,REGSC
},{1,1,PINT
,LDAH
, 0,1,1,1,0,0,0,0,0,0,0,1} },
103 {0xf4003a00,"lda.h ",{21,5,REG
} ,{16,5,REG
} ,{0,5,REGSC
},{1,1,PINT
,LDAH
, 0,1,1,1,0,0,0,0,0,0,0,1} },
104 {0xf4003600,"lda ",{21,5,REG
} ,{16,5,REG
} ,{0,5,REGSC
},{1,1,PINT
,LDA
, 0,1,1,1,0,0,0,0,0,0,0,1} },
105 {0xf4003200,"lda.d ",{21,5,REG
} ,{16,5,REG
} ,{0,5,REGSC
},{1,1,PINT
,LDAD
, 0,1,1,1,0,0,0,0,0,0,0,1} },
107 {0x80004000,"ldcr ",{21,5,REG
} ,{5,6,CRREG
} ,NO_OPERAND
,{1,1,PINT
,LDCR
, 0,1,1,1,0,0,0,0,0,0,0,0} },
108 {0x80008000,"stcr ",{16,5,REG
} ,{5,6,CRREG
} ,NO_OPERAND
,{1,1,PINT
,STCR
, 0,1,1,1,0,0,0,0,0,0,0,0} },
109 {0x8000c000,"xcr ",{21,5,REG
} ,{16,5,REG
} ,{5,6,CRREG
},{1,1,PINT
,XCR
, 0,1,1,1,0,0,0,0,0,0,0,0} },
111 {0xf4006000,"addu ",{21,5,REG
} ,{16,5,REG
} ,{0,5,REG
} , {1,1,PINT
,ADDU
, 0,1,1,1,0,0,0,0,0,0,0,0} },
112 {0xf4006200,"addu.ci ",{21,5,REG
} ,{16,5,REG
} ,{0,5,REG
} , {1,1,PINT
,ADDU
, 0,1,1,1,0,0,0,0,0,0,0,0} },
113 {0xf4006100,"addu.co ",{21,5,REG
} ,{16,5,REG
} ,{0,5,REG
} , {1,1,PINT
,ADDU
, 0,1,1,1,0,0,0,0,0,0,0,0} },
114 {0xf4006300,"addu.cio ",{21,5,REG
} ,{16,5,REG
} ,{0,5,REG
} , {1,1,PINT
,ADDU
, 0,1,1,1,0,0,0,0,0,0,0,0} },
115 {0xf4006400,"subu ",{21,5,REG
} ,{16,5,REG
} ,{0,5,REG
} , {1,1,PINT
,SUBU
, 0,1,1,1,0,0,0,0,0,0,0,0} },
116 {0xf4006600,"subu.ci ",{21,5,REG
} ,{16,5,REG
} ,{0,5,REG
} , {1,1,PINT
,SUBU
, 0,1,1,1,0,0,0,0,0,0,0,0} },
117 {0xf4006500,"subu.co ",{21,5,REG
} ,{16,5,REG
} ,{0,5,REG
} , {1,1,PINT
,SUBU
, 0,1,1,1,0,0,0,0,0,0,0,0} },
118 {0xf4006700,"subu.cio ",{21,5,REG
} ,{16,5,REG
} ,{0,5,REG
} , {1,1,PINT
,SUBU
, 0,1,1,1,0,0,0,0,0,0,0,0} },
119 {0xf4006800,"divu ",{21,5,REG
} ,{16,5,REG
} ,{0,5,REG
} , {32,32,PINT
,DIVU
, 0,1,1,1,0,0,0,0,0,0,0,0} },
120 {0xf4006900,"divu.d ",{21,5,REG
} ,{16,5,REG
} ,{0,5,REG
} , {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,} },
121 {0xf4006e00,"muls ",{21,5,REG
} ,{16,5,REG
} ,{0,5,REG
} , {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,} },
122 {0xf4006c00,"mulu ",{21,5,REG
} ,{16,5,REG
} ,{0,5,REG
} , {1,4,PINT
,MUL
, 0,1,1,1,0,0,0,0,0,0,0,0} },
123 {0xf4007000,"add ",{21,5,REG
} ,{16,5,REG
} ,{0,5,REG
} , {1,1,PINT
,ADD
, 0,1,1,1,0,0,0,0,0,0,0,0} },
124 {0xf4007200,"add.ci ",{21,5,REG
} ,{16,5,REG
} ,{0,5,REG
} , {1,1,PINT
,ADD
, 0,1,1,1,0,0,0,0,0,0,0,0} },
125 {0xf4007100,"add.co ",{21,5,REG
} ,{16,5,REG
} ,{0,5,REG
} , {1,1,PINT
,ADD
, 0,1,1,1,0,0,0,0,0,0,0,0} },
126 {0xf4007300,"add.cio ",{21,5,REG
} ,{16,5,REG
} ,{0,5,REG
} , {1,1,PINT
,ADD
, 0,1,1,1,0,0,0,0,0,0,0,0} },
127 {0xf4007400,"sub ",{21,5,REG
} ,{16,5,REG
} ,{0,5,REG
} , {1,1,PINT
,SUB
, 0,1,1,1,0,0,0,0,0,0,0,0} },
128 {0xf4007600,"sub.ci ",{21,5,REG
} ,{16,5,REG
} ,{0,5,REG
} , {1,1,PINT
,SUB
, 0,1,1,1,0,0,0,0,0,0,0,0} },
129 {0xf4007500,"sub.co ",{21,5,REG
} ,{16,5,REG
} ,{0,5,REG
} , {1,1,PINT
,SUB
, 0,1,1,1,0,0,0,0,0,0,0,0} },
130 {0xf4007700,"sub.cio ",{21,5,REG
} ,{16,5,REG
} ,{0,5,REG
} , {1,1,PINT
,SUB
, 0,1,1,1,0,0,0,0,0,0,0,0} },
131 {0xf4007800,"divs ",{21,5,REG
} ,{16,5,REG
} ,{0,5,REG
} , {32,32,PINT
,DIV
, 0,1,1,1,0,0,0,0,0,0,0,0} },
132 {0xf4007c00,"cmp ",{21,5,REG
} ,{16,5,REG
} ,{0,5,REG
} , {1,1,PINT
,CMP
, 0,1,1,1,0,0,0,0,0,0,0,0} },
134 {0x60000000,"addu ",{21,5,REG
} ,{16,5,REG
} ,{0,16,HEX
}, {1,1,PINT
,ADDU
, i16bit
,1,0,1,0,0,0,0,0,0,0,0} },
135 {0x64000000,"subu ",{21,5,REG
} ,{16,5,REG
} ,{0,16,HEX
}, {1,1,PINT
,SUBU
, i16bit
,1,0,1,0,0,0,0,0,0,0,0} },
137 {0x68000000,"divu ",{21,5,REG
} ,{16,5,REG
} ,{0,16,HEX
}, {32,32,PINT
,DIVU
, i16bit
,1,0,1,0,0,0,0,0,0,0,0} },
138 {0x6c000000,"mulu ",{21,5,REG
} ,{16,5,REG
} ,{0,16,HEX
}, {4,1,PINT
,MUL
, i16bit
,1,0,1,0,0,0,0,0,0,0,0} },
139 {0x70000000,"add ",{21,5,REG
} ,{16,5,REG
} ,{0,16,HEX
}, {1,1,PINT
,ADD
, i16bit
,1,0,1,0,0,0,0,0,0,0,0} },
140 {0x74000000,"sub ",{21,5,REG
} ,{16,5,REG
} ,{0,16,HEX
}, {1,1,PINT
,SUB
, i16bit
,1,0,1,0,0,0,0,0,0,0,0} },
141 {0x78000000,"divs ",{21,5,REG
} ,{16,5,REG
} ,{0,16,HEX
}, {32,32,PINT
,DIV
, i16bit
,1,0,1,0,0,0,0,0,0,0,0} },
142 {0x7c000000,"cmp ",{21,5,REG
} ,{16,5,REG
} ,{0,16,HEX
}, {1,1,PINT
,CMP
, i16bit
,1,0,1,0,0,0,0,0,0,0,0} },
144 {0xf4004000,"and ",{21,5,REG
} ,{16,5,REG
} ,{0,5,REG
} , {1,1,PINT
,AND_
,0,1,1,1,0,0,0,0,0,0,0,0} },
145 {0xf4004400,"and.c ",{21,5,REG
} ,{16,5,REG
} ,{0,5,REG
} , {1,1,PINT
,AND_
,0,1,1,1,1,0,0,0,0,0,0,0} },
146 {0xf4005800,"or ",{21,5,REG
} ,{16,5,REG
} ,{0,5,REG
} , {1,1,PINT
,OR
,0,1,1,1,0,0,0,0,0,0,0,0} },
147 {0xf4005c00,"or.c ",{21,5,REG
} ,{16,5,REG
} ,{0,5,REG
} , {1,1,PINT
,OR
,0,1,1,1,1,0,0,0,0,0,0,0} },
148 {0xf4005000,"xor ",{21,5,REG
} ,{16,5,REG
} ,{0,5,REG
} , {1,1,PINT
,XOR
,0,1,1,1,0,0,0,0,0,0,0,0} },
149 {0xf4005400,"xor.c ",{21,5,REG
} ,{16,5,REG
} ,{0,5,REG
} , {1,1,PINT
,XOR
,0,1,1,1,1,0,0,0,0,0,0,0} },
150 {0x40000000,"and ",{21,5,REG
} ,{16,5,REG
} ,{0,16,HEX
}, {1,1,PINT
,AND_
,i16bit
,1,0,1,0,0,0,0,0,0,0,0} },
151 {0x44000000,"and.u ",{21,5,REG
} ,{16,5,REG
} ,{0,16,HEX
}, {1,1,PINT
,AND_
,i16bit
,1,0,1,0,1,0,0,0,0,0,0} },
152 {0x58000000,"or ",{21,5,REG
} ,{16,5,REG
} ,{0,16,HEX
}, {1,1,PINT
,OR
,i16bit
,1,0,1,0,0,0,0,0,0,0,0} },
153 {0x5c000000,"or.u ",{21,5,REG
} ,{16,5,REG
} ,{0,16,HEX
}, {1,1,PINT
,OR
,i16bit
,1,0,1,0,1,0,0,0,0,0,0} },
154 {0x50000000,"xor ",{21,5,REG
} ,{16,5,REG
} ,{0,16,HEX
}, {1,1,PINT
,XOR
,i16bit
,1,0,1,0,0,0,0,0,0,0,0} },
155 {0x54000000,"xor.u ",{21,5,REG
} ,{16,5,REG
} ,{0,16,HEX
}, {1,1,PINT
,XOR
,i16bit
,1,0,1,0,1,0,0,0,0,0,0} },
156 {0x48000000,"mask ",{21,5,REG
} ,{16,5,REG
} ,{0,16,HEX
}, {1,1,PINT
,MASK
,i16bit
,1,0,1,0,0,0,0,0,0,0,0} },
157 {0x4c000000,"mask.u ",{21,5,REG
} ,{16,5,REG
} ,{0,16,HEX
}, {1,1,PINT
,MASK
,i16bit
,1,0,1,0,1,0,0,0,0,0,0} },
158 {0xf400ec00,"ff0 ",{21,5,REG
} ,{0,5,REG
} ,NO_OPERAND
, {1,1,PINT
,FF0
,0,0,1,1,0,0,0,0,0,0,0,0} },
159 {0xf400e800,"ff1 ",{21,5,REG
} ,{0,5,REG
} ,NO_OPERAND
, {1,1,PINT
,FF1
,0,0,1,1,0,0,0,0,0,0,0,0} },
160 {0xf0008000,"clr ",{21,5,REG
} ,{16,5,REG
} ,{0,10,BF
} , {1,1,PINT
,CLR
,i10bit
,1,0,1,0,0,0,0,0,0,0,0} },
161 {0xf0008800,"set ",{21,5,REG
} ,{16,5,REG
} ,{0,10,BF
} , {1,1,PINT
,SET
,i10bit
,1,0,1,0,0,0,0,0,0,0,0} },
162 {0xf0009000,"ext ",{21,5,REG
} ,{16,5,REG
} ,{0,10,BF
} , {1,1,PINT
,EXT
,i10bit
,1,0,1,0,0,0,0,0,0,0,0} },
163 {0xf0009800,"extu ",{21,5,REG
} ,{16,5,REG
} ,{0,10,BF
} , {1,1,PINT
,EXTU
,i10bit
,1,0,1,0,0,0,0,0,0,0,0} },
164 {0xf000a000,"mak ",{21,5,REG
} ,{16,5,REG
} ,{0,10,BF
} , {1,1,PINT
,MAK
,i10bit
,1,0,1,0,0,0,0,0,0,0,0} },
165 {0xf000a800,"rot ",{21,5,REG
} ,{16,5,REG
} ,{0,10,BF
} , {1,1,PINT
,ROT
,i10bit
,1,0,1,0,0,0,0,0,0,0,0} },
166 {0xf4008000,"clr ",{21,5,REG
} ,{16,5,REG
} ,{0,5,REG
} , {1,1,PINT
,CLR
,0,1,1,1,0,0,0,0,0,0,0,0} },
167 {0xf4008800,"set ",{21,5,REG
} ,{16,5,REG
} ,{0,5,REG
} , {1,1,PINT
,SET
,0,1,1,1,0,0,0,0,0,0,0,0} },
168 {0xf4009000,"ext ",{21,5,REG
} ,{16,5,REG
} ,{0,5,REG
} , {1,1,PINT
,EXT
,0,1,1,1,0,0,0,0,0,0,0,0} },
169 {0xf4009800,"extu ",{21,5,REG
} ,{16,5,REG
} ,{0,5,REG
} , {1,1,PINT
,EXTU
,0,1,1,1,0,0,0,0,0,0,0,0} },
170 {0xf400a000,"mak ",{21,5,REG
} ,{16,5,REG
} ,{0,5,REG
} , {1,1,PINT
,MAK
,0,1,1,1,0,0,0,0,0,0,0,0} },
171 {0xf400a800,"rot ",{21,5,REG
} ,{16,5,REG
} ,{0,5,REG
} , {1,1,PINT
,ROT
,0,1,1,1,0,0,0,0,0,0,0,0} },
173 {0x84002800,"fadd.sss ",{21,5,REG
} ,{16,5,REG
} ,{0,5,REG
} , {5,1,PFLT
,FADD
,0,1,1,1,0,0,0,1,0,0,0,0} },
174 {0x84002880,"fadd.ssd ",{21,5,REG
} ,{16,5,REG
} ,{0,5,REG
} , {6,2,PFLT
,FADD
,0,1,1,1,0,0,0,1,0,0,1,0} },
175 {0x84002a00,"fadd.sds ",{21,5,REG
} ,{16,5,REG
} ,{0,5,REG
} , {6,2,PFLT
,FADD
,0,1,1,1,0,0,0,1,0,1,0,0} },
176 {0x84002a80,"fadd.sdd ",{21,5,REG
} ,{16,5,REG
} ,{0,5,REG
} , {6,2,PFLT
,FADD
,0,1,1,1,0,0,0,1,0,1,1,0} },
177 {0x84002820,"fadd.dss ",{21,5,REG
} ,{16,5,REG
} ,{0,5,REG
} , {6,2,PFLT
,FADD
,0,1,1,1,0,0,0,1,1,0,0,0} },
178 {0x840028a0,"fadd.dsd ",{21,5,REG
} ,{16,5,REG
} ,{0,5,REG
} , {6,2,PFLT
,FADD
,0,1,1,1,0,0,0,1,1,0,1,0} },
179 {0x84002a20,"fadd.dds ",{21,5,REG
} ,{16,5,REG
} ,{0,5,REG
} , {6,2,PFLT
,FADD
,0,1,1,1,0,0,0,1,1,1,0,0} },
180 {0x84002aa0,"fadd.ddd ",{21,5,REG
} ,{16,5,REG
} ,{0,5,REG
} , {6,2,PFLT
,FADD
,0,1,1,1,0,0,0,1,1,1,1,0} },
181 {0x84003000,"fsub.sss ",{21,5,REG
} ,{16,5,REG
} ,{0,5,REG
} , {5,1,PFLT
,FSUB
,0,1,1,1,0,0,0,1,0,0,0,0} },
182 {0x84003080,"fsub.ssd ",{21,5,REG
} ,{16,5,REG
} ,{0,5,REG
} , {6,2,PFLT
,FSUB
,0,1,1,1,0,0,0,1,0,0,1,0} },
183 {0x84003200,"fsub.sds ",{21,5,REG
} ,{16,5,REG
} ,{0,5,REG
} , {6,2,PFLT
,FSUB
,0,1,1,1,0,0,0,1,0,1,0,0} },
184 {0x84003280,"fsub.sdd ",{21,5,REG
} ,{16,5,REG
} ,{0,5,REG
} , {6,2,PFLT
,FSUB
,0,1,1,1,0,0,0,1,0,1,1,0} },
185 {0x84003020,"fsub.dss ",{21,5,REG
} ,{16,5,REG
} ,{0,5,REG
} , {6,2,PFLT
,FSUB
,0,1,1,1,0,0,0,1,1,0,0,0} },
186 {0x840030a0,"fsub.dsd ",{21,5,REG
} ,{16,5,REG
} ,{0,5,REG
} , {6,2,PFLT
,FSUB
,0,1,1,1,0,0,0,1,1,0,1,0} },
187 {0x84003220,"fsub.dds ",{21,5,REG
} ,{16,5,REG
} ,{0,5,REG
} , {6,2,PFLT
,FSUB
,0,1,1,1,0,0,0,1,1,1,0,0} },
188 {0x840032a0,"fsub.ddd ",{21,5,REG
} ,{16,5,REG
} ,{0,5,REG
} , {6,2,PFLT
,FSUB
,0,1,1,1,0,0,0,1,1,1,1,0} },
189 {0x84000000,"fmul.sss ",{21,5,REG
} ,{16,5,REG
} ,{0,5,REG
} , {6,1,PFLT
,FMUL
,0,1,1,1,0,0,0,1,0,0,0,0} },
190 {0x84000080,"fmul.ssd ",{21,5,REG
} ,{16,5,REG
} ,{0,5,REG
} , {9,2,PFLT
,FMUL
,0,1,1,1,0,0,0,1,0,0,1,0} },
191 {0x84000200,"fmul.sds ",{21,5,REG
} ,{16,5,REG
} ,{0,5,REG
} , {9,2,PFLT
,FMUL
,0,1,1,1,0,0,0,1,0,1,0,0} },
192 {0x84000280,"fmul.sdd ",{21,5,REG
} ,{16,5,REG
} ,{0,5,REG
} , {9,2,PFLT
,FMUL
,0,1,1,1,0,0,0,1,0,1,1,0} },
193 {0x84000020,"fmul.dss ",{21,5,REG
} ,{16,5,REG
} ,{0,5,REG
} , {9,2,PFLT
,FMUL
,0,1,1,1,0,0,0,1,1,0,0,0} },
194 {0x840000a0,"fmul.dsd ",{21,5,REG
} ,{16,5,REG
} ,{0,5,REG
} , {9,2,PFLT
,FMUL
,0,1,1,1,0,0,0,1,1,0,1,0} },
195 {0x84000220,"fmul.dds ",{21,5,REG
} ,{16,5,REG
} ,{0,5,REG
} , {9,2,PFLT
,FMUL
,0,1,1,1,0,0,0,1,1,1,0,0} },
196 {0x840002a0,"fmul.ddd ",{21,5,REG
} ,{16,5,REG
} ,{0,5,REG
} , {9,2,PFLT
,FMUL
,0,1,1,1,0,0,0,1,1,1,1,0} },
197 {0x84007000,"fdiv.sss ",{21,5,REG
} ,{16,5,REG
} ,{0,5,REG
} , {30,30,PFLT
,FDIV
,0,1,1,1,0,0,0,1,0,0,0,0} },
198 {0x84007080,"fdiv.ssd ",{21,5,REG
} ,{16,5,REG
} ,{0,5,REG
} , {60,60,PFLT
,FDIV
,0,1,1,1,0,0,0,1,0,0,1,0} },
199 {0x84007200,"fdiv.sds ",{21,5,REG
} ,{16,5,REG
} ,{0,5,REG
} , {60,60,PFLT
,FDIV
,0,1,1,1,0,0,0,1,0,1,0,0} },
200 {0x84007280,"fdiv.sdd ",{21,5,REG
} ,{16,5,REG
} ,{0,5,REG
} , {60,60,PFLT
,FDIV
,0,1,1,1,0,0,0,1,0,1,1,0} },
201 {0x84007020,"fdiv.dss ",{21,5,REG
} ,{16,5,REG
} ,{0,5,REG
} , {60,60,PFLT
,FDIV
,0,1,1,1,0,0,0,1,1,0,0,0} },
202 {0x840070a0,"fdiv.dsd ",{21,5,REG
} ,{16,5,REG
} ,{0,5,REG
} , {60,60,PFLT
,FDIV
,0,1,1,1,0,0,0,1,1,0,1,0} },
203 {0x84007220,"fdiv.dds ",{21,5,REG
} ,{16,5,REG
} ,{0,5,REG
} , {60,60,PFLT
,FDIV
,0,1,1,1,0,0,0,1,1,1,0,0} },
204 {0x840072a0,"fdiv.ddd ",{21,5,REG
} ,{16,5,REG
} ,{0,5,REG
} , {60,60,PFLT
,FDIV
,0,1,1,1,0,0,0,1,1,1,1,0} },
205 {0x84007800,"fsqrt.ss ",{21,5,REG
} ,{0,5,REG
} ,NO_OPERAND
, {5,1,PFLT
,FLT
,0,0,1,1,0,0,0,1,0,0,0,0} },
206 {0x84007820,"fsqrt.sd ",{21,5,REG
} ,{0,5,REG
} ,NO_OPERAND
, {5,1,PFLT
,FLT
,0,0,1,1,0,0,0,1,0,0,0,0} },
207 {0x84007880,"fsqrt.ds ",{21,5,REG
} ,{0,5,REG
} ,NO_OPERAND
, {5,1,PFLT
,FLT
,0,0,1,1,0,0,0,1,0,0,0,0} },
208 {0x840078a0,"fsqrt.dd ",{21,5,REG
} ,{0,5,REG
} ,NO_OPERAND
, {6,1,PFLT
,FLT
,0,0,1,1,0,0,0,1,1,0,0,0} },
209 {0x84003800,"fcmp.ss ",{21,5,REG
} ,{16,5,REG
} ,{0,5,REG
} , {5,1,PFLT
,FCMP
,0,1,1,1,0,0,0,1,0,0,0,0} },
210 {0x84003880,"fcmp.sd ",{21,5,REG
} ,{16,5,REG
} ,{0,5,REG
} , {6,1,PFLT
,FCMP
,0,1,1,1,0,0,0,1,0,1,0,0} },
211 {0x84003a00,"fcmp.ds ",{21,5,REG
} ,{16,5,REG
} ,{0,5,REG
} , {6,1,PFLT
,FCMP
,0,1,1,1,0,0,0,1,1,0,0,0} },
212 {0x84003a80,"fcmp.dd ",{21,5,REG
} ,{16,5,REG
} ,{0,5,REG
} , {6,1,PFLT
,FCMP
,0,1,1,1,0,0,0,1,1,1,0,0} },
213 {0x84002000,"flt.s ",{21,5,REG
} ,{0,5,REG
} ,NO_OPERAND
, {5,1,PFLT
,FLT
,0,0,1,1,0,0,0,1,0,0,0,0} },
214 {0x84002020,"flt.d ",{21,5,REG
} ,{0,5,REG
} ,NO_OPERAND
, {6,1,PFLT
,FLT
,0,0,1,1,0,0,0,1,1,0,0,0} },
215 {0x84004800,"int.s ",{21,5,REG
} ,{0,5,REG
} ,NO_OPERAND
, {5,1,PFLT
,INT
,0,0,1,1,0,0,0,1,0,0,0,0} },
216 {0x84004880,"int.d ",{21,5,REG
} ,{0,5,REG
} ,NO_OPERAND
, {6,1,PFLT
,INT
,0,0,1,1,0,0,0,1,1,0,0,0} },
217 {0x84005000,"nint.s ",{21,5,REG
} ,{0,5,REG
} ,NO_OPERAND
, {5,1,PFLT
,INT
,0,0,1,1,0,0,0,1,0,0,0,0} },
218 {0x84005080,"nint.d ",{21,5,REG
} ,{0,5,REG
} ,NO_OPERAND
, {6,1,PFLT
,INT
,0,0,1,1,0,0,0,1,1,0,0,0} },
219 {0x84005800,"trnc.s ",{21,5,REG
} ,{0,5,REG
} ,NO_OPERAND
, {5,1,PFLT
,TRNC
,0,0,1,1,0,0,0,1,0,0,0,0} },
220 {0x84005880,"trnc.d ",{21,5,REG
} ,{0,5,REG
} ,NO_OPERAND
, {6,1,PFLT
,TRNC
,0,0,1,1,0,0,0,1,1,0,0,0} },
222 {0x80004800,"fldcr ",{21,5,REG
} ,{5,6,FCRREG
} ,NO_OPERAND
, {1,1,PFLT
,FLDC
,0,0,1,1,0,0,0,1,0,0,0,0} },
223 {0x80008800,"fstcr ",{16,5,REG
} ,{5,6,FCRREG
} ,NO_OPERAND
, {1,1,PFLT
,FSTC
,0,0,1,1,0,0,0,1,0,0,0,0} },
224 {0x8000c800,"fxcr ",{21,5,REG
} ,{16,5,REG
} ,{5,6,FCRREG
} , {1,1,PFLT
,FXC
,0,0,1,1,0,0,0,1,0,0,0,0} },
226 /* The following are new for the 88110. */
228 {0x8400aaa0,"fadd.ddd ",{21,5,XREG
} ,{16,5,XREG
} ,{0,5,XREG
}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0} },
229 {0x8400aa80,"fadd.dds ",{21,5,XREG
} ,{16,5,XREG
} ,{0,5,XREG
}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0} },
230 {0x8400aac0,"fadd.ddx ",{21,5,XREG
} ,{16,5,XREG
} ,{0,5,XREG
}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0} },
231 {0x8400aa20,"fadd.dsd ",{21,5,XREG
} ,{16,5,XREG
} ,{0,5,XREG
}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0} },
232 {0x8400aa00,"fadd.dss ",{21,5,XREG
} ,{16,5,XREG
} ,{0,5,XREG
}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0} },
233 {0x8400aa40,"fadd.dsx ",{21,5,XREG
} ,{16,5,XREG
} ,{0,5,XREG
}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0} },
234 {0x8400ab20,"fadd.dxd ",{21,5,XREG
} ,{16,5,XREG
} ,{0,5,XREG
}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0} },
235 {0x8400ab00,"fadd.dxs ",{21,5,XREG
} ,{16,5,XREG
} ,{0,5,XREG
}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0} },
236 {0x8400ab40,"fadd.dxx ",{21,5,XREG
} ,{16,5,XREG
} ,{0,5,XREG
}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0} },
237 {0x8400a8a0,"fadd.sdd ",{21,5,XREG
} ,{16,5,XREG
} ,{0,5,XREG
}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0} },
238 {0x8400a880,"fadd.sds ",{21,5,XREG
} ,{16,5,XREG
} ,{0,5,XREG
}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0} },
239 {0x8400a8c0,"fadd.sdx ",{21,5,XREG
} ,{16,5,XREG
} ,{0,5,XREG
}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0} },
240 {0x8400a820,"fadd.ssd ",{21,5,XREG
} ,{16,5,XREG
} ,{0,5,XREG
}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0} },
241 {0x8400a800,"fadd.sss ",{21,5,XREG
} ,{16,5,XREG
} ,{0,5,XREG
}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0} },
242 {0x8400a840,"fadd.ssx ",{21,5,XREG
} ,{16,5,XREG
} ,{0,5,XREG
}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0} },
243 {0x8400a920,"fadd.sxd ",{21,5,XREG
} ,{16,5,XREG
} ,{0,5,XREG
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244 {0x8400a900,"fadd.sxs ",{21,5,XREG
} ,{16,5,XREG
} ,{0,5,XREG
}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0} },
245 {0x8400a940,"fadd.sxx ",{21,5,XREG
} ,{16,5,XREG
} ,{0,5,XREG
}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0} },
246 {0x8400aca0,"fadd.xdd ",{21,5,XREG
} ,{16,5,XREG
} ,{0,5,XREG
}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0} },
247 {0x8400ac80,"fadd.xds ",{21,5,XREG
} ,{16,5,XREG
} ,{0,5,XREG
}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0} },
248 {0x8400acc0,"fadd.xdx ",{21,5,XREG
} ,{16,5,XREG
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}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0} },
249 {0x8400ac20,"fadd.xsd ",{21,5,XREG
} ,{16,5,XREG
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}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0} },
250 {0x8400ac00,"fadd.xss ",{21,5,XREG
} ,{16,5,XREG
} ,{0,5,XREG
}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0} },
251 {0x8400ac40,"fadd.xsx ",{21,5,XREG
} ,{16,5,XREG
} ,{0,5,XREG
}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0} },
252 {0x8400ad20,"fadd.xxd ",{21,5,XREG
} ,{16,5,XREG
} ,{0,5,XREG
}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0} },
253 {0x8400ad00,"fadd.xxs ",{21,5,XREG
} ,{16,5,XREG
} ,{0,5,XREG
}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0} },
254 {0x8400ad40,"fadd.xxx ",{21,5,XREG
} ,{16,5,XREG
} ,{0,5,XREG
}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0} },
256 {0x8400ba80,"fcmp.sdd ",{21,5,REG
} ,{16,5,XREG
} ,{0,5,XREG
}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0} },
257 {0x8400ba00,"fcmp.sds ",{21,5,REG
} ,{16,5,XREG
} ,{0,5,XREG
}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0} },
258 {0x8400bb00,"fcmp.sdx ",{21,5,REG
} ,{16,5,XREG
} ,{0,5,XREG
}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0} },
259 {0x8400b880,"fcmp.ssd ",{21,5,REG
} ,{16,5,XREG
} ,{0,5,XREG
}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0} },
260 {0x8400b800,"fcmp.sss ",{21,5,REG
} ,{16,5,XREG
} ,{0,5,XREG
}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0} },
261 {0x8400b900,"fcmp.ssx ",{21,5,REG
} ,{16,5,XREG
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}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0} },
262 {0x8400bc80,"fcmp.sxd ",{21,5,REG
} ,{16,5,XREG
} ,{0,5,XREG
}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0} },
263 {0x8400bc00,"fcmp.sxs ",{21,5,REG
} ,{16,5,XREG
} ,{0,5,XREG
}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0} },
264 {0x8400bd00,"fcmp.sxx ",{21,5,REG
} ,{16,5,XREG
} ,{0,5,XREG
}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0} },
266 {0x8400baa0,"fcmpu.sdd ",{21,5,REG
} ,{16,5,XREG
} ,{0,5,XREG
}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0} },
267 {0x8400ba20,"fcmpu.sds ",{21,5,REG
} ,{16,5,XREG
} ,{0,5,XREG
}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0} },
268 {0x8400bb20,"fcmpu.sdx ",{21,5,REG
} ,{16,5,XREG
} ,{0,5,XREG
}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0} },
269 {0x8400b8a0,"fcmpu.ssd ",{21,5,REG
} ,{16,5,XREG
} ,{0,5,XREG
}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0} },
270 {0x8400b820,"fcmpu.sss ",{21,5,REG
} ,{16,5,XREG
} ,{0,5,XREG
}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0} },
271 {0x8400b920,"fcmpu.ssx ",{21,5,REG
} ,{16,5,XREG
} ,{0,5,XREG
}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0} },
272 {0x8400bca0,"fcmpu.sxd ",{21,5,REG
} ,{16,5,XREG
} ,{0,5,XREG
}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0} },
273 {0x8400bc20,"fcmpu.sxs ",{21,5,REG
} ,{16,5,XREG
} ,{0,5,XREG
}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0} },
274 {0x8400bd20,"fcmpu.sxx ",{21,5,REG
} ,{16,5,XREG
} ,{0,5,XREG
}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0} },
276 {0x84000820,"fcvt.sd ",{21,5,REG
} ,{0,5,REG
} ,NO_OPERAND
, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0} },
277 {0x84000880,"fcvt.ds ",{21,5,REG
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, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0} },
279 {0x84008880,"fcvt.ds ",{21,5,XREG
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, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0} },
280 {0x840088c0,"fcvt.dx ",{21,5,XREG
} ,{0,5,XREG
} ,NO_OPERAND
, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0} },
281 {0x84008820,"fcvt.sd ",{21,5,XREG
} ,{0,5,XREG
} ,NO_OPERAND
, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0} },
282 {0x84008840,"fcvt.sx ",{21,5,XREG
} ,{0,5,XREG
} ,NO_OPERAND
, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0} },
283 {0x84008920,"fcvt.xd ",{21,5,XREG
} ,{0,5,XREG
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, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0} },
284 {0x84008900,"fcvt.xs ",{21,5,XREG
} ,{0,5,XREG
} ,NO_OPERAND
, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0} },
286 {0x8400f2a0,"fdiv.ddd ",{21,5,XREG
} ,{16,5,XREG
} ,{0,5,XREG
}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0} },
287 {0x8400f280,"fdiv.dds ",{21,5,XREG
} ,{16,5,XREG
} ,{0,5,XREG
}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0} },
288 {0x8400f2c0,"fdiv.ddx ",{21,5,XREG
} ,{16,5,XREG
} ,{0,5,XREG
}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0} },
289 {0x8400f220,"fdiv.dsd ",{21,5,XREG
} ,{16,5,XREG
} ,{0,5,XREG
}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0} },
290 {0x8400f200,"fdiv.dss ",{21,5,XREG
} ,{16,5,XREG
} ,{0,5,XREG
}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0} },
291 {0x8400f240,"fdiv.dsx ",{21,5,XREG
} ,{16,5,XREG
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}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0} },
292 {0x8400f320,"fdiv.dxd ",{21,5,XREG
} ,{16,5,XREG
} ,{0,5,XREG
}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0} },
293 {0x8400f300,"fdiv.dxs ",{21,5,XREG
} ,{16,5,XREG
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}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0} },
294 {0x8400f340,"fdiv.dxx ",{21,5,XREG
} ,{16,5,XREG
} ,{0,5,XREG
}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0} },
295 {0x8400f0a0,"fdiv.sdd ",{21,5,XREG
} ,{16,5,XREG
} ,{0,5,XREG
}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0} },
296 {0x8400f080,"fdiv.sds ",{21,5,XREG
} ,{16,5,XREG
} ,{0,5,XREG
}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0} },
297 {0x8400f0c0,"fdiv.sdx ",{21,5,XREG
} ,{16,5,XREG
} ,{0,5,XREG
}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0} },
298 {0x8400f020,"fdiv.ssd ",{21,5,XREG
} ,{16,5,XREG
} ,{0,5,XREG
}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0} },
299 {0x8400f000,"fdiv.sss ",{21,5,XREG
} ,{16,5,XREG
} ,{0,5,XREG
}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0} },
300 {0x8400f040,"fdiv.ssx ",{21,5,XREG
} ,{16,5,XREG
} ,{0,5,XREG
}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0} },
301 {0x8400f120,"fdiv.sxd ",{21,5,XREG
} ,{16,5,XREG
} ,{0,5,XREG
}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0} },
302 {0x8400f100,"fdiv.sxs ",{21,5,XREG
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}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0} },
303 {0x8400f140,"fdiv.sxx ",{21,5,XREG
} ,{16,5,XREG
} ,{0,5,XREG
}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0} },
304 {0x8400f4a0,"fdiv.xdd ",{21,5,XREG
} ,{16,5,XREG
} ,{0,5,XREG
}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0} },
305 {0x8400f480,"fdiv.xds ",{21,5,XREG
} ,{16,5,XREG
} ,{0,5,XREG
}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0} },
306 {0x8400f4c0,"fdiv.xdx ",{21,5,XREG
} ,{16,5,XREG
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}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0} },
307 {0x8400f420,"fdiv.xsd ",{21,5,XREG
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} ,{0,5,XREG
}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0} },
308 {0x8400f400,"fdiv.xss ",{21,5,XREG
} ,{16,5,XREG
} ,{0,5,XREG
}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0} },
309 {0x8400f440,"fdiv.xsx ",{21,5,XREG
} ,{16,5,XREG
} ,{0,5,XREG
}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0} },
310 {0x8400f520,"fdiv.xxd ",{21,5,XREG
} ,{16,5,XREG
} ,{0,5,XREG
}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0} },
311 {0x8400f500,"fdiv.xxs ",{21,5,XREG
} ,{16,5,XREG
} ,{0,5,XREG
}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0} },
312 {0x8400f540,"fdiv.xxx ",{21,5,XREG
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314 {0x84002220,"flt.ds ",{21,5,XREG
} ,{0,5,REG
} ,NO_OPERAND
, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0} },
315 {0x84002200,"flt.ss ",{21,5,XREG
} ,{0,5,REG
} ,NO_OPERAND
, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0} },
316 {0x84002240,"flt.xs ",{21,5,XREG
} ,{0,5,REG
} ,NO_OPERAND
, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0} },
318 {0x840082a0,"fmul.ddd ",{21,5,XREG
} ,{16,5,XREG
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}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0} },
319 {0x84008280,"fmul.dds ",{21,5,XREG
} ,{16,5,XREG
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}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0} },
320 {0x840082c0,"fmul.ddx ",{21,5,XREG
} ,{16,5,XREG
} ,{0,5,XREG
}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0} },
321 {0x84008220,"fmul.dsd ",{21,5,XREG
} ,{16,5,XREG
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322 {0x84008200,"fmul.dss ",{21,5,XREG
} ,{16,5,XREG
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323 {0x84008240,"fmul.dsx ",{21,5,XREG
} ,{16,5,XREG
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324 {0x84008320,"fmul.dxd ",{21,5,XREG
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325 {0x84008300,"fmul.dxs ",{21,5,XREG
} ,{16,5,XREG
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}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0} },
326 {0x84008340,"fmul.dxx ",{21,5,XREG
} ,{16,5,XREG
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327 {0x840080a0,"fmul.sdd ",{21,5,XREG
} ,{16,5,XREG
} ,{0,5,XREG
}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0} },
328 {0x84008080,"fmul.sds ",{21,5,XREG
} ,{16,5,XREG
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}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0} },
329 {0x840080c0,"fmul.sdx ",{21,5,XREG
} ,{16,5,XREG
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}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0} },
330 {0x84008020,"fmul.ssd ",{21,5,XREG
} ,{16,5,XREG
} ,{0,5,XREG
}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0} },
331 {0x84008000,"fmul.sss ",{21,5,XREG
} ,{16,5,XREG
} ,{0,5,XREG
}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0} },
332 {0x84008040,"fmul.ssx ",{21,5,XREG
} ,{16,5,XREG
} ,{0,5,XREG
}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0} },
333 {0x84008120,"fmul.sxd ",{21,5,XREG
} ,{16,5,XREG
} ,{0,5,XREG
}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0} },
334 {0x84008100,"fmul.sxs ",{21,5,XREG
} ,{16,5,XREG
} ,{0,5,XREG
}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0} },
335 {0x84008140,"fmul.sxx ",{21,5,XREG
} ,{16,5,XREG
} ,{0,5,XREG
}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0} },
336 {0x840084a0,"fmul.xdd ",{21,5,XREG
} ,{16,5,XREG
} ,{0,5,XREG
}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0} },
337 {0x84008480,"fmul.xds ",{21,5,XREG
} ,{16,5,XREG
} ,{0,5,XREG
}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0} },
338 {0x840084c0,"fmul.xdx ",{21,5,XREG
} ,{16,5,XREG
} ,{0,5,XREG
}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0} },
339 {0x84008420,"fmul.xsd ",{21,5,XREG
} ,{16,5,XREG
} ,{0,5,XREG
}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0} },
340 {0x84008400,"fmul.xss ",{21,5,XREG
} ,{16,5,XREG
} ,{0,5,XREG
}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0} },
341 {0x84008440,"fmul.xsx ",{21,5,XREG
} ,{16,5,XREG
} ,{0,5,XREG
}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0} },
342 {0x84008520,"fmul.xxd ",{21,5,XREG
} ,{16,5,XREG
} ,{0,5,XREG
}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0} },
343 {0x84008500,"fmul.xxs ",{21,5,XREG
} ,{16,5,XREG
} ,{0,5,XREG
}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0} },
344 {0x84008540,"fmul.xxx ",{21,5,XREG
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}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0} },
346 {0x8400f8a0,"fsqrt.dd ",{21,5,XREG
}, {0,5,XREG
}, NO_OPERAND
, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0} },
347 {0x8400f880,"fsqrt.ds ",{21,5,XREG
}, {0,5,XREG
}, NO_OPERAND
, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0} },
348 {0x8400f8c0,"fsqrt.dx ",{21,5,XREG
}, {0,5,XREG
}, NO_OPERAND
, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0} },
349 {0x8400f820,"fsqrt.sd ",{21,5,XREG
}, {0,5,XREG
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, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0} },
350 {0x8400f800,"fsqrt.ss ",{21,5,XREG
}, {0,5,XREG
}, NO_OPERAND
, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0} },
351 {0x8400f840,"fsqrt.sx ",{21,5,XREG
}, {0,5,XREG
}, NO_OPERAND
, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0} },
352 {0x8400f920,"fsqrt.xd ",{21,5,XREG
}, {0,5,XREG
}, NO_OPERAND
, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0} },
353 {0x8400f900,"fsqrt.xs ",{21,5,XREG
}, {0,5,XREG
}, NO_OPERAND
, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0} },
354 {0x8400f940,"fsqrt.xx ",{21,5,XREG
}, {0,5,XREG
}, NO_OPERAND
, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0} },
356 {0x8400b2a0,"fsub.ddd ",{21,5,XREG
} ,{16,5,XREG
} ,{0,5,XREG
}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0} },
357 {0x8400b280,"fsub.dds ",{21,5,XREG
} ,{16,5,XREG
} ,{0,5,XREG
}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0} },
358 {0x8400b2c0,"fsub.ddx ",{21,5,XREG
} ,{16,5,XREG
} ,{0,5,XREG
}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0} },
359 {0x8400b220,"fsub.dsd ",{21,5,XREG
} ,{16,5,XREG
} ,{0,5,XREG
}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0} },
360 {0x8400b200,"fsub.dss ",{21,5,XREG
} ,{16,5,XREG
} ,{0,5,XREG
}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0} },
361 {0x8400b240,"fsub.dsx ",{21,5,XREG
} ,{16,5,XREG
} ,{0,5,XREG
}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0} },
362 {0x8400b320,"fsub.dxd ",{21,5,XREG
} ,{16,5,XREG
} ,{0,5,XREG
}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0} },
363 {0x8400b300,"fsub.dxs ",{21,5,XREG
} ,{16,5,XREG
} ,{0,5,XREG
}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0} },
364 {0x8400b340,"fsub.dxx ",{21,5,XREG
} ,{16,5,XREG
} ,{0,5,XREG
}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0} },
365 {0x8400b0a0,"fsub.sdd ",{21,5,XREG
} ,{16,5,XREG
} ,{0,5,XREG
}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0} },
366 {0x8400b080,"fsub.sds ",{21,5,XREG
} ,{16,5,XREG
} ,{0,5,XREG
}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0} },
367 {0x8400b0c0,"fsub.sdx ",{21,5,XREG
} ,{16,5,XREG
} ,{0,5,XREG
}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0} },
368 {0x8400b020,"fsub.ssd ",{21,5,XREG
} ,{16,5,XREG
} ,{0,5,XREG
}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0} },
369 {0x8400b000,"fsub.sss ",{21,5,XREG
} ,{16,5,XREG
} ,{0,5,XREG
}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0} },
370 {0x8400b040,"fsub.ssx ",{21,5,XREG
} ,{16,5,XREG
} ,{0,5,XREG
}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0} },
371 {0x8400b120,"fsub.sxd ",{21,5,XREG
} ,{16,5,XREG
} ,{0,5,XREG
}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0} },
372 {0x8400b100,"fsub.sxs ",{21,5,XREG
} ,{16,5,XREG
} ,{0,5,XREG
}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0} },
373 {0x8400b140,"fsub.sxx ",{21,5,XREG
} ,{16,5,XREG
} ,{0,5,XREG
}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0} },
374 {0x8400b4a0,"fsub.xdd ",{21,5,XREG
} ,{16,5,XREG
} ,{0,5,XREG
}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0} },
375 {0x8400b480,"fsub.xds ",{21,5,XREG
} ,{16,5,XREG
} ,{0,5,XREG
}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0} },
376 {0x8400b4c0,"fsub.xdx ",{21,5,XREG
} ,{16,5,XREG
} ,{0,5,XREG
}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0} },
377 {0x8400b420,"fsub.xsd ",{21,5,XREG
} ,{16,5,XREG
} ,{0,5,XREG
}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0} },
378 {0x8400b400,"fsub.xss ",{21,5,XREG
} ,{16,5,XREG
} ,{0,5,XREG
}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0} },
379 {0x8400b440,"fsub.xsx ",{21,5,XREG
} ,{16,5,XREG
} ,{0,5,XREG
}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0} },
380 {0x8400b520,"fsub.xxd ",{21,5,XREG
} ,{16,5,XREG
} ,{0,5,XREG
}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0} },
381 {0x8400b500,"fsub.xxs ",{21,5,XREG
} ,{16,5,XREG
} ,{0,5,XREG
}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0} },
382 {0x8400b540,"fsub.xxx ",{21,5,XREG
} ,{16,5,XREG
} ,{0,5,XREG
}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0} },
384 {0x8400fc00,"illop", {0,2,DEC
}, NO_OPERAND
, NO_OPERAND
, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0} },
386 {0x8400c800,"int.ss ", {21,5,REG
}, {0,5,XREG
}, NO_OPERAND
, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0} },
387 {0x8400c880,"int.sd ", {21,5,REG
}, {0,5,XREG
}, NO_OPERAND
, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0} },
388 {0x8400c900,"int.sx ", {21,5,REG
}, {0,5,XREG
}, NO_OPERAND
, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0} },
390 {0x04000000,"ld ", {21,5,XREG
}, {16,5,REG
}, {0,16,HEX
}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0} },
391 {0x00000000,"ld.d ", {21,5,XREG
}, {16,5,REG
}, {0,16,HEX
}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0} },
392 {0x3c000000,"ld.x ", {21,5,XREG
}, {16,5,REG
}, {0,16,HEX
}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0} },
394 {0xf0001400,"ld ", {21,5,XREG
}, {16,5,REG
}, {0,5,REG
}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0} },
395 {0xf0001000,"ld.d ", {21,5,XREG
}, {16,5,REG
}, {0,5,REG
}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0} },
396 {0xf0001800,"ld.x ", {21,5,XREG
}, {16,5,REG
}, {0,5,REG
}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0} },
397 {0xf0001500,"ld.usr ", {21,5,XREG
}, {16,5,REG
}, {0,5,REG
}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0} },
398 {0xf0001100,"ld.d.usr ", {21,5,XREG
}, {16,5,REG
}, {0,5,REG
}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0} },
399 {0xf0001900,"ld.x.usr ", {21,5,XREG
}, {16,5,REG
}, {0,5,REG
}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0} },
401 {0xf0001600,"ld ", {21,5,XREG
}, {16,5,REG
}, {0,5,REGSC
}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0} },
402 {0xf0001200,"ld.d ", {21,5,XREG
}, {16,5,REG
}, {0,5,REGSC
}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0} },
403 {0xf0001a00,"ld.x ", {21,5,XREG
}, {16,5,REG
}, {0,5,REGSC
}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0} },
404 {0xf0001700,"ld.usr ", {21,5,XREG
}, {16,5,REG
}, {0,5,REGSC
}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0} },
405 {0xf0001300,"ld.d.usr ", {21,5,XREG
}, {16,5,REG
}, {0,5,REGSC
}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0} },
406 {0xf0001b00,"ld.x.usr ", {21,5,XREG
}, {16,5,REG
}, {0,5,REGSC
}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0} },
408 {0x8400c000,"mov.s ", {21,5,REG
}, {0,5,XREG
}, NO_OPERAND
, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0} },
409 {0x8400c080,"mov.d ", {21,5,REG
}, {0,5,XREG
}, NO_OPERAND
, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0} },
410 {0x84004200,"mov.s ", {21,5,XREG
}, {0,5,REG
}, NO_OPERAND
, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0} },
411 {0x84004280,"mov.d ", {21,5,XREG
}, {0,5,REG
}, NO_OPERAND
, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0} },
412 {0x8400c300,"mov ", {21,5,XREG
}, {0,5,XREG
}, NO_OPERAND
, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0} },
414 {0xf4006d00,"mulu.d ", {21,5,REG
}, {16,5,REG
}, {0,5,REG
}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0} },
416 {0x8400d080,"nint.sd ", {21,5,REG
}, {0,5,XREG
}, NO_OPERAND
, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0} },
417 {0x8400d000,"nint.ss ", {21,5,REG
}, {0,5,XREG
}, NO_OPERAND
, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0} },
418 {0x8400d100,"nint.sx ", {21,5,REG
}, {0,5,XREG
}, NO_OPERAND
, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0} },
420 {0x88002020,"padd.b ", {21,5,REG
}, {16,5,REG
}, {0,5,REG
}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0} },
421 {0x88002040,"padd.h ", {21,5,REG
}, {16,5,REG
}, {0,5,REG
}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0} },
422 {0x88002060,"padd ", {21,5,REG
}, {16,5,REG
}, {0,5,REG
}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0} },
424 {0x880021e0,"padds.s ", {21,5,REG
}, {16,5,REG
}, {0,5,REG
}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0} },
425 {0x880021a0,"padds.s.b ", {21,5,REG
}, {16,5,REG
}, {0,5,REG
}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0} },
426 {0x880021c0,"padds.s.h ", {21,5,REG
}, {16,5,REG
}, {0,5,REG
}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0} },
427 {0x880020e0,"padds.u ", {21,5,REG
}, {16,5,REG
}, {0,5,REG
}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0} },
428 {0x880020a0,"padds.u.b ", {21,5,REG
}, {16,5,REG
}, {0,5,REG
}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0} },
429 {0x880020c0,"padds.u.h ", {21,5,REG
}, {16,5,REG
}, {0,5,REG
}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0} },
430 {0x88002160,"padds.us ", {21,5,REG
}, {16,5,REG
}, {0,5,REG
}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0} },
431 {0x88002120,"padds.us.b ", {21,5,REG
}, {16,5,REG
}, {0,5,REG
}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0} },
432 {0x88002140,"padds.us.h ", {21,5,REG
}, {16,5,REG
}, {0,5,REG
}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0} },
434 {0x88003860,"pcmp ", {21,5,REG
}, {16,5,REG
}, {0,5,REG
}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0} },
436 {0x88000000,"pmul ", {21,5,REG
}, {16,5,REG
}, {0,5,REG
}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0} },
438 {0x88006260,"ppack.16 ", {21,5,REG
}, {16,5,REG
}, {0,5,REG
}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0} },
439 {0x88006240,"ppack.16.h ", {21,5,REG
}, {16,5,REG
}, {0,5,REG
}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0} },
440 {0x88006460,"ppack.32 ", {21,5,REG
}, {16,5,REG
}, {0,5,REG
}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0} },
441 {0x88006420,"ppack.32.b ", {21,5,REG
}, {16,5,REG
}, {0,5,REG
}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0} },
442 {0x88006440,"ppack.32.h ", {21,5,REG
}, {16,5,REG
}, {0,5,REG
}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0} },
443 {0x88006160,"ppack.8 ", {21,5,REG
}, {16,5,REG
}, {0,5,REG
}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0} },
445 {0x88007200,"prot ", {21,5,REG
}, {16,5,REG
}, {5,6,HEX
}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0} },
446 {0x88007800,"prot ", {21,5,REG
}, {16,5,REG
}, {0,5,REG
}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0} },
448 {0x88003020,"psub.b ", {21,5,REG
}, {16,5,REG
}, {0,5,REG
}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0} },
449 {0x88003040,"psub.h ", {21,5,REG
}, {16,5,REG
}, {0,5,REG
}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0} },
450 {0x88003060,"psub ", {21,5,REG
}, {16,5,REG
}, {0,5,REG
}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0} },
452 {0x880031e0,"psubs.s ", {21,5,REG
}, {16,5,REG
}, {0,5,REG
}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0} },
453 {0x880031a0,"psubs.s.b ", {21,5,REG
}, {16,5,REG
}, {0,5,REG
}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0} },
454 {0x880031c0,"psubs.s.h ", {21,5,REG
}, {16,5,REG
}, {0,5,REG
}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0} },
455 {0x880030e0,"psubs.u ", {21,5,REG
}, {16,5,REG
}, {0,5,REG
}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0} },
456 {0x880030a0,"psubs.u.b ", {21,5,REG
}, {16,5,REG
}, {0,5,REG
}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0} },
457 {0x880030c0,"psubs.u.h ", {21,5,REG
}, {16,5,REG
}, {0,5,REG
}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0} },
458 {0x88003160,"psubs.us ", {21,5,REG
}, {16,5,REG
}, {0,5,REG
}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0} },
459 {0x88003120,"psubs.us.b ", {21,5,REG
}, {16,5,REG
}, {0,5,REG
}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0} },
460 {0x88003140,"psubs.us.h ", {21,5,REG
}, {16,5,REG
}, {0,5,REG
}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0} },
462 {0x88006800,"punpk.n ", {21,5,REG
}, {16,5,REG
}, NO_OPERAND
, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0} },
463 {0x88006820,"punpk.b ", {21,5,REG
}, {16,5,REG
}, NO_OPERAND
, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0} },
465 {0x34000000,"st ", {21,5,XREG
}, {16,5,REG
}, {0,16,HEX
}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0} },
466 {0x30000000,"st.d ", {21,5,XREG
}, {16,5,REG
}, {0,16,HEX
}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0} },
467 {0x38000000,"st.x ", {21,5,XREG
}, {16,5,REG
}, {0,16,HEX
}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0} },
469 {0xf4002c80,"st.b.wt ", {21,5,REG
}, {16,5,REG
}, {0,5,REG
}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0} },
470 {0xf4002880,"st.h.wt ", {21,5,REG
}, {16,5,REG
}, {0,5,REG
}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0} },
471 {0xf4002480,"st.wt ", {21,5,REG
}, {16,5,REG
}, {0,5,REG
}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0} },
472 {0xf4002080,"st.d.wt ", {21,5,REG
}, {16,5,REG
}, {0,5,REG
}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0} },
473 {0xf4002d80,"st.b.usr.wt ", {21,5,REG
}, {16,5,REG
}, {0,5,REG
}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0} },
474 {0xf4002980,"st.h.usr.wt ", {21,5,REG
}, {16,5,REG
}, {0,5,REG
}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0} },
475 {0xf4002580,"st.usr.wt ", {21,5,REG
}, {16,5,REG
}, {0,5,REG
}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0} },
476 {0xf4002180,"st.d.usr.wt ", {21,5,REG
}, {16,5,REG
}, {0,5,REG
}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0} },
478 {0xf0002400,"st ", {21,5,XREG
}, {16,5,REG
}, {0,5,REG
}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0} },
479 {0xf0002000,"st.d ", {21,5,XREG
}, {16,5,REG
}, {0,5,REG
}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0} },
480 {0xf0002100,"st.d.usr ", {21,5,XREG
}, {16,5,REG
}, {0,5,REG
}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0} },
481 {0xf0002180,"st.d.usr.wt ", {21,5,XREG
}, {16,5,REG
}, {0,5,REG
}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0} },
482 {0xf0002080,"st.d.wt ", {21,5,XREG
}, {16,5,REG
}, {0,5,REG
}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0} },
483 {0xf0002500,"st.usr ", {21,5,XREG
}, {16,5,REG
}, {0,5,REG
}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0} },
484 {0xf0002580,"st.usr.wt ", {21,5,XREG
}, {16,5,REG
}, {0,5,REG
}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0} },
485 {0xf0002480,"st.wt ", {21,5,XREG
}, {16,5,REG
}, {0,5,REG
}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0} },
486 {0xf0002800,"st.x ", {21,5,XREG
}, {16,5,REG
}, {0,5,REG
}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0} },
487 {0xf0002900,"st.x.usr ", {21,5,XREG
}, {16,5,REG
}, {0,5,REG
}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0} },
488 {0xf0002980,"st.x.usr.wt ", {21,5,XREG
}, {16,5,REG
}, {0,5,REG
}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0} },
489 {0xf0002880,"st.x.wt ", {21,5,XREG
}, {16,5,REG
}, {0,5,REG
}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0} },
491 {0xf4002f80,"st.b.usr.wt ", {21,5,REG
}, {16,5,REG
}, {0,5,REGSC
}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0} },
492 {0xf4002e80,"st.b.wt ", {21,5,REG
}, {16,5,REG
}, {0,5,REGSC
}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0} },
493 {0xf4002380,"st.d.usr.wt ", {21,5,REG
}, {16,5,REG
}, {0,5,REGSC
}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0} },
494 {0xf4002280,"st.d.wt ", {21,5,REG
}, {16,5,REG
}, {0,5,REGSC
}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0} },
495 {0xf4002b80,"st.h.usr.wt ", {21,5,REG
}, {16,5,REG
}, {0,5,REGSC
}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0} },
496 {0xf4002a80,"st.h.wt ", {21,5,REG
}, {16,5,REG
}, {0,5,REGSC
}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0} },
497 {0xf4002780,"st.usr.wt ", {21,5,REG
}, {16,5,REG
}, {0,5,REGSC
}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0} },
498 {0xf4002680,"st.wt ", {21,5,REG
}, {16,5,REG
}, {0,5,REGSC
}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0} },
500 {0xf0002600,"st ", {21,5,XREG
}, {16,5,REG
}, {0,5,REGSC
}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0} },
501 {0xf0002200,"st.d ", {21,5,XREG
}, {16,5,REG
}, {0,5,REGSC
}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0} },
502 {0xf0002300,"st.d.usr ", {21,5,XREG
}, {16,5,REG
}, {0,5,REGSC
}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0} },
503 {0xf0002380,"st.d.usr.wt ", {21,5,XREG
}, {16,5,REG
}, {0,5,REGSC
}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0} },
504 {0xf0002280,"st.d.wt ", {21,5,XREG
}, {16,5,REG
}, {0,5,REGSC
}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0} },
505 {0xf0002700,"st.usr ", {21,5,XREG
}, {16,5,REG
}, {0,5,REGSC
}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0} },
506 {0xf0002780,"st.usr.wt ", {21,5,XREG
}, {16,5,REG
}, {0,5,REGSC
}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0} },
507 {0xf0002680,"st.wt ", {21,5,XREG
}, {16,5,REG
}, {0,5,REGSC
}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0} },
508 {0xf0002a00,"st.x ", {21,5,XREG
}, {16,5,REG
}, {0,5,REGSC
}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0} },
509 {0xf0002b00,"st.x.usr ", {21,5,XREG
}, {16,5,REG
}, {0,5,REGSC
}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0} },
510 {0xf0002b80,"st.x.usr.wt ", {21,5,XREG
}, {16,5,REG
}, {0,5,REGSC
}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0} },
511 {0xf0002a80,"st.x.wt ", {21,5,XREG
}, {16,5,REG
}, {0,5,REGSC
}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0} },
513 {0x8400d880,"trnc.sd ", {21,5,REG
}, {0,5,XREG
}, NO_OPERAND
, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0} },
514 {0x8400d800,"trnc.ss ", {21,5,REG
}, {0,5,XREG
}, NO_OPERAND
, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0} },
515 {0x8400d900,"trnc.sx ", {21,5,REG
}, {0,5,XREG
}, NO_OPERAND
, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0} },
519 HASHTAB
*hashtable
[HASHVAL
] = {0};
522 m88kdis
PARAMS ((bfd_vma
, unsigned long, struct disassemble_info
*));
525 printop
PARAMS ((struct disassemble_info
*, const OPSPEC
*, unsigned long, bfd_vma
, int));
528 init_disasm
PARAMS ((void));
531 /* Disassemble an M88000 instruction at `memaddr'. */
534 print_insn_m88k (memaddr
, info
)
536 struct disassemble_info
*info
;
541 /* Instruction addresses may have low two bits set. Clear them. */
542 memaddr
&=~ (bfd_vma
) 3;
544 status
= (*info
->read_memory_func
) (memaddr
, buffer
, 4, info
);
547 (*info
->memory_error_func
) (status
, memaddr
, info
);
551 return m88kdis (memaddr
, bfd_getb32 (buffer
), info
);
555 * Disassemble the instruction in `instruction'.
556 * `pc' should be the address of this instruction, it will be used to
557 * print the target address if this is a relative jump or call the
558 * disassembled instruction is written to `info'.
560 * The function returns the length of this instruction in bytes.
564 m88kdis (pc
, instruction
, info
)
566 unsigned long instruction
;
567 struct disassemble_info
*info
;
569 static int ihashtab_initialized
= 0;
571 const HASHTAB
*entry_ptr
;
575 if (! ihashtab_initialized
)
578 ihashtab_initialized
= 1;
581 /* Create the appropriate mask to isolate the opcode. */
583 class = instruction
& DEFMASK
;
584 if ((class >= SFU0
) && (class <= SFU7
))
586 if (instruction
< SFU1
)
591 else if (class == RRR
)
593 else if (class == RRI10
)
596 /* Isolate the opcode. */
597 opcode
= instruction
& opmask
;
599 /* Search the hash table with the isolated opcode. */
600 for (entry_ptr
= hashtable
[opcode
% HASHVAL
];
601 (entry_ptr
!= NULL
) && (entry_ptr
->instr
->opcode
!= opcode
);
602 entry_ptr
= entry_ptr
->next
)
605 if (entry_ptr
== NULL
)
606 (*info
->fprintf_func
) (info
->stream
, "word\t%08x", instruction
);
609 (*info
->fprintf_func
) (info
->stream
, "%s", entry_ptr
->instr
->mnemonic
);
610 printop (info
, &(entry_ptr
->instr
->op1
), instruction
, pc
, 1);
611 printop (info
, &(entry_ptr
->instr
->op2
), instruction
, pc
, 0);
612 printop (info
, &(entry_ptr
->instr
->op3
), instruction
, pc
, 0);
619 * Decode an Operand of an instruction.
621 * This function formats and writes an operand of an instruction to
622 * info based on the operand specification. When the `first' flag is
623 * set this is the first operand of an instruction. Undefined operand
624 * types cause a <dis error> message.
627 * disassemble_info where the operand may be printed
628 * OPSPEC *opptr pointer to an operand specification
629 * UINT inst instruction from which operand is extracted
630 * UINT pc pc of instruction; used for pc-relative disp.
631 * int first flag which if nonzero indicates the first
632 * operand of an instruction
634 * The operand specified is extracted from the instruction and is
635 * written to buf in the format specified. The operand is preceded by
636 * a comma if it is not the first operand of an instruction and it is
637 * not a register indirect form. Registers are preceded by 'r' and
638 * hex values by '0x'.
642 printop (info
, opptr
, inst
, pc
, first
)
643 struct disassemble_info
*info
;
652 if (opptr
->width
== 0)
663 (*info
->fprintf_func
) (info
->stream
, ",");
671 (*info
->fprintf_func
) (info
->stream
, "cr%d",
672 UEXT (inst
, opptr
->offset
, opptr
->width
));
676 (*info
->fprintf_func
) (info
->stream
, "fcr%d",
677 UEXT (inst
, opptr
->offset
, opptr
->width
));
681 (*info
->fprintf_func
) (info
->stream
, "[r%d]",
682 UEXT (inst
, opptr
->offset
, opptr
->width
));
686 (*info
->fprintf_func
) (info
->stream
, "r%d",
687 UEXT (inst
, opptr
->offset
, opptr
->width
));
691 (*info
->fprintf_func
) (info
->stream
, "x%d",
692 UEXT (inst
, opptr
->offset
, opptr
->width
));
696 extracted_field
= UEXT (inst
, opptr
->offset
, opptr
->width
);
697 if (extracted_field
== 0)
698 (*info
->fprintf_func
) (info
->stream
, "0");
700 (*info
->fprintf_func
) (info
->stream
, "0x%02x", extracted_field
);
704 extracted_field
= UEXT (inst
, opptr
->offset
, opptr
->width
);
705 (*info
->fprintf_func
) (info
->stream
, "%d", extracted_field
);
709 extracted_field
= UEXT (inst
, opptr
->offset
, opptr
->width
);
710 switch (extracted_field
& 0x0f)
712 case 0x1: cond_mask_sym
= "gt0"; break;
713 case 0x2: cond_mask_sym
= "eq0"; break;
714 case 0x3: cond_mask_sym
= "ge0"; break;
715 case 0xc: cond_mask_sym
= "lt0"; break;
716 case 0xd: cond_mask_sym
= "ne0"; break;
717 case 0xe: cond_mask_sym
= "le0"; break;
718 default: cond_mask_sym
= NULL
; break;
720 if (cond_mask_sym
!= NULL
)
721 (*info
->fprintf_func
) (info
->stream
, "%s", cond_mask_sym
);
723 (*info
->fprintf_func
) (info
->stream
, "%x", extracted_field
);
727 (*info
->print_address_func
)
728 (pc
+ (4 * (SEXT (inst
, opptr
->offset
, opptr
->width
))),
733 (*info
->fprintf_func
) (info
->stream
, "%d,r%d",
734 UEXT (inst
, opptr
->offset
, 5),
735 UEXT (inst
, (opptr
->offset
) + 5, 5));
739 (*info
->fprintf_func
) (info
->stream
, "%d<%d>",
740 UEXT (inst
, (opptr
->offset
) + 5, 5),
741 UEXT (inst
, opptr
->offset
, 5));
745 /* xgettext:c-format */
746 (*info
->fprintf_func
) (info
->stream
, _("# <dis error: %08x>"), inst
);
751 * Initialize the disassembler instruction table.
753 * Initialize the hash table and instruction table for the
754 * disassembler. This should be called once before the first call to
761 unsigned int hashvalue
, hashsize
;
762 struct HASHTAB
*hashentries
;
765 hashsize
= sizeof (instructions
) / sizeof (INSTAB
);
767 hashentries
= (struct HASHTAB
*) xmalloc (hashsize
* sizeof (struct HASHTAB
));
769 for (i
= 0; i
< HASHVAL
; i
++)
772 for (i
= 0; i
< hashsize
; i
++)
774 hashvalue
= (instructions
[i
].opcode
) % HASHVAL
;
775 hashentries
[i
].instr
= &instructions
[i
];
776 hashentries
[i
].next
= hashtable
[hashvalue
];
777 hashtable
[hashvalue
] = &hashentries
[i
];
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