opcodes/mep-desc.c

   1 /* CPU data for mep.
   2
   3 THIS FILE IS MACHINE GENERATED WITH CGEN.
   4
   5 Copyright 1996-2007 Free Software Foundation, Inc.
   6
   7 This file is part of the GNU Binutils and/or GDB, the GNU debugger.
   8
   9    This file is free software; you can redistribute it and/or modify
  10    it under the terms of the GNU General Public License as published by
  11    the Free Software Foundation; either version 3, or (at your option)
  12    any later version.
  13
  14    It is distributed in the hope that it will be useful, but WITHOUT
  15    ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  16    or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
  17    License for more details.
  18
  19    You should have received a copy of the GNU General Public License along
  20    with this program; if not, write to the Free Software Foundation, Inc.,
  21    51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
  22
  23 */
  24
  25 #include "sysdep.h"
  26 #include <stdio.h>
  27 #include <stdarg.h>
  28 #include "ansidecl.h"
  29 #include "bfd.h"
  30 #include "symcat.h"
  31 #include "mep-desc.h"
  32 #include "mep-opc.h"
  33 #include "opintl.h"
  34 #include "libiberty.h"
  35 #include "xregex.h"
  36
  37 /* Attributes.  */
  38
  39 static const CGEN_ATTR_ENTRY bool_attr[] =
  40 {
  41   { "#f", 0 },
  42   { "#t", 1 },
  43   { 0, 0 }
  44 };
  45
  46 static const CGEN_ATTR_ENTRY MACH_attr[] ATTRIBUTE_UNUSED =
  47 {
  48   { "base", MACH_BASE },
  49   { "mep", MACH_MEP },
  50   { "h1", MACH_H1 },
  51   { "c5", MACH_C5 },
  52   { "max", MACH_MAX },
  53   { 0, 0 }
  54 };
  55
  56 static const CGEN_ATTR_ENTRY ISA_attr[] ATTRIBUTE_UNUSED =
  57 {
  58   { "mep", ISA_MEP },
  59   { "ext_core1", ISA_EXT_CORE1 },
  60   { "ext_cop1_16", ISA_EXT_COP1_16 },
  61   { "ext_cop1_32", ISA_EXT_COP1_32 },
  62   { "ext_cop1_48", ISA_EXT_COP1_48 },
  63   { "ext_cop1_64", ISA_EXT_COP1_64 },
  64   { "max", ISA_MAX },
  65   { 0, 0 }
  66 };
  67
  68 static const CGEN_ATTR_ENTRY CDATA_attr[] ATTRIBUTE_UNUSED =
  69 {
  70   { "LABEL", CDATA_LABEL },
  71   { "REGNUM", CDATA_REGNUM },
  72   { "FMAX_FLOAT", CDATA_FMAX_FLOAT },
  73   { "FMAX_INT", CDATA_FMAX_INT },
  74   { "POINTER", CDATA_POINTER },
  75   { "LONG", CDATA_LONG },
  76   { "ULONG", CDATA_ULONG },
  77   { "SHORT", CDATA_SHORT },
  78   { "USHORT", CDATA_USHORT },
  79   { "CHAR", CDATA_CHAR },
  80   { "UCHAR", CDATA_UCHAR },
  81   { "CP_DATA_BUS_INT", CDATA_CP_DATA_BUS_INT },
  82   { 0, 0 }
  83 };
  84
  85 static const CGEN_ATTR_ENTRY ALIGN_attr [] ATTRIBUTE_UNUSED =
  86 {
  87   {"integer", 1},
  88   { 0, 0 }
  89 };
  90
  91 static const CGEN_ATTR_ENTRY LATENCY_attr [] ATTRIBUTE_UNUSED =
  92 {
  93   {"integer", 0},
  94   { 0, 0 }
  95 };
  96
  97 static const CGEN_ATTR_ENTRY CONFIG_attr[] ATTRIBUTE_UNUSED =
  98 {
  99   { "NONE", CONFIG_NONE },
 100   { "default", CONFIG_DEFAULT },
 101   { 0, 0 }
 102 };
 103
 104 static const CGEN_ATTR_ENTRY SLOTS_attr[] ATTRIBUTE_UNUSED =
 105 {
 106   { "core", SLOTS_CORE },
 107   { "c3", SLOTS_C3 },
 108   { "p0s", SLOTS_P0S },
 109   { "p0", SLOTS_P0 },
 110   { "p1", SLOTS_P1 },
 111   { 0, 0 }
 112 };
 113
 114 const CGEN_ATTR_TABLE mep_cgen_ifield_attr_table[] =
 115 {
 116   { "MACH", & MACH_attr[0], & MACH_attr[0] },
 117   { "ISA", & ISA_attr[0], & ISA_attr[0] },
 118   { "VIRTUAL", &bool_attr[0], &bool_attr[0] },
 119   { "PCREL-ADDR", &bool_attr[0], &bool_attr[0] },
 120   { "ABS-ADDR", &bool_attr[0], &bool_attr[0] },
 121   { "RESERVED", &bool_attr[0], &bool_attr[0] },
 122   { "SIGN-OPT", &bool_attr[0], &bool_attr[0] },
 123   { "SIGNED", &bool_attr[0], &bool_attr[0] },
 124   { 0, 0, 0 }
 125 };
 126
 127 const CGEN_ATTR_TABLE mep_cgen_hardware_attr_table[] =
 128 {
 129   { "MACH", & MACH_attr[0], & MACH_attr[0] },
 130   { "ISA", & ISA_attr[0], & ISA_attr[0] },
 131   { "VIRTUAL", &bool_attr[0], &bool_attr[0] },
 132   { "CACHE-ADDR", &bool_attr[0], &bool_attr[0] },
 133   { "PC", &bool_attr[0], &bool_attr[0] },
 134   { "PROFILE", &bool_attr[0], &bool_attr[0] },
 135   { "IS_FLOAT", &bool_attr[0], &bool_attr[0] },
 136   { 0, 0, 0 }
 137 };
 138
 139 const CGEN_ATTR_TABLE mep_cgen_operand_attr_table[] =
 140 {
 141   { "MACH", & MACH_attr[0], & MACH_attr[0] },
 142   { "ISA", & ISA_attr[0], & ISA_attr[0] },
 143   { "CDATA", & CDATA_attr[0], & CDATA_attr[0] },
 144   { "ALIGN", & ALIGN_attr[0], & ALIGN_attr[0] },
 145   { "VIRTUAL", &bool_attr[0], &bool_attr[0] },
 146   { "PCREL-ADDR", &bool_attr[0], &bool_attr[0] },
 147   { "ABS-ADDR", &bool_attr[0], &bool_attr[0] },
 148   { "SIGN-OPT", &bool_attr[0], &bool_attr[0] },
 149   { "SIGNED", &bool_attr[0], &bool_attr[0] },
 150   { "NEGATIVE", &bool_attr[0], &bool_attr[0] },
 151   { "RELAX", &bool_attr[0], &bool_attr[0] },
 152   { "SEM-ONLY", &bool_attr[0], &bool_attr[0] },
 153   { "RELOC_IMPLIES_OVERFLOW", &bool_attr[0], &bool_attr[0] },
 154   { 0, 0, 0 }
 155 };
 156
 157 const CGEN_ATTR_TABLE mep_cgen_insn_attr_table[] =
 158 {
 159   { "MACH", & MACH_attr[0], & MACH_attr[0] },
 160   { "ISA", & ISA_attr[0], & ISA_attr[0] },
 161   { "LATENCY", & LATENCY_attr[0], & LATENCY_attr[0] },
 162   { "CONFIG", & CONFIG_attr[0], & CONFIG_attr[0] },
 163   { "SLOTS", & SLOTS_attr[0], & SLOTS_attr[0] },
 164   { "ALIAS", &bool_attr[0], &bool_attr[0] },
 165   { "VIRTUAL", &bool_attr[0], &bool_attr[0] },
 166   { "UNCOND-CTI", &bool_attr[0], &bool_attr[0] },
 167   { "COND-CTI", &bool_attr[0], &bool_attr[0] },
 168   { "SKIP-CTI", &bool_attr[0], &bool_attr[0] },
 169   { "DELAY-SLOT", &bool_attr[0], &bool_attr[0] },
 170   { "RELAXABLE", &bool_attr[0], &bool_attr[0] },
 171   { "RELAXED", &bool_attr[0], &bool_attr[0] },
 172   { "NO-DIS", &bool_attr[0], &bool_attr[0] },
 173   { "PBB", &bool_attr[0], &bool_attr[0] },
 174   { "OPTIONAL_BIT_INSN", &bool_attr[0], &bool_attr[0] },
 175   { "OPTIONAL_MUL_INSN", &bool_attr[0], &bool_attr[0] },
 176   { "OPTIONAL_DIV_INSN", &bool_attr[0], &bool_attr[0] },
 177   { "OPTIONAL_DEBUG_INSN", &bool_attr[0], &bool_attr[0] },
 178   { "OPTIONAL_LDZ_INSN", &bool_attr[0], &bool_attr[0] },
 179   { "OPTIONAL_ABS_INSN", &bool_attr[0], &bool_attr[0] },
 180   { "OPTIONAL_AVE_INSN", &bool_attr[0], &bool_attr[0] },
 181   { "OPTIONAL_MINMAX_INSN", &bool_attr[0], &bool_attr[0] },
 182   { "OPTIONAL_CLIP_INSN", &bool_attr[0], &bool_attr[0] },
 183   { "OPTIONAL_SAT_INSN", &bool_attr[0], &bool_attr[0] },
 184   { "OPTIONAL_UCI_INSN", &bool_attr[0], &bool_attr[0] },
 185   { "OPTIONAL_DSP_INSN", &bool_attr[0], &bool_attr[0] },
 186   { "OPTIONAL_CP_INSN", &bool_attr[0], &bool_attr[0] },
 187   { "OPTIONAL_CP64_INSN", &bool_attr[0], &bool_attr[0] },
 188   { "OPTIONAL_VLIW64", &bool_attr[0], &bool_attr[0] },
 189   { "MAY_TRAP", &bool_attr[0], &bool_attr[0] },
 190   { "VLIW_ALONE", &bool_attr[0], &bool_attr[0] },
 191   { "VLIW_NO_CORE_NOP", &bool_attr[0], &bool_attr[0] },
 192   { "VLIW_NO_COP_NOP", &bool_attr[0], &bool_attr[0] },
 193   { "VLIW64_NO_MATCHING_NOP", &bool_attr[0], &bool_attr[0] },
 194   { "VLIW32_NO_MATCHING_NOP", &bool_attr[0], &bool_attr[0] },
 195   { "VOLATILE", &bool_attr[0], &bool_attr[0] },
 196   { 0, 0, 0 }
 197 };
 198
 199 /* Instruction set variants.  */
 200
 201 static const CGEN_ISA mep_cgen_isa_table[] = {
 202   { "mep", 32, 32, 16, 32 },
 203   { "ext_core1", 32, 32, 16, 32 },
 204   { "ext_cop1_16", 32, 32, 32, 32 },
 205   { "ext_cop1_32", 32, 32, 32, 32 },
 206   { "ext_cop1_48", 32, 32, 32, 32 },
 207   { "ext_cop1_64", 32, 32, 32, 32 },
 208   { 0, 0, 0, 0, 0 }
 209 };
 210
 211 /* Machine variants.  */
 212
 213 static const CGEN_MACH mep_cgen_mach_table[] = {
 214   { "mep", "mep", MACH_MEP, 16 },
 215   { "h1", "h1", MACH_H1, 16 },
 216   { "c5", "c5", MACH_C5, 16 },
 217   { 0, 0, 0, 0 }
 218 };
 219
 220 static CGEN_KEYWORD_ENTRY mep_cgen_opval_h_gpr_entries[] =
 221 {
 222   { "$0", 0, {0, {{{0, 0}}}}, 0, 0 },
 223   { "$1", 1, {0, {{{0, 0}}}}, 0, 0 },
 224   { "$2", 2, {0, {{{0, 0}}}}, 0, 0 },
 225   { "$3", 3, {0, {{{0, 0}}}}, 0, 0 },
 226   { "$4", 4, {0, {{{0, 0}}}}, 0, 0 },
 227   { "$5", 5, {0, {{{0, 0}}}}, 0, 0 },
 228   { "$6", 6, {0, {{{0, 0}}}}, 0, 0 },
 229   { "$7", 7, {0, {{{0, 0}}}}, 0, 0 },
 230   { "$8", 8, {0, {{{0, 0}}}}, 0, 0 },
 231   { "$9", 9, {0, {{{0, 0}}}}, 0, 0 },
 232   { "$10", 10, {0, {{{0, 0}}}}, 0, 0 },
 233   { "$11", 11, {0, {{{0, 0}}}}, 0, 0 },
 234   { "$fp", 8, {0, {{{0, 0}}}}, 0, 0 },
 235   { "$tp", 13, {0, {{{0, 0}}}}, 0, 0 },
 236   { "$gp", 14, {0, {{{0, 0}}}}, 0, 0 },
 237   { "$sp", 15, {0, {{{0, 0}}}}, 0, 0 },
 238   { "$12", 12, {0, {{{0, 0}}}}, 0, 0 },
 239   { "$13", 13, {0, {{{0, 0}}}}, 0, 0 },
 240   { "$14", 14, {0, {{{0, 0}}}}, 0, 0 },
 241   { "$15", 15, {0, {{{0, 0}}}}, 0, 0 }
 242 };
 243
 244 CGEN_KEYWORD mep_cgen_opval_h_gpr =
 245 {
 246   & mep_cgen_opval_h_gpr_entries[0],
 247   20,
 248   0, 0, 0, 0, ""
 249 };
 250
 251 static CGEN_KEYWORD_ENTRY mep_cgen_opval_h_csr_entries[] =
 252 {
 253   { "$pc", 0, {0, {{{0, 0}}}}, 0, 0 },
 254   { "$lp", 1, {0, {{{0, 0}}}}, 0, 0 },
 255   { "$sar", 2, {0, {{{0, 0}}}}, 0, 0 },
 256   { "$rpb", 4, {0, {{{0, 0}}}}, 0, 0 },
 257   { "$rpe", 5, {0, {{{0, 0}}}}, 0, 0 },
 258   { "$rpc", 6, {0, {{{0, 0}}}}, 0, 0 },
 259   { "$hi", 7, {0, {{{0, 0}}}}, 0, 0 },
 260   { "$lo", 8, {0, {{{0, 0}}}}, 0, 0 },
 261   { "$mb0", 12, {0, {{{0, 0}}}}, 0, 0 },
 262   { "$me0", 13, {0, {{{0, 0}}}}, 0, 0 },
 263   { "$mb1", 14, {0, {{{0, 0}}}}, 0, 0 },
 264   { "$me1", 15, {0, {{{0, 0}}}}, 0, 0 },
 265   { "$psw", 16, {0, {{{0, 0}}}}, 0, 0 },
 266   { "$id", 17, {0, {{{0, 0}}}}, 0, 0 },
 267   { "$tmp", 18, {0, {{{0, 0}}}}, 0, 0 },
 268   { "$epc", 19, {0, {{{0, 0}}}}, 0, 0 },
 269   { "$exc", 20, {0, {{{0, 0}}}}, 0, 0 },
 270   { "$cfg", 21, {0, {{{0, 0}}}}, 0, 0 },
 271   { "$npc", 23, {0, {{{0, 0}}}}, 0, 0 },
 272   { "$dbg", 24, {0, {{{0, 0}}}}, 0, 0 },
 273   { "$depc", 25, {0, {{{0, 0}}}}, 0, 0 },
 274   { "$opt", 26, {0, {{{0, 0}}}}, 0, 0 },
 275   { "$rcfg", 27, {0, {{{0, 0}}}}, 0, 0 },
 276   { "$ccfg", 28, {0, {{{0, 0}}}}, 0, 0 },
 277   { "$vid", 22, {0, {{{0, 0}}}}, 0, 0 }
 278 };
 279
 280 CGEN_KEYWORD mep_cgen_opval_h_csr =
 281 {
 282   & mep_cgen_opval_h_csr_entries[0],
 283   25,
 284   0, 0, 0, 0, ""
 285 };
 286
 287 static CGEN_KEYWORD_ENTRY mep_cgen_opval_h_cr64_entries[] =
 288 {
 289   { "$c0", 0, {0, {{{0, 0}}}}, 0, 0 },
 290   { "$c1", 1, {0, {{{0, 0}}}}, 0, 0 },
 291   { "$c2", 2, {0, {{{0, 0}}}}, 0, 0 },
 292   { "$c3", 3, {0, {{{0, 0}}}}, 0, 0 },
 293   { "$c4", 4, {0, {{{0, 0}}}}, 0, 0 },
 294   { "$c5", 5, {0, {{{0, 0}}}}, 0, 0 },
 295   { "$c6", 6, {0, {{{0, 0}}}}, 0, 0 },
 296   { "$c7", 7, {0, {{{0, 0}}}}, 0, 0 },
 297   { "$c8", 8, {0, {{{0, 0}}}}, 0, 0 },
 298   { "$c9", 9, {0, {{{0, 0}}}}, 0, 0 },
 299   { "$c10", 10, {0, {{{0, 0}}}}, 0, 0 },
 300   { "$c11", 11, {0, {{{0, 0}}}}, 0, 0 },
 301   { "$c12", 12, {0, {{{0, 0}}}}, 0, 0 },
 302   { "$c13", 13, {0, {{{0, 0}}}}, 0, 0 },
 303   { "$c14", 14, {0, {{{0, 0}}}}, 0, 0 },
 304   { "$c15", 15, {0, {{{0, 0}}}}, 0, 0 },
 305   { "$c16", 16, {0, {{{0, 0}}}}, 0, 0 },
 306   { "$c17", 17, {0, {{{0, 0}}}}, 0, 0 },
 307   { "$c18", 18, {0, {{{0, 0}}}}, 0, 0 },
 308   { "$c19", 19, {0, {{{0, 0}}}}, 0, 0 },
 309   { "$c20", 20, {0, {{{0, 0}}}}, 0, 0 },
 310   { "$c21", 21, {0, {{{0, 0}}}}, 0, 0 },
 311   { "$c22", 22, {0, {{{0, 0}}}}, 0, 0 },
 312   { "$c23", 23, {0, {{{0, 0}}}}, 0, 0 },
 313   { "$c24", 24, {0, {{{0, 0}}}}, 0, 0 },
 314   { "$c25", 25, {0, {{{0, 0}}}}, 0, 0 },
 315   { "$c26", 26, {0, {{{0, 0}}}}, 0, 0 },
 316   { "$c27", 27, {0, {{{0, 0}}}}, 0, 0 },
 317   { "$c28", 28, {0, {{{0, 0}}}}, 0, 0 },
 318   { "$c29", 29, {0, {{{0, 0}}}}, 0, 0 },
 319   { "$c30", 30, {0, {{{0, 0}}}}, 0, 0 },
 320   { "$c31", 31, {0, {{{0, 0}}}}, 0, 0 }
 321 };
 322
 323 CGEN_KEYWORD mep_cgen_opval_h_cr64 =
 324 {
 325   & mep_cgen_opval_h_cr64_entries[0],
 326   32,
 327   0, 0, 0, 0, ""
 328 };
 329
 330 static CGEN_KEYWORD_ENTRY mep_cgen_opval_h_cr_entries[] =
 331 {
 332   { "$c0", 0, {0, {{{0, 0}}}}, 0, 0 },
 333   { "$c1", 1, {0, {{{0, 0}}}}, 0, 0 },
 334   { "$c2", 2, {0, {{{0, 0}}}}, 0, 0 },
 335   { "$c3", 3, {0, {{{0, 0}}}}, 0, 0 },
 336   { "$c4", 4, {0, {{{0, 0}}}}, 0, 0 },
 337   { "$c5", 5, {0, {{{0, 0}}}}, 0, 0 },
 338   { "$c6", 6, {0, {{{0, 0}}}}, 0, 0 },
 339   { "$c7", 7, {0, {{{0, 0}}}}, 0, 0 },
 340   { "$c8", 8, {0, {{{0, 0}}}}, 0, 0 },
 341   { "$c9", 9, {0, {{{0, 0}}}}, 0, 0 },
 342   { "$c10", 10, {0, {{{0, 0}}}}, 0, 0 },
 343   { "$c11", 11, {0, {{{0, 0}}}}, 0, 0 },
 344   { "$c12", 12, {0, {{{0, 0}}}}, 0, 0 },
 345   { "$c13", 13, {0, {{{0, 0}}}}, 0, 0 },
 346   { "$c14", 14, {0, {{{0, 0}}}}, 0, 0 },
 347   { "$c15", 15, {0, {{{0, 0}}}}, 0, 0 },
 348   { "$c16", 16, {0, {{{0, 0}}}}, 0, 0 },
 349   { "$c17", 17, {0, {{{0, 0}}}}, 0, 0 },
 350   { "$c18", 18, {0, {{{0, 0}}}}, 0, 0 },
 351   { "$c19", 19, {0, {{{0, 0}}}}, 0, 0 },
 352   { "$c20", 20, {0, {{{0, 0}}}}, 0, 0 },
 353   { "$c21", 21, {0, {{{0, 0}}}}, 0, 0 },
 354   { "$c22", 22, {0, {{{0, 0}}}}, 0, 0 },
 355   { "$c23", 23, {0, {{{0, 0}}}}, 0, 0 },
 356   { "$c24", 24, {0, {{{0, 0}}}}, 0, 0 },
 357   { "$c25", 25, {0, {{{0, 0}}}}, 0, 0 },
 358   { "$c26", 26, {0, {{{0, 0}}}}, 0, 0 },
 359   { "$c27", 27, {0, {{{0, 0}}}}, 0, 0 },
 360   { "$c28", 28, {0, {{{0, 0}}}}, 0, 0 },
 361   { "$c29", 29, {0, {{{0, 0}}}}, 0, 0 },
 362   { "$c30", 30, {0, {{{0, 0}}}}, 0, 0 },
 363   { "$c31", 31, {0, {{{0, 0}}}}, 0, 0 }
 364 };
 365
 366 CGEN_KEYWORD mep_cgen_opval_h_cr =
 367 {
 368   & mep_cgen_opval_h_cr_entries[0],
 369   32,
 370   0, 0, 0, 0, ""
 371 };
 372
 373 static CGEN_KEYWORD_ENTRY mep_cgen_opval_h_ccr_entries[] =
 374 {
 375   { "$ccr0", 0, {0, {{{0, 0}}}}, 0, 0 },
 376   { "$ccr1", 1, {0, {{{0, 0}}}}, 0, 0 },
 377   { "$ccr2", 2, {0, {{{0, 0}}}}, 0, 0 },
 378   { "$ccr3", 3, {0, {{{0, 0}}}}, 0, 0 },
 379   { "$ccr4", 4, {0, {{{0, 0}}}}, 0, 0 },
 380   { "$ccr5", 5, {0, {{{0, 0}}}}, 0, 0 },
 381   { "$ccr6", 6, {0, {{{0, 0}}}}, 0, 0 },
 382   { "$ccr7", 7, {0, {{{0, 0}}}}, 0, 0 },
 383   { "$ccr8", 8, {0, {{{0, 0}}}}, 0, 0 },
 384   { "$ccr9", 9, {0, {{{0, 0}}}}, 0, 0 },
 385   { "$ccr10", 10, {0, {{{0, 0}}}}, 0, 0 },
 386   { "$ccr11", 11, {0, {{{0, 0}}}}, 0, 0 },
 387   { "$ccr12", 12, {0, {{{0, 0}}}}, 0, 0 },
 388   { "$ccr13", 13, {0, {{{0, 0}}}}, 0, 0 },
 389   { "$ccr14", 14, {0, {{{0, 0}}}}, 0, 0 },
 390   { "$ccr15", 15, {0, {{{0, 0}}}}, 0, 0 },
 391   { "$ccr16", 16, {0, {{{0, 0}}}}, 0, 0 },
 392   { "$ccr17", 17, {0, {{{0, 0}}}}, 0, 0 },
 393   { "$ccr18", 18, {0, {{{0, 0}}}}, 0, 0 },
 394   { "$ccr19", 19, {0, {{{0, 0}}}}, 0, 0 },
 395   { "$ccr20", 20, {0, {{{0, 0}}}}, 0, 0 },
 396   { "$ccr21", 21, {0, {{{0, 0}}}}, 0, 0 },
 397   { "$ccr22", 22, {0, {{{0, 0}}}}, 0, 0 },
 398   { "$ccr23", 23, {0, {{{0, 0}}}}, 0, 0 },
 399   { "$ccr24", 24, {0, {{{0, 0}}}}, 0, 0 },
 400   { "$ccr25", 25, {0, {{{0, 0}}}}, 0, 0 },
 401   { "$ccr26", 26, {0, {{{0, 0}}}}, 0, 0 },
 402   { "$ccr27", 27, {0, {{{0, 0}}}}, 0, 0 },
 403   { "$ccr28", 28, {0, {{{0, 0}}}}, 0, 0 },
 404   { "$ccr29", 29, {0, {{{0, 0}}}}, 0, 0 },
 405   { "$ccr30", 30, {0, {{{0, 0}}}}, 0, 0 },
 406   { "$ccr31", 31, {0, {{{0, 0}}}}, 0, 0 },
 407   { "$ccr32", 32, {0, {{{0, 0}}}}, 0, 0 },
 408   { "$ccr33", 33, {0, {{{0, 0}}}}, 0, 0 },
 409   { "$ccr34", 34, {0, {{{0, 0}}}}, 0, 0 },
 410   { "$ccr35", 35, {0, {{{0, 0}}}}, 0, 0 },
 411   { "$ccr36", 36, {0, {{{0, 0}}}}, 0, 0 },
 412   { "$ccr37", 37, {0, {{{0, 0}}}}, 0, 0 },
 413   { "$ccr38", 38, {0, {{{0, 0}}}}, 0, 0 },
 414   { "$ccr39", 39, {0, {{{0, 0}}}}, 0, 0 },
 415   { "$ccr40", 40, {0, {{{0, 0}}}}, 0, 0 },
 416   { "$ccr41", 41, {0, {{{0, 0}}}}, 0, 0 },
 417   { "$ccr42", 42, {0, {{{0, 0}}}}, 0, 0 },
 418   { "$ccr43", 43, {0, {{{0, 0}}}}, 0, 0 },
 419   { "$ccr44", 44, {0, {{{0, 0}}}}, 0, 0 },
 420   { "$ccr45", 45, {0, {{{0, 0}}}}, 0, 0 },
 421   { "$ccr46", 46, {0, {{{0, 0}}}}, 0, 0 },
 422   { "$ccr47", 47, {0, {{{0, 0}}}}, 0, 0 },
 423   { "$ccr48", 48, {0, {{{0, 0}}}}, 0, 0 },
 424   { "$ccr49", 49, {0, {{{0, 0}}}}, 0, 0 },
 425   { "$ccr50", 50, {0, {{{0, 0}}}}, 0, 0 },
 426   { "$ccr51", 51, {0, {{{0, 0}}}}, 0, 0 },
 427   { "$ccr52", 52, {0, {{{0, 0}}}}, 0, 0 },
 428   { "$ccr53", 53, {0, {{{0, 0}}}}, 0, 0 },
 429   { "$ccr54", 54, {0, {{{0, 0}}}}, 0, 0 },
 430   { "$ccr55", 55, {0, {{{0, 0}}}}, 0, 0 },
 431   { "$ccr56", 56, {0, {{{0, 0}}}}, 0, 0 },
 432   { "$ccr57", 57, {0, {{{0, 0}}}}, 0, 0 },
 433   { "$ccr58", 58, {0, {{{0, 0}}}}, 0, 0 },
 434   { "$ccr59", 59, {0, {{{0, 0}}}}, 0, 0 },
 435   { "$ccr60", 60, {0, {{{0, 0}}}}, 0, 0 },
 436   { "$ccr61", 61, {0, {{{0, 0}}}}, 0, 0 },
 437   { "$ccr62", 62, {0, {{{0, 0}}}}, 0, 0 },
 438   { "$ccr63", 63, {0, {{{0, 0}}}}, 0, 0 }
 439 };
 440
 441 CGEN_KEYWORD mep_cgen_opval_h_ccr =
 442 {
 443   & mep_cgen_opval_h_ccr_entries[0],
 444   64,
 445   0, 0, 0, 0, ""
 446 };
 447
 448 static CGEN_KEYWORD_ENTRY mep_cgen_opval_h_cr_ivc2_entries[] =
 449 {
 450   { "$c0", 0, {0, {{{0, 0}}}}, 0, 0 },
 451   { "$c1", 1, {0, {{{0, 0}}}}, 0, 0 },
 452   { "$c2", 2, {0, {{{0, 0}}}}, 0, 0 },
 453   { "$c3", 3, {0, {{{0, 0}}}}, 0, 0 },
 454   { "$c4", 4, {0, {{{0, 0}}}}, 0, 0 },
 455   { "$c5", 5, {0, {{{0, 0}}}}, 0, 0 },
 456   { "$c6", 6, {0, {{{0, 0}}}}, 0, 0 },
 457   { "$c7", 7, {0, {{{0, 0}}}}, 0, 0 }
 458 };
 459
 460 CGEN_KEYWORD mep_cgen_opval_h_cr_ivc2 =
 461 {
 462   & mep_cgen_opval_h_cr_ivc2_entries[0],
 463   8,
 464   0, 0, 0, 0, ""
 465 };
 466
 467 static CGEN_KEYWORD_ENTRY mep_cgen_opval_h_ccr_ivc2_entries[] =
 468 {
 469   { "$ivc2_acc0_0", 16, {0, {{{0, 0}}}}, 0, 0 },
 470   { "$ivc2_acc0_1", 17, {0, {{{0, 0}}}}, 0, 0 },
 471   { "$ivc2_acc0_2", 18, {0, {{{0, 0}}}}, 0, 0 },
 472   { "$ivc2_acc0_3", 19, {0, {{{0, 0}}}}, 0, 0 },
 473   { "$ivc2_acc0_4", 20, {0, {{{0, 0}}}}, 0, 0 },
 474   { "$ivc2_acc0_5", 21, {0, {{{0, 0}}}}, 0, 0 },
 475   { "$ivc2_acc0_6", 22, {0, {{{0, 0}}}}, 0, 0 },
 476   { "$ivc2_acc0_7", 23, {0, {{{0, 0}}}}, 0, 0 },
 477   { "$ivc2_acc1_0", 24, {0, {{{0, 0}}}}, 0, 0 },
 478   { "$ivc2_acc1_1", 25, {0, {{{0, 0}}}}, 0, 0 },
 479   { "$ivc2_acc1_2", 26, {0, {{{0, 0}}}}, 0, 0 },
 480   { "$ivc2_acc1_3", 27, {0, {{{0, 0}}}}, 0, 0 },
 481   { "$ivc2_acc1_4", 28, {0, {{{0, 0}}}}, 0, 0 },
 482   { "$ivc2_acc1_5", 29, {0, {{{0, 0}}}}, 0, 0 },
 483   { "$ivc2_acc1_6", 30, {0, {{{0, 0}}}}, 0, 0 },
 484   { "$ivc2_acc1_7", 31, {0, {{{0, 0}}}}, 0, 0 },
 485   { "$ivc2_csar0", 0, {0, {{{0, 0}}}}, 0, 0 },
 486   { "$ivc2_csar1", 15, {0, {{{0, 0}}}}, 0, 0 },
 487   { "$ivc2_cc", 1, {0, {{{0, 0}}}}, 0, 0 },
 488   { "$ivc2_cofr0", 4, {0, {{{0, 0}}}}, 0, 0 },
 489   { "$ivc2_cofr1", 5, {0, {{{0, 0}}}}, 0, 0 },
 490   { "$ivc2_cofa0", 6, {0, {{{0, 0}}}}, 0, 0 },
 491   { "$ivc2_cofa1", 7, {0, {{{0, 0}}}}, 0, 0 },
 492   { "$ivc2_ccr2", 2, {0, {{{0, 0}}}}, 0, 0 },
 493   { "$ivc2_ccr3", 3, {0, {{{0, 0}}}}, 0, 0 },
 494   { "$ivc2_ccr12", 12, {0, {{{0, 0}}}}, 0, 0 },
 495   { "$ivc2_ccr13", 13, {0, {{{0, 0}}}}, 0, 0 },
 496   { "$ivc2_ccr14", 14, {0, {{{0, 0}}}}, 0, 0 }
 497 };
 498
 499 CGEN_KEYWORD mep_cgen_opval_h_ccr_ivc2 =
 500 {
 501   & mep_cgen_opval_h_ccr_ivc2_entries[0],
 502   28,
 503   0, 0, 0, 0, ""
 504 };
 505
 506
 507 /* The hardware table.  */
 508
 509 #if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
 510 #define A(a) (1 << CGEN_HW_##a)
 511 #else
 512 #define A(a) (1 << CGEN_HW_/**/a)
 513 #endif
 514
 515 const CGEN_HW_ENTRY mep_cgen_hw_table[] =
 516 {
 517   { "h-memory", HW_H_MEMORY, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } } } } },
 518   { "h-sint", HW_H_SINT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } } } } },
 519   { "h-uint", HW_H_UINT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } } } } },
 520   { "h-addr", HW_H_ADDR, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } } } } },
 521   { "h-iaddr", HW_H_IADDR, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } } } } },
 522   { "h-pc", HW_H_PC, CGEN_ASM_NONE, 0, { 0|A(PROFILE)|A(PC), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } } } } },
 523   { "h-gpr", HW_H_GPR, CGEN_ASM_KEYWORD, (PTR) & mep_cgen_opval_h_gpr, { 0|A(PROFILE)|A(CACHE_ADDR), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } } } } },
 524   { "h-csr", HW_H_CSR, CGEN_ASM_KEYWORD, (PTR) & mep_cgen_opval_h_csr, { 0|A(PROFILE), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } } } } },
 525   { "h-cr64", HW_H_CR64, CGEN_ASM_KEYWORD, (PTR) & mep_cgen_opval_h_cr64, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } } } } },
 526   { "h-cr64-w", HW_H_CR64_W, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } } } } },
 527   { "h-cr", HW_H_CR, CGEN_ASM_KEYWORD, (PTR) & mep_cgen_opval_h_cr, { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } } } } },
 528   { "h-ccr", HW_H_CCR, CGEN_ASM_KEYWORD, (PTR) & mep_cgen_opval_h_ccr, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } } } } },
 529   { "h-ccr-w", HW_H_CCR_W, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } } } } },
 530   { "h-cr-ivc2", HW_H_CR_IVC2, CGEN_ASM_KEYWORD, (PTR) & mep_cgen_opval_h_cr_ivc2, { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } } } } },
 531   { "h-ccr-ivc2", HW_H_CCR_IVC2, CGEN_ASM_KEYWORD, (PTR) & mep_cgen_opval_h_ccr_ivc2, { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } } } } },
 532   { 0, 0, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }
 533 };
 534
 535 #undef A
 536
 537
 538 /* The instruction field table.  */
 539
 540 #if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
 541 #define A(a) (1 << CGEN_IFLD_##a)
 542 #else
 543 #define A(a) (1 << CGEN_IFLD_/**/a)
 544 #endif
 545
 546 const CGEN_IFLD mep_cgen_ifld_table[] =
 547 {
 548   { MEP_F_NIL, "f-nil", 0, 0, 0, 0, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }  },
 549   { MEP_F_ANYOF, "f-anyof", 0, 0, 0, 0, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }  },
 550   { MEP_F_MAJOR, "f-major", 0, 32, 0, 4, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } } } }  },
 551   { MEP_F_RN, "f-rn", 0, 32, 4, 4, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } } } }  },
 552   { MEP_F_RN3, "f-rn3", 0, 32, 5, 3, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } } } }  },
 553   { MEP_F_RM, "f-rm", 0, 32, 8, 4, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } } } }  },
 554   { MEP_F_RL, "f-rl", 0, 32, 12, 4, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } } } }  },
 555   { MEP_F_SUB2, "f-sub2", 0, 32, 14, 2, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } } } }  },
 556   { MEP_F_SUB3, "f-sub3", 0, 32, 13, 3, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } } } }  },
 557   { MEP_F_SUB4, "f-sub4", 0, 32, 12, 4, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } } } }  },
 558   { MEP_F_EXT, "f-ext", 0, 32, 16, 8, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } } } }  },
 559   { MEP_F_EXT4, "f-ext4", 0, 32, 16, 4, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } } } }  },
 560   { MEP_F_EXT62, "f-ext62", 0, 32, 20, 2, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } } } }  },
 561   { MEP_F_CRN, "f-crn", 0, 32, 4, 4, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } } } }  },
 562   { MEP_F_CSRN_HI, "f-csrn-hi", 0, 32, 15, 1, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } } } }  },
 563   { MEP_F_CSRN_LO, "f-csrn-lo", 0, 32, 8, 4, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } } } }  },
 564   { MEP_F_CSRN, "f-csrn", 0, 0, 0, 0,{ 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } } } }  },
 565   { MEP_F_CRNX_HI, "f-crnx-hi", 0, 32, 28, 1, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } } } }  },
 566   { MEP_F_CRNX_LO, "f-crnx-lo", 0, 32, 4, 4, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } } } }  },
 567   { MEP_F_CRNX, "f-crnx", 0, 0, 0, 0,{ 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } } } }  },
 568   { MEP_F_0, "f-0", 0, 32, 0, 1, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } } } }  },
 569   { MEP_F_1, "f-1", 0, 32, 1, 1, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } } } }  },
 570   { MEP_F_2, "f-2", 0, 32, 2, 1, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } } } }  },
 571   { MEP_F_3, "f-3", 0, 32, 3, 1, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } } } }  },
 572   { MEP_F_4, "f-4", 0, 32, 4, 1, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } } } }  },
 573   { MEP_F_5, "f-5", 0, 32, 5, 1, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } } } }  },
 574   { MEP_F_6, "f-6", 0, 32, 6, 1, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } } } }  },
 575   { MEP_F_7, "f-7", 0, 32, 7, 1, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } } } }  },
 576   { MEP_F_8, "f-8", 0, 32, 8, 1, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } } } }  },
 577   { MEP_F_9, "f-9", 0, 32, 9, 1, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } } } }  },
 578   { MEP_F_10, "f-10", 0, 32, 10, 1, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } } } }  },
 579   { MEP_F_11, "f-11", 0, 32, 11, 1, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } } } }  },
 580   { MEP_F_12, "f-12", 0, 32, 12, 1, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } } } }  },
 581   { MEP_F_13, "f-13", 0, 32, 13, 1, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } } } }  },
 582   { MEP_F_14, "f-14", 0, 32, 14, 1, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } } } }  },
 583   { MEP_F_15, "f-15", 0, 32, 15, 1, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } } } }  },
 584   { MEP_F_16, "f-16", 0, 32, 16, 1, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } } } }  },
 585   { MEP_F_17, "f-17", 0, 32, 17, 1, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } } } }  },
 586   { MEP_F_18, "f-18", 0, 32, 18, 1, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } } } }  },
 587   { MEP_F_19, "f-19", 0, 32, 19, 1, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } } } }  },
 588   { MEP_F_20, "f-20", 0, 32, 20, 1, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } } } }  },
 589   { MEP_F_21, "f-21", 0, 32, 21, 1, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } } } }  },
 590   { MEP_F_22, "f-22", 0, 32, 22, 1, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } } } }  },
 591   { MEP_F_23, "f-23", 0, 32, 23, 1, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } } } }  },
 592   { MEP_F_24, "f-24", 0, 32, 24, 1, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } } } }  },
 593   { MEP_F_25, "f-25", 0, 32, 25, 1, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } } } }  },
 594   { MEP_F_26, "f-26", 0, 32, 26, 1, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } } } }  },
 595   { MEP_F_27, "f-27", 0, 32, 27, 1, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } } } }  },
 596   { MEP_F_28, "f-28", 0, 32, 28, 1, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } } } }  },
 597   { MEP_F_29, "f-29", 0, 32, 29, 1, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } } } }  },
 598   { MEP_F_30, "f-30", 0, 32, 30, 1, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } } } }  },
 599   { MEP_F_31, "f-31", 0, 32, 31, 1, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } } } }  },
 600   { MEP_F_8S8A2, "f-8s8a2", 0, 32, 8, 7, { 0|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } } } }  },
 601   { MEP_F_12S4A2, "f-12s4a2", 0, 32, 4, 11, { 0|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } } } }  },
 602   { MEP_F_17S16A2, "f-17s16a2", 0, 32, 16, 16, { 0|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } } } }  },
 603   { MEP_F_24S5A2N_HI, "f-24s5a2n-hi", 0, 32, 16, 16, { 0|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } } } }  },
 604   { MEP_F_24S5A2N_LO, "f-24s5a2n-lo", 0, 32, 5, 7, { 0|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } } } }  },
 605   { MEP_F_24S5A2N, "f-24s5a2n", 0, 0, 0, 0,{ 0|A(PCREL_ADDR)|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } } } }  },
 606   { MEP_F_24U5A2N_HI, "f-24u5a2n-hi", 0, 32, 16, 16, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } } } }  },
 607   { MEP_F_24U5A2N_LO, "f-24u5a2n-lo", 0, 32, 5, 7, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } } } }  },
 608   { MEP_F_24U5A2N, "f-24u5a2n", 0, 0, 0, 0,{ 0|A(ABS_ADDR)|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } } } }  },
 609   { MEP_F_2U6, "f-2u6", 0, 32, 6, 2, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } } } }  },
 610   { MEP_F_7U9, "f-7u9", 0, 32, 9, 7, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } } } }  },
 611   { MEP_F_7U9A2, "f-7u9a2", 0, 32, 9, 6, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } } } }  },
 612   { MEP_F_7U9A4, "f-7u9a4", 0, 32, 9, 5, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } } } }  },
 613   { MEP_F_16S16, "f-16s16", 0, 32, 16, 16, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } } } }  },
 614   { MEP_F_2U10, "f-2u10", 0, 32, 10, 2, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } } } }  },
 615   { MEP_F_3U5, "f-3u5", 0, 32, 5, 3, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } } } }  },
 616   { MEP_F_4U8, "f-4u8", 0, 32, 8, 4, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } } } }  },
 617   { MEP_F_5U8, "f-5u8", 0, 32, 8, 5, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } } } }  },
 618   { MEP_F_5U24, "f-5u24", 0, 32, 24, 5, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } } } }  },
 619   { MEP_F_6S8, "f-6s8", 0, 32, 8, 6, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } } } }  },
 620   { MEP_F_8S8, "f-8s8", 0, 32, 8, 8, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } } } }  },
 621   { MEP_F_16U16, "f-16u16", 0, 32, 16, 16, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } } } }  },
 622   { MEP_F_12U16, "f-12u16", 0, 32, 16, 12, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } } } }  },
 623   { MEP_F_3U29, "f-3u29", 0, 32, 29, 3, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } } } }  },
 624   { MEP_F_CDISP10, "f-cdisp10", 0, 32, 22, 10, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } } } }  },
 625   { MEP_F_24U8A4N_HI, "f-24u8a4n-hi", 0, 32, 16, 16, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } } } }  },
 626   { MEP_F_24U8A4N_LO, "f-24u8a4n-lo", 0, 32, 8, 6, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } } } }  },
 627   { MEP_F_24U8A4N, "f-24u8a4n", 0, 0, 0, 0,{ 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } } } }  },
 628   { MEP_F_24U8N_HI, "f-24u8n-hi", 0, 32, 16, 16, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } } } }  },
 629   { MEP_F_24U8N_LO, "f-24u8n-lo", 0, 32, 8, 8, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } } } }  },
 630   { MEP_F_24U8N, "f-24u8n", 0, 0, 0, 0,{ 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } } } }  },
 631   { MEP_F_24U4N_HI, "f-24u4n-hi", 0, 32, 4, 8, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } } } }  },
 632   { MEP_F_24U4N_LO, "f-24u4n-lo", 0, 32, 16, 16, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } } } }  },
 633   { MEP_F_24U4N, "f-24u4n", 0, 0, 0, 0,{ 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } } } }  },
 634   { MEP_F_CALLNUM, "f-callnum", 0, 0, 0, 0,{ 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } } } }  },
 635   { MEP_F_CCRN_HI, "f-ccrn-hi", 0, 32, 28, 2, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } } } }  },
 636   { MEP_F_CCRN_LO, "f-ccrn-lo", 0, 32, 4, 4, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } } } }  },
 637   { MEP_F_CCRN, "f-ccrn", 0, 0, 0, 0,{ 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } } } }  },
 638   { MEP_F_C5N4, "f-c5n4", 0, 32, 16, 4, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } } } }  },
 639   { MEP_F_C5N5, "f-c5n5", 0, 32, 20, 4, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } } } }  },
 640   { MEP_F_C5N6, "f-c5n6", 0, 32, 24, 4, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } } } }  },
 641   { MEP_F_C5N7, "f-c5n7", 0, 32, 28, 4, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } } } }  },
 642   { MEP_F_RL5, "f-rl5", 0, 32, 20, 4, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } } } }  },
 643   { MEP_F_12S20, "f-12s20", 0, 32, 20, 12, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } } } }  },
 644   { MEP_F_C5_RNM, "f-c5-rnm", 0, 32, 4, 8, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } } } }  },
 645   { MEP_F_C5_RM, "f-c5-rm", 0, 32, 8, 4, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } } } }  },
 646   { MEP_F_C5_16U16, "f-c5-16u16", 0, 32, 16, 16, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } } } }  },
 647   { MEP_F_C5_RMUIMM20, "f-c5-rmuimm20", 0, 0, 0, 0,{ 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } } } }  },
 648   { MEP_F_C5_RNMUIMM24, "f-c5-rnmuimm24", 0, 0, 0, 0,{ 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } } } }  },
 649   { MEP_F_IVC2_2U4, "f-ivc2-2u4", 0, 32, 4, 2, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } } } }  },
 650   { MEP_F_IVC2_3U4, "f-ivc2-3u4", 0, 32, 4, 3, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } } } }  },
 651   { MEP_F_IVC2_8U4, "f-ivc2-8u4", 0, 32, 4, 8, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } } } }  },
 652   { MEP_F_IVC2_8S4, "f-ivc2-8s4", 0, 32, 4, 8, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } } } }  },
 653   { MEP_F_IVC2_1U6, "f-ivc2-1u6", 0, 32, 6, 1, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } } } }  },
 654   { MEP_F_IVC2_2U6, "f-ivc2-2u6", 0, 32, 6, 2, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } } } }  },
 655   { MEP_F_IVC2_3U6, "f-ivc2-3u6", 0, 32, 6, 3, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } } } }  },
 656   { MEP_F_IVC2_6U6, "f-ivc2-6u6", 0, 32, 6, 6, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } } } }  },
 657   { MEP_F_IVC2_5U7, "f-ivc2-5u7", 0, 32, 7, 5, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } } } }  },
 658   { MEP_F_IVC2_4U8, "f-ivc2-4u8", 0, 32, 8, 4, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } } } }  },
 659   { MEP_F_IVC2_3U9, "f-ivc2-3u9", 0, 32, 9, 3, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } } } }  },
 660   { MEP_F_IVC2_5U16, "f-ivc2-5u16", 0, 32, 16, 5, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } } } }  },
 661   { MEP_F_IVC2_5U21, "f-ivc2-5u21", 0, 32, 21, 5, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } } } }  },
 662   { MEP_F_IVC2_5U26, "f-ivc2-5u26", 0, 32, 26, 5, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } } } }  },
 663   { MEP_F_IVC2_1U31, "f-ivc2-1u31", 0, 32, 31, 1, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } } } }  },
 664   { MEP_F_IVC2_4U16, "f-ivc2-4u16", 0, 32, 16, 4, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } } } }  },
 665   { MEP_F_IVC2_4U20, "f-ivc2-4u20", 0, 32, 20, 4, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } } } }  },
 666   { MEP_F_IVC2_4U24, "f-ivc2-4u24", 0, 32, 24, 4, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } } } }  },
 667   { MEP_F_IVC2_4U28, "f-ivc2-4u28", 0, 32, 28, 4, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } } } }  },
 668   { MEP_F_IVC2_2U0, "f-ivc2-2u0", 0, 32, 0, 2, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } } } }  },
 669   { MEP_F_IVC2_3U0, "f-ivc2-3u0", 0, 32, 0, 3, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } } } }  },
 670   { MEP_F_IVC2_4U0, "f-ivc2-4u0", 0, 32, 0, 4, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } } } }  },
 671   { MEP_F_IVC2_5U0, "f-ivc2-5u0", 0, 32, 0, 5, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } } } }  },
 672   { MEP_F_IVC2_8U0, "f-ivc2-8u0", 0, 32, 0, 8, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } } } }  },
 673   { MEP_F_IVC2_8S0, "f-ivc2-8s0", 0, 32, 0, 8, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } } } }  },
 674   { MEP_F_IVC2_6U2, "f-ivc2-6u2", 0, 32, 2, 6, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } } } }  },
 675   { MEP_F_IVC2_5U3, "f-ivc2-5u3", 0, 32, 3, 5, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } } } }  },
 676   { MEP_F_IVC2_4U4, "f-ivc2-4u4", 0, 32, 4, 4, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } } } }  },
 677   { MEP_F_IVC2_3U5, "f-ivc2-3u5", 0, 32, 5, 3, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } } } }  },
 678   { MEP_F_IVC2_5U8, "f-ivc2-5u8", 0, 32, 8, 5, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } } } }  },
 679   { MEP_F_IVC2_4U10, "f-ivc2-4u10", 0, 32, 10, 4, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } } } }  },
 680   { MEP_F_IVC2_3U12, "f-ivc2-3u12", 0, 32, 12, 3, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } } } }  },
 681   { MEP_F_IVC2_5U13, "f-ivc2-5u13", 0, 32, 13, 5, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } } } }  },
 682   { MEP_F_IVC2_2U18, "f-ivc2-2u18", 0, 32, 18, 2, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } } } }  },
 683   { MEP_F_IVC2_5U18, "f-ivc2-5u18", 0, 32, 18, 5, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } } } }  },
 684   { MEP_F_IVC2_8U20, "f-ivc2-8u20", 0, 32, 20, 8, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } } } }  },
 685   { MEP_F_IVC2_8S20, "f-ivc2-8s20", 0, 32, 20, 8, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } } } }  },
 686   { MEP_F_IVC2_5U23, "f-ivc2-5u23", 0, 32, 23, 5, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } } } }  },
 687   { MEP_F_IVC2_2U23, "f-ivc2-2u23", 0, 32, 23, 2, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } } } }  },
 688   { MEP_F_IVC2_3U25, "f-ivc2-3u25", 0, 32, 25, 3, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } } } }  },
 689   { MEP_F_IVC2_IMM16P0, "f-ivc2-imm16p0", 0, 0, 0, 0,{ 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } } } }  },
 690   { MEP_F_IVC2_SIMM16P0, "f-ivc2-simm16p0", 0, 0, 0, 0,{ 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } } } }  },
 691   { MEP_F_IVC2_CRN, "f-ivc2-crn", 0, 32, 0, 4, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } } } }  },
 692   { MEP_F_IVC2_CRM, "f-ivc2-crm", 0, 32, 4, 4, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } } } }  },
 693   { MEP_F_IVC2_CCRN_H1, "f-ivc2-ccrn-h1", 0, 32, 20, 1, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } } } }  },
 694   { MEP_F_IVC2_CCRN_H2, "f-ivc2-ccrn-h2", 0, 32, 20, 2, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } } } }  },
 695   { MEP_F_IVC2_CCRN_LO, "f-ivc2-ccrn-lo", 0, 32, 0, 4, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } } } }  },
 696   { MEP_F_IVC2_CMOV1, "f-ivc2-cmov1", 0, 32, 8, 12, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } } } }  },
 697   { MEP_F_IVC2_CMOV2, "f-ivc2-cmov2", 0, 32, 22, 6, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } } } }  },
 698   { MEP_F_IVC2_CMOV3, "f-ivc2-cmov3", 0, 32, 28, 4, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } } } }  },
 699   { MEP_F_IVC2_CCRN, "f-ivc2-ccrn", 0, 0, 0, 0,{ 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } } } }  },
 700   { MEP_F_IVC2_CRNX, "f-ivc2-crnx", 0, 0, 0, 0,{ 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } } } }  },
 701   { 0, 0, 0, 0, 0, 0, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }
 702 };
 703
 704 #undef A
 705
 706
 707
 708 /* multi ifield declarations */
 709
 710 const CGEN_MAYBE_MULTI_IFLD MEP_F_CSRN_MULTI_IFIELD [];
 711 const CGEN_MAYBE_MULTI_IFLD MEP_F_CRNX_MULTI_IFIELD [];
 712 const CGEN_MAYBE_MULTI_IFLD MEP_F_24S5A2N_MULTI_IFIELD [];
 713 const CGEN_MAYBE_MULTI_IFLD MEP_F_24U5A2N_MULTI_IFIELD [];
 714 const CGEN_MAYBE_MULTI_IFLD MEP_F_24U8A4N_MULTI_IFIELD [];
 715 const CGEN_MAYBE_MULTI_IFLD MEP_F_24U8N_MULTI_IFIELD [];
 716 const CGEN_MAYBE_MULTI_IFLD MEP_F_24U4N_MULTI_IFIELD [];
 717 const CGEN_MAYBE_MULTI_IFLD MEP_F_CALLNUM_MULTI_IFIELD [];
 718 const CGEN_MAYBE_MULTI_IFLD MEP_F_CCRN_MULTI_IFIELD [];
 719 const CGEN_MAYBE_MULTI_IFLD MEP_F_C5_RMUIMM20_MULTI_IFIELD [];
 720 const CGEN_MAYBE_MULTI_IFLD MEP_F_C5_RNMUIMM24_MULTI_IFIELD [];
 721 const CGEN_MAYBE_MULTI_IFLD MEP_F_IVC2_IMM16P0_MULTI_IFIELD [];
 722 const CGEN_MAYBE_MULTI_IFLD MEP_F_IVC2_SIMM16P0_MULTI_IFIELD [];
 723 const CGEN_MAYBE_MULTI_IFLD MEP_F_IVC2_CCRN_MULTI_IFIELD [];
 724 const CGEN_MAYBE_MULTI_IFLD MEP_F_IVC2_CRNX_MULTI_IFIELD [];
 725
 726
 727 /* multi ifield definitions */
 728
 729 const CGEN_MAYBE_MULTI_IFLD MEP_F_CSRN_MULTI_IFIELD [] =
 730 {
 731     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_CSRN_HI] } },
 732     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_CSRN_LO] } },
 733     { 0, { (const PTR) 0 } }
 734 };
 735 const CGEN_MAYBE_MULTI_IFLD MEP_F_CRNX_MULTI_IFIELD [] =
 736 {
 737     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_CRNX_HI] } },
 738     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_CRNX_LO] } },
 739     { 0, { (const PTR) 0 } }
 740 };
 741 const CGEN_MAYBE_MULTI_IFLD MEP_F_24S5A2N_MULTI_IFIELD [] =
 742 {
 743     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_24S5A2N_HI] } },
 744     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_24S5A2N_LO] } },
 745     { 0, { (const PTR) 0 } }
 746 };
 747 const CGEN_MAYBE_MULTI_IFLD MEP_F_24U5A2N_MULTI_IFIELD [] =
 748 {
 749     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_24U5A2N_HI] } },
 750     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_24U5A2N_LO] } },
 751     { 0, { (const PTR) 0 } }
 752 };
 753 const CGEN_MAYBE_MULTI_IFLD MEP_F_24U8A4N_MULTI_IFIELD [] =
 754 {
 755     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_24U8A4N_HI] } },
 756     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_24U8A4N_LO] } },
 757     { 0, { (const PTR) 0 } }
 758 };
 759 const CGEN_MAYBE_MULTI_IFLD MEP_F_24U8N_MULTI_IFIELD [] =
 760 {
 761     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_24U8N_HI] } },
 762     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_24U8N_LO] } },
 763     { 0, { (const PTR) 0 } }
 764 };
 765 const CGEN_MAYBE_MULTI_IFLD MEP_F_24U4N_MULTI_IFIELD [] =
 766 {
 767     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_24U4N_HI] } },
 768     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_24U4N_LO] } },
 769     { 0, { (const PTR) 0 } }
 770 };
 771 const CGEN_MAYBE_MULTI_IFLD MEP_F_CALLNUM_MULTI_IFIELD [] =
 772 {
 773     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_5] } },
 774     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_6] } },
 775     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_7] } },
 776     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_11] } },
 777     { 0, { (const PTR) 0 } }
 778 };
 779 const CGEN_MAYBE_MULTI_IFLD MEP_F_CCRN_MULTI_IFIELD [] =
 780 {
 781     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_CCRN_HI] } },
 782     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_CCRN_LO] } },
 783     { 0, { (const PTR) 0 } }
 784 };
 785 const CGEN_MAYBE_MULTI_IFLD MEP_F_C5_RMUIMM20_MULTI_IFIELD [] =
 786 {
 787     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_C5_RM] } },
 788     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_C5_16U16] } },
 789     { 0, { (const PTR) 0 } }
 790 };
 791 const CGEN_MAYBE_MULTI_IFLD MEP_F_C5_RNMUIMM24_MULTI_IFIELD [] =
 792 {
 793     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_C5_RNM] } },
 794     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_C5_16U16] } },
 795     { 0, { (const PTR) 0 } }
 796 };
 797 const CGEN_MAYBE_MULTI_IFLD MEP_F_IVC2_IMM16P0_MULTI_IFIELD [] =
 798 {
 799     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_IVC2_8U0] } },
 800     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_IVC2_8U20] } },
 801     { 0, { (const PTR) 0 } }
 802 };
 803 const CGEN_MAYBE_MULTI_IFLD MEP_F_IVC2_SIMM16P0_MULTI_IFIELD [] =
 804 {
 805     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_IVC2_8U0] } },
 806     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_IVC2_8U20] } },
 807     { 0, { (const PTR) 0 } }
 808 };
 809 const CGEN_MAYBE_MULTI_IFLD MEP_F_IVC2_CCRN_MULTI_IFIELD [] =
 810 {
 811     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_IVC2_CCRN_H2] } },
 812     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_IVC2_CCRN_LO] } },
 813     { 0, { (const PTR) 0 } }
 814 };
 815 const CGEN_MAYBE_MULTI_IFLD MEP_F_IVC2_CRNX_MULTI_IFIELD [] =
 816 {
 817     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_IVC2_CCRN_H1] } },
 818     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_IVC2_CCRN_LO] } },
 819     { 0, { (const PTR) 0 } }
 820 };
 821
 822 /* The operand table.  */
 823
 824 #if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
 825 #define A(a) (1 << CGEN_OPERAND_##a)
 826 #else
 827 #define A(a) (1 << CGEN_OPERAND_/**/a)
 828 #endif
 829 #if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
 830 #define OPERAND(op) MEP_OPERAND_##op
 831 #else
 832 #define OPERAND(op) MEP_OPERAND_/**/op
 833 #endif
 834
 835 const CGEN_OPERAND mep_cgen_operand_table[] =
 836 {
 837 /* pc: program counter */
 838   { "pc", MEP_OPERAND_PC, HW_H_PC, 0, 0,
 839     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_NIL] } },
 840     { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
 841 /* r0: register 0 */
 842   { "r0", MEP_OPERAND_R0, HW_H_GPR, 0, 0,
 843     { 0, { (const PTR) 0 } },
 844     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
 845 /* rn: register Rn */
 846   { "rn", MEP_OPERAND_RN, HW_H_GPR, 4, 4,
 847     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_RN] } },
 848     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
 849 /* rm: register Rm */
 850   { "rm", MEP_OPERAND_RM, HW_H_GPR, 8, 4,
 851     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_RM] } },
 852     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
 853 /* rl: register Rl */
 854   { "rl", MEP_OPERAND_RL, HW_H_GPR, 12, 4,
 855     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_RL] } },
 856     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
 857 /* rn3: register 0-7 */
 858   { "rn3", MEP_OPERAND_RN3, HW_H_GPR, 5, 3,
 859     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_RN3] } },
 860     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
 861 /* rma: register Rm holding pointer */
 862   { "rma", MEP_OPERAND_RMA, HW_H_GPR, 8, 4,
 863     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_RM] } },
 864     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_POINTER, 0 } }, { { 1, 0 } } } }  },
 865 /* rnc: register Rn holding char */
 866   { "rnc", MEP_OPERAND_RNC, HW_H_GPR, 4, 4,
 867     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_RN] } },
 868     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
 869 /* rnuc: register Rn holding unsigned char */
 870   { "rnuc", MEP_OPERAND_RNUC, HW_H_GPR, 4, 4,
 871     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_RN] } },
 872     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
 873 /* rns: register Rn holding short */
 874   { "rns", MEP_OPERAND_RNS, HW_H_GPR, 4, 4,
 875     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_RN] } },
 876     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
 877 /* rnus: register Rn holding unsigned short */
 878   { "rnus", MEP_OPERAND_RNUS, HW_H_GPR, 4, 4,
 879     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_RN] } },
 880     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
 881 /* rnl: register Rn holding long */
 882   { "rnl", MEP_OPERAND_RNL, HW_H_GPR, 4, 4,
 883     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_RN] } },
 884     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
 885 /* rnul: register Rn holding unsigned  long */
 886   { "rnul", MEP_OPERAND_RNUL, HW_H_GPR, 4, 4,
 887     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_RN] } },
 888     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_ULONG, 0 } }, { { 1, 0 } } } }  },
 889 /* rn3c: register 0-7 holding unsigned char */
 890   { "rn3c", MEP_OPERAND_RN3C, HW_H_GPR, 5, 3,
 891     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_RN3] } },
 892     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
 893 /* rn3uc: register 0-7 holding byte */
 894   { "rn3uc", MEP_OPERAND_RN3UC, HW_H_GPR, 5, 3,
 895     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_RN3] } },
 896     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
 897 /* rn3s: register 0-7 holding unsigned short */
 898   { "rn3s", MEP_OPERAND_RN3S, HW_H_GPR, 5, 3,
 899     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_RN3] } },
 900     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
 901 /* rn3us: register 0-7 holding short */
 902   { "rn3us", MEP_OPERAND_RN3US, HW_H_GPR, 5, 3,
 903     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_RN3] } },
 904     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
 905 /* rn3l: register 0-7 holding unsigned long */
 906   { "rn3l", MEP_OPERAND_RN3L, HW_H_GPR, 5, 3,
 907     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_RN3] } },
 908     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
 909 /* rn3ul: register 0-7 holding long */
 910   { "rn3ul", MEP_OPERAND_RN3UL, HW_H_GPR, 5, 3,
 911     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_RN3] } },
 912     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_ULONG, 0 } }, { { 1, 0 } } } }  },
 913 /* lp: link pointer */
 914   { "lp", MEP_OPERAND_LP, HW_H_CSR, 0, 0,
 915     { 0, { (const PTR) 0 } },
 916     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
 917 /* sar: shift amount register */
 918   { "sar", MEP_OPERAND_SAR, HW_H_CSR, 0, 0,
 919     { 0, { (const PTR) 0 } },
 920     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
 921 /* hi: high result */
 922   { "hi", MEP_OPERAND_HI, HW_H_CSR, 0, 0,
 923     { 0, { (const PTR) 0 } },
 924     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
 925 /* lo: low result */
 926   { "lo", MEP_OPERAND_LO, HW_H_CSR, 0, 0,
 927     { 0, { (const PTR) 0 } },
 928     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
 929 /* mb0: modulo begin register 0 */
 930   { "mb0", MEP_OPERAND_MB0, HW_H_CSR, 0, 0,
 931     { 0, { (const PTR) 0 } },
 932     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
 933 /* me0: modulo end register 0 */
 934   { "me0", MEP_OPERAND_ME0, HW_H_CSR, 0, 0,
 935     { 0, { (const PTR) 0 } },
 936     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
 937 /* mb1: modulo begin register 1 */
 938   { "mb1", MEP_OPERAND_MB1, HW_H_CSR, 0, 0,
 939     { 0, { (const PTR) 0 } },
 940     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
 941 /* me1: modulo end register 1 */
 942   { "me1", MEP_OPERAND_ME1, HW_H_CSR, 0, 0,
 943     { 0, { (const PTR) 0 } },
 944     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
 945 /* psw: program status word */
 946   { "psw", MEP_OPERAND_PSW, HW_H_CSR, 0, 0,
 947     { 0, { (const PTR) 0 } },
 948     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
 949 /* epc: exception prog counter */
 950   { "epc", MEP_OPERAND_EPC, HW_H_CSR, 0, 0,
 951     { 0, { (const PTR) 0 } },
 952     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
 953 /* exc: exception cause */
 954   { "exc", MEP_OPERAND_EXC, HW_H_CSR, 0, 0,
 955     { 0, { (const PTR) 0 } },
 956     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
 957 /* npc: nmi program counter */
 958   { "npc", MEP_OPERAND_NPC, HW_H_CSR, 0, 0,
 959     { 0, { (const PTR) 0 } },
 960     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
 961 /* dbg: debug register */
 962   { "dbg", MEP_OPERAND_DBG, HW_H_CSR, 0, 0,
 963     { 0, { (const PTR) 0 } },
 964     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
 965 /* depc: debug exception pc */
 966   { "depc", MEP_OPERAND_DEPC, HW_H_CSR, 0, 0,
 967     { 0, { (const PTR) 0 } },
 968     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
 969 /* opt: option register */
 970   { "opt", MEP_OPERAND_OPT, HW_H_CSR, 0, 0,
 971     { 0, { (const PTR) 0 } },
 972     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
 973 /* r1: register 1 */
 974   { "r1", MEP_OPERAND_R1, HW_H_GPR, 0, 0,
 975     { 0, { (const PTR) 0 } },
 976     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
 977 /* tp: tiny data area pointer */
 978   { "tp", MEP_OPERAND_TP, HW_H_GPR, 0, 0,
 979     { 0, { (const PTR) 0 } },
 980     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
 981 /* sp: stack pointer */
 982   { "sp", MEP_OPERAND_SP, HW_H_GPR, 0, 0,
 983     { 0, { (const PTR) 0 } },
 984     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
 985 /* tpr: comment */
 986   { "tpr", MEP_OPERAND_TPR, HW_H_GPR, 0, 0,
 987     { 0, { (const PTR) 0 } },
 988     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
 989 /* spr: comment */
 990   { "spr", MEP_OPERAND_SPR, HW_H_GPR, 0, 0,
 991     { 0, { (const PTR) 0 } },
 992     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
 993 /* csrn: control/special register */
 994   { "csrn", MEP_OPERAND_CSRN, HW_H_CSR, 8, 5,
 995     { 2, { (const PTR) &MEP_F_CSRN_MULTI_IFIELD[0] } },
 996     { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_REGNUM, 0 } }, { { 1, 0 } } } }  },
 997 /* csrn-idx: control/special reg idx */
 998   { "csrn-idx", MEP_OPERAND_CSRN_IDX, HW_H_UINT, 8, 5,
 999     { 2, { (const PTR) &MEP_F_CSRN_MULTI_IFIELD[0] } },
1000     { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
1001 /* crn64: copro Rn (64-bit) */
1002   { "crn64", MEP_OPERAND_CRN64, HW_H_CR64, 4, 4,
1003     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_CRN] } },
1004     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_CP_DATA_BUS_INT, 0 } }, { { 1, 0 } } } }  },
1005 /* crn: copro Rn (32-bit) */
1006   { "crn", MEP_OPERAND_CRN, HW_H_CR, 4, 4,
1007     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_CRN] } },
1008     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_CP_DATA_BUS_INT, 0 } }, { { 1, 0 } } } }  },
1009 /* crnx64: copro Rn (0-31, 64-bit) */
1010   { "crnx64", MEP_OPERAND_CRNX64, HW_H_CR64, 4, 5,
1011     { 2, { (const PTR) &MEP_F_CRNX_MULTI_IFIELD[0] } },
1012     { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_CP_DATA_BUS_INT, 0 } }, { { 1, 0 } } } }  },
1013 /* crnx: copro Rn (0-31, 32-bit) */
1014   { "crnx", MEP_OPERAND_CRNX, HW_H_CR, 4, 5,
1015     { 2, { (const PTR) &MEP_F_CRNX_MULTI_IFIELD[0] } },
1016     { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_CP_DATA_BUS_INT, 0 } }, { { 1, 0 } } } }  },
1017 /* ccrn: copro control reg CCRn */
1018   { "ccrn", MEP_OPERAND_CCRN, HW_H_CCR, 4, 6,
1019     { 2, { (const PTR) &MEP_F_CCRN_MULTI_IFIELD[0] } },
1020     { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_REGNUM, 0 } }, { { 1, 0 } } } }  },
1021 /* cccc: copro flags */
1022   { "cccc", MEP_OPERAND_CCCC, HW_H_UINT, 8, 4,
1023     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_RM] } },
1024     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
1025 /* pcrel8a2: comment */
1026   { "pcrel8a2", MEP_OPERAND_PCREL8A2, HW_H_SINT, 8, 7,
1027     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_8S8A2] } },
1028     { 0|A(RELAX)|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_LABEL, 0 } }, { { 1, 0 } } } }  },
1029 /* pcrel12a2: comment */
1030   { "pcrel12a2", MEP_OPERAND_PCREL12A2, HW_H_SINT, 4, 11,
1031     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_12S4A2] } },
1032     { 0|A(RELAX)|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_LABEL, 0 } }, { { 1, 0 } } } }  },
1033 /* pcrel17a2: comment */
1034   { "pcrel17a2", MEP_OPERAND_PCREL17A2, HW_H_SINT, 16, 16,
1035     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_17S16A2] } },
1036     { 0|A(RELAX)|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_LABEL, 0 } }, { { 1, 0 } } } }  },
1037 /* pcrel24a2: comment */
1038   { "pcrel24a2", MEP_OPERAND_PCREL24A2, HW_H_SINT, 5, 23,
1039     { 2, { (const PTR) &MEP_F_24S5A2N_MULTI_IFIELD[0] } },
1040     { 0|A(PCREL_ADDR)|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_LABEL, 0 } }, { { 1, 0 } } } }  },
1041 /* pcabs24a2: comment */
1042   { "pcabs24a2", MEP_OPERAND_PCABS24A2, HW_H_UINT, 5, 23,
1043     { 2, { (const PTR) &MEP_F_24U5A2N_MULTI_IFIELD[0] } },
1044     { 0|A(ABS_ADDR)|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_LABEL, 0 } }, { { 1, 0 } } } }  },
1045 /* sdisp16: comment */
1046   { "sdisp16", MEP_OPERAND_SDISP16, HW_H_SINT, 16, 16,
1047     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_16S16] } },
1048     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
1049 /* simm16: comment */
1050   { "simm16", MEP_OPERAND_SIMM16, HW_H_SINT, 16, 16,
1051     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_16S16] } },
1052     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
1053 /* uimm16: comment */
1054   { "uimm16", MEP_OPERAND_UIMM16, HW_H_UINT, 16, 16,
1055     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_16U16] } },
1056     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
1057 /* code16: uci/dsp code (16 bits) */
1058   { "code16", MEP_OPERAND_CODE16, HW_H_UINT, 16, 16,
1059     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_16U16] } },
1060     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
1061 /* udisp2: SSARB addend (2 bits) */
1062   { "udisp2", MEP_OPERAND_UDISP2, HW_H_SINT, 6, 2,
1063     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_2U6] } },
1064     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
1065 /* uimm2: interrupt (2 bits) */
1066   { "uimm2", MEP_OPERAND_UIMM2, HW_H_UINT, 10, 2,
1067     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_2U10] } },
1068     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
1069 /* simm6: add const (6 bits) */
1070   { "simm6", MEP_OPERAND_SIMM6, HW_H_SINT, 8, 6,
1071     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_6S8] } },
1072     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
1073 /* simm8: mov const (8 bits) */
1074   { "simm8", MEP_OPERAND_SIMM8, HW_H_SINT, 8, 8,
1075     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_8S8] } },
1076     { 0|A(RELOC_IMPLIES_OVERFLOW), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
1077 /* addr24a4: comment */
1078   { "addr24a4", MEP_OPERAND_ADDR24A4, HW_H_UINT, 8, 22,
1079     { 2, { (const PTR) &MEP_F_24U8A4N_MULTI_IFIELD[0] } },
1080     { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_LONG, 0 } }, { { 4, 0 } } } }  },
1081 /* code24: coprocessor code */
1082   { "code24", MEP_OPERAND_CODE24, HW_H_UINT, 4, 24,
1083     { 2, { (const PTR) &MEP_F_24U4N_MULTI_IFIELD[0] } },
1084     { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
1085 /* callnum: system call number */
1086   { "callnum", MEP_OPERAND_CALLNUM, HW_H_UINT, 5, 4,
1087     { 4, { (const PTR) &MEP_F_CALLNUM_MULTI_IFIELD[0] } },
1088     { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
1089 /* uimm3: bit immediate (3 bits) */
1090   { "uimm3", MEP_OPERAND_UIMM3, HW_H_UINT, 5, 3,
1091     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_3U5] } },
1092     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
1093 /* uimm4: bCC const (4 bits) */
1094   { "uimm4", MEP_OPERAND_UIMM4, HW_H_UINT, 8, 4,
1095     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_4U8] } },
1096     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
1097 /* uimm5: bit/shift val (5 bits) */
1098   { "uimm5", MEP_OPERAND_UIMM5, HW_H_UINT, 8, 5,
1099     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_5U8] } },
1100     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
1101 /* udisp7: comment */
1102   { "udisp7", MEP_OPERAND_UDISP7, HW_H_UINT, 9, 7,
1103     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_7U9] } },
1104     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
1105 /* udisp7a2: comment */
1106   { "udisp7a2", MEP_OPERAND_UDISP7A2, HW_H_UINT, 9, 6,
1107     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_7U9A2] } },
1108     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_LONG, 0 } }, { { 2, 0 } } } }  },
1109 /* udisp7a4: comment */
1110   { "udisp7a4", MEP_OPERAND_UDISP7A4, HW_H_UINT, 9, 5,
1111     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_7U9A4] } },
1112     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_LONG, 0 } }, { { 4, 0 } } } }  },
1113 /* uimm7a4: comment */
1114   { "uimm7a4", MEP_OPERAND_UIMM7A4, HW_H_UINT, 9, 5,
1115     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_7U9A4] } },
1116     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_LONG, 0 } }, { { 4, 0 } } } }  },
1117 /* uimm24: immediate (24 bits) */
1118   { "uimm24", MEP_OPERAND_UIMM24, HW_H_UINT, 8, 24,
1119     { 2, { (const PTR) &MEP_F_24U8N_MULTI_IFIELD[0] } },
1120     { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
1121 /* cimm4: cache immed'te (4 bits) */
1122   { "cimm4", MEP_OPERAND_CIMM4, HW_H_UINT, 4, 4,
1123     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_RN] } },
1124     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
1125 /* cimm5: clip immediate (5 bits) */
1126   { "cimm5", MEP_OPERAND_CIMM5, HW_H_UINT, 24, 5,
1127     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_5U24] } },
1128     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
1129 /* cdisp10: comment */
1130   { "cdisp10", MEP_OPERAND_CDISP10, HW_H_SINT, 22, 10,
1131     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_CDISP10] } },
1132     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
1133 /* cdisp10a2: comment */
1134   { "cdisp10a2", MEP_OPERAND_CDISP10A2, HW_H_SINT, 22, 10,
1135     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_CDISP10] } },
1136     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
1137 /* cdisp10a4: comment */
1138   { "cdisp10a4", MEP_OPERAND_CDISP10A4, HW_H_SINT, 22, 10,
1139     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_CDISP10] } },
1140     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
1141 /* cdisp10a8: comment */
1142   { "cdisp10a8", MEP_OPERAND_CDISP10A8, HW_H_SINT, 22, 10,
1143     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_CDISP10] } },
1144     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
1145 /* zero: Zero operand */
1146   { "zero", MEP_OPERAND_ZERO, HW_H_SINT, 0, 0,
1147     { 0, { (const PTR) 0 } },
1148     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
1149 /* rl5: register Rl c5 */
1150   { "rl5", MEP_OPERAND_RL5, HW_H_GPR, 20, 4,
1151     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_RL5] } },
1152     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
1153 /* cdisp12: copro addend (12 bits) */
1154   { "cdisp12", MEP_OPERAND_CDISP12, HW_H_SINT, 20, 12,
1155     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_12S20] } },
1156     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
1157 /* c5rmuimm20: 20-bit immediate in rm and imm16 */
1158   { "c5rmuimm20", MEP_OPERAND_C5RMUIMM20, HW_H_UINT, 8, 20,
1159     { 2, { (const PTR) &MEP_F_C5_RMUIMM20_MULTI_IFIELD[0] } },
1160     { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
1161 /* c5rnmuimm24: 24-bit immediate in rn, rm, and imm16 */
1162   { "c5rnmuimm24", MEP_OPERAND_C5RNMUIMM24, HW_H_UINT, 4, 24,
1163     { 2, { (const PTR) &MEP_F_C5_RNMUIMM24_MULTI_IFIELD[0] } },
1164     { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
1165 /* cp_flag: branch condition register */
1166   { "cp_flag", MEP_OPERAND_CP_FLAG, HW_H_CCR, 0, 0,
1167     { 0, { (const PTR) 0 } },
1168     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
1169 /* croc: $CRo C3 */
1170   { "croc", MEP_OPERAND_CROC, HW_H_CR64, 7, 5,
1171     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_IVC2_5U7] } },
1172     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
1173 /* crqc: $CRq C3 */
1174   { "crqc", MEP_OPERAND_CRQC, HW_H_CR64, 21, 5,
1175     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_IVC2_5U21] } },
1176     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
1177 /* crpc: $CRp C3 */
1178   { "crpc", MEP_OPERAND_CRPC, HW_H_CR64, 26, 5,
1179     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_IVC2_5U26] } },
1180     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
1181 /* ivc-x-6-1: filler */
1182   { "ivc-x-6-1", MEP_OPERAND_IVC_X_6_1, HW_H_UINT, 6, 1,
1183     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_IVC2_1U6] } },
1184     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
1185 /* ivc-x-6-2: filler */
1186   { "ivc-x-6-2", MEP_OPERAND_IVC_X_6_2, HW_H_UINT, 6, 2,
1187     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_IVC2_2U6] } },
1188     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
1189 /* ivc-x-6-3: filler */
1190   { "ivc-x-6-3", MEP_OPERAND_IVC_X_6_3, HW_H_UINT, 6, 3,
1191     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_IVC2_3U6] } },
1192     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
1193 /* imm3p4: Imm3p4 */
1194   { "imm3p4", MEP_OPERAND_IMM3P4, HW_H_UINT, 4, 3,
1195     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_IVC2_3U4] } },
1196     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
1197 /* imm3p9: Imm3p9 */
1198   { "imm3p9", MEP_OPERAND_IMM3P9, HW_H_UINT, 9, 3,
1199     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_IVC2_3U9] } },
1200     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
1201 /* imm4p8: Imm4p8 */
1202   { "imm4p8", MEP_OPERAND_IMM4P8, HW_H_UINT, 8, 4,
1203     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_IVC2_4U8] } },
1204     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
1205 /* imm5p7: Imm5p7 */
1206   { "imm5p7", MEP_OPERAND_IMM5P7, HW_H_UINT, 7, 5,
1207     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_IVC2_5U7] } },
1208     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
1209 /* imm6p6: Imm6p6 */
1210   { "imm6p6", MEP_OPERAND_IMM6P6, HW_H_UINT, 6, 6,
1211     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_IVC2_6U6] } },
1212     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
1213 /* imm8p4: Imm8p4 */
1214   { "imm8p4", MEP_OPERAND_IMM8P4, HW_H_UINT, 4, 8,
1215     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_IVC2_8U4] } },
1216     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
1217 /* simm8p4: sImm8p4 */
1218   { "simm8p4", MEP_OPERAND_SIMM8P4, HW_H_SINT, 4, 8,
1219     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_IVC2_8S4] } },
1220     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
1221 /* imm3p5: Imm3p5 */
1222   { "imm3p5", MEP_OPERAND_IMM3P5, HW_H_UINT, 5, 3,
1223     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_IVC2_3U5] } },
1224     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
1225 /* imm3p12: Imm3p12 */
1226   { "imm3p12", MEP_OPERAND_IMM3P12, HW_H_UINT, 12, 3,
1227     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_IVC2_3U12] } },
1228     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
1229 /* imm4p4: Imm4p4 */
1230   { "imm4p4", MEP_OPERAND_IMM4P4, HW_H_UINT, 4, 4,
1231     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_IVC2_4U4] } },
1232     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
1233 /* imm4p10: Imm4p10 */
1234   { "imm4p10", MEP_OPERAND_IMM4P10, HW_H_UINT, 10, 4,
1235     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_IVC2_4U10] } },
1236     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
1237 /* imm5p8: Imm5p8 */
1238   { "imm5p8", MEP_OPERAND_IMM5P8, HW_H_UINT, 8, 5,
1239     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_IVC2_5U8] } },
1240     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
1241 /* imm5p3: Imm5p3 */
1242   { "imm5p3", MEP_OPERAND_IMM5P3, HW_H_UINT, 3, 5,
1243     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_IVC2_5U3] } },
1244     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
1245 /* imm6p2: Imm6p2 */
1246   { "imm6p2", MEP_OPERAND_IMM6P2, HW_H_UINT, 2, 6,
1247     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_IVC2_6U2] } },
1248     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
1249 /* imm5p23: Imm5p23 */
1250   { "imm5p23", MEP_OPERAND_IMM5P23, HW_H_UINT, 23, 5,
1251     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_IVC2_5U23] } },
1252     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
1253 /* imm3p25: Imm3p25 */
1254   { "imm3p25", MEP_OPERAND_IMM3P25, HW_H_UINT, 25, 3,
1255     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_IVC2_3U25] } },
1256     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
1257 /* imm8p0: Imm8p0 */
1258   { "imm8p0", MEP_OPERAND_IMM8P0, HW_H_UINT, 0, 8,
1259     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_IVC2_8U0] } },
1260     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
1261 /* simm8p0: sImm8p0 */
1262   { "simm8p0", MEP_OPERAND_SIMM8P0, HW_H_SINT, 0, 8,
1263     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_IVC2_8S0] } },
1264     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
1265 /* imm8p20: Imm8p20 */
1266   { "imm8p20", MEP_OPERAND_IMM8P20, HW_H_UINT, 20, 8,
1267     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_IVC2_8U20] } },
1268     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
1269 /* crop: $CRo Pn */
1270   { "crop", MEP_OPERAND_CROP, HW_H_CR64, 23, 5,
1271     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_IVC2_5U23] } },
1272     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
1273 /* crqp: $CRq Pn */
1274   { "crqp", MEP_OPERAND_CRQP, HW_H_CR64, 13, 5,
1275     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_IVC2_5U13] } },
1276     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
1277 /* crpp: $CRp Pn */
1278   { "crpp", MEP_OPERAND_CRPP, HW_H_CR64, 18, 5,
1279     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_IVC2_5U18] } },
1280     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
1281 /* ivc-x-0-2: filler */
1282   { "ivc-x-0-2", MEP_OPERAND_IVC_X_0_2, HW_H_UINT, 0, 2,
1283     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_IVC2_2U0] } },
1284     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
1285 /* ivc-x-0-3: filler */
1286   { "ivc-x-0-3", MEP_OPERAND_IVC_X_0_3, HW_H_UINT, 0, 3,
1287     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_IVC2_3U0] } },
1288     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
1289 /* ivc-x-0-4: filler */
1290   { "ivc-x-0-4", MEP_OPERAND_IVC_X_0_4, HW_H_UINT, 0, 4,
1291     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_IVC2_4U0] } },
1292     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
1293 /* ivc-x-0-5: filler */
1294   { "ivc-x-0-5", MEP_OPERAND_IVC_X_0_5, HW_H_UINT, 0, 5,
1295     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_IVC2_5U0] } },
1296     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
1297 /* imm16p0: Imm16p0 */
1298   { "imm16p0", MEP_OPERAND_IMM16P0, HW_H_UINT, 0, 16,
1299     { 2, { (const PTR) &MEP_F_IVC2_IMM16P0_MULTI_IFIELD[0] } },
1300     { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
1301 /* simm16p0: sImm16p0 */
1302   { "simm16p0", MEP_OPERAND_SIMM16P0, HW_H_SINT, 0, 16,
1303     { 2, { (const PTR) &MEP_F_IVC2_SIMM16P0_MULTI_IFIELD[0] } },
1304     { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
1305 /* ivc2rm: reg Rm */
1306   { "ivc2rm", MEP_OPERAND_IVC2RM, HW_H_GPR, 4, 4,
1307     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_IVC2_CRM] } },
1308     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } }, { { CDATA_REGNUM, 0 } }, { { 1, 0 } } } }  },
1309 /* ivc2crn: copro Rn (0-31, 64-bit */
1310   { "ivc2crn", MEP_OPERAND_IVC2CRN, HW_H_CR64, 0, 5,
1311     { 2, { (const PTR) &MEP_F_IVC2_CRNX_MULTI_IFIELD[0] } },
1312     { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } }, { { CDATA_REGNUM, 0 } }, { { 1, 0 } } } }  },
1313 /* ivc2ccrn: copro control reg CCRn */
1314   { "ivc2ccrn", MEP_OPERAND_IVC2CCRN, HW_H_CCR, 0, 6,
1315     { 2, { (const PTR) &MEP_F_IVC2_CCRN_MULTI_IFIELD[0] } },
1316     { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } }, { { CDATA_REGNUM, 0 } }, { { 1, 0 } } } }  },
1317 /* sentinel */
1318   { 0, 0, 0, 0, 0,
1319     { 0, { (const PTR) 0 } },
1320     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } }
1321 };
1322
1323 #undef A
1324
1325
1326 /* The instruction table.  */
1327
1328 #define OP(field) CGEN_SYNTAX_MAKE_FIELD (OPERAND (field))
1329 #if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
1330 #define A(a) (1 << CGEN_INSN_##a)
1331 #else
1332 #define A(a) (1 << CGEN_INSN_/**/a)
1333 #endif
1334
1335 static const CGEN_IBASE mep_cgen_insn_table[MAX_INSNS] =
1336 {
1337   /* Special null first entry.
1338      A `num' value of zero is thus invalid.
1339      Also, the special `invalid' insn resides here.  */
1340   { 0, 0, 0, 0, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } } },
1341 /* stcb $rn,($rma) */
1342   {
1343     MEP_INSN_STCB_R, "stcb_r", "stcb", 16,
1344     { 0|A(VOLATILE), { { { (1<<MACH_C5), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
1345   },
1346 /* ldcb $rn,($rma) */
1347   {
1348     MEP_INSN_LDCB_R, "ldcb_r", "ldcb", 16,
1349     { 0|A(VOLATILE), { { { (1<<MACH_C5), 0 } }, { { 1, "\xc0" } }, { { 3, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
1350   },
1351 /* pref $cimm4,($rma) */
1352   {
1353     MEP_INSN_PREF, "pref", "pref", 16,
1354     { 0|A(VOLATILE), { { { (1<<MACH_C5), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
1355   },
1356 /* pref $cimm4,$sdisp16($rma) */
1357   {
1358     MEP_INSN_PREFD, "prefd", "pref", 32,
1359     { 0|A(VOLATILE), { { { (1<<MACH_C5), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
1360   },
1361 /* casb3 $rl5,$rn,($rm) */
1362   {
1363     MEP_INSN_CASB3, "casb3", "casb3", 32,
1364     { 0|A(OPTIONAL_BIT_INSN)|A(VOLATILE), { { { (1<<MACH_C5), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
1365   },
1366 /* cash3 $rl5,$rn,($rm) */
1367   {
1368     MEP_INSN_CASH3, "cash3", "cash3", 32,
1369     { 0|A(OPTIONAL_BIT_INSN)|A(VOLATILE), { { { (1<<MACH_C5), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
1370   },
1371 /* casw3 $rl5,$rn,($rm) */
1372   {
1373     MEP_INSN_CASW3, "casw3", "casw3", 32,
1374     { 0|A(OPTIONAL_BIT_INSN)|A(VOLATILE), { { { (1<<MACH_C5), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
1375   },
1376 /* sbcp $crn,$cdisp12($rma) */
1377   {
1378     MEP_INSN_SBCP, "sbcp", "sbcp", 32,
1379     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_C5), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
1380   },
1381 /* lbcp $crn,$cdisp12($rma) */
1382   {
1383     MEP_INSN_LBCP, "lbcp", "lbcp", 32,
1384     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_C5), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
1385   },
1386 /* lbucp $crn,$cdisp12($rma) */
1387   {
1388     MEP_INSN_LBUCP, "lbucp", "lbucp", 32,
1389     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_C5), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
1390   },
1391 /* shcp $crn,$cdisp12($rma) */
1392   {
1393     MEP_INSN_SHCP, "shcp", "shcp", 32,
1394     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_C5), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
1395   },
1396 /* lhcp $crn,$cdisp12($rma) */
1397   {
1398     MEP_INSN_LHCP, "lhcp", "lhcp", 32,
1399     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_C5), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
1400   },
1401 /* lhucp $crn,$cdisp12($rma) */
1402   {
1403     MEP_INSN_LHUCP, "lhucp", "lhucp", 32,
1404     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_C5), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
1405   },
1406 /* lbucpa $crn,($rma+),$cdisp10 */
1407   {
1408     MEP_INSN_LBUCPA, "lbucpa", "lbucpa", 32,
1409     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_C5), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
1410   },
1411 /* lhucpa $crn,($rma+),$cdisp10a2 */
1412   {
1413     MEP_INSN_LHUCPA, "lhucpa", "lhucpa", 32,
1414     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_C5), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
1415   },
1416 /* lbucpm0 $crn,($rma+),$cdisp10 */
1417   {
1418     MEP_INSN_LBUCPM0, "lbucpm0", "lbucpm0", 32,
1419     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_C5), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
1420   },
1421 /* lhucpm0 $crn,($rma+),$cdisp10a2 */
1422   {
1423     MEP_INSN_LHUCPM0, "lhucpm0", "lhucpm0", 32,
1424     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_C5), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
1425   },
1426 /* lbucpm1 $crn,($rma+),$cdisp10 */
1427   {
1428     MEP_INSN_LBUCPM1, "lbucpm1", "lbucpm1", 32,
1429     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_C5), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
1430   },
1431 /* lhucpm1 $crn,($rma+),$cdisp10a2 */
1432   {
1433     MEP_INSN_LHUCPM1, "lhucpm1", "lhucpm1", 32,
1434     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_C5), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
1435   },
1436 /* uci $rn,$rm,$uimm16 */
1437   {
1438     MEP_INSN_UCI, "uci", "uci", 32,
1439     { 0|A(VOLATILE), { { { (1<<MACH_C5), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
1440   },
1441 /* dsp $rn,$rm,$uimm16 */
1442   {
1443     MEP_INSN_DSP, "dsp", "dsp", 32,
1444     { 0|A(VOLATILE), { { { (1<<MACH_C5), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
1445   },
1446 /* dsp0 $c5rnmuimm24 */
1447   {
1448     -1, "dsp0", "dsp0", 32,
1449     { 0|A(ALIAS)|A(NO_DIS)|A(VOLATILE), { { { (1<<MACH_C5), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
1450   },
1451 /* dsp1 $rn,$c5rmuimm20 */
1452   {
1453     -1, "dsp1", "dsp1", 32,
1454     { 0|A(ALIAS)|A(NO_DIS)|A(VOLATILE), { { { (1<<MACH_C5), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
1455   },
1456 /* sb $rnc,($rma) */
1457   {
1458     MEP_INSN_SB, "sb", "sb", 16,
1459     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
1460   },
1461 /* sh $rns,($rma) */
1462   {
1463     MEP_INSN_SH, "sh", "sh", 16,
1464     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
1465   },
1466 /* sw $rnl,($rma) */
1467   {
1468     MEP_INSN_SW, "sw", "sw", 16,
1469     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
1470   },
1471 /* lb $rnc,($rma) */
1472   {
1473     MEP_INSN_LB, "lb", "lb", 16,
1474     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 2, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
1475   },
1476 /* lh $rns,($rma) */
1477   {
1478     MEP_INSN_LH, "lh", "lh", 16,
1479     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 2, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
1480   },
1481 /* lw $rnl,($rma) */
1482   {
1483     MEP_INSN_LW, "lw", "lw", 16,
1484     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 2, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
1485   },
1486 /* lbu $rnuc,($rma) */
1487   {
1488     MEP_INSN_LBU, "lbu", "lbu", 16,
1489     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 2, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
1490   },
1491 /* lhu $rnus,($rma) */
1492   {
1493     MEP_INSN_LHU, "lhu", "lhu", 16,
1494     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 2, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
1495   },
1496 /* sw $rnl,$udisp7a4($spr) */
1497   {
1498     MEP_INSN_SW_SP, "sw-sp", "sw", 16,
1499     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
1500   },
1501 /* lw $rnl,$udisp7a4($spr) */
1502   {
1503     MEP_INSN_LW_SP, "lw-sp", "lw", 16,
1504     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 2, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
1505   },
1506 /* sb $rn3c,$udisp7($tpr) */
1507   {
1508     MEP_INSN_SB_TP, "sb-tp", "sb", 16,
1509     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
1510   },
1511 /* sh $rn3s,$udisp7a2($tpr) */
1512   {
1513     MEP_INSN_SH_TP, "sh-tp", "sh", 16,
1514     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
1515   },
1516 /* sw $rn3l,$udisp7a4($tpr) */
1517   {
1518     MEP_INSN_SW_TP, "sw-tp", "sw", 16,
1519     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
1520   },
1521 /* lb $rn3c,$udisp7($tpr) */
1522   {
1523     MEP_INSN_LB_TP, "lb-tp", "lb", 16,
1524     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 2, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
1525   },
1526 /* lh $rn3s,$udisp7a2($tpr) */
1527   {
1528     MEP_INSN_LH_TP, "lh-tp", "lh", 16,
1529     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 2, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
1530   },
1531 /* lw $rn3l,$udisp7a4($tpr) */
1532   {
1533     MEP_INSN_LW_TP, "lw-tp", "lw", 16,
1534     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 2, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
1535   },
1536 /* lbu $rn3uc,$udisp7($tpr) */
1537   {
1538     MEP_INSN_LBU_TP, "lbu-tp", "lbu", 16,
1539     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 2, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
1540   },
1541 /* lhu $rn3us,$udisp7a2($tpr) */
1542   {
1543     MEP_INSN_LHU_TP, "lhu-tp", "lhu", 16,
1544     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 2, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
1545   },
1546 /* sb $rnc,$sdisp16($rma) */
1547   {
1548     MEP_INSN_SB16, "sb16", "sb", 32,
1549     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
1550   },
1551 /* sh $rns,$sdisp16($rma) */
1552   {
1553     MEP_INSN_SH16, "sh16", "sh", 32,
1554     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
1555   },
1556 /* sw $rnl,$sdisp16($rma) */
1557   {
1558     MEP_INSN_SW16, "sw16", "sw", 32,
1559     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
1560   },
1561 /* lb $rnc,$sdisp16($rma) */
1562   {
1563     MEP_INSN_LB16, "lb16", "lb", 32,
1564     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 2, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
1565   },
1566 /* lh $rns,$sdisp16($rma) */
1567   {
1568     MEP_INSN_LH16, "lh16", "lh", 32,
1569     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 2, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
1570   },
1571 /* lw $rnl,$sdisp16($rma) */
1572   {
1573     MEP_INSN_LW16, "lw16", "lw", 32,
1574     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 2, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
1575   },
1576 /* lbu $rnuc,$sdisp16($rma) */
1577   {
1578     MEP_INSN_LBU16, "lbu16", "lbu", 32,
1579     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 2, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
1580   },
1581 /* lhu $rnus,$sdisp16($rma) */
1582   {
1583     MEP_INSN_LHU16, "lhu16", "lhu", 32,
1584     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 2, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
1585   },
1586 /* sw $rnl,($addr24a4) */
1587   {
1588     MEP_INSN_SW24, "sw24", "sw", 32,
1589     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
1590   },
1591 /* lw $rnl,($addr24a4) */
1592   {
1593     MEP_INSN_LW24, "lw24", "lw", 32,
1594     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 2, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
1595   },
1596 /* extb $rn */
1597   {
1598     MEP_INSN_EXTB, "extb", "extb", 16,
1599     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
1600   },
1601 /* exth $rn */
1602   {
1603     MEP_INSN_EXTH, "exth", "exth", 16,
1604     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
1605   },
1606 /* extub $rn */
1607   {
1608     MEP_INSN_EXTUB, "extub", "extub", 16,
1609     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
1610   },
1611 /* extuh $rn */
1612   {
1613     MEP_INSN_EXTUH, "extuh", "extuh", 16,
1614     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
1615   },
1616 /* ssarb $udisp2($rm) */
1617   {
1618     MEP_INSN_SSARB, "ssarb", "ssarb", 16,
1619     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
1620   },
1621 /* mov $rn,$rm */
1622   {
1623     MEP_INSN_MOV, "mov", "mov", 16,
1624     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
1625   },
1626 /* mov $rn,$simm8 */
1627   {
1628     MEP_INSN_MOVI8, "movi8", "mov", 16,
1629     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
1630   },
1631 /* mov $rn,$simm16 */
1632   {
1633     MEP_INSN_MOVI16, "movi16", "mov", 32,
1634     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
1635   },
1636 /* movu $rn3,$uimm24 */
1637   {
1638     MEP_INSN_MOVU24, "movu24", "movu", 32,
1639     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
1640   },
1641 /* movu $rn,$uimm16 */
1642   {
1643     MEP_INSN_MOVU16, "movu16", "movu", 32,
1644     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
1645   },
1646 /* movh $rn,$uimm16 */
1647   {
1648     MEP_INSN_MOVH, "movh", "movh", 32,
1649     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
1650   },
1651 /* add3 $rl,$rn,$rm */
1652   {
1653     MEP_INSN_ADD3, "add3", "add3", 16,
1654     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
1655   },
1656 /* add $rn,$simm6 */
1657   {
1658     MEP_INSN_ADD, "add", "add", 16,
1659     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
1660   },
1661 /* add3 $rn,$spr,$uimm7a4 */
1662   {
1663     MEP_INSN_ADD3I, "add3i", "add3", 16,
1664     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
1665   },
1666 /* advck3 \$0,$rn,$rm */
1667   {
1668     MEP_INSN_ADVCK3, "advck3", "advck3", 16,
1669     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
1670   },
1671 /* sub $rn,$rm */
1672   {
1673     MEP_INSN_SUB, "sub", "sub", 16,
1674     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
1675   },
1676 /* sbvck3 \$0,$rn,$rm */
1677   {
1678     MEP_INSN_SBVCK3, "sbvck3", "sbvck3", 16,
1679     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
1680   },
1681 /* neg $rn,$rm */
1682   {
1683     MEP_INSN_NEG, "neg", "neg", 16,
1684     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
1685   },
1686 /* slt3 \$0,$rn,$rm */
1687   {
1688     MEP_INSN_SLT3, "slt3", "slt3", 16,
1689     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
1690   },
1691 /* sltu3 \$0,$rn,$rm */
1692   {
1693     MEP_INSN_SLTU3, "sltu3", "sltu3", 16,
1694     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
1695   },
1696 /* slt3 \$0,$rn,$uimm5 */
1697   {
1698     MEP_INSN_SLT3I, "slt3i", "slt3", 16,
1699     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
1700   },
1701 /* sltu3 \$0,$rn,$uimm5 */
1702   {
1703     MEP_INSN_SLTU3I, "sltu3i", "sltu3", 16,
1704     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
1705   },
1706 /* sl1ad3 \$0,$rn,$rm */
1707   {
1708     MEP_INSN_SL1AD3, "sl1ad3", "sl1ad3", 16,
1709     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
1710   },
1711 /* sl2ad3 \$0,$rn,$rm */
1712   {
1713     MEP_INSN_SL2AD3, "sl2ad3", "sl2ad3", 16,
1714     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
1715   },
1716 /* add3 $rn,$rm,$simm16 */
1717   {
1718     MEP_INSN_ADD3X, "add3x", "add3", 32,
1719     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
1720   },
1721 /* slt3 $rn,$rm,$simm16 */
1722   {
1723     MEP_INSN_SLT3X, "slt3x", "slt3", 32,
1724     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
1725   },
1726 /* sltu3 $rn,$rm,$uimm16 */
1727   {
1728     MEP_INSN_SLTU3X, "sltu3x", "sltu3", 32,
1729     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
1730   },
1731 /* or $rn,$rm */
1732   {
1733     MEP_INSN_OR, "or", "or", 16,
1734     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
1735   },
1736 /* and $rn,$rm */
1737   {
1738     MEP_INSN_AND, "and", "and", 16,
1739     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
1740   },
1741 /* xor $rn,$rm */
1742   {
1743     MEP_INSN_XOR, "xor", "xor", 16,
1744     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
1745   },
1746 /* nor $rn,$rm */
1747   {
1748     MEP_INSN_NOR, "nor", "nor", 16,
1749     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
1750   },
1751 /* or3 $rn,$rm,$uimm16 */
1752   {
1753     MEP_INSN_OR3, "or3", "or3", 32,
1754     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
1755   },
1756 /* and3 $rn,$rm,$uimm16 */
1757   {
1758     MEP_INSN_AND3, "and3", "and3", 32,
1759     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
1760   },
1761 /* xor3 $rn,$rm,$uimm16 */
1762   {
1763     MEP_INSN_XOR3, "xor3", "xor3", 32,
1764     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
1765   },
1766 /* sra $rn,$rm */
1767   {
1768     MEP_INSN_SRA, "sra", "sra", 16,
1769     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
1770   },
1771 /* srl $rn,$rm */
1772   {
1773     MEP_INSN_SRL, "srl", "srl", 16,
1774     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
1775   },
1776 /* sll $rn,$rm */
1777   {
1778     MEP_INSN_SLL, "sll", "sll", 16,
1779     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
1780   },
1781 /* sra $rn,$uimm5 */
1782   {
1783     MEP_INSN_SRAI, "srai", "sra", 16,
1784     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
1785   },
1786 /* srl $rn,$uimm5 */
1787   {
1788     MEP_INSN_SRLI, "srli", "srl", 16,
1789     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
1790   },
1791 /* sll $rn,$uimm5 */
1792   {
1793     MEP_INSN_SLLI, "slli", "sll", 16,
1794     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
1795   },
1796 /* sll3 \$0,$rn,$uimm5 */
1797   {
1798     MEP_INSN_SLL3, "sll3", "sll3", 16,
1799     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
1800   },
1801 /* fsft $rn,$rm */
1802   {
1803     MEP_INSN_FSFT, "fsft", "fsft", 16,
1804     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
1805   },
1806 /* bra $pcrel12a2 */
1807   {
1808     MEP_INSN_BRA, "bra", "bra", 16,
1809     { 0|A(RELAXABLE)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
1810   },
1811 /* beqz $rn,$pcrel8a2 */
1812   {
1813     MEP_INSN_BEQZ, "beqz", "beqz", 16,
1814     { 0|A(RELAXABLE)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
1815   },
1816 /* bnez $rn,$pcrel8a2 */
1817   {
1818     MEP_INSN_BNEZ, "bnez", "bnez", 16,
1819     { 0|A(RELAXABLE)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
1820   },
1821 /* beqi $rn,$uimm4,$pcrel17a2 */
1822   {
1823     MEP_INSN_BEQI, "beqi", "beqi", 32,
1824     { 0|A(RELAXABLE)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
1825   },
1826 /* bnei $rn,$uimm4,$pcrel17a2 */
1827   {
1828     MEP_INSN_BNEI, "bnei", "bnei", 32,
1829     { 0|A(RELAXABLE)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
1830   },
1831 /* blti $rn,$uimm4,$pcrel17a2 */
1832   {
1833     MEP_INSN_BLTI, "blti", "blti", 32,
1834     { 0|A(RELAXABLE)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
1835   },
1836 /* bgei $rn,$uimm4,$pcrel17a2 */
1837   {
1838     MEP_INSN_BGEI, "bgei", "bgei", 32,
1839     { 0|A(RELAXABLE)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
1840   },
1841 /* beq $rn,$rm,$pcrel17a2 */
1842   {
1843     MEP_INSN_BEQ, "beq", "beq", 32,
1844     { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
1845   },
1846 /* bne $rn,$rm,$pcrel17a2 */
1847   {
1848     MEP_INSN_BNE, "bne", "bne", 32,
1849     { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
1850   },
1851 /* bsr $pcrel12a2 */
1852   {
1853     MEP_INSN_BSR12, "bsr12", "bsr", 16,
1854     { 0|A(RELAXABLE)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
1855   },
1856 /* bsr $pcrel24a2 */
1857   {
1858     MEP_INSN_BSR24, "bsr24", "bsr", 32,
1859     { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
1860   },
1861 /* jmp $rm */
1862   {
1863     MEP_INSN_JMP, "jmp", "jmp", 16,
1864     { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
1865   },
1866 /* jmp $pcabs24a2 */
1867   {
1868     MEP_INSN_JMP24, "jmp24", "jmp", 32,
1869     { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
1870   },
1871 /* jsr $rm */
1872   {
1873     MEP_INSN_JSR, "jsr", "jsr", 16,
1874     { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
1875   },
1876 /* ret */
1877   {
1878     MEP_INSN_RET, "ret", "ret", 16,
1879     { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
1880   },
1881 /* repeat $rn,$pcrel17a2 */
1882   {
1883     MEP_INSN_REPEAT, "repeat", "repeat", 32,
1884     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
1885   },
1886 /* erepeat $pcrel17a2 */
1887   {
1888     MEP_INSN_EREPEAT, "erepeat", "erepeat", 32,
1889     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
1890   },
1891 /* stc $rn,\$lp */
1892   {
1893     MEP_INSN_STC_LP, "stc_lp", "stc", 16,
1894     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
1895   },
1896 /* stc $rn,\$hi */
1897   {
1898     MEP_INSN_STC_HI, "stc_hi", "stc", 16,
1899     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
1900   },
1901 /* stc $rn,\$lo */
1902   {
1903     MEP_INSN_STC_LO, "stc_lo", "stc", 16,
1904     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
1905   },
1906 /* stc $rn,$csrn */
1907   {
1908     MEP_INSN_STC, "stc", "stc", 16,
1909     { 0|A(VOLATILE), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
1910   },
1911 /* ldc $rn,\$lp */
1912   {
1913     MEP_INSN_LDC_LP, "ldc_lp", "ldc", 16,
1914     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
1915   },
1916 /* ldc $rn,\$hi */
1917   {
1918     MEP_INSN_LDC_HI, "ldc_hi", "ldc", 16,
1919     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
1920   },
1921 /* ldc $rn,\$lo */
1922   {
1923     MEP_INSN_LDC_LO, "ldc_lo", "ldc", 16,
1924     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
1925   },
1926 /* ldc $rn,$csrn */
1927   {
1928     MEP_INSN_LDC, "ldc", "ldc", 16,
1929     { 0|A(VOLATILE), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 2, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
1930   },
1931 /* di */
1932   {
1933     MEP_INSN_DI, "di", "di", 16,
1934     { 0|A(VOLATILE), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
1935   },
1936 /* ei */
1937   {
1938     MEP_INSN_EI, "ei", "ei", 16,
1939     { 0|A(VOLATILE), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
1940   },
1941 /* reti */
1942   {
1943     MEP_INSN_RETI, "reti", "reti", 16,
1944     { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
1945   },
1946 /* halt */
1947   {
1948     MEP_INSN_HALT, "halt", "halt", 16,
1949     { 0|A(VOLATILE), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
1950   },
1951 /* sleep */
1952   {
1953     MEP_INSN_SLEEP, "sleep", "sleep", 16,
1954     { 0|A(VOLATILE), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
1955   },
1956 /* swi $uimm2 */
1957   {
1958     MEP_INSN_SWI, "swi", "swi", 16,
1959     { 0|A(VOLATILE)|A(MAY_TRAP), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
1960   },
1961 /* break */
1962   {
1963     MEP_INSN_BREAK, "break", "break", 16,
1964     { 0|A(VOLATILE)|A(MAY_TRAP)|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
1965   },
1966 /* syncm */
1967   {
1968     MEP_INSN_SYNCM, "syncm", "syncm", 16,
1969     { 0|A(VOLATILE), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
1970   },
1971 /* stcb $rn,$uimm16 */
1972   {
1973     MEP_INSN_STCB, "stcb", "stcb", 32,
1974     { 0|A(VOLATILE), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
1975   },
1976 /* ldcb $rn,$uimm16 */
1977   {
1978     MEP_INSN_LDCB, "ldcb", "ldcb", 32,
1979     { 0|A(VOLATILE), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 3, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
1980   },
1981 /* bsetm ($rma),$uimm3 */
1982   {
1983     MEP_INSN_BSETM, "bsetm", "bsetm", 16,
1984     { 0|A(OPTIONAL_BIT_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
1985   },
1986 /* bclrm ($rma),$uimm3 */
1987   {
1988     MEP_INSN_BCLRM, "bclrm", "bclrm", 16,
1989     { 0|A(OPTIONAL_BIT_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
1990   },
1991 /* bnotm ($rma),$uimm3 */
1992   {
1993     MEP_INSN_BNOTM, "bnotm", "bnotm", 16,
1994     { 0|A(OPTIONAL_BIT_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
1995   },
1996 /* btstm \$0,($rma),$uimm3 */
1997   {
1998     MEP_INSN_BTSTM, "btstm", "btstm", 16,
1999     { 0|A(OPTIONAL_BIT_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
2000   },
2001 /* tas $rn,($rma) */
2002   {
2003     MEP_INSN_TAS, "tas", "tas", 16,
2004     { 0|A(OPTIONAL_BIT_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
2005   },
2006 /* cache $cimm4,($rma) */
2007   {
2008     MEP_INSN_CACHE, "cache", "cache", 16,
2009     { 0|A(VOLATILE), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
2010   },
2011 /* mul $rn,$rm */
2012   {
2013     MEP_INSN_MUL, "mul", "mul", 16,
2014     { 0|A(OPTIONAL_MUL_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
2015   },
2016 /* mulu $rn,$rm */
2017   {
2018     MEP_INSN_MULU, "mulu", "mulu", 16,
2019     { 0|A(OPTIONAL_MUL_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
2020   },
2021 /* mulr $rn,$rm */
2022   {
2023     MEP_INSN_MULR, "mulr", "mulr", 16,
2024     { 0|A(OPTIONAL_MUL_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 3, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
2025   },
2026 /* mulru $rn,$rm */
2027   {
2028     MEP_INSN_MULRU, "mulru", "mulru", 16,
2029     { 0|A(OPTIONAL_MUL_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 3, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
2030   },
2031 /* madd $rn,$rm */
2032   {
2033     MEP_INSN_MADD, "madd", "madd", 32,
2034     { 0|A(OPTIONAL_MUL_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
2035   },
2036 /* maddu $rn,$rm */
2037   {
2038     MEP_INSN_MADDU, "maddu", "maddu", 32,
2039     { 0|A(OPTIONAL_MUL_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
2040   },
2041 /* maddr $rn,$rm */
2042   {
2043     MEP_INSN_MADDR, "maddr", "maddr", 32,
2044     { 0|A(OPTIONAL_MUL_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 3, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
2045   },
2046 /* maddru $rn,$rm */
2047   {
2048     MEP_INSN_MADDRU, "maddru", "maddru", 32,
2049     { 0|A(OPTIONAL_MUL_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 3, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
2050   },
2051 /* div $rn,$rm */
2052   {
2053     MEP_INSN_DIV, "div", "div", 16,
2054     { 0|A(MAY_TRAP)|A(OPTIONAL_DIV_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 34, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
2055   },
2056 /* divu $rn,$rm */
2057   {
2058     MEP_INSN_DIVU, "divu", "divu", 16,
2059     { 0|A(MAY_TRAP)|A(OPTIONAL_DIV_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 34, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
2060   },
2061 /* dret */
2062   {
2063     MEP_INSN_DRET, "dret", "dret", 16,
2064     { 0|A(OPTIONAL_DEBUG_INSN)|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
2065   },
2066 /* dbreak */
2067   {
2068     MEP_INSN_DBREAK, "dbreak", "dbreak", 16,
2069     { 0|A(VOLATILE)|A(MAY_TRAP)|A(OPTIONAL_DEBUG_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
2070   },
2071 /* ldz $rn,$rm */
2072   {
2073     MEP_INSN_LDZ, "ldz", "ldz", 32,
2074     { 0|A(OPTIONAL_LDZ_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
2075   },
2076 /* abs $rn,$rm */
2077   {
2078     MEP_INSN_ABS, "abs", "abs", 32,
2079     { 0|A(OPTIONAL_ABS_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
2080   },
2081 /* ave $rn,$rm */
2082   {
2083     MEP_INSN_AVE, "ave", "ave", 32,
2084     { 0|A(OPTIONAL_AVE_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
2085   },
2086 /* min $rn,$rm */
2087   {
2088     MEP_INSN_MIN, "min", "min", 32,
2089     { 0|A(OPTIONAL_MINMAX_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
2090   },
2091 /* max $rn,$rm */
2092   {
2093     MEP_INSN_MAX, "max", "max", 32,
2094     { 0|A(OPTIONAL_MINMAX_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
2095   },
2096 /* minu $rn,$rm */
2097   {
2098     MEP_INSN_MINU, "minu", "minu", 32,
2099     { 0|A(OPTIONAL_MINMAX_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
2100   },
2101 /* maxu $rn,$rm */
2102   {
2103     MEP_INSN_MAXU, "maxu", "maxu", 32,
2104     { 0|A(OPTIONAL_MINMAX_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
2105   },
2106 /* clip $rn,$cimm5 */
2107   {
2108     MEP_INSN_CLIP, "clip", "clip", 32,
2109     { 0|A(OPTIONAL_CLIP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
2110   },
2111 /* clipu $rn,$cimm5 */
2112   {
2113     MEP_INSN_CLIPU, "clipu", "clipu", 32,
2114     { 0|A(OPTIONAL_CLIP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
2115   },
2116 /* sadd $rn,$rm */
2117   {
2118     MEP_INSN_SADD, "sadd", "sadd", 32,
2119     { 0|A(OPTIONAL_SAT_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
2120   },
2121 /* ssub $rn,$rm */
2122   {
2123     MEP_INSN_SSUB, "ssub", "ssub", 32,
2124     { 0|A(OPTIONAL_SAT_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
2125   },
2126 /* saddu $rn,$rm */
2127   {
2128     MEP_INSN_SADDU, "saddu", "saddu", 32,
2129     { 0|A(OPTIONAL_SAT_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
2130   },
2131 /* ssubu $rn,$rm */
2132   {
2133     MEP_INSN_SSUBU, "ssubu", "ssubu", 32,
2134     { 0|A(OPTIONAL_SAT_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
2135   },
2136 /* swcp $crn,($rma) */
2137   {
2138     MEP_INSN_SWCP, "swcp", "swcp", 16,
2139     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
2140   },
2141 /* lwcp $crn,($rma) */
2142   {
2143     MEP_INSN_LWCP, "lwcp", "lwcp", 16,
2144     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
2145   },
2146 /* smcp $crn64,($rma) */
2147   {
2148     MEP_INSN_SMCP, "smcp", "smcp", 16,
2149     { 0|A(OPTIONAL_CP64_INSN)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
2150   },
2151 /* lmcp $crn64,($rma) */
2152   {
2153     MEP_INSN_LMCP, "lmcp", "lmcp", 16,
2154     { 0|A(OPTIONAL_CP64_INSN)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
2155   },
2156 /* swcpi $crn,($rma+) */
2157   {
2158     MEP_INSN_SWCPI, "swcpi", "swcpi", 16,
2159     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
2160   },
2161 /* lwcpi $crn,($rma+) */
2162   {
2163     MEP_INSN_LWCPI, "lwcpi", "lwcpi", 16,
2164     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
2165   },
2166 /* smcpi $crn64,($rma+) */
2167   {
2168     MEP_INSN_SMCPI, "smcpi", "smcpi", 16,
2169     { 0|A(OPTIONAL_CP64_INSN)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
2170   },
2171 /* lmcpi $crn64,($rma+) */
2172   {
2173     MEP_INSN_LMCPI, "lmcpi", "lmcpi", 16,
2174     { 0|A(OPTIONAL_CP64_INSN)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
2175   },
2176 /* swcp $crn,$sdisp16($rma) */
2177   {
2178     MEP_INSN_SWCP16, "swcp16", "swcp", 32,
2179     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
2180   },
2181 /* lwcp $crn,$sdisp16($rma) */
2182   {
2183     MEP_INSN_LWCP16, "lwcp16", "lwcp", 32,
2184     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
2185   },
2186 /* smcp $crn64,$sdisp16($rma) */
2187   {
2188     MEP_INSN_SMCP16, "smcp16", "smcp", 32,
2189     { 0|A(OPTIONAL_CP64_INSN)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
2190   },
2191 /* lmcp $crn64,$sdisp16($rma) */
2192   {
2193     MEP_INSN_LMCP16, "lmcp16", "lmcp", 32,
2194     { 0|A(OPTIONAL_CP64_INSN)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
2195   },
2196 /* sbcpa $crn,($rma+),$cdisp10 */
2197   {
2198     MEP_INSN_SBCPA, "sbcpa", "sbcpa", 32,
2199     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
2200   },
2201 /* lbcpa $crn,($rma+),$cdisp10 */
2202   {
2203     MEP_INSN_LBCPA, "lbcpa", "lbcpa", 32,
2204     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
2205   },
2206 /* shcpa $crn,($rma+),$cdisp10a2 */
2207   {
2208     MEP_INSN_SHCPA, "shcpa", "shcpa", 32,
2209     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
2210   },
2211 /* lhcpa $crn,($rma+),$cdisp10a2 */
2212   {
2213     MEP_INSN_LHCPA, "lhcpa", "lhcpa", 32,
2214     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
2215   },
2216 /* swcpa $crn,($rma+),$cdisp10a4 */
2217   {
2218     MEP_INSN_SWCPA, "swcpa", "swcpa", 32,
2219     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
2220   },
2221 /* lwcpa $crn,($rma+),$cdisp10a4 */
2222   {
2223     MEP_INSN_LWCPA, "lwcpa", "lwcpa", 32,
2224     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
2225   },
2226 /* smcpa $crn64,($rma+),$cdisp10a8 */
2227   {
2228     MEP_INSN_SMCPA, "smcpa", "smcpa", 32,
2229     { 0|A(OPTIONAL_CP64_INSN)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
2230   },
2231 /* lmcpa $crn64,($rma+),$cdisp10a8 */
2232   {
2233     MEP_INSN_LMCPA, "lmcpa", "lmcpa", 32,
2234     { 0|A(OPTIONAL_CP64_INSN)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
2235   },
2236 /* sbcpm0 $crn,($rma+),$cdisp10 */
2237   {
2238     MEP_INSN_SBCPM0, "sbcpm0", "sbcpm0", 32,
2239     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
2240   },
2241 /* lbcpm0 $crn,($rma+),$cdisp10 */
2242   {
2243     MEP_INSN_LBCPM0, "lbcpm0", "lbcpm0", 32,
2244     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
2245   },
2246 /* shcpm0 $crn,($rma+),$cdisp10a2 */
2247   {
2248     MEP_INSN_SHCPM0, "shcpm0", "shcpm0", 32,
2249     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
2250   },
2251 /* lhcpm0 $crn,($rma+),$cdisp10a2 */
2252   {
2253     MEP_INSN_LHCPM0, "lhcpm0", "lhcpm0", 32,
2254     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
2255   },
2256 /* swcpm0 $crn,($rma+),$cdisp10a4 */
2257   {
2258     MEP_INSN_SWCPM0, "swcpm0", "swcpm0", 32,
2259     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
2260   },
2261 /* lwcpm0 $crn,($rma+),$cdisp10a4 */
2262   {
2263     MEP_INSN_LWCPM0, "lwcpm0", "lwcpm0", 32,
2264     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
2265   },
2266 /* smcpm0 $crn64,($rma+),$cdisp10a8 */
2267   {
2268     MEP_INSN_SMCPM0, "smcpm0", "smcpm0", 32,
2269     { 0|A(OPTIONAL_CP64_INSN)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
2270   },
2271 /* lmcpm0 $crn64,($rma+),$cdisp10a8 */
2272   {
2273     MEP_INSN_LMCPM0, "lmcpm0", "lmcpm0", 32,
2274     { 0|A(OPTIONAL_CP64_INSN)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
2275   },
2276 /* sbcpm1 $crn,($rma+),$cdisp10 */
2277   {
2278     MEP_INSN_SBCPM1, "sbcpm1", "sbcpm1", 32,
2279     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
2280   },
2281 /* lbcpm1 $crn,($rma+),$cdisp10 */
2282   {
2283     MEP_INSN_LBCPM1, "lbcpm1", "lbcpm1", 32,
2284     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
2285   },
2286 /* shcpm1 $crn,($rma+),$cdisp10a2 */
2287   {
2288     MEP_INSN_SHCPM1, "shcpm1", "shcpm1", 32,
2289     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
2290   },
2291 /* lhcpm1 $crn,($rma+),$cdisp10a2 */
2292   {
2293     MEP_INSN_LHCPM1, "lhcpm1", "lhcpm1", 32,
2294     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
2295   },
2296 /* swcpm1 $crn,($rma+),$cdisp10a4 */
2297   {
2298     MEP_INSN_SWCPM1, "swcpm1", "swcpm1", 32,
2299     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
2300   },
2301 /* lwcpm1 $crn,($rma+),$cdisp10a4 */
2302   {
2303     MEP_INSN_LWCPM1, "lwcpm1", "lwcpm1", 32,
2304     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
2305   },
2306 /* smcpm1 $crn64,($rma+),$cdisp10a8 */
2307   {
2308     MEP_INSN_SMCPM1, "smcpm1", "smcpm1", 32,
2309     { 0|A(OPTIONAL_CP64_INSN)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
2310   },
2311 /* lmcpm1 $crn64,($rma+),$cdisp10a8 */
2312   {
2313     MEP_INSN_LMCPM1, "lmcpm1", "lmcpm1", 32,
2314     { 0|A(OPTIONAL_CP64_INSN)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
2315   },
2316 /* bcpeq $cccc,$pcrel17a2 */
2317   {
2318     MEP_INSN_BCPEQ, "bcpeq", "bcpeq", 32,
2319     { 0|A(RELAXABLE)|A(OPTIONAL_CP_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
2320   },
2321 /* bcpne $cccc,$pcrel17a2 */
2322   {
2323     MEP_INSN_BCPNE, "bcpne", "bcpne", 32,
2324     { 0|A(RELAXABLE)|A(OPTIONAL_CP_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
2325   },
2326 /* bcpat $cccc,$pcrel17a2 */
2327   {
2328     MEP_INSN_BCPAT, "bcpat", "bcpat", 32,
2329     { 0|A(RELAXABLE)|A(OPTIONAL_CP_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
2330   },
2331 /* bcpaf $cccc,$pcrel17a2 */
2332   {
2333     MEP_INSN_BCPAF, "bcpaf", "bcpaf", 32,
2334     { 0|A(RELAXABLE)|A(OPTIONAL_CP_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
2335   },
2336 /* synccp */
2337   {
2338     MEP_INSN_SYNCCP, "synccp", "synccp", 16,
2339     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
2340   },
2341 /* jsrv $rm */
2342   {
2343     MEP_INSN_JSRV, "jsrv", "jsrv", 16,
2344     { 0|A(OPTIONAL_CP_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
2345   },
2346 /* bsrv $pcrel24a2 */
2347   {
2348     MEP_INSN_BSRV, "bsrv", "bsrv", 32,
2349     { 0|A(OPTIONAL_CP_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
2350   },
2351 /* --syscall-- */
2352   {
2353     MEP_INSN_SIM_SYSCALL, "sim-syscall", "--syscall--", 16,
2354     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
2355   },
2356 /* --reserved-- */
2357   {
2358     MEP_INSN_RI_0, "ri-0", "--reserved--", 16,
2359     { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
2360   },
2361 /* --reserved-- */
2362   {
2363     MEP_INSN_RI_1, "ri-1", "--reserved--", 16,
2364     { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
2365   },
2366 /* --reserved-- */
2367   {
2368     MEP_INSN_RI_2, "ri-2", "--reserved--", 16,
2369     { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
2370   },
2371 /* --reserved-- */
2372   {
2373     MEP_INSN_RI_3, "ri-3", "--reserved--", 16,
2374     { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
2375   },
2376 /* --reserved-- */
2377   {
2378     MEP_INSN_RI_4, "ri-4", "--reserved--", 16,
2379     { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
2380   },
2381 /* --reserved-- */
2382   {
2383     MEP_INSN_RI_5, "ri-5", "--reserved--", 16,
2384     { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
2385   },
2386 /* --reserved-- */
2387   {
2388     MEP_INSN_RI_6, "ri-6", "--reserved--", 16,
2389     { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
2390   },
2391 /* --reserved-- */
2392   {
2393     MEP_INSN_RI_7, "ri-7", "--reserved--", 16,
2394     { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
2395   },
2396 /* --reserved-- */
2397   {
2398     MEP_INSN_RI_8, "ri-8", "--reserved--", 16,
2399     { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
2400   },
2401 /* --reserved-- */
2402   {
2403     MEP_INSN_RI_9, "ri-9", "--reserved--", 16,
2404     { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
2405   },
2406 /* --reserved-- */
2407   {
2408     MEP_INSN_RI_10, "ri-10", "--reserved--", 16,
2409     { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
2410   },
2411 /* --reserved-- */
2412   {
2413     MEP_INSN_RI_11, "ri-11", "--reserved--", 16,
2414     { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
2415   },
2416 /* --reserved-- */
2417   {
2418     MEP_INSN_RI_12, "ri-12", "--reserved--", 16,
2419     { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
2420   },
2421 /* --reserved-- */
2422   {
2423     MEP_INSN_RI_13, "ri-13", "--reserved--", 16,
2424     { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
2425   },
2426 /* --reserved-- */
2427   {
2428     MEP_INSN_RI_14, "ri-14", "--reserved--", 16,
2429     { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
2430   },
2431 /* --reserved-- */
2432   {
2433     MEP_INSN_RI_15, "ri-15", "--reserved--", 16,
2434     { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
2435   },
2436 /* --reserved-- */
2437   {
2438     MEP_INSN_RI_17, "ri-17", "--reserved--", 16,
2439     { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
2440   },
2441 /* --reserved-- */
2442   {
2443     MEP_INSN_RI_20, "ri-20", "--reserved--", 16,
2444     { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
2445   },
2446 /* --reserved-- */
2447   {
2448     MEP_INSN_RI_21, "ri-21", "--reserved--", 16,
2449     { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
2450   },
2451 /* --reserved-- */
2452   {
2453     MEP_INSN_RI_22, "ri-22", "--reserved--", 16,
2454     { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
2455   },
2456 /* --reserved-- */
2457   {
2458     MEP_INSN_RI_23, "ri-23", "--reserved--", 16,
2459     { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
2460   },
2461 /* --reserved-- */
2462   {
2463     MEP_INSN_RI_26, "ri-26", "--reserved--", 16,
2464     { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
2465   },
2466 /* cmov $crnx64,$rm */
2467   {
2468     MEP_INSN_CMOV_CRN_RM, "cmov-crn-rm", "cmov", 32,
2469     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
2470   },
2471 /* cmov $rm,$crnx64 */
2472   {
2473     MEP_INSN_CMOV_RN_CRM, "cmov-rn-crm", "cmov", 32,
2474     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
2475   },
2476 /* cmovc $ccrn,$rm */
2477   {
2478     MEP_INSN_CMOVC_CCRN_RM, "cmovc-ccrn-rm", "cmovc", 32,
2479     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
2480   },
2481 /* cmovc $rm,$ccrn */
2482   {
2483     MEP_INSN_CMOVC_RN_CCRM, "cmovc-rn-ccrm", "cmovc", 32,
2484     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
2485   },
2486 /* cmovh $crnx64,$rm */
2487   {
2488     MEP_INSN_CMOVH_CRN_RM, "cmovh-crn-rm", "cmovh", 32,
2489     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
2490   },
2491 /* cmovh $rm,$crnx64 */
2492   {
2493     MEP_INSN_CMOVH_RN_CRM, "cmovh-rn-crm", "cmovh", 32,
2494     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
2495   },
2496 /* cmov $ivc2crn,$ivc2rm */
2497   {
2498     MEP_INSN_CMOV_CRN_RM_P0, "cmov-crn-rm-p0", "cmov", 32,
2499     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x8" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0), 0 } } } }
2500   },
2501 /* cmov $ivc2rm,$ivc2crn */
2502   {
2503     MEP_INSN_CMOV_RN_CRM_P0, "cmov-rn-crm-p0", "cmov", 32,
2504     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x8" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0), 0 } } } }
2505   },
2506 /* cmovc $ivc2ccrn,$ivc2rm */
2507   {
2508     MEP_INSN_CMOVC_CCRN_RM_P0, "cmovc-ccrn-rm-p0", "cmovc", 32,
2509     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x8" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0), 0 } } } }
2510   },
2511 /* cmovc $ivc2rm,$ivc2ccrn */
2512   {
2513     MEP_INSN_CMOVC_RN_CCRM_P0, "cmovc-rn-ccrm-p0", "cmovc", 32,
2514     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x8" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0), 0 } } } }
2515   },
2516 /* cmovh $ivc2crn,$ivc2rm */
2517   {
2518     MEP_INSN_CMOVH_CRN_RM_P0, "cmovh-crn-rm-p0", "cmovh", 32,
2519     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x8" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0), 0 } } } }
2520   },
2521 /* cmovh $ivc2rm,$ivc2crn */
2522   {
2523     MEP_INSN_CMOVH_RN_CRM_P0, "cmovh-rn-crm-p0", "cmovh", 32,
2524     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x8" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0), 0 } } } }
2525   },
2526 /* cpadd3.b $croc,$crqc,$crpc */
2527   {
2528     MEP_INSN_CPADD3_B_C3, "cpadd3_b_C3", "cpadd3.b", 32,
2529     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
2530   },
2531 /* cpadd3.h $croc,$crqc,$crpc */
2532   {
2533     MEP_INSN_CPADD3_H_C3, "cpadd3_h_C3", "cpadd3.h", 32,
2534     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
2535   },
2536 /* cpadd3.w $croc,$crqc,$crpc */
2537   {
2538     MEP_INSN_CPADD3_W_C3, "cpadd3_w_C3", "cpadd3.w", 32,
2539     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
2540   },
2541 /* cdadd3 $croc,$crqc,$crpc */
2542   {
2543     MEP_INSN_CDADD3_C3, "cdadd3_C3", "cdadd3", 32,
2544     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
2545   },
2546 /* cpsub3.b $croc,$crqc,$crpc */
2547   {
2548     MEP_INSN_CPSUB3_B_C3, "cpsub3_b_C3", "cpsub3.b", 32,
2549     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
2550   },
2551 /* cpsub3.h $croc,$crqc,$crpc */
2552   {
2553     MEP_INSN_CPSUB3_H_C3, "cpsub3_h_C3", "cpsub3.h", 32,
2554     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
2555   },
2556 /* cpsub3.w $croc,$crqc,$crpc */
2557   {
2558     MEP_INSN_CPSUB3_W_C3, "cpsub3_w_C3", "cpsub3.w", 32,
2559     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
2560   },
2561 /* cdsub3 $croc,$crqc,$crpc */
2562   {
2563     MEP_INSN_CDSUB3_C3, "cdsub3_C3", "cdsub3", 32,
2564     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
2565   },
2566 /* cpand3 $croc,$crqc,$crpc */
2567   {
2568     MEP_INSN_CPAND3_C3, "cpand3_C3", "cpand3", 32,
2569     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
2570   },
2571 /* cpor3 $croc,$crqc,$crpc */
2572   {
2573     MEP_INSN_CPOR3_C3, "cpor3_C3", "cpor3", 32,
2574     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
2575   },
2576 /* cpnor3 $croc,$crqc,$crpc */
2577   {
2578     MEP_INSN_CPNOR3_C3, "cpnor3_C3", "cpnor3", 32,
2579     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
2580   },
2581 /* cpxor3 $croc,$crqc,$crpc */
2582   {
2583     MEP_INSN_CPXOR3_C3, "cpxor3_C3", "cpxor3", 32,
2584     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
2585   },
2586 /* cpsel $croc,$crqc,$crpc */
2587   {
2588     MEP_INSN_CPSEL_C3, "cpsel_C3", "cpsel", 32,
2589     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
2590   },
2591 /* cpfsftbi $croc,$crqc,$crpc,$imm3p4 */
2592   {
2593     MEP_INSN_CPFSFTBI_C3, "cpfsftbi_C3", "cpfsftbi", 32,
2594     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
2595   },
2596 /* cpfsftbs0 $croc,$crqc,$crpc */
2597   {
2598     MEP_INSN_CPFSFTBS0_C3, "cpfsftbs0_C3", "cpfsftbs0", 32,
2599     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
2600   },
2601 /* cpfsftbs1 $croc,$crqc,$crpc */
2602   {
2603     MEP_INSN_CPFSFTBS1_C3, "cpfsftbs1_C3", "cpfsftbs1", 32,
2604     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
2605   },
2606 /* cpunpacku.b $croc,$crqc,$crpc */
2607   {
2608     MEP_INSN_CPUNPACKU_B_C3, "cpunpacku_b_C3", "cpunpacku.b", 32,
2609     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
2610   },
2611 /* cpunpacku.h $croc,$crqc,$crpc */
2612   {
2613     MEP_INSN_CPUNPACKU_H_C3, "cpunpacku_h_C3", "cpunpacku.h", 32,
2614     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
2615   },
2616 /* cpunpacku.w $croc,$crqc,$crpc */
2617   {
2618     MEP_INSN_CPUNPACKU_W_C3, "cpunpacku_w_C3", "cpunpacku.w", 32,
2619     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
2620   },
2621 /* cpunpackl.b $croc,$crqc,$crpc */
2622   {
2623     MEP_INSN_CPUNPACKL_B_C3, "cpunpackl_b_C3", "cpunpackl.b", 32,
2624     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
2625   },
2626 /* cpunpackl.h $croc,$crqc,$crpc */
2627   {
2628     MEP_INSN_CPUNPACKL_H_C3, "cpunpackl_h_C3", "cpunpackl.h", 32,
2629     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
2630   },
2631 /* cpunpackl.w $croc,$crqc,$crpc */
2632   {
2633     MEP_INSN_CPUNPACKL_W_C3, "cpunpackl_w_C3", "cpunpackl.w", 32,
2634     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
2635   },
2636 /* cppacku.b $croc,$crqc,$crpc */
2637   {
2638     MEP_INSN_CPPACKU_B_C3, "cppacku_b_C3", "cppacku.b", 32,
2639     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
2640   },
2641 /* cppack.b $croc,$crqc,$crpc */
2642   {
2643     MEP_INSN_CPPACK_B_C3, "cppack_b_C3", "cppack.b", 32,
2644     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
2645   },
2646 /* cppack.h $croc,$crqc,$crpc */
2647   {
2648     MEP_INSN_CPPACK_H_C3, "cppack_h_C3", "cppack.h", 32,
2649     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
2650   },
2651 /* cpsrl3.b $croc,$crqc,$crpc */
2652   {
2653     MEP_INSN_CPSRL3_B_C3, "cpsrl3_b_C3", "cpsrl3.b", 32,
2654     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
2655   },
2656 /* cpssrl3.b $croc,$crqc,$crpc */
2657   {
2658     MEP_INSN_CPSSRL3_B_C3, "cpssrl3_b_C3", "cpssrl3.b", 32,
2659     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
2660   },
2661 /* cpsrl3.h $croc,$crqc,$crpc */
2662   {
2663     MEP_INSN_CPSRL3_H_C3, "cpsrl3_h_C3", "cpsrl3.h", 32,
2664     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
2665   },
2666 /* cpssrl3.h $croc,$crqc,$crpc */
2667   {
2668     MEP_INSN_CPSSRL3_H_C3, "cpssrl3_h_C3", "cpssrl3.h", 32,
2669     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
2670   },
2671 /* cpsrl3.w $croc,$crqc,$crpc */
2672   {
2673     MEP_INSN_CPSRL3_W_C3, "cpsrl3_w_C3", "cpsrl3.w", 32,
2674     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
2675   },
2676 /* cpssrl3.w $croc,$crqc,$crpc */
2677   {
2678     MEP_INSN_CPSSRL3_W_C3, "cpssrl3_w_C3", "cpssrl3.w", 32,
2679     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
2680   },
2681 /* cdsrl3 $croc,$crqc,$crpc */
2682   {
2683     MEP_INSN_CDSRL3_C3, "cdsrl3_C3", "cdsrl3", 32,
2684     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
2685   },
2686 /* cpsra3.b $croc,$crqc,$crpc */
2687   {
2688     MEP_INSN_CPSRA3_B_C3, "cpsra3_b_C3", "cpsra3.b", 32,
2689     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
2690   },
2691 /* cpssra3.b $croc,$crqc,$crpc */
2692   {
2693     MEP_INSN_CPSSRA3_B_C3, "cpssra3_b_C3", "cpssra3.b", 32,
2694     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
2695   },
2696 /* cpsra3.h $croc,$crqc,$crpc */
2697   {
2698     MEP_INSN_CPSRA3_H_C3, "cpsra3_h_C3", "cpsra3.h", 32,
2699     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
2700   },
2701 /* cpssra3.h $croc,$crqc,$crpc */
2702   {
2703     MEP_INSN_CPSSRA3_H_C3, "cpssra3_h_C3", "cpssra3.h", 32,
2704     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
2705   },
2706 /* cpsra3.w $croc,$crqc,$crpc */
2707   {
2708     MEP_INSN_CPSRA3_W_C3, "cpsra3_w_C3", "cpsra3.w", 32,
2709     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
2710   },
2711 /* cpssra3.w $croc,$crqc,$crpc */
2712   {
2713     MEP_INSN_CPSSRA3_W_C3, "cpssra3_w_C3", "cpssra3.w", 32,
2714     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
2715   },
2716 /* cdsra3 $croc,$crqc,$crpc */
2717   {
2718     MEP_INSN_CDSRA3_C3, "cdsra3_C3", "cdsra3", 32,
2719     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
2720   },
2721 /* cpsll3.b $croc,$crqc,$crpc */
2722   {
2723     MEP_INSN_CPSLL3_B_C3, "cpsll3_b_C3", "cpsll3.b", 32,
2724     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
2725   },
2726 /* cpssll3.b $croc,$crqc,$crpc */
2727   {
2728     MEP_INSN_CPSSLL3_B_C3, "cpssll3_b_C3", "cpssll3.b", 32,
2729     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
2730   },
2731 /* cpsll3.h $croc,$crqc,$crpc */
2732   {
2733     MEP_INSN_CPSLL3_H_C3, "cpsll3_h_C3", "cpsll3.h", 32,
2734     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
2735   },
2736 /* cpssll3.h $croc,$crqc,$crpc */
2737   {
2738     MEP_INSN_CPSSLL3_H_C3, "cpssll3_h_C3", "cpssll3.h", 32,
2739     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
2740   },
2741 /* cpsll3.w $croc,$crqc,$crpc */
2742   {
2743     MEP_INSN_CPSLL3_W_C3, "cpsll3_w_C3", "cpsll3.w", 32,
2744     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
2745   },
2746 /* cpssll3.w $croc,$crqc,$crpc */
2747   {
2748     MEP_INSN_CPSSLL3_W_C3, "cpssll3_w_C3", "cpssll3.w", 32,
2749     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
2750   },
2751 /* cdsll3 $croc,$crqc,$crpc */
2752   {
2753     MEP_INSN_CDSLL3_C3, "cdsll3_C3", "cdsll3", 32,
2754     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
2755   },
2756 /* cpsla3.h $croc,$crqc,$crpc */
2757   {
2758     MEP_INSN_CPSLA3_H_C3, "cpsla3_h_C3", "cpsla3.h", 32,
2759     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
2760   },
2761 /* cpsla3.w $croc,$crqc,$crpc */
2762   {
2763     MEP_INSN_CPSLA3_W_C3, "cpsla3_w_C3", "cpsla3.w", 32,
2764     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
2765   },
2766 /* cpsadd3.h $croc,$crqc,$crpc */
2767   {
2768     MEP_INSN_CPSADD3_H_C3, "cpsadd3_h_C3", "cpsadd3.h", 32,
2769     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
2770   },
2771 /* cpsadd3.w $croc,$crqc,$crpc */
2772   {
2773     MEP_INSN_CPSADD3_W_C3, "cpsadd3_w_C3", "cpsadd3.w", 32,
2774     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
2775   },
2776 /* cpssub3.h $croc,$crqc,$crpc */
2777   {
2778     MEP_INSN_CPSSUB3_H_C3, "cpssub3_h_C3", "cpssub3.h", 32,
2779     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
2780   },
2781 /* cpssub3.w $croc,$crqc,$crpc */
2782   {
2783     MEP_INSN_CPSSUB3_W_C3, "cpssub3_w_C3", "cpssub3.w", 32,
2784     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
2785   },
2786 /* cpextuaddu3.b $croc,$crqc,$crpc */
2787   {
2788     MEP_INSN_CPEXTUADDU3_B_C3, "cpextuaddu3_b_C3", "cpextuaddu3.b", 32,
2789     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
2790   },
2791 /* cpextuadd3.b $croc,$crqc,$crpc */
2792   {
2793     MEP_INSN_CPEXTUADD3_B_C3, "cpextuadd3_b_C3", "cpextuadd3.b", 32,
2794     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
2795   },
2796 /* cpextladdu3.b $croc,$crqc,$crpc */
2797   {
2798     MEP_INSN_CPEXTLADDU3_B_C3, "cpextladdu3_b_C3", "cpextladdu3.b", 32,
2799     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
2800   },
2801 /* cpextladd3.b $croc,$crqc,$crpc */
2802   {
2803     MEP_INSN_CPEXTLADD3_B_C3, "cpextladd3_b_C3", "cpextladd3.b", 32,
2804     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
2805   },
2806 /* cpextusubu3.b $croc,$crqc,$crpc */
2807   {
2808     MEP_INSN_CPEXTUSUBU3_B_C3, "cpextusubu3_b_C3", "cpextusubu3.b", 32,
2809     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
2810   },
2811 /* cpextusub3.b $croc,$crqc,$crpc */
2812   {
2813     MEP_INSN_CPEXTUSUB3_B_C3, "cpextusub3_b_C3", "cpextusub3.b", 32,
2814     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
2815   },
2816 /* cpextlsubu3.b $croc,$crqc,$crpc */
2817   {
2818     MEP_INSN_CPEXTLSUBU3_B_C3, "cpextlsubu3_b_C3", "cpextlsubu3.b", 32,
2819     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
2820   },
2821 /* cpextlsub3.b $croc,$crqc,$crpc */
2822   {
2823     MEP_INSN_CPEXTLSUB3_B_C3, "cpextlsub3_b_C3", "cpextlsub3.b", 32,
2824     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
2825   },
2826 /* cpaveu3.b $croc,$crqc,$crpc */
2827   {
2828     MEP_INSN_CPAVEU3_B_C3, "cpaveu3_b_C3", "cpaveu3.b", 32,
2829     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
2830   },
2831 /* cpave3.b $croc,$crqc,$crpc */
2832   {
2833     MEP_INSN_CPAVE3_B_C3, "cpave3_b_C3", "cpave3.b", 32,
2834     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
2835   },
2836 /* cpave3.h $croc,$crqc,$crpc */
2837   {
2838     MEP_INSN_CPAVE3_H_C3, "cpave3_h_C3", "cpave3.h", 32,
2839     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
2840   },
2841 /* cpave3.w $croc,$crqc,$crpc */
2842   {
2843     MEP_INSN_CPAVE3_W_C3, "cpave3_w_C3", "cpave3.w", 32,
2844     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
2845   },
2846 /* cpaddsru3.b $croc,$crqc,$crpc */
2847   {
2848     MEP_INSN_CPADDSRU3_B_C3, "cpaddsru3_b_C3", "cpaddsru3.b", 32,
2849     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
2850   },
2851 /* cpaddsr3.b $croc,$crqc,$crpc */
2852   {
2853     MEP_INSN_CPADDSR3_B_C3, "cpaddsr3_b_C3", "cpaddsr3.b", 32,
2854     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
2855   },
2856 /* cpaddsr3.h $croc,$crqc,$crpc */
2857   {
2858     MEP_INSN_CPADDSR3_H_C3, "cpaddsr3_h_C3", "cpaddsr3.h", 32,
2859     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
2860   },
2861 /* cpaddsr3.w $croc,$crqc,$crpc */
2862   {
2863     MEP_INSN_CPADDSR3_W_C3, "cpaddsr3_w_C3", "cpaddsr3.w", 32,
2864     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
2865   },
2866 /* cpabsu3.b $croc,$crqc,$crpc */
2867   {
2868     MEP_INSN_CPABSU3_B_C3, "cpabsu3_b_C3", "cpabsu3.b", 32,
2869     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
2870   },
2871 /* cpabs3.b $croc,$crqc,$crpc */
2872   {
2873     MEP_INSN_CPABS3_B_C3, "cpabs3_b_C3", "cpabs3.b", 32,
2874     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
2875   },
2876 /* cpabs3.h $croc,$crqc,$crpc */
2877   {
2878     MEP_INSN_CPABS3_H_C3, "cpabs3_h_C3", "cpabs3.h", 32,
2879     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
2880   },
2881 /* cpmaxu3.b $croc,$crqc,$crpc */
2882   {
2883     MEP_INSN_CPMAXU3_B_C3, "cpmaxu3_b_C3", "cpmaxu3.b", 32,
2884     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
2885   },
2886 /* cpmax3.b $croc,$crqc,$crpc */
2887   {
2888     MEP_INSN_CPMAX3_B_C3, "cpmax3_b_C3", "cpmax3.b", 32,
2889     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
2890   },
2891 /* cpmax3.h $croc,$crqc,$crpc */
2892   {
2893     MEP_INSN_CPMAX3_H_C3, "cpmax3_h_C3", "cpmax3.h", 32,
2894     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
2895   },
2896 /* cpmaxu3.w $croc,$crqc,$crpc */
2897   {
2898     MEP_INSN_CPMAXU3_W_C3, "cpmaxu3_w_C3", "cpmaxu3.w", 32,
2899     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
2900   },
2901 /* cpmax3.w $croc,$crqc,$crpc */
2902   {
2903     MEP_INSN_CPMAX3_W_C3, "cpmax3_w_C3", "cpmax3.w", 32,
2904     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
2905   },
2906 /* cpminu3.b $croc,$crqc,$crpc */
2907   {
2908     MEP_INSN_CPMINU3_B_C3, "cpminu3_b_C3", "cpminu3.b", 32,
2909     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
2910   },
2911 /* cpmin3.b $croc,$crqc,$crpc */
2912   {
2913     MEP_INSN_CPMIN3_B_C3, "cpmin3_b_C3", "cpmin3.b", 32,
2914     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
2915   },
2916 /* cpmin3.h $croc,$crqc,$crpc */
2917   {
2918     MEP_INSN_CPMIN3_H_C3, "cpmin3_h_C3", "cpmin3.h", 32,
2919     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
2920   },
2921 /* cpminu3.w $croc,$crqc,$crpc */
2922   {
2923     MEP_INSN_CPMINU3_W_C3, "cpminu3_w_C3", "cpminu3.w", 32,
2924     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
2925   },
2926 /* cpmin3.w $croc,$crqc,$crpc */
2927   {
2928     MEP_INSN_CPMIN3_W_C3, "cpmin3_w_C3", "cpmin3.w", 32,
2929     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
2930   },
2931 /* cpmovfrcsar0 $croc */
2932   {
2933     MEP_INSN_CPMOVFRCSAR0_C3, "cpmovfrcsar0_C3", "cpmovfrcsar0", 32,
2934     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
2935   },
2936 /* cpmovfrcsar1 $croc */
2937   {
2938     MEP_INSN_CPMOVFRCSAR1_C3, "cpmovfrcsar1_C3", "cpmovfrcsar1", 32,
2939     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
2940   },
2941 /* cpmovfrcc $croc */
2942   {
2943     MEP_INSN_CPMOVFRCC_C3, "cpmovfrcc_C3", "cpmovfrcc", 32,
2944     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
2945   },
2946 /* cpmovtocsar0 $crqc */
2947   {
2948     MEP_INSN_CPMOVTOCSAR0_C3, "cpmovtocsar0_C3", "cpmovtocsar0", 32,
2949     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
2950   },
2951 /* cpmovtocsar1 $crqc */
2952   {
2953     MEP_INSN_CPMOVTOCSAR1_C3, "cpmovtocsar1_C3", "cpmovtocsar1", 32,
2954     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
2955   },
2956 /* cpmovtocc $crqc */
2957   {
2958     MEP_INSN_CPMOVTOCC_C3, "cpmovtocc_C3", "cpmovtocc", 32,
2959     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
2960   },
2961 /* cpmov $croc,$crqc */
2962   {
2963     MEP_INSN_CPMOV_C3, "cpmov_C3", "cpmov", 32,
2964     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
2965   },
2966 /* cpabsz.b $croc,$crqc */
2967   {
2968     MEP_INSN_CPABSZ_B_C3, "cpabsz_b_C3", "cpabsz.b", 32,
2969     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
2970   },
2971 /* cpabsz.h $croc,$crqc */
2972   {
2973     MEP_INSN_CPABSZ_H_C3, "cpabsz_h_C3", "cpabsz.h", 32,
2974     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
2975   },
2976 /* cpabsz.w $croc,$crqc */
2977   {
2978     MEP_INSN_CPABSZ_W_C3, "cpabsz_w_C3", "cpabsz.w", 32,
2979     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
2980   },
2981 /* cpldz.h $croc,$crqc */
2982   {
2983     MEP_INSN_CPLDZ_H_C3, "cpldz_h_C3", "cpldz.h", 32,
2984     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
2985   },
2986 /* cpldz.w $croc,$crqc */
2987   {
2988     MEP_INSN_CPLDZ_W_C3, "cpldz_w_C3", "cpldz.w", 32,
2989     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
2990   },
2991 /* cpnorm.h $croc,$crqc */
2992   {
2993     MEP_INSN_CPNORM_H_C3, "cpnorm_h_C3", "cpnorm.h", 32,
2994     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
2995   },
2996 /* cpnorm.w $croc,$crqc */
2997   {
2998     MEP_INSN_CPNORM_W_C3, "cpnorm_w_C3", "cpnorm.w", 32,
2999     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3000   },
3001 /* cphaddu.b $croc,$crqc */
3002   {
3003     MEP_INSN_CPHADDU_B_C3, "cphaddu_b_C3", "cphaddu.b", 32,
3004     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3005   },
3006 /* cphadd.b $croc,$crqc */
3007   {
3008     MEP_INSN_CPHADD_B_C3, "cphadd_b_C3", "cphadd.b", 32,
3009     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3010   },
3011 /* cphadd.h $croc,$crqc */
3012   {
3013     MEP_INSN_CPHADD_H_C3, "cphadd_h_C3", "cphadd.h", 32,
3014     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3015   },
3016 /* cphadd.w $croc,$crqc */
3017   {
3018     MEP_INSN_CPHADD_W_C3, "cphadd_w_C3", "cphadd.w", 32,
3019     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3020   },
3021 /* cpccadd.b $crqc */
3022   {
3023     MEP_INSN_CPCCADD_B_C3, "cpccadd_b_C3", "cpccadd.b", 32,
3024     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3025   },
3026 /* cpbcast.b $croc,$crqc */
3027   {
3028     MEP_INSN_CPBCAST_B_C3, "cpbcast_b_C3", "cpbcast.b", 32,
3029     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3030   },
3031 /* cpbcast.h $croc,$crqc */
3032   {
3033     MEP_INSN_CPBCAST_H_C3, "cpbcast_h_C3", "cpbcast.h", 32,
3034     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3035   },
3036 /* cpbcast.w $croc,$crqc */
3037   {
3038     MEP_INSN_CPBCAST_W_C3, "cpbcast_w_C3", "cpbcast.w", 32,
3039     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3040   },
3041 /* cpextuu.b $croc,$crqc */
3042   {
3043     MEP_INSN_CPEXTUU_B_C3, "cpextuu_b_C3", "cpextuu.b", 32,
3044     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3045   },
3046 /* cpextu.b $croc,$crqc */
3047   {
3048     MEP_INSN_CPEXTU_B_C3, "cpextu_b_C3", "cpextu.b", 32,
3049     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3050   },
3051 /* cpextuu.h $croc,$crqc */
3052   {
3053     MEP_INSN_CPEXTUU_H_C3, "cpextuu_h_C3", "cpextuu.h", 32,
3054     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3055   },
3056 /* cpextu.h $croc,$crqc */
3057   {
3058     MEP_INSN_CPEXTU_H_C3, "cpextu_h_C3", "cpextu.h", 32,
3059     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3060   },
3061 /* cpextlu.b $croc,$crqc */
3062   {
3063     MEP_INSN_CPEXTLU_B_C3, "cpextlu_b_C3", "cpextlu.b", 32,
3064     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3065   },
3066 /* cpextl.b $croc,$crqc */
3067   {
3068     MEP_INSN_CPEXTL_B_C3, "cpextl_b_C3", "cpextl.b", 32,
3069     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3070   },
3071 /* cpextlu.h $croc,$crqc */
3072   {
3073     MEP_INSN_CPEXTLU_H_C3, "cpextlu_h_C3", "cpextlu.h", 32,
3074     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3075   },
3076 /* cpextl.h $croc,$crqc */
3077   {
3078     MEP_INSN_CPEXTL_H_C3, "cpextl_h_C3", "cpextl.h", 32,
3079     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3080   },
3081 /* cpcastub.h $croc,$crqc */
3082   {
3083     MEP_INSN_CPCASTUB_H_C3, "cpcastub_h_C3", "cpcastub.h", 32,
3084     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3085   },
3086 /* cpcastb.h $croc,$crqc */
3087   {
3088     MEP_INSN_CPCASTB_H_C3, "cpcastb_h_C3", "cpcastb.h", 32,
3089     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3090   },
3091 /* cpcastub.w $croc,$crqc */
3092   {
3093     MEP_INSN_CPCASTUB_W_C3, "cpcastub_w_C3", "cpcastub.w", 32,
3094     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3095   },
3096 /* cpcastb.w $croc,$crqc */
3097   {
3098     MEP_INSN_CPCASTB_W_C3, "cpcastb_w_C3", "cpcastb.w", 32,
3099     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3100   },
3101 /* cpcastuh.w $croc,$crqc */
3102   {
3103     MEP_INSN_CPCASTUH_W_C3, "cpcastuh_w_C3", "cpcastuh.w", 32,
3104     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3105   },
3106 /* cpcasth.w $croc,$crqc */
3107   {
3108     MEP_INSN_CPCASTH_W_C3, "cpcasth_w_C3", "cpcasth.w", 32,
3109     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3110   },
3111 /* cdcastuw $croc,$crqc */
3112   {
3113     MEP_INSN_CDCASTUW_C3, "cdcastuw_C3", "cdcastuw", 32,
3114     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3115   },
3116 /* cdcastw $croc,$crqc */
3117   {
3118     MEP_INSN_CDCASTW_C3, "cdcastw_C3", "cdcastw", 32,
3119     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3120   },
3121 /* cpcmpeqz.b $crqc,$crpc */
3122   {
3123     MEP_INSN_CPCMPEQZ_B_C3, "cpcmpeqz_b_C3", "cpcmpeqz.b", 32,
3124     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3125   },
3126 /* cpcmpeq.b $crqc,$crpc */
3127   {
3128     MEP_INSN_CPCMPEQ_B_C3, "cpcmpeq_b_C3", "cpcmpeq.b", 32,
3129     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3130   },
3131 /* cpcmpeq.h $crqc,$crpc */
3132   {
3133     MEP_INSN_CPCMPEQ_H_C3, "cpcmpeq_h_C3", "cpcmpeq.h", 32,
3134     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3135   },
3136 /* cpcmpeq.w $crqc,$crpc */
3137   {
3138     MEP_INSN_CPCMPEQ_W_C3, "cpcmpeq_w_C3", "cpcmpeq.w", 32,
3139     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3140   },
3141 /* cpcmpne.b $crqc,$crpc */
3142   {
3143     MEP_INSN_CPCMPNE_B_C3, "cpcmpne_b_C3", "cpcmpne.b", 32,
3144     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3145   },
3146 /* cpcmpne.h $crqc,$crpc */
3147   {
3148     MEP_INSN_CPCMPNE_H_C3, "cpcmpne_h_C3", "cpcmpne.h", 32,
3149     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3150   },
3151 /* cpcmpne.w $crqc,$crpc */
3152   {
3153     MEP_INSN_CPCMPNE_W_C3, "cpcmpne_w_C3", "cpcmpne.w", 32,
3154     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3155   },
3156 /* cpcmpgtu.b $crqc,$crpc */
3157   {
3158     MEP_INSN_CPCMPGTU_B_C3, "cpcmpgtu_b_C3", "cpcmpgtu.b", 32,
3159     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3160   },
3161 /* cpcmpgt.b $crqc,$crpc */
3162   {
3163     MEP_INSN_CPCMPGT_B_C3, "cpcmpgt_b_C3", "cpcmpgt.b", 32,
3164     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3165   },
3166 /* cpcmpgt.h $crqc,$crpc */
3167   {
3168     MEP_INSN_CPCMPGT_H_C3, "cpcmpgt_h_C3", "cpcmpgt.h", 32,
3169     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3170   },
3171 /* cpcmpgtu.w $crqc,$crpc */
3172   {
3173     MEP_INSN_CPCMPGTU_W_C3, "cpcmpgtu_w_C3", "cpcmpgtu.w", 32,
3174     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3175   },
3176 /* cpcmpgt.w $crqc,$crpc */
3177   {
3178     MEP_INSN_CPCMPGT_W_C3, "cpcmpgt_w_C3", "cpcmpgt.w", 32,
3179     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3180   },
3181 /* cpcmpgeu.b $crqc,$crpc */
3182   {
3183     MEP_INSN_CPCMPGEU_B_C3, "cpcmpgeu_b_C3", "cpcmpgeu.b", 32,
3184     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3185   },
3186 /* cpcmpge.b $crqc,$crpc */
3187   {
3188     MEP_INSN_CPCMPGE_B_C3, "cpcmpge_b_C3", "cpcmpge.b", 32,
3189     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3190   },
3191 /* cpcmpge.h $crqc,$crpc */
3192   {
3193     MEP_INSN_CPCMPGE_H_C3, "cpcmpge_h_C3", "cpcmpge.h", 32,
3194     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3195   },
3196 /* cpcmpgeu.w $crqc,$crpc */
3197   {
3198     MEP_INSN_CPCMPGEU_W_C3, "cpcmpgeu_w_C3", "cpcmpgeu.w", 32,
3199     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3200   },
3201 /* cpcmpge.w $crqc,$crpc */
3202   {
3203     MEP_INSN_CPCMPGE_W_C3, "cpcmpge_w_C3", "cpcmpge.w", 32,
3204     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3205   },
3206 /* cpacmpeq.b $crqc,$crpc */
3207   {
3208     MEP_INSN_CPACMPEQ_B_C3, "cpacmpeq_b_C3", "cpacmpeq.b", 32,
3209     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3210   },
3211 /* cpacmpeq.h $crqc,$crpc */
3212   {
3213     MEP_INSN_CPACMPEQ_H_C3, "cpacmpeq_h_C3", "cpacmpeq.h", 32,
3214     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3215   },
3216 /* cpacmpeq.w $crqc,$crpc */
3217   {
3218     MEP_INSN_CPACMPEQ_W_C3, "cpacmpeq_w_C3", "cpacmpeq.w", 32,
3219     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3220   },
3221 /* cpacmpne.b $crqc,$crpc */
3222   {
3223     MEP_INSN_CPACMPNE_B_C3, "cpacmpne_b_C3", "cpacmpne.b", 32,
3224     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3225   },
3226 /* cpacmpne.h $crqc,$crpc */
3227   {
3228     MEP_INSN_CPACMPNE_H_C3, "cpacmpne_h_C3", "cpacmpne.h", 32,
3229     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3230   },
3231 /* cpacmpne.w $crqc,$crpc */
3232   {
3233     MEP_INSN_CPACMPNE_W_C3, "cpacmpne_w_C3", "cpacmpne.w", 32,
3234     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3235   },
3236 /* cpacmpgtu.b $crqc,$crpc */
3237   {
3238     MEP_INSN_CPACMPGTU_B_C3, "cpacmpgtu_b_C3", "cpacmpgtu.b", 32,
3239     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3240   },
3241 /* cpacmpgt.b $crqc,$crpc */
3242   {
3243     MEP_INSN_CPACMPGT_B_C3, "cpacmpgt_b_C3", "cpacmpgt.b", 32,
3244     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3245   },
3246 /* cpacmpgt.h $crqc,$crpc */
3247   {
3248     MEP_INSN_CPACMPGT_H_C3, "cpacmpgt_h_C3", "cpacmpgt.h", 32,
3249     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3250   },
3251 /* cpacmpgtu.w $crqc,$crpc */
3252   {
3253     MEP_INSN_CPACMPGTU_W_C3, "cpacmpgtu_w_C3", "cpacmpgtu.w", 32,
3254     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3255   },
3256 /* cpacmpgt.w $crqc,$crpc */
3257   {
3258     MEP_INSN_CPACMPGT_W_C3, "cpacmpgt_w_C3", "cpacmpgt.w", 32,
3259     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3260   },
3261 /* cpacmpgeu.b $crqc,$crpc */
3262   {
3263     MEP_INSN_CPACMPGEU_B_C3, "cpacmpgeu_b_C3", "cpacmpgeu.b", 32,
3264     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3265   },
3266 /* cpacmpge.b $crqc,$crpc */
3267   {
3268     MEP_INSN_CPACMPGE_B_C3, "cpacmpge_b_C3", "cpacmpge.b", 32,
3269     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3270   },
3271 /* cpacmpge.h $crqc,$crpc */
3272   {
3273     MEP_INSN_CPACMPGE_H_C3, "cpacmpge_h_C3", "cpacmpge.h", 32,
3274     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3275   },
3276 /* cpacmpgeu.w $crqc,$crpc */
3277   {
3278     MEP_INSN_CPACMPGEU_W_C3, "cpacmpgeu_w_C3", "cpacmpgeu.w", 32,
3279     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3280   },
3281 /* cpacmpge.w $crqc,$crpc */
3282   {
3283     MEP_INSN_CPACMPGE_W_C3, "cpacmpge_w_C3", "cpacmpge.w", 32,
3284     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3285   },
3286 /* cpocmpeq.b $crqc,$crpc */
3287   {
3288     MEP_INSN_CPOCMPEQ_B_C3, "cpocmpeq_b_C3", "cpocmpeq.b", 32,
3289     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3290   },
3291 /* cpocmpeq.h $crqc,$crpc */
3292   {
3293     MEP_INSN_CPOCMPEQ_H_C3, "cpocmpeq_h_C3", "cpocmpeq.h", 32,
3294     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3295   },
3296 /* cpocmpeq.w $crqc,$crpc */
3297   {
3298     MEP_INSN_CPOCMPEQ_W_C3, "cpocmpeq_w_C3", "cpocmpeq.w", 32,
3299     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3300   },
3301 /* cpocmpne.b $crqc,$crpc */
3302   {
3303     MEP_INSN_CPOCMPNE_B_C3, "cpocmpne_b_C3", "cpocmpne.b", 32,
3304     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3305   },
3306 /* cpocmpne.h $crqc,$crpc */
3307   {
3308     MEP_INSN_CPOCMPNE_H_C3, "cpocmpne_h_C3", "cpocmpne.h", 32,
3309     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3310   },
3311 /* cpocmpne.w $crqc,$crpc */
3312   {
3313     MEP_INSN_CPOCMPNE_W_C3, "cpocmpne_w_C3", "cpocmpne.w", 32,
3314     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3315   },
3316 /* cpocmpgtu.b $crqc,$crpc */
3317   {
3318     MEP_INSN_CPOCMPGTU_B_C3, "cpocmpgtu_b_C3", "cpocmpgtu.b", 32,
3319     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3320   },
3321 /* cpocmpgt.b $crqc,$crpc */
3322   {
3323     MEP_INSN_CPOCMPGT_B_C3, "cpocmpgt_b_C3", "cpocmpgt.b", 32,
3324     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3325   },
3326 /* cpocmpgt.h $crqc,$crpc */
3327   {
3328     MEP_INSN_CPOCMPGT_H_C3, "cpocmpgt_h_C3", "cpocmpgt.h", 32,
3329     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3330   },
3331 /* cpocmpgtu.w $crqc,$crpc */
3332   {
3333     MEP_INSN_CPOCMPGTU_W_C3, "cpocmpgtu_w_C3", "cpocmpgtu.w", 32,
3334     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3335   },
3336 /* cpocmpgt.w $crqc,$crpc */
3337   {
3338     MEP_INSN_CPOCMPGT_W_C3, "cpocmpgt_w_C3", "cpocmpgt.w", 32,
3339     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3340   },
3341 /* cpocmpgeu.b $crqc,$crpc */
3342   {
3343     MEP_INSN_CPOCMPGEU_B_C3, "cpocmpgeu_b_C3", "cpocmpgeu.b", 32,
3344     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3345   },
3346 /* cpocmpge.b $crqc,$crpc */
3347   {
3348     MEP_INSN_CPOCMPGE_B_C3, "cpocmpge_b_C3", "cpocmpge.b", 32,
3349     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3350   },
3351 /* cpocmpge.h $crqc,$crpc */
3352   {
3353     MEP_INSN_CPOCMPGE_H_C3, "cpocmpge_h_C3", "cpocmpge.h", 32,
3354     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3355   },
3356 /* cpocmpgeu.w $crqc,$crpc */
3357   {
3358     MEP_INSN_CPOCMPGEU_W_C3, "cpocmpgeu_w_C3", "cpocmpgeu.w", 32,
3359     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3360   },
3361 /* cpocmpge.w $crqc,$crpc */
3362   {
3363     MEP_INSN_CPOCMPGE_W_C3, "cpocmpge_w_C3", "cpocmpge.w", 32,
3364     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3365   },
3366 /* cpsrli3.b $crqc,$crpc,$imm3p9 */
3367   {
3368     MEP_INSN_CPSRLI3_B_C3, "cpsrli3_b_C3", "cpsrli3.b", 32,
3369     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3370   },
3371 /* cpsrli3.h $crqc,$crpc,$imm4p8 */
3372   {
3373     MEP_INSN_CPSRLI3_H_C3, "cpsrli3_h_C3", "cpsrli3.h", 32,
3374     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3375   },
3376 /* cpsrli3.w $crqc,$crpc,$imm5p7 */
3377   {
3378     MEP_INSN_CPSRLI3_W_C3, "cpsrli3_w_C3", "cpsrli3.w", 32,
3379     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3380   },
3381 /* cdsrli3 $crqc,$crpc,$imm6p6 */
3382   {
3383     MEP_INSN_CDSRLI3_C3, "cdsrli3_C3", "cdsrli3", 32,
3384     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3385   },
3386 /* cpsrai3.b $crqc,$crpc,$imm3p9 */
3387   {
3388     MEP_INSN_CPSRAI3_B_C3, "cpsrai3_b_C3", "cpsrai3.b", 32,
3389     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3390   },
3391 /* cpsrai3.h $crqc,$crpc,$imm4p8 */
3392   {
3393     MEP_INSN_CPSRAI3_H_C3, "cpsrai3_h_C3", "cpsrai3.h", 32,
3394     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3395   },
3396 /* cpsrai3.w $crqc,$crpc,$imm5p7 */
3397   {
3398     MEP_INSN_CPSRAI3_W_C3, "cpsrai3_w_C3", "cpsrai3.w", 32,
3399     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3400   },
3401 /* cdsrai3 $crqc,$crpc,$imm6p6 */
3402   {
3403     MEP_INSN_CDSRAI3_C3, "cdsrai3_C3", "cdsrai3", 32,
3404     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3405   },
3406 /* cpslli3.b $crqc,$crpc,$imm3p9 */
3407   {
3408     MEP_INSN_CPSLLI3_B_C3, "cpslli3_b_C3", "cpslli3.b", 32,
3409     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3410   },
3411 /* cpslli3.h $crqc,$crpc,$imm4p8 */
3412   {
3413     MEP_INSN_CPSLLI3_H_C3, "cpslli3_h_C3", "cpslli3.h", 32,
3414     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3415   },
3416 /* cpslli3.w $crqc,$crpc,$imm5p7 */
3417   {
3418     MEP_INSN_CPSLLI3_W_C3, "cpslli3_w_C3", "cpslli3.w", 32,
3419     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3420   },
3421 /* cdslli3 $crqc,$crpc,$imm6p6 */
3422   {
3423     MEP_INSN_CDSLLI3_C3, "cdslli3_C3", "cdslli3", 32,
3424     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3425   },
3426 /* cpslai3.h $crqc,$crpc,$imm4p8 */
3427   {
3428     MEP_INSN_CPSLAI3_H_C3, "cpslai3_h_C3", "cpslai3.h", 32,
3429     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3430   },
3431 /* cpslai3.w $crqc,$crpc,$imm5p7 */
3432   {
3433     MEP_INSN_CPSLAI3_W_C3, "cpslai3_w_C3", "cpslai3.w", 32,
3434     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3435   },
3436 /* cpclipiu3.w $crqc,$crpc,$imm5p7 */
3437   {
3438     MEP_INSN_CPCLIPIU3_W_C3, "cpclipiu3_w_C3", "cpclipiu3.w", 32,
3439     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3440   },
3441 /* cpclipi3.w $crqc,$crpc,$imm5p7 */
3442   {
3443     MEP_INSN_CPCLIPI3_W_C3, "cpclipi3_w_C3", "cpclipi3.w", 32,
3444     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3445   },
3446 /* cdclipiu3 $crqc,$crpc,$imm6p6 */
3447   {
3448     MEP_INSN_CDCLIPIU3_C3, "cdclipiu3_C3", "cdclipiu3", 32,
3449     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3450   },
3451 /* cdclipi3 $crqc,$crpc,$imm6p6 */
3452   {
3453     MEP_INSN_CDCLIPI3_C3, "cdclipi3_C3", "cdclipi3", 32,
3454     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3455   },
3456 /* cpmovi.b $crqc,$simm8p4 */
3457   {
3458     MEP_INSN_CPMOVI_B_C3, "cpmovi_b_C3", "cpmovi.b", 32,
3459     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3460   },
3461 /* cpmoviu.h $crqc,$imm8p4 */
3462   {
3463     MEP_INSN_CPMOVIU_H_C3, "cpmoviu_h_C3", "cpmoviu.h", 32,
3464     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3465   },
3466 /* cpmovi.h $crqc,$simm8p4 */
3467   {
3468     MEP_INSN_CPMOVI_H_C3, "cpmovi_h_C3", "cpmovi.h", 32,
3469     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3470   },
3471 /* cpmoviu.w $crqc,$imm8p4 */
3472   {
3473     MEP_INSN_CPMOVIU_W_C3, "cpmoviu_w_C3", "cpmoviu.w", 32,
3474     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3475   },
3476 /* cpmovi.w $crqc,$simm8p4 */
3477   {
3478     MEP_INSN_CPMOVI_W_C3, "cpmovi_w_C3", "cpmovi.w", 32,
3479     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3480   },
3481 /* cdmoviu $crqc,$imm8p4 */
3482   {
3483     MEP_INSN_CDMOVIU_C3, "cdmoviu_C3", "cdmoviu", 32,
3484     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3485   },
3486 /* cdmovi $crqc,$simm8p4 */
3487   {
3488     MEP_INSN_CDMOVI_C3, "cdmovi_C3", "cdmovi", 32,
3489     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3490   },
3491 /* cpadda1u.b $crqc,$crpc */
3492   {
3493     MEP_INSN_CPADDA1U_B_C3, "cpadda1u_b_C3", "cpadda1u.b", 32,
3494     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3495   },
3496 /* cpadda1.b $crqc,$crpc */
3497   {
3498     MEP_INSN_CPADDA1_B_C3, "cpadda1_b_C3", "cpadda1.b", 32,
3499     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3500   },
3501 /* cpaddua1.h $crqc,$crpc */
3502   {
3503     MEP_INSN_CPADDUA1_H_C3, "cpaddua1_h_C3", "cpaddua1.h", 32,
3504     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3505   },
3506 /* cpaddla1.h $crqc,$crpc */
3507   {
3508     MEP_INSN_CPADDLA1_H_C3, "cpaddla1_h_C3", "cpaddla1.h", 32,
3509     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3510   },
3511 /* cpaddaca1u.b $crqc,$crpc */
3512   {
3513     MEP_INSN_CPADDACA1U_B_C3, "cpaddaca1u_b_C3", "cpaddaca1u.b", 32,
3514     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3515   },
3516 /* cpaddaca1.b $crqc,$crpc */
3517   {
3518     MEP_INSN_CPADDACA1_B_C3, "cpaddaca1_b_C3", "cpaddaca1.b", 32,
3519     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3520   },
3521 /* cpaddacua1.h $crqc,$crpc */
3522   {
3523     MEP_INSN_CPADDACUA1_H_C3, "cpaddacua1_h_C3", "cpaddacua1.h", 32,
3524     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3525   },
3526 /* cpaddacla1.h $crqc,$crpc */
3527   {
3528     MEP_INSN_CPADDACLA1_H_C3, "cpaddacla1_h_C3", "cpaddacla1.h", 32,
3529     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3530   },
3531 /* cpsuba1u.b $crqc,$crpc */
3532   {
3533     MEP_INSN_CPSUBA1U_B_C3, "cpsuba1u_b_C3", "cpsuba1u.b", 32,
3534     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3535   },
3536 /* cpsuba1.b $crqc,$crpc */
3537   {
3538     MEP_INSN_CPSUBA1_B_C3, "cpsuba1_b_C3", "cpsuba1.b", 32,
3539     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3540   },
3541 /* cpsubua1.h $crqc,$crpc */
3542   {
3543     MEP_INSN_CPSUBUA1_H_C3, "cpsubua1_h_C3", "cpsubua1.h", 32,
3544     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3545   },
3546 /* cpsubla1.h $crqc,$crpc */
3547   {
3548     MEP_INSN_CPSUBLA1_H_C3, "cpsubla1_h_C3", "cpsubla1.h", 32,
3549     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3550   },
3551 /* cpsubaca1u.b $crqc,$crpc */
3552   {
3553     MEP_INSN_CPSUBACA1U_B_C3, "cpsubaca1u_b_C3", "cpsubaca1u.b", 32,
3554     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3555   },
3556 /* cpsubaca1.b $crqc,$crpc */
3557   {
3558     MEP_INSN_CPSUBACA1_B_C3, "cpsubaca1_b_C3", "cpsubaca1.b", 32,
3559     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3560   },
3561 /* cpsubacua1.h $crqc,$crpc */
3562   {
3563     MEP_INSN_CPSUBACUA1_H_C3, "cpsubacua1_h_C3", "cpsubacua1.h", 32,
3564     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3565   },
3566 /* cpsubacla1.h $crqc,$crpc */
3567   {
3568     MEP_INSN_CPSUBACLA1_H_C3, "cpsubacla1_h_C3", "cpsubacla1.h", 32,
3569     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3570   },
3571 /* cpabsa1u.b $crqc,$crpc */
3572   {
3573     MEP_INSN_CPABSA1U_B_C3, "cpabsa1u_b_C3", "cpabsa1u.b", 32,
3574     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3575   },
3576 /* cpabsa1.b $crqc,$crpc */
3577   {
3578     MEP_INSN_CPABSA1_B_C3, "cpabsa1_b_C3", "cpabsa1.b", 32,
3579     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3580   },
3581 /* cpabsua1.h $crqc,$crpc */
3582   {
3583     MEP_INSN_CPABSUA1_H_C3, "cpabsua1_h_C3", "cpabsua1.h", 32,
3584     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3585   },
3586 /* cpabsla1.h $crqc,$crpc */
3587   {
3588     MEP_INSN_CPABSLA1_H_C3, "cpabsla1_h_C3", "cpabsla1.h", 32,
3589     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3590   },
3591 /* cpsada1u.b $crqc,$crpc */
3592   {
3593     MEP_INSN_CPSADA1U_B_C3, "cpsada1u_b_C3", "cpsada1u.b", 32,
3594     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3595   },
3596 /* cpsada1.b $crqc,$crpc */
3597   {
3598     MEP_INSN_CPSADA1_B_C3, "cpsada1_b_C3", "cpsada1.b", 32,
3599     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3600   },
3601 /* cpsadua1.h $crqc,$crpc */
3602   {
3603     MEP_INSN_CPSADUA1_H_C3, "cpsadua1_h_C3", "cpsadua1.h", 32,
3604     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3605   },
3606 /* cpsadla1.h $crqc,$crpc */
3607   {
3608     MEP_INSN_CPSADLA1_H_C3, "cpsadla1_h_C3", "cpsadla1.h", 32,
3609     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3610   },
3611 /* cpseta1.h $crqc,$crpc */
3612   {
3613     MEP_INSN_CPSETA1_H_C3, "cpseta1_h_C3", "cpseta1.h", 32,
3614     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3615   },
3616 /* cpsetua1.w $crqc,$crpc */
3617   {
3618     MEP_INSN_CPSETUA1_W_C3, "cpsetua1_w_C3", "cpsetua1.w", 32,
3619     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3620   },
3621 /* cpsetla1.w $crqc,$crpc */
3622   {
3623     MEP_INSN_CPSETLA1_W_C3, "cpsetla1_w_C3", "cpsetla1.w", 32,
3624     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3625   },
3626 /* cpmova1.b $croc */
3627   {
3628     MEP_INSN_CPMOVA1_B_C3, "cpmova1_b_C3", "cpmova1.b", 32,
3629     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3630   },
3631 /* cpmovua1.h $croc */
3632   {
3633     MEP_INSN_CPMOVUA1_H_C3, "cpmovua1_h_C3", "cpmovua1.h", 32,
3634     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3635   },
3636 /* cpmovla1.h $croc */
3637   {
3638     MEP_INSN_CPMOVLA1_H_C3, "cpmovla1_h_C3", "cpmovla1.h", 32,
3639     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3640   },
3641 /* cpmovuua1.w $croc */
3642   {
3643     MEP_INSN_CPMOVUUA1_W_C3, "cpmovuua1_w_C3", "cpmovuua1.w", 32,
3644     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3645   },
3646 /* cpmovula1.w $croc */
3647   {
3648     MEP_INSN_CPMOVULA1_W_C3, "cpmovula1_w_C3", "cpmovula1.w", 32,
3649     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3650   },
3651 /* cpmovlua1.w $croc */
3652   {
3653     MEP_INSN_CPMOVLUA1_W_C3, "cpmovlua1_w_C3", "cpmovlua1.w", 32,
3654     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3655   },
3656 /* cpmovlla1.w $croc */
3657   {
3658     MEP_INSN_CPMOVLLA1_W_C3, "cpmovlla1_w_C3", "cpmovlla1.w", 32,
3659     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3660   },
3661 /* cppacka1u.b $croc */
3662   {
3663     MEP_INSN_CPPACKA1U_B_C3, "cppacka1u_b_C3", "cppacka1u.b", 32,
3664     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3665   },
3666 /* cppacka1.b $croc */
3667   {
3668     MEP_INSN_CPPACKA1_B_C3, "cppacka1_b_C3", "cppacka1.b", 32,
3669     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3670   },
3671 /* cppackua1.h $croc */
3672   {
3673     MEP_INSN_CPPACKUA1_H_C3, "cppackua1_h_C3", "cppackua1.h", 32,
3674     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3675   },
3676 /* cppackla1.h $croc */
3677   {
3678     MEP_INSN_CPPACKLA1_H_C3, "cppackla1_h_C3", "cppackla1.h", 32,
3679     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3680   },
3681 /* cppackua1.w $croc */
3682   {
3683     MEP_INSN_CPPACKUA1_W_C3, "cppackua1_w_C3", "cppackua1.w", 32,
3684     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3685   },
3686 /* cppackla1.w $croc */
3687   {
3688     MEP_INSN_CPPACKLA1_W_C3, "cppackla1_w_C3", "cppackla1.w", 32,
3689     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3690   },
3691 /* cpmovhua1.w $croc */
3692   {
3693     MEP_INSN_CPMOVHUA1_W_C3, "cpmovhua1_w_C3", "cpmovhua1.w", 32,
3694     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3695   },
3696 /* cpmovhla1.w $croc */
3697   {
3698     MEP_INSN_CPMOVHLA1_W_C3, "cpmovhla1_w_C3", "cpmovhla1.w", 32,
3699     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3700   },
3701 /* cpsrla1 $crqc */
3702   {
3703     MEP_INSN_CPSRLA1_C3, "cpsrla1_C3", "cpsrla1", 32,
3704     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3705   },
3706 /* cpsraa1 $crqc */
3707   {
3708     MEP_INSN_CPSRAA1_C3, "cpsraa1_C3", "cpsraa1", 32,
3709     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3710   },
3711 /* cpslla1 $crqc */
3712   {
3713     MEP_INSN_CPSLLA1_C3, "cpslla1_C3", "cpslla1", 32,
3714     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3715   },
3716 /* cpsrlia1 $imm5p7 */
3717   {
3718     MEP_INSN_CPSRLIA1_P1, "cpsrlia1_P1", "cpsrlia1", 32,
3719     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3720   },
3721 /* cpsraia1 $imm5p7 */
3722   {
3723     MEP_INSN_CPSRAIA1_P1, "cpsraia1_P1", "cpsraia1", 32,
3724     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3725   },
3726 /* cpsllia1 $imm5p7 */
3727   {
3728     MEP_INSN_CPSLLIA1_P1, "cpsllia1_P1", "cpsllia1", 32,
3729     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3730   },
3731 /* cpssqa1u.b $crqc,$crpc */
3732   {
3733     MEP_INSN_CPSSQA1U_B_C3, "cpssqa1u_b_C3", "cpssqa1u.b", 32,
3734     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3735   },
3736 /* cpssqa1.b $crqc,$crpc */
3737   {
3738     MEP_INSN_CPSSQA1_B_C3, "cpssqa1_b_C3", "cpssqa1.b", 32,
3739     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3740   },
3741 /* cpssda1u.b $crqc,$crpc */
3742   {
3743     MEP_INSN_CPSSDA1U_B_C3, "cpssda1u_b_C3", "cpssda1u.b", 32,
3744     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3745   },
3746 /* cpssda1.b $crqc,$crpc */
3747   {
3748     MEP_INSN_CPSSDA1_B_C3, "cpssda1_b_C3", "cpssda1.b", 32,
3749     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3750   },
3751 /* cpmula1u.b $crqc,$crpc */
3752   {
3753     MEP_INSN_CPMULA1U_B_C3, "cpmula1u_b_C3", "cpmula1u.b", 32,
3754     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3755   },
3756 /* cpmula1.b $crqc,$crpc */
3757   {
3758     MEP_INSN_CPMULA1_B_C3, "cpmula1_b_C3", "cpmula1.b", 32,
3759     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3760   },
3761 /* cpmulua1.h $crqc,$crpc */
3762   {
3763     MEP_INSN_CPMULUA1_H_C3, "cpmulua1_h_C3", "cpmulua1.h", 32,
3764     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3765   },
3766 /* cpmulla1.h $crqc,$crpc */
3767   {
3768     MEP_INSN_CPMULLA1_H_C3, "cpmulla1_h_C3", "cpmulla1.h", 32,
3769     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3770   },
3771 /* cpmulua1u.w $crqc,$crpc */
3772   {
3773     MEP_INSN_CPMULUA1U_W_C3, "cpmulua1u_w_C3", "cpmulua1u.w", 32,
3774     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3775   },
3776 /* cpmulla1u.w $crqc,$crpc */
3777   {
3778     MEP_INSN_CPMULLA1U_W_C3, "cpmulla1u_w_C3", "cpmulla1u.w", 32,
3779     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3780   },
3781 /* cpmulua1.w $crqc,$crpc */
3782   {
3783     MEP_INSN_CPMULUA1_W_C3, "cpmulua1_w_C3", "cpmulua1.w", 32,
3784     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3785   },
3786 /* cpmulla1.w $crqc,$crpc */
3787   {
3788     MEP_INSN_CPMULLA1_W_C3, "cpmulla1_w_C3", "cpmulla1.w", 32,
3789     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3790   },
3791 /* cpmada1u.b $crqc,$crpc */
3792   {
3793     MEP_INSN_CPMADA1U_B_C3, "cpmada1u_b_C3", "cpmada1u.b", 32,
3794     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3795   },
3796 /* cpmada1.b $crqc,$crpc */
3797   {
3798     MEP_INSN_CPMADA1_B_C3, "cpmada1_b_C3", "cpmada1.b", 32,
3799     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3800   },
3801 /* cpmadua1.h $crqc,$crpc */
3802   {
3803     MEP_INSN_CPMADUA1_H_C3, "cpmadua1_h_C3", "cpmadua1.h", 32,
3804     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3805   },
3806 /* cpmadla1.h $crqc,$crpc */
3807   {
3808     MEP_INSN_CPMADLA1_H_C3, "cpmadla1_h_C3", "cpmadla1.h", 32,
3809     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3810   },
3811 /* cpmadua1u.w $crqc,$crpc */
3812   {
3813     MEP_INSN_CPMADUA1U_W_C3, "cpmadua1u_w_C3", "cpmadua1u.w", 32,
3814     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3815   },
3816 /* cpmadla1u.w $crqc,$crpc */
3817   {
3818     MEP_INSN_CPMADLA1U_W_C3, "cpmadla1u_w_C3", "cpmadla1u.w", 32,
3819     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3820   },
3821 /* cpmadua1.w $crqc,$crpc */
3822   {
3823     MEP_INSN_CPMADUA1_W_C3, "cpmadua1_w_C3", "cpmadua1.w", 32,
3824     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3825   },
3826 /* cpmadla1.w $crqc,$crpc */
3827   {
3828     MEP_INSN_CPMADLA1_W_C3, "cpmadla1_w_C3", "cpmadla1.w", 32,
3829     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3830   },
3831 /* cpmsbua1.h $crqc,$crpc */
3832   {
3833     MEP_INSN_CPMSBUA1_H_C3, "cpmsbua1_h_C3", "cpmsbua1.h", 32,
3834     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3835   },
3836 /* cpmsbla1.h $crqc,$crpc */
3837   {
3838     MEP_INSN_CPMSBLA1_H_C3, "cpmsbla1_h_C3", "cpmsbla1.h", 32,
3839     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3840   },
3841 /* cpmsbua1u.w $crqc,$crpc */
3842   {
3843     MEP_INSN_CPMSBUA1U_W_C3, "cpmsbua1u_w_C3", "cpmsbua1u.w", 32,
3844     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3845   },
3846 /* cpmsbla1u.w $crqc,$crpc */
3847   {
3848     MEP_INSN_CPMSBLA1U_W_C3, "cpmsbla1u_w_C3", "cpmsbla1u.w", 32,
3849     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3850   },
3851 /* cpmsbua1.w $crqc,$crpc */
3852   {
3853     MEP_INSN_CPMSBUA1_W_C3, "cpmsbua1_w_C3", "cpmsbua1.w", 32,
3854     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3855   },
3856 /* cpmsbla1.w $crqc,$crpc */
3857   {
3858     MEP_INSN_CPMSBLA1_W_C3, "cpmsbla1_w_C3", "cpmsbla1.w", 32,
3859     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3860   },
3861 /* cpsmadua1.h $crqc,$crpc */
3862   {
3863     MEP_INSN_CPSMADUA1_H_C3, "cpsmadua1_h_C3", "cpsmadua1.h", 32,
3864     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3865   },
3866 /* cpsmadla1.h $crqc,$crpc */
3867   {
3868     MEP_INSN_CPSMADLA1_H_C3, "cpsmadla1_h_C3", "cpsmadla1.h", 32,
3869     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3870   },
3871 /* cpsmadua1.w $crqc,$crpc */
3872   {
3873     MEP_INSN_CPSMADUA1_W_C3, "cpsmadua1_w_C3", "cpsmadua1.w", 32,
3874     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3875   },
3876 /* cpsmadla1.w $crqc,$crpc */
3877   {
3878     MEP_INSN_CPSMADLA1_W_C3, "cpsmadla1_w_C3", "cpsmadla1.w", 32,
3879     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3880   },
3881 /* cpsmsbua1.h $crqc,$crpc */
3882   {
3883     MEP_INSN_CPSMSBUA1_H_C3, "cpsmsbua1_h_C3", "cpsmsbua1.h", 32,
3884     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3885   },
3886 /* cpsmsbla1.h $crqc,$crpc */
3887   {
3888     MEP_INSN_CPSMSBLA1_H_C3, "cpsmsbla1_h_C3", "cpsmsbla1.h", 32,
3889     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3890   },
3891 /* cpsmsbua1.w $crqc,$crpc */
3892   {
3893     MEP_INSN_CPSMSBUA1_W_C3, "cpsmsbua1_w_C3", "cpsmsbua1.w", 32,
3894     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3895   },
3896 /* cpsmsbla1.w $crqc,$crpc */
3897   {
3898     MEP_INSN_CPSMSBLA1_W_C3, "cpsmsbla1_w_C3", "cpsmsbla1.w", 32,
3899     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3900   },
3901 /* cpmulslua1.h $crqc,$crpc */
3902   {
3903     MEP_INSN_CPMULSLUA1_H_C3, "cpmulslua1_h_C3", "cpmulslua1.h", 32,
3904     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3905   },
3906 /* cpmulslla1.h $crqc,$crpc */
3907   {
3908     MEP_INSN_CPMULSLLA1_H_C3, "cpmulslla1_h_C3", "cpmulslla1.h", 32,
3909     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3910   },
3911 /* cpmulslua1.w $crqc,$crpc */
3912   {
3913     MEP_INSN_CPMULSLUA1_W_C3, "cpmulslua1_w_C3", "cpmulslua1.w", 32,
3914     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3915   },
3916 /* cpmulslla1.w $crqc,$crpc */
3917   {
3918     MEP_INSN_CPMULSLLA1_W_C3, "cpmulslla1_w_C3", "cpmulslla1.w", 32,
3919     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3920   },
3921 /* cpsmadslua1.h $crqc,$crpc */
3922   {
3923     MEP_INSN_CPSMADSLUA1_H_C3, "cpsmadslua1_h_C3", "cpsmadslua1.h", 32,
3924     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3925   },
3926 /* cpsmadslla1.h $crqc,$crpc */
3927   {
3928     MEP_INSN_CPSMADSLLA1_H_C3, "cpsmadslla1_h_C3", "cpsmadslla1.h", 32,
3929     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3930   },
3931 /* cpsmadslua1.w $crqc,$crpc */
3932   {
3933     MEP_INSN_CPSMADSLUA1_W_C3, "cpsmadslua1_w_C3", "cpsmadslua1.w", 32,
3934     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3935   },
3936 /* cpsmadslla1.w $crqc,$crpc */
3937   {
3938     MEP_INSN_CPSMADSLLA1_W_C3, "cpsmadslla1_w_C3", "cpsmadslla1.w", 32,
3939     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3940   },
3941 /* cpsmsbslua1.h $crqc,$crpc */
3942   {
3943     MEP_INSN_CPSMSBSLUA1_H_C3, "cpsmsbslua1_h_C3", "cpsmsbslua1.h", 32,
3944     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3945   },
3946 /* cpsmsbslla1.h $crqc,$crpc */
3947   {
3948     MEP_INSN_CPSMSBSLLA1_H_C3, "cpsmsbslla1_h_C3", "cpsmsbslla1.h", 32,
3949     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3950   },
3951 /* cpsmsbslua1.w $crqc,$crpc */
3952   {
3953     MEP_INSN_CPSMSBSLUA1_W_C3, "cpsmsbslua1_w_C3", "cpsmsbslua1.w", 32,
3954     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3955   },
3956 /* cpsmsbslla1.w $crqc,$crpc */
3957   {
3958     MEP_INSN_CPSMSBSLLA1_W_C3, "cpsmsbslla1_w_C3", "cpsmsbslla1.w", 32,
3959     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3960   },
3961 /* c0nop */
3962   {
3963     MEP_INSN_C0NOP_P0_P0S, "c0nop_P0_P0S", "c0nop", 32,
3964     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x28" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P0S), 0 } } } }
3965   },
3966 /* cpadd3.b $crop,$crqp,$crpp */
3967   {
3968     MEP_INSN_CPADD3_B_P0S_P1, "cpadd3_b_P0S_P1", "cpadd3.b", 32,
3969     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x24" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S)|(1<<SLOTS_P1), 0 } } } }
3970   },
3971 /* cpadd3.h $crop,$crqp,$crpp */
3972   {
3973     MEP_INSN_CPADD3_H_P0S_P1, "cpadd3_h_P0S_P1", "cpadd3.h", 32,
3974     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x24" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S)|(1<<SLOTS_P1), 0 } } } }
3975   },
3976 /* cpadd3.w $crop,$crqp,$crpp */
3977   {
3978     MEP_INSN_CPADD3_W_P0S_P1, "cpadd3_w_P0S_P1", "cpadd3.w", 32,
3979     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x24" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S)|(1<<SLOTS_P1), 0 } } } }
3980   },
3981 /* cpunpacku.b $crop,$crqp,$crpp */
3982   {
3983     MEP_INSN_CPUNPACKU_B_P0S_P1, "cpunpacku_b_P0S_P1", "cpunpacku.b", 32,
3984     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x24" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S)|(1<<SLOTS_P1), 0 } } } }
3985   },
3986 /* cpunpacku.h $crop,$crqp,$crpp */
3987   {
3988     MEP_INSN_CPUNPACKU_H_P0S_P1, "cpunpacku_h_P0S_P1", "cpunpacku.h", 32,
3989     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x24" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S)|(1<<SLOTS_P1), 0 } } } }
3990   },
3991 /* cpunpacku.w $crop,$crqp,$crpp */
3992   {
3993     MEP_INSN_CPUNPACKU_W_P0S_P1, "cpunpacku_w_P0S_P1", "cpunpacku.w", 32,
3994     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x24" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S)|(1<<SLOTS_P1), 0 } } } }
3995   },
3996 /* cpunpackl.b $crop,$crqp,$crpp */
3997   {
3998     MEP_INSN_CPUNPACKL_B_P0S_P1, "cpunpackl_b_P0S_P1", "cpunpackl.b", 32,
3999     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x24" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S)|(1<<SLOTS_P1), 0 } } } }
4000   },
4001 /* cpunpackl.h $crop,$crqp,$crpp */
4002   {
4003     MEP_INSN_CPUNPACKL_H_P0S_P1, "cpunpackl_h_P0S_P1", "cpunpackl.h", 32,
4004     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x24" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S)|(1<<SLOTS_P1), 0 } } } }
4005   },
4006 /* cpunpackl.w $crop,$crqp,$crpp */
4007   {
4008     MEP_INSN_CPUNPACKL_W_P0S_P1, "cpunpackl_w_P0S_P1", "cpunpackl.w", 32,
4009     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x24" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S)|(1<<SLOTS_P1), 0 } } } }
4010   },
4011 /* cpsel $crop,$crqp,$crpp */
4012   {
4013     MEP_INSN_CPSEL_P0S_P1, "cpsel_P0S_P1", "cpsel", 32,
4014     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x24" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S)|(1<<SLOTS_P1), 0 } } } }
4015   },
4016 /* cpfsftbs0 $crop,$crqp,$crpp */
4017   {
4018     MEP_INSN_CPFSFTBS0_P0S_P1, "cpfsftbs0_P0S_P1", "cpfsftbs0", 32,
4019     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x24" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S)|(1<<SLOTS_P1), 0 } } } }
4020   },
4021 /* cpfsftbs1 $crop,$crqp,$crpp */
4022   {
4023     MEP_INSN_CPFSFTBS1_P0S_P1, "cpfsftbs1_P0S_P1", "cpfsftbs1", 32,
4024     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x24" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S)|(1<<SLOTS_P1), 0 } } } }
4025   },
4026 /* cpmov $crop,$crqp */
4027   {
4028     MEP_INSN_CPMOV_P0S_P1, "cpmov_P0S_P1", "cpmov", 32,
4029     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x24" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S)|(1<<SLOTS_P1), 0 } } } }
4030   },
4031 /* cpabsz.b $crop,$crqp */
4032   {
4033     MEP_INSN_CPABSZ_B_P0S_P1, "cpabsz_b_P0S_P1", "cpabsz.b", 32,
4034     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x24" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S)|(1<<SLOTS_P1), 0 } } } }
4035   },
4036 /* cpabsz.h $crop,$crqp */
4037   {
4038     MEP_INSN_CPABSZ_H_P0S_P1, "cpabsz_h_P0S_P1", "cpabsz.h", 32,
4039     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x24" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S)|(1<<SLOTS_P1), 0 } } } }
4040   },
4041 /* cpabsz.w $crop,$crqp */
4042   {
4043     MEP_INSN_CPABSZ_W_P0S_P1, "cpabsz_w_P0S_P1", "cpabsz.w", 32,
4044     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x24" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S)|(1<<SLOTS_P1), 0 } } } }
4045   },
4046 /* cpldz.h $crop,$crqp */
4047   {
4048     MEP_INSN_CPLDZ_H_P0S_P1, "cpldz_h_P0S_P1", "cpldz.h", 32,
4049     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x24" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S)|(1<<SLOTS_P1), 0 } } } }
4050   },
4051 /* cpldz.w $crop,$crqp */
4052   {
4053     MEP_INSN_CPLDZ_W_P0S_P1, "cpldz_w_P0S_P1", "cpldz.w", 32,
4054     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x24" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S)|(1<<SLOTS_P1), 0 } } } }
4055   },
4056 /* cpnorm.h $crop,$crqp */
4057   {
4058     MEP_INSN_CPNORM_H_P0S_P1, "cpnorm_h_P0S_P1", "cpnorm.h", 32,
4059     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x24" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S)|(1<<SLOTS_P1), 0 } } } }
4060   },
4061 /* cpnorm.w $crop,$crqp */
4062   {
4063     MEP_INSN_CPNORM_W_P0S_P1, "cpnorm_w_P0S_P1", "cpnorm.w", 32,
4064     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x24" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S)|(1<<SLOTS_P1), 0 } } } }
4065   },
4066 /* cphaddu.b $crop,$crqp */
4067   {
4068     MEP_INSN_CPHADDU_B_P0S_P1, "cphaddu_b_P0S_P1", "cphaddu.b", 32,
4069     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x24" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S)|(1<<SLOTS_P1), 0 } } } }
4070   },
4071 /* cphadd.b $crop,$crqp */
4072   {
4073     MEP_INSN_CPHADD_B_P0S_P1, "cphadd_b_P0S_P1", "cphadd.b", 32,
4074     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x24" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S)|(1<<SLOTS_P1), 0 } } } }
4075   },
4076 /* cphadd.h $crop,$crqp */
4077   {
4078     MEP_INSN_CPHADD_H_P0S_P1, "cphadd_h_P0S_P1", "cphadd.h", 32,
4079     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x24" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S)|(1<<SLOTS_P1), 0 } } } }
4080   },
4081 /* cphadd.w $crop,$crqp */
4082   {
4083     MEP_INSN_CPHADD_W_P0S_P1, "cphadd_w_P0S_P1", "cphadd.w", 32,
4084     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x24" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S)|(1<<SLOTS_P1), 0 } } } }
4085   },
4086 /* cpccadd.b $crqp */
4087   {
4088     MEP_INSN_CPCCADD_B_P0S_P1, "cpccadd_b_P0S_P1", "cpccadd.b", 32,
4089     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x24" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S)|(1<<SLOTS_P1), 0 } } } }
4090   },
4091 /* cpbcast.b $crop,$crqp */
4092   {
4093     MEP_INSN_CPBCAST_B_P0S_P1, "cpbcast_b_P0S_P1", "cpbcast.b", 32,
4094     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x24" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S)|(1<<SLOTS_P1), 0 } } } }
4095   },
4096 /* cpbcast.h $crop,$crqp */
4097   {
4098     MEP_INSN_CPBCAST_H_P0S_P1, "cpbcast_h_P0S_P1", "cpbcast.h", 32,
4099     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x24" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S)|(1<<SLOTS_P1), 0 } } } }
4100   },
4101 /* cpbcast.w $crop,$crqp */
4102   {
4103     MEP_INSN_CPBCAST_W_P0S_P1, "cpbcast_w_P0S_P1", "cpbcast.w", 32,
4104     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x24" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S)|(1<<SLOTS_P1), 0 } } } }
4105   },
4106 /* cpextuu.b $crop,$crqp */
4107   {
4108     MEP_INSN_CPEXTUU_B_P0S_P1, "cpextuu_b_P0S_P1", "cpextuu.b", 32,
4109     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x24" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S)|(1<<SLOTS_P1), 0 } } } }
4110   },
4111 /* cpextu.b $crop,$crqp */
4112   {
4113     MEP_INSN_CPEXTU_B_P0S_P1, "cpextu_b_P0S_P1", "cpextu.b", 32,
4114     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x24" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S)|(1<<SLOTS_P1), 0 } } } }
4115   },
4116 /* cpextuu.h $crop,$crqp */
4117   {
4118     MEP_INSN_CPEXTUU_H_P0S_P1, "cpextuu_h_P0S_P1", "cpextuu.h", 32,
4119     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x24" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S)|(1<<SLOTS_P1), 0 } } } }
4120   },
4121 /* cpextu.h $crop,$crqp */
4122   {
4123     MEP_INSN_CPEXTU_H_P0S_P1, "cpextu_h_P0S_P1", "cpextu.h", 32,
4124     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x24" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S)|(1<<SLOTS_P1), 0 } } } }
4125   },
4126 /* cpextlu.b $crop,$crqp */
4127   {
4128     MEP_INSN_CPEXTLU_B_P0S_P1, "cpextlu_b_P0S_P1", "cpextlu.b", 32,
4129     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x24" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S)|(1<<SLOTS_P1), 0 } } } }
4130   },
4131 /* cpextl.b $crop,$crqp */
4132   {
4133     MEP_INSN_CPEXTL_B_P0S_P1, "cpextl_b_P0S_P1", "cpextl.b", 32,
4134     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x24" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S)|(1<<SLOTS_P1), 0 } } } }
4135   },
4136 /* cpextlu.h $crop,$crqp */
4137   {
4138     MEP_INSN_CPEXTLU_H_P0S_P1, "cpextlu_h_P0S_P1", "cpextlu.h", 32,
4139     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x24" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S)|(1<<SLOTS_P1), 0 } } } }
4140   },
4141 /* cpextl.h $crop,$crqp */
4142   {
4143     MEP_INSN_CPEXTL_H_P0S_P1, "cpextl_h_P0S_P1", "cpextl.h", 32,
4144     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x24" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S)|(1<<SLOTS_P1), 0 } } } }
4145   },
4146 /* cpcastub.h $crop,$crqp */
4147   {
4148     MEP_INSN_CPCASTUB_H_P0S_P1, "cpcastub_h_P0S_P1", "cpcastub.h", 32,
4149     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x24" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S)|(1<<SLOTS_P1), 0 } } } }
4150   },
4151 /* cpcastb.h $crop,$crqp */
4152   {
4153     MEP_INSN_CPCASTB_H_P0S_P1, "cpcastb_h_P0S_P1", "cpcastb.h", 32,
4154     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x24" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S)|(1<<SLOTS_P1), 0 } } } }
4155   },
4156 /* cpcastub.w $crop,$crqp */
4157   {
4158     MEP_INSN_CPCASTUB_W_P0S_P1, "cpcastub_w_P0S_P1", "cpcastub.w", 32,
4159     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x24" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S)|(1<<SLOTS_P1), 0 } } } }
4160   },
4161 /* cpcastb.w $crop,$crqp */
4162   {
4163     MEP_INSN_CPCASTB_W_P0S_P1, "cpcastb_w_P0S_P1", "cpcastb.w", 32,
4164     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x24" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S)|(1<<SLOTS_P1), 0 } } } }
4165   },
4166 /* cpcastuh.w $crop,$crqp */
4167   {
4168     MEP_INSN_CPCASTUH_W_P0S_P1, "cpcastuh_w_P0S_P1", "cpcastuh.w", 32,
4169     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x24" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S)|(1<<SLOTS_P1), 0 } } } }
4170   },
4171 /* cpcasth.w $crop,$crqp */
4172   {
4173     MEP_INSN_CPCASTH_W_P0S_P1, "cpcasth_w_P0S_P1", "cpcasth.w", 32,
4174     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x24" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S)|(1<<SLOTS_P1), 0 } } } }
4175   },
4176 /* cdcastuw $crop,$crqp */
4177   {
4178     MEP_INSN_CDCASTUW_P0S_P1, "cdcastuw_P0S_P1", "cdcastuw", 32,
4179     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x24" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S)|(1<<SLOTS_P1), 0 } } } }
4180   },
4181 /* cdcastw $crop,$crqp */
4182   {
4183     MEP_INSN_CDCASTW_P0S_P1, "cdcastw_P0S_P1", "cdcastw", 32,
4184     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x24" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S)|(1<<SLOTS_P1), 0 } } } }
4185   },
4186 /* cpmovfrcsar0 $crop */
4187   {
4188     MEP_INSN_CPMOVFRCSAR0_P0S_P1, "cpmovfrcsar0_P0S_P1", "cpmovfrcsar0", 32,
4189     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x24" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S)|(1<<SLOTS_P1), 0 } } } }
4190   },
4191 /* cpmovfrcsar1 $crop */
4192   {
4193     MEP_INSN_CPMOVFRCSAR1_P0S_P1, "cpmovfrcsar1_P0S_P1", "cpmovfrcsar1", 32,
4194     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x24" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S)|(1<<SLOTS_P1), 0 } } } }
4195   },
4196 /* cpmovfrcc $crop */
4197   {
4198     MEP_INSN_CPMOVFRCC_P0S_P1, "cpmovfrcc_P0S_P1", "cpmovfrcc", 32,
4199     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x24" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S)|(1<<SLOTS_P1), 0 } } } }
4200   },
4201 /* cpmovtocsar0 $crqp */
4202   {
4203     MEP_INSN_CPMOVTOCSAR0_P0S_P1, "cpmovtocsar0_P0S_P1", "cpmovtocsar0", 32,
4204     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x24" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S)|(1<<SLOTS_P1), 0 } } } }
4205   },
4206 /* cpmovtocsar1 $crqp */
4207   {
4208     MEP_INSN_CPMOVTOCSAR1_P0S_P1, "cpmovtocsar1_P0S_P1", "cpmovtocsar1", 32,
4209     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x24" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S)|(1<<SLOTS_P1), 0 } } } }
4210   },
4211 /* cpmovtocc $crqp */
4212   {
4213     MEP_INSN_CPMOVTOCC_P0S_P1, "cpmovtocc_P0S_P1", "cpmovtocc", 32,
4214     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x24" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S)|(1<<SLOTS_P1), 0 } } } }
4215   },
4216 /* cpcmpeqz.b $crqp,$crpp */
4217   {
4218     MEP_INSN_CPCMPEQZ_B_P0S_P1, "cpcmpeqz_b_P0S_P1", "cpcmpeqz.b", 32,
4219     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x24" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S)|(1<<SLOTS_P1), 0 } } } }
4220   },
4221 /* cpcmpeq.b $crqp,$crpp */
4222   {
4223     MEP_INSN_CPCMPEQ_B_P0S_P1, "cpcmpeq_b_P0S_P1", "cpcmpeq.b", 32,
4224     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x24" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S)|(1<<SLOTS_P1), 0 } } } }
4225   },
4226 /* cpcmpeq.h $crqp,$crpp */
4227   {
4228     MEP_INSN_CPCMPEQ_H_P0S_P1, "cpcmpeq_h_P0S_P1", "cpcmpeq.h", 32,
4229     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x24" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S)|(1<<SLOTS_P1), 0 } } } }
4230   },
4231 /* cpcmpeq.w $crqp,$crpp */
4232   {
4233     MEP_INSN_CPCMPEQ_W_P0S_P1, "cpcmpeq_w_P0S_P1", "cpcmpeq.w", 32,
4234     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x24" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S)|(1<<SLOTS_P1), 0 } } } }
4235   },
4236 /* cpcmpne.b $crqp,$crpp */
4237   {
4238     MEP_INSN_CPCMPNE_B_P0S_P1, "cpcmpne_b_P0S_P1", "cpcmpne.b", 32,
4239     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x24" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S)|(1<<SLOTS_P1), 0 } } } }
4240   },
4241 /* cpcmpne.h $crqp,$crpp */
4242   {
4243     MEP_INSN_CPCMPNE_H_P0S_P1, "cpcmpne_h_P0S_P1", "cpcmpne.h", 32,
4244     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x24" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S)|(1<<SLOTS_P1), 0 } } } }
4245   },
4246 /* cpcmpne.w $crqp,$crpp */
4247   {
4248     MEP_INSN_CPCMPNE_W_P0S_P1, "cpcmpne_w_P0S_P1", "cpcmpne.w", 32,
4249     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x24" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S)|(1<<SLOTS_P1), 0 } } } }
4250   },
4251 /* cpcmpgtu.b $crqp,$crpp */
4252   {
4253     MEP_INSN_CPCMPGTU_B_P0S_P1, "cpcmpgtu_b_P0S_P1", "cpcmpgtu.b", 32,
4254     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x24" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S)|(1<<SLOTS_P1), 0 } } } }
4255   },
4256 /* cpcmpgt.b $crqp,$crpp */
4257   {
4258     MEP_INSN_CPCMPGT_B_P0S_P1, "cpcmpgt_b_P0S_P1", "cpcmpgt.b", 32,
4259     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x24" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S)|(1<<SLOTS_P1), 0 } } } }
4260   },
4261 /* cpcmpgt.h $crqp,$crpp */
4262   {
4263     MEP_INSN_CPCMPGT_H_P0S_P1, "cpcmpgt_h_P0S_P1", "cpcmpgt.h", 32,
4264     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x24" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S)|(1<<SLOTS_P1), 0 } } } }
4265   },
4266 /* cpcmpgtu.w $crqp,$crpp */
4267   {
4268     MEP_INSN_CPCMPGTU_W_P0S_P1, "cpcmpgtu_w_P0S_P1", "cpcmpgtu.w", 32,
4269     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x24" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S)|(1<<SLOTS_P1), 0 } } } }
4270   },
4271 /* cpcmpgt.w $crqp,$crpp */
4272   {
4273     MEP_INSN_CPCMPGT_W_P0S_P1, "cpcmpgt_w_P0S_P1", "cpcmpgt.w", 32,
4274     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x24" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S)|(1<<SLOTS_P1), 0 } } } }
4275   },
4276 /* cpcmpgeu.b $crqp,$crpp */
4277   {
4278     MEP_INSN_CPCMPGEU_B_P0S_P1, "cpcmpgeu_b_P0S_P1", "cpcmpgeu.b", 32,
4279     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x24" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S)|(1<<SLOTS_P1), 0 } } } }
4280   },
4281 /* cpcmpge.b $crqp,$crpp */
4282   {
4283     MEP_INSN_CPCMPGE_B_P0S_P1, "cpcmpge_b_P0S_P1", "cpcmpge.b", 32,
4284     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x24" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S)|(1<<SLOTS_P1), 0 } } } }
4285   },
4286 /* cpcmpge.h $crqp,$crpp */
4287   {
4288     MEP_INSN_CPCMPGE_H_P0S_P1, "cpcmpge_h_P0S_P1", "cpcmpge.h", 32,
4289     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x24" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S)|(1<<SLOTS_P1), 0 } } } }
4290   },
4291 /* cpcmpgeu.w $crqp,$crpp */
4292   {
4293     MEP_INSN_CPCMPGEU_W_P0S_P1, "cpcmpgeu_w_P0S_P1", "cpcmpgeu.w", 32,
4294     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x24" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S)|(1<<SLOTS_P1), 0 } } } }
4295   },
4296 /* cpcmpge.w $crqp,$crpp */
4297   {
4298     MEP_INSN_CPCMPGE_W_P0S_P1, "cpcmpge_w_P0S_P1", "cpcmpge.w", 32,
4299     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x24" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S)|(1<<SLOTS_P1), 0 } } } }
4300   },
4301 /* cpadda0u.b $crqp,$crpp */
4302   {
4303     MEP_INSN_CPADDA0U_B_P0S, "cpadda0u_b_P0S", "cpadda0u.b", 32,
4304     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S), 0 } } } }
4305   },
4306 /* cpadda0.b $crqp,$crpp */
4307   {
4308     MEP_INSN_CPADDA0_B_P0S, "cpadda0_b_P0S", "cpadda0.b", 32,
4309     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S), 0 } } } }
4310   },
4311 /* cpaddua0.h $crqp,$crpp */
4312   {
4313     MEP_INSN_CPADDUA0_H_P0S, "cpaddua0_h_P0S", "cpaddua0.h", 32,
4314     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S), 0 } } } }
4315   },
4316 /* cpaddla0.h $crqp,$crpp */
4317   {
4318     MEP_INSN_CPADDLA0_H_P0S, "cpaddla0_h_P0S", "cpaddla0.h", 32,
4319     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S), 0 } } } }
4320   },
4321 /* cpaddaca0u.b $crqp,$crpp */
4322   {
4323     MEP_INSN_CPADDACA0U_B_P0S, "cpaddaca0u_b_P0S", "cpaddaca0u.b", 32,
4324     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S), 0 } } } }
4325   },
4326 /* cpaddaca0.b $crqp,$crpp */
4327   {
4328     MEP_INSN_CPADDACA0_B_P0S, "cpaddaca0_b_P0S", "cpaddaca0.b", 32,
4329     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S), 0 } } } }
4330   },
4331 /* cpaddacua0.h $crqp,$crpp */
4332   {
4333     MEP_INSN_CPADDACUA0_H_P0S, "cpaddacua0_h_P0S", "cpaddacua0.h", 32,
4334     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S), 0 } } } }
4335   },
4336 /* cpaddacla0.h $crqp,$crpp */
4337   {
4338     MEP_INSN_CPADDACLA0_H_P0S, "cpaddacla0_h_P0S", "cpaddacla0.h", 32,
4339     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S), 0 } } } }
4340   },
4341 /* cpsuba0u.b $crqp,$crpp */
4342   {
4343     MEP_INSN_CPSUBA0U_B_P0S, "cpsuba0u_b_P0S", "cpsuba0u.b", 32,
4344     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S), 0 } } } }
4345   },
4346 /* cpsuba0.b $crqp,$crpp */
4347   {
4348     MEP_INSN_CPSUBA0_B_P0S, "cpsuba0_b_P0S", "cpsuba0.b", 32,
4349     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S), 0 } } } }
4350   },
4351 /* cpsubua0.h $crqp,$crpp */
4352   {
4353     MEP_INSN_CPSUBUA0_H_P0S, "cpsubua0_h_P0S", "cpsubua0.h", 32,
4354     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S), 0 } } } }
4355   },
4356 /* cpsubla0.h $crqp,$crpp */
4357   {
4358     MEP_INSN_CPSUBLA0_H_P0S, "cpsubla0_h_P0S", "cpsubla0.h", 32,
4359     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S), 0 } } } }
4360   },
4361 /* cpsubaca0u.b $crqp,$crpp */
4362   {
4363     MEP_INSN_CPSUBACA0U_B_P0S, "cpsubaca0u_b_P0S", "cpsubaca0u.b", 32,
4364     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S), 0 } } } }
4365   },
4366 /* cpsubaca0.b $crqp,$crpp */
4367   {
4368     MEP_INSN_CPSUBACA0_B_P0S, "cpsubaca0_b_P0S", "cpsubaca0.b", 32,
4369     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S), 0 } } } }
4370   },
4371 /* cpsubacua0.h $crqp,$crpp */
4372   {
4373     MEP_INSN_CPSUBACUA0_H_P0S, "cpsubacua0_h_P0S", "cpsubacua0.h", 32,
4374     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S), 0 } } } }
4375   },
4376 /* cpsubacla0.h $crqp,$crpp */
4377   {
4378     MEP_INSN_CPSUBACLA0_H_P0S, "cpsubacla0_h_P0S", "cpsubacla0.h", 32,
4379     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S), 0 } } } }
4380   },
4381 /* cpabsa0u.b $crqp,$crpp */
4382   {
4383     MEP_INSN_CPABSA0U_B_P0S, "cpabsa0u_b_P0S", "cpabsa0u.b", 32,
4384     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S), 0 } } } }
4385   },
4386 /* cpabsa0.b $crqp,$crpp */
4387   {
4388     MEP_INSN_CPABSA0_B_P0S, "cpabsa0_b_P0S", "cpabsa0.b", 32,
4389     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S), 0 } } } }
4390   },
4391 /* cpabsua0.h $crqp,$crpp */
4392   {
4393     MEP_INSN_CPABSUA0_H_P0S, "cpabsua0_h_P0S", "cpabsua0.h", 32,
4394     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S), 0 } } } }
4395   },
4396 /* cpabsla0.h $crqp,$crpp */
4397   {
4398     MEP_INSN_CPABSLA0_H_P0S, "cpabsla0_h_P0S", "cpabsla0.h", 32,
4399     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S), 0 } } } }
4400   },
4401 /* cpsada0u.b $crqp,$crpp */
4402   {
4403     MEP_INSN_CPSADA0U_B_P0S, "cpsada0u_b_P0S", "cpsada0u.b", 32,
4404     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S), 0 } } } }
4405   },
4406 /* cpsada0.b $crqp,$crpp */
4407   {
4408     MEP_INSN_CPSADA0_B_P0S, "cpsada0_b_P0S", "cpsada0.b", 32,
4409     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S), 0 } } } }
4410   },
4411 /* cpsadua0.h $crqp,$crpp */
4412   {
4413     MEP_INSN_CPSADUA0_H_P0S, "cpsadua0_h_P0S", "cpsadua0.h", 32,
4414     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S), 0 } } } }
4415   },
4416 /* cpsadla0.h $crqp,$crpp */
4417   {
4418     MEP_INSN_CPSADLA0_H_P0S, "cpsadla0_h_P0S", "cpsadla0.h", 32,
4419     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S), 0 } } } }
4420   },
4421 /* cpseta0.h $crqp,$crpp */
4422   {
4423     MEP_INSN_CPSETA0_H_P0S, "cpseta0_h_P0S", "cpseta0.h", 32,
4424     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S), 0 } } } }
4425   },
4426 /* cpsetua0.w $crqp,$crpp */
4427   {
4428     MEP_INSN_CPSETUA0_W_P0S, "cpsetua0_w_P0S", "cpsetua0.w", 32,
4429     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S), 0 } } } }
4430   },
4431 /* cpsetla0.w $crqp,$crpp */
4432   {
4433     MEP_INSN_CPSETLA0_W_P0S, "cpsetla0_w_P0S", "cpsetla0.w", 32,
4434     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S), 0 } } } }
4435   },
4436 /* cpmova0.b $crop */
4437   {
4438     MEP_INSN_CPMOVA0_B_P0S, "cpmova0_b_P0S", "cpmova0.b", 32,
4439     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S), 0 } } } }
4440   },
4441 /* cpmovua0.h $crop */
4442   {
4443     MEP_INSN_CPMOVUA0_H_P0S, "cpmovua0_h_P0S", "cpmovua0.h", 32,
4444     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S), 0 } } } }
4445   },
4446 /* cpmovla0.h $crop */
4447   {
4448     MEP_INSN_CPMOVLA0_H_P0S, "cpmovla0_h_P0S", "cpmovla0.h", 32,
4449     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S), 0 } } } }
4450   },
4451 /* cpmovuua0.w $crop */
4452   {
4453     MEP_INSN_CPMOVUUA0_W_P0S, "cpmovuua0_w_P0S", "cpmovuua0.w", 32,
4454     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S), 0 } } } }
4455   },
4456 /* cpmovula0.w $crop */
4457   {
4458     MEP_INSN_CPMOVULA0_W_P0S, "cpmovula0_w_P0S", "cpmovula0.w", 32,
4459     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S), 0 } } } }
4460   },
4461 /* cpmovlua0.w $crop */
4462   {
4463     MEP_INSN_CPMOVLUA0_W_P0S, "cpmovlua0_w_P0S", "cpmovlua0.w", 32,
4464     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S), 0 } } } }
4465   },
4466 /* cpmovlla0.w $crop */
4467   {
4468     MEP_INSN_CPMOVLLA0_W_P0S, "cpmovlla0_w_P0S", "cpmovlla0.w", 32,
4469     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S), 0 } } } }
4470   },
4471 /* cppacka0u.b $crop */
4472   {
4473     MEP_INSN_CPPACKA0U_B_P0S, "cppacka0u_b_P0S", "cppacka0u.b", 32,
4474     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S), 0 } } } }
4475   },
4476 /* cppacka0.b $crop */
4477   {
4478     MEP_INSN_CPPACKA0_B_P0S, "cppacka0_b_P0S", "cppacka0.b", 32,
4479     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S), 0 } } } }
4480   },
4481 /* cppackua0.h $crop */
4482   {
4483     MEP_INSN_CPPACKUA0_H_P0S, "cppackua0_h_P0S", "cppackua0.h", 32,
4484     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S), 0 } } } }
4485   },
4486 /* cppackla0.h $crop */
4487   {
4488     MEP_INSN_CPPACKLA0_H_P0S, "cppackla0_h_P0S", "cppackla0.h", 32,
4489     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S), 0 } } } }
4490   },
4491 /* cppackua0.w $crop */
4492   {
4493     MEP_INSN_CPPACKUA0_W_P0S, "cppackua0_w_P0S", "cppackua0.w", 32,
4494     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S), 0 } } } }
4495   },
4496 /* cppackla0.w $crop */
4497   {
4498     MEP_INSN_CPPACKLA0_W_P0S, "cppackla0_w_P0S", "cppackla0.w", 32,
4499     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S), 0 } } } }
4500   },
4501 /* cpmovhua0.w $crop */
4502   {
4503     MEP_INSN_CPMOVHUA0_W_P0S, "cpmovhua0_w_P0S", "cpmovhua0.w", 32,
4504     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S), 0 } } } }
4505   },
4506 /* cpmovhla0.w $crop */
4507   {
4508     MEP_INSN_CPMOVHLA0_W_P0S, "cpmovhla0_w_P0S", "cpmovhla0.w", 32,
4509     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S), 0 } } } }
4510   },
4511 /* cpacsuma0 */
4512   {
4513     MEP_INSN_CPACSUMA0_P0S, "cpacsuma0_P0S", "cpacsuma0", 32,
4514     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S), 0 } } } }
4515   },
4516 /* cpaccpa0 */
4517   {
4518     MEP_INSN_CPACCPA0_P0S, "cpaccpa0_P0S", "cpaccpa0", 32,
4519     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S), 0 } } } }
4520   },
4521 /* cpsrla0 $crqp */
4522   {
4523     MEP_INSN_CPSRLA0_P0S, "cpsrla0_P0S", "cpsrla0", 32,
4524     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S), 0 } } } }
4525   },
4526 /* cpsraa0 $crqp */
4527   {
4528     MEP_INSN_CPSRAA0_P0S, "cpsraa0_P0S", "cpsraa0", 32,
4529     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S), 0 } } } }
4530   },
4531 /* cpslla0 $crqp */
4532   {
4533     MEP_INSN_CPSLLA0_P0S, "cpslla0_P0S", "cpslla0", 32,
4534     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S), 0 } } } }
4535   },
4536 /* cpsrlia0 $imm5p23 */
4537   {
4538     MEP_INSN_CPSRLIA0_P0S, "cpsrlia0_P0S", "cpsrlia0", 32,
4539     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S), 0 } } } }
4540   },
4541 /* cpsraia0 $imm5p23 */
4542   {
4543     MEP_INSN_CPSRAIA0_P0S, "cpsraia0_P0S", "cpsraia0", 32,
4544     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S), 0 } } } }
4545   },
4546 /* cpsllia0 $imm5p23 */
4547   {
4548     MEP_INSN_CPSLLIA0_P0S, "cpsllia0_P0S", "cpsllia0", 32,
4549     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S), 0 } } } }
4550   },
4551 /* cpfsftba0s0u.b $crqp,$crpp */
4552   {
4553     MEP_INSN_CPFSFTBA0S0U_B_P0S, "cpfsftba0s0u_b_P0S", "cpfsftba0s0u.b", 32,
4554     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S), 0 } } } }
4555   },
4556 /* cpfsftba0s0.b $crqp,$crpp */
4557   {
4558     MEP_INSN_CPFSFTBA0S0_B_P0S, "cpfsftba0s0_b_P0S", "cpfsftba0s0.b", 32,
4559     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S), 0 } } } }
4560   },
4561 /* cpfsftbua0s0.h $crqp,$crpp */
4562   {
4563     MEP_INSN_CPFSFTBUA0S0_H_P0S, "cpfsftbua0s0_h_P0S", "cpfsftbua0s0.h", 32,
4564     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S), 0 } } } }
4565   },
4566 /* cpfsftbla0s0.h $crqp,$crpp */
4567   {
4568     MEP_INSN_CPFSFTBLA0S0_H_P0S, "cpfsftbla0s0_h_P0S", "cpfsftbla0s0.h", 32,
4569     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S), 0 } } } }
4570   },
4571 /* cpfaca0s0u.b $crqp,$crpp */
4572   {
4573     MEP_INSN_CPFACA0S0U_B_P0S, "cpfaca0s0u_b_P0S", "cpfaca0s0u.b", 32,
4574     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S), 0 } } } }
4575   },
4576 /* cpfaca0s0.b $crqp,$crpp */
4577   {
4578     MEP_INSN_CPFACA0S0_B_P0S, "cpfaca0s0_b_P0S", "cpfaca0s0.b", 32,
4579     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S), 0 } } } }
4580   },
4581 /* cpfacua0s0.h $crqp,$crpp */
4582   {
4583     MEP_INSN_CPFACUA0S0_H_P0S, "cpfacua0s0_h_P0S", "cpfacua0s0.h", 32,
4584     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S), 0 } } } }
4585   },
4586 /* cpfacla0s0.h $crqp,$crpp */
4587   {
4588     MEP_INSN_CPFACLA0S0_H_P0S, "cpfacla0s0_h_P0S", "cpfacla0s0.h", 32,
4589     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S), 0 } } } }
4590   },
4591 /* cpfsftba0s1u.b $crqp,$crpp */
4592   {
4593     MEP_INSN_CPFSFTBA0S1U_B_P0S, "cpfsftba0s1u_b_P0S", "cpfsftba0s1u.b", 32,
4594     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S), 0 } } } }
4595   },
4596 /* cpfsftba0s1.b $crqp,$crpp */
4597   {
4598     MEP_INSN_CPFSFTBA0S1_B_P0S, "cpfsftba0s1_b_P0S", "cpfsftba0s1.b", 32,
4599     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S), 0 } } } }
4600   },
4601 /* cpfsftbua0s1.h $crqp,$crpp */
4602   {
4603     MEP_INSN_CPFSFTBUA0S1_H_P0S, "cpfsftbua0s1_h_P0S", "cpfsftbua0s1.h", 32,
4604     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S), 0 } } } }
4605   },
4606 /* cpfsftbla0s1.h $crqp,$crpp */
4607   {
4608     MEP_INSN_CPFSFTBLA0S1_H_P0S, "cpfsftbla0s1_h_P0S", "cpfsftbla0s1.h", 32,
4609     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S), 0 } } } }
4610   },
4611 /* cpfaca0s1u.b $crqp,$crpp */
4612   {
4613     MEP_INSN_CPFACA0S1U_B_P0S, "cpfaca0s1u_b_P0S", "cpfaca0s1u.b", 32,
4614     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S), 0 } } } }
4615   },
4616 /* cpfaca0s1.b $crqp,$crpp */
4617   {
4618     MEP_INSN_CPFACA0S1_B_P0S, "cpfaca0s1_b_P0S", "cpfaca0s1.b", 32,
4619     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S), 0 } } } }
4620   },
4621 /* cpfacua0s1.h $crqp,$crpp */
4622   {
4623     MEP_INSN_CPFACUA0S1_H_P0S, "cpfacua0s1_h_P0S", "cpfacua0s1.h", 32,
4624     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S), 0 } } } }
4625   },
4626 /* cpfacla0s1.h $crqp,$crpp */
4627   {
4628     MEP_INSN_CPFACLA0S1_H_P0S, "cpfacla0s1_h_P0S", "cpfacla0s1.h", 32,
4629     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S), 0 } } } }
4630   },
4631 /* cpfsftbi $crop,$crqp,$crpp,$imm3p5 */
4632   {
4633     MEP_INSN_CPFSFTBI_P0_P1, "cpfsftbi_P0_P1", "cpfsftbi", 32,
4634     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
4635   },
4636 /* cpacmpeq.b $crqp,$crpp */
4637   {
4638     MEP_INSN_CPACMPEQ_B_P0_P1, "cpacmpeq_b_P0_P1", "cpacmpeq.b", 32,
4639     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
4640   },
4641 /* cpacmpeq.h $crqp,$crpp */
4642   {
4643     MEP_INSN_CPACMPEQ_H_P0_P1, "cpacmpeq_h_P0_P1", "cpacmpeq.h", 32,
4644     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
4645   },
4646 /* cpacmpeq.w $crqp,$crpp */
4647   {
4648     MEP_INSN_CPACMPEQ_W_P0_P1, "cpacmpeq_w_P0_P1", "cpacmpeq.w", 32,
4649     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
4650   },
4651 /* cpacmpne.b $crqp,$crpp */
4652   {
4653     MEP_INSN_CPACMPNE_B_P0_P1, "cpacmpne_b_P0_P1", "cpacmpne.b", 32,
4654     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
4655   },
4656 /* cpacmpne.h $crqp,$crpp */
4657   {
4658     MEP_INSN_CPACMPNE_H_P0_P1, "cpacmpne_h_P0_P1", "cpacmpne.h", 32,
4659     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
4660   },
4661 /* cpacmpne.w $crqp,$crpp */
4662   {
4663     MEP_INSN_CPACMPNE_W_P0_P1, "cpacmpne_w_P0_P1", "cpacmpne.w", 32,
4664     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
4665   },
4666 /* cpacmpgtu.b $crqp,$crpp */
4667   {
4668     MEP_INSN_CPACMPGTU_B_P0_P1, "cpacmpgtu_b_P0_P1", "cpacmpgtu.b", 32,
4669     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
4670   },
4671 /* cpacmpgt.b $crqp,$crpp */
4672   {
4673     MEP_INSN_CPACMPGT_B_P0_P1, "cpacmpgt_b_P0_P1", "cpacmpgt.b", 32,
4674     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
4675   },
4676 /* cpacmpgt.h $crqp,$crpp */
4677   {
4678     MEP_INSN_CPACMPGT_H_P0_P1, "cpacmpgt_h_P0_P1", "cpacmpgt.h", 32,
4679     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
4680   },
4681 /* cpacmpgtu.w $crqp,$crpp */
4682   {
4683     MEP_INSN_CPACMPGTU_W_P0_P1, "cpacmpgtu_w_P0_P1", "cpacmpgtu.w", 32,
4684     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
4685   },
4686 /* cpacmpgt.w $crqp,$crpp */
4687   {
4688     MEP_INSN_CPACMPGT_W_P0_P1, "cpacmpgt_w_P0_P1", "cpacmpgt.w", 32,
4689     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
4690   },
4691 /* cpacmpgeu.b $crqp,$crpp */
4692   {
4693     MEP_INSN_CPACMPGEU_B_P0_P1, "cpacmpgeu_b_P0_P1", "cpacmpgeu.b", 32,
4694     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
4695   },
4696 /* cpacmpge.b $crqp,$crpp */
4697   {
4698     MEP_INSN_CPACMPGE_B_P0_P1, "cpacmpge_b_P0_P1", "cpacmpge.b", 32,
4699     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
4700   },
4701 /* cpacmpge.h $crqp,$crpp */
4702   {
4703     MEP_INSN_CPACMPGE_H_P0_P1, "cpacmpge_h_P0_P1", "cpacmpge.h", 32,
4704     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
4705   },
4706 /* cpacmpgeu.w $crqp,$crpp */
4707   {
4708     MEP_INSN_CPACMPGEU_W_P0_P1, "cpacmpgeu_w_P0_P1", "cpacmpgeu.w", 32,
4709     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
4710   },
4711 /* cpacmpge.w $crqp,$crpp */
4712   {
4713     MEP_INSN_CPACMPGE_W_P0_P1, "cpacmpge_w_P0_P1", "cpacmpge.w", 32,
4714     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
4715   },
4716 /* cpocmpeq.b $crqp,$crpp */
4717   {
4718     MEP_INSN_CPOCMPEQ_B_P0_P1, "cpocmpeq_b_P0_P1", "cpocmpeq.b", 32,
4719     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
4720   },
4721 /* cpocmpeq.h $crqp,$crpp */
4722   {
4723     MEP_INSN_CPOCMPEQ_H_P0_P1, "cpocmpeq_h_P0_P1", "cpocmpeq.h", 32,
4724     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
4725   },
4726 /* cpocmpeq.w $crqp,$crpp */
4727   {
4728     MEP_INSN_CPOCMPEQ_W_P0_P1, "cpocmpeq_w_P0_P1", "cpocmpeq.w", 32,
4729     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
4730   },
4731 /* cpocmpne.b $crqp,$crpp */
4732   {
4733     MEP_INSN_CPOCMPNE_B_P0_P1, "cpocmpne_b_P0_P1", "cpocmpne.b", 32,
4734     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
4735   },
4736 /* cpocmpne.h $crqp,$crpp */
4737   {
4738     MEP_INSN_CPOCMPNE_H_P0_P1, "cpocmpne_h_P0_P1", "cpocmpne.h", 32,
4739     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
4740   },
4741 /* cpocmpne.w $crqp,$crpp */
4742   {
4743     MEP_INSN_CPOCMPNE_W_P0_P1, "cpocmpne_w_P0_P1", "cpocmpne.w", 32,
4744     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
4745   },
4746 /* cpocmpgtu.b $crqp,$crpp */
4747   {
4748     MEP_INSN_CPOCMPGTU_B_P0_P1, "cpocmpgtu_b_P0_P1", "cpocmpgtu.b", 32,
4749     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
4750   },
4751 /* cpocmpgt.b $crqp,$crpp */
4752   {
4753     MEP_INSN_CPOCMPGT_B_P0_P1, "cpocmpgt_b_P0_P1", "cpocmpgt.b", 32,
4754     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
4755   },
4756 /* cpocmpgt.h $crqp,$crpp */
4757   {
4758     MEP_INSN_CPOCMPGT_H_P0_P1, "cpocmpgt_h_P0_P1", "cpocmpgt.h", 32,
4759     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
4760   },
4761 /* cpocmpgtu.w $crqp,$crpp */
4762   {
4763     MEP_INSN_CPOCMPGTU_W_P0_P1, "cpocmpgtu_w_P0_P1", "cpocmpgtu.w", 32,
4764     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
4765   },
4766 /* cpocmpgt.w $crqp,$crpp */
4767   {
4768     MEP_INSN_CPOCMPGT_W_P0_P1, "cpocmpgt_w_P0_P1", "cpocmpgt.w", 32,
4769     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
4770   },
4771 /* cpocmpgeu.b $crqp,$crpp */
4772   {
4773     MEP_INSN_CPOCMPGEU_B_P0_P1, "cpocmpgeu_b_P0_P1", "cpocmpgeu.b", 32,
4774     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
4775   },
4776 /* cpocmpge.b $crqp,$crpp */
4777   {
4778     MEP_INSN_CPOCMPGE_B_P0_P1, "cpocmpge_b_P0_P1", "cpocmpge.b", 32,
4779     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
4780   },
4781 /* cpocmpge.h $crqp,$crpp */
4782   {
4783     MEP_INSN_CPOCMPGE_H_P0_P1, "cpocmpge_h_P0_P1", "cpocmpge.h", 32,
4784     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
4785   },
4786 /* cpocmpgeu.w $crqp,$crpp */
4787   {
4788     MEP_INSN_CPOCMPGEU_W_P0_P1, "cpocmpgeu_w_P0_P1", "cpocmpgeu.w", 32,
4789     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
4790   },
4791 /* cpocmpge.w $crqp,$crpp */
4792   {
4793     MEP_INSN_CPOCMPGE_W_P0_P1, "cpocmpge_w_P0_P1", "cpocmpge.w", 32,
4794     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
4795   },
4796 /* cdadd3 $crop,$crqp,$crpp */
4797   {
4798     MEP_INSN_CDADD3_P0_P1, "cdadd3_P0_P1", "cdadd3", 32,
4799     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
4800   },
4801 /* cpsub3.b $crop,$crqp,$crpp */
4802   {
4803     MEP_INSN_CPSUB3_B_P0_P1, "cpsub3_b_P0_P1", "cpsub3.b", 32,
4804     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
4805   },
4806 /* cpsub3.h $crop,$crqp,$crpp */
4807   {
4808     MEP_INSN_CPSUB3_H_P0_P1, "cpsub3_h_P0_P1", "cpsub3.h", 32,
4809     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
4810   },
4811 /* cpsub3.w $crop,$crqp,$crpp */
4812   {
4813     MEP_INSN_CPSUB3_W_P0_P1, "cpsub3_w_P0_P1", "cpsub3.w", 32,
4814     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
4815   },
4816 /* cdsub3 $crop,$crqp,$crpp */
4817   {
4818     MEP_INSN_CDSUB3_P0_P1, "cdsub3_P0_P1", "cdsub3", 32,
4819     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
4820   },
4821 /* cpsadd3.h $crop,$crqp,$crpp */
4822   {
4823     MEP_INSN_CPSADD3_H_P0_P1, "cpsadd3_h_P0_P1", "cpsadd3.h", 32,
4824     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
4825   },
4826 /* cpsadd3.w $crop,$crqp,$crpp */
4827   {
4828     MEP_INSN_CPSADD3_W_P0_P1, "cpsadd3_w_P0_P1", "cpsadd3.w", 32,
4829     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
4830   },
4831 /* cpssub3.h $crop,$crqp,$crpp */
4832   {
4833     MEP_INSN_CPSSUB3_H_P0_P1, "cpssub3_h_P0_P1", "cpssub3.h", 32,
4834     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
4835   },
4836 /* cpssub3.w $crop,$crqp,$crpp */
4837   {
4838     MEP_INSN_CPSSUB3_W_P0_P1, "cpssub3_w_P0_P1", "cpssub3.w", 32,
4839     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
4840   },
4841 /* cpextuaddu3.b $crop,$crqp,$crpp */
4842   {
4843     MEP_INSN_CPEXTUADDU3_B_P0_P1, "cpextuaddu3_b_P0_P1", "cpextuaddu3.b", 32,
4844     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
4845   },
4846 /* cpextuadd3.b $crop,$crqp,$crpp */
4847   {
4848     MEP_INSN_CPEXTUADD3_B_P0_P1, "cpextuadd3_b_P0_P1", "cpextuadd3.b", 32,
4849     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
4850   },
4851 /* cpextladdu3.b $crop,$crqp,$crpp */
4852   {
4853     MEP_INSN_CPEXTLADDU3_B_P0_P1, "cpextladdu3_b_P0_P1", "cpextladdu3.b", 32,
4854     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
4855   },
4856 /* cpextladd3.b $crop,$crqp,$crpp */
4857   {
4858     MEP_INSN_CPEXTLADD3_B_P0_P1, "cpextladd3_b_P0_P1", "cpextladd3.b", 32,
4859     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
4860   },
4861 /* cpextusubu3.b $crop,$crqp,$crpp */
4862   {
4863     MEP_INSN_CPEXTUSUBU3_B_P0_P1, "cpextusubu3_b_P0_P1", "cpextusubu3.b", 32,
4864     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
4865   },
4866 /* cpextusub3.b $crop,$crqp,$crpp */
4867   {
4868     MEP_INSN_CPEXTUSUB3_B_P0_P1, "cpextusub3_b_P0_P1", "cpextusub3.b", 32,
4869     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
4870   },
4871 /* cpextlsubu3.b $crop,$crqp,$crpp */
4872   {
4873     MEP_INSN_CPEXTLSUBU3_B_P0_P1, "cpextlsubu3_b_P0_P1", "cpextlsubu3.b", 32,
4874     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
4875   },
4876 /* cpextlsub3.b $crop,$crqp,$crpp */
4877   {
4878     MEP_INSN_CPEXTLSUB3_B_P0_P1, "cpextlsub3_b_P0_P1", "cpextlsub3.b", 32,
4879     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
4880   },
4881 /* cpaveu3.b $crop,$crqp,$crpp */
4882   {
4883     MEP_INSN_CPAVEU3_B_P0_P1, "cpaveu3_b_P0_P1", "cpaveu3.b", 32,
4884     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
4885   },
4886 /* cpave3.b $crop,$crqp,$crpp */
4887   {
4888     MEP_INSN_CPAVE3_B_P0_P1, "cpave3_b_P0_P1", "cpave3.b", 32,
4889     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
4890   },
4891 /* cpave3.h $crop,$crqp,$crpp */
4892   {
4893     MEP_INSN_CPAVE3_H_P0_P1, "cpave3_h_P0_P1", "cpave3.h", 32,
4894     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
4895   },
4896 /* cpave3.w $crop,$crqp,$crpp */
4897   {
4898     MEP_INSN_CPAVE3_W_P0_P1, "cpave3_w_P0_P1", "cpave3.w", 32,
4899     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
4900   },
4901 /* cpaddsru3.b $crop,$crqp,$crpp */
4902   {
4903     MEP_INSN_CPADDSRU3_B_P0_P1, "cpaddsru3_b_P0_P1", "cpaddsru3.b", 32,
4904     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
4905   },
4906 /* cpaddsr3.b $crop,$crqp,$crpp */
4907   {
4908     MEP_INSN_CPADDSR3_B_P0_P1, "cpaddsr3_b_P0_P1", "cpaddsr3.b", 32,
4909     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
4910   },
4911 /* cpaddsr3.h $crop,$crqp,$crpp */
4912   {
4913     MEP_INSN_CPADDSR3_H_P0_P1, "cpaddsr3_h_P0_P1", "cpaddsr3.h", 32,
4914     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
4915   },
4916 /* cpaddsr3.w $crop,$crqp,$crpp */
4917   {
4918     MEP_INSN_CPADDSR3_W_P0_P1, "cpaddsr3_w_P0_P1", "cpaddsr3.w", 32,
4919     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
4920   },
4921 /* cpabsu3.b $crop,$crqp,$crpp */
4922   {
4923     MEP_INSN_CPABSU3_B_P0_P1, "cpabsu3_b_P0_P1", "cpabsu3.b", 32,
4924     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
4925   },
4926 /* cpabs3.b $crop,$crqp,$crpp */
4927   {
4928     MEP_INSN_CPABS3_B_P0_P1, "cpabs3_b_P0_P1", "cpabs3.b", 32,
4929     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
4930   },
4931 /* cpabs3.h $crop,$crqp,$crpp */
4932   {
4933     MEP_INSN_CPABS3_H_P0_P1, "cpabs3_h_P0_P1", "cpabs3.h", 32,
4934     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
4935   },
4936 /* cpand3 $crop,$crqp,$crpp */
4937   {
4938     MEP_INSN_CPAND3_P0_P1, "cpand3_P0_P1", "cpand3", 32,
4939     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
4940   },
4941 /* cpor3 $crop,$crqp,$crpp */
4942   {
4943     MEP_INSN_CPOR3_P0_P1, "cpor3_P0_P1", "cpor3", 32,
4944     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
4945   },
4946 /* cpnor3 $crop,$crqp,$crpp */
4947   {
4948     MEP_INSN_CPNOR3_P0_P1, "cpnor3_P0_P1", "cpnor3", 32,
4949     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
4950   },
4951 /* cpxor3 $crop,$crqp,$crpp */
4952   {
4953     MEP_INSN_CPXOR3_P0_P1, "cpxor3_P0_P1", "cpxor3", 32,
4954     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
4955   },
4956 /* cppacku.b $crop,$crqp,$crpp */
4957   {
4958     MEP_INSN_CPPACKU_B_P0_P1, "cppacku_b_P0_P1", "cppacku.b", 32,
4959     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
4960   },
4961 /* cppack.b $crop,$crqp,$crpp */
4962   {
4963     MEP_INSN_CPPACK_B_P0_P1, "cppack_b_P0_P1", "cppack.b", 32,
4964     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
4965   },
4966 /* cppack.h $crop,$crqp,$crpp */
4967   {
4968     MEP_INSN_CPPACK_H_P0_P1, "cppack_h_P0_P1", "cppack.h", 32,
4969     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
4970   },
4971 /* cpmaxu3.b $crop,$crqp,$crpp */
4972   {
4973     MEP_INSN_CPMAXU3_B_P0_P1, "cpmaxu3_b_P0_P1", "cpmaxu3.b", 32,
4974     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
4975   },
4976 /* cpmax3.b $crop,$crqp,$crpp */
4977   {
4978     MEP_INSN_CPMAX3_B_P0_P1, "cpmax3_b_P0_P1", "cpmax3.b", 32,
4979     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
4980   },
4981 /* cpmax3.h $crop,$crqp,$crpp */
4982   {
4983     MEP_INSN_CPMAX3_H_P0_P1, "cpmax3_h_P0_P1", "cpmax3.h", 32,
4984     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
4985   },
4986 /* cpmaxu3.w $crop,$crqp,$crpp */
4987   {
4988     MEP_INSN_CPMAXU3_W_P0_P1, "cpmaxu3_w_P0_P1", "cpmaxu3.w", 32,
4989     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
4990   },
4991 /* cpmax3.w $crop,$crqp,$crpp */
4992   {
4993     MEP_INSN_CPMAX3_W_P0_P1, "cpmax3_w_P0_P1", "cpmax3.w", 32,
4994     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
4995   },
4996 /* cpminu3.b $crop,$crqp,$crpp */
4997   {
4998     MEP_INSN_CPMINU3_B_P0_P1, "cpminu3_b_P0_P1", "cpminu3.b", 32,
4999     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
5000   },
5001 /* cpmin3.b $crop,$crqp,$crpp */
5002   {
5003     MEP_INSN_CPMIN3_B_P0_P1, "cpmin3_b_P0_P1", "cpmin3.b", 32,
5004     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
5005   },
5006 /* cpmin3.h $crop,$crqp,$crpp */
5007   {
5008     MEP_INSN_CPMIN3_H_P0_P1, "cpmin3_h_P0_P1", "cpmin3.h", 32,
5009     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
5010   },
5011 /* cpminu3.w $crop,$crqp,$crpp */
5012   {
5013     MEP_INSN_CPMINU3_W_P0_P1, "cpminu3_w_P0_P1", "cpminu3.w", 32,
5014     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
5015   },
5016 /* cpmin3.w $crop,$crqp,$crpp */
5017   {
5018     MEP_INSN_CPMIN3_W_P0_P1, "cpmin3_w_P0_P1", "cpmin3.w", 32,
5019     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
5020   },
5021 /* cpsrl3.b $crop,$crqp,$crpp */
5022   {
5023     MEP_INSN_CPSRL3_B_P0_P1, "cpsrl3_b_P0_P1", "cpsrl3.b", 32,
5024     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
5025   },
5026 /* cpssrl3.b $crop,$crqp,$crpp */
5027   {
5028     MEP_INSN_CPSSRL3_B_P0_P1, "cpssrl3_b_P0_P1", "cpssrl3.b", 32,
5029     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
5030   },
5031 /* cpsrl3.h $crop,$crqp,$crpp */
5032   {
5033     MEP_INSN_CPSRL3_H_P0_P1, "cpsrl3_h_P0_P1", "cpsrl3.h", 32,
5034     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
5035   },
5036 /* cpssrl3.h $crop,$crqp,$crpp */
5037   {
5038     MEP_INSN_CPSSRL3_H_P0_P1, "cpssrl3_h_P0_P1", "cpssrl3.h", 32,
5039     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
5040   },
5041 /* cpsrl3.w $crop,$crqp,$crpp */
5042   {
5043     MEP_INSN_CPSRL3_W_P0_P1, "cpsrl3_w_P0_P1", "cpsrl3.w", 32,
5044     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
5045   },
5046 /* cpssrl3.w $crop,$crqp,$crpp */
5047   {
5048     MEP_INSN_CPSSRL3_W_P0_P1, "cpssrl3_w_P0_P1", "cpssrl3.w", 32,
5049     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
5050   },
5051 /* cdsrl3 $crop,$crqp,$crpp */
5052   {
5053     MEP_INSN_CDSRL3_P0_P1, "cdsrl3_P0_P1", "cdsrl3", 32,
5054     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
5055   },
5056 /* cpsra3.b $crop,$crqp,$crpp */
5057   {
5058     MEP_INSN_CPSRA3_B_P0_P1, "cpsra3_b_P0_P1", "cpsra3.b", 32,
5059     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
5060   },
5061 /* cpssra3.b $crop,$crqp,$crpp */
5062   {
5063     MEP_INSN_CPSSRA3_B_P0_P1, "cpssra3_b_P0_P1", "cpssra3.b", 32,
5064     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
5065   },
5066 /* cpsra3.h $crop,$crqp,$crpp */
5067   {
5068     MEP_INSN_CPSRA3_H_P0_P1, "cpsra3_h_P0_P1", "cpsra3.h", 32,
5069     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
5070   },
5071 /* cpssra3.h $crop,$crqp,$crpp */
5072   {
5073     MEP_INSN_CPSSRA3_H_P0_P1, "cpssra3_h_P0_P1", "cpssra3.h", 32,
5074     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
5075   },
5076 /* cpsra3.w $crop,$crqp,$crpp */
5077   {
5078     MEP_INSN_CPSRA3_W_P0_P1, "cpsra3_w_P0_P1", "cpsra3.w", 32,
5079     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
5080   },
5081 /* cpssra3.w $crop,$crqp,$crpp */
5082   {
5083     MEP_INSN_CPSSRA3_W_P0_P1, "cpssra3_w_P0_P1", "cpssra3.w", 32,
5084     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
5085   },
5086 /* cdsra3 $crop,$crqp,$crpp */
5087   {
5088     MEP_INSN_CDSRA3_P0_P1, "cdsra3_P0_P1", "cdsra3", 32,
5089     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
5090   },
5091 /* cpsll3.b $crop,$crqp,$crpp */
5092   {
5093     MEP_INSN_CPSLL3_B_P0_P1, "cpsll3_b_P0_P1", "cpsll3.b", 32,
5094     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
5095   },
5096 /* cpssll3.b $crop,$crqp,$crpp */
5097   {
5098     MEP_INSN_CPSSLL3_B_P0_P1, "cpssll3_b_P0_P1", "cpssll3.b", 32,
5099     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
5100   },
5101 /* cpsll3.h $crop,$crqp,$crpp */
5102   {
5103     MEP_INSN_CPSLL3_H_P0_P1, "cpsll3_h_P0_P1", "cpsll3.h", 32,
5104     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
5105   },
5106 /* cpssll3.h $crop,$crqp,$crpp */
5107   {
5108     MEP_INSN_CPSSLL3_H_P0_P1, "cpssll3_h_P0_P1", "cpssll3.h", 32,
5109     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
5110   },
5111 /* cpsll3.w $crop,$crqp,$crpp */
5112   {
5113     MEP_INSN_CPSLL3_W_P0_P1, "cpsll3_w_P0_P1", "cpsll3.w", 32,
5114     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
5115   },
5116 /* cpssll3.w $crop,$crqp,$crpp */
5117   {
5118     MEP_INSN_CPSSLL3_W_P0_P1, "cpssll3_w_P0_P1", "cpssll3.w", 32,
5119     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
5120   },
5121 /* cdsll3 $crop,$crqp,$crpp */
5122   {
5123     MEP_INSN_CDSLL3_P0_P1, "cdsll3_P0_P1", "cdsll3", 32,
5124     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
5125   },
5126 /* cpsla3.h $crop,$crqp,$crpp */
5127   {
5128     MEP_INSN_CPSLA3_H_P0_P1, "cpsla3_h_P0_P1", "cpsla3.h", 32,
5129     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
5130   },
5131 /* cpsla3.w $crop,$crqp,$crpp */
5132   {
5133     MEP_INSN_CPSLA3_W_P0_P1, "cpsla3_w_P0_P1", "cpsla3.w", 32,
5134     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
5135   },
5136 /* cpsrli3.b $crop,$crqp,$imm3p5 */
5137   {
5138     MEP_INSN_CPSRLI3_B_P0_P1, "cpsrli3_b_P0_P1", "cpsrli3.b", 32,
5139     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
5140   },
5141 /* cpsrli3.h $crop,$crqp,$imm4p4 */
5142   {
5143     MEP_INSN_CPSRLI3_H_P0_P1, "cpsrli3_h_P0_P1", "cpsrli3.h", 32,
5144     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
5145   },
5146 /* cpsrli3.w $crop,$crqp,$imm5p3 */
5147   {
5148     MEP_INSN_CPSRLI3_W_P0_P1, "cpsrli3_w_P0_P1", "cpsrli3.w", 32,
5149     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
5150   },
5151 /* cdsrli3 $crop,$crqp,$imm6p2 */
5152   {
5153     MEP_INSN_CDSRLI3_P0_P1, "cdsrli3_P0_P1", "cdsrli3", 32,
5154     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
5155   },
5156 /* cpsrai3.b $crop,$crqp,$imm3p5 */
5157   {
5158     MEP_INSN_CPSRAI3_B_P0_P1, "cpsrai3_b_P0_P1", "cpsrai3.b", 32,
5159     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
5160   },
5161 /* cpsrai3.h $crop,$crqp,$imm4p4 */
5162   {
5163     MEP_INSN_CPSRAI3_H_P0_P1, "cpsrai3_h_P0_P1", "cpsrai3.h", 32,
5164     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
5165   },
5166 /* cpsrai3.w $crop,$crqp,$imm5p3 */
5167   {
5168     MEP_INSN_CPSRAI3_W_P0_P1, "cpsrai3_w_P0_P1", "cpsrai3.w", 32,
5169     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
5170   },
5171 /* cdsrai3 $crop,$crqp,$imm6p2 */
5172   {
5173     MEP_INSN_CDSRAI3_P0_P1, "cdsrai3_P0_P1", "cdsrai3", 32,
5174     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
5175   },
5176 /* cpslli3.b $crop,$crqp,$imm3p5 */
5177   {
5178     MEP_INSN_CPSLLI3_B_P0_P1, "cpslli3_b_P0_P1", "cpslli3.b", 32,
5179     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
5180   },
5181 /* cpslli3.h $crop,$crqp,$imm4p4 */
5182   {
5183     MEP_INSN_CPSLLI3_H_P0_P1, "cpslli3_h_P0_P1", "cpslli3.h", 32,
5184     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
5185   },
5186 /* cpslli3.w $crop,$crqp,$imm5p3 */
5187   {
5188     MEP_INSN_CPSLLI3_W_P0_P1, "cpslli3_w_P0_P1", "cpslli3.w", 32,
5189     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
5190   },
5191 /* cdslli3 $crop,$crqp,$imm6p2 */
5192   {
5193     MEP_INSN_CDSLLI3_P0_P1, "cdslli3_P0_P1", "cdslli3", 32,
5194     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
5195   },
5196 /* cpslai3.h $crop,$crqp,$imm4p4 */
5197   {
5198     MEP_INSN_CPSLAI3_H_P0_P1, "cpslai3_h_P0_P1", "cpslai3.h", 32,
5199     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
5200   },
5201 /* cpslai3.w $crop,$crqp,$imm5p3 */
5202   {
5203     MEP_INSN_CPSLAI3_W_P0_P1, "cpslai3_w_P0_P1", "cpslai3.w", 32,
5204     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
5205   },
5206 /* cpclipiu3.w $crop,$crqp,$imm5p3 */
5207   {
5208     MEP_INSN_CPCLIPIU3_W_P0_P1, "cpclipiu3_w_P0_P1", "cpclipiu3.w", 32,
5209     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
5210   },
5211 /* cpclipi3.w $crop,$crqp,$imm5p3 */
5212   {
5213     MEP_INSN_CPCLIPI3_W_P0_P1, "cpclipi3_w_P0_P1", "cpclipi3.w", 32,
5214     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
5215   },
5216 /* cdclipiu3 $crop,$crqp,$imm6p2 */
5217   {
5218     MEP_INSN_CDCLIPIU3_P0_P1, "cdclipiu3_P0_P1", "cdclipiu3", 32,
5219     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
5220   },
5221 /* cdclipi3 $crop,$crqp,$imm6p2 */
5222   {
5223     MEP_INSN_CDCLIPI3_P0_P1, "cdclipi3_P0_P1", "cdclipi3", 32,
5224     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
5225   },
5226 /* cpmovi.h $crqp,$simm16p0 */
5227   {
5228     MEP_INSN_CPMOVI_H_P0_P1, "cpmovi_h_P0_P1", "cpmovi.h", 32,
5229     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
5230   },
5231 /* cpmoviu.w $crqp,$imm16p0 */
5232   {
5233     MEP_INSN_CPMOVIU_W_P0_P1, "cpmoviu_w_P0_P1", "cpmoviu.w", 32,
5234     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
5235   },
5236 /* cpmovi.w $crqp,$simm16p0 */
5237   {
5238     MEP_INSN_CPMOVI_W_P0_P1, "cpmovi_w_P0_P1", "cpmovi.w", 32,
5239     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
5240   },
5241 /* cdmoviu $crqp,$imm16p0 */
5242   {
5243     MEP_INSN_CDMOVIU_P0_P1, "cdmoviu_P0_P1", "cdmoviu", 32,
5244     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
5245   },
5246 /* cdmovi $crqp,$simm16p0 */
5247   {
5248     MEP_INSN_CDMOVI_P0_P1, "cdmovi_P0_P1", "cdmovi", 32,
5249     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
5250   },
5251 /* c1nop */
5252   {
5253     MEP_INSN_C1NOP_P1, "c1nop_P1", "c1nop", 32,
5254     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
5255   },
5256 /* cpadda1u.b $crqp,$crpp */
5257   {
5258     MEP_INSN_CPADDA1U_B_P1, "cpadda1u_b_P1", "cpadda1u.b", 32,
5259     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
5260   },
5261 /* cpadda1.b $crqp,$crpp */
5262   {
5263     MEP_INSN_CPADDA1_B_P1, "cpadda1_b_P1", "cpadda1.b", 32,
5264     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
5265   },
5266 /* cpaddua1.h $crqp,$crpp */
5267   {
5268     MEP_INSN_CPADDUA1_H_P1, "cpaddua1_h_P1", "cpaddua1.h", 32,
5269     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
5270   },
5271 /* cpaddla1.h $crqp,$crpp */
5272   {
5273     MEP_INSN_CPADDLA1_H_P1, "cpaddla1_h_P1", "cpaddla1.h", 32,
5274     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
5275   },
5276 /* cpaddaca1u.b $crqp,$crpp */
5277   {
5278     MEP_INSN_CPADDACA1U_B_P1, "cpaddaca1u_b_P1", "cpaddaca1u.b", 32,
5279     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
5280   },
5281 /* cpaddaca1.b $crqp,$crpp */
5282   {
5283     MEP_INSN_CPADDACA1_B_P1, "cpaddaca1_b_P1", "cpaddaca1.b", 32,
5284     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
5285   },
5286 /* cpaddacua1.h $crqp,$crpp */
5287   {
5288     MEP_INSN_CPADDACUA1_H_P1, "cpaddacua1_h_P1", "cpaddacua1.h", 32,
5289     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
5290   },
5291 /* cpaddacla1.h $crqp,$crpp */
5292   {
5293     MEP_INSN_CPADDACLA1_H_P1, "cpaddacla1_h_P1", "cpaddacla1.h", 32,
5294     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
5295   },
5296 /* cpsuba1u.b $crqp,$crpp */
5297   {
5298     MEP_INSN_CPSUBA1U_B_P1, "cpsuba1u_b_P1", "cpsuba1u.b", 32,
5299     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
5300   },
5301 /* cpsuba1.b $crqp,$crpp */
5302   {
5303     MEP_INSN_CPSUBA1_B_P1, "cpsuba1_b_P1", "cpsuba1.b", 32,
5304     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
5305   },
5306 /* cpsubua1.h $crqp,$crpp */
5307   {
5308     MEP_INSN_CPSUBUA1_H_P1, "cpsubua1_h_P1", "cpsubua1.h", 32,
5309     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
5310   },
5311 /* cpsubla1.h $crqp,$crpp */
5312   {
5313     MEP_INSN_CPSUBLA1_H_P1, "cpsubla1_h_P1", "cpsubla1.h", 32,
5314     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
5315   },
5316 /* cpsubaca1u.b $crqp,$crpp */
5317   {
5318     MEP_INSN_CPSUBACA1U_B_P1, "cpsubaca1u_b_P1", "cpsubaca1u.b", 32,
5319     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
5320   },
5321 /* cpsubaca1.b $crqp,$crpp */
5322   {
5323     MEP_INSN_CPSUBACA1_B_P1, "cpsubaca1_b_P1", "cpsubaca1.b", 32,
5324     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
5325   },
5326 /* cpsubacua1.h $crqp,$crpp */
5327   {
5328     MEP_INSN_CPSUBACUA1_H_P1, "cpsubacua1_h_P1", "cpsubacua1.h", 32,
5329     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
5330   },
5331 /* cpsubacla1.h $crqp,$crpp */
5332   {
5333     MEP_INSN_CPSUBACLA1_H_P1, "cpsubacla1_h_P1", "cpsubacla1.h", 32,
5334     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
5335   },
5336 /* cpabsa1u.b $crqp,$crpp */
5337   {
5338     MEP_INSN_CPABSA1U_B_P1, "cpabsa1u_b_P1", "cpabsa1u.b", 32,
5339     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
5340   },
5341 /* cpabsa1.b $crqp,$crpp */
5342   {
5343     MEP_INSN_CPABSA1_B_P1, "cpabsa1_b_P1", "cpabsa1.b", 32,
5344     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
5345   },
5346 /* cpabsua1.h $crqp,$crpp */
5347   {
5348     MEP_INSN_CPABSUA1_H_P1, "cpabsua1_h_P1", "cpabsua1.h", 32,
5349     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
5350   },
5351 /* cpabsla1.h $crqp,$crpp */
5352   {
5353     MEP_INSN_CPABSLA1_H_P1, "cpabsla1_h_P1", "cpabsla1.h", 32,
5354     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
5355   },
5356 /* cpsada1u.b $crqp,$crpp */
5357   {
5358     MEP_INSN_CPSADA1U_B_P1, "cpsada1u_b_P1", "cpsada1u.b", 32,
5359     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
5360   },
5361 /* cpsada1.b $crqp,$crpp */
5362   {
5363     MEP_INSN_CPSADA1_B_P1, "cpsada1_b_P1", "cpsada1.b", 32,
5364     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
5365   },
5366 /* cpsadua1.h $crqp,$crpp */
5367   {
5368     MEP_INSN_CPSADUA1_H_P1, "cpsadua1_h_P1", "cpsadua1.h", 32,
5369     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
5370   },
5371 /* cpsadla1.h $crqp,$crpp */
5372   {
5373     MEP_INSN_CPSADLA1_H_P1, "cpsadla1_h_P1", "cpsadla1.h", 32,
5374     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
5375   },
5376 /* cpseta1.h $crqp,$crpp */
5377   {
5378     MEP_INSN_CPSETA1_H_P1, "cpseta1_h_P1", "cpseta1.h", 32,
5379     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
5380   },
5381 /* cpsetua1.w $crqp,$crpp */
5382   {
5383     MEP_INSN_CPSETUA1_W_P1, "cpsetua1_w_P1", "cpsetua1.w", 32,
5384     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
5385   },
5386 /* cpsetla1.w $crqp,$crpp */
5387   {
5388     MEP_INSN_CPSETLA1_W_P1, "cpsetla1_w_P1", "cpsetla1.w", 32,
5389     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
5390   },
5391 /* cpmova1.b $crop */
5392   {
5393     MEP_INSN_CPMOVA1_B_P1, "cpmova1_b_P1", "cpmova1.b", 32,
5394     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
5395   },
5396 /* cpmovua1.h $crop */
5397   {
5398     MEP_INSN_CPMOVUA1_H_P1, "cpmovua1_h_P1", "cpmovua1.h", 32,
5399     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
5400   },
5401 /* cpmovla1.h $crop */
5402   {
5403     MEP_INSN_CPMOVLA1_H_P1, "cpmovla1_h_P1", "cpmovla1.h", 32,
5404     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
5405   },
5406 /* cpmovuua1.w $crop */
5407   {
5408     MEP_INSN_CPMOVUUA1_W_P1, "cpmovuua1_w_P1", "cpmovuua1.w", 32,
5409     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
5410   },
5411 /* cpmovula1.w $crop */
5412   {
5413     MEP_INSN_CPMOVULA1_W_P1, "cpmovula1_w_P1", "cpmovula1.w", 32,
5414     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
5415   },
5416 /* cpmovlua1.w $crop */
5417   {
5418     MEP_INSN_CPMOVLUA1_W_P1, "cpmovlua1_w_P1", "cpmovlua1.w", 32,
5419     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
5420   },
5421 /* cpmovlla1.w $crop */
5422   {
5423     MEP_INSN_CPMOVLLA1_W_P1, "cpmovlla1_w_P1", "cpmovlla1.w", 32,
5424     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
5425   },
5426 /* cppacka1u.b $crop */
5427   {
5428     MEP_INSN_CPPACKA1U_B_P1, "cppacka1u_b_P1", "cppacka1u.b", 32,
5429     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
5430   },
5431 /* cppacka1.b $crop */
5432   {
5433     MEP_INSN_CPPACKA1_B_P1, "cppacka1_b_P1", "cppacka1.b", 32,
5434     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
5435   },
5436 /* cppackua1.h $crop */
5437   {
5438     MEP_INSN_CPPACKUA1_H_P1, "cppackua1_h_P1", "cppackua1.h", 32,
5439     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
5440   },
5441 /* cppackla1.h $crop */
5442   {
5443     MEP_INSN_CPPACKLA1_H_P1, "cppackla1_h_P1", "cppackla1.h", 32,
5444     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
5445   },
5446 /* cppackua1.w $crop */
5447   {
5448     MEP_INSN_CPPACKUA1_W_P1, "cppackua1_w_P1", "cppackua1.w", 32,
5449     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
5450   },
5451 /* cppackla1.w $crop */
5452   {
5453     MEP_INSN_CPPACKLA1_W_P1, "cppackla1_w_P1", "cppackla1.w", 32,
5454     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
5455   },
5456 /* cpmovhua1.w $crop */
5457   {
5458     MEP_INSN_CPMOVHUA1_W_P1, "cpmovhua1_w_P1", "cpmovhua1.w", 32,
5459     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
5460   },
5461 /* cpmovhla1.w $crop */
5462   {
5463     MEP_INSN_CPMOVHLA1_W_P1, "cpmovhla1_w_P1", "cpmovhla1.w", 32,
5464     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
5465   },
5466 /* cpacsuma1 */
5467   {
5468     MEP_INSN_CPACSUMA1_P1, "cpacsuma1_P1", "cpacsuma1", 32,
5469     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
5470   },
5471 /* cpaccpa1 */
5472   {
5473     MEP_INSN_CPACCPA1_P1, "cpaccpa1_P1", "cpaccpa1", 32,
5474     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
5475   },
5476 /* cpacswp */
5477   {
5478     MEP_INSN_CPACSWP_P1, "cpacswp_P1", "cpacswp", 32,
5479     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
5480   },
5481 /* cpsrla1 $crqp */
5482   {
5483     MEP_INSN_CPSRLA1_P1, "cpsrla1_P1", "cpsrla1", 32,
5484     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
5485   },
5486 /* cpsraa1 $crqp */
5487   {
5488     MEP_INSN_CPSRAA1_P1, "cpsraa1_P1", "cpsraa1", 32,
5489     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
5490   },
5491 /* cpslla1 $crqp */
5492   {
5493     MEP_INSN_CPSLLA1_P1, "cpslla1_P1", "cpslla1", 32,
5494     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
5495   },
5496 /* cpsrlia1 $imm5p23 */
5497   {
5498     MEP_INSN_CPSRLIA1_1_P1, "cpsrlia1_1_p1", "cpsrlia1", 32,
5499     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
5500   },
5501 /* cpsraia1 $imm5p23 */
5502   {
5503     MEP_INSN_CPSRAIA1_1_P1, "cpsraia1_1_p1", "cpsraia1", 32,
5504     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
5505   },
5506 /* cpsllia1 $imm5p23 */
5507   {
5508     MEP_INSN_CPSLLIA1_1_P1, "cpsllia1_1_p1", "cpsllia1", 32,
5509     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
5510   },
5511 /* cpfmulia1s0u.b $crqp,$crpp,$simm8p0 */
5512   {
5513     MEP_INSN_CPFMULIA1S0U_B_P1, "cpfmulia1s0u_b_P1", "cpfmulia1s0u.b", 32,
5514     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
5515   },
5516 /* cpfmulia1s0.b $crqp,$crpp,$simm8p0 */
5517   {
5518     MEP_INSN_CPFMULIA1S0_B_P1, "cpfmulia1s0_b_P1", "cpfmulia1s0.b", 32,
5519     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
5520   },
5521 /* cpfmuliua1s0.h $crqp,$crpp,$simm8p0 */
5522   {
5523     MEP_INSN_CPFMULIUA1S0_H_P1, "cpfmuliua1s0_h_P1", "cpfmuliua1s0.h", 32,
5524     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
5525   },
5526 /* cpfmulila1s0.h $crqp,$crpp,$simm8p0 */
5527   {
5528     MEP_INSN_CPFMULILA1S0_H_P1, "cpfmulila1s0_h_P1", "cpfmulila1s0.h", 32,
5529     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
5530   },
5531 /* cpfmadia1s0u.b $crqp,$crpp,$simm8p0 */
5532   {
5533     MEP_INSN_CPFMADIA1S0U_B_P1, "cpfmadia1s0u_b_P1", "cpfmadia1s0u.b", 32,
5534     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
5535   },
5536 /* cpfmadia1s0.b $crqp,$crpp,$simm8p0 */
5537   {
5538     MEP_INSN_CPFMADIA1S0_B_P1, "cpfmadia1s0_b_P1", "cpfmadia1s0.b", 32,
5539     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
5540   },
5541 /* cpfmadiua1s0.h $crqp,$crpp,$simm8p0 */
5542   {
5543     MEP_INSN_CPFMADIUA1S0_H_P1, "cpfmadiua1s0_h_P1", "cpfmadiua1s0.h", 32,
5544     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
5545   },
5546 /* cpfmadila1s0.h $crqp,$crpp,$simm8p0 */
5547   {
5548     MEP_INSN_CPFMADILA1S0_H_P1, "cpfmadila1s0_h_P1", "cpfmadila1s0.h", 32,
5549     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
5550   },
5551 /* cpfmulia1s1u.b $crqp,$crpp,$simm8p0 */
5552   {
5553     MEP_INSN_CPFMULIA1S1U_B_P1, "cpfmulia1s1u_b_P1", "cpfmulia1s1u.b", 32,
5554     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
5555   },
5556 /* cpfmulia1s1.b $crqp,$crpp,$simm8p0 */
5557   {
5558     MEP_INSN_CPFMULIA1S1_B_P1, "cpfmulia1s1_b_P1", "cpfmulia1s1.b", 32,
5559     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
5560   },
5561 /* cpfmuliua1s1.h $crqp,$crpp,$simm8p0 */
5562   {
5563     MEP_INSN_CPFMULIUA1S1_H_P1, "cpfmuliua1s1_h_P1", "cpfmuliua1s1.h", 32,
5564     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
5565   },
5566 /* cpfmulila1s1.h $crqp,$crpp,$simm8p0 */
5567   {
5568     MEP_INSN_CPFMULILA1S1_H_P1, "cpfmulila1s1_h_P1", "cpfmulila1s1.h", 32,
5569     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
5570   },
5571 /* cpfmadia1s1u.b $crqp,$crpp,$simm8p0 */
5572   {
5573     MEP_INSN_CPFMADIA1S1U_B_P1, "cpfmadia1s1u_b_P1", "cpfmadia1s1u.b", 32,
5574     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
5575   },
5576 /* cpfmadia1s1.b $crqp,$crpp,$simm8p0 */
5577   {
5578     MEP_INSN_CPFMADIA1S1_B_P1, "cpfmadia1s1_b_P1", "cpfmadia1s1.b", 32,
5579     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
5580   },
5581 /* cpfmadiua1s1.h $crqp,$crpp,$simm8p0 */
5582   {
5583     MEP_INSN_CPFMADIUA1S1_H_P1, "cpfmadiua1s1_h_P1", "cpfmadiua1s1.h", 32,
5584     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
5585   },
5586 /* cpfmadila1s1.h $crqp,$crpp,$simm8p0 */
5587   {
5588     MEP_INSN_CPFMADILA1S1_H_P1, "cpfmadila1s1_h_P1", "cpfmadila1s1.h", 32,
5589     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
5590   },
5591 /* cpamulia1u.b $crqp,$crpp,$simm8p0 */
5592   {
5593     MEP_INSN_CPAMULIA1U_B_P1, "cpamulia1u_b_P1", "cpamulia1u.b", 32,
5594     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
5595   },
5596 /* cpamulia1.b $crqp,$crpp,$simm8p0 */
5597   {
5598     MEP_INSN_CPAMULIA1_B_P1, "cpamulia1_b_P1", "cpamulia1.b", 32,
5599     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
5600   },
5601 /* cpamuliua1.h $crqp,$crpp,$simm8p0 */
5602   {
5603     MEP_INSN_CPAMULIUA1_H_P1, "cpamuliua1_h_P1", "cpamuliua1.h", 32,
5604     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
5605   },
5606 /* cpamulila1.h $crqp,$crpp,$simm8p0 */
5607   {
5608     MEP_INSN_CPAMULILA1_H_P1, "cpamulila1_h_P1", "cpamulila1.h", 32,
5609     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
5610   },
5611 /* cpamadia1u.b $crqp,$crpp,$simm8p0 */
5612   {
5613     MEP_INSN_CPAMADIA1U_B_P1, "cpamadia1u_b_P1", "cpamadia1u.b", 32,
5614     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
5615   },
5616 /* cpamadia1.b $crqp,$crpp,$simm8p0 */
5617   {
5618     MEP_INSN_CPAMADIA1_B_P1, "cpamadia1_b_P1", "cpamadia1.b", 32,
5619     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
5620   },
5621 /* cpamadiua1.h $crqp,$crpp,$simm8p0 */
5622   {
5623     MEP_INSN_CPAMADIUA1_H_P1, "cpamadiua1_h_P1", "cpamadiua1.h", 32,
5624     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
5625   },
5626 /* cpamadila1.h $crqp,$crpp,$simm8p0 */
5627   {
5628     MEP_INSN_CPAMADILA1_H_P1, "cpamadila1_h_P1", "cpamadila1.h", 32,
5629     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
5630   },
5631 /* cpfmulia1u.b $crqp,$crpp,$imm3p25,$simm8p0 */
5632   {
5633     MEP_INSN_CPFMULIA1U_B_P1, "cpfmulia1u_b_P1", "cpfmulia1u.b", 32,
5634     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
5635   },
5636 /* cpfmulia1.b $crqp,$crpp,$imm3p25,$simm8p0 */
5637   {
5638     MEP_INSN_CPFMULIA1_B_P1, "cpfmulia1_b_P1", "cpfmulia1.b", 32,
5639     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
5640   },
5641 /* cpfmuliua1.h $crqp,$crpp,$imm3p25,$simm8p0 */
5642   {
5643     MEP_INSN_CPFMULIUA1_H_P1, "cpfmuliua1_h_P1", "cpfmuliua1.h", 32,
5644     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
5645   },
5646 /* cpfmulila1.h $crqp,$crpp,$imm3p25,$simm8p0 */
5647   {
5648     MEP_INSN_CPFMULILA1_H_P1, "cpfmulila1_h_P1", "cpfmulila1.h", 32,
5649     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
5650   },
5651 /* cpfmadia1u.b $crqp,$crpp,$imm3p25,$simm8p0 */
5652   {
5653     MEP_INSN_CPFMADIA1U_B_P1, "cpfmadia1u_b_P1", "cpfmadia1u.b", 32,
5654     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
5655   },
5656 /* cpfmadia1.b $crqp,$crpp,$imm3p25,$simm8p0 */
5657   {
5658     MEP_INSN_CPFMADIA1_B_P1, "cpfmadia1_b_P1", "cpfmadia1.b", 32,
5659     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
5660   },
5661 /* cpfmadiua1.h $crqp,$crpp,$imm3p25,$simm8p0 */
5662   {
5663     MEP_INSN_CPFMADIUA1_H_P1, "cpfmadiua1_h_P1", "cpfmadiua1.h", 32,
5664     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
5665   },
5666 /* cpfmadila1.h $crqp,$crpp,$imm3p25,$simm8p0 */
5667   {
5668     MEP_INSN_CPFMADILA1_H_P1, "cpfmadila1_h_P1", "cpfmadila1.h", 32,
5669     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
5670   },
5671 /* cpssqa1u.b $crqp,$crpp */
5672   {
5673     MEP_INSN_CPSSQA1U_B_P1, "cpssqa1u_b_P1", "cpssqa1u.b", 32,
5674     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
5675   },
5676 /* cpssqa1.b $crqp,$crpp */
5677   {
5678     MEP_INSN_CPSSQA1_B_P1, "cpssqa1_b_P1", "cpssqa1.b", 32,
5679     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
5680   },
5681 /* cpssda1u.b $crqp,$crpp */
5682   {
5683     MEP_INSN_CPSSDA1U_B_P1, "cpssda1u_b_P1", "cpssda1u.b", 32,
5684     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
5685   },
5686 /* cpssda1.b $crqp,$crpp */
5687   {
5688     MEP_INSN_CPSSDA1_B_P1, "cpssda1_b_P1", "cpssda1.b", 32,
5689     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
5690   },
5691 /* cpmula1u.b $crqp,$crpp */
5692   {
5693     MEP_INSN_CPMULA1U_B_P1, "cpmula1u_b_P1", "cpmula1u.b", 32,
5694     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
5695   },
5696 /* cpmula1.b $crqp,$crpp */
5697   {
5698     MEP_INSN_CPMULA1_B_P1, "cpmula1_b_P1", "cpmula1.b", 32,
5699     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
5700   },
5701 /* cpmulua1.h $crqp,$crpp */
5702   {
5703     MEP_INSN_CPMULUA1_H_P1, "cpmulua1_h_P1", "cpmulua1.h", 32,
5704     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
5705   },
5706 /* cpmulla1.h $crqp,$crpp */
5707   {
5708     MEP_INSN_CPMULLA1_H_P1, "cpmulla1_h_P1", "cpmulla1.h", 32,
5709     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
5710   },
5711 /* cpmulua1u.w $crqp,$crpp */
5712   {
5713     MEP_INSN_CPMULUA1U_W_P1, "cpmulua1u_w_P1", "cpmulua1u.w", 32,
5714     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
5715   },
5716 /* cpmulla1u.w $crqp,$crpp */
5717   {
5718     MEP_INSN_CPMULLA1U_W_P1, "cpmulla1u_w_P1", "cpmulla1u.w", 32,
5719     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
5720   },
5721 /* cpmulua1.w $crqp,$crpp */
5722   {
5723     MEP_INSN_CPMULUA1_W_P1, "cpmulua1_w_P1", "cpmulua1.w", 32,
5724     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
5725   },
5726 /* cpmulla1.w $crqp,$crpp */
5727   {
5728     MEP_INSN_CPMULLA1_W_P1, "cpmulla1_w_P1", "cpmulla1.w", 32,
5729     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
5730   },
5731 /* cpmada1u.b $crqp,$crpp */
5732   {
5733     MEP_INSN_CPMADA1U_B_P1, "cpmada1u_b_P1", "cpmada1u.b", 32,
5734     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
5735   },
5736 /* cpmada1.b $crqp,$crpp */
5737   {
5738     MEP_INSN_CPMADA1_B_P1, "cpmada1_b_P1", "cpmada1.b", 32,
5739     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
5740   },
5741 /* cpmadua1.h $crqp,$crpp */
5742   {
5743     MEP_INSN_CPMADUA1_H_P1, "cpmadua1_h_P1", "cpmadua1.h", 32,
5744     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
5745   },
5746 /* cpmadla1.h $crqp,$crpp */
5747   {
5748     MEP_INSN_CPMADLA1_H_P1, "cpmadla1_h_P1", "cpmadla1.h", 32,
5749     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
5750   },
5751 /* cpmadua1u.w $crqp,$crpp */
5752   {
5753     MEP_INSN_CPMADUA1U_W_P1, "cpmadua1u_w_P1", "cpmadua1u.w", 32,
5754     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
5755   },
5756 /* cpmadla1u.w $crqp,$crpp */
5757   {
5758     MEP_INSN_CPMADLA1U_W_P1, "cpmadla1u_w_P1", "cpmadla1u.w", 32,
5759     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
5760   },
5761 /* cpmadua1.w $crqp,$crpp */
5762   {
5763     MEP_INSN_CPMADUA1_W_P1, "cpmadua1_w_P1", "cpmadua1.w", 32,
5764     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
5765   },
5766 /* cpmadla1.w $crqp,$crpp */
5767   {
5768     MEP_INSN_CPMADLA1_W_P1, "cpmadla1_w_P1", "cpmadla1.w", 32,
5769     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
5770   },
5771 /* cpmsbua1.h $crqp,$crpp */
5772   {
5773     MEP_INSN_CPMSBUA1_H_P1, "cpmsbua1_h_P1", "cpmsbua1.h", 32,
5774     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
5775   },
5776 /* cpmsbla1.h $crqp,$crpp */
5777   {
5778     MEP_INSN_CPMSBLA1_H_P1, "cpmsbla1_h_P1", "cpmsbla1.h", 32,
5779     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
5780   },
5781 /* cpmsbua1u.w $crqp,$crpp */
5782   {
5783     MEP_INSN_CPMSBUA1U_W_P1, "cpmsbua1u_w_P1", "cpmsbua1u.w", 32,
5784     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
5785   },
5786 /* cpmsbla1u.w $crqp,$crpp */
5787   {
5788     MEP_INSN_CPMSBLA1U_W_P1, "cpmsbla1u_w_P1", "cpmsbla1u.w", 32,
5789     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
5790   },
5791 /* cpmsbua1.w $crqp,$crpp */
5792   {
5793     MEP_INSN_CPMSBUA1_W_P1, "cpmsbua1_w_P1", "cpmsbua1.w", 32,
5794     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
5795   },
5796 /* cpmsbla1.w $crqp,$crpp */
5797   {
5798     MEP_INSN_CPMSBLA1_W_P1, "cpmsbla1_w_P1", "cpmsbla1.w", 32,
5799     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
5800   },
5801 /* cpsmadua1.h $crqp,$crpp */
5802   {
5803     MEP_INSN_CPSMADUA1_H_P1, "cpsmadua1_h_P1", "cpsmadua1.h", 32,
5804     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
5805   },
5806 /* cpsmadla1.h $crqp,$crpp */
5807   {
5808     MEP_INSN_CPSMADLA1_H_P1, "cpsmadla1_h_P1", "cpsmadla1.h", 32,
5809     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
5810   },
5811 /* cpsmadua1.w $crqp,$crpp */
5812   {
5813     MEP_INSN_CPSMADUA1_W_P1, "cpsmadua1_w_P1", "cpsmadua1.w", 32,
5814     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
5815   },
5816 /* cpsmadla1.w $crqp,$crpp */
5817   {
5818     MEP_INSN_CPSMADLA1_W_P1, "cpsmadla1_w_P1", "cpsmadla1.w", 32,
5819     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
5820   },
5821 /* cpsmsbua1.h $crqp,$crpp */
5822   {
5823     MEP_INSN_CPSMSBUA1_H_P1, "cpsmsbua1_h_P1", "cpsmsbua1.h", 32,
5824     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
5825   },
5826 /* cpsmsbla1.h $crqp,$crpp */
5827   {
5828     MEP_INSN_CPSMSBLA1_H_P1, "cpsmsbla1_h_P1", "cpsmsbla1.h", 32,
5829     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
5830   },
5831 /* cpsmsbua1.w $crqp,$crpp */
5832   {
5833     MEP_INSN_CPSMSBUA1_W_P1, "cpsmsbua1_w_P1", "cpsmsbua1.w", 32,
5834     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
5835   },
5836 /* cpsmsbla1.w $crqp,$crpp */
5837   {
5838     MEP_INSN_CPSMSBLA1_W_P1, "cpsmsbla1_w_P1", "cpsmsbla1.w", 32,
5839     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
5840   },
5841 /* cpmulslua1.h $crqp,$crpp */
5842   {
5843     MEP_INSN_CPMULSLUA1_H_P1, "cpmulslua1_h_P1", "cpmulslua1.h", 32,
5844     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
5845   },
5846 /* cpmulslla1.h $crqp,$crpp */
5847   {
5848     MEP_INSN_CPMULSLLA1_H_P1, "cpmulslla1_h_P1", "cpmulslla1.h", 32,
5849     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
5850   },
5851 /* cpmulslua1.w $crqp,$crpp */
5852   {
5853     MEP_INSN_CPMULSLUA1_W_P1, "cpmulslua1_w_P1", "cpmulslua1.w", 32,
5854     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
5855   },
5856 /* cpmulslla1.w $crqp,$crpp */
5857   {
5858     MEP_INSN_CPMULSLLA1_W_P1, "cpmulslla1_w_P1", "cpmulslla1.w", 32,
5859     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
5860   },
5861 /* cpsmadslua1.h $crqp,$crpp */
5862   {
5863     MEP_INSN_CPSMADSLUA1_H_P1, "cpsmadslua1_h_P1", "cpsmadslua1.h", 32,
5864     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
5865   },
5866 /* cpsmadslla1.h $crqp,$crpp */
5867   {
5868     MEP_INSN_CPSMADSLLA1_H_P1, "cpsmadslla1_h_P1", "cpsmadslla1.h", 32,
5869     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
5870   },
5871 /* cpsmadslua1.w $crqp,$crpp */
5872   {
5873     MEP_INSN_CPSMADSLUA1_W_P1, "cpsmadslua1_w_P1", "cpsmadslua1.w", 32,
5874     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
5875   },
5876 /* cpsmadslla1.w $crqp,$crpp */
5877   {
5878     MEP_INSN_CPSMADSLLA1_W_P1, "cpsmadslla1_w_P1", "cpsmadslla1.w", 32,
5879     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
5880   },
5881 /* cpsmsbslua1.h $crqp,$crpp */
5882   {
5883     MEP_INSN_CPSMSBSLUA1_H_P1, "cpsmsbslua1_h_P1", "cpsmsbslua1.h", 32,
5884     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
5885   },
5886 /* cpsmsbslla1.h $crqp,$crpp */
5887   {
5888     MEP_INSN_CPSMSBSLLA1_H_P1, "cpsmsbslla1_h_P1", "cpsmsbslla1.h", 32,
5889     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
5890   },
5891 /* cpsmsbslua1.w $crqp,$crpp */
5892   {
5893     MEP_INSN_CPSMSBSLUA1_W_P1, "cpsmsbslua1_w_P1", "cpsmsbslua1.w", 32,
5894     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
5895   },
5896 /* cpsmsbslla1.w $crqp,$crpp */
5897   {
5898     MEP_INSN_CPSMSBSLLA1_W_P1, "cpsmsbslla1_w_P1", "cpsmsbslla1.w", 32,
5899     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
5900   },
5901 };
5902
5903 #undef OP
5904 #undef A
5905
5906 /* Initialize anything needed to be done once, before any cpu_open call.  */
5907
5908 static void
5909 init_tables (void)
5910 {
5911 }
5912
5913 static const CGEN_MACH * lookup_mach_via_bfd_name (const CGEN_MACH *, const char *);
5914 static void build_hw_table      (CGEN_CPU_TABLE *);
5915 static void build_ifield_table  (CGEN_CPU_TABLE *);
5916 static void build_operand_table (CGEN_CPU_TABLE *);
5917 static void build_insn_table    (CGEN_CPU_TABLE *);
5918 static void mep_cgen_rebuild_tables (CGEN_CPU_TABLE *);
5919
5920 /* Subroutine of mep_cgen_cpu_open to look up a mach via its bfd name.  */
5921
5922 static const CGEN_MACH *
5923 lookup_mach_via_bfd_name (const CGEN_MACH *table, const char *name)
5924 {
5925   while (table->name)
5926     {
5927       if (strcmp (name, table->bfd_name) == 0)
5928         return table;
5929       ++table;
5930     }
5931   abort ();
5932 }
5933
5934 /* Subroutine of mep_cgen_cpu_open to build the hardware table.  */
5935
5936 static void
5937 build_hw_table (CGEN_CPU_TABLE *cd)
5938 {
5939   int i;
5940   int machs = cd->machs;
5941   const CGEN_HW_ENTRY *init = & mep_cgen_hw_table[0];
5942   /* MAX_HW is only an upper bound on the number of selected entries.
5943      However each entry is indexed by it's enum so there can be holes in
5944      the table.  */
5945   const CGEN_HW_ENTRY **selected =
5946     (const CGEN_HW_ENTRY **) xmalloc (MAX_HW * sizeof (CGEN_HW_ENTRY *));
5947
5948   cd->hw_table.init_entries = init;
5949   cd->hw_table.entry_size = sizeof (CGEN_HW_ENTRY);
5950   memset (selected, 0, MAX_HW * sizeof (CGEN_HW_ENTRY *));
5951   /* ??? For now we just use machs to determine which ones we want.  */
5952   for (i = 0; init[i].name != NULL; ++i)
5953     if (CGEN_HW_ATTR_VALUE (&init[i], CGEN_HW_MACH)
5954         & machs)
5955       selected[init[i].type] = &init[i];
5956   cd->hw_table.entries = selected;
5957   cd->hw_table.num_entries = MAX_HW;
5958 }
5959
5960 /* Subroutine of mep_cgen_cpu_open to build the hardware table.  */
5961
5962 static void
5963 build_ifield_table (CGEN_CPU_TABLE *cd)
5964 {
5965   cd->ifld_table = & mep_cgen_ifld_table[0];
5966 }
5967
5968 /* Subroutine of mep_cgen_cpu_open to build the hardware table.  */
5969
5970 static void
5971 build_operand_table (CGEN_CPU_TABLE *cd)
5972 {
5973   int i;
5974   int machs = cd->machs;
5975   const CGEN_OPERAND *init = & mep_cgen_operand_table[0];
5976   /* MAX_OPERANDS is only an upper bound on the number of selected entries.
5977      However each entry is indexed by it's enum so there can be holes in
5978      the table.  */
5979   const CGEN_OPERAND **selected = xmalloc (MAX_OPERANDS * sizeof (* selected));
5980
5981   cd->operand_table.init_entries = init;
5982   cd->operand_table.entry_size = sizeof (CGEN_OPERAND);
5983   memset (selected, 0, MAX_OPERANDS * sizeof (CGEN_OPERAND *));
5984   /* ??? For now we just use mach to determine which ones we want.  */
5985   for (i = 0; init[i].name != NULL; ++i)
5986     if (CGEN_OPERAND_ATTR_VALUE (&init[i], CGEN_OPERAND_MACH)
5987         & machs)
5988       selected[init[i].type] = &init[i];
5989   cd->operand_table.entries = selected;
5990   cd->operand_table.num_entries = MAX_OPERANDS;
5991 }
5992
5993 /* Subroutine of mep_cgen_cpu_open to build the hardware table.
5994    ??? This could leave out insns not supported by the specified mach/isa,
5995    but that would cause errors like "foo only supported by bar" to become
5996    "unknown insn", so for now we include all insns and require the app to
5997    do the checking later.
5998    ??? On the other hand, parsing of such insns may require their hardware or
5999    operand elements to be in the table [which they mightn't be].  */
6000
6001 static void
6002 build_insn_table (CGEN_CPU_TABLE *cd)
6003 {
6004   int i;
6005   const CGEN_IBASE *ib = & mep_cgen_insn_table[0];
6006   CGEN_INSN *insns = xmalloc (MAX_INSNS * sizeof (CGEN_INSN));
6007
6008   memset (insns, 0, MAX_INSNS * sizeof (CGEN_INSN));
6009   for (i = 0; i < MAX_INSNS; ++i)
6010     insns[i].base = &ib[i];
6011   cd->insn_table.init_entries = insns;
6012   cd->insn_table.entry_size = sizeof (CGEN_IBASE);
6013   cd->insn_table.num_init_entries = MAX_INSNS;
6014 }
6015
6016 /* Subroutine of mep_cgen_cpu_open to rebuild the tables.  */
6017
6018 static void
6019 mep_cgen_rebuild_tables (CGEN_CPU_TABLE *cd)
6020 {
6021   int i;
6022   CGEN_BITSET *isas = cd->isas;
6023   unsigned int machs = cd->machs;
6024
6025   cd->int_insn_p = CGEN_INT_INSN_P;
6026
6027   /* Data derived from the isa spec.  */
6028 #define UNSET (CGEN_SIZE_UNKNOWN + 1)
6029   cd->default_insn_bitsize = UNSET;
6030   cd->base_insn_bitsize = UNSET;
6031   cd->min_insn_bitsize = 65535; /* Some ridiculously big number.  */
6032   cd->max_insn_bitsize = 0;
6033   for (i = 0; i < MAX_ISAS; ++i)
6034     if (cgen_bitset_contains (isas, i))
6035       {
6036         const CGEN_ISA *isa = & mep_cgen_isa_table[i];
6037
6038         /* Default insn sizes of all selected isas must be
6039            equal or we set the result to 0, meaning "unknown".  */
6040         if (cd->default_insn_bitsize == UNSET)
6041           cd->default_insn_bitsize = isa->default_insn_bitsize;
6042         else if (isa->default_insn_bitsize == cd->default_insn_bitsize)
6043           ; /* This is ok.  */
6044         else
6045           cd->default_insn_bitsize = CGEN_SIZE_UNKNOWN;
6046
6047         /* Base insn sizes of all selected isas must be equal
6048            or we set the result to 0, meaning "unknown".  */
6049         if (cd->base_insn_bitsize == UNSET)
6050           cd->base_insn_bitsize = isa->base_insn_bitsize;
6051         else if (isa->base_insn_bitsize == cd->base_insn_bitsize)
6052           ; /* This is ok.  */
6053         else
6054           cd->base_insn_bitsize = CGEN_SIZE_UNKNOWN;
6055
6056         /* Set min,max insn sizes.  */
6057         if (isa->min_insn_bitsize < cd->min_insn_bitsize)
6058           cd->min_insn_bitsize = isa->min_insn_bitsize;
6059         if (isa->max_insn_bitsize > cd->max_insn_bitsize)
6060           cd->max_insn_bitsize = isa->max_insn_bitsize;
6061       }
6062
6063   /* Data derived from the mach spec.  */
6064   for (i = 0; i < MAX_MACHS; ++i)
6065     if (((1 << i) & machs) != 0)
6066       {
6067         const CGEN_MACH *mach = & mep_cgen_mach_table[i];
6068
6069         if (mach->insn_chunk_bitsize != 0)
6070         {
6071           if (cd->insn_chunk_bitsize != 0 && cd->insn_chunk_bitsize != mach->insn_chunk_bitsize)
6072             {
6073               fprintf (stderr, "mep_cgen_rebuild_tables: conflicting insn-chunk-bitsize values: `%d' vs. `%d'\n",
6074                        cd->insn_chunk_bitsize, mach->insn_chunk_bitsize);
6075               abort ();
6076             }
6077
6078           cd->insn_chunk_bitsize = mach->insn_chunk_bitsize;
6079         }
6080       }
6081
6082   /* Determine which hw elements are used by MACH.  */
6083   build_hw_table (cd);
6084
6085   /* Build the ifield table.  */
6086   build_ifield_table (cd);
6087
6088   /* Determine which operands are used by MACH/ISA.  */
6089   build_operand_table (cd);
6090
6091   /* Build the instruction table.  */
6092   build_insn_table (cd);
6093 }
6094
6095 /* Initialize a cpu table and return a descriptor.
6096    It's much like opening a file, and must be the first function called.
6097    The arguments are a set of (type/value) pairs, terminated with
6098    CGEN_CPU_OPEN_END.
6099
6100    Currently supported values:
6101    CGEN_CPU_OPEN_ISAS:    bitmap of values in enum isa_attr
6102    CGEN_CPU_OPEN_MACHS:   bitmap of values in enum mach_attr
6103    CGEN_CPU_OPEN_BFDMACH: specify 1 mach using bfd name
6104    CGEN_CPU_OPEN_ENDIAN:  specify endian choice
6105    CGEN_CPU_OPEN_END:     terminates arguments
6106
6107    ??? Simultaneous multiple isas might not make sense, but it's not (yet)
6108    precluded.
6109
6110    ??? We only support ISO C stdargs here, not K&R.
6111    Laziness, plus experiment to see if anything requires K&R - eventually
6112    K&R will no longer be supported - e.g. GDB is currently trying this.  */
6113
6114 CGEN_CPU_DESC
6115 mep_cgen_cpu_open (enum cgen_cpu_open_arg arg_type, ...)
6116 {
6117   CGEN_CPU_TABLE *cd = (CGEN_CPU_TABLE *) xmalloc (sizeof (CGEN_CPU_TABLE));
6118   static int init_p;
6119   CGEN_BITSET *isas = 0;  /* 0 = "unspecified" */
6120   unsigned int machs = 0; /* 0 = "unspecified" */
6121   enum cgen_endian endian = CGEN_ENDIAN_UNKNOWN;
6122   va_list ap;
6123
6124   if (! init_p)
6125     {
6126       init_tables ();
6127       init_p = 1;
6128     }
6129
6130   memset (cd, 0, sizeof (*cd));
6131
6132   va_start (ap, arg_type);
6133   while (arg_type != CGEN_CPU_OPEN_END)
6134     {
6135       switch (arg_type)
6136         {
6137         case CGEN_CPU_OPEN_ISAS :
6138           isas = va_arg (ap, CGEN_BITSET *);
6139           break;
6140         case CGEN_CPU_OPEN_MACHS :
6141           machs = va_arg (ap, unsigned int);
6142           break;
6143         case CGEN_CPU_OPEN_BFDMACH :
6144           {
6145             const char *name = va_arg (ap, const char *);
6146             const CGEN_MACH *mach =
6147               lookup_mach_via_bfd_name (mep_cgen_mach_table, name);
6148
6149             machs |= 1 << mach->num;
6150             break;
6151           }
6152         case CGEN_CPU_OPEN_ENDIAN :
6153           endian = va_arg (ap, enum cgen_endian);
6154           break;
6155         default :
6156           fprintf (stderr, "mep_cgen_cpu_open: unsupported argument `%d'\n",
6157                    arg_type);
6158           abort (); /* ??? return NULL? */
6159         }
6160       arg_type = va_arg (ap, enum cgen_cpu_open_arg);
6161     }
6162   va_end (ap);
6163
6164   /* Mach unspecified means "all".  */
6165   if (machs == 0)
6166     machs = (1 << MAX_MACHS) - 1;
6167   /* Base mach is always selected.  */
6168   machs |= 1;
6169   if (endian == CGEN_ENDIAN_UNKNOWN)
6170     {
6171       /* ??? If target has only one, could have a default.  */
6172       fprintf (stderr, "mep_cgen_cpu_open: no endianness specified\n");
6173       abort ();
6174     }
6175
6176   cd->isas = cgen_bitset_copy (isas);
6177   cd->machs = machs;
6178   cd->endian = endian;
6179   /* FIXME: for the sparc case we can determine insn-endianness statically.
6180      The worry here is where both data and insn endian can be independently
6181      chosen, in which case this function will need another argument.
6182      Actually, will want to allow for more arguments in the future anyway.  */
6183   cd->insn_endian = endian;
6184
6185   /* Table (re)builder.  */
6186   cd->rebuild_tables = mep_cgen_rebuild_tables;
6187   mep_cgen_rebuild_tables (cd);
6188
6189   /* Default to not allowing signed overflow.  */
6190   cd->signed_overflow_ok_p = 0;
6191
6192   return (CGEN_CPU_DESC) cd;
6193 }
6194
6195 /* Cover fn to mep_cgen_cpu_open to handle the simple case of 1 isa, 1 mach.
6196    MACH_NAME is the bfd name of the mach.  */
6197
6198 CGEN_CPU_DESC
6199 mep_cgen_cpu_open_1 (const char *mach_name, enum cgen_endian endian)
6200 {
6201   return mep_cgen_cpu_open (CGEN_CPU_OPEN_BFDMACH, mach_name,
6202                                CGEN_CPU_OPEN_ENDIAN, endian,
6203                                CGEN_CPU_OPEN_END);
6204 }
6205
6206 /* Close a cpu table.
6207    ??? This can live in a machine independent file, but there's currently
6208    no place to put this file (there's no libcgen).  libopcodes is the wrong
6209    place as some simulator ports use this but they don't use libopcodes.  */
6210
6211 void
6212 mep_cgen_cpu_close (CGEN_CPU_DESC cd)
6213 {
6214   unsigned int i;
6215   const CGEN_INSN *insns;
6216
6217   if (cd->macro_insn_table.init_entries)
6218     {
6219       insns = cd->macro_insn_table.init_entries;
6220       for (i = 0; i < cd->macro_insn_table.num_init_entries; ++i, ++insns)
6221         if (CGEN_INSN_RX ((insns)))
6222           regfree (CGEN_INSN_RX (insns));
6223     }
6224
6225   if (cd->insn_table.init_entries)
6226     {
6227       insns = cd->insn_table.init_entries;
6228       for (i = 0; i < cd->insn_table.num_init_entries; ++i, ++insns)
6229         if (CGEN_INSN_RX (insns))
6230           regfree (CGEN_INSN_RX (insns));
6231     }
6232
6233   if (cd->macro_insn_table.init_entries)
6234     free ((CGEN_INSN *) cd->macro_insn_table.init_entries);
6235
6236   if (cd->insn_table.init_entries)
6237     free ((CGEN_INSN *) cd->insn_table.init_entries);
6238
6239   if (cd->hw_table.entries)
6240     free ((CGEN_HW_ENTRY *) cd->hw_table.entries);
6241
6242   if (cd->operand_table.entries)
6243     free ((CGEN_HW_ENTRY *) cd->operand_table.entries);
6244
6245   free (cd);
6246 }
6247