opcodes/mep-desc.c

   1 /* CPU data for mep.
   2
   3 THIS FILE IS MACHINE GENERATED WITH CGEN.
   4
   5 Copyright 1996-2007 Free Software Foundation, Inc.
   6
   7 This file is part of the GNU Binutils and/or GDB, the GNU debugger.
   8
   9    This file is free software; you can redistribute it and/or modify
  10    it under the terms of the GNU General Public License as published by
  11    the Free Software Foundation; either version 3, or (at your option)
  12    any later version.
  13
  14    It is distributed in the hope that it will be useful, but WITHOUT
  15    ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  16    or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
  17    License for more details.
  18
  19    You should have received a copy of the GNU General Public License along
  20    with this program; if not, write to the Free Software Foundation, Inc.,
  21    51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
  22
  23 */
  24
  25 #include "sysdep.h"
  26 #include <stdio.h>
  27 #include <stdarg.h>
  28 #include "ansidecl.h"
  29 #include "bfd.h"
  30 #include "symcat.h"
  31 #include "mep-desc.h"
  32 #include "mep-opc.h"
  33 #include "opintl.h"
  34 #include "libiberty.h"
  35 #include "xregex.h"
  36
  37 /* Attributes.  */
  38
  39 static const CGEN_ATTR_ENTRY bool_attr[] =
  40 {
  41   { "#f", 0 },
  42   { "#t", 1 },
  43   { 0, 0 }
  44 };
  45
  46 static const CGEN_ATTR_ENTRY MACH_attr[] ATTRIBUTE_UNUSED =
  47 {
  48   { "base", MACH_BASE },
  49   { "mep", MACH_MEP },
  50   { "h1", MACH_H1 },
  51   { "max", MACH_MAX },
  52   { 0, 0 }
  53 };
  54
  55 static const CGEN_ATTR_ENTRY ISA_attr[] ATTRIBUTE_UNUSED =
  56 {
  57   { "mep", ISA_MEP },
  58   { "ext_core1", ISA_EXT_CORE1 },
  59   { "max", ISA_MAX },
  60   { 0, 0 }
  61 };
  62
  63 static const CGEN_ATTR_ENTRY CDATA_attr[] ATTRIBUTE_UNUSED =
  64 {
  65   { "LABEL", CDATA_LABEL },
  66   { "REGNUM", CDATA_REGNUM },
  67   { "FMAX_FLOAT", CDATA_FMAX_FLOAT },
  68   { "FMAX_INT", CDATA_FMAX_INT },
  69   { "POINTER", CDATA_POINTER },
  70   { "LONG", CDATA_LONG },
  71   { "ULONG", CDATA_ULONG },
  72   { "SHORT", CDATA_SHORT },
  73   { "USHORT", CDATA_USHORT },
  74   { "CHAR", CDATA_CHAR },
  75   { "UCHAR", CDATA_UCHAR },
  76   { "CP_DATA_BUS_INT", CDATA_CP_DATA_BUS_INT },
  77   { 0, 0 }
  78 };
  79
  80 static const CGEN_ATTR_ENTRY ALIGN_attr [] ATTRIBUTE_UNUSED =
  81 {
  82   {"integer", 1},
  83   { 0, 0 }
  84 };
  85
  86 static const CGEN_ATTR_ENTRY LATENCY_attr [] ATTRIBUTE_UNUSED =
  87 {
  88   {"integer", 0},
  89   { 0, 0 }
  90 };
  91
  92 static const CGEN_ATTR_ENTRY CONFIG_attr[] ATTRIBUTE_UNUSED =
  93 {
  94   { "NONE", CONFIG_NONE },
  95   { "default", CONFIG_DEFAULT },
  96   { 0, 0 }
  97 };
  98
  99 const CGEN_ATTR_TABLE mep_cgen_ifield_attr_table[] =
 100 {
 101   { "MACH", & MACH_attr[0], & MACH_attr[0] },
 102   { "ISA", & ISA_attr[0], & ISA_attr[0] },
 103   { "VIRTUAL", &bool_attr[0], &bool_attr[0] },
 104   { "PCREL-ADDR", &bool_attr[0], &bool_attr[0] },
 105   { "ABS-ADDR", &bool_attr[0], &bool_attr[0] },
 106   { "RESERVED", &bool_attr[0], &bool_attr[0] },
 107   { "SIGN-OPT", &bool_attr[0], &bool_attr[0] },
 108   { "SIGNED", &bool_attr[0], &bool_attr[0] },
 109   { 0, 0, 0 }
 110 };
 111
 112 const CGEN_ATTR_TABLE mep_cgen_hardware_attr_table[] =
 113 {
 114   { "MACH", & MACH_attr[0], & MACH_attr[0] },
 115   { "ISA", & ISA_attr[0], & ISA_attr[0] },
 116   { "VIRTUAL", &bool_attr[0], &bool_attr[0] },
 117   { "CACHE-ADDR", &bool_attr[0], &bool_attr[0] },
 118   { "PC", &bool_attr[0], &bool_attr[0] },
 119   { "PROFILE", &bool_attr[0], &bool_attr[0] },
 120   { "IS_FLOAT", &bool_attr[0], &bool_attr[0] },
 121   { 0, 0, 0 }
 122 };
 123
 124 const CGEN_ATTR_TABLE mep_cgen_operand_attr_table[] =
 125 {
 126   { "MACH", & MACH_attr[0], & MACH_attr[0] },
 127   { "ISA", & ISA_attr[0], & ISA_attr[0] },
 128   { "CDATA", & CDATA_attr[0], & CDATA_attr[0] },
 129   { "ALIGN", & ALIGN_attr[0], & ALIGN_attr[0] },
 130   { "VIRTUAL", &bool_attr[0], &bool_attr[0] },
 131   { "PCREL-ADDR", &bool_attr[0], &bool_attr[0] },
 132   { "ABS-ADDR", &bool_attr[0], &bool_attr[0] },
 133   { "SIGN-OPT", &bool_attr[0], &bool_attr[0] },
 134   { "SIGNED", &bool_attr[0], &bool_attr[0] },
 135   { "NEGATIVE", &bool_attr[0], &bool_attr[0] },
 136   { "RELAX", &bool_attr[0], &bool_attr[0] },
 137   { "SEM-ONLY", &bool_attr[0], &bool_attr[0] },
 138   { "RELOC_IMPLIES_OVERFLOW", &bool_attr[0], &bool_attr[0] },
 139   { 0, 0, 0 }
 140 };
 141
 142 const CGEN_ATTR_TABLE mep_cgen_insn_attr_table[] =
 143 {
 144   { "MACH", & MACH_attr[0], & MACH_attr[0] },
 145   { "ISA", & ISA_attr[0], & ISA_attr[0] },
 146   { "LATENCY", & LATENCY_attr[0], & LATENCY_attr[0] },
 147   { "CONFIG", & CONFIG_attr[0], & CONFIG_attr[0] },
 148   { "ALIAS", &bool_attr[0], &bool_attr[0] },
 149   { "VIRTUAL", &bool_attr[0], &bool_attr[0] },
 150   { "UNCOND-CTI", &bool_attr[0], &bool_attr[0] },
 151   { "COND-CTI", &bool_attr[0], &bool_attr[0] },
 152   { "SKIP-CTI", &bool_attr[0], &bool_attr[0] },
 153   { "DELAY-SLOT", &bool_attr[0], &bool_attr[0] },
 154   { "RELAXABLE", &bool_attr[0], &bool_attr[0] },
 155   { "RELAXED", &bool_attr[0], &bool_attr[0] },
 156   { "NO-DIS", &bool_attr[0], &bool_attr[0] },
 157   { "PBB", &bool_attr[0], &bool_attr[0] },
 158   { "OPTIONAL_BIT_INSN", &bool_attr[0], &bool_attr[0] },
 159   { "OPTIONAL_MUL_INSN", &bool_attr[0], &bool_attr[0] },
 160   { "OPTIONAL_DIV_INSN", &bool_attr[0], &bool_attr[0] },
 161   { "OPTIONAL_DEBUG_INSN", &bool_attr[0], &bool_attr[0] },
 162   { "OPTIONAL_LDZ_INSN", &bool_attr[0], &bool_attr[0] },
 163   { "OPTIONAL_ABS_INSN", &bool_attr[0], &bool_attr[0] },
 164   { "OPTIONAL_AVE_INSN", &bool_attr[0], &bool_attr[0] },
 165   { "OPTIONAL_MINMAX_INSN", &bool_attr[0], &bool_attr[0] },
 166   { "OPTIONAL_CLIP_INSN", &bool_attr[0], &bool_attr[0] },
 167   { "OPTIONAL_SAT_INSN", &bool_attr[0], &bool_attr[0] },
 168   { "OPTIONAL_UCI_INSN", &bool_attr[0], &bool_attr[0] },
 169   { "OPTIONAL_DSP_INSN", &bool_attr[0], &bool_attr[0] },
 170   { "OPTIONAL_CP_INSN", &bool_attr[0], &bool_attr[0] },
 171   { "OPTIONAL_CP64_INSN", &bool_attr[0], &bool_attr[0] },
 172   { "OPTIONAL_VLIW64", &bool_attr[0], &bool_attr[0] },
 173   { "MAY_TRAP", &bool_attr[0], &bool_attr[0] },
 174   { "VLIW_ALONE", &bool_attr[0], &bool_attr[0] },
 175   { "VLIW_NO_CORE_NOP", &bool_attr[0], &bool_attr[0] },
 176   { "VLIW_NO_COP_NOP", &bool_attr[0], &bool_attr[0] },
 177   { "VLIW64_NO_MATCHING_NOP", &bool_attr[0], &bool_attr[0] },
 178   { "VLIW32_NO_MATCHING_NOP", &bool_attr[0], &bool_attr[0] },
 179   { "VOLATILE", &bool_attr[0], &bool_attr[0] },
 180   { 0, 0, 0 }
 181 };
 182
 183 /* Instruction set variants.  */
 184
 185 static const CGEN_ISA mep_cgen_isa_table[] = {
 186   { "mep", 32, 32, 16, 32 },
 187   { "ext_core1", 32, 32, 16, 32 },
 188   { 0, 0, 0, 0, 0 }
 189 };
 190
 191 /* Machine variants.  */
 192
 193 static const CGEN_MACH mep_cgen_mach_table[] = {
 194   { "mep", "mep", MACH_MEP, 16 },
 195   { "h1", "h1", MACH_H1, 16 },
 196   { 0, 0, 0, 0 }
 197 };
 198
 199 static CGEN_KEYWORD_ENTRY mep_cgen_opval_h_gpr_entries[] =
 200 {
 201   { "$0", 0, {0, {{{0, 0}}}}, 0, 0 },
 202   { "$1", 1, {0, {{{0, 0}}}}, 0, 0 },
 203   { "$2", 2, {0, {{{0, 0}}}}, 0, 0 },
 204   { "$3", 3, {0, {{{0, 0}}}}, 0, 0 },
 205   { "$4", 4, {0, {{{0, 0}}}}, 0, 0 },
 206   { "$5", 5, {0, {{{0, 0}}}}, 0, 0 },
 207   { "$6", 6, {0, {{{0, 0}}}}, 0, 0 },
 208   { "$7", 7, {0, {{{0, 0}}}}, 0, 0 },
 209   { "$8", 8, {0, {{{0, 0}}}}, 0, 0 },
 210   { "$9", 9, {0, {{{0, 0}}}}, 0, 0 },
 211   { "$10", 10, {0, {{{0, 0}}}}, 0, 0 },
 212   { "$11", 11, {0, {{{0, 0}}}}, 0, 0 },
 213   { "$fp", 8, {0, {{{0, 0}}}}, 0, 0 },
 214   { "$tp", 13, {0, {{{0, 0}}}}, 0, 0 },
 215   { "$gp", 14, {0, {{{0, 0}}}}, 0, 0 },
 216   { "$sp", 15, {0, {{{0, 0}}}}, 0, 0 },
 217   { "$12", 12, {0, {{{0, 0}}}}, 0, 0 },
 218   { "$13", 13, {0, {{{0, 0}}}}, 0, 0 },
 219   { "$14", 14, {0, {{{0, 0}}}}, 0, 0 },
 220   { "$15", 15, {0, {{{0, 0}}}}, 0, 0 }
 221 };
 222
 223 CGEN_KEYWORD mep_cgen_opval_h_gpr =
 224 {
 225   & mep_cgen_opval_h_gpr_entries[0],
 226   20,
 227   0, 0, 0, 0, ""
 228 };
 229
 230 static CGEN_KEYWORD_ENTRY mep_cgen_opval_h_csr_entries[] =
 231 {
 232   { "$pc", 0, {0, {{{0, 0}}}}, 0, 0 },
 233   { "$lp", 1, {0, {{{0, 0}}}}, 0, 0 },
 234   { "$sar", 2, {0, {{{0, 0}}}}, 0, 0 },
 235   { "$rpb", 4, {0, {{{0, 0}}}}, 0, 0 },
 236   { "$rpe", 5, {0, {{{0, 0}}}}, 0, 0 },
 237   { "$rpc", 6, {0, {{{0, 0}}}}, 0, 0 },
 238   { "$hi", 7, {0, {{{0, 0}}}}, 0, 0 },
 239   { "$lo", 8, {0, {{{0, 0}}}}, 0, 0 },
 240   { "$mb0", 12, {0, {{{0, 0}}}}, 0, 0 },
 241   { "$me0", 13, {0, {{{0, 0}}}}, 0, 0 },
 242   { "$mb1", 14, {0, {{{0, 0}}}}, 0, 0 },
 243   { "$me1", 15, {0, {{{0, 0}}}}, 0, 0 },
 244   { "$psw", 16, {0, {{{0, 0}}}}, 0, 0 },
 245   { "$id", 17, {0, {{{0, 0}}}}, 0, 0 },
 246   { "$tmp", 18, {0, {{{0, 0}}}}, 0, 0 },
 247   { "$epc", 19, {0, {{{0, 0}}}}, 0, 0 },
 248   { "$exc", 20, {0, {{{0, 0}}}}, 0, 0 },
 249   { "$cfg", 21, {0, {{{0, 0}}}}, 0, 0 },
 250   { "$npc", 23, {0, {{{0, 0}}}}, 0, 0 },
 251   { "$dbg", 24, {0, {{{0, 0}}}}, 0, 0 },
 252   { "$depc", 25, {0, {{{0, 0}}}}, 0, 0 },
 253   { "$opt", 26, {0, {{{0, 0}}}}, 0, 0 },
 254   { "$rcfg", 27, {0, {{{0, 0}}}}, 0, 0 },
 255   { "$ccfg", 28, {0, {{{0, 0}}}}, 0, 0 },
 256   { "$vid", 22, {0, {{{0, 0}}}}, 0, 0 }
 257 };
 258
 259 CGEN_KEYWORD mep_cgen_opval_h_csr =
 260 {
 261   & mep_cgen_opval_h_csr_entries[0],
 262   25,
 263   0, 0, 0, 0, ""
 264 };
 265
 266 static CGEN_KEYWORD_ENTRY mep_cgen_opval_h_cr64_entries[] =
 267 {
 268   { "$c0", 0, {0, {{{0, 0}}}}, 0, 0 },
 269   { "$c1", 1, {0, {{{0, 0}}}}, 0, 0 },
 270   { "$c2", 2, {0, {{{0, 0}}}}, 0, 0 },
 271   { "$c3", 3, {0, {{{0, 0}}}}, 0, 0 },
 272   { "$c4", 4, {0, {{{0, 0}}}}, 0, 0 },
 273   { "$c5", 5, {0, {{{0, 0}}}}, 0, 0 },
 274   { "$c6", 6, {0, {{{0, 0}}}}, 0, 0 },
 275   { "$c7", 7, {0, {{{0, 0}}}}, 0, 0 },
 276   { "$c8", 8, {0, {{{0, 0}}}}, 0, 0 },
 277   { "$c9", 9, {0, {{{0, 0}}}}, 0, 0 },
 278   { "$c10", 10, {0, {{{0, 0}}}}, 0, 0 },
 279   { "$c11", 11, {0, {{{0, 0}}}}, 0, 0 },
 280   { "$c12", 12, {0, {{{0, 0}}}}, 0, 0 },
 281   { "$c13", 13, {0, {{{0, 0}}}}, 0, 0 },
 282   { "$c14", 14, {0, {{{0, 0}}}}, 0, 0 },
 283   { "$c15", 15, {0, {{{0, 0}}}}, 0, 0 },
 284   { "$c16", 16, {0, {{{0, 0}}}}, 0, 0 },
 285   { "$c17", 17, {0, {{{0, 0}}}}, 0, 0 },
 286   { "$c18", 18, {0, {{{0, 0}}}}, 0, 0 },
 287   { "$c19", 19, {0, {{{0, 0}}}}, 0, 0 },
 288   { "$c20", 20, {0, {{{0, 0}}}}, 0, 0 },
 289   { "$c21", 21, {0, {{{0, 0}}}}, 0, 0 },
 290   { "$c22", 22, {0, {{{0, 0}}}}, 0, 0 },
 291   { "$c23", 23, {0, {{{0, 0}}}}, 0, 0 },
 292   { "$c24", 24, {0, {{{0, 0}}}}, 0, 0 },
 293   { "$c25", 25, {0, {{{0, 0}}}}, 0, 0 },
 294   { "$c26", 26, {0, {{{0, 0}}}}, 0, 0 },
 295   { "$c27", 27, {0, {{{0, 0}}}}, 0, 0 },
 296   { "$c28", 28, {0, {{{0, 0}}}}, 0, 0 },
 297   { "$c29", 29, {0, {{{0, 0}}}}, 0, 0 },
 298   { "$c30", 30, {0, {{{0, 0}}}}, 0, 0 },
 299   { "$c31", 31, {0, {{{0, 0}}}}, 0, 0 }
 300 };
 301
 302 CGEN_KEYWORD mep_cgen_opval_h_cr64 =
 303 {
 304   & mep_cgen_opval_h_cr64_entries[0],
 305   32,
 306   0, 0, 0, 0, ""
 307 };
 308
 309 static CGEN_KEYWORD_ENTRY mep_cgen_opval_h_cr_entries[] =
 310 {
 311   { "$c0", 0, {0, {{{0, 0}}}}, 0, 0 },
 312   { "$c1", 1, {0, {{{0, 0}}}}, 0, 0 },
 313   { "$c2", 2, {0, {{{0, 0}}}}, 0, 0 },
 314   { "$c3", 3, {0, {{{0, 0}}}}, 0, 0 },
 315   { "$c4", 4, {0, {{{0, 0}}}}, 0, 0 },
 316   { "$c5", 5, {0, {{{0, 0}}}}, 0, 0 },
 317   { "$c6", 6, {0, {{{0, 0}}}}, 0, 0 },
 318   { "$c7", 7, {0, {{{0, 0}}}}, 0, 0 },
 319   { "$c8", 8, {0, {{{0, 0}}}}, 0, 0 },
 320   { "$c9", 9, {0, {{{0, 0}}}}, 0, 0 },
 321   { "$c10", 10, {0, {{{0, 0}}}}, 0, 0 },
 322   { "$c11", 11, {0, {{{0, 0}}}}, 0, 0 },
 323   { "$c12", 12, {0, {{{0, 0}}}}, 0, 0 },
 324   { "$c13", 13, {0, {{{0, 0}}}}, 0, 0 },
 325   { "$c14", 14, {0, {{{0, 0}}}}, 0, 0 },
 326   { "$c15", 15, {0, {{{0, 0}}}}, 0, 0 },
 327   { "$c16", 16, {0, {{{0, 0}}}}, 0, 0 },
 328   { "$c17", 17, {0, {{{0, 0}}}}, 0, 0 },
 329   { "$c18", 18, {0, {{{0, 0}}}}, 0, 0 },
 330   { "$c19", 19, {0, {{{0, 0}}}}, 0, 0 },
 331   { "$c20", 20, {0, {{{0, 0}}}}, 0, 0 },
 332   { "$c21", 21, {0, {{{0, 0}}}}, 0, 0 },
 333   { "$c22", 22, {0, {{{0, 0}}}}, 0, 0 },
 334   { "$c23", 23, {0, {{{0, 0}}}}, 0, 0 },
 335   { "$c24", 24, {0, {{{0, 0}}}}, 0, 0 },
 336   { "$c25", 25, {0, {{{0, 0}}}}, 0, 0 },
 337   { "$c26", 26, {0, {{{0, 0}}}}, 0, 0 },
 338   { "$c27", 27, {0, {{{0, 0}}}}, 0, 0 },
 339   { "$c28", 28, {0, {{{0, 0}}}}, 0, 0 },
 340   { "$c29", 29, {0, {{{0, 0}}}}, 0, 0 },
 341   { "$c30", 30, {0, {{{0, 0}}}}, 0, 0 },
 342   { "$c31", 31, {0, {{{0, 0}}}}, 0, 0 }
 343 };
 344
 345 CGEN_KEYWORD mep_cgen_opval_h_cr =
 346 {
 347   & mep_cgen_opval_h_cr_entries[0],
 348   32,
 349   0, 0, 0, 0, ""
 350 };
 351
 352 static CGEN_KEYWORD_ENTRY mep_cgen_opval_h_ccr_entries[] =
 353 {
 354   { "$ccr0", 0, {0, {{{0, 0}}}}, 0, 0 },
 355   { "$ccr1", 1, {0, {{{0, 0}}}}, 0, 0 },
 356   { "$ccr2", 2, {0, {{{0, 0}}}}, 0, 0 },
 357   { "$ccr3", 3, {0, {{{0, 0}}}}, 0, 0 },
 358   { "$ccr4", 4, {0, {{{0, 0}}}}, 0, 0 },
 359   { "$ccr5", 5, {0, {{{0, 0}}}}, 0, 0 },
 360   { "$ccr6", 6, {0, {{{0, 0}}}}, 0, 0 },
 361   { "$ccr7", 7, {0, {{{0, 0}}}}, 0, 0 },
 362   { "$ccr8", 8, {0, {{{0, 0}}}}, 0, 0 },
 363   { "$ccr9", 9, {0, {{{0, 0}}}}, 0, 0 },
 364   { "$ccr10", 10, {0, {{{0, 0}}}}, 0, 0 },
 365   { "$ccr11", 11, {0, {{{0, 0}}}}, 0, 0 },
 366   { "$ccr12", 12, {0, {{{0, 0}}}}, 0, 0 },
 367   { "$ccr13", 13, {0, {{{0, 0}}}}, 0, 0 },
 368   { "$ccr14", 14, {0, {{{0, 0}}}}, 0, 0 },
 369   { "$ccr15", 15, {0, {{{0, 0}}}}, 0, 0 },
 370   { "$ccr16", 16, {0, {{{0, 0}}}}, 0, 0 },
 371   { "$ccr17", 17, {0, {{{0, 0}}}}, 0, 0 },
 372   { "$ccr18", 18, {0, {{{0, 0}}}}, 0, 0 },
 373   { "$ccr19", 19, {0, {{{0, 0}}}}, 0, 0 },
 374   { "$ccr20", 20, {0, {{{0, 0}}}}, 0, 0 },
 375   { "$ccr21", 21, {0, {{{0, 0}}}}, 0, 0 },
 376   { "$ccr22", 22, {0, {{{0, 0}}}}, 0, 0 },
 377   { "$ccr23", 23, {0, {{{0, 0}}}}, 0, 0 },
 378   { "$ccr24", 24, {0, {{{0, 0}}}}, 0, 0 },
 379   { "$ccr25", 25, {0, {{{0, 0}}}}, 0, 0 },
 380   { "$ccr26", 26, {0, {{{0, 0}}}}, 0, 0 },
 381   { "$ccr27", 27, {0, {{{0, 0}}}}, 0, 0 },
 382   { "$ccr28", 28, {0, {{{0, 0}}}}, 0, 0 },
 383   { "$ccr29", 29, {0, {{{0, 0}}}}, 0, 0 },
 384   { "$ccr30", 30, {0, {{{0, 0}}}}, 0, 0 },
 385   { "$ccr31", 31, {0, {{{0, 0}}}}, 0, 0 },
 386   { "$ccr32", 32, {0, {{{0, 0}}}}, 0, 0 },
 387   { "$ccr33", 33, {0, {{{0, 0}}}}, 0, 0 },
 388   { "$ccr34", 34, {0, {{{0, 0}}}}, 0, 0 },
 389   { "$ccr35", 35, {0, {{{0, 0}}}}, 0, 0 },
 390   { "$ccr36", 36, {0, {{{0, 0}}}}, 0, 0 },
 391   { "$ccr37", 37, {0, {{{0, 0}}}}, 0, 0 },
 392   { "$ccr38", 38, {0, {{{0, 0}}}}, 0, 0 },
 393   { "$ccr39", 39, {0, {{{0, 0}}}}, 0, 0 },
 394   { "$ccr40", 40, {0, {{{0, 0}}}}, 0, 0 },
 395   { "$ccr41", 41, {0, {{{0, 0}}}}, 0, 0 },
 396   { "$ccr42", 42, {0, {{{0, 0}}}}, 0, 0 },
 397   { "$ccr43", 43, {0, {{{0, 0}}}}, 0, 0 },
 398   { "$ccr44", 44, {0, {{{0, 0}}}}, 0, 0 },
 399   { "$ccr45", 45, {0, {{{0, 0}}}}, 0, 0 },
 400   { "$ccr46", 46, {0, {{{0, 0}}}}, 0, 0 },
 401   { "$ccr47", 47, {0, {{{0, 0}}}}, 0, 0 },
 402   { "$ccr48", 48, {0, {{{0, 0}}}}, 0, 0 },
 403   { "$ccr49", 49, {0, {{{0, 0}}}}, 0, 0 },
 404   { "$ccr50", 50, {0, {{{0, 0}}}}, 0, 0 },
 405   { "$ccr51", 51, {0, {{{0, 0}}}}, 0, 0 },
 406   { "$ccr52", 52, {0, {{{0, 0}}}}, 0, 0 },
 407   { "$ccr53", 53, {0, {{{0, 0}}}}, 0, 0 },
 408   { "$ccr54", 54, {0, {{{0, 0}}}}, 0, 0 },
 409   { "$ccr55", 55, {0, {{{0, 0}}}}, 0, 0 },
 410   { "$ccr56", 56, {0, {{{0, 0}}}}, 0, 0 },
 411   { "$ccr57", 57, {0, {{{0, 0}}}}, 0, 0 },
 412   { "$ccr58", 58, {0, {{{0, 0}}}}, 0, 0 },
 413   { "$ccr59", 59, {0, {{{0, 0}}}}, 0, 0 },
 414   { "$ccr60", 60, {0, {{{0, 0}}}}, 0, 0 },
 415   { "$ccr61", 61, {0, {{{0, 0}}}}, 0, 0 },
 416   { "$ccr62", 62, {0, {{{0, 0}}}}, 0, 0 },
 417   { "$ccr63", 63, {0, {{{0, 0}}}}, 0, 0 }
 418 };
 419
 420 CGEN_KEYWORD mep_cgen_opval_h_ccr =
 421 {
 422   & mep_cgen_opval_h_ccr_entries[0],
 423   64,
 424   0, 0, 0, 0, ""
 425 };
 426
 427
 428 /* The hardware table.  */
 429
 430 #if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
 431 #define A(a) (1 << CGEN_HW_##a)
 432 #else
 433 #define A(a) (1 << CGEN_HW_/**/a)
 434 #endif
 435
 436 const CGEN_HW_ENTRY mep_cgen_hw_table[] =
 437 {
 438   { "h-memory", HW_H_MEMORY, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
 439   { "h-sint", HW_H_SINT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
 440   { "h-uint", HW_H_UINT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
 441   { "h-addr", HW_H_ADDR, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
 442   { "h-iaddr", HW_H_IADDR, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
 443   { "h-pc", HW_H_PC, CGEN_ASM_NONE, 0, { 0|A(PROFILE)|A(PC), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
 444   { "h-gpr", HW_H_GPR, CGEN_ASM_KEYWORD, (PTR) & mep_cgen_opval_h_gpr, { 0|A(PROFILE)|A(CACHE_ADDR), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
 445   { "h-csr", HW_H_CSR, CGEN_ASM_KEYWORD, (PTR) & mep_cgen_opval_h_csr, { 0|A(PROFILE), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
 446   { "h-cr64", HW_H_CR64, CGEN_ASM_KEYWORD, (PTR) & mep_cgen_opval_h_cr64, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
 447   { "h-cr", HW_H_CR, CGEN_ASM_KEYWORD, (PTR) & mep_cgen_opval_h_cr, { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
 448   { "h-ccr", HW_H_CCR, CGEN_ASM_KEYWORD, (PTR) & mep_cgen_opval_h_ccr, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
 449   { 0, 0, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }
 450 };
 451
 452 #undef A
 453
 454
 455 /* The instruction field table.  */
 456
 457 #if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
 458 #define A(a) (1 << CGEN_IFLD_##a)
 459 #else
 460 #define A(a) (1 << CGEN_IFLD_/**/a)
 461 #endif
 462
 463 const CGEN_IFLD mep_cgen_ifld_table[] =
 464 {
 465   { MEP_F_NIL, "f-nil", 0, 0, 0, 0, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }  },
 466   { MEP_F_ANYOF, "f-anyof", 0, 0, 0, 0, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }  },
 467   { MEP_F_MAJOR, "f-major", 0, 32, 0, 4, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }  },
 468   { MEP_F_RN, "f-rn", 0, 32, 4, 4, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }  },
 469   { MEP_F_RN3, "f-rn3", 0, 32, 5, 3, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }  },
 470   { MEP_F_RM, "f-rm", 0, 32, 8, 4, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }  },
 471   { MEP_F_RL, "f-rl", 0, 32, 12, 4, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }  },
 472   { MEP_F_SUB2, "f-sub2", 0, 32, 14, 2, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }  },
 473   { MEP_F_SUB3, "f-sub3", 0, 32, 13, 3, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }  },
 474   { MEP_F_SUB4, "f-sub4", 0, 32, 12, 4, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }  },
 475   { MEP_F_EXT, "f-ext", 0, 32, 16, 8, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }  },
 476   { MEP_F_CRN, "f-crn", 0, 32, 4, 4, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }  },
 477   { MEP_F_CSRN_HI, "f-csrn-hi", 0, 32, 15, 1, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }  },
 478   { MEP_F_CSRN_LO, "f-csrn-lo", 0, 32, 8, 4, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }  },
 479   { MEP_F_CSRN, "f-csrn", 0, 0, 0, 0,{ 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }  },
 480   { MEP_F_CRNX_HI, "f-crnx-hi", 0, 32, 28, 1, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }  },
 481   { MEP_F_CRNX_LO, "f-crnx-lo", 0, 32, 4, 4, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }  },
 482   { MEP_F_CRNX, "f-crnx", 0, 0, 0, 0,{ 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }  },
 483   { MEP_F_0, "f-0", 0, 32, 0, 1, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }  },
 484   { MEP_F_1, "f-1", 0, 32, 1, 1, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }  },
 485   { MEP_F_2, "f-2", 0, 32, 2, 1, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }  },
 486   { MEP_F_3, "f-3", 0, 32, 3, 1, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }  },
 487   { MEP_F_4, "f-4", 0, 32, 4, 1, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }  },
 488   { MEP_F_5, "f-5", 0, 32, 5, 1, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }  },
 489   { MEP_F_6, "f-6", 0, 32, 6, 1, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }  },
 490   { MEP_F_7, "f-7", 0, 32, 7, 1, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }  },
 491   { MEP_F_8, "f-8", 0, 32, 8, 1, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }  },
 492   { MEP_F_9, "f-9", 0, 32, 9, 1, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }  },
 493   { MEP_F_10, "f-10", 0, 32, 10, 1, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }  },
 494   { MEP_F_11, "f-11", 0, 32, 11, 1, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }  },
 495   { MEP_F_12, "f-12", 0, 32, 12, 1, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }  },
 496   { MEP_F_13, "f-13", 0, 32, 13, 1, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }  },
 497   { MEP_F_14, "f-14", 0, 32, 14, 1, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }  },
 498   { MEP_F_15, "f-15", 0, 32, 15, 1, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }  },
 499   { MEP_F_16, "f-16", 0, 32, 16, 1, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }  },
 500   { MEP_F_17, "f-17", 0, 32, 17, 1, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }  },
 501   { MEP_F_18, "f-18", 0, 32, 18, 1, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }  },
 502   { MEP_F_19, "f-19", 0, 32, 19, 1, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }  },
 503   { MEP_F_20, "f-20", 0, 32, 20, 1, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }  },
 504   { MEP_F_21, "f-21", 0, 32, 21, 1, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }  },
 505   { MEP_F_22, "f-22", 0, 32, 22, 1, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }  },
 506   { MEP_F_23, "f-23", 0, 32, 23, 1, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }  },
 507   { MEP_F_24, "f-24", 0, 32, 24, 1, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }  },
 508   { MEP_F_25, "f-25", 0, 32, 25, 1, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }  },
 509   { MEP_F_26, "f-26", 0, 32, 26, 1, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }  },
 510   { MEP_F_27, "f-27", 0, 32, 27, 1, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }  },
 511   { MEP_F_28, "f-28", 0, 32, 28, 1, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }  },
 512   { MEP_F_29, "f-29", 0, 32, 29, 1, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }  },
 513   { MEP_F_30, "f-30", 0, 32, 30, 1, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }  },
 514   { MEP_F_31, "f-31", 0, 32, 31, 1, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }  },
 515   { MEP_F_8S8A2, "f-8s8a2", 0, 32, 8, 7, { 0|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }  },
 516   { MEP_F_12S4A2, "f-12s4a2", 0, 32, 4, 11, { 0|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }  },
 517   { MEP_F_17S16A2, "f-17s16a2", 0, 32, 16, 16, { 0|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }  },
 518   { MEP_F_24S5A2N_HI, "f-24s5a2n-hi", 0, 32, 16, 16, { 0|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }  },
 519   { MEP_F_24S5A2N_LO, "f-24s5a2n-lo", 0, 32, 5, 7, { 0|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }  },
 520   { MEP_F_24S5A2N, "f-24s5a2n", 0, 0, 0, 0,{ 0|A(PCREL_ADDR)|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }  },
 521   { MEP_F_24U5A2N_HI, "f-24u5a2n-hi", 0, 32, 16, 16, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }  },
 522   { MEP_F_24U5A2N_LO, "f-24u5a2n-lo", 0, 32, 5, 7, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }  },
 523   { MEP_F_24U5A2N, "f-24u5a2n", 0, 0, 0, 0,{ 0|A(ABS_ADDR)|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }  },
 524   { MEP_F_2U6, "f-2u6", 0, 32, 6, 2, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }  },
 525   { MEP_F_7U9, "f-7u9", 0, 32, 9, 7, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }  },
 526   { MEP_F_7U9A2, "f-7u9a2", 0, 32, 9, 6, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }  },
 527   { MEP_F_7U9A4, "f-7u9a4", 0, 32, 9, 5, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }  },
 528   { MEP_F_16S16, "f-16s16", 0, 32, 16, 16, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }  },
 529   { MEP_F_2U10, "f-2u10", 0, 32, 10, 2, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }  },
 530   { MEP_F_3U5, "f-3u5", 0, 32, 5, 3, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }  },
 531   { MEP_F_4U8, "f-4u8", 0, 32, 8, 4, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }  },
 532   { MEP_F_5U8, "f-5u8", 0, 32, 8, 5, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }  },
 533   { MEP_F_5U24, "f-5u24", 0, 32, 24, 5, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }  },
 534   { MEP_F_6S8, "f-6s8", 0, 32, 8, 6, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }  },
 535   { MEP_F_8S8, "f-8s8", 0, 32, 8, 8, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }  },
 536   { MEP_F_16U16, "f-16u16", 0, 32, 16, 16, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }  },
 537   { MEP_F_12U16, "f-12u16", 0, 32, 16, 12, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }  },
 538   { MEP_F_3U29, "f-3u29", 0, 32, 29, 3, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }  },
 539   { MEP_F_8S24, "f-8s24", 0, 32, 24, 8, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }  },
 540   { MEP_F_8S24A2, "f-8s24a2", 0, 32, 24, 7, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }  },
 541   { MEP_F_8S24A4, "f-8s24a4", 0, 32, 24, 6, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }  },
 542   { MEP_F_8S24A8, "f-8s24a8", 0, 32, 24, 5, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }  },
 543   { MEP_F_24U8A4N_HI, "f-24u8a4n-hi", 0, 32, 16, 16, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }  },
 544   { MEP_F_24U8A4N_LO, "f-24u8a4n-lo", 0, 32, 8, 6, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }  },
 545   { MEP_F_24U8A4N, "f-24u8a4n", 0, 0, 0, 0,{ 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }  },
 546   { MEP_F_24U8N_HI, "f-24u8n-hi", 0, 32, 16, 16, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }  },
 547   { MEP_F_24U8N_LO, "f-24u8n-lo", 0, 32, 8, 8, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }  },
 548   { MEP_F_24U8N, "f-24u8n", 0, 0, 0, 0,{ 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }  },
 549   { MEP_F_24U4N_HI, "f-24u4n-hi", 0, 32, 4, 8, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }  },
 550   { MEP_F_24U4N_LO, "f-24u4n-lo", 0, 32, 16, 16, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }  },
 551   { MEP_F_24U4N, "f-24u4n", 0, 0, 0, 0,{ 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }  },
 552   { MEP_F_CALLNUM, "f-callnum", 0, 0, 0, 0,{ 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }  },
 553   { MEP_F_CCRN_HI, "f-ccrn-hi", 0, 32, 28, 2, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }  },
 554   { MEP_F_CCRN_LO, "f-ccrn-lo", 0, 32, 4, 4, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }  },
 555   { MEP_F_CCRN, "f-ccrn", 0, 0, 0, 0,{ 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }  },
 556   { 0, 0, 0, 0, 0, 0, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }
 557 };
 558
 559 #undef A
 560
 561
 562
 563 /* multi ifield declarations */
 564
 565 const CGEN_MAYBE_MULTI_IFLD MEP_F_CSRN_MULTI_IFIELD [];
 566 const CGEN_MAYBE_MULTI_IFLD MEP_F_CRNX_MULTI_IFIELD [];
 567 const CGEN_MAYBE_MULTI_IFLD MEP_F_24S5A2N_MULTI_IFIELD [];
 568 const CGEN_MAYBE_MULTI_IFLD MEP_F_24U5A2N_MULTI_IFIELD [];
 569 const CGEN_MAYBE_MULTI_IFLD MEP_F_24U8A4N_MULTI_IFIELD [];
 570 const CGEN_MAYBE_MULTI_IFLD MEP_F_24U8N_MULTI_IFIELD [];
 571 const CGEN_MAYBE_MULTI_IFLD MEP_F_24U4N_MULTI_IFIELD [];
 572 const CGEN_MAYBE_MULTI_IFLD MEP_F_CALLNUM_MULTI_IFIELD [];
 573 const CGEN_MAYBE_MULTI_IFLD MEP_F_CCRN_MULTI_IFIELD [];
 574
 575
 576 /* multi ifield definitions */
 577
 578 const CGEN_MAYBE_MULTI_IFLD MEP_F_CSRN_MULTI_IFIELD [] =
 579 {
 580     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_CSRN_HI] } },
 581     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_CSRN_LO] } },
 582     { 0, { (const PTR) 0 } }
 583 };
 584 const CGEN_MAYBE_MULTI_IFLD MEP_F_CRNX_MULTI_IFIELD [] =
 585 {
 586     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_CRNX_HI] } },
 587     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_CRNX_LO] } },
 588     { 0, { (const PTR) 0 } }
 589 };
 590 const CGEN_MAYBE_MULTI_IFLD MEP_F_24S5A2N_MULTI_IFIELD [] =
 591 {
 592     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_24S5A2N_HI] } },
 593     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_24S5A2N_LO] } },
 594     { 0, { (const PTR) 0 } }
 595 };
 596 const CGEN_MAYBE_MULTI_IFLD MEP_F_24U5A2N_MULTI_IFIELD [] =
 597 {
 598     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_24U5A2N_HI] } },
 599     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_24U5A2N_LO] } },
 600     { 0, { (const PTR) 0 } }
 601 };
 602 const CGEN_MAYBE_MULTI_IFLD MEP_F_24U8A4N_MULTI_IFIELD [] =
 603 {
 604     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_24U8A4N_HI] } },
 605     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_24U8A4N_LO] } },
 606     { 0, { (const PTR) 0 } }
 607 };
 608 const CGEN_MAYBE_MULTI_IFLD MEP_F_24U8N_MULTI_IFIELD [] =
 609 {
 610     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_24U8N_HI] } },
 611     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_24U8N_LO] } },
 612     { 0, { (const PTR) 0 } }
 613 };
 614 const CGEN_MAYBE_MULTI_IFLD MEP_F_24U4N_MULTI_IFIELD [] =
 615 {
 616     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_24U4N_HI] } },
 617     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_24U4N_LO] } },
 618     { 0, { (const PTR) 0 } }
 619 };
 620 const CGEN_MAYBE_MULTI_IFLD MEP_F_CALLNUM_MULTI_IFIELD [] =
 621 {
 622     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_5] } },
 623     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_6] } },
 624     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_7] } },
 625     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_11] } },
 626     { 0, { (const PTR) 0 } }
 627 };
 628 const CGEN_MAYBE_MULTI_IFLD MEP_F_CCRN_MULTI_IFIELD [] =
 629 {
 630     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_CCRN_HI] } },
 631     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_CCRN_LO] } },
 632     { 0, { (const PTR) 0 } }
 633 };
 634
 635 /* The operand table.  */
 636
 637 #if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
 638 #define A(a) (1 << CGEN_OPERAND_##a)
 639 #else
 640 #define A(a) (1 << CGEN_OPERAND_/**/a)
 641 #endif
 642 #if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
 643 #define OPERAND(op) MEP_OPERAND_##op
 644 #else
 645 #define OPERAND(op) MEP_OPERAND_/**/op
 646 #endif
 647
 648 const CGEN_OPERAND mep_cgen_operand_table[] =
 649 {
 650 /* pc: program counter */
 651   { "pc", MEP_OPERAND_PC, HW_H_PC, 0, 0,
 652     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_NIL] } },
 653     { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
 654 /* r0: register 0 */
 655   { "r0", MEP_OPERAND_R0, HW_H_GPR, 0, 0,
 656     { 0, { (const PTR) 0 } },
 657     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
 658 /* rn: register Rn */
 659   { "rn", MEP_OPERAND_RN, HW_H_GPR, 4, 4,
 660     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_RN] } },
 661     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
 662 /* rm: register Rm */
 663   { "rm", MEP_OPERAND_RM, HW_H_GPR, 8, 4,
 664     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_RM] } },
 665     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
 666 /* rl: register Rl */
 667   { "rl", MEP_OPERAND_RL, HW_H_GPR, 12, 4,
 668     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_RL] } },
 669     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
 670 /* rn3: register 0-7 */
 671   { "rn3", MEP_OPERAND_RN3, HW_H_GPR, 5, 3,
 672     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_RN3] } },
 673     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
 674 /* rma: register Rm holding pointer */
 675   { "rma", MEP_OPERAND_RMA, HW_H_GPR, 8, 4,
 676     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_RM] } },
 677     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CDATA_POINTER, 0 } }, { { 1, 0 } } } }  },
 678 /* rnc: register Rn holding char */
 679   { "rnc", MEP_OPERAND_RNC, HW_H_GPR, 4, 4,
 680     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_RN] } },
 681     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
 682 /* rnuc: register Rn holding unsigned char */
 683   { "rnuc", MEP_OPERAND_RNUC, HW_H_GPR, 4, 4,
 684     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_RN] } },
 685     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
 686 /* rns: register Rn holding short */
 687   { "rns", MEP_OPERAND_RNS, HW_H_GPR, 4, 4,
 688     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_RN] } },
 689     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
 690 /* rnus: register Rn holding unsigned short */
 691   { "rnus", MEP_OPERAND_RNUS, HW_H_GPR, 4, 4,
 692     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_RN] } },
 693     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
 694 /* rnl: register Rn holding long */
 695   { "rnl", MEP_OPERAND_RNL, HW_H_GPR, 4, 4,
 696     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_RN] } },
 697     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
 698 /* rnul: register Rn holding unsigned  long */
 699   { "rnul", MEP_OPERAND_RNUL, HW_H_GPR, 4, 4,
 700     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_RN] } },
 701     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CDATA_ULONG, 0 } }, { { 1, 0 } } } }  },
 702 /* rn3c: register 0-7 holding unsigned char */
 703   { "rn3c", MEP_OPERAND_RN3C, HW_H_GPR, 5, 3,
 704     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_RN3] } },
 705     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
 706 /* rn3uc: register 0-7 holding byte */
 707   { "rn3uc", MEP_OPERAND_RN3UC, HW_H_GPR, 5, 3,
 708     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_RN3] } },
 709     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
 710 /* rn3s: register 0-7 holding unsigned short */
 711   { "rn3s", MEP_OPERAND_RN3S, HW_H_GPR, 5, 3,
 712     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_RN3] } },
 713     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
 714 /* rn3us: register 0-7 holding short */
 715   { "rn3us", MEP_OPERAND_RN3US, HW_H_GPR, 5, 3,
 716     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_RN3] } },
 717     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
 718 /* rn3l: register 0-7 holding unsigned long */
 719   { "rn3l", MEP_OPERAND_RN3L, HW_H_GPR, 5, 3,
 720     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_RN3] } },
 721     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
 722 /* rn3ul: register 0-7 holding long */
 723   { "rn3ul", MEP_OPERAND_RN3UL, HW_H_GPR, 5, 3,
 724     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_RN3] } },
 725     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CDATA_ULONG, 0 } }, { { 1, 0 } } } }  },
 726 /* lp: link pointer */
 727   { "lp", MEP_OPERAND_LP, HW_H_CSR, 0, 0,
 728     { 0, { (const PTR) 0 } },
 729     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
 730 /* sar: shift amount register */
 731   { "sar", MEP_OPERAND_SAR, HW_H_CSR, 0, 0,
 732     { 0, { (const PTR) 0 } },
 733     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
 734 /* hi: high result */
 735   { "hi", MEP_OPERAND_HI, HW_H_CSR, 0, 0,
 736     { 0, { (const PTR) 0 } },
 737     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
 738 /* lo: low result */
 739   { "lo", MEP_OPERAND_LO, HW_H_CSR, 0, 0,
 740     { 0, { (const PTR) 0 } },
 741     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
 742 /* mb0: modulo begin register 0 */
 743   { "mb0", MEP_OPERAND_MB0, HW_H_CSR, 0, 0,
 744     { 0, { (const PTR) 0 } },
 745     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
 746 /* me0: modulo end register 0 */
 747   { "me0", MEP_OPERAND_ME0, HW_H_CSR, 0, 0,
 748     { 0, { (const PTR) 0 } },
 749     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
 750 /* mb1: modulo begin register 1 */
 751   { "mb1", MEP_OPERAND_MB1, HW_H_CSR, 0, 0,
 752     { 0, { (const PTR) 0 } },
 753     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
 754 /* me1: modulo end register 1 */
 755   { "me1", MEP_OPERAND_ME1, HW_H_CSR, 0, 0,
 756     { 0, { (const PTR) 0 } },
 757     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
 758 /* psw: program status word */
 759   { "psw", MEP_OPERAND_PSW, HW_H_CSR, 0, 0,
 760     { 0, { (const PTR) 0 } },
 761     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
 762 /* epc: exception prog counter */
 763   { "epc", MEP_OPERAND_EPC, HW_H_CSR, 0, 0,
 764     { 0, { (const PTR) 0 } },
 765     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
 766 /* exc: exception cause */
 767   { "exc", MEP_OPERAND_EXC, HW_H_CSR, 0, 0,
 768     { 0, { (const PTR) 0 } },
 769     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
 770 /* npc: nmi program counter */
 771   { "npc", MEP_OPERAND_NPC, HW_H_CSR, 0, 0,
 772     { 0, { (const PTR) 0 } },
 773     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
 774 /* dbg: debug register */
 775   { "dbg", MEP_OPERAND_DBG, HW_H_CSR, 0, 0,
 776     { 0, { (const PTR) 0 } },
 777     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
 778 /* depc: debug exception pc */
 779   { "depc", MEP_OPERAND_DEPC, HW_H_CSR, 0, 0,
 780     { 0, { (const PTR) 0 } },
 781     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
 782 /* opt: option register */
 783   { "opt", MEP_OPERAND_OPT, HW_H_CSR, 0, 0,
 784     { 0, { (const PTR) 0 } },
 785     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
 786 /* r1: register 1 */
 787   { "r1", MEP_OPERAND_R1, HW_H_GPR, 0, 0,
 788     { 0, { (const PTR) 0 } },
 789     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
 790 /* tp: tiny data area pointer */
 791   { "tp", MEP_OPERAND_TP, HW_H_GPR, 0, 0,
 792     { 0, { (const PTR) 0 } },
 793     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
 794 /* sp: stack pointer */
 795   { "sp", MEP_OPERAND_SP, HW_H_GPR, 0, 0,
 796     { 0, { (const PTR) 0 } },
 797     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
 798 /* tpr: comment */
 799   { "tpr", MEP_OPERAND_TPR, HW_H_GPR, 0, 0,
 800     { 0, { (const PTR) 0 } },
 801     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
 802 /* spr: comment */
 803   { "spr", MEP_OPERAND_SPR, HW_H_GPR, 0, 0,
 804     { 0, { (const PTR) 0 } },
 805     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
 806 /* csrn: control/special register */
 807   { "csrn", MEP_OPERAND_CSRN, HW_H_CSR, 8, 5,
 808     { 2, { (const PTR) &MEP_F_CSRN_MULTI_IFIELD[0] } },
 809     { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CDATA_REGNUM, 0 } }, { { 1, 0 } } } }  },
 810 /* csrn-idx: control/special reg idx */
 811   { "csrn-idx", MEP_OPERAND_CSRN_IDX, HW_H_UINT, 8, 5,
 812     { 2, { (const PTR) &MEP_F_CSRN_MULTI_IFIELD[0] } },
 813     { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
 814 /* crn64: copro Rn (64-bit) */
 815   { "crn64", MEP_OPERAND_CRN64, HW_H_CR64, 4, 4,
 816     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_CRN] } },
 817     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CDATA_CP_DATA_BUS_INT, 0 } }, { { 1, 0 } } } }  },
 818 /* crn: copro Rn (32-bit) */
 819   { "crn", MEP_OPERAND_CRN, HW_H_CR, 4, 4,
 820     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_CRN] } },
 821     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CDATA_CP_DATA_BUS_INT, 0 } }, { { 1, 0 } } } }  },
 822 /* crnx64: copro Rn (0-31, 64-bit) */
 823   { "crnx64", MEP_OPERAND_CRNX64, HW_H_CR64, 4, 5,
 824     { 2, { (const PTR) &MEP_F_CRNX_MULTI_IFIELD[0] } },
 825     { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CDATA_CP_DATA_BUS_INT, 0 } }, { { 1, 0 } } } }  },
 826 /* crnx: copro Rn (0-31, 32-bit) */
 827   { "crnx", MEP_OPERAND_CRNX, HW_H_CR, 4, 5,
 828     { 2, { (const PTR) &MEP_F_CRNX_MULTI_IFIELD[0] } },
 829     { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CDATA_CP_DATA_BUS_INT, 0 } }, { { 1, 0 } } } }  },
 830 /* ccrn: copro control reg CCRn */
 831   { "ccrn", MEP_OPERAND_CCRN, HW_H_CCR, 4, 6,
 832     { 2, { (const PTR) &MEP_F_CCRN_MULTI_IFIELD[0] } },
 833     { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CDATA_REGNUM, 0 } }, { { 1, 0 } } } }  },
 834 /* cccc: copro flags */
 835   { "cccc", MEP_OPERAND_CCCC, HW_H_UINT, 8, 4,
 836     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_RM] } },
 837     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
 838 /* pcrel8a2: comment */
 839   { "pcrel8a2", MEP_OPERAND_PCREL8A2, HW_H_SINT, 8, 7,
 840     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_8S8A2] } },
 841     { 0|A(RELAX)|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CDATA_LABEL, 0 } }, { { 1, 0 } } } }  },
 842 /* pcrel12a2: comment */
 843   { "pcrel12a2", MEP_OPERAND_PCREL12A2, HW_H_SINT, 4, 11,
 844     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_12S4A2] } },
 845     { 0|A(RELAX)|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CDATA_LABEL, 0 } }, { { 1, 0 } } } }  },
 846 /* pcrel17a2: comment */
 847   { "pcrel17a2", MEP_OPERAND_PCREL17A2, HW_H_SINT, 16, 16,
 848     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_17S16A2] } },
 849     { 0|A(RELAX)|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CDATA_LABEL, 0 } }, { { 1, 0 } } } }  },
 850 /* pcrel24a2: comment */
 851   { "pcrel24a2", MEP_OPERAND_PCREL24A2, HW_H_SINT, 5, 23,
 852     { 2, { (const PTR) &MEP_F_24S5A2N_MULTI_IFIELD[0] } },
 853     { 0|A(PCREL_ADDR)|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CDATA_LABEL, 0 } }, { { 1, 0 } } } }  },
 854 /* pcabs24a2: comment */
 855   { "pcabs24a2", MEP_OPERAND_PCABS24A2, HW_H_UINT, 5, 23,
 856     { 2, { (const PTR) &MEP_F_24U5A2N_MULTI_IFIELD[0] } },
 857     { 0|A(ABS_ADDR)|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CDATA_LABEL, 0 } }, { { 1, 0 } } } }  },
 858 /* sdisp16: comment */
 859   { "sdisp16", MEP_OPERAND_SDISP16, HW_H_SINT, 16, 16,
 860     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_16S16] } },
 861     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
 862 /* simm16: comment */
 863   { "simm16", MEP_OPERAND_SIMM16, HW_H_SINT, 16, 16,
 864     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_16S16] } },
 865     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
 866 /* uimm16: comment */
 867   { "uimm16", MEP_OPERAND_UIMM16, HW_H_UINT, 16, 16,
 868     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_16U16] } },
 869     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
 870 /* code16: uci/dsp code (16 bits) */
 871   { "code16", MEP_OPERAND_CODE16, HW_H_UINT, 16, 16,
 872     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_16U16] } },
 873     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
 874 /* udisp2: SSARB addend (2 bits) */
 875   { "udisp2", MEP_OPERAND_UDISP2, HW_H_SINT, 6, 2,
 876     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_2U6] } },
 877     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
 878 /* uimm2: interrupt (2 bits) */
 879   { "uimm2", MEP_OPERAND_UIMM2, HW_H_UINT, 10, 2,
 880     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_2U10] } },
 881     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
 882 /* simm6: add const (6 bits) */
 883   { "simm6", MEP_OPERAND_SIMM6, HW_H_SINT, 8, 6,
 884     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_6S8] } },
 885     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
 886 /* simm8: mov const (8 bits) */
 887   { "simm8", MEP_OPERAND_SIMM8, HW_H_SINT, 8, 8,
 888     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_8S8] } },
 889     { 0|A(RELOC_IMPLIES_OVERFLOW), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
 890 /* addr24a4: comment */
 891   { "addr24a4", MEP_OPERAND_ADDR24A4, HW_H_UINT, 8, 22,
 892     { 2, { (const PTR) &MEP_F_24U8A4N_MULTI_IFIELD[0] } },
 893     { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CDATA_LONG, 0 } }, { { 4, 0 } } } }  },
 894 /* code24: coprocessor code */
 895   { "code24", MEP_OPERAND_CODE24, HW_H_UINT, 4, 24,
 896     { 2, { (const PTR) &MEP_F_24U4N_MULTI_IFIELD[0] } },
 897     { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
 898 /* callnum: system call number */
 899   { "callnum", MEP_OPERAND_CALLNUM, HW_H_UINT, 5, 4,
 900     { 4, { (const PTR) &MEP_F_CALLNUM_MULTI_IFIELD[0] } },
 901     { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
 902 /* uimm3: bit immediate (3 bits) */
 903   { "uimm3", MEP_OPERAND_UIMM3, HW_H_UINT, 5, 3,
 904     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_3U5] } },
 905     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
 906 /* uimm4: bCC const (4 bits) */
 907   { "uimm4", MEP_OPERAND_UIMM4, HW_H_UINT, 8, 4,
 908     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_4U8] } },
 909     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
 910 /* uimm5: bit/shift val (5 bits) */
 911   { "uimm5", MEP_OPERAND_UIMM5, HW_H_UINT, 8, 5,
 912     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_5U8] } },
 913     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
 914 /* udisp7: comment */
 915   { "udisp7", MEP_OPERAND_UDISP7, HW_H_UINT, 9, 7,
 916     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_7U9] } },
 917     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
 918 /* udisp7a2: comment */
 919   { "udisp7a2", MEP_OPERAND_UDISP7A2, HW_H_UINT, 9, 6,
 920     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_7U9A2] } },
 921     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CDATA_LONG, 0 } }, { { 2, 0 } } } }  },
 922 /* udisp7a4: comment */
 923   { "udisp7a4", MEP_OPERAND_UDISP7A4, HW_H_UINT, 9, 5,
 924     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_7U9A4] } },
 925     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CDATA_LONG, 0 } }, { { 4, 0 } } } }  },
 926 /* uimm7a4: comment */
 927   { "uimm7a4", MEP_OPERAND_UIMM7A4, HW_H_UINT, 9, 5,
 928     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_7U9A4] } },
 929     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CDATA_LONG, 0 } }, { { 4, 0 } } } }  },
 930 /* uimm24: immediate (24 bits) */
 931   { "uimm24", MEP_OPERAND_UIMM24, HW_H_UINT, 8, 24,
 932     { 2, { (const PTR) &MEP_F_24U8N_MULTI_IFIELD[0] } },
 933     { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
 934 /* cimm4: cache immed'te (4 bits) */
 935   { "cimm4", MEP_OPERAND_CIMM4, HW_H_UINT, 4, 4,
 936     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_RN] } },
 937     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
 938 /* cimm5: clip immediate (5 bits) */
 939   { "cimm5", MEP_OPERAND_CIMM5, HW_H_UINT, 24, 5,
 940     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_5U24] } },
 941     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
 942 /* cdisp8: copro addend (8 bits) */
 943   { "cdisp8", MEP_OPERAND_CDISP8, HW_H_SINT, 24, 8,
 944     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_8S24] } },
 945     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
 946 /* cdisp8a2: comment */
 947   { "cdisp8a2", MEP_OPERAND_CDISP8A2, HW_H_SINT, 24, 7,
 948     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_8S24A2] } },
 949     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CDATA_LONG, 0 } }, { { 2, 0 } } } }  },
 950 /* cdisp8a4: comment */
 951   { "cdisp8a4", MEP_OPERAND_CDISP8A4, HW_H_SINT, 24, 6,
 952     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_8S24A4] } },
 953     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CDATA_LONG, 0 } }, { { 4, 0 } } } }  },
 954 /* cdisp8a8: comment */
 955   { "cdisp8a8", MEP_OPERAND_CDISP8A8, HW_H_SINT, 24, 5,
 956     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_8S24A8] } },
 957     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CDATA_LONG, 0 } }, { { 8, 0 } } } }  },
 958 /* zero: Zero operand */
 959   { "zero", MEP_OPERAND_ZERO, HW_H_SINT, 0, 0,
 960     { 0, { (const PTR) 0 } },
 961     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
 962 /* cp_flag: branch condition register */
 963   { "cp_flag", MEP_OPERAND_CP_FLAG, HW_H_CCR, 0, 0,
 964     { 0, { (const PTR) 0 } },
 965     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
 966 /* sentinel */
 967   { 0, 0, 0, 0, 0,
 968     { 0, { (const PTR) 0 } },
 969     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } }
 970 };
 971
 972 #undef A
 973
 974
 975 /* The instruction table.  */
 976
 977 #define OP(field) CGEN_SYNTAX_MAKE_FIELD (OPERAND (field))
 978 #if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
 979 #define A(a) (1 << CGEN_INSN_##a)
 980 #else
 981 #define A(a) (1 << CGEN_INSN_/**/a)
 982 #endif
 983
 984 static const CGEN_IBASE mep_cgen_insn_table[MAX_INSNS] =
 985 {
 986   /* Special null first entry.
 987      A `num' value of zero is thus invalid.
 988      Also, the special `invalid' insn resides here.  */
 989   { 0, 0, 0, 0, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } } },
 990 /* sb $rnc,($rma) */
 991   {
 992     MEP_INSN_SB, "sb", "sb", 16,
 993     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
 994   },
 995 /* sh $rns,($rma) */
 996   {
 997     MEP_INSN_SH, "sh", "sh", 16,
 998     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
 999   },
1000 /* sw $rnl,($rma) */
1001   {
1002     MEP_INSN_SW, "sw", "sw", 16,
1003     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
1004   },
1005 /* lb $rnc,($rma) */
1006   {
1007     MEP_INSN_LB, "lb", "lb", 16,
1008     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 2, 0 } }, { { CONFIG_NONE, 0 } } } }
1009   },
1010 /* lh $rns,($rma) */
1011   {
1012     MEP_INSN_LH, "lh", "lh", 16,
1013     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 2, 0 } }, { { CONFIG_NONE, 0 } } } }
1014   },
1015 /* lw $rnl,($rma) */
1016   {
1017     MEP_INSN_LW, "lw", "lw", 16,
1018     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 2, 0 } }, { { CONFIG_NONE, 0 } } } }
1019   },
1020 /* lbu $rnuc,($rma) */
1021   {
1022     MEP_INSN_LBU, "lbu", "lbu", 16,
1023     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 2, 0 } }, { { CONFIG_NONE, 0 } } } }
1024   },
1025 /* lhu $rnus,($rma) */
1026   {
1027     MEP_INSN_LHU, "lhu", "lhu", 16,
1028     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 2, 0 } }, { { CONFIG_NONE, 0 } } } }
1029   },
1030 /* sw $rnl,$udisp7a4($spr) */
1031   {
1032     MEP_INSN_SW_SP, "sw-sp", "sw", 16,
1033     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
1034   },
1035 /* lw $rnl,$udisp7a4($spr) */
1036   {
1037     MEP_INSN_LW_SP, "lw-sp", "lw", 16,
1038     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 2, 0 } }, { { CONFIG_NONE, 0 } } } }
1039   },
1040 /* sb $rn3c,$udisp7($tpr) */
1041   {
1042     MEP_INSN_SB_TP, "sb-tp", "sb", 16,
1043     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
1044   },
1045 /* sh $rn3s,$udisp7a2($tpr) */
1046   {
1047     MEP_INSN_SH_TP, "sh-tp", "sh", 16,
1048     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
1049   },
1050 /* sw $rn3l,$udisp7a4($tpr) */
1051   {
1052     MEP_INSN_SW_TP, "sw-tp", "sw", 16,
1053     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
1054   },
1055 /* lb $rn3c,$udisp7($tpr) */
1056   {
1057     MEP_INSN_LB_TP, "lb-tp", "lb", 16,
1058     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 2, 0 } }, { { CONFIG_NONE, 0 } } } }
1059   },
1060 /* lh $rn3s,$udisp7a2($tpr) */
1061   {
1062     MEP_INSN_LH_TP, "lh-tp", "lh", 16,
1063     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 2, 0 } }, { { CONFIG_NONE, 0 } } } }
1064   },
1065 /* lw $rn3l,$udisp7a4($tpr) */
1066   {
1067     MEP_INSN_LW_TP, "lw-tp", "lw", 16,
1068     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 2, 0 } }, { { CONFIG_NONE, 0 } } } }
1069   },
1070 /* lbu $rn3uc,$udisp7($tpr) */
1071   {
1072     MEP_INSN_LBU_TP, "lbu-tp", "lbu", 16,
1073     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 2, 0 } }, { { CONFIG_NONE, 0 } } } }
1074   },
1075 /* lhu $rn3us,$udisp7a2($tpr) */
1076   {
1077     MEP_INSN_LHU_TP, "lhu-tp", "lhu", 16,
1078     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 2, 0 } }, { { CONFIG_NONE, 0 } } } }
1079   },
1080 /* sb $rnc,$sdisp16($rma) */
1081   {
1082     MEP_INSN_SB16, "sb16", "sb", 32,
1083     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
1084   },
1085 /* sh $rns,$sdisp16($rma) */
1086   {
1087     MEP_INSN_SH16, "sh16", "sh", 32,
1088     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
1089   },
1090 /* sw $rnl,$sdisp16($rma) */
1091   {
1092     MEP_INSN_SW16, "sw16", "sw", 32,
1093     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
1094   },
1095 /* lb $rnc,$sdisp16($rma) */
1096   {
1097     MEP_INSN_LB16, "lb16", "lb", 32,
1098     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 2, 0 } }, { { CONFIG_NONE, 0 } } } }
1099   },
1100 /* lh $rns,$sdisp16($rma) */
1101   {
1102     MEP_INSN_LH16, "lh16", "lh", 32,
1103     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 2, 0 } }, { { CONFIG_NONE, 0 } } } }
1104   },
1105 /* lw $rnl,$sdisp16($rma) */
1106   {
1107     MEP_INSN_LW16, "lw16", "lw", 32,
1108     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 2, 0 } }, { { CONFIG_NONE, 0 } } } }
1109   },
1110 /* lbu $rnuc,$sdisp16($rma) */
1111   {
1112     MEP_INSN_LBU16, "lbu16", "lbu", 32,
1113     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 2, 0 } }, { { CONFIG_NONE, 0 } } } }
1114   },
1115 /* lhu $rnus,$sdisp16($rma) */
1116   {
1117     MEP_INSN_LHU16, "lhu16", "lhu", 32,
1118     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 2, 0 } }, { { CONFIG_NONE, 0 } } } }
1119   },
1120 /* sw $rnl,($addr24a4) */
1121   {
1122     MEP_INSN_SW24, "sw24", "sw", 32,
1123     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
1124   },
1125 /* lw $rnl,($addr24a4) */
1126   {
1127     MEP_INSN_LW24, "lw24", "lw", 32,
1128     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 2, 0 } }, { { CONFIG_NONE, 0 } } } }
1129   },
1130 /* extb $rn */
1131   {
1132     MEP_INSN_EXTB, "extb", "extb", 16,
1133     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
1134   },
1135 /* exth $rn */
1136   {
1137     MEP_INSN_EXTH, "exth", "exth", 16,
1138     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
1139   },
1140 /* extub $rn */
1141   {
1142     MEP_INSN_EXTUB, "extub", "extub", 16,
1143     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
1144   },
1145 /* extuh $rn */
1146   {
1147     MEP_INSN_EXTUH, "extuh", "extuh", 16,
1148     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
1149   },
1150 /* ssarb $udisp2($rm) */
1151   {
1152     MEP_INSN_SSARB, "ssarb", "ssarb", 16,
1153     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
1154   },
1155 /* mov $rn,$rm */
1156   {
1157     MEP_INSN_MOV, "mov", "mov", 16,
1158     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
1159   },
1160 /* mov $rn,$simm8 */
1161   {
1162     MEP_INSN_MOVI8, "movi8", "mov", 16,
1163     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
1164   },
1165 /* mov $rn,$simm16 */
1166   {
1167     MEP_INSN_MOVI16, "movi16", "mov", 32,
1168     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
1169   },
1170 /* movu $rn3,$uimm24 */
1171   {
1172     MEP_INSN_MOVU24, "movu24", "movu", 32,
1173     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
1174   },
1175 /* movu $rn,$uimm16 */
1176   {
1177     MEP_INSN_MOVU16, "movu16", "movu", 32,
1178     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
1179   },
1180 /* movh $rn,$uimm16 */
1181   {
1182     MEP_INSN_MOVH, "movh", "movh", 32,
1183     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
1184   },
1185 /* add3 $rl,$rn,$rm */
1186   {
1187     MEP_INSN_ADD3, "add3", "add3", 16,
1188     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
1189   },
1190 /* add $rn,$simm6 */
1191   {
1192     MEP_INSN_ADD, "add", "add", 16,
1193     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
1194   },
1195 /* add3 $rn,$spr,$uimm7a4 */
1196   {
1197     MEP_INSN_ADD3I, "add3i", "add3", 16,
1198     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
1199   },
1200 /* advck3 \$0,$rn,$rm */
1201   {
1202     MEP_INSN_ADVCK3, "advck3", "advck3", 16,
1203     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
1204   },
1205 /* sub $rn,$rm */
1206   {
1207     MEP_INSN_SUB, "sub", "sub", 16,
1208     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
1209   },
1210 /* sbvck3 \$0,$rn,$rm */
1211   {
1212     MEP_INSN_SBVCK3, "sbvck3", "sbvck3", 16,
1213     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
1214   },
1215 /* neg $rn,$rm */
1216   {
1217     MEP_INSN_NEG, "neg", "neg", 16,
1218     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
1219   },
1220 /* slt3 \$0,$rn,$rm */
1221   {
1222     MEP_INSN_SLT3, "slt3", "slt3", 16,
1223     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
1224   },
1225 /* sltu3 \$0,$rn,$rm */
1226   {
1227     MEP_INSN_SLTU3, "sltu3", "sltu3", 16,
1228     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
1229   },
1230 /* slt3 \$0,$rn,$uimm5 */
1231   {
1232     MEP_INSN_SLT3I, "slt3i", "slt3", 16,
1233     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
1234   },
1235 /* sltu3 \$0,$rn,$uimm5 */
1236   {
1237     MEP_INSN_SLTU3I, "sltu3i", "sltu3", 16,
1238     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
1239   },
1240 /* sl1ad3 \$0,$rn,$rm */
1241   {
1242     MEP_INSN_SL1AD3, "sl1ad3", "sl1ad3", 16,
1243     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
1244   },
1245 /* sl2ad3 \$0,$rn,$rm */
1246   {
1247     MEP_INSN_SL2AD3, "sl2ad3", "sl2ad3", 16,
1248     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
1249   },
1250 /* add3 $rn,$rm,$simm16 */
1251   {
1252     MEP_INSN_ADD3X, "add3x", "add3", 32,
1253     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
1254   },
1255 /* slt3 $rn,$rm,$simm16 */
1256   {
1257     MEP_INSN_SLT3X, "slt3x", "slt3", 32,
1258     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
1259   },
1260 /* sltu3 $rn,$rm,$uimm16 */
1261   {
1262     MEP_INSN_SLTU3X, "sltu3x", "sltu3", 32,
1263     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
1264   },
1265 /* or $rn,$rm */
1266   {
1267     MEP_INSN_OR, "or", "or", 16,
1268     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
1269   },
1270 /* and $rn,$rm */
1271   {
1272     MEP_INSN_AND, "and", "and", 16,
1273     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
1274   },
1275 /* xor $rn,$rm */
1276   {
1277     MEP_INSN_XOR, "xor", "xor", 16,
1278     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
1279   },
1280 /* nor $rn,$rm */
1281   {
1282     MEP_INSN_NOR, "nor", "nor", 16,
1283     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
1284   },
1285 /* or3 $rn,$rm,$uimm16 */
1286   {
1287     MEP_INSN_OR3, "or3", "or3", 32,
1288     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
1289   },
1290 /* and3 $rn,$rm,$uimm16 */
1291   {
1292     MEP_INSN_AND3, "and3", "and3", 32,
1293     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
1294   },
1295 /* xor3 $rn,$rm,$uimm16 */
1296   {
1297     MEP_INSN_XOR3, "xor3", "xor3", 32,
1298     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
1299   },
1300 /* sra $rn,$rm */
1301   {
1302     MEP_INSN_SRA, "sra", "sra", 16,
1303     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
1304   },
1305 /* srl $rn,$rm */
1306   {
1307     MEP_INSN_SRL, "srl", "srl", 16,
1308     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
1309   },
1310 /* sll $rn,$rm */
1311   {
1312     MEP_INSN_SLL, "sll", "sll", 16,
1313     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
1314   },
1315 /* sra $rn,$uimm5 */
1316   {
1317     MEP_INSN_SRAI, "srai", "sra", 16,
1318     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
1319   },
1320 /* srl $rn,$uimm5 */
1321   {
1322     MEP_INSN_SRLI, "srli", "srl", 16,
1323     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
1324   },
1325 /* sll $rn,$uimm5 */
1326   {
1327     MEP_INSN_SLLI, "slli", "sll", 16,
1328     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
1329   },
1330 /* sll3 \$0,$rn,$uimm5 */
1331   {
1332     MEP_INSN_SLL3, "sll3", "sll3", 16,
1333     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
1334   },
1335 /* fsft $rn,$rm */
1336   {
1337     MEP_INSN_FSFT, "fsft", "fsft", 16,
1338     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
1339   },
1340 /* bra $pcrel12a2 */
1341   {
1342     MEP_INSN_BRA, "bra", "bra", 16,
1343     { 0|A(RELAXABLE)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
1344   },
1345 /* beqz $rn,$pcrel8a2 */
1346   {
1347     MEP_INSN_BEQZ, "beqz", "beqz", 16,
1348     { 0|A(RELAXABLE)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
1349   },
1350 /* bnez $rn,$pcrel8a2 */
1351   {
1352     MEP_INSN_BNEZ, "bnez", "bnez", 16,
1353     { 0|A(RELAXABLE)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
1354   },
1355 /* beqi $rn,$uimm4,$pcrel17a2 */
1356   {
1357     MEP_INSN_BEQI, "beqi", "beqi", 32,
1358     { 0|A(RELAXABLE)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
1359   },
1360 /* bnei $rn,$uimm4,$pcrel17a2 */
1361   {
1362     MEP_INSN_BNEI, "bnei", "bnei", 32,
1363     { 0|A(RELAXABLE)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
1364   },
1365 /* blti $rn,$uimm4,$pcrel17a2 */
1366   {
1367     MEP_INSN_BLTI, "blti", "blti", 32,
1368     { 0|A(RELAXABLE)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
1369   },
1370 /* bgei $rn,$uimm4,$pcrel17a2 */
1371   {
1372     MEP_INSN_BGEI, "bgei", "bgei", 32,
1373     { 0|A(RELAXABLE)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
1374   },
1375 /* beq $rn,$rm,$pcrel17a2 */
1376   {
1377     MEP_INSN_BEQ, "beq", "beq", 32,
1378     { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
1379   },
1380 /* bne $rn,$rm,$pcrel17a2 */
1381   {
1382     MEP_INSN_BNE, "bne", "bne", 32,
1383     { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
1384   },
1385 /* bsr $pcrel12a2 */
1386   {
1387     MEP_INSN_BSR12, "bsr12", "bsr", 16,
1388     { 0|A(RELAXABLE)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
1389   },
1390 /* bsr $pcrel24a2 */
1391   {
1392     MEP_INSN_BSR24, "bsr24", "bsr", 32,
1393     { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
1394   },
1395 /* jmp $rm */
1396   {
1397     MEP_INSN_JMP, "jmp", "jmp", 16,
1398     { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
1399   },
1400 /* jmp $pcabs24a2 */
1401   {
1402     MEP_INSN_JMP24, "jmp24", "jmp", 32,
1403     { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
1404   },
1405 /* jsr $rm */
1406   {
1407     MEP_INSN_JSR, "jsr", "jsr", 16,
1408     { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
1409   },
1410 /* ret */
1411   {
1412     MEP_INSN_RET, "ret", "ret", 16,
1413     { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
1414   },
1415 /* repeat $rn,$pcrel17a2 */
1416   {
1417     MEP_INSN_REPEAT, "repeat", "repeat", 32,
1418     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
1419   },
1420 /* erepeat $pcrel17a2 */
1421   {
1422     MEP_INSN_EREPEAT, "erepeat", "erepeat", 32,
1423     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
1424   },
1425 /* stc $rn,\$lp */
1426   {
1427     MEP_INSN_STC_LP, "stc_lp", "stc", 16,
1428     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
1429   },
1430 /* stc $rn,\$hi */
1431   {
1432     MEP_INSN_STC_HI, "stc_hi", "stc", 16,
1433     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
1434   },
1435 /* stc $rn,\$lo */
1436   {
1437     MEP_INSN_STC_LO, "stc_lo", "stc", 16,
1438     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
1439   },
1440 /* stc $rn,$csrn */
1441   {
1442     MEP_INSN_STC, "stc", "stc", 16,
1443     { 0|A(VOLATILE), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
1444   },
1445 /* ldc $rn,\$lp */
1446   {
1447     MEP_INSN_LDC_LP, "ldc_lp", "ldc", 16,
1448     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
1449   },
1450 /* ldc $rn,\$hi */
1451   {
1452     MEP_INSN_LDC_HI, "ldc_hi", "ldc", 16,
1453     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
1454   },
1455 /* ldc $rn,\$lo */
1456   {
1457     MEP_INSN_LDC_LO, "ldc_lo", "ldc", 16,
1458     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
1459   },
1460 /* ldc $rn,$csrn */
1461   {
1462     MEP_INSN_LDC, "ldc", "ldc", 16,
1463     { 0|A(VOLATILE), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 2, 0 } }, { { CONFIG_NONE, 0 } } } }
1464   },
1465 /* di */
1466   {
1467     MEP_INSN_DI, "di", "di", 16,
1468     { 0|A(VOLATILE), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
1469   },
1470 /* ei */
1471   {
1472     MEP_INSN_EI, "ei", "ei", 16,
1473     { 0|A(VOLATILE), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
1474   },
1475 /* reti */
1476   {
1477     MEP_INSN_RETI, "reti", "reti", 16,
1478     { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
1479   },
1480 /* halt */
1481   {
1482     MEP_INSN_HALT, "halt", "halt", 16,
1483     { 0|A(VOLATILE), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
1484   },
1485 /* sleep */
1486   {
1487     MEP_INSN_SLEEP, "sleep", "sleep", 16,
1488     { 0|A(VOLATILE), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
1489   },
1490 /* swi $uimm2 */
1491   {
1492     MEP_INSN_SWI, "swi", "swi", 16,
1493     { 0|A(VOLATILE)|A(MAY_TRAP), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
1494   },
1495 /* break */
1496   {
1497     MEP_INSN_BREAK, "break", "break", 16,
1498     { 0|A(VOLATILE)|A(MAY_TRAP)|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
1499   },
1500 /* syncm */
1501   {
1502     MEP_INSN_SYNCM, "syncm", "syncm", 16,
1503     { 0|A(VOLATILE), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
1504   },
1505 /* stcb $rn,$uimm16 */
1506   {
1507     MEP_INSN_STCB, "stcb", "stcb", 32,
1508     { 0|A(VOLATILE), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
1509   },
1510 /* ldcb $rn,$uimm16 */
1511   {
1512     MEP_INSN_LDCB, "ldcb", "ldcb", 32,
1513     { 0|A(VOLATILE), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 3, 0 } }, { { CONFIG_NONE, 0 } } } }
1514   },
1515 /* bsetm ($rma),$uimm3 */
1516   {
1517     MEP_INSN_BSETM, "bsetm", "bsetm", 16,
1518     { 0|A(OPTIONAL_BIT_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
1519   },
1520 /* bclrm ($rma),$uimm3 */
1521   {
1522     MEP_INSN_BCLRM, "bclrm", "bclrm", 16,
1523     { 0|A(OPTIONAL_BIT_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
1524   },
1525 /* bnotm ($rma),$uimm3 */
1526   {
1527     MEP_INSN_BNOTM, "bnotm", "bnotm", 16,
1528     { 0|A(OPTIONAL_BIT_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
1529   },
1530 /* btstm \$0,($rma),$uimm3 */
1531   {
1532     MEP_INSN_BTSTM, "btstm", "btstm", 16,
1533     { 0|A(OPTIONAL_BIT_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
1534   },
1535 /* tas $rn,($rma) */
1536   {
1537     MEP_INSN_TAS, "tas", "tas", 16,
1538     { 0|A(OPTIONAL_BIT_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
1539   },
1540 /* cache $cimm4,($rma) */
1541   {
1542     MEP_INSN_CACHE, "cache", "cache", 16,
1543     { 0|A(VOLATILE), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
1544   },
1545 /* mul $rn,$rm */
1546   {
1547     MEP_INSN_MUL, "mul", "mul", 16,
1548     { 0|A(OPTIONAL_MUL_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
1549   },
1550 /* mulu $rn,$rm */
1551   {
1552     MEP_INSN_MULU, "mulu", "mulu", 16,
1553     { 0|A(OPTIONAL_MUL_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
1554   },
1555 /* mulr $rn,$rm */
1556   {
1557     MEP_INSN_MULR, "mulr", "mulr", 16,
1558     { 0|A(OPTIONAL_MUL_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 3, 0 } }, { { CONFIG_NONE, 0 } } } }
1559   },
1560 /* mulru $rn,$rm */
1561   {
1562     MEP_INSN_MULRU, "mulru", "mulru", 16,
1563     { 0|A(OPTIONAL_MUL_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 3, 0 } }, { { CONFIG_NONE, 0 } } } }
1564   },
1565 /* madd $rn,$rm */
1566   {
1567     MEP_INSN_MADD, "madd", "madd", 32,
1568     { 0|A(OPTIONAL_MUL_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
1569   },
1570 /* maddu $rn,$rm */
1571   {
1572     MEP_INSN_MADDU, "maddu", "maddu", 32,
1573     { 0|A(OPTIONAL_MUL_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
1574   },
1575 /* maddr $rn,$rm */
1576   {
1577     MEP_INSN_MADDR, "maddr", "maddr", 32,
1578     { 0|A(OPTIONAL_MUL_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 3, 0 } }, { { CONFIG_NONE, 0 } } } }
1579   },
1580 /* maddru $rn,$rm */
1581   {
1582     MEP_INSN_MADDRU, "maddru", "maddru", 32,
1583     { 0|A(OPTIONAL_MUL_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 3, 0 } }, { { CONFIG_NONE, 0 } } } }
1584   },
1585 /* div $rn,$rm */
1586   {
1587     MEP_INSN_DIV, "div", "div", 16,
1588     { 0|A(MAY_TRAP)|A(OPTIONAL_DIV_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 34, 0 } }, { { CONFIG_NONE, 0 } } } }
1589   },
1590 /* divu $rn,$rm */
1591   {
1592     MEP_INSN_DIVU, "divu", "divu", 16,
1593     { 0|A(MAY_TRAP)|A(OPTIONAL_DIV_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 34, 0 } }, { { CONFIG_NONE, 0 } } } }
1594   },
1595 /* dret */
1596   {
1597     MEP_INSN_DRET, "dret", "dret", 16,
1598     { 0|A(OPTIONAL_DEBUG_INSN)|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
1599   },
1600 /* dbreak */
1601   {
1602     MEP_INSN_DBREAK, "dbreak", "dbreak", 16,
1603     { 0|A(VOLATILE)|A(MAY_TRAP)|A(OPTIONAL_DEBUG_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
1604   },
1605 /* ldz $rn,$rm */
1606   {
1607     MEP_INSN_LDZ, "ldz", "ldz", 32,
1608     { 0|A(OPTIONAL_LDZ_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
1609   },
1610 /* abs $rn,$rm */
1611   {
1612     MEP_INSN_ABS, "abs", "abs", 32,
1613     { 0|A(OPTIONAL_ABS_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
1614   },
1615 /* ave $rn,$rm */
1616   {
1617     MEP_INSN_AVE, "ave", "ave", 32,
1618     { 0|A(OPTIONAL_AVE_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
1619   },
1620 /* min $rn,$rm */
1621   {
1622     MEP_INSN_MIN, "min", "min", 32,
1623     { 0|A(OPTIONAL_MINMAX_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
1624   },
1625 /* max $rn,$rm */
1626   {
1627     MEP_INSN_MAX, "max", "max", 32,
1628     { 0|A(OPTIONAL_MINMAX_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
1629   },
1630 /* minu $rn,$rm */
1631   {
1632     MEP_INSN_MINU, "minu", "minu", 32,
1633     { 0|A(OPTIONAL_MINMAX_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
1634   },
1635 /* maxu $rn,$rm */
1636   {
1637     MEP_INSN_MAXU, "maxu", "maxu", 32,
1638     { 0|A(OPTIONAL_MINMAX_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
1639   },
1640 /* clip $rn,$cimm5 */
1641   {
1642     MEP_INSN_CLIP, "clip", "clip", 32,
1643     { 0|A(OPTIONAL_CLIP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
1644   },
1645 /* clipu $rn,$cimm5 */
1646   {
1647     MEP_INSN_CLIPU, "clipu", "clipu", 32,
1648     { 0|A(OPTIONAL_CLIP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
1649   },
1650 /* sadd $rn,$rm */
1651   {
1652     MEP_INSN_SADD, "sadd", "sadd", 32,
1653     { 0|A(OPTIONAL_SAT_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
1654   },
1655 /* ssub $rn,$rm */
1656   {
1657     MEP_INSN_SSUB, "ssub", "ssub", 32,
1658     { 0|A(OPTIONAL_SAT_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
1659   },
1660 /* saddu $rn,$rm */
1661   {
1662     MEP_INSN_SADDU, "saddu", "saddu", 32,
1663     { 0|A(OPTIONAL_SAT_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
1664   },
1665 /* ssubu $rn,$rm */
1666   {
1667     MEP_INSN_SSUBU, "ssubu", "ssubu", 32,
1668     { 0|A(OPTIONAL_SAT_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
1669   },
1670 /* swcp $crn,($rma) */
1671   {
1672     MEP_INSN_SWCP, "swcp", "swcp", 16,
1673     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
1674   },
1675 /* lwcp $crn,($rma) */
1676   {
1677     MEP_INSN_LWCP, "lwcp", "lwcp", 16,
1678     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
1679   },
1680 /* smcp $crn64,($rma) */
1681   {
1682     MEP_INSN_SMCP, "smcp", "smcp", 16,
1683     { 0|A(OPTIONAL_CP64_INSN)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
1684   },
1685 /* lmcp $crn64,($rma) */
1686   {
1687     MEP_INSN_LMCP, "lmcp", "lmcp", 16,
1688     { 0|A(OPTIONAL_CP64_INSN)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
1689   },
1690 /* swcpi $crn,($rma+) */
1691   {
1692     MEP_INSN_SWCPI, "swcpi", "swcpi", 16,
1693     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
1694   },
1695 /* lwcpi $crn,($rma+) */
1696   {
1697     MEP_INSN_LWCPI, "lwcpi", "lwcpi", 16,
1698     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
1699   },
1700 /* smcpi $crn64,($rma+) */
1701   {
1702     MEP_INSN_SMCPI, "smcpi", "smcpi", 16,
1703     { 0|A(OPTIONAL_CP64_INSN)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
1704   },
1705 /* lmcpi $crn64,($rma+) */
1706   {
1707     MEP_INSN_LMCPI, "lmcpi", "lmcpi", 16,
1708     { 0|A(OPTIONAL_CP64_INSN)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
1709   },
1710 /* swcp $crn,$sdisp16($rma) */
1711   {
1712     MEP_INSN_SWCP16, "swcp16", "swcp", 32,
1713     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
1714   },
1715 /* lwcp $crn,$sdisp16($rma) */
1716   {
1717     MEP_INSN_LWCP16, "lwcp16", "lwcp", 32,
1718     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
1719   },
1720 /* smcp $crn64,$sdisp16($rma) */
1721   {
1722     MEP_INSN_SMCP16, "smcp16", "smcp", 32,
1723     { 0|A(OPTIONAL_CP64_INSN)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
1724   },
1725 /* lmcp $crn64,$sdisp16($rma) */
1726   {
1727     MEP_INSN_LMCP16, "lmcp16", "lmcp", 32,
1728     { 0|A(OPTIONAL_CP64_INSN)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
1729   },
1730 /* sbcpa $crn,($rma+),$cdisp8 */
1731   {
1732     MEP_INSN_SBCPA, "sbcpa", "sbcpa", 32,
1733     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
1734   },
1735 /* lbcpa $crn,($rma+),$cdisp8 */
1736   {
1737     MEP_INSN_LBCPA, "lbcpa", "lbcpa", 32,
1738     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
1739   },
1740 /* shcpa $crn,($rma+),$cdisp8a2 */
1741   {
1742     MEP_INSN_SHCPA, "shcpa", "shcpa", 32,
1743     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
1744   },
1745 /* lhcpa $crn,($rma+),$cdisp8a2 */
1746   {
1747     MEP_INSN_LHCPA, "lhcpa", "lhcpa", 32,
1748     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
1749   },
1750 /* swcpa $crn,($rma+),$cdisp8a4 */
1751   {
1752     MEP_INSN_SWCPA, "swcpa", "swcpa", 32,
1753     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
1754   },
1755 /* lwcpa $crn,($rma+),$cdisp8a4 */
1756   {
1757     MEP_INSN_LWCPA, "lwcpa", "lwcpa", 32,
1758     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
1759   },
1760 /* smcpa $crn64,($rma+),$cdisp8a8 */
1761   {
1762     MEP_INSN_SMCPA, "smcpa", "smcpa", 32,
1763     { 0|A(OPTIONAL_CP64_INSN)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
1764   },
1765 /* lmcpa $crn64,($rma+),$cdisp8a8 */
1766   {
1767     MEP_INSN_LMCPA, "lmcpa", "lmcpa", 32,
1768     { 0|A(OPTIONAL_CP64_INSN)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
1769   },
1770 /* sbcpm0 $crn,($rma+),$cdisp8 */
1771   {
1772     MEP_INSN_SBCPM0, "sbcpm0", "sbcpm0", 32,
1773     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
1774   },
1775 /* lbcpm0 $crn,($rma+),$cdisp8 */
1776   {
1777     MEP_INSN_LBCPM0, "lbcpm0", "lbcpm0", 32,
1778     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
1779   },
1780 /* shcpm0 $crn,($rma+),$cdisp8a2 */
1781   {
1782     MEP_INSN_SHCPM0, "shcpm0", "shcpm0", 32,
1783     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
1784   },
1785 /* lhcpm0 $crn,($rma+),$cdisp8a2 */
1786   {
1787     MEP_INSN_LHCPM0, "lhcpm0", "lhcpm0", 32,
1788     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
1789   },
1790 /* swcpm0 $crn,($rma+),$cdisp8a4 */
1791   {
1792     MEP_INSN_SWCPM0, "swcpm0", "swcpm0", 32,
1793     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
1794   },
1795 /* lwcpm0 $crn,($rma+),$cdisp8a4 */
1796   {
1797     MEP_INSN_LWCPM0, "lwcpm0", "lwcpm0", 32,
1798     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
1799   },
1800 /* smcpm0 $crn64,($rma+),$cdisp8a8 */
1801   {
1802     MEP_INSN_SMCPM0, "smcpm0", "smcpm0", 32,
1803     { 0|A(OPTIONAL_CP64_INSN)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
1804   },
1805 /* lmcpm0 $crn64,($rma+),$cdisp8a8 */
1806   {
1807     MEP_INSN_LMCPM0, "lmcpm0", "lmcpm0", 32,
1808     { 0|A(OPTIONAL_CP64_INSN)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
1809   },
1810 /* sbcpm1 $crn,($rma+),$cdisp8 */
1811   {
1812     MEP_INSN_SBCPM1, "sbcpm1", "sbcpm1", 32,
1813     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
1814   },
1815 /* lbcpm1 $crn,($rma+),$cdisp8 */
1816   {
1817     MEP_INSN_LBCPM1, "lbcpm1", "lbcpm1", 32,
1818     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
1819   },
1820 /* shcpm1 $crn,($rma+),$cdisp8a2 */
1821   {
1822     MEP_INSN_SHCPM1, "shcpm1", "shcpm1", 32,
1823     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
1824   },
1825 /* lhcpm1 $crn,($rma+),$cdisp8a2 */
1826   {
1827     MEP_INSN_LHCPM1, "lhcpm1", "lhcpm1", 32,
1828     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
1829   },
1830 /* swcpm1 $crn,($rma+),$cdisp8a4 */
1831   {
1832     MEP_INSN_SWCPM1, "swcpm1", "swcpm1", 32,
1833     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
1834   },
1835 /* lwcpm1 $crn,($rma+),$cdisp8a4 */
1836   {
1837     MEP_INSN_LWCPM1, "lwcpm1", "lwcpm1", 32,
1838     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
1839   },
1840 /* smcpm1 $crn64,($rma+),$cdisp8a8 */
1841   {
1842     MEP_INSN_SMCPM1, "smcpm1", "smcpm1", 32,
1843     { 0|A(OPTIONAL_CP64_INSN)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
1844   },
1845 /* lmcpm1 $crn64,($rma+),$cdisp8a8 */
1846   {
1847     MEP_INSN_LMCPM1, "lmcpm1", "lmcpm1", 32,
1848     { 0|A(OPTIONAL_CP64_INSN)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
1849   },
1850 /* bcpeq $cccc,$pcrel17a2 */
1851   {
1852     MEP_INSN_BCPEQ, "bcpeq", "bcpeq", 32,
1853     { 0|A(RELAXABLE)|A(OPTIONAL_CP_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
1854   },
1855 /* bcpne $cccc,$pcrel17a2 */
1856   {
1857     MEP_INSN_BCPNE, "bcpne", "bcpne", 32,
1858     { 0|A(RELAXABLE)|A(OPTIONAL_CP_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
1859   },
1860 /* bcpat $cccc,$pcrel17a2 */
1861   {
1862     MEP_INSN_BCPAT, "bcpat", "bcpat", 32,
1863     { 0|A(RELAXABLE)|A(OPTIONAL_CP_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
1864   },
1865 /* bcpaf $cccc,$pcrel17a2 */
1866   {
1867     MEP_INSN_BCPAF, "bcpaf", "bcpaf", 32,
1868     { 0|A(RELAXABLE)|A(OPTIONAL_CP_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
1869   },
1870 /* synccp */
1871   {
1872     MEP_INSN_SYNCCP, "synccp", "synccp", 16,
1873     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
1874   },
1875 /* jsrv $rm */
1876   {
1877     MEP_INSN_JSRV, "jsrv", "jsrv", 16,
1878     { 0|A(OPTIONAL_CP_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
1879   },
1880 /* bsrv $pcrel24a2 */
1881   {
1882     MEP_INSN_BSRV, "bsrv", "bsrv", 32,
1883     { 0|A(OPTIONAL_CP_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
1884   },
1885 /* --unused-- */
1886   {
1887     MEP_INSN_SIM_SYSCALL, "sim-syscall", "--unused--", 16,
1888     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
1889   },
1890 /* --reserved-- */
1891   {
1892     MEP_INSN_RI_0, "ri-0", "--reserved--", 16,
1893     { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
1894   },
1895 /* --reserved-- */
1896   {
1897     MEP_INSN_RI_1, "ri-1", "--reserved--", 16,
1898     { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
1899   },
1900 /* --reserved-- */
1901   {
1902     MEP_INSN_RI_2, "ri-2", "--reserved--", 16,
1903     { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
1904   },
1905 /* --reserved-- */
1906   {
1907     MEP_INSN_RI_3, "ri-3", "--reserved--", 16,
1908     { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
1909   },
1910 /* --reserved-- */
1911   {
1912     MEP_INSN_RI_4, "ri-4", "--reserved--", 16,
1913     { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
1914   },
1915 /* --reserved-- */
1916   {
1917     MEP_INSN_RI_5, "ri-5", "--reserved--", 16,
1918     { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
1919   },
1920 /* --reserved-- */
1921   {
1922     MEP_INSN_RI_6, "ri-6", "--reserved--", 16,
1923     { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
1924   },
1925 /* --reserved-- */
1926   {
1927     MEP_INSN_RI_7, "ri-7", "--reserved--", 16,
1928     { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
1929   },
1930 /* --reserved-- */
1931   {
1932     MEP_INSN_RI_8, "ri-8", "--reserved--", 16,
1933     { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
1934   },
1935 /* --reserved-- */
1936   {
1937     MEP_INSN_RI_9, "ri-9", "--reserved--", 16,
1938     { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
1939   },
1940 /* --reserved-- */
1941   {
1942     MEP_INSN_RI_10, "ri-10", "--reserved--", 16,
1943     { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
1944   },
1945 /* --reserved-- */
1946   {
1947     MEP_INSN_RI_11, "ri-11", "--reserved--", 16,
1948     { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
1949   },
1950 /* --reserved-- */
1951   {
1952     MEP_INSN_RI_12, "ri-12", "--reserved--", 16,
1953     { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
1954   },
1955 /* --reserved-- */
1956   {
1957     MEP_INSN_RI_13, "ri-13", "--reserved--", 16,
1958     { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
1959   },
1960 /* --reserved-- */
1961   {
1962     MEP_INSN_RI_14, "ri-14", "--reserved--", 16,
1963     { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
1964   },
1965 /* --reserved-- */
1966   {
1967     MEP_INSN_RI_15, "ri-15", "--reserved--", 16,
1968     { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
1969   },
1970 /* --reserved-- */
1971   {
1972     MEP_INSN_RI_17, "ri-17", "--reserved--", 16,
1973     { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
1974   },
1975 /* --reserved-- */
1976   {
1977     MEP_INSN_RI_20, "ri-20", "--reserved--", 16,
1978     { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
1979   },
1980 /* --reserved-- */
1981   {
1982     MEP_INSN_RI_21, "ri-21", "--reserved--", 16,
1983     { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
1984   },
1985 /* --reserved-- */
1986   {
1987     MEP_INSN_RI_22, "ri-22", "--reserved--", 16,
1988     { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
1989   },
1990 /* --reserved-- */
1991   {
1992     MEP_INSN_RI_23, "ri-23", "--reserved--", 16,
1993     { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
1994   },
1995 /* --reserved-- */
1996   {
1997     MEP_INSN_RI_24, "ri-24", "--reserved--", 16,
1998     { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
1999   },
2000 /* --reserved-- */
2001   {
2002     MEP_INSN_RI_25, "ri-25", "--reserved--", 16,
2003     { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
2004   },
2005 /* --reserved-- */
2006   {
2007     MEP_INSN_RI_26, "ri-26", "--reserved--", 16,
2008     { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
2009   },
2010 /* --reserved-- */
2011   {
2012     MEP_INSN_RI_16, "ri-16", "--reserved--", 16,
2013     { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
2014   },
2015 /* --reserved-- */
2016   {
2017     MEP_INSN_RI_18, "ri-18", "--reserved--", 16,
2018     { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
2019   },
2020 /* --reserved-- */
2021   {
2022     MEP_INSN_RI_19, "ri-19", "--reserved--", 16,
2023     { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
2024   },
2025 };
2026
2027 #undef OP
2028 #undef A
2029
2030 /* Initialize anything needed to be done once, before any cpu_open call.  */
2031
2032 static void
2033 init_tables (void)
2034 {
2035 }
2036
2037 static const CGEN_MACH * lookup_mach_via_bfd_name (const CGEN_MACH *, const char *);
2038 static void build_hw_table      (CGEN_CPU_TABLE *);
2039 static void build_ifield_table  (CGEN_CPU_TABLE *);
2040 static void build_operand_table (CGEN_CPU_TABLE *);
2041 static void build_insn_table    (CGEN_CPU_TABLE *);
2042 static void mep_cgen_rebuild_tables (CGEN_CPU_TABLE *);
2043
2044 /* Subroutine of mep_cgen_cpu_open to look up a mach via its bfd name.  */
2045
2046 static const CGEN_MACH *
2047 lookup_mach_via_bfd_name (const CGEN_MACH *table, const char *name)
2048 {
2049   while (table->name)
2050     {
2051       if (strcmp (name, table->bfd_name) == 0)
2052         return table;
2053       ++table;
2054     }
2055   abort ();
2056 }
2057
2058 /* Subroutine of mep_cgen_cpu_open to build the hardware table.  */
2059
2060 static void
2061 build_hw_table (CGEN_CPU_TABLE *cd)
2062 {
2063   int i;
2064   int machs = cd->machs;
2065   const CGEN_HW_ENTRY *init = & mep_cgen_hw_table[0];
2066   /* MAX_HW is only an upper bound on the number of selected entries.
2067      However each entry is indexed by it's enum so there can be holes in
2068      the table.  */
2069   const CGEN_HW_ENTRY **selected =
2070     (const CGEN_HW_ENTRY **) xmalloc (MAX_HW * sizeof (CGEN_HW_ENTRY *));
2071
2072   cd->hw_table.init_entries = init;
2073   cd->hw_table.entry_size = sizeof (CGEN_HW_ENTRY);
2074   memset (selected, 0, MAX_HW * sizeof (CGEN_HW_ENTRY *));
2075   /* ??? For now we just use machs to determine which ones we want.  */
2076   for (i = 0; init[i].name != NULL; ++i)
2077     if (CGEN_HW_ATTR_VALUE (&init[i], CGEN_HW_MACH)
2078         & machs)
2079       selected[init[i].type] = &init[i];
2080   cd->hw_table.entries = selected;
2081   cd->hw_table.num_entries = MAX_HW;
2082 }
2083
2084 /* Subroutine of mep_cgen_cpu_open to build the hardware table.  */
2085
2086 static void
2087 build_ifield_table (CGEN_CPU_TABLE *cd)
2088 {
2089   cd->ifld_table = & mep_cgen_ifld_table[0];
2090 }
2091
2092 /* Subroutine of mep_cgen_cpu_open to build the hardware table.  */
2093
2094 static void
2095 build_operand_table (CGEN_CPU_TABLE *cd)
2096 {
2097   int i;
2098   int machs = cd->machs;
2099   const CGEN_OPERAND *init = & mep_cgen_operand_table[0];
2100   /* MAX_OPERANDS is only an upper bound on the number of selected entries.
2101      However each entry is indexed by it's enum so there can be holes in
2102      the table.  */
2103   const CGEN_OPERAND **selected = xmalloc (MAX_OPERANDS * sizeof (* selected));
2104
2105   cd->operand_table.init_entries = init;
2106   cd->operand_table.entry_size = sizeof (CGEN_OPERAND);
2107   memset (selected, 0, MAX_OPERANDS * sizeof (CGEN_OPERAND *));
2108   /* ??? For now we just use mach to determine which ones we want.  */
2109   for (i = 0; init[i].name != NULL; ++i)
2110     if (CGEN_OPERAND_ATTR_VALUE (&init[i], CGEN_OPERAND_MACH)
2111         & machs)
2112       selected[init[i].type] = &init[i];
2113   cd->operand_table.entries = selected;
2114   cd->operand_table.num_entries = MAX_OPERANDS;
2115 }
2116
2117 /* Subroutine of mep_cgen_cpu_open to build the hardware table.
2118    ??? This could leave out insns not supported by the specified mach/isa,
2119    but that would cause errors like "foo only supported by bar" to become
2120    "unknown insn", so for now we include all insns and require the app to
2121    do the checking later.
2122    ??? On the other hand, parsing of such insns may require their hardware or
2123    operand elements to be in the table [which they mightn't be].  */
2124
2125 static void
2126 build_insn_table (CGEN_CPU_TABLE *cd)
2127 {
2128   int i;
2129   const CGEN_IBASE *ib = & mep_cgen_insn_table[0];
2130   CGEN_INSN *insns = xmalloc (MAX_INSNS * sizeof (CGEN_INSN));
2131
2132   memset (insns, 0, MAX_INSNS * sizeof (CGEN_INSN));
2133   for (i = 0; i < MAX_INSNS; ++i)
2134     insns[i].base = &ib[i];
2135   cd->insn_table.init_entries = insns;
2136   cd->insn_table.entry_size = sizeof (CGEN_IBASE);
2137   cd->insn_table.num_init_entries = MAX_INSNS;
2138 }
2139
2140 /* Subroutine of mep_cgen_cpu_open to rebuild the tables.  */
2141
2142 static void
2143 mep_cgen_rebuild_tables (CGEN_CPU_TABLE *cd)
2144 {
2145   int i;
2146   CGEN_BITSET *isas = cd->isas;
2147   unsigned int machs = cd->machs;
2148
2149   cd->int_insn_p = CGEN_INT_INSN_P;
2150
2151   /* Data derived from the isa spec.  */
2152 #define UNSET (CGEN_SIZE_UNKNOWN + 1)
2153   cd->default_insn_bitsize = UNSET;
2154   cd->base_insn_bitsize = UNSET;
2155   cd->min_insn_bitsize = 65535; /* Some ridiculously big number.  */
2156   cd->max_insn_bitsize = 0;
2157   for (i = 0; i < MAX_ISAS; ++i)
2158     if (cgen_bitset_contains (isas, i))
2159       {
2160         const CGEN_ISA *isa = & mep_cgen_isa_table[i];
2161
2162         /* Default insn sizes of all selected isas must be
2163            equal or we set the result to 0, meaning "unknown".  */
2164         if (cd->default_insn_bitsize == UNSET)
2165           cd->default_insn_bitsize = isa->default_insn_bitsize;
2166         else if (isa->default_insn_bitsize == cd->default_insn_bitsize)
2167           ; /* This is ok.  */
2168         else
2169           cd->default_insn_bitsize = CGEN_SIZE_UNKNOWN;
2170
2171         /* Base insn sizes of all selected isas must be equal
2172            or we set the result to 0, meaning "unknown".  */
2173         if (cd->base_insn_bitsize == UNSET)
2174           cd->base_insn_bitsize = isa->base_insn_bitsize;
2175         else if (isa->base_insn_bitsize == cd->base_insn_bitsize)
2176           ; /* This is ok.  */
2177         else
2178           cd->base_insn_bitsize = CGEN_SIZE_UNKNOWN;
2179
2180         /* Set min,max insn sizes.  */
2181         if (isa->min_insn_bitsize < cd->min_insn_bitsize)
2182           cd->min_insn_bitsize = isa->min_insn_bitsize;
2183         if (isa->max_insn_bitsize > cd->max_insn_bitsize)
2184           cd->max_insn_bitsize = isa->max_insn_bitsize;
2185       }
2186
2187   /* Data derived from the mach spec.  */
2188   for (i = 0; i < MAX_MACHS; ++i)
2189     if (((1 << i) & machs) != 0)
2190       {
2191         const CGEN_MACH *mach = & mep_cgen_mach_table[i];
2192
2193         if (mach->insn_chunk_bitsize != 0)
2194         {
2195           if (cd->insn_chunk_bitsize != 0 && cd->insn_chunk_bitsize != mach->insn_chunk_bitsize)
2196             {
2197               fprintf (stderr, "mep_cgen_rebuild_tables: conflicting insn-chunk-bitsize values: `%d' vs. `%d'\n",
2198                        cd->insn_chunk_bitsize, mach->insn_chunk_bitsize);
2199               abort ();
2200             }
2201
2202           cd->insn_chunk_bitsize = mach->insn_chunk_bitsize;
2203         }
2204       }
2205
2206   /* Determine which hw elements are used by MACH.  */
2207   build_hw_table (cd);
2208
2209   /* Build the ifield table.  */
2210   build_ifield_table (cd);
2211
2212   /* Determine which operands are used by MACH/ISA.  */
2213   build_operand_table (cd);
2214
2215   /* Build the instruction table.  */
2216   build_insn_table (cd);
2217 }
2218
2219 /* Initialize a cpu table and return a descriptor.
2220    It's much like opening a file, and must be the first function called.
2221    The arguments are a set of (type/value) pairs, terminated with
2222    CGEN_CPU_OPEN_END.
2223
2224    Currently supported values:
2225    CGEN_CPU_OPEN_ISAS:    bitmap of values in enum isa_attr
2226    CGEN_CPU_OPEN_MACHS:   bitmap of values in enum mach_attr
2227    CGEN_CPU_OPEN_BFDMACH: specify 1 mach using bfd name
2228    CGEN_CPU_OPEN_ENDIAN:  specify endian choice
2229    CGEN_CPU_OPEN_END:     terminates arguments
2230
2231    ??? Simultaneous multiple isas might not make sense, but it's not (yet)
2232    precluded.
2233
2234    ??? We only support ISO C stdargs here, not K&R.
2235    Laziness, plus experiment to see if anything requires K&R - eventually
2236    K&R will no longer be supported - e.g. GDB is currently trying this.  */
2237
2238 CGEN_CPU_DESC
2239 mep_cgen_cpu_open (enum cgen_cpu_open_arg arg_type, ...)
2240 {
2241   CGEN_CPU_TABLE *cd = (CGEN_CPU_TABLE *) xmalloc (sizeof (CGEN_CPU_TABLE));
2242   static int init_p;
2243   CGEN_BITSET *isas = 0;  /* 0 = "unspecified" */
2244   unsigned int machs = 0; /* 0 = "unspecified" */
2245   enum cgen_endian endian = CGEN_ENDIAN_UNKNOWN;
2246   va_list ap;
2247
2248   if (! init_p)
2249     {
2250       init_tables ();
2251       init_p = 1;
2252     }
2253
2254   memset (cd, 0, sizeof (*cd));
2255
2256   va_start (ap, arg_type);
2257   while (arg_type != CGEN_CPU_OPEN_END)
2258     {
2259       switch (arg_type)
2260         {
2261         case CGEN_CPU_OPEN_ISAS :
2262           isas = va_arg (ap, CGEN_BITSET *);
2263           break;
2264         case CGEN_CPU_OPEN_MACHS :
2265           machs = va_arg (ap, unsigned int);
2266           break;
2267         case CGEN_CPU_OPEN_BFDMACH :
2268           {
2269             const char *name = va_arg (ap, const char *);
2270             const CGEN_MACH *mach =
2271               lookup_mach_via_bfd_name (mep_cgen_mach_table, name);
2272
2273             machs |= 1 << mach->num;
2274             break;
2275           }
2276         case CGEN_CPU_OPEN_ENDIAN :
2277           endian = va_arg (ap, enum cgen_endian);
2278           break;
2279         default :
2280           fprintf (stderr, "mep_cgen_cpu_open: unsupported argument `%d'\n",
2281                    arg_type);
2282           abort (); /* ??? return NULL? */
2283         }
2284       arg_type = va_arg (ap, enum cgen_cpu_open_arg);
2285     }
2286   va_end (ap);
2287
2288   /* Mach unspecified means "all".  */
2289   if (machs == 0)
2290     machs = (1 << MAX_MACHS) - 1;
2291   /* Base mach is always selected.  */
2292   machs |= 1;
2293   if (endian == CGEN_ENDIAN_UNKNOWN)
2294     {
2295       /* ??? If target has only one, could have a default.  */
2296       fprintf (stderr, "mep_cgen_cpu_open: no endianness specified\n");
2297       abort ();
2298     }
2299
2300   cd->isas = cgen_bitset_copy (isas);
2301   cd->machs = machs;
2302   cd->endian = endian;
2303   /* FIXME: for the sparc case we can determine insn-endianness statically.
2304      The worry here is where both data and insn endian can be independently
2305      chosen, in which case this function will need another argument.
2306      Actually, will want to allow for more arguments in the future anyway.  */
2307   cd->insn_endian = endian;
2308
2309   /* Table (re)builder.  */
2310   cd->rebuild_tables = mep_cgen_rebuild_tables;
2311   mep_cgen_rebuild_tables (cd);
2312
2313   /* Default to not allowing signed overflow.  */
2314   cd->signed_overflow_ok_p = 0;
2315
2316   return (CGEN_CPU_DESC) cd;
2317 }
2318
2319 /* Cover fn to mep_cgen_cpu_open to handle the simple case of 1 isa, 1 mach.
2320    MACH_NAME is the bfd name of the mach.  */
2321
2322 CGEN_CPU_DESC
2323 mep_cgen_cpu_open_1 (const char *mach_name, enum cgen_endian endian)
2324 {
2325   return mep_cgen_cpu_open (CGEN_CPU_OPEN_BFDMACH, mach_name,
2326                                CGEN_CPU_OPEN_ENDIAN, endian,
2327                                CGEN_CPU_OPEN_END);
2328 }
2329
2330 /* Close a cpu table.
2331    ??? This can live in a machine independent file, but there's currently
2332    no place to put this file (there's no libcgen).  libopcodes is the wrong
2333    place as some simulator ports use this but they don't use libopcodes.  */
2334
2335 void
2336 mep_cgen_cpu_close (CGEN_CPU_DESC cd)
2337 {
2338   unsigned int i;
2339   const CGEN_INSN *insns;
2340
2341   if (cd->macro_insn_table.init_entries)
2342     {
2343       insns = cd->macro_insn_table.init_entries;
2344       for (i = 0; i < cd->macro_insn_table.num_init_entries; ++i, ++insns)
2345         if (CGEN_INSN_RX ((insns)))
2346           regfree (CGEN_INSN_RX (insns));
2347     }
2348
2349   if (cd->insn_table.init_entries)
2350     {
2351       insns = cd->insn_table.init_entries;
2352       for (i = 0; i < cd->insn_table.num_init_entries; ++i, ++insns)
2353         if (CGEN_INSN_RX (insns))
2354           regfree (CGEN_INSN_RX (insns));
2355     }
2356
2357   if (cd->macro_insn_table.init_entries)
2358     free ((CGEN_INSN *) cd->macro_insn_table.init_entries);
2359
2360   if (cd->insn_table.init_entries)
2361     free ((CGEN_INSN *) cd->insn_table.init_entries);
2362
2363   if (cd->hw_table.entries)
2364     free ((CGEN_HW_ENTRY *) cd->hw_table.entries);
2365
2366   if (cd->operand_table.entries)
2367     free ((CGEN_HW_ENTRY *) cd->operand_table.entries);
2368
2369   free (cd);
2370 }
2371