1e3577cec32dc90a500e7101f485cf4eb9ee81f0
1 /* Print mips instructions for GDB, the GNU debugger, or for objdump.
2 Copyright (c) 1989, 91-97, 1998 Free Software Foundation, Inc.
3 Contributed by Nobuyuki Hikichi(hikichi@sra.co.jp).
5 This file is part of GDB, GAS, and the GNU binutils.
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2 of the License, or
10 (at your option) any later version.
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this program; if not, write to the Free Software
19 Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
24 #include "opcode/mips.h"
27 /* FIXME: These are needed to figure out if the code is mips16 or
28 not. The low bit of the address is often a good indicator. No
29 symbol table is available when this code runs out in an embedded
30 system as when it is used for disassembler support in a monitor. */
32 #if !defined(EMBEDDED_ENV)
33 #define SYMTAB_AVAILABLE 1
38 static int print_insn_mips16
PARAMS ((bfd_vma
, struct disassemble_info
*));
39 static void print_mips16_insn_arg
40 PARAMS ((int, const struct mips_opcode
*, int, boolean
, int, bfd_vma
,
41 struct disassemble_info
*));
43 /* Mips instructions are never longer than this many bytes. */
46 static void print_insn_arg
PARAMS ((const char *, unsigned long, bfd_vma
,
47 struct disassemble_info
*));
48 static int _print_insn_mips
PARAMS ((bfd_vma
, unsigned long int,
49 struct disassemble_info
*));
52 /* FIXME: This should be shared with gdb somehow. */
53 #define REGISTER_NAMES \
54 { "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3", \
55 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7", \
56 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", \
57 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra", \
58 "sr", "lo", "hi", "bad", "cause","pc", \
59 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", \
60 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", \
61 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",\
62 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",\
63 "fsr", "fir", "fp", "inx", "rand", "tlblo","ctxt", "tlbhi",\
67 static CONST
char * CONST reg_names
[] = REGISTER_NAMES
;
69 /* The mips16 register names. */
70 static const char * const mips16_reg_names
[] =
72 "s0", "s1", "v0", "v1", "a0", "a1", "a2", "a3"
77 print_insn_arg (d
, l
, pc
, info
)
79 register unsigned long int l
;
81 struct disassemble_info
*info
;
90 (*info
->fprintf_func
) (info
->stream
, "%c", *d
);
97 (*info
->fprintf_func
) (info
->stream
, "$%s",
98 reg_names
[(l
>> OP_SH_RS
) & OP_MASK_RS
]);
103 (*info
->fprintf_func
) (info
->stream
, "$%s",
104 reg_names
[(l
>> OP_SH_RT
) & OP_MASK_RT
]);
109 (*info
->fprintf_func
) (info
->stream
, "0x%x",
110 (l
>> OP_SH_IMMEDIATE
) & OP_MASK_IMMEDIATE
);
113 case 'j': /* same as i, but sign-extended */
115 delta
= (l
>> OP_SH_DELTA
) & OP_MASK_DELTA
;
118 (*info
->fprintf_func
) (info
->stream
, "%d",
123 (*info
->fprintf_func
) (info
->stream
, "0x%x",
124 (unsigned int) ((l
>> OP_SH_PREFX
)
129 (*info
->fprintf_func
) (info
->stream
, "0x%x",
130 (unsigned int) ((l
>> OP_SH_CACHE
)
135 (*info
->print_address_func
)
136 (((pc
& 0xF0000000) | (((l
>> OP_SH_TARGET
) & OP_MASK_TARGET
) << 2)),
141 /* sign extend the displacement */
142 delta
= (l
>> OP_SH_DELTA
) & OP_MASK_DELTA
;
145 (*info
->print_address_func
)
146 ((delta
<< 2) + pc
+ 4,
151 (*info
->fprintf_func
) (info
->stream
, "$%s",
152 reg_names
[(l
>> OP_SH_RD
) & OP_MASK_RD
]);
156 (*info
->fprintf_func
) (info
->stream
, "$%s", reg_names
[0]);
160 (*info
->fprintf_func
) (info
->stream
, "0x%x",
161 (l
>> OP_SH_SHAMT
) & OP_MASK_SHAMT
);
165 (*info
->fprintf_func
) (info
->stream
, "0x%x",
166 (l
>> OP_SH_CODE
) & OP_MASK_CODE
);
171 (*info
->fprintf_func
) (info
->stream
, "0x%x",
172 (l
>> OP_SH_CODE2
) & OP_MASK_CODE2
);
176 (*info
->fprintf_func
) (info
->stream
, "0x%x",
177 (l
>> OP_SH_COPZ
) & OP_MASK_COPZ
);
181 (*info
->fprintf_func
) (info
->stream
, "0x%x",
182 (l
>> OP_SH_SYSCALL
) & OP_MASK_SYSCALL
);
187 (*info
->fprintf_func
) (info
->stream
, "$f%d",
188 (l
>> OP_SH_FS
) & OP_MASK_FS
);
194 (*info
->fprintf_func
) (info
->stream
, "$f%d",
195 (l
>> OP_SH_FT
) & OP_MASK_FT
);
199 (*info
->fprintf_func
) (info
->stream
, "$f%d",
200 (l
>> OP_SH_FD
) & OP_MASK_FD
);
204 (*info
->fprintf_func
) (info
->stream
, "$f%d",
205 (l
>> OP_SH_FR
) & OP_MASK_FR
);
209 (*info
->fprintf_func
) (info
->stream
, "$%d",
210 (l
>> OP_SH_RT
) & OP_MASK_RT
);
214 (*info
->fprintf_func
) (info
->stream
, "$%d",
215 (l
>> OP_SH_RD
) & OP_MASK_RD
);
219 (*info
->fprintf_func
) (info
->stream
, "$fcc%d",
220 (l
>> OP_SH_BCC
) & OP_MASK_BCC
);
224 (*info
->fprintf_func
) (info
->stream
, "$fcc%d",
225 (l
>> OP_SH_CCC
) & OP_MASK_CCC
);
229 (*info
->fprintf_func
) (info
->stream
, "%d",
230 (l
>> OP_SH_PERFREG
) & OP_MASK_PERFREG
);
235 /* xgettext:c-format */
236 (*info
->fprintf_func
) (info
->stream
,
237 _("# internal error, undefined modifier(%c)"),
245 /* Figure out the MIPS ISA and CPU based on the machine number.
246 FIXME: What does this have to do with SYMTAB_AVAILABLE? */
249 set_mips_isa_type (mach
, isa
, cputype
)
254 int target_processor
= 0;
259 case bfd_mach_mips3000
:
260 target_processor
= 3000;
263 case bfd_mach_mips3900
:
264 target_processor
= 3900;
267 case bfd_mach_mips4000
:
268 target_processor
= 4000;
271 case bfd_mach_mips4010
:
272 target_processor
= 4010;
275 case bfd_mach_mips4100
:
276 target_processor
= 4100;
279 case bfd_mach_mips4111
:
280 target_processor
= 4100;
283 case bfd_mach_mips4300
:
284 target_processor
= 4300;
287 case bfd_mach_mips4400
:
288 target_processor
= 4400;
291 case bfd_mach_mips4600
:
292 target_processor
= 4600;
295 case bfd_mach_mips4650
:
296 target_processor
= 4650;
299 case bfd_mach_mips5000
:
300 target_processor
= 5000;
303 case bfd_mach_mips6000
:
304 target_processor
= 6000;
307 case bfd_mach_mips8000
:
308 target_processor
= 8000;
311 case bfd_mach_mips10000
:
312 target_processor
= 10000;
315 case bfd_mach_mips16
:
316 target_processor
= 16;
320 target_processor
= 3000;
327 *cputype
= target_processor
;
330 #endif /* SYMTAB_AVAILABLE */
332 /* Print the mips instruction at address MEMADDR in debugged memory,
333 on using INFO. Returns length of the instruction, in bytes, which is
334 always 4. BIGENDIAN must be 1 if this is big-endian code, 0 if
335 this is little-endian code. */
338 _print_insn_mips (memaddr
, word
, info
)
340 unsigned long int word
;
341 struct disassemble_info
*info
;
343 register const struct mips_opcode
*op
;
344 int target_processor
, mips_isa
;
345 static boolean init
= 0;
346 static const struct mips_opcode
*mips_hash
[OP_MASK_OP
+ 1];
348 /* Build a hash table to shorten the search time. */
353 for (i
= 0; i
<= OP_MASK_OP
; i
++)
355 for (op
= mips_opcodes
; op
< &mips_opcodes
[NUMOPCODES
]; op
++)
357 if (op
->pinfo
== INSN_MACRO
)
359 if (i
== ((op
->match
>> OP_SH_OP
) & OP_MASK_OP
))
370 #if ! SYMTAB_AVAILABLE
371 /* This is running out on a target machine, not in a host tool.
372 FIXME: Where does mips_target_info come from? */
373 target_processor
= mips_target_info
.processor
;
374 mips_isa
= mips_target_info
.isa
;
376 set_mips_isa_type (info
->mach
, &mips_isa
, &target_processor
);
379 info
->bytes_per_chunk
= 4;
380 info
->display_endian
= info
->endian
;
382 op
= mips_hash
[(word
>> OP_SH_OP
) & OP_MASK_OP
];
385 for (; op
< &mips_opcodes
[NUMOPCODES
]; op
++)
387 if (op
->pinfo
!= INSN_MACRO
&& (word
& op
->mask
) == op
->match
)
389 register const char *d
;
392 if ((op
->membership
& INSN_ISA
) == INSN_ISA1
)
394 else if ((op
->membership
& INSN_ISA
) == INSN_ISA2
)
396 else if ((op
->membership
& INSN_ISA
) == INSN_ISA3
)
398 else if ((op
->membership
& INSN_ISA
) == INSN_ISA4
)
403 if (insn_isa
> mips_isa
404 && (target_processor
== 4650
405 && op
->membership
& INSN_4650
) == 0
406 && (target_processor
== 4010
407 && op
->membership
& INSN_4010
) == 0
408 && (target_processor
== 4100
409 && op
->membership
& INSN_4100
) == 0
410 && (target_processor
== 3900
411 && op
->membership
& INSN_3900
) == 0)
414 (*info
->fprintf_func
) (info
->stream
, "%s", op
->name
);
417 if (d
!= NULL
&& *d
!= '\0')
419 (*info
->fprintf_func
) (info
->stream
, "\t");
420 for (; *d
!= '\0'; d
++)
421 print_insn_arg (d
, word
, memaddr
, info
);
429 /* Handle undefined instructions. */
430 (*info
->fprintf_func
) (info
->stream
, "0x%x", word
);
435 /* In an environment where we do not know the symbol type of the
436 instruction we are forced to assume that the low order bit of the
437 instructions' address may mark it as a mips16 instruction. If we
438 are single stepping, or the pc is within the disassembled function,
439 this works. Otherwise, we need a clue. Sometimes. */
442 print_insn_big_mips (memaddr
, info
)
444 struct disassemble_info
*info
;
450 /* FIXME: If odd address, this is CLEARLY a mips 16 instruction. */
451 /* Only a few tools will work this way. */
453 return print_insn_mips16 (memaddr
, info
);
458 || (info
->flavour
== bfd_target_elf_flavour
459 && info
->symbols
!= NULL
460 && ((*(elf_symbol_type
**) info
->symbols
)->internal_elf_sym
.st_other
462 return print_insn_mips16 (memaddr
, info
);
465 status
= (*info
->read_memory_func
) (memaddr
, buffer
, 4, info
);
467 return _print_insn_mips (memaddr
, (unsigned long) bfd_getb32 (buffer
),
471 (*info
->memory_error_func
) (status
, memaddr
, info
);
477 print_insn_little_mips (memaddr
, info
)
479 struct disassemble_info
*info
;
487 return print_insn_mips16 (memaddr
, info
);
492 || (info
->flavour
== bfd_target_elf_flavour
493 && info
->symbols
!= NULL
494 && ((*(elf_symbol_type
**) info
->symbols
)->internal_elf_sym
.st_other
496 return print_insn_mips16 (memaddr
, info
);
499 status
= (*info
->read_memory_func
) (memaddr
, buffer
, 4, info
);
501 return _print_insn_mips (memaddr
, (unsigned long) bfd_getl32 (buffer
),
505 (*info
->memory_error_func
) (status
, memaddr
, info
);
510 /* Disassemble mips16 instructions. */
513 print_insn_mips16 (memaddr
, info
)
515 struct disassemble_info
*info
;
523 const struct mips_opcode
*op
, *opend
;
525 info
->bytes_per_chunk
= 2;
526 info
->display_endian
= info
->endian
;
528 info
->insn_info_valid
= 1;
529 info
->branch_delay_insns
= 0;
531 info
->insn_type
= dis_nonbranch
;
535 status
= (*info
->read_memory_func
) (memaddr
, buffer
, 2, info
);
538 (*info
->memory_error_func
) (status
, memaddr
, info
);
544 if (info
->endian
== BFD_ENDIAN_BIG
)
545 insn
= bfd_getb16 (buffer
);
547 insn
= bfd_getl16 (buffer
);
549 /* Handle the extend opcode specially. */
551 if ((insn
& 0xf800) == 0xf000)
554 extend
= insn
& 0x7ff;
558 status
= (*info
->read_memory_func
) (memaddr
, buffer
, 2, info
);
561 (*info
->fprintf_func
) (info
->stream
, "extend 0x%x",
562 (unsigned int) extend
);
563 (*info
->memory_error_func
) (status
, memaddr
, info
);
567 if (info
->endian
== BFD_ENDIAN_BIG
)
568 insn
= bfd_getb16 (buffer
);
570 insn
= bfd_getl16 (buffer
);
572 /* Check for an extend opcode followed by an extend opcode. */
573 if ((insn
& 0xf800) == 0xf000)
575 (*info
->fprintf_func
) (info
->stream
, "extend 0x%x",
576 (unsigned int) extend
);
577 info
->insn_type
= dis_noninsn
;
584 /* FIXME: Should probably use a hash table on the major opcode here. */
586 opend
= mips16_opcodes
+ bfd_mips16_num_opcodes
;
587 for (op
= mips16_opcodes
; op
< opend
; op
++)
589 if (op
->pinfo
!= INSN_MACRO
&& (insn
& op
->mask
) == op
->match
)
593 if (strchr (op
->args
, 'a') != NULL
)
597 (*info
->fprintf_func
) (info
->stream
, "extend 0x%x",
598 (unsigned int) extend
);
599 info
->insn_type
= dis_noninsn
;
607 status
= (*info
->read_memory_func
) (memaddr
, buffer
, 2,
612 if (info
->endian
== BFD_ENDIAN_BIG
)
613 extend
= bfd_getb16 (buffer
);
615 extend
= bfd_getl16 (buffer
);
620 (*info
->fprintf_func
) (info
->stream
, "%s", op
->name
);
621 if (op
->args
[0] != '\0')
622 (*info
->fprintf_func
) (info
->stream
, "\t");
624 for (s
= op
->args
; *s
!= '\0'; s
++)
628 && (((insn
>> MIPS16OP_SH_RX
) & MIPS16OP_MASK_RX
)
629 == ((insn
>> MIPS16OP_SH_RY
) & MIPS16OP_MASK_RY
)))
631 /* Skip the register and the comma. */
637 && (((insn
>> MIPS16OP_SH_RZ
) & MIPS16OP_MASK_RZ
)
638 == ((insn
>> MIPS16OP_SH_RX
) & MIPS16OP_MASK_RX
)))
640 /* Skip the register and the comma. */
644 print_mips16_insn_arg (*s
, op
, insn
, use_extend
, extend
, memaddr
,
648 if ((op
->pinfo
& INSN_UNCOND_BRANCH_DELAY
) != 0)
650 info
->branch_delay_insns
= 1;
651 if (info
->insn_type
!= dis_jsr
)
652 info
->insn_type
= dis_branch
;
660 (*info
->fprintf_func
) (info
->stream
, "0x%x", extend
| 0xf000);
661 (*info
->fprintf_func
) (info
->stream
, "0x%x", insn
);
662 info
->insn_type
= dis_noninsn
;
667 /* Disassemble an operand for a mips16 instruction. */
670 print_mips16_insn_arg (type
, op
, l
, use_extend
, extend
, memaddr
, info
)
672 const struct mips_opcode
*op
;
677 struct disassemble_info
*info
;
684 (*info
->fprintf_func
) (info
->stream
, "%c", type
);
689 (*info
->fprintf_func
) (info
->stream
, "$%s",
690 mips16_reg_names
[((l
>> MIPS16OP_SH_RY
)
691 & MIPS16OP_MASK_RY
)]);
696 (*info
->fprintf_func
) (info
->stream
, "$%s",
697 mips16_reg_names
[((l
>> MIPS16OP_SH_RX
)
698 & MIPS16OP_MASK_RX
)]);
702 (*info
->fprintf_func
) (info
->stream
, "$%s",
703 mips16_reg_names
[((l
>> MIPS16OP_SH_RZ
)
704 & MIPS16OP_MASK_RZ
)]);
708 (*info
->fprintf_func
) (info
->stream
, "$%s",
709 mips16_reg_names
[((l
>> MIPS16OP_SH_MOVE32Z
)
710 & MIPS16OP_MASK_MOVE32Z
)]);
714 (*info
->fprintf_func
) (info
->stream
, "$%s", reg_names
[0]);
718 (*info
->fprintf_func
) (info
->stream
, "$%s", reg_names
[29]);
722 (*info
->fprintf_func
) (info
->stream
, "$pc");
726 (*info
->fprintf_func
) (info
->stream
, "$%s", reg_names
[31]);
730 (*info
->fprintf_func
) (info
->stream
, "$%s",
731 reg_names
[((l
>> MIPS16OP_SH_REGR32
)
732 & MIPS16OP_MASK_REGR32
)]);
736 (*info
->fprintf_func
) (info
->stream
, "$%s",
737 reg_names
[MIPS16OP_EXTRACT_REG32R (l
)]);
763 int immed
, nbits
, shift
, signedp
, extbits
, pcrel
, extu
, branch
;
775 immed
= (l
>> MIPS16OP_SH_RZ
) & MIPS16OP_MASK_RZ
;
781 immed
= (l
>> MIPS16OP_SH_RX
) & MIPS16OP_MASK_RX
;
787 immed
= (l
>> MIPS16OP_SH_RZ
) & MIPS16OP_MASK_RZ
;
793 immed
= (l
>> MIPS16OP_SH_RX
) & MIPS16OP_MASK_RX
;
799 immed
= (l
>> MIPS16OP_SH_IMM4
) & MIPS16OP_MASK_IMM4
;
805 immed
= (l
>> MIPS16OP_SH_IMM5
) & MIPS16OP_MASK_IMM5
;
806 info
->insn_type
= dis_dref
;
812 immed
= (l
>> MIPS16OP_SH_IMM5
) & MIPS16OP_MASK_IMM5
;
813 info
->insn_type
= dis_dref
;
819 immed
= (l
>> MIPS16OP_SH_IMM5
) & MIPS16OP_MASK_IMM5
;
820 if ((op
->pinfo
& MIPS16_INSN_READ_PC
) == 0
821 && (op
->pinfo
& MIPS16_INSN_READ_SP
) == 0)
823 info
->insn_type
= dis_dref
;
830 immed
= (l
>> MIPS16OP_SH_IMM5
) & MIPS16OP_MASK_IMM5
;
831 info
->insn_type
= dis_dref
;
836 immed
= (l
>> MIPS16OP_SH_IMM5
) & MIPS16OP_MASK_IMM5
;
841 immed
= (l
>> MIPS16OP_SH_IMM6
) & MIPS16OP_MASK_IMM6
;
845 immed
= (l
>> MIPS16OP_SH_IMM8
) & MIPS16OP_MASK_IMM8
;
850 immed
= (l
>> MIPS16OP_SH_IMM8
) & MIPS16OP_MASK_IMM8
;
851 /* FIXME: This might be lw, or it might be addiu to $sp or
852 $pc. We assume it's load. */
853 info
->insn_type
= dis_dref
;
859 immed
= (l
>> MIPS16OP_SH_IMM8
) & MIPS16OP_MASK_IMM8
;
860 info
->insn_type
= dis_dref
;
865 immed
= (l
>> MIPS16OP_SH_IMM8
) & MIPS16OP_MASK_IMM8
;
870 immed
= (l
>> MIPS16OP_SH_IMM8
) & MIPS16OP_MASK_IMM8
;
876 immed
= (l
>> MIPS16OP_SH_IMM8
) & MIPS16OP_MASK_IMM8
;
881 immed
= (l
>> MIPS16OP_SH_IMM8
) & MIPS16OP_MASK_IMM8
;
885 info
->insn_type
= dis_condbranch
;
889 immed
= (l
>> MIPS16OP_SH_IMM11
) & MIPS16OP_MASK_IMM11
;
893 info
->insn_type
= dis_branch
;
898 immed
= (l
>> MIPS16OP_SH_IMM8
) & MIPS16OP_MASK_IMM8
;
900 /* FIXME: This can be lw or la. We assume it is lw. */
901 info
->insn_type
= dis_dref
;
907 immed
= (l
>> MIPS16OP_SH_IMM5
) & MIPS16OP_MASK_IMM5
;
909 info
->insn_type
= dis_dref
;
915 immed
= (l
>> MIPS16OP_SH_IMM5
) & MIPS16OP_MASK_IMM5
;
924 if (signedp
&& immed
>= (1 << (nbits
- 1)))
927 if ((type
== '<' || type
== '>' || type
== '[' || type
== ']')
934 immed
|= ((extend
& 0x1f) << 11) | (extend
& 0x7e0);
935 else if (extbits
== 15)
936 immed
|= ((extend
& 0xf) << 11) | (extend
& 0x7f0);
938 immed
= ((extend
>> 6) & 0x1f) | (extend
& 0x20);
939 immed
&= (1 << extbits
) - 1;
940 if (! extu
&& immed
>= (1 << (extbits
- 1)))
941 immed
-= 1 << extbits
;
945 (*info
->fprintf_func
) (info
->stream
, "%d", immed
);
954 baseaddr
= memaddr
+ 2;
957 baseaddr
= memaddr
- 2;
965 /* If this instruction is in the delay slot of a jr
966 instruction, the base address is the address of the
967 jr instruction. If it is in the delay slot of jalr
968 instruction, the base address is the address of the
969 jalr instruction. This test is unreliable: we have
970 no way of knowing whether the previous word is
971 instruction or data. */
972 status
= (*info
->read_memory_func
) (memaddr
- 4, buffer
, 2,
975 && (((info
->endian
== BFD_ENDIAN_BIG
976 ? bfd_getb16 (buffer
)
977 : bfd_getl16 (buffer
))
978 & 0xf800) == 0x1800))
979 baseaddr
= memaddr
- 4;
982 status
= (*info
->read_memory_func
) (memaddr
- 2, buffer
,
985 && (((info
->endian
== BFD_ENDIAN_BIG
986 ? bfd_getb16 (buffer
)
987 : bfd_getl16 (buffer
))
988 & 0xf81f) == 0xe800))
989 baseaddr
= memaddr
- 2;
992 val
= (baseaddr
& ~ ((1 << shift
) - 1)) + immed
;
993 (*info
->print_address_func
) (val
, info
);
1002 l
= ((l
& 0x1f) << 23) | ((l
& 0x3e0) << 13) | (extend
<< 2);
1003 (*info
->print_address_func
) ((memaddr
& 0xf0000000) | l
, info
);
1004 info
->insn_type
= dis_jsr
;
1005 info
->target
= (memaddr
& 0xf0000000) | l
;
1006 info
->branch_delay_insns
= 1;
1012 int need_comma
, amask
, smask
;
1016 l
= (l
>> MIPS16OP_SH_IMM6
) & MIPS16OP_MASK_IMM6
;
1018 amask
= (l
>> 3) & 7;
1020 if (amask
> 0 && amask
< 5)
1022 (*info
->fprintf_func
) (info
->stream
, "$%s", reg_names
[4]);
1024 (*info
->fprintf_func
) (info
->stream
, "-$%s",
1025 reg_names
[amask
+ 3]);
1029 smask
= (l
>> 1) & 3;
1032 (*info
->fprintf_func
) (info
->stream
, "%s??",
1033 need_comma
? "," : "");
1038 (*info
->fprintf_func
) (info
->stream
, "%s$%s",
1039 need_comma
? "," : "",
1042 (*info
->fprintf_func
) (info
->stream
, "-$%s",
1043 reg_names
[smask
+ 15]);
1049 (*info
->fprintf_func
) (info
->stream
, "%s$%s",
1050 need_comma
? "," : "",
1055 if (amask
== 5 || amask
== 6)
1057 (*info
->fprintf_func
) (info
->stream
, "%s$f0",
1058 need_comma
? "," : "");
1060 (*info
->fprintf_func
) (info
->stream
, "-$f1");
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