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* s390.h (s390_opcode_cpu_val): Add enum for cpu type z9-109.
[deliverable/binutils-gdb.git] / opcodes / mips-dis.c
1 /* Print mips instructions for GDB, the GNU debugger, or for objdump.
2 Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
3 2000, 2001, 2002, 2003, 2005
4 Free Software Foundation, Inc.
5 Contributed by Nobuyuki Hikichi(hikichi@sra.co.jp).
6
7 This file is part of GDB, GAS, and the GNU binutils.
8
9 This program is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 2 of the License, or
12 (at your option) any later version.
13
14 This program is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
18
19 You should have received a copy of the GNU General Public License
20 along with this program; if not, write to the Free Software
21 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
22 MA 02110-1301, USA. */
23
24 #include "sysdep.h"
25 #include "dis-asm.h"
26 #include "libiberty.h"
27 #include "opcode/mips.h"
28 #include "opintl.h"
29
30 /* FIXME: These are needed to figure out if the code is mips16 or
31 not. The low bit of the address is often a good indicator. No
32 symbol table is available when this code runs out in an embedded
33 system as when it is used for disassembler support in a monitor. */
34
35 #if !defined(EMBEDDED_ENV)
36 #define SYMTAB_AVAILABLE 1
37 #include "elf-bfd.h"
38 #include "elf/mips.h"
39 #endif
40
41 /* Mips instructions are at maximum this many bytes long. */
42 #define INSNLEN 4
43
44 \f
45 /* FIXME: These should be shared with gdb somehow. */
46
47 struct mips_cp0sel_name
48 {
49 unsigned int cp0reg;
50 unsigned int sel;
51 const char * const name;
52 };
53
54 /* The mips16 register names. */
55 static const char * const mips16_reg_names[] =
56 {
57 "s0", "s1", "v0", "v1", "a0", "a1", "a2", "a3"
58 };
59
60 static const char * const mips_gpr_names_numeric[32] =
61 {
62 "$0", "$1", "$2", "$3", "$4", "$5", "$6", "$7",
63 "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15",
64 "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23",
65 "$24", "$25", "$26", "$27", "$28", "$29", "$30", "$31"
66 };
67
68 static const char * const mips_gpr_names_oldabi[32] =
69 {
70 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
71 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7",
72 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
73 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra"
74 };
75
76 static const char * const mips_gpr_names_newabi[32] =
77 {
78 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
79 "a4", "a5", "a6", "a7", "t0", "t1", "t2", "t3",
80 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
81 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra"
82 };
83
84 static const char * const mips_fpr_names_numeric[32] =
85 {
86 "$f0", "$f1", "$f2", "$f3", "$f4", "$f5", "$f6", "$f7",
87 "$f8", "$f9", "$f10", "$f11", "$f12", "$f13", "$f14", "$f15",
88 "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23",
89 "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31"
90 };
91
92 static const char * const mips_fpr_names_32[32] =
93 {
94 "fv0", "fv0f", "fv1", "fv1f", "ft0", "ft0f", "ft1", "ft1f",
95 "ft2", "ft2f", "ft3", "ft3f", "fa0", "fa0f", "fa1", "fa1f",
96 "ft4", "ft4f", "ft5", "ft5f", "fs0", "fs0f", "fs1", "fs1f",
97 "fs2", "fs2f", "fs3", "fs3f", "fs4", "fs4f", "fs5", "fs5f"
98 };
99
100 static const char * const mips_fpr_names_n32[32] =
101 {
102 "fv0", "ft14", "fv1", "ft15", "ft0", "ft1", "ft2", "ft3",
103 "ft4", "ft5", "ft6", "ft7", "fa0", "fa1", "fa2", "fa3",
104 "fa4", "fa5", "fa6", "fa7", "fs0", "ft8", "fs1", "ft9",
105 "fs2", "ft10", "fs3", "ft11", "fs4", "ft12", "fs5", "ft13"
106 };
107
108 static const char * const mips_fpr_names_64[32] =
109 {
110 "fv0", "ft12", "fv1", "ft13", "ft0", "ft1", "ft2", "ft3",
111 "ft4", "ft5", "ft6", "ft7", "fa0", "fa1", "fa2", "fa3",
112 "fa4", "fa5", "fa6", "fa7", "ft8", "ft9", "ft10", "ft11",
113 "fs0", "fs1", "fs2", "fs3", "fs4", "fs5", "fs6", "fs7"
114 };
115
116 static const char * const mips_cp0_names_numeric[32] =
117 {
118 "$0", "$1", "$2", "$3", "$4", "$5", "$6", "$7",
119 "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15",
120 "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23",
121 "$24", "$25", "$26", "$27", "$28", "$29", "$30", "$31"
122 };
123
124 static const char * const mips_cp0_names_mips3264[32] =
125 {
126 "c0_index", "c0_random", "c0_entrylo0", "c0_entrylo1",
127 "c0_context", "c0_pagemask", "c0_wired", "$7",
128 "c0_badvaddr", "c0_count", "c0_entryhi", "c0_compare",
129 "c0_status", "c0_cause", "c0_epc", "c0_prid",
130 "c0_config", "c0_lladdr", "c0_watchlo", "c0_watchhi",
131 "c0_xcontext", "$21", "$22", "c0_debug",
132 "c0_depc", "c0_perfcnt", "c0_errctl", "c0_cacheerr",
133 "c0_taglo", "c0_taghi", "c0_errorepc", "c0_desave",
134 };
135
136 static const struct mips_cp0sel_name mips_cp0sel_names_mips3264[] =
137 {
138 { 16, 1, "c0_config1" },
139 { 16, 2, "c0_config2" },
140 { 16, 3, "c0_config3" },
141 { 18, 1, "c0_watchlo,1" },
142 { 18, 2, "c0_watchlo,2" },
143 { 18, 3, "c0_watchlo,3" },
144 { 18, 4, "c0_watchlo,4" },
145 { 18, 5, "c0_watchlo,5" },
146 { 18, 6, "c0_watchlo,6" },
147 { 18, 7, "c0_watchlo,7" },
148 { 19, 1, "c0_watchhi,1" },
149 { 19, 2, "c0_watchhi,2" },
150 { 19, 3, "c0_watchhi,3" },
151 { 19, 4, "c0_watchhi,4" },
152 { 19, 5, "c0_watchhi,5" },
153 { 19, 6, "c0_watchhi,6" },
154 { 19, 7, "c0_watchhi,7" },
155 { 25, 1, "c0_perfcnt,1" },
156 { 25, 2, "c0_perfcnt,2" },
157 { 25, 3, "c0_perfcnt,3" },
158 { 25, 4, "c0_perfcnt,4" },
159 { 25, 5, "c0_perfcnt,5" },
160 { 25, 6, "c0_perfcnt,6" },
161 { 25, 7, "c0_perfcnt,7" },
162 { 27, 1, "c0_cacheerr,1" },
163 { 27, 2, "c0_cacheerr,2" },
164 { 27, 3, "c0_cacheerr,3" },
165 { 28, 1, "c0_datalo" },
166 { 29, 1, "c0_datahi" }
167 };
168
169 static const char * const mips_cp0_names_mips3264r2[32] =
170 {
171 "c0_index", "c0_random", "c0_entrylo0", "c0_entrylo1",
172 "c0_context", "c0_pagemask", "c0_wired", "c0_hwrena",
173 "c0_badvaddr", "c0_count", "c0_entryhi", "c0_compare",
174 "c0_status", "c0_cause", "c0_epc", "c0_prid",
175 "c0_config", "c0_lladdr", "c0_watchlo", "c0_watchhi",
176 "c0_xcontext", "$21", "$22", "c0_debug",
177 "c0_depc", "c0_perfcnt", "c0_errctl", "c0_cacheerr",
178 "c0_taglo", "c0_taghi", "c0_errorepc", "c0_desave",
179 };
180
181 static const struct mips_cp0sel_name mips_cp0sel_names_mips3264r2[] =
182 {
183 { 4, 1, "c0_contextconfig" },
184 { 5, 1, "c0_pagegrain" },
185 { 12, 1, "c0_intctl" },
186 { 12, 2, "c0_srsctl" },
187 { 12, 3, "c0_srsmap" },
188 { 15, 1, "c0_ebase" },
189 { 16, 1, "c0_config1" },
190 { 16, 2, "c0_config2" },
191 { 16, 3, "c0_config3" },
192 { 18, 1, "c0_watchlo,1" },
193 { 18, 2, "c0_watchlo,2" },
194 { 18, 3, "c0_watchlo,3" },
195 { 18, 4, "c0_watchlo,4" },
196 { 18, 5, "c0_watchlo,5" },
197 { 18, 6, "c0_watchlo,6" },
198 { 18, 7, "c0_watchlo,7" },
199 { 19, 1, "c0_watchhi,1" },
200 { 19, 2, "c0_watchhi,2" },
201 { 19, 3, "c0_watchhi,3" },
202 { 19, 4, "c0_watchhi,4" },
203 { 19, 5, "c0_watchhi,5" },
204 { 19, 6, "c0_watchhi,6" },
205 { 19, 7, "c0_watchhi,7" },
206 { 23, 1, "c0_tracecontrol" },
207 { 23, 2, "c0_tracecontrol2" },
208 { 23, 3, "c0_usertracedata" },
209 { 23, 4, "c0_tracebpc" },
210 { 25, 1, "c0_perfcnt,1" },
211 { 25, 2, "c0_perfcnt,2" },
212 { 25, 3, "c0_perfcnt,3" },
213 { 25, 4, "c0_perfcnt,4" },
214 { 25, 5, "c0_perfcnt,5" },
215 { 25, 6, "c0_perfcnt,6" },
216 { 25, 7, "c0_perfcnt,7" },
217 { 27, 1, "c0_cacheerr,1" },
218 { 27, 2, "c0_cacheerr,2" },
219 { 27, 3, "c0_cacheerr,3" },
220 { 28, 1, "c0_datalo" },
221 { 28, 2, "c0_taglo1" },
222 { 28, 3, "c0_datalo1" },
223 { 28, 4, "c0_taglo2" },
224 { 28, 5, "c0_datalo2" },
225 { 28, 6, "c0_taglo3" },
226 { 28, 7, "c0_datalo3" },
227 { 29, 1, "c0_datahi" },
228 { 29, 2, "c0_taghi1" },
229 { 29, 3, "c0_datahi1" },
230 { 29, 4, "c0_taghi2" },
231 { 29, 5, "c0_datahi2" },
232 { 29, 6, "c0_taghi3" },
233 { 29, 7, "c0_datahi3" },
234 };
235
236 /* SB-1: MIPS64 (mips_cp0_names_mips3264) with minor mods. */
237 static const char * const mips_cp0_names_sb1[32] =
238 {
239 "c0_index", "c0_random", "c0_entrylo0", "c0_entrylo1",
240 "c0_context", "c0_pagemask", "c0_wired", "$7",
241 "c0_badvaddr", "c0_count", "c0_entryhi", "c0_compare",
242 "c0_status", "c0_cause", "c0_epc", "c0_prid",
243 "c0_config", "c0_lladdr", "c0_watchlo", "c0_watchhi",
244 "c0_xcontext", "$21", "$22", "c0_debug",
245 "c0_depc", "c0_perfcnt", "c0_errctl", "c0_cacheerr_i",
246 "c0_taglo_i", "c0_taghi_i", "c0_errorepc", "c0_desave",
247 };
248
249 static const struct mips_cp0sel_name mips_cp0sel_names_sb1[] =
250 {
251 { 16, 1, "c0_config1" },
252 { 18, 1, "c0_watchlo,1" },
253 { 19, 1, "c0_watchhi,1" },
254 { 22, 0, "c0_perftrace" },
255 { 23, 3, "c0_edebug" },
256 { 25, 1, "c0_perfcnt,1" },
257 { 25, 2, "c0_perfcnt,2" },
258 { 25, 3, "c0_perfcnt,3" },
259 { 25, 4, "c0_perfcnt,4" },
260 { 25, 5, "c0_perfcnt,5" },
261 { 25, 6, "c0_perfcnt,6" },
262 { 25, 7, "c0_perfcnt,7" },
263 { 26, 1, "c0_buserr_pa" },
264 { 27, 1, "c0_cacheerr_d" },
265 { 27, 3, "c0_cacheerr_d_pa" },
266 { 28, 1, "c0_datalo_i" },
267 { 28, 2, "c0_taglo_d" },
268 { 28, 3, "c0_datalo_d" },
269 { 29, 1, "c0_datahi_i" },
270 { 29, 2, "c0_taghi_d" },
271 { 29, 3, "c0_datahi_d" },
272 };
273
274 static const char * const mips_hwr_names_numeric[32] =
275 {
276 "$0", "$1", "$2", "$3", "$4", "$5", "$6", "$7",
277 "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15",
278 "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23",
279 "$24", "$25", "$26", "$27", "$28", "$29", "$30", "$31"
280 };
281
282 static const char * const mips_hwr_names_mips3264r2[32] =
283 {
284 "hwr_cpunum", "hwr_synci_step", "hwr_cc", "hwr_ccres",
285 "$4", "$5", "$6", "$7",
286 "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15",
287 "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23",
288 "$24", "$25", "$26", "$27", "$28", "$29", "$30", "$31"
289 };
290
291 struct mips_abi_choice
292 {
293 const char * name;
294 const char * const *gpr_names;
295 const char * const *fpr_names;
296 };
297
298 struct mips_abi_choice mips_abi_choices[] =
299 {
300 { "numeric", mips_gpr_names_numeric, mips_fpr_names_numeric },
301 { "32", mips_gpr_names_oldabi, mips_fpr_names_32 },
302 { "n32", mips_gpr_names_newabi, mips_fpr_names_n32 },
303 { "64", mips_gpr_names_newabi, mips_fpr_names_64 },
304 };
305
306 struct mips_arch_choice
307 {
308 const char *name;
309 int bfd_mach_valid;
310 unsigned long bfd_mach;
311 int processor;
312 int isa;
313 const char * const *cp0_names;
314 const struct mips_cp0sel_name *cp0sel_names;
315 unsigned int cp0sel_names_len;
316 const char * const *hwr_names;
317 };
318
319 const struct mips_arch_choice mips_arch_choices[] =
320 {
321 { "numeric", 0, 0, 0, 0,
322 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
323
324 { "r3000", 1, bfd_mach_mips3000, CPU_R3000, ISA_MIPS1,
325 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
326 { "r3900", 1, bfd_mach_mips3900, CPU_R3900, ISA_MIPS1,
327 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
328 { "r4000", 1, bfd_mach_mips4000, CPU_R4000, ISA_MIPS3,
329 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
330 { "r4010", 1, bfd_mach_mips4010, CPU_R4010, ISA_MIPS2,
331 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
332 { "vr4100", 1, bfd_mach_mips4100, CPU_VR4100, ISA_MIPS3,
333 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
334 { "vr4111", 1, bfd_mach_mips4111, CPU_R4111, ISA_MIPS3,
335 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
336 { "vr4120", 1, bfd_mach_mips4120, CPU_VR4120, ISA_MIPS3,
337 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
338 { "r4300", 1, bfd_mach_mips4300, CPU_R4300, ISA_MIPS3,
339 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
340 { "r4400", 1, bfd_mach_mips4400, CPU_R4400, ISA_MIPS3,
341 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
342 { "r4600", 1, bfd_mach_mips4600, CPU_R4600, ISA_MIPS3,
343 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
344 { "r4650", 1, bfd_mach_mips4650, CPU_R4650, ISA_MIPS3,
345 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
346 { "r5000", 1, bfd_mach_mips5000, CPU_R5000, ISA_MIPS4,
347 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
348 { "vr5400", 1, bfd_mach_mips5400, CPU_VR5400, ISA_MIPS4,
349 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
350 { "vr5500", 1, bfd_mach_mips5500, CPU_VR5500, ISA_MIPS4,
351 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
352 { "r6000", 1, bfd_mach_mips6000, CPU_R6000, ISA_MIPS2,
353 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
354 { "rm7000", 1, bfd_mach_mips7000, CPU_RM7000, ISA_MIPS4,
355 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
356 { "rm9000", 1, bfd_mach_mips7000, CPU_RM7000, ISA_MIPS4,
357 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
358 { "r8000", 1, bfd_mach_mips8000, CPU_R8000, ISA_MIPS4,
359 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
360 { "r10000", 1, bfd_mach_mips10000, CPU_R10000, ISA_MIPS4,
361 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
362 { "r12000", 1, bfd_mach_mips12000, CPU_R12000, ISA_MIPS4,
363 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
364 { "mips5", 1, bfd_mach_mips5, CPU_MIPS5, ISA_MIPS5,
365 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
366
367 /* For stock MIPS32, disassemble all applicable MIPS-specified ASEs.
368 Note that MIPS-3D and MDMX are not applicable to MIPS32. (See
369 _MIPS32 Architecture For Programmers Volume I: Introduction to the
370 MIPS32 Architecture_ (MIPS Document Number MD00082, Revision 0.95),
371 page 1. */
372 { "mips32", 1, bfd_mach_mipsisa32, CPU_MIPS32,
373 ISA_MIPS32 | INSN_MIPS16,
374 mips_cp0_names_mips3264,
375 mips_cp0sel_names_mips3264, ARRAY_SIZE (mips_cp0sel_names_mips3264),
376 mips_hwr_names_numeric },
377
378 { "mips32r2", 1, bfd_mach_mipsisa32r2, CPU_MIPS32R2,
379 ISA_MIPS32R2 | INSN_MIPS16,
380 mips_cp0_names_mips3264r2,
381 mips_cp0sel_names_mips3264r2, ARRAY_SIZE (mips_cp0sel_names_mips3264r2),
382 mips_hwr_names_mips3264r2 },
383
384 /* For stock MIPS64, disassemble all applicable MIPS-specified ASEs. */
385 { "mips64", 1, bfd_mach_mipsisa64, CPU_MIPS64,
386 ISA_MIPS64 | INSN_MIPS16 | INSN_MIPS3D | INSN_MDMX,
387 mips_cp0_names_mips3264,
388 mips_cp0sel_names_mips3264, ARRAY_SIZE (mips_cp0sel_names_mips3264),
389 mips_hwr_names_numeric },
390
391 { "mips64r2", 1, bfd_mach_mipsisa64r2, CPU_MIPS64R2,
392 ISA_MIPS64R2 | INSN_MIPS16 | INSN_MIPS3D | INSN_MDMX,
393 mips_cp0_names_mips3264r2,
394 mips_cp0sel_names_mips3264r2, ARRAY_SIZE (mips_cp0sel_names_mips3264r2),
395 mips_hwr_names_mips3264r2 },
396
397 { "sb1", 1, bfd_mach_mips_sb1, CPU_SB1,
398 ISA_MIPS64 | INSN_MIPS3D | INSN_SB1,
399 mips_cp0_names_sb1,
400 mips_cp0sel_names_sb1, ARRAY_SIZE (mips_cp0sel_names_sb1),
401 mips_hwr_names_numeric },
402
403 /* This entry, mips16, is here only for ISA/processor selection; do
404 not print its name. */
405 { "", 1, bfd_mach_mips16, CPU_MIPS16, ISA_MIPS3 | INSN_MIPS16,
406 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
407 };
408
409 /* ISA and processor type to disassemble for, and register names to use.
410 set_default_mips_dis_options and parse_mips_dis_options fill in these
411 values. */
412 static int mips_processor;
413 static int mips_isa;
414 static const char * const *mips_gpr_names;
415 static const char * const *mips_fpr_names;
416 static const char * const *mips_cp0_names;
417 static const struct mips_cp0sel_name *mips_cp0sel_names;
418 static int mips_cp0sel_names_len;
419 static const char * const *mips_hwr_names;
420
421 /* Other options */
422 static int no_aliases; /* If set disassemble as most general inst. */
423 \f
424 static const struct mips_abi_choice *
425 choose_abi_by_name (const char *name, unsigned int namelen)
426 {
427 const struct mips_abi_choice *c;
428 unsigned int i;
429
430 for (i = 0, c = NULL; i < ARRAY_SIZE (mips_abi_choices) && c == NULL; i++)
431 if (strncmp (mips_abi_choices[i].name, name, namelen) == 0
432 && strlen (mips_abi_choices[i].name) == namelen)
433 c = &mips_abi_choices[i];
434
435 return c;
436 }
437
438 static const struct mips_arch_choice *
439 choose_arch_by_name (const char *name, unsigned int namelen)
440 {
441 const struct mips_arch_choice *c = NULL;
442 unsigned int i;
443
444 for (i = 0, c = NULL; i < ARRAY_SIZE (mips_arch_choices) && c == NULL; i++)
445 if (strncmp (mips_arch_choices[i].name, name, namelen) == 0
446 && strlen (mips_arch_choices[i].name) == namelen)
447 c = &mips_arch_choices[i];
448
449 return c;
450 }
451
452 static const struct mips_arch_choice *
453 choose_arch_by_number (unsigned long mach)
454 {
455 static unsigned long hint_bfd_mach;
456 static const struct mips_arch_choice *hint_arch_choice;
457 const struct mips_arch_choice *c;
458 unsigned int i;
459
460 /* We optimize this because even if the user specifies no
461 flags, this will be done for every instruction! */
462 if (hint_bfd_mach == mach
463 && hint_arch_choice != NULL
464 && hint_arch_choice->bfd_mach == hint_bfd_mach)
465 return hint_arch_choice;
466
467 for (i = 0, c = NULL; i < ARRAY_SIZE (mips_arch_choices) && c == NULL; i++)
468 {
469 if (mips_arch_choices[i].bfd_mach_valid
470 && mips_arch_choices[i].bfd_mach == mach)
471 {
472 c = &mips_arch_choices[i];
473 hint_bfd_mach = mach;
474 hint_arch_choice = c;
475 }
476 }
477 return c;
478 }
479
480 /* Check if the object uses NewABI conventions. */
481
482 static int
483 is_newabi (Elf_Internal_Ehdr *header)
484 {
485 /* There are no old-style ABIs which use 64-bit ELF. */
486 if (header->e_ident[EI_CLASS] == ELFCLASS64)
487 return 1;
488
489 /* If a 32-bit ELF file, n32 is a new-style ABI. */
490 if ((header->e_flags & EF_MIPS_ABI2) != 0)
491 return 1;
492
493 return 0;
494 }
495
496 static void
497 set_default_mips_dis_options (struct disassemble_info *info)
498 {
499 const struct mips_arch_choice *chosen_arch;
500
501 /* Defaults: mipsIII/r3000 (?!), (o)32-style ("oldabi") GPR names,
502 and numeric FPR, CP0 register, and HWR names. */
503 mips_isa = ISA_MIPS3;
504 mips_processor = CPU_R3000;
505 mips_gpr_names = mips_gpr_names_oldabi;
506 mips_fpr_names = mips_fpr_names_numeric;
507 mips_cp0_names = mips_cp0_names_numeric;
508 mips_cp0sel_names = NULL;
509 mips_cp0sel_names_len = 0;
510 mips_hwr_names = mips_hwr_names_numeric;
511 no_aliases = 0;
512
513 /* If an ELF "newabi" binary, use the n32/(n)64 GPR names. */
514 if (info->flavour == bfd_target_elf_flavour && info->section != NULL)
515 {
516 Elf_Internal_Ehdr *header;
517
518 header = elf_elfheader (info->section->owner);
519 if (is_newabi (header))
520 mips_gpr_names = mips_gpr_names_newabi;
521 }
522
523 /* Set ISA, architecture, and cp0 register names as best we can. */
524 #if ! SYMTAB_AVAILABLE
525 /* This is running out on a target machine, not in a host tool.
526 FIXME: Where does mips_target_info come from? */
527 target_processor = mips_target_info.processor;
528 mips_isa = mips_target_info.isa;
529 #else
530 chosen_arch = choose_arch_by_number (info->mach);
531 if (chosen_arch != NULL)
532 {
533 mips_processor = chosen_arch->processor;
534 mips_isa = chosen_arch->isa;
535 mips_cp0_names = chosen_arch->cp0_names;
536 mips_cp0sel_names = chosen_arch->cp0sel_names;
537 mips_cp0sel_names_len = chosen_arch->cp0sel_names_len;
538 mips_hwr_names = chosen_arch->hwr_names;
539 }
540 #endif
541 }
542
543 static void
544 parse_mips_dis_option (const char *option, unsigned int len)
545 {
546 unsigned int i, optionlen, vallen;
547 const char *val;
548 const struct mips_abi_choice *chosen_abi;
549 const struct mips_arch_choice *chosen_arch;
550
551 /* Try to match options that are simple flags */
552 if (strncmp (option, "no-aliases", 10) == 0)
553 {
554 no_aliases = 1;
555 return;
556 }
557
558 /* Look for the = that delimits the end of the option name. */
559 for (i = 0; i < len; i++)
560 if (option[i] == '=')
561 break;
562
563 if (i == 0) /* Invalid option: no name before '='. */
564 return;
565 if (i == len) /* Invalid option: no '='. */
566 return;
567 if (i == (len - 1)) /* Invalid option: no value after '='. */
568 return;
569
570 optionlen = i;
571 val = option + (optionlen + 1);
572 vallen = len - (optionlen + 1);
573
574 if (strncmp ("gpr-names", option, optionlen) == 0
575 && strlen ("gpr-names") == optionlen)
576 {
577 chosen_abi = choose_abi_by_name (val, vallen);
578 if (chosen_abi != NULL)
579 mips_gpr_names = chosen_abi->gpr_names;
580 return;
581 }
582
583 if (strncmp ("fpr-names", option, optionlen) == 0
584 && strlen ("fpr-names") == optionlen)
585 {
586 chosen_abi = choose_abi_by_name (val, vallen);
587 if (chosen_abi != NULL)
588 mips_fpr_names = chosen_abi->fpr_names;
589 return;
590 }
591
592 if (strncmp ("cp0-names", option, optionlen) == 0
593 && strlen ("cp0-names") == optionlen)
594 {
595 chosen_arch = choose_arch_by_name (val, vallen);
596 if (chosen_arch != NULL)
597 {
598 mips_cp0_names = chosen_arch->cp0_names;
599 mips_cp0sel_names = chosen_arch->cp0sel_names;
600 mips_cp0sel_names_len = chosen_arch->cp0sel_names_len;
601 }
602 return;
603 }
604
605 if (strncmp ("hwr-names", option, optionlen) == 0
606 && strlen ("hwr-names") == optionlen)
607 {
608 chosen_arch = choose_arch_by_name (val, vallen);
609 if (chosen_arch != NULL)
610 mips_hwr_names = chosen_arch->hwr_names;
611 return;
612 }
613
614 if (strncmp ("reg-names", option, optionlen) == 0
615 && strlen ("reg-names") == optionlen)
616 {
617 /* We check both ABI and ARCH here unconditionally, so
618 that "numeric" will do the desirable thing: select
619 numeric register names for all registers. Other than
620 that, a given name probably won't match both. */
621 chosen_abi = choose_abi_by_name (val, vallen);
622 if (chosen_abi != NULL)
623 {
624 mips_gpr_names = chosen_abi->gpr_names;
625 mips_fpr_names = chosen_abi->fpr_names;
626 }
627 chosen_arch = choose_arch_by_name (val, vallen);
628 if (chosen_arch != NULL)
629 {
630 mips_cp0_names = chosen_arch->cp0_names;
631 mips_cp0sel_names = chosen_arch->cp0sel_names;
632 mips_cp0sel_names_len = chosen_arch->cp0sel_names_len;
633 mips_hwr_names = chosen_arch->hwr_names;
634 }
635 return;
636 }
637
638 /* Invalid option. */
639 }
640
641 static void
642 parse_mips_dis_options (const char *options)
643 {
644 const char *option_end;
645
646 if (options == NULL)
647 return;
648
649 while (*options != '\0')
650 {
651 /* Skip empty options. */
652 if (*options == ',')
653 {
654 options++;
655 continue;
656 }
657
658 /* We know that *options is neither NUL or a comma. */
659 option_end = options + 1;
660 while (*option_end != ',' && *option_end != '\0')
661 option_end++;
662
663 parse_mips_dis_option (options, option_end - options);
664
665 /* Go on to the next one. If option_end points to a comma, it
666 will be skipped above. */
667 options = option_end;
668 }
669 }
670
671 static const struct mips_cp0sel_name *
672 lookup_mips_cp0sel_name (const struct mips_cp0sel_name *names,
673 unsigned int len,
674 unsigned int cp0reg,
675 unsigned int sel)
676 {
677 unsigned int i;
678
679 for (i = 0; i < len; i++)
680 if (names[i].cp0reg == cp0reg && names[i].sel == sel)
681 return &names[i];
682 return NULL;
683 }
684 \f
685 /* Print insn arguments for 32/64-bit code. */
686
687 static void
688 print_insn_args (const char *d,
689 register unsigned long int l,
690 bfd_vma pc,
691 struct disassemble_info *info)
692 {
693 int op, delta;
694 unsigned int lsb, msb, msbd;
695
696 lsb = 0;
697
698 for (; *d != '\0'; d++)
699 {
700 switch (*d)
701 {
702 case ',':
703 case '(':
704 case ')':
705 case '[':
706 case ']':
707 (*info->fprintf_func) (info->stream, "%c", *d);
708 break;
709
710 case '+':
711 /* Extension character; switch for second char. */
712 d++;
713 switch (*d)
714 {
715 case '\0':
716 /* xgettext:c-format */
717 (*info->fprintf_func) (info->stream,
718 _("# internal error, incomplete extension sequence (+)"));
719 return;
720
721 case 'A':
722 lsb = (l >> OP_SH_SHAMT) & OP_MASK_SHAMT;
723 (*info->fprintf_func) (info->stream, "0x%x", lsb);
724 break;
725
726 case 'B':
727 msb = (l >> OP_SH_INSMSB) & OP_MASK_INSMSB;
728 (*info->fprintf_func) (info->stream, "0x%x", msb - lsb + 1);
729 break;
730
731 case 'C':
732 case 'H':
733 msbd = (l >> OP_SH_EXTMSBD) & OP_MASK_EXTMSBD;
734 (*info->fprintf_func) (info->stream, "0x%x", msbd + 1);
735 break;
736
737 case 'D':
738 {
739 const struct mips_cp0sel_name *n;
740 unsigned int cp0reg, sel;
741
742 cp0reg = (l >> OP_SH_RD) & OP_MASK_RD;
743 sel = (l >> OP_SH_SEL) & OP_MASK_SEL;
744
745 /* CP0 register including 'sel' code for mtcN (et al.), to be
746 printed textually if known. If not known, print both
747 CP0 register name and sel numerically since CP0 register
748 with sel 0 may have a name unrelated to register being
749 printed. */
750 n = lookup_mips_cp0sel_name(mips_cp0sel_names,
751 mips_cp0sel_names_len, cp0reg, sel);
752 if (n != NULL)
753 (*info->fprintf_func) (info->stream, "%s", n->name);
754 else
755 (*info->fprintf_func) (info->stream, "$%d,%d", cp0reg, sel);
756 break;
757 }
758
759 case 'E':
760 lsb = ((l >> OP_SH_SHAMT) & OP_MASK_SHAMT) + 32;
761 (*info->fprintf_func) (info->stream, "0x%x", lsb);
762 break;
763
764 case 'F':
765 msb = ((l >> OP_SH_INSMSB) & OP_MASK_INSMSB) + 32;
766 (*info->fprintf_func) (info->stream, "0x%x", msb - lsb + 1);
767 break;
768
769 case 'G':
770 msbd = ((l >> OP_SH_EXTMSBD) & OP_MASK_EXTMSBD) + 32;
771 (*info->fprintf_func) (info->stream, "0x%x", msbd + 1);
772 break;
773
774 default:
775 /* xgettext:c-format */
776 (*info->fprintf_func) (info->stream,
777 _("# internal error, undefined extension sequence (+%c)"),
778 *d);
779 return;
780 }
781 break;
782
783 case 's':
784 case 'b':
785 case 'r':
786 case 'v':
787 (*info->fprintf_func) (info->stream, "%s",
788 mips_gpr_names[(l >> OP_SH_RS) & OP_MASK_RS]);
789 break;
790
791 case 't':
792 case 'w':
793 (*info->fprintf_func) (info->stream, "%s",
794 mips_gpr_names[(l >> OP_SH_RT) & OP_MASK_RT]);
795 break;
796
797 case 'i':
798 case 'u':
799 (*info->fprintf_func) (info->stream, "0x%lx",
800 (l >> OP_SH_IMMEDIATE) & OP_MASK_IMMEDIATE);
801 break;
802
803 case 'j': /* Same as i, but sign-extended. */
804 case 'o':
805 delta = (l >> OP_SH_DELTA) & OP_MASK_DELTA;
806 if (delta & 0x8000)
807 delta |= ~0xffff;
808 (*info->fprintf_func) (info->stream, "%d",
809 delta);
810 break;
811
812 case 'h':
813 (*info->fprintf_func) (info->stream, "0x%x",
814 (unsigned int) ((l >> OP_SH_PREFX)
815 & OP_MASK_PREFX));
816 break;
817
818 case 'k':
819 (*info->fprintf_func) (info->stream, "0x%x",
820 (unsigned int) ((l >> OP_SH_CACHE)
821 & OP_MASK_CACHE));
822 break;
823
824 case 'a':
825 info->target = (((pc + 4) & ~(bfd_vma) 0x0fffffff)
826 | (((l >> OP_SH_TARGET) & OP_MASK_TARGET) << 2));
827 (*info->print_address_func) (info->target, info);
828 break;
829
830 case 'p':
831 /* Sign extend the displacement. */
832 delta = (l >> OP_SH_DELTA) & OP_MASK_DELTA;
833 if (delta & 0x8000)
834 delta |= ~0xffff;
835 info->target = (delta << 2) + pc + INSNLEN;
836 (*info->print_address_func) (info->target, info);
837 break;
838
839 case 'd':
840 (*info->fprintf_func) (info->stream, "%s",
841 mips_gpr_names[(l >> OP_SH_RD) & OP_MASK_RD]);
842 break;
843
844 case 'U':
845 {
846 /* First check for both rd and rt being equal. */
847 unsigned int reg = (l >> OP_SH_RD) & OP_MASK_RD;
848 if (reg == ((l >> OP_SH_RT) & OP_MASK_RT))
849 (*info->fprintf_func) (info->stream, "%s",
850 mips_gpr_names[reg]);
851 else
852 {
853 /* If one is zero use the other. */
854 if (reg == 0)
855 (*info->fprintf_func) (info->stream, "%s",
856 mips_gpr_names[(l >> OP_SH_RT) & OP_MASK_RT]);
857 else if (((l >> OP_SH_RT) & OP_MASK_RT) == 0)
858 (*info->fprintf_func) (info->stream, "%s",
859 mips_gpr_names[reg]);
860 else /* Bogus, result depends on processor. */
861 (*info->fprintf_func) (info->stream, "%s or %s",
862 mips_gpr_names[reg],
863 mips_gpr_names[(l >> OP_SH_RT) & OP_MASK_RT]);
864 }
865 }
866 break;
867
868 case 'z':
869 (*info->fprintf_func) (info->stream, "%s", mips_gpr_names[0]);
870 break;
871
872 case '<':
873 (*info->fprintf_func) (info->stream, "0x%lx",
874 (l >> OP_SH_SHAMT) & OP_MASK_SHAMT);
875 break;
876
877 case 'c':
878 (*info->fprintf_func) (info->stream, "0x%lx",
879 (l >> OP_SH_CODE) & OP_MASK_CODE);
880 break;
881
882 case 'q':
883 (*info->fprintf_func) (info->stream, "0x%lx",
884 (l >> OP_SH_CODE2) & OP_MASK_CODE2);
885 break;
886
887 case 'C':
888 (*info->fprintf_func) (info->stream, "0x%lx",
889 (l >> OP_SH_COPZ) & OP_MASK_COPZ);
890 break;
891
892 case 'B':
893 (*info->fprintf_func) (info->stream, "0x%lx",
894
895 (l >> OP_SH_CODE20) & OP_MASK_CODE20);
896 break;
897
898 case 'J':
899 (*info->fprintf_func) (info->stream, "0x%lx",
900 (l >> OP_SH_CODE19) & OP_MASK_CODE19);
901 break;
902
903 case 'S':
904 case 'V':
905 (*info->fprintf_func) (info->stream, "%s",
906 mips_fpr_names[(l >> OP_SH_FS) & OP_MASK_FS]);
907 break;
908
909 case 'T':
910 case 'W':
911 (*info->fprintf_func) (info->stream, "%s",
912 mips_fpr_names[(l >> OP_SH_FT) & OP_MASK_FT]);
913 break;
914
915 case 'D':
916 (*info->fprintf_func) (info->stream, "%s",
917 mips_fpr_names[(l >> OP_SH_FD) & OP_MASK_FD]);
918 break;
919
920 case 'R':
921 (*info->fprintf_func) (info->stream, "%s",
922 mips_fpr_names[(l >> OP_SH_FR) & OP_MASK_FR]);
923 break;
924
925 case 'E':
926 /* Coprocessor register for lwcN instructions, et al.
927
928 Note that there is no load/store cp0 instructions, and
929 that FPU (cp1) instructions disassemble this field using
930 'T' format. Therefore, until we gain understanding of
931 cp2 register names, we can simply print the register
932 numbers. */
933 (*info->fprintf_func) (info->stream, "$%ld",
934 (l >> OP_SH_RT) & OP_MASK_RT);
935 break;
936
937 case 'G':
938 /* Coprocessor register for mtcN instructions, et al. Note
939 that FPU (cp1) instructions disassemble this field using
940 'S' format. Therefore, we only need to worry about cp0,
941 cp2, and cp3. */
942 op = (l >> OP_SH_OP) & OP_MASK_OP;
943 if (op == OP_OP_COP0)
944 (*info->fprintf_func) (info->stream, "%s",
945 mips_cp0_names[(l >> OP_SH_RD) & OP_MASK_RD]);
946 else
947 (*info->fprintf_func) (info->stream, "$%ld",
948 (l >> OP_SH_RD) & OP_MASK_RD);
949 break;
950
951 case 'K':
952 (*info->fprintf_func) (info->stream, "%s",
953 mips_hwr_names[(l >> OP_SH_RD) & OP_MASK_RD]);
954 break;
955
956 case 'N':
957 (*info->fprintf_func) (info->stream, "$fcc%ld",
958 (l >> OP_SH_BCC) & OP_MASK_BCC);
959 break;
960
961 case 'M':
962 (*info->fprintf_func) (info->stream, "$fcc%ld",
963 (l >> OP_SH_CCC) & OP_MASK_CCC);
964 break;
965
966 case 'P':
967 (*info->fprintf_func) (info->stream, "%ld",
968 (l >> OP_SH_PERFREG) & OP_MASK_PERFREG);
969 break;
970
971 case 'e':
972 (*info->fprintf_func) (info->stream, "%ld",
973 (l >> OP_SH_VECBYTE) & OP_MASK_VECBYTE);
974 break;
975
976 case '%':
977 (*info->fprintf_func) (info->stream, "%ld",
978 (l >> OP_SH_VECALIGN) & OP_MASK_VECALIGN);
979 break;
980
981 case 'H':
982 (*info->fprintf_func) (info->stream, "%ld",
983 (l >> OP_SH_SEL) & OP_MASK_SEL);
984 break;
985
986 case 'O':
987 (*info->fprintf_func) (info->stream, "%ld",
988 (l >> OP_SH_ALN) & OP_MASK_ALN);
989 break;
990
991 case 'Q':
992 {
993 unsigned int vsel = (l >> OP_SH_VSEL) & OP_MASK_VSEL;
994
995 if ((vsel & 0x10) == 0)
996 {
997 int fmt;
998
999 vsel &= 0x0f;
1000 for (fmt = 0; fmt < 3; fmt++, vsel >>= 1)
1001 if ((vsel & 1) == 0)
1002 break;
1003 (*info->fprintf_func) (info->stream, "$v%ld[%d]",
1004 (l >> OP_SH_FT) & OP_MASK_FT,
1005 vsel >> 1);
1006 }
1007 else if ((vsel & 0x08) == 0)
1008 {
1009 (*info->fprintf_func) (info->stream, "$v%ld",
1010 (l >> OP_SH_FT) & OP_MASK_FT);
1011 }
1012 else
1013 {
1014 (*info->fprintf_func) (info->stream, "0x%lx",
1015 (l >> OP_SH_FT) & OP_MASK_FT);
1016 }
1017 }
1018 break;
1019
1020 case 'X':
1021 (*info->fprintf_func) (info->stream, "$v%ld",
1022 (l >> OP_SH_FD) & OP_MASK_FD);
1023 break;
1024
1025 case 'Y':
1026 (*info->fprintf_func) (info->stream, "$v%ld",
1027 (l >> OP_SH_FS) & OP_MASK_FS);
1028 break;
1029
1030 case 'Z':
1031 (*info->fprintf_func) (info->stream, "$v%ld",
1032 (l >> OP_SH_FT) & OP_MASK_FT);
1033 break;
1034
1035 default:
1036 /* xgettext:c-format */
1037 (*info->fprintf_func) (info->stream,
1038 _("# internal error, undefined modifier(%c)"),
1039 *d);
1040 return;
1041 }
1042 }
1043 }
1044 \f
1045 /* Print the mips instruction at address MEMADDR in debugged memory,
1046 on using INFO. Returns length of the instruction, in bytes, which is
1047 always INSNLEN. BIGENDIAN must be 1 if this is big-endian code, 0 if
1048 this is little-endian code. */
1049
1050 static int
1051 print_insn_mips (bfd_vma memaddr,
1052 unsigned long int word,
1053 struct disassemble_info *info)
1054 {
1055 const struct mips_opcode *op;
1056 static bfd_boolean init = 0;
1057 static const struct mips_opcode *mips_hash[OP_MASK_OP + 1];
1058
1059 /* Build a hash table to shorten the search time. */
1060 if (! init)
1061 {
1062 unsigned int i;
1063
1064 for (i = 0; i <= OP_MASK_OP; i++)
1065 {
1066 for (op = mips_opcodes; op < &mips_opcodes[NUMOPCODES]; op++)
1067 {
1068 if (op->pinfo == INSN_MACRO
1069 || (no_aliases && (op->pinfo2 & INSN2_ALIAS)))
1070 continue;
1071 if (i == ((op->match >> OP_SH_OP) & OP_MASK_OP))
1072 {
1073 mips_hash[i] = op;
1074 break;
1075 }
1076 }
1077 }
1078
1079 init = 1;
1080 }
1081
1082 info->bytes_per_chunk = INSNLEN;
1083 info->display_endian = info->endian;
1084 info->insn_info_valid = 1;
1085 info->branch_delay_insns = 0;
1086 info->data_size = 0;
1087 info->insn_type = dis_nonbranch;
1088 info->target = 0;
1089 info->target2 = 0;
1090
1091 op = mips_hash[(word >> OP_SH_OP) & OP_MASK_OP];
1092 if (op != NULL)
1093 {
1094 for (; op < &mips_opcodes[NUMOPCODES]; op++)
1095 {
1096 if (op->pinfo != INSN_MACRO
1097 && !(no_aliases && (op->pinfo2 & INSN2_ALIAS))
1098 && (word & op->mask) == op->match)
1099 {
1100 const char *d;
1101
1102 /* We always allow to disassemble the jalx instruction. */
1103 if (! OPCODE_IS_MEMBER (op, mips_isa, mips_processor)
1104 && strcmp (op->name, "jalx"))
1105 continue;
1106
1107 /* Figure out instruction type and branch delay information. */
1108 if ((op->pinfo & INSN_UNCOND_BRANCH_DELAY) != 0)
1109 {
1110 if ((info->insn_type & INSN_WRITE_GPR_31) != 0)
1111 info->insn_type = dis_jsr;
1112 else
1113 info->insn_type = dis_branch;
1114 info->branch_delay_insns = 1;
1115 }
1116 else if ((op->pinfo & (INSN_COND_BRANCH_DELAY
1117 | INSN_COND_BRANCH_LIKELY)) != 0)
1118 {
1119 if ((info->insn_type & INSN_WRITE_GPR_31) != 0)
1120 info->insn_type = dis_condjsr;
1121 else
1122 info->insn_type = dis_condbranch;
1123 info->branch_delay_insns = 1;
1124 }
1125 else if ((op->pinfo & (INSN_STORE_MEMORY
1126 | INSN_LOAD_MEMORY_DELAY)) != 0)
1127 info->insn_type = dis_dref;
1128
1129 (*info->fprintf_func) (info->stream, "%s", op->name);
1130
1131 d = op->args;
1132 if (d != NULL && *d != '\0')
1133 {
1134 (*info->fprintf_func) (info->stream, "\t");
1135 print_insn_args (d, word, memaddr, info);
1136 }
1137
1138 return INSNLEN;
1139 }
1140 }
1141 }
1142
1143 /* Handle undefined instructions. */
1144 info->insn_type = dis_noninsn;
1145 (*info->fprintf_func) (info->stream, "0x%lx", word);
1146 return INSNLEN;
1147 }
1148 \f
1149 /* Disassemble an operand for a mips16 instruction. */
1150
1151 static void
1152 print_mips16_insn_arg (char type,
1153 const struct mips_opcode *op,
1154 int l,
1155 bfd_boolean use_extend,
1156 int extend,
1157 bfd_vma memaddr,
1158 struct disassemble_info *info)
1159 {
1160 switch (type)
1161 {
1162 case ',':
1163 case '(':
1164 case ')':
1165 (*info->fprintf_func) (info->stream, "%c", type);
1166 break;
1167
1168 case 'y':
1169 case 'w':
1170 (*info->fprintf_func) (info->stream, "%s",
1171 mips16_reg_names[((l >> MIPS16OP_SH_RY)
1172 & MIPS16OP_MASK_RY)]);
1173 break;
1174
1175 case 'x':
1176 case 'v':
1177 (*info->fprintf_func) (info->stream, "%s",
1178 mips16_reg_names[((l >> MIPS16OP_SH_RX)
1179 & MIPS16OP_MASK_RX)]);
1180 break;
1181
1182 case 'z':
1183 (*info->fprintf_func) (info->stream, "%s",
1184 mips16_reg_names[((l >> MIPS16OP_SH_RZ)
1185 & MIPS16OP_MASK_RZ)]);
1186 break;
1187
1188 case 'Z':
1189 (*info->fprintf_func) (info->stream, "%s",
1190 mips16_reg_names[((l >> MIPS16OP_SH_MOVE32Z)
1191 & MIPS16OP_MASK_MOVE32Z)]);
1192 break;
1193
1194 case '0':
1195 (*info->fprintf_func) (info->stream, "%s", mips_gpr_names[0]);
1196 break;
1197
1198 case 'S':
1199 (*info->fprintf_func) (info->stream, "%s", mips_gpr_names[29]);
1200 break;
1201
1202 case 'P':
1203 (*info->fprintf_func) (info->stream, "$pc");
1204 break;
1205
1206 case 'R':
1207 (*info->fprintf_func) (info->stream, "%s", mips_gpr_names[31]);
1208 break;
1209
1210 case 'X':
1211 (*info->fprintf_func) (info->stream, "%s",
1212 mips_gpr_names[((l >> MIPS16OP_SH_REGR32)
1213 & MIPS16OP_MASK_REGR32)]);
1214 break;
1215
1216 case 'Y':
1217 (*info->fprintf_func) (info->stream, "%s",
1218 mips_gpr_names[MIPS16OP_EXTRACT_REG32R (l)]);
1219 break;
1220
1221 case '<':
1222 case '>':
1223 case '[':
1224 case ']':
1225 case '4':
1226 case '5':
1227 case 'H':
1228 case 'W':
1229 case 'D':
1230 case 'j':
1231 case '6':
1232 case '8':
1233 case 'V':
1234 case 'C':
1235 case 'U':
1236 case 'k':
1237 case 'K':
1238 case 'p':
1239 case 'q':
1240 case 'A':
1241 case 'B':
1242 case 'E':
1243 {
1244 int immed, nbits, shift, signedp, extbits, pcrel, extu, branch;
1245
1246 shift = 0;
1247 signedp = 0;
1248 extbits = 16;
1249 pcrel = 0;
1250 extu = 0;
1251 branch = 0;
1252 switch (type)
1253 {
1254 case '<':
1255 nbits = 3;
1256 immed = (l >> MIPS16OP_SH_RZ) & MIPS16OP_MASK_RZ;
1257 extbits = 5;
1258 extu = 1;
1259 break;
1260 case '>':
1261 nbits = 3;
1262 immed = (l >> MIPS16OP_SH_RX) & MIPS16OP_MASK_RX;
1263 extbits = 5;
1264 extu = 1;
1265 break;
1266 case '[':
1267 nbits = 3;
1268 immed = (l >> MIPS16OP_SH_RZ) & MIPS16OP_MASK_RZ;
1269 extbits = 6;
1270 extu = 1;
1271 break;
1272 case ']':
1273 nbits = 3;
1274 immed = (l >> MIPS16OP_SH_RX) & MIPS16OP_MASK_RX;
1275 extbits = 6;
1276 extu = 1;
1277 break;
1278 case '4':
1279 nbits = 4;
1280 immed = (l >> MIPS16OP_SH_IMM4) & MIPS16OP_MASK_IMM4;
1281 signedp = 1;
1282 extbits = 15;
1283 break;
1284 case '5':
1285 nbits = 5;
1286 immed = (l >> MIPS16OP_SH_IMM5) & MIPS16OP_MASK_IMM5;
1287 info->insn_type = dis_dref;
1288 info->data_size = 1;
1289 break;
1290 case 'H':
1291 nbits = 5;
1292 shift = 1;
1293 immed = (l >> MIPS16OP_SH_IMM5) & MIPS16OP_MASK_IMM5;
1294 info->insn_type = dis_dref;
1295 info->data_size = 2;
1296 break;
1297 case 'W':
1298 nbits = 5;
1299 shift = 2;
1300 immed = (l >> MIPS16OP_SH_IMM5) & MIPS16OP_MASK_IMM5;
1301 if ((op->pinfo & MIPS16_INSN_READ_PC) == 0
1302 && (op->pinfo & MIPS16_INSN_READ_SP) == 0)
1303 {
1304 info->insn_type = dis_dref;
1305 info->data_size = 4;
1306 }
1307 break;
1308 case 'D':
1309 nbits = 5;
1310 shift = 3;
1311 immed = (l >> MIPS16OP_SH_IMM5) & MIPS16OP_MASK_IMM5;
1312 info->insn_type = dis_dref;
1313 info->data_size = 8;
1314 break;
1315 case 'j':
1316 nbits = 5;
1317 immed = (l >> MIPS16OP_SH_IMM5) & MIPS16OP_MASK_IMM5;
1318 signedp = 1;
1319 break;
1320 case '6':
1321 nbits = 6;
1322 immed = (l >> MIPS16OP_SH_IMM6) & MIPS16OP_MASK_IMM6;
1323 break;
1324 case '8':
1325 nbits = 8;
1326 immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8;
1327 break;
1328 case 'V':
1329 nbits = 8;
1330 shift = 2;
1331 immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8;
1332 /* FIXME: This might be lw, or it might be addiu to $sp or
1333 $pc. We assume it's load. */
1334 info->insn_type = dis_dref;
1335 info->data_size = 4;
1336 break;
1337 case 'C':
1338 nbits = 8;
1339 shift = 3;
1340 immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8;
1341 info->insn_type = dis_dref;
1342 info->data_size = 8;
1343 break;
1344 case 'U':
1345 nbits = 8;
1346 immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8;
1347 extu = 1;
1348 break;
1349 case 'k':
1350 nbits = 8;
1351 immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8;
1352 signedp = 1;
1353 break;
1354 case 'K':
1355 nbits = 8;
1356 shift = 3;
1357 immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8;
1358 signedp = 1;
1359 break;
1360 case 'p':
1361 nbits = 8;
1362 immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8;
1363 signedp = 1;
1364 pcrel = 1;
1365 branch = 1;
1366 info->insn_type = dis_condbranch;
1367 break;
1368 case 'q':
1369 nbits = 11;
1370 immed = (l >> MIPS16OP_SH_IMM11) & MIPS16OP_MASK_IMM11;
1371 signedp = 1;
1372 pcrel = 1;
1373 branch = 1;
1374 info->insn_type = dis_branch;
1375 break;
1376 case 'A':
1377 nbits = 8;
1378 shift = 2;
1379 immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8;
1380 pcrel = 1;
1381 /* FIXME: This can be lw or la. We assume it is lw. */
1382 info->insn_type = dis_dref;
1383 info->data_size = 4;
1384 break;
1385 case 'B':
1386 nbits = 5;
1387 shift = 3;
1388 immed = (l >> MIPS16OP_SH_IMM5) & MIPS16OP_MASK_IMM5;
1389 pcrel = 1;
1390 info->insn_type = dis_dref;
1391 info->data_size = 8;
1392 break;
1393 case 'E':
1394 nbits = 5;
1395 shift = 2;
1396 immed = (l >> MIPS16OP_SH_IMM5) & MIPS16OP_MASK_IMM5;
1397 pcrel = 1;
1398 break;
1399 default:
1400 abort ();
1401 }
1402
1403 if (! use_extend)
1404 {
1405 if (signedp && immed >= (1 << (nbits - 1)))
1406 immed -= 1 << nbits;
1407 immed <<= shift;
1408 if ((type == '<' || type == '>' || type == '[' || type == ']')
1409 && immed == 0)
1410 immed = 8;
1411 }
1412 else
1413 {
1414 if (extbits == 16)
1415 immed |= ((extend & 0x1f) << 11) | (extend & 0x7e0);
1416 else if (extbits == 15)
1417 immed |= ((extend & 0xf) << 11) | (extend & 0x7f0);
1418 else
1419 immed = ((extend >> 6) & 0x1f) | (extend & 0x20);
1420 immed &= (1 << extbits) - 1;
1421 if (! extu && immed >= (1 << (extbits - 1)))
1422 immed -= 1 << extbits;
1423 }
1424
1425 if (! pcrel)
1426 (*info->fprintf_func) (info->stream, "%d", immed);
1427 else
1428 {
1429 bfd_vma baseaddr;
1430
1431 if (branch)
1432 {
1433 immed *= 2;
1434 baseaddr = memaddr + 2;
1435 }
1436 else if (use_extend)
1437 baseaddr = memaddr - 2;
1438 else
1439 {
1440 int status;
1441 bfd_byte buffer[2];
1442
1443 baseaddr = memaddr;
1444
1445 /* If this instruction is in the delay slot of a jr
1446 instruction, the base address is the address of the
1447 jr instruction. If it is in the delay slot of jalr
1448 instruction, the base address is the address of the
1449 jalr instruction. This test is unreliable: we have
1450 no way of knowing whether the previous word is
1451 instruction or data. */
1452 status = (*info->read_memory_func) (memaddr - 4, buffer, 2,
1453 info);
1454 if (status == 0
1455 && (((info->endian == BFD_ENDIAN_BIG
1456 ? bfd_getb16 (buffer)
1457 : bfd_getl16 (buffer))
1458 & 0xf800) == 0x1800))
1459 baseaddr = memaddr - 4;
1460 else
1461 {
1462 status = (*info->read_memory_func) (memaddr - 2, buffer,
1463 2, info);
1464 if (status == 0
1465 && (((info->endian == BFD_ENDIAN_BIG
1466 ? bfd_getb16 (buffer)
1467 : bfd_getl16 (buffer))
1468 & 0xf81f) == 0xe800))
1469 baseaddr = memaddr - 2;
1470 }
1471 }
1472 info->target = (baseaddr & ~((1 << shift) - 1)) + immed;
1473 (*info->print_address_func) (info->target, info);
1474 }
1475 }
1476 break;
1477
1478 case 'a':
1479 if (! use_extend)
1480 extend = 0;
1481 l = ((l & 0x1f) << 23) | ((l & 0x3e0) << 13) | (extend << 2);
1482 info->target = ((memaddr + 4) & ~(bfd_vma) 0x0fffffff) | l;
1483 (*info->print_address_func) (info->target, info);
1484 info->insn_type = dis_jsr;
1485 info->branch_delay_insns = 1;
1486 break;
1487
1488 case 'l':
1489 case 'L':
1490 {
1491 int need_comma, amask, smask;
1492
1493 need_comma = 0;
1494
1495 l = (l >> MIPS16OP_SH_IMM6) & MIPS16OP_MASK_IMM6;
1496
1497 amask = (l >> 3) & 7;
1498
1499 if (amask > 0 && amask < 5)
1500 {
1501 (*info->fprintf_func) (info->stream, "%s", mips_gpr_names[4]);
1502 if (amask > 1)
1503 (*info->fprintf_func) (info->stream, "-%s",
1504 mips_gpr_names[amask + 3]);
1505 need_comma = 1;
1506 }
1507
1508 smask = (l >> 1) & 3;
1509 if (smask == 3)
1510 {
1511 (*info->fprintf_func) (info->stream, "%s??",
1512 need_comma ? "," : "");
1513 need_comma = 1;
1514 }
1515 else if (smask > 0)
1516 {
1517 (*info->fprintf_func) (info->stream, "%s%s",
1518 need_comma ? "," : "",
1519 mips_gpr_names[16]);
1520 if (smask > 1)
1521 (*info->fprintf_func) (info->stream, "-%s",
1522 mips_gpr_names[smask + 15]);
1523 need_comma = 1;
1524 }
1525
1526 if (l & 1)
1527 {
1528 (*info->fprintf_func) (info->stream, "%s%s",
1529 need_comma ? "," : "",
1530 mips_gpr_names[31]);
1531 need_comma = 1;
1532 }
1533
1534 if (amask == 5 || amask == 6)
1535 {
1536 (*info->fprintf_func) (info->stream, "%s$f0",
1537 need_comma ? "," : "");
1538 if (amask == 6)
1539 (*info->fprintf_func) (info->stream, "-$f1");
1540 }
1541 }
1542 break;
1543
1544 default:
1545 /* xgettext:c-format */
1546 (*info->fprintf_func)
1547 (info->stream,
1548 _("# internal disassembler error, unrecognised modifier (%c)"),
1549 type);
1550 abort ();
1551 }
1552 }
1553
1554 /* Disassemble mips16 instructions. */
1555
1556 static int
1557 print_insn_mips16 (bfd_vma memaddr, struct disassemble_info *info)
1558 {
1559 int status;
1560 bfd_byte buffer[2];
1561 int length;
1562 int insn;
1563 bfd_boolean use_extend;
1564 int extend = 0;
1565 const struct mips_opcode *op, *opend;
1566
1567 info->bytes_per_chunk = 2;
1568 info->display_endian = info->endian;
1569 info->insn_info_valid = 1;
1570 info->branch_delay_insns = 0;
1571 info->data_size = 0;
1572 info->insn_type = dis_nonbranch;
1573 info->target = 0;
1574 info->target2 = 0;
1575
1576 status = (*info->read_memory_func) (memaddr, buffer, 2, info);
1577 if (status != 0)
1578 {
1579 (*info->memory_error_func) (status, memaddr, info);
1580 return -1;
1581 }
1582
1583 length = 2;
1584
1585 if (info->endian == BFD_ENDIAN_BIG)
1586 insn = bfd_getb16 (buffer);
1587 else
1588 insn = bfd_getl16 (buffer);
1589
1590 /* Handle the extend opcode specially. */
1591 use_extend = FALSE;
1592 if ((insn & 0xf800) == 0xf000)
1593 {
1594 use_extend = TRUE;
1595 extend = insn & 0x7ff;
1596
1597 memaddr += 2;
1598
1599 status = (*info->read_memory_func) (memaddr, buffer, 2, info);
1600 if (status != 0)
1601 {
1602 (*info->fprintf_func) (info->stream, "extend 0x%x",
1603 (unsigned int) extend);
1604 (*info->memory_error_func) (status, memaddr, info);
1605 return -1;
1606 }
1607
1608 if (info->endian == BFD_ENDIAN_BIG)
1609 insn = bfd_getb16 (buffer);
1610 else
1611 insn = bfd_getl16 (buffer);
1612
1613 /* Check for an extend opcode followed by an extend opcode. */
1614 if ((insn & 0xf800) == 0xf000)
1615 {
1616 (*info->fprintf_func) (info->stream, "extend 0x%x",
1617 (unsigned int) extend);
1618 info->insn_type = dis_noninsn;
1619 return length;
1620 }
1621
1622 length += 2;
1623 }
1624
1625 /* FIXME: Should probably use a hash table on the major opcode here. */
1626
1627 opend = mips16_opcodes + bfd_mips16_num_opcodes;
1628 for (op = mips16_opcodes; op < opend; op++)
1629 {
1630 if (op->pinfo != INSN_MACRO
1631 && !(no_aliases && (op->pinfo2 & INSN2_ALIAS))
1632 && (insn & op->mask) == op->match)
1633 {
1634 const char *s;
1635
1636 if (strchr (op->args, 'a') != NULL)
1637 {
1638 if (use_extend)
1639 {
1640 (*info->fprintf_func) (info->stream, "extend 0x%x",
1641 (unsigned int) extend);
1642 info->insn_type = dis_noninsn;
1643 return length - 2;
1644 }
1645
1646 use_extend = FALSE;
1647
1648 memaddr += 2;
1649
1650 status = (*info->read_memory_func) (memaddr, buffer, 2,
1651 info);
1652 if (status == 0)
1653 {
1654 use_extend = TRUE;
1655 if (info->endian == BFD_ENDIAN_BIG)
1656 extend = bfd_getb16 (buffer);
1657 else
1658 extend = bfd_getl16 (buffer);
1659 length += 2;
1660 }
1661 }
1662
1663 (*info->fprintf_func) (info->stream, "%s", op->name);
1664 if (op->args[0] != '\0')
1665 (*info->fprintf_func) (info->stream, "\t");
1666
1667 for (s = op->args; *s != '\0'; s++)
1668 {
1669 if (*s == ','
1670 && s[1] == 'w'
1671 && (((insn >> MIPS16OP_SH_RX) & MIPS16OP_MASK_RX)
1672 == ((insn >> MIPS16OP_SH_RY) & MIPS16OP_MASK_RY)))
1673 {
1674 /* Skip the register and the comma. */
1675 ++s;
1676 continue;
1677 }
1678 if (*s == ','
1679 && s[1] == 'v'
1680 && (((insn >> MIPS16OP_SH_RZ) & MIPS16OP_MASK_RZ)
1681 == ((insn >> MIPS16OP_SH_RX) & MIPS16OP_MASK_RX)))
1682 {
1683 /* Skip the register and the comma. */
1684 ++s;
1685 continue;
1686 }
1687 print_mips16_insn_arg (*s, op, insn, use_extend, extend, memaddr,
1688 info);
1689 }
1690
1691 if ((op->pinfo & INSN_UNCOND_BRANCH_DELAY) != 0)
1692 {
1693 info->branch_delay_insns = 1;
1694 if (info->insn_type != dis_jsr)
1695 info->insn_type = dis_branch;
1696 }
1697
1698 return length;
1699 }
1700 }
1701
1702 if (use_extend)
1703 (*info->fprintf_func) (info->stream, "0x%x", extend | 0xf000);
1704 (*info->fprintf_func) (info->stream, "0x%x", insn);
1705 info->insn_type = dis_noninsn;
1706
1707 return length;
1708 }
1709
1710 /* In an environment where we do not know the symbol type of the
1711 instruction we are forced to assume that the low order bit of the
1712 instructions' address may mark it as a mips16 instruction. If we
1713 are single stepping, or the pc is within the disassembled function,
1714 this works. Otherwise, we need a clue. Sometimes. */
1715
1716 static int
1717 _print_insn_mips (bfd_vma memaddr,
1718 struct disassemble_info *info,
1719 enum bfd_endian endianness)
1720 {
1721 bfd_byte buffer[INSNLEN];
1722 int status;
1723
1724 set_default_mips_dis_options (info);
1725 parse_mips_dis_options (info->disassembler_options);
1726
1727 #if 1
1728 /* FIXME: If odd address, this is CLEARLY a mips 16 instruction. */
1729 /* Only a few tools will work this way. */
1730 if (memaddr & 0x01)
1731 return print_insn_mips16 (memaddr, info);
1732 #endif
1733
1734 #if SYMTAB_AVAILABLE
1735 if (info->mach == bfd_mach_mips16
1736 || (info->flavour == bfd_target_elf_flavour
1737 && info->symbols != NULL
1738 && ((*(elf_symbol_type **) info->symbols)->internal_elf_sym.st_other
1739 == STO_MIPS16)))
1740 return print_insn_mips16 (memaddr, info);
1741 #endif
1742
1743 status = (*info->read_memory_func) (memaddr, buffer, INSNLEN, info);
1744 if (status == 0)
1745 {
1746 unsigned long insn;
1747
1748 if (endianness == BFD_ENDIAN_BIG)
1749 insn = (unsigned long) bfd_getb32 (buffer);
1750 else
1751 insn = (unsigned long) bfd_getl32 (buffer);
1752
1753 return print_insn_mips (memaddr, insn, info);
1754 }
1755 else
1756 {
1757 (*info->memory_error_func) (status, memaddr, info);
1758 return -1;
1759 }
1760 }
1761
1762 int
1763 print_insn_big_mips (bfd_vma memaddr, struct disassemble_info *info)
1764 {
1765 return _print_insn_mips (memaddr, info, BFD_ENDIAN_BIG);
1766 }
1767
1768 int
1769 print_insn_little_mips (bfd_vma memaddr, struct disassemble_info *info)
1770 {
1771 return _print_insn_mips (memaddr, info, BFD_ENDIAN_LITTLE);
1772 }
1773 \f
1774 void
1775 print_mips_disassembler_options (FILE *stream)
1776 {
1777 unsigned int i;
1778
1779 fprintf (stream, _("\n\
1780 The following MIPS specific disassembler options are supported for use\n\
1781 with the -M switch (multiple options should be separated by commas):\n"));
1782
1783 fprintf (stream, _("\n\
1784 gpr-names=ABI Print GPR names according to specified ABI.\n\
1785 Default: based on binary being disassembled.\n"));
1786
1787 fprintf (stream, _("\n\
1788 fpr-names=ABI Print FPR names according to specified ABI.\n\
1789 Default: numeric.\n"));
1790
1791 fprintf (stream, _("\n\
1792 cp0-names=ARCH Print CP0 register names according to\n\
1793 specified architecture.\n\
1794 Default: based on binary being disassembled.\n"));
1795
1796 fprintf (stream, _("\n\
1797 hwr-names=ARCH Print HWR names according to specified \n\
1798 architecture.\n\
1799 Default: based on binary being disassembled.\n"));
1800
1801 fprintf (stream, _("\n\
1802 reg-names=ABI Print GPR and FPR names according to\n\
1803 specified ABI.\n"));
1804
1805 fprintf (stream, _("\n\
1806 reg-names=ARCH Print CP0 register and HWR names according to\n\
1807 specified architecture.\n"));
1808
1809 fprintf (stream, _("\n\
1810 For the options above, the following values are supported for \"ABI\":\n\
1811 "));
1812 for (i = 0; i < ARRAY_SIZE (mips_abi_choices); i++)
1813 fprintf (stream, " %s", mips_abi_choices[i].name);
1814 fprintf (stream, _("\n"));
1815
1816 fprintf (stream, _("\n\
1817 For the options above, The following values are supported for \"ARCH\":\n\
1818 "));
1819 for (i = 0; i < ARRAY_SIZE (mips_arch_choices); i++)
1820 if (*mips_arch_choices[i].name != '\0')
1821 fprintf (stream, " %s", mips_arch_choices[i].name);
1822 fprintf (stream, _("\n"));
1823
1824 fprintf (stream, _("\n"));
1825 }
GDB Binutils - Deliverables
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