1 /* Print mips instructions for GDB, the GNU debugger, or for objdump.
2 Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
4 Free Software Foundation, Inc.
5 Contributed by Nobuyuki Hikichi(hikichi@sra.co.jp).
7 This file is part of GDB, GAS, and the GNU binutils.
9 This program is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 2 of the License, or
12 (at your option) any later version.
14 This program is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with this program; if not, write to the Free Software
21 Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
25 #include "opcode/mips.h"
28 /* FIXME: These are needed to figure out if the code is mips16 or
29 not. The low bit of the address is often a good indicator. No
30 symbol table is available when this code runs out in an embedded
31 system as when it is used for disassembler support in a monitor. */
33 #if !defined(EMBEDDED_ENV)
34 #define SYMTAB_AVAILABLE 1
39 /* Mips instructions are at maximum this many bytes long. */
42 static int _print_insn_mips
43 PARAMS ((bfd_vma
, struct disassemble_info
*, enum bfd_endian
));
44 static int print_insn_mips
45 PARAMS ((bfd_vma
, unsigned long int, struct disassemble_info
*));
46 static void print_insn_arg
47 PARAMS ((const char *, unsigned long, bfd_vma
, struct disassemble_info
*));
48 static int print_insn_mips16
49 PARAMS ((bfd_vma
, struct disassemble_info
*));
50 static void print_mips16_insn_arg
51 PARAMS ((int, const struct mips_opcode
*, int, boolean
, int, bfd_vma
,
52 struct disassemble_info
*));
54 /* FIXME: These should be shared with gdb somehow. */
56 /* The mips16 register names. */
57 static const char * const mips16_reg_names
[] =
59 "s0", "s1", "v0", "v1", "a0", "a1", "a2", "a3"
62 static const char * const mips32_reg_names
[] =
64 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
65 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7",
66 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
67 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra",
68 "sr", "lo", "hi", "bad", "cause", "pc",
69 "fv0", "$f1", "fv1", "$f3", "ft0", "$f5", "ft1", "$f7",
70 "ft2", "$f9", "ft3", "$f11", "fa0", "$f13", "fa1", "$f15",
71 "ft4", "f17", "ft5", "f19", "fs0", "f21", "fs1", "f23",
72 "fs2", "$f25", "fs3", "$f27", "fs4", "$f29", "fs5", "$f31",
73 "fsr", "fir", "fp", "inx", "rand", "tlblo", "ctxt", "tlbhi",
77 static const char * const mips64_reg_names
[] =
79 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
80 "a4", "a5", "a6", "a7", "t0", "t1", "t2", "t3",
81 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
82 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra",
83 "sr", "lo", "hi", "bad", "cause", "pc",
84 "fv0", "$f1", "fv1", "$f3", "ft0", "ft1", "ft2", "ft3",
85 "ft4", "ft5", "ft6", "ft7", "fa0", "fa1", "fa2", "fa3",
86 "fa4", "fa5", "fa6", "fa7", "ft8", "ft9", "ft10", "ft11",
87 "fs0", "fs1", "fs2", "fs3", "fs4", "fs5", "fs6", "fs7",
88 "fsr", "fir", "fp", "inx", "rand", "tlblo", "ctxt", "tlbhi",
92 /* Scalar register names. _print_insn_mips() decides which register name
94 static const char * const *reg_names
= NULL
;
96 /* Print insn arguments for 32/64-bit code */
99 print_insn_arg (d
, l
, pc
, info
)
101 register unsigned long int l
;
103 struct disassemble_info
*info
;
112 (*info
->fprintf_func
) (info
->stream
, "%c", *d
);
119 (*info
->fprintf_func
) (info
->stream
, "%s",
120 reg_names
[(l
>> OP_SH_RS
) & OP_MASK_RS
]);
125 (*info
->fprintf_func
) (info
->stream
, "%s",
126 reg_names
[(l
>> OP_SH_RT
) & OP_MASK_RT
]);
131 (*info
->fprintf_func
) (info
->stream
, "0x%x",
132 (l
>> OP_SH_IMMEDIATE
) & OP_MASK_IMMEDIATE
);
135 case 'j': /* same as i, but sign-extended */
137 delta
= (l
>> OP_SH_DELTA
) & OP_MASK_DELTA
;
140 (*info
->fprintf_func
) (info
->stream
, "%d",
145 (*info
->fprintf_func
) (info
->stream
, "0x%x",
146 (unsigned int) ((l
>> OP_SH_PREFX
)
151 (*info
->fprintf_func
) (info
->stream
, "0x%x",
152 (unsigned int) ((l
>> OP_SH_CACHE
)
157 (*info
->print_address_func
)
158 ((((pc
+ 4) & ~ (bfd_vma
) 0x0fffffff)
159 | (((l
>> OP_SH_TARGET
) & OP_MASK_TARGET
) << 2)),
164 /* sign extend the displacement */
165 delta
= (l
>> OP_SH_DELTA
) & OP_MASK_DELTA
;
168 (*info
->print_address_func
)
169 ((delta
<< 2) + pc
+ INSNLEN
,
174 (*info
->fprintf_func
) (info
->stream
, "%s",
175 reg_names
[(l
>> OP_SH_RD
) & OP_MASK_RD
]);
180 /* First check for both rd and rt being equal. */
181 unsigned int reg
= (l
>> OP_SH_RD
) & OP_MASK_RD
;
182 if (reg
== ((l
>> OP_SH_RT
) & OP_MASK_RT
))
183 (*info
->fprintf_func
) (info
->stream
, "%s",
187 /* If one is zero use the other. */
189 (*info
->fprintf_func
) (info
->stream
, "%s",
190 reg_names
[(l
>> OP_SH_RT
) & OP_MASK_RT
]);
191 else if (((l
>> OP_SH_RT
) & OP_MASK_RT
) == 0)
192 (*info
->fprintf_func
) (info
->stream
, "%s",
194 else /* Bogus, result depends on processor. */
195 (*info
->fprintf_func
) (info
->stream
, "%s or %s",
197 reg_names
[(l
>> OP_SH_RT
) & OP_MASK_RT
]);
203 (*info
->fprintf_func
) (info
->stream
, "%s", reg_names
[0]);
207 (*info
->fprintf_func
) (info
->stream
, "0x%x",
208 (l
>> OP_SH_SHAMT
) & OP_MASK_SHAMT
);
212 (*info
->fprintf_func
) (info
->stream
, "0x%x",
213 (l
>> OP_SH_CODE
) & OP_MASK_CODE
);
217 (*info
->fprintf_func
) (info
->stream
, "0x%x",
218 (l
>> OP_SH_CODE2
) & OP_MASK_CODE2
);
222 (*info
->fprintf_func
) (info
->stream
, "0x%x",
223 (l
>> OP_SH_COPZ
) & OP_MASK_COPZ
);
227 (*info
->fprintf_func
) (info
->stream
, "0x%x",
228 (l
>> OP_SH_CODE20
) & OP_MASK_CODE20
);
232 (*info
->fprintf_func
) (info
->stream
, "0x%x",
233 (l
>> OP_SH_CODE19
) & OP_MASK_CODE19
);
238 (*info
->fprintf_func
) (info
->stream
, "$f%d",
239 (l
>> OP_SH_FS
) & OP_MASK_FS
);
244 (*info
->fprintf_func
) (info
->stream
, "$f%d",
245 (l
>> OP_SH_FT
) & OP_MASK_FT
);
249 (*info
->fprintf_func
) (info
->stream
, "$f%d",
250 (l
>> OP_SH_FD
) & OP_MASK_FD
);
254 (*info
->fprintf_func
) (info
->stream
, "$f%d",
255 (l
>> OP_SH_FR
) & OP_MASK_FR
);
259 (*info
->fprintf_func
) (info
->stream
, "%s",
260 reg_names
[(l
>> OP_SH_RT
) & OP_MASK_RT
]);
264 (*info
->fprintf_func
) (info
->stream
, "%s",
265 reg_names
[(l
>> OP_SH_RD
) & OP_MASK_RD
]);
269 (*info
->fprintf_func
) (info
->stream
, "$fcc%d",
270 (l
>> OP_SH_BCC
) & OP_MASK_BCC
);
274 (*info
->fprintf_func
) (info
->stream
, "$fcc%d",
275 (l
>> OP_SH_CCC
) & OP_MASK_CCC
);
279 (*info
->fprintf_func
) (info
->stream
, "%d",
280 (l
>> OP_SH_PERFREG
) & OP_MASK_PERFREG
);
284 (*info
->fprintf_func
) (info
->stream
, "%d",
285 (l
>> OP_SH_SEL
) & OP_MASK_SEL
);
289 /* xgettext:c-format */
290 (*info
->fprintf_func
) (info
->stream
,
291 _("# internal error, undefined modifier(%c)"),
297 /* Figure out the MIPS ISA and CPU based on the machine number. */
300 mips_isa_type (mach
, isa
, cputype
)
307 case bfd_mach_mips3000
:
308 *cputype
= CPU_R3000
;
311 case bfd_mach_mips3900
:
312 *cputype
= CPU_R3900
;
315 case bfd_mach_mips4000
:
316 *cputype
= CPU_R4000
;
319 case bfd_mach_mips4010
:
320 *cputype
= CPU_R4010
;
323 case bfd_mach_mips4100
:
324 *cputype
= CPU_VR4100
;
327 case bfd_mach_mips4111
:
328 *cputype
= CPU_R4111
;
331 case bfd_mach_mips4300
:
332 *cputype
= CPU_R4300
;
335 case bfd_mach_mips4400
:
336 *cputype
= CPU_R4400
;
339 case bfd_mach_mips4600
:
340 *cputype
= CPU_R4600
;
343 case bfd_mach_mips4650
:
344 *cputype
= CPU_R4650
;
347 case bfd_mach_mips5000
:
348 *cputype
= CPU_R5000
;
351 case bfd_mach_mips6000
:
352 *cputype
= CPU_R6000
;
355 case bfd_mach_mips8000
:
356 *cputype
= CPU_R8000
;
359 case bfd_mach_mips10000
:
360 *cputype
= CPU_R10000
;
363 case bfd_mach_mips12000
:
364 *cputype
= CPU_R12000
;
367 case bfd_mach_mips16
:
368 *cputype
= CPU_MIPS16
;
371 case bfd_mach_mips32
:
372 *cputype
= CPU_MIPS32
;
375 case bfd_mach_mips32_4k
:
376 *cputype
= CPU_MIPS32_4K
;
380 *cputype
= CPU_MIPS5
;
383 case bfd_mach_mips64
:
384 *cputype
= CPU_MIPS64
;
387 case bfd_mach_mips_sb1
:
392 *cputype
= CPU_R3000
;
398 /* Figure out ISA from disassemble_info data */
402 struct disassemble_info
*info
;
407 mips_isa_type (info
->mach
, &isa
, &cpu
);
411 /* Print the mips instruction at address MEMADDR in debugged memory,
412 on using INFO. Returns length of the instruction, in bytes, which is
413 always INSNLEN. BIGENDIAN must be 1 if this is big-endian code, 0 if
414 this is little-endian code. */
417 print_insn_mips (memaddr
, word
, info
)
419 unsigned long int word
;
420 struct disassemble_info
*info
;
422 register const struct mips_opcode
*op
;
423 int target_processor
, mips_isa
;
424 static boolean init
= 0;
425 static const struct mips_opcode
*mips_hash
[OP_MASK_OP
+ 1];
427 /* Build a hash table to shorten the search time. */
432 for (i
= 0; i
<= OP_MASK_OP
; i
++)
434 for (op
= mips_opcodes
; op
< &mips_opcodes
[NUMOPCODES
]; op
++)
436 if (op
->pinfo
== INSN_MACRO
)
438 if (i
== ((op
->match
>> OP_SH_OP
) & OP_MASK_OP
))
449 #if ! SYMTAB_AVAILABLE
450 /* This is running out on a target machine, not in a host tool.
451 FIXME: Where does mips_target_info come from? */
452 target_processor
= mips_target_info
.processor
;
453 mips_isa
= mips_target_info
.isa
;
455 mips_isa_type (info
->mach
, &mips_isa
, &target_processor
);
458 info
->bytes_per_chunk
= INSNLEN
;
459 info
->display_endian
= info
->endian
;
461 op
= mips_hash
[(word
>> OP_SH_OP
) & OP_MASK_OP
];
464 for (; op
< &mips_opcodes
[NUMOPCODES
]; op
++)
466 if (op
->pinfo
!= INSN_MACRO
&& (word
& op
->mask
) == op
->match
)
468 register const char *d
;
470 if (! OPCODE_IS_MEMBER (op
, mips_isa
, target_processor
, 0))
473 (*info
->fprintf_func
) (info
->stream
, "%s", op
->name
);
476 if (d
!= NULL
&& *d
!= '\0')
478 (*info
->fprintf_func
) (info
->stream
, "\t");
479 for (; *d
!= '\0'; d
++)
480 print_insn_arg (d
, word
, memaddr
, info
);
488 /* Handle undefined instructions. */
489 (*info
->fprintf_func
) (info
->stream
, "0x%x", word
);
493 /* In an environment where we do not know the symbol type of the
494 instruction we are forced to assume that the low order bit of the
495 instructions' address may mark it as a mips16 instruction. If we
496 are single stepping, or the pc is within the disassembled function,
497 this works. Otherwise, we need a clue. Sometimes. */
500 _print_insn_mips (memaddr
, info
, endianness
)
502 struct disassemble_info
*info
;
503 enum bfd_endian endianness
;
505 bfd_byte buffer
[INSNLEN
];
509 /* FIXME: If odd address, this is CLEARLY a mips 16 instruction. */
510 /* Only a few tools will work this way. */
512 return print_insn_mips16 (memaddr
, info
);
517 || (info
->flavour
== bfd_target_elf_flavour
518 && info
->symbols
!= NULL
519 && ((*(elf_symbol_type
**) info
->symbols
)->internal_elf_sym
.st_other
521 return print_insn_mips16 (memaddr
, info
);
524 /* Use mips64_reg_names for new ABI. */
525 if (info
->flavour
== bfd_target_elf_flavour
526 && info
->symbols
!= NULL
527 && (((get_mips_isa(info
) | INSN_ISA_MASK
) & ISA_MIPS2
) != 0)
528 && ((elf_elfheader (bfd_asymbol_bfd(*(info
->symbols
)))->e_flags
529 & EF_MIPS_ABI2
) != 0))
530 reg_names
= mips64_reg_names
;
532 reg_names
= mips32_reg_names
;
534 status
= (*info
->read_memory_func
) (memaddr
, buffer
, INSNLEN
, info
);
539 if (endianness
== BFD_ENDIAN_BIG
)
540 insn
= (unsigned long) bfd_getb32 (buffer
);
542 insn
= (unsigned long) bfd_getl32 (buffer
);
544 return print_insn_mips (memaddr
, insn
, info
);
548 (*info
->memory_error_func
) (status
, memaddr
, info
);
554 print_insn_big_mips (memaddr
, info
)
556 struct disassemble_info
*info
;
558 return _print_insn_mips (memaddr
, info
, BFD_ENDIAN_BIG
);
562 print_insn_little_mips (memaddr
, info
)
564 struct disassemble_info
*info
;
566 return _print_insn_mips (memaddr
, info
, BFD_ENDIAN_LITTLE
);
569 /* Disassemble mips16 instructions. */
572 print_insn_mips16 (memaddr
, info
)
574 struct disassemble_info
*info
;
582 const struct mips_opcode
*op
, *opend
;
584 info
->bytes_per_chunk
= 2;
585 info
->display_endian
= info
->endian
;
586 info
->insn_info_valid
= 1;
587 info
->branch_delay_insns
= 0;
589 info
->insn_type
= dis_nonbranch
;
593 status
= (*info
->read_memory_func
) (memaddr
, buffer
, 2, info
);
596 (*info
->memory_error_func
) (status
, memaddr
, info
);
602 if (info
->endian
== BFD_ENDIAN_BIG
)
603 insn
= bfd_getb16 (buffer
);
605 insn
= bfd_getl16 (buffer
);
607 /* Handle the extend opcode specially. */
609 if ((insn
& 0xf800) == 0xf000)
612 extend
= insn
& 0x7ff;
616 status
= (*info
->read_memory_func
) (memaddr
, buffer
, 2, info
);
619 (*info
->fprintf_func
) (info
->stream
, "extend 0x%x",
620 (unsigned int) extend
);
621 (*info
->memory_error_func
) (status
, memaddr
, info
);
625 if (info
->endian
== BFD_ENDIAN_BIG
)
626 insn
= bfd_getb16 (buffer
);
628 insn
= bfd_getl16 (buffer
);
630 /* Check for an extend opcode followed by an extend opcode. */
631 if ((insn
& 0xf800) == 0xf000)
633 (*info
->fprintf_func
) (info
->stream
, "extend 0x%x",
634 (unsigned int) extend
);
635 info
->insn_type
= dis_noninsn
;
642 /* FIXME: Should probably use a hash table on the major opcode here. */
644 opend
= mips16_opcodes
+ bfd_mips16_num_opcodes
;
645 for (op
= mips16_opcodes
; op
< opend
; op
++)
647 if (op
->pinfo
!= INSN_MACRO
&& (insn
& op
->mask
) == op
->match
)
651 if (strchr (op
->args
, 'a') != NULL
)
655 (*info
->fprintf_func
) (info
->stream
, "extend 0x%x",
656 (unsigned int) extend
);
657 info
->insn_type
= dis_noninsn
;
665 status
= (*info
->read_memory_func
) (memaddr
, buffer
, 2,
670 if (info
->endian
== BFD_ENDIAN_BIG
)
671 extend
= bfd_getb16 (buffer
);
673 extend
= bfd_getl16 (buffer
);
678 (*info
->fprintf_func
) (info
->stream
, "%s", op
->name
);
679 if (op
->args
[0] != '\0')
680 (*info
->fprintf_func
) (info
->stream
, "\t");
682 for (s
= op
->args
; *s
!= '\0'; s
++)
686 && (((insn
>> MIPS16OP_SH_RX
) & MIPS16OP_MASK_RX
)
687 == ((insn
>> MIPS16OP_SH_RY
) & MIPS16OP_MASK_RY
)))
689 /* Skip the register and the comma. */
695 && (((insn
>> MIPS16OP_SH_RZ
) & MIPS16OP_MASK_RZ
)
696 == ((insn
>> MIPS16OP_SH_RX
) & MIPS16OP_MASK_RX
)))
698 /* Skip the register and the comma. */
702 print_mips16_insn_arg (*s
, op
, insn
, use_extend
, extend
, memaddr
,
706 if ((op
->pinfo
& INSN_UNCOND_BRANCH_DELAY
) != 0)
708 info
->branch_delay_insns
= 1;
709 if (info
->insn_type
!= dis_jsr
)
710 info
->insn_type
= dis_branch
;
718 (*info
->fprintf_func
) (info
->stream
, "0x%x", extend
| 0xf000);
719 (*info
->fprintf_func
) (info
->stream
, "0x%x", insn
);
720 info
->insn_type
= dis_noninsn
;
725 /* Disassemble an operand for a mips16 instruction. */
728 print_mips16_insn_arg (type
, op
, l
, use_extend
, extend
, memaddr
, info
)
730 const struct mips_opcode
*op
;
735 struct disassemble_info
*info
;
742 (*info
->fprintf_func
) (info
->stream
, "%c", type
);
747 (*info
->fprintf_func
) (info
->stream
, "%s",
748 mips16_reg_names
[((l
>> MIPS16OP_SH_RY
)
749 & MIPS16OP_MASK_RY
)]);
754 (*info
->fprintf_func
) (info
->stream
, "%s",
755 mips16_reg_names
[((l
>> MIPS16OP_SH_RX
)
756 & MIPS16OP_MASK_RX
)]);
760 (*info
->fprintf_func
) (info
->stream
, "%s",
761 mips16_reg_names
[((l
>> MIPS16OP_SH_RZ
)
762 & MIPS16OP_MASK_RZ
)]);
766 (*info
->fprintf_func
) (info
->stream
, "%s",
767 mips16_reg_names
[((l
>> MIPS16OP_SH_MOVE32Z
)
768 & MIPS16OP_MASK_MOVE32Z
)]);
772 (*info
->fprintf_func
) (info
->stream
, "%s", mips32_reg_names
[0]);
776 (*info
->fprintf_func
) (info
->stream
, "%s", mips32_reg_names
[29]);
780 (*info
->fprintf_func
) (info
->stream
, "$pc");
784 (*info
->fprintf_func
) (info
->stream
, "%s", mips32_reg_names
[31]);
788 (*info
->fprintf_func
) (info
->stream
, "%s",
789 mips32_reg_names
[((l
>> MIPS16OP_SH_REGR32
)
790 & MIPS16OP_MASK_REGR32
)]);
794 (*info
->fprintf_func
) (info
->stream
, "%s",
795 mips32_reg_names
[MIPS16OP_EXTRACT_REG32R (l
)]);
821 int immed
, nbits
, shift
, signedp
, extbits
, pcrel
, extu
, branch
;
833 immed
= (l
>> MIPS16OP_SH_RZ
) & MIPS16OP_MASK_RZ
;
839 immed
= (l
>> MIPS16OP_SH_RX
) & MIPS16OP_MASK_RX
;
845 immed
= (l
>> MIPS16OP_SH_RZ
) & MIPS16OP_MASK_RZ
;
851 immed
= (l
>> MIPS16OP_SH_RX
) & MIPS16OP_MASK_RX
;
857 immed
= (l
>> MIPS16OP_SH_IMM4
) & MIPS16OP_MASK_IMM4
;
863 immed
= (l
>> MIPS16OP_SH_IMM5
) & MIPS16OP_MASK_IMM5
;
864 info
->insn_type
= dis_dref
;
870 immed
= (l
>> MIPS16OP_SH_IMM5
) & MIPS16OP_MASK_IMM5
;
871 info
->insn_type
= dis_dref
;
877 immed
= (l
>> MIPS16OP_SH_IMM5
) & MIPS16OP_MASK_IMM5
;
878 if ((op
->pinfo
& MIPS16_INSN_READ_PC
) == 0
879 && (op
->pinfo
& MIPS16_INSN_READ_SP
) == 0)
881 info
->insn_type
= dis_dref
;
888 immed
= (l
>> MIPS16OP_SH_IMM5
) & MIPS16OP_MASK_IMM5
;
889 info
->insn_type
= dis_dref
;
894 immed
= (l
>> MIPS16OP_SH_IMM5
) & MIPS16OP_MASK_IMM5
;
899 immed
= (l
>> MIPS16OP_SH_IMM6
) & MIPS16OP_MASK_IMM6
;
903 immed
= (l
>> MIPS16OP_SH_IMM8
) & MIPS16OP_MASK_IMM8
;
908 immed
= (l
>> MIPS16OP_SH_IMM8
) & MIPS16OP_MASK_IMM8
;
909 /* FIXME: This might be lw, or it might be addiu to $sp or
910 $pc. We assume it's load. */
911 info
->insn_type
= dis_dref
;
917 immed
= (l
>> MIPS16OP_SH_IMM8
) & MIPS16OP_MASK_IMM8
;
918 info
->insn_type
= dis_dref
;
923 immed
= (l
>> MIPS16OP_SH_IMM8
) & MIPS16OP_MASK_IMM8
;
928 immed
= (l
>> MIPS16OP_SH_IMM8
) & MIPS16OP_MASK_IMM8
;
934 immed
= (l
>> MIPS16OP_SH_IMM8
) & MIPS16OP_MASK_IMM8
;
939 immed
= (l
>> MIPS16OP_SH_IMM8
) & MIPS16OP_MASK_IMM8
;
943 info
->insn_type
= dis_condbranch
;
947 immed
= (l
>> MIPS16OP_SH_IMM11
) & MIPS16OP_MASK_IMM11
;
951 info
->insn_type
= dis_branch
;
956 immed
= (l
>> MIPS16OP_SH_IMM8
) & MIPS16OP_MASK_IMM8
;
958 /* FIXME: This can be lw or la. We assume it is lw. */
959 info
->insn_type
= dis_dref
;
965 immed
= (l
>> MIPS16OP_SH_IMM5
) & MIPS16OP_MASK_IMM5
;
967 info
->insn_type
= dis_dref
;
973 immed
= (l
>> MIPS16OP_SH_IMM5
) & MIPS16OP_MASK_IMM5
;
982 if (signedp
&& immed
>= (1 << (nbits
- 1)))
985 if ((type
== '<' || type
== '>' || type
== '[' || type
== ']')
992 immed
|= ((extend
& 0x1f) << 11) | (extend
& 0x7e0);
993 else if (extbits
== 15)
994 immed
|= ((extend
& 0xf) << 11) | (extend
& 0x7f0);
996 immed
= ((extend
>> 6) & 0x1f) | (extend
& 0x20);
997 immed
&= (1 << extbits
) - 1;
998 if (! extu
&& immed
>= (1 << (extbits
- 1)))
999 immed
-= 1 << extbits
;
1003 (*info
->fprintf_func
) (info
->stream
, "%d", immed
);
1012 baseaddr
= memaddr
+ 2;
1014 else if (use_extend
)
1015 baseaddr
= memaddr
- 2;
1023 /* If this instruction is in the delay slot of a jr
1024 instruction, the base address is the address of the
1025 jr instruction. If it is in the delay slot of jalr
1026 instruction, the base address is the address of the
1027 jalr instruction. This test is unreliable: we have
1028 no way of knowing whether the previous word is
1029 instruction or data. */
1030 status
= (*info
->read_memory_func
) (memaddr
- 4, buffer
, 2,
1033 && (((info
->endian
== BFD_ENDIAN_BIG
1034 ? bfd_getb16 (buffer
)
1035 : bfd_getl16 (buffer
))
1036 & 0xf800) == 0x1800))
1037 baseaddr
= memaddr
- 4;
1040 status
= (*info
->read_memory_func
) (memaddr
- 2, buffer
,
1043 && (((info
->endian
== BFD_ENDIAN_BIG
1044 ? bfd_getb16 (buffer
)
1045 : bfd_getl16 (buffer
))
1046 & 0xf81f) == 0xe800))
1047 baseaddr
= memaddr
- 2;
1050 val
= (baseaddr
& ~ ((1 << shift
) - 1)) + immed
;
1051 (*info
->print_address_func
) (val
, info
);
1060 l
= ((l
& 0x1f) << 23) | ((l
& 0x3e0) << 13) | (extend
<< 2);
1061 (*info
->print_address_func
) (((memaddr
+ 4) & 0xf0000000) | l
, info
);
1062 info
->insn_type
= dis_jsr
;
1063 info
->target
= ((memaddr
+ 4) & 0xf0000000) | l
;
1064 info
->branch_delay_insns
= 1;
1070 int need_comma
, amask
, smask
;
1074 l
= (l
>> MIPS16OP_SH_IMM6
) & MIPS16OP_MASK_IMM6
;
1076 amask
= (l
>> 3) & 7;
1078 if (amask
> 0 && amask
< 5)
1080 (*info
->fprintf_func
) (info
->stream
, "%s", mips32_reg_names
[4]);
1082 (*info
->fprintf_func
) (info
->stream
, "-%s",
1083 mips32_reg_names
[amask
+ 3]);
1087 smask
= (l
>> 1) & 3;
1090 (*info
->fprintf_func
) (info
->stream
, "%s??",
1091 need_comma
? "," : "");
1096 (*info
->fprintf_func
) (info
->stream
, "%s%s",
1097 need_comma
? "," : "",
1098 mips32_reg_names
[16]);
1100 (*info
->fprintf_func
) (info
->stream
, "-%s",
1101 mips32_reg_names
[smask
+ 15]);
1107 (*info
->fprintf_func
) (info
->stream
, "%s%s",
1108 need_comma
? "," : "",
1109 mips32_reg_names
[31]);
1113 if (amask
== 5 || amask
== 6)
1115 (*info
->fprintf_func
) (info
->stream
, "%s$f0",
1116 need_comma
? "," : "");
1118 (*info
->fprintf_func
) (info
->stream
, "-$f1");
1124 /* xgettext:c-format */
1125 (*info
->fprintf_func
)
1127 _("# internal disassembler error, unrecognised modifier (%c)"),
This page took 0.062541 seconds and 4 git commands to generate.