1 /* Print mips instructions for GDB, the GNU debugger, or for objdump.
2 Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
4 Free Software Foundation, Inc.
5 Contributed by Nobuyuki Hikichi(hikichi@sra.co.jp).
7 This file is part of GDB, GAS, and the GNU binutils.
9 This program is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 2 of the License, or
12 (at your option) any later version.
14 This program is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with this program; if not, write to the Free Software
21 Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
25 #include "opcode/mips.h"
28 /* FIXME: These are needed to figure out if the code is mips16 or
29 not. The low bit of the address is often a good indicator. No
30 symbol table is available when this code runs out in an embedded
31 system as when it is used for disassembler support in a monitor. */
33 #if !defined(EMBEDDED_ENV)
34 #define SYMTAB_AVAILABLE 1
39 /* Mips instructions are at maximum this many bytes long. */
42 static int _print_insn_mips
43 PARAMS ((bfd_vma
, struct disassemble_info
*, enum bfd_endian
));
44 static int print_insn_mips
45 PARAMS ((bfd_vma
, unsigned long int, struct disassemble_info
*));
46 static void print_insn_arg
47 PARAMS ((const char *, unsigned long, bfd_vma
, struct disassemble_info
*));
48 static void mips_isa_type
49 PARAMS ((int, int *, int *));
50 static int print_insn_mips16
51 PARAMS ((bfd_vma
, struct disassemble_info
*));
53 PARAMS ((Elf_Internal_Ehdr
*));
54 static void print_mips16_insn_arg
55 PARAMS ((int, const struct mips_opcode
*, int, boolean
, int, bfd_vma
,
56 struct disassemble_info
*));
58 /* FIXME: These should be shared with gdb somehow. */
60 /* The mips16 register names. */
61 static const char * const mips16_reg_names
[] = {
62 "s0", "s1", "v0", "v1", "a0", "a1", "a2", "a3"
65 static const char * const mips32_reg_names
[] = {
66 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
67 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7",
68 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
69 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra",
70 "sr", "lo", "hi", "bad", "cause", "pc",
71 "fv0", "$f1", "fv1", "$f3", "ft0", "$f5", "ft1", "$f7",
72 "ft2", "$f9", "ft3", "$f11", "fa0", "$f13", "fa1", "$f15",
73 "ft4", "f17", "ft5", "f19", "fs0", "f21", "fs1", "f23",
74 "fs2", "$f25", "fs3", "$f27", "fs4", "$f29", "fs5", "$f31",
75 "fsr", "fir", "fp", "inx", "rand", "tlblo", "ctxt", "tlbhi",
79 static const char * const mips64_reg_names
[] = {
80 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
81 "a4", "a5", "a6", "a7", "t0", "t1", "t2", "t3",
82 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
83 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra",
84 "sr", "lo", "hi", "bad", "cause", "pc",
85 "fv0", "$f1", "fv1", "$f3", "ft0", "ft1", "ft2", "ft3",
86 "ft4", "ft5", "ft6", "ft7", "fa0", "fa1", "fa2", "fa3",
87 "fa4", "fa5", "fa6", "fa7", "ft8", "ft9", "ft10", "ft11",
88 "fs0", "fs1", "fs2", "fs3", "fs4", "fs5", "fs6", "fs7",
89 "fsr", "fir", "fp", "inx", "rand", "tlblo", "ctxt", "tlbhi",
93 /* Scalar register names. _print_insn_mips() decides which register name
95 static const char * const *reg_names
= NULL
;
97 /* Print insn arguments for 32/64-bit code. */
100 print_insn_arg (d
, l
, pc
, info
)
102 register unsigned long int l
;
104 struct disassemble_info
*info
;
113 (*info
->fprintf_func
) (info
->stream
, "%c", *d
);
120 (*info
->fprintf_func
) (info
->stream
, "%s",
121 reg_names
[(l
>> OP_SH_RS
) & OP_MASK_RS
]);
126 (*info
->fprintf_func
) (info
->stream
, "%s",
127 reg_names
[(l
>> OP_SH_RT
) & OP_MASK_RT
]);
132 (*info
->fprintf_func
) (info
->stream
, "0x%x",
133 (l
>> OP_SH_IMMEDIATE
) & OP_MASK_IMMEDIATE
);
136 case 'j': /* Same as i, but sign-extended. */
138 delta
= (l
>> OP_SH_DELTA
) & OP_MASK_DELTA
;
141 (*info
->fprintf_func
) (info
->stream
, "%d",
146 (*info
->fprintf_func
) (info
->stream
, "0x%x",
147 (unsigned int) ((l
>> OP_SH_PREFX
)
152 (*info
->fprintf_func
) (info
->stream
, "0x%x",
153 (unsigned int) ((l
>> OP_SH_CACHE
)
158 (*info
->print_address_func
)
159 ((((pc
+ 4) & ~(bfd_vma
) 0x0fffffff)
160 | (((l
>> OP_SH_TARGET
) & OP_MASK_TARGET
) << 2)),
165 /* Sign extend the displacement. */
166 delta
= (l
>> OP_SH_DELTA
) & OP_MASK_DELTA
;
169 (*info
->print_address_func
)
170 ((delta
<< 2) + pc
+ INSNLEN
,
175 (*info
->fprintf_func
) (info
->stream
, "%s",
176 reg_names
[(l
>> OP_SH_RD
) & OP_MASK_RD
]);
181 /* First check for both rd and rt being equal. */
182 unsigned int reg
= (l
>> OP_SH_RD
) & OP_MASK_RD
;
183 if (reg
== ((l
>> OP_SH_RT
) & OP_MASK_RT
))
184 (*info
->fprintf_func
) (info
->stream
, "%s",
188 /* If one is zero use the other. */
190 (*info
->fprintf_func
) (info
->stream
, "%s",
191 reg_names
[(l
>> OP_SH_RT
) & OP_MASK_RT
]);
192 else if (((l
>> OP_SH_RT
) & OP_MASK_RT
) == 0)
193 (*info
->fprintf_func
) (info
->stream
, "%s",
195 else /* Bogus, result depends on processor. */
196 (*info
->fprintf_func
) (info
->stream
, "%s or %s",
198 reg_names
[(l
>> OP_SH_RT
) & OP_MASK_RT
]);
204 (*info
->fprintf_func
) (info
->stream
, "%s", reg_names
[0]);
208 (*info
->fprintf_func
) (info
->stream
, "0x%x",
209 (l
>> OP_SH_SHAMT
) & OP_MASK_SHAMT
);
213 (*info
->fprintf_func
) (info
->stream
, "0x%x",
214 (l
>> OP_SH_CODE
) & OP_MASK_CODE
);
218 (*info
->fprintf_func
) (info
->stream
, "0x%x",
219 (l
>> OP_SH_CODE2
) & OP_MASK_CODE2
);
223 (*info
->fprintf_func
) (info
->stream
, "0x%x",
224 (l
>> OP_SH_COPZ
) & OP_MASK_COPZ
);
228 (*info
->fprintf_func
) (info
->stream
, "0x%x",
229 (l
>> OP_SH_CODE20
) & OP_MASK_CODE20
);
233 (*info
->fprintf_func
) (info
->stream
, "0x%x",
234 (l
>> OP_SH_CODE19
) & OP_MASK_CODE19
);
239 (*info
->fprintf_func
) (info
->stream
, "$f%d",
240 (l
>> OP_SH_FS
) & OP_MASK_FS
);
245 (*info
->fprintf_func
) (info
->stream
, "$f%d",
246 (l
>> OP_SH_FT
) & OP_MASK_FT
);
250 (*info
->fprintf_func
) (info
->stream
, "$f%d",
251 (l
>> OP_SH_FD
) & OP_MASK_FD
);
255 (*info
->fprintf_func
) (info
->stream
, "$f%d",
256 (l
>> OP_SH_FR
) & OP_MASK_FR
);
260 (*info
->fprintf_func
) (info
->stream
, "$%d",
261 (l
>> OP_SH_RT
) & OP_MASK_RT
);
265 (*info
->fprintf_func
) (info
->stream
, "$%d",
266 (l
>> OP_SH_RD
) & OP_MASK_RD
);
270 (*info
->fprintf_func
) (info
->stream
, "$fcc%d",
271 (l
>> OP_SH_BCC
) & OP_MASK_BCC
);
275 (*info
->fprintf_func
) (info
->stream
, "$fcc%d",
276 (l
>> OP_SH_CCC
) & OP_MASK_CCC
);
280 (*info
->fprintf_func
) (info
->stream
, "%d",
281 (l
>> OP_SH_PERFREG
) & OP_MASK_PERFREG
);
285 (*info
->fprintf_func
) (info
->stream
, "%d",
286 (l
>> OP_SH_SEL
) & OP_MASK_SEL
);
290 /* xgettext:c-format */
291 (*info
->fprintf_func
) (info
->stream
,
292 _("# internal error, undefined modifier(%c)"),
298 /* Figure out the MIPS ISA and CPU based on the machine number. */
301 mips_isa_type (mach
, isa
, cputype
)
308 case bfd_mach_mips3000
:
309 *cputype
= CPU_R3000
;
312 case bfd_mach_mips3900
:
313 *cputype
= CPU_R3900
;
316 case bfd_mach_mips4000
:
317 *cputype
= CPU_R4000
;
320 case bfd_mach_mips4010
:
321 *cputype
= CPU_R4010
;
324 case bfd_mach_mips4100
:
325 *cputype
= CPU_VR4100
;
328 case bfd_mach_mips4111
:
329 *cputype
= CPU_R4111
;
332 case bfd_mach_mips4300
:
333 *cputype
= CPU_R4300
;
336 case bfd_mach_mips4400
:
337 *cputype
= CPU_R4400
;
340 case bfd_mach_mips4600
:
341 *cputype
= CPU_R4600
;
344 case bfd_mach_mips4650
:
345 *cputype
= CPU_R4650
;
348 case bfd_mach_mips5000
:
349 *cputype
= CPU_R5000
;
352 case bfd_mach_mips6000
:
353 *cputype
= CPU_R6000
;
356 case bfd_mach_mips8000
:
357 *cputype
= CPU_R8000
;
360 case bfd_mach_mips10000
:
361 *cputype
= CPU_R10000
;
364 case bfd_mach_mips12000
:
365 *cputype
= CPU_R12000
;
368 case bfd_mach_mips16
:
369 *cputype
= CPU_MIPS16
;
372 case bfd_mach_mips32
:
373 *cputype
= CPU_MIPS32
;
376 case bfd_mach_mips32_4k
:
377 *cputype
= CPU_MIPS32_4K
;
381 *cputype
= CPU_MIPS5
;
384 case bfd_mach_mips64
:
385 *cputype
= CPU_MIPS64
;
388 case bfd_mach_mips_sb1
:
393 *cputype
= CPU_R3000
;
399 /* Check if the object uses NewABI conventions. */
403 Elf_Internal_Ehdr
*header
;
406 & (E_MIPS_ABI_EABI32
| E_MIPS_ABI_EABI64
| EF_MIPS_ABI2
)) != 0
407 || (header
->e_ident
[EI_CLASS
] == ELFCLASS64
408 && (header
->e_flags
& E_MIPS_ABI_O64
) == 0))
414 /* Print the mips instruction at address MEMADDR in debugged memory,
415 on using INFO. Returns length of the instruction, in bytes, which is
416 always INSNLEN. BIGENDIAN must be 1 if this is big-endian code, 0 if
417 this is little-endian code. */
420 print_insn_mips (memaddr
, word
, info
)
422 unsigned long int word
;
423 struct disassemble_info
*info
;
425 register const struct mips_opcode
*op
;
426 int target_processor
, mips_isa
;
427 static boolean init
= 0;
428 static const struct mips_opcode
*mips_hash
[OP_MASK_OP
+ 1];
430 /* Build a hash table to shorten the search time. */
435 for (i
= 0; i
<= OP_MASK_OP
; i
++)
437 for (op
= mips_opcodes
; op
< &mips_opcodes
[NUMOPCODES
]; op
++)
439 if (op
->pinfo
== INSN_MACRO
)
441 if (i
== ((op
->match
>> OP_SH_OP
) & OP_MASK_OP
))
452 #if ! SYMTAB_AVAILABLE
453 /* This is running out on a target machine, not in a host tool.
454 FIXME: Where does mips_target_info come from? */
455 target_processor
= mips_target_info
.processor
;
456 mips_isa
= mips_target_info
.isa
;
458 mips_isa_type (info
->mach
, &mips_isa
, &target_processor
);
461 info
->bytes_per_chunk
= INSNLEN
;
462 info
->display_endian
= info
->endian
;
464 op
= mips_hash
[(word
>> OP_SH_OP
) & OP_MASK_OP
];
467 for (; op
< &mips_opcodes
[NUMOPCODES
]; op
++)
469 if (op
->pinfo
!= INSN_MACRO
&& (word
& op
->mask
) == op
->match
)
471 register const char *d
;
473 if (! OPCODE_IS_MEMBER (op
, mips_isa
, target_processor
))
476 (*info
->fprintf_func
) (info
->stream
, "%s", op
->name
);
479 if (d
!= NULL
&& *d
!= '\0')
481 (*info
->fprintf_func
) (info
->stream
, "\t");
482 for (; *d
!= '\0'; d
++)
483 print_insn_arg (d
, word
, memaddr
, info
);
491 /* Handle undefined instructions. */
492 (*info
->fprintf_func
) (info
->stream
, "0x%x", word
);
496 /* In an environment where we do not know the symbol type of the
497 instruction we are forced to assume that the low order bit of the
498 instructions' address may mark it as a mips16 instruction. If we
499 are single stepping, or the pc is within the disassembled function,
500 this works. Otherwise, we need a clue. Sometimes. */
503 _print_insn_mips (memaddr
, info
, endianness
)
505 struct disassemble_info
*info
;
506 enum bfd_endian endianness
;
508 bfd_byte buffer
[INSNLEN
];
512 /* FIXME: If odd address, this is CLEARLY a mips 16 instruction. */
513 /* Only a few tools will work this way. */
515 return print_insn_mips16 (memaddr
, info
);
520 || (info
->flavour
== bfd_target_elf_flavour
521 && info
->symbols
!= NULL
522 && ((*(elf_symbol_type
**) info
->symbols
)->internal_elf_sym
.st_other
524 return print_insn_mips16 (memaddr
, info
);
527 /* Use mips64_reg_names for new ABI. */
528 reg_names
= mips32_reg_names
;
530 if (info
->flavour
== bfd_target_elf_flavour
&& info
->symbols
!= NULL
)
532 Elf_Internal_Ehdr
*header
;
534 header
= elf_elfheader (bfd_asymbol_bfd (*(info
->symbols
)));
535 if (is_newabi (header
))
536 reg_names
= mips64_reg_names
;
539 status
= (*info
->read_memory_func
) (memaddr
, buffer
, INSNLEN
, info
);
544 if (endianness
== BFD_ENDIAN_BIG
)
545 insn
= (unsigned long) bfd_getb32 (buffer
);
547 insn
= (unsigned long) bfd_getl32 (buffer
);
549 return print_insn_mips (memaddr
, insn
, info
);
553 (*info
->memory_error_func
) (status
, memaddr
, info
);
559 print_insn_big_mips (memaddr
, info
)
561 struct disassemble_info
*info
;
563 return _print_insn_mips (memaddr
, info
, BFD_ENDIAN_BIG
);
567 print_insn_little_mips (memaddr
, info
)
569 struct disassemble_info
*info
;
571 return _print_insn_mips (memaddr
, info
, BFD_ENDIAN_LITTLE
);
574 /* Disassemble mips16 instructions. */
577 print_insn_mips16 (memaddr
, info
)
579 struct disassemble_info
*info
;
587 const struct mips_opcode
*op
, *opend
;
589 info
->bytes_per_chunk
= 2;
590 info
->display_endian
= info
->endian
;
591 info
->insn_info_valid
= 1;
592 info
->branch_delay_insns
= 0;
594 info
->insn_type
= dis_nonbranch
;
598 status
= (*info
->read_memory_func
) (memaddr
, buffer
, 2, info
);
601 (*info
->memory_error_func
) (status
, memaddr
, info
);
607 if (info
->endian
== BFD_ENDIAN_BIG
)
608 insn
= bfd_getb16 (buffer
);
610 insn
= bfd_getl16 (buffer
);
612 /* Handle the extend opcode specially. */
614 if ((insn
& 0xf800) == 0xf000)
617 extend
= insn
& 0x7ff;
621 status
= (*info
->read_memory_func
) (memaddr
, buffer
, 2, info
);
624 (*info
->fprintf_func
) (info
->stream
, "extend 0x%x",
625 (unsigned int) extend
);
626 (*info
->memory_error_func
) (status
, memaddr
, info
);
630 if (info
->endian
== BFD_ENDIAN_BIG
)
631 insn
= bfd_getb16 (buffer
);
633 insn
= bfd_getl16 (buffer
);
635 /* Check for an extend opcode followed by an extend opcode. */
636 if ((insn
& 0xf800) == 0xf000)
638 (*info
->fprintf_func
) (info
->stream
, "extend 0x%x",
639 (unsigned int) extend
);
640 info
->insn_type
= dis_noninsn
;
647 /* FIXME: Should probably use a hash table on the major opcode here. */
649 opend
= mips16_opcodes
+ bfd_mips16_num_opcodes
;
650 for (op
= mips16_opcodes
; op
< opend
; op
++)
652 if (op
->pinfo
!= INSN_MACRO
&& (insn
& op
->mask
) == op
->match
)
656 if (strchr (op
->args
, 'a') != NULL
)
660 (*info
->fprintf_func
) (info
->stream
, "extend 0x%x",
661 (unsigned int) extend
);
662 info
->insn_type
= dis_noninsn
;
670 status
= (*info
->read_memory_func
) (memaddr
, buffer
, 2,
675 if (info
->endian
== BFD_ENDIAN_BIG
)
676 extend
= bfd_getb16 (buffer
);
678 extend
= bfd_getl16 (buffer
);
683 (*info
->fprintf_func
) (info
->stream
, "%s", op
->name
);
684 if (op
->args
[0] != '\0')
685 (*info
->fprintf_func
) (info
->stream
, "\t");
687 for (s
= op
->args
; *s
!= '\0'; s
++)
691 && (((insn
>> MIPS16OP_SH_RX
) & MIPS16OP_MASK_RX
)
692 == ((insn
>> MIPS16OP_SH_RY
) & MIPS16OP_MASK_RY
)))
694 /* Skip the register and the comma. */
700 && (((insn
>> MIPS16OP_SH_RZ
) & MIPS16OP_MASK_RZ
)
701 == ((insn
>> MIPS16OP_SH_RX
) & MIPS16OP_MASK_RX
)))
703 /* Skip the register and the comma. */
707 print_mips16_insn_arg (*s
, op
, insn
, use_extend
, extend
, memaddr
,
711 if ((op
->pinfo
& INSN_UNCOND_BRANCH_DELAY
) != 0)
713 info
->branch_delay_insns
= 1;
714 if (info
->insn_type
!= dis_jsr
)
715 info
->insn_type
= dis_branch
;
723 (*info
->fprintf_func
) (info
->stream
, "0x%x", extend
| 0xf000);
724 (*info
->fprintf_func
) (info
->stream
, "0x%x", insn
);
725 info
->insn_type
= dis_noninsn
;
730 /* Disassemble an operand for a mips16 instruction. */
733 print_mips16_insn_arg (type
, op
, l
, use_extend
, extend
, memaddr
, info
)
735 const struct mips_opcode
*op
;
740 struct disassemble_info
*info
;
747 (*info
->fprintf_func
) (info
->stream
, "%c", type
);
752 (*info
->fprintf_func
) (info
->stream
, "%s",
753 mips16_reg_names
[((l
>> MIPS16OP_SH_RY
)
754 & MIPS16OP_MASK_RY
)]);
759 (*info
->fprintf_func
) (info
->stream
, "%s",
760 mips16_reg_names
[((l
>> MIPS16OP_SH_RX
)
761 & MIPS16OP_MASK_RX
)]);
765 (*info
->fprintf_func
) (info
->stream
, "%s",
766 mips16_reg_names
[((l
>> MIPS16OP_SH_RZ
)
767 & MIPS16OP_MASK_RZ
)]);
771 (*info
->fprintf_func
) (info
->stream
, "%s",
772 mips16_reg_names
[((l
>> MIPS16OP_SH_MOVE32Z
)
773 & MIPS16OP_MASK_MOVE32Z
)]);
777 (*info
->fprintf_func
) (info
->stream
, "%s", mips32_reg_names
[0]);
781 (*info
->fprintf_func
) (info
->stream
, "%s", mips32_reg_names
[29]);
785 (*info
->fprintf_func
) (info
->stream
, "$pc");
789 (*info
->fprintf_func
) (info
->stream
, "%s", mips32_reg_names
[31]);
793 (*info
->fprintf_func
) (info
->stream
, "%s",
794 mips32_reg_names
[((l
>> MIPS16OP_SH_REGR32
)
795 & MIPS16OP_MASK_REGR32
)]);
799 (*info
->fprintf_func
) (info
->stream
, "%s",
800 mips32_reg_names
[MIPS16OP_EXTRACT_REG32R (l
)]);
826 int immed
, nbits
, shift
, signedp
, extbits
, pcrel
, extu
, branch
;
838 immed
= (l
>> MIPS16OP_SH_RZ
) & MIPS16OP_MASK_RZ
;
844 immed
= (l
>> MIPS16OP_SH_RX
) & MIPS16OP_MASK_RX
;
850 immed
= (l
>> MIPS16OP_SH_RZ
) & MIPS16OP_MASK_RZ
;
856 immed
= (l
>> MIPS16OP_SH_RX
) & MIPS16OP_MASK_RX
;
862 immed
= (l
>> MIPS16OP_SH_IMM4
) & MIPS16OP_MASK_IMM4
;
868 immed
= (l
>> MIPS16OP_SH_IMM5
) & MIPS16OP_MASK_IMM5
;
869 info
->insn_type
= dis_dref
;
875 immed
= (l
>> MIPS16OP_SH_IMM5
) & MIPS16OP_MASK_IMM5
;
876 info
->insn_type
= dis_dref
;
882 immed
= (l
>> MIPS16OP_SH_IMM5
) & MIPS16OP_MASK_IMM5
;
883 if ((op
->pinfo
& MIPS16_INSN_READ_PC
) == 0
884 && (op
->pinfo
& MIPS16_INSN_READ_SP
) == 0)
886 info
->insn_type
= dis_dref
;
893 immed
= (l
>> MIPS16OP_SH_IMM5
) & MIPS16OP_MASK_IMM5
;
894 info
->insn_type
= dis_dref
;
899 immed
= (l
>> MIPS16OP_SH_IMM5
) & MIPS16OP_MASK_IMM5
;
904 immed
= (l
>> MIPS16OP_SH_IMM6
) & MIPS16OP_MASK_IMM6
;
908 immed
= (l
>> MIPS16OP_SH_IMM8
) & MIPS16OP_MASK_IMM8
;
913 immed
= (l
>> MIPS16OP_SH_IMM8
) & MIPS16OP_MASK_IMM8
;
914 /* FIXME: This might be lw, or it might be addiu to $sp or
915 $pc. We assume it's load. */
916 info
->insn_type
= dis_dref
;
922 immed
= (l
>> MIPS16OP_SH_IMM8
) & MIPS16OP_MASK_IMM8
;
923 info
->insn_type
= dis_dref
;
928 immed
= (l
>> MIPS16OP_SH_IMM8
) & MIPS16OP_MASK_IMM8
;
933 immed
= (l
>> MIPS16OP_SH_IMM8
) & MIPS16OP_MASK_IMM8
;
939 immed
= (l
>> MIPS16OP_SH_IMM8
) & MIPS16OP_MASK_IMM8
;
944 immed
= (l
>> MIPS16OP_SH_IMM8
) & MIPS16OP_MASK_IMM8
;
948 info
->insn_type
= dis_condbranch
;
952 immed
= (l
>> MIPS16OP_SH_IMM11
) & MIPS16OP_MASK_IMM11
;
956 info
->insn_type
= dis_branch
;
961 immed
= (l
>> MIPS16OP_SH_IMM8
) & MIPS16OP_MASK_IMM8
;
963 /* FIXME: This can be lw or la. We assume it is lw. */
964 info
->insn_type
= dis_dref
;
970 immed
= (l
>> MIPS16OP_SH_IMM5
) & MIPS16OP_MASK_IMM5
;
972 info
->insn_type
= dis_dref
;
978 immed
= (l
>> MIPS16OP_SH_IMM5
) & MIPS16OP_MASK_IMM5
;
987 if (signedp
&& immed
>= (1 << (nbits
- 1)))
990 if ((type
== '<' || type
== '>' || type
== '[' || type
== ']')
997 immed
|= ((extend
& 0x1f) << 11) | (extend
& 0x7e0);
998 else if (extbits
== 15)
999 immed
|= ((extend
& 0xf) << 11) | (extend
& 0x7f0);
1001 immed
= ((extend
>> 6) & 0x1f) | (extend
& 0x20);
1002 immed
&= (1 << extbits
) - 1;
1003 if (! extu
&& immed
>= (1 << (extbits
- 1)))
1004 immed
-= 1 << extbits
;
1008 (*info
->fprintf_func
) (info
->stream
, "%d", immed
);
1017 baseaddr
= memaddr
+ 2;
1019 else if (use_extend
)
1020 baseaddr
= memaddr
- 2;
1028 /* If this instruction is in the delay slot of a jr
1029 instruction, the base address is the address of the
1030 jr instruction. If it is in the delay slot of jalr
1031 instruction, the base address is the address of the
1032 jalr instruction. This test is unreliable: we have
1033 no way of knowing whether the previous word is
1034 instruction or data. */
1035 status
= (*info
->read_memory_func
) (memaddr
- 4, buffer
, 2,
1038 && (((info
->endian
== BFD_ENDIAN_BIG
1039 ? bfd_getb16 (buffer
)
1040 : bfd_getl16 (buffer
))
1041 & 0xf800) == 0x1800))
1042 baseaddr
= memaddr
- 4;
1045 status
= (*info
->read_memory_func
) (memaddr
- 2, buffer
,
1048 && (((info
->endian
== BFD_ENDIAN_BIG
1049 ? bfd_getb16 (buffer
)
1050 : bfd_getl16 (buffer
))
1051 & 0xf81f) == 0xe800))
1052 baseaddr
= memaddr
- 2;
1055 val
= (baseaddr
& ~((1 << shift
) - 1)) + immed
;
1056 (*info
->print_address_func
) (val
, info
);
1065 l
= ((l
& 0x1f) << 23) | ((l
& 0x3e0) << 13) | (extend
<< 2);
1066 (*info
->print_address_func
) (((memaddr
+ 4) & 0xf0000000) | l
, info
);
1067 info
->insn_type
= dis_jsr
;
1068 info
->target
= ((memaddr
+ 4) & 0xf0000000) | l
;
1069 info
->branch_delay_insns
= 1;
1075 int need_comma
, amask
, smask
;
1079 l
= (l
>> MIPS16OP_SH_IMM6
) & MIPS16OP_MASK_IMM6
;
1081 amask
= (l
>> 3) & 7;
1083 if (amask
> 0 && amask
< 5)
1085 (*info
->fprintf_func
) (info
->stream
, "%s", mips32_reg_names
[4]);
1087 (*info
->fprintf_func
) (info
->stream
, "-%s",
1088 mips32_reg_names
[amask
+ 3]);
1092 smask
= (l
>> 1) & 3;
1095 (*info
->fprintf_func
) (info
->stream
, "%s??",
1096 need_comma
? "," : "");
1101 (*info
->fprintf_func
) (info
->stream
, "%s%s",
1102 need_comma
? "," : "",
1103 mips32_reg_names
[16]);
1105 (*info
->fprintf_func
) (info
->stream
, "-%s",
1106 mips32_reg_names
[smask
+ 15]);
1112 (*info
->fprintf_func
) (info
->stream
, "%s%s",
1113 need_comma
? "," : "",
1114 mips32_reg_names
[31]);
1118 if (amask
== 5 || amask
== 6)
1120 (*info
->fprintf_func
) (info
->stream
, "%s$f0",
1121 need_comma
? "," : "");
1123 (*info
->fprintf_func
) (info
->stream
, "-$f1");
1129 /* xgettext:c-format */
1130 (*info
->fprintf_func
)
1132 _("# internal disassembler error, unrecognised modifier (%c)"),
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