1 /* Print mips instructions for GDB, the GNU debugger, or for objdump.
2 Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
4 Free Software Foundation, Inc.
5 Contributed by Nobuyuki Hikichi(hikichi@sra.co.jp).
7 This file is part of GDB, GAS, and the GNU binutils.
9 This program is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 2 of the License, or
12 (at your option) any later version.
14 This program is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with this program; if not, write to the Free Software
21 Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
25 #include "opcode/mips.h"
28 /* FIXME: These are needed to figure out if the code is mips16 or
29 not. The low bit of the address is often a good indicator. No
30 symbol table is available when this code runs out in an embedded
31 system as when it is used for disassembler support in a monitor. */
33 #if !defined(EMBEDDED_ENV)
34 #define SYMTAB_AVAILABLE 1
39 /* Mips instructions are at maximum this many bytes long. */
42 static int _print_insn_mips
43 PARAMS ((bfd_vma
, struct disassemble_info
*, enum bfd_endian
));
44 static int print_insn_mips
45 PARAMS ((bfd_vma
, unsigned long int, struct disassemble_info
*));
46 static void print_insn_arg
47 PARAMS ((const char *, unsigned long, bfd_vma
, struct disassemble_info
*));
48 static void mips_isa_type
49 PARAMS ((int, int *, int *));
50 static int print_insn_mips16
51 PARAMS ((bfd_vma
, struct disassemble_info
*));
53 PARAMS ((Elf_Internal_Ehdr
*));
54 static void print_mips16_insn_arg
55 PARAMS ((int, const struct mips_opcode
*, int, boolean
, int, bfd_vma
,
56 struct disassemble_info
*));
58 /* FIXME: These should be shared with gdb somehow. */
60 /* The mips16 register names. */
61 static const char * const mips16_reg_names
[] = {
62 "s0", "s1", "v0", "v1", "a0", "a1", "a2", "a3"
65 static const char * const mips32_reg_names
[] = {
66 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
67 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7",
68 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
69 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra",
70 "sr", "lo", "hi", "bad", "cause", "pc",
71 "fv0", "$f1", "fv1", "$f3", "ft0", "$f5", "ft1", "$f7",
72 "ft2", "$f9", "ft3", "$f11", "fa0", "$f13", "fa1", "$f15",
73 "ft4", "f17", "ft5", "f19", "fs0", "f21", "fs1", "f23",
74 "fs2", "$f25", "fs3", "$f27", "fs4", "$f29", "fs5", "$f31",
75 "fsr", "fir", "fp", "inx", "rand", "tlblo", "ctxt", "tlbhi",
79 static const char * const mips64_reg_names
[] = {
80 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
81 "a4", "a5", "a6", "a7", "t0", "t1", "t2", "t3",
82 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
83 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra",
84 "sr", "lo", "hi", "bad", "cause", "pc",
85 "fv0", "$f1", "fv1", "$f3", "ft0", "ft1", "ft2", "ft3",
86 "ft4", "ft5", "ft6", "ft7", "fa0", "fa1", "fa2", "fa3",
87 "fa4", "fa5", "fa6", "fa7", "ft8", "ft9", "ft10", "ft11",
88 "fs0", "fs1", "fs2", "fs3", "fs4", "fs5", "fs6", "fs7",
89 "fsr", "fir", "fp", "inx", "rand", "tlblo", "ctxt", "tlbhi",
93 /* Scalar register names. _print_insn_mips() decides which register name
95 static const char * const *reg_names
= NULL
;
97 /* Print insn arguments for 32/64-bit code. */
100 print_insn_arg (d
, l
, pc
, info
)
102 register unsigned long int l
;
104 struct disassemble_info
*info
;
113 (*info
->fprintf_func
) (info
->stream
, "%c", *d
);
120 (*info
->fprintf_func
) (info
->stream
, "%s",
121 reg_names
[(l
>> OP_SH_RS
) & OP_MASK_RS
]);
126 (*info
->fprintf_func
) (info
->stream
, "%s",
127 reg_names
[(l
>> OP_SH_RT
) & OP_MASK_RT
]);
132 (*info
->fprintf_func
) (info
->stream
, "0x%x",
133 (l
>> OP_SH_IMMEDIATE
) & OP_MASK_IMMEDIATE
);
136 case 'j': /* Same as i, but sign-extended. */
138 delta
= (l
>> OP_SH_DELTA
) & OP_MASK_DELTA
;
141 (*info
->fprintf_func
) (info
->stream
, "%d",
146 (*info
->fprintf_func
) (info
->stream
, "0x%x",
147 (unsigned int) ((l
>> OP_SH_PREFX
)
152 (*info
->fprintf_func
) (info
->stream
, "0x%x",
153 (unsigned int) ((l
>> OP_SH_CACHE
)
158 (*info
->print_address_func
)
159 ((((pc
+ 4) & ~(bfd_vma
) 0x0fffffff)
160 | (((l
>> OP_SH_TARGET
) & OP_MASK_TARGET
) << 2)),
165 /* Sign extend the displacement. */
166 delta
= (l
>> OP_SH_DELTA
) & OP_MASK_DELTA
;
169 (*info
->print_address_func
)
170 ((delta
<< 2) + pc
+ INSNLEN
,
175 (*info
->fprintf_func
) (info
->stream
, "%s",
176 reg_names
[(l
>> OP_SH_RD
) & OP_MASK_RD
]);
181 /* First check for both rd and rt being equal. */
182 unsigned int reg
= (l
>> OP_SH_RD
) & OP_MASK_RD
;
183 if (reg
== ((l
>> OP_SH_RT
) & OP_MASK_RT
))
184 (*info
->fprintf_func
) (info
->stream
, "%s",
188 /* If one is zero use the other. */
190 (*info
->fprintf_func
) (info
->stream
, "%s",
191 reg_names
[(l
>> OP_SH_RT
) & OP_MASK_RT
]);
192 else if (((l
>> OP_SH_RT
) & OP_MASK_RT
) == 0)
193 (*info
->fprintf_func
) (info
->stream
, "%s",
195 else /* Bogus, result depends on processor. */
196 (*info
->fprintf_func
) (info
->stream
, "%s or %s",
198 reg_names
[(l
>> OP_SH_RT
) & OP_MASK_RT
]);
204 (*info
->fprintf_func
) (info
->stream
, "%s", reg_names
[0]);
208 (*info
->fprintf_func
) (info
->stream
, "0x%x",
209 (l
>> OP_SH_SHAMT
) & OP_MASK_SHAMT
);
213 (*info
->fprintf_func
) (info
->stream
, "0x%x",
214 (l
>> OP_SH_CODE
) & OP_MASK_CODE
);
218 (*info
->fprintf_func
) (info
->stream
, "0x%x",
219 (l
>> OP_SH_CODE2
) & OP_MASK_CODE2
);
223 (*info
->fprintf_func
) (info
->stream
, "0x%x",
224 (l
>> OP_SH_COPZ
) & OP_MASK_COPZ
);
228 (*info
->fprintf_func
) (info
->stream
, "0x%x",
229 (l
>> OP_SH_CODE20
) & OP_MASK_CODE20
);
233 (*info
->fprintf_func
) (info
->stream
, "0x%x",
234 (l
>> OP_SH_CODE19
) & OP_MASK_CODE19
);
239 (*info
->fprintf_func
) (info
->stream
, "$f%d",
240 (l
>> OP_SH_FS
) & OP_MASK_FS
);
245 (*info
->fprintf_func
) (info
->stream
, "$f%d",
246 (l
>> OP_SH_FT
) & OP_MASK_FT
);
250 (*info
->fprintf_func
) (info
->stream
, "$f%d",
251 (l
>> OP_SH_FD
) & OP_MASK_FD
);
255 (*info
->fprintf_func
) (info
->stream
, "$f%d",
256 (l
>> OP_SH_FR
) & OP_MASK_FR
);
260 (*info
->fprintf_func
) (info
->stream
, "$%d",
261 (l
>> OP_SH_RT
) & OP_MASK_RT
);
265 (*info
->fprintf_func
) (info
->stream
, "$%d",
266 (l
>> OP_SH_RD
) & OP_MASK_RD
);
270 (*info
->fprintf_func
) (info
->stream
, "$fcc%d",
271 (l
>> OP_SH_BCC
) & OP_MASK_BCC
);
275 (*info
->fprintf_func
) (info
->stream
, "$fcc%d",
276 (l
>> OP_SH_CCC
) & OP_MASK_CCC
);
280 (*info
->fprintf_func
) (info
->stream
, "%d",
281 (l
>> OP_SH_PERFREG
) & OP_MASK_PERFREG
);
285 (*info
->fprintf_func
) (info
->stream
, "%d",
286 (l
>> OP_SH_SEL
) & OP_MASK_SEL
);
290 /* xgettext:c-format */
291 (*info
->fprintf_func
) (info
->stream
,
292 _("# internal error, undefined modifier(%c)"),
298 /* Figure out the MIPS ISA and CPU based on the machine number. */
301 mips_isa_type (mach
, isa
, cputype
)
308 case bfd_mach_mips3000
:
309 *cputype
= CPU_R3000
;
312 case bfd_mach_mips3900
:
313 *cputype
= CPU_R3900
;
316 case bfd_mach_mips4000
:
317 *cputype
= CPU_R4000
;
320 case bfd_mach_mips4010
:
321 *cputype
= CPU_R4010
;
324 case bfd_mach_mips4100
:
325 *cputype
= CPU_VR4100
;
328 case bfd_mach_mips4111
:
329 *cputype
= CPU_R4111
;
332 case bfd_mach_mips4300
:
333 *cputype
= CPU_R4300
;
336 case bfd_mach_mips4400
:
337 *cputype
= CPU_R4400
;
340 case bfd_mach_mips4600
:
341 *cputype
= CPU_R4600
;
344 case bfd_mach_mips4650
:
345 *cputype
= CPU_R4650
;
348 case bfd_mach_mips5000
:
349 *cputype
= CPU_R5000
;
352 case bfd_mach_mips6000
:
353 *cputype
= CPU_R6000
;
356 case bfd_mach_mips8000
:
357 *cputype
= CPU_R8000
;
360 case bfd_mach_mips10000
:
361 *cputype
= CPU_R10000
;
364 case bfd_mach_mips12000
:
365 *cputype
= CPU_R12000
;
368 case bfd_mach_mips16
:
369 *cputype
= CPU_MIPS16
;
373 *cputype
= CPU_MIPS5
;
376 case bfd_mach_mips_sb1
:
380 case bfd_mach_mipsisa32
:
381 * cputype
= CPU_MIPS32
;
384 case bfd_mach_mipsisa64
:
385 * cputype
= CPU_MIPS64
;
390 *cputype
= CPU_R3000
;
396 /* Check if the object uses NewABI conventions. */
400 Elf_Internal_Ehdr
*header
;
403 & (E_MIPS_ABI_EABI32
| E_MIPS_ABI_EABI64
| EF_MIPS_ABI2
)) != 0
404 || (header
->e_ident
[EI_CLASS
] == ELFCLASS64
405 && (header
->e_flags
& E_MIPS_ABI_O64
) == 0))
411 /* Print the mips instruction at address MEMADDR in debugged memory,
412 on using INFO. Returns length of the instruction, in bytes, which is
413 always INSNLEN. BIGENDIAN must be 1 if this is big-endian code, 0 if
414 this is little-endian code. */
417 print_insn_mips (memaddr
, word
, info
)
419 unsigned long int word
;
420 struct disassemble_info
*info
;
422 register const struct mips_opcode
*op
;
423 int target_processor
, mips_isa
;
424 static boolean init
= 0;
425 static const struct mips_opcode
*mips_hash
[OP_MASK_OP
+ 1];
427 /* Build a hash table to shorten the search time. */
432 for (i
= 0; i
<= OP_MASK_OP
; i
++)
434 for (op
= mips_opcodes
; op
< &mips_opcodes
[NUMOPCODES
]; op
++)
436 if (op
->pinfo
== INSN_MACRO
)
438 if (i
== ((op
->match
>> OP_SH_OP
) & OP_MASK_OP
))
449 #if ! SYMTAB_AVAILABLE
450 /* This is running out on a target machine, not in a host tool.
451 FIXME: Where does mips_target_info come from? */
452 target_processor
= mips_target_info
.processor
;
453 mips_isa
= mips_target_info
.isa
;
455 mips_isa_type (info
->mach
, &mips_isa
, &target_processor
);
458 info
->bytes_per_chunk
= INSNLEN
;
459 info
->display_endian
= info
->endian
;
461 op
= mips_hash
[(word
>> OP_SH_OP
) & OP_MASK_OP
];
464 for (; op
< &mips_opcodes
[NUMOPCODES
]; op
++)
466 if (op
->pinfo
!= INSN_MACRO
&& (word
& op
->mask
) == op
->match
)
468 register const char *d
;
470 if (! OPCODE_IS_MEMBER (op
, mips_isa
, target_processor
))
473 (*info
->fprintf_func
) (info
->stream
, "%s", op
->name
);
476 if (d
!= NULL
&& *d
!= '\0')
478 (*info
->fprintf_func
) (info
->stream
, "\t");
479 for (; *d
!= '\0'; d
++)
480 print_insn_arg (d
, word
, memaddr
, info
);
488 /* Handle undefined instructions. */
489 (*info
->fprintf_func
) (info
->stream
, "0x%x", word
);
493 /* In an environment where we do not know the symbol type of the
494 instruction we are forced to assume that the low order bit of the
495 instructions' address may mark it as a mips16 instruction. If we
496 are single stepping, or the pc is within the disassembled function,
497 this works. Otherwise, we need a clue. Sometimes. */
500 _print_insn_mips (memaddr
, info
, endianness
)
502 struct disassemble_info
*info
;
503 enum bfd_endian endianness
;
505 bfd_byte buffer
[INSNLEN
];
509 /* FIXME: If odd address, this is CLEARLY a mips 16 instruction. */
510 /* Only a few tools will work this way. */
512 return print_insn_mips16 (memaddr
, info
);
517 || (info
->flavour
== bfd_target_elf_flavour
518 && info
->symbols
!= NULL
519 && ((*(elf_symbol_type
**) info
->symbols
)->internal_elf_sym
.st_other
521 return print_insn_mips16 (memaddr
, info
);
524 /* Use mips64_reg_names for new ABI. */
525 reg_names
= mips32_reg_names
;
527 if (info
->flavour
== bfd_target_elf_flavour
&& info
->symbols
!= NULL
)
529 Elf_Internal_Ehdr
*header
;
531 header
= elf_elfheader (bfd_asymbol_bfd (*(info
->symbols
)));
532 if (is_newabi (header
))
533 reg_names
= mips64_reg_names
;
536 status
= (*info
->read_memory_func
) (memaddr
, buffer
, INSNLEN
, info
);
541 if (endianness
== BFD_ENDIAN_BIG
)
542 insn
= (unsigned long) bfd_getb32 (buffer
);
544 insn
= (unsigned long) bfd_getl32 (buffer
);
546 return print_insn_mips (memaddr
, insn
, info
);
550 (*info
->memory_error_func
) (status
, memaddr
, info
);
556 print_insn_big_mips (memaddr
, info
)
558 struct disassemble_info
*info
;
560 return _print_insn_mips (memaddr
, info
, BFD_ENDIAN_BIG
);
564 print_insn_little_mips (memaddr
, info
)
566 struct disassemble_info
*info
;
568 return _print_insn_mips (memaddr
, info
, BFD_ENDIAN_LITTLE
);
571 /* Disassemble mips16 instructions. */
574 print_insn_mips16 (memaddr
, info
)
576 struct disassemble_info
*info
;
584 const struct mips_opcode
*op
, *opend
;
586 info
->bytes_per_chunk
= 2;
587 info
->display_endian
= info
->endian
;
588 info
->insn_info_valid
= 1;
589 info
->branch_delay_insns
= 0;
591 info
->insn_type
= dis_nonbranch
;
595 status
= (*info
->read_memory_func
) (memaddr
, buffer
, 2, info
);
598 (*info
->memory_error_func
) (status
, memaddr
, info
);
604 if (info
->endian
== BFD_ENDIAN_BIG
)
605 insn
= bfd_getb16 (buffer
);
607 insn
= bfd_getl16 (buffer
);
609 /* Handle the extend opcode specially. */
611 if ((insn
& 0xf800) == 0xf000)
614 extend
= insn
& 0x7ff;
618 status
= (*info
->read_memory_func
) (memaddr
, buffer
, 2, info
);
621 (*info
->fprintf_func
) (info
->stream
, "extend 0x%x",
622 (unsigned int) extend
);
623 (*info
->memory_error_func
) (status
, memaddr
, info
);
627 if (info
->endian
== BFD_ENDIAN_BIG
)
628 insn
= bfd_getb16 (buffer
);
630 insn
= bfd_getl16 (buffer
);
632 /* Check for an extend opcode followed by an extend opcode. */
633 if ((insn
& 0xf800) == 0xf000)
635 (*info
->fprintf_func
) (info
->stream
, "extend 0x%x",
636 (unsigned int) extend
);
637 info
->insn_type
= dis_noninsn
;
644 /* FIXME: Should probably use a hash table on the major opcode here. */
646 opend
= mips16_opcodes
+ bfd_mips16_num_opcodes
;
647 for (op
= mips16_opcodes
; op
< opend
; op
++)
649 if (op
->pinfo
!= INSN_MACRO
&& (insn
& op
->mask
) == op
->match
)
653 if (strchr (op
->args
, 'a') != NULL
)
657 (*info
->fprintf_func
) (info
->stream
, "extend 0x%x",
658 (unsigned int) extend
);
659 info
->insn_type
= dis_noninsn
;
667 status
= (*info
->read_memory_func
) (memaddr
, buffer
, 2,
672 if (info
->endian
== BFD_ENDIAN_BIG
)
673 extend
= bfd_getb16 (buffer
);
675 extend
= bfd_getl16 (buffer
);
680 (*info
->fprintf_func
) (info
->stream
, "%s", op
->name
);
681 if (op
->args
[0] != '\0')
682 (*info
->fprintf_func
) (info
->stream
, "\t");
684 for (s
= op
->args
; *s
!= '\0'; s
++)
688 && (((insn
>> MIPS16OP_SH_RX
) & MIPS16OP_MASK_RX
)
689 == ((insn
>> MIPS16OP_SH_RY
) & MIPS16OP_MASK_RY
)))
691 /* Skip the register and the comma. */
697 && (((insn
>> MIPS16OP_SH_RZ
) & MIPS16OP_MASK_RZ
)
698 == ((insn
>> MIPS16OP_SH_RX
) & MIPS16OP_MASK_RX
)))
700 /* Skip the register and the comma. */
704 print_mips16_insn_arg (*s
, op
, insn
, use_extend
, extend
, memaddr
,
708 if ((op
->pinfo
& INSN_UNCOND_BRANCH_DELAY
) != 0)
710 info
->branch_delay_insns
= 1;
711 if (info
->insn_type
!= dis_jsr
)
712 info
->insn_type
= dis_branch
;
720 (*info
->fprintf_func
) (info
->stream
, "0x%x", extend
| 0xf000);
721 (*info
->fprintf_func
) (info
->stream
, "0x%x", insn
);
722 info
->insn_type
= dis_noninsn
;
727 /* Disassemble an operand for a mips16 instruction. */
730 print_mips16_insn_arg (type
, op
, l
, use_extend
, extend
, memaddr
, info
)
732 const struct mips_opcode
*op
;
737 struct disassemble_info
*info
;
744 (*info
->fprintf_func
) (info
->stream
, "%c", type
);
749 (*info
->fprintf_func
) (info
->stream
, "%s",
750 mips16_reg_names
[((l
>> MIPS16OP_SH_RY
)
751 & MIPS16OP_MASK_RY
)]);
756 (*info
->fprintf_func
) (info
->stream
, "%s",
757 mips16_reg_names
[((l
>> MIPS16OP_SH_RX
)
758 & MIPS16OP_MASK_RX
)]);
762 (*info
->fprintf_func
) (info
->stream
, "%s",
763 mips16_reg_names
[((l
>> MIPS16OP_SH_RZ
)
764 & MIPS16OP_MASK_RZ
)]);
768 (*info
->fprintf_func
) (info
->stream
, "%s",
769 mips16_reg_names
[((l
>> MIPS16OP_SH_MOVE32Z
)
770 & MIPS16OP_MASK_MOVE32Z
)]);
774 (*info
->fprintf_func
) (info
->stream
, "%s", mips32_reg_names
[0]);
778 (*info
->fprintf_func
) (info
->stream
, "%s", mips32_reg_names
[29]);
782 (*info
->fprintf_func
) (info
->stream
, "$pc");
786 (*info
->fprintf_func
) (info
->stream
, "%s", mips32_reg_names
[31]);
790 (*info
->fprintf_func
) (info
->stream
, "%s",
791 mips32_reg_names
[((l
>> MIPS16OP_SH_REGR32
)
792 & MIPS16OP_MASK_REGR32
)]);
796 (*info
->fprintf_func
) (info
->stream
, "%s",
797 mips32_reg_names
[MIPS16OP_EXTRACT_REG32R (l
)]);
823 int immed
, nbits
, shift
, signedp
, extbits
, pcrel
, extu
, branch
;
835 immed
= (l
>> MIPS16OP_SH_RZ
) & MIPS16OP_MASK_RZ
;
841 immed
= (l
>> MIPS16OP_SH_RX
) & MIPS16OP_MASK_RX
;
847 immed
= (l
>> MIPS16OP_SH_RZ
) & MIPS16OP_MASK_RZ
;
853 immed
= (l
>> MIPS16OP_SH_RX
) & MIPS16OP_MASK_RX
;
859 immed
= (l
>> MIPS16OP_SH_IMM4
) & MIPS16OP_MASK_IMM4
;
865 immed
= (l
>> MIPS16OP_SH_IMM5
) & MIPS16OP_MASK_IMM5
;
866 info
->insn_type
= dis_dref
;
872 immed
= (l
>> MIPS16OP_SH_IMM5
) & MIPS16OP_MASK_IMM5
;
873 info
->insn_type
= dis_dref
;
879 immed
= (l
>> MIPS16OP_SH_IMM5
) & MIPS16OP_MASK_IMM5
;
880 if ((op
->pinfo
& MIPS16_INSN_READ_PC
) == 0
881 && (op
->pinfo
& MIPS16_INSN_READ_SP
) == 0)
883 info
->insn_type
= dis_dref
;
890 immed
= (l
>> MIPS16OP_SH_IMM5
) & MIPS16OP_MASK_IMM5
;
891 info
->insn_type
= dis_dref
;
896 immed
= (l
>> MIPS16OP_SH_IMM5
) & MIPS16OP_MASK_IMM5
;
901 immed
= (l
>> MIPS16OP_SH_IMM6
) & MIPS16OP_MASK_IMM6
;
905 immed
= (l
>> MIPS16OP_SH_IMM8
) & MIPS16OP_MASK_IMM8
;
910 immed
= (l
>> MIPS16OP_SH_IMM8
) & MIPS16OP_MASK_IMM8
;
911 /* FIXME: This might be lw, or it might be addiu to $sp or
912 $pc. We assume it's load. */
913 info
->insn_type
= dis_dref
;
919 immed
= (l
>> MIPS16OP_SH_IMM8
) & MIPS16OP_MASK_IMM8
;
920 info
->insn_type
= dis_dref
;
925 immed
= (l
>> MIPS16OP_SH_IMM8
) & MIPS16OP_MASK_IMM8
;
930 immed
= (l
>> MIPS16OP_SH_IMM8
) & MIPS16OP_MASK_IMM8
;
936 immed
= (l
>> MIPS16OP_SH_IMM8
) & MIPS16OP_MASK_IMM8
;
941 immed
= (l
>> MIPS16OP_SH_IMM8
) & MIPS16OP_MASK_IMM8
;
945 info
->insn_type
= dis_condbranch
;
949 immed
= (l
>> MIPS16OP_SH_IMM11
) & MIPS16OP_MASK_IMM11
;
953 info
->insn_type
= dis_branch
;
958 immed
= (l
>> MIPS16OP_SH_IMM8
) & MIPS16OP_MASK_IMM8
;
960 /* FIXME: This can be lw or la. We assume it is lw. */
961 info
->insn_type
= dis_dref
;
967 immed
= (l
>> MIPS16OP_SH_IMM5
) & MIPS16OP_MASK_IMM5
;
969 info
->insn_type
= dis_dref
;
975 immed
= (l
>> MIPS16OP_SH_IMM5
) & MIPS16OP_MASK_IMM5
;
984 if (signedp
&& immed
>= (1 << (nbits
- 1)))
987 if ((type
== '<' || type
== '>' || type
== '[' || type
== ']')
994 immed
|= ((extend
& 0x1f) << 11) | (extend
& 0x7e0);
995 else if (extbits
== 15)
996 immed
|= ((extend
& 0xf) << 11) | (extend
& 0x7f0);
998 immed
= ((extend
>> 6) & 0x1f) | (extend
& 0x20);
999 immed
&= (1 << extbits
) - 1;
1000 if (! extu
&& immed
>= (1 << (extbits
- 1)))
1001 immed
-= 1 << extbits
;
1005 (*info
->fprintf_func
) (info
->stream
, "%d", immed
);
1014 baseaddr
= memaddr
+ 2;
1016 else if (use_extend
)
1017 baseaddr
= memaddr
- 2;
1025 /* If this instruction is in the delay slot of a jr
1026 instruction, the base address is the address of the
1027 jr instruction. If it is in the delay slot of jalr
1028 instruction, the base address is the address of the
1029 jalr instruction. This test is unreliable: we have
1030 no way of knowing whether the previous word is
1031 instruction or data. */
1032 status
= (*info
->read_memory_func
) (memaddr
- 4, buffer
, 2,
1035 && (((info
->endian
== BFD_ENDIAN_BIG
1036 ? bfd_getb16 (buffer
)
1037 : bfd_getl16 (buffer
))
1038 & 0xf800) == 0x1800))
1039 baseaddr
= memaddr
- 4;
1042 status
= (*info
->read_memory_func
) (memaddr
- 2, buffer
,
1045 && (((info
->endian
== BFD_ENDIAN_BIG
1046 ? bfd_getb16 (buffer
)
1047 : bfd_getl16 (buffer
))
1048 & 0xf81f) == 0xe800))
1049 baseaddr
= memaddr
- 2;
1052 val
= (baseaddr
& ~((1 << shift
) - 1)) + immed
;
1053 (*info
->print_address_func
) (val
, info
);
1062 l
= ((l
& 0x1f) << 23) | ((l
& 0x3e0) << 13) | (extend
<< 2);
1063 (*info
->print_address_func
) (((memaddr
+ 4) & 0xf0000000) | l
, info
);
1064 info
->insn_type
= dis_jsr
;
1065 info
->target
= ((memaddr
+ 4) & 0xf0000000) | l
;
1066 info
->branch_delay_insns
= 1;
1072 int need_comma
, amask
, smask
;
1076 l
= (l
>> MIPS16OP_SH_IMM6
) & MIPS16OP_MASK_IMM6
;
1078 amask
= (l
>> 3) & 7;
1080 if (amask
> 0 && amask
< 5)
1082 (*info
->fprintf_func
) (info
->stream
, "%s", mips32_reg_names
[4]);
1084 (*info
->fprintf_func
) (info
->stream
, "-%s",
1085 mips32_reg_names
[amask
+ 3]);
1089 smask
= (l
>> 1) & 3;
1092 (*info
->fprintf_func
) (info
->stream
, "%s??",
1093 need_comma
? "," : "");
1098 (*info
->fprintf_func
) (info
->stream
, "%s%s",
1099 need_comma
? "," : "",
1100 mips32_reg_names
[16]);
1102 (*info
->fprintf_func
) (info
->stream
, "-%s",
1103 mips32_reg_names
[smask
+ 15]);
1109 (*info
->fprintf_func
) (info
->stream
, "%s%s",
1110 need_comma
? "," : "",
1111 mips32_reg_names
[31]);
1115 if (amask
== 5 || amask
== 6)
1117 (*info
->fprintf_func
) (info
->stream
, "%s$f0",
1118 need_comma
? "," : "");
1120 (*info
->fprintf_func
) (info
->stream
, "-$f1");
1126 /* xgettext:c-format */
1127 (*info
->fprintf_func
)
1129 _("# internal disassembler error, unrecognised modifier (%c)"),
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