97f263d4df494dd8730d088353461ca8339ffe6b
1 /* Print mips instructions for GDB, the GNU debugger, or for objdump.
2 Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
4 Free Software Foundation, Inc.
5 Contributed by Nobuyuki Hikichi(hikichi@sra.co.jp).
7 This file is part of GDB, GAS, and the GNU binutils.
9 This program is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 2 of the License, or
12 (at your option) any later version.
14 This program is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with this program; if not, write to the Free Software
21 Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
25 #include "opcode/mips.h"
28 /* FIXME: These are needed to figure out if the code is mips16 or
29 not. The low bit of the address is often a good indicator. No
30 symbol table is available when this code runs out in an embedded
31 system as when it is used for disassembler support in a monitor. */
33 #if !defined(EMBEDDED_ENV)
34 #define SYMTAB_AVAILABLE 1
39 /* Mips instructions are at maximum this many bytes long. */
42 static int _print_insn_mips
43 PARAMS ((bfd_vma
, struct disassemble_info
*, enum bfd_endian
));
44 static int print_insn_mips
45 PARAMS ((bfd_vma
, unsigned long int, struct disassemble_info
*));
46 static void print_insn_arg
47 PARAMS ((const char *, unsigned long, bfd_vma
, struct disassemble_info
*));
48 static int print_insn_mips16
49 PARAMS ((bfd_vma
, struct disassemble_info
*));
50 static void print_mips16_insn_arg
51 PARAMS ((int, const struct mips_opcode
*, int, boolean
, int, bfd_vma
,
52 struct disassemble_info
*));
54 /* FIXME: These should be shared with gdb somehow. */
56 /* The mips16 register names. */
57 static const char * const mips16_reg_names
[] =
59 "s0", "s1", "v0", "v1", "a0", "a1", "a2", "a3"
62 static const char * const mips32_reg_names
[] =
64 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
65 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7",
66 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
67 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra",
68 "sr", "lo", "hi", "bad", "cause", "pc",
69 "fv0", "$f1", "fv1", "$f3", "ft0", "$f5", "ft1", "$f7",
70 "ft2", "$f9", "ft3", "$f11", "fa0", "$f13", "fa1", "$f15",
71 "ft4", "f17", "ft5", "f19", "fs0", "f21", "fs1", "f23",
72 "fs2", "$f25", "fs3", "$f27", "fs4", "$f29", "fs5", "$f31",
73 "fsr", "fir", "fp", "inx", "rand", "tlblo", "ctxt", "tlbhi",
77 static const char * const mips64_reg_names
[] =
79 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
80 "a4", "a5", "a6", "a7", "t0", "t1", "t2", "t3",
81 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
82 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra",
83 "sr", "lo", "hi", "bad", "cause", "pc",
84 "fv0", "$f1", "fv1", "$f3", "ft0", "ft1", "ft2", "ft3",
85 "ft4", "ft5", "ft6", "ft7", "fa0", "fa1", "fa2", "fa3",
86 "fa4", "fa5", "fa6", "fa7", "ft8", "ft9", "ft10", "ft11",
87 "fs0", "fs1", "fs2", "fs3", "fs4", "fs5", "fs6", "fs7",
88 "fsr", "fir", "fp", "inx", "rand", "tlblo", "ctxt", "tlbhi",
92 /* Scalar register names. _print_insn_mips() decides which register name
94 static const char * const *reg_names
= NULL
;
96 /* Print insn arguments for 32/64-bit code */
99 print_insn_arg (d
, l
, pc
, info
)
101 register unsigned long int l
;
103 struct disassemble_info
*info
;
112 (*info
->fprintf_func
) (info
->stream
, "%c", *d
);
119 (*info
->fprintf_func
) (info
->stream
, "%s",
120 reg_names
[(l
>> OP_SH_RS
) & OP_MASK_RS
]);
125 (*info
->fprintf_func
) (info
->stream
, "%s",
126 reg_names
[(l
>> OP_SH_RT
) & OP_MASK_RT
]);
131 (*info
->fprintf_func
) (info
->stream
, "0x%x",
132 (l
>> OP_SH_IMMEDIATE
) & OP_MASK_IMMEDIATE
);
135 case 'j': /* same as i, but sign-extended */
137 delta
= (l
>> OP_SH_DELTA
) & OP_MASK_DELTA
;
140 (*info
->fprintf_func
) (info
->stream
, "%d",
145 (*info
->fprintf_func
) (info
->stream
, "0x%x",
146 (unsigned int) ((l
>> OP_SH_PREFX
)
151 (*info
->fprintf_func
) (info
->stream
, "0x%x",
152 (unsigned int) ((l
>> OP_SH_CACHE
)
157 (*info
->print_address_func
)
158 ((((pc
+ 4) & ~ (bfd_vma
) 0x0fffffff)
159 | (((l
>> OP_SH_TARGET
) & OP_MASK_TARGET
) << 2)),
164 /* sign extend the displacement */
165 delta
= (l
>> OP_SH_DELTA
) & OP_MASK_DELTA
;
168 (*info
->print_address_func
)
169 ((delta
<< 2) + pc
+ INSNLEN
,
174 (*info
->fprintf_func
) (info
->stream
, "%s",
175 reg_names
[(l
>> OP_SH_RD
) & OP_MASK_RD
]);
180 /* First check for both rd and rt being equal. */
181 unsigned int reg
= (l
>> OP_SH_RD
) & OP_MASK_RD
;
182 if (reg
== ((l
>> OP_SH_RT
) & OP_MASK_RT
))
183 (*info
->fprintf_func
) (info
->stream
, "%s",
187 /* If one is zero use the other. */
189 (*info
->fprintf_func
) (info
->stream
, "%s",
190 reg_names
[(l
>> OP_SH_RT
) & OP_MASK_RT
]);
191 else if (((l
>> OP_SH_RT
) & OP_MASK_RT
) == 0)
192 (*info
->fprintf_func
) (info
->stream
, "%s",
194 else /* Bogus, result depends on processor. */
195 (*info
->fprintf_func
) (info
->stream
, "%s or %s",
197 reg_names
[(l
>> OP_SH_RT
) & OP_MASK_RT
]);
203 (*info
->fprintf_func
) (info
->stream
, "%s", reg_names
[0]);
207 (*info
->fprintf_func
) (info
->stream
, "0x%x",
208 (l
>> OP_SH_SHAMT
) & OP_MASK_SHAMT
);
212 (*info
->fprintf_func
) (info
->stream
, "0x%x",
213 (l
>> OP_SH_CODE
) & OP_MASK_CODE
);
217 (*info
->fprintf_func
) (info
->stream
, "0x%x",
218 (l
>> OP_SH_CODE2
) & OP_MASK_CODE2
);
222 (*info
->fprintf_func
) (info
->stream
, "0x%x",
223 (l
>> OP_SH_COPZ
) & OP_MASK_COPZ
);
227 (*info
->fprintf_func
) (info
->stream
, "0x%x",
228 (l
>> OP_SH_CODE20
) & OP_MASK_CODE20
);
232 (*info
->fprintf_func
) (info
->stream
, "0x%x",
233 (l
>> OP_SH_CODE19
) & OP_MASK_CODE19
);
238 (*info
->fprintf_func
) (info
->stream
, "$f%d",
239 (l
>> OP_SH_FS
) & OP_MASK_FS
);
244 (*info
->fprintf_func
) (info
->stream
, "$f%d",
245 (l
>> OP_SH_FT
) & OP_MASK_FT
);
249 (*info
->fprintf_func
) (info
->stream
, "$f%d",
250 (l
>> OP_SH_FD
) & OP_MASK_FD
);
254 (*info
->fprintf_func
) (info
->stream
, "$f%d",
255 (l
>> OP_SH_FR
) & OP_MASK_FR
);
259 (*info
->fprintf_func
) (info
->stream
, "$%d",
260 (l
>> OP_SH_RT
) & OP_MASK_RT
);
264 (*info
->fprintf_func
) (info
->stream
, "$%d",
265 (l
>> OP_SH_RD
) & OP_MASK_RD
);
269 (*info
->fprintf_func
) (info
->stream
, "$fcc%d",
270 (l
>> OP_SH_BCC
) & OP_MASK_BCC
);
274 (*info
->fprintf_func
) (info
->stream
, "$fcc%d",
275 (l
>> OP_SH_CCC
) & OP_MASK_CCC
);
279 (*info
->fprintf_func
) (info
->stream
, "%d",
280 (l
>> OP_SH_PERFREG
) & OP_MASK_PERFREG
);
284 (*info
->fprintf_func
) (info
->stream
, "%d",
285 (l
>> OP_SH_SEL
) & OP_MASK_SEL
);
289 /* xgettext:c-format */
290 (*info
->fprintf_func
) (info
->stream
,
291 _("# internal error, undefined modifier(%c)"),
297 /* Figure out the MIPS ISA and CPU based on the machine number. */
300 mips_isa_type (mach
, isa
, cputype
)
307 case bfd_mach_mips3000
:
308 *cputype
= CPU_R3000
;
311 case bfd_mach_mips3900
:
312 *cputype
= CPU_R3900
;
315 case bfd_mach_mips4000
:
316 *cputype
= CPU_R4000
;
319 case bfd_mach_mips4010
:
320 *cputype
= CPU_R4010
;
323 case bfd_mach_mips4100
:
324 *cputype
= CPU_VR4100
;
327 case bfd_mach_mips4111
:
328 *cputype
= CPU_R4111
;
331 case bfd_mach_mips4300
:
332 *cputype
= CPU_R4300
;
335 case bfd_mach_mips4400
:
336 *cputype
= CPU_R4400
;
339 case bfd_mach_mips4600
:
340 *cputype
= CPU_R4600
;
343 case bfd_mach_mips4650
:
344 *cputype
= CPU_R4650
;
347 case bfd_mach_mips5000
:
348 *cputype
= CPU_R5000
;
351 case bfd_mach_mips6000
:
352 *cputype
= CPU_R6000
;
355 case bfd_mach_mips8000
:
356 *cputype
= CPU_R8000
;
359 case bfd_mach_mips10000
:
360 *cputype
= CPU_R10000
;
363 case bfd_mach_mips12000
:
364 *cputype
= CPU_R12000
;
367 case bfd_mach_mips16
:
368 *cputype
= CPU_MIPS16
;
371 case bfd_mach_mips32
:
372 *cputype
= CPU_MIPS32
;
375 case bfd_mach_mips32_4k
:
376 *cputype
= CPU_MIPS32_4K
;
380 *cputype
= CPU_MIPS5
;
383 case bfd_mach_mips64
:
384 *cputype
= CPU_MIPS64
;
387 case bfd_mach_mips_sb1
:
392 *cputype
= CPU_R3000
;
398 /* Check if the object uses NewABI conventions. */
402 Elf_Internal_Ehdr
*header
;
405 & (E_MIPS_ABI_EABI32
| E_MIPS_ABI_EABI64
| EF_MIPS_ABI2
)) != 0
406 || (header
->e_ident
[EI_CLASS
] == ELFCLASS64
407 && (header
->e_flags
& E_MIPS_ABI_O64
) == 0))
413 /* Print the mips instruction at address MEMADDR in debugged memory,
414 on using INFO. Returns length of the instruction, in bytes, which is
415 always INSNLEN. BIGENDIAN must be 1 if this is big-endian code, 0 if
416 this is little-endian code. */
419 print_insn_mips (memaddr
, word
, info
)
421 unsigned long int word
;
422 struct disassemble_info
*info
;
424 register const struct mips_opcode
*op
;
425 int target_processor
, mips_isa
;
426 static boolean init
= 0;
427 static const struct mips_opcode
*mips_hash
[OP_MASK_OP
+ 1];
429 /* Build a hash table to shorten the search time. */
434 for (i
= 0; i
<= OP_MASK_OP
; i
++)
436 for (op
= mips_opcodes
; op
< &mips_opcodes
[NUMOPCODES
]; op
++)
438 if (op
->pinfo
== INSN_MACRO
)
440 if (i
== ((op
->match
>> OP_SH_OP
) & OP_MASK_OP
))
451 #if ! SYMTAB_AVAILABLE
452 /* This is running out on a target machine, not in a host tool.
453 FIXME: Where does mips_target_info come from? */
454 target_processor
= mips_target_info
.processor
;
455 mips_isa
= mips_target_info
.isa
;
457 mips_isa_type (info
->mach
, &mips_isa
, &target_processor
);
460 info
->bytes_per_chunk
= INSNLEN
;
461 info
->display_endian
= info
->endian
;
463 op
= mips_hash
[(word
>> OP_SH_OP
) & OP_MASK_OP
];
466 for (; op
< &mips_opcodes
[NUMOPCODES
]; op
++)
468 if (op
->pinfo
!= INSN_MACRO
&& (word
& op
->mask
) == op
->match
)
470 register const char *d
;
472 if (! OPCODE_IS_MEMBER (op
, mips_isa
, target_processor
, 0))
475 (*info
->fprintf_func
) (info
->stream
, "%s", op
->name
);
478 if (d
!= NULL
&& *d
!= '\0')
480 (*info
->fprintf_func
) (info
->stream
, "\t");
481 for (; *d
!= '\0'; d
++)
482 print_insn_arg (d
, word
, memaddr
, info
);
490 /* Handle undefined instructions. */
491 (*info
->fprintf_func
) (info
->stream
, "0x%x", word
);
495 /* In an environment where we do not know the symbol type of the
496 instruction we are forced to assume that the low order bit of the
497 instructions' address may mark it as a mips16 instruction. If we
498 are single stepping, or the pc is within the disassembled function,
499 this works. Otherwise, we need a clue. Sometimes. */
502 _print_insn_mips (memaddr
, info
, endianness
)
504 struct disassemble_info
*info
;
505 enum bfd_endian endianness
;
507 bfd_byte buffer
[INSNLEN
];
511 /* FIXME: If odd address, this is CLEARLY a mips 16 instruction. */
512 /* Only a few tools will work this way. */
514 return print_insn_mips16 (memaddr
, info
);
519 || (info
->flavour
== bfd_target_elf_flavour
520 && info
->symbols
!= NULL
521 && ((*(elf_symbol_type
**) info
->symbols
)->internal_elf_sym
.st_other
523 return print_insn_mips16 (memaddr
, info
);
526 /* Use mips64_reg_names for new ABI. */
527 reg_names
= mips32_reg_names
;
529 if (info
->flavour
== bfd_target_elf_flavour
&& info
->symbols
!= NULL
)
531 Elf_Internal_Ehdr
*header
;
533 header
= elf_elfheader(bfd_asymbol_bfd(*(info
->symbols
)));
534 if (is_newabi(header
))
535 reg_names
= mips64_reg_names
;
538 status
= (*info
->read_memory_func
) (memaddr
, buffer
, INSNLEN
, info
);
543 if (endianness
== BFD_ENDIAN_BIG
)
544 insn
= (unsigned long) bfd_getb32 (buffer
);
546 insn
= (unsigned long) bfd_getl32 (buffer
);
548 return print_insn_mips (memaddr
, insn
, info
);
552 (*info
->memory_error_func
) (status
, memaddr
, info
);
558 print_insn_big_mips (memaddr
, info
)
560 struct disassemble_info
*info
;
562 return _print_insn_mips (memaddr
, info
, BFD_ENDIAN_BIG
);
566 print_insn_little_mips (memaddr
, info
)
568 struct disassemble_info
*info
;
570 return _print_insn_mips (memaddr
, info
, BFD_ENDIAN_LITTLE
);
573 /* Disassemble mips16 instructions. */
576 print_insn_mips16 (memaddr
, info
)
578 struct disassemble_info
*info
;
586 const struct mips_opcode
*op
, *opend
;
588 info
->bytes_per_chunk
= 2;
589 info
->display_endian
= info
->endian
;
590 info
->insn_info_valid
= 1;
591 info
->branch_delay_insns
= 0;
593 info
->insn_type
= dis_nonbranch
;
597 status
= (*info
->read_memory_func
) (memaddr
, buffer
, 2, info
);
600 (*info
->memory_error_func
) (status
, memaddr
, info
);
606 if (info
->endian
== BFD_ENDIAN_BIG
)
607 insn
= bfd_getb16 (buffer
);
609 insn
= bfd_getl16 (buffer
);
611 /* Handle the extend opcode specially. */
613 if ((insn
& 0xf800) == 0xf000)
616 extend
= insn
& 0x7ff;
620 status
= (*info
->read_memory_func
) (memaddr
, buffer
, 2, info
);
623 (*info
->fprintf_func
) (info
->stream
, "extend 0x%x",
624 (unsigned int) extend
);
625 (*info
->memory_error_func
) (status
, memaddr
, info
);
629 if (info
->endian
== BFD_ENDIAN_BIG
)
630 insn
= bfd_getb16 (buffer
);
632 insn
= bfd_getl16 (buffer
);
634 /* Check for an extend opcode followed by an extend opcode. */
635 if ((insn
& 0xf800) == 0xf000)
637 (*info
->fprintf_func
) (info
->stream
, "extend 0x%x",
638 (unsigned int) extend
);
639 info
->insn_type
= dis_noninsn
;
646 /* FIXME: Should probably use a hash table on the major opcode here. */
648 opend
= mips16_opcodes
+ bfd_mips16_num_opcodes
;
649 for (op
= mips16_opcodes
; op
< opend
; op
++)
651 if (op
->pinfo
!= INSN_MACRO
&& (insn
& op
->mask
) == op
->match
)
655 if (strchr (op
->args
, 'a') != NULL
)
659 (*info
->fprintf_func
) (info
->stream
, "extend 0x%x",
660 (unsigned int) extend
);
661 info
->insn_type
= dis_noninsn
;
669 status
= (*info
->read_memory_func
) (memaddr
, buffer
, 2,
674 if (info
->endian
== BFD_ENDIAN_BIG
)
675 extend
= bfd_getb16 (buffer
);
677 extend
= bfd_getl16 (buffer
);
682 (*info
->fprintf_func
) (info
->stream
, "%s", op
->name
);
683 if (op
->args
[0] != '\0')
684 (*info
->fprintf_func
) (info
->stream
, "\t");
686 for (s
= op
->args
; *s
!= '\0'; s
++)
690 && (((insn
>> MIPS16OP_SH_RX
) & MIPS16OP_MASK_RX
)
691 == ((insn
>> MIPS16OP_SH_RY
) & MIPS16OP_MASK_RY
)))
693 /* Skip the register and the comma. */
699 && (((insn
>> MIPS16OP_SH_RZ
) & MIPS16OP_MASK_RZ
)
700 == ((insn
>> MIPS16OP_SH_RX
) & MIPS16OP_MASK_RX
)))
702 /* Skip the register and the comma. */
706 print_mips16_insn_arg (*s
, op
, insn
, use_extend
, extend
, memaddr
,
710 if ((op
->pinfo
& INSN_UNCOND_BRANCH_DELAY
) != 0)
712 info
->branch_delay_insns
= 1;
713 if (info
->insn_type
!= dis_jsr
)
714 info
->insn_type
= dis_branch
;
722 (*info
->fprintf_func
) (info
->stream
, "0x%x", extend
| 0xf000);
723 (*info
->fprintf_func
) (info
->stream
, "0x%x", insn
);
724 info
->insn_type
= dis_noninsn
;
729 /* Disassemble an operand for a mips16 instruction. */
732 print_mips16_insn_arg (type
, op
, l
, use_extend
, extend
, memaddr
, info
)
734 const struct mips_opcode
*op
;
739 struct disassemble_info
*info
;
746 (*info
->fprintf_func
) (info
->stream
, "%c", type
);
751 (*info
->fprintf_func
) (info
->stream
, "%s",
752 mips16_reg_names
[((l
>> MIPS16OP_SH_RY
)
753 & MIPS16OP_MASK_RY
)]);
758 (*info
->fprintf_func
) (info
->stream
, "%s",
759 mips16_reg_names
[((l
>> MIPS16OP_SH_RX
)
760 & MIPS16OP_MASK_RX
)]);
764 (*info
->fprintf_func
) (info
->stream
, "%s",
765 mips16_reg_names
[((l
>> MIPS16OP_SH_RZ
)
766 & MIPS16OP_MASK_RZ
)]);
770 (*info
->fprintf_func
) (info
->stream
, "%s",
771 mips16_reg_names
[((l
>> MIPS16OP_SH_MOVE32Z
)
772 & MIPS16OP_MASK_MOVE32Z
)]);
776 (*info
->fprintf_func
) (info
->stream
, "%s", mips32_reg_names
[0]);
780 (*info
->fprintf_func
) (info
->stream
, "%s", mips32_reg_names
[29]);
784 (*info
->fprintf_func
) (info
->stream
, "$pc");
788 (*info
->fprintf_func
) (info
->stream
, "%s", mips32_reg_names
[31]);
792 (*info
->fprintf_func
) (info
->stream
, "%s",
793 mips32_reg_names
[((l
>> MIPS16OP_SH_REGR32
)
794 & MIPS16OP_MASK_REGR32
)]);
798 (*info
->fprintf_func
) (info
->stream
, "%s",
799 mips32_reg_names
[MIPS16OP_EXTRACT_REG32R (l
)]);
825 int immed
, nbits
, shift
, signedp
, extbits
, pcrel
, extu
, branch
;
837 immed
= (l
>> MIPS16OP_SH_RZ
) & MIPS16OP_MASK_RZ
;
843 immed
= (l
>> MIPS16OP_SH_RX
) & MIPS16OP_MASK_RX
;
849 immed
= (l
>> MIPS16OP_SH_RZ
) & MIPS16OP_MASK_RZ
;
855 immed
= (l
>> MIPS16OP_SH_RX
) & MIPS16OP_MASK_RX
;
861 immed
= (l
>> MIPS16OP_SH_IMM4
) & MIPS16OP_MASK_IMM4
;
867 immed
= (l
>> MIPS16OP_SH_IMM5
) & MIPS16OP_MASK_IMM5
;
868 info
->insn_type
= dis_dref
;
874 immed
= (l
>> MIPS16OP_SH_IMM5
) & MIPS16OP_MASK_IMM5
;
875 info
->insn_type
= dis_dref
;
881 immed
= (l
>> MIPS16OP_SH_IMM5
) & MIPS16OP_MASK_IMM5
;
882 if ((op
->pinfo
& MIPS16_INSN_READ_PC
) == 0
883 && (op
->pinfo
& MIPS16_INSN_READ_SP
) == 0)
885 info
->insn_type
= dis_dref
;
892 immed
= (l
>> MIPS16OP_SH_IMM5
) & MIPS16OP_MASK_IMM5
;
893 info
->insn_type
= dis_dref
;
898 immed
= (l
>> MIPS16OP_SH_IMM5
) & MIPS16OP_MASK_IMM5
;
903 immed
= (l
>> MIPS16OP_SH_IMM6
) & MIPS16OP_MASK_IMM6
;
907 immed
= (l
>> MIPS16OP_SH_IMM8
) & MIPS16OP_MASK_IMM8
;
912 immed
= (l
>> MIPS16OP_SH_IMM8
) & MIPS16OP_MASK_IMM8
;
913 /* FIXME: This might be lw, or it might be addiu to $sp or
914 $pc. We assume it's load. */
915 info
->insn_type
= dis_dref
;
921 immed
= (l
>> MIPS16OP_SH_IMM8
) & MIPS16OP_MASK_IMM8
;
922 info
->insn_type
= dis_dref
;
927 immed
= (l
>> MIPS16OP_SH_IMM8
) & MIPS16OP_MASK_IMM8
;
932 immed
= (l
>> MIPS16OP_SH_IMM8
) & MIPS16OP_MASK_IMM8
;
938 immed
= (l
>> MIPS16OP_SH_IMM8
) & MIPS16OP_MASK_IMM8
;
943 immed
= (l
>> MIPS16OP_SH_IMM8
) & MIPS16OP_MASK_IMM8
;
947 info
->insn_type
= dis_condbranch
;
951 immed
= (l
>> MIPS16OP_SH_IMM11
) & MIPS16OP_MASK_IMM11
;
955 info
->insn_type
= dis_branch
;
960 immed
= (l
>> MIPS16OP_SH_IMM8
) & MIPS16OP_MASK_IMM8
;
962 /* FIXME: This can be lw or la. We assume it is lw. */
963 info
->insn_type
= dis_dref
;
969 immed
= (l
>> MIPS16OP_SH_IMM5
) & MIPS16OP_MASK_IMM5
;
971 info
->insn_type
= dis_dref
;
977 immed
= (l
>> MIPS16OP_SH_IMM5
) & MIPS16OP_MASK_IMM5
;
986 if (signedp
&& immed
>= (1 << (nbits
- 1)))
989 if ((type
== '<' || type
== '>' || type
== '[' || type
== ']')
996 immed
|= ((extend
& 0x1f) << 11) | (extend
& 0x7e0);
997 else if (extbits
== 15)
998 immed
|= ((extend
& 0xf) << 11) | (extend
& 0x7f0);
1000 immed
= ((extend
>> 6) & 0x1f) | (extend
& 0x20);
1001 immed
&= (1 << extbits
) - 1;
1002 if (! extu
&& immed
>= (1 << (extbits
- 1)))
1003 immed
-= 1 << extbits
;
1007 (*info
->fprintf_func
) (info
->stream
, "%d", immed
);
1016 baseaddr
= memaddr
+ 2;
1018 else if (use_extend
)
1019 baseaddr
= memaddr
- 2;
1027 /* If this instruction is in the delay slot of a jr
1028 instruction, the base address is the address of the
1029 jr instruction. If it is in the delay slot of jalr
1030 instruction, the base address is the address of the
1031 jalr instruction. This test is unreliable: we have
1032 no way of knowing whether the previous word is
1033 instruction or data. */
1034 status
= (*info
->read_memory_func
) (memaddr
- 4, buffer
, 2,
1037 && (((info
->endian
== BFD_ENDIAN_BIG
1038 ? bfd_getb16 (buffer
)
1039 : bfd_getl16 (buffer
))
1040 & 0xf800) == 0x1800))
1041 baseaddr
= memaddr
- 4;
1044 status
= (*info
->read_memory_func
) (memaddr
- 2, buffer
,
1047 && (((info
->endian
== BFD_ENDIAN_BIG
1048 ? bfd_getb16 (buffer
)
1049 : bfd_getl16 (buffer
))
1050 & 0xf81f) == 0xe800))
1051 baseaddr
= memaddr
- 2;
1054 val
= (baseaddr
& ~ ((1 << shift
) - 1)) + immed
;
1055 (*info
->print_address_func
) (val
, info
);
1064 l
= ((l
& 0x1f) << 23) | ((l
& 0x3e0) << 13) | (extend
<< 2);
1065 (*info
->print_address_func
) (((memaddr
+ 4) & 0xf0000000) | l
, info
);
1066 info
->insn_type
= dis_jsr
;
1067 info
->target
= ((memaddr
+ 4) & 0xf0000000) | l
;
1068 info
->branch_delay_insns
= 1;
1074 int need_comma
, amask
, smask
;
1078 l
= (l
>> MIPS16OP_SH_IMM6
) & MIPS16OP_MASK_IMM6
;
1080 amask
= (l
>> 3) & 7;
1082 if (amask
> 0 && amask
< 5)
1084 (*info
->fprintf_func
) (info
->stream
, "%s", mips32_reg_names
[4]);
1086 (*info
->fprintf_func
) (info
->stream
, "-%s",
1087 mips32_reg_names
[amask
+ 3]);
1091 smask
= (l
>> 1) & 3;
1094 (*info
->fprintf_func
) (info
->stream
, "%s??",
1095 need_comma
? "," : "");
1100 (*info
->fprintf_func
) (info
->stream
, "%s%s",
1101 need_comma
? "," : "",
1102 mips32_reg_names
[16]);
1104 (*info
->fprintf_func
) (info
->stream
, "-%s",
1105 mips32_reg_names
[smask
+ 15]);
1111 (*info
->fprintf_func
) (info
->stream
, "%s%s",
1112 need_comma
? "," : "",
1113 mips32_reg_names
[31]);
1117 if (amask
== 5 || amask
== 6)
1119 (*info
->fprintf_func
) (info
->stream
, "%s$f0",
1120 need_comma
? "," : "");
1122 (*info
->fprintf_func
) (info
->stream
, "-$f1");
1128 /* xgettext:c-format */
1129 (*info
->fprintf_func
)
1131 _("# internal disassembler error, unrecognised modifier (%c)"),
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