1 /* Print mips instructions for GDB, the GNU debugger, or for objdump.
2 Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
4 Free Software Foundation, Inc.
5 Contributed by Nobuyuki Hikichi(hikichi@sra.co.jp).
7 This file is part of GDB, GAS, and the GNU binutils.
9 This program is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 2 of the License, or
12 (at your option) any later version.
14 This program is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with this program; if not, write to the Free Software
21 Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
25 #include "opcode/mips.h"
28 /* FIXME: These are needed to figure out if the code is mips16 or
29 not. The low bit of the address is often a good indicator. No
30 symbol table is available when this code runs out in an embedded
31 system as when it is used for disassembler support in a monitor. */
33 #if !defined(EMBEDDED_ENV)
34 #define SYMTAB_AVAILABLE 1
39 /* Mips instructions are at maximum this many bytes long. */
42 static int _print_insn_mips
43 PARAMS ((bfd_vma
, struct disassemble_info
*, enum bfd_endian
));
44 static int print_insn_mips
45 PARAMS ((bfd_vma
, unsigned long int, struct disassemble_info
*));
46 static void print_insn_arg
47 PARAMS ((const char *, unsigned long, bfd_vma
, struct disassemble_info
*));
48 static void mips_isa_type
49 PARAMS ((int, int *, int *));
50 static int print_insn_mips16
51 PARAMS ((bfd_vma
, struct disassemble_info
*));
53 PARAMS ((Elf_Internal_Ehdr
*));
54 static void print_mips16_insn_arg
55 PARAMS ((int, const struct mips_opcode
*, int, boolean
, int, bfd_vma
,
56 struct disassemble_info
*));
58 /* FIXME: These should be shared with gdb somehow. */
60 /* The mips16 register names. */
61 static const char * const mips16_reg_names
[] = {
62 "s0", "s1", "v0", "v1", "a0", "a1", "a2", "a3"
65 static const char * const mips32_reg_names
[] = {
66 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
67 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7",
68 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
69 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra",
70 "sr", "lo", "hi", "bad", "cause", "pc",
71 "fv0", "$f1", "fv1", "$f3", "ft0", "$f5", "ft1", "$f7",
72 "ft2", "$f9", "ft3", "$f11", "fa0", "$f13", "fa1", "$f15",
73 "ft4", "f17", "ft5", "f19", "fs0", "f21", "fs1", "f23",
74 "fs2", "$f25", "fs3", "$f27", "fs4", "$f29", "fs5", "$f31",
75 "fsr", "fir", "fp", "inx", "rand", "tlblo", "ctxt", "tlbhi",
79 static const char * const mips64_reg_names
[] = {
80 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
81 "a4", "a5", "a6", "a7", "t0", "t1", "t2", "t3",
82 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
83 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra",
84 "sr", "lo", "hi", "bad", "cause", "pc",
85 "fv0", "$f1", "fv1", "$f3", "ft0", "ft1", "ft2", "ft3",
86 "ft4", "ft5", "ft6", "ft7", "fa0", "fa1", "fa2", "fa3",
87 "fa4", "fa5", "fa6", "fa7", "ft8", "ft9", "ft10", "ft11",
88 "fs0", "fs1", "fs2", "fs3", "fs4", "fs5", "fs6", "fs7",
89 "fsr", "fir", "fp", "inx", "rand", "tlblo", "ctxt", "tlbhi",
93 /* Scalar register names. _print_insn_mips() decides which register name
95 static const char * const *reg_names
= NULL
;
97 /* Print insn arguments for 32/64-bit code. */
100 print_insn_arg (d
, l
, pc
, info
)
102 register unsigned long int l
;
104 struct disassemble_info
*info
;
113 (*info
->fprintf_func
) (info
->stream
, "%c", *d
);
120 (*info
->fprintf_func
) (info
->stream
, "%s",
121 reg_names
[(l
>> OP_SH_RS
) & OP_MASK_RS
]);
126 (*info
->fprintf_func
) (info
->stream
, "%s",
127 reg_names
[(l
>> OP_SH_RT
) & OP_MASK_RT
]);
132 (*info
->fprintf_func
) (info
->stream
, "0x%x",
133 (l
>> OP_SH_IMMEDIATE
) & OP_MASK_IMMEDIATE
);
136 case 'j': /* Same as i, but sign-extended. */
138 delta
= (l
>> OP_SH_DELTA
) & OP_MASK_DELTA
;
141 (*info
->fprintf_func
) (info
->stream
, "%d",
146 (*info
->fprintf_func
) (info
->stream
, "0x%x",
147 (unsigned int) ((l
>> OP_SH_PREFX
)
152 (*info
->fprintf_func
) (info
->stream
, "0x%x",
153 (unsigned int) ((l
>> OP_SH_CACHE
)
158 info
->target
= (((pc
+ 4) & ~(bfd_vma
) 0x0fffffff)
159 | (((l
>> OP_SH_TARGET
) & OP_MASK_TARGET
) << 2));
160 (*info
->print_address_func
) (info
->target
, info
);
164 /* Sign extend the displacement. */
165 delta
= (l
>> OP_SH_DELTA
) & OP_MASK_DELTA
;
168 info
->target
= (delta
<< 2) + pc
+ INSNLEN
;
169 (*info
->print_address_func
) (info
->target
, info
);
173 (*info
->fprintf_func
) (info
->stream
, "%s",
174 reg_names
[(l
>> OP_SH_RD
) & OP_MASK_RD
]);
179 /* First check for both rd and rt being equal. */
180 unsigned int reg
= (l
>> OP_SH_RD
) & OP_MASK_RD
;
181 if (reg
== ((l
>> OP_SH_RT
) & OP_MASK_RT
))
182 (*info
->fprintf_func
) (info
->stream
, "%s",
186 /* If one is zero use the other. */
188 (*info
->fprintf_func
) (info
->stream
, "%s",
189 reg_names
[(l
>> OP_SH_RT
) & OP_MASK_RT
]);
190 else if (((l
>> OP_SH_RT
) & OP_MASK_RT
) == 0)
191 (*info
->fprintf_func
) (info
->stream
, "%s",
193 else /* Bogus, result depends on processor. */
194 (*info
->fprintf_func
) (info
->stream
, "%s or %s",
196 reg_names
[(l
>> OP_SH_RT
) & OP_MASK_RT
]);
202 (*info
->fprintf_func
) (info
->stream
, "%s", reg_names
[0]);
206 (*info
->fprintf_func
) (info
->stream
, "0x%x",
207 (l
>> OP_SH_SHAMT
) & OP_MASK_SHAMT
);
211 (*info
->fprintf_func
) (info
->stream
, "0x%x",
212 (l
>> OP_SH_CODE
) & OP_MASK_CODE
);
216 (*info
->fprintf_func
) (info
->stream
, "0x%x",
217 (l
>> OP_SH_CODE2
) & OP_MASK_CODE2
);
221 (*info
->fprintf_func
) (info
->stream
, "0x%x",
222 (l
>> OP_SH_COPZ
) & OP_MASK_COPZ
);
226 (*info
->fprintf_func
) (info
->stream
, "0x%x",
227 (l
>> OP_SH_CODE20
) & OP_MASK_CODE20
);
231 (*info
->fprintf_func
) (info
->stream
, "0x%x",
232 (l
>> OP_SH_CODE19
) & OP_MASK_CODE19
);
237 (*info
->fprintf_func
) (info
->stream
, "$f%d",
238 (l
>> OP_SH_FS
) & OP_MASK_FS
);
243 (*info
->fprintf_func
) (info
->stream
, "$f%d",
244 (l
>> OP_SH_FT
) & OP_MASK_FT
);
248 (*info
->fprintf_func
) (info
->stream
, "$f%d",
249 (l
>> OP_SH_FD
) & OP_MASK_FD
);
253 (*info
->fprintf_func
) (info
->stream
, "$f%d",
254 (l
>> OP_SH_FR
) & OP_MASK_FR
);
258 (*info
->fprintf_func
) (info
->stream
, "$%d",
259 (l
>> OP_SH_RT
) & OP_MASK_RT
);
263 (*info
->fprintf_func
) (info
->stream
, "$%d",
264 (l
>> OP_SH_RD
) & OP_MASK_RD
);
268 (*info
->fprintf_func
) (info
->stream
, "$fcc%d",
269 (l
>> OP_SH_BCC
) & OP_MASK_BCC
);
273 (*info
->fprintf_func
) (info
->stream
, "$fcc%d",
274 (l
>> OP_SH_CCC
) & OP_MASK_CCC
);
278 (*info
->fprintf_func
) (info
->stream
, "%d",
279 (l
>> OP_SH_PERFREG
) & OP_MASK_PERFREG
);
283 (*info
->fprintf_func
) (info
->stream
, "%d",
284 (l
>> OP_SH_SEL
) & OP_MASK_SEL
);
288 /* xgettext:c-format */
289 (*info
->fprintf_func
) (info
->stream
,
290 _("# internal error, undefined modifier(%c)"),
296 /* Figure out the MIPS ISA and CPU based on the machine number. */
299 mips_isa_type (mach
, isa
, cputype
)
306 case bfd_mach_mips3000
:
307 *cputype
= CPU_R3000
;
310 case bfd_mach_mips3900
:
311 *cputype
= CPU_R3900
;
314 case bfd_mach_mips4000
:
315 *cputype
= CPU_R4000
;
318 case bfd_mach_mips4010
:
319 *cputype
= CPU_R4010
;
322 case bfd_mach_mips4100
:
323 *cputype
= CPU_VR4100
;
326 case bfd_mach_mips4111
:
327 *cputype
= CPU_R4111
;
330 case bfd_mach_mips4300
:
331 *cputype
= CPU_R4300
;
334 case bfd_mach_mips4400
:
335 *cputype
= CPU_R4400
;
338 case bfd_mach_mips4600
:
339 *cputype
= CPU_R4600
;
342 case bfd_mach_mips4650
:
343 *cputype
= CPU_R4650
;
346 case bfd_mach_mips5000
:
347 *cputype
= CPU_R5000
;
350 case bfd_mach_mips6000
:
351 *cputype
= CPU_R6000
;
354 case bfd_mach_mips8000
:
355 *cputype
= CPU_R8000
;
358 case bfd_mach_mips10000
:
359 *cputype
= CPU_R10000
;
362 case bfd_mach_mips12000
:
363 *cputype
= CPU_R12000
;
366 case bfd_mach_mips16
:
367 *cputype
= CPU_MIPS16
;
371 *cputype
= CPU_MIPS5
;
374 case bfd_mach_mips_sb1
:
376 *isa
= ISA_MIPS64
| INSN_MIPS3D
| INSN_SB1
;
378 case bfd_mach_mipsisa32
:
379 *cputype
= CPU_MIPS32
;
380 /* For stock MIPS32, disassemble all applicable MIPS-specified ASEs.
381 Note that MIPS-3D is not applicable to MIPS32. (See _MIPS32
382 Architecture For Programmers Volume I: Introduction to the
383 MIPS32 Architecture_ (MIPS Document Number MD00082, Revision 0.95),
387 case bfd_mach_mipsisa64
:
388 *cputype
= CPU_MIPS64
;
389 /* For stock MIPS64, disassemble all applicable MIPS-specified ASEs. */
390 *isa
= ISA_MIPS64
| INSN_MIPS3D
;
394 *cputype
= CPU_R3000
;
400 /* Check if the object uses NewABI conventions. */
404 Elf_Internal_Ehdr
*header
;
406 /* There are no old-style ABIs which use 64-bit ELF. */
407 if (header
->e_ident
[EI_CLASS
] == ELFCLASS64
)
410 /* If a 32-bit ELF file, N32, EABI32, and EABI64 are new-style ABIs. */
411 if ((header
->e_flags
& EF_MIPS_ABI2
) != 0
412 || (header
->e_flags
& EF_MIPS_ABI
) == E_MIPS_ABI_EABI32
413 || (header
->e_flags
& EF_MIPS_ABI
) == E_MIPS_ABI_EABI64
)
419 /* Print the mips instruction at address MEMADDR in debugged memory,
420 on using INFO. Returns length of the instruction, in bytes, which is
421 always INSNLEN. BIGENDIAN must be 1 if this is big-endian code, 0 if
422 this is little-endian code. */
425 print_insn_mips (memaddr
, word
, info
)
427 unsigned long int word
;
428 struct disassemble_info
*info
;
430 register const struct mips_opcode
*op
;
431 int target_processor
, mips_isa
;
432 static boolean init
= 0;
433 static const struct mips_opcode
*mips_hash
[OP_MASK_OP
+ 1];
435 /* Build a hash table to shorten the search time. */
440 for (i
= 0; i
<= OP_MASK_OP
; i
++)
442 for (op
= mips_opcodes
; op
< &mips_opcodes
[NUMOPCODES
]; op
++)
444 if (op
->pinfo
== INSN_MACRO
)
446 if (i
== ((op
->match
>> OP_SH_OP
) & OP_MASK_OP
))
457 #if ! SYMTAB_AVAILABLE
458 /* This is running out on a target machine, not in a host tool.
459 FIXME: Where does mips_target_info come from? */
460 target_processor
= mips_target_info
.processor
;
461 mips_isa
= mips_target_info
.isa
;
463 mips_isa_type (info
->mach
, &mips_isa
, &target_processor
);
466 info
->bytes_per_chunk
= INSNLEN
;
467 info
->display_endian
= info
->endian
;
468 info
->insn_info_valid
= 1;
469 info
->branch_delay_insns
= 0;
471 info
->insn_type
= dis_nonbranch
;
475 op
= mips_hash
[(word
>> OP_SH_OP
) & OP_MASK_OP
];
478 for (; op
< &mips_opcodes
[NUMOPCODES
]; op
++)
480 if (op
->pinfo
!= INSN_MACRO
&& (word
& op
->mask
) == op
->match
)
482 register const char *d
;
484 if (! OPCODE_IS_MEMBER (op
, mips_isa
, target_processor
))
487 /* Figure out instruction type and branch delay information. */
488 if ((op
->pinfo
& INSN_UNCOND_BRANCH_DELAY
) != 0)
490 if ((info
->insn_type
& INSN_WRITE_GPR_31
) != 0)
491 info
->insn_type
= dis_jsr
;
493 info
->insn_type
= dis_branch
;
494 info
->branch_delay_insns
= 1;
496 else if ((op
->pinfo
& (INSN_COND_BRANCH_DELAY
497 | INSN_COND_BRANCH_LIKELY
)) != 0)
499 if ((info
->insn_type
& INSN_WRITE_GPR_31
) != 0)
500 info
->insn_type
= dis_condjsr
;
502 info
->insn_type
= dis_condbranch
;
503 info
->branch_delay_insns
= 1;
505 else if ((op
->pinfo
& (INSN_STORE_MEMORY
506 | INSN_LOAD_MEMORY_DELAY
)) != 0)
507 info
->insn_type
= dis_dref
;
509 (*info
->fprintf_func
) (info
->stream
, "%s", op
->name
);
512 if (d
!= NULL
&& *d
!= '\0')
514 (*info
->fprintf_func
) (info
->stream
, "\t");
515 for (; *d
!= '\0'; d
++)
516 print_insn_arg (d
, word
, memaddr
, info
);
524 /* Handle undefined instructions. */
525 info
->insn_type
= dis_noninsn
;
526 (*info
->fprintf_func
) (info
->stream
, "0x%x", word
);
530 /* In an environment where we do not know the symbol type of the
531 instruction we are forced to assume that the low order bit of the
532 instructions' address may mark it as a mips16 instruction. If we
533 are single stepping, or the pc is within the disassembled function,
534 this works. Otherwise, we need a clue. Sometimes. */
537 _print_insn_mips (memaddr
, info
, endianness
)
539 struct disassemble_info
*info
;
540 enum bfd_endian endianness
;
542 bfd_byte buffer
[INSNLEN
];
546 /* FIXME: If odd address, this is CLEARLY a mips 16 instruction. */
547 /* Only a few tools will work this way. */
549 return print_insn_mips16 (memaddr
, info
);
554 || (info
->flavour
== bfd_target_elf_flavour
555 && info
->symbols
!= NULL
556 && ((*(elf_symbol_type
**) info
->symbols
)->internal_elf_sym
.st_other
558 return print_insn_mips16 (memaddr
, info
);
561 /* Use mips64_reg_names for new ABI. */
562 reg_names
= mips32_reg_names
;
564 if (info
->flavour
== bfd_target_elf_flavour
&& info
->symbols
!= NULL
)
566 Elf_Internal_Ehdr
*header
;
568 header
= elf_elfheader (bfd_asymbol_bfd (*(info
->symbols
)));
569 if (is_newabi (header
))
570 reg_names
= mips64_reg_names
;
573 status
= (*info
->read_memory_func
) (memaddr
, buffer
, INSNLEN
, info
);
578 if (endianness
== BFD_ENDIAN_BIG
)
579 insn
= (unsigned long) bfd_getb32 (buffer
);
581 insn
= (unsigned long) bfd_getl32 (buffer
);
583 return print_insn_mips (memaddr
, insn
, info
);
587 (*info
->memory_error_func
) (status
, memaddr
, info
);
593 print_insn_big_mips (memaddr
, info
)
595 struct disassemble_info
*info
;
597 return _print_insn_mips (memaddr
, info
, BFD_ENDIAN_BIG
);
601 print_insn_little_mips (memaddr
, info
)
603 struct disassemble_info
*info
;
605 return _print_insn_mips (memaddr
, info
, BFD_ENDIAN_LITTLE
);
608 /* Disassemble mips16 instructions. */
611 print_insn_mips16 (memaddr
, info
)
613 struct disassemble_info
*info
;
621 const struct mips_opcode
*op
, *opend
;
623 info
->bytes_per_chunk
= 2;
624 info
->display_endian
= info
->endian
;
625 info
->insn_info_valid
= 1;
626 info
->branch_delay_insns
= 0;
628 info
->insn_type
= dis_nonbranch
;
632 status
= (*info
->read_memory_func
) (memaddr
, buffer
, 2, info
);
635 (*info
->memory_error_func
) (status
, memaddr
, info
);
641 if (info
->endian
== BFD_ENDIAN_BIG
)
642 insn
= bfd_getb16 (buffer
);
644 insn
= bfd_getl16 (buffer
);
646 /* Handle the extend opcode specially. */
648 if ((insn
& 0xf800) == 0xf000)
651 extend
= insn
& 0x7ff;
655 status
= (*info
->read_memory_func
) (memaddr
, buffer
, 2, info
);
658 (*info
->fprintf_func
) (info
->stream
, "extend 0x%x",
659 (unsigned int) extend
);
660 (*info
->memory_error_func
) (status
, memaddr
, info
);
664 if (info
->endian
== BFD_ENDIAN_BIG
)
665 insn
= bfd_getb16 (buffer
);
667 insn
= bfd_getl16 (buffer
);
669 /* Check for an extend opcode followed by an extend opcode. */
670 if ((insn
& 0xf800) == 0xf000)
672 (*info
->fprintf_func
) (info
->stream
, "extend 0x%x",
673 (unsigned int) extend
);
674 info
->insn_type
= dis_noninsn
;
681 /* FIXME: Should probably use a hash table on the major opcode here. */
683 opend
= mips16_opcodes
+ bfd_mips16_num_opcodes
;
684 for (op
= mips16_opcodes
; op
< opend
; op
++)
686 if (op
->pinfo
!= INSN_MACRO
&& (insn
& op
->mask
) == op
->match
)
690 if (strchr (op
->args
, 'a') != NULL
)
694 (*info
->fprintf_func
) (info
->stream
, "extend 0x%x",
695 (unsigned int) extend
);
696 info
->insn_type
= dis_noninsn
;
704 status
= (*info
->read_memory_func
) (memaddr
, buffer
, 2,
709 if (info
->endian
== BFD_ENDIAN_BIG
)
710 extend
= bfd_getb16 (buffer
);
712 extend
= bfd_getl16 (buffer
);
717 (*info
->fprintf_func
) (info
->stream
, "%s", op
->name
);
718 if (op
->args
[0] != '\0')
719 (*info
->fprintf_func
) (info
->stream
, "\t");
721 for (s
= op
->args
; *s
!= '\0'; s
++)
725 && (((insn
>> MIPS16OP_SH_RX
) & MIPS16OP_MASK_RX
)
726 == ((insn
>> MIPS16OP_SH_RY
) & MIPS16OP_MASK_RY
)))
728 /* Skip the register and the comma. */
734 && (((insn
>> MIPS16OP_SH_RZ
) & MIPS16OP_MASK_RZ
)
735 == ((insn
>> MIPS16OP_SH_RX
) & MIPS16OP_MASK_RX
)))
737 /* Skip the register and the comma. */
741 print_mips16_insn_arg (*s
, op
, insn
, use_extend
, extend
, memaddr
,
745 if ((op
->pinfo
& INSN_UNCOND_BRANCH_DELAY
) != 0)
747 info
->branch_delay_insns
= 1;
748 if (info
->insn_type
!= dis_jsr
)
749 info
->insn_type
= dis_branch
;
757 (*info
->fprintf_func
) (info
->stream
, "0x%x", extend
| 0xf000);
758 (*info
->fprintf_func
) (info
->stream
, "0x%x", insn
);
759 info
->insn_type
= dis_noninsn
;
764 /* Disassemble an operand for a mips16 instruction. */
767 print_mips16_insn_arg (type
, op
, l
, use_extend
, extend
, memaddr
, info
)
769 const struct mips_opcode
*op
;
774 struct disassemble_info
*info
;
781 (*info
->fprintf_func
) (info
->stream
, "%c", type
);
786 (*info
->fprintf_func
) (info
->stream
, "%s",
787 mips16_reg_names
[((l
>> MIPS16OP_SH_RY
)
788 & MIPS16OP_MASK_RY
)]);
793 (*info
->fprintf_func
) (info
->stream
, "%s",
794 mips16_reg_names
[((l
>> MIPS16OP_SH_RX
)
795 & MIPS16OP_MASK_RX
)]);
799 (*info
->fprintf_func
) (info
->stream
, "%s",
800 mips16_reg_names
[((l
>> MIPS16OP_SH_RZ
)
801 & MIPS16OP_MASK_RZ
)]);
805 (*info
->fprintf_func
) (info
->stream
, "%s",
806 mips16_reg_names
[((l
>> MIPS16OP_SH_MOVE32Z
)
807 & MIPS16OP_MASK_MOVE32Z
)]);
811 (*info
->fprintf_func
) (info
->stream
, "%s", mips32_reg_names
[0]);
815 (*info
->fprintf_func
) (info
->stream
, "%s", mips32_reg_names
[29]);
819 (*info
->fprintf_func
) (info
->stream
, "$pc");
823 (*info
->fprintf_func
) (info
->stream
, "%s", mips32_reg_names
[31]);
827 (*info
->fprintf_func
) (info
->stream
, "%s",
828 mips32_reg_names
[((l
>> MIPS16OP_SH_REGR32
)
829 & MIPS16OP_MASK_REGR32
)]);
833 (*info
->fprintf_func
) (info
->stream
, "%s",
834 mips32_reg_names
[MIPS16OP_EXTRACT_REG32R (l
)]);
860 int immed
, nbits
, shift
, signedp
, extbits
, pcrel
, extu
, branch
;
872 immed
= (l
>> MIPS16OP_SH_RZ
) & MIPS16OP_MASK_RZ
;
878 immed
= (l
>> MIPS16OP_SH_RX
) & MIPS16OP_MASK_RX
;
884 immed
= (l
>> MIPS16OP_SH_RZ
) & MIPS16OP_MASK_RZ
;
890 immed
= (l
>> MIPS16OP_SH_RX
) & MIPS16OP_MASK_RX
;
896 immed
= (l
>> MIPS16OP_SH_IMM4
) & MIPS16OP_MASK_IMM4
;
902 immed
= (l
>> MIPS16OP_SH_IMM5
) & MIPS16OP_MASK_IMM5
;
903 info
->insn_type
= dis_dref
;
909 immed
= (l
>> MIPS16OP_SH_IMM5
) & MIPS16OP_MASK_IMM5
;
910 info
->insn_type
= dis_dref
;
916 immed
= (l
>> MIPS16OP_SH_IMM5
) & MIPS16OP_MASK_IMM5
;
917 if ((op
->pinfo
& MIPS16_INSN_READ_PC
) == 0
918 && (op
->pinfo
& MIPS16_INSN_READ_SP
) == 0)
920 info
->insn_type
= dis_dref
;
927 immed
= (l
>> MIPS16OP_SH_IMM5
) & MIPS16OP_MASK_IMM5
;
928 info
->insn_type
= dis_dref
;
933 immed
= (l
>> MIPS16OP_SH_IMM5
) & MIPS16OP_MASK_IMM5
;
938 immed
= (l
>> MIPS16OP_SH_IMM6
) & MIPS16OP_MASK_IMM6
;
942 immed
= (l
>> MIPS16OP_SH_IMM8
) & MIPS16OP_MASK_IMM8
;
947 immed
= (l
>> MIPS16OP_SH_IMM8
) & MIPS16OP_MASK_IMM8
;
948 /* FIXME: This might be lw, or it might be addiu to $sp or
949 $pc. We assume it's load. */
950 info
->insn_type
= dis_dref
;
956 immed
= (l
>> MIPS16OP_SH_IMM8
) & MIPS16OP_MASK_IMM8
;
957 info
->insn_type
= dis_dref
;
962 immed
= (l
>> MIPS16OP_SH_IMM8
) & MIPS16OP_MASK_IMM8
;
967 immed
= (l
>> MIPS16OP_SH_IMM8
) & MIPS16OP_MASK_IMM8
;
973 immed
= (l
>> MIPS16OP_SH_IMM8
) & MIPS16OP_MASK_IMM8
;
978 immed
= (l
>> MIPS16OP_SH_IMM8
) & MIPS16OP_MASK_IMM8
;
982 info
->insn_type
= dis_condbranch
;
986 immed
= (l
>> MIPS16OP_SH_IMM11
) & MIPS16OP_MASK_IMM11
;
990 info
->insn_type
= dis_branch
;
995 immed
= (l
>> MIPS16OP_SH_IMM8
) & MIPS16OP_MASK_IMM8
;
997 /* FIXME: This can be lw or la. We assume it is lw. */
998 info
->insn_type
= dis_dref
;
1004 immed
= (l
>> MIPS16OP_SH_IMM5
) & MIPS16OP_MASK_IMM5
;
1006 info
->insn_type
= dis_dref
;
1007 info
->data_size
= 8;
1012 immed
= (l
>> MIPS16OP_SH_IMM5
) & MIPS16OP_MASK_IMM5
;
1021 if (signedp
&& immed
>= (1 << (nbits
- 1)))
1022 immed
-= 1 << nbits
;
1024 if ((type
== '<' || type
== '>' || type
== '[' || type
== ']')
1031 immed
|= ((extend
& 0x1f) << 11) | (extend
& 0x7e0);
1032 else if (extbits
== 15)
1033 immed
|= ((extend
& 0xf) << 11) | (extend
& 0x7f0);
1035 immed
= ((extend
>> 6) & 0x1f) | (extend
& 0x20);
1036 immed
&= (1 << extbits
) - 1;
1037 if (! extu
&& immed
>= (1 << (extbits
- 1)))
1038 immed
-= 1 << extbits
;
1042 (*info
->fprintf_func
) (info
->stream
, "%d", immed
);
1050 baseaddr
= memaddr
+ 2;
1052 else if (use_extend
)
1053 baseaddr
= memaddr
- 2;
1061 /* If this instruction is in the delay slot of a jr
1062 instruction, the base address is the address of the
1063 jr instruction. If it is in the delay slot of jalr
1064 instruction, the base address is the address of the
1065 jalr instruction. This test is unreliable: we have
1066 no way of knowing whether the previous word is
1067 instruction or data. */
1068 status
= (*info
->read_memory_func
) (memaddr
- 4, buffer
, 2,
1071 && (((info
->endian
== BFD_ENDIAN_BIG
1072 ? bfd_getb16 (buffer
)
1073 : bfd_getl16 (buffer
))
1074 & 0xf800) == 0x1800))
1075 baseaddr
= memaddr
- 4;
1078 status
= (*info
->read_memory_func
) (memaddr
- 2, buffer
,
1081 && (((info
->endian
== BFD_ENDIAN_BIG
1082 ? bfd_getb16 (buffer
)
1083 : bfd_getl16 (buffer
))
1084 & 0xf81f) == 0xe800))
1085 baseaddr
= memaddr
- 2;
1088 info
->target
= (baseaddr
& ~((1 << shift
) - 1)) + immed
;
1089 (*info
->print_address_func
) (info
->target
, info
);
1097 l
= ((l
& 0x1f) << 23) | ((l
& 0x3e0) << 13) | (extend
<< 2);
1098 info
->target
= ((memaddr
+ 4) & ~(bfd_vma
) 0x0fffffff) | l
;
1099 (*info
->print_address_func
) (info
->target
, info
);
1100 info
->insn_type
= dis_jsr
;
1101 info
->branch_delay_insns
= 1;
1107 int need_comma
, amask
, smask
;
1111 l
= (l
>> MIPS16OP_SH_IMM6
) & MIPS16OP_MASK_IMM6
;
1113 amask
= (l
>> 3) & 7;
1115 if (amask
> 0 && amask
< 5)
1117 (*info
->fprintf_func
) (info
->stream
, "%s", mips32_reg_names
[4]);
1119 (*info
->fprintf_func
) (info
->stream
, "-%s",
1120 mips32_reg_names
[amask
+ 3]);
1124 smask
= (l
>> 1) & 3;
1127 (*info
->fprintf_func
) (info
->stream
, "%s??",
1128 need_comma
? "," : "");
1133 (*info
->fprintf_func
) (info
->stream
, "%s%s",
1134 need_comma
? "," : "",
1135 mips32_reg_names
[16]);
1137 (*info
->fprintf_func
) (info
->stream
, "-%s",
1138 mips32_reg_names
[smask
+ 15]);
1144 (*info
->fprintf_func
) (info
->stream
, "%s%s",
1145 need_comma
? "," : "",
1146 mips32_reg_names
[31]);
1150 if (amask
== 5 || amask
== 6)
1152 (*info
->fprintf_func
) (info
->stream
, "%s$f0",
1153 need_comma
? "," : "");
1155 (*info
->fprintf_func
) (info
->stream
, "-$f1");
1161 /* xgettext:c-format */
1162 (*info
->fprintf_func
)
1164 _("# internal disassembler error, unrecognised modifier (%c)"),
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