bb970ef5483b7c8c3ae103d58b42f9a72dd1be64
1 /* Print mips instructions for GDB, the GNU debugger, or for objdump.
2 Copyright (c) 1989, 91, 92, 93, 94, 95, 96, 97, 98, 99, 2000
3 Free Software Foundation, Inc.
4 Contributed by Nobuyuki Hikichi(hikichi@sra.co.jp).
6 This file is part of GDB, GAS, and the GNU binutils.
8 This program is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2 of the License, or
11 (at your option) any later version.
13 This program is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with this program; if not, write to the Free Software
20 Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
24 #include "opcode/mips.h"
27 /* FIXME: These are needed to figure out if the code is mips16 or
28 not. The low bit of the address is often a good indicator. No
29 symbol table is available when this code runs out in an embedded
30 system as when it is used for disassembler support in a monitor. */
32 #if !defined(EMBEDDED_ENV)
33 #define SYMTAB_AVAILABLE 1
38 static int print_insn_mips16
PARAMS ((bfd_vma
, struct disassemble_info
*));
39 static void print_mips16_insn_arg
40 PARAMS ((int, const struct mips_opcode
*, int, boolean
, int, bfd_vma
,
41 struct disassemble_info
*));
43 /* Mips instructions are never longer than this many bytes. */
46 static void print_insn_arg
PARAMS ((const char *, unsigned long, bfd_vma
,
47 struct disassemble_info
*));
48 static int _print_insn_mips
PARAMS ((bfd_vma
, unsigned long int,
49 struct disassemble_info
*));
52 /* FIXME: This should be shared with gdb somehow. */
53 #define STD_REGISTER_NAMES \
54 { "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3", \
55 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7", \
56 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", \
57 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra", \
58 "sr", "lo", "hi", "bad", "cause","pc", \
59 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", \
60 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", \
61 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",\
62 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",\
63 "fsr", "fir", "fp", "inx", "rand", "tlblo","ctxt", "tlbhi",\
67 static CONST
char * CONST std_reg_names
[] = STD_REGISTER_NAMES
;
69 /* The mips16 register names. */
70 static const char * const mips16_reg_names
[] =
72 "s0", "s1", "v0", "v1", "a0", "a1", "a2", "a3"
75 /* Scalar register names. set_mips_isa_type() decides which register name
77 static CONST
char * CONST
*reg_names
= NULL
;
81 print_insn_arg (d
, l
, pc
, info
)
83 register unsigned long int l
;
85 struct disassemble_info
*info
;
94 (*info
->fprintf_func
) (info
->stream
, "%c", *d
);
101 (*info
->fprintf_func
) (info
->stream
, "$%s",
102 reg_names
[(l
>> OP_SH_RS
) & OP_MASK_RS
]);
107 (*info
->fprintf_func
) (info
->stream
, "$%s",
108 reg_names
[(l
>> OP_SH_RT
) & OP_MASK_RT
]);
113 (*info
->fprintf_func
) (info
->stream
, "0x%x",
114 (l
>> OP_SH_IMMEDIATE
) & OP_MASK_IMMEDIATE
);
117 case 'j': /* same as i, but sign-extended */
119 delta
= (l
>> OP_SH_DELTA
) & OP_MASK_DELTA
;
122 (*info
->fprintf_func
) (info
->stream
, "%d",
127 (*info
->fprintf_func
) (info
->stream
, "0x%x",
128 (unsigned int) ((l
>> OP_SH_PREFX
)
133 (*info
->fprintf_func
) (info
->stream
, "0x%x",
134 (unsigned int) ((l
>> OP_SH_CACHE
)
139 (*info
->print_address_func
)
140 (((pc
& ~ (bfd_vma
) 0x0fffffff)
141 | (((l
>> OP_SH_TARGET
) & OP_MASK_TARGET
) << 2)),
146 /* sign extend the displacement */
147 delta
= (l
>> OP_SH_DELTA
) & OP_MASK_DELTA
;
150 (*info
->print_address_func
)
151 ((delta
<< 2) + pc
+ 4,
156 (*info
->fprintf_func
) (info
->stream
, "$%s",
157 reg_names
[(l
>> OP_SH_RD
) & OP_MASK_RD
]);
162 /* First check for both rd and rt being equal. */
163 int reg
= (l
>> OP_SH_RD
) & OP_MASK_RD
;
164 if (reg
== ((l
>> OP_SH_RT
) & OP_MASK_RT
))
165 (*info
->fprintf_func
) (info
->stream
, "$%s",
169 /* If one is zero use the other. */
171 (*info
->fprintf_func
) (info
->stream
, "$%s",
172 reg_names
[(l
>> OP_SH_RT
) & OP_MASK_RT
]);
173 else if (((l
>> OP_SH_RT
) & OP_MASK_RT
) == 0)
174 (*info
->fprintf_func
) (info
->stream
, "$%s",
176 else /* Bogus, result depends on processor. */
177 (*info
->fprintf_func
) (info
->stream
, "$%s or $%s",
179 reg_names
[(l
>> OP_SH_RT
) & OP_MASK_RT
]);
185 (*info
->fprintf_func
) (info
->stream
, "$%s", reg_names
[0]);
189 (*info
->fprintf_func
) (info
->stream
, "0x%x",
190 (l
>> OP_SH_SHAMT
) & OP_MASK_SHAMT
);
194 (*info
->fprintf_func
) (info
->stream
, "0x%x",
195 (l
>> OP_SH_CODE
) & OP_MASK_CODE
);
199 (*info
->fprintf_func
) (info
->stream
, "0x%x",
200 (l
>> OP_SH_CODE2
) & OP_MASK_CODE2
);
204 (*info
->fprintf_func
) (info
->stream
, "0x%x",
205 (l
>> OP_SH_COPZ
) & OP_MASK_COPZ
);
209 (*info
->fprintf_func
) (info
->stream
, "0x%x",
210 (l
>> OP_SH_CODE20
) & OP_MASK_CODE20
);
214 (*info
->fprintf_func
) (info
->stream
, "0x%x",
215 (l
>> OP_SH_CODE19
) & OP_MASK_CODE19
);
220 (*info
->fprintf_func
) (info
->stream
, "$f%d",
221 (l
>> OP_SH_FS
) & OP_MASK_FS
);
226 (*info
->fprintf_func
) (info
->stream
, "$f%d",
227 (l
>> OP_SH_FT
) & OP_MASK_FT
);
231 (*info
->fprintf_func
) (info
->stream
, "$f%d",
232 (l
>> OP_SH_FD
) & OP_MASK_FD
);
236 (*info
->fprintf_func
) (info
->stream
, "$f%d",
237 (l
>> OP_SH_FR
) & OP_MASK_FR
);
241 (*info
->fprintf_func
) (info
->stream
, "$%d",
242 (l
>> OP_SH_RT
) & OP_MASK_RT
);
246 (*info
->fprintf_func
) (info
->stream
, "$%d",
247 (l
>> OP_SH_RD
) & OP_MASK_RD
);
251 (*info
->fprintf_func
) (info
->stream
, "$fcc%d",
252 (l
>> OP_SH_BCC
) & OP_MASK_BCC
);
256 (*info
->fprintf_func
) (info
->stream
, "$fcc%d",
257 (l
>> OP_SH_CCC
) & OP_MASK_CCC
);
261 (*info
->fprintf_func
) (info
->stream
, "%d",
262 (l
>> OP_SH_PERFREG
) & OP_MASK_PERFREG
);
266 (*info
->fprintf_func
) (info
->stream
, "%d",
267 (l
>> OP_SH_SEL
) & OP_MASK_SEL
);
271 /* xgettext:c-format */
272 (*info
->fprintf_func
) (info
->stream
,
273 _("# internal error, undefined modifier(%c)"),
281 /* Figure out the MIPS ISA and CPU based on the machine number.
282 FIXME: What does this have to do with SYMTAB_AVAILABLE? */
285 set_mips_isa_type (mach
, isa
, cputype
)
290 int target_processor
= CPU_UNKNOWN
;
291 int mips_isa
= ISA_UNKNOWN
;
293 /* Use standard MIPS register names by default. */
294 reg_names
= std_reg_names
;
298 case bfd_mach_mips3000
:
299 target_processor
= CPU_R3000
;
300 mips_isa
= ISA_MIPS1
;
302 case bfd_mach_mips3900
:
303 target_processor
= CPU_R3900
;
304 mips_isa
= ISA_MIPS1
;
306 case bfd_mach_mips4000
:
307 target_processor
= CPU_R4000
;
308 mips_isa
= ISA_MIPS3
;
310 case bfd_mach_mips4010
:
311 target_processor
= CPU_R4010
;
312 mips_isa
= ISA_MIPS2
;
314 case bfd_mach_mips4100
:
315 target_processor
= CPU_VR4100
;
316 mips_isa
= ISA_MIPS3
;
318 case bfd_mach_mips4111
:
319 target_processor
= CPU_VR4100
; /* FIXME: Shouldn't this be CPU_R4111 ??? */
320 mips_isa
= ISA_MIPS3
;
322 case bfd_mach_mips4300
:
323 target_processor
= CPU_R4300
;
324 mips_isa
= ISA_MIPS3
;
326 case bfd_mach_mips4400
:
327 target_processor
= CPU_R4400
;
328 mips_isa
= ISA_MIPS3
;
330 case bfd_mach_mips4600
:
331 target_processor
= CPU_R4600
;
332 mips_isa
= ISA_MIPS3
;
334 case bfd_mach_mips4650
:
335 target_processor
= CPU_R4650
;
336 mips_isa
= ISA_MIPS3
;
338 case bfd_mach_mips5000
:
339 target_processor
= CPU_R5000
;
340 mips_isa
= ISA_MIPS4
;
342 case bfd_mach_mips6000
:
343 target_processor
= CPU_R6000
;
344 mips_isa
= ISA_MIPS2
;
346 case bfd_mach_mips8000
:
347 target_processor
= CPU_R8000
;
348 mips_isa
= ISA_MIPS4
;
350 case bfd_mach_mips10000
:
351 target_processor
= CPU_R10000
;
352 mips_isa
= ISA_MIPS4
;
354 case bfd_mach_mips16
:
355 target_processor
= CPU_MIPS16
;
356 mips_isa
= ISA_MIPS3
;
358 case bfd_mach_mips32
:
359 target_processor
= CPU_MIPS32
;
360 mips_isa
= ISA_MIPS32
;
362 case bfd_mach_mips32_4k
:
363 target_processor
= CPU_MIPS32_4K
;
364 mips_isa
= ISA_MIPS32
;
367 target_processor
= CPU_R3000
;
368 mips_isa
= ISA_MIPS3
;
373 *cputype
= target_processor
;
376 #endif /* SYMTAB_AVAILABLE */
378 /* Print the mips instruction at address MEMADDR in debugged memory,
379 on using INFO. Returns length of the instruction, in bytes, which is
380 always 4. BIGENDIAN must be 1 if this is big-endian code, 0 if
381 this is little-endian code. */
384 _print_insn_mips (memaddr
, word
, info
)
386 unsigned long int word
;
387 struct disassemble_info
*info
;
389 register const struct mips_opcode
*op
;
390 int target_processor
, mips_isa
;
391 static boolean init
= 0;
392 static const struct mips_opcode
*mips_hash
[OP_MASK_OP
+ 1];
394 /* Build a hash table to shorten the search time. */
399 for (i
= 0; i
<= OP_MASK_OP
; i
++)
401 for (op
= mips_opcodes
; op
< &mips_opcodes
[NUMOPCODES
]; op
++)
403 if (op
->pinfo
== INSN_MACRO
)
405 if (i
== ((op
->match
>> OP_SH_OP
) & OP_MASK_OP
))
416 #if ! SYMTAB_AVAILABLE
417 /* This is running out on a target machine, not in a host tool.
418 FIXME: Where does mips_target_info come from? */
419 target_processor
= mips_target_info
.processor
;
420 mips_isa
= mips_target_info
.isa
;
422 set_mips_isa_type (info
->mach
, &mips_isa
, &target_processor
);
425 info
->bytes_per_chunk
= 4;
426 info
->display_endian
= info
->endian
;
428 op
= mips_hash
[(word
>> OP_SH_OP
) & OP_MASK_OP
];
431 for (; op
< &mips_opcodes
[NUMOPCODES
]; op
++)
433 if (op
->pinfo
!= INSN_MACRO
&& (word
& op
->mask
) == op
->match
)
435 register const char *d
;
437 if (! OPCODE_IS_MEMBER (op
, mips_isa
, target_processor
, 0))
440 (*info
->fprintf_func
) (info
->stream
, "%s", op
->name
);
443 if (d
!= NULL
&& *d
!= '\0')
445 (*info
->fprintf_func
) (info
->stream
, "\t");
446 for (; *d
!= '\0'; d
++)
447 print_insn_arg (d
, word
, memaddr
, info
);
455 /* Handle undefined instructions. */
456 (*info
->fprintf_func
) (info
->stream
, "0x%x", word
);
461 /* In an environment where we do not know the symbol type of the
462 instruction we are forced to assume that the low order bit of the
463 instructions' address may mark it as a mips16 instruction. If we
464 are single stepping, or the pc is within the disassembled function,
465 this works. Otherwise, we need a clue. Sometimes. */
468 print_insn_big_mips (memaddr
, info
)
470 struct disassemble_info
*info
;
476 /* FIXME: If odd address, this is CLEARLY a mips 16 instruction. */
477 /* Only a few tools will work this way. */
479 return print_insn_mips16 (memaddr
, info
);
484 || (info
->flavour
== bfd_target_elf_flavour
485 && info
->symbols
!= NULL
486 && ((*(elf_symbol_type
**) info
->symbols
)->internal_elf_sym
.st_other
488 return print_insn_mips16 (memaddr
, info
);
491 status
= (*info
->read_memory_func
) (memaddr
, buffer
, 4, info
);
493 return _print_insn_mips (memaddr
, (unsigned long) bfd_getb32 (buffer
),
497 (*info
->memory_error_func
) (status
, memaddr
, info
);
503 print_insn_little_mips (memaddr
, info
)
505 struct disassemble_info
*info
;
513 return print_insn_mips16 (memaddr
, info
);
518 || (info
->flavour
== bfd_target_elf_flavour
519 && info
->symbols
!= NULL
520 && ((*(elf_symbol_type
**) info
->symbols
)->internal_elf_sym
.st_other
522 return print_insn_mips16 (memaddr
, info
);
525 status
= (*info
->read_memory_func
) (memaddr
, buffer
, 4, info
);
527 return _print_insn_mips (memaddr
, (unsigned long) bfd_getl32 (buffer
),
531 (*info
->memory_error_func
) (status
, memaddr
, info
);
536 /* Disassemble mips16 instructions. */
539 print_insn_mips16 (memaddr
, info
)
541 struct disassemble_info
*info
;
549 const struct mips_opcode
*op
, *opend
;
551 info
->bytes_per_chunk
= 2;
552 info
->display_endian
= info
->endian
;
554 info
->insn_info_valid
= 1;
555 info
->branch_delay_insns
= 0;
557 info
->insn_type
= dis_nonbranch
;
561 status
= (*info
->read_memory_func
) (memaddr
, buffer
, 2, info
);
564 (*info
->memory_error_func
) (status
, memaddr
, info
);
570 if (info
->endian
== BFD_ENDIAN_BIG
)
571 insn
= bfd_getb16 (buffer
);
573 insn
= bfd_getl16 (buffer
);
575 /* Handle the extend opcode specially. */
577 if ((insn
& 0xf800) == 0xf000)
580 extend
= insn
& 0x7ff;
584 status
= (*info
->read_memory_func
) (memaddr
, buffer
, 2, info
);
587 (*info
->fprintf_func
) (info
->stream
, "extend 0x%x",
588 (unsigned int) extend
);
589 (*info
->memory_error_func
) (status
, memaddr
, info
);
593 if (info
->endian
== BFD_ENDIAN_BIG
)
594 insn
= bfd_getb16 (buffer
);
596 insn
= bfd_getl16 (buffer
);
598 /* Check for an extend opcode followed by an extend opcode. */
599 if ((insn
& 0xf800) == 0xf000)
601 (*info
->fprintf_func
) (info
->stream
, "extend 0x%x",
602 (unsigned int) extend
);
603 info
->insn_type
= dis_noninsn
;
610 /* FIXME: Should probably use a hash table on the major opcode here. */
612 opend
= mips16_opcodes
+ bfd_mips16_num_opcodes
;
613 for (op
= mips16_opcodes
; op
< opend
; op
++)
615 if (op
->pinfo
!= INSN_MACRO
&& (insn
& op
->mask
) == op
->match
)
619 if (strchr (op
->args
, 'a') != NULL
)
623 (*info
->fprintf_func
) (info
->stream
, "extend 0x%x",
624 (unsigned int) extend
);
625 info
->insn_type
= dis_noninsn
;
633 status
= (*info
->read_memory_func
) (memaddr
, buffer
, 2,
638 if (info
->endian
== BFD_ENDIAN_BIG
)
639 extend
= bfd_getb16 (buffer
);
641 extend
= bfd_getl16 (buffer
);
646 (*info
->fprintf_func
) (info
->stream
, "%s", op
->name
);
647 if (op
->args
[0] != '\0')
648 (*info
->fprintf_func
) (info
->stream
, "\t");
650 for (s
= op
->args
; *s
!= '\0'; s
++)
654 && (((insn
>> MIPS16OP_SH_RX
) & MIPS16OP_MASK_RX
)
655 == ((insn
>> MIPS16OP_SH_RY
) & MIPS16OP_MASK_RY
)))
657 /* Skip the register and the comma. */
663 && (((insn
>> MIPS16OP_SH_RZ
) & MIPS16OP_MASK_RZ
)
664 == ((insn
>> MIPS16OP_SH_RX
) & MIPS16OP_MASK_RX
)))
666 /* Skip the register and the comma. */
670 print_mips16_insn_arg (*s
, op
, insn
, use_extend
, extend
, memaddr
,
674 if ((op
->pinfo
& INSN_UNCOND_BRANCH_DELAY
) != 0)
676 info
->branch_delay_insns
= 1;
677 if (info
->insn_type
!= dis_jsr
)
678 info
->insn_type
= dis_branch
;
686 (*info
->fprintf_func
) (info
->stream
, "0x%x", extend
| 0xf000);
687 (*info
->fprintf_func
) (info
->stream
, "0x%x", insn
);
688 info
->insn_type
= dis_noninsn
;
693 /* Disassemble an operand for a mips16 instruction. */
696 print_mips16_insn_arg (type
, op
, l
, use_extend
, extend
, memaddr
, info
)
698 const struct mips_opcode
*op
;
703 struct disassemble_info
*info
;
710 (*info
->fprintf_func
) (info
->stream
, "%c", type
);
715 (*info
->fprintf_func
) (info
->stream
, "$%s",
716 mips16_reg_names
[((l
>> MIPS16OP_SH_RY
)
717 & MIPS16OP_MASK_RY
)]);
722 (*info
->fprintf_func
) (info
->stream
, "$%s",
723 mips16_reg_names
[((l
>> MIPS16OP_SH_RX
)
724 & MIPS16OP_MASK_RX
)]);
728 (*info
->fprintf_func
) (info
->stream
, "$%s",
729 mips16_reg_names
[((l
>> MIPS16OP_SH_RZ
)
730 & MIPS16OP_MASK_RZ
)]);
734 (*info
->fprintf_func
) (info
->stream
, "$%s",
735 mips16_reg_names
[((l
>> MIPS16OP_SH_MOVE32Z
)
736 & MIPS16OP_MASK_MOVE32Z
)]);
740 (*info
->fprintf_func
) (info
->stream
, "$%s", reg_names
[0]);
744 (*info
->fprintf_func
) (info
->stream
, "$%s", reg_names
[29]);
748 (*info
->fprintf_func
) (info
->stream
, "$pc");
752 (*info
->fprintf_func
) (info
->stream
, "$%s", reg_names
[31]);
756 (*info
->fprintf_func
) (info
->stream
, "$%s",
757 reg_names
[((l
>> MIPS16OP_SH_REGR32
)
758 & MIPS16OP_MASK_REGR32
)]);
762 (*info
->fprintf_func
) (info
->stream
, "$%s",
763 reg_names
[MIPS16OP_EXTRACT_REG32R (l
)]);
789 int immed
, nbits
, shift
, signedp
, extbits
, pcrel
, extu
, branch
;
801 immed
= (l
>> MIPS16OP_SH_RZ
) & MIPS16OP_MASK_RZ
;
807 immed
= (l
>> MIPS16OP_SH_RX
) & MIPS16OP_MASK_RX
;
813 immed
= (l
>> MIPS16OP_SH_RZ
) & MIPS16OP_MASK_RZ
;
819 immed
= (l
>> MIPS16OP_SH_RX
) & MIPS16OP_MASK_RX
;
825 immed
= (l
>> MIPS16OP_SH_IMM4
) & MIPS16OP_MASK_IMM4
;
831 immed
= (l
>> MIPS16OP_SH_IMM5
) & MIPS16OP_MASK_IMM5
;
832 info
->insn_type
= dis_dref
;
838 immed
= (l
>> MIPS16OP_SH_IMM5
) & MIPS16OP_MASK_IMM5
;
839 info
->insn_type
= dis_dref
;
845 immed
= (l
>> MIPS16OP_SH_IMM5
) & MIPS16OP_MASK_IMM5
;
846 if ((op
->pinfo
& MIPS16_INSN_READ_PC
) == 0
847 && (op
->pinfo
& MIPS16_INSN_READ_SP
) == 0)
849 info
->insn_type
= dis_dref
;
856 immed
= (l
>> MIPS16OP_SH_IMM5
) & MIPS16OP_MASK_IMM5
;
857 info
->insn_type
= dis_dref
;
862 immed
= (l
>> MIPS16OP_SH_IMM5
) & MIPS16OP_MASK_IMM5
;
867 immed
= (l
>> MIPS16OP_SH_IMM6
) & MIPS16OP_MASK_IMM6
;
871 immed
= (l
>> MIPS16OP_SH_IMM8
) & MIPS16OP_MASK_IMM8
;
876 immed
= (l
>> MIPS16OP_SH_IMM8
) & MIPS16OP_MASK_IMM8
;
877 /* FIXME: This might be lw, or it might be addiu to $sp or
878 $pc. We assume it's load. */
879 info
->insn_type
= dis_dref
;
885 immed
= (l
>> MIPS16OP_SH_IMM8
) & MIPS16OP_MASK_IMM8
;
886 info
->insn_type
= dis_dref
;
891 immed
= (l
>> MIPS16OP_SH_IMM8
) & MIPS16OP_MASK_IMM8
;
896 immed
= (l
>> MIPS16OP_SH_IMM8
) & MIPS16OP_MASK_IMM8
;
902 immed
= (l
>> MIPS16OP_SH_IMM8
) & MIPS16OP_MASK_IMM8
;
907 immed
= (l
>> MIPS16OP_SH_IMM8
) & MIPS16OP_MASK_IMM8
;
911 info
->insn_type
= dis_condbranch
;
915 immed
= (l
>> MIPS16OP_SH_IMM11
) & MIPS16OP_MASK_IMM11
;
919 info
->insn_type
= dis_branch
;
924 immed
= (l
>> MIPS16OP_SH_IMM8
) & MIPS16OP_MASK_IMM8
;
926 /* FIXME: This can be lw or la. We assume it is lw. */
927 info
->insn_type
= dis_dref
;
933 immed
= (l
>> MIPS16OP_SH_IMM5
) & MIPS16OP_MASK_IMM5
;
935 info
->insn_type
= dis_dref
;
941 immed
= (l
>> MIPS16OP_SH_IMM5
) & MIPS16OP_MASK_IMM5
;
950 if (signedp
&& immed
>= (1 << (nbits
- 1)))
953 if ((type
== '<' || type
== '>' || type
== '[' || type
== ']')
960 immed
|= ((extend
& 0x1f) << 11) | (extend
& 0x7e0);
961 else if (extbits
== 15)
962 immed
|= ((extend
& 0xf) << 11) | (extend
& 0x7f0);
964 immed
= ((extend
>> 6) & 0x1f) | (extend
& 0x20);
965 immed
&= (1 << extbits
) - 1;
966 if (! extu
&& immed
>= (1 << (extbits
- 1)))
967 immed
-= 1 << extbits
;
971 (*info
->fprintf_func
) (info
->stream
, "%d", immed
);
980 baseaddr
= memaddr
+ 2;
983 baseaddr
= memaddr
- 2;
991 /* If this instruction is in the delay slot of a jr
992 instruction, the base address is the address of the
993 jr instruction. If it is in the delay slot of jalr
994 instruction, the base address is the address of the
995 jalr instruction. This test is unreliable: we have
996 no way of knowing whether the previous word is
997 instruction or data. */
998 status
= (*info
->read_memory_func
) (memaddr
- 4, buffer
, 2,
1001 && (((info
->endian
== BFD_ENDIAN_BIG
1002 ? bfd_getb16 (buffer
)
1003 : bfd_getl16 (buffer
))
1004 & 0xf800) == 0x1800))
1005 baseaddr
= memaddr
- 4;
1008 status
= (*info
->read_memory_func
) (memaddr
- 2, buffer
,
1011 && (((info
->endian
== BFD_ENDIAN_BIG
1012 ? bfd_getb16 (buffer
)
1013 : bfd_getl16 (buffer
))
1014 & 0xf81f) == 0xe800))
1015 baseaddr
= memaddr
- 2;
1018 val
= (baseaddr
& ~ ((1 << shift
) - 1)) + immed
;
1019 (*info
->print_address_func
) (val
, info
);
1028 l
= ((l
& 0x1f) << 23) | ((l
& 0x3e0) << 13) | (extend
<< 2);
1029 (*info
->print_address_func
) ((memaddr
& 0xf0000000) | l
, info
);
1030 info
->insn_type
= dis_jsr
;
1031 info
->target
= (memaddr
& 0xf0000000) | l
;
1032 info
->branch_delay_insns
= 1;
1038 int need_comma
, amask
, smask
;
1042 l
= (l
>> MIPS16OP_SH_IMM6
) & MIPS16OP_MASK_IMM6
;
1044 amask
= (l
>> 3) & 7;
1046 if (amask
> 0 && amask
< 5)
1048 (*info
->fprintf_func
) (info
->stream
, "$%s", reg_names
[4]);
1050 (*info
->fprintf_func
) (info
->stream
, "-$%s",
1051 reg_names
[amask
+ 3]);
1055 smask
= (l
>> 1) & 3;
1058 (*info
->fprintf_func
) (info
->stream
, "%s??",
1059 need_comma
? "," : "");
1064 (*info
->fprintf_func
) (info
->stream
, "%s$%s",
1065 need_comma
? "," : "",
1068 (*info
->fprintf_func
) (info
->stream
, "-$%s",
1069 reg_names
[smask
+ 15]);
1075 (*info
->fprintf_func
) (info
->stream
, "%s$%s",
1076 need_comma
? "," : "",
1081 if (amask
== 5 || amask
== 6)
1083 (*info
->fprintf_func
) (info
->stream
, "%s$f0",
1084 need_comma
? "," : "");
1086 (*info
->fprintf_func
) (info
->stream
, "-$f1");
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