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[deliverable/binutils-gdb.git] / opcodes / mips-dis.c
1 /* Print mips instructions for GDB, the GNU debugger, or for objdump.
2 Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
3 2000, 2001, 2002, 2003, 2005
4 Free Software Foundation, Inc.
5 Contributed by Nobuyuki Hikichi(hikichi@sra.co.jp).
6
7 This file is part of GDB, GAS, and the GNU binutils.
8
9 This program is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 2 of the License, or
12 (at your option) any later version.
13
14 This program is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
18
19 You should have received a copy of the GNU General Public License
20 along with this program; if not, write to the Free Software
21 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
22 MA 02110-1301, USA. */
23
24 #include "sysdep.h"
25 #include "dis-asm.h"
26 #include "libiberty.h"
27 #include "opcode/mips.h"
28 #include "opintl.h"
29
30 /* FIXME: These are needed to figure out if the code is mips16 or
31 not. The low bit of the address is often a good indicator. No
32 symbol table is available when this code runs out in an embedded
33 system as when it is used for disassembler support in a monitor. */
34
35 #if !defined(EMBEDDED_ENV)
36 #define SYMTAB_AVAILABLE 1
37 #include "elf-bfd.h"
38 #include "elf/mips.h"
39 #endif
40
41 /* Mips instructions are at maximum this many bytes long. */
42 #define INSNLEN 4
43
44 \f
45 /* FIXME: These should be shared with gdb somehow. */
46
47 struct mips_cp0sel_name
48 {
49 unsigned int cp0reg;
50 unsigned int sel;
51 const char * const name;
52 };
53
54 /* The mips16 registers. */
55 static const unsigned int mips16_to_32_reg_map[] =
56 {
57 16, 17, 2, 3, 4, 5, 6, 7
58 };
59
60 #define mips16_reg_names(rn) mips_gpr_names[mips16_to_32_reg_map[rn]]
61
62
63 static const char * const mips_gpr_names_numeric[32] =
64 {
65 "$0", "$1", "$2", "$3", "$4", "$5", "$6", "$7",
66 "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15",
67 "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23",
68 "$24", "$25", "$26", "$27", "$28", "$29", "$30", "$31"
69 };
70
71 static const char * const mips_gpr_names_oldabi[32] =
72 {
73 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
74 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7",
75 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
76 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra"
77 };
78
79 static const char * const mips_gpr_names_newabi[32] =
80 {
81 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
82 "a4", "a5", "a6", "a7", "t0", "t1", "t2", "t3",
83 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
84 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra"
85 };
86
87 static const char * const mips_fpr_names_numeric[32] =
88 {
89 "$f0", "$f1", "$f2", "$f3", "$f4", "$f5", "$f6", "$f7",
90 "$f8", "$f9", "$f10", "$f11", "$f12", "$f13", "$f14", "$f15",
91 "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23",
92 "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31"
93 };
94
95 static const char * const mips_fpr_names_32[32] =
96 {
97 "fv0", "fv0f", "fv1", "fv1f", "ft0", "ft0f", "ft1", "ft1f",
98 "ft2", "ft2f", "ft3", "ft3f", "fa0", "fa0f", "fa1", "fa1f",
99 "ft4", "ft4f", "ft5", "ft5f", "fs0", "fs0f", "fs1", "fs1f",
100 "fs2", "fs2f", "fs3", "fs3f", "fs4", "fs4f", "fs5", "fs5f"
101 };
102
103 static const char * const mips_fpr_names_n32[32] =
104 {
105 "fv0", "ft14", "fv1", "ft15", "ft0", "ft1", "ft2", "ft3",
106 "ft4", "ft5", "ft6", "ft7", "fa0", "fa1", "fa2", "fa3",
107 "fa4", "fa5", "fa6", "fa7", "fs0", "ft8", "fs1", "ft9",
108 "fs2", "ft10", "fs3", "ft11", "fs4", "ft12", "fs5", "ft13"
109 };
110
111 static const char * const mips_fpr_names_64[32] =
112 {
113 "fv0", "ft12", "fv1", "ft13", "ft0", "ft1", "ft2", "ft3",
114 "ft4", "ft5", "ft6", "ft7", "fa0", "fa1", "fa2", "fa3",
115 "fa4", "fa5", "fa6", "fa7", "ft8", "ft9", "ft10", "ft11",
116 "fs0", "fs1", "fs2", "fs3", "fs4", "fs5", "fs6", "fs7"
117 };
118
119 static const char * const mips_cp0_names_numeric[32] =
120 {
121 "$0", "$1", "$2", "$3", "$4", "$5", "$6", "$7",
122 "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15",
123 "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23",
124 "$24", "$25", "$26", "$27", "$28", "$29", "$30", "$31"
125 };
126
127 static const char * const mips_cp0_names_mips3264[32] =
128 {
129 "c0_index", "c0_random", "c0_entrylo0", "c0_entrylo1",
130 "c0_context", "c0_pagemask", "c0_wired", "$7",
131 "c0_badvaddr", "c0_count", "c0_entryhi", "c0_compare",
132 "c0_status", "c0_cause", "c0_epc", "c0_prid",
133 "c0_config", "c0_lladdr", "c0_watchlo", "c0_watchhi",
134 "c0_xcontext", "$21", "$22", "c0_debug",
135 "c0_depc", "c0_perfcnt", "c0_errctl", "c0_cacheerr",
136 "c0_taglo", "c0_taghi", "c0_errorepc", "c0_desave",
137 };
138
139 static const struct mips_cp0sel_name mips_cp0sel_names_mips3264[] =
140 {
141 { 16, 1, "c0_config1" },
142 { 16, 2, "c0_config2" },
143 { 16, 3, "c0_config3" },
144 { 18, 1, "c0_watchlo,1" },
145 { 18, 2, "c0_watchlo,2" },
146 { 18, 3, "c0_watchlo,3" },
147 { 18, 4, "c0_watchlo,4" },
148 { 18, 5, "c0_watchlo,5" },
149 { 18, 6, "c0_watchlo,6" },
150 { 18, 7, "c0_watchlo,7" },
151 { 19, 1, "c0_watchhi,1" },
152 { 19, 2, "c0_watchhi,2" },
153 { 19, 3, "c0_watchhi,3" },
154 { 19, 4, "c0_watchhi,4" },
155 { 19, 5, "c0_watchhi,5" },
156 { 19, 6, "c0_watchhi,6" },
157 { 19, 7, "c0_watchhi,7" },
158 { 25, 1, "c0_perfcnt,1" },
159 { 25, 2, "c0_perfcnt,2" },
160 { 25, 3, "c0_perfcnt,3" },
161 { 25, 4, "c0_perfcnt,4" },
162 { 25, 5, "c0_perfcnt,5" },
163 { 25, 6, "c0_perfcnt,6" },
164 { 25, 7, "c0_perfcnt,7" },
165 { 27, 1, "c0_cacheerr,1" },
166 { 27, 2, "c0_cacheerr,2" },
167 { 27, 3, "c0_cacheerr,3" },
168 { 28, 1, "c0_datalo" },
169 { 29, 1, "c0_datahi" }
170 };
171
172 static const char * const mips_cp0_names_mips3264r2[32] =
173 {
174 "c0_index", "c0_random", "c0_entrylo0", "c0_entrylo1",
175 "c0_context", "c0_pagemask", "c0_wired", "c0_hwrena",
176 "c0_badvaddr", "c0_count", "c0_entryhi", "c0_compare",
177 "c0_status", "c0_cause", "c0_epc", "c0_prid",
178 "c0_config", "c0_lladdr", "c0_watchlo", "c0_watchhi",
179 "c0_xcontext", "$21", "$22", "c0_debug",
180 "c0_depc", "c0_perfcnt", "c0_errctl", "c0_cacheerr",
181 "c0_taglo", "c0_taghi", "c0_errorepc", "c0_desave",
182 };
183
184 static const struct mips_cp0sel_name mips_cp0sel_names_mips3264r2[] =
185 {
186 { 4, 1, "c0_contextconfig" },
187 { 0, 1, "c0_mvpcontrol" },
188 { 0, 2, "c0_mvpconf0" },
189 { 0, 3, "c0_mvpconf1" },
190 { 1, 1, "c0_vpecontrol" },
191 { 1, 2, "c0_vpeconf0" },
192 { 1, 3, "c0_vpeconf1" },
193 { 1, 4, "c0_yqmask" },
194 { 1, 5, "c0_vpeschedule" },
195 { 1, 6, "c0_vpeschefback" },
196 { 2, 1, "c0_tcstatus" },
197 { 2, 2, "c0_tcbind" },
198 { 2, 3, "c0_tcrestart" },
199 { 2, 4, "c0_tchalt" },
200 { 2, 5, "c0_tccontext" },
201 { 2, 6, "c0_tcschedule" },
202 { 2, 7, "c0_tcschefback" },
203 { 5, 1, "c0_pagegrain" },
204 { 6, 1, "c0_srsconf0" },
205 { 6, 2, "c0_srsconf1" },
206 { 6, 3, "c0_srsconf2" },
207 { 6, 4, "c0_srsconf3" },
208 { 6, 5, "c0_srsconf4" },
209 { 12, 1, "c0_intctl" },
210 { 12, 2, "c0_srsctl" },
211 { 12, 3, "c0_srsmap" },
212 { 15, 1, "c0_ebase" },
213 { 16, 1, "c0_config1" },
214 { 16, 2, "c0_config2" },
215 { 16, 3, "c0_config3" },
216 { 18, 1, "c0_watchlo,1" },
217 { 18, 2, "c0_watchlo,2" },
218 { 18, 3, "c0_watchlo,3" },
219 { 18, 4, "c0_watchlo,4" },
220 { 18, 5, "c0_watchlo,5" },
221 { 18, 6, "c0_watchlo,6" },
222 { 18, 7, "c0_watchlo,7" },
223 { 19, 1, "c0_watchhi,1" },
224 { 19, 2, "c0_watchhi,2" },
225 { 19, 3, "c0_watchhi,3" },
226 { 19, 4, "c0_watchhi,4" },
227 { 19, 5, "c0_watchhi,5" },
228 { 19, 6, "c0_watchhi,6" },
229 { 19, 7, "c0_watchhi,7" },
230 { 23, 1, "c0_tracecontrol" },
231 { 23, 2, "c0_tracecontrol2" },
232 { 23, 3, "c0_usertracedata" },
233 { 23, 4, "c0_tracebpc" },
234 { 25, 1, "c0_perfcnt,1" },
235 { 25, 2, "c0_perfcnt,2" },
236 { 25, 3, "c0_perfcnt,3" },
237 { 25, 4, "c0_perfcnt,4" },
238 { 25, 5, "c0_perfcnt,5" },
239 { 25, 6, "c0_perfcnt,6" },
240 { 25, 7, "c0_perfcnt,7" },
241 { 27, 1, "c0_cacheerr,1" },
242 { 27, 2, "c0_cacheerr,2" },
243 { 27, 3, "c0_cacheerr,3" },
244 { 28, 1, "c0_datalo" },
245 { 28, 2, "c0_taglo1" },
246 { 28, 3, "c0_datalo1" },
247 { 28, 4, "c0_taglo2" },
248 { 28, 5, "c0_datalo2" },
249 { 28, 6, "c0_taglo3" },
250 { 28, 7, "c0_datalo3" },
251 { 29, 1, "c0_datahi" },
252 { 29, 2, "c0_taghi1" },
253 { 29, 3, "c0_datahi1" },
254 { 29, 4, "c0_taghi2" },
255 { 29, 5, "c0_datahi2" },
256 { 29, 6, "c0_taghi3" },
257 { 29, 7, "c0_datahi3" },
258 };
259
260 /* SB-1: MIPS64 (mips_cp0_names_mips3264) with minor mods. */
261 static const char * const mips_cp0_names_sb1[32] =
262 {
263 "c0_index", "c0_random", "c0_entrylo0", "c0_entrylo1",
264 "c0_context", "c0_pagemask", "c0_wired", "$7",
265 "c0_badvaddr", "c0_count", "c0_entryhi", "c0_compare",
266 "c0_status", "c0_cause", "c0_epc", "c0_prid",
267 "c0_config", "c0_lladdr", "c0_watchlo", "c0_watchhi",
268 "c0_xcontext", "$21", "$22", "c0_debug",
269 "c0_depc", "c0_perfcnt", "c0_errctl", "c0_cacheerr_i",
270 "c0_taglo_i", "c0_taghi_i", "c0_errorepc", "c0_desave",
271 };
272
273 static const struct mips_cp0sel_name mips_cp0sel_names_sb1[] =
274 {
275 { 16, 1, "c0_config1" },
276 { 18, 1, "c0_watchlo,1" },
277 { 19, 1, "c0_watchhi,1" },
278 { 22, 0, "c0_perftrace" },
279 { 23, 3, "c0_edebug" },
280 { 25, 1, "c0_perfcnt,1" },
281 { 25, 2, "c0_perfcnt,2" },
282 { 25, 3, "c0_perfcnt,3" },
283 { 25, 4, "c0_perfcnt,4" },
284 { 25, 5, "c0_perfcnt,5" },
285 { 25, 6, "c0_perfcnt,6" },
286 { 25, 7, "c0_perfcnt,7" },
287 { 26, 1, "c0_buserr_pa" },
288 { 27, 1, "c0_cacheerr_d" },
289 { 27, 3, "c0_cacheerr_d_pa" },
290 { 28, 1, "c0_datalo_i" },
291 { 28, 2, "c0_taglo_d" },
292 { 28, 3, "c0_datalo_d" },
293 { 29, 1, "c0_datahi_i" },
294 { 29, 2, "c0_taghi_d" },
295 { 29, 3, "c0_datahi_d" },
296 };
297
298 static const char * const mips_hwr_names_numeric[32] =
299 {
300 "$0", "$1", "$2", "$3", "$4", "$5", "$6", "$7",
301 "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15",
302 "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23",
303 "$24", "$25", "$26", "$27", "$28", "$29", "$30", "$31"
304 };
305
306 static const char * const mips_hwr_names_mips3264r2[32] =
307 {
308 "hwr_cpunum", "hwr_synci_step", "hwr_cc", "hwr_ccres",
309 "$4", "$5", "$6", "$7",
310 "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15",
311 "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23",
312 "$24", "$25", "$26", "$27", "$28", "$29", "$30", "$31"
313 };
314
315 struct mips_abi_choice
316 {
317 const char * name;
318 const char * const *gpr_names;
319 const char * const *fpr_names;
320 };
321
322 struct mips_abi_choice mips_abi_choices[] =
323 {
324 { "numeric", mips_gpr_names_numeric, mips_fpr_names_numeric },
325 { "32", mips_gpr_names_oldabi, mips_fpr_names_32 },
326 { "n32", mips_gpr_names_newabi, mips_fpr_names_n32 },
327 { "64", mips_gpr_names_newabi, mips_fpr_names_64 },
328 };
329
330 struct mips_arch_choice
331 {
332 const char *name;
333 int bfd_mach_valid;
334 unsigned long bfd_mach;
335 int processor;
336 int isa;
337 const char * const *cp0_names;
338 const struct mips_cp0sel_name *cp0sel_names;
339 unsigned int cp0sel_names_len;
340 const char * const *hwr_names;
341 };
342
343 const struct mips_arch_choice mips_arch_choices[] =
344 {
345 { "numeric", 0, 0, 0, 0,
346 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
347
348 { "r3000", 1, bfd_mach_mips3000, CPU_R3000, ISA_MIPS1,
349 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
350 { "r3900", 1, bfd_mach_mips3900, CPU_R3900, ISA_MIPS1,
351 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
352 { "r4000", 1, bfd_mach_mips4000, CPU_R4000, ISA_MIPS3,
353 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
354 { "r4010", 1, bfd_mach_mips4010, CPU_R4010, ISA_MIPS2,
355 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
356 { "vr4100", 1, bfd_mach_mips4100, CPU_VR4100, ISA_MIPS3,
357 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
358 { "vr4111", 1, bfd_mach_mips4111, CPU_R4111, ISA_MIPS3,
359 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
360 { "vr4120", 1, bfd_mach_mips4120, CPU_VR4120, ISA_MIPS3,
361 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
362 { "r4300", 1, bfd_mach_mips4300, CPU_R4300, ISA_MIPS3,
363 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
364 { "r4400", 1, bfd_mach_mips4400, CPU_R4400, ISA_MIPS3,
365 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
366 { "r4600", 1, bfd_mach_mips4600, CPU_R4600, ISA_MIPS3,
367 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
368 { "r4650", 1, bfd_mach_mips4650, CPU_R4650, ISA_MIPS3,
369 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
370 { "r5000", 1, bfd_mach_mips5000, CPU_R5000, ISA_MIPS4,
371 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
372 { "vr5400", 1, bfd_mach_mips5400, CPU_VR5400, ISA_MIPS4,
373 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
374 { "vr5500", 1, bfd_mach_mips5500, CPU_VR5500, ISA_MIPS4,
375 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
376 { "r6000", 1, bfd_mach_mips6000, CPU_R6000, ISA_MIPS2,
377 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
378 { "rm7000", 1, bfd_mach_mips7000, CPU_RM7000, ISA_MIPS4,
379 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
380 { "rm9000", 1, bfd_mach_mips7000, CPU_RM7000, ISA_MIPS4,
381 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
382 { "r8000", 1, bfd_mach_mips8000, CPU_R8000, ISA_MIPS4,
383 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
384 { "r10000", 1, bfd_mach_mips10000, CPU_R10000, ISA_MIPS4,
385 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
386 { "r12000", 1, bfd_mach_mips12000, CPU_R12000, ISA_MIPS4,
387 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
388 { "mips5", 1, bfd_mach_mips5, CPU_MIPS5, ISA_MIPS5,
389 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
390
391 /* For stock MIPS32, disassemble all applicable MIPS-specified ASEs.
392 Note that MIPS-3D and MDMX are not applicable to MIPS32. (See
393 _MIPS32 Architecture For Programmers Volume I: Introduction to the
394 MIPS32 Architecture_ (MIPS Document Number MD00082, Revision 0.95),
395 page 1. */
396 { "mips32", 1, bfd_mach_mipsisa32, CPU_MIPS32,
397 ISA_MIPS32 | INSN_MIPS16 | INSN_DSP,
398 mips_cp0_names_mips3264,
399 mips_cp0sel_names_mips3264, ARRAY_SIZE (mips_cp0sel_names_mips3264),
400 mips_hwr_names_numeric },
401
402 { "mips32r2", 1, bfd_mach_mipsisa32r2, CPU_MIPS32R2,
403 ISA_MIPS32R2 | INSN_MIPS16 | INSN_DSP | INSN_MT,
404 mips_cp0_names_mips3264r2,
405 mips_cp0sel_names_mips3264r2, ARRAY_SIZE (mips_cp0sel_names_mips3264r2),
406 mips_hwr_names_mips3264r2 },
407
408 /* For stock MIPS64, disassemble all applicable MIPS-specified ASEs. */
409 { "mips64", 1, bfd_mach_mipsisa64, CPU_MIPS64,
410 ISA_MIPS64 | INSN_MIPS16 | INSN_MIPS3D | INSN_MDMX | INSN_DSP,
411 mips_cp0_names_mips3264,
412 mips_cp0sel_names_mips3264, ARRAY_SIZE (mips_cp0sel_names_mips3264),
413 mips_hwr_names_numeric },
414
415 { "mips64r2", 1, bfd_mach_mipsisa64r2, CPU_MIPS64R2,
416 ISA_MIPS64R2 | INSN_MIPS16 | INSN_MIPS3D | INSN_MDMX | INSN_DSP,
417 mips_cp0_names_mips3264r2,
418 mips_cp0sel_names_mips3264r2, ARRAY_SIZE (mips_cp0sel_names_mips3264r2),
419 mips_hwr_names_mips3264r2 },
420
421 { "sb1", 1, bfd_mach_mips_sb1, CPU_SB1,
422 ISA_MIPS64 | INSN_MIPS3D | INSN_SB1,
423 mips_cp0_names_sb1,
424 mips_cp0sel_names_sb1, ARRAY_SIZE (mips_cp0sel_names_sb1),
425 mips_hwr_names_numeric },
426
427 /* This entry, mips16, is here only for ISA/processor selection; do
428 not print its name. */
429 { "", 1, bfd_mach_mips16, CPU_MIPS16, ISA_MIPS3 | INSN_MIPS16,
430 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
431 };
432
433 /* ISA and processor type to disassemble for, and register names to use.
434 set_default_mips_dis_options and parse_mips_dis_options fill in these
435 values. */
436 static int mips_processor;
437 static int mips_isa;
438 static const char * const *mips_gpr_names;
439 static const char * const *mips_fpr_names;
440 static const char * const *mips_cp0_names;
441 static const struct mips_cp0sel_name *mips_cp0sel_names;
442 static int mips_cp0sel_names_len;
443 static const char * const *mips_hwr_names;
444
445 /* Other options */
446 static int no_aliases; /* If set disassemble as most general inst. */
447 \f
448 static const struct mips_abi_choice *
449 choose_abi_by_name (const char *name, unsigned int namelen)
450 {
451 const struct mips_abi_choice *c;
452 unsigned int i;
453
454 for (i = 0, c = NULL; i < ARRAY_SIZE (mips_abi_choices) && c == NULL; i++)
455 if (strncmp (mips_abi_choices[i].name, name, namelen) == 0
456 && strlen (mips_abi_choices[i].name) == namelen)
457 c = &mips_abi_choices[i];
458
459 return c;
460 }
461
462 static const struct mips_arch_choice *
463 choose_arch_by_name (const char *name, unsigned int namelen)
464 {
465 const struct mips_arch_choice *c = NULL;
466 unsigned int i;
467
468 for (i = 0, c = NULL; i < ARRAY_SIZE (mips_arch_choices) && c == NULL; i++)
469 if (strncmp (mips_arch_choices[i].name, name, namelen) == 0
470 && strlen (mips_arch_choices[i].name) == namelen)
471 c = &mips_arch_choices[i];
472
473 return c;
474 }
475
476 static const struct mips_arch_choice *
477 choose_arch_by_number (unsigned long mach)
478 {
479 static unsigned long hint_bfd_mach;
480 static const struct mips_arch_choice *hint_arch_choice;
481 const struct mips_arch_choice *c;
482 unsigned int i;
483
484 /* We optimize this because even if the user specifies no
485 flags, this will be done for every instruction! */
486 if (hint_bfd_mach == mach
487 && hint_arch_choice != NULL
488 && hint_arch_choice->bfd_mach == hint_bfd_mach)
489 return hint_arch_choice;
490
491 for (i = 0, c = NULL; i < ARRAY_SIZE (mips_arch_choices) && c == NULL; i++)
492 {
493 if (mips_arch_choices[i].bfd_mach_valid
494 && mips_arch_choices[i].bfd_mach == mach)
495 {
496 c = &mips_arch_choices[i];
497 hint_bfd_mach = mach;
498 hint_arch_choice = c;
499 }
500 }
501 return c;
502 }
503
504 /* Check if the object uses NewABI conventions. */
505
506 static int
507 is_newabi (Elf_Internal_Ehdr *header)
508 {
509 /* There are no old-style ABIs which use 64-bit ELF. */
510 if (header->e_ident[EI_CLASS] == ELFCLASS64)
511 return 1;
512
513 /* If a 32-bit ELF file, n32 is a new-style ABI. */
514 if ((header->e_flags & EF_MIPS_ABI2) != 0)
515 return 1;
516
517 return 0;
518 }
519
520 static void
521 set_default_mips_dis_options (struct disassemble_info *info)
522 {
523 const struct mips_arch_choice *chosen_arch;
524
525 /* Defaults: mipsIII/r3000 (?!), (o)32-style ("oldabi") GPR names,
526 and numeric FPR, CP0 register, and HWR names. */
527 mips_isa = ISA_MIPS3;
528 mips_processor = CPU_R3000;
529 mips_gpr_names = mips_gpr_names_oldabi;
530 mips_fpr_names = mips_fpr_names_numeric;
531 mips_cp0_names = mips_cp0_names_numeric;
532 mips_cp0sel_names = NULL;
533 mips_cp0sel_names_len = 0;
534 mips_hwr_names = mips_hwr_names_numeric;
535 no_aliases = 0;
536
537 /* If an ELF "newabi" binary, use the n32/(n)64 GPR names. */
538 if (info->flavour == bfd_target_elf_flavour && info->section != NULL)
539 {
540 Elf_Internal_Ehdr *header;
541
542 header = elf_elfheader (info->section->owner);
543 if (is_newabi (header))
544 mips_gpr_names = mips_gpr_names_newabi;
545 }
546
547 /* Set ISA, architecture, and cp0 register names as best we can. */
548 #if ! SYMTAB_AVAILABLE
549 /* This is running out on a target machine, not in a host tool.
550 FIXME: Where does mips_target_info come from? */
551 target_processor = mips_target_info.processor;
552 mips_isa = mips_target_info.isa;
553 #else
554 chosen_arch = choose_arch_by_number (info->mach);
555 if (chosen_arch != NULL)
556 {
557 mips_processor = chosen_arch->processor;
558 mips_isa = chosen_arch->isa;
559 mips_cp0_names = chosen_arch->cp0_names;
560 mips_cp0sel_names = chosen_arch->cp0sel_names;
561 mips_cp0sel_names_len = chosen_arch->cp0sel_names_len;
562 mips_hwr_names = chosen_arch->hwr_names;
563 }
564 #endif
565 }
566
567 static void
568 parse_mips_dis_option (const char *option, unsigned int len)
569 {
570 unsigned int i, optionlen, vallen;
571 const char *val;
572 const struct mips_abi_choice *chosen_abi;
573 const struct mips_arch_choice *chosen_arch;
574
575 /* Try to match options that are simple flags */
576 if (strncmp (option, "no-aliases", 10) == 0)
577 {
578 no_aliases = 1;
579 return;
580 }
581
582 /* Look for the = that delimits the end of the option name. */
583 for (i = 0; i < len; i++)
584 if (option[i] == '=')
585 break;
586
587 if (i == 0) /* Invalid option: no name before '='. */
588 return;
589 if (i == len) /* Invalid option: no '='. */
590 return;
591 if (i == (len - 1)) /* Invalid option: no value after '='. */
592 return;
593
594 optionlen = i;
595 val = option + (optionlen + 1);
596 vallen = len - (optionlen + 1);
597
598 if (strncmp ("gpr-names", option, optionlen) == 0
599 && strlen ("gpr-names") == optionlen)
600 {
601 chosen_abi = choose_abi_by_name (val, vallen);
602 if (chosen_abi != NULL)
603 mips_gpr_names = chosen_abi->gpr_names;
604 return;
605 }
606
607 if (strncmp ("fpr-names", option, optionlen) == 0
608 && strlen ("fpr-names") == optionlen)
609 {
610 chosen_abi = choose_abi_by_name (val, vallen);
611 if (chosen_abi != NULL)
612 mips_fpr_names = chosen_abi->fpr_names;
613 return;
614 }
615
616 if (strncmp ("cp0-names", option, optionlen) == 0
617 && strlen ("cp0-names") == optionlen)
618 {
619 chosen_arch = choose_arch_by_name (val, vallen);
620 if (chosen_arch != NULL)
621 {
622 mips_cp0_names = chosen_arch->cp0_names;
623 mips_cp0sel_names = chosen_arch->cp0sel_names;
624 mips_cp0sel_names_len = chosen_arch->cp0sel_names_len;
625 }
626 return;
627 }
628
629 if (strncmp ("hwr-names", option, optionlen) == 0
630 && strlen ("hwr-names") == optionlen)
631 {
632 chosen_arch = choose_arch_by_name (val, vallen);
633 if (chosen_arch != NULL)
634 mips_hwr_names = chosen_arch->hwr_names;
635 return;
636 }
637
638 if (strncmp ("reg-names", option, optionlen) == 0
639 && strlen ("reg-names") == optionlen)
640 {
641 /* We check both ABI and ARCH here unconditionally, so
642 that "numeric" will do the desirable thing: select
643 numeric register names for all registers. Other than
644 that, a given name probably won't match both. */
645 chosen_abi = choose_abi_by_name (val, vallen);
646 if (chosen_abi != NULL)
647 {
648 mips_gpr_names = chosen_abi->gpr_names;
649 mips_fpr_names = chosen_abi->fpr_names;
650 }
651 chosen_arch = choose_arch_by_name (val, vallen);
652 if (chosen_arch != NULL)
653 {
654 mips_cp0_names = chosen_arch->cp0_names;
655 mips_cp0sel_names = chosen_arch->cp0sel_names;
656 mips_cp0sel_names_len = chosen_arch->cp0sel_names_len;
657 mips_hwr_names = chosen_arch->hwr_names;
658 }
659 return;
660 }
661
662 /* Invalid option. */
663 }
664
665 static void
666 parse_mips_dis_options (const char *options)
667 {
668 const char *option_end;
669
670 if (options == NULL)
671 return;
672
673 while (*options != '\0')
674 {
675 /* Skip empty options. */
676 if (*options == ',')
677 {
678 options++;
679 continue;
680 }
681
682 /* We know that *options is neither NUL or a comma. */
683 option_end = options + 1;
684 while (*option_end != ',' && *option_end != '\0')
685 option_end++;
686
687 parse_mips_dis_option (options, option_end - options);
688
689 /* Go on to the next one. If option_end points to a comma, it
690 will be skipped above. */
691 options = option_end;
692 }
693 }
694
695 static const struct mips_cp0sel_name *
696 lookup_mips_cp0sel_name (const struct mips_cp0sel_name *names,
697 unsigned int len,
698 unsigned int cp0reg,
699 unsigned int sel)
700 {
701 unsigned int i;
702
703 for (i = 0; i < len; i++)
704 if (names[i].cp0reg == cp0reg && names[i].sel == sel)
705 return &names[i];
706 return NULL;
707 }
708 \f
709 /* Print insn arguments for 32/64-bit code. */
710
711 static void
712 print_insn_args (const char *d,
713 register unsigned long int l,
714 bfd_vma pc,
715 struct disassemble_info *info,
716 const struct mips_opcode *opp)
717 {
718 int op, delta;
719 unsigned int lsb, msb, msbd;
720
721 lsb = 0;
722
723 for (; *d != '\0'; d++)
724 {
725 switch (*d)
726 {
727 case ',':
728 case '(':
729 case ')':
730 case '[':
731 case ']':
732 (*info->fprintf_func) (info->stream, "%c", *d);
733 break;
734
735 case '+':
736 /* Extension character; switch for second char. */
737 d++;
738 switch (*d)
739 {
740 case '\0':
741 /* xgettext:c-format */
742 (*info->fprintf_func) (info->stream,
743 _("# internal error, incomplete extension sequence (+)"));
744 return;
745
746 case 'A':
747 lsb = (l >> OP_SH_SHAMT) & OP_MASK_SHAMT;
748 (*info->fprintf_func) (info->stream, "0x%x", lsb);
749 break;
750
751 case 'B':
752 msb = (l >> OP_SH_INSMSB) & OP_MASK_INSMSB;
753 (*info->fprintf_func) (info->stream, "0x%x", msb - lsb + 1);
754 break;
755
756 case '1':
757 (*info->fprintf_func) (info->stream, "0x%lx",
758 (l >> OP_SH_UDI1) & OP_MASK_UDI1);
759 break;
760
761 case '2':
762 (*info->fprintf_func) (info->stream, "0x%lx",
763 (l >> OP_SH_UDI2) & OP_MASK_UDI2);
764 break;
765
766 case '3':
767 (*info->fprintf_func) (info->stream, "0x%lx",
768 (l >> OP_SH_UDI3) & OP_MASK_UDI3);
769 break;
770
771 case '4':
772 (*info->fprintf_func) (info->stream, "0x%lx",
773 (l >> OP_SH_UDI4) & OP_MASK_UDI4);
774 break;
775
776 case 'C':
777 case 'H':
778 msbd = (l >> OP_SH_EXTMSBD) & OP_MASK_EXTMSBD;
779 (*info->fprintf_func) (info->stream, "0x%x", msbd + 1);
780 break;
781
782 case 'D':
783 {
784 const struct mips_cp0sel_name *n;
785 unsigned int cp0reg, sel;
786
787 cp0reg = (l >> OP_SH_RD) & OP_MASK_RD;
788 sel = (l >> OP_SH_SEL) & OP_MASK_SEL;
789
790 /* CP0 register including 'sel' code for mtcN (et al.), to be
791 printed textually if known. If not known, print both
792 CP0 register name and sel numerically since CP0 register
793 with sel 0 may have a name unrelated to register being
794 printed. */
795 n = lookup_mips_cp0sel_name(mips_cp0sel_names,
796 mips_cp0sel_names_len, cp0reg, sel);
797 if (n != NULL)
798 (*info->fprintf_func) (info->stream, "%s", n->name);
799 else
800 (*info->fprintf_func) (info->stream, "$%d,%d", cp0reg, sel);
801 break;
802 }
803
804 case 'E':
805 lsb = ((l >> OP_SH_SHAMT) & OP_MASK_SHAMT) + 32;
806 (*info->fprintf_func) (info->stream, "0x%x", lsb);
807 break;
808
809 case 'F':
810 msb = ((l >> OP_SH_INSMSB) & OP_MASK_INSMSB) + 32;
811 (*info->fprintf_func) (info->stream, "0x%x", msb - lsb + 1);
812 break;
813
814 case 'G':
815 msbd = ((l >> OP_SH_EXTMSBD) & OP_MASK_EXTMSBD) + 32;
816 (*info->fprintf_func) (info->stream, "0x%x", msbd + 1);
817 break;
818
819 case 't': /* Coprocessor 0 reg name */
820 (*info->fprintf_func) (info->stream, "%s",
821 mips_cp0_names[(l >> OP_SH_RT) &
822 OP_MASK_RT]);
823 break;
824
825 case 'T': /* Coprocessor 0 reg name */
826 {
827 const struct mips_cp0sel_name *n;
828 unsigned int cp0reg, sel;
829
830 cp0reg = (l >> OP_SH_RT) & OP_MASK_RT;
831 sel = (l >> OP_SH_SEL) & OP_MASK_SEL;
832
833 /* CP0 register including 'sel' code for mftc0, to be
834 printed textually if known. If not known, print both
835 CP0 register name and sel numerically since CP0 register
836 with sel 0 may have a name unrelated to register being
837 printed. */
838 n = lookup_mips_cp0sel_name(mips_cp0sel_names,
839 mips_cp0sel_names_len, cp0reg, sel);
840 if (n != NULL)
841 (*info->fprintf_func) (info->stream, "%s", n->name);
842 else
843 (*info->fprintf_func) (info->stream, "$%d,%d", cp0reg, sel);
844 break;
845 }
846
847 default:
848 /* xgettext:c-format */
849 (*info->fprintf_func) (info->stream,
850 _("# internal error, undefined extension sequence (+%c)"),
851 *d);
852 return;
853 }
854 break;
855
856 case '3':
857 (*info->fprintf_func) (info->stream, "0x%lx",
858 (l >> OP_SH_SA3) & OP_MASK_SA3);
859 break;
860
861 case '4':
862 (*info->fprintf_func) (info->stream, "0x%lx",
863 (l >> OP_SH_SA4) & OP_MASK_SA4);
864 break;
865
866 case '5':
867 (*info->fprintf_func) (info->stream, "0x%lx",
868 (l >> OP_SH_IMM8) & OP_MASK_IMM8);
869 break;
870
871 case '6':
872 (*info->fprintf_func) (info->stream, "0x%lx",
873 (l >> OP_SH_RS) & OP_MASK_RS);
874 break;
875
876 case '7':
877 (*info->fprintf_func) (info->stream, "$ac%ld",
878 (l >> OP_SH_DSPACC) & OP_MASK_DSPACC);
879 break;
880
881 case '8':
882 (*info->fprintf_func) (info->stream, "0x%lx",
883 (l >> OP_SH_WRDSP) & OP_MASK_WRDSP);
884 break;
885
886 case '9':
887 (*info->fprintf_func) (info->stream, "$ac%ld",
888 (l >> OP_SH_DSPACC_S) & OP_MASK_DSPACC_S);
889 break;
890
891 case '0': /* dsp 6-bit signed immediate in bit 20 */
892 delta = ((l >> OP_SH_DSPSFT) & OP_MASK_DSPSFT);
893 if (delta & 0x20) /* test sign bit */
894 delta |= ~OP_MASK_DSPSFT;
895 (*info->fprintf_func) (info->stream, "%d", delta);
896 break;
897
898 case ':': /* dsp 7-bit signed immediate in bit 19 */
899 delta = ((l >> OP_SH_DSPSFT_7) & OP_MASK_DSPSFT_7);
900 if (delta & 0x40) /* test sign bit */
901 delta |= ~OP_MASK_DSPSFT_7;
902 (*info->fprintf_func) (info->stream, "%d", delta);
903 break;
904
905 case '\'':
906 (*info->fprintf_func) (info->stream, "0x%lx",
907 (l >> OP_SH_RDDSP) & OP_MASK_RDDSP);
908 break;
909
910 case '@': /* dsp 10-bit signed immediate in bit 16 */
911 delta = ((l >> OP_SH_IMM10) & OP_MASK_IMM10);
912 if (delta & 0x200) /* test sign bit */
913 delta |= ~OP_MASK_IMM10;
914 (*info->fprintf_func) (info->stream, "%d", delta);
915 break;
916
917 case '!':
918 (*info->fprintf_func) (info->stream, "%ld",
919 (l >> OP_SH_MT_U) & OP_MASK_MT_U);
920 break;
921
922 case '$':
923 (*info->fprintf_func) (info->stream, "%ld",
924 (l >> OP_SH_MT_H) & OP_MASK_MT_H);
925 break;
926
927 case '*':
928 (*info->fprintf_func) (info->stream, "$ac%ld",
929 (l >> OP_SH_MTACC_T) & OP_MASK_MTACC_T);
930 break;
931
932 case '&':
933 (*info->fprintf_func) (info->stream, "$ac%ld",
934 (l >> OP_SH_MTACC_D) & OP_MASK_MTACC_D);
935 break;
936
937 case 'g':
938 /* Coprocessor register for CTTC1, MTTC2, MTHC2, CTTC2. */
939 (*info->fprintf_func) (info->stream, "$%ld",
940 (l >> OP_SH_RD) & OP_MASK_RD);
941 break;
942
943 case 's':
944 case 'b':
945 case 'r':
946 case 'v':
947 (*info->fprintf_func) (info->stream, "%s",
948 mips_gpr_names[(l >> OP_SH_RS) & OP_MASK_RS]);
949 break;
950
951 case 't':
952 case 'w':
953 (*info->fprintf_func) (info->stream, "%s",
954 mips_gpr_names[(l >> OP_SH_RT) & OP_MASK_RT]);
955 break;
956
957 case 'i':
958 case 'u':
959 (*info->fprintf_func) (info->stream, "0x%lx",
960 (l >> OP_SH_IMMEDIATE) & OP_MASK_IMMEDIATE);
961 break;
962
963 case 'j': /* Same as i, but sign-extended. */
964 case 'o':
965 delta = (l >> OP_SH_DELTA) & OP_MASK_DELTA;
966 if (delta & 0x8000)
967 delta |= ~0xffff;
968 (*info->fprintf_func) (info->stream, "%d",
969 delta);
970 break;
971
972 case 'h':
973 (*info->fprintf_func) (info->stream, "0x%x",
974 (unsigned int) ((l >> OP_SH_PREFX)
975 & OP_MASK_PREFX));
976 break;
977
978 case 'k':
979 (*info->fprintf_func) (info->stream, "0x%x",
980 (unsigned int) ((l >> OP_SH_CACHE)
981 & OP_MASK_CACHE));
982 break;
983
984 case 'a':
985 info->target = (((pc + 4) & ~(bfd_vma) 0x0fffffff)
986 | (((l >> OP_SH_TARGET) & OP_MASK_TARGET) << 2));
987 (*info->print_address_func) (info->target, info);
988 break;
989
990 case 'p':
991 /* Sign extend the displacement. */
992 delta = (l >> OP_SH_DELTA) & OP_MASK_DELTA;
993 if (delta & 0x8000)
994 delta |= ~0xffff;
995 info->target = (delta << 2) + pc + INSNLEN;
996 (*info->print_address_func) (info->target, info);
997 break;
998
999 case 'd':
1000 (*info->fprintf_func) (info->stream, "%s",
1001 mips_gpr_names[(l >> OP_SH_RD) & OP_MASK_RD]);
1002 break;
1003
1004 case 'U':
1005 {
1006 /* First check for both rd and rt being equal. */
1007 unsigned int reg = (l >> OP_SH_RD) & OP_MASK_RD;
1008 if (reg == ((l >> OP_SH_RT) & OP_MASK_RT))
1009 (*info->fprintf_func) (info->stream, "%s",
1010 mips_gpr_names[reg]);
1011 else
1012 {
1013 /* If one is zero use the other. */
1014 if (reg == 0)
1015 (*info->fprintf_func) (info->stream, "%s",
1016 mips_gpr_names[(l >> OP_SH_RT) & OP_MASK_RT]);
1017 else if (((l >> OP_SH_RT) & OP_MASK_RT) == 0)
1018 (*info->fprintf_func) (info->stream, "%s",
1019 mips_gpr_names[reg]);
1020 else /* Bogus, result depends on processor. */
1021 (*info->fprintf_func) (info->stream, "%s or %s",
1022 mips_gpr_names[reg],
1023 mips_gpr_names[(l >> OP_SH_RT) & OP_MASK_RT]);
1024 }
1025 }
1026 break;
1027
1028 case 'z':
1029 (*info->fprintf_func) (info->stream, "%s", mips_gpr_names[0]);
1030 break;
1031
1032 case '<':
1033 (*info->fprintf_func) (info->stream, "0x%lx",
1034 (l >> OP_SH_SHAMT) & OP_MASK_SHAMT);
1035 break;
1036
1037 case 'c':
1038 (*info->fprintf_func) (info->stream, "0x%lx",
1039 (l >> OP_SH_CODE) & OP_MASK_CODE);
1040 break;
1041
1042 case 'q':
1043 (*info->fprintf_func) (info->stream, "0x%lx",
1044 (l >> OP_SH_CODE2) & OP_MASK_CODE2);
1045 break;
1046
1047 case 'C':
1048 (*info->fprintf_func) (info->stream, "0x%lx",
1049 (l >> OP_SH_COPZ) & OP_MASK_COPZ);
1050 break;
1051
1052 case 'B':
1053 (*info->fprintf_func) (info->stream, "0x%lx",
1054
1055 (l >> OP_SH_CODE20) & OP_MASK_CODE20);
1056 break;
1057
1058 case 'J':
1059 (*info->fprintf_func) (info->stream, "0x%lx",
1060 (l >> OP_SH_CODE19) & OP_MASK_CODE19);
1061 break;
1062
1063 case 'S':
1064 case 'V':
1065 (*info->fprintf_func) (info->stream, "%s",
1066 mips_fpr_names[(l >> OP_SH_FS) & OP_MASK_FS]);
1067 break;
1068
1069 case 'T':
1070 case 'W':
1071 (*info->fprintf_func) (info->stream, "%s",
1072 mips_fpr_names[(l >> OP_SH_FT) & OP_MASK_FT]);
1073 break;
1074
1075 case 'D':
1076 (*info->fprintf_func) (info->stream, "%s",
1077 mips_fpr_names[(l >> OP_SH_FD) & OP_MASK_FD]);
1078 break;
1079
1080 case 'R':
1081 (*info->fprintf_func) (info->stream, "%s",
1082 mips_fpr_names[(l >> OP_SH_FR) & OP_MASK_FR]);
1083 break;
1084
1085 case 'E':
1086 /* Coprocessor register for lwcN instructions, et al.
1087
1088 Note that there is no load/store cp0 instructions, and
1089 that FPU (cp1) instructions disassemble this field using
1090 'T' format. Therefore, until we gain understanding of
1091 cp2 register names, we can simply print the register
1092 numbers. */
1093 (*info->fprintf_func) (info->stream, "$%ld",
1094 (l >> OP_SH_RT) & OP_MASK_RT);
1095 break;
1096
1097 case 'G':
1098 /* Coprocessor register for mtcN instructions, et al. Note
1099 that FPU (cp1) instructions disassemble this field using
1100 'S' format. Therefore, we only need to worry about cp0,
1101 cp2, and cp3. */
1102 op = (l >> OP_SH_OP) & OP_MASK_OP;
1103 if (op == OP_OP_COP0)
1104 (*info->fprintf_func) (info->stream, "%s",
1105 mips_cp0_names[(l >> OP_SH_RD) & OP_MASK_RD]);
1106 else
1107 (*info->fprintf_func) (info->stream, "$%ld",
1108 (l >> OP_SH_RD) & OP_MASK_RD);
1109 break;
1110
1111 case 'K':
1112 (*info->fprintf_func) (info->stream, "%s",
1113 mips_hwr_names[(l >> OP_SH_RD) & OP_MASK_RD]);
1114 break;
1115
1116 case 'N':
1117 (*info->fprintf_func) (info->stream,
1118 ((opp->pinfo & (FP_D | FP_S)) != 0
1119 ? "$fcc%ld" : "$cc%ld"),
1120 (l >> OP_SH_BCC) & OP_MASK_BCC);
1121 break;
1122
1123 case 'M':
1124 (*info->fprintf_func) (info->stream, "$fcc%ld",
1125 (l >> OP_SH_CCC) & OP_MASK_CCC);
1126 break;
1127
1128 case 'P':
1129 (*info->fprintf_func) (info->stream, "%ld",
1130 (l >> OP_SH_PERFREG) & OP_MASK_PERFREG);
1131 break;
1132
1133 case 'e':
1134 (*info->fprintf_func) (info->stream, "%ld",
1135 (l >> OP_SH_VECBYTE) & OP_MASK_VECBYTE);
1136 break;
1137
1138 case '%':
1139 (*info->fprintf_func) (info->stream, "%ld",
1140 (l >> OP_SH_VECALIGN) & OP_MASK_VECALIGN);
1141 break;
1142
1143 case 'H':
1144 (*info->fprintf_func) (info->stream, "%ld",
1145 (l >> OP_SH_SEL) & OP_MASK_SEL);
1146 break;
1147
1148 case 'O':
1149 (*info->fprintf_func) (info->stream, "%ld",
1150 (l >> OP_SH_ALN) & OP_MASK_ALN);
1151 break;
1152
1153 case 'Q':
1154 {
1155 unsigned int vsel = (l >> OP_SH_VSEL) & OP_MASK_VSEL;
1156
1157 if ((vsel & 0x10) == 0)
1158 {
1159 int fmt;
1160
1161 vsel &= 0x0f;
1162 for (fmt = 0; fmt < 3; fmt++, vsel >>= 1)
1163 if ((vsel & 1) == 0)
1164 break;
1165 (*info->fprintf_func) (info->stream, "$v%ld[%d]",
1166 (l >> OP_SH_FT) & OP_MASK_FT,
1167 vsel >> 1);
1168 }
1169 else if ((vsel & 0x08) == 0)
1170 {
1171 (*info->fprintf_func) (info->stream, "$v%ld",
1172 (l >> OP_SH_FT) & OP_MASK_FT);
1173 }
1174 else
1175 {
1176 (*info->fprintf_func) (info->stream, "0x%lx",
1177 (l >> OP_SH_FT) & OP_MASK_FT);
1178 }
1179 }
1180 break;
1181
1182 case 'X':
1183 (*info->fprintf_func) (info->stream, "$v%ld",
1184 (l >> OP_SH_FD) & OP_MASK_FD);
1185 break;
1186
1187 case 'Y':
1188 (*info->fprintf_func) (info->stream, "$v%ld",
1189 (l >> OP_SH_FS) & OP_MASK_FS);
1190 break;
1191
1192 case 'Z':
1193 (*info->fprintf_func) (info->stream, "$v%ld",
1194 (l >> OP_SH_FT) & OP_MASK_FT);
1195 break;
1196
1197 default:
1198 /* xgettext:c-format */
1199 (*info->fprintf_func) (info->stream,
1200 _("# internal error, undefined modifier(%c)"),
1201 *d);
1202 return;
1203 }
1204 }
1205 }
1206 \f
1207 /* Print the mips instruction at address MEMADDR in debugged memory,
1208 on using INFO. Returns length of the instruction, in bytes, which is
1209 always INSNLEN. BIGENDIAN must be 1 if this is big-endian code, 0 if
1210 this is little-endian code. */
1211
1212 static int
1213 print_insn_mips (bfd_vma memaddr,
1214 unsigned long int word,
1215 struct disassemble_info *info)
1216 {
1217 const struct mips_opcode *op;
1218 static bfd_boolean init = 0;
1219 static const struct mips_opcode *mips_hash[OP_MASK_OP + 1];
1220
1221 /* Build a hash table to shorten the search time. */
1222 if (! init)
1223 {
1224 unsigned int i;
1225
1226 for (i = 0; i <= OP_MASK_OP; i++)
1227 {
1228 for (op = mips_opcodes; op < &mips_opcodes[NUMOPCODES]; op++)
1229 {
1230 if (op->pinfo == INSN_MACRO
1231 || (no_aliases && (op->pinfo2 & INSN2_ALIAS)))
1232 continue;
1233 if (i == ((op->match >> OP_SH_OP) & OP_MASK_OP))
1234 {
1235 mips_hash[i] = op;
1236 break;
1237 }
1238 }
1239 }
1240
1241 init = 1;
1242 }
1243
1244 info->bytes_per_chunk = INSNLEN;
1245 info->display_endian = info->endian;
1246 info->insn_info_valid = 1;
1247 info->branch_delay_insns = 0;
1248 info->data_size = 0;
1249 info->insn_type = dis_nonbranch;
1250 info->target = 0;
1251 info->target2 = 0;
1252
1253 op = mips_hash[(word >> OP_SH_OP) & OP_MASK_OP];
1254 if (op != NULL)
1255 {
1256 for (; op < &mips_opcodes[NUMOPCODES]; op++)
1257 {
1258 if (op->pinfo != INSN_MACRO
1259 && !(no_aliases && (op->pinfo2 & INSN2_ALIAS))
1260 && (word & op->mask) == op->match)
1261 {
1262 const char *d;
1263
1264 /* We always allow to disassemble the jalx instruction. */
1265 if (! OPCODE_IS_MEMBER (op, mips_isa, mips_processor)
1266 && strcmp (op->name, "jalx"))
1267 continue;
1268
1269 /* Figure out instruction type and branch delay information. */
1270 if ((op->pinfo & INSN_UNCOND_BRANCH_DELAY) != 0)
1271 {
1272 if ((info->insn_type & INSN_WRITE_GPR_31) != 0)
1273 info->insn_type = dis_jsr;
1274 else
1275 info->insn_type = dis_branch;
1276 info->branch_delay_insns = 1;
1277 }
1278 else if ((op->pinfo & (INSN_COND_BRANCH_DELAY
1279 | INSN_COND_BRANCH_LIKELY)) != 0)
1280 {
1281 if ((info->insn_type & INSN_WRITE_GPR_31) != 0)
1282 info->insn_type = dis_condjsr;
1283 else
1284 info->insn_type = dis_condbranch;
1285 info->branch_delay_insns = 1;
1286 }
1287 else if ((op->pinfo & (INSN_STORE_MEMORY
1288 | INSN_LOAD_MEMORY_DELAY)) != 0)
1289 info->insn_type = dis_dref;
1290
1291 (*info->fprintf_func) (info->stream, "%s", op->name);
1292
1293 d = op->args;
1294 if (d != NULL && *d != '\0')
1295 {
1296 (*info->fprintf_func) (info->stream, "\t");
1297 print_insn_args (d, word, memaddr, info, op);
1298 }
1299
1300 return INSNLEN;
1301 }
1302 }
1303 }
1304
1305 /* Handle undefined instructions. */
1306 info->insn_type = dis_noninsn;
1307 (*info->fprintf_func) (info->stream, "0x%lx", word);
1308 return INSNLEN;
1309 }
1310 \f
1311 /* Disassemble an operand for a mips16 instruction. */
1312
1313 static void
1314 print_mips16_insn_arg (char type,
1315 const struct mips_opcode *op,
1316 int l,
1317 bfd_boolean use_extend,
1318 int extend,
1319 bfd_vma memaddr,
1320 struct disassemble_info *info)
1321 {
1322 switch (type)
1323 {
1324 case ',':
1325 case '(':
1326 case ')':
1327 (*info->fprintf_func) (info->stream, "%c", type);
1328 break;
1329
1330 case 'y':
1331 case 'w':
1332 (*info->fprintf_func) (info->stream, "%s",
1333 mips16_reg_names(((l >> MIPS16OP_SH_RY)
1334 & MIPS16OP_MASK_RY)));
1335 break;
1336
1337 case 'x':
1338 case 'v':
1339 (*info->fprintf_func) (info->stream, "%s",
1340 mips16_reg_names(((l >> MIPS16OP_SH_RX)
1341 & MIPS16OP_MASK_RX)));
1342 break;
1343
1344 case 'z':
1345 (*info->fprintf_func) (info->stream, "%s",
1346 mips16_reg_names(((l >> MIPS16OP_SH_RZ)
1347 & MIPS16OP_MASK_RZ)));
1348 break;
1349
1350 case 'Z':
1351 (*info->fprintf_func) (info->stream, "%s",
1352 mips16_reg_names(((l >> MIPS16OP_SH_MOVE32Z)
1353 & MIPS16OP_MASK_MOVE32Z)));
1354 break;
1355
1356 case '0':
1357 (*info->fprintf_func) (info->stream, "%s", mips_gpr_names[0]);
1358 break;
1359
1360 case 'S':
1361 (*info->fprintf_func) (info->stream, "%s", mips_gpr_names[29]);
1362 break;
1363
1364 case 'P':
1365 (*info->fprintf_func) (info->stream, "$pc");
1366 break;
1367
1368 case 'R':
1369 (*info->fprintf_func) (info->stream, "%s", mips_gpr_names[31]);
1370 break;
1371
1372 case 'X':
1373 (*info->fprintf_func) (info->stream, "%s",
1374 mips_gpr_names[((l >> MIPS16OP_SH_REGR32)
1375 & MIPS16OP_MASK_REGR32)]);
1376 break;
1377
1378 case 'Y':
1379 (*info->fprintf_func) (info->stream, "%s",
1380 mips_gpr_names[MIPS16OP_EXTRACT_REG32R (l)]);
1381 break;
1382
1383 case '<':
1384 case '>':
1385 case '[':
1386 case ']':
1387 case '4':
1388 case '5':
1389 case 'H':
1390 case 'W':
1391 case 'D':
1392 case 'j':
1393 case '6':
1394 case '8':
1395 case 'V':
1396 case 'C':
1397 case 'U':
1398 case 'k':
1399 case 'K':
1400 case 'p':
1401 case 'q':
1402 case 'A':
1403 case 'B':
1404 case 'E':
1405 {
1406 int immed, nbits, shift, signedp, extbits, pcrel, extu, branch;
1407
1408 shift = 0;
1409 signedp = 0;
1410 extbits = 16;
1411 pcrel = 0;
1412 extu = 0;
1413 branch = 0;
1414 switch (type)
1415 {
1416 case '<':
1417 nbits = 3;
1418 immed = (l >> MIPS16OP_SH_RZ) & MIPS16OP_MASK_RZ;
1419 extbits = 5;
1420 extu = 1;
1421 break;
1422 case '>':
1423 nbits = 3;
1424 immed = (l >> MIPS16OP_SH_RX) & MIPS16OP_MASK_RX;
1425 extbits = 5;
1426 extu = 1;
1427 break;
1428 case '[':
1429 nbits = 3;
1430 immed = (l >> MIPS16OP_SH_RZ) & MIPS16OP_MASK_RZ;
1431 extbits = 6;
1432 extu = 1;
1433 break;
1434 case ']':
1435 nbits = 3;
1436 immed = (l >> MIPS16OP_SH_RX) & MIPS16OP_MASK_RX;
1437 extbits = 6;
1438 extu = 1;
1439 break;
1440 case '4':
1441 nbits = 4;
1442 immed = (l >> MIPS16OP_SH_IMM4) & MIPS16OP_MASK_IMM4;
1443 signedp = 1;
1444 extbits = 15;
1445 break;
1446 case '5':
1447 nbits = 5;
1448 immed = (l >> MIPS16OP_SH_IMM5) & MIPS16OP_MASK_IMM5;
1449 info->insn_type = dis_dref;
1450 info->data_size = 1;
1451 break;
1452 case 'H':
1453 nbits = 5;
1454 shift = 1;
1455 immed = (l >> MIPS16OP_SH_IMM5) & MIPS16OP_MASK_IMM5;
1456 info->insn_type = dis_dref;
1457 info->data_size = 2;
1458 break;
1459 case 'W':
1460 nbits = 5;
1461 shift = 2;
1462 immed = (l >> MIPS16OP_SH_IMM5) & MIPS16OP_MASK_IMM5;
1463 if ((op->pinfo & MIPS16_INSN_READ_PC) == 0
1464 && (op->pinfo & MIPS16_INSN_READ_SP) == 0)
1465 {
1466 info->insn_type = dis_dref;
1467 info->data_size = 4;
1468 }
1469 break;
1470 case 'D':
1471 nbits = 5;
1472 shift = 3;
1473 immed = (l >> MIPS16OP_SH_IMM5) & MIPS16OP_MASK_IMM5;
1474 info->insn_type = dis_dref;
1475 info->data_size = 8;
1476 break;
1477 case 'j':
1478 nbits = 5;
1479 immed = (l >> MIPS16OP_SH_IMM5) & MIPS16OP_MASK_IMM5;
1480 signedp = 1;
1481 break;
1482 case '6':
1483 nbits = 6;
1484 immed = (l >> MIPS16OP_SH_IMM6) & MIPS16OP_MASK_IMM6;
1485 break;
1486 case '8':
1487 nbits = 8;
1488 immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8;
1489 break;
1490 case 'V':
1491 nbits = 8;
1492 shift = 2;
1493 immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8;
1494 /* FIXME: This might be lw, or it might be addiu to $sp or
1495 $pc. We assume it's load. */
1496 info->insn_type = dis_dref;
1497 info->data_size = 4;
1498 break;
1499 case 'C':
1500 nbits = 8;
1501 shift = 3;
1502 immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8;
1503 info->insn_type = dis_dref;
1504 info->data_size = 8;
1505 break;
1506 case 'U':
1507 nbits = 8;
1508 immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8;
1509 extu = 1;
1510 break;
1511 case 'k':
1512 nbits = 8;
1513 immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8;
1514 signedp = 1;
1515 break;
1516 case 'K':
1517 nbits = 8;
1518 shift = 3;
1519 immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8;
1520 signedp = 1;
1521 break;
1522 case 'p':
1523 nbits = 8;
1524 immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8;
1525 signedp = 1;
1526 pcrel = 1;
1527 branch = 1;
1528 info->insn_type = dis_condbranch;
1529 break;
1530 case 'q':
1531 nbits = 11;
1532 immed = (l >> MIPS16OP_SH_IMM11) & MIPS16OP_MASK_IMM11;
1533 signedp = 1;
1534 pcrel = 1;
1535 branch = 1;
1536 info->insn_type = dis_branch;
1537 break;
1538 case 'A':
1539 nbits = 8;
1540 shift = 2;
1541 immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8;
1542 pcrel = 1;
1543 /* FIXME: This can be lw or la. We assume it is lw. */
1544 info->insn_type = dis_dref;
1545 info->data_size = 4;
1546 break;
1547 case 'B':
1548 nbits = 5;
1549 shift = 3;
1550 immed = (l >> MIPS16OP_SH_IMM5) & MIPS16OP_MASK_IMM5;
1551 pcrel = 1;
1552 info->insn_type = dis_dref;
1553 info->data_size = 8;
1554 break;
1555 case 'E':
1556 nbits = 5;
1557 shift = 2;
1558 immed = (l >> MIPS16OP_SH_IMM5) & MIPS16OP_MASK_IMM5;
1559 pcrel = 1;
1560 break;
1561 default:
1562 abort ();
1563 }
1564
1565 if (! use_extend)
1566 {
1567 if (signedp && immed >= (1 << (nbits - 1)))
1568 immed -= 1 << nbits;
1569 immed <<= shift;
1570 if ((type == '<' || type == '>' || type == '[' || type == ']')
1571 && immed == 0)
1572 immed = 8;
1573 }
1574 else
1575 {
1576 if (extbits == 16)
1577 immed |= ((extend & 0x1f) << 11) | (extend & 0x7e0);
1578 else if (extbits == 15)
1579 immed |= ((extend & 0xf) << 11) | (extend & 0x7f0);
1580 else
1581 immed = ((extend >> 6) & 0x1f) | (extend & 0x20);
1582 immed &= (1 << extbits) - 1;
1583 if (! extu && immed >= (1 << (extbits - 1)))
1584 immed -= 1 << extbits;
1585 }
1586
1587 if (! pcrel)
1588 (*info->fprintf_func) (info->stream, "%d", immed);
1589 else
1590 {
1591 bfd_vma baseaddr;
1592
1593 if (branch)
1594 {
1595 immed *= 2;
1596 baseaddr = memaddr + 2;
1597 }
1598 else if (use_extend)
1599 baseaddr = memaddr - 2;
1600 else
1601 {
1602 int status;
1603 bfd_byte buffer[2];
1604
1605 baseaddr = memaddr;
1606
1607 /* If this instruction is in the delay slot of a jr
1608 instruction, the base address is the address of the
1609 jr instruction. If it is in the delay slot of jalr
1610 instruction, the base address is the address of the
1611 jalr instruction. This test is unreliable: we have
1612 no way of knowing whether the previous word is
1613 instruction or data. */
1614 status = (*info->read_memory_func) (memaddr - 4, buffer, 2,
1615 info);
1616 if (status == 0
1617 && (((info->endian == BFD_ENDIAN_BIG
1618 ? bfd_getb16 (buffer)
1619 : bfd_getl16 (buffer))
1620 & 0xf800) == 0x1800))
1621 baseaddr = memaddr - 4;
1622 else
1623 {
1624 status = (*info->read_memory_func) (memaddr - 2, buffer,
1625 2, info);
1626 if (status == 0
1627 && (((info->endian == BFD_ENDIAN_BIG
1628 ? bfd_getb16 (buffer)
1629 : bfd_getl16 (buffer))
1630 & 0xf81f) == 0xe800))
1631 baseaddr = memaddr - 2;
1632 }
1633 }
1634 info->target = (baseaddr & ~((1 << shift) - 1)) + immed;
1635 (*info->print_address_func) (info->target, info);
1636 }
1637 }
1638 break;
1639
1640 case 'a':
1641 if (! use_extend)
1642 extend = 0;
1643 l = ((l & 0x1f) << 23) | ((l & 0x3e0) << 13) | (extend << 2);
1644 info->target = ((memaddr + 4) & ~(bfd_vma) 0x0fffffff) | l;
1645 (*info->print_address_func) (info->target, info);
1646 info->insn_type = dis_jsr;
1647 info->branch_delay_insns = 1;
1648 break;
1649
1650 case 'l':
1651 case 'L':
1652 {
1653 int need_comma, amask, smask;
1654
1655 need_comma = 0;
1656
1657 l = (l >> MIPS16OP_SH_IMM6) & MIPS16OP_MASK_IMM6;
1658
1659 amask = (l >> 3) & 7;
1660
1661 if (amask > 0 && amask < 5)
1662 {
1663 (*info->fprintf_func) (info->stream, "%s", mips_gpr_names[4]);
1664 if (amask > 1)
1665 (*info->fprintf_func) (info->stream, "-%s",
1666 mips_gpr_names[amask + 3]);
1667 need_comma = 1;
1668 }
1669
1670 smask = (l >> 1) & 3;
1671 if (smask == 3)
1672 {
1673 (*info->fprintf_func) (info->stream, "%s??",
1674 need_comma ? "," : "");
1675 need_comma = 1;
1676 }
1677 else if (smask > 0)
1678 {
1679 (*info->fprintf_func) (info->stream, "%s%s",
1680 need_comma ? "," : "",
1681 mips_gpr_names[16]);
1682 if (smask > 1)
1683 (*info->fprintf_func) (info->stream, "-%s",
1684 mips_gpr_names[smask + 15]);
1685 need_comma = 1;
1686 }
1687
1688 if (l & 1)
1689 {
1690 (*info->fprintf_func) (info->stream, "%s%s",
1691 need_comma ? "," : "",
1692 mips_gpr_names[31]);
1693 need_comma = 1;
1694 }
1695
1696 if (amask == 5 || amask == 6)
1697 {
1698 (*info->fprintf_func) (info->stream, "%s$f0",
1699 need_comma ? "," : "");
1700 if (amask == 6)
1701 (*info->fprintf_func) (info->stream, "-$f1");
1702 }
1703 }
1704 break;
1705
1706 case 'm':
1707 case 'M':
1708 /* MIPS16e save/restore. */
1709 {
1710 int need_comma = 0;
1711 int amask, args, statics;
1712 int nsreg, smask;
1713 int framesz;
1714 int i, j;
1715
1716 l = l & 0x7f;
1717 if (use_extend)
1718 l |= extend << 16;
1719
1720 amask = (l >> 16) & 0xf;
1721 if (amask == MIPS16_ALL_ARGS)
1722 {
1723 args = 4;
1724 statics = 0;
1725 }
1726 else if (amask == MIPS16_ALL_STATICS)
1727 {
1728 args = 0;
1729 statics = 4;
1730 }
1731 else
1732 {
1733 args = amask >> 2;
1734 statics = amask & 3;
1735 }
1736
1737 if (args > 0) {
1738 (*info->fprintf_func) (info->stream, "%s", mips_gpr_names[4]);
1739 if (args > 1)
1740 (*info->fprintf_func) (info->stream, "-%s",
1741 mips_gpr_names[4 + args - 1]);
1742 need_comma = 1;
1743 }
1744
1745 framesz = (((l >> 16) & 0xf0) | (l & 0x0f)) * 8;
1746 if (framesz == 0 && !use_extend)
1747 framesz = 128;
1748
1749 (*info->fprintf_func) (info->stream, "%s%d",
1750 need_comma ? "," : "",
1751 framesz);
1752
1753 if (l & 0x40) /* $ra */
1754 (*info->fprintf_func) (info->stream, ",%s", mips_gpr_names[31]);
1755
1756 nsreg = (l >> 24) & 0x7;
1757 smask = 0;
1758 if (l & 0x20) /* $s0 */
1759 smask |= 1 << 0;
1760 if (l & 0x10) /* $s1 */
1761 smask |= 1 << 1;
1762 if (nsreg > 0) /* $s2-$s8 */
1763 smask |= ((1 << nsreg) - 1) << 2;
1764
1765 /* Find first set static reg bit. */
1766 for (i = 0; i < 9; i++)
1767 {
1768 if (smask & (1 << i))
1769 {
1770 (*info->fprintf_func) (info->stream, ",%s",
1771 mips_gpr_names[i == 8 ? 30 : (16 + i)]);
1772 /* Skip over string of set bits. */
1773 for (j = i; smask & (2 << j); j++)
1774 continue;
1775 if (j > i)
1776 (*info->fprintf_func) (info->stream, "-%s",
1777 mips_gpr_names[j == 8 ? 30 : (16 + j)]);
1778 i = j + 1;
1779 }
1780 }
1781
1782 /* Statics $ax - $a3. */
1783 if (statics == 1)
1784 (*info->fprintf_func) (info->stream, ",%s", mips_gpr_names[7]);
1785 else if (statics > 0)
1786 (*info->fprintf_func) (info->stream, ",%s-%s",
1787 mips_gpr_names[7 - statics + 1],
1788 mips_gpr_names[7]);
1789 }
1790 break;
1791
1792 default:
1793 /* xgettext:c-format */
1794 (*info->fprintf_func)
1795 (info->stream,
1796 _("# internal disassembler error, unrecognised modifier (%c)"),
1797 type);
1798 abort ();
1799 }
1800 }
1801
1802 /* Disassemble mips16 instructions. */
1803
1804 static int
1805 print_insn_mips16 (bfd_vma memaddr, struct disassemble_info *info)
1806 {
1807 int status;
1808 bfd_byte buffer[2];
1809 int length;
1810 int insn;
1811 bfd_boolean use_extend;
1812 int extend = 0;
1813 const struct mips_opcode *op, *opend;
1814
1815 info->bytes_per_chunk = 2;
1816 info->display_endian = info->endian;
1817 info->insn_info_valid = 1;
1818 info->branch_delay_insns = 0;
1819 info->data_size = 0;
1820 info->insn_type = dis_nonbranch;
1821 info->target = 0;
1822 info->target2 = 0;
1823
1824 status = (*info->read_memory_func) (memaddr, buffer, 2, info);
1825 if (status != 0)
1826 {
1827 (*info->memory_error_func) (status, memaddr, info);
1828 return -1;
1829 }
1830
1831 length = 2;
1832
1833 if (info->endian == BFD_ENDIAN_BIG)
1834 insn = bfd_getb16 (buffer);
1835 else
1836 insn = bfd_getl16 (buffer);
1837
1838 /* Handle the extend opcode specially. */
1839 use_extend = FALSE;
1840 if ((insn & 0xf800) == 0xf000)
1841 {
1842 use_extend = TRUE;
1843 extend = insn & 0x7ff;
1844
1845 memaddr += 2;
1846
1847 status = (*info->read_memory_func) (memaddr, buffer, 2, info);
1848 if (status != 0)
1849 {
1850 (*info->fprintf_func) (info->stream, "extend 0x%x",
1851 (unsigned int) extend);
1852 (*info->memory_error_func) (status, memaddr, info);
1853 return -1;
1854 }
1855
1856 if (info->endian == BFD_ENDIAN_BIG)
1857 insn = bfd_getb16 (buffer);
1858 else
1859 insn = bfd_getl16 (buffer);
1860
1861 /* Check for an extend opcode followed by an extend opcode. */
1862 if ((insn & 0xf800) == 0xf000)
1863 {
1864 (*info->fprintf_func) (info->stream, "extend 0x%x",
1865 (unsigned int) extend);
1866 info->insn_type = dis_noninsn;
1867 return length;
1868 }
1869
1870 length += 2;
1871 }
1872
1873 /* FIXME: Should probably use a hash table on the major opcode here. */
1874
1875 opend = mips16_opcodes + bfd_mips16_num_opcodes;
1876 for (op = mips16_opcodes; op < opend; op++)
1877 {
1878 if (op->pinfo != INSN_MACRO
1879 && !(no_aliases && (op->pinfo2 & INSN2_ALIAS))
1880 && (insn & op->mask) == op->match)
1881 {
1882 const char *s;
1883
1884 if (strchr (op->args, 'a') != NULL)
1885 {
1886 if (use_extend)
1887 {
1888 (*info->fprintf_func) (info->stream, "extend 0x%x",
1889 (unsigned int) extend);
1890 info->insn_type = dis_noninsn;
1891 return length - 2;
1892 }
1893
1894 use_extend = FALSE;
1895
1896 memaddr += 2;
1897
1898 status = (*info->read_memory_func) (memaddr, buffer, 2,
1899 info);
1900 if (status == 0)
1901 {
1902 use_extend = TRUE;
1903 if (info->endian == BFD_ENDIAN_BIG)
1904 extend = bfd_getb16 (buffer);
1905 else
1906 extend = bfd_getl16 (buffer);
1907 length += 2;
1908 }
1909 }
1910
1911 (*info->fprintf_func) (info->stream, "%s", op->name);
1912 if (op->args[0] != '\0')
1913 (*info->fprintf_func) (info->stream, "\t");
1914
1915 for (s = op->args; *s != '\0'; s++)
1916 {
1917 if (*s == ','
1918 && s[1] == 'w'
1919 && (((insn >> MIPS16OP_SH_RX) & MIPS16OP_MASK_RX)
1920 == ((insn >> MIPS16OP_SH_RY) & MIPS16OP_MASK_RY)))
1921 {
1922 /* Skip the register and the comma. */
1923 ++s;
1924 continue;
1925 }
1926 if (*s == ','
1927 && s[1] == 'v'
1928 && (((insn >> MIPS16OP_SH_RZ) & MIPS16OP_MASK_RZ)
1929 == ((insn >> MIPS16OP_SH_RX) & MIPS16OP_MASK_RX)))
1930 {
1931 /* Skip the register and the comma. */
1932 ++s;
1933 continue;
1934 }
1935 print_mips16_insn_arg (*s, op, insn, use_extend, extend, memaddr,
1936 info);
1937 }
1938
1939 if ((op->pinfo & INSN_UNCOND_BRANCH_DELAY) != 0)
1940 {
1941 info->branch_delay_insns = 1;
1942 if (info->insn_type != dis_jsr)
1943 info->insn_type = dis_branch;
1944 }
1945
1946 return length;
1947 }
1948 }
1949
1950 if (use_extend)
1951 (*info->fprintf_func) (info->stream, "0x%x", extend | 0xf000);
1952 (*info->fprintf_func) (info->stream, "0x%x", insn);
1953 info->insn_type = dis_noninsn;
1954
1955 return length;
1956 }
1957
1958 /* In an environment where we do not know the symbol type of the
1959 instruction we are forced to assume that the low order bit of the
1960 instructions' address may mark it as a mips16 instruction. If we
1961 are single stepping, or the pc is within the disassembled function,
1962 this works. Otherwise, we need a clue. Sometimes. */
1963
1964 static int
1965 _print_insn_mips (bfd_vma memaddr,
1966 struct disassemble_info *info,
1967 enum bfd_endian endianness)
1968 {
1969 bfd_byte buffer[INSNLEN];
1970 int status;
1971
1972 set_default_mips_dis_options (info);
1973 parse_mips_dis_options (info->disassembler_options);
1974
1975 #if 1
1976 /* FIXME: If odd address, this is CLEARLY a mips 16 instruction. */
1977 /* Only a few tools will work this way. */
1978 if (memaddr & 0x01)
1979 return print_insn_mips16 (memaddr, info);
1980 #endif
1981
1982 #if SYMTAB_AVAILABLE
1983 if (info->mach == bfd_mach_mips16
1984 || (info->flavour == bfd_target_elf_flavour
1985 && info->symbols != NULL
1986 && ((*(elf_symbol_type **) info->symbols)->internal_elf_sym.st_other
1987 == STO_MIPS16)))
1988 return print_insn_mips16 (memaddr, info);
1989 #endif
1990
1991 status = (*info->read_memory_func) (memaddr, buffer, INSNLEN, info);
1992 if (status == 0)
1993 {
1994 unsigned long insn;
1995
1996 if (endianness == BFD_ENDIAN_BIG)
1997 insn = (unsigned long) bfd_getb32 (buffer);
1998 else
1999 insn = (unsigned long) bfd_getl32 (buffer);
2000
2001 return print_insn_mips (memaddr, insn, info);
2002 }
2003 else
2004 {
2005 (*info->memory_error_func) (status, memaddr, info);
2006 return -1;
2007 }
2008 }
2009
2010 int
2011 print_insn_big_mips (bfd_vma memaddr, struct disassemble_info *info)
2012 {
2013 return _print_insn_mips (memaddr, info, BFD_ENDIAN_BIG);
2014 }
2015
2016 int
2017 print_insn_little_mips (bfd_vma memaddr, struct disassemble_info *info)
2018 {
2019 return _print_insn_mips (memaddr, info, BFD_ENDIAN_LITTLE);
2020 }
2021 \f
2022 void
2023 print_mips_disassembler_options (FILE *stream)
2024 {
2025 unsigned int i;
2026
2027 fprintf (stream, _("\n\
2028 The following MIPS specific disassembler options are supported for use\n\
2029 with the -M switch (multiple options should be separated by commas):\n"));
2030
2031 fprintf (stream, _("\n\
2032 gpr-names=ABI Print GPR names according to specified ABI.\n\
2033 Default: based on binary being disassembled.\n"));
2034
2035 fprintf (stream, _("\n\
2036 fpr-names=ABI Print FPR names according to specified ABI.\n\
2037 Default: numeric.\n"));
2038
2039 fprintf (stream, _("\n\
2040 cp0-names=ARCH Print CP0 register names according to\n\
2041 specified architecture.\n\
2042 Default: based on binary being disassembled.\n"));
2043
2044 fprintf (stream, _("\n\
2045 hwr-names=ARCH Print HWR names according to specified \n\
2046 architecture.\n\
2047 Default: based on binary being disassembled.\n"));
2048
2049 fprintf (stream, _("\n\
2050 reg-names=ABI Print GPR and FPR names according to\n\
2051 specified ABI.\n"));
2052
2053 fprintf (stream, _("\n\
2054 reg-names=ARCH Print CP0 register and HWR names according to\n\
2055 specified architecture.\n"));
2056
2057 fprintf (stream, _("\n\
2058 For the options above, the following values are supported for \"ABI\":\n\
2059 "));
2060 for (i = 0; i < ARRAY_SIZE (mips_abi_choices); i++)
2061 fprintf (stream, " %s", mips_abi_choices[i].name);
2062 fprintf (stream, _("\n"));
2063
2064 fprintf (stream, _("\n\
2065 For the options above, The following values are supported for \"ARCH\":\n\
2066 "));
2067 for (i = 0; i < ARRAY_SIZE (mips_arch_choices); i++)
2068 if (*mips_arch_choices[i].name != '\0')
2069 fprintf (stream, " %s", mips_arch_choices[i].name);
2070 fprintf (stream, _("\n"));
2071
2072 fprintf (stream, _("\n"));
2073 }
GDB Binutils - Deliverables
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