1 /* Print mips instructions for GDB, the GNU debugger, or for objdump.
2 Copyright 1989, 91-97, 1998 Free Software Foundation, Inc.
3 Contributed by Nobuyuki Hikichi(hikichi@sra.co.jp).
5 This file is part of GDB, GAS, and the GNU binutils.
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2 of the License, or
10 (at your option) any later version.
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this program; if not, write to the Free Software
19 Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
24 #include "opcode/mips.h"
26 /* FIXME: These are needed to figure out if this is a mips16 symbol or
27 not. It would be better to think of a cleaner way to do this. */
31 static int print_insn_mips16
PARAMS ((bfd_vma
, struct disassemble_info
*));
32 static void print_mips16_insn_arg
33 PARAMS ((int, const struct mips_opcode
*, int, boolean
, int, bfd_vma
,
34 struct disassemble_info
*));
36 /* Mips instructions are never longer than this many bytes. */
39 static void print_insn_arg
PARAMS ((const char *, unsigned long, bfd_vma
,
40 struct disassemble_info
*));
41 static int _print_insn_mips
PARAMS ((bfd_vma
, unsigned long int,
42 struct disassemble_info
*));
45 /* FIXME: This should be shared with gdb somehow. */
46 #define REGISTER_NAMES \
47 { "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3", \
48 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7", \
49 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", \
50 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra", \
51 "sr", "lo", "hi", "bad", "cause","pc", \
52 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", \
53 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", \
54 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",\
55 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",\
56 "fsr", "fir", "fp", "inx", "rand", "tlblo","ctxt", "tlbhi",\
60 static CONST
char * CONST reg_names
[] = REGISTER_NAMES
;
62 /* The mips16 register names. */
63 static const char * const mips16_reg_names
[] =
65 "s0", "s1", "v0", "v1", "a0", "a1", "a2", "a3"
70 print_insn_arg (d
, l
, pc
, info
)
72 register unsigned long int l
;
74 struct disassemble_info
*info
;
83 /* start-sanitize-vr5400 */
86 /* end-sanitize-vr5400 */
87 /* start-sanitize-r5900 */
90 /* end-santiize-r5900 */
91 (*info
->fprintf_func
) (info
->stream
, "%c", *d
);
98 (*info
->fprintf_func
) (info
->stream
, "$%s",
99 reg_names
[(l
>> OP_SH_RS
) & OP_MASK_RS
]);
104 (*info
->fprintf_func
) (info
->stream
, "$%s",
105 reg_names
[(l
>> OP_SH_RT
) & OP_MASK_RT
]);
110 (*info
->fprintf_func
) (info
->stream
, "0x%x",
111 (l
>> OP_SH_IMMEDIATE
) & OP_MASK_IMMEDIATE
);
114 case 'j': /* same as i, but sign-extended */
116 delta
= (l
>> OP_SH_DELTA
) & OP_MASK_DELTA
;
119 (*info
->fprintf_func
) (info
->stream
, "%d",
124 (*info
->fprintf_func
) (info
->stream
, "0x%x",
125 (unsigned int) ((l
>> OP_SH_PREFX
)
130 (*info
->fprintf_func
) (info
->stream
, "0x%x",
131 (unsigned int) ((l
>> OP_SH_CACHE
)
136 (*info
->print_address_func
)
137 (((pc
& 0xF0000000) | (((l
>> OP_SH_TARGET
) & OP_MASK_TARGET
) << 2)),
142 /* sign extend the displacement */
143 delta
= (l
>> OP_SH_DELTA
) & OP_MASK_DELTA
;
146 (*info
->print_address_func
)
147 ((delta
<< 2) + pc
+ 4,
152 (*info
->fprintf_func
) (info
->stream
, "$%s",
153 reg_names
[(l
>> OP_SH_RD
) & OP_MASK_RD
]);
157 (*info
->fprintf_func
) (info
->stream
, "$%s", reg_names
[0]);
161 (*info
->fprintf_func
) (info
->stream
, "0x%x",
162 (l
>> OP_SH_SHAMT
) & OP_MASK_SHAMT
);
166 (*info
->fprintf_func
) (info
->stream
, "0x%x",
167 (l
>> OP_SH_CODE
) & OP_MASK_CODE
);
171 (*info
->fprintf_func
) (info
->stream
, "0x%x",
172 (l
>> OP_SH_COPZ
) & OP_MASK_COPZ
);
176 (*info
->fprintf_func
) (info
->stream
, "0x%x",
177 (l
>> OP_SH_SYSCALL
) & OP_MASK_SYSCALL
);
182 (*info
->fprintf_func
) (info
->stream
, "$f%d",
183 (l
>> OP_SH_FS
) & OP_MASK_FS
);
186 /* start-sanitize-r5900
188 (*info->fprintf_func) (info->stream, "0x%x",
193 (*info->fprintf_func) (info->stream, "vi19");
197 (*info->fprintf_func) (info->stream, "vf%d",
198 (l >> OP_SH_FT) & OP_MASK_FT);
201 (*info->fprintf_func) (info->stream, "vf%d",
202 (l >> OP_SH_FS) & OP_MASK_FS);
205 (*info->fprintf_func) (info->stream, "vf%d",
206 (l >> OP_SH_FD) & OP_MASK_FD);
210 (*info->fprintf_func) (info->stream, "vi%d",
211 (l >> OP_SH_FT) & OP_MASK_FT);
214 (*info->fprintf_func) (info->stream, "vi%d",
215 (l >> OP_SH_FS) & OP_MASK_FS);
218 (*info->fprintf_func) (info->stream, "vi%d",
219 (l >> OP_SH_FD) & OP_MASK_FD);
223 (*info->fprintf_func) (info->stream, "vf%d",
224 (l >> OP_SH_FT) & OP_MASK_FT);
225 switch ((l >> 23) & 0x3)
228 (*info->fprintf_func) (info->stream, "x");
231 (*info->fprintf_func) (info->stream, "y");
234 (*info->fprintf_func) (info->stream, "z");
237 (*info->fprintf_func) (info->stream, "w");
245 (*info->fprintf_func) (info->stream, ".");
247 (*info->fprintf_func) (info->stream, "w");
249 (*info->fprintf_func) (info->stream, "x");
251 (*info->fprintf_func) (info->stream, "y");
253 (*info->fprintf_func) (info->stream, "z");
254 (*info->fprintf_func) (info->stream, "\t");
258 (*info->fprintf_func) (info->stream, "vf%d",
259 (l >> OP_SH_FS) & OP_MASK_FS);
260 switch ((l >> 21) & 0x3)
263 (*info->fprintf_func) (info->stream, "x");
266 (*info->fprintf_func) (info->stream, "y");
269 (*info->fprintf_func) (info->stream, "z");
272 (*info->fprintf_func) (info->stream, "w");
277 (*info->fprintf_func) (info->stream, "I");
281 (*info->fprintf_func) (info->stream, "Q");
285 (*info->fprintf_func) (info->stream, "R");
289 (*info->fprintf_func) (info->stream, "ACC");
293 delta = (l >> 6) & 0x7fff;
295 (*info->print_address_func) (delta, info);
298 /* end-sanitize-r5900 */
302 (*info
->fprintf_func
) (info
->stream
, "$f%d",
303 (l
>> OP_SH_FT
) & OP_MASK_FT
);
307 (*info
->fprintf_func
) (info
->stream
, "$f%d",
308 (l
>> OP_SH_FD
) & OP_MASK_FD
);
312 (*info
->fprintf_func
) (info
->stream
, "$f%d",
313 (l
>> OP_SH_FR
) & OP_MASK_FR
);
317 (*info
->fprintf_func
) (info
->stream
, "$%d",
318 (l
>> OP_SH_RT
) & OP_MASK_RT
);
322 (*info
->fprintf_func
) (info
->stream
, "$%d",
323 (l
>> OP_SH_RD
) & OP_MASK_RD
);
327 (*info
->fprintf_func
) (info
->stream
, "$fcc%d",
328 (l
>> OP_SH_BCC
) & OP_MASK_BCC
);
332 (*info
->fprintf_func
) (info
->stream
, "$fcc%d",
333 (l
>> OP_SH_CCC
) & OP_MASK_CCC
);
337 (*info
->fprintf_func
) (info
->stream
, "%d",
338 (l
>> OP_SH_PERFREG
) & OP_MASK_PERFREG
);
341 /* start-sanitize-vr5400 */
343 (*info
->fprintf_func
) (info
->stream
, "%d",
344 (l
>> OP_SH_VECBYTE
) & OP_MASK_VECBYTE
);
348 (*info
->fprintf_func
) (info
->stream
, "%d",
349 (l
>> OP_SH_VECALIGN
) & OP_MASK_VECALIGN
);
351 /* end-sanitize-vr5400 */
354 (*info
->fprintf_func
) (info
->stream
,
355 "# internal error, undefined modifier(%c)", *d
);
360 /* Print the mips instruction at address MEMADDR in debugged memory,
361 on using INFO. Returns length of the instruction, in bytes, which is
362 always 4. BIGENDIAN must be 1 if this is big-endian code, 0 if
363 this is little-endian code. */
366 _print_insn_mips (memaddr
, word
, info
)
368 unsigned long int word
;
369 struct disassemble_info
*info
;
371 register const struct mips_opcode
*op
;
372 int target_processor
, mips_isa
;
373 static boolean init
= 0;
374 static const struct mips_opcode
*mips_hash
[OP_MASK_OP
+ 1];
376 /* Build a hash table to shorten the search time. */
381 for (i
= 0; i
<= OP_MASK_OP
; i
++)
383 for (op
= mips_opcodes
; op
< &mips_opcodes
[NUMOPCODES
]; op
++)
385 if (op
->pinfo
== INSN_MACRO
)
387 if (i
== ((op
->match
>> OP_SH_OP
) & OP_MASK_OP
))
400 /* start-sanitize-tx19 */
401 case bfd_mach_mips1900
:
402 target_processor
= 1900;
405 /* end-sanitize-tx19 */
406 case bfd_mach_mips3000
:
407 target_processor
= 3000;
410 case bfd_mach_mips3900
:
411 target_processor
= 3900;
414 case bfd_mach_mips4000
:
415 target_processor
= 4000;
418 case bfd_mach_mips4010
:
419 target_processor
= 4010;
422 case bfd_mach_mips4100
:
423 target_processor
= 4100;
426 case bfd_mach_mips4300
:
427 target_processor
= 4300;
430 /* start-sanitize-vr4320 */
431 case bfd_mach_mips4320
:
432 target_processor
= 4320;
435 /* end-sanitize-vr4320 */
436 case bfd_mach_mips4400
:
437 target_processor
= 4400;
440 case bfd_mach_mips4600
:
441 target_processor
= 4600;
444 case bfd_mach_mips4650
:
445 target_processor
= 4650;
448 /* start-sanitize-tx49 */
449 case bfd_mach_mips4900
:
450 target_processor
= 4900;
453 /* end-sanitize-tx49 */
454 case bfd_mach_mips5000
:
455 target_processor
= 5000;
458 /* start-sanitize-vr5400 */
459 case bfd_mach_mips5400
:
460 target_processor
= 5400;
463 /* end-sanitize-vr5400 */
464 /* start-sanitize-r5900 */
465 case bfd_mach_mips5900
:
466 target_processor
= 5900;
469 /* end-sanitize-r5900 */
470 case bfd_mach_mips6000
:
471 target_processor
= 6000;
474 case bfd_mach_mips8000
:
475 target_processor
= 8000;
478 case bfd_mach_mips10000
:
479 target_processor
= 10000;
482 case bfd_mach_mips16
:
483 target_processor
= 16;
487 target_processor
= 3000;
493 info
->bytes_per_chunk
= 4;
494 info
->display_endian
= info
->endian
;
496 op
= mips_hash
[(word
>> OP_SH_OP
) & OP_MASK_OP
];
499 for (; op
< &mips_opcodes
[NUMOPCODES
]; op
++)
501 if (op
->pinfo
!= INSN_MACRO
&& (word
& op
->mask
) == op
->match
)
503 register const char *d
;
506 if ((op
->membership
& INSN_ISA
) == INSN_ISA1
)
508 else if ((op
->membership
& INSN_ISA
) == INSN_ISA2
)
510 else if ((op
->membership
& INSN_ISA
) == INSN_ISA3
)
512 else if ((op
->membership
& INSN_ISA
) == INSN_ISA4
)
517 if (insn_isa
> mips_isa
518 && (target_processor
== 4650
519 && op
->membership
& INSN_4650
) == 0
520 && (target_processor
== 4010
521 && op
->membership
& INSN_4010
) == 0
522 && (target_processor
== 4100
523 && op
->membership
& INSN_4100
) == 0
524 /* start-sanitize-vr4320 */
525 && (target_processor
== 4320
526 && op
->membership
& INSN_4320
) == 0
527 /* end-sanitize-vr4320 */
528 /* start-sanitize-vr5400 */
529 && (target_processor
== 5400
530 && op
->membership
& INSN_5400
) == 0
531 /* end-sanitize-vr5400 */
532 /* start-sanitize-r5900 */
533 && (target_processor
== 5900
534 && op
->membership
& INSN_5900
) == 0
535 /* end-sanitize-r5900 */
536 /* start-sanitize-tx49 */
537 && (target_processor
== 4900
538 && op
->membership
& INSN_4900
) == 0
539 /* end-sanitize-tx49 */
540 && (target_processor
== 3900
541 && op
->membership
& INSN_3900
) == 0)
544 (*info
->fprintf_func
) (info
->stream
, "%s", op
->name
);
547 if (d
!= NULL
&& *d
!= '\0')
549 /* start-sanitize-r5900 */
550 /* If this is an opcode completer, then do not emit
551 a tab after the opcode. */
553 /* end-sanitize-r5900 */
554 (*info
->fprintf_func
) (info
->stream
, "\t");
555 for (; *d
!= '\0'; d
++)
556 /* start-sanitize-r5900 */
557 /* If this is an escape character, go ahead and print the
558 next character in the arg string verbatim. */
562 (*info
->fprintf_func
) (info
->stream
, "%c", *d
);
565 /* end-sanitize-r5900 */
566 print_insn_arg (d
, word
, memaddr
, info
);
574 /* Handle undefined instructions. */
575 (*info
->fprintf_func
) (info
->stream
, "0x%x", word
);
580 print_insn_big_mips (memaddr
, info
)
582 struct disassemble_info
*info
;
588 || (info
->flavour
== bfd_target_elf_flavour
589 && info
->symbols
!= NULL
590 && ((*(elf_symbol_type
**) info
->symbols
)->internal_elf_sym
.st_other
592 return print_insn_mips16 (memaddr
, info
);
594 status
= (*info
->read_memory_func
) (memaddr
, buffer
, 4, info
);
596 return _print_insn_mips (memaddr
, (unsigned long) bfd_getb32 (buffer
),
600 (*info
->memory_error_func
) (status
, memaddr
, info
);
606 print_insn_little_mips (memaddr
, info
)
608 struct disassemble_info
*info
;
613 /* start-sanitize-sky */
616 /* bfd_mach_dvp_p is a macro which may evaluate its arguments more than
617 once. Since dvp_mach_type is a function, ensure it's only called
619 int mach
= dvp_info_mach_type (info
);
621 if (bfd_mach_dvp_p (info
->mach
)
622 || bfd_mach_dvp_p (mach
))
623 return print_insn_dvp (memaddr
, info
);
626 /* end-sanitize-sky */
629 || (info
->flavour
== bfd_target_elf_flavour
630 && info
->symbols
!= NULL
631 && ((*(elf_symbol_type
**) info
->symbols
)->internal_elf_sym
.st_other
633 return print_insn_mips16 (memaddr
, info
);
635 status
= (*info
->read_memory_func
) (memaddr
, buffer
, 4, info
);
637 return _print_insn_mips (memaddr
, (unsigned long) bfd_getl32 (buffer
),
641 (*info
->memory_error_func
) (status
, memaddr
, info
);
646 /* Disassemble mips16 instructions. */
649 print_insn_mips16 (memaddr
, info
)
651 struct disassemble_info
*info
;
659 const struct mips_opcode
*op
, *opend
;
661 info
->bytes_per_chunk
= 2;
662 info
->display_endian
= info
->endian
;
664 info
->insn_info_valid
= 1;
665 info
->branch_delay_insns
= 0;
667 info
->insn_type
= dis_nonbranch
;
671 status
= (*info
->read_memory_func
) (memaddr
, buffer
, 2, info
);
674 (*info
->memory_error_func
) (status
, memaddr
, info
);
680 if (info
->endian
== BFD_ENDIAN_BIG
)
681 insn
= bfd_getb16 (buffer
);
683 insn
= bfd_getl16 (buffer
);
685 /* Handle the extend opcode specially. */
687 if ((insn
& 0xf800) == 0xf000)
690 extend
= insn
& 0x7ff;
694 status
= (*info
->read_memory_func
) (memaddr
, buffer
, 2, info
);
697 (*info
->fprintf_func
) (info
->stream
, "extend 0x%x",
698 (unsigned int) extend
);
699 (*info
->memory_error_func
) (status
, memaddr
, info
);
703 if (info
->endian
== BFD_ENDIAN_BIG
)
704 insn
= bfd_getb16 (buffer
);
706 insn
= bfd_getl16 (buffer
);
708 /* Check for an extend opcode followed by an extend opcode. */
709 if ((insn
& 0xf800) == 0xf000)
711 (*info
->fprintf_func
) (info
->stream
, "extend 0x%x",
712 (unsigned int) extend
);
713 info
->insn_type
= dis_noninsn
;
720 /* FIXME: Should probably use a hash table on the major opcode here. */
722 opend
= mips16_opcodes
+ bfd_mips16_num_opcodes
;
723 for (op
= mips16_opcodes
; op
< opend
; op
++)
725 if (op
->pinfo
!= INSN_MACRO
&& (insn
& op
->mask
) == op
->match
)
729 if (strchr (op
->args
, 'a') != NULL
)
733 (*info
->fprintf_func
) (info
->stream
, "extend 0x%x",
734 (unsigned int) extend
);
735 info
->insn_type
= dis_noninsn
;
743 status
= (*info
->read_memory_func
) (memaddr
, buffer
, 2,
748 if (info
->endian
== BFD_ENDIAN_BIG
)
749 extend
= bfd_getb16 (buffer
);
751 extend
= bfd_getl16 (buffer
);
756 (*info
->fprintf_func
) (info
->stream
, "%s", op
->name
);
757 if (op
->args
[0] != '\0')
758 (*info
->fprintf_func
) (info
->stream
, "\t");
760 for (s
= op
->args
; *s
!= '\0'; s
++)
764 && (((insn
>> MIPS16OP_SH_RX
) & MIPS16OP_MASK_RX
)
765 == ((insn
>> MIPS16OP_SH_RY
) & MIPS16OP_MASK_RY
)))
767 /* Skip the register and the comma. */
773 && (((insn
>> MIPS16OP_SH_RZ
) & MIPS16OP_MASK_RZ
)
774 == ((insn
>> MIPS16OP_SH_RX
) & MIPS16OP_MASK_RX
)))
776 /* Skip the register and the comma. */
780 print_mips16_insn_arg (*s
, op
, insn
, use_extend
, extend
, memaddr
,
784 if ((op
->pinfo
& INSN_UNCOND_BRANCH_DELAY
) != 0)
786 info
->branch_delay_insns
= 1;
787 if (info
->insn_type
!= dis_jsr
)
788 info
->insn_type
= dis_branch
;
796 (*info
->fprintf_func
) (info
->stream
, "0x%x", extend
| 0xf000);
797 (*info
->fprintf_func
) (info
->stream
, "0x%x", insn
);
798 info
->insn_type
= dis_noninsn
;
803 /* Disassemble an operand for a mips16 instruction. */
806 print_mips16_insn_arg (type
, op
, l
, use_extend
, extend
, memaddr
, info
)
808 const struct mips_opcode
*op
;
813 struct disassemble_info
*info
;
820 (*info
->fprintf_func
) (info
->stream
, "%c", type
);
825 (*info
->fprintf_func
) (info
->stream
, "$%s",
826 mips16_reg_names
[((l
>> MIPS16OP_SH_RY
)
827 & MIPS16OP_MASK_RY
)]);
832 (*info
->fprintf_func
) (info
->stream
, "$%s",
833 mips16_reg_names
[((l
>> MIPS16OP_SH_RX
)
834 & MIPS16OP_MASK_RX
)]);
838 (*info
->fprintf_func
) (info
->stream
, "$%s",
839 mips16_reg_names
[((l
>> MIPS16OP_SH_RZ
)
840 & MIPS16OP_MASK_RZ
)]);
844 (*info
->fprintf_func
) (info
->stream
, "$%s",
845 mips16_reg_names
[((l
>> MIPS16OP_SH_MOVE32Z
)
846 & MIPS16OP_MASK_MOVE32Z
)]);
850 (*info
->fprintf_func
) (info
->stream
, "$%s", reg_names
[0]);
854 (*info
->fprintf_func
) (info
->stream
, "$%s", reg_names
[29]);
858 (*info
->fprintf_func
) (info
->stream
, "$pc");
862 (*info
->fprintf_func
) (info
->stream
, "$%s", reg_names
[31]);
866 (*info
->fprintf_func
) (info
->stream
, "$%s",
867 reg_names
[((l
>> MIPS16OP_SH_REGR32
)
868 & MIPS16OP_MASK_REGR32
)]);
872 (*info
->fprintf_func
) (info
->stream
, "$%s",
873 reg_names
[MIPS16OP_EXTRACT_REG32R (l
)]);
899 int immed
, nbits
, shift
, signedp
, extbits
, pcrel
, extu
, branch
;
911 immed
= (l
>> MIPS16OP_SH_RZ
) & MIPS16OP_MASK_RZ
;
917 immed
= (l
>> MIPS16OP_SH_RX
) & MIPS16OP_MASK_RX
;
923 immed
= (l
>> MIPS16OP_SH_RZ
) & MIPS16OP_MASK_RZ
;
929 immed
= (l
>> MIPS16OP_SH_RX
) & MIPS16OP_MASK_RX
;
935 immed
= (l
>> MIPS16OP_SH_IMM4
) & MIPS16OP_MASK_IMM4
;
941 immed
= (l
>> MIPS16OP_SH_IMM5
) & MIPS16OP_MASK_IMM5
;
942 info
->insn_type
= dis_dref
;
948 immed
= (l
>> MIPS16OP_SH_IMM5
) & MIPS16OP_MASK_IMM5
;
949 info
->insn_type
= dis_dref
;
955 immed
= (l
>> MIPS16OP_SH_IMM5
) & MIPS16OP_MASK_IMM5
;
956 if ((op
->pinfo
& MIPS16_INSN_READ_PC
) == 0
957 && (op
->pinfo
& MIPS16_INSN_READ_SP
) == 0)
959 info
->insn_type
= dis_dref
;
966 immed
= (l
>> MIPS16OP_SH_IMM5
) & MIPS16OP_MASK_IMM5
;
967 info
->insn_type
= dis_dref
;
972 immed
= (l
>> MIPS16OP_SH_IMM5
) & MIPS16OP_MASK_IMM5
;
977 immed
= (l
>> MIPS16OP_SH_IMM6
) & MIPS16OP_MASK_IMM6
;
981 immed
= (l
>> MIPS16OP_SH_IMM8
) & MIPS16OP_MASK_IMM8
;
986 immed
= (l
>> MIPS16OP_SH_IMM8
) & MIPS16OP_MASK_IMM8
;
987 /* FIXME: This might be lw, or it might be addiu to $sp or
988 $pc. We assume it's load. */
989 info
->insn_type
= dis_dref
;
995 immed
= (l
>> MIPS16OP_SH_IMM8
) & MIPS16OP_MASK_IMM8
;
996 info
->insn_type
= dis_dref
;
1001 immed
= (l
>> MIPS16OP_SH_IMM8
) & MIPS16OP_MASK_IMM8
;
1006 immed
= (l
>> MIPS16OP_SH_IMM8
) & MIPS16OP_MASK_IMM8
;
1012 immed
= (l
>> MIPS16OP_SH_IMM8
) & MIPS16OP_MASK_IMM8
;
1017 immed
= (l
>> MIPS16OP_SH_IMM8
) & MIPS16OP_MASK_IMM8
;
1021 info
->insn_type
= dis_condbranch
;
1025 immed
= (l
>> MIPS16OP_SH_IMM11
) & MIPS16OP_MASK_IMM11
;
1029 info
->insn_type
= dis_branch
;
1034 immed
= (l
>> MIPS16OP_SH_IMM8
) & MIPS16OP_MASK_IMM8
;
1036 /* FIXME: This can be lw or la. We assume it is lw. */
1037 info
->insn_type
= dis_dref
;
1038 info
->data_size
= 4;
1043 immed
= (l
>> MIPS16OP_SH_IMM5
) & MIPS16OP_MASK_IMM5
;
1045 info
->insn_type
= dis_dref
;
1046 info
->data_size
= 8;
1051 immed
= (l
>> MIPS16OP_SH_IMM5
) & MIPS16OP_MASK_IMM5
;
1060 if (signedp
&& immed
>= (1 << (nbits
- 1)))
1061 immed
-= 1 << nbits
;
1063 if ((type
== '<' || type
== '>' || type
== '[' || type
== '[')
1070 immed
|= ((extend
& 0x1f) << 11) | (extend
& 0x7e0);
1071 else if (extbits
== 15)
1072 immed
|= ((extend
& 0xf) << 11) | (extend
& 0x7f0);
1074 immed
= ((extend
>> 6) & 0x1f) | (extend
& 0x20);
1075 immed
&= (1 << extbits
) - 1;
1076 if (! extu
&& immed
>= (1 << (extbits
- 1)))
1077 immed
-= 1 << extbits
;
1081 (*info
->fprintf_func
) (info
->stream
, "%d", immed
);
1090 baseaddr
= memaddr
+ 2;
1092 else if (use_extend
)
1093 baseaddr
= memaddr
- 2;
1101 /* If this instruction is in the delay slot of a jr
1102 instruction, the base address is the address of the
1103 jr instruction. If it is in the delay slot of jalr
1104 instruction, the base address is the address of the
1105 jalr instruction. This test is unreliable: we have
1106 no way of knowing whether the previous word is
1107 instruction or data. */
1108 status
= (*info
->read_memory_func
) (memaddr
- 4, buffer
, 2,
1111 && (((info
->endian
== BFD_ENDIAN_BIG
1112 ? bfd_getb16 (buffer
)
1113 : bfd_getl16 (buffer
))
1114 & 0xf800) == 0x1800))
1115 baseaddr
= memaddr
- 4;
1118 status
= (*info
->read_memory_func
) (memaddr
- 2, buffer
,
1121 && (((info
->endian
== BFD_ENDIAN_BIG
1122 ? bfd_getb16 (buffer
)
1123 : bfd_getl16 (buffer
))
1124 & 0xf81f) == 0xe800))
1125 baseaddr
= memaddr
- 2;
1128 val
= (baseaddr
& ~ ((1 << shift
) - 1)) + immed
;
1129 (*info
->print_address_func
) (val
, info
);
1138 l
= ((l
& 0x1f) << 23) | ((l
& 0x3e0) << 13) | (extend
<< 2);
1139 (*info
->print_address_func
) ((memaddr
& 0xf0000000) | l
, info
);
1140 info
->insn_type
= dis_jsr
;
1141 info
->target
= (memaddr
& 0xf0000000) | l
;
1142 info
->branch_delay_insns
= 1;
1148 int need_comma
, amask
, smask
;
1152 l
= (l
>> MIPS16OP_SH_IMM6
) & MIPS16OP_MASK_IMM6
;
1154 amask
= (l
>> 3) & 7;
1156 if (amask
> 0 && amask
< 5)
1158 (*info
->fprintf_func
) (info
->stream
, "$%s", reg_names
[4]);
1160 (*info
->fprintf_func
) (info
->stream
, "-$%s",
1161 reg_names
[amask
+ 3]);
1165 smask
= (l
>> 1) & 3;
1168 (*info
->fprintf_func
) (info
->stream
, "%s??",
1169 need_comma
? "," : "");
1174 (*info
->fprintf_func
) (info
->stream
, "%s$%s",
1175 need_comma
? "," : "",
1178 (*info
->fprintf_func
) (info
->stream
, "-$%s",
1179 reg_names
[smask
+ 15]);
1185 (*info
->fprintf_func
) (info
->stream
, "%s$%s",
1186 need_comma
? "," : "",
1191 if (amask
== 5 || amask
== 6)
1193 (*info
->fprintf_func
) (info
->stream
, "%s$f0",
1194 need_comma
? "," : "");
1196 (*info
->fprintf_func
) (info
->stream
, "-$f1");
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