1 /* Print mips instructions for GDB, the GNU debugger, or for objdump.
2 Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
4 Free Software Foundation, Inc.
5 Contributed by Nobuyuki Hikichi(hikichi@sra.co.jp).
7 This file is part of GDB, GAS, and the GNU binutils.
9 This program is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 2 of the License, or
12 (at your option) any later version.
14 This program is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with this program; if not, write to the Free Software
21 Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
25 #include "opcode/mips.h"
28 /* FIXME: These are needed to figure out if the code is mips16 or
29 not. The low bit of the address is often a good indicator. No
30 symbol table is available when this code runs out in an embedded
31 system as when it is used for disassembler support in a monitor. */
33 #if !defined(EMBEDDED_ENV)
34 #define SYMTAB_AVAILABLE 1
39 /* Mips instructions are at maximum this many bytes long. */
42 static int _print_insn_mips
43 PARAMS ((bfd_vma
, struct disassemble_info
*, enum bfd_endian
));
44 static int print_insn_mips
45 PARAMS ((bfd_vma
, unsigned long int, struct disassemble_info
*));
46 static void print_insn_arg
47 PARAMS ((const char *, unsigned long, bfd_vma
, struct disassemble_info
*));
48 static void mips_isa_type
49 PARAMS ((int, int *, int *));
50 static int print_insn_mips16
51 PARAMS ((bfd_vma
, struct disassemble_info
*));
53 PARAMS ((Elf_Internal_Ehdr
*));
54 static void print_mips16_insn_arg
55 PARAMS ((int, const struct mips_opcode
*, int, boolean
, int, bfd_vma
,
56 struct disassemble_info
*));
58 /* FIXME: These should be shared with gdb somehow. */
60 /* The mips16 register names. */
61 static const char * const mips16_reg_names
[] = {
62 "s0", "s1", "v0", "v1", "a0", "a1", "a2", "a3"
65 static const char * const mips32_reg_names
[] = {
66 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
67 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7",
68 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
69 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra",
70 "sr", "lo", "hi", "bad", "cause", "pc",
71 "fv0", "$f1", "fv1", "$f3", "ft0", "$f5", "ft1", "$f7",
72 "ft2", "$f9", "ft3", "$f11", "fa0", "$f13", "fa1", "$f15",
73 "ft4", "f17", "ft5", "f19", "fs0", "f21", "fs1", "f23",
74 "fs2", "$f25", "fs3", "$f27", "fs4", "$f29", "fs5", "$f31",
75 "fsr", "fir", "fp", "inx", "rand", "tlblo", "ctxt", "tlbhi",
79 static const char * const mips64_reg_names
[] = {
80 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
81 "a4", "a5", "a6", "a7", "t0", "t1", "t2", "t3",
82 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
83 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra",
84 "sr", "lo", "hi", "bad", "cause", "pc",
85 "fv0", "$f1", "fv1", "$f3", "ft0", "ft1", "ft2", "ft3",
86 "ft4", "ft5", "ft6", "ft7", "fa0", "fa1", "fa2", "fa3",
87 "fa4", "fa5", "fa6", "fa7", "ft8", "ft9", "ft10", "ft11",
88 "fs0", "fs1", "fs2", "fs3", "fs4", "fs5", "fs6", "fs7",
89 "fsr", "fir", "fp", "inx", "rand", "tlblo", "ctxt", "tlbhi",
93 /* Scalar register names. _print_insn_mips() decides which register name
95 static const char * const *reg_names
= NULL
;
97 /* Print insn arguments for 32/64-bit code. */
100 print_insn_arg (d
, l
, pc
, info
)
102 register unsigned long int l
;
104 struct disassemble_info
*info
;
113 (*info
->fprintf_func
) (info
->stream
, "%c", *d
);
120 (*info
->fprintf_func
) (info
->stream
, "%s",
121 reg_names
[(l
>> OP_SH_RS
) & OP_MASK_RS
]);
126 (*info
->fprintf_func
) (info
->stream
, "%s",
127 reg_names
[(l
>> OP_SH_RT
) & OP_MASK_RT
]);
132 (*info
->fprintf_func
) (info
->stream
, "0x%x",
133 (l
>> OP_SH_IMMEDIATE
) & OP_MASK_IMMEDIATE
);
136 case 'j': /* Same as i, but sign-extended. */
138 delta
= (l
>> OP_SH_DELTA
) & OP_MASK_DELTA
;
141 (*info
->fprintf_func
) (info
->stream
, "%d",
146 (*info
->fprintf_func
) (info
->stream
, "0x%x",
147 (unsigned int) ((l
>> OP_SH_PREFX
)
152 (*info
->fprintf_func
) (info
->stream
, "0x%x",
153 (unsigned int) ((l
>> OP_SH_CACHE
)
158 info
->target
= (((pc
+ 4) & ~(bfd_vma
) 0x0fffffff)
159 | (((l
>> OP_SH_TARGET
) & OP_MASK_TARGET
) << 2));
160 (*info
->print_address_func
) (info
->target
, info
);
164 /* Sign extend the displacement. */
165 delta
= (l
>> OP_SH_DELTA
) & OP_MASK_DELTA
;
168 info
->target
= (delta
<< 2) + pc
+ INSNLEN
;
169 (*info
->print_address_func
) (info
->target
, info
);
173 (*info
->fprintf_func
) (info
->stream
, "%s",
174 reg_names
[(l
>> OP_SH_RD
) & OP_MASK_RD
]);
179 /* First check for both rd and rt being equal. */
180 unsigned int reg
= (l
>> OP_SH_RD
) & OP_MASK_RD
;
181 if (reg
== ((l
>> OP_SH_RT
) & OP_MASK_RT
))
182 (*info
->fprintf_func
) (info
->stream
, "%s",
186 /* If one is zero use the other. */
188 (*info
->fprintf_func
) (info
->stream
, "%s",
189 reg_names
[(l
>> OP_SH_RT
) & OP_MASK_RT
]);
190 else if (((l
>> OP_SH_RT
) & OP_MASK_RT
) == 0)
191 (*info
->fprintf_func
) (info
->stream
, "%s",
193 else /* Bogus, result depends on processor. */
194 (*info
->fprintf_func
) (info
->stream
, "%s or %s",
196 reg_names
[(l
>> OP_SH_RT
) & OP_MASK_RT
]);
202 (*info
->fprintf_func
) (info
->stream
, "%s", reg_names
[0]);
206 (*info
->fprintf_func
) (info
->stream
, "0x%x",
207 (l
>> OP_SH_SHAMT
) & OP_MASK_SHAMT
);
211 (*info
->fprintf_func
) (info
->stream
, "0x%x",
212 (l
>> OP_SH_CODE
) & OP_MASK_CODE
);
216 (*info
->fprintf_func
) (info
->stream
, "0x%x",
217 (l
>> OP_SH_CODE2
) & OP_MASK_CODE2
);
221 (*info
->fprintf_func
) (info
->stream
, "0x%x",
222 (l
>> OP_SH_COPZ
) & OP_MASK_COPZ
);
226 (*info
->fprintf_func
) (info
->stream
, "0x%x",
227 (l
>> OP_SH_CODE20
) & OP_MASK_CODE20
);
231 (*info
->fprintf_func
) (info
->stream
, "0x%x",
232 (l
>> OP_SH_CODE19
) & OP_MASK_CODE19
);
237 (*info
->fprintf_func
) (info
->stream
, "$f%d",
238 (l
>> OP_SH_FS
) & OP_MASK_FS
);
243 (*info
->fprintf_func
) (info
->stream
, "$f%d",
244 (l
>> OP_SH_FT
) & OP_MASK_FT
);
248 (*info
->fprintf_func
) (info
->stream
, "$f%d",
249 (l
>> OP_SH_FD
) & OP_MASK_FD
);
253 (*info
->fprintf_func
) (info
->stream
, "$f%d",
254 (l
>> OP_SH_FR
) & OP_MASK_FR
);
258 (*info
->fprintf_func
) (info
->stream
, "$%d",
259 (l
>> OP_SH_RT
) & OP_MASK_RT
);
263 (*info
->fprintf_func
) (info
->stream
, "$%d",
264 (l
>> OP_SH_RD
) & OP_MASK_RD
);
268 (*info
->fprintf_func
) (info
->stream
, "$fcc%d",
269 (l
>> OP_SH_BCC
) & OP_MASK_BCC
);
273 (*info
->fprintf_func
) (info
->stream
, "$fcc%d",
274 (l
>> OP_SH_CCC
) & OP_MASK_CCC
);
278 (*info
->fprintf_func
) (info
->stream
, "%d",
279 (l
>> OP_SH_PERFREG
) & OP_MASK_PERFREG
);
283 (*info
->fprintf_func
) (info
->stream
, "%d",
284 (l
>> OP_SH_SEL
) & OP_MASK_SEL
);
288 (*info
->fprintf_func
) (info
->stream
, "%d",
289 (l
>> OP_SH_ALN
) & OP_MASK_ALN
);
294 unsigned int vsel
= (l
>> OP_SH_VSEL
) & OP_MASK_VSEL
;
295 if ((vsel
& 0x10) == 0)
299 for (fmt
= 0; fmt
< 3; fmt
++, vsel
>>= 1)
302 (*info
->fprintf_func
) (info
->stream
, "$v%d[%d]",
303 (l
>> OP_SH_FT
) & OP_MASK_FT
,
306 else if ((vsel
& 0x08) == 0)
308 (*info
->fprintf_func
) (info
->stream
, "$v%d",
309 (l
>> OP_SH_FT
) & OP_MASK_FT
);
313 (*info
->fprintf_func
) (info
->stream
, "0x%x",
314 (l
>> OP_SH_FT
) & OP_MASK_FT
);
320 (*info
->fprintf_func
) (info
->stream
, "$v%d",
321 (l
>> OP_SH_FD
) & OP_MASK_FD
);
325 (*info
->fprintf_func
) (info
->stream
, "$v%d",
326 (l
>> OP_SH_FS
) & OP_MASK_FS
);
330 (*info
->fprintf_func
) (info
->stream
, "$v%d",
331 (l
>> OP_SH_FT
) & OP_MASK_FT
);
335 /* xgettext:c-format */
336 (*info
->fprintf_func
) (info
->stream
,
337 _("# internal error, undefined modifier(%c)"),
343 /* Figure out the MIPS ISA and CPU based on the machine number. */
346 mips_isa_type (mach
, isa
, cputype
)
353 case bfd_mach_mips3000
:
354 *cputype
= CPU_R3000
;
357 case bfd_mach_mips3900
:
358 *cputype
= CPU_R3900
;
361 case bfd_mach_mips4000
:
362 *cputype
= CPU_R4000
;
365 case bfd_mach_mips4010
:
366 *cputype
= CPU_R4010
;
369 case bfd_mach_mips4100
:
370 *cputype
= CPU_VR4100
;
373 case bfd_mach_mips4111
:
374 *cputype
= CPU_R4111
;
377 case bfd_mach_mips4300
:
378 *cputype
= CPU_R4300
;
381 case bfd_mach_mips4400
:
382 *cputype
= CPU_R4400
;
385 case bfd_mach_mips4600
:
386 *cputype
= CPU_R4600
;
389 case bfd_mach_mips4650
:
390 *cputype
= CPU_R4650
;
393 case bfd_mach_mips5000
:
394 *cputype
= CPU_R5000
;
397 case bfd_mach_mips6000
:
398 *cputype
= CPU_R6000
;
401 case bfd_mach_mips8000
:
402 *cputype
= CPU_R8000
;
405 case bfd_mach_mips10000
:
406 *cputype
= CPU_R10000
;
409 case bfd_mach_mips12000
:
410 *cputype
= CPU_R12000
;
413 case bfd_mach_mips16
:
414 *cputype
= CPU_MIPS16
;
415 *isa
= ISA_MIPS3
| INSN_MIPS16
;
418 *cputype
= CPU_MIPS5
;
421 case bfd_mach_mips_sb1
:
423 *isa
= ISA_MIPS64
| INSN_MIPS3D
| INSN_SB1
;
425 case bfd_mach_mipsisa32
:
426 *cputype
= CPU_MIPS32
;
427 /* For stock MIPS32, disassemble all applicable MIPS-specified ASEs.
428 Note that MIPS-3D and MDMX are not applicable to MIPS32. (See
429 _MIPS32 Architecture For Programmers Volume I: Introduction to the
430 MIPS32 Architecture_ (MIPS Document Number MD00082, Revision 0.95),
432 *isa
= ISA_MIPS32
| INSN_MIPS16
;
434 case bfd_mach_mipsisa64
:
435 *cputype
= CPU_MIPS64
;
436 /* For stock MIPS64, disassemble all applicable MIPS-specified ASEs. */
437 *isa
= ISA_MIPS64
| INSN_MIPS16
| INSN_MIPS3D
| INSN_MDMX
;
441 *cputype
= CPU_R3000
;
447 /* Check if the object uses NewABI conventions. */
451 Elf_Internal_Ehdr
*header
;
453 /* There are no old-style ABIs which use 64-bit ELF. */
454 if (header
->e_ident
[EI_CLASS
] == ELFCLASS64
)
457 /* If a 32-bit ELF file, n32 is a new-style ABI. */
458 if ((header
->e_flags
& EF_MIPS_ABI2
) != 0)
464 /* Print the mips instruction at address MEMADDR in debugged memory,
465 on using INFO. Returns length of the instruction, in bytes, which is
466 always INSNLEN. BIGENDIAN must be 1 if this is big-endian code, 0 if
467 this is little-endian code. */
470 print_insn_mips (memaddr
, word
, info
)
472 unsigned long int word
;
473 struct disassemble_info
*info
;
475 register const struct mips_opcode
*op
;
476 int target_processor
, mips_isa
;
477 static boolean init
= 0;
478 static const struct mips_opcode
*mips_hash
[OP_MASK_OP
+ 1];
480 /* Build a hash table to shorten the search time. */
485 for (i
= 0; i
<= OP_MASK_OP
; i
++)
487 for (op
= mips_opcodes
; op
< &mips_opcodes
[NUMOPCODES
]; op
++)
489 if (op
->pinfo
== INSN_MACRO
)
491 if (i
== ((op
->match
>> OP_SH_OP
) & OP_MASK_OP
))
502 #if ! SYMTAB_AVAILABLE
503 /* This is running out on a target machine, not in a host tool.
504 FIXME: Where does mips_target_info come from? */
505 target_processor
= mips_target_info
.processor
;
506 mips_isa
= mips_target_info
.isa
;
508 mips_isa_type (info
->mach
, &mips_isa
, &target_processor
);
511 info
->bytes_per_chunk
= INSNLEN
;
512 info
->display_endian
= info
->endian
;
513 info
->insn_info_valid
= 1;
514 info
->branch_delay_insns
= 0;
516 info
->insn_type
= dis_nonbranch
;
520 op
= mips_hash
[(word
>> OP_SH_OP
) & OP_MASK_OP
];
523 for (; op
< &mips_opcodes
[NUMOPCODES
]; op
++)
525 if (op
->pinfo
!= INSN_MACRO
&& (word
& op
->mask
) == op
->match
)
527 register const char *d
;
529 /* We always allow to disassemble the jalx instruction. */
530 if (! OPCODE_IS_MEMBER (op
, mips_isa
, target_processor
)
531 && strcmp (op
->name
, "jalx"))
534 /* Figure out instruction type and branch delay information. */
535 if ((op
->pinfo
& INSN_UNCOND_BRANCH_DELAY
) != 0)
537 if ((info
->insn_type
& INSN_WRITE_GPR_31
) != 0)
538 info
->insn_type
= dis_jsr
;
540 info
->insn_type
= dis_branch
;
541 info
->branch_delay_insns
= 1;
543 else if ((op
->pinfo
& (INSN_COND_BRANCH_DELAY
544 | INSN_COND_BRANCH_LIKELY
)) != 0)
546 if ((info
->insn_type
& INSN_WRITE_GPR_31
) != 0)
547 info
->insn_type
= dis_condjsr
;
549 info
->insn_type
= dis_condbranch
;
550 info
->branch_delay_insns
= 1;
552 else if ((op
->pinfo
& (INSN_STORE_MEMORY
553 | INSN_LOAD_MEMORY_DELAY
)) != 0)
554 info
->insn_type
= dis_dref
;
556 (*info
->fprintf_func
) (info
->stream
, "%s", op
->name
);
559 if (d
!= NULL
&& *d
!= '\0')
561 (*info
->fprintf_func
) (info
->stream
, "\t");
562 for (; *d
!= '\0'; d
++)
563 print_insn_arg (d
, word
, memaddr
, info
);
571 /* Handle undefined instructions. */
572 info
->insn_type
= dis_noninsn
;
573 (*info
->fprintf_func
) (info
->stream
, "0x%x", word
);
577 /* In an environment where we do not know the symbol type of the
578 instruction we are forced to assume that the low order bit of the
579 instructions' address may mark it as a mips16 instruction. If we
580 are single stepping, or the pc is within the disassembled function,
581 this works. Otherwise, we need a clue. Sometimes. */
584 _print_insn_mips (memaddr
, info
, endianness
)
586 struct disassemble_info
*info
;
587 enum bfd_endian endianness
;
589 bfd_byte buffer
[INSNLEN
];
593 /* FIXME: If odd address, this is CLEARLY a mips 16 instruction. */
594 /* Only a few tools will work this way. */
596 return print_insn_mips16 (memaddr
, info
);
600 if (info
->mach
== bfd_mach_mips16
601 || (info
->flavour
== bfd_target_elf_flavour
602 && info
->symbols
!= NULL
603 && ((*(elf_symbol_type
**) info
->symbols
)->internal_elf_sym
.st_other
605 return print_insn_mips16 (memaddr
, info
);
608 /* Use mips64_reg_names for new ABI. */
609 reg_names
= mips32_reg_names
;
611 if (info
->flavour
== bfd_target_elf_flavour
&& info
->symbols
!= NULL
)
613 Elf_Internal_Ehdr
*header
;
615 header
= elf_elfheader (bfd_asymbol_bfd (*(info
->symbols
)));
616 if (is_newabi (header
))
617 reg_names
= mips64_reg_names
;
620 status
= (*info
->read_memory_func
) (memaddr
, buffer
, INSNLEN
, info
);
625 if (endianness
== BFD_ENDIAN_BIG
)
626 insn
= (unsigned long) bfd_getb32 (buffer
);
628 insn
= (unsigned long) bfd_getl32 (buffer
);
630 return print_insn_mips (memaddr
, insn
, info
);
634 (*info
->memory_error_func
) (status
, memaddr
, info
);
640 print_insn_big_mips (memaddr
, info
)
642 struct disassemble_info
*info
;
644 return _print_insn_mips (memaddr
, info
, BFD_ENDIAN_BIG
);
648 print_insn_little_mips (memaddr
, info
)
650 struct disassemble_info
*info
;
652 return _print_insn_mips (memaddr
, info
, BFD_ENDIAN_LITTLE
);
655 /* Disassemble mips16 instructions. */
658 print_insn_mips16 (memaddr
, info
)
660 struct disassemble_info
*info
;
668 const struct mips_opcode
*op
, *opend
;
670 info
->bytes_per_chunk
= 2;
671 info
->display_endian
= info
->endian
;
672 info
->insn_info_valid
= 1;
673 info
->branch_delay_insns
= 0;
675 info
->insn_type
= dis_nonbranch
;
679 status
= (*info
->read_memory_func
) (memaddr
, buffer
, 2, info
);
682 (*info
->memory_error_func
) (status
, memaddr
, info
);
688 if (info
->endian
== BFD_ENDIAN_BIG
)
689 insn
= bfd_getb16 (buffer
);
691 insn
= bfd_getl16 (buffer
);
693 /* Handle the extend opcode specially. */
695 if ((insn
& 0xf800) == 0xf000)
698 extend
= insn
& 0x7ff;
702 status
= (*info
->read_memory_func
) (memaddr
, buffer
, 2, info
);
705 (*info
->fprintf_func
) (info
->stream
, "extend 0x%x",
706 (unsigned int) extend
);
707 (*info
->memory_error_func
) (status
, memaddr
, info
);
711 if (info
->endian
== BFD_ENDIAN_BIG
)
712 insn
= bfd_getb16 (buffer
);
714 insn
= bfd_getl16 (buffer
);
716 /* Check for an extend opcode followed by an extend opcode. */
717 if ((insn
& 0xf800) == 0xf000)
719 (*info
->fprintf_func
) (info
->stream
, "extend 0x%x",
720 (unsigned int) extend
);
721 info
->insn_type
= dis_noninsn
;
728 /* FIXME: Should probably use a hash table on the major opcode here. */
730 opend
= mips16_opcodes
+ bfd_mips16_num_opcodes
;
731 for (op
= mips16_opcodes
; op
< opend
; op
++)
733 if (op
->pinfo
!= INSN_MACRO
&& (insn
& op
->mask
) == op
->match
)
737 if (strchr (op
->args
, 'a') != NULL
)
741 (*info
->fprintf_func
) (info
->stream
, "extend 0x%x",
742 (unsigned int) extend
);
743 info
->insn_type
= dis_noninsn
;
751 status
= (*info
->read_memory_func
) (memaddr
, buffer
, 2,
756 if (info
->endian
== BFD_ENDIAN_BIG
)
757 extend
= bfd_getb16 (buffer
);
759 extend
= bfd_getl16 (buffer
);
764 (*info
->fprintf_func
) (info
->stream
, "%s", op
->name
);
765 if (op
->args
[0] != '\0')
766 (*info
->fprintf_func
) (info
->stream
, "\t");
768 for (s
= op
->args
; *s
!= '\0'; s
++)
772 && (((insn
>> MIPS16OP_SH_RX
) & MIPS16OP_MASK_RX
)
773 == ((insn
>> MIPS16OP_SH_RY
) & MIPS16OP_MASK_RY
)))
775 /* Skip the register and the comma. */
781 && (((insn
>> MIPS16OP_SH_RZ
) & MIPS16OP_MASK_RZ
)
782 == ((insn
>> MIPS16OP_SH_RX
) & MIPS16OP_MASK_RX
)))
784 /* Skip the register and the comma. */
788 print_mips16_insn_arg (*s
, op
, insn
, use_extend
, extend
, memaddr
,
792 if ((op
->pinfo
& INSN_UNCOND_BRANCH_DELAY
) != 0)
794 info
->branch_delay_insns
= 1;
795 if (info
->insn_type
!= dis_jsr
)
796 info
->insn_type
= dis_branch
;
804 (*info
->fprintf_func
) (info
->stream
, "0x%x", extend
| 0xf000);
805 (*info
->fprintf_func
) (info
->stream
, "0x%x", insn
);
806 info
->insn_type
= dis_noninsn
;
811 /* Disassemble an operand for a mips16 instruction. */
814 print_mips16_insn_arg (type
, op
, l
, use_extend
, extend
, memaddr
, info
)
816 const struct mips_opcode
*op
;
821 struct disassemble_info
*info
;
828 (*info
->fprintf_func
) (info
->stream
, "%c", type
);
833 (*info
->fprintf_func
) (info
->stream
, "%s",
834 mips16_reg_names
[((l
>> MIPS16OP_SH_RY
)
835 & MIPS16OP_MASK_RY
)]);
840 (*info
->fprintf_func
) (info
->stream
, "%s",
841 mips16_reg_names
[((l
>> MIPS16OP_SH_RX
)
842 & MIPS16OP_MASK_RX
)]);
846 (*info
->fprintf_func
) (info
->stream
, "%s",
847 mips16_reg_names
[((l
>> MIPS16OP_SH_RZ
)
848 & MIPS16OP_MASK_RZ
)]);
852 (*info
->fprintf_func
) (info
->stream
, "%s",
853 mips16_reg_names
[((l
>> MIPS16OP_SH_MOVE32Z
)
854 & MIPS16OP_MASK_MOVE32Z
)]);
858 (*info
->fprintf_func
) (info
->stream
, "%s", mips32_reg_names
[0]);
862 (*info
->fprintf_func
) (info
->stream
, "%s", mips32_reg_names
[29]);
866 (*info
->fprintf_func
) (info
->stream
, "$pc");
870 (*info
->fprintf_func
) (info
->stream
, "%s", mips32_reg_names
[31]);
874 (*info
->fprintf_func
) (info
->stream
, "%s",
875 mips32_reg_names
[((l
>> MIPS16OP_SH_REGR32
)
876 & MIPS16OP_MASK_REGR32
)]);
880 (*info
->fprintf_func
) (info
->stream
, "%s",
881 mips32_reg_names
[MIPS16OP_EXTRACT_REG32R (l
)]);
907 int immed
, nbits
, shift
, signedp
, extbits
, pcrel
, extu
, branch
;
919 immed
= (l
>> MIPS16OP_SH_RZ
) & MIPS16OP_MASK_RZ
;
925 immed
= (l
>> MIPS16OP_SH_RX
) & MIPS16OP_MASK_RX
;
931 immed
= (l
>> MIPS16OP_SH_RZ
) & MIPS16OP_MASK_RZ
;
937 immed
= (l
>> MIPS16OP_SH_RX
) & MIPS16OP_MASK_RX
;
943 immed
= (l
>> MIPS16OP_SH_IMM4
) & MIPS16OP_MASK_IMM4
;
949 immed
= (l
>> MIPS16OP_SH_IMM5
) & MIPS16OP_MASK_IMM5
;
950 info
->insn_type
= dis_dref
;
956 immed
= (l
>> MIPS16OP_SH_IMM5
) & MIPS16OP_MASK_IMM5
;
957 info
->insn_type
= dis_dref
;
963 immed
= (l
>> MIPS16OP_SH_IMM5
) & MIPS16OP_MASK_IMM5
;
964 if ((op
->pinfo
& MIPS16_INSN_READ_PC
) == 0
965 && (op
->pinfo
& MIPS16_INSN_READ_SP
) == 0)
967 info
->insn_type
= dis_dref
;
974 immed
= (l
>> MIPS16OP_SH_IMM5
) & MIPS16OP_MASK_IMM5
;
975 info
->insn_type
= dis_dref
;
980 immed
= (l
>> MIPS16OP_SH_IMM5
) & MIPS16OP_MASK_IMM5
;
985 immed
= (l
>> MIPS16OP_SH_IMM6
) & MIPS16OP_MASK_IMM6
;
989 immed
= (l
>> MIPS16OP_SH_IMM8
) & MIPS16OP_MASK_IMM8
;
994 immed
= (l
>> MIPS16OP_SH_IMM8
) & MIPS16OP_MASK_IMM8
;
995 /* FIXME: This might be lw, or it might be addiu to $sp or
996 $pc. We assume it's load. */
997 info
->insn_type
= dis_dref
;
1003 immed
= (l
>> MIPS16OP_SH_IMM8
) & MIPS16OP_MASK_IMM8
;
1004 info
->insn_type
= dis_dref
;
1005 info
->data_size
= 8;
1009 immed
= (l
>> MIPS16OP_SH_IMM8
) & MIPS16OP_MASK_IMM8
;
1014 immed
= (l
>> MIPS16OP_SH_IMM8
) & MIPS16OP_MASK_IMM8
;
1020 immed
= (l
>> MIPS16OP_SH_IMM8
) & MIPS16OP_MASK_IMM8
;
1025 immed
= (l
>> MIPS16OP_SH_IMM8
) & MIPS16OP_MASK_IMM8
;
1029 info
->insn_type
= dis_condbranch
;
1033 immed
= (l
>> MIPS16OP_SH_IMM11
) & MIPS16OP_MASK_IMM11
;
1037 info
->insn_type
= dis_branch
;
1042 immed
= (l
>> MIPS16OP_SH_IMM8
) & MIPS16OP_MASK_IMM8
;
1044 /* FIXME: This can be lw or la. We assume it is lw. */
1045 info
->insn_type
= dis_dref
;
1046 info
->data_size
= 4;
1051 immed
= (l
>> MIPS16OP_SH_IMM5
) & MIPS16OP_MASK_IMM5
;
1053 info
->insn_type
= dis_dref
;
1054 info
->data_size
= 8;
1059 immed
= (l
>> MIPS16OP_SH_IMM5
) & MIPS16OP_MASK_IMM5
;
1068 if (signedp
&& immed
>= (1 << (nbits
- 1)))
1069 immed
-= 1 << nbits
;
1071 if ((type
== '<' || type
== '>' || type
== '[' || type
== ']')
1078 immed
|= ((extend
& 0x1f) << 11) | (extend
& 0x7e0);
1079 else if (extbits
== 15)
1080 immed
|= ((extend
& 0xf) << 11) | (extend
& 0x7f0);
1082 immed
= ((extend
>> 6) & 0x1f) | (extend
& 0x20);
1083 immed
&= (1 << extbits
) - 1;
1084 if (! extu
&& immed
>= (1 << (extbits
- 1)))
1085 immed
-= 1 << extbits
;
1089 (*info
->fprintf_func
) (info
->stream
, "%d", immed
);
1097 baseaddr
= memaddr
+ 2;
1099 else if (use_extend
)
1100 baseaddr
= memaddr
- 2;
1108 /* If this instruction is in the delay slot of a jr
1109 instruction, the base address is the address of the
1110 jr instruction. If it is in the delay slot of jalr
1111 instruction, the base address is the address of the
1112 jalr instruction. This test is unreliable: we have
1113 no way of knowing whether the previous word is
1114 instruction or data. */
1115 status
= (*info
->read_memory_func
) (memaddr
- 4, buffer
, 2,
1118 && (((info
->endian
== BFD_ENDIAN_BIG
1119 ? bfd_getb16 (buffer
)
1120 : bfd_getl16 (buffer
))
1121 & 0xf800) == 0x1800))
1122 baseaddr
= memaddr
- 4;
1125 status
= (*info
->read_memory_func
) (memaddr
- 2, buffer
,
1128 && (((info
->endian
== BFD_ENDIAN_BIG
1129 ? bfd_getb16 (buffer
)
1130 : bfd_getl16 (buffer
))
1131 & 0xf81f) == 0xe800))
1132 baseaddr
= memaddr
- 2;
1135 info
->target
= (baseaddr
& ~((1 << shift
) - 1)) + immed
;
1136 (*info
->print_address_func
) (info
->target
, info
);
1144 l
= ((l
& 0x1f) << 23) | ((l
& 0x3e0) << 13) | (extend
<< 2);
1145 info
->target
= ((memaddr
+ 4) & ~(bfd_vma
) 0x0fffffff) | l
;
1146 (*info
->print_address_func
) (info
->target
, info
);
1147 info
->insn_type
= dis_jsr
;
1148 info
->branch_delay_insns
= 1;
1154 int need_comma
, amask
, smask
;
1158 l
= (l
>> MIPS16OP_SH_IMM6
) & MIPS16OP_MASK_IMM6
;
1160 amask
= (l
>> 3) & 7;
1162 if (amask
> 0 && amask
< 5)
1164 (*info
->fprintf_func
) (info
->stream
, "%s", mips32_reg_names
[4]);
1166 (*info
->fprintf_func
) (info
->stream
, "-%s",
1167 mips32_reg_names
[amask
+ 3]);
1171 smask
= (l
>> 1) & 3;
1174 (*info
->fprintf_func
) (info
->stream
, "%s??",
1175 need_comma
? "," : "");
1180 (*info
->fprintf_func
) (info
->stream
, "%s%s",
1181 need_comma
? "," : "",
1182 mips32_reg_names
[16]);
1184 (*info
->fprintf_func
) (info
->stream
, "-%s",
1185 mips32_reg_names
[smask
+ 15]);
1191 (*info
->fprintf_func
) (info
->stream
, "%s%s",
1192 need_comma
? "," : "",
1193 mips32_reg_names
[31]);
1197 if (amask
== 5 || amask
== 6)
1199 (*info
->fprintf_func
) (info
->stream
, "%s$f0",
1200 need_comma
? "," : "");
1202 (*info
->fprintf_func
) (info
->stream
, "-$f1");
1208 /* xgettext:c-format */
1209 (*info
->fprintf_func
)
1211 _("# internal disassembler error, unrecognised modifier (%c)"),
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