1 /* Print mips instructions for GDB, the GNU debugger, or for objdump.
2 Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
3 2000, 2001, 2002, 2003, 2005
4 Free Software Foundation, Inc.
5 Contributed by Nobuyuki Hikichi(hikichi@sra.co.jp).
7 This file is part of GDB, GAS, and the GNU binutils.
9 This program is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 2 of the License, or
12 (at your option) any later version.
14 This program is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with this program; if not, write to the Free Software
21 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
22 MA 02110-1301, USA. */
26 #include "libiberty.h"
27 #include "opcode/mips.h"
30 /* FIXME: These are needed to figure out if the code is mips16 or
31 not. The low bit of the address is often a good indicator. No
32 symbol table is available when this code runs out in an embedded
33 system as when it is used for disassembler support in a monitor. */
35 #if !defined(EMBEDDED_ENV)
36 #define SYMTAB_AVAILABLE 1
41 /* Mips instructions are at maximum this many bytes long. */
45 /* FIXME: These should be shared with gdb somehow. */
47 struct mips_cp0sel_name
51 const char * const name
;
54 /* The mips16 registers. */
55 static const unsigned int mips16_to_32_reg_map
[] =
57 16, 17, 2, 3, 4, 5, 6, 7
60 #define mips16_reg_names(rn) mips_gpr_names[mips16_to_32_reg_map[rn]]
63 static const char * const mips_gpr_names_numeric
[32] =
65 "$0", "$1", "$2", "$3", "$4", "$5", "$6", "$7",
66 "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15",
67 "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23",
68 "$24", "$25", "$26", "$27", "$28", "$29", "$30", "$31"
71 static const char * const mips_gpr_names_oldabi
[32] =
73 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
74 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7",
75 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
76 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra"
79 static const char * const mips_gpr_names_newabi
[32] =
81 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
82 "a4", "a5", "a6", "a7", "t0", "t1", "t2", "t3",
83 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
84 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra"
87 static const char * const mips_fpr_names_numeric
[32] =
89 "$f0", "$f1", "$f2", "$f3", "$f4", "$f5", "$f6", "$f7",
90 "$f8", "$f9", "$f10", "$f11", "$f12", "$f13", "$f14", "$f15",
91 "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23",
92 "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31"
95 static const char * const mips_fpr_names_32
[32] =
97 "fv0", "fv0f", "fv1", "fv1f", "ft0", "ft0f", "ft1", "ft1f",
98 "ft2", "ft2f", "ft3", "ft3f", "fa0", "fa0f", "fa1", "fa1f",
99 "ft4", "ft4f", "ft5", "ft5f", "fs0", "fs0f", "fs1", "fs1f",
100 "fs2", "fs2f", "fs3", "fs3f", "fs4", "fs4f", "fs5", "fs5f"
103 static const char * const mips_fpr_names_n32
[32] =
105 "fv0", "ft14", "fv1", "ft15", "ft0", "ft1", "ft2", "ft3",
106 "ft4", "ft5", "ft6", "ft7", "fa0", "fa1", "fa2", "fa3",
107 "fa4", "fa5", "fa6", "fa7", "fs0", "ft8", "fs1", "ft9",
108 "fs2", "ft10", "fs3", "ft11", "fs4", "ft12", "fs5", "ft13"
111 static const char * const mips_fpr_names_64
[32] =
113 "fv0", "ft12", "fv1", "ft13", "ft0", "ft1", "ft2", "ft3",
114 "ft4", "ft5", "ft6", "ft7", "fa0", "fa1", "fa2", "fa3",
115 "fa4", "fa5", "fa6", "fa7", "ft8", "ft9", "ft10", "ft11",
116 "fs0", "fs1", "fs2", "fs3", "fs4", "fs5", "fs6", "fs7"
119 static const char * const mips_cp0_names_numeric
[32] =
121 "$0", "$1", "$2", "$3", "$4", "$5", "$6", "$7",
122 "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15",
123 "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23",
124 "$24", "$25", "$26", "$27", "$28", "$29", "$30", "$31"
127 static const char * const mips_cp0_names_mips3264
[32] =
129 "c0_index", "c0_random", "c0_entrylo0", "c0_entrylo1",
130 "c0_context", "c0_pagemask", "c0_wired", "$7",
131 "c0_badvaddr", "c0_count", "c0_entryhi", "c0_compare",
132 "c0_status", "c0_cause", "c0_epc", "c0_prid",
133 "c0_config", "c0_lladdr", "c0_watchlo", "c0_watchhi",
134 "c0_xcontext", "$21", "$22", "c0_debug",
135 "c0_depc", "c0_perfcnt", "c0_errctl", "c0_cacheerr",
136 "c0_taglo", "c0_taghi", "c0_errorepc", "c0_desave",
139 static const struct mips_cp0sel_name mips_cp0sel_names_mips3264
[] =
141 { 16, 1, "c0_config1" },
142 { 16, 2, "c0_config2" },
143 { 16, 3, "c0_config3" },
144 { 18, 1, "c0_watchlo,1" },
145 { 18, 2, "c0_watchlo,2" },
146 { 18, 3, "c0_watchlo,3" },
147 { 18, 4, "c0_watchlo,4" },
148 { 18, 5, "c0_watchlo,5" },
149 { 18, 6, "c0_watchlo,6" },
150 { 18, 7, "c0_watchlo,7" },
151 { 19, 1, "c0_watchhi,1" },
152 { 19, 2, "c0_watchhi,2" },
153 { 19, 3, "c0_watchhi,3" },
154 { 19, 4, "c0_watchhi,4" },
155 { 19, 5, "c0_watchhi,5" },
156 { 19, 6, "c0_watchhi,6" },
157 { 19, 7, "c0_watchhi,7" },
158 { 25, 1, "c0_perfcnt,1" },
159 { 25, 2, "c0_perfcnt,2" },
160 { 25, 3, "c0_perfcnt,3" },
161 { 25, 4, "c0_perfcnt,4" },
162 { 25, 5, "c0_perfcnt,5" },
163 { 25, 6, "c0_perfcnt,6" },
164 { 25, 7, "c0_perfcnt,7" },
165 { 27, 1, "c0_cacheerr,1" },
166 { 27, 2, "c0_cacheerr,2" },
167 { 27, 3, "c0_cacheerr,3" },
168 { 28, 1, "c0_datalo" },
169 { 29, 1, "c0_datahi" }
172 static const char * const mips_cp0_names_mips3264r2
[32] =
174 "c0_index", "c0_random", "c0_entrylo0", "c0_entrylo1",
175 "c0_context", "c0_pagemask", "c0_wired", "c0_hwrena",
176 "c0_badvaddr", "c0_count", "c0_entryhi", "c0_compare",
177 "c0_status", "c0_cause", "c0_epc", "c0_prid",
178 "c0_config", "c0_lladdr", "c0_watchlo", "c0_watchhi",
179 "c0_xcontext", "$21", "$22", "c0_debug",
180 "c0_depc", "c0_perfcnt", "c0_errctl", "c0_cacheerr",
181 "c0_taglo", "c0_taghi", "c0_errorepc", "c0_desave",
184 static const struct mips_cp0sel_name mips_cp0sel_names_mips3264r2
[] =
186 { 4, 1, "c0_contextconfig" },
187 { 0, 1, "c0_mvpcontrol" },
188 { 0, 2, "c0_mvpconf0" },
189 { 0, 3, "c0_mvpconf1" },
190 { 1, 1, "c0_vpecontrol" },
191 { 1, 2, "c0_vpeconf0" },
192 { 1, 3, "c0_vpeconf1" },
193 { 1, 4, "c0_yqmask" },
194 { 1, 5, "c0_vpeschedule" },
195 { 1, 6, "c0_vpeschefback" },
196 { 2, 1, "c0_tcstatus" },
197 { 2, 2, "c0_tcbind" },
198 { 2, 3, "c0_tcrestart" },
199 { 2, 4, "c0_tchalt" },
200 { 2, 5, "c0_tccontext" },
201 { 2, 6, "c0_tcschedule" },
202 { 2, 7, "c0_tcschefback" },
203 { 5, 1, "c0_pagegrain" },
204 { 6, 1, "c0_srsconf0" },
205 { 6, 2, "c0_srsconf1" },
206 { 6, 3, "c0_srsconf2" },
207 { 6, 4, "c0_srsconf3" },
208 { 6, 5, "c0_srsconf4" },
209 { 12, 1, "c0_intctl" },
210 { 12, 2, "c0_srsctl" },
211 { 12, 3, "c0_srsmap" },
212 { 15, 1, "c0_ebase" },
213 { 16, 1, "c0_config1" },
214 { 16, 2, "c0_config2" },
215 { 16, 3, "c0_config3" },
216 { 18, 1, "c0_watchlo,1" },
217 { 18, 2, "c0_watchlo,2" },
218 { 18, 3, "c0_watchlo,3" },
219 { 18, 4, "c0_watchlo,4" },
220 { 18, 5, "c0_watchlo,5" },
221 { 18, 6, "c0_watchlo,6" },
222 { 18, 7, "c0_watchlo,7" },
223 { 19, 1, "c0_watchhi,1" },
224 { 19, 2, "c0_watchhi,2" },
225 { 19, 3, "c0_watchhi,3" },
226 { 19, 4, "c0_watchhi,4" },
227 { 19, 5, "c0_watchhi,5" },
228 { 19, 6, "c0_watchhi,6" },
229 { 19, 7, "c0_watchhi,7" },
230 { 23, 1, "c0_tracecontrol" },
231 { 23, 2, "c0_tracecontrol2" },
232 { 23, 3, "c0_usertracedata" },
233 { 23, 4, "c0_tracebpc" },
234 { 25, 1, "c0_perfcnt,1" },
235 { 25, 2, "c0_perfcnt,2" },
236 { 25, 3, "c0_perfcnt,3" },
237 { 25, 4, "c0_perfcnt,4" },
238 { 25, 5, "c0_perfcnt,5" },
239 { 25, 6, "c0_perfcnt,6" },
240 { 25, 7, "c0_perfcnt,7" },
241 { 27, 1, "c0_cacheerr,1" },
242 { 27, 2, "c0_cacheerr,2" },
243 { 27, 3, "c0_cacheerr,3" },
244 { 28, 1, "c0_datalo" },
245 { 28, 2, "c0_taglo1" },
246 { 28, 3, "c0_datalo1" },
247 { 28, 4, "c0_taglo2" },
248 { 28, 5, "c0_datalo2" },
249 { 28, 6, "c0_taglo3" },
250 { 28, 7, "c0_datalo3" },
251 { 29, 1, "c0_datahi" },
252 { 29, 2, "c0_taghi1" },
253 { 29, 3, "c0_datahi1" },
254 { 29, 4, "c0_taghi2" },
255 { 29, 5, "c0_datahi2" },
256 { 29, 6, "c0_taghi3" },
257 { 29, 7, "c0_datahi3" },
260 /* SB-1: MIPS64 (mips_cp0_names_mips3264) with minor mods. */
261 static const char * const mips_cp0_names_sb1
[32] =
263 "c0_index", "c0_random", "c0_entrylo0", "c0_entrylo1",
264 "c0_context", "c0_pagemask", "c0_wired", "$7",
265 "c0_badvaddr", "c0_count", "c0_entryhi", "c0_compare",
266 "c0_status", "c0_cause", "c0_epc", "c0_prid",
267 "c0_config", "c0_lladdr", "c0_watchlo", "c0_watchhi",
268 "c0_xcontext", "$21", "$22", "c0_debug",
269 "c0_depc", "c0_perfcnt", "c0_errctl", "c0_cacheerr_i",
270 "c0_taglo_i", "c0_taghi_i", "c0_errorepc", "c0_desave",
273 static const struct mips_cp0sel_name mips_cp0sel_names_sb1
[] =
275 { 16, 1, "c0_config1" },
276 { 18, 1, "c0_watchlo,1" },
277 { 19, 1, "c0_watchhi,1" },
278 { 22, 0, "c0_perftrace" },
279 { 23, 3, "c0_edebug" },
280 { 25, 1, "c0_perfcnt,1" },
281 { 25, 2, "c0_perfcnt,2" },
282 { 25, 3, "c0_perfcnt,3" },
283 { 25, 4, "c0_perfcnt,4" },
284 { 25, 5, "c0_perfcnt,5" },
285 { 25, 6, "c0_perfcnt,6" },
286 { 25, 7, "c0_perfcnt,7" },
287 { 26, 1, "c0_buserr_pa" },
288 { 27, 1, "c0_cacheerr_d" },
289 { 27, 3, "c0_cacheerr_d_pa" },
290 { 28, 1, "c0_datalo_i" },
291 { 28, 2, "c0_taglo_d" },
292 { 28, 3, "c0_datalo_d" },
293 { 29, 1, "c0_datahi_i" },
294 { 29, 2, "c0_taghi_d" },
295 { 29, 3, "c0_datahi_d" },
298 static const char * const mips_hwr_names_numeric
[32] =
300 "$0", "$1", "$2", "$3", "$4", "$5", "$6", "$7",
301 "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15",
302 "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23",
303 "$24", "$25", "$26", "$27", "$28", "$29", "$30", "$31"
306 static const char * const mips_hwr_names_mips3264r2
[32] =
308 "hwr_cpunum", "hwr_synci_step", "hwr_cc", "hwr_ccres",
309 "$4", "$5", "$6", "$7",
310 "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15",
311 "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23",
312 "$24", "$25", "$26", "$27", "$28", "$29", "$30", "$31"
315 struct mips_abi_choice
318 const char * const *gpr_names
;
319 const char * const *fpr_names
;
322 struct mips_abi_choice mips_abi_choices
[] =
324 { "numeric", mips_gpr_names_numeric
, mips_fpr_names_numeric
},
325 { "32", mips_gpr_names_oldabi
, mips_fpr_names_32
},
326 { "n32", mips_gpr_names_newabi
, mips_fpr_names_n32
},
327 { "64", mips_gpr_names_newabi
, mips_fpr_names_64
},
330 struct mips_arch_choice
334 unsigned long bfd_mach
;
337 const char * const *cp0_names
;
338 const struct mips_cp0sel_name
*cp0sel_names
;
339 unsigned int cp0sel_names_len
;
340 const char * const *hwr_names
;
343 const struct mips_arch_choice mips_arch_choices
[] =
345 { "numeric", 0, 0, 0, 0,
346 mips_cp0_names_numeric
, NULL
, 0, mips_hwr_names_numeric
},
348 { "r3000", 1, bfd_mach_mips3000
, CPU_R3000
, ISA_MIPS1
,
349 mips_cp0_names_numeric
, NULL
, 0, mips_hwr_names_numeric
},
350 { "r3900", 1, bfd_mach_mips3900
, CPU_R3900
, ISA_MIPS1
,
351 mips_cp0_names_numeric
, NULL
, 0, mips_hwr_names_numeric
},
352 { "r4000", 1, bfd_mach_mips4000
, CPU_R4000
, ISA_MIPS3
,
353 mips_cp0_names_numeric
, NULL
, 0, mips_hwr_names_numeric
},
354 { "r4010", 1, bfd_mach_mips4010
, CPU_R4010
, ISA_MIPS2
,
355 mips_cp0_names_numeric
, NULL
, 0, mips_hwr_names_numeric
},
356 { "vr4100", 1, bfd_mach_mips4100
, CPU_VR4100
, ISA_MIPS3
,
357 mips_cp0_names_numeric
, NULL
, 0, mips_hwr_names_numeric
},
358 { "vr4111", 1, bfd_mach_mips4111
, CPU_R4111
, ISA_MIPS3
,
359 mips_cp0_names_numeric
, NULL
, 0, mips_hwr_names_numeric
},
360 { "vr4120", 1, bfd_mach_mips4120
, CPU_VR4120
, ISA_MIPS3
,
361 mips_cp0_names_numeric
, NULL
, 0, mips_hwr_names_numeric
},
362 { "r4300", 1, bfd_mach_mips4300
, CPU_R4300
, ISA_MIPS3
,
363 mips_cp0_names_numeric
, NULL
, 0, mips_hwr_names_numeric
},
364 { "r4400", 1, bfd_mach_mips4400
, CPU_R4400
, ISA_MIPS3
,
365 mips_cp0_names_numeric
, NULL
, 0, mips_hwr_names_numeric
},
366 { "r4600", 1, bfd_mach_mips4600
, CPU_R4600
, ISA_MIPS3
,
367 mips_cp0_names_numeric
, NULL
, 0, mips_hwr_names_numeric
},
368 { "r4650", 1, bfd_mach_mips4650
, CPU_R4650
, ISA_MIPS3
,
369 mips_cp0_names_numeric
, NULL
, 0, mips_hwr_names_numeric
},
370 { "r5000", 1, bfd_mach_mips5000
, CPU_R5000
, ISA_MIPS4
,
371 mips_cp0_names_numeric
, NULL
, 0, mips_hwr_names_numeric
},
372 { "vr5400", 1, bfd_mach_mips5400
, CPU_VR5400
, ISA_MIPS4
,
373 mips_cp0_names_numeric
, NULL
, 0, mips_hwr_names_numeric
},
374 { "vr5500", 1, bfd_mach_mips5500
, CPU_VR5500
, ISA_MIPS4
,
375 mips_cp0_names_numeric
, NULL
, 0, mips_hwr_names_numeric
},
376 { "r6000", 1, bfd_mach_mips6000
, CPU_R6000
, ISA_MIPS2
,
377 mips_cp0_names_numeric
, NULL
, 0, mips_hwr_names_numeric
},
378 { "rm7000", 1, bfd_mach_mips7000
, CPU_RM7000
, ISA_MIPS4
,
379 mips_cp0_names_numeric
, NULL
, 0, mips_hwr_names_numeric
},
380 { "rm9000", 1, bfd_mach_mips7000
, CPU_RM7000
, ISA_MIPS4
,
381 mips_cp0_names_numeric
, NULL
, 0, mips_hwr_names_numeric
},
382 { "r8000", 1, bfd_mach_mips8000
, CPU_R8000
, ISA_MIPS4
,
383 mips_cp0_names_numeric
, NULL
, 0, mips_hwr_names_numeric
},
384 { "r10000", 1, bfd_mach_mips10000
, CPU_R10000
, ISA_MIPS4
,
385 mips_cp0_names_numeric
, NULL
, 0, mips_hwr_names_numeric
},
386 { "r12000", 1, bfd_mach_mips12000
, CPU_R12000
, ISA_MIPS4
,
387 mips_cp0_names_numeric
, NULL
, 0, mips_hwr_names_numeric
},
388 { "mips5", 1, bfd_mach_mips5
, CPU_MIPS5
, ISA_MIPS5
,
389 mips_cp0_names_numeric
, NULL
, 0, mips_hwr_names_numeric
},
391 /* For stock MIPS32, disassemble all applicable MIPS-specified ASEs.
392 Note that MIPS-3D and MDMX are not applicable to MIPS32. (See
393 _MIPS32 Architecture For Programmers Volume I: Introduction to the
394 MIPS32 Architecture_ (MIPS Document Number MD00082, Revision 0.95),
396 { "mips32", 1, bfd_mach_mipsisa32
, CPU_MIPS32
,
397 ISA_MIPS32
| INSN_MIPS16
| INSN_DSP
,
398 mips_cp0_names_mips3264
,
399 mips_cp0sel_names_mips3264
, ARRAY_SIZE (mips_cp0sel_names_mips3264
),
400 mips_hwr_names_numeric
},
402 { "mips32r2", 1, bfd_mach_mipsisa32r2
, CPU_MIPS32R2
,
403 ISA_MIPS32R2
| INSN_MIPS16
| INSN_DSP
| INSN_MT
,
404 mips_cp0_names_mips3264r2
,
405 mips_cp0sel_names_mips3264r2
, ARRAY_SIZE (mips_cp0sel_names_mips3264r2
),
406 mips_hwr_names_mips3264r2
},
408 /* For stock MIPS64, disassemble all applicable MIPS-specified ASEs. */
409 { "mips64", 1, bfd_mach_mipsisa64
, CPU_MIPS64
,
410 ISA_MIPS64
| INSN_MIPS16
| INSN_MIPS3D
| INSN_MDMX
| INSN_DSP
,
411 mips_cp0_names_mips3264
,
412 mips_cp0sel_names_mips3264
, ARRAY_SIZE (mips_cp0sel_names_mips3264
),
413 mips_hwr_names_numeric
},
415 { "mips64r2", 1, bfd_mach_mipsisa64r2
, CPU_MIPS64R2
,
416 ISA_MIPS64R2
| INSN_MIPS16
| INSN_MIPS3D
| INSN_MDMX
| INSN_DSP
,
417 mips_cp0_names_mips3264r2
,
418 mips_cp0sel_names_mips3264r2
, ARRAY_SIZE (mips_cp0sel_names_mips3264r2
),
419 mips_hwr_names_mips3264r2
},
421 { "sb1", 1, bfd_mach_mips_sb1
, CPU_SB1
,
422 ISA_MIPS64
| INSN_MIPS3D
| INSN_SB1
,
424 mips_cp0sel_names_sb1
, ARRAY_SIZE (mips_cp0sel_names_sb1
),
425 mips_hwr_names_numeric
},
427 /* This entry, mips16, is here only for ISA/processor selection; do
428 not print its name. */
429 { "", 1, bfd_mach_mips16
, CPU_MIPS16
, ISA_MIPS3
| INSN_MIPS16
,
430 mips_cp0_names_numeric
, NULL
, 0, mips_hwr_names_numeric
},
433 /* ISA and processor type to disassemble for, and register names to use.
434 set_default_mips_dis_options and parse_mips_dis_options fill in these
436 static int mips_processor
;
438 static const char * const *mips_gpr_names
;
439 static const char * const *mips_fpr_names
;
440 static const char * const *mips_cp0_names
;
441 static const struct mips_cp0sel_name
*mips_cp0sel_names
;
442 static int mips_cp0sel_names_len
;
443 static const char * const *mips_hwr_names
;
446 static int no_aliases
; /* If set disassemble as most general inst. */
448 static const struct mips_abi_choice
*
449 choose_abi_by_name (const char *name
, unsigned int namelen
)
451 const struct mips_abi_choice
*c
;
454 for (i
= 0, c
= NULL
; i
< ARRAY_SIZE (mips_abi_choices
) && c
== NULL
; i
++)
455 if (strncmp (mips_abi_choices
[i
].name
, name
, namelen
) == 0
456 && strlen (mips_abi_choices
[i
].name
) == namelen
)
457 c
= &mips_abi_choices
[i
];
462 static const struct mips_arch_choice
*
463 choose_arch_by_name (const char *name
, unsigned int namelen
)
465 const struct mips_arch_choice
*c
= NULL
;
468 for (i
= 0, c
= NULL
; i
< ARRAY_SIZE (mips_arch_choices
) && c
== NULL
; i
++)
469 if (strncmp (mips_arch_choices
[i
].name
, name
, namelen
) == 0
470 && strlen (mips_arch_choices
[i
].name
) == namelen
)
471 c
= &mips_arch_choices
[i
];
476 static const struct mips_arch_choice
*
477 choose_arch_by_number (unsigned long mach
)
479 static unsigned long hint_bfd_mach
;
480 static const struct mips_arch_choice
*hint_arch_choice
;
481 const struct mips_arch_choice
*c
;
484 /* We optimize this because even if the user specifies no
485 flags, this will be done for every instruction! */
486 if (hint_bfd_mach
== mach
487 && hint_arch_choice
!= NULL
488 && hint_arch_choice
->bfd_mach
== hint_bfd_mach
)
489 return hint_arch_choice
;
491 for (i
= 0, c
= NULL
; i
< ARRAY_SIZE (mips_arch_choices
) && c
== NULL
; i
++)
493 if (mips_arch_choices
[i
].bfd_mach_valid
494 && mips_arch_choices
[i
].bfd_mach
== mach
)
496 c
= &mips_arch_choices
[i
];
497 hint_bfd_mach
= mach
;
498 hint_arch_choice
= c
;
504 /* Check if the object uses NewABI conventions. */
507 is_newabi (Elf_Internal_Ehdr
*header
)
509 /* There are no old-style ABIs which use 64-bit ELF. */
510 if (header
->e_ident
[EI_CLASS
] == ELFCLASS64
)
513 /* If a 32-bit ELF file, n32 is a new-style ABI. */
514 if ((header
->e_flags
& EF_MIPS_ABI2
) != 0)
521 set_default_mips_dis_options (struct disassemble_info
*info
)
523 const struct mips_arch_choice
*chosen_arch
;
525 /* Defaults: mipsIII/r3000 (?!), (o)32-style ("oldabi") GPR names,
526 and numeric FPR, CP0 register, and HWR names. */
527 mips_isa
= ISA_MIPS3
;
528 mips_processor
= CPU_R3000
;
529 mips_gpr_names
= mips_gpr_names_oldabi
;
530 mips_fpr_names
= mips_fpr_names_numeric
;
531 mips_cp0_names
= mips_cp0_names_numeric
;
532 mips_cp0sel_names
= NULL
;
533 mips_cp0sel_names_len
= 0;
534 mips_hwr_names
= mips_hwr_names_numeric
;
537 /* If an ELF "newabi" binary, use the n32/(n)64 GPR names. */
538 if (info
->flavour
== bfd_target_elf_flavour
&& info
->section
!= NULL
)
540 Elf_Internal_Ehdr
*header
;
542 header
= elf_elfheader (info
->section
->owner
);
543 if (is_newabi (header
))
544 mips_gpr_names
= mips_gpr_names_newabi
;
547 /* Set ISA, architecture, and cp0 register names as best we can. */
548 #if ! SYMTAB_AVAILABLE
549 /* This is running out on a target machine, not in a host tool.
550 FIXME: Where does mips_target_info come from? */
551 target_processor
= mips_target_info
.processor
;
552 mips_isa
= mips_target_info
.isa
;
554 chosen_arch
= choose_arch_by_number (info
->mach
);
555 if (chosen_arch
!= NULL
)
557 mips_processor
= chosen_arch
->processor
;
558 mips_isa
= chosen_arch
->isa
;
559 mips_cp0_names
= chosen_arch
->cp0_names
;
560 mips_cp0sel_names
= chosen_arch
->cp0sel_names
;
561 mips_cp0sel_names_len
= chosen_arch
->cp0sel_names_len
;
562 mips_hwr_names
= chosen_arch
->hwr_names
;
568 parse_mips_dis_option (const char *option
, unsigned int len
)
570 unsigned int i
, optionlen
, vallen
;
572 const struct mips_abi_choice
*chosen_abi
;
573 const struct mips_arch_choice
*chosen_arch
;
575 /* Try to match options that are simple flags */
576 if (strncmp (option
, "no-aliases", 10) == 0)
582 /* Look for the = that delimits the end of the option name. */
583 for (i
= 0; i
< len
; i
++)
584 if (option
[i
] == '=')
587 if (i
== 0) /* Invalid option: no name before '='. */
589 if (i
== len
) /* Invalid option: no '='. */
591 if (i
== (len
- 1)) /* Invalid option: no value after '='. */
595 val
= option
+ (optionlen
+ 1);
596 vallen
= len
- (optionlen
+ 1);
598 if (strncmp ("gpr-names", option
, optionlen
) == 0
599 && strlen ("gpr-names") == optionlen
)
601 chosen_abi
= choose_abi_by_name (val
, vallen
);
602 if (chosen_abi
!= NULL
)
603 mips_gpr_names
= chosen_abi
->gpr_names
;
607 if (strncmp ("fpr-names", option
, optionlen
) == 0
608 && strlen ("fpr-names") == optionlen
)
610 chosen_abi
= choose_abi_by_name (val
, vallen
);
611 if (chosen_abi
!= NULL
)
612 mips_fpr_names
= chosen_abi
->fpr_names
;
616 if (strncmp ("cp0-names", option
, optionlen
) == 0
617 && strlen ("cp0-names") == optionlen
)
619 chosen_arch
= choose_arch_by_name (val
, vallen
);
620 if (chosen_arch
!= NULL
)
622 mips_cp0_names
= chosen_arch
->cp0_names
;
623 mips_cp0sel_names
= chosen_arch
->cp0sel_names
;
624 mips_cp0sel_names_len
= chosen_arch
->cp0sel_names_len
;
629 if (strncmp ("hwr-names", option
, optionlen
) == 0
630 && strlen ("hwr-names") == optionlen
)
632 chosen_arch
= choose_arch_by_name (val
, vallen
);
633 if (chosen_arch
!= NULL
)
634 mips_hwr_names
= chosen_arch
->hwr_names
;
638 if (strncmp ("reg-names", option
, optionlen
) == 0
639 && strlen ("reg-names") == optionlen
)
641 /* We check both ABI and ARCH here unconditionally, so
642 that "numeric" will do the desirable thing: select
643 numeric register names for all registers. Other than
644 that, a given name probably won't match both. */
645 chosen_abi
= choose_abi_by_name (val
, vallen
);
646 if (chosen_abi
!= NULL
)
648 mips_gpr_names
= chosen_abi
->gpr_names
;
649 mips_fpr_names
= chosen_abi
->fpr_names
;
651 chosen_arch
= choose_arch_by_name (val
, vallen
);
652 if (chosen_arch
!= NULL
)
654 mips_cp0_names
= chosen_arch
->cp0_names
;
655 mips_cp0sel_names
= chosen_arch
->cp0sel_names
;
656 mips_cp0sel_names_len
= chosen_arch
->cp0sel_names_len
;
657 mips_hwr_names
= chosen_arch
->hwr_names
;
662 /* Invalid option. */
666 parse_mips_dis_options (const char *options
)
668 const char *option_end
;
673 while (*options
!= '\0')
675 /* Skip empty options. */
682 /* We know that *options is neither NUL or a comma. */
683 option_end
= options
+ 1;
684 while (*option_end
!= ',' && *option_end
!= '\0')
687 parse_mips_dis_option (options
, option_end
- options
);
689 /* Go on to the next one. If option_end points to a comma, it
690 will be skipped above. */
691 options
= option_end
;
695 static const struct mips_cp0sel_name
*
696 lookup_mips_cp0sel_name (const struct mips_cp0sel_name
*names
,
703 for (i
= 0; i
< len
; i
++)
704 if (names
[i
].cp0reg
== cp0reg
&& names
[i
].sel
== sel
)
709 /* Print insn arguments for 32/64-bit code. */
712 print_insn_args (const char *d
,
713 register unsigned long int l
,
715 struct disassemble_info
*info
,
716 const struct mips_opcode
*opp
)
719 unsigned int lsb
, msb
, msbd
;
723 for (; *d
!= '\0'; d
++)
732 (*info
->fprintf_func
) (info
->stream
, "%c", *d
);
736 /* Extension character; switch for second char. */
741 /* xgettext:c-format */
742 (*info
->fprintf_func
) (info
->stream
,
743 _("# internal error, incomplete extension sequence (+)"));
747 lsb
= (l
>> OP_SH_SHAMT
) & OP_MASK_SHAMT
;
748 (*info
->fprintf_func
) (info
->stream
, "0x%x", lsb
);
752 msb
= (l
>> OP_SH_INSMSB
) & OP_MASK_INSMSB
;
753 (*info
->fprintf_func
) (info
->stream
, "0x%x", msb
- lsb
+ 1);
758 msbd
= (l
>> OP_SH_EXTMSBD
) & OP_MASK_EXTMSBD
;
759 (*info
->fprintf_func
) (info
->stream
, "0x%x", msbd
+ 1);
764 const struct mips_cp0sel_name
*n
;
765 unsigned int cp0reg
, sel
;
767 cp0reg
= (l
>> OP_SH_RD
) & OP_MASK_RD
;
768 sel
= (l
>> OP_SH_SEL
) & OP_MASK_SEL
;
770 /* CP0 register including 'sel' code for mtcN (et al.), to be
771 printed textually if known. If not known, print both
772 CP0 register name and sel numerically since CP0 register
773 with sel 0 may have a name unrelated to register being
775 n
= lookup_mips_cp0sel_name(mips_cp0sel_names
,
776 mips_cp0sel_names_len
, cp0reg
, sel
);
778 (*info
->fprintf_func
) (info
->stream
, "%s", n
->name
);
780 (*info
->fprintf_func
) (info
->stream
, "$%d,%d", cp0reg
, sel
);
785 lsb
= ((l
>> OP_SH_SHAMT
) & OP_MASK_SHAMT
) + 32;
786 (*info
->fprintf_func
) (info
->stream
, "0x%x", lsb
);
790 msb
= ((l
>> OP_SH_INSMSB
) & OP_MASK_INSMSB
) + 32;
791 (*info
->fprintf_func
) (info
->stream
, "0x%x", msb
- lsb
+ 1);
795 msbd
= ((l
>> OP_SH_EXTMSBD
) & OP_MASK_EXTMSBD
) + 32;
796 (*info
->fprintf_func
) (info
->stream
, "0x%x", msbd
+ 1);
799 case 't': /* Coprocessor 0 reg name */
800 (*info
->fprintf_func
) (info
->stream
, "%s",
801 mips_cp0_names
[(l
>> OP_SH_RT
) &
805 case 'T': /* Coprocessor 0 reg name */
807 const struct mips_cp0sel_name
*n
;
808 unsigned int cp0reg
, sel
;
810 cp0reg
= (l
>> OP_SH_RT
) & OP_MASK_RT
;
811 sel
= (l
>> OP_SH_SEL
) & OP_MASK_SEL
;
813 /* CP0 register including 'sel' code for mftc0, to be
814 printed textually if known. If not known, print both
815 CP0 register name and sel numerically since CP0 register
816 with sel 0 may have a name unrelated to register being
818 n
= lookup_mips_cp0sel_name(mips_cp0sel_names
,
819 mips_cp0sel_names_len
, cp0reg
, sel
);
821 (*info
->fprintf_func
) (info
->stream
, "%s", n
->name
);
823 (*info
->fprintf_func
) (info
->stream
, "$%d,%d", cp0reg
, sel
);
828 /* xgettext:c-format */
829 (*info
->fprintf_func
) (info
->stream
,
830 _("# internal error, undefined extension sequence (+%c)"),
837 (*info
->fprintf_func
) (info
->stream
, "0x%lx",
838 (l
>> OP_SH_SA3
) & OP_MASK_SA3
);
842 (*info
->fprintf_func
) (info
->stream
, "0x%lx",
843 (l
>> OP_SH_SA4
) & OP_MASK_SA4
);
847 (*info
->fprintf_func
) (info
->stream
, "0x%lx",
848 (l
>> OP_SH_IMM8
) & OP_MASK_IMM8
);
852 (*info
->fprintf_func
) (info
->stream
, "0x%lx",
853 (l
>> OP_SH_RS
) & OP_MASK_RS
);
857 (*info
->fprintf_func
) (info
->stream
, "$ac%ld",
858 (l
>> OP_SH_DSPACC
) & OP_MASK_DSPACC
);
862 (*info
->fprintf_func
) (info
->stream
, "0x%lx",
863 (l
>> OP_SH_WRDSP
) & OP_MASK_WRDSP
);
867 (*info
->fprintf_func
) (info
->stream
, "$ac%ld",
868 (l
>> OP_SH_DSPACC_S
) & OP_MASK_DSPACC_S
);
871 case '0': /* dsp 6-bit signed immediate in bit 20 */
872 delta
= ((l
>> OP_SH_DSPSFT
) & OP_MASK_DSPSFT
);
873 if (delta
& 0x20) /* test sign bit */
874 delta
|= ~OP_MASK_DSPSFT
;
875 (*info
->fprintf_func
) (info
->stream
, "%d", delta
);
878 case ':': /* dsp 7-bit signed immediate in bit 19 */
879 delta
= ((l
>> OP_SH_DSPSFT_7
) & OP_MASK_DSPSFT_7
);
880 if (delta
& 0x40) /* test sign bit */
881 delta
|= ~OP_MASK_DSPSFT_7
;
882 (*info
->fprintf_func
) (info
->stream
, "%d", delta
);
886 (*info
->fprintf_func
) (info
->stream
, "0x%lx",
887 (l
>> OP_SH_RDDSP
) & OP_MASK_RDDSP
);
890 case '@': /* dsp 10-bit signed immediate in bit 16 */
891 delta
= ((l
>> OP_SH_IMM10
) & OP_MASK_IMM10
);
892 if (delta
& 0x200) /* test sign bit */
893 delta
|= ~OP_MASK_IMM10
;
894 (*info
->fprintf_func
) (info
->stream
, "%d", delta
);
898 (*info
->fprintf_func
) (info
->stream
, "%ld",
899 (l
>> OP_SH_MT_U
) & OP_MASK_MT_U
);
903 (*info
->fprintf_func
) (info
->stream
, "%ld",
904 (l
>> OP_SH_MT_H
) & OP_MASK_MT_H
);
908 (*info
->fprintf_func
) (info
->stream
, "$ac%ld",
909 (l
>> OP_SH_MTACC_T
) & OP_MASK_MTACC_T
);
913 (*info
->fprintf_func
) (info
->stream
, "$ac%ld",
914 (l
>> OP_SH_MTACC_D
) & OP_MASK_MTACC_D
);
918 /* Coprocessor register for CTTC1, MTTC2, MTHC2, CTTC2. */
919 (*info
->fprintf_func
) (info
->stream
, "$%ld",
920 (l
>> OP_SH_RD
) & OP_MASK_RD
);
927 (*info
->fprintf_func
) (info
->stream
, "%s",
928 mips_gpr_names
[(l
>> OP_SH_RS
) & OP_MASK_RS
]);
933 (*info
->fprintf_func
) (info
->stream
, "%s",
934 mips_gpr_names
[(l
>> OP_SH_RT
) & OP_MASK_RT
]);
939 (*info
->fprintf_func
) (info
->stream
, "0x%lx",
940 (l
>> OP_SH_IMMEDIATE
) & OP_MASK_IMMEDIATE
);
943 case 'j': /* Same as i, but sign-extended. */
945 delta
= (l
>> OP_SH_DELTA
) & OP_MASK_DELTA
;
948 (*info
->fprintf_func
) (info
->stream
, "%d",
953 (*info
->fprintf_func
) (info
->stream
, "0x%x",
954 (unsigned int) ((l
>> OP_SH_PREFX
)
959 (*info
->fprintf_func
) (info
->stream
, "0x%x",
960 (unsigned int) ((l
>> OP_SH_CACHE
)
965 info
->target
= (((pc
+ 4) & ~(bfd_vma
) 0x0fffffff)
966 | (((l
>> OP_SH_TARGET
) & OP_MASK_TARGET
) << 2));
967 (*info
->print_address_func
) (info
->target
, info
);
971 /* Sign extend the displacement. */
972 delta
= (l
>> OP_SH_DELTA
) & OP_MASK_DELTA
;
975 info
->target
= (delta
<< 2) + pc
+ INSNLEN
;
976 (*info
->print_address_func
) (info
->target
, info
);
980 (*info
->fprintf_func
) (info
->stream
, "%s",
981 mips_gpr_names
[(l
>> OP_SH_RD
) & OP_MASK_RD
]);
986 /* First check for both rd and rt being equal. */
987 unsigned int reg
= (l
>> OP_SH_RD
) & OP_MASK_RD
;
988 if (reg
== ((l
>> OP_SH_RT
) & OP_MASK_RT
))
989 (*info
->fprintf_func
) (info
->stream
, "%s",
990 mips_gpr_names
[reg
]);
993 /* If one is zero use the other. */
995 (*info
->fprintf_func
) (info
->stream
, "%s",
996 mips_gpr_names
[(l
>> OP_SH_RT
) & OP_MASK_RT
]);
997 else if (((l
>> OP_SH_RT
) & OP_MASK_RT
) == 0)
998 (*info
->fprintf_func
) (info
->stream
, "%s",
999 mips_gpr_names
[reg
]);
1000 else /* Bogus, result depends on processor. */
1001 (*info
->fprintf_func
) (info
->stream
, "%s or %s",
1002 mips_gpr_names
[reg
],
1003 mips_gpr_names
[(l
>> OP_SH_RT
) & OP_MASK_RT
]);
1009 (*info
->fprintf_func
) (info
->stream
, "%s", mips_gpr_names
[0]);
1013 (*info
->fprintf_func
) (info
->stream
, "0x%lx",
1014 (l
>> OP_SH_SHAMT
) & OP_MASK_SHAMT
);
1018 (*info
->fprintf_func
) (info
->stream
, "0x%lx",
1019 (l
>> OP_SH_CODE
) & OP_MASK_CODE
);
1023 (*info
->fprintf_func
) (info
->stream
, "0x%lx",
1024 (l
>> OP_SH_CODE2
) & OP_MASK_CODE2
);
1028 (*info
->fprintf_func
) (info
->stream
, "0x%lx",
1029 (l
>> OP_SH_COPZ
) & OP_MASK_COPZ
);
1033 (*info
->fprintf_func
) (info
->stream
, "0x%lx",
1035 (l
>> OP_SH_CODE20
) & OP_MASK_CODE20
);
1039 (*info
->fprintf_func
) (info
->stream
, "0x%lx",
1040 (l
>> OP_SH_CODE19
) & OP_MASK_CODE19
);
1045 (*info
->fprintf_func
) (info
->stream
, "%s",
1046 mips_fpr_names
[(l
>> OP_SH_FS
) & OP_MASK_FS
]);
1051 (*info
->fprintf_func
) (info
->stream
, "%s",
1052 mips_fpr_names
[(l
>> OP_SH_FT
) & OP_MASK_FT
]);
1056 (*info
->fprintf_func
) (info
->stream
, "%s",
1057 mips_fpr_names
[(l
>> OP_SH_FD
) & OP_MASK_FD
]);
1061 (*info
->fprintf_func
) (info
->stream
, "%s",
1062 mips_fpr_names
[(l
>> OP_SH_FR
) & OP_MASK_FR
]);
1066 /* Coprocessor register for lwcN instructions, et al.
1068 Note that there is no load/store cp0 instructions, and
1069 that FPU (cp1) instructions disassemble this field using
1070 'T' format. Therefore, until we gain understanding of
1071 cp2 register names, we can simply print the register
1073 (*info
->fprintf_func
) (info
->stream
, "$%ld",
1074 (l
>> OP_SH_RT
) & OP_MASK_RT
);
1078 /* Coprocessor register for mtcN instructions, et al. Note
1079 that FPU (cp1) instructions disassemble this field using
1080 'S' format. Therefore, we only need to worry about cp0,
1082 op
= (l
>> OP_SH_OP
) & OP_MASK_OP
;
1083 if (op
== OP_OP_COP0
)
1084 (*info
->fprintf_func
) (info
->stream
, "%s",
1085 mips_cp0_names
[(l
>> OP_SH_RD
) & OP_MASK_RD
]);
1087 (*info
->fprintf_func
) (info
->stream
, "$%ld",
1088 (l
>> OP_SH_RD
) & OP_MASK_RD
);
1092 (*info
->fprintf_func
) (info
->stream
, "%s",
1093 mips_hwr_names
[(l
>> OP_SH_RD
) & OP_MASK_RD
]);
1097 (*info
->fprintf_func
) (info
->stream
,
1098 ((opp
->pinfo
& (FP_D
| FP_S
)) != 0
1099 ? "$fcc%ld" : "$cc%ld"),
1100 (l
>> OP_SH_BCC
) & OP_MASK_BCC
);
1104 (*info
->fprintf_func
) (info
->stream
, "$fcc%ld",
1105 (l
>> OP_SH_CCC
) & OP_MASK_CCC
);
1109 (*info
->fprintf_func
) (info
->stream
, "%ld",
1110 (l
>> OP_SH_PERFREG
) & OP_MASK_PERFREG
);
1114 (*info
->fprintf_func
) (info
->stream
, "%ld",
1115 (l
>> OP_SH_VECBYTE
) & OP_MASK_VECBYTE
);
1119 (*info
->fprintf_func
) (info
->stream
, "%ld",
1120 (l
>> OP_SH_VECALIGN
) & OP_MASK_VECALIGN
);
1124 (*info
->fprintf_func
) (info
->stream
, "%ld",
1125 (l
>> OP_SH_SEL
) & OP_MASK_SEL
);
1129 (*info
->fprintf_func
) (info
->stream
, "%ld",
1130 (l
>> OP_SH_ALN
) & OP_MASK_ALN
);
1135 unsigned int vsel
= (l
>> OP_SH_VSEL
) & OP_MASK_VSEL
;
1137 if ((vsel
& 0x10) == 0)
1142 for (fmt
= 0; fmt
< 3; fmt
++, vsel
>>= 1)
1143 if ((vsel
& 1) == 0)
1145 (*info
->fprintf_func
) (info
->stream
, "$v%ld[%d]",
1146 (l
>> OP_SH_FT
) & OP_MASK_FT
,
1149 else if ((vsel
& 0x08) == 0)
1151 (*info
->fprintf_func
) (info
->stream
, "$v%ld",
1152 (l
>> OP_SH_FT
) & OP_MASK_FT
);
1156 (*info
->fprintf_func
) (info
->stream
, "0x%lx",
1157 (l
>> OP_SH_FT
) & OP_MASK_FT
);
1163 (*info
->fprintf_func
) (info
->stream
, "$v%ld",
1164 (l
>> OP_SH_FD
) & OP_MASK_FD
);
1168 (*info
->fprintf_func
) (info
->stream
, "$v%ld",
1169 (l
>> OP_SH_FS
) & OP_MASK_FS
);
1173 (*info
->fprintf_func
) (info
->stream
, "$v%ld",
1174 (l
>> OP_SH_FT
) & OP_MASK_FT
);
1178 /* xgettext:c-format */
1179 (*info
->fprintf_func
) (info
->stream
,
1180 _("# internal error, undefined modifier(%c)"),
1187 /* Print the mips instruction at address MEMADDR in debugged memory,
1188 on using INFO. Returns length of the instruction, in bytes, which is
1189 always INSNLEN. BIGENDIAN must be 1 if this is big-endian code, 0 if
1190 this is little-endian code. */
1193 print_insn_mips (bfd_vma memaddr
,
1194 unsigned long int word
,
1195 struct disassemble_info
*info
)
1197 const struct mips_opcode
*op
;
1198 static bfd_boolean init
= 0;
1199 static const struct mips_opcode
*mips_hash
[OP_MASK_OP
+ 1];
1201 /* Build a hash table to shorten the search time. */
1206 for (i
= 0; i
<= OP_MASK_OP
; i
++)
1208 for (op
= mips_opcodes
; op
< &mips_opcodes
[NUMOPCODES
]; op
++)
1210 if (op
->pinfo
== INSN_MACRO
1211 || (no_aliases
&& (op
->pinfo2
& INSN2_ALIAS
)))
1213 if (i
== ((op
->match
>> OP_SH_OP
) & OP_MASK_OP
))
1224 info
->bytes_per_chunk
= INSNLEN
;
1225 info
->display_endian
= info
->endian
;
1226 info
->insn_info_valid
= 1;
1227 info
->branch_delay_insns
= 0;
1228 info
->data_size
= 0;
1229 info
->insn_type
= dis_nonbranch
;
1233 op
= mips_hash
[(word
>> OP_SH_OP
) & OP_MASK_OP
];
1236 for (; op
< &mips_opcodes
[NUMOPCODES
]; op
++)
1238 if (op
->pinfo
!= INSN_MACRO
1239 && !(no_aliases
&& (op
->pinfo2
& INSN2_ALIAS
))
1240 && (word
& op
->mask
) == op
->match
)
1244 /* We always allow to disassemble the jalx instruction. */
1245 if (! OPCODE_IS_MEMBER (op
, mips_isa
, mips_processor
)
1246 && strcmp (op
->name
, "jalx"))
1249 /* Figure out instruction type and branch delay information. */
1250 if ((op
->pinfo
& INSN_UNCOND_BRANCH_DELAY
) != 0)
1252 if ((info
->insn_type
& INSN_WRITE_GPR_31
) != 0)
1253 info
->insn_type
= dis_jsr
;
1255 info
->insn_type
= dis_branch
;
1256 info
->branch_delay_insns
= 1;
1258 else if ((op
->pinfo
& (INSN_COND_BRANCH_DELAY
1259 | INSN_COND_BRANCH_LIKELY
)) != 0)
1261 if ((info
->insn_type
& INSN_WRITE_GPR_31
) != 0)
1262 info
->insn_type
= dis_condjsr
;
1264 info
->insn_type
= dis_condbranch
;
1265 info
->branch_delay_insns
= 1;
1267 else if ((op
->pinfo
& (INSN_STORE_MEMORY
1268 | INSN_LOAD_MEMORY_DELAY
)) != 0)
1269 info
->insn_type
= dis_dref
;
1271 (*info
->fprintf_func
) (info
->stream
, "%s", op
->name
);
1274 if (d
!= NULL
&& *d
!= '\0')
1276 (*info
->fprintf_func
) (info
->stream
, "\t");
1277 print_insn_args (d
, word
, memaddr
, info
, op
);
1285 /* Handle undefined instructions. */
1286 info
->insn_type
= dis_noninsn
;
1287 (*info
->fprintf_func
) (info
->stream
, "0x%lx", word
);
1291 /* Disassemble an operand for a mips16 instruction. */
1294 print_mips16_insn_arg (char type
,
1295 const struct mips_opcode
*op
,
1297 bfd_boolean use_extend
,
1300 struct disassemble_info
*info
)
1307 (*info
->fprintf_func
) (info
->stream
, "%c", type
);
1312 (*info
->fprintf_func
) (info
->stream
, "%s",
1313 mips16_reg_names(((l
>> MIPS16OP_SH_RY
)
1314 & MIPS16OP_MASK_RY
)));
1319 (*info
->fprintf_func
) (info
->stream
, "%s",
1320 mips16_reg_names(((l
>> MIPS16OP_SH_RX
)
1321 & MIPS16OP_MASK_RX
)));
1325 (*info
->fprintf_func
) (info
->stream
, "%s",
1326 mips16_reg_names(((l
>> MIPS16OP_SH_RZ
)
1327 & MIPS16OP_MASK_RZ
)));
1331 (*info
->fprintf_func
) (info
->stream
, "%s",
1332 mips16_reg_names(((l
>> MIPS16OP_SH_MOVE32Z
)
1333 & MIPS16OP_MASK_MOVE32Z
)));
1337 (*info
->fprintf_func
) (info
->stream
, "%s", mips_gpr_names
[0]);
1341 (*info
->fprintf_func
) (info
->stream
, "%s", mips_gpr_names
[29]);
1345 (*info
->fprintf_func
) (info
->stream
, "$pc");
1349 (*info
->fprintf_func
) (info
->stream
, "%s", mips_gpr_names
[31]);
1353 (*info
->fprintf_func
) (info
->stream
, "%s",
1354 mips_gpr_names
[((l
>> MIPS16OP_SH_REGR32
)
1355 & MIPS16OP_MASK_REGR32
)]);
1359 (*info
->fprintf_func
) (info
->stream
, "%s",
1360 mips_gpr_names
[MIPS16OP_EXTRACT_REG32R (l
)]);
1386 int immed
, nbits
, shift
, signedp
, extbits
, pcrel
, extu
, branch
;
1398 immed
= (l
>> MIPS16OP_SH_RZ
) & MIPS16OP_MASK_RZ
;
1404 immed
= (l
>> MIPS16OP_SH_RX
) & MIPS16OP_MASK_RX
;
1410 immed
= (l
>> MIPS16OP_SH_RZ
) & MIPS16OP_MASK_RZ
;
1416 immed
= (l
>> MIPS16OP_SH_RX
) & MIPS16OP_MASK_RX
;
1422 immed
= (l
>> MIPS16OP_SH_IMM4
) & MIPS16OP_MASK_IMM4
;
1428 immed
= (l
>> MIPS16OP_SH_IMM5
) & MIPS16OP_MASK_IMM5
;
1429 info
->insn_type
= dis_dref
;
1430 info
->data_size
= 1;
1435 immed
= (l
>> MIPS16OP_SH_IMM5
) & MIPS16OP_MASK_IMM5
;
1436 info
->insn_type
= dis_dref
;
1437 info
->data_size
= 2;
1442 immed
= (l
>> MIPS16OP_SH_IMM5
) & MIPS16OP_MASK_IMM5
;
1443 if ((op
->pinfo
& MIPS16_INSN_READ_PC
) == 0
1444 && (op
->pinfo
& MIPS16_INSN_READ_SP
) == 0)
1446 info
->insn_type
= dis_dref
;
1447 info
->data_size
= 4;
1453 immed
= (l
>> MIPS16OP_SH_IMM5
) & MIPS16OP_MASK_IMM5
;
1454 info
->insn_type
= dis_dref
;
1455 info
->data_size
= 8;
1459 immed
= (l
>> MIPS16OP_SH_IMM5
) & MIPS16OP_MASK_IMM5
;
1464 immed
= (l
>> MIPS16OP_SH_IMM6
) & MIPS16OP_MASK_IMM6
;
1468 immed
= (l
>> MIPS16OP_SH_IMM8
) & MIPS16OP_MASK_IMM8
;
1473 immed
= (l
>> MIPS16OP_SH_IMM8
) & MIPS16OP_MASK_IMM8
;
1474 /* FIXME: This might be lw, or it might be addiu to $sp or
1475 $pc. We assume it's load. */
1476 info
->insn_type
= dis_dref
;
1477 info
->data_size
= 4;
1482 immed
= (l
>> MIPS16OP_SH_IMM8
) & MIPS16OP_MASK_IMM8
;
1483 info
->insn_type
= dis_dref
;
1484 info
->data_size
= 8;
1488 immed
= (l
>> MIPS16OP_SH_IMM8
) & MIPS16OP_MASK_IMM8
;
1493 immed
= (l
>> MIPS16OP_SH_IMM8
) & MIPS16OP_MASK_IMM8
;
1499 immed
= (l
>> MIPS16OP_SH_IMM8
) & MIPS16OP_MASK_IMM8
;
1504 immed
= (l
>> MIPS16OP_SH_IMM8
) & MIPS16OP_MASK_IMM8
;
1508 info
->insn_type
= dis_condbranch
;
1512 immed
= (l
>> MIPS16OP_SH_IMM11
) & MIPS16OP_MASK_IMM11
;
1516 info
->insn_type
= dis_branch
;
1521 immed
= (l
>> MIPS16OP_SH_IMM8
) & MIPS16OP_MASK_IMM8
;
1523 /* FIXME: This can be lw or la. We assume it is lw. */
1524 info
->insn_type
= dis_dref
;
1525 info
->data_size
= 4;
1530 immed
= (l
>> MIPS16OP_SH_IMM5
) & MIPS16OP_MASK_IMM5
;
1532 info
->insn_type
= dis_dref
;
1533 info
->data_size
= 8;
1538 immed
= (l
>> MIPS16OP_SH_IMM5
) & MIPS16OP_MASK_IMM5
;
1547 if (signedp
&& immed
>= (1 << (nbits
- 1)))
1548 immed
-= 1 << nbits
;
1550 if ((type
== '<' || type
== '>' || type
== '[' || type
== ']')
1557 immed
|= ((extend
& 0x1f) << 11) | (extend
& 0x7e0);
1558 else if (extbits
== 15)
1559 immed
|= ((extend
& 0xf) << 11) | (extend
& 0x7f0);
1561 immed
= ((extend
>> 6) & 0x1f) | (extend
& 0x20);
1562 immed
&= (1 << extbits
) - 1;
1563 if (! extu
&& immed
>= (1 << (extbits
- 1)))
1564 immed
-= 1 << extbits
;
1568 (*info
->fprintf_func
) (info
->stream
, "%d", immed
);
1576 baseaddr
= memaddr
+ 2;
1578 else if (use_extend
)
1579 baseaddr
= memaddr
- 2;
1587 /* If this instruction is in the delay slot of a jr
1588 instruction, the base address is the address of the
1589 jr instruction. If it is in the delay slot of jalr
1590 instruction, the base address is the address of the
1591 jalr instruction. This test is unreliable: we have
1592 no way of knowing whether the previous word is
1593 instruction or data. */
1594 status
= (*info
->read_memory_func
) (memaddr
- 4, buffer
, 2,
1597 && (((info
->endian
== BFD_ENDIAN_BIG
1598 ? bfd_getb16 (buffer
)
1599 : bfd_getl16 (buffer
))
1600 & 0xf800) == 0x1800))
1601 baseaddr
= memaddr
- 4;
1604 status
= (*info
->read_memory_func
) (memaddr
- 2, buffer
,
1607 && (((info
->endian
== BFD_ENDIAN_BIG
1608 ? bfd_getb16 (buffer
)
1609 : bfd_getl16 (buffer
))
1610 & 0xf81f) == 0xe800))
1611 baseaddr
= memaddr
- 2;
1614 info
->target
= (baseaddr
& ~((1 << shift
) - 1)) + immed
;
1615 (*info
->print_address_func
) (info
->target
, info
);
1623 l
= ((l
& 0x1f) << 23) | ((l
& 0x3e0) << 13) | (extend
<< 2);
1624 info
->target
= ((memaddr
+ 4) & ~(bfd_vma
) 0x0fffffff) | l
;
1625 (*info
->print_address_func
) (info
->target
, info
);
1626 info
->insn_type
= dis_jsr
;
1627 info
->branch_delay_insns
= 1;
1633 int need_comma
, amask
, smask
;
1637 l
= (l
>> MIPS16OP_SH_IMM6
) & MIPS16OP_MASK_IMM6
;
1639 amask
= (l
>> 3) & 7;
1641 if (amask
> 0 && amask
< 5)
1643 (*info
->fprintf_func
) (info
->stream
, "%s", mips_gpr_names
[4]);
1645 (*info
->fprintf_func
) (info
->stream
, "-%s",
1646 mips_gpr_names
[amask
+ 3]);
1650 smask
= (l
>> 1) & 3;
1653 (*info
->fprintf_func
) (info
->stream
, "%s??",
1654 need_comma
? "," : "");
1659 (*info
->fprintf_func
) (info
->stream
, "%s%s",
1660 need_comma
? "," : "",
1661 mips_gpr_names
[16]);
1663 (*info
->fprintf_func
) (info
->stream
, "-%s",
1664 mips_gpr_names
[smask
+ 15]);
1670 (*info
->fprintf_func
) (info
->stream
, "%s%s",
1671 need_comma
? "," : "",
1672 mips_gpr_names
[31]);
1676 if (amask
== 5 || amask
== 6)
1678 (*info
->fprintf_func
) (info
->stream
, "%s$f0",
1679 need_comma
? "," : "");
1681 (*info
->fprintf_func
) (info
->stream
, "-$f1");
1688 /* MIPS16e save/restore. */
1691 int amask
, args
, statics
;
1700 amask
= (l
>> 16) & 0xf;
1701 if (amask
== MIPS16_ALL_ARGS
)
1706 else if (amask
== MIPS16_ALL_STATICS
)
1714 statics
= amask
& 3;
1718 (*info
->fprintf_func
) (info
->stream
, "%s", mips_gpr_names
[4]);
1720 (*info
->fprintf_func
) (info
->stream
, "-%s",
1721 mips_gpr_names
[4 + args
- 1]);
1725 framesz
= (((l
>> 16) & 0xf0) | (l
& 0x0f)) * 8;
1726 if (framesz
== 0 && !use_extend
)
1729 (*info
->fprintf_func
) (info
->stream
, "%s%d",
1730 need_comma
? "," : "",
1733 if (l
& 0x40) /* $ra */
1734 (*info
->fprintf_func
) (info
->stream
, ",%s", mips_gpr_names
[31]);
1736 nsreg
= (l
>> 24) & 0x7;
1738 if (l
& 0x20) /* $s0 */
1740 if (l
& 0x10) /* $s1 */
1742 if (nsreg
> 0) /* $s2-$s8 */
1743 smask
|= ((1 << nsreg
) - 1) << 2;
1745 /* Find first set static reg bit. */
1746 for (i
= 0; i
< 9; i
++)
1748 if (smask
& (1 << i
))
1750 (*info
->fprintf_func
) (info
->stream
, ",%s",
1751 mips_gpr_names
[i
== 8 ? 30 : (16 + i
)]);
1752 /* Skip over string of set bits. */
1753 for (j
= i
; smask
& (2 << j
); j
++)
1756 (*info
->fprintf_func
) (info
->stream
, "-%s",
1757 mips_gpr_names
[j
== 8 ? 30 : (16 + j
)]);
1762 /* Statics $ax - $a3. */
1764 (*info
->fprintf_func
) (info
->stream
, ",%s", mips_gpr_names
[7]);
1765 else if (statics
> 0)
1766 (*info
->fprintf_func
) (info
->stream
, ",%s-%s",
1767 mips_gpr_names
[7 - statics
+ 1],
1773 /* xgettext:c-format */
1774 (*info
->fprintf_func
)
1776 _("# internal disassembler error, unrecognised modifier (%c)"),
1782 /* Disassemble mips16 instructions. */
1785 print_insn_mips16 (bfd_vma memaddr
, struct disassemble_info
*info
)
1791 bfd_boolean use_extend
;
1793 const struct mips_opcode
*op
, *opend
;
1795 info
->bytes_per_chunk
= 2;
1796 info
->display_endian
= info
->endian
;
1797 info
->insn_info_valid
= 1;
1798 info
->branch_delay_insns
= 0;
1799 info
->data_size
= 0;
1800 info
->insn_type
= dis_nonbranch
;
1804 status
= (*info
->read_memory_func
) (memaddr
, buffer
, 2, info
);
1807 (*info
->memory_error_func
) (status
, memaddr
, info
);
1813 if (info
->endian
== BFD_ENDIAN_BIG
)
1814 insn
= bfd_getb16 (buffer
);
1816 insn
= bfd_getl16 (buffer
);
1818 /* Handle the extend opcode specially. */
1820 if ((insn
& 0xf800) == 0xf000)
1823 extend
= insn
& 0x7ff;
1827 status
= (*info
->read_memory_func
) (memaddr
, buffer
, 2, info
);
1830 (*info
->fprintf_func
) (info
->stream
, "extend 0x%x",
1831 (unsigned int) extend
);
1832 (*info
->memory_error_func
) (status
, memaddr
, info
);
1836 if (info
->endian
== BFD_ENDIAN_BIG
)
1837 insn
= bfd_getb16 (buffer
);
1839 insn
= bfd_getl16 (buffer
);
1841 /* Check for an extend opcode followed by an extend opcode. */
1842 if ((insn
& 0xf800) == 0xf000)
1844 (*info
->fprintf_func
) (info
->stream
, "extend 0x%x",
1845 (unsigned int) extend
);
1846 info
->insn_type
= dis_noninsn
;
1853 /* FIXME: Should probably use a hash table on the major opcode here. */
1855 opend
= mips16_opcodes
+ bfd_mips16_num_opcodes
;
1856 for (op
= mips16_opcodes
; op
< opend
; op
++)
1858 if (op
->pinfo
!= INSN_MACRO
1859 && !(no_aliases
&& (op
->pinfo2
& INSN2_ALIAS
))
1860 && (insn
& op
->mask
) == op
->match
)
1864 if (strchr (op
->args
, 'a') != NULL
)
1868 (*info
->fprintf_func
) (info
->stream
, "extend 0x%x",
1869 (unsigned int) extend
);
1870 info
->insn_type
= dis_noninsn
;
1878 status
= (*info
->read_memory_func
) (memaddr
, buffer
, 2,
1883 if (info
->endian
== BFD_ENDIAN_BIG
)
1884 extend
= bfd_getb16 (buffer
);
1886 extend
= bfd_getl16 (buffer
);
1891 (*info
->fprintf_func
) (info
->stream
, "%s", op
->name
);
1892 if (op
->args
[0] != '\0')
1893 (*info
->fprintf_func
) (info
->stream
, "\t");
1895 for (s
= op
->args
; *s
!= '\0'; s
++)
1899 && (((insn
>> MIPS16OP_SH_RX
) & MIPS16OP_MASK_RX
)
1900 == ((insn
>> MIPS16OP_SH_RY
) & MIPS16OP_MASK_RY
)))
1902 /* Skip the register and the comma. */
1908 && (((insn
>> MIPS16OP_SH_RZ
) & MIPS16OP_MASK_RZ
)
1909 == ((insn
>> MIPS16OP_SH_RX
) & MIPS16OP_MASK_RX
)))
1911 /* Skip the register and the comma. */
1915 print_mips16_insn_arg (*s
, op
, insn
, use_extend
, extend
, memaddr
,
1919 if ((op
->pinfo
& INSN_UNCOND_BRANCH_DELAY
) != 0)
1921 info
->branch_delay_insns
= 1;
1922 if (info
->insn_type
!= dis_jsr
)
1923 info
->insn_type
= dis_branch
;
1931 (*info
->fprintf_func
) (info
->stream
, "0x%x", extend
| 0xf000);
1932 (*info
->fprintf_func
) (info
->stream
, "0x%x", insn
);
1933 info
->insn_type
= dis_noninsn
;
1938 /* In an environment where we do not know the symbol type of the
1939 instruction we are forced to assume that the low order bit of the
1940 instructions' address may mark it as a mips16 instruction. If we
1941 are single stepping, or the pc is within the disassembled function,
1942 this works. Otherwise, we need a clue. Sometimes. */
1945 _print_insn_mips (bfd_vma memaddr
,
1946 struct disassemble_info
*info
,
1947 enum bfd_endian endianness
)
1949 bfd_byte buffer
[INSNLEN
];
1952 set_default_mips_dis_options (info
);
1953 parse_mips_dis_options (info
->disassembler_options
);
1956 /* FIXME: If odd address, this is CLEARLY a mips 16 instruction. */
1957 /* Only a few tools will work this way. */
1959 return print_insn_mips16 (memaddr
, info
);
1962 #if SYMTAB_AVAILABLE
1963 if (info
->mach
== bfd_mach_mips16
1964 || (info
->flavour
== bfd_target_elf_flavour
1965 && info
->symbols
!= NULL
1966 && ((*(elf_symbol_type
**) info
->symbols
)->internal_elf_sym
.st_other
1968 return print_insn_mips16 (memaddr
, info
);
1971 status
= (*info
->read_memory_func
) (memaddr
, buffer
, INSNLEN
, info
);
1976 if (endianness
== BFD_ENDIAN_BIG
)
1977 insn
= (unsigned long) bfd_getb32 (buffer
);
1979 insn
= (unsigned long) bfd_getl32 (buffer
);
1981 return print_insn_mips (memaddr
, insn
, info
);
1985 (*info
->memory_error_func
) (status
, memaddr
, info
);
1991 print_insn_big_mips (bfd_vma memaddr
, struct disassemble_info
*info
)
1993 return _print_insn_mips (memaddr
, info
, BFD_ENDIAN_BIG
);
1997 print_insn_little_mips (bfd_vma memaddr
, struct disassemble_info
*info
)
1999 return _print_insn_mips (memaddr
, info
, BFD_ENDIAN_LITTLE
);
2003 print_mips_disassembler_options (FILE *stream
)
2007 fprintf (stream
, _("\n\
2008 The following MIPS specific disassembler options are supported for use\n\
2009 with the -M switch (multiple options should be separated by commas):\n"));
2011 fprintf (stream
, _("\n\
2012 gpr-names=ABI Print GPR names according to specified ABI.\n\
2013 Default: based on binary being disassembled.\n"));
2015 fprintf (stream
, _("\n\
2016 fpr-names=ABI Print FPR names according to specified ABI.\n\
2017 Default: numeric.\n"));
2019 fprintf (stream
, _("\n\
2020 cp0-names=ARCH Print CP0 register names according to\n\
2021 specified architecture.\n\
2022 Default: based on binary being disassembled.\n"));
2024 fprintf (stream
, _("\n\
2025 hwr-names=ARCH Print HWR names according to specified \n\
2027 Default: based on binary being disassembled.\n"));
2029 fprintf (stream
, _("\n\
2030 reg-names=ABI Print GPR and FPR names according to\n\
2031 specified ABI.\n"));
2033 fprintf (stream
, _("\n\
2034 reg-names=ARCH Print CP0 register and HWR names according to\n\
2035 specified architecture.\n"));
2037 fprintf (stream
, _("\n\
2038 For the options above, the following values are supported for \"ABI\":\n\
2040 for (i
= 0; i
< ARRAY_SIZE (mips_abi_choices
); i
++)
2041 fprintf (stream
, " %s", mips_abi_choices
[i
].name
);
2042 fprintf (stream
, _("\n"));
2044 fprintf (stream
, _("\n\
2045 For the options above, The following values are supported for \"ARCH\":\n\
2047 for (i
= 0; i
< ARRAY_SIZE (mips_arch_choices
); i
++)
2048 if (*mips_arch_choices
[i
].name
!= '\0')
2049 fprintf (stream
, " %s", mips_arch_choices
[i
].name
);
2050 fprintf (stream
, _("\n"));
2052 fprintf (stream
, _("\n"));