* config/tc-d10v.c (write_2_short): Fix bug that wouldn't allow
[deliverable/binutils-gdb.git] / opcodes / mips-opc.c
1 /* mips.h. Mips opcode list for GDB, the GNU debugger.
2 Copyright 1993, 1994, 1995, 1996, 1997 Free Software Foundation, Inc.
3 Contributed by Ralph Campbell and OSF
4 Commented and modified by Ian Lance Taylor, Cygnus Support
5
6 This file is part of GDB, GAS, and the GNU binutils.
7
8 GDB, GAS, and the GNU binutils are free software; you can redistribute
9 them and/or modify them under the terms of the GNU General Public
10 License as published by the Free Software Foundation; either version
11 1, or (at your option) any later version.
12
13 GDB, GAS, and the GNU binutils are distributed in the hope that they
14 will be useful, but WITHOUT ANY WARRANTY; without even the implied
15 warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See
16 the GNU General Public License for more details.
17
18 You should have received a copy of the GNU General Public License
19 along with this file; see the file COPYING. If not, write to the Free
20 Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
21
22 #include <stdio.h>
23 #include "ansidecl.h"
24 #include "opcode/mips.h"
25
26 /* Short hand so the lines aren't too long. */
27
28 #define LDD INSN_LOAD_MEMORY_DELAY
29 #define LCD INSN_LOAD_COPROC_DELAY
30 #define UBD INSN_UNCOND_BRANCH_DELAY
31 #define CBD INSN_COND_BRANCH_DELAY
32 #define COD INSN_COPROC_MOVE_DELAY
33 #define CLD INSN_COPROC_MEMORY_DELAY
34 #define CBL INSN_COND_BRANCH_LIKELY
35 #define TRAP INSN_TRAP
36 #define SM INSN_STORE_MEMORY
37
38 #define WR_d INSN_WRITE_GPR_D
39 #define WR_t INSN_WRITE_GPR_T
40 #define WR_31 INSN_WRITE_GPR_31
41 #define WR_D INSN_WRITE_FPR_D
42 #define WR_T INSN_WRITE_FPR_T
43 #define WR_S INSN_WRITE_FPR_S
44 #define RD_s INSN_READ_GPR_S
45 #define RD_b INSN_READ_GPR_S
46 #define RD_t INSN_READ_GPR_T
47 #define RD_S INSN_READ_FPR_S
48 #define RD_T INSN_READ_FPR_T
49 #define RD_R INSN_READ_FPR_R
50 #define WR_CC INSN_WRITE_COND_CODE
51 #define RD_CC INSN_READ_COND_CODE
52 #define RD_C0 INSN_COP
53 #define RD_C1 INSN_COP
54 #define RD_C2 INSN_COP
55 #define RD_C3 INSN_COP
56 #define WR_C0 INSN_COP
57 #define WR_C1 INSN_COP
58 #define WR_C2 INSN_COP
59 #define WR_C3 INSN_COP
60 #define WR_HI INSN_WRITE_HI
61 #define WR_LO INSN_WRITE_LO
62 #define RD_HI INSN_READ_HI
63 #define RD_LO INSN_READ_LO
64
65 #define I1 INSN_ISA1
66 #define I2 INSN_ISA2
67 #define I3 INSN_ISA3
68 #define I4 INSN_ISA4
69 #define P3 INSN_4650
70 #define L1 INSN_4010
71 #define V1 INSN_4100
72 #define T3 INSN_3900
73
74 /* start-sanitize-r5900 */
75 #define T5 INSN_5900
76 /* end-sanitize-r5900 */
77
78 #define G1 (T3 \
79 /* start-sanitize-r5900 */ \
80 | T5 \
81 /* end-sanitize-r5900 */ \
82 )
83
84
85 /* The order of overloaded instructions matters. Label arguments and
86 register arguments look the same. Instructions that can have either
87 for arguments must apear in the correct order in this table for the
88 assembler to pick the right one. In other words, entries with
89 immediate operands must apear after the same instruction with
90 registers.
91
92 Many instructions are short hand for other instructions (i.e., The
93 jal <register> instruction is short for jalr <register>). */
94
95 const struct mips_opcode mips_builtin_opcodes[] = {
96 /* These instructions appear first so that the disassembler will find
97 them first. The assemblers uses a hash table based on the
98 instruction name anyhow. */
99 /* name, args, mask, match, pinfo */
100 {"nop", "", 0x00000000, 0xffffffff, 0, I1 },
101 {"li", "t,j", 0x24000000, 0xffe00000, WR_t, I1 }, /* addiu */
102 {"li", "t,i", 0x34000000, 0xffe00000, WR_t, I1 }, /* ori */
103 {"li", "t,I", 0, (int) M_LI, INSN_MACRO },
104 {"move", "d,s", 0x0000002d, 0xfc1f07ff, WR_d|RD_s, I3 },/* daddu */
105 {"move", "d,s", 0x00000021, 0xfc1f07ff, WR_d|RD_s, I1 },/* addu */
106 {"move", "d,s", 0x00000025, 0xfc1f07ff, WR_d|RD_s, I1 },/* or */
107 {"b", "p", 0x10000000, 0xffff0000, UBD, I1 },/* beq 0,0 */
108 {"b", "p", 0x04010000, 0xffff0000, UBD, I1 },/* bgez 0 */
109 {"bal", "p", 0x04110000, 0xffff0000, UBD|WR_31, I1 },/* bgezal 0*/
110
111 {"abs", "d,v", 0, (int) M_ABS, INSN_MACRO },
112 {"abs.s", "D,V", 0x46000005, 0xffff003f, WR_D|RD_S|FP_S, I1 },
113 {"abs.d", "D,V", 0x46200005, 0xffff003f, WR_D|RD_S|FP_D, I1 },
114 {"add", "d,v,t", 0x00000020, 0xfc0007ff, WR_d|RD_s|RD_t, I1 },
115 {"add", "t,r,I", 0, (int) M_ADD_I, INSN_MACRO },
116 {"add.s", "D,V,T", 0x46000000, 0xffe0003f, WR_D|RD_S|RD_T|FP_S, I1},
117 {"add.d", "D,V,T", 0x46200000, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, I1},
118 {"addi", "t,r,j", 0x20000000, 0xfc000000, WR_t|RD_s, I1 },
119 {"addiu", "t,r,j", 0x24000000, 0xfc000000, WR_t|RD_s, I1 },
120 {"addu", "d,v,t", 0x00000021, 0xfc0007ff, WR_d|RD_s|RD_t, I1 },
121 {"addu", "t,r,I", 0, (int) M_ADDU_I, INSN_MACRO },
122 {"and", "d,v,t", 0x00000024, 0xfc0007ff, WR_d|RD_s|RD_t, I1 },
123 {"and", "t,r,I", 0, (int) M_AND_I, INSN_MACRO },
124 {"andi", "t,r,i", 0x30000000, 0xfc000000, WR_t|RD_s, I1 },
125 /* b is at the top of the table. */
126 /* bal is at the top of the table. */
127 {"bc0f", "p", 0x41000000, 0xffff0000, CBD|RD_CC, I1 },
128 {"bc0fl", "p", 0x41020000, 0xffff0000, CBL|RD_CC, I2|T3 },
129 {"bc1f", "p", 0x45000000, 0xffff0000, CBD|RD_CC|FP_S, I1 },
130 {"bc1f", "N,p", 0x45000000, 0xffe30000, CBD|RD_CC|FP_S, I4 },
131 {"bc1fl", "p", 0x45020000, 0xffff0000, CBL|RD_CC|FP_S, I2|T3 },
132 {"bc1fl", "N,p", 0x45020000, 0xffe30000, CBL|RD_CC|FP_S, I4 },
133 {"bc2f", "p", 0x49000000, 0xffff0000, CBD|RD_CC, I1 },
134 {"bc2fl", "p", 0x49020000, 0xffff0000, CBL|RD_CC, I2|T3 },
135 {"bc3f", "p", 0x4d000000, 0xffff0000, CBD|RD_CC, I1 },
136 {"bc3fl", "p", 0x4d020000, 0xffff0000, CBL|RD_CC, I2|T3 },
137 {"bc0t", "p", 0x41010000, 0xffff0000, CBD|RD_CC, I1 },
138 {"bc0tl", "p", 0x41030000, 0xffff0000, CBL|RD_CC, I2|T3 },
139 {"bc1t", "p", 0x45010000, 0xffff0000, CBD|RD_CC|FP_S, I1 },
140 {"bc1t", "N,p", 0x45010000, 0xffe30000, CBD|RD_CC|FP_S, I4 },
141 {"bc1tl", "p", 0x45030000, 0xffff0000, CBL|RD_CC|FP_S, I2|T3 },
142 {"bc1tl", "N,p", 0x45030000, 0xffe30000, CBL|RD_CC|FP_S, I4 },
143 {"bc2t", "p", 0x49010000, 0xffff0000, CBD|RD_CC, I1 },
144 {"bc2tl", "p", 0x49030000, 0xffff0000, CBL|RD_CC, I2|T3 },
145 {"bc3t", "p", 0x4d010000, 0xffff0000, CBD|RD_CC, I1 },
146 {"bc3tl", "p", 0x4d030000, 0xffff0000, CBL|RD_CC, I2|T3 },
147 {"beqz", "s,p", 0x10000000, 0xfc1f0000, CBD|RD_s, I1 },
148 {"beqzl", "s,p", 0x50000000, 0xfc1f0000, CBL|RD_s, I2 },
149 {"beq", "s,t,p", 0x10000000, 0xfc000000, CBD|RD_s|RD_t, I1 },
150 {"beq", "s,I,p", 0, (int) M_BEQ_I, INSN_MACRO },
151 {"beql", "s,t,p", 0x50000000, 0xfc000000, CBL|RD_s|RD_t, I2|T3 },
152 {"beql", "s,I,p", 2, (int) M_BEQL_I, INSN_MACRO },
153 {"bge", "s,t,p", 0, (int) M_BGE, INSN_MACRO },
154 {"bge", "s,I,p", 0, (int) M_BGE_I, INSN_MACRO },
155 {"bgel", "s,t,p", 2, (int) M_BGEL, INSN_MACRO },
156 {"bgel", "s,I,p", 2, (int) M_BGEL_I, INSN_MACRO },
157 {"bgeu", "s,t,p", 0, (int) M_BGEU, INSN_MACRO },
158 {"bgeu", "s,I,p", 0, (int) M_BGEU_I, INSN_MACRO },
159 {"bgeul", "s,t,p", 2, (int) M_BGEUL, INSN_MACRO },
160 {"bgeul", "s,I,p", 2, (int) M_BGEUL_I, INSN_MACRO },
161 {"bgez", "s,p", 0x04010000, 0xfc1f0000, CBD|RD_s, I1 },
162 {"bgezl", "s,p", 0x04030000, 0xfc1f0000, CBL|RD_s, I2|T3 },
163 {"bgezal", "s,p", 0x04110000, 0xfc1f0000, CBD|RD_s|WR_31, I1 },
164 {"bgezall", "s,p", 0x04130000, 0xfc1f0000, CBL|RD_s, I2|T3 },
165 {"bgt", "s,t,p", 0, (int) M_BGT, INSN_MACRO },
166 {"bgt", "s,I,p", 0, (int) M_BGT_I, INSN_MACRO },
167 {"bgtl", "s,t,p", 2, (int) M_BGTL, INSN_MACRO },
168 {"bgtl", "s,I,p", 2, (int) M_BGTL_I, INSN_MACRO },
169 {"bgtu", "s,t,p", 0, (int) M_BGTU, INSN_MACRO },
170 {"bgtu", "s,I,p", 0, (int) M_BGTU_I, INSN_MACRO },
171 {"bgtul", "s,t,p", 2, (int) M_BGTUL, INSN_MACRO },
172 {"bgtul", "s,I,p", 2, (int) M_BGTUL_I, INSN_MACRO },
173 {"bgtz", "s,p", 0x1c000000, 0xfc1f0000, CBD|RD_s, I1 },
174 {"bgtzl", "s,p", 0x5c000000, 0xfc1f0000, CBL|RD_s, I2|T3 },
175 {"ble", "s,t,p", 0, (int) M_BLE, INSN_MACRO },
176 {"ble", "s,I,p", 0, (int) M_BLE_I, INSN_MACRO },
177 {"blel", "s,t,p", 2, (int) M_BLEL, INSN_MACRO },
178 {"blel", "s,I,p", 2, (int) M_BLEL_I, INSN_MACRO },
179 {"bleu", "s,t,p", 0, (int) M_BLEU, INSN_MACRO },
180 {"bleu", "s,I,p", 0, (int) M_BLEU_I, INSN_MACRO },
181 {"bleul", "s,t,p", 2, (int) M_BLEUL, INSN_MACRO },
182 {"bleul", "s,I,p", 2, (int) M_BLEUL_I, INSN_MACRO },
183 {"blez", "s,p", 0x18000000, 0xfc1f0000, CBD|RD_s, I1 },
184 {"blezl", "s,p", 0x58000000, 0xfc1f0000, CBL|RD_s, I2|T3 },
185 {"blt", "s,t,p", 0, (int) M_BLT, INSN_MACRO },
186 {"blt", "s,I,p", 0, (int) M_BLT_I, INSN_MACRO },
187 {"bltl", "s,t,p", 2, (int) M_BLTL, INSN_MACRO },
188 {"bltl", "s,I,p", 2, (int) M_BLTL_I, INSN_MACRO },
189 {"bltu", "s,t,p", 0, (int) M_BLTU, INSN_MACRO },
190 {"bltu", "s,I,p", 0, (int) M_BLTU_I, INSN_MACRO },
191 {"bltul", "s,t,p", 2, (int) M_BLTUL, INSN_MACRO },
192 {"bltul", "s,I,p", 2, (int) M_BLTUL_I, INSN_MACRO },
193 {"bltz", "s,p", 0x04000000, 0xfc1f0000, CBD|RD_s, I1 },
194 {"bltzl", "s,p", 0x04020000, 0xfc1f0000, CBL|RD_s, I2|T3 },
195 {"bltzal", "s,p", 0x04100000, 0xfc1f0000, CBD|RD_s|WR_31, I1 },
196 {"bltzall", "s,p", 0x04120000, 0xfc1f0000, CBL|RD_s, I2|T3 },
197 {"bnez", "s,p", 0x14000000, 0xfc1f0000, CBD|RD_s, I1 },
198 {"bnezl", "s,p", 0x54000000, 0xfc1f0000, CBL|RD_s, I2 },
199 {"bne", "s,t,p", 0x14000000, 0xfc000000, CBD|RD_s|RD_t, I1 },
200 {"bne", "s,I,p", 0, (int) M_BNE_I, INSN_MACRO },
201 {"bnel", "s,t,p", 0x54000000, 0xfc000000, CBL|RD_s|RD_t, I2|T3 },
202 {"bnel", "s,I,p", 2, (int) M_BNEL_I, INSN_MACRO },
203 {"break", "", 0x0000000d, 0xffffffff, TRAP, I1 },
204 {"break", "c", 0x0000000d, 0xfc00003f, TRAP, I1 },
205 {"c.f.d", "S,T", 0x46200030, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, I1 },
206 {"c.f.d", "M,S,T", 0x46200030, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I4 },
207 {"c.f.s", "S,T", 0x46000030, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, I1 },
208 {"c.f.s", "M,S,T", 0x46000030, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, I4 },
209 {"c.un.d", "S,T", 0x46200031, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, I1 },
210 {"c.un.d", "M,S,T", 0x46200031, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I4 },
211 {"c.un.s", "S,T", 0x46000031, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, I1 },
212 {"c.un.s", "M,S,T", 0x46000031, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, I4 },
213 {"c.eq.d", "S,T", 0x46200032, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, I1 },
214 {"c.eq.d", "M,S,T", 0x46200032, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I4 },
215 {"c.eq.s", "S,T", 0x46000032, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, I1 },
216 {"c.eq.s", "M,S,T", 0x46000032, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, I4 },
217 {"c.ueq.d", "S,T", 0x46200033, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, I1 },
218 {"c.ueq.d", "M,S,T", 0x46200033, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I4 },
219 {"c.ueq.s", "S,T", 0x46000033, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, I1 },
220 {"c.ueq.s", "M,S,T", 0x46000033, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, I4 },
221 {"c.olt.d", "S,T", 0x46200034, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, I1 },
222 {"c.olt.d", "M,S,T", 0x46200034, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I4 },
223 {"c.olt.s", "S,T", 0x46000034, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, I1 },
224 {"c.olt.s", "M,S,T", 0x46000034, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, I4 },
225 {"c.ult.d", "S,T", 0x46200035, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, I1 },
226 {"c.ult.d", "M,S,T", 0x46200035, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I4 },
227 {"c.ult.s", "S,T", 0x46000035, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, I1 },
228 {"c.ult.s", "M,S,T", 0x46000035, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, I4 },
229 {"c.ole.d", "S,T", 0x46200036, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, I1 },
230 {"c.ole.d", "M,S,T", 0x46200036, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I4 },
231 {"c.ole.s", "S,T", 0x46000036, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, I1 },
232 {"c.ole.s", "M,S,T", 0x46000036, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, I4 },
233 {"c.ule.d", "S,T", 0x46200037, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, I1 },
234 {"c.ule.d", "M,S,T", 0x46200037, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I4 },
235 {"c.ule.s", "S,T", 0x46000037, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, I1 },
236 {"c.ule.s", "M,S,T", 0x46000037, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, I4 },
237 {"c.sf.d", "S,T", 0x46200038, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, I1 },
238 {"c.sf.d", "M,S,T", 0x46200038, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I4 },
239 {"c.sf.s", "S,T", 0x46000038, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, I1 },
240 {"c.sf.s", "M,S,T", 0x46000038, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, I4 },
241 {"c.ngle.d","S,T", 0x46200039, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, I1 },
242 {"c.ngle.d","M,S,T", 0x46200039, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I4 },
243 {"c.ngle.s","S,T", 0x46000039, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, I1 },
244 {"c.ngle.s","M,S,T", 0x46000039, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, I4 },
245 {"c.seq.d", "S,T", 0x4620003a, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, I1 },
246 {"c.seq.d", "M,S,T", 0x4620003a, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I4 },
247 {"c.seq.s", "S,T", 0x4600003a, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, I1 },
248 {"c.seq.s", "M,S,T", 0x4600003a, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, I4 },
249 {"c.ngl.d", "S,T", 0x4620003b, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, I1 },
250 {"c.ngl.d", "M,S,T", 0x4620003b, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I4 },
251 {"c.ngl.s", "S,T", 0x4600003b, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, I1 },
252 {"c.ngl.s", "M,S,T", 0x4600003b, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, I4 },
253 {"c.lt.d", "S,T", 0x4620003c, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, I1 },
254 {"c.lt.d", "M,S,T", 0x4620003c, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I4 },
255 {"c.lt.s", "S,T", 0x4600003c, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, I1 },
256 {"c.lt.s", "M,S,T", 0x4600003c, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, I4 },
257 {"c.nge.d", "S,T", 0x4620003d, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, I1 },
258 {"c.nge.d", "M,S,T", 0x4620003d, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I4 },
259 {"c.nge.s", "S,T", 0x4600003d, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, I1 },
260 {"c.nge.s", "M,S,T", 0x4600003d, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, I4 },
261 {"c.le.d", "S,T", 0x4620003e, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, I1 },
262 {"c.le.d", "M,S,T", 0x4620003e, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I4 },
263 {"c.le.s", "S,T", 0x4600003e, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, I1 },
264 {"c.le.s", "M,S,T", 0x4600003e, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, I4 },
265 {"c.ngt.d", "S,T", 0x4620003f, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, I1 },
266 {"c.ngt.d", "M,S,T", 0x4620003f, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I4 },
267 {"c.ngt.s", "S,T", 0x4600003f, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, I1 },
268 {"c.ngt.s", "M,S,T", 0x4600003f, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, I4 },
269 {"cache", "k,o(b)", 0xbc000000, 0xfc000000, RD_b, I3 },
270 {"ceil.l.d", "D,S", 0x4620000a, 0xffff003f, WR_D|RD_S|FP_D, I3 },
271 {"ceil.l.s", "D,S", 0x4600000a, 0xffff003f, WR_D|RD_S|FP_S, I3 },
272 {"ceil.w.d", "D,S", 0x4620000e, 0xffff003f, WR_D|RD_S|FP_D, I2 },
273 {"ceil.w.s", "D,S", 0x4600000e, 0xffff003f, WR_D|RD_S|FP_S, I2 },
274 {"cfc0", "t,G", 0x40400000, 0xffe007ff, LCD|WR_t|RD_C0, I1 },
275 {"cfc1", "t,G", 0x44400000, 0xffe007ff, LCD|WR_t|RD_C1|FP_S, I1 },
276 {"cfc1", "t,S", 0x44400000, 0xffe007ff, LCD|WR_t|RD_C1|FP_S, I1 },
277 {"cfc2", "t,G", 0x48400000, 0xffe007ff, LCD|WR_t|RD_C2, I1 },
278 {"cfc3", "t,G", 0x4c400000, 0xffe007ff, LCD|WR_t|RD_C3, I1 },
279 {"ctc0", "t,G", 0x40c00000, 0xffe007ff, COD|RD_t|WR_CC, I1 },
280 {"ctc1", "t,G", 0x44c00000, 0xffe007ff, COD|RD_t|WR_CC|FP_S, I1 },
281 {"ctc1", "t,S", 0x44c00000, 0xffe007ff, COD|RD_t|WR_CC|FP_S, I1 },
282 {"ctc2", "t,G", 0x48c00000, 0xffe007ff, COD|RD_t|WR_CC, I1 },
283 {"ctc3", "t,G", 0x4cc00000, 0xffe007ff, COD|RD_t|WR_CC, I1 },
284 {"cvt.d.l", "D,S", 0x46a00021, 0xffff003f, WR_D|RD_S|FP_D, I3 },
285 {"cvt.d.s", "D,S", 0x46000021, 0xffff003f, WR_D|RD_S|FP_D|FP_S, I1 },
286 {"cvt.d.w", "D,S", 0x46800021, 0xffff003f, WR_D|RD_S|FP_D, I1 },
287 {"cvt.l.d", "D,S", 0x46200025, 0xffff003f, WR_D|RD_S|FP_D, I3 },
288 {"cvt.l.s", "D,S", 0x46000025, 0xffff003f, WR_D|RD_S|FP_S, I3 },
289 {"cvt.s.l", "D,S", 0x46a00020, 0xffff003f, WR_D|RD_S|FP_S, I3 },
290 {"cvt.s.d", "D,S", 0x46200020, 0xffff003f, WR_D|RD_S|FP_S|FP_D, I1 },
291 {"cvt.s.w", "D,S", 0x46800020, 0xffff003f, WR_D|RD_S|FP_S, I1 },
292 {"cvt.w.d", "D,S", 0x46200024, 0xffff003f, WR_D|RD_S|FP_D, I1 },
293 {"cvt.w.s", "D,S", 0x46000024, 0xffff003f, WR_D|RD_S|FP_S, I1 },
294 {"dabs", "d,v", 3, (int) M_DABS, INSN_MACRO },
295 {"dadd", "d,v,t", 0x0000002c, 0xfc0007ff, WR_d|RD_s|RD_t, I3 },
296 {"dadd", "t,r,I", 3, (int) M_DADD_I, INSN_MACRO },
297 {"daddi", "t,r,j", 0x60000000, 0xfc000000, WR_t|RD_s, I3 },
298 {"daddiu", "t,r,j", 0x64000000, 0xfc000000, WR_t|RD_s, I3 },
299 {"daddu", "d,v,t", 0x0000002d, 0xfc0007ff, WR_d|RD_s|RD_t, I3 },
300 {"daddu", "t,r,I", 3, (int) M_DADDU_I, INSN_MACRO },
301 /* dctr and dctw are used on the r5000. */
302 {"dctr", "o(b)", 0xbc050000, 0xfc1f0000, RD_b, I3 },
303 {"dctw", "o(b)", 0xbc090000, 0xfc1f0000, RD_b, I3 },
304 {"deret", "", 0x4200001f, 0xffffffff, 0, T3 },
305 /* For ddiv, see the comments about div. */
306 {"ddiv", "z,s,t", 0x0000001e, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO, I3 },
307 {"ddiv", "d,v,t", 3, (int) M_DDIV_3, INSN_MACRO },
308 {"ddiv", "d,v,I", 3, (int) M_DDIV_3I, INSN_MACRO },
309 /* For ddivu, see the comments about div. */
310 {"ddivu", "z,s,t", 0x0000001f, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO, I3 },
311 {"ddivu", "d,v,t", 3, (int) M_DDIVU_3, INSN_MACRO },
312 {"ddivu", "d,v,I", 3, (int) M_DDIVU_3I, INSN_MACRO },
313 /* The MIPS assembler treats the div opcode with two operands as
314 though the first operand appeared twice (the first operand is both
315 a source and a destination). To get the div machine instruction,
316 you must use an explicit destination of $0. */
317 {"div", "z,s,t", 0x0000001a, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO, I1 },
318 {"div", "z,t", 0x0000001a, 0xffe0ffff, RD_s|RD_t|WR_HI|WR_LO, I1 },
319 {"div", "d,v,t", 0, (int) M_DIV_3, INSN_MACRO },
320 {"div", "d,v,I", 0, (int) M_DIV_3I, INSN_MACRO },
321 /* start-sanitize-r5900 */
322 {"div1", "s,t", 0x7000001a, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO, T5 },
323 /* end-sanitize-r5900 */
324 {"div.d", "D,V,T", 0x46200003, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, I1 },
325 {"div.s", "D,V,T", 0x46000003, 0xffe0003f, WR_D|RD_S|RD_T|FP_S, I1 },
326 /* For divu, see the comments about div. */
327 {"divu", "z,s,t", 0x0000001b, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO, I1 },
328 {"divu", "z,t", 0x0000001b, 0xffe0ffff, RD_s|RD_t|WR_HI|WR_LO, I1 },
329 {"divu", "d,v,t", 0, (int) M_DIVU_3, INSN_MACRO },
330 {"divu", "d,v,I", 0, (int) M_DIVU_3I, INSN_MACRO },
331 /* start-sanitize-r5900 */
332 {"divu1", "s,t", 0x7000001b, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO, T5 },
333 /* end-sanitize-r5900 */
334 {"dla", "t,A(b)", 3, (int) M_DLA_AB, INSN_MACRO },
335 {"dli", "t,j", 0x24000000, 0xffe00000, WR_t, I3 }, /* addiu */
336 {"dli", "t,i", 0x34000000, 0xffe00000, WR_t, I3 }, /* ori */
337 {"dli", "t,I", 3, (int) M_DLI, INSN_MACRO },
338 {"dmadd16", "s,t", 0x00000029, 0xfc00ffff, RD_s|RD_t|WR_LO|RD_LO, V1 },
339 {"dmfc0", "t,G", 0x40200000, 0xffe007ff, LCD|WR_t|RD_C0, I3 },
340 {"dmtc0", "t,G", 0x40a00000, 0xffe007ff, COD|RD_t|WR_C0|WR_CC, I3 },
341 {"dmfc1", "t,S", 0x44200000, 0xffe007ff, LCD|WR_t|RD_S|FP_S, I3 },
342 {"dmtc1", "t,S", 0x44a00000, 0xffe007ff, COD|RD_t|WR_S|FP_S, I3 },
343 {"dmul", "d,v,t", 3, (int) M_DMUL, INSN_MACRO },
344 {"dmul", "d,v,I", 3, (int) M_DMUL_I, INSN_MACRO },
345 {"dmulo", "d,v,t", 3, (int) M_DMULO, INSN_MACRO },
346 {"dmulo", "d,v,I", 3, (int) M_DMULO_I, INSN_MACRO },
347 {"dmulou", "d,v,t", 3, (int) M_DMULOU, INSN_MACRO },
348 {"dmulou", "d,v,I", 3, (int) M_DMULOU_I, INSN_MACRO },
349 {"dmult", "s,t", 0x0000001c, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO, I3 },
350 {"dmultu", "s,t", 0x0000001d, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO, I3 },
351 {"dneg", "d,w", 0x0000002e, 0xffe007ff, WR_d|RD_t, I3 }, /* dsub 0 */
352 {"dnegu", "d,w", 0x0000002f, 0xffe007ff, WR_d|RD_t, I3 }, /* dsubu 0*/
353 {"drem", "z,s,t", 0x0000001e, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO, I3 },
354 {"drem", "d,v,t", 3, (int) M_DREM_3, INSN_MACRO },
355 {"drem", "d,v,I", 3, (int) M_DREM_3I, INSN_MACRO },
356 {"dremu", "z,s,t", 0x0000001f, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO, I3 },
357 {"dremu", "d,v,t", 3, (int) M_DREMU_3, INSN_MACRO },
358 {"dremu", "d,v,I", 3, (int) M_DREMU_3I, INSN_MACRO },
359 {"dsllv", "d,t,s", 0x00000014, 0xfc0007ff, WR_d|RD_t|RD_s, I3 },
360 {"dsll32", "d,w,<", 0x0000003c, 0xffe0003f, WR_d|RD_t, I3 },
361 {"dsll", "d,w,s", 0x00000014, 0xfc0007ff, WR_d|RD_t|RD_s, I3 }, /* dsllv */
362 {"dsll", "d,w,>", 0x0000003c, 0xffe0003f, WR_d|RD_t, I3 }, /* dsll32 */
363 {"dsll", "d,w,<", 0x00000038, 0xffe0003f, WR_d|RD_t, I3 },
364 {"dsrav", "d,t,s", 0x00000017, 0xfc0007ff, WR_d|RD_t|RD_s, I3 },
365 {"dsra32", "d,w,<", 0x0000003f, 0xffe0003f, WR_d|RD_t, I3 },
366 {"dsra", "d,w,s", 0x00000017, 0xfc0007ff, WR_d|RD_t|RD_s, I3 }, /* dsrav */
367 {"dsra", "d,w,>", 0x0000003f, 0xffe0003f, WR_d|RD_t, I3 }, /* dsra32 */
368 {"dsra", "d,w,<", 0x0000003b, 0xffe0003f, WR_d|RD_t, I3 },
369 {"dsrlv", "d,t,s", 0x00000016, 0xfc0007ff, WR_d|RD_t|RD_s, I3 },
370 {"dsrl32", "d,w,<", 0x0000003e, 0xffe0003f, WR_d|RD_t, I3 },
371 {"dsrl", "d,w,s", 0x00000016, 0xfc0007ff, WR_d|RD_t|RD_s, I3 }, /* dsrlv */
372 {"dsrl", "d,w,>", 0x0000003e, 0xffe0003f, WR_d|RD_t, I3 }, /* dsrl32 */
373 {"dsrl", "d,w,<", 0x0000003a, 0xffe0003f, WR_d|RD_t, I3 },
374 {"dsub", "d,v,t", 0x0000002e, 0xfc0007ff, WR_d|RD_s|RD_t, I3 },
375 {"dsub", "d,v,I", 3, (int) M_DSUB_I, INSN_MACRO },
376 {"dsubu", "d,v,t", 0x0000002f, 0xfc0007ff, WR_d|RD_s|RD_t, I3 },
377 {"dsubu", "d,v,I", 3, (int) M_DSUBU_I, INSN_MACRO },
378 {"eret", "", 0x42000018, 0xffffffff, 0, I3 },
379 {"floor.l.d", "D,S", 0x4620000b, 0xffff003f, WR_D|RD_S|FP_D, I3 },
380 {"floor.l.s", "D,S", 0x4600000b, 0xffff003f, WR_D|RD_S|FP_S, I3 },
381 {"floor.w.d", "D,S", 0x4620000f, 0xffff003f, WR_D|RD_S|FP_D, I2 },
382 {"floor.w.s", "D,S", 0x4600000f, 0xffff003f, WR_D|RD_S|FP_S, I2 },
383 {"flushi", "", 0xbc010000, 0xffffffff, 0, L1 },
384 {"flushd", "", 0xbc020000, 0xffffffff, 0, L1 },
385 {"flushid", "", 0xbc030000, 0xffffffff, 0, L1 },
386 {"hibernate","", 0x42000023, 0xffffffff, 0, V1 },
387 {"jr", "s", 0x00000008, 0xfc1fffff, UBD|RD_s, I1 },
388 {"j", "s", 0x00000008, 0xfc1fffff, UBD|RD_s, I1 }, /* jr */
389 /* SVR4 PIC code requires special handling for j, so it must be a
390 macro. */
391 {"j", "a", 0, (int) M_J_A, INSN_MACRO },
392 /* This form of j is used by the disassembler and internally by the
393 assembler, but will never match user input (because the line above
394 will match first). */
395 {"j", "a", 0x08000000, 0xfc000000, UBD, I1 },
396 {"jalr", "s", 0x0000f809, 0xfc1fffff, UBD|RD_s|WR_d, I1 },
397 {"jalr", "d,s", 0x00000009, 0xfc1f07ff, UBD|RD_s|WR_d, I1 },
398 /* SVR4 PIC code requires special handling for jal, so it must be a
399 macro. */
400 {"jal", "d,s", 0, (int) M_JAL_2, INSN_MACRO },
401 {"jal", "s", 0, (int) M_JAL_1, INSN_MACRO },
402 {"jal", "a", 0, (int) M_JAL_A, INSN_MACRO },
403 /* This form of jal is used by the disassembler and internally by the
404 assembler, but will never match user input (because the line above
405 will match first). */
406 {"jal", "a", 0x0c000000, 0xfc000000, UBD|WR_31, I1 },
407 {"jalx", "a", 0x74000000, 0xfc000000, UBD|WR_31, I1 },
408 {"la", "t,A(b)", 0, (int) M_LA_AB, INSN_MACRO },
409 {"lb", "t,o(b)", 0x80000000, 0xfc000000, LDD|RD_b|WR_t, I1 },
410 {"lb", "t,A(b)", 0, (int) M_LB_AB, INSN_MACRO },
411 {"lbu", "t,o(b)", 0x90000000, 0xfc000000, LDD|RD_b|WR_t, I1 },
412 {"lbu", "t,A(b)", 0, (int) M_LBU_AB, INSN_MACRO },
413 {"ld", "t,o(b)", 0xdc000000, 0xfc000000, WR_t|RD_b, I3 },
414 {"ld", "t,o(b)", 0, (int) M_LD_OB, INSN_MACRO },
415 {"ld", "t,A(b)", 0, (int) M_LD_AB, INSN_MACRO },
416 {"ldc1", "T,o(b)", 0xd4000000, 0xfc000000, CLD|RD_b|WR_T|FP_D, I2 },
417 {"ldc1", "E,o(b)", 0xd4000000, 0xfc000000, CLD|RD_b|WR_T|FP_D, I2 },
418 {"ldc1", "T,A(b)", 2, (int) M_LDC1_AB, INSN_MACRO },
419 {"ldc1", "E,A(b)", 2, (int) M_LDC1_AB, INSN_MACRO },
420 {"l.d", "T,o(b)", 0xd4000000, 0xfc000000, CLD|RD_b|WR_T|FP_D, I2 }, /* ldc1 */
421 {"l.d", "T,o(b)", 0, (int) M_L_DOB, INSN_MACRO },
422 {"l.d", "T,A(b)", 0, (int) M_L_DAB, INSN_MACRO },
423 {"ldc2", "E,o(b)", 0xd8000000, 0xfc000000, CLD|RD_b|WR_CC, I2 },
424 {"ldc2", "E,A(b)", 2, (int) M_LDC2_AB, INSN_MACRO },
425 {"ldc3", "E,o(b)", 0xdc000000, 0xfc000000, CLD|RD_b|WR_CC, I2 },
426 {"ldc3", "E,A(b)", 2, (int) M_LDC3_AB, INSN_MACRO },
427 {"ldl", "t,o(b)", 0x68000000, 0xfc000000, LDD|WR_t|RD_b, I3 },
428 {"ldl", "t,A(b)", 3, (int) M_LDL_AB, INSN_MACRO },
429 {"ldr", "t,o(b)", 0x6c000000, 0xfc000000, LDD|WR_t|RD_b, I3 },
430 {"ldr", "t,A(b)", 3, (int) M_LDR_AB, INSN_MACRO },
431 {"ldxc1", "D,t(b)", 0x4c000001, 0xfc00f83f, LDD|WR_D|RD_t|RD_b, I4 },
432 {"lh", "t,o(b)", 0x84000000, 0xfc000000, LDD|RD_b|WR_t, I1 },
433 {"lh", "t,A(b)", 0, (int) M_LH_AB, INSN_MACRO },
434 {"lhu", "t,o(b)", 0x94000000, 0xfc000000, LDD|RD_b|WR_t, I1 },
435 {"lhu", "t,A(b)", 0, (int) M_LHU_AB, INSN_MACRO },
436 /* li is at the start of the table. */
437 {"li.d", "t,F", 0, (int) M_LI_D, INSN_MACRO },
438 {"li.d", "T,L", 0, (int) M_LI_DD, INSN_MACRO },
439 {"li.s", "t,f", 0, (int) M_LI_S, INSN_MACRO },
440 {"li.s", "T,l", 0, (int) M_LI_SS, INSN_MACRO },
441 {"ll", "t,o(b)", 0xc0000000, 0xfc000000, LDD|RD_b|WR_t, I2 },
442 {"ll", "t,A(b)", 2, (int) M_LL_AB, INSN_MACRO },
443 {"lld", "t,o(b)", 0xd0000000, 0xfc000000, LDD|RD_b|WR_t, I3 },
444 {"lld", "t,A(b)", 3, (int) M_LLD_AB, INSN_MACRO },
445 {"lui", "t,u", 0x3c000000, 0xffe00000, WR_t, I1 },
446 /* start-sanitize-r5900 */
447 {"lq", "t,o(b)", 0x78000000, 0xfc000000, WR_t|RD_b, T5 },
448 /* end-sanitize-r5900 */
449 {"lw", "t,o(b)", 0x8c000000, 0xfc000000, LDD|RD_b|WR_t, I1 },
450 {"lw", "t,A(b)", 0, (int) M_LW_AB, INSN_MACRO },
451 {"lwc0", "E,o(b)", 0xc0000000, 0xfc000000, CLD|RD_b|WR_CC, I1 },
452 {"lwc0", "E,A(b)", 0, (int) M_LWC0_AB, INSN_MACRO },
453 {"lwc1", "T,o(b)", 0xc4000000, 0xfc000000, CLD|RD_b|WR_T|FP_S, I1 },
454 {"lwc1", "E,o(b)", 0xc4000000, 0xfc000000, CLD|RD_b|WR_T|FP_S, I1 },
455 {"lwc1", "T,A(b)", 0, (int) M_LWC1_AB, INSN_MACRO },
456 {"lwc1", "E,A(b)", 0, (int) M_LWC1_AB, INSN_MACRO },
457 {"l.s", "T,o(b)", 0xc4000000, 0xfc000000, CLD|RD_b|WR_T|FP_S, I1 }, /* lwc1 */
458 {"l.s", "T,A(b)", 0, (int) M_LWC1_AB, INSN_MACRO },
459 {"lwc2", "E,o(b)", 0xc8000000, 0xfc000000, CLD|RD_b|WR_CC, I1 },
460 {"lwc2", "E,A(b)", 0, (int) M_LWC2_AB, INSN_MACRO },
461 {"lwc3", "E,o(b)", 0xcc000000, 0xfc000000, CLD|RD_b|WR_CC, I1 },
462 {"lwc3", "E,A(b)", 0, (int) M_LWC3_AB, INSN_MACRO },
463 {"lwl", "t,o(b)", 0x88000000, 0xfc000000, LDD|RD_b|WR_t, I1 },
464 {"lwl", "t,A(b)", 0, (int) M_LWL_AB, INSN_MACRO },
465 {"lcache", "t,o(b)", 0x88000000, 0xfc000000, LDD|RD_b|WR_t, I2 }, /* same */
466 {"lcache", "t,A(b)", 2, (int) M_LWL_AB, INSN_MACRO }, /* as lwl */
467 {"lwr", "t,o(b)", 0x98000000, 0xfc000000, LDD|RD_b|WR_t, I1 },
468 {"lwr", "t,A(b)", 0, (int) M_LWR_AB, INSN_MACRO },
469 {"flush", "t,o(b)", 0x98000000, 0xfc000000, LDD|RD_b|WR_t, I2 }, /* same */
470 {"flush", "t,A(b)", 2, (int) M_LWR_AB, INSN_MACRO }, /* as lwr */
471 {"lwu", "t,o(b)", 0x9c000000, 0xfc000000, LDD|RD_b|WR_t, I3 },
472 {"lwu", "t,A(b)", 3, (int) M_LWU_AB, INSN_MACRO },
473 {"lwxc1", "D,t(b)", 0x4c000000, 0xfc00f83f, LDD|WR_D|RD_t|RD_b, I4 },
474 {"mad", "s,t", 0x70000000, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO|RD_HI|RD_LO, P3 },
475 {"madu", "s,t", 0x70000001, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO|RD_HI|RD_LO, P3 },
476 {"addciu", "t,r,j", 0x70000000, 0xfc000000, WR_t|RD_s,L1 },
477 {"madd.d", "D,R,S,T", 0x4c000021, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D, I4 },
478 {"madd.s", "D,R,S,T", 0x4c000020, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_S, I4 },
479 /* start-sanitize-r5900 */
480 {"madd.s", "D,R,S,T", 0x4c000020, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_S, T5 },
481 /* end-sanitize-r5900 */
482 {"madd", "s,t", 0x0000001c, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO, L1 },
483 {"madd", "s,t", 0x70000000, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO, T3 },
484 {"madd", "d,s,t", 0x70000000, 0xfc0007ff, RD_s|RD_t|WR_HI|WR_LO|WR_d, T3 },
485 /* start-sanitize-r5900 */
486 {"madd", "s,t", 0x70000000, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO, T5 },
487 {"madd", "d,s,t", 0x70000000, 0xfc0007ff, RD_s|RD_t|WR_HI|WR_LO|WR_d, T5 },
488 {"madd1", "s,t", 0x70000020, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO, T5 },
489 {"madd1", "d,s,t", 0x70000020, 0xfc0007ff, RD_s|RD_t|WR_HI|WR_LO|WR_d, T5 },
490 /* end-sanitize-r5900 */
491 {"maddu", "s,t", 0x0000001d, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO, L1 },
492 {"maddu", "s,t", 0x70000001, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO, T3 },
493 {"maddu", "d,s,t", 0x70000001, 0xfc0007ff, RD_s|RD_t|WR_HI|WR_LO|WR_d, T3 },
494 /* start-sanitize-r5900 */
495 {"maddu", "s,t", 0x70000001, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO, T5 },
496 {"maddu", "d,s,t", 0x70000001, 0xfc0007ff, RD_s|RD_t|WR_HI|WR_LO|WR_d, T5 },
497 {"maddu1", "s,t", 0x70000021, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO, T5 },
498 {"maddu1", "d,s,t", 0x70000021, 0xfc0007ff, RD_s|RD_t|WR_HI|WR_LO|WR_d, T5 },
499 /* end-sanitize-r5900 */
500 {"madd16", "s,t", 0x00000028, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO|RD_HI|RD_LO, V1 },
501 {"mfc0", "t,G", 0x40000000, 0xffe007ff, LCD|WR_t|RD_C0, I1 },
502 {"mfc1", "t,S", 0x44000000, 0xffe007ff, LCD|WR_t|RD_S|FP_S, I1 },
503 {"mfc1", "t,G", 0x44000000, 0xffe007ff, LCD|WR_t|RD_S|FP_S, I1 },
504 {"mfc2", "t,G", 0x48000000, 0xffe007ff, LCD|WR_t|RD_C2, I1 },
505 {"mfc3", "t,G", 0x4c000000, 0xffe007ff, LCD|WR_t|RD_C3, I1 },
506 {"mfhi", "d", 0x00000010, 0xffff07ff, WR_d|RD_HI, I1 },
507 /* start-sanitize-r5900 */
508 {"mfhi1", "d", 0x70000010, 0xffff07ff, WR_d|RD_HI, T5 },
509 /* end-sanitize-r5900 */
510 {"mflo", "d", 0x00000012, 0xffff07ff, WR_d|RD_LO, I1 },
511 /* start-sanitize-r5900 */
512 {"mflo1", "d", 0x70000012, 0xffff07ff, WR_d|RD_LO, T5 },
513 {"mfsa", "d", 0x00000028, 0xffff07ff, WR_d, T5 },
514 /* end-sanitize-r5900 */
515 {"mov.d", "D,S", 0x46200006, 0xffff003f, WR_D|RD_S|FP_D, I1 },
516 {"mov.s", "D,S", 0x46000006, 0xffff003f, WR_D|RD_S|FP_S, I1 },
517 {"movf", "d,s,N", 0x00000001, 0xfc0307ff, WR_d|RD_s|RD_CC|FP_D|FP_S, I4 },
518 {"movf.d", "D,S,N", 0x46200011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_D, I4 },
519 {"movf.s", "D,S,N", 0x46000011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_S, I4 },
520 {"movn", "d,v,t", 0x0000000b, 0xfc0007ff, WR_d|RD_s|RD_t, I4 },
521 /* start-sanitize-r5900 */
522 {"movn", "d,v,t", 0x0000000b, 0xfc0007ff, WR_d|RD_s|RD_t, T5 },
523 /* end-sanitize-r5900 */
524 {"ffc", "d,v", 0x0000000b, 0xfc0007ff, WR_d|RD_s,L1 },
525 {"movn.d", "D,S,t", 0x46200013, 0xffe0003f, WR_D|RD_S|RD_t|FP_D, I4 },
526 {"movn.s", "D,S,t", 0x46000013, 0xffe0003f, WR_D|RD_S|RD_t|FP_S, I4 },
527 {"movt", "d,s,N", 0x00010001, 0xfc0307ff, WR_d|RD_s|RD_CC, I4 },
528 {"movt.d", "D,S,N", 0x46210011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_D, I4 },
529 {"movt.s", "D,S,N", 0x46010011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_S, I4 },
530 {"movz", "d,v,t", 0x0000000a, 0xfc0007ff, WR_d|RD_s|RD_t, I4 },
531 /* start-sanitize-r5900 */
532 {"movz", "d,v,t", 0x0000000a, 0xfc0007ff, WR_d|RD_s|RD_t, T5 },
533 /* end-sanitize-r5900 */
534 {"ffs", "d,v", 0x0000000a, 0xfc0007ff, WR_d|RD_s,L1 },
535 {"movz.d", "D,S,t", 0x46200012, 0xffe0003f, WR_D|RD_S|RD_t|FP_D, I4 },
536 {"movz.s", "D,S,t", 0x46000012, 0xffe0003f, WR_D|RD_S|RD_t|FP_S, I4 },
537 /* move is at the top of the table. */
538 {"msub.d", "D,R,S,T", 0x4c000029, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D, I4 },
539 {"msub.s", "D,R,S,T", 0x4c000028, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_S, I4 },
540 /* start-sanitize-r5900 */
541 {"msub.s", "D,R,S,T", 0x4c000028, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_S, T5 },
542 /* end-sanitize-r5900 */
543 {"msub", "s,t", 0x0000001e, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO,L1 },
544 {"msubu", "s,t", 0x0000001f, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO,L1 },
545 {"mtc0", "t,G", 0x40800000, 0xffe007ff, COD|RD_t|WR_C0|WR_CC, I1 },
546 {"mtc1", "t,S", 0x44800000, 0xffe007ff, COD|RD_t|WR_S|FP_S, I1 },
547 {"mtc1", "t,G", 0x44800000, 0xffe007ff, COD|RD_t|WR_S|FP_S, I1 },
548 {"mtc2", "t,G", 0x48800000, 0xffe007ff, COD|RD_t|WR_C2|WR_CC, I1 },
549 {"mtc3", "t,G", 0x4c800000, 0xffe007ff, COD|RD_t|WR_C3|WR_CC, I1 },
550 {"mthi", "s", 0x00000011, 0xfc1fffff, RD_s|WR_HI, I1 },
551 /* start-sanitize-r5900 */
552 {"mthi1", "s", 0x70000011, 0xfc1fffff, RD_s|WR_HI, T5 },
553 /* end-sanitize-r5900 */
554 {"mtlo", "s", 0x00000013, 0xfc1fffff, RD_s|WR_LO, I1 },
555 /* start-sanitize-r5900 */
556 {"mtlo1", "s", 0x70000013, 0xfc1fffff, RD_s|WR_LO, T5 },
557 {"mtsa", "s", 0x00000029, 0xfc1fffff, RD_s, T5 },
558 {"mtsab", "s,j", 0x04180000, 0xfc1f0000, RD_s, T5 },
559 {"mtsah", "s,j", 0x04190000, 0xfc1f0000, RD_s, T5 },
560 /* end-sanitize-r5900 */
561 {"mul.d", "D,V,T", 0x46200002, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, I1 },
562 {"mul.s", "D,V,T", 0x46000002, 0xffe0003f, WR_D|RD_S|RD_T|FP_S, I1 },
563 {"mul", "d,v,t", 0x70000002, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HI|WR_LO, P3 },
564 {"mul", "d,v,t", 0, (int) M_MUL, INSN_MACRO },
565 {"mul", "d,v,I", 0, (int) M_MUL_I, INSN_MACRO },
566 {"mulo", "d,v,t", 0, (int) M_MULO, INSN_MACRO },
567 {"mulo", "d,v,I", 0, (int) M_MULO_I, INSN_MACRO },
568 {"mulou", "d,v,t", 0, (int) M_MULOU, INSN_MACRO },
569 {"mulou", "d,v,I", 0, (int) M_MULOU_I, INSN_MACRO },
570 {"mult", "s,t", 0x00000018, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO, I1},
571 {"mult", "d,s,t", 0x00000018, 0xfc0007ff, RD_s|RD_t|WR_HI|WR_LO|WR_d, G1},
572 /* start-sanitize-r5900 */
573 {"mult1", "d,s,t", 0x70000018, 0xfc0007ff, RD_s|RD_t|WR_HI|WR_LO|WR_d, T5},
574 /* end-sanitize-r5900 */
575 {"multu", "s,t", 0x00000019, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO, I1},
576 {"multu", "d,s,t", 0x00000019, 0xfc0007ff, RD_s|RD_t|WR_HI|WR_LO|WR_d, G1},
577 /* start-sanitize-r5900 */
578 {"multu1", "d,s,t", 0x70000019, 0xfc0007ff, RD_s|RD_t|WR_HI|WR_LO|WR_d, T5},
579 /* end-sanitize-r5900 */
580 {"neg", "d,w", 0x00000022, 0xffe007ff, WR_d|RD_t, I1 }, /* sub 0 */
581 {"negu", "d,w", 0x00000023, 0xffe007ff, WR_d|RD_t, I1 }, /* subu 0 */
582 {"neg.d", "D,V", 0x46200007, 0xffff003f, WR_D|RD_S|FP_D, I1 },
583 {"neg.s", "D,V", 0x46000007, 0xffff003f, WR_D|RD_S|FP_S, I1 },
584 {"nmadd.d", "D,R,S,T", 0x4c000031, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D, I4 },
585 {"nmadd.s", "D,R,S,T", 0x4c000030, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_S, I4 },
586 {"nmsub.d", "D,R,S,T", 0x4c000039, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D, I4 },
587 {"nmsub.s", "D,R,S,T", 0x4c000038, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_S, I4 },
588 /* nop is at the start of the table. */
589 {"nor", "d,v,t", 0x00000027, 0xfc0007ff, WR_d|RD_s|RD_t, I1 },
590 {"nor", "t,r,I", 0, (int) M_NOR_I, INSN_MACRO },
591 {"not", "d,v", 0x00000027, 0xfc0007ff, WR_d|RD_s|RD_t, I1 },/*nor d,s,0*/
592 {"or", "d,v,t", 0x00000025, 0xfc0007ff, WR_d|RD_s|RD_t, I1 },
593 {"or", "t,r,I", 0, (int) M_OR_I, INSN_MACRO },
594 {"ori", "t,r,i", 0x34000000, 0xfc000000, WR_t|RD_s, I1 },
595
596 /* start-sanitize-r5900 */
597 {"pabsh", "d,t", 0x70000168, 0xffe007ff, WR_d|RD_t, T5 },
598 {"pabsw", "d,t", 0x70000068, 0xffe007ff, WR_d|RD_t, T5 },
599 {"paddb", "d,v,t", 0x70000208, 0xfc0007ff, WR_d|RD_s|RD_t, T5 },
600 {"paddh", "d,v,t", 0x70000108, 0xfc0007ff, WR_d|RD_s|RD_t, T5 },
601 {"paddw", "d,v,t", 0x70000008, 0xfc0007ff, WR_d|RD_s|RD_t, T5 },
602 {"paddsb", "d,v,t", 0x70000608, 0xfc0007ff, WR_d|RD_s|RD_t, T5 },
603 {"paddsh", "d,v,t", 0x70000508, 0xfc0007ff, WR_d|RD_s|RD_t, T5 },
604 {"paddsw", "d,v,t", 0x70000408, 0xfc0007ff, WR_d|RD_s|RD_t, T5 },
605 {"paddub", "d,v,t", 0x70000628, 0xfc0007ff, WR_d|RD_s|RD_t, T5 },
606 {"padduh", "d,v,t", 0x70000528, 0xfc0007ff, WR_d|RD_s|RD_t, T5 },
607 {"padduw", "d,v,t", 0x70000428, 0xfc0007ff, WR_d|RD_s|RD_t, T5 },
608 {"padsbh", "d,v,t", 0x70000128, 0xfc0007ff, WR_d|RD_s|RD_t, T5 },
609 {"pand", "d,v,t", 0x70000489, 0xfc0007ff, WR_d|RD_s|RD_t, T5 },
610 {"pceqb", "d,v,t", 0x700002a8, 0xfc0007ff, WR_d|RD_s|RD_t, T5 },
611 {"pceqh", "d,v,t", 0x700001a8, 0xfc0007ff, WR_d|RD_s|RD_t, T5 },
612 {"pceqw", "d,v,t", 0x700000a8, 0xfc0007ff, WR_d|RD_s|RD_t, T5 },
613
614 {"pcgtb", "d,v,t", 0x70000288, 0xfc0007ff, WR_d|RD_s|RD_t, T5 },
615 {"pcgth", "d,v,t", 0x70000188, 0xfc0007ff, WR_d|RD_s|RD_t, T5 },
616 {"pcgtw", "d,v,t", 0x70000088, 0xfc0007ff, WR_d|RD_s|RD_t, T5 },
617
618 {"pcpyh", "d,t", 0x700006e9, 0xffe007ff, WR_d|RD_t, T5 },
619
620 {"pcpyld", "d,v,t", 0x70000389, 0xfc0007ff, WR_d|RD_s|RD_t, T5 },
621 {"pcpyud", "d,v,t", 0x700003a9, 0xfc0007ff, WR_d|RD_s|RD_t, T5 },
622
623 {"pdivbw", "s,t", 0x70000749, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO, T5 },
624 {"pdivuw", "s,t", 0x70000369, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO, T5 },
625 {"pdivw", "s,t", 0x70000349, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO, T5 },
626
627 {"pexch", "d,t", 0x700006a9, 0xffe007ff, WR_d|RD_t, T5 },
628 {"pexcw", "d,t", 0x700007a9, 0xffe007ff, WR_d|RD_t, T5 },
629 {"pexeh", "d,t", 0x70000689, 0xffe007ff, WR_d|RD_t, T5 },
630 {"pexoh", "d,t", 0x70000689, 0xffe007ff, WR_d|RD_t, T5 },
631 {"pexew", "d,t", 0x70000789, 0xffe007ff, WR_d|RD_t, T5 },
632 {"pexow", "d,t", 0x70000789, 0xffe007ff, WR_d|RD_t, T5 },
633
634 {"pext5", "d,t", 0x70000788, 0xffe007ff, WR_d|RD_t, T5 },
635
636 {"pextlb", "d,v,t", 0x70000688, 0xfc0007ff, WR_d|RD_s|RD_t, T5 },
637 {"pextlh", "d,v,t", 0x70000588, 0xfc0007ff, WR_d|RD_s|RD_t, T5 },
638 {"pextlw", "d,v,t", 0x70000488, 0xfc0007ff, WR_d|RD_s|RD_t, T5 },
639 {"pextub", "d,v,t", 0x700006a8, 0xfc0007ff, WR_d|RD_s|RD_t, T5 },
640 {"pextuh", "d,v,t", 0x700005a8, 0xfc0007ff, WR_d|RD_s|RD_t, T5 },
641 {"pextuw", "d,v,t", 0x700004a8, 0xfc0007ff, WR_d|RD_s|RD_t, T5 },
642
643 {"phmaddh", "d,v,t", 0x70000449, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HI|WR_LO, T5 },
644 {"phmsubh", "d,v,t", 0x70000549, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HI|WR_LO, T5 },
645
646 {"pinth", "d,v,t", 0x70000289, 0xfc0007ff, WR_d|RD_s|RD_t, T5 },
647 {"pinteh", "d,v,t", 0x700002a9, 0xfc0007ff, WR_d|RD_s|RD_t, T5 },
648 {"pintoh", "d,v,t", 0x700002a9, 0xfc0007ff, WR_d|RD_s|RD_t, T5 },
649
650 {"plzcw", "d,v", 0x70000004, 0xfc1f07ff, WR_d|RD_s, T5 },
651
652 {"pmaddh", "d,v,t", 0x70000409, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HI|WR_LO, T5 },
653 {"pmadduw", "d,v,t", 0x70000029, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HI|WR_LO, T5 },
654 {"pmaddw", "d,v,t", 0x70000009, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HI|WR_LO, T5 },
655
656 {"pmaxh", "d,v,t", 0x700001c8, 0xfc0007ff, WR_d|RD_s|RD_t, T5 },
657 {"pmaxw", "d,v,t", 0x700000c8, 0xfc0007ff, WR_d|RD_s|RD_t, T5 },
658
659 {"pmfhi", "d", 0x70000209, 0xffff07ff, WR_d|RD_HI, T5 },
660 {"pmflo", "d", 0x70000249, 0xffff07ff, WR_d|RD_LO, T5 },
661
662 {"pmfhl.lw", "d", 0x70000030, 0xffff07ff, WR_d|RD_LO|RD_HI, T5 },
663 {"pmfhl.uw", "d", 0x70000070, 0xffff07ff, WR_d|RD_LO|RD_HI, T5 },
664 {"pmfhl.slw","d", 0x700000b0, 0xffff07ff, WR_d|RD_LO|RD_HI, T5 },
665 {"pmfhl.lh", "d", 0x700000f0, 0xffff07ff, WR_d|RD_LO|RD_HI, T5 },
666 {"pmfhl.sh", "d", 0x70000130, 0xffff07ff, WR_d|RD_LO|RD_HI, T5 },
667
668 {"pminh", "d,v,t", 0x700001e8, 0xfc0007ff, WR_d|RD_s|RD_t, T5 },
669 {"pminw", "d,v,t", 0x700000e8, 0xfc0007ff, WR_d|RD_s|RD_t, T5 },
670
671 {"pmsubh", "d,v,t", 0x70000509, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HI|WR_LO, T5 },
672 {"pmsubw", "d,v,t", 0x70000109, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HI|WR_LO, T5 },
673
674 {"pmthi", "v", 0x70000229, 0xfc1fffff, WR_HI|RD_s, T5 },
675 {"pmtlo", "v", 0x70000269, 0xfc1fffff, WR_LO|RD_s, T5 },
676
677 {"pmthl.lw", "v", 0x70000031, 0xfc1fffff, WR_HI|WR_LO|RD_s, T5 },
678
679 {"pmulth", "d,v,t", 0x70000709, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HI|WR_LO, T5 },
680 {"pmultuw", "d,v,t", 0x70000329, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HI|WR_LO, T5 },
681 {"pmultw", "d,v,t", 0x70000309, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HI|WR_LO, T5 },
682
683 {"pnor", "d,v,t", 0x700004e9, 0xfc0007ff, WR_d|RD_s|RD_t, T5 },
684 {"por", "d,v,t", 0x700004a9, 0xfc0007ff, WR_d|RD_s|RD_t, T5 },
685
686 {"ppac5", "d,t", 0x700007c8, 0xffe007ff, WR_d|RD_t, T5 },
687
688 {"ppacb", "d,v,t", 0x700006c8, 0xfc0007ff, WR_d|RD_s|RD_t, T5 },
689 {"ppach", "d,v,t", 0x700005c8, 0xfc0007ff, WR_d|RD_s|RD_t, T5 },
690 {"ppacw", "d,v,t", 0x700004c8, 0xfc0007ff, WR_d|RD_s|RD_t, T5 },
691
692 {"prevh", "d,t", 0x700006c9, 0xffe007ff, WR_d|RD_t, T5 },
693 {"prot3w", "d,t", 0x700007c9, 0xffe007ff, WR_d|RD_t, T5 },
694
695 {"psllh", "d,t,<", 0x70000034, 0xffe0003f, WR_d|RD_t, T5 },
696 {"psllvw", "d,t,s", 0x70000089, 0xfc0007ff, WR_d|RD_t|RD_s, T5 },
697 {"psllw", "d,t,<", 0x7000003c, 0xffe0003f, WR_d|RD_t, T5 },
698
699 {"psrah", "d,t,<", 0x70000037, 0xffe0003f, WR_d|RD_t, T5 },
700 {"psravw", "d,t,s", 0x700000e9, 0xfc0007ff, WR_d|RD_t|RD_s, T5 },
701 {"psraw", "d,t,<", 0x7000003f, 0xffe0003f, WR_d|RD_t, T5 },
702
703 {"psrlh", "d,t,<", 0x70000036, 0xffe0003f, WR_d|RD_t, T5 },
704 {"psrlvw", "d,t,s", 0x700000c9, 0xfc0007ff, WR_d|RD_t|RD_s, T5 },
705 {"psrlw", "d,t,<", 0x7000003e, 0xffe0003f, WR_d|RD_t, T5 },
706
707 {"psubb", "d,v,t", 0x70000248, 0xfc0007ff, WR_d|RD_s|RD_t, T5 },
708 {"psubh", "d,v,t", 0x70000148, 0xfc0007ff, WR_d|RD_s|RD_t, T5 },
709 {"psubsb", "d,v,t", 0x70000648, 0xfc0007ff, WR_d|RD_s|RD_t, T5 },
710 {"psubsh", "d,v,t", 0x70000548, 0xfc0007ff, WR_d|RD_s|RD_t, T5 },
711 {"psubsw", "d,v,t", 0x70000448, 0xfc0007ff, WR_d|RD_s|RD_t, T5 },
712 {"psubub", "d,v,t", 0x70000668, 0xfc0007ff, WR_d|RD_s|RD_t, T5 },
713 {"psubuh", "d,v,t", 0x70000568, 0xfc0007ff, WR_d|RD_s|RD_t, T5 },
714 {"psubuw", "d,v,t", 0x70000468, 0xfc0007ff, WR_d|RD_s|RD_t, T5 },
715 {"psubw", "d,v,t", 0x70000048, 0xfc0007ff, WR_d|RD_s|RD_t, T5 },
716
717 {"pxor", "d,v,t", 0x700004c9, 0xfc0007ff, WR_d|RD_s|RD_t, T5 },
718 /* end-sanitize-r5900 */
719
720 {"pref", "k,o(b)", 0xcc000000, 0xfc000000, RD_b, I4 },
721 {"prefx", "h,t(b)", 0x4c00000f, 0xfc0007ff, RD_b|RD_t, I4 },
722
723 /* start-sanitize-r5900 */
724 {"qfsrv", "d,v,t", 0x700006e8, 0xfc0007ff, WR_d|RD_s|RD_t, T5 },
725 /* end-sanitize-r5900 */
726
727 {"recip.d", "D,S", 0x46200015, 0xffff003f, WR_D|RD_S|FP_D, I4 },
728 {"recip.s", "D,S", 0x46000015, 0xffff003f, WR_D|RD_S|FP_S, I4 },
729 {"rem", "z,s,t", 0x0000001a, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO, I1 },
730 {"rem", "d,v,t", 0, (int) M_REM_3, INSN_MACRO },
731 {"rem", "d,v,I", 0, (int) M_REM_3I, INSN_MACRO },
732 {"remu", "z,s,t", 0x0000001b, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO, I1 },
733 {"remu", "d,v,t", 0, (int) M_REMU_3, INSN_MACRO },
734 {"remu", "d,v,I", 0, (int) M_REMU_3I, INSN_MACRO },
735 {"rfe", "", 0x42000010, 0xffffffff, 0, I1|T3 },
736 {"rol", "d,v,t", 0, (int) M_ROL, INSN_MACRO },
737 {"rol", "d,v,I", 0, (int) M_ROL_I, INSN_MACRO },
738 {"ror", "d,v,t", 0, (int) M_ROR, INSN_MACRO },
739 {"ror", "d,v,I", 0, (int) M_ROR_I, INSN_MACRO },
740 {"round.l.d", "D,S", 0x46200008, 0xffff003f, WR_D|RD_S|FP_D, I3 },
741 {"round.l.s", "D,S", 0x46000008, 0xffff003f, WR_D|RD_S|FP_S, I3 },
742 {"round.w.d", "D,S", 0x4620000c, 0xffff003f, WR_D|RD_S|FP_D, I2 },
743 {"round.w.s", "D,S", 0x4600000c, 0xffff003f, WR_D|RD_S|FP_S, I2 },
744 {"rsqrt.d", "D,S", 0x46200016, 0xffff003f, WR_D|RD_S|FP_D, I4 },
745 {"rsqrt.s", "D,S", 0x46000016, 0xffff003f, WR_D|RD_S|FP_S, I4 },
746 /* start-sanitize-r5900 */
747 {"rsqrt.s", "D,S", 0x46000016, 0xffff003f, WR_D|RD_S|FP_S, T5 },
748 /* end-sanitize-r5900 */
749 {"sb", "t,o(b)", 0xa0000000, 0xfc000000, SM|RD_t|RD_b, I1 },
750 {"sb", "t,A(b)", 0, (int) M_SB_AB, INSN_MACRO },
751 {"sc", "t,o(b)", 0xe0000000, 0xfc000000, SM|RD_t|WR_t|RD_b, I2 },
752 {"sc", "t,A(b)", 2, (int) M_SC_AB, INSN_MACRO },
753 {"scd", "t,o(b)", 0xf0000000, 0xfc000000, SM|RD_t|WR_t|RD_b, I3 },
754 {"scd", "t,A(b)", 3, (int) M_SCD_AB, INSN_MACRO },
755 {"sd", "t,o(b)", 0xfc000000, 0xfc000000, SM|RD_t|RD_b, I3 },
756 {"sd", "t,o(b)", 0, (int) M_SD_OB, INSN_MACRO },
757 {"sd", "t,A(b)", 0, (int) M_SD_AB, INSN_MACRO },
758 {"sdbbp", "", 0x0000000e, 0xffffffff, TRAP, T3 },
759 {"sdbbp", "c", 0x0000000e, 0xfc00003f, TRAP, T3 },
760 {"sdc1", "T,o(b)", 0xf4000000, 0xfc000000, SM|RD_T|RD_b|FP_D, I2 },
761 {"sdc1", "E,o(b)", 0xf4000000, 0xfc000000, SM|RD_T|RD_b|FP_D, I2 },
762 {"sdc1", "T,A(b)", 2, (int) M_SDC1_AB, INSN_MACRO },
763 {"sdc1", "E,A(b)", 2, (int) M_SDC1_AB, INSN_MACRO },
764 {"sdc2", "E,o(b)", 0xf8000000, 0xfc000000, SM|RD_C2|RD_b, I2 },
765 {"sdc2", "E,A(b)", 2, (int) M_SDC2_AB, INSN_MACRO },
766 {"sdc3", "E,o(b)", 0xfc000000, 0xfc000000, SM|RD_C3|RD_b, I2 },
767 {"sdc3", "E,A(b)", 2, (int) M_SDC3_AB, INSN_MACRO },
768 {"s.d", "T,o(b)", 0xf4000000, 0xfc000000, SM|RD_T|RD_b, I2 },
769 {"s.d", "T,o(b)", 0, (int) M_S_DOB, INSN_MACRO },
770 {"s.d", "T,A(b)", 0, (int) M_S_DAB, INSN_MACRO },
771 {"sdl", "t,o(b)", 0xb0000000, 0xfc000000, SM|RD_t|RD_b, I3 },
772 {"sdl", "t,A(b)", 3, (int) M_SDL_AB, INSN_MACRO },
773 {"sdr", "t,o(b)", 0xb4000000, 0xfc000000, SM|RD_t|RD_b, I3 },
774 {"sdr", "t,A(b)", 3, (int) M_SDR_AB, INSN_MACRO },
775 {"sdxc1", "S,t(b)", 0x4c000009, 0xfc0007ff, SM|RD_S|RD_t|RD_b, I4 },
776 {"selsl", "d,v,t", 0x00000005, 0xfc0007ff, WR_d|RD_s|RD_t,L1 },
777 {"selsr", "d,v,t", 0x00000001, 0xfc0007ff, WR_d|RD_s|RD_t,L1 },
778 {"seq", "d,v,t", 0, (int) M_SEQ, INSN_MACRO },
779 {"seq", "d,v,I", 0, (int) M_SEQ_I, INSN_MACRO },
780 {"sge", "d,v,t", 0, (int) M_SGE, INSN_MACRO },
781 {"sge", "d,v,I", 0, (int) M_SGE_I, INSN_MACRO },
782 {"sgeu", "d,v,t", 0, (int) M_SGEU, INSN_MACRO },
783 {"sgeu", "d,v,I", 0, (int) M_SGEU_I, INSN_MACRO },
784 {"sgt", "d,v,t", 0, (int) M_SGT, INSN_MACRO },
785 {"sgt", "d,v,I", 0, (int) M_SGT_I, INSN_MACRO },
786 {"sgtu", "d,v,t", 0, (int) M_SGTU, INSN_MACRO },
787 {"sgtu", "d,v,I", 0, (int) M_SGTU_I, INSN_MACRO },
788 {"sh", "t,o(b)", 0xa4000000, 0xfc000000, SM|RD_t|RD_b, I1 },
789 {"sh", "t,A(b)", 0, (int) M_SH_AB, INSN_MACRO },
790 {"sle", "d,v,t", 0, (int) M_SLE, INSN_MACRO },
791 {"sle", "d,v,I", 0, (int) M_SLE_I, INSN_MACRO },
792 {"sleu", "d,v,t", 0, (int) M_SLEU, INSN_MACRO },
793 {"sleu", "d,v,I", 0, (int) M_SLEU_I, INSN_MACRO },
794 {"sllv", "d,t,s", 0x00000004, 0xfc0007ff, WR_d|RD_t|RD_s, I1 },
795 {"sll", "d,w,s", 0x00000004, 0xfc0007ff, WR_d|RD_t|RD_s, I1 }, /* sllv */
796 {"sll", "d,w,<", 0x00000000, 0xffe0003f, WR_d|RD_t, I1 },
797 {"slt", "d,v,t", 0x0000002a, 0xfc0007ff, WR_d|RD_s|RD_t, I1 },
798 {"slt", "d,v,I", 0, (int) M_SLT_I, INSN_MACRO },
799 {"slti", "t,r,j", 0x28000000, 0xfc000000, WR_t|RD_s, I1 },
800 {"sltiu", "t,r,j", 0x2c000000, 0xfc000000, WR_t|RD_s, I1 },
801 {"sltu", "d,v,t", 0x0000002b, 0xfc0007ff, WR_d|RD_s|RD_t, I1 },
802 {"sltu", "d,v,I", 0, (int) M_SLTU_I, INSN_MACRO },
803 {"sne", "d,v,t", 0, (int) M_SNE, INSN_MACRO },
804 {"sne", "d,v,I", 0, (int) M_SNE_I, INSN_MACRO },
805 /* start-sanitize-r5900 */
806 {"sq", "t,o(b)", 0x7c000000, 0xfc000000, SM|RD_t|RD_b, T5 },
807 /* end-sanitize-r5900 */
808 {"sqrt.d", "D,S", 0x46200004, 0xffff003f, WR_D|RD_S|FP_D, I2 },
809 {"sqrt.s", "D,S", 0x46000004, 0xffff003f, WR_D|RD_S|FP_S, I2 },
810 {"srav", "d,t,s", 0x00000007, 0xfc0007ff, WR_d|RD_t|RD_s, I1 },
811 {"sra", "d,w,s", 0x00000007, 0xfc0007ff, WR_d|RD_t|RD_s, I1 }, /* srav */
812 {"sra", "d,w,<", 0x00000003, 0xffe0003f, WR_d|RD_t, I1 },
813 {"srlv", "d,t,s", 0x00000006, 0xfc0007ff, WR_d|RD_t|RD_s, I1 },
814 {"srl", "d,w,s", 0x00000006, 0xfc0007ff, WR_d|RD_t|RD_s, I1 }, /* srlv */
815 {"srl", "d,w,<", 0x00000002, 0xffe0003f, WR_d|RD_t, I1 },
816 {"standby", "", 0x42000021, 0xffffffff, 0, V1 },
817 {"sub", "d,v,t", 0x00000022, 0xfc0007ff, WR_d|RD_s|RD_t, I1 },
818 {"sub", "d,v,I", 0, (int) M_SUB_I, INSN_MACRO },
819 {"sub.d", "D,V,T", 0x46200001, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, I1 },
820 {"sub.s", "D,V,T", 0x46000001, 0xffe0003f, WR_D|RD_S|RD_T|FP_S, I1 },
821 {"subu", "d,v,t", 0x00000023, 0xfc0007ff, WR_d|RD_s|RD_t, I1 },
822 {"subu", "d,v,I", 0, (int) M_SUBU_I, INSN_MACRO },
823 {"suspend", "", 0x42000022, 0xffffffff, 0, V1 },
824 {"sw", "t,o(b)", 0xac000000, 0xfc000000, SM|RD_t|RD_b, I1 },
825 {"sw", "t,A(b)", 0, (int) M_SW_AB, INSN_MACRO },
826 {"swc0", "E,o(b)", 0xe0000000, 0xfc000000, SM|RD_C0|RD_b, I1 },
827 {"swc0", "E,A(b)", 0, (int) M_SWC0_AB, INSN_MACRO },
828 {"swc1", "T,o(b)", 0xe4000000, 0xfc000000, SM|RD_T|RD_b|FP_S, I1 },
829 {"swc1", "E,o(b)", 0xe4000000, 0xfc000000, SM|RD_T|RD_b|FP_S, I1 },
830 {"swc1", "T,A(b)", 0, (int) M_SWC1_AB, INSN_MACRO },
831 {"swc1", "E,A(b)", 0, (int) M_SWC1_AB, INSN_MACRO },
832 {"s.s", "T,o(b)", 0xe4000000, 0xfc000000, SM|RD_T|RD_b|FP_S, I1 }, /* swc1 */
833 {"s.s", "T,A(b)", 0, (int) M_SWC1_AB, INSN_MACRO },
834 {"swc2", "E,o(b)", 0xe8000000, 0xfc000000, SM|RD_C2|RD_b, I1 },
835 {"swc2", "E,A(b)", 0, (int) M_SWC2_AB, INSN_MACRO },
836 {"swc3", "E,o(b)", 0xec000000, 0xfc000000, SM|RD_C3|RD_b, I1 },
837 {"swc3", "E,A(b)", 0, (int) M_SWC3_AB, INSN_MACRO },
838 {"swl", "t,o(b)", 0xa8000000, 0xfc000000, SM|RD_t|RD_b, I1 },
839 {"swl", "t,A(b)", 0, (int) M_SWL_AB, INSN_MACRO },
840 {"scache", "t,o(b)", 0xa8000000, 0xfc000000, RD_t|RD_b, I2 }, /* same */
841 {"scache", "t,A(b)", 2, (int) M_SWL_AB, INSN_MACRO }, /* as swl */
842 {"swr", "t,o(b)", 0xb8000000, 0xfc000000, SM|RD_t|RD_b, I1 },
843 {"swr", "t,A(b)", 0, (int) M_SWR_AB, INSN_MACRO },
844 {"invalidate", "t,o(b)",0xb8000000, 0xfc000000, RD_t|RD_b, I2 }, /* same */
845 {"invalidate", "t,A(b)",2, (int) M_SWR_AB, INSN_MACRO }, /* as swr */
846 {"swxc1", "S,t(b)", 0x4c000008, 0xfc0007ff, SM|RD_S|RD_t|RD_b, I4 },
847 {"sync", "", 0x0000000f, 0xffffffff, 0, I2 },
848 {"syscall", "", 0x0000000c, 0xffffffff, TRAP, I1 },
849 {"syscall", "B", 0x0000000c, 0xfc00003f, TRAP, I1 },
850 {"teqi", "s,j", 0x040c0000, 0xfc1f0000, RD_s|TRAP, I2 },
851 {"teq", "s,t", 0x00000034, 0xfc00003f, RD_s|RD_t|TRAP, I2 },
852 {"teq", "s,j", 0x040c0000, 0xfc1f0000, RD_s|TRAP, I2 }, /* teqi */
853 {"teq", "s,I", 2, (int) M_TEQ_I, INSN_MACRO },
854 {"tgei", "s,j", 0x04080000, 0xfc1f0000, RD_s|TRAP, I2 },
855 {"tge", "s,t", 0x00000030, 0xfc00003f, RD_s|RD_t|TRAP, I2 },
856 {"tge", "s,j", 0x04080000, 0xfc1f0000, RD_s|TRAP, I2 }, /* tgei */
857 {"tge", "s,I", 2, (int) M_TGE_I, INSN_MACRO },
858 {"tgeiu", "s,j", 0x04090000, 0xfc1f0000, RD_s|TRAP, I2 },
859 {"tgeu", "s,t", 0x00000031, 0xfc00003f, RD_s|RD_t|TRAP, I2 },
860 {"tgeu", "s,j", 0x04090000, 0xfc1f0000, RD_s|TRAP, I2 }, /* tgeiu */
861 {"tgeu", "s,I", 2, (int) M_TGEU_I, INSN_MACRO },
862 {"tlbp", "", 0x42000008, 0xffffffff, INSN_TLB, I1 },
863 {"tlbr", "", 0x42000001, 0xffffffff, INSN_TLB, I1 },
864 {"tlbwi", "", 0x42000002, 0xffffffff, INSN_TLB, I1 },
865 {"tlbwr", "", 0x42000006, 0xffffffff, INSN_TLB, I1 },
866 {"tlti", "s,j", 0x040a0000, 0xfc1f0000, RD_s|TRAP, I2 },
867 {"tlt", "s,t", 0x00000032, 0xfc00003f, RD_s|RD_t|TRAP, I2 },
868 {"tlt", "s,j", 0x040a0000, 0xfc1f0000, RD_s|TRAP, I2 }, /* tlti */
869 {"tlt", "s,I", 2, (int) M_TLT_I, INSN_MACRO },
870 {"tltiu", "s,j", 0x040b0000, 0xfc1f0000, RD_s|TRAP, I2 },
871 {"tltu", "s,t", 0x00000033, 0xfc00003f, RD_s|RD_t|TRAP, I2 },
872 {"tltu", "s,j", 0x040b0000, 0xfc1f0000, RD_s|TRAP, I2 }, /* tltiu */
873 {"tltu", "s,I", 2, (int) M_TLTU_I, INSN_MACRO },
874 {"tnei", "s,j", 0x040e0000, 0xfc1f0000, RD_s|TRAP, I2 },
875 {"tne", "s,t", 0x00000036, 0xfc00003f, RD_s|RD_t|TRAP, I2 },
876 {"tne", "s,j", 0x040e0000, 0xfc1f0000, RD_s|TRAP, I2 }, /* tnei */
877 {"tne", "s,I", 2, (int) M_TNE_I, INSN_MACRO },
878 {"trunc.l.d", "D,S", 0x46200009, 0xffff003f, WR_D|RD_S|FP_D, I3 },
879 {"trunc.l.s", "D,S", 0x46000009, 0xffff003f, WR_D|RD_S|FP_S, I3 },
880 {"trunc.w.d", "D,S", 0x4620000d, 0xffff003f, WR_D|RD_S|FP_D, I2 },
881 {"trunc.w.d", "D,S,x", 0x4620000d, 0xffff003f, WR_D|RD_S|FP_D, I2 },
882 {"trunc.w.d", "D,S,t", 0, (int) M_TRUNCWD, INSN_MACRO },
883 {"trunc.w.s", "D,S", 0x4600000d, 0xffff003f, WR_D|RD_S|FP_S, I2 },
884 {"trunc.w.s", "D,S,x", 0x4600000d, 0xffff003f, WR_D|RD_S|FP_S, I2 },
885 {"trunc.w.s", "D,S,t", 0, (int) M_TRUNCWS, INSN_MACRO },
886 {"uld", "t,o(b)", 3, (int) M_ULD, INSN_MACRO },
887 {"uld", "t,A(b)", 3, (int) M_ULD_A, INSN_MACRO },
888 {"ulh", "t,o(b)", 0, (int) M_ULH, INSN_MACRO },
889 {"ulh", "t,A(b)", 0, (int) M_ULH_A, INSN_MACRO },
890 {"ulhu", "t,o(b)", 0, (int) M_ULHU, INSN_MACRO },
891 {"ulhu", "t,A(b)", 0, (int) M_ULHU_A, INSN_MACRO },
892 {"ulw", "t,o(b)", 0, (int) M_ULW, INSN_MACRO },
893 {"ulw", "t,A(b)", 0, (int) M_ULW_A, INSN_MACRO },
894 {"usd", "t,o(b)", 3, (int) M_USD, INSN_MACRO },
895 {"usd", "t,A(b)", 3, (int) M_USD_A, INSN_MACRO },
896 {"ush", "t,o(b)", 0, (int) M_USH, INSN_MACRO },
897 {"ush", "t,A(b)", 0, (int) M_USH_A, INSN_MACRO },
898 {"usw", "t,o(b)", 0, (int) M_USW, INSN_MACRO },
899 {"usw", "t,A(b)", 0, (int) M_USW_A, INSN_MACRO },
900 {"xor", "d,v,t", 0x00000026, 0xfc0007ff, WR_d|RD_s|RD_t, I1 },
901 {"xor", "t,r,I", 0, (int) M_XOR_I, INSN_MACRO },
902 {"xori", "t,r,i", 0x38000000, 0xfc000000, WR_t|RD_s, I1 },
903 {"wait", "", 0x42000020, 0xffffffff, TRAP, I3 },
904 {"waiti", "", 0x42000020, 0xffffffff, TRAP, L1 },
905 {"wb", "o(b)", 0xbc040000, 0xfc1f0000, SM|RD_b, L1 },
906 /* No hazard protection on coprocessor instructions--they shouldn't
907 change the state of the processor and if they do it's up to the
908 user to put in nops as necessary. These are at the end so that the
909 disasembler recognizes more specific versions first. */
910 {"c0", "C", 0x42000000, 0xfe000000, 0, I1 },
911 {"c1", "C", 0x46000000, 0xfe000000, 0, I1 },
912 {"c2", "C", 0x4a000000, 0xfe000000, 0, I1 },
913 {"c3", "C", 0x4e000000, 0xfe000000, 0, I1 },
914 {"cop0", "C", 0, (int) M_COP0, INSN_MACRO },
915 {"cop1", "C", 0, (int) M_COP1, INSN_MACRO },
916 {"cop2", "C", 0, (int) M_COP2, INSN_MACRO },
917 {"cop3", "C", 0, (int) M_COP3, INSN_MACRO },
918 };
919
920 #define MIPS_NUM_OPCODES \
921 ((sizeof mips_builtin_opcodes) / (sizeof (mips_builtin_opcodes[0])))
922 const int bfd_mips_num_builtin_opcodes = MIPS_NUM_OPCODES;
923
924 /* const removed from the following to allow for dynamic extensions to the
925 * built-in instruction set. */
926 struct mips_opcode *mips_opcodes =
927 (struct mips_opcode *) mips_builtin_opcodes;
928 int bfd_mips_num_opcodes = MIPS_NUM_OPCODES;
929 #undef MIPS_NUM_OPCODES
930
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