opcodes/mips-opc.c

   1 /* mips.h.  Mips opcode list for GDB, the GNU debugger.
   2    Copyright 1993 Free Software Foundation, Inc.
   3    Contributed by Ralph Campbell and OSF
   4    Commented and modified by Ian Lance Taylor, Cygnus Support
   5
   6 This file is part of GDB, GAS, and the GNU binutils.
   7
   8 GDB, GAS, and the GNU binutils are free software; you can redistribute
   9 them and/or modify them under the terms of the GNU General Public
  10 License as published by the Free Software Foundation; either version
  11 1, or (at your option) any later version.
  12
  13 GDB, GAS, and the GNU binutils are distributed in the hope that they
  14 will be useful, but WITHOUT ANY WARRANTY; without even the implied
  15 warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See
  16 the GNU General Public License for more details.
  17
  18 You should have received a copy of the GNU General Public License
  19 along with this file; see the file COPYING.  If not, write to the Free
  20 Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.  */
  21
  22 #include <stdio.h>
  23 #include "ansidecl.h"
  24 #include "opcode/mips.h"
  25
  26 /* Short hand so the lines aren't too long.  */
  27
  28 #define LDD     INSN_LOAD_MEMORY_DELAY
  29 #define LCD     INSN_LOAD_COPROC_DELAY
  30 #define UBD     INSN_UNCOND_BRANCH_DELAY
  31 #define CBD     INSN_COND_BRANCH_DELAY
  32 #define COD     INSN_COPROC_MOVE_DELAY
  33 #define CLD     INSN_COPROC_MEMORY_DELAY
  34 #define CBL     INSN_COND_BRANCH_LIKELY
  35 #define TRAP    INSN_TRAP
  36 #define SM      INSN_STORE_MEMORY
  37
  38 #define WR_d    INSN_WRITE_GPR_D
  39 #define WR_t    INSN_WRITE_GPR_T
  40 #define WR_31   INSN_WRITE_GPR_31
  41 #define WR_D    INSN_WRITE_FPR_D
  42 #define WR_T    INSN_WRITE_FPR_T
  43 #define WR_S    INSN_WRITE_FPR_S
  44 #define RD_s    INSN_READ_GPR_S
  45 #define RD_b    INSN_READ_GPR_S
  46 #define RD_t    INSN_READ_GPR_T
  47 #define RD_S    INSN_READ_FPR_S
  48 #define RD_T    INSN_READ_FPR_T
  49 #define WR_CC   INSN_WRITE_COND_CODE
  50 #define RD_CC   INSN_READ_COND_CODE
  51 #define RD_C0   INSN_COP
  52 #define RD_C1   INSN_COP
  53 #define RD_C2   INSN_COP
  54 #define RD_C3   INSN_COP
  55 #define WR_C0   INSN_COP
  56 #define WR_C1   INSN_COP
  57 #define WR_C2   INSN_COP
  58 #define WR_C3   INSN_COP
  59 #define WR_HI   INSN_WRITE_HI
  60 #define WR_LO   INSN_WRITE_LO
  61 #define RD_HI   INSN_READ_HI
  62 #define RD_LO   INSN_READ_LO
  63
  64 #define I2      INSN_ISA2
  65 #define I3      INSN_ISA3
  66 #define P3      INSN_4650
  67
  68 /* The order of overloaded instructions matters.  Label arguments and
  69    register arguments look the same. Instructions that can have either
  70    for arguments must apear in the correct order in this table for the
  71    assembler to pick the right one. In other words, entries with
  72    immediate operands must apear after the same instruction with
  73    registers.
  74
  75    Many instructions are short hand for other instructions (i.e., The
  76    jal <register> instruction is short for jalr <register>).  */
  77
  78 const struct mips_opcode mips_opcodes[] = {
  79 /* These instructions appear first so that the disassembler will find
  80    them first.  The assemblers uses a hash table based on the
  81    instruction name anyhow.  */
  82 {"nop",     "",         0x00000000, 0xffffffff, 0               },
  83 {"li",      "t,j",      0x24000000, 0xffe00000, WR_t            }, /* addiu */
  84 {"li",      "t,i",      0x34000000, 0xffe00000, WR_t            }, /* ori */
  85 {"li",      "t,I",      0,    (int) M_LI,       INSN_MACRO      },
  86 /* dli is used on Irix 6 for a 64 bit load--our li can do that.  */
  87 {"dli",     "t,j",      0x24000000, 0xffe00000, WR_t            }, /* addiu */
  88 {"dli",     "t,i",      0x34000000, 0xffe00000, WR_t            }, /* ori */
  89 {"dli",     "t,I",      0,    (int) M_LI,       INSN_MACRO      },
  90 {"move",    "d,s",      0x00000025, 0xfc1f07ff, WR_d|RD_s       },/* or */
  91 {"b",       "p",        0x10000000, 0xffff0000, UBD             },/* beq 0,0 */
  92 {"b",       "p",        0x04010000, 0xffff0000, UBD             },/* bgez 0 */
  93 {"bal",     "p",        0x04110000, 0xffff0000, UBD|WR_31       },/* bgezal 0*/
  94
  95 {"abs",     "d,v",      0,    (int) M_ABS,      INSN_MACRO      },
  96 {"abs.s",   "D,V",      0x46000005, 0xffff003f, WR_D|RD_S       },
  97 {"abs.d",   "D,V",      0x46200005, 0xffff003f, WR_D|RD_S       },
  98 {"add",     "d,v,t",    0x00000020, 0xfc0007ff, WR_d|RD_s|RD_t  },
  99 {"add",     "t,r,I",    0,    (int) M_ADD_I,    INSN_MACRO      },
 100 {"add.s",   "D,V,T",    0x46000000, 0xffe0003f, WR_D|RD_S|RD_T  },
 101 {"add.d",   "D,V,T",    0x46200000, 0xffe0003f, WR_D|RD_S|RD_T  },
 102 {"addi",    "t,r,j",    0x20000000, 0xfc000000, WR_t|RD_s       },
 103 {"addiu",   "t,r,j",    0x24000000, 0xfc000000, WR_t|RD_s       },
 104 {"addu",    "d,v,t",    0x00000021, 0xfc0007ff, WR_d|RD_s|RD_t  },
 105 {"addu",    "t,r,I",    0,    (int) M_ADDU_I,   INSN_MACRO      },
 106 {"and",     "d,v,t",    0x00000024, 0xfc0007ff, WR_d|RD_s|RD_t  },
 107 {"and",     "t,r,I",    0,    (int) M_AND_I,    INSN_MACRO      },
 108 {"andi",    "t,r,i",    0x30000000, 0xfc000000, WR_t|RD_s       },
 109 /* b is at the top of the table.  */
 110 /* bal is at the top of the table.  */
 111 {"bc0f",    "p",        0x41000000, 0xffff0000, CBD|RD_CC       },
 112 {"bc0fl",   "p",        0x41020000, 0xffff0000, CBL|RD_CC|I2    },
 113 {"bc1f",    "p",        0x45000000, 0xffff0000, CBD|RD_CC       },
 114 {"bc1fl",   "p",        0x45020000, 0xffff0000, CBL|RD_CC|I2    },
 115 {"bc2f",    "p",        0x49000000, 0xffff0000, CBD|RD_CC       },
 116 {"bc2fl",   "p",        0x49020000, 0xffff0000, CBL|RD_CC|I2    },
 117 {"bc3f",    "p",        0x4d000000, 0xffff0000, CBD|RD_CC       },
 118 {"bc3fl",   "p",        0x4d020000, 0xffff0000, CBL|RD_CC|I2    },
 119 {"bc0t",    "p",        0x41010000, 0xffff0000, CBD|RD_CC       },
 120 {"bc0tl",   "p",        0x41030000, 0xffff0000, CBL|RD_CC|I2    },
 121 {"bc1t",    "p",        0x45010000, 0xffff0000, CBD|RD_CC       },
 122 {"bc1tl",   "p",        0x45030000, 0xffff0000, CBL|RD_CC|I2    },
 123 {"bc2t",    "p",        0x49010000, 0xffff0000, CBD|RD_CC       },
 124 {"bc2tl",   "p",        0x49030000, 0xffff0000, CBL|RD_CC|I2    },
 125 {"bc3t",    "p",        0x4d010000, 0xffff0000, CBD|RD_CC       },
 126 {"bc3tl",   "p",        0x4d030000, 0xffff0000, CBL|RD_CC|I2    },
 127 {"beqz",    "s,p",      0x10000000, 0xfc1f0000, CBD|RD_s        },
 128 {"beqzl",   "s,p",      0x50000000, 0xfc1f0000, CBL|RD_s|I2     },
 129 {"beq",     "s,t,p",    0x10000000, 0xfc000000, CBD|RD_s|RD_t   },
 130 {"beq",     "s,I,p",    0,    (int) M_BEQ_I,    INSN_MACRO      },
 131 {"beql",    "s,t,p",    0x50000000, 0xfc000000, CBL|RD_s|RD_t|I2},
 132 {"beql",    "s,I,p",    2,    (int) M_BEQL_I,   INSN_MACRO      },
 133 {"bge",     "s,t,p",    0,    (int) M_BGE,      INSN_MACRO      },
 134 {"bge",     "s,I,p",    0,    (int) M_BGE_I,    INSN_MACRO      },
 135 {"bgel",    "s,t,p",    2,    (int) M_BGEL,     INSN_MACRO      },
 136 {"bgel",    "s,I,p",    2,    (int) M_BGEL_I,   INSN_MACRO      },
 137 {"bgeu",    "s,t,p",    0,    (int) M_BGEU,     INSN_MACRO      },
 138 {"bgeu",    "s,I,p",    0,    (int) M_BGEU_I,   INSN_MACRO      },
 139 {"bgeul",   "s,t,p",    2,    (int) M_BGEUL,    INSN_MACRO      },
 140 {"bgeul",   "s,I,p",    2,    (int) M_BGEUL_I,  INSN_MACRO      },
 141 {"bgez",    "s,p",      0x04010000, 0xfc1f0000, CBD|RD_s        },
 142 {"bgezl",   "s,p",      0x04030000, 0xfc1f0000, CBL|RD_s|I2     },
 143 {"bgezal",  "s,p",      0x04110000, 0xfc1f0000, CBD|RD_s|WR_31  },
 144 {"bgezall", "s,p",      0x04130000, 0xfc1f0000, CBL|RD_s|I2     },
 145 {"bgt",     "s,t,p",    0,    (int) M_BGT,      INSN_MACRO      },
 146 {"bgt",     "s,I,p",    0,    (int) M_BGT_I,    INSN_MACRO      },
 147 {"bgtl",    "s,t,p",    2,    (int) M_BGTL,     INSN_MACRO      },
 148 {"bgtl",    "s,I,p",    2,    (int) M_BGTL_I,   INSN_MACRO      },
 149 {"bgtu",    "s,t,p",    0,    (int) M_BGTU,     INSN_MACRO      },
 150 {"bgtu",    "s,I,p",    0,    (int) M_BGTU_I,   INSN_MACRO      },
 151 {"bgtul",   "s,t,p",    2,    (int) M_BGTUL,    INSN_MACRO      },
 152 {"bgtul",   "s,I,p",    2,    (int) M_BGTUL_I,  INSN_MACRO      },
 153 {"bgtz",    "s,p",      0x1c000000, 0xfc1f0000, CBD|RD_s        },
 154 {"bgtzl",   "s,p",      0x5c000000, 0xfc1f0000, CBL|RD_s|I2     },
 155 {"ble",     "s,t,p",    0,    (int) M_BLE,      INSN_MACRO      },
 156 {"ble",     "s,I,p",    0,    (int) M_BLE_I,    INSN_MACRO      },
 157 {"blel",    "s,t,p",    2,    (int) M_BLEL,     INSN_MACRO      },
 158 {"blel",    "s,I,p",    2,    (int) M_BLEL_I,   INSN_MACRO      },
 159 {"bleu",    "s,t,p",    0,    (int) M_BLEU,     INSN_MACRO      },
 160 {"bleu",    "s,I,p",    0,    (int) M_BLEU_I,   INSN_MACRO      },
 161 {"bleul",   "s,t,p",    2,    (int) M_BLEUL,    INSN_MACRO      },
 162 {"bleul",   "s,I,p",    2,    (int) M_BLEUL_I,  INSN_MACRO      },
 163 {"blez",    "s,p",      0x18000000, 0xfc1f0000, CBD|RD_s        },
 164 {"blezl",   "s,p",      0x58000000, 0xfc1f0000, CBL|RD_s|I2     },
 165 {"blt",     "s,t,p",    0,    (int) M_BLT,      INSN_MACRO      },
 166 {"blt",     "s,I,p",    0,    (int) M_BLT_I,    INSN_MACRO      },
 167 {"bltl",    "s,t,p",    2,    (int) M_BLTL,     INSN_MACRO      },
 168 {"bltl",    "s,I,p",    2,    (int) M_BLTL_I,   INSN_MACRO      },
 169 {"bltu",    "s,t,p",    0,    (int) M_BLTU,     INSN_MACRO      },
 170 {"bltu",    "s,I,p",    0,    (int) M_BLTU_I,   INSN_MACRO      },
 171 {"bltul",   "s,t,p",    2,    (int) M_BLTUL,    INSN_MACRO      },
 172 {"bltul",   "s,I,p",    2,    (int) M_BLTUL_I,  INSN_MACRO      },
 173 {"bltz",    "s,p",      0x04000000, 0xfc1f0000, CBD|RD_s        },
 174 {"bltzl",   "s,p",      0x04020000, 0xfc1f0000, CBL|RD_s|I2     },
 175 {"bltzal",  "s,p",      0x04100000, 0xfc1f0000, CBD|RD_s|WR_31  },
 176 {"bltzall", "s,p",      0x04120000, 0xfc1f0000, CBL|RD_s|I2     },
 177 {"bnez",    "s,p",      0x14000000, 0xfc1f0000, CBD|RD_s        },
 178 {"bnezl",   "s,p",      0x54000000, 0xfc1f0000, CBL|RD_s|I2     },
 179 {"bne",     "s,t,p",    0x14000000, 0xfc000000, CBD|RD_s|RD_t   },
 180 {"bne",     "s,I,p",    0,    (int) M_BNE_I,    INSN_MACRO      },
 181 {"bnel",    "s,t,p",    0x54000000, 0xfc000000, CBL|RD_s|RD_t|I2},
 182 {"bnel",    "s,I,p",    2,    (int) M_BNEL_I,   INSN_MACRO      },
 183 {"break",   "",         0x0000000d, 0xffffffff, TRAP            },
 184 {"break",   "c",        0x0000000d, 0xfc00003f, TRAP            },
 185 {"c.f.d",   "S,T",      0x46200030, 0xffe007ff, RD_S|RD_T|WR_CC },
 186 {"c.f.s",   "S,T",      0x46000030, 0xffe007ff, RD_S|RD_T|WR_CC },
 187 {"c.un.d",  "S,T",      0x46200031, 0xffe007ff, RD_S|RD_T|WR_CC },
 188 {"c.un.s",  "S,T",      0x46000031, 0xffe007ff, RD_S|RD_T|WR_CC },
 189 {"c.eq.d",  "S,T",      0x46200032, 0xffe007ff, RD_S|RD_T|WR_CC },
 190 {"c.eq.s",  "S,T",      0x46000032, 0xffe007ff, RD_S|RD_T|WR_CC },
 191 {"c.ueq.d", "S,T",      0x46200033, 0xffe007ff, RD_S|RD_T|WR_CC },
 192 {"c.ueq.s", "S,T",      0x46000033, 0xffe007ff, RD_S|RD_T|WR_CC },
 193 {"c.olt.d", "S,T",      0x46200034, 0xffe007ff, RD_S|RD_T|WR_CC },
 194 {"c.olt.s", "S,T",      0x46000034, 0xffe007ff, RD_S|RD_T|WR_CC },
 195 {"c.ult.d", "S,T",      0x46200035, 0xffe007ff, RD_S|RD_T|WR_CC },
 196 {"c.ult.s", "S,T",      0x46000035, 0xffe007ff, RD_S|RD_T|WR_CC },
 197 {"c.ole.d", "S,T",      0x46200036, 0xffe007ff, RD_S|RD_T|WR_CC },
 198 {"c.ole.s", "S,T",      0x46000036, 0xffe007ff, RD_S|RD_T|WR_CC },
 199 {"c.ule.d", "S,T",      0x46200037, 0xffe007ff, RD_S|RD_T|WR_CC },
 200 {"c.ule.s", "S,T",      0x46000037, 0xffe007ff, RD_S|RD_T|WR_CC },
 201 {"c.sf.d",  "S,T",      0x46200038, 0xffe007ff, RD_S|RD_T|WR_CC },
 202 {"c.sf.s",  "S,T",      0x46000038, 0xffe007ff, RD_S|RD_T|WR_CC },
 203 {"c.ngle.d","S,T",      0x46200039, 0xffe007ff, RD_S|RD_T|WR_CC },
 204 {"c.ngle.s","S,T",      0x46000039, 0xffe007ff, RD_S|RD_T|WR_CC },
 205 {"c.seq.d", "S,T",      0x4620003a, 0xffe007ff, RD_S|RD_T|WR_CC },
 206 {"c.seq.s", "S,T",      0x4600003a, 0xffe007ff, RD_S|RD_T|WR_CC },
 207 {"c.ngl.d", "S,T",      0x4620003b, 0xffe007ff, RD_S|RD_T|WR_CC },
 208 {"c.ngl.s", "S,T",      0x4600003b, 0xffe007ff, RD_S|RD_T|WR_CC },
 209 {"c.lt.d",  "S,T",      0x4620003c, 0xffe007ff, RD_S|RD_T|WR_CC },
 210 {"c.lt.s",  "S,T",      0x4600003c, 0xffe007ff, RD_S|RD_T|WR_CC },
 211 {"c.nge.d", "S,T",      0x4620003d, 0xffe007ff, RD_S|RD_T|WR_CC },
 212 {"c.nge.s", "S,T",      0x4600003d, 0xffe007ff, RD_S|RD_T|WR_CC },
 213 {"c.le.d",  "S,T",      0x4620003e, 0xffe007ff, RD_S|RD_T|WR_CC },
 214 {"c.le.s",  "S,T",      0x4600003e, 0xffe007ff, RD_S|RD_T|WR_CC },
 215 {"c.ngt.d", "S,T",      0x4620003f, 0xffe007ff, RD_S|RD_T|WR_CC },
 216 {"c.ngt.s", "S,T",      0x4600003f, 0xffe007ff, RD_S|RD_T|WR_CC },
 217 {"cache",   "k,o(b)",   0xbc000000, 0xfc000000, RD_b|I3         },
 218 {"ceil.l.d", "D,S",     0x4620000a, 0xffff003f, WR_D|RD_S|I3    },
 219 {"ceil.l.s", "D,S",     0x4600000a, 0xffff003f, WR_D|RD_S|I3    },
 220 {"ceil.w.d", "D,S",     0x4620000e, 0xffff003f, WR_D|RD_S|I2    },
 221 {"ceil.w.s", "D,S",     0x4600000e, 0xffff003f, WR_D|RD_S|I2    },
 222 {"cfc0",    "t,G",      0x40400000, 0xffe007ff, LCD|WR_t|RD_C0  },
 223 {"cfc1",    "t,G",      0x44400000, 0xffe007ff, LCD|WR_t|RD_C1  },
 224 {"cfc1",    "t,S",      0x44400000, 0xffe007ff, LCD|WR_t|RD_C1  },
 225 {"cfc2",    "t,G",      0x48400000, 0xffe007ff, LCD|WR_t|RD_C2  },
 226 {"cfc3",    "t,G",      0x4c400000, 0xffe007ff, LCD|WR_t|RD_C3  },
 227 {"ctc0",    "t,G",      0x40c00000, 0xffe007ff, COD|RD_t|WR_CC  },
 228 {"ctc1",    "t,G",      0x44c00000, 0xffe007ff, COD|RD_t|WR_CC  },
 229 {"ctc1",    "t,S",      0x44c00000, 0xffe007ff, COD|RD_t|WR_CC  },
 230 {"ctc2",    "t,G",      0x48c00000, 0xffe007ff, COD|RD_t|WR_CC  },
 231 {"ctc3",    "t,G",      0x4cc00000, 0xffe007ff, COD|RD_t|WR_CC  },
 232 {"cvt.d.l", "D,S",      0x46a00021, 0xffff003f, WR_D|RD_S|I3    },
 233 {"cvt.d.s", "D,S",      0x46000021, 0xffff003f, WR_D|RD_S       },
 234 {"cvt.d.w", "D,S",      0x46800021, 0xffff003f, WR_D|RD_S       },
 235 {"cvt.l.d", "D,S",      0x46200025, 0xffff003f, WR_D|RD_S|I3    },
 236 {"cvt.l.s", "D,S",      0x46000025, 0xffff003f, WR_D|RD_S|I3    },
 237 {"cvt.s.l", "D,S",      0x46a00020, 0xffff003f, WR_D|RD_S|I3    },
 238 {"cvt.s.d", "D,S",      0x46200020, 0xffff003f, WR_D|RD_S       },
 239 {"cvt.s.w", "D,S",      0x46800020, 0xffff003f, WR_D|RD_S       },
 240 {"cvt.w.d", "D,S",      0x46200024, 0xffff003f, WR_D|RD_S       },
 241 {"cvt.w.s", "D,S",      0x46000024, 0xffff003f, WR_D|RD_S       },
 242 {"dabs",    "d,v",      3,    (int) M_DABS,     INSN_MACRO      },
 243 {"dadd",    "d,v,t",    0x0000002c, 0xfc0007ff, WR_d|RD_s|RD_t|I3},
 244 {"dadd",    "t,r,I",    3,    (int) M_DADD_I,   INSN_MACRO      },
 245 {"daddi",   "t,r,j",    0x60000000, 0xfc000000, WR_t|RD_s|I3    },
 246 {"daddiu",  "t,r,j",    0x64000000, 0xfc000000, WR_t|RD_s|I3    },
 247 {"daddu",   "d,v,t",    0x0000002d, 0xfc0007ff, WR_d|RD_s|RD_t|I3},
 248 {"daddu",   "t,r,I",    3,    (int) M_DADDU_I,  INSN_MACRO      },
 249 /* For ddiv, see the comments about div.  */
 250 {"ddiv",    "z,s,t",    0x0000001e, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO|I3 },
 251 {"ddiv",    "d,v,t",    3,    (int) M_DDIV_3,   INSN_MACRO      },
 252 {"ddiv",    "d,v,I",    3,    (int) M_DDIV_3I,  INSN_MACRO      },
 253 /* For ddivu, see the comments about div.  */
 254 {"ddivu",   "z,s,t",    0x0000001f, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO|I3 },
 255 {"ddivu",   "d,v,t",    3,    (int) M_DDIVU_3,  INSN_MACRO      },
 256 {"ddivu",   "d,v,I",    3,    (int) M_DDIVU_3I, INSN_MACRO      },
 257 /* The MIPS assembler treats the div opcode with two operands as
 258    though the first operand appeared twice (the first operand is both
 259    a source and a destination).  To get the div machine instruction,
 260    you must use an explicit destination of $0.  */
 261 {"div",     "z,s,t",    0x0000001a, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO   },
 262 {"div",     "d,v,t",    0,    (int) M_DIV_3,    INSN_MACRO      },
 263 {"div",     "d,v,I",    0,    (int) M_DIV_3I,   INSN_MACRO      },
 264 {"div.d",   "D,V,T",    0x46200003, 0xffe0003f, WR_D|RD_S|RD_T  },
 265 {"div.s",   "D,V,T",    0x46000003, 0xffe0003f, WR_D|RD_S|RD_T  },
 266 /* For divu, see the comments about div.  */
 267 {"divu",    "z,s,t",    0x0000001b, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO   },
 268 {"divu",    "d,v,t",    0,    (int) M_DIVU_3,   INSN_MACRO      },
 269 {"divu",    "d,v,I",    0,    (int) M_DIVU_3I,  INSN_MACRO      },
 270 {"dmfc0",   "t,G",      0x40200000, 0xffe007ff, LCD|WR_t|RD_C0|I3 },
 271 {"dmtc0",   "t,G",      0x40a00000, 0xffe007ff, COD|RD_t|WR_C0|WR_CC|I3 },
 272 {"dmfc1",   "t,S",      0x44200000, 0xffe007ff, LCD|WR_t|RD_S|I3 },
 273 {"dmtc1",   "t,S",      0x44a00000, 0xffe007ff, COD|RD_t|WR_S|I3 },
 274 {"dmul",    "d,v,t",    3,    (int) M_DMUL,     INSN_MACRO      },
 275 {"dmul",    "d,v,I",    3,    (int) M_DMUL_I,   INSN_MACRO      },
 276 {"dmulo",   "d,v,t",    3,    (int) M_DMULO,    INSN_MACRO      },
 277 {"dmulo",   "d,v,I",    3,    (int) M_DMULO_I,  INSN_MACRO      },
 278 {"dmulou",  "d,v,t",    3,    (int) M_DMULOU,   INSN_MACRO      },
 279 {"dmulou",  "d,v,I",    3,    (int) M_DMULOU_I, INSN_MACRO      },
 280 {"dmult",   "s,t",      0x0000001c, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO|I3 },
 281 {"dmultu",  "s,t",      0x0000001d, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO|I3 },
 282 {"dneg",    "d,w",      0x0000002e, 0xffe007ff, WR_d|RD_t|I3    }, /* dsub 0 */
 283 {"dnegu",   "d,w",      0x0000002f, 0xffe007ff, WR_d|RD_t|I3    }, /* dsubu 0*/
 284 {"drem",    "z,s,t",    0x0000001e, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO|I3 },
 285 {"drem",    "d,v,t",    3,    (int) M_DREM_3,   INSN_MACRO      },
 286 {"drem",    "d,v,I",    3,    (int) M_DREM_3I,  INSN_MACRO      },
 287 {"dremu",   "z,s,t",    0x0000001f, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO|I3 },
 288 {"dremu",   "d,v,t",    3,    (int) M_DREMU_3,  INSN_MACRO      },
 289 {"dremu",   "d,v,I",    3,    (int) M_DREMU_3I, INSN_MACRO      },
 290 {"dsllv",   "d,t,s",    0x00000014, 0xfc0007ff, WR_d|RD_t|RD_s|I3},
 291 {"dsll32",  "d,w,<",    0x0000003c, 0xffe0003f, WR_d|RD_t|I3    },
 292 {"dsll",    "d,w,s",    0x00000014, 0xfc0007ff, WR_d|RD_t|RD_s|I3}, /* dsllv */
 293 {"dsll",    "d,w,>",    0x0000003c, 0xffe0003f, WR_d|RD_t|I3    }, /* dsll32 */
 294 {"dsll",    "d,w,<",    0x00000038, 0xffe0003f, WR_d|RD_t|I3    },
 295 {"dsrav",   "d,t,s",    0x00000017, 0xfc0007ff, WR_d|RD_t|RD_s|I3},
 296 {"dsra32",  "d,w,<",    0x0000003f, 0xffe0003f, WR_d|RD_t|I3    },
 297 {"dsra",    "d,w,s",    0x00000017, 0xfc0007ff, WR_d|RD_t|RD_s|I3}, /* dsrav */
 298 {"dsra",    "d,w,>",    0x0000003f, 0xffe0003f, WR_d|RD_t|I3    }, /* dsra32 */
 299 {"dsra",    "d,w,<",    0x0000003b, 0xffe0003f, WR_d|RD_t|I3    },
 300 {"dsrlv",   "d,t,s",    0x00000016, 0xfc0007ff, WR_d|RD_t|RD_s|I3},
 301 {"dsrl32",  "d,w,<",    0x0000003e, 0xffe0003f, WR_d|RD_t|I3    },
 302 {"dsrl",    "d,w,s",    0x00000016, 0xfc0007ff, WR_d|RD_t|RD_s|I3}, /* dsrlv */
 303 {"dsrl",    "d,w,>",    0x0000003e, 0xffe0003f, WR_d|RD_t|I3    }, /* dsrl32 */
 304 {"dsrl",    "d,w,<",    0x0000003a, 0xffe0003f, WR_d|RD_t|I3    },
 305 {"dsub",    "d,v,t",    0x0000002e, 0xfc0007ff, WR_d|RD_s|RD_t|I3},
 306 {"dsub",    "d,v,I",    3,    (int) M_DSUB_I,   INSN_MACRO      },
 307 {"dsubu",   "d,v,t",    0x0000002f, 0xfc0007ff, WR_d|RD_s|RD_t|I3},
 308 {"dsubu",   "d,v,I",    3,    (int) M_DSUBU_I,  INSN_MACRO      },
 309 {"eret",    "",         0x42000018, 0xffffffff, I3              },
 310 {"floor.l.d", "D,S",    0x4620000b, 0xffff003f, WR_D|RD_S|I3    },
 311 {"floor.l.s", "D,S",    0x4600000b, 0xffff003f, WR_D|RD_S|I3    },
 312 {"floor.w.d", "D,S",    0x4620000f, 0xffff003f, WR_D|RD_S|I2    },
 313 {"floor.w.s", "D,S",    0x4600000f, 0xffff003f, WR_D|RD_S|I2    },
 314 {"jr",      "s",        0x00000008, 0xfc1fffff, UBD|RD_s        },
 315 {"j",       "s",        0x00000008, 0xfc1fffff, UBD|RD_s        }, /* jr */
 316 /* SVR4 PIC code requires special handling for j, so it must be a
 317    macro.  */
 318 {"j",       "a",        0,     (int) M_J_A,     INSN_MACRO      },
 319 /* This form of j is used by the disassembler and internally by the
 320    assembler, but will never match user input (because the line above
 321    will match first).  */
 322 {"j",       "a",        0x08000000, 0xfc000000, UBD             },
 323 {"jalr",    "s",        0x0000f809, 0xfc1fffff, UBD|RD_s|WR_d   },
 324 {"jalr",    "d,s",      0x00000009, 0xfc1f07ff, UBD|RD_s|WR_d   },
 325 /* SVR4 PIC code requires special handling for jal, so it must be a
 326    macro.  */
 327 {"jal",     "d,s",      0,     (int) M_JAL_2,   INSN_MACRO      },
 328 {"jal",     "s",        0,     (int) M_JAL_1,   INSN_MACRO      },
 329 {"jal",     "a",        0,     (int) M_JAL_A,   INSN_MACRO      },
 330 /* This form of jal is used by the disassembler and internally by the
 331    assembler, but will never match user input (because the line above
 332    will match first).  */
 333 {"jal",     "a",        0x0c000000, 0xfc000000, UBD|WR_31       },
 334 {"la",      "t,A(b)",   0,    (int) M_LA_AB,    INSN_MACRO      },
 335 {"lb",      "t,o(b)",   0x80000000, 0xfc000000, LDD|RD_b|WR_t   },
 336 {"lb",      "t,A(b)",   0,    (int) M_LB_AB,    INSN_MACRO      },
 337 {"lbu",     "t,o(b)",   0x90000000, 0xfc000000, LDD|RD_b|WR_t   },
 338 {"lbu",     "t,A(b)",   0,    (int) M_LBU_AB,   INSN_MACRO      },
 339 {"ld",      "t,o(b)",   0xdc000000, 0xfc000000, WR_t|RD_b|I3    },
 340 {"ld",      "t,o(b)",   0,    (int) M_LD_OB,    INSN_MACRO      },
 341 {"ld",      "t,A(b)",   0,    (int) M_LD_AB,    INSN_MACRO      },
 342 {"ldc1",    "T,o(b)",   0xd4000000, 0xfc000000, CLD|RD_b|WR_T|I2},
 343 {"ldc1",    "E,o(b)",   0xd4000000, 0xfc000000, CLD|RD_b|WR_T|I2},
 344 {"ldc1",    "T,A(b)",   2,    (int) M_LDC1_AB,  INSN_MACRO      },
 345 {"ldc1",    "E,A(b)",   2,    (int) M_LDC1_AB,  INSN_MACRO      },
 346 {"l.d",     "T,o(b)",   0xd4000000, 0xfc000000, CLD|RD_b|WR_T|I2}, /* ldc1 */
 347 {"l.d",     "T,o(b)",   0,    (int) M_L_DOB,    INSN_MACRO      },
 348 {"l.d",     "T,A(b)",   0,    (int) M_L_DAB,    INSN_MACRO      },
 349 {"ldc2",    "E,o(b)",   0xd8000000, 0xfc000000, CLD|RD_b|WR_CC|I2},
 350 {"ldc2",    "E,A(b)",   2,    (int) M_LDC2_AB,  INSN_MACRO      },
 351 {"ldc3",    "E,o(b)",   0xdc000000, 0xfc000000, CLD|RD_b|WR_CC|I2},
 352 {"ldc3",    "E,A(b)",   2,    (int) M_LDC3_AB,  INSN_MACRO      },
 353 {"ldl",     "t,o(b)",   0x68000000, 0xfc000000, LDD|WR_t|RD_b|I3},
 354 {"ldl",     "t,A(b)",   3,    (int) M_LDL_AB,   INSN_MACRO      },
 355 {"ldr",     "t,o(b)",   0x6c000000, 0xfc000000, LDD|WR_t|RD_b|I3},
 356 {"ldr",     "t,A(b)",   3,    (int) M_LDR_AB,   INSN_MACRO      },
 357 {"lh",      "t,o(b)",   0x84000000, 0xfc000000, LDD|RD_b|WR_t   },
 358 {"lh",      "t,A(b)",   0,    (int) M_LH_AB,    INSN_MACRO      },
 359 {"lhu",     "t,o(b)",   0x94000000, 0xfc000000, LDD|RD_b|WR_t   },
 360 {"lhu",     "t,A(b)",   0,    (int) M_LHU_AB,   INSN_MACRO      },
 361 /* li is at the start of the table.  */
 362 {"li.d",    "t,F",      0,    (int) M_LI_D,     INSN_MACRO      },
 363 {"li.d",    "T,L",      0,    (int) M_LI_DD,    INSN_MACRO      },
 364 {"li.s",    "t,f",      0,    (int) M_LI_S,     INSN_MACRO      },
 365 {"li.s",    "T,l",      0,    (int) M_LI_SS,    INSN_MACRO      },
 366 {"ll",      "t,o(b)",   0xc0000000, 0xfc000000, LDD|RD_b|WR_t|I2},
 367 {"ll",      "t,A(b)",   2,    (int) M_LL_AB,    INSN_MACRO      },
 368 {"lld",     "t,o(b)",   0xd0000000, 0xfc000000, LDD|RD_b|WR_t|I3},
 369 {"lld",     "t,A(b)",   3,    (int) M_LLD_AB,   INSN_MACRO      },
 370 {"lui",     "t,u",      0x3c000000, 0xffe00000, WR_t            },
 371 {"lw",      "t,o(b)",   0x8c000000, 0xfc000000, LDD|RD_b|WR_t   },
 372 {"lw",      "t,A(b)",   0,    (int) M_LW_AB,    INSN_MACRO      },
 373 {"lwc0",    "E,o(b)",   0xc0000000, 0xfc000000, CLD|RD_b|WR_CC  },
 374 {"lwc0",    "E,A(b)",   0,    (int) M_LWC0_AB,  INSN_MACRO      },
 375 {"lwc1",    "T,o(b)",   0xc4000000, 0xfc000000, CLD|RD_b|WR_T   },
 376 {"lwc1",    "E,o(b)",   0xc4000000, 0xfc000000, CLD|RD_b|WR_T   },
 377 {"lwc1",    "T,A(b)",   0,    (int) M_LWC1_AB,  INSN_MACRO      },
 378 {"lwc1",    "E,A(b)",   0,    (int) M_LWC1_AB,  INSN_MACRO      },
 379 {"l.s",     "T,o(b)",   0xc4000000, 0xfc000000, CLD|RD_b|WR_T   }, /* lwc1 */
 380 {"l.s",     "T,A(b)",   0,    (int) M_LWC1_AB,  INSN_MACRO      },
 381 {"lwc2",    "E,o(b)",   0xc8000000, 0xfc000000, CLD|RD_b|WR_CC  },
 382 {"lwc2",    "E,A(b)",   0,    (int) M_LWC2_AB,  INSN_MACRO      },
 383 {"lwc3",    "E,o(b)",   0xcc000000, 0xfc000000, CLD|RD_b|WR_CC  },
 384 {"lwc3",    "E,A(b)",   0,    (int) M_LWC3_AB,  INSN_MACRO      },
 385 {"lwl",     "t,o(b)",   0x88000000, 0xfc000000, LDD|RD_b|WR_t   },
 386 {"lwl",     "t,A(b)",   0,    (int) M_LWL_AB,   INSN_MACRO      },
 387 {"lcache",  "t,o(b)",   0x88000000, 0xfc000000, LDD|RD_b|WR_t|I2}, /* same */
 388 {"lcache",  "t,A(b)",   2,    (int) M_LWL_AB,   INSN_MACRO      }, /* as lwl */
 389 {"lwr",     "t,o(b)",   0x98000000, 0xfc000000, LDD|RD_b|WR_t   },
 390 {"lwr",     "t,A(b)",   0,    (int) M_LWR_AB,   INSN_MACRO      },
 391 {"flush",   "t,o(b)",   0x98000000, 0xfc000000, LDD|RD_b|WR_t|I2}, /* same */
 392 {"flush",   "t,A(b)",   2,    (int) M_LWR_AB,   INSN_MACRO      }, /* as lwr */
 393 {"lwu",     "t,o(b)",   0x9c000000, 0xfc000000, LDD|RD_b|WR_t|I3},
 394 {"lwu",     "t,A(b)",   3,    (int) M_LWU_AB,   INSN_MACRO      },
 395 {"mad",     "s,t",      0x70000000, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO|RD_HI|RD_LO|P3},
 396 {"madu",    "s,t",      0x70000001, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO|RD_HI|RD_LO|P3},
 397 {"mfc0",    "t,G",      0x40000000, 0xffe007ff, LCD|WR_t|RD_C0  },
 398 {"mfc1",    "t,S",      0x44000000, 0xffe007ff, LCD|WR_t|RD_S   },
 399 {"mfc1",    "t,G",      0x44000000, 0xffe007ff, LCD|WR_t|RD_S   },
 400 {"mfc2",    "t,G",      0x48000000, 0xffe007ff, LCD|WR_t|RD_C2  },
 401 {"mfc3",    "t,G",      0x4c000000, 0xffe007ff, LCD|WR_t|RD_C3  },
 402 {"mfhi",    "d",        0x00000010, 0xffff07ff, WR_d|RD_HI      },
 403 {"mflo",    "d",        0x00000012, 0xffff07ff, WR_d|RD_LO      },
 404 {"mov.d",   "D,S",      0x46200006, 0xffff003f, WR_D|RD_S       },
 405 {"mov.s",   "D,S",      0x46000006, 0xffff003f, WR_D|RD_S       },
 406 /* move is at the top of the table.  */
 407 {"mtc0",    "t,G",      0x40800000, 0xffe007ff, COD|RD_t|WR_C0|WR_CC    },
 408 {"mtc1",    "t,S",      0x44800000, 0xffe007ff, COD|RD_t|WR_S   },
 409 {"mtc1",    "t,G",      0x44800000, 0xffe007ff, COD|RD_t|WR_S   },
 410 {"mtc2",    "t,G",      0x48800000, 0xffe007ff, COD|RD_t|WR_C2|WR_CC    },
 411 {"mtc3",    "t,G",      0x4c800000, 0xffe007ff, COD|RD_t|WR_C3|WR_CC    },
 412 {"mthi",    "s",        0x00000011, 0xfc1fffff, RD_s|WR_HI      },
 413 {"mtlo",    "s",        0x00000013, 0xfc1fffff, RD_s|WR_LO      },
 414 {"mul.d",   "D,V,T",    0x46200002, 0xffe0003f, WR_D|RD_S|RD_T  },
 415 {"mul.s",   "D,V,T",    0x46000002, 0xffe0003f, WR_D|RD_S|RD_T  },
 416 {"mul",     "d,v,t",    0x70000002, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HI|WR_LO|P3},
 417 {"mul",     "d,v,t",    0,    (int) M_MUL,      INSN_MACRO      },
 418 {"mul",     "d,v,I",    0,    (int) M_MUL_I,    INSN_MACRO      },
 419 {"mulo",    "d,v,t",    0,    (int) M_MULO,     INSN_MACRO      },
 420 {"mulo",    "d,v,I",    0,    (int) M_MULO_I,   INSN_MACRO      },
 421 {"mulou",   "d,v,t",    0,    (int) M_MULOU,    INSN_MACRO      },
 422 {"mulou",   "d,v,I",    0,    (int) M_MULOU_I,  INSN_MACRO      },
 423 {"mult",    "s,t",      0x00000018, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO   },
 424 {"multu",   "s,t",      0x00000019, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO   },
 425 {"neg",     "d,w",      0x00000022, 0xffe007ff, WR_d|RD_t       }, /* sub 0 */
 426 {"negu",    "d,w",      0x00000023, 0xffe007ff, WR_d|RD_t       }, /* subu 0 */
 427 {"neg.d",   "D,V",      0x46200007, 0xffff003f, WR_D|RD_S       },
 428 {"neg.s",   "D,V",      0x46000007, 0xffff003f, WR_D|RD_S       },
 429 /* nop is at the start of the table.  */
 430 {"nor",     "d,v,t",    0x00000027, 0xfc0007ff, WR_d|RD_s|RD_t  },
 431 {"nor",     "t,r,I",    0,    (int) M_NOR_I,    INSN_MACRO      },
 432 {"not",     "d,v",      0x00000027, 0xfc0007ff, WR_d|RD_s|RD_t  },/*nor d,s,0*/
 433 {"or",      "d,v,t",    0x00000025, 0xfc0007ff, WR_d|RD_s|RD_t  },
 434 {"or",      "t,r,I",    0,    (int) M_OR_I,     INSN_MACRO      },
 435 {"ori",     "t,r,i",    0x34000000, 0xfc000000, WR_t|RD_s       },
 436 {"rem",     "z,s,t",    0x0000001a, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO },
 437 {"rem",     "d,v,t",    0,    (int) M_REM_3,    INSN_MACRO      },
 438 {"rem",     "d,v,I",    0,    (int) M_REM_3I,   INSN_MACRO      },
 439 {"remu",    "z,s,t",    0x0000001b, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO },
 440 {"remu",    "d,v,t",    0,    (int) M_REMU_3,   INSN_MACRO      },
 441 {"remu",    "d,v,I",    0,    (int) M_REMU_3I,  INSN_MACRO      },
 442 {"rfe",     "",         0x42000010, 0xffffffff, INSN_RFE        },
 443 {"rol",     "d,v,t",    0,    (int) M_ROL,      INSN_MACRO      },
 444 {"rol",     "d,v,I",    0,    (int) M_ROL_I,    INSN_MACRO      },
 445 {"ror",     "d,v,t",    0,    (int) M_ROR,      INSN_MACRO      },
 446 {"ror",     "d,v,I",    0,    (int) M_ROR_I,    INSN_MACRO      },
 447 {"round.l.d", "D,S",    0x46200008, 0xffff003f, WR_D|RD_S|I3    },
 448 {"round.l.s", "D,S",    0x46000008, 0xffff003f, WR_D|RD_S|I3    },
 449 {"round.w.d", "D,S",    0x4620000c, 0xffff003f, WR_D|RD_S|I2    },
 450 {"round.w.s", "D,S",    0x4600000c, 0xffff003f, WR_D|RD_S|I2    },
 451 {"sb",      "t,o(b)",   0xa0000000, 0xfc000000, SM|RD_t|RD_b    },
 452 {"sb",      "t,A(b)",   0,    (int) M_SB_AB,    INSN_MACRO      },
 453 {"sc",      "t,o(b)",   0xe0000000, 0xfc000000, SM|RD_t|WR_t|RD_b|I2 },
 454 {"sc",      "t,A(b)",   2,    (int) M_SC_AB,    INSN_MACRO      },
 455 {"scd",     "t,o(b)",   0xf0000000, 0xfc000000, SM|RD_t|WR_t|RD_b|I3 },
 456 {"scd",     "t,A(b)",   3,    (int) M_SCD_AB,   INSN_MACRO      },
 457 {"sd",      "t,o(b)",   0xfc000000, 0xfc000000, SM|RD_t|RD_b|I3 },
 458 {"sd",      "t,o(b)",   0,    (int) M_SD_OB,    INSN_MACRO      },
 459 {"sd",      "t,A(b)",   0,    (int) M_SD_AB,    INSN_MACRO      },
 460 {"sdc1",    "T,o(b)",   0xf4000000, 0xfc000000, SM|RD_T|RD_b|I2 },
 461 {"sdc1",    "E,o(b)",   0xf4000000, 0xfc000000, SM|RD_T|RD_b|I2 },
 462 {"sdc1",    "T,A(b)",   2,    (int) M_SDC1_AB,  INSN_MACRO      },
 463 {"sdc1",    "E,A(b)",   2,    (int) M_SDC1_AB,  INSN_MACRO      },
 464 {"sdc2",    "E,o(b)",   0xf8000000, 0xfc000000, SM|RD_C2|RD_b|I2 },
 465 {"sdc2",    "E,A(b)",   2,    (int) M_SDC2_AB,  INSN_MACRO      },
 466 {"sdc3",    "E,o(b)",   0xfc000000, 0xfc000000, SM|RD_C3|RD_b|I2 },
 467 {"sdc3",    "E,A(b)",   2,    (int) M_SDC3_AB,  INSN_MACRO      },
 468 {"s.d",     "T,o(b)",   0xf4000000, 0xfc000000, SM|RD_T|RD_b|I2 },
 469 {"s.d",     "T,o(b)",   0,    (int) M_S_DOB,    INSN_MACRO      },
 470 {"s.d",     "T,A(b)",   0,    (int) M_S_DAB,    INSN_MACRO      },
 471 {"sdl",     "t,o(b)",   0xb0000000, 0xfc000000, SM|RD_t|RD_b|I3 },
 472 {"sdl",     "t,A(b)",   3,    (int) M_SDL_AB,   INSN_MACRO      },
 473 {"sdr",     "t,o(b)",   0xb4000000, 0xfc000000, SM|RD_t|RD_b|I3 },
 474 {"sdr",     "t,A(b)",   3,    (int) M_SDR_AB,   INSN_MACRO      },
 475 {"seq",     "d,v,t",    0,    (int) M_SEQ,      INSN_MACRO      },
 476 {"seq",     "d,v,I",    0,    (int) M_SEQ_I,    INSN_MACRO      },
 477 {"sge",     "d,v,t",    0,    (int) M_SGE,      INSN_MACRO      },
 478 {"sge",     "d,v,I",    0,    (int) M_SGE_I,    INSN_MACRO      },
 479 {"sgeu",    "d,v,t",    0,    (int) M_SGEU,     INSN_MACRO      },
 480 {"sgeu",    "d,v,I",    0,    (int) M_SGEU_I,   INSN_MACRO      },
 481 {"sgt",     "d,v,t",    0,    (int) M_SGT,      INSN_MACRO      },
 482 {"sgt",     "d,v,I",    0,    (int) M_SGT_I,    INSN_MACRO      },
 483 {"sgtu",    "d,v,t",    0,    (int) M_SGTU,     INSN_MACRO      },
 484 {"sgtu",    "d,v,I",    0,    (int) M_SGTU_I,   INSN_MACRO      },
 485 {"sh",      "t,o(b)",   0xa4000000, 0xfc000000, SM|RD_t|RD_b    },
 486 {"sh",      "t,A(b)",   0,    (int) M_SH_AB,    INSN_MACRO      },
 487 {"sle",     "d,v,t",    0,    (int) M_SLE,      INSN_MACRO      },
 488 {"sle",     "d,v,I",    0,    (int) M_SLE_I,    INSN_MACRO      },
 489 {"sleu",    "d,v,t",    0,    (int) M_SLEU,     INSN_MACRO      },
 490 {"sleu",    "d,v,I",    0,    (int) M_SLEU_I,   INSN_MACRO      },
 491 {"sllv",    "d,t,s",    0x00000004, 0xfc0007ff, WR_d|RD_t|RD_s  },
 492 {"sll",     "d,w,s",    0x00000004, 0xfc0007ff, WR_d|RD_t|RD_s  }, /* sllv */
 493 {"sll",     "d,w,<",    0x00000000, 0xffe0003f, WR_d|RD_t       },
 494 {"slt",     "d,v,t",    0x0000002a, 0xfc0007ff, WR_d|RD_s|RD_t  },
 495 {"slt",     "d,v,I",    0,    (int) M_SLT_I,    INSN_MACRO      },
 496 {"slti",    "t,r,j",    0x28000000, 0xfc000000, WR_t|RD_s       },
 497 {"sltiu",   "t,r,j",    0x2c000000, 0xfc000000, WR_t|RD_s       },
 498 {"sltu",    "d,v,t",    0x0000002b, 0xfc0007ff, WR_d|RD_s|RD_t  },
 499 {"sltu",    "d,v,I",    0,    (int) M_SLTU_I,   INSN_MACRO      },
 500 {"sne",     "d,v,t",    0,    (int) M_SNE,      INSN_MACRO      },
 501 {"sne",     "d,v,I",    0,    (int) M_SNE_I,    INSN_MACRO      },
 502 {"sqrt.d",  "D,S",      0x46200004, 0xffff003f, WR_D|RD_S|I2    },
 503 {"sqrt.s",  "D,S",      0x46000004, 0xffff003f, WR_D|RD_S|I2    },
 504 {"srav",    "d,t,s",    0x00000007, 0xfc0007ff, WR_d|RD_t|RD_s  },
 505 {"sra",     "d,w,s",    0x00000007, 0xfc0007ff, WR_d|RD_t|RD_s  }, /* srav */
 506 {"sra",     "d,w,<",    0x00000003, 0xffe0003f, WR_d|RD_t       },
 507 {"srlv",    "d,t,s",    0x00000006, 0xfc0007ff, WR_d|RD_t|RD_s  },
 508 {"srl",     "d,w,s",    0x00000006, 0xfc0007ff, WR_d|RD_t|RD_s  }, /* srlv */
 509 {"srl",     "d,w,<",    0x00000002, 0xffe0003f, WR_d|RD_t       },
 510 {"sub",     "d,v,t",    0x00000022, 0xfc0007ff, WR_d|RD_s|RD_t  },
 511 {"sub",     "d,v,I",    0,    (int) M_SUB_I,    INSN_MACRO      },
 512 {"sub.d",   "D,V,T",    0x46200001, 0xffe0003f, WR_D|RD_S|RD_T  },
 513 {"sub.s",   "D,V,T",    0x46000001, 0xffe0003f, WR_D|RD_S|RD_T  },
 514 {"subu",    "d,v,t",    0x00000023, 0xfc0007ff, WR_d|RD_s|RD_t  },
 515 {"subu",    "d,v,I",    0,    (int) M_SUBU_I,   INSN_MACRO      },
 516 {"sw",      "t,o(b)",   0xac000000, 0xfc000000, SM|RD_t|RD_b    },
 517 {"sw",      "t,A(b)",   0,    (int) M_SW_AB,    INSN_MACRO      },
 518 {"swc0",    "E,o(b)",   0xe0000000, 0xfc000000, SM|RD_C0|RD_b   },
 519 {"swc0",    "E,A(b)",   0,    (int) M_SWC0_AB,  INSN_MACRO      },
 520 {"swc1",    "T,o(b)",   0xe4000000, 0xfc000000, SM|RD_T|RD_b    },
 521 {"swc1",    "E,o(b)",   0xe4000000, 0xfc000000, SM|RD_T|RD_b    },
 522 {"swc1",    "T,A(b)",   0,    (int) M_SWC1_AB,  INSN_MACRO      },
 523 {"swc1",    "E,A(b)",   0,    (int) M_SWC1_AB,  INSN_MACRO      },
 524 {"s.s",     "T,o(b)",   0xe4000000, 0xfc000000, SM|RD_T|RD_b    }, /* swc1 */
 525 {"s.s",     "T,A(b)",   0,    (int) M_SWC1_AB,  INSN_MACRO      },
 526 {"swc2",    "E,o(b)",   0xe8000000, 0xfc000000, SM|RD_C2|RD_b   },
 527 {"swc2",    "E,A(b)",   0,    (int) M_SWC2_AB,  INSN_MACRO      },
 528 {"swc3",    "E,o(b)",   0xec000000, 0xfc000000, SM|RD_C3|RD_b   },
 529 {"swc3",    "E,A(b)",   0,    (int) M_SWC3_AB,  INSN_MACRO      },
 530 {"swl",     "t,o(b)",   0xa8000000, 0xfc000000, SM|RD_t|RD_b    },
 531 {"swl",     "t,A(b)",   0,    (int) M_SWL_AB,   INSN_MACRO      },
 532 {"scache",  "t,o(b)",   0xa8000000, 0xfc000000, RD_t|RD_b|I2    }, /* same */
 533 {"scache",  "t,A(b)",   2,    (int) M_SWL_AB,   INSN_MACRO      }, /* as swl */
 534 {"swr",     "t,o(b)",   0xb8000000, 0xfc000000, SM|RD_t|RD_b    },
 535 {"swr",     "t,A(b)",   0,    (int) M_SWR_AB,   INSN_MACRO      },
 536 {"invalidate", "t,o(b)",0xb8000000, 0xfc000000, RD_t|RD_b|I2    }, /* same */
 537 {"invalidate", "t,A(b)",2,    (int) M_SWR_AB,   INSN_MACRO      }, /* as swr */
 538 {"sync",    "",         0x0000000f, 0xffffffff, I2              },
 539 {"syscall", "",         0x0000000c, 0xffffffff, TRAP            },
 540 {"syscall", "B",        0x0000000c, 0xfc00003f, TRAP            },
 541 {"teqi",    "s,j",      0x040c0000, 0xfc1f0000, RD_s|I2|TRAP    },
 542 {"teq",     "s,t",      0x00000034, 0xfc00003f, RD_s|RD_t|I2|TRAP },
 543 {"teq",     "s,j",      0x040c0000, 0xfc1f0000, RD_s|I2|TRAP    }, /* teqi */
 544 {"teq",     "s,I",      2,    (int) M_TEQ_I,    INSN_MACRO      },
 545 {"tgei",    "s,j",      0x04080000, 0xfc1f0000, RD_s|I2|TRAP    },
 546 {"tge",     "s,t",      0x00000030, 0xfc00003f, RD_s|RD_t|I2|TRAP },
 547 {"tge",     "s,j",      0x04080000, 0xfc1f0000, RD_s|I2|TRAP    }, /* tgei */
 548 {"tge",     "s,I",      2,    (int) M_TGE_I,    INSN_MACRO      },
 549 {"tgeiu",   "s,j",      0x04090000, 0xfc1f0000, RD_s|I2|TRAP    },
 550 {"tgeu",    "s,t",      0x00000031, 0xfc00003f, RD_s|RD_t|I2|TRAP },
 551 {"tgeu",    "s,j",      0x04090000, 0xfc1f0000, RD_s|I2|TRAP    }, /* tgeiu */
 552 {"tgeu",    "s,I",      2,    (int) M_TGEU_I,   INSN_MACRO      },
 553 {"tlbp",    "",         0x42000008, 0xffffffff, INSN_TLB        },
 554 {"tlbr",    "",         0x42000001, 0xffffffff, INSN_TLB        },
 555 {"tlbwi",   "",         0x42000002, 0xffffffff, INSN_TLB        },
 556 {"tlbwr",   "",         0x42000006, 0xffffffff, INSN_TLB        },
 557 {"tlti",    "s,j",      0x040a0000, 0xfc1f0000, RD_s|I2|TRAP    },
 558 {"tlt",     "s,t",      0x00000032, 0xfc00003f, RD_s|RD_t|I2|TRAP },
 559 {"tlt",     "s,j",      0x040a0000, 0xfc1f0000, RD_s|I2|TRAP    }, /* tlti */
 560 {"tlt",     "s,I",      2,    (int) M_TLT_I,    INSN_MACRO      },
 561 {"tltiu",   "s,j",      0x040b0000, 0xfc1f0000, RD_s|I2|TRAP    },
 562 {"tltu",    "s,t",      0x00000033, 0xfc00003f, RD_s|RD_t|I2|TRAP },
 563 {"tltu",    "s,j",      0x040b0000, 0xfc1f0000, RD_s|I2|TRAP    }, /* tltiu */
 564 {"tltu",    "s,I",      2,    (int) M_TLTU_I,   INSN_MACRO      },
 565 {"tnei",    "s,j",      0x040e0000, 0xfc1f0000, RD_s|I2|TRAP    },
 566 {"tne",     "s,t",      0x00000036, 0xfc00003f, RD_s|RD_t|I2|TRAP },
 567 {"tne",     "s,j",      0x040e0000, 0xfc1f0000, RD_s|I2|TRAP    }, /* tnei */
 568 {"tne",     "s,I",      2,    (int) M_TNE_I,    INSN_MACRO      },
 569 {"trunc.l.d", "D,S",    0x46200009, 0xffff003f, WR_D|RD_S|I3    },
 570 {"trunc.l.s", "D,S",    0x46000009, 0xffff003f, WR_D|RD_S|I3    },
 571 {"trunc.w.d", "D,S",    0x4620000d, 0xffff003f, WR_D|RD_S|I2    },
 572 {"trunc.w.d", "D,S,x",  0x4620000d, 0xffff003f, WR_D|RD_S|I2    },
 573 {"trunc.w.d", "D,S,t",  0,    (int) M_TRUNCWD,  INSN_MACRO      },
 574 {"trunc.w.s", "D,S",    0x4600000d, 0xffff003f, WR_D|RD_S|I2    },
 575 {"trunc.w.s", "D,S,x",  0x4600000d, 0xffff003f, WR_D|RD_S|I2    },
 576 {"trunc.w.s", "D,S,t",  0,    (int) M_TRUNCWS,  INSN_MACRO      },
 577 {"uld",     "t,o(b)",   3,    (int) M_ULD,      INSN_MACRO      },
 578 {"uld",     "t,A",      3,    (int) M_ULD_A,    INSN_MACRO      },
 579 {"ulh",     "t,o(b)",   0,    (int) M_ULH,      INSN_MACRO      },
 580 {"ulh",     "t,A",      0,    (int) M_ULH_A,    INSN_MACRO      },
 581 {"ulhu",    "t,o(b)",   0,    (int) M_ULHU,     INSN_MACRO      },
 582 {"ulhu",    "t,A",      0,    (int) M_ULHU_A,   INSN_MACRO      },
 583 {"ulw",     "t,o(b)",   0,    (int) M_ULW,      INSN_MACRO      },
 584 {"ulw",     "t,A",      0,    (int) M_ULW_A,    INSN_MACRO      },
 585 {"usd",     "t,o(b)",   3,    (int) M_USD,      INSN_MACRO      },
 586 {"usd",     "t,A",      3,    (int) M_USD_A,    INSN_MACRO      },
 587 {"ush",     "t,o(b)",   0,    (int) M_USH,      INSN_MACRO      },
 588 {"ush",     "t,A",      0,    (int) M_USH_A,    INSN_MACRO      },
 589 {"usw",     "t,o(b)",   0,    (int) M_USW,      INSN_MACRO      },
 590 {"usw",     "t,A",      0,    (int) M_USW_A,    INSN_MACRO      },
 591 {"xor",     "d,v,t",    0x00000026, 0xfc0007ff, WR_d|RD_s|RD_t  },
 592 {"xor",     "t,r,I",    0,    (int) M_XOR_I,    INSN_MACRO      },
 593 {"xori",    "t,r,i",    0x38000000, 0xfc000000, WR_t|RD_s       },
 594 /* No hazard protection on coprocessor instructions--they shouldn't
 595    change the state of the processor and if they do it's up to the
 596    user to put in nops as necessary.  These are at the end so that the
 597    disasembler recognizes more specific versions first.  */
 598 {"c0",      "C",        0x42000000, 0xfe000000, 0               },
 599 {"c1",      "C",        0x46000000, 0xfe000000, 0               },
 600 {"c2",      "C",        0x4a000000, 0xfe000000, 0               },
 601 {"c3",      "C",        0x4e000000, 0xfe000000, 0               },
 602 };
 603
 604 const int bfd_mips_num_opcodes =
 605   ((sizeof mips_opcodes) / (sizeof (mips_opcodes[0])));