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7aa1d0e1bef8b1c7b990d388e3499dac39a2b68c
[deliverable/binutils-gdb.git] / opcodes / mips-opc.c
1 /* mips.h. Mips opcode list for GDB, the GNU debugger.
2 Copyright 1993 Free Software Foundation, Inc.
3 Contributed by Ralph Campbell and OSF
4 Commented and modified by Ian Lance Taylor, Cygnus Support
5
6 This file is part of GDB, GAS, and the GNU binutils.
7
8 GDB, GAS, and the GNU binutils are free software; you can redistribute
9 them and/or modify them under the terms of the GNU General Public
10 License as published by the Free Software Foundation; either version
11 1, or (at your option) any later version.
12
13 GDB, GAS, and the GNU binutils are distributed in the hope that they
14 will be useful, but WITHOUT ANY WARRANTY; without even the implied
15 warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See
16 the GNU General Public License for more details.
17
18 You should have received a copy of the GNU General Public License
19 along with this file; see the file COPYING. If not, write to the Free
20 Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
21
22 #include <stdio.h>
23 #include "ansidecl.h"
24 #include "opcode/mips.h"
25
26 /* Short hand so the lines aren't too long. */
27
28 #define LDD INSN_LOAD_MEMORY_DELAY
29 #define LCD INSN_LOAD_COPROC_DELAY
30 #define UBD INSN_UNCOND_BRANCH_DELAY
31 #define CBD INSN_COND_BRANCH_DELAY
32 #define COD INSN_COPROC_MOVE_DELAY
33 #define CLD INSN_COPROC_MEMORY_DELAY
34 #define CBL INSN_COND_BRANCH_LIKELY
35 #define TRAP INSN_TRAP
36 #define SM INSN_STORE_MEMORY
37
38 #define WR_d INSN_WRITE_GPR_D
39 #define WR_t INSN_WRITE_GPR_T
40 #define WR_31 INSN_WRITE_GPR_31
41 #define WR_D INSN_WRITE_FPR_D
42 #define WR_T INSN_WRITE_FPR_T
43 #define WR_S INSN_WRITE_FPR_S
44 #define RD_s INSN_READ_GPR_S
45 #define RD_b INSN_READ_GPR_S
46 #define RD_t INSN_READ_GPR_T
47 #define RD_S INSN_READ_FPR_S
48 #define RD_T INSN_READ_FPR_T
49 #define RD_R INSN_READ_FPR_R
50 #define WR_CC INSN_WRITE_COND_CODE
51 #define RD_CC INSN_READ_COND_CODE
52 #define RD_C0 INSN_COP
53 #define RD_C1 INSN_COP
54 #define RD_C2 INSN_COP
55 #define RD_C3 INSN_COP
56 #define WR_C0 INSN_COP
57 #define WR_C1 INSN_COP
58 #define WR_C2 INSN_COP
59 #define WR_C3 INSN_COP
60 #define WR_HI INSN_WRITE_HI
61 #define WR_LO INSN_WRITE_LO
62 #define RD_HI INSN_READ_HI
63 #define RD_LO INSN_READ_LO
64
65 #define I2 INSN_ISA2
66 #define I3 INSN_ISA3
67 #define P3 INSN_4650
68 #define I4 INSN_ISA4
69 #define L1 INSN_4010
70 #define V1 INSN_4100
71
72 /* The order of overloaded instructions matters. Label arguments and
73 register arguments look the same. Instructions that can have either
74 for arguments must apear in the correct order in this table for the
75 assembler to pick the right one. In other words, entries with
76 immediate operands must apear after the same instruction with
77 registers.
78
79 Many instructions are short hand for other instructions (i.e., The
80 jal <register> instruction is short for jalr <register>). */
81
82 const struct mips_opcode mips_opcodes[] = {
83 /* These instructions appear first so that the disassembler will find
84 them first. The assemblers uses a hash table based on the
85 instruction name anyhow. */
86 {"nop", "", 0x00000000, 0xffffffff, 0 },
87 {"li", "t,j", 0x24000000, 0xffe00000, WR_t }, /* addiu */
88 {"li", "t,i", 0x34000000, 0xffe00000, WR_t }, /* ori */
89 {"li", "t,I", 0, (int) M_LI, INSN_MACRO },
90 {"move", "d,s", 0x0000002d, 0xfc1f07ff, WR_d|RD_s|I3 },/* daddu */
91 {"move", "d,s", 0x00000021, 0xfc1f07ff, WR_d|RD_s },/* addu */
92 {"move", "d,s", 0x00000025, 0xfc1f07ff, WR_d|RD_s },/* or */
93 {"b", "p", 0x10000000, 0xffff0000, UBD },/* beq 0,0 */
94 {"b", "p", 0x04010000, 0xffff0000, UBD },/* bgez 0 */
95 {"bal", "p", 0x04110000, 0xffff0000, UBD|WR_31 },/* bgezal 0*/
96
97 {"abs", "d,v", 0, (int) M_ABS, INSN_MACRO },
98 {"abs.s", "D,V", 0x46000005, 0xffff003f, WR_D|RD_S },
99 {"abs.d", "D,V", 0x46200005, 0xffff003f, WR_D|RD_S },
100 {"add", "d,v,t", 0x00000020, 0xfc0007ff, WR_d|RD_s|RD_t },
101 {"add", "t,r,I", 0, (int) M_ADD_I, INSN_MACRO },
102 {"add.s", "D,V,T", 0x46000000, 0xffe0003f, WR_D|RD_S|RD_T },
103 {"add.d", "D,V,T", 0x46200000, 0xffe0003f, WR_D|RD_S|RD_T },
104 {"addi", "t,r,j", 0x20000000, 0xfc000000, WR_t|RD_s },
105 {"addiu", "t,r,j", 0x24000000, 0xfc000000, WR_t|RD_s },
106 {"addu", "d,v,t", 0x00000021, 0xfc0007ff, WR_d|RD_s|RD_t },
107 {"addu", "t,r,I", 0, (int) M_ADDU_I, INSN_MACRO },
108 {"and", "d,v,t", 0x00000024, 0xfc0007ff, WR_d|RD_s|RD_t },
109 {"and", "t,r,I", 0, (int) M_AND_I, INSN_MACRO },
110 {"andi", "t,r,i", 0x30000000, 0xfc000000, WR_t|RD_s },
111 /* b is at the top of the table. */
112 /* bal is at the top of the table. */
113 {"bc0f", "p", 0x41000000, 0xffff0000, CBD|RD_CC },
114 {"bc0fl", "p", 0x41020000, 0xffff0000, CBL|RD_CC|I2 },
115 {"bc1f", "p", 0x45000000, 0xffff0000, CBD|RD_CC },
116 {"bc1f", "N,p", 0x45000000, 0xffe30000, CBD|RD_CC|I4 },
117 {"bc1fl", "p", 0x45020000, 0xffff0000, CBL|RD_CC|I2 },
118 {"bc1fl", "N,p", 0x45020000, 0xffe30000, CBL|RD_CC|I4 },
119 {"bc2f", "p", 0x49000000, 0xffff0000, CBD|RD_CC },
120 {"bc2fl", "p", 0x49020000, 0xffff0000, CBL|RD_CC|I2 },
121 {"bc3f", "p", 0x4d000000, 0xffff0000, CBD|RD_CC },
122 {"bc3fl", "p", 0x4d020000, 0xffff0000, CBL|RD_CC|I2 },
123 {"bc0t", "p", 0x41010000, 0xffff0000, CBD|RD_CC },
124 {"bc0tl", "p", 0x41030000, 0xffff0000, CBL|RD_CC|I2 },
125 {"bc1t", "p", 0x45010000, 0xffff0000, CBD|RD_CC },
126 {"bc1t", "N,p", 0x45010000, 0xffe30000, CBD|RD_CC|I4 },
127 {"bc1tl", "p", 0x45030000, 0xffff0000, CBL|RD_CC|I2 },
128 {"bc1tl", "N,p", 0x45030000, 0xffe30000, CBL|RD_CC|I4 },
129 {"bc2t", "p", 0x49010000, 0xffff0000, CBD|RD_CC },
130 {"bc2tl", "p", 0x49030000, 0xffff0000, CBL|RD_CC|I2 },
131 {"bc3t", "p", 0x4d010000, 0xffff0000, CBD|RD_CC },
132 {"bc3tl", "p", 0x4d030000, 0xffff0000, CBL|RD_CC|I2 },
133 {"beqz", "s,p", 0x10000000, 0xfc1f0000, CBD|RD_s },
134 {"beqzl", "s,p", 0x50000000, 0xfc1f0000, CBL|RD_s|I2 },
135 {"beq", "s,t,p", 0x10000000, 0xfc000000, CBD|RD_s|RD_t },
136 {"beq", "s,I,p", 0, (int) M_BEQ_I, INSN_MACRO },
137 {"beql", "s,t,p", 0x50000000, 0xfc000000, CBL|RD_s|RD_t|I2},
138 {"beql", "s,I,p", 2, (int) M_BEQL_I, INSN_MACRO },
139 {"bge", "s,t,p", 0, (int) M_BGE, INSN_MACRO },
140 {"bge", "s,I,p", 0, (int) M_BGE_I, INSN_MACRO },
141 {"bgel", "s,t,p", 2, (int) M_BGEL, INSN_MACRO },
142 {"bgel", "s,I,p", 2, (int) M_BGEL_I, INSN_MACRO },
143 {"bgeu", "s,t,p", 0, (int) M_BGEU, INSN_MACRO },
144 {"bgeu", "s,I,p", 0, (int) M_BGEU_I, INSN_MACRO },
145 {"bgeul", "s,t,p", 2, (int) M_BGEUL, INSN_MACRO },
146 {"bgeul", "s,I,p", 2, (int) M_BGEUL_I, INSN_MACRO },
147 {"bgez", "s,p", 0x04010000, 0xfc1f0000, CBD|RD_s },
148 {"bgezl", "s,p", 0x04030000, 0xfc1f0000, CBL|RD_s|I2 },
149 {"bgezal", "s,p", 0x04110000, 0xfc1f0000, CBD|RD_s|WR_31 },
150 {"bgezall", "s,p", 0x04130000, 0xfc1f0000, CBL|RD_s|I2 },
151 {"bgt", "s,t,p", 0, (int) M_BGT, INSN_MACRO },
152 {"bgt", "s,I,p", 0, (int) M_BGT_I, INSN_MACRO },
153 {"bgtl", "s,t,p", 2, (int) M_BGTL, INSN_MACRO },
154 {"bgtl", "s,I,p", 2, (int) M_BGTL_I, INSN_MACRO },
155 {"bgtu", "s,t,p", 0, (int) M_BGTU, INSN_MACRO },
156 {"bgtu", "s,I,p", 0, (int) M_BGTU_I, INSN_MACRO },
157 {"bgtul", "s,t,p", 2, (int) M_BGTUL, INSN_MACRO },
158 {"bgtul", "s,I,p", 2, (int) M_BGTUL_I, INSN_MACRO },
159 {"bgtz", "s,p", 0x1c000000, 0xfc1f0000, CBD|RD_s },
160 {"bgtzl", "s,p", 0x5c000000, 0xfc1f0000, CBL|RD_s|I2 },
161 {"ble", "s,t,p", 0, (int) M_BLE, INSN_MACRO },
162 {"ble", "s,I,p", 0, (int) M_BLE_I, INSN_MACRO },
163 {"blel", "s,t,p", 2, (int) M_BLEL, INSN_MACRO },
164 {"blel", "s,I,p", 2, (int) M_BLEL_I, INSN_MACRO },
165 {"bleu", "s,t,p", 0, (int) M_BLEU, INSN_MACRO },
166 {"bleu", "s,I,p", 0, (int) M_BLEU_I, INSN_MACRO },
167 {"bleul", "s,t,p", 2, (int) M_BLEUL, INSN_MACRO },
168 {"bleul", "s,I,p", 2, (int) M_BLEUL_I, INSN_MACRO },
169 {"blez", "s,p", 0x18000000, 0xfc1f0000, CBD|RD_s },
170 {"blezl", "s,p", 0x58000000, 0xfc1f0000, CBL|RD_s|I2 },
171 {"blt", "s,t,p", 0, (int) M_BLT, INSN_MACRO },
172 {"blt", "s,I,p", 0, (int) M_BLT_I, INSN_MACRO },
173 {"bltl", "s,t,p", 2, (int) M_BLTL, INSN_MACRO },
174 {"bltl", "s,I,p", 2, (int) M_BLTL_I, INSN_MACRO },
175 {"bltu", "s,t,p", 0, (int) M_BLTU, INSN_MACRO },
176 {"bltu", "s,I,p", 0, (int) M_BLTU_I, INSN_MACRO },
177 {"bltul", "s,t,p", 2, (int) M_BLTUL, INSN_MACRO },
178 {"bltul", "s,I,p", 2, (int) M_BLTUL_I, INSN_MACRO },
179 {"bltz", "s,p", 0x04000000, 0xfc1f0000, CBD|RD_s },
180 {"bltzl", "s,p", 0x04020000, 0xfc1f0000, CBL|RD_s|I2 },
181 {"bltzal", "s,p", 0x04100000, 0xfc1f0000, CBD|RD_s|WR_31 },
182 {"bltzall", "s,p", 0x04120000, 0xfc1f0000, CBL|RD_s|I2 },
183 {"bnez", "s,p", 0x14000000, 0xfc1f0000, CBD|RD_s },
184 {"bnezl", "s,p", 0x54000000, 0xfc1f0000, CBL|RD_s|I2 },
185 {"bne", "s,t,p", 0x14000000, 0xfc000000, CBD|RD_s|RD_t },
186 {"bne", "s,I,p", 0, (int) M_BNE_I, INSN_MACRO },
187 {"bnel", "s,t,p", 0x54000000, 0xfc000000, CBL|RD_s|RD_t|I2},
188 {"bnel", "s,I,p", 2, (int) M_BNEL_I, INSN_MACRO },
189 {"break", "", 0x0000000d, 0xffffffff, TRAP },
190 {"break", "c", 0x0000000d, 0xfc00003f, TRAP },
191 {"c.f.d", "S,T", 0x46200030, 0xffe007ff, RD_S|RD_T|WR_CC },
192 {"c.f.d", "M,S,T", 0x46200030, 0xffe000ff, RD_S|RD_T|WR_CC|I4 },
193 {"c.f.s", "S,T", 0x46000030, 0xffe007ff, RD_S|RD_T|WR_CC },
194 {"c.f.s", "M,S,T", 0x46000030, 0xffe000ff, RD_S|RD_T|WR_CC|I4 },
195 {"c.un.d", "S,T", 0x46200031, 0xffe007ff, RD_S|RD_T|WR_CC },
196 {"c.un.d", "M,S,T", 0x46200031, 0xffe000ff, RD_S|RD_T|WR_CC|I4 },
197 {"c.un.s", "S,T", 0x46000031, 0xffe007ff, RD_S|RD_T|WR_CC },
198 {"c.un.s", "M,S,T", 0x46000031, 0xffe000ff, RD_S|RD_T|WR_CC|I4 },
199 {"c.eq.d", "S,T", 0x46200032, 0xffe007ff, RD_S|RD_T|WR_CC },
200 {"c.eq.d", "M,S,T", 0x46200032, 0xffe000ff, RD_S|RD_T|WR_CC|I4 },
201 {"c.eq.s", "S,T", 0x46000032, 0xffe007ff, RD_S|RD_T|WR_CC },
202 {"c.eq.s", "M,S,T", 0x46000032, 0xffe000ff, RD_S|RD_T|WR_CC|I4 },
203 {"c.ueq.d", "S,T", 0x46200033, 0xffe007ff, RD_S|RD_T|WR_CC },
204 {"c.ueq.d", "M,S,T", 0x46200033, 0xffe000ff, RD_S|RD_T|WR_CC|I4 },
205 {"c.ueq.s", "S,T", 0x46000033, 0xffe007ff, RD_S|RD_T|WR_CC },
206 {"c.ueq.s", "M,S,T", 0x46000033, 0xffe000ff, RD_S|RD_T|WR_CC|I4 },
207 {"c.olt.d", "S,T", 0x46200034, 0xffe007ff, RD_S|RD_T|WR_CC },
208 {"c.olt.d", "M,S,T", 0x46200034, 0xffe000ff, RD_S|RD_T|WR_CC|I4 },
209 {"c.olt.s", "S,T", 0x46000034, 0xffe007ff, RD_S|RD_T|WR_CC },
210 {"c.olt.s", "M,S,T", 0x46000034, 0xffe000ff, RD_S|RD_T|WR_CC|I4 },
211 {"c.ult.d", "S,T", 0x46200035, 0xffe007ff, RD_S|RD_T|WR_CC },
212 {"c.ult.d", "M,S,T", 0x46200035, 0xffe000ff, RD_S|RD_T|WR_CC|I4 },
213 {"c.ult.s", "S,T", 0x46000035, 0xffe007ff, RD_S|RD_T|WR_CC },
214 {"c.ult.s", "M,S,T", 0x46000035, 0xffe000ff, RD_S|RD_T|WR_CC|I4 },
215 {"c.ole.d", "S,T", 0x46200036, 0xffe007ff, RD_S|RD_T|WR_CC },
216 {"c.ole.d", "M,S,T", 0x46200036, 0xffe000ff, RD_S|RD_T|WR_CC|I4 },
217 {"c.ole.s", "S,T", 0x46000036, 0xffe007ff, RD_S|RD_T|WR_CC },
218 {"c.ole.s", "M,S,T", 0x46000036, 0xffe000ff, RD_S|RD_T|WR_CC|I4 },
219 {"c.ule.d", "S,T", 0x46200037, 0xffe007ff, RD_S|RD_T|WR_CC },
220 {"c.ule.d", "M,S,T", 0x46200037, 0xffe000ff, RD_S|RD_T|WR_CC|I4 },
221 {"c.ule.s", "S,T", 0x46000037, 0xffe007ff, RD_S|RD_T|WR_CC },
222 {"c.ule.s", "M,S,T", 0x46000037, 0xffe000ff, RD_S|RD_T|WR_CC|I4 },
223 {"c.sf.d", "S,T", 0x46200038, 0xffe007ff, RD_S|RD_T|WR_CC },
224 {"c.sf.d", "M,S,T", 0x46200038, 0xffe000ff, RD_S|RD_T|WR_CC|I4 },
225 {"c.sf.s", "S,T", 0x46000038, 0xffe007ff, RD_S|RD_T|WR_CC },
226 {"c.sf.s", "M,S,T", 0x46000038, 0xffe000ff, RD_S|RD_T|WR_CC|I4 },
227 {"c.ngle.d","S,T", 0x46200039, 0xffe007ff, RD_S|RD_T|WR_CC },
228 {"c.ngle.d","M,S,T", 0x46200039, 0xffe000ff, RD_S|RD_T|WR_CC|I4 },
229 {"c.ngle.s","S,T", 0x46000039, 0xffe007ff, RD_S|RD_T|WR_CC },
230 {"c.ngle.s","M,S,T", 0x46000039, 0xffe000ff, RD_S|RD_T|WR_CC|I4 },
231 {"c.seq.d", "S,T", 0x4620003a, 0xffe007ff, RD_S|RD_T|WR_CC },
232 {"c.seq.d", "M,S,T", 0x4620003a, 0xffe000ff, RD_S|RD_T|WR_CC|I4 },
233 {"c.seq.s", "S,T", 0x4600003a, 0xffe007ff, RD_S|RD_T|WR_CC },
234 {"c.seq.s", "M,S,T", 0x4600003a, 0xffe000ff, RD_S|RD_T|WR_CC|I4 },
235 {"c.ngl.d", "S,T", 0x4620003b, 0xffe007ff, RD_S|RD_T|WR_CC },
236 {"c.ngl.d", "M,S,T", 0x4620003b, 0xffe000ff, RD_S|RD_T|WR_CC|I4 },
237 {"c.ngl.s", "S,T", 0x4600003b, 0xffe007ff, RD_S|RD_T|WR_CC },
238 {"c.ngl.s", "M,S,T", 0x4600003b, 0xffe000ff, RD_S|RD_T|WR_CC|I4 },
239 {"c.lt.d", "S,T", 0x4620003c, 0xffe007ff, RD_S|RD_T|WR_CC },
240 {"c.lt.d", "M,S,T", 0x4620003c, 0xffe000ff, RD_S|RD_T|WR_CC|I4 },
241 {"c.lt.s", "S,T", 0x4600003c, 0xffe007ff, RD_S|RD_T|WR_CC },
242 {"c.lt.s", "M,S,T", 0x4600003c, 0xffe000ff, RD_S|RD_T|WR_CC|I4 },
243 {"c.nge.d", "S,T", 0x4620003d, 0xffe007ff, RD_S|RD_T|WR_CC },
244 {"c.nge.d", "M,S,T", 0x4620003d, 0xffe000ff, RD_S|RD_T|WR_CC|I4 },
245 {"c.nge.s", "S,T", 0x4600003d, 0xffe007ff, RD_S|RD_T|WR_CC },
246 {"c.nge.s", "M,S,T", 0x4600003d, 0xffe000ff, RD_S|RD_T|WR_CC|I4 },
247 {"c.le.d", "S,T", 0x4620003e, 0xffe007ff, RD_S|RD_T|WR_CC },
248 {"c.le.d", "M,S,T", 0x4620003e, 0xffe000ff, RD_S|RD_T|WR_CC|I4 },
249 {"c.le.s", "S,T", 0x4600003e, 0xffe007ff, RD_S|RD_T|WR_CC },
250 {"c.le.s", "M,S,T", 0x4600003e, 0xffe000ff, RD_S|RD_T|WR_CC|I4 },
251 {"c.ngt.d", "S,T", 0x4620003f, 0xffe007ff, RD_S|RD_T|WR_CC },
252 {"c.ngt.d", "M,S,T", 0x4620003f, 0xffe000ff, RD_S|RD_T|WR_CC|I4 },
253 {"c.ngt.s", "S,T", 0x4600003f, 0xffe007ff, RD_S|RD_T|WR_CC },
254 {"c.ngt.s", "M,S,T", 0x4600003f, 0xffe000ff, RD_S|RD_T|WR_CC|I4 },
255 {"cache", "k,o(b)", 0xbc000000, 0xfc000000, RD_b|I3 },
256 {"ceil.l.d", "D,S", 0x4620000a, 0xffff003f, WR_D|RD_S|I3 },
257 {"ceil.l.s", "D,S", 0x4600000a, 0xffff003f, WR_D|RD_S|I3 },
258 {"ceil.w.d", "D,S", 0x4620000e, 0xffff003f, WR_D|RD_S|I2 },
259 {"ceil.w.s", "D,S", 0x4600000e, 0xffff003f, WR_D|RD_S|I2 },
260 {"cfc0", "t,G", 0x40400000, 0xffe007ff, LCD|WR_t|RD_C0 },
261 {"cfc1", "t,G", 0x44400000, 0xffe007ff, LCD|WR_t|RD_C1 },
262 {"cfc1", "t,S", 0x44400000, 0xffe007ff, LCD|WR_t|RD_C1 },
263 {"cfc2", "t,G", 0x48400000, 0xffe007ff, LCD|WR_t|RD_C2 },
264 {"cfc3", "t,G", 0x4c400000, 0xffe007ff, LCD|WR_t|RD_C3 },
265 {"ctc0", "t,G", 0x40c00000, 0xffe007ff, COD|RD_t|WR_CC },
266 {"ctc1", "t,G", 0x44c00000, 0xffe007ff, COD|RD_t|WR_CC },
267 {"ctc1", "t,S", 0x44c00000, 0xffe007ff, COD|RD_t|WR_CC },
268 {"ctc2", "t,G", 0x48c00000, 0xffe007ff, COD|RD_t|WR_CC },
269 {"ctc3", "t,G", 0x4cc00000, 0xffe007ff, COD|RD_t|WR_CC },
270 {"cvt.d.l", "D,S", 0x46a00021, 0xffff003f, WR_D|RD_S|I3 },
271 {"cvt.d.s", "D,S", 0x46000021, 0xffff003f, WR_D|RD_S },
272 {"cvt.d.w", "D,S", 0x46800021, 0xffff003f, WR_D|RD_S },
273 {"cvt.l.d", "D,S", 0x46200025, 0xffff003f, WR_D|RD_S|I3 },
274 {"cvt.l.s", "D,S", 0x46000025, 0xffff003f, WR_D|RD_S|I3 },
275 {"cvt.s.l", "D,S", 0x46a00020, 0xffff003f, WR_D|RD_S|I3 },
276 {"cvt.s.d", "D,S", 0x46200020, 0xffff003f, WR_D|RD_S },
277 {"cvt.s.w", "D,S", 0x46800020, 0xffff003f, WR_D|RD_S },
278 {"cvt.w.d", "D,S", 0x46200024, 0xffff003f, WR_D|RD_S },
279 {"cvt.w.s", "D,S", 0x46000024, 0xffff003f, WR_D|RD_S },
280 {"dabs", "d,v", 3, (int) M_DABS, INSN_MACRO },
281 {"dadd", "d,v,t", 0x0000002c, 0xfc0007ff, WR_d|RD_s|RD_t|I3},
282 {"dadd", "t,r,I", 3, (int) M_DADD_I, INSN_MACRO },
283 {"daddi", "t,r,j", 0x60000000, 0xfc000000, WR_t|RD_s|I3 },
284 {"daddiu", "t,r,j", 0x64000000, 0xfc000000, WR_t|RD_s|I3 },
285 {"daddu", "d,v,t", 0x0000002d, 0xfc0007ff, WR_d|RD_s|RD_t|I3},
286 {"daddu", "t,r,I", 3, (int) M_DADDU_I, INSN_MACRO },
287 /* For ddiv, see the comments about div. */
288 {"ddiv", "z,s,t", 0x0000001e, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO|I3 },
289 {"ddiv", "d,v,t", 3, (int) M_DDIV_3, INSN_MACRO },
290 {"ddiv", "d,v,I", 3, (int) M_DDIV_3I, INSN_MACRO },
291 /* For ddivu, see the comments about div. */
292 {"ddivu", "z,s,t", 0x0000001f, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO|I3 },
293 {"ddivu", "d,v,t", 3, (int) M_DDIVU_3, INSN_MACRO },
294 {"ddivu", "d,v,I", 3, (int) M_DDIVU_3I, INSN_MACRO },
295 /* The MIPS assembler treats the div opcode with two operands as
296 though the first operand appeared twice (the first operand is both
297 a source and a destination). To get the div machine instruction,
298 you must use an explicit destination of $0. */
299 {"div", "z,s,t", 0x0000001a, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO },
300 {"div", "z,t", 0x0000001a, 0xffe0ffff, RD_s|RD_t|WR_HI|WR_LO },
301 {"div", "d,v,t", 0, (int) M_DIV_3, INSN_MACRO },
302 {"div", "d,v,I", 0, (int) M_DIV_3I, INSN_MACRO },
303 {"div.d", "D,V,T", 0x46200003, 0xffe0003f, WR_D|RD_S|RD_T },
304 {"div.s", "D,V,T", 0x46000003, 0xffe0003f, WR_D|RD_S|RD_T },
305 /* For divu, see the comments about div. */
306 {"divu", "z,s,t", 0x0000001b, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO },
307 {"divu", "z,t", 0x0000001b, 0xffe0ffff, RD_s|RD_t|WR_HI|WR_LO },
308 {"divu", "d,v,t", 0, (int) M_DIVU_3, INSN_MACRO },
309 {"divu", "d,v,I", 0, (int) M_DIVU_3I, INSN_MACRO },
310 {"dla", "t,A(b)", 3, (int) M_DLA_AB, INSN_MACRO },
311 {"dli", "t,j", 0x24000000, 0xffe00000, WR_t|I3 }, /* addiu */
312 {"dli", "t,i", 0x34000000, 0xffe00000, WR_t|I3 }, /* ori */
313 {"dli", "t,I", 3, (int) M_DLI, INSN_MACRO },
314 {"dmadd16", "s,t", 0x00000029, 0xfc00ffff, RD_s|RD_t|WR_LO|RD_LO|V1 },
315 {"dmfc0", "t,G", 0x40200000, 0xffe007ff, LCD|WR_t|RD_C0|I3 },
316 {"dmtc0", "t,G", 0x40a00000, 0xffe007ff, COD|RD_t|WR_C0|WR_CC|I3 },
317 {"dmfc1", "t,S", 0x44200000, 0xffe007ff, LCD|WR_t|RD_S|I3 },
318 {"dmtc1", "t,S", 0x44a00000, 0xffe007ff, COD|RD_t|WR_S|I3 },
319 {"dmul", "d,v,t", 3, (int) M_DMUL, INSN_MACRO },
320 {"dmul", "d,v,I", 3, (int) M_DMUL_I, INSN_MACRO },
321 {"dmulo", "d,v,t", 3, (int) M_DMULO, INSN_MACRO },
322 {"dmulo", "d,v,I", 3, (int) M_DMULO_I, INSN_MACRO },
323 {"dmulou", "d,v,t", 3, (int) M_DMULOU, INSN_MACRO },
324 {"dmulou", "d,v,I", 3, (int) M_DMULOU_I, INSN_MACRO },
325 {"dmult", "s,t", 0x0000001c, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO|I3 },
326 {"dmultu", "s,t", 0x0000001d, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO|I3 },
327 {"dneg", "d,w", 0x0000002e, 0xffe007ff, WR_d|RD_t|I3 }, /* dsub 0 */
328 {"dnegu", "d,w", 0x0000002f, 0xffe007ff, WR_d|RD_t|I3 }, /* dsubu 0*/
329 {"drem", "z,s,t", 0x0000001e, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO|I3 },
330 {"drem", "d,v,t", 3, (int) M_DREM_3, INSN_MACRO },
331 {"drem", "d,v,I", 3, (int) M_DREM_3I, INSN_MACRO },
332 {"dremu", "z,s,t", 0x0000001f, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO|I3 },
333 {"dremu", "d,v,t", 3, (int) M_DREMU_3, INSN_MACRO },
334 {"dremu", "d,v,I", 3, (int) M_DREMU_3I, INSN_MACRO },
335 {"dsllv", "d,t,s", 0x00000014, 0xfc0007ff, WR_d|RD_t|RD_s|I3},
336 {"dsll32", "d,w,<", 0x0000003c, 0xffe0003f, WR_d|RD_t|I3 },
337 {"dsll", "d,w,s", 0x00000014, 0xfc0007ff, WR_d|RD_t|RD_s|I3}, /* dsllv */
338 {"dsll", "d,w,>", 0x0000003c, 0xffe0003f, WR_d|RD_t|I3 }, /* dsll32 */
339 {"dsll", "d,w,<", 0x00000038, 0xffe0003f, WR_d|RD_t|I3 },
340 {"dsrav", "d,t,s", 0x00000017, 0xfc0007ff, WR_d|RD_t|RD_s|I3},
341 {"dsra32", "d,w,<", 0x0000003f, 0xffe0003f, WR_d|RD_t|I3 },
342 {"dsra", "d,w,s", 0x00000017, 0xfc0007ff, WR_d|RD_t|RD_s|I3}, /* dsrav */
343 {"dsra", "d,w,>", 0x0000003f, 0xffe0003f, WR_d|RD_t|I3 }, /* dsra32 */
344 {"dsra", "d,w,<", 0x0000003b, 0xffe0003f, WR_d|RD_t|I3 },
345 {"dsrlv", "d,t,s", 0x00000016, 0xfc0007ff, WR_d|RD_t|RD_s|I3},
346 {"dsrl32", "d,w,<", 0x0000003e, 0xffe0003f, WR_d|RD_t|I3 },
347 {"dsrl", "d,w,s", 0x00000016, 0xfc0007ff, WR_d|RD_t|RD_s|I3}, /* dsrlv */
348 {"dsrl", "d,w,>", 0x0000003e, 0xffe0003f, WR_d|RD_t|I3 }, /* dsrl32 */
349 {"dsrl", "d,w,<", 0x0000003a, 0xffe0003f, WR_d|RD_t|I3 },
350 {"dsub", "d,v,t", 0x0000002e, 0xfc0007ff, WR_d|RD_s|RD_t|I3},
351 {"dsub", "d,v,I", 3, (int) M_DSUB_I, INSN_MACRO },
352 {"dsubu", "d,v,t", 0x0000002f, 0xfc0007ff, WR_d|RD_s|RD_t|I3},
353 {"dsubu", "d,v,I", 3, (int) M_DSUBU_I, INSN_MACRO },
354 {"eret", "", 0x42000018, 0xffffffff, I3 },
355 {"floor.l.d", "D,S", 0x4620000b, 0xffff003f, WR_D|RD_S|I3 },
356 {"floor.l.s", "D,S", 0x4600000b, 0xffff003f, WR_D|RD_S|I3 },
357 {"floor.w.d", "D,S", 0x4620000f, 0xffff003f, WR_D|RD_S|I2 },
358 {"floor.w.s", "D,S", 0x4600000f, 0xffff003f, WR_D|RD_S|I2 },
359 {"flushi", "", 0xbc010000, 0xffffffff, L1 },
360 {"flushd", "", 0xbc020000, 0xffffffff, L1 },
361 {"flushid", "", 0xbc030000, 0xffffffff, L1 },
362 {"hibernate","", 0x42000023, 0xffffffff, V1 },
363 {"jr", "s", 0x00000008, 0xfc1fffff, UBD|RD_s },
364 {"j", "s", 0x00000008, 0xfc1fffff, UBD|RD_s }, /* jr */
365 /* SVR4 PIC code requires special handling for j, so it must be a
366 macro. */
367 {"j", "a", 0, (int) M_J_A, INSN_MACRO },
368 /* This form of j is used by the disassembler and internally by the
369 assembler, but will never match user input (because the line above
370 will match first). */
371 {"j", "a", 0x08000000, 0xfc000000, UBD },
372 {"jalr", "s", 0x0000f809, 0xfc1fffff, UBD|RD_s|WR_d },
373 {"jalr", "d,s", 0x00000009, 0xfc1f07ff, UBD|RD_s|WR_d },
374 /* SVR4 PIC code requires special handling for jal, so it must be a
375 macro. */
376 {"jal", "d,s", 0, (int) M_JAL_2, INSN_MACRO },
377 {"jal", "s", 0, (int) M_JAL_1, INSN_MACRO },
378 {"jal", "a", 0, (int) M_JAL_A, INSN_MACRO },
379 /* This form of jal is used by the disassembler and internally by the
380 assembler, but will never match user input (because the line above
381 will match first). */
382 {"jal", "a", 0x0c000000, 0xfc000000, UBD|WR_31 },
383 {"jalx", "a", 0x74000000, 0xfc000000, UBD|WR_31 },
384 {"la", "t,A(b)", 0, (int) M_LA_AB, INSN_MACRO },
385 {"lb", "t,o(b)", 0x80000000, 0xfc000000, LDD|RD_b|WR_t },
386 {"lb", "t,A(b)", 0, (int) M_LB_AB, INSN_MACRO },
387 {"lbu", "t,o(b)", 0x90000000, 0xfc000000, LDD|RD_b|WR_t },
388 {"lbu", "t,A(b)", 0, (int) M_LBU_AB, INSN_MACRO },
389 {"ld", "t,o(b)", 0xdc000000, 0xfc000000, WR_t|RD_b|I3 },
390 {"ld", "t,o(b)", 0, (int) M_LD_OB, INSN_MACRO },
391 {"ld", "t,A(b)", 0, (int) M_LD_AB, INSN_MACRO },
392 {"ldc1", "T,o(b)", 0xd4000000, 0xfc000000, CLD|RD_b|WR_T|I2},
393 {"ldc1", "E,o(b)", 0xd4000000, 0xfc000000, CLD|RD_b|WR_T|I2},
394 {"ldc1", "T,A(b)", 2, (int) M_LDC1_AB, INSN_MACRO },
395 {"ldc1", "E,A(b)", 2, (int) M_LDC1_AB, INSN_MACRO },
396 {"l.d", "T,o(b)", 0xd4000000, 0xfc000000, CLD|RD_b|WR_T|I2}, /* ldc1 */
397 {"l.d", "T,o(b)", 0, (int) M_L_DOB, INSN_MACRO },
398 {"l.d", "T,A(b)", 0, (int) M_L_DAB, INSN_MACRO },
399 {"ldc2", "E,o(b)", 0xd8000000, 0xfc000000, CLD|RD_b|WR_CC|I2},
400 {"ldc2", "E,A(b)", 2, (int) M_LDC2_AB, INSN_MACRO },
401 {"ldc3", "E,o(b)", 0xdc000000, 0xfc000000, CLD|RD_b|WR_CC|I2},
402 {"ldc3", "E,A(b)", 2, (int) M_LDC3_AB, INSN_MACRO },
403 {"ldl", "t,o(b)", 0x68000000, 0xfc000000, LDD|WR_t|RD_b|I3},
404 {"ldl", "t,A(b)", 3, (int) M_LDL_AB, INSN_MACRO },
405 {"ldr", "t,o(b)", 0x6c000000, 0xfc000000, LDD|WR_t|RD_b|I3},
406 {"ldr", "t,A(b)", 3, (int) M_LDR_AB, INSN_MACRO },
407 {"ldxc1", "D,t(b)", 0x4c000001, 0xfc00f83f, LDD|WR_D|RD_t|RD_b|I4 },
408 {"lh", "t,o(b)", 0x84000000, 0xfc000000, LDD|RD_b|WR_t },
409 {"lh", "t,A(b)", 0, (int) M_LH_AB, INSN_MACRO },
410 {"lhu", "t,o(b)", 0x94000000, 0xfc000000, LDD|RD_b|WR_t },
411 {"lhu", "t,A(b)", 0, (int) M_LHU_AB, INSN_MACRO },
412 /* li is at the start of the table. */
413 {"li.d", "t,F", 0, (int) M_LI_D, INSN_MACRO },
414 {"li.d", "T,L", 0, (int) M_LI_DD, INSN_MACRO },
415 {"li.s", "t,f", 0, (int) M_LI_S, INSN_MACRO },
416 {"li.s", "T,l", 0, (int) M_LI_SS, INSN_MACRO },
417 {"ll", "t,o(b)", 0xc0000000, 0xfc000000, LDD|RD_b|WR_t|I2},
418 {"ll", "t,A(b)", 2, (int) M_LL_AB, INSN_MACRO },
419 {"lld", "t,o(b)", 0xd0000000, 0xfc000000, LDD|RD_b|WR_t|I3},
420 {"lld", "t,A(b)", 3, (int) M_LLD_AB, INSN_MACRO },
421 {"lui", "t,u", 0x3c000000, 0xffe00000, WR_t },
422 {"lw", "t,o(b)", 0x8c000000, 0xfc000000, LDD|RD_b|WR_t },
423 {"lw", "t,A(b)", 0, (int) M_LW_AB, INSN_MACRO },
424 {"lwc0", "E,o(b)", 0xc0000000, 0xfc000000, CLD|RD_b|WR_CC },
425 {"lwc0", "E,A(b)", 0, (int) M_LWC0_AB, INSN_MACRO },
426 {"lwc1", "T,o(b)", 0xc4000000, 0xfc000000, CLD|RD_b|WR_T },
427 {"lwc1", "E,o(b)", 0xc4000000, 0xfc000000, CLD|RD_b|WR_T },
428 {"lwc1", "T,A(b)", 0, (int) M_LWC1_AB, INSN_MACRO },
429 {"lwc1", "E,A(b)", 0, (int) M_LWC1_AB, INSN_MACRO },
430 {"l.s", "T,o(b)", 0xc4000000, 0xfc000000, CLD|RD_b|WR_T }, /* lwc1 */
431 {"l.s", "T,A(b)", 0, (int) M_LWC1_AB, INSN_MACRO },
432 {"lwc2", "E,o(b)", 0xc8000000, 0xfc000000, CLD|RD_b|WR_CC },
433 {"lwc2", "E,A(b)", 0, (int) M_LWC2_AB, INSN_MACRO },
434 {"lwc3", "E,o(b)", 0xcc000000, 0xfc000000, CLD|RD_b|WR_CC },
435 {"lwc3", "E,A(b)", 0, (int) M_LWC3_AB, INSN_MACRO },
436 {"lwl", "t,o(b)", 0x88000000, 0xfc000000, LDD|RD_b|WR_t },
437 {"lwl", "t,A(b)", 0, (int) M_LWL_AB, INSN_MACRO },
438 {"lcache", "t,o(b)", 0x88000000, 0xfc000000, LDD|RD_b|WR_t|I2}, /* same */
439 {"lcache", "t,A(b)", 2, (int) M_LWL_AB, INSN_MACRO }, /* as lwl */
440 {"lwr", "t,o(b)", 0x98000000, 0xfc000000, LDD|RD_b|WR_t },
441 {"lwr", "t,A(b)", 0, (int) M_LWR_AB, INSN_MACRO },
442 {"flush", "t,o(b)", 0x98000000, 0xfc000000, LDD|RD_b|WR_t|I2}, /* same */
443 {"flush", "t,A(b)", 2, (int) M_LWR_AB, INSN_MACRO }, /* as lwr */
444 {"lwu", "t,o(b)", 0x9c000000, 0xfc000000, LDD|RD_b|WR_t|I3},
445 {"lwu", "t,A(b)", 3, (int) M_LWU_AB, INSN_MACRO },
446 {"lwxc1", "D,t(b)", 0x4c000000, 0xfc00f83f, LDD|WR_D|RD_t|RD_b|I4 },
447 {"mad", "s,t", 0x70000000, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO|RD_HI|RD_LO|P3},
448 {"madu", "s,t", 0x70000001, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO|RD_HI|RD_LO|P3},
449 {"addciu", "t,r,j", 0x70000000, 0xfc000000, WR_t|RD_s|L1 },
450 {"madd.d", "D,R,S,T", 0x4c000021, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|I4 },
451 {"madd.s", "D,R,S,T", 0x4c000020, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|I4 },
452 {"madd", "s,t", 0x0000001c, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO|L1 },
453 {"maddu", "s,t", 0x0000001d, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO|L1 },
454 {"madd16", "s,t", 0x00000028, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO|RD_HI|RD_LO|V1 },
455 {"mfc0", "t,G", 0x40000000, 0xffe007ff, LCD|WR_t|RD_C0 },
456 {"mfc1", "t,S", 0x44000000, 0xffe007ff, LCD|WR_t|RD_S },
457 {"mfc1", "t,G", 0x44000000, 0xffe007ff, LCD|WR_t|RD_S },
458 {"mfc2", "t,G", 0x48000000, 0xffe007ff, LCD|WR_t|RD_C2 },
459 {"mfc3", "t,G", 0x4c000000, 0xffe007ff, LCD|WR_t|RD_C3 },
460 {"mfhi", "d", 0x00000010, 0xffff07ff, WR_d|RD_HI },
461 {"mflo", "d", 0x00000012, 0xffff07ff, WR_d|RD_LO },
462 {"mov.d", "D,S", 0x46200006, 0xffff003f, WR_D|RD_S },
463 {"mov.s", "D,S", 0x46000006, 0xffff003f, WR_D|RD_S },
464 {"movf", "d,s,N", 0x00000001, 0xfc0307ff, WR_d|RD_s|RD_CC|I4 },
465 {"movf.d", "D,S,N", 0x46200011, 0xffe3003f, WR_D|RD_S|RD_CC|I4 },
466 {"movf.s", "D,S,N", 0x46000011, 0xffe3003f, WR_D|RD_S|RD_CC|I4 },
467 {"movn", "d,v,t", 0x0000000b, 0xfc0007ff, WR_d|RD_s|RD_t|I4 },
468 {"ffc", "d,v", 0x0000000b, 0xfc0007ff, WR_d|RD_s|L1 },
469 {"movn.d", "D,S,t", 0x46200013, 0xffe0003f, WR_D|RD_S|RD_t|I4 },
470 {"movn.s", "D,S,t", 0x46000013, 0xffe0003f, WR_D|RD_S|RD_t|I4 },
471 {"movt", "d,s,N", 0x00010001, 0xfc0307ff, WR_d|RD_s|RD_CC|I4 },
472 {"movt.d", "D,S,N", 0x46210011, 0xffe3003f, WR_D|RD_S|RD_CC|I4 },
473 {"movt.s", "D,S,N", 0x46010011, 0xffe3003f, WR_D|RD_S|RD_CC|I4 },
474 {"movz", "d,v,t", 0x0000000a, 0xfc0007ff, WR_d|RD_s|RD_t|I4 },
475 {"ffs", "d,v", 0x0000000a, 0xfc0007ff, WR_d|RD_s|L1 },
476 {"movz.d", "D,S,t", 0x46200012, 0xffe0003f, WR_D|RD_S|RD_t|I4 },
477 {"movz.s", "D,S,t", 0x46000012, 0xffe0003f, WR_D|RD_S|RD_t|I4 },
478 /* move is at the top of the table. */
479 {"msub.d", "D,R,S,T", 0x4c000029, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|I4 },
480 {"msub.s", "D,R,S,T", 0x4c000028, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|I4 },
481 {"msub", "s,t", 0x0000001e, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO|L1 },
482 {"msubu", "s,t", 0x0000001f, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO|L1 },
483 {"mtc0", "t,G", 0x40800000, 0xffe007ff, COD|RD_t|WR_C0|WR_CC },
484 {"mtc1", "t,S", 0x44800000, 0xffe007ff, COD|RD_t|WR_S },
485 {"mtc1", "t,G", 0x44800000, 0xffe007ff, COD|RD_t|WR_S },
486 {"mtc2", "t,G", 0x48800000, 0xffe007ff, COD|RD_t|WR_C2|WR_CC },
487 {"mtc3", "t,G", 0x4c800000, 0xffe007ff, COD|RD_t|WR_C3|WR_CC },
488 {"mthi", "s", 0x00000011, 0xfc1fffff, RD_s|WR_HI },
489 {"mtlo", "s", 0x00000013, 0xfc1fffff, RD_s|WR_LO },
490 {"mul.d", "D,V,T", 0x46200002, 0xffe0003f, WR_D|RD_S|RD_T },
491 {"mul.s", "D,V,T", 0x46000002, 0xffe0003f, WR_D|RD_S|RD_T },
492 {"mul", "d,v,t", 0x70000002, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HI|WR_LO|P3},
493 {"mul", "d,v,t", 0, (int) M_MUL, INSN_MACRO },
494 {"mul", "d,v,I", 0, (int) M_MUL_I, INSN_MACRO },
495 {"mulo", "d,v,t", 0, (int) M_MULO, INSN_MACRO },
496 {"mulo", "d,v,I", 0, (int) M_MULO_I, INSN_MACRO },
497 {"mulou", "d,v,t", 0, (int) M_MULOU, INSN_MACRO },
498 {"mulou", "d,v,I", 0, (int) M_MULOU_I, INSN_MACRO },
499 {"mult", "s,t", 0x00000018, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO },
500 {"multu", "s,t", 0x00000019, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO },
501 {"neg", "d,w", 0x00000022, 0xffe007ff, WR_d|RD_t }, /* sub 0 */
502 {"negu", "d,w", 0x00000023, 0xffe007ff, WR_d|RD_t }, /* subu 0 */
503 {"neg.d", "D,V", 0x46200007, 0xffff003f, WR_D|RD_S },
504 {"neg.s", "D,V", 0x46000007, 0xffff003f, WR_D|RD_S },
505 {"nmadd.d", "D,R,S,T", 0x4c000031, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|I4 },
506 {"nmadd.s", "D,R,S,T", 0x4c000030, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|I4 },
507 {"nmsub.d", "D,R,S,T", 0x4c000039, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|I4 },
508 {"nmsub.s", "D,R,S,T", 0x4c000038, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|I4 },
509 /* nop is at the start of the table. */
510 {"nor", "d,v,t", 0x00000027, 0xfc0007ff, WR_d|RD_s|RD_t },
511 {"nor", "t,r,I", 0, (int) M_NOR_I, INSN_MACRO },
512 {"not", "d,v", 0x00000027, 0xfc0007ff, WR_d|RD_s|RD_t },/*nor d,s,0*/
513 {"or", "d,v,t", 0x00000025, 0xfc0007ff, WR_d|RD_s|RD_t },
514 {"or", "t,r,I", 0, (int) M_OR_I, INSN_MACRO },
515 {"ori", "t,r,i", 0x34000000, 0xfc000000, WR_t|RD_s },
516 {"pref", "k,o(b)", 0xcc000000, 0xfc000000, RD_b|I4 },
517 {"prefx", "h,t(b)", 0x4c00000f, 0xfc0007ff, RD_b|RD_t|I4 },
518 {"recip.d", "D,S", 0x46200015, 0xffff003f, WR_D|RD_S|I4 },
519 {"recip.s", "D,S", 0x46000015, 0xffff003f, WR_D|RD_S|I4 },
520 {"rem", "z,s,t", 0x0000001a, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO },
521 {"rem", "d,v,t", 0, (int) M_REM_3, INSN_MACRO },
522 {"rem", "d,v,I", 0, (int) M_REM_3I, INSN_MACRO },
523 {"remu", "z,s,t", 0x0000001b, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO },
524 {"remu", "d,v,t", 0, (int) M_REMU_3, INSN_MACRO },
525 {"remu", "d,v,I", 0, (int) M_REMU_3I, INSN_MACRO },
526 {"rfe", "", 0x42000010, 0xffffffff, 0 },
527 {"rol", "d,v,t", 0, (int) M_ROL, INSN_MACRO },
528 {"rol", "d,v,I", 0, (int) M_ROL_I, INSN_MACRO },
529 {"ror", "d,v,t", 0, (int) M_ROR, INSN_MACRO },
530 {"ror", "d,v,I", 0, (int) M_ROR_I, INSN_MACRO },
531 {"round.l.d", "D,S", 0x46200008, 0xffff003f, WR_D|RD_S|I3 },
532 {"round.l.s", "D,S", 0x46000008, 0xffff003f, WR_D|RD_S|I3 },
533 {"round.w.d", "D,S", 0x4620000c, 0xffff003f, WR_D|RD_S|I2 },
534 {"round.w.s", "D,S", 0x4600000c, 0xffff003f, WR_D|RD_S|I2 },
535 {"rsqrt.d", "D,S", 0x46200016, 0xffff003f, WR_D|RD_S|I4 },
536 {"rsqrt.s", "D,S", 0x46000016, 0xffff003f, WR_D|RD_S|I4 },
537 {"sb", "t,o(b)", 0xa0000000, 0xfc000000, SM|RD_t|RD_b },
538 {"sb", "t,A(b)", 0, (int) M_SB_AB, INSN_MACRO },
539 {"sc", "t,o(b)", 0xe0000000, 0xfc000000, SM|RD_t|WR_t|RD_b|I2 },
540 {"sc", "t,A(b)", 2, (int) M_SC_AB, INSN_MACRO },
541 {"scd", "t,o(b)", 0xf0000000, 0xfc000000, SM|RD_t|WR_t|RD_b|I3 },
542 {"scd", "t,A(b)", 3, (int) M_SCD_AB, INSN_MACRO },
543 {"sd", "t,o(b)", 0xfc000000, 0xfc000000, SM|RD_t|RD_b|I3 },
544 {"sd", "t,o(b)", 0, (int) M_SD_OB, INSN_MACRO },
545 {"sd", "t,A(b)", 0, (int) M_SD_AB, INSN_MACRO },
546 {"sdc1", "T,o(b)", 0xf4000000, 0xfc000000, SM|RD_T|RD_b|I2 },
547 {"sdc1", "E,o(b)", 0xf4000000, 0xfc000000, SM|RD_T|RD_b|I2 },
548 {"sdc1", "T,A(b)", 2, (int) M_SDC1_AB, INSN_MACRO },
549 {"sdc1", "E,A(b)", 2, (int) M_SDC1_AB, INSN_MACRO },
550 {"sdc2", "E,o(b)", 0xf8000000, 0xfc000000, SM|RD_C2|RD_b|I2 },
551 {"sdc2", "E,A(b)", 2, (int) M_SDC2_AB, INSN_MACRO },
552 {"sdc3", "E,o(b)", 0xfc000000, 0xfc000000, SM|RD_C3|RD_b|I2 },
553 {"sdc3", "E,A(b)", 2, (int) M_SDC3_AB, INSN_MACRO },
554 {"s.d", "T,o(b)", 0xf4000000, 0xfc000000, SM|RD_T|RD_b|I2 },
555 {"s.d", "T,o(b)", 0, (int) M_S_DOB, INSN_MACRO },
556 {"s.d", "T,A(b)", 0, (int) M_S_DAB, INSN_MACRO },
557 {"sdl", "t,o(b)", 0xb0000000, 0xfc000000, SM|RD_t|RD_b|I3 },
558 {"sdl", "t,A(b)", 3, (int) M_SDL_AB, INSN_MACRO },
559 {"sdr", "t,o(b)", 0xb4000000, 0xfc000000, SM|RD_t|RD_b|I3 },
560 {"sdr", "t,A(b)", 3, (int) M_SDR_AB, INSN_MACRO },
561 {"sdxc1", "S,t(b)", 0x4c000009, 0xfc0007ff, SM|RD_S|RD_t|RD_b|I4 },
562 {"selsl", "d,v,t", 0x00000005, 0xfc0007ff, WR_d|RD_s|RD_t|L1 },
563 {"selsr", "d,v,t", 0x00000001, 0xfc0007ff, WR_d|RD_s|RD_t|L1 },
564 {"seq", "d,v,t", 0, (int) M_SEQ, INSN_MACRO },
565 {"seq", "d,v,I", 0, (int) M_SEQ_I, INSN_MACRO },
566 {"sge", "d,v,t", 0, (int) M_SGE, INSN_MACRO },
567 {"sge", "d,v,I", 0, (int) M_SGE_I, INSN_MACRO },
568 {"sgeu", "d,v,t", 0, (int) M_SGEU, INSN_MACRO },
569 {"sgeu", "d,v,I", 0, (int) M_SGEU_I, INSN_MACRO },
570 {"sgt", "d,v,t", 0, (int) M_SGT, INSN_MACRO },
571 {"sgt", "d,v,I", 0, (int) M_SGT_I, INSN_MACRO },
572 {"sgtu", "d,v,t", 0, (int) M_SGTU, INSN_MACRO },
573 {"sgtu", "d,v,I", 0, (int) M_SGTU_I, INSN_MACRO },
574 {"sh", "t,o(b)", 0xa4000000, 0xfc000000, SM|RD_t|RD_b },
575 {"sh", "t,A(b)", 0, (int) M_SH_AB, INSN_MACRO },
576 {"sle", "d,v,t", 0, (int) M_SLE, INSN_MACRO },
577 {"sle", "d,v,I", 0, (int) M_SLE_I, INSN_MACRO },
578 {"sleu", "d,v,t", 0, (int) M_SLEU, INSN_MACRO },
579 {"sleu", "d,v,I", 0, (int) M_SLEU_I, INSN_MACRO },
580 {"sllv", "d,t,s", 0x00000004, 0xfc0007ff, WR_d|RD_t|RD_s },
581 {"sll", "d,w,s", 0x00000004, 0xfc0007ff, WR_d|RD_t|RD_s }, /* sllv */
582 {"sll", "d,w,<", 0x00000000, 0xffe0003f, WR_d|RD_t },
583 {"slt", "d,v,t", 0x0000002a, 0xfc0007ff, WR_d|RD_s|RD_t },
584 {"slt", "d,v,I", 0, (int) M_SLT_I, INSN_MACRO },
585 {"slti", "t,r,j", 0x28000000, 0xfc000000, WR_t|RD_s },
586 {"sltiu", "t,r,j", 0x2c000000, 0xfc000000, WR_t|RD_s },
587 {"sltu", "d,v,t", 0x0000002b, 0xfc0007ff, WR_d|RD_s|RD_t },
588 {"sltu", "d,v,I", 0, (int) M_SLTU_I, INSN_MACRO },
589 {"sne", "d,v,t", 0, (int) M_SNE, INSN_MACRO },
590 {"sne", "d,v,I", 0, (int) M_SNE_I, INSN_MACRO },
591 {"sqrt.d", "D,S", 0x46200004, 0xffff003f, WR_D|RD_S|I2 },
592 {"sqrt.s", "D,S", 0x46000004, 0xffff003f, WR_D|RD_S|I2 },
593 {"srav", "d,t,s", 0x00000007, 0xfc0007ff, WR_d|RD_t|RD_s },
594 {"sra", "d,w,s", 0x00000007, 0xfc0007ff, WR_d|RD_t|RD_s }, /* srav */
595 {"sra", "d,w,<", 0x00000003, 0xffe0003f, WR_d|RD_t },
596 {"srlv", "d,t,s", 0x00000006, 0xfc0007ff, WR_d|RD_t|RD_s },
597 {"srl", "d,w,s", 0x00000006, 0xfc0007ff, WR_d|RD_t|RD_s }, /* srlv */
598 {"srl", "d,w,<", 0x00000002, 0xffe0003f, WR_d|RD_t },
599 {"standby", "", 0x42000021, 0xffffffff, V1 },
600 {"sub", "d,v,t", 0x00000022, 0xfc0007ff, WR_d|RD_s|RD_t },
601 {"sub", "d,v,I", 0, (int) M_SUB_I, INSN_MACRO },
602 {"sub.d", "D,V,T", 0x46200001, 0xffe0003f, WR_D|RD_S|RD_T },
603 {"sub.s", "D,V,T", 0x46000001, 0xffe0003f, WR_D|RD_S|RD_T },
604 {"subu", "d,v,t", 0x00000023, 0xfc0007ff, WR_d|RD_s|RD_t },
605 {"subu", "d,v,I", 0, (int) M_SUBU_I, INSN_MACRO },
606 {"suspend", "", 0x42000022, 0xffffffff, V1 },
607 {"sw", "t,o(b)", 0xac000000, 0xfc000000, SM|RD_t|RD_b },
608 {"sw", "t,A(b)", 0, (int) M_SW_AB, INSN_MACRO },
609 {"swc0", "E,o(b)", 0xe0000000, 0xfc000000, SM|RD_C0|RD_b },
610 {"swc0", "E,A(b)", 0, (int) M_SWC0_AB, INSN_MACRO },
611 {"swc1", "T,o(b)", 0xe4000000, 0xfc000000, SM|RD_T|RD_b },
612 {"swc1", "E,o(b)", 0xe4000000, 0xfc000000, SM|RD_T|RD_b },
613 {"swc1", "T,A(b)", 0, (int) M_SWC1_AB, INSN_MACRO },
614 {"swc1", "E,A(b)", 0, (int) M_SWC1_AB, INSN_MACRO },
615 {"s.s", "T,o(b)", 0xe4000000, 0xfc000000, SM|RD_T|RD_b }, /* swc1 */
616 {"s.s", "T,A(b)", 0, (int) M_SWC1_AB, INSN_MACRO },
617 {"swc2", "E,o(b)", 0xe8000000, 0xfc000000, SM|RD_C2|RD_b },
618 {"swc2", "E,A(b)", 0, (int) M_SWC2_AB, INSN_MACRO },
619 {"swc3", "E,o(b)", 0xec000000, 0xfc000000, SM|RD_C3|RD_b },
620 {"swc3", "E,A(b)", 0, (int) M_SWC3_AB, INSN_MACRO },
621 {"swl", "t,o(b)", 0xa8000000, 0xfc000000, SM|RD_t|RD_b },
622 {"swl", "t,A(b)", 0, (int) M_SWL_AB, INSN_MACRO },
623 {"scache", "t,o(b)", 0xa8000000, 0xfc000000, RD_t|RD_b|I2 }, /* same */
624 {"scache", "t,A(b)", 2, (int) M_SWL_AB, INSN_MACRO }, /* as swl */
625 {"swr", "t,o(b)", 0xb8000000, 0xfc000000, SM|RD_t|RD_b },
626 {"swr", "t,A(b)", 0, (int) M_SWR_AB, INSN_MACRO },
627 {"invalidate", "t,o(b)",0xb8000000, 0xfc000000, RD_t|RD_b|I2 }, /* same */
628 {"invalidate", "t,A(b)",2, (int) M_SWR_AB, INSN_MACRO }, /* as swr */
629 {"swxc1", "S,t(b)", 0x4c000008, 0xfc0007ff, SM|RD_S|RD_t|RD_b|I4 },
630 {"sync", "", 0x0000000f, 0xffffffff, I2 },
631 {"syscall", "", 0x0000000c, 0xffffffff, TRAP },
632 {"syscall", "B", 0x0000000c, 0xfc00003f, TRAP },
633 {"teqi", "s,j", 0x040c0000, 0xfc1f0000, RD_s|I2|TRAP },
634 {"teq", "s,t", 0x00000034, 0xfc00003f, RD_s|RD_t|I2|TRAP },
635 {"teq", "s,j", 0x040c0000, 0xfc1f0000, RD_s|I2|TRAP }, /* teqi */
636 {"teq", "s,I", 2, (int) M_TEQ_I, INSN_MACRO },
637 {"tgei", "s,j", 0x04080000, 0xfc1f0000, RD_s|I2|TRAP },
638 {"tge", "s,t", 0x00000030, 0xfc00003f, RD_s|RD_t|I2|TRAP },
639 {"tge", "s,j", 0x04080000, 0xfc1f0000, RD_s|I2|TRAP }, /* tgei */
640 {"tge", "s,I", 2, (int) M_TGE_I, INSN_MACRO },
641 {"tgeiu", "s,j", 0x04090000, 0xfc1f0000, RD_s|I2|TRAP },
642 {"tgeu", "s,t", 0x00000031, 0xfc00003f, RD_s|RD_t|I2|TRAP },
643 {"tgeu", "s,j", 0x04090000, 0xfc1f0000, RD_s|I2|TRAP }, /* tgeiu */
644 {"tgeu", "s,I", 2, (int) M_TGEU_I, INSN_MACRO },
645 {"tlbp", "", 0x42000008, 0xffffffff, INSN_TLB },
646 {"tlbr", "", 0x42000001, 0xffffffff, INSN_TLB },
647 {"tlbwi", "", 0x42000002, 0xffffffff, INSN_TLB },
648 {"tlbwr", "", 0x42000006, 0xffffffff, INSN_TLB },
649 {"tlti", "s,j", 0x040a0000, 0xfc1f0000, RD_s|I2|TRAP },
650 {"tlt", "s,t", 0x00000032, 0xfc00003f, RD_s|RD_t|I2|TRAP },
651 {"tlt", "s,j", 0x040a0000, 0xfc1f0000, RD_s|I2|TRAP }, /* tlti */
652 {"tlt", "s,I", 2, (int) M_TLT_I, INSN_MACRO },
653 {"tltiu", "s,j", 0x040b0000, 0xfc1f0000, RD_s|I2|TRAP },
654 {"tltu", "s,t", 0x00000033, 0xfc00003f, RD_s|RD_t|I2|TRAP },
655 {"tltu", "s,j", 0x040b0000, 0xfc1f0000, RD_s|I2|TRAP }, /* tltiu */
656 {"tltu", "s,I", 2, (int) M_TLTU_I, INSN_MACRO },
657 {"tnei", "s,j", 0x040e0000, 0xfc1f0000, RD_s|I2|TRAP },
658 {"tne", "s,t", 0x00000036, 0xfc00003f, RD_s|RD_t|I2|TRAP },
659 {"tne", "s,j", 0x040e0000, 0xfc1f0000, RD_s|I2|TRAP }, /* tnei */
660 {"tne", "s,I", 2, (int) M_TNE_I, INSN_MACRO },
661 {"trunc.l.d", "D,S", 0x46200009, 0xffff003f, WR_D|RD_S|I3 },
662 {"trunc.l.s", "D,S", 0x46000009, 0xffff003f, WR_D|RD_S|I3 },
663 {"trunc.w.d", "D,S", 0x4620000d, 0xffff003f, WR_D|RD_S|I2 },
664 {"trunc.w.d", "D,S,x", 0x4620000d, 0xffff003f, WR_D|RD_S|I2 },
665 {"trunc.w.d", "D,S,t", 0, (int) M_TRUNCWD, INSN_MACRO },
666 {"trunc.w.s", "D,S", 0x4600000d, 0xffff003f, WR_D|RD_S|I2 },
667 {"trunc.w.s", "D,S,x", 0x4600000d, 0xffff003f, WR_D|RD_S|I2 },
668 {"trunc.w.s", "D,S,t", 0, (int) M_TRUNCWS, INSN_MACRO },
669 {"uld", "t,o(b)", 3, (int) M_ULD, INSN_MACRO },
670 {"uld", "t,A(b)", 3, (int) M_ULD_A, INSN_MACRO },
671 {"ulh", "t,o(b)", 0, (int) M_ULH, INSN_MACRO },
672 {"ulh", "t,A(b)", 0, (int) M_ULH_A, INSN_MACRO },
673 {"ulhu", "t,o(b)", 0, (int) M_ULHU, INSN_MACRO },
674 {"ulhu", "t,A(b)", 0, (int) M_ULHU_A, INSN_MACRO },
675 {"ulw", "t,o(b)", 0, (int) M_ULW, INSN_MACRO },
676 {"ulw", "t,A(b)", 0, (int) M_ULW_A, INSN_MACRO },
677 {"usd", "t,o(b)", 3, (int) M_USD, INSN_MACRO },
678 {"usd", "t,A(b)", 3, (int) M_USD_A, INSN_MACRO },
679 {"ush", "t,o(b)", 0, (int) M_USH, INSN_MACRO },
680 {"ush", "t,A(b)", 0, (int) M_USH_A, INSN_MACRO },
681 {"usw", "t,o(b)", 0, (int) M_USW, INSN_MACRO },
682 {"usw", "t,A(b)", 0, (int) M_USW_A, INSN_MACRO },
683 {"xor", "d,v,t", 0x00000026, 0xfc0007ff, WR_d|RD_s|RD_t },
684 {"xor", "t,r,I", 0, (int) M_XOR_I, INSN_MACRO },
685 {"xori", "t,r,i", 0x38000000, 0xfc000000, WR_t|RD_s },
686 {"waiti", "", 0x42000020, 0xffffffff, TRAP|L1 },
687 {"wb", "o(b)", 0xbc040000, 0xfc1f0000, SM|RD_b|L1 },
688 /* No hazard protection on coprocessor instructions--they shouldn't
689 change the state of the processor and if they do it's up to the
690 user to put in nops as necessary. These are at the end so that the
691 disasembler recognizes more specific versions first. */
692 {"c0", "C", 0x42000000, 0xfe000000, 0 },
693 {"c1", "C", 0x46000000, 0xfe000000, 0 },
694 {"c2", "C", 0x4a000000, 0xfe000000, 0 },
695 {"c3", "C", 0x4e000000, 0xfe000000, 0 },
696 };
697
698 const int bfd_mips_num_opcodes =
699 ((sizeof mips_opcodes) / (sizeof (mips_opcodes[0])));
GDB Binutils - Deliverables
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