opcodes/mips-opc.c

   1 /* mips.h.  Mips opcode list for GDB, the GNU debugger.
   2    Copyright 1993 Free Software Foundation, Inc.
   3    Contributed by Ralph Campbell and OSF
   4    Commented and modified by Ian Lance Taylor, Cygnus Support
   5
   6 This file is part of GDB, GAS, and the GNU binutils.
   7
   8 GDB, GAS, and the GNU binutils are free software; you can redistribute
   9 them and/or modify them under the terms of the GNU General Public
  10 License as published by the Free Software Foundation; either version
  11 1, or (at your option) any later version.
  12
  13 GDB, GAS, and the GNU binutils are distributed in the hope that they
  14 will be useful, but WITHOUT ANY WARRANTY; without even the implied
  15 warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See
  16 the GNU General Public License for more details.
  17
  18 You should have received a copy of the GNU General Public License
  19 along with this file; see the file COPYING.  If not, write to the Free
  20 Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.  */
  21
  22 #include <stdio.h>
  23 #include "ansidecl.h"
  24 #include "opcode/mips.h"
  25
  26 /* Short hand so the lines aren't too long.  */
  27
  28 #define LDD     INSN_LOAD_DELAY
  29 #define UBD     INSN_UNCOND_BRANCH_DELAY
  30 #define CBD     INSN_COND_BRANCH_DELAY
  31 #define COD     INSN_COPROC_DELAY
  32
  33 #define WR_d    INSN_WRITE_GPR_D
  34 #define WR_t    INSN_WRITE_GPR_T
  35 #define WR_31   INSN_WRITE_GPR_31
  36 #define WR_D    INSN_WRITE_FPR_D
  37 #define WR_T    INSN_WRITE_FPR_T
  38 #define RD_s    INSN_READ_GPR_S
  39 #define RD_b    INSN_READ_GPR_S
  40 #define RD_t    INSN_READ_GPR_T
  41 #define RD_S    INSN_READ_FPR_S
  42 #define RD_T    INSN_READ_FPR_T
  43 #define WR_CC   INSN_WRITE_COND_CODE
  44 #define RD_CC   INSN_READ_COND_CODE
  45 #define RD_C0   INSN_COP
  46 #define RD_C1   INSN_COP
  47 #define RD_C2   INSN_COP
  48 #define RD_C3   INSN_COP
  49 #define WR_C0   INSN_COP
  50 #define WR_C1   INSN_COP
  51 #define WR_C2   INSN_COP
  52 #define WR_C3   INSN_COP
  53 #define WR_HI   INSN_WRITE_HI
  54 #define WR_LO   INSN_WRITE_LO
  55 #define RD_HI   INSN_READ_HI
  56 #define RD_LO   INSN_READ_LO
  57
  58 /* The order of overloaded instructions matters.  Label arguments and
  59    register arguments look the same. Instructions that can have either
  60    for arguments must apear in the correct order in this table for the
  61    assembler to pick the right one. In other words, entries with
  62    immediate operands must apear after the same instruction with
  63    registers.
  64
  65    Many instructions are short hand for other instructions (i.e., The
  66    jal <register> instruction is short for jalr <register>).  */
  67
  68 const struct mips_opcode mips_opcodes[] = {
  69 /* These instructions appear first so that the disassembler will find
  70    them first.  The assemblers uses a hash table based on the
  71    instruction name anyhow.  */
  72 {"nop",     "",         0x00000000, 0xffffffff, 0               },
  73 {"li",      "t,j",      0x24000000, 0xffe00000, WR_t            }, /* addiu */
  74 {"li",      "t,i",      0x34000000, 0xffe00000, WR_t            }, /* ori */
  75 {"li",      "t,I",      0,    (int) M_LI,       INSN_MACRO      },
  76 {"move",    "d,s",      0x00000021, 0xfc1f07ff, WR_d|RD_s       }, /* addu */
  77 {"b",       "p",        0x10000000, 0xffff0000, UBD             }, /* beq 0,0 */
  78 {"b",       "p",        0x40100000, 0xffff0000, UBD             }, /* bgez 0 */
  79 {"bal",     "p",        0x04110000, 0xffff0000, UBD             }, /* bgezal 0 */
  80
  81 {"abs",     "d,v",      0,    (int) M_ABS,      INSN_MACRO      },
  82 {"abs.s",   "D,V",      0x46000005, 0xffff003f, WR_D|RD_S       },
  83 {"abs.d",   "D,V",      0x46200005, 0xffff003f, WR_D|RD_S       },
  84 {"absu",    "d,s",      0,    (int) M_ABSU,     INSN_MACRO      },
  85 {"add",     "d,v,t",    0x00000020, 0xfc0007ff, WR_d|RD_s|RD_t  },
  86 {"add",     "t,r,I",    0,    (int) M_ADD_I,    INSN_MACRO      },
  87 {"add.s",   "D,V,T",    0x46000000, 0xffe0003f, WR_D|RD_S|RD_T  },
  88 {"add.d",   "D,V,T",    0x46200000, 0xffe0003f, WR_D|RD_S|RD_T  },
  89 {"addi",    "t,r,j",    0x20000000, 0xfc000000, WR_t|RD_s       },
  90 {"addiu",   "t,r,j",    0x24000000, 0xfc000000, WR_t|RD_s       },
  91 {"addu",    "d,v,t",    0x00000021, 0xfc0007ff, WR_d|RD_s|RD_t  },
  92 {"addu",    "t,r,I",    0,    (int) M_ADDU_I,   INSN_MACRO      },
  93 {"and",     "d,v,t",    0x00000024, 0xfc0007ff, WR_d|RD_s|RD_t  },
  94 {"and",     "t,r,I",    0,    (int) M_AND_I,    INSN_MACRO      },
  95 {"andi",    "t,r,i",    0x30000000, 0xfc000000, WR_t|RD_s       },
  96 /* b is at the top of the table.  */
  97 /* bal is at the top of the table.  */
  98 {"bc0f",    "p",        0x41000000, 0xffff0000, CBD|RD_CC       },
  99 {"bc1f",    "p",        0x45000000, 0xffff0000, CBD|RD_CC       },
 100 {"bc2f",    "p",        0x49000000, 0xffff0000, CBD|RD_CC       },
 101 {"bc3f",    "p",        0x4d000000, 0xffff0000, CBD|RD_CC       },
 102 {"bc0t",    "p",        0x41010000, 0xffff0000, CBD|RD_CC       },
 103 {"bc1t",    "p",        0x45010000, 0xffff0000, CBD|RD_CC       },
 104 {"bc2t",    "p",        0x49010000, 0xffff0000, CBD|RD_CC       },
 105 {"bc3t",    "p",        0x4d010000, 0xffff0000, CBD|RD_CC       },
 106 {"beq",     "s,t,p",    0x10000000, 0xfc000000, CBD|RD_s|RD_t   },
 107 {"beq",     "s,I,p",    0,    (int) M_BEQ_I,    INSN_MACRO      },
 108 {"beqz",    "s,p",      0x10000000, 0xfc1f0000, CBD|RD_s        },
 109 {"bge",     "s,t,p",    0,    (int) M_BGE,      INSN_MACRO      },
 110 {"bge",     "s,I,p",    0,    (int) M_BGE_I,    INSN_MACRO      },
 111 {"bgeu",    "s,t,p",    0,    (int) M_BGEU,     INSN_MACRO      },
 112 {"bgeu",    "s,I,p",    0,    (int) M_BGEU_I,   INSN_MACRO      },
 113 {"bgez",    "s,p",      0x04010000, 0xfc1f0000, CBD|RD_s        },
 114 {"bgezal",  "s,p",      0x04110000, 0xfc1f0000, CBD|RD_s        },
 115 {"bgt",     "s,t,p",    0,    (int) M_BGT,      INSN_MACRO      },
 116 {"bgt",     "s,I,p",    0,    (int) M_BGT_I,    INSN_MACRO      },
 117 {"bgtu",    "s,t,p",    0,    (int) M_BGTU,     INSN_MACRO      },
 118 {"bgtu",    "s,I,p",    0,    (int) M_BGTU_I,   INSN_MACRO      },
 119 {"bgtz",    "s,p",      0x1c000000, 0xfc1f0000, CBD|RD_s        },
 120 {"ble",     "s,t,p",    0,    (int) M_BLE,      INSN_MACRO      },
 121 {"ble",     "s,I,p",    0,    (int) M_BLE_I,    INSN_MACRO      },
 122 {"bleu",    "s,t,p",    0,    (int) M_BLEU,     INSN_MACRO      },
 123 {"bleu",    "s,I,p",    0,    (int) M_BLEU_I,   INSN_MACRO      },
 124 {"blez",    "s,p",      0x18000000, 0xfc1f0000, CBD|RD_s        },
 125 {"blt",     "s,t,p",    0,    (int) M_BLT,      INSN_MACRO      },
 126 {"blt",     "s,I,p",    0,    (int) M_BLT_I,    INSN_MACRO      },
 127 {"bltu",    "s,t,p",    0,    (int) M_BLTU,     INSN_MACRO      },
 128 {"bltu",    "s,I,p",    0,    (int) M_BLTU_I,   INSN_MACRO      },
 129 {"bltz",    "s,p",      0x04000000, 0xfc1f0000, CBD|RD_s        },
 130 {"bltzal",  "s,p",      0x04100000, 0xfc1f0000, CBD|RD_s        },
 131 {"bne",     "s,t,p",    0x14000000, 0xfc000000, CBD|RD_s|RD_t   },
 132 {"bne",     "s,I,p",    0,    (int) M_BNE_I,    INSN_MACRO      },
 133 {"bnez",    "s,p",      0x14000000, 0xfc1f0000, CBD|RD_s        },
 134 {"break",   "",         0x0000000d, 0xffffffff, INSN_TRAP       },
 135 {"break",   "c",        0x0000000d, 0xfc00003f, INSN_TRAP       },
 136 {"c.f.d",   "S,T",      0x46200030, 0xffe007ff, RD_S|RD_T|WR_CC },
 137 {"c.f.s",   "S,T",      0x46000030, 0xffe007ff, RD_S|RD_T|WR_CC },
 138 {"c.un.d",  "S,T",      0x46200031, 0xffe007ff, RD_S|RD_T|WR_CC },
 139 {"c.un.s",  "S,T",      0x46000031, 0xffe007ff, RD_S|RD_T|WR_CC },
 140 {"c.eq.d",  "S,T",      0x46200032, 0xffe007ff, RD_S|RD_T|WR_CC },
 141 {"c.eq.s",  "S,T",      0x46000032, 0xffe007ff, RD_S|RD_T|WR_CC },
 142 {"c.ueq.d", "S,T",      0x46200033, 0xffe007ff, RD_S|RD_T|WR_CC },
 143 {"c.ueq.s", "S,T",      0x46000033, 0xffe007ff, RD_S|RD_T|WR_CC },
 144 {"c.olt.d", "S,T",      0x46200034, 0xffe007ff, RD_S|RD_T|WR_CC },
 145 {"c.olt.s", "S,T",      0x46000034, 0xffe007ff, RD_S|RD_T|WR_CC },
 146 {"c.ult.d", "S,T",      0x46200035, 0xffe007ff, RD_S|RD_T|WR_CC },
 147 {"c.ult.s", "S,T",      0x46000035, 0xffe007ff, RD_S|RD_T|WR_CC },
 148 {"c.ole.d", "S,T",      0x46200036, 0xffe007ff, RD_S|RD_T|WR_CC },
 149 {"c.ole.s", "S,T",      0x46000036, 0xffe007ff, RD_S|RD_T|WR_CC },
 150 {"c.ule.d", "S,T",      0x46200037, 0xffe007ff, RD_S|RD_T|WR_CC },
 151 {"c.ule.s", "S,T",      0x46000037, 0xffe007ff, RD_S|RD_T|WR_CC },
 152 {"c.sf.d",  "S,T",      0x46200038, 0xffe007ff, RD_S|RD_T|WR_CC },
 153 {"c.sf.s",  "S,T",      0x46000038, 0xffe007ff, RD_S|RD_T|WR_CC },
 154 {"c.ngle.d","S,T",      0x46200039, 0xffe007ff, RD_S|RD_T|WR_CC },
 155 {"c.ngle.s","S,T",      0x46000039, 0xffe007ff, RD_S|RD_T|WR_CC },
 156 {"c.seq.d", "S,T",      0x4620003a, 0xffe007ff, RD_S|RD_T|WR_CC },
 157 {"c.seq.s", "S,T",      0x4600003a, 0xffe007ff, RD_S|RD_T|WR_CC },
 158 {"c.ngl.d", "S,T",      0x4620003b, 0xffe007ff, RD_S|RD_T|WR_CC },
 159 {"c.ngl.s", "S,T",      0x4600003b, 0xffe007ff, RD_S|RD_T|WR_CC },
 160 {"c.lt.d",  "S,T",      0x4620003c, 0xffe007ff, RD_S|RD_T|WR_CC },
 161 {"c.lt.s",  "S,T",      0x4600003c, 0xffe007ff, RD_S|RD_T|WR_CC },
 162 {"c.nge.d", "S,T",      0x4620003d, 0xffe007ff, RD_S|RD_T|WR_CC },
 163 {"c.nge.s", "S,T",      0x4600003d, 0xffe007ff, RD_S|RD_T|WR_CC },
 164 {"c.le.d",  "S,T",      0x4620003e, 0xffe007ff, RD_S|RD_T|WR_CC },
 165 {"c.le.s",  "S,T",      0x4600003e, 0xffe007ff, RD_S|RD_T|WR_CC },
 166 {"c.ngt.d", "S,T",      0x4620003f, 0xffe007ff, RD_S|RD_T|WR_CC },
 167 {"c.ngt.s", "S,T",      0x4600003f, 0xffe007ff, RD_S|RD_T|WR_CC },
 168 {"cfc0",    "t,G",      0x40400000, 0xffe007ff, LDD|WR_t|RD_C0  },
 169 {"cfc1",    "t,G",      0x44400000, 0xffe007ff, LDD|WR_t|RD_C1  },
 170 {"cfc1",    "t,S",      0x44400000, 0xffe007ff, LDD|WR_t|RD_C1  },
 171 {"cfc2",    "t,G",      0x48400000, 0xffe007ff, LDD|WR_t|RD_C2  },
 172 {"cfc3",    "t,G",      0x4c400000, 0xffe007ff, LDD|WR_t|RD_C3  },
 173 {"ctc0",    "t,G",      0x40c00000, 0xffe007ff, COD|RD_t|WR_CC  },
 174 {"ctc1",    "t,G",      0x44c00000, 0xffe007ff, COD|RD_t|WR_CC  },
 175 {"ctc1",    "t,S",      0x44c00000, 0xffe007ff, COD|RD_t|WR_CC  },
 176 {"ctc2",    "t,G",      0x48c00000, 0xffe007ff, COD|RD_t|WR_CC  },
 177 {"ctc3",    "t,G",      0x4cc00000, 0xffe007ff, COD|RD_t|WR_CC  },
 178 {"cvt.d.s", "D,S",      0x46000021, 0xffff003f, WR_D|RD_S       },
 179 {"cvt.d.w", "D,S",      0x46800021, 0xffff003f, WR_D|RD_S       },
 180 {"cvt.s.d", "D,S",      0x46200020, 0xffff003f, WR_D|RD_S       },
 181 {"cvt.s.w", "D,S",      0x46800020, 0xffff003f, WR_D|RD_S       },
 182 {"cvt.w.d", "D,S",      0x46200024, 0xffff003f, WR_D|RD_S       },
 183 {"cvt.w.s", "D,S",      0x46000024, 0xffff003f, WR_D|RD_S       },
 184 {"div",     "s,t",      0x0000001a, 0xfc00003f, RD_s|RD_t|WR_HI|WR_LO   },
 185 {"div",     "d,s,t",    0,    (int) M_DIV_3,    INSN_MACRO      },
 186 {"div",     "d,v,I",    0,    (int) M_DIV_3I,   INSN_MACRO      },
 187 {"div.d",   "D,V,T",    0x46200003, 0xffe0003f, WR_D|RD_S|RD_T  },
 188 {"div.s",   "D,V,T",    0x46000003, 0xffe0003f, WR_D|RD_S|RD_T  },
 189 {"divu",    "s,t",      0x0000001b, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO   },
 190 {"divu",    "d,s,t",    0,    (int) M_DIVU_3,   INSN_MACRO      },
 191 {"divu",    "d,v,I",    0,    (int) M_DIVU_3I,  INSN_MACRO      },
 192 {"jr",      "s",        0x00000008, 0xfc1fffff, UBD|RD_s        },
 193 {"j",       "s",        0x00000008, 0xfc1fffff, UBD|RD_s        },
 194 {"j",       "a",        0x08000000, 0xfc000000, UBD             },
 195 {"jalr",    "s",        0x0000f809, 0xfc1fffff, UBD|RD_s|WR_d   },
 196 {"jalr",    "d,s",      0x00000009, 0xfc1f07ff, UBD|RD_s|WR_d   },
 197 {"jal",     "d,s",      0x00000009, 0xfc1f07ff, UBD|RD_s|WR_d   },/* jalr */
 198 {"jal",     "s",        0x0000f809, 0xfc1fffff, UBD|RD_s|WR_d   },/* jalr $ra */
 199 {"jal",     "a",        0x0c000000, 0xfc000000, UBD|WR_31       },
 200 {"l.d",     "T,o(b)",   0,    (int) M_L_DOB,    INSN_MACRO      },
 201 {"l.d",     "T,A(b)",   0,    (int) M_L_DAB,    INSN_MACRO      },
 202 {"la",      "t,A",      0,    (int) M_LA,       INSN_MACRO      },
 203 {"la",      "t,A(b)",   0,    (int) M_LA_AB,    INSN_MACRO      },
 204 {"lb",      "t,o(b)",   0x80000000, 0xfc000000, LDD|RD_b|WR_t   },
 205 {"lb",      "t,A(b)",   0,    (int) M_LB_AB,    INSN_MACRO      },
 206 {"lbu",     "t,o(b)",   0x90000000, 0xfc000000, LDD|RD_b|WR_t   },
 207 {"lbu",     "t,A(b)",   0,    (int) M_LBU_AB,   INSN_MACRO      },
 208 {"ld",      "t,o(b)",   0,    (int) M_LD_OB,    INSN_MACRO      },
 209 {"ld",      "t,A(b)",   0,    (int) M_LD_AB,    INSN_MACRO      },
 210 {"lh",      "t,o(b)",   0x84000000, 0xfc000000, LDD|RD_b|WR_t   },
 211 {"lh",      "t,A(b)",   0,    (int) M_LH_AB,    INSN_MACRO      },
 212 {"lhu",     "t,o(b)",   0x94000000, 0xfc000000, LDD|RD_b|WR_t   },
 213 {"lhu",     "t,A(b)",   0,    (int) M_LHU_AB,   INSN_MACRO      },
 214 /* li is at the start of the table.  */
 215 {"li.d",    "t,F",      0,    (int) M_LI_D,     INSN_MACRO      },
 216 {"li.d",    "T,L",      0,    (int) M_LI_DD,    INSN_MACRO      },
 217 {"li.s",    "t,f",      0,    (int) M_LI_S,     INSN_MACRO      },
 218 {"li.s",    "T,l",      0,    (int) M_LI_SS,    INSN_MACRO      },
 219 {"lui",     "t,u",      0x3c000000, 0xffe00000, WR_t            },
 220 {"lw",      "t,o(b)",   0x8c000000, 0xfc000000, LDD|RD_b|WR_t   },
 221 {"lw",      "t,A(b)",   0,    (int) M_LW_AB,    INSN_MACRO      },
 222 {"lwc0",    "E,o(b)",   0xc0000000, 0xfc000000, COD|RD_b|WR_CC  },
 223 {"lwc0",    "E,A(b)",   0,    (int) M_LWC0_AB,  INSN_MACRO      },
 224 {"lwc1",    "T,o(b)",   0xc4000000, 0xfc000000, COD|RD_b|WR_T   },
 225 {"lwc1",    "E,o(b)",   0xc4000000, 0xfc000000, COD|RD_b|WR_T   },
 226 {"lwc1",    "T,A(b)",   0,    (int) M_LWC1_AB,  INSN_MACRO      },
 227 {"lwc1",    "E,A(b)",   0,    (int) M_LWC1_AB,  INSN_MACRO      },
 228 {"l.s",     "T,o(b)",   0xc4000000, 0xfc000000, COD|RD_b|WR_T   }, /* lwc1 */
 229 {"l.s",     "T,A(b)",   0,    (int) M_LWC1_AB,  INSN_MACRO      },
 230 {"lwc2",    "E,o(b)",   0xc8000000, 0xfc000000, COD|RD_b|WR_CC  },
 231 {"lwc2",    "E,A(b)",   0,    (int) M_LWC2_AB,  INSN_MACRO      },
 232 {"lwc3",    "E,o(b)",   0xcc000000, 0xfc000000, COD|RD_b|WR_CC  },
 233 {"lwc3",    "E,A(b)",   0,    (int) M_LWC3_AB,  INSN_MACRO      },
 234 {"lwl",     "t,o(b)",   0x88000000, 0xfc000000, LDD|RD_b|WR_t   },
 235 {"lwl",     "t,A(b)",   0,    (int) M_LWL_AB,   INSN_MACRO      },
 236 {"lwr",     "t,o(b)",   0x98000000, 0xfc000000, LDD|RD_b|WR_t   },
 237 {"lwr",     "t,A(b)",   0,    (int) M_LWR_AB,   INSN_MACRO      },
 238 {"mfc0",    "t,G",      0x40000000, 0xffe007ff, LDD|WR_t|RD_C0  },
 239 {"mfc1",    "t,S",      0x44000000, 0xffe007ff, LDD|WR_t|RD_S   },
 240 {"mfc1",    "t,G",      0x44000000, 0xffe007ff, LDD|WR_t|RD_S   },
 241 {"mfc2",    "t,G",      0x48000000, 0xffe007ff, LDD|WR_t|RD_C2  },
 242 {"mfc3",    "t,G",      0x4c000000, 0xffe007ff, LDD|WR_t|RD_C3  },
 243 {"mfhi",    "d",        0x00000010, 0xffff07ff, WR_d|RD_HI      },
 244 {"mflo",    "d",        0x00000012, 0xffff07ff, WR_d|RD_LO      },
 245 {"mov.d",   "D,S",      0x46200006, 0xffff003f, WR_D|RD_S       },
 246 {"mov.s",   "D,S",      0x46000006, 0xffff003f, WR_D|RD_S       },
 247 /* move is at the top of the table.  */
 248 {"mtc0",    "t,G",      0x40800000, 0xffe007ff, COD|RD_t|WR_C0|WR_CC    },
 249 {"mtc1",    "t,S",      0x44800000, 0xffe007ff, COD|RD_t|WR_D   },
 250 {"mtc1",    "t,G",      0x44800000, 0xffe007ff, COD|RD_t|WR_D   },
 251 {"mtc2",    "t,G",      0x48800000, 0xffe007ff, COD|RD_t|WR_C2|WR_CC    },
 252 {"mtc3",    "t,G",      0x4c800000, 0xffe007ff, COD|RD_t|WR_C3|WR_CC    },
 253 {"mthi",    "s",        0x00000011, 0xfc1fffff, RD_s|WR_HI      },
 254 {"mtlo",    "s",        0x00000013, 0xfc1fffff, RD_s|WR_LO      },
 255 {"mul.d",   "D,V,T",    0x46200002, 0xffe0003f, WR_D|RD_S|RD_T  },
 256 {"mul.s",   "D,V,T",    0x46000002, 0xffe0003f, WR_D|RD_S|RD_T  },
 257 {"mul",     "d,v,t",    0,    (int) M_MUL,      INSN_MACRO      },
 258 {"mul",     "d,v,I",    0,    (int) M_MUL_I,    INSN_MACRO      },
 259 {"mulo",    "d,v,t",    0,    (int) M_MULO,     INSN_MACRO      },
 260 {"mulo",    "d,v,I",    0,    (int) M_MULO_I,   INSN_MACRO      },
 261 {"mulou",   "d,v,t",    0,    (int) M_MULOU,    INSN_MACRO      },
 262 {"mulou",   "d,v,I",    0,    (int) M_MULOU_I,  INSN_MACRO      },
 263 {"mult",    "s,t",      0x00000018, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO   },
 264 {"multu",   "s,t",      0x00000019, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO   },
 265 {"neg",     "d,w",      0x00000022, 0xffe007ff, WR_d|RD_t       }, /* sub 0 */
 266 {"negu",    "d,w",      0x00000023, 0xffe007ff, WR_d|RD_t       }, /* subu 0 */
 267 {"neg.d",   "D,V",      0x46200007, 0xffff003f, WR_D|RD_S       },
 268 {"neg.s",   "D,V",      0x46000007, 0xffff003f, WR_D|RD_S       },
 269 /* nop is at the start of the table.  */
 270 {"nor",     "d,v,t",    0x00000027, 0xfc0007ff, WR_d|RD_s|RD_t  },
 271 {"nor",     "d,v,I",    0,    (int) M_NOR_I,    INSN_MACRO      },
 272 {"not",     "d,v",      0x00000027, 0xfc0007ff, WR_d|RD_s|RD_t  }, /* nor d,s,zero */
 273 {"or",      "d,v,t",    0x00000025, 0xfc0007ff, WR_d|RD_s|RD_t  },
 274 {"or",      "t,r,I",    0,    (int) M_OR_I,     INSN_MACRO      },
 275 {"ori",     "t,r,i",    0x34000000, 0xfc000000, WR_t|RD_s       },
 276 {"rem",     "d,v,t",    0,    (int) M_REM_3,    INSN_MACRO      },
 277 {"rem",     "d,v,I",    0,    (int) M_REM_3I,   INSN_MACRO      },
 278 {"remu",    "d,v,t",    0,    (int) M_REMU_3,   INSN_MACRO      },
 279 {"remu",    "d,v,I",    0,    (int) M_REMU_3I,  INSN_MACRO      },
 280 {"rfe",     "",         0x42000010, 0xffffffff, INSN_RFE        },
 281 {"rol",     "d,v,t",    0,    (int) M_ROL,      INSN_MACRO      },
 282 {"rol",     "d,v,I",    0,    (int) M_ROL_I,    INSN_MACRO      },
 283 {"ror",     "d,v,t",    0,    (int) M_ROR,      INSN_MACRO      },
 284 {"ror",     "d,v,I",    0,    (int) M_ROR_I,    INSN_MACRO      },
 285 {"s.d",     "T,o(b)",   0,    (int) M_S_DOB,    INSN_MACRO      },
 286 {"s.d",     "T,A(b)",   0,    (int) M_S_DAB,    INSN_MACRO      },
 287 {"sb",      "t,o(b)",   0xa0000000, 0xfc000000, RD_t|RD_b       },
 288 {"sb",      "t,A(b)",   0,    (int) M_SB_AB,    INSN_MACRO      },
 289 {"sd",      "t,o(b)",   0,    (int) M_SD_OB,    INSN_MACRO      },
 290 {"sd",      "t,A(b)",   0,    (int) M_SD_AB,    INSN_MACRO      },
 291 {"seq",     "d,v,t",    0,    (int) M_SEQ,      INSN_MACRO      },
 292 {"seq",     "d,v,I",    0,    (int) M_SEQ_I,    INSN_MACRO      },
 293 {"sge",     "d,v,t",    0,    (int) M_SGE,      INSN_MACRO      },
 294 {"sge",     "d,v,I",    0,    (int) M_SGE_I,    INSN_MACRO      },
 295 {"sgeu",    "d,v,t",    0,    (int) M_SGEU,     INSN_MACRO      },
 296 {"sgeu",    "d,v,I",    0,    (int) M_SGEU_I,   INSN_MACRO      },
 297 {"sgt",     "d,v,t",    0,    (int) M_SGT,      INSN_MACRO      },
 298 {"sgt",     "d,v,I",    0,    (int) M_SGT_I,    INSN_MACRO      },
 299 {"sgtu",    "d,v,t",    0,    (int) M_SGTU,     INSN_MACRO      },
 300 {"sgtu",    "d,v,I",    0,    (int) M_SGTU_I,   INSN_MACRO      },
 301 {"sh",      "t,o(b)",   0xa4000000, 0xfc000000, RD_t|RD_b       },
 302 {"sh",      "t,A(b)",   0,    (int) M_SH_AB,    INSN_MACRO      },
 303 {"sle",     "d,v,t",    0,    (int) M_SLE,      INSN_MACRO      },
 304 {"sle",     "d,v,I",    0,    (int) M_SLE_I,    INSN_MACRO      },
 305 {"sleu",    "d,v,t",    0,    (int) M_SLEU,     INSN_MACRO      },
 306 {"sleu",    "d,v,I",    0,    (int) M_SLEU_I,   INSN_MACRO      },
 307 {"sllv",    "d,t,s",    0x00000004, 0xfc0007ff, WR_d|RD_t|RD_s  },
 308 {"sll",     "d,w,s",    0x00000004, 0xfc0007ff, WR_d|RD_t|RD_s  }, /* sllv */
 309 {"sll",     "d,w,<",    0x00000000, 0xffe0003f, WR_d|RD_t       },
 310 {"slt",     "d,v,t",    0x0000002a, 0xfc0007ff, WR_d|RD_s|RD_t  },
 311 {"slt",     "d,v,I",    0,    (int) M_SLT_I,    INSN_MACRO      },
 312 {"slti",    "t,r,j",    0x28000000, 0xfc000000, WR_t|RD_s       },
 313 {"sltiu",   "t,r,j",    0x2c000000, 0xfc000000, WR_t|RD_s       },
 314 {"sltu",    "d,v,t",    0x0000002b, 0xfc0007ff, WR_d|RD_s|RD_t  },
 315 {"sltu",    "d,v,I",    0,    (int) M_SLTU_I,   INSN_MACRO      },
 316 {"sne",     "d,v,t",    0,    (int) M_SNE,      INSN_MACRO      },
 317 {"sne",     "d,v,I",    0,    (int) M_SNE_I,    INSN_MACRO      },
 318 {"srav",    "d,t,s",    0x00000007, 0xfc0007ff, WR_d|RD_t|RD_s  },
 319 {"sra",     "d,w,s",    0x00000007, 0xfc0007ff, WR_d|RD_t|RD_s  }, /* srav */
 320 {"sra",     "d,w,<",    0x00000003, 0xffe0003f, WR_d|RD_t       },
 321 {"srlv",    "d,t,s",    0x00000006, 0xfc0007ff, WR_d|RD_t|RD_s  },
 322 {"srl",     "d,w,s",    0x00000006, 0xfc0007ff, WR_d|RD_t|RD_s  }, /* srlv */
 323 {"srl",     "d,w,<",    0x00000002, 0xffe0003f, WR_d|RD_t       },
 324 {"sub",     "d,v,t",    0x00000022, 0xfc0007ff, WR_d|RD_s|RD_t  },
 325 {"sub",     "d,v,I",    0,    (int) M_SUB_I,    INSN_MACRO      },
 326 {"sub.d",   "D,V,T",    0x46200001, 0xffe0003f, WR_D|RD_S|RD_T  },
 327 {"sub.s",   "D,V,T",    0x46000001, 0xffe0003f, WR_D|RD_S|RD_T  },
 328 {"subu",    "d,v,t",    0x00000023, 0xfc0007ff, WR_d|RD_s|RD_t  },
 329 {"subu",    "d,v,I",    0,    (int) M_SUBU_I,   INSN_MACRO      },
 330 {"sw",      "t,o(b)",   0xac000000, 0xfc000000, RD_t|RD_b       },
 331 {"sw",      "t,A(b)",   0,    (int) M_SW_AB,    INSN_MACRO      },
 332 {"swc0",    "E,o(b)",   0xe0000000, 0xfc000000, RD_C0|RD_b      },
 333 {"swc0",    "E,A(b)",   0,    (int) M_SWC0_AB,  INSN_MACRO      },
 334 {"swc1",    "T,o(b)",   0xe4000000, 0xfc000000, RD_T|RD_b       },
 335 {"swc1",    "E,o(b)",   0xe4000000, 0xfc000000, RD_T|RD_b       },
 336 {"swc1",    "T,A(b)",   0,    (int) M_SWC1_AB,  INSN_MACRO      },
 337 {"swc1",    "E,A(b)",   0,    (int) M_SWC1_AB,  INSN_MACRO      },
 338 {"s.s",     "T,o(b)",   0xe4000000, 0xfc000000, RD_T|RD_b       }, /* swc1 */
 339 {"s.s",     "T,A(b)",   0,    (int) M_SWC1_AB,  INSN_MACRO      },
 340 {"swc2",    "E,o(b)",   0xe8000000, 0xfc000000, RD_C2|RD_b      },
 341 {"swc2",    "E,A(b)",   0,    (int) M_SWC2_AB,  INSN_MACRO      },
 342 {"swc3",    "E,o(b)",   0xec000000, 0xfc000000, RD_C3|RD_b      },
 343 {"swc3",    "E,A(b)",   0,    (int) M_SWC3_AB,  INSN_MACRO      },
 344 {"swl",     "t,o(b)",   0xa8000000, 0xfc000000, RD_t|RD_b       },
 345 {"swl",     "t,A(b)",   0,    (int) M_SWL_AB,   INSN_MACRO      },
 346 {"swr",     "t,o(b)",   0xb8000000, 0xfc000000, RD_t|RD_b       },
 347 {"swr",     "t,A(b)",   0,    (int) M_SWR_AB,   INSN_MACRO      },
 348 {"syscall", "",         0x0000000c, 0xffffffff, INSN_TRAP       },
 349 {"syscall", "B",        0x0000000c, 0xfc00003f, INSN_TRAP       },
 350 {"tlbp",    "",         0x42000008, 0xffffffff, INSN_TLB        },
 351 {"tlbr",    "",         0x42000001, 0xffffffff, INSN_TLB        },
 352 {"tlbwi",   "",         0x42000002, 0xffffffff, INSN_TLB        },
 353 {"tlbwr",   "",         0x42000006, 0xffffffff, INSN_TLB        },
 354 {"trunc.w.d", "D,S,t",  0,    (int) M_TRUNCWD,  INSN_MACRO      },
 355 {"trunc.w.s", "D,S,t",  0,    (int) M_TRUNCWS,  INSN_MACRO      },
 356 {"ulh",     "t,o(b)",   0,    (int) M_ULH,      INSN_MACRO      },
 357 {"ulh",     "t,A",      0,    (int) M_ULH_A,    INSN_MACRO      },
 358 {"ulhu",    "t,o(b)",   0,    (int) M_ULHU,     INSN_MACRO      },
 359 {"ulhu",    "t,A",      0,    (int) M_ULHU_A,   INSN_MACRO      },
 360 {"ulw",     "t,o(b)",   0,    (int) M_ULW,      INSN_MACRO      },
 361 {"ulw",     "t,A",      0,    (int) M_ULW_A,    INSN_MACRO      },
 362 {"ush",     "t,o(b)",   0,    (int) M_USH,      INSN_MACRO      },
 363 {"ush",     "t,A",      0,    (int) M_USH_A,    INSN_MACRO      },
 364 {"usw",     "t,o(b)",   0,    (int) M_USW,      INSN_MACRO      },
 365 {"usw",     "t,A",      0,    (int) M_USW_A,    INSN_MACRO      },
 366 {"xor",     "d,v,t",    0x00000026, 0xfc0007ff, WR_d|RD_s|RD_t  },
 367 {"xor",     "t,r,I",    0,    (int) M_XOR_I,    INSN_MACRO      },
 368 {"xori",    "t,r,i",    0x38000000, 0xfc000000, WR_t|RD_s       },
 369 /* No hazard protection on coprocessor instructions--they shouldn't
 370    change the state of the processor and if they do it's up to the
 371    user to put in nops as necessary.  These are at the end so that the
 372    disasembler recognizes more specific versions first.  */
 373 {"c0",      "C",        0x42000000, 0xfe000000, 0               },
 374 {"c1",      "C",        0x46000000, 0xfe000000, 0               },
 375 {"c2",      "C",        0x4a000000, 0xfe000000, 0               },
 376 {"c3",      "C",        0x4e000000, 0xfe000000, 0               },
 377 };
 378
 379 const int bfd_mips_num_opcodes =
 380   ((sizeof mips_opcodes) / (sizeof (mips_opcodes[0])));