1 /* mips.h. Mips opcode list for GDB, the GNU debugger.
2 Copyright 1993 Free Software Foundation, Inc.
3 Contributed by Ralph Campbell and OSF
4 Commented and modified by Ian Lance Taylor, Cygnus Support
6 This file is part of GDB, GAS, and the GNU binutils.
8 GDB, GAS, and the GNU binutils are free software; you can redistribute
9 them and/or modify them under the terms of the GNU General Public
10 License as published by the Free Software Foundation; either version
11 1, or (at your option) any later version.
13 GDB, GAS, and the GNU binutils are distributed in the hope that they
14 will be useful, but WITHOUT ANY WARRANTY; without even the implied
15 warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See
16 the GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with this file; see the file COPYING. If not, write to the Free
20 Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */
24 #include "opcode/mips.h"
26 /* Short hand so the lines aren't too long. */
28 #define LDD INSN_LOAD_MEMORY_DELAY
29 #define LCD INSN_LOAD_COPROC_DELAY
30 #define UBD INSN_UNCOND_BRANCH_DELAY
31 #define CBD INSN_COND_BRANCH_DELAY
32 #define COD INSN_COPROC_MOVE_DELAY
33 #define CLD INSN_COPROC_MEMORY_DELAY
34 #define CBL INSN_COND_BRANCH_LIKELY
36 #define WR_d INSN_WRITE_GPR_D
37 #define WR_t INSN_WRITE_GPR_T
38 #define WR_31 INSN_WRITE_GPR_31
39 #define WR_D INSN_WRITE_FPR_D
40 #define WR_T INSN_WRITE_FPR_T
41 #define WR_S INSN_WRITE_FPR_S
42 #define RD_s INSN_READ_GPR_S
43 #define RD_b INSN_READ_GPR_S
44 #define RD_t INSN_READ_GPR_T
45 #define RD_S INSN_READ_FPR_S
46 #define RD_T INSN_READ_FPR_T
47 #define WR_CC INSN_WRITE_COND_CODE
48 #define RD_CC INSN_READ_COND_CODE
49 #define RD_C0 INSN_COP
50 #define RD_C1 INSN_COP
51 #define RD_C2 INSN_COP
52 #define RD_C3 INSN_COP
53 #define WR_C0 INSN_COP
54 #define WR_C1 INSN_COP
55 #define WR_C2 INSN_COP
56 #define WR_C3 INSN_COP
57 #define WR_HI INSN_WRITE_HI
58 #define WR_LO INSN_WRITE_LO
59 #define RD_HI INSN_READ_HI
60 #define RD_LO INSN_READ_LO
65 /* The order of overloaded instructions matters. Label arguments and
66 register arguments look the same. Instructions that can have either
67 for arguments must apear in the correct order in this table for the
68 assembler to pick the right one. In other words, entries with
69 immediate operands must apear after the same instruction with
72 Many instructions are short hand for other instructions (i.e., The
73 jal <register> instruction is short for jalr <register>). */
75 const struct mips_opcode mips_opcodes
[] = {
76 /* These instructions appear first so that the disassembler will find
77 them first. The assemblers uses a hash table based on the
78 instruction name anyhow. */
79 {"nop", "", 0x00000000, 0xffffffff, 0 },
80 {"li", "t,j", 0x24000000, 0xffe00000, WR_t
}, /* addiu */
81 {"li", "t,i", 0x34000000, 0xffe00000, WR_t
}, /* ori */
82 {"li", "t,I", 0, (int) M_LI
, INSN_MACRO
},
83 {"move", "d,s", 0x00000021, 0xfc1f07ff, WR_d
|RD_s
}, /* addu */
84 {"b", "p", 0x10000000, 0xffff0000, UBD
}, /* beq 0,0 */
85 {"b", "p", 0x40100000, 0xffff0000, UBD
}, /* bgez 0 */
86 {"bal", "p", 0x04110000, 0xffff0000, UBD
|WR_31
}, /* bgezal 0 */
88 {"abs", "d,v", 0, (int) M_ABS
, INSN_MACRO
},
89 {"abs.s", "D,V", 0x46000005, 0xffff003f, WR_D
|RD_S
},
90 {"abs.d", "D,V", 0x46200005, 0xffff003f, WR_D
|RD_S
},
91 {"add", "d,v,t", 0x00000020, 0xfc0007ff, WR_d
|RD_s
|RD_t
},
92 {"add", "t,r,I", 0, (int) M_ADD_I
, INSN_MACRO
},
93 {"add.s", "D,V,T", 0x46000000, 0xffe0003f, WR_D
|RD_S
|RD_T
},
94 {"add.d", "D,V,T", 0x46200000, 0xffe0003f, WR_D
|RD_S
|RD_T
},
95 {"addi", "t,r,j", 0x20000000, 0xfc000000, WR_t
|RD_s
},
96 {"addiu", "t,r,j", 0x24000000, 0xfc000000, WR_t
|RD_s
},
97 {"addu", "d,v,t", 0x00000021, 0xfc0007ff, WR_d
|RD_s
|RD_t
},
98 {"addu", "t,r,I", 0, (int) M_ADDU_I
, INSN_MACRO
},
99 {"and", "d,v,t", 0x00000024, 0xfc0007ff, WR_d
|RD_s
|RD_t
},
100 {"and", "t,r,I", 0, (int) M_AND_I
, INSN_MACRO
},
101 {"andi", "t,r,i", 0x30000000, 0xfc000000, WR_t
|RD_s
},
102 /* b is at the top of the table. */
103 /* bal is at the top of the table. */
104 {"bc0f", "p", 0x41000000, 0xffff0000, CBD
|RD_CC
},
105 {"bc0fl", "p", 0x41020000, 0xffff0000, CBL
|RD_CC
|I2
},
106 {"bc1f", "p", 0x45000000, 0xffff0000, CBD
|RD_CC
},
107 {"bc1fl", "p", 0x45020000, 0xffff0000, CBL
|RD_CC
|I2
},
108 {"bc2f", "p", 0x49000000, 0xffff0000, CBD
|RD_CC
},
109 {"bc2fl", "p", 0x49020000, 0xffff0000, CBL
|RD_CC
|I2
},
110 {"bc3f", "p", 0x4d000000, 0xffff0000, CBD
|RD_CC
},
111 {"bc3fl", "p", 0x4d020000, 0xffff0000, CBL
|RD_CC
|I2
},
112 {"bc0t", "p", 0x41010000, 0xffff0000, CBD
|RD_CC
},
113 {"bc0tl", "p", 0x41030000, 0xffff0000, CBL
|RD_CC
|I2
},
114 {"bc1t", "p", 0x45010000, 0xffff0000, CBD
|RD_CC
},
115 {"bc1tl", "p", 0x45030000, 0xffff0000, CBL
|RD_CC
|I2
},
116 {"bc2t", "p", 0x49010000, 0xffff0000, CBD
|RD_CC
},
117 {"bc2tl", "p", 0x49030000, 0xffff0000, CBL
|RD_CC
|I2
},
118 {"bc3t", "p", 0x4d010000, 0xffff0000, CBD
|RD_CC
},
119 {"bc3tl", "p", 0x4d030000, 0xffff0000, CBL
|RD_CC
|I2
},
120 {"beqz", "s,p", 0x10000000, 0xfc1f0000, CBD
|RD_s
},
121 {"beqzl", "s,p", 0x50000000, 0xfc1f0000, CBD
|RD_s
|I2
},
122 {"beq", "s,t,p", 0x10000000, 0xfc000000, CBD
|RD_s
|RD_t
},
123 {"beq", "s,I,p", 0, (int) M_BEQ_I
, INSN_MACRO
},
124 {"beql", "s,t,p", 0x50000000, 0xfc000000, CBL
|RD_s
|RD_t
|I2
},
125 {"beql", "s,I,p", 2, (int) M_BEQL_I
, INSN_MACRO
},
126 {"bge", "s,t,p", 0, (int) M_BGE
, INSN_MACRO
},
127 {"bge", "s,I,p", 0, (int) M_BGE_I
, INSN_MACRO
},
128 {"bgel", "s,t,p", 2, (int) M_BGEL
, INSN_MACRO
},
129 {"bgel", "s,I,p", 2, (int) M_BGEL_I
, INSN_MACRO
},
130 {"bgeu", "s,t,p", 0, (int) M_BGEU
, INSN_MACRO
},
131 {"bgeu", "s,I,p", 0, (int) M_BGEU_I
, INSN_MACRO
},
132 {"bgeul", "s,t,p", 2, (int) M_BGEUL
, INSN_MACRO
},
133 {"bgeul", "s,I,p", 2, (int) M_BGEUL_I
, INSN_MACRO
},
134 {"bgez", "s,p", 0x04010000, 0xfc1f0000, CBD
|RD_s
},
135 {"bgezl", "s,p", 0x04030000, 0xfc1f0000, CBD
|RD_s
|I2
},
136 {"bgezal", "s,p", 0x04110000, 0xfc1f0000, CBD
|RD_s
|WR_31
},
137 {"bgezall", "s,p", 0x04130000, 0xfc1f0000, CBD
|RD_s
|I2
},
138 {"bgt", "s,t,p", 0, (int) M_BGT
, INSN_MACRO
},
139 {"bgt", "s,I,p", 0, (int) M_BGT_I
, INSN_MACRO
},
140 {"bgtl", "s,t,p", 2, (int) M_BGTL
, INSN_MACRO
},
141 {"bgtl", "s,I,p", 2, (int) M_BGTL_I
, INSN_MACRO
},
142 {"bgtu", "s,t,p", 0, (int) M_BGTU
, INSN_MACRO
},
143 {"bgtu", "s,I,p", 0, (int) M_BGTU_I
, INSN_MACRO
},
144 {"bgtul", "s,t,p", 2, (int) M_BGTUL
, INSN_MACRO
},
145 {"bgtul", "s,I,p", 2, (int) M_BGTUL_I
, INSN_MACRO
},
146 {"bgtz", "s,p", 0x1c000000, 0xfc1f0000, CBD
|RD_s
},
147 {"bgtzl", "s,p", 0x5c000000, 0xfc1f0000, CBD
|RD_s
|I2
},
148 {"ble", "s,t,p", 0, (int) M_BLE
, INSN_MACRO
},
149 {"ble", "s,I,p", 0, (int) M_BLE_I
, INSN_MACRO
},
150 {"blel", "s,t,p", 2, (int) M_BLEL
, INSN_MACRO
},
151 {"blel", "s,I,p", 2, (int) M_BLEL_I
, INSN_MACRO
},
152 {"bleu", "s,t,p", 0, (int) M_BLEU
, INSN_MACRO
},
153 {"bleu", "s,I,p", 0, (int) M_BLEU_I
, INSN_MACRO
},
154 {"bleul", "s,t,p", 2, (int) M_BLEUL
, INSN_MACRO
},
155 {"bleul", "s,I,p", 2, (int) M_BLEUL_I
, INSN_MACRO
},
156 {"blez", "s,p", 0x18000000, 0xfc1f0000, CBD
|RD_s
},
157 {"blezl", "s,p", 0x58000000, 0xfc1f0000, CBD
|RD_s
|I2
},
158 {"blt", "s,t,p", 0, (int) M_BLT
, INSN_MACRO
},
159 {"blt", "s,I,p", 0, (int) M_BLT_I
, INSN_MACRO
},
160 {"bltl", "s,t,p", 2, (int) M_BLTL
, INSN_MACRO
},
161 {"bltl", "s,I,p", 2, (int) M_BLTL_I
, INSN_MACRO
},
162 {"bltu", "s,t,p", 0, (int) M_BLTU
, INSN_MACRO
},
163 {"bltu", "s,I,p", 0, (int) M_BLTU_I
, INSN_MACRO
},
164 {"bltul", "s,t,p", 2, (int) M_BLTUL
, INSN_MACRO
},
165 {"bltul", "s,I,p", 2, (int) M_BLTUL_I
, INSN_MACRO
},
166 {"bltz", "s,p", 0x04000000, 0xfc1f0000, CBD
|RD_s
},
167 {"bltzl", "s,p", 0x04020000, 0xfc1f0000, CBD
|RD_s
|I2
},
168 {"bltzal", "s,p", 0x04100000, 0xfc1f0000, CBD
|RD_s
|WR_31
},
169 {"bltzall", "s,p", 0x04120000, 0xfc1f0000, CBD
|RD_s
|I2
},
170 {"bnez", "s,p", 0x14000000, 0xfc1f0000, CBD
|RD_s
},
171 {"bnezl", "s,p", 0x54000000, 0xfc1f0000, CBD
|RD_s
|I2
},
172 {"bne", "s,t,p", 0x14000000, 0xfc000000, CBD
|RD_s
|RD_t
},
173 {"bne", "s,I,p", 0, (int) M_BNE_I
, INSN_MACRO
},
174 {"bnel", "s,t,p", 0x54000000, 0xfc000000, CBD
|RD_s
|RD_t
},
175 {"bnel", "s,I,p", 2, (int) M_BNEL_I
, INSN_MACRO
},
176 {"break", "", 0x0000000d, 0xffffffff, INSN_TRAP
},
177 {"break", "c", 0x0000000d, 0xfc00003f, INSN_TRAP
},
178 {"c.f.d", "S,T", 0x46200030, 0xffe007ff, RD_S
|RD_T
|WR_CC
},
179 {"c.f.s", "S,T", 0x46000030, 0xffe007ff, RD_S
|RD_T
|WR_CC
},
180 {"c.un.d", "S,T", 0x46200031, 0xffe007ff, RD_S
|RD_T
|WR_CC
},
181 {"c.un.s", "S,T", 0x46000031, 0xffe007ff, RD_S
|RD_T
|WR_CC
},
182 {"c.eq.d", "S,T", 0x46200032, 0xffe007ff, RD_S
|RD_T
|WR_CC
},
183 {"c.eq.s", "S,T", 0x46000032, 0xffe007ff, RD_S
|RD_T
|WR_CC
},
184 {"c.ueq.d", "S,T", 0x46200033, 0xffe007ff, RD_S
|RD_T
|WR_CC
},
185 {"c.ueq.s", "S,T", 0x46000033, 0xffe007ff, RD_S
|RD_T
|WR_CC
},
186 {"c.olt.d", "S,T", 0x46200034, 0xffe007ff, RD_S
|RD_T
|WR_CC
},
187 {"c.olt.s", "S,T", 0x46000034, 0xffe007ff, RD_S
|RD_T
|WR_CC
},
188 {"c.ult.d", "S,T", 0x46200035, 0xffe007ff, RD_S
|RD_T
|WR_CC
},
189 {"c.ult.s", "S,T", 0x46000035, 0xffe007ff, RD_S
|RD_T
|WR_CC
},
190 {"c.ole.d", "S,T", 0x46200036, 0xffe007ff, RD_S
|RD_T
|WR_CC
},
191 {"c.ole.s", "S,T", 0x46000036, 0xffe007ff, RD_S
|RD_T
|WR_CC
},
192 {"c.ule.d", "S,T", 0x46200037, 0xffe007ff, RD_S
|RD_T
|WR_CC
},
193 {"c.ule.s", "S,T", 0x46000037, 0xffe007ff, RD_S
|RD_T
|WR_CC
},
194 {"c.sf.d", "S,T", 0x46200038, 0xffe007ff, RD_S
|RD_T
|WR_CC
},
195 {"c.sf.s", "S,T", 0x46000038, 0xffe007ff, RD_S
|RD_T
|WR_CC
},
196 {"c.ngle.d","S,T", 0x46200039, 0xffe007ff, RD_S
|RD_T
|WR_CC
},
197 {"c.ngle.s","S,T", 0x46000039, 0xffe007ff, RD_S
|RD_T
|WR_CC
},
198 {"c.seq.d", "S,T", 0x4620003a, 0xffe007ff, RD_S
|RD_T
|WR_CC
},
199 {"c.seq.s", "S,T", 0x4600003a, 0xffe007ff, RD_S
|RD_T
|WR_CC
},
200 {"c.ngl.d", "S,T", 0x4620003b, 0xffe007ff, RD_S
|RD_T
|WR_CC
},
201 {"c.ngl.s", "S,T", 0x4600003b, 0xffe007ff, RD_S
|RD_T
|WR_CC
},
202 {"c.lt.d", "S,T", 0x4620003c, 0xffe007ff, RD_S
|RD_T
|WR_CC
},
203 {"c.lt.s", "S,T", 0x4600003c, 0xffe007ff, RD_S
|RD_T
|WR_CC
},
204 {"c.nge.d", "S,T", 0x4620003d, 0xffe007ff, RD_S
|RD_T
|WR_CC
},
205 {"c.nge.s", "S,T", 0x4600003d, 0xffe007ff, RD_S
|RD_T
|WR_CC
},
206 {"c.le.d", "S,T", 0x4620003e, 0xffe007ff, RD_S
|RD_T
|WR_CC
},
207 {"c.le.s", "S,T", 0x4600003e, 0xffe007ff, RD_S
|RD_T
|WR_CC
},
208 {"c.ngt.d", "S,T", 0x4620003f, 0xffe007ff, RD_S
|RD_T
|WR_CC
},
209 {"c.ngt.s", "S,T", 0x4600003f, 0xffe007ff, RD_S
|RD_T
|WR_CC
},
210 {"cache", "t,o(b)", 0xbc000000, 0xfc000000, RD_b
|I3
},
211 {"ceil.l.d", "D,S", 0x4620000a, 0xffff003f, WR_D
|RD_S
|I3
},
212 {"ceil.l.s", "D,S", 0x4600000a, 0xffff003f, WR_D
|RD_S
|I3
},
213 {"ceil.w.d", "D,S", 0x4620000e, 0xffff003f, WR_D
|RD_S
|I2
},
214 {"ceil.w.s", "D,S", 0x4600000e, 0xffff003f, WR_D
|RD_S
|I2
},
215 {"cfc0", "t,G", 0x40400000, 0xffe007ff, LCD
|WR_t
|RD_C0
},
216 {"cfc1", "t,G", 0x44400000, 0xffe007ff, LCD
|WR_t
|RD_C1
},
217 {"cfc1", "t,S", 0x44400000, 0xffe007ff, LCD
|WR_t
|RD_C1
},
218 {"cfc2", "t,G", 0x48400000, 0xffe007ff, LCD
|WR_t
|RD_C2
},
219 {"cfc3", "t,G", 0x4c400000, 0xffe007ff, LCD
|WR_t
|RD_C3
},
220 {"ctc0", "t,G", 0x40c00000, 0xffe007ff, COD
|RD_t
|WR_CC
},
221 {"ctc1", "t,G", 0x44c00000, 0xffe007ff, COD
|RD_t
|WR_CC
},
222 {"ctc1", "t,S", 0x44c00000, 0xffe007ff, COD
|RD_t
|WR_CC
},
223 {"ctc2", "t,G", 0x48c00000, 0xffe007ff, COD
|RD_t
|WR_CC
},
224 {"ctc3", "t,G", 0x4cc00000, 0xffe007ff, COD
|RD_t
|WR_CC
},
225 {"cvt.d.l", "D,S", 0x46a00021, 0xffff003f, WR_D
|RD_S
|I3
},
226 {"cvt.d.s", "D,S", 0x46000021, 0xffff003f, WR_D
|RD_S
},
227 {"cvt.d.w", "D,S", 0x46800021, 0xffff003f, WR_D
|RD_S
},
228 {"cvt.l.d", "D,S", 0x46200025, 0xffff003f, WR_D
|RD_S
|I3
},
229 {"cvt.l.s", "D,S", 0x46000025, 0xffff003f, WR_D
|RD_S
|I3
},
230 {"cvt.s.l", "D,S", 0x46a00020, 0xffff003f, WR_D
|RD_S
|I3
},
231 {"cvt.s.d", "D,S", 0x46200020, 0xffff003f, WR_D
|RD_S
},
232 {"cvt.s.w", "D,S", 0x46800020, 0xffff003f, WR_D
|RD_S
},
233 {"cvt.w.d", "D,S", 0x46200024, 0xffff003f, WR_D
|RD_S
},
234 {"cvt.w.s", "D,S", 0x46000024, 0xffff003f, WR_D
|RD_S
},
235 {"dabs", "d,v", 0, (int) M_DABS
, INSN_MACRO
},
236 {"dadd", "d,v,t", 0x0000002c, 0xfc0007ff, WR_d
|RD_s
|RD_t
|I3
},
237 {"dadd", "t,r,I", 3, (int) M_DADD_I
, INSN_MACRO
},
238 {"daddi", "t,r,j", 0x60000000, 0xfc000000, WR_t
|RD_s
|I3
},
239 {"daddiu", "t,r,j", 0x64000000, 0xfc000000, WR_t
|RD_s
|I3
},
240 {"daddu", "d,v,t", 0x0000002d, 0xfc0007ff, WR_d
|RD_s
|RD_t
|I3
},
241 {"daddu", "t,r,I", 3, (int) M_DADDU_I
, INSN_MACRO
},
242 /* For ddiv, see the comments about div. */
243 {"ddiv", "z,s,t", 0x0000001e, 0xfc00ffff, RD_s
|RD_t
|WR_HI
|WR_LO
|I3
},
244 {"ddiv", "d,v,t", 3, (int) M_DDIV_3
, INSN_MACRO
},
245 {"ddiv", "d,v,I", 3, (int) M_DDIV_3I
, INSN_MACRO
},
246 /* For ddivu, see the comments about div. */
247 {"ddivu", "z,s,t", 0x0000001f, 0xfc00ffff, RD_s
|RD_t
|WR_HI
|WR_LO
|I3
},
248 {"ddivu", "d,v,t", 3, (int) M_DDIVU_3
, INSN_MACRO
},
249 {"ddivu", "d,v,I", 3, (int) M_DDIVU_3I
, INSN_MACRO
},
250 /* The MIPS assembler treats the div opcode with two operands as
251 though the first operand appeared twice (the first operand is both
252 a source and a destination). To get the div machine instruction,
253 you must use an explicit destination of $0. */
254 {"div", "z,s,t", 0x0000001a, 0xfc00ffff, RD_s
|RD_t
|WR_HI
|WR_LO
},
255 {"div", "d,v,t", 0, (int) M_DIV_3
, INSN_MACRO
},
256 {"div", "d,v,I", 0, (int) M_DIV_3I
, INSN_MACRO
},
257 {"div.d", "D,V,T", 0x46200003, 0xffe0003f, WR_D
|RD_S
|RD_T
},
258 {"div.s", "D,V,T", 0x46000003, 0xffe0003f, WR_D
|RD_S
|RD_T
},
259 /* For divu, see the comments about div. */
260 {"divu", "z,s,t", 0x0000001b, 0xfc00ffff, RD_s
|RD_t
|WR_HI
|WR_LO
},
261 {"divu", "d,v,t", 0, (int) M_DIVU_3
, INSN_MACRO
},
262 {"divu", "d,v,I", 0, (int) M_DIVU_3I
, INSN_MACRO
},
263 {"dmfc0", "t,G", 0x40200000, 0xffe007ff, LCD
|WR_t
|RD_C0
|I3
},
264 {"dmtc0", "t,G", 0x40a00000, 0xffe007ff, COD
|RD_t
|WR_C0
|WR_CC
|I3
},
265 {"dmfc1", "t,S", 0x44200000, 0xffe007ff, LCD
|WR_t
|RD_S
|I3
},
266 {"dmtc1", "t,S", 0x44a00000, 0xffe007ff, COD
|RD_t
|WR_S
|I3
},
267 {"dmul", "d,v,t", 3, (int) M_DMUL
, INSN_MACRO
},
268 {"dmul", "d,v,I", 3, (int) M_DMUL_I
, INSN_MACRO
},
269 {"dmulo", "d,v,t", 3, (int) M_DMULO
, INSN_MACRO
},
270 {"dmulo", "d,v,I", 3, (int) M_DMULO_I
, INSN_MACRO
},
271 {"dmulou", "d,v,t", 3, (int) M_DMULOU
, INSN_MACRO
},
272 {"dmulou", "d,v,I", 3, (int) M_DMULOU_I
, INSN_MACRO
},
273 {"dmult", "s,t", 0x0000001c, 0xfc00ffff, RD_s
|RD_t
|WR_HI
|WR_LO
|I3
},
274 {"dmultu", "s,t", 0x0000001d, 0xfc00ffff, RD_s
|RD_t
|WR_HI
|WR_LO
|I3
},
275 {"dneg", "d,w", 0x0000002e, 0xffe007ff, WR_d
|RD_t
|I3
}, /* dsub 0 */
276 {"dnegu", "d,w", 0x0000002f, 0xffe007ff, WR_d
|RD_t
|I3
}, /* dsubu 0*/
277 {"drem", "z,s,t", 0x0000001e, 0xfc00ffff, RD_s
|RD_t
|WR_HI
|WR_LO
|I3
},
278 {"drem", "d,v,t", 3, (int) M_DREM_3
, INSN_MACRO
},
279 {"drem", "d,v,I", 3, (int) M_DREM_3I
, INSN_MACRO
},
280 {"dremu", "z,s,t", 0x0000001f, 0xfc00ffff, RD_s
|RD_t
|WR_HI
|WR_LO
|I3
},
281 {"dremu", "d,v,t", 3, (int) M_DREMU_3
, INSN_MACRO
},
282 {"dremu", "d,v,I", 3, (int) M_DREMU_3I
, INSN_MACRO
},
283 {"dsllv", "d,t,s", 0x00000014, 0xfc0007ff, WR_d
|RD_t
|RD_s
|I3
},
284 {"dsll", "d,w,s", 0x00000014, 0xfc0007ff, WR_d
|RD_t
|RD_s
|I3
}, /* dsllv */
285 {"dsll", "d,w,<", 0x00000038, 0xffe0003f, WR_d
|RD_t
|I3
},
286 {"dsll32", "d,w,<", 0x0000003c, 0xffe0003f, WR_d
|RD_t
|I3
},
287 {"dsrav", "d,t,s", 0x00000017, 0xfc0007ff, WR_d
|RD_t
|RD_s
|I3
},
288 {"dsra", "d,w,s", 0x00000017, 0xfc0007ff, WR_d
|RD_t
|RD_s
|I3
}, /* dsrav */
289 {"dsra", "d,w,<", 0x0000003b, 0xffe0003f, WR_d
|RD_t
|I3
},
290 {"dsra32", "d,w,<", 0x0000003f, 0xffe0003f, WR_d
|RD_t
|I3
},
291 {"dsrlv", "d,t,s", 0x00000016, 0xfc0007ff, WR_d
|RD_t
|RD_s
|I3
},
292 {"dsrl", "d,w,s", 0x00000016, 0xfc0007ff, WR_d
|RD_t
|RD_s
|I3
}, /* dsrlv */
293 {"dsrl", "d,w,<", 0x0000003a, 0xffe0003f, WR_d
|RD_t
|I3
},
294 {"dsrl32", "d,w,<", 0x0000003e, 0xffe0003f, WR_d
|RD_t
|I3
},
295 {"dsub", "d,v,t", 0x0000002e, 0xfc0007ff, WR_d
|RD_s
|RD_t
|I3
},
296 {"dsub", "d,v,I", 3, (int) M_DSUB_I
, INSN_MACRO
},
297 {"dsubu", "d,v,t", 0x0000002f, 0xfc0007ff, WR_d
|RD_s
|RD_t
|I3
},
298 {"dsubu", "d,v,I", 3, (int) M_DSUBU_I
, INSN_MACRO
},
299 {"eret", "", 0x42000018, 0xffffffff, I3
},
300 {"floor.l.d", "D,S", 0x4620000b, 0xffff003f, WR_D
|RD_S
|I3
},
301 {"floor.l.s", "D,S", 0x4600000b, 0xffff003f, WR_D
|RD_S
|I3
},
302 {"floor.w.d", "D,S", 0x4620000f, 0xffff003f, WR_D
|RD_S
|I2
},
303 {"floor.w.s", "D,S", 0x4600000f, 0xffff003f, WR_D
|RD_S
|I2
},
304 {"jr", "s", 0x00000008, 0xfc1fffff, UBD
|RD_s
},
305 {"j", "s", 0x00000008, 0xfc1fffff, UBD
|RD_s
},
306 {"j", "a", 0x08000000, 0xfc000000, UBD
},
307 {"jalr", "s", 0x0000f809, 0xfc1fffff, UBD
|RD_s
|WR_d
},
308 {"jalr", "d,s", 0x00000009, 0xfc1f07ff, UBD
|RD_s
|WR_d
},
309 {"jal", "d,s", 0x00000009, 0xfc1f07ff, UBD
|RD_s
|WR_d
},/* jalr */
310 {"jal", "s", 0x0000f809, 0xfc1fffff, UBD
|RD_s
|WR_d
},/* jalr $ra*/
311 {"jal", "a", 0x0c000000, 0xfc000000, UBD
|WR_31
},
312 {"l.d", "T,o(b)", 0xd4000000, 0xfc000000, CLD
|RD_b
|WR_T
|I2
},
313 {"l.d", "T,o(b)", 0, (int) M_L_DOB
, INSN_MACRO
},
314 {"l.d", "T,A(b)", 0, (int) M_L_DAB
, INSN_MACRO
},
315 {"la", "t,A", 0, (int) M_LA
, INSN_MACRO
},
316 {"la", "t,A(b)", 0, (int) M_LA_AB
, INSN_MACRO
},
317 {"lb", "t,o(b)", 0x80000000, 0xfc000000, LDD
|RD_b
|WR_t
},
318 {"lb", "t,A(b)", 0, (int) M_LB_AB
, INSN_MACRO
},
319 {"lbu", "t,o(b)", 0x90000000, 0xfc000000, LDD
|RD_b
|WR_t
},
320 {"lbu", "t,A(b)", 0, (int) M_LBU_AB
, INSN_MACRO
},
321 {"ld", "t,o(b)", 0xdc000000, 0xfc000000, WR_t
|RD_b
|I3
},
322 {"ld", "t,o(b)", 0, (int) M_LD_OB
, INSN_MACRO
},
323 {"ld", "t,A(b)", 0, (int) M_LD_AB
, INSN_MACRO
},
324 {"ldc1", "T,o(b)", 0xd4000000, 0xfc000000, CLD
|RD_b
|WR_T
|I2
},
325 {"ldc1", "E,o(b)", 0xd4000000, 0xfc000000, CLD
|RD_b
|WR_T
|I2
},
326 {"ldc1", "T,A(b)", 2, (int) M_LDC1_AB
, INSN_MACRO
},
327 {"ldc1", "E,A(b)", 2, (int) M_LDC1_AB
, INSN_MACRO
},
328 {"ldc2", "E,o(b)", 0xd8000000, 0xfc000000, CLD
|RD_b
|WR_CC
|I2
},
329 {"ldc2", "E,A(b)", 2, (int) M_LDC2_AB
, INSN_MACRO
},
330 {"ldc3", "E,o(b)", 0xdc000000, 0xfc000000, CLD
|RD_b
|WR_CC
|I2
},
331 {"ldc3", "E,A(b)", 2, (int) M_LDC3_AB
, INSN_MACRO
},
332 {"ldl", "t,o(b)", 0x68000000, 0xfc000000, LDD
|WR_t
|RD_b
|I3
},
333 {"ldl", "t,A(b)", 3, (int) M_LDL_AB
, INSN_MACRO
},
334 {"ldr", "t,o(b)", 0x6c000000, 0xfc000000, LDD
|WR_t
|RD_b
|I3
},
335 {"ldr", "t,A(b)", 3, (int) M_LDR_AB
, INSN_MACRO
},
336 {"lh", "t,o(b)", 0x84000000, 0xfc000000, LDD
|RD_b
|WR_t
},
337 {"lh", "t,A(b)", 0, (int) M_LH_AB
, INSN_MACRO
},
338 {"lhu", "t,o(b)", 0x94000000, 0xfc000000, LDD
|RD_b
|WR_t
},
339 {"lhu", "t,A(b)", 0, (int) M_LHU_AB
, INSN_MACRO
},
340 /* li is at the start of the table. */
341 {"li.d", "t,F", 0, (int) M_LI_D
, INSN_MACRO
},
342 {"li.d", "T,L", 0, (int) M_LI_DD
, INSN_MACRO
},
343 {"li.s", "t,f", 0, (int) M_LI_S
, INSN_MACRO
},
344 {"li.s", "T,l", 0, (int) M_LI_SS
, INSN_MACRO
},
345 {"ll", "t,o(b)", 0xc0000000, 0xfc000000, LDD
|RD_b
|WR_t
|I2
},
346 {"ll", "t,A(b)", 2, (int) M_LL_AB
, INSN_MACRO
},
347 {"lld", "t,o(b)", 0xd0000000, 0xfc000000, LDD
|RD_b
|WR_t
|I3
},
348 {"lld", "t,A(b)", 3, (int) M_LLD_AB
, INSN_MACRO
},
349 {"lui", "t,u", 0x3c000000, 0xffe00000, WR_t
},
350 {"lw", "t,o(b)", 0x8c000000, 0xfc000000, LDD
|RD_b
|WR_t
},
351 {"lw", "t,A(b)", 0, (int) M_LW_AB
, INSN_MACRO
},
352 {"lwc0", "E,o(b)", 0xc0000000, 0xfc000000, CLD
|RD_b
|WR_CC
},
353 {"lwc0", "E,A(b)", 0, (int) M_LWC0_AB
, INSN_MACRO
},
354 {"lwc1", "T,o(b)", 0xc4000000, 0xfc000000, CLD
|RD_b
|WR_T
},
355 {"lwc1", "E,o(b)", 0xc4000000, 0xfc000000, CLD
|RD_b
|WR_T
},
356 {"lwc1", "T,A(b)", 0, (int) M_LWC1_AB
, INSN_MACRO
},
357 {"lwc1", "E,A(b)", 0, (int) M_LWC1_AB
, INSN_MACRO
},
358 {"l.s", "T,o(b)", 0xc4000000, 0xfc000000, CLD
|RD_b
|WR_T
}, /* lwc1 */
359 {"l.s", "T,A(b)", 0, (int) M_LWC1_AB
, INSN_MACRO
},
360 {"lwc2", "E,o(b)", 0xc8000000, 0xfc000000, CLD
|RD_b
|WR_CC
},
361 {"lwc2", "E,A(b)", 0, (int) M_LWC2_AB
, INSN_MACRO
},
362 {"lwc3", "E,o(b)", 0xcc000000, 0xfc000000, CLD
|RD_b
|WR_CC
},
363 {"lwc3", "E,A(b)", 0, (int) M_LWC3_AB
, INSN_MACRO
},
364 {"lwl", "t,o(b)", 0x88000000, 0xfc000000, LDD
|RD_b
|WR_t
},
365 {"lwl", "t,A(b)", 0, (int) M_LWL_AB
, INSN_MACRO
},
366 {"lcache", "t,o(b)", 0x88000000, 0xfc000000, LDD
|RD_b
|WR_t
|I2
}, /* same */
367 {"lcache", "t,A(b)", 2, (int) M_LWL_AB
, INSN_MACRO
}, /* as lwl */
368 {"lwr", "t,o(b)", 0x98000000, 0xfc000000, LDD
|RD_b
|WR_t
},
369 {"lwr", "t,A(b)", 0, (int) M_LWR_AB
, INSN_MACRO
},
370 {"flush", "t,o(b)", 0x98000000, 0xfc000000, LDD
|RD_b
|WR_t
|I2
}, /* same */
371 {"flush", "t,A(b)", 2, (int) M_LWR_AB
, INSN_MACRO
}, /* as lwr */
372 {"lwu", "t,o(b)", 0xbc000000, 0xfc000000, LDD
|RD_b
|WR_t
|I3
},
373 {"lwu", "t,A(b)", 3, (int) M_LWU_AB
, INSN_MACRO
},
374 {"mfc0", "t,G", 0x40000000, 0xffe007ff, LCD
|WR_t
|RD_C0
},
375 {"mfc1", "t,S", 0x44000000, 0xffe007ff, LCD
|WR_t
|RD_S
},
376 {"mfc1", "t,G", 0x44000000, 0xffe007ff, LCD
|WR_t
|RD_S
},
377 {"mfc2", "t,G", 0x48000000, 0xffe007ff, LCD
|WR_t
|RD_C2
},
378 {"mfc3", "t,G", 0x4c000000, 0xffe007ff, LCD
|WR_t
|RD_C3
},
379 {"mfhi", "d", 0x00000010, 0xffff07ff, WR_d
|RD_HI
},
380 {"mflo", "d", 0x00000012, 0xffff07ff, WR_d
|RD_LO
},
381 {"mov.d", "D,S", 0x46200006, 0xffff003f, WR_D
|RD_S
},
382 {"mov.s", "D,S", 0x46000006, 0xffff003f, WR_D
|RD_S
},
383 /* move is at the top of the table. */
384 {"mtc0", "t,G", 0x40800000, 0xffe007ff, COD
|RD_t
|WR_C0
|WR_CC
},
385 {"mtc1", "t,S", 0x44800000, 0xffe007ff, COD
|RD_t
|WR_S
},
386 {"mtc1", "t,G", 0x44800000, 0xffe007ff, COD
|RD_t
|WR_S
},
387 {"mtc2", "t,G", 0x48800000, 0xffe007ff, COD
|RD_t
|WR_C2
|WR_CC
},
388 {"mtc3", "t,G", 0x4c800000, 0xffe007ff, COD
|RD_t
|WR_C3
|WR_CC
},
389 {"mthi", "s", 0x00000011, 0xfc1fffff, RD_s
|WR_HI
},
390 {"mtlo", "s", 0x00000013, 0xfc1fffff, RD_s
|WR_LO
},
391 {"mul.d", "D,V,T", 0x46200002, 0xffe0003f, WR_D
|RD_S
|RD_T
},
392 {"mul.s", "D,V,T", 0x46000002, 0xffe0003f, WR_D
|RD_S
|RD_T
},
393 {"mul", "d,v,t", 0, (int) M_MUL
, INSN_MACRO
},
394 {"mul", "d,v,I", 0, (int) M_MUL_I
, INSN_MACRO
},
395 {"mulo", "d,v,t", 0, (int) M_MULO
, INSN_MACRO
},
396 {"mulo", "d,v,I", 0, (int) M_MULO_I
, INSN_MACRO
},
397 {"mulou", "d,v,t", 0, (int) M_MULOU
, INSN_MACRO
},
398 {"mulou", "d,v,I", 0, (int) M_MULOU_I
, INSN_MACRO
},
399 {"mult", "s,t", 0x00000018, 0xfc00ffff, RD_s
|RD_t
|WR_HI
|WR_LO
},
400 {"multu", "s,t", 0x00000019, 0xfc00ffff, RD_s
|RD_t
|WR_HI
|WR_LO
},
401 {"neg", "d,w", 0x00000022, 0xffe007ff, WR_d
|RD_t
}, /* sub 0 */
402 {"negu", "d,w", 0x00000023, 0xffe007ff, WR_d
|RD_t
}, /* subu 0 */
403 {"neg.d", "D,V", 0x46200007, 0xffff003f, WR_D
|RD_S
},
404 {"neg.s", "D,V", 0x46000007, 0xffff003f, WR_D
|RD_S
},
405 /* nop is at the start of the table. */
406 {"nor", "d,v,t", 0x00000027, 0xfc0007ff, WR_d
|RD_s
|RD_t
},
407 {"nor", "d,v,I", 0, (int) M_NOR_I
, INSN_MACRO
},
408 {"not", "d,v", 0x00000027, 0xfc0007ff, WR_d
|RD_s
|RD_t
}, /* nor d,s,zero */
409 {"or", "d,v,t", 0x00000025, 0xfc0007ff, WR_d
|RD_s
|RD_t
},
410 {"or", "t,r,I", 0, (int) M_OR_I
, INSN_MACRO
},
411 {"ori", "t,r,i", 0x34000000, 0xfc000000, WR_t
|RD_s
},
412 {"rem", "z,s,t", 0x0000001a, 0xfc00ffff, RD_s
|RD_t
|WR_HI
|WR_LO
},
413 {"rem", "d,v,t", 0, (int) M_REM_3
, INSN_MACRO
},
414 {"rem", "d,v,I", 0, (int) M_REM_3I
, INSN_MACRO
},
415 {"remu", "z,s,t", 0x0000001b, 0xfc00ffff, RD_s
|RD_t
|WR_HI
|WR_LO
},
416 {"remu", "d,v,t", 0, (int) M_REMU_3
, INSN_MACRO
},
417 {"remu", "d,v,I", 0, (int) M_REMU_3I
, INSN_MACRO
},
418 {"rfe", "", 0x42000010, 0xffffffff, INSN_RFE
},
419 {"rol", "d,v,t", 0, (int) M_ROL
, INSN_MACRO
},
420 {"rol", "d,v,I", 0, (int) M_ROL_I
, INSN_MACRO
},
421 {"ror", "d,v,t", 0, (int) M_ROR
, INSN_MACRO
},
422 {"ror", "d,v,I", 0, (int) M_ROR_I
, INSN_MACRO
},
423 {"round.l.d", "D,S", 0x46200008, 0xffff003f, WR_D
|RD_S
|I3
},
424 {"round.l.s", "D,S", 0x46000008, 0xffff003f, WR_D
|RD_S
|I3
},
425 {"round.w.d", "D,S", 0x4620000c, 0xffff003f, WR_D
|RD_S
|I2
},
426 {"round.w.s", "D,S", 0x4600000c, 0xffff003f, WR_D
|RD_S
|I2
},
427 {"sb", "t,o(b)", 0xa0000000, 0xfc000000, RD_t
|RD_b
},
428 {"sb", "t,A(b)", 0, (int) M_SB_AB
, INSN_MACRO
},
429 {"sc", "t,o(b)", 0xe0000000, 0xfc000000, RD_t
|RD_b
|I2
},
430 {"sc", "t,A(b)", 2, (int) M_SC_AB
, INSN_MACRO
},
431 {"scd", "t,o(b)", 0xf0000000, 0xfc000000, RD_t
|RD_b
|I3
},
432 {"scd", "t,A(b)", 3, (int) M_SCD_AB
, INSN_MACRO
},
433 {"sd", "t,o(b)", 0xfc000000, 0xfc000000, RD_t
|RD_b
|I3
},
434 {"sd", "t,o(b)", 0, (int) M_SD_OB
, INSN_MACRO
},
435 {"sd", "t,A(b)", 0, (int) M_SD_AB
, INSN_MACRO
},
436 {"sdc1", "T,o(b)", 0xf4000000, 0xfc000000, RD_T
|RD_b
|I2
},
437 {"sdc1", "E,o(b)", 0xf4000000, 0xfc000000, RD_T
|RD_b
|I2
},
438 {"sdc1", "T,A(b)", 2, (int) M_SDC1_AB
, INSN_MACRO
},
439 {"sdc1", "E,A(b)", 2, (int) M_SDC1_AB
, INSN_MACRO
},
440 {"sdc2", "E,o(b)", 0xf8000000, 0xfc000000, RD_C2
|RD_b
|I2
},
441 {"sdc2", "E,A(b)", 2, (int) M_SDC2_AB
, INSN_MACRO
},
442 {"sdc3", "E,o(b)", 0xfc000000, 0xfc000000, RD_C3
|RD_b
|I2
},
443 {"sdc3", "E,A(b)", 2, (int) M_SDC3_AB
, INSN_MACRO
},
444 {"s.d", "T,o(b)", 0xf4000000, 0xfc000000, RD_T
|RD_b
|I2
},
445 {"s.d", "T,o(b)", 0, (int) M_S_DOB
, INSN_MACRO
},
446 {"s.d", "T,A(b)", 0, (int) M_S_DAB
, INSN_MACRO
},
447 {"sdl", "t,o(b)", 0xb0000000, 0xfc000000, RD_t
|RD_b
|I3
},
448 {"sdl", "t,A(b)", 3, (int) M_SDL_AB
, INSN_MACRO
},
449 {"sdr", "t,o(b)", 0xb4000000, 0xfc000000, RD_t
|RD_b
|I3
},
450 {"sdr", "t,A(b)", 3, (int) M_SDR_AB
, INSN_MACRO
},
451 {"seq", "d,v,t", 0, (int) M_SEQ
, INSN_MACRO
},
452 {"seq", "d,v,I", 0, (int) M_SEQ_I
, INSN_MACRO
},
453 {"sge", "d,v,t", 0, (int) M_SGE
, INSN_MACRO
},
454 {"sge", "d,v,I", 0, (int) M_SGE_I
, INSN_MACRO
},
455 {"sgeu", "d,v,t", 0, (int) M_SGEU
, INSN_MACRO
},
456 {"sgeu", "d,v,I", 0, (int) M_SGEU_I
, INSN_MACRO
},
457 {"sgt", "d,v,t", 0, (int) M_SGT
, INSN_MACRO
},
458 {"sgt", "d,v,I", 0, (int) M_SGT_I
, INSN_MACRO
},
459 {"sgtu", "d,v,t", 0, (int) M_SGTU
, INSN_MACRO
},
460 {"sgtu", "d,v,I", 0, (int) M_SGTU_I
, INSN_MACRO
},
461 {"sh", "t,o(b)", 0xa4000000, 0xfc000000, RD_t
|RD_b
},
462 {"sh", "t,A(b)", 0, (int) M_SH_AB
, INSN_MACRO
},
463 {"sle", "d,v,t", 0, (int) M_SLE
, INSN_MACRO
},
464 {"sle", "d,v,I", 0, (int) M_SLE_I
, INSN_MACRO
},
465 {"sleu", "d,v,t", 0, (int) M_SLEU
, INSN_MACRO
},
466 {"sleu", "d,v,I", 0, (int) M_SLEU_I
, INSN_MACRO
},
467 {"sllv", "d,t,s", 0x00000004, 0xfc0007ff, WR_d
|RD_t
|RD_s
},
468 {"sll", "d,w,s", 0x00000004, 0xfc0007ff, WR_d
|RD_t
|RD_s
}, /* sllv */
469 {"sll", "d,w,<", 0x00000000, 0xffe0003f, WR_d
|RD_t
},
470 {"slt", "d,v,t", 0x0000002a, 0xfc0007ff, WR_d
|RD_s
|RD_t
},
471 {"slt", "d,v,I", 0, (int) M_SLT_I
, INSN_MACRO
},
472 {"slti", "t,r,j", 0x28000000, 0xfc000000, WR_t
|RD_s
},
473 {"sltiu", "t,r,j", 0x2c000000, 0xfc000000, WR_t
|RD_s
},
474 {"sltu", "d,v,t", 0x0000002b, 0xfc0007ff, WR_d
|RD_s
|RD_t
},
475 {"sltu", "d,v,I", 0, (int) M_SLTU_I
, INSN_MACRO
},
476 {"sne", "d,v,t", 0, (int) M_SNE
, INSN_MACRO
},
477 {"sne", "d,v,I", 0, (int) M_SNE_I
, INSN_MACRO
},
478 {"sqrt.d", "D,S", 0x46200004, 0xffff003f, WR_D
|RD_S
|I2
},
479 {"sqrt.w", "D,S", 0x46000004, 0xffff003f, WR_D
|RD_S
|I2
},
480 {"srav", "d,t,s", 0x00000007, 0xfc0007ff, WR_d
|RD_t
|RD_s
},
481 {"sra", "d,w,s", 0x00000007, 0xfc0007ff, WR_d
|RD_t
|RD_s
}, /* srav */
482 {"sra", "d,w,<", 0x00000003, 0xffe0003f, WR_d
|RD_t
},
483 {"srlv", "d,t,s", 0x00000006, 0xfc0007ff, WR_d
|RD_t
|RD_s
},
484 {"srl", "d,w,s", 0x00000006, 0xfc0007ff, WR_d
|RD_t
|RD_s
}, /* srlv */
485 {"srl", "d,w,<", 0x00000002, 0xffe0003f, WR_d
|RD_t
},
486 {"sub", "d,v,t", 0x00000022, 0xfc0007ff, WR_d
|RD_s
|RD_t
},
487 {"sub", "d,v,I", 0, (int) M_SUB_I
, INSN_MACRO
},
488 {"sub.d", "D,V,T", 0x46200001, 0xffe0003f, WR_D
|RD_S
|RD_T
},
489 {"sub.s", "D,V,T", 0x46000001, 0xffe0003f, WR_D
|RD_S
|RD_T
},
490 {"subu", "d,v,t", 0x00000023, 0xfc0007ff, WR_d
|RD_s
|RD_t
},
491 {"subu", "d,v,I", 0, (int) M_SUBU_I
, INSN_MACRO
},
492 {"sw", "t,o(b)", 0xac000000, 0xfc000000, RD_t
|RD_b
},
493 {"sw", "t,A(b)", 0, (int) M_SW_AB
, INSN_MACRO
},
494 {"swc0", "E,o(b)", 0xe0000000, 0xfc000000, RD_C0
|RD_b
},
495 {"swc0", "E,A(b)", 0, (int) M_SWC0_AB
, INSN_MACRO
},
496 {"swc1", "T,o(b)", 0xe4000000, 0xfc000000, RD_T
|RD_b
},
497 {"swc1", "E,o(b)", 0xe4000000, 0xfc000000, RD_T
|RD_b
},
498 {"swc1", "T,A(b)", 0, (int) M_SWC1_AB
, INSN_MACRO
},
499 {"swc1", "E,A(b)", 0, (int) M_SWC1_AB
, INSN_MACRO
},
500 {"s.s", "T,o(b)", 0xe4000000, 0xfc000000, RD_T
|RD_b
}, /* swc1 */
501 {"s.s", "T,A(b)", 0, (int) M_SWC1_AB
, INSN_MACRO
},
502 {"swc2", "E,o(b)", 0xe8000000, 0xfc000000, RD_C2
|RD_b
},
503 {"swc2", "E,A(b)", 0, (int) M_SWC2_AB
, INSN_MACRO
},
504 {"swc3", "E,o(b)", 0xec000000, 0xfc000000, RD_C3
|RD_b
},
505 {"swc3", "E,A(b)", 0, (int) M_SWC3_AB
, INSN_MACRO
},
506 {"swl", "t,o(b)", 0xa8000000, 0xfc000000, RD_t
|RD_b
},
507 {"swl", "t,A(b)", 0, (int) M_SWL_AB
, INSN_MACRO
},
508 {"scache", "t,o(b)", 0xa8000000, 0xfc000000, RD_t
|RD_b
|I2
}, /* same */
509 {"scache", "t,A(b)", 2, (int) M_SWL_AB
, INSN_MACRO
}, /* as swl */
510 {"swr", "t,o(b)", 0xb8000000, 0xfc000000, RD_t
|RD_b
},
511 {"swr", "t,A(b)", 0, (int) M_SWR_AB
, INSN_MACRO
},
512 {"invalidate", "t,o(b)",0xb8000000, 0xfc000000, RD_t
|RD_b
|I2
}, /* same */
513 {"invalidate", "t,A(b)",2, (int) M_SWR_AB
, INSN_MACRO
}, /* as swr */
514 {"sync", "", 0x0000000f, 0xffffffff, I2
},
515 {"syscall", "", 0x0000000c, 0xffffffff, INSN_TRAP
},
516 {"syscall", "B", 0x0000000c, 0xfc00003f, INSN_TRAP
},
517 {"teqi", "s,j", 0x040c0000, 0xfc1f0000, RD_s
|I2
},
518 {"teq", "s,t", 0x00000034, 0xfc00003f, RD_s
|RD_t
|I2
},
519 {"teq", "s,j", 0x040c0000, 0xfc1f0000, RD_s
|I2
}, /* teqi */
520 {"teq", "s,I", 2, (int) M_TEQ_I
, INSN_MACRO
},
521 {"tgei", "s,j", 0x04080000, 0xfc1f0000, RD_s
|I2
},
522 {"tge", "s,t", 0x00000030, 0xfc00003f, RD_s
|RD_t
|I2
},
523 {"tge", "s,j", 0x04080000, 0xfc1f0000, RD_s
|I2
}, /* tgei */
524 {"tge", "s,I", 2, (int) M_TGE_I
, INSN_MACRO
},
525 {"tgeiu", "s,j", 0x04090000, 0xfc1f0000, RD_s
|I2
},
526 {"tgeu", "s,t", 0x00000031, 0xfc00003f, RD_s
|RD_t
|I2
},
527 {"tgeu", "s,j", 0x04090000, 0xfc1f0000, RD_s
|I2
}, /* tgeiu */
528 {"tgeu", "s,I", 2, (int) M_TGEU_I
, INSN_MACRO
},
529 {"tlbp", "", 0x42000008, 0xffffffff, INSN_TLB
},
530 {"tlbr", "", 0x42000001, 0xffffffff, INSN_TLB
},
531 {"tlbwi", "", 0x42000002, 0xffffffff, INSN_TLB
},
532 {"tlbwr", "", 0x42000006, 0xffffffff, INSN_TLB
},
533 {"tlti", "s,j", 0x040a0000, 0xfc1f0000, RD_s
|I2
},
534 {"tlt", "s,t", 0x00000032, 0xfc00003f, RD_s
|RD_t
|I2
},
535 {"tlt", "s,j", 0x040a0000, 0xfc1f0000, RD_s
|I2
}, /* tlti */
536 {"tlt", "s,I", 2, (int) M_TLT_I
, INSN_MACRO
},
537 {"tltiu", "s,j", 0x040b0000, 0xfc1f0000, RD_s
|I2
},
538 {"tltu", "s,t", 0x00000033, 0xfc00003f, RD_s
|RD_t
|I2
},
539 {"tltu", "s,j", 0x040b0000, 0xfc1f0000, RD_s
|I2
}, /* tltiu */
540 {"tltu", "s,I", 2, (int) M_TLTU_I
, INSN_MACRO
},
541 {"tnei", "s,j", 0x040e0000, 0xfc1f0000, RD_s
|I2
},
542 {"tne", "s,t", 0x00000036, 0xfc00003f, RD_s
|RD_t
|I2
},
543 {"tne", "s,j", 0x040e0000, 0xfc1f0000, RD_s
|I2
}, /* tnei */
544 {"tne", "s,I", 2, (int) M_TNE_I
, INSN_MACRO
},
545 {"trunc.l.d", "D,S", 0x46200009, 0xffff003f, WR_D
|RD_S
|I3
},
546 {"trunc.l.s", "D,S", 0x46000009, 0xffff003f, WR_D
|RD_S
|I3
},
547 {"trunc.w.d", "D,S", 0x4620000d, 0xffff003f, WR_D
|RD_S
|I2
},
548 {"trunc.w.d", "D,S,x", 0x4620000d, 0xffff003f, WR_D
|RD_S
|I2
},
549 {"trunc.w.d", "D,S,t", 0, (int) M_TRUNCWD
, INSN_MACRO
},
550 {"trunc.w.s", "D,S", 0x4600000d, 0xffff003f, WR_D
|RD_S
|I2
},
551 {"trunc.w.s", "D,S,x", 0x4600000d, 0xffff003f, WR_D
|RD_S
|I2
},
552 {"trunc.w.s", "D,S,t", 0, (int) M_TRUNCWS
, INSN_MACRO
},
553 {"ulh", "t,o(b)", 0, (int) M_ULH
, INSN_MACRO
},
554 {"ulh", "t,A", 0, (int) M_ULH_A
, INSN_MACRO
},
555 {"ulhu", "t,o(b)", 0, (int) M_ULHU
, INSN_MACRO
},
556 {"ulhu", "t,A", 0, (int) M_ULHU_A
, INSN_MACRO
},
557 {"ulw", "t,o(b)", 0, (int) M_ULW
, INSN_MACRO
},
558 {"ulw", "t,A", 0, (int) M_ULW_A
, INSN_MACRO
},
559 {"ush", "t,o(b)", 0, (int) M_USH
, INSN_MACRO
},
560 {"ush", "t,A", 0, (int) M_USH_A
, INSN_MACRO
},
561 {"usw", "t,o(b)", 0, (int) M_USW
, INSN_MACRO
},
562 {"usw", "t,A", 0, (int) M_USW_A
, INSN_MACRO
},
563 {"xor", "d,v,t", 0x00000026, 0xfc0007ff, WR_d
|RD_s
|RD_t
},
564 {"xor", "t,r,I", 0, (int) M_XOR_I
, INSN_MACRO
},
565 {"xori", "t,r,i", 0x38000000, 0xfc000000, WR_t
|RD_s
},
566 /* No hazard protection on coprocessor instructions--they shouldn't
567 change the state of the processor and if they do it's up to the
568 user to put in nops as necessary. These are at the end so that the
569 disasembler recognizes more specific versions first. */
570 {"c0", "C", 0x42000000, 0xfe000000, 0 },
571 {"c1", "C", 0x46000000, 0xfe000000, 0 },
572 {"c2", "C", 0x4a000000, 0xfe000000, 0 },
573 {"c3", "C", 0x4e000000, 0xfe000000, 0 },
576 const int bfd_mips_num_opcodes
=
577 ((sizeof mips_opcodes
) / (sizeof (mips_opcodes
[0])));
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