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opcodes/mips-opc.c: Fix formatting.
[deliverable/binutils-gdb.git] / opcodes / mips-opc.c
1 /* mips.h. Mips opcode list for GDB, the GNU debugger.
2 Copyright 1993, 1994, 1995, 1996, 1997 Free Software Foundation, Inc.
3 Contributed by Ralph Campbell and OSF
4 Commented and modified by Ian Lance Taylor, Cygnus Support
5
6 This file is part of GDB, GAS, and the GNU binutils.
7
8 GDB, GAS, and the GNU binutils are free software; you can redistribute
9 them and/or modify them under the terms of the GNU General Public
10 License as published by the Free Software Foundation; either version
11 1, or (at your option) any later version.
12
13 GDB, GAS, and the GNU binutils are distributed in the hope that they
14 will be useful, but WITHOUT ANY WARRANTY; without even the implied
15 warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See
16 the GNU General Public License for more details.
17
18 You should have received a copy of the GNU General Public License
19 along with this file; see the file COPYING. If not, write to the Free
20 Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
21
22 #include <stdio.h>
23 #include "ansidecl.h"
24 #include "opcode/mips.h"
25
26 /* Short hand so the lines aren't too long. */
27
28 #define LDD INSN_LOAD_MEMORY_DELAY
29 #define LCD INSN_LOAD_COPROC_DELAY
30 #define UBD INSN_UNCOND_BRANCH_DELAY
31 #define CBD INSN_COND_BRANCH_DELAY
32 #define COD INSN_COPROC_MOVE_DELAY
33 #define CLD INSN_COPROC_MEMORY_DELAY
34 #define CBL INSN_COND_BRANCH_LIKELY
35 #define TRAP INSN_TRAP
36 #define SM INSN_STORE_MEMORY
37
38 #define WR_d INSN_WRITE_GPR_D
39 #define WR_t INSN_WRITE_GPR_T
40 #define WR_31 INSN_WRITE_GPR_31
41 #define WR_D INSN_WRITE_FPR_D
42 #define WR_T INSN_WRITE_FPR_T
43 #define WR_S INSN_WRITE_FPR_S
44 #define RD_s INSN_READ_GPR_S
45 #define RD_b INSN_READ_GPR_S
46 #define RD_t INSN_READ_GPR_T
47 #define RD_S INSN_READ_FPR_S
48 #define RD_T INSN_READ_FPR_T
49 #define RD_R INSN_READ_FPR_R
50 #define WR_CC INSN_WRITE_COND_CODE
51 #define RD_CC INSN_READ_COND_CODE
52 #define RD_C0 INSN_COP
53 #define RD_C1 INSN_COP
54 #define RD_C2 INSN_COP
55 #define RD_C3 INSN_COP
56 #define WR_C0 INSN_COP
57 #define WR_C1 INSN_COP
58 #define WR_C2 INSN_COP
59 #define WR_C3 INSN_COP
60 #define WR_HI INSN_WRITE_HI
61 #define WR_LO INSN_WRITE_LO
62 #define RD_HI INSN_READ_HI
63 #define RD_LO INSN_READ_LO
64
65 #define I1 INSN_ISA1
66 #define I2 INSN_ISA2
67 #define I3 INSN_ISA3
68 #define I4 INSN_ISA4
69 #define P3 INSN_4650
70 #define L1 INSN_4010
71 #define V1 INSN_4100
72 #define T3 INSN_3900
73
74 /* start-sanitize-r5900 */
75 #define T5 INSN_5900
76 /* end-sanitize-r5900 */
77
78
79
80 /* The order of overloaded instructions matters. Label arguments and
81 register arguments look the same. Instructions that can have either
82 for arguments must apear in the correct order in this table for the
83 assembler to pick the right one. In other words, entries with
84 immediate operands must apear after the same instruction with
85 registers.
86
87 Many instructions are short hand for other instructions (i.e., The
88 jal <register> instruction is short for jalr <register>). */
89
90 const struct mips_opcode mips_builtin_opcodes[] = {
91 /* These instructions appear first so that the disassembler will find
92 them first. The assemblers uses a hash table based on the
93 instruction name anyhow. */
94 /* name, args, mask, match, pinfo */
95 {"nop", "", 0x00000000, 0xffffffff, 0, I1 },
96 {"li", "t,j", 0x24000000, 0xffe00000, WR_t, I1 }, /* addiu */
97 {"li", "t,i", 0x34000000, 0xffe00000, WR_t, I1 }, /* ori */
98 {"li", "t,I", 0, (int) M_LI, INSN_MACRO },
99 {"move", "d,s", 0x0000002d, 0xfc1f07ff, WR_d|RD_s, I3 },/* daddu */
100 {"move", "d,s", 0x00000021, 0xfc1f07ff, WR_d|RD_s, I1 },/* addu */
101 {"move", "d,s", 0x00000025, 0xfc1f07ff, WR_d|RD_s, I1 },/* or */
102 {"b", "p", 0x10000000, 0xffff0000, UBD, I1 },/* beq 0,0 */
103 {"b", "p", 0x04010000, 0xffff0000, UBD, I1 },/* bgez 0 */
104 {"bal", "p", 0x04110000, 0xffff0000, UBD|WR_31, I1 },/* bgezal 0*/
105
106 {"abs", "d,v", 0, (int) M_ABS, INSN_MACRO },
107 {"abs.s", "D,V", 0x46000005, 0xffff003f, WR_D|RD_S|FP_S, I1 },
108 {"abs.d", "D,V", 0x46200005, 0xffff003f, WR_D|RD_S|FP_D, I1 },
109 {"add", "d,v,t", 0x00000020, 0xfc0007ff, WR_d|RD_s|RD_t, I1 },
110 {"add", "t,r,I", 0, (int) M_ADD_I, INSN_MACRO },
111 {"add.s", "D,V,T", 0x46000000, 0xffe0003f, WR_D|RD_S|RD_T|FP_S, I1},
112 {"add.d", "D,V,T", 0x46200000, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, I1},
113 {"addi", "t,r,j", 0x20000000, 0xfc000000, WR_t|RD_s, I1 },
114 {"addiu", "t,r,j", 0x24000000, 0xfc000000, WR_t|RD_s, I1 },
115 {"addu", "d,v,t", 0x00000021, 0xfc0007ff, WR_d|RD_s|RD_t, I1 },
116 {"addu", "t,r,I", 0, (int) M_ADDU_I, INSN_MACRO },
117 {"and", "d,v,t", 0x00000024, 0xfc0007ff, WR_d|RD_s|RD_t, I1 },
118 {"and", "t,r,I", 0, (int) M_AND_I, INSN_MACRO },
119 {"andi", "t,r,i", 0x30000000, 0xfc000000, WR_t|RD_s, I1 },
120 /* b is at the top of the table. */
121 /* bal is at the top of the table. */
122 {"bc0f", "p", 0x41000000, 0xffff0000, CBD|RD_CC, I1 },
123 {"bc0fl", "p", 0x41020000, 0xffff0000, CBL|RD_CC, I2|T3 },
124 {"bc1f", "p", 0x45000000, 0xffff0000, CBD|RD_CC|FP_S, I1 },
125 {"bc1f", "N,p", 0x45000000, 0xffe30000, CBD|RD_CC|FP_S, I4 },
126 {"bc1fl", "p", 0x45020000, 0xffff0000, CBL|RD_CC|FP_S, I2|T3 },
127 {"bc1fl", "N,p", 0x45020000, 0xffe30000, CBL|RD_CC|FP_S, I4 },
128 {"bc2f", "p", 0x49000000, 0xffff0000, CBD|RD_CC, I1 },
129 {"bc2fl", "p", 0x49020000, 0xffff0000, CBL|RD_CC, I2|T3 },
130 {"bc3f", "p", 0x4d000000, 0xffff0000, CBD|RD_CC, I1 },
131 {"bc3fl", "p", 0x4d020000, 0xffff0000, CBL|RD_CC, I2|T3 },
132 {"bc0t", "p", 0x41010000, 0xffff0000, CBD|RD_CC, I1 },
133 {"bc0tl", "p", 0x41030000, 0xffff0000, CBL|RD_CC, I2|T3 },
134 {"bc1t", "p", 0x45010000, 0xffff0000, CBD|RD_CC|FP_S, I1 },
135 {"bc1t", "N,p", 0x45010000, 0xffe30000, CBD|RD_CC|FP_S, I4 },
136 {"bc1tl", "p", 0x45030000, 0xffff0000, CBL|RD_CC|FP_S, I2|T3 },
137 {"bc1tl", "N,p", 0x45030000, 0xffe30000, CBL|RD_CC|FP_S, I4 },
138 {"bc2t", "p", 0x49010000, 0xffff0000, CBD|RD_CC, I1 },
139 {"bc2tl", "p", 0x49030000, 0xffff0000, CBL|RD_CC, I2|T3 },
140 {"bc3t", "p", 0x4d010000, 0xffff0000, CBD|RD_CC, I1 },
141 {"bc3tl", "p", 0x4d030000, 0xffff0000, CBL|RD_CC, I2|T3 },
142 {"beqz", "s,p", 0x10000000, 0xfc1f0000, CBD|RD_s, I1 },
143 {"beqzl", "s,p", 0x50000000, 0xfc1f0000, CBL|RD_s, I2 },
144 {"beq", "s,t,p", 0x10000000, 0xfc000000, CBD|RD_s|RD_t, I1 },
145 {"beq", "s,I,p", 0, (int) M_BEQ_I, INSN_MACRO },
146 {"beql", "s,t,p", 0x50000000, 0xfc000000, CBL|RD_s|RD_t, I2|T3 },
147 {"beql", "s,I,p", 2, (int) M_BEQL_I, INSN_MACRO },
148 {"bge", "s,t,p", 0, (int) M_BGE, INSN_MACRO },
149 {"bge", "s,I,p", 0, (int) M_BGE_I, INSN_MACRO },
150 {"bgel", "s,t,p", 2, (int) M_BGEL, INSN_MACRO },
151 {"bgel", "s,I,p", 2, (int) M_BGEL_I, INSN_MACRO },
152 {"bgeu", "s,t,p", 0, (int) M_BGEU, INSN_MACRO },
153 {"bgeu", "s,I,p", 0, (int) M_BGEU_I, INSN_MACRO },
154 {"bgeul", "s,t,p", 2, (int) M_BGEUL, INSN_MACRO },
155 {"bgeul", "s,I,p", 2, (int) M_BGEUL_I, INSN_MACRO },
156 {"bgez", "s,p", 0x04010000, 0xfc1f0000, CBD|RD_s, I1 },
157 {"bgezl", "s,p", 0x04030000, 0xfc1f0000, CBL|RD_s, I2|T3 },
158 {"bgezal", "s,p", 0x04110000, 0xfc1f0000, CBD|RD_s|WR_31, I1 },
159 {"bgezall", "s,p", 0x04130000, 0xfc1f0000, CBL|RD_s, I2|T3 },
160 {"bgt", "s,t,p", 0, (int) M_BGT, INSN_MACRO },
161 {"bgt", "s,I,p", 0, (int) M_BGT_I, INSN_MACRO },
162 {"bgtl", "s,t,p", 2, (int) M_BGTL, INSN_MACRO },
163 {"bgtl", "s,I,p", 2, (int) M_BGTL_I, INSN_MACRO },
164 {"bgtu", "s,t,p", 0, (int) M_BGTU, INSN_MACRO },
165 {"bgtu", "s,I,p", 0, (int) M_BGTU_I, INSN_MACRO },
166 {"bgtul", "s,t,p", 2, (int) M_BGTUL, INSN_MACRO },
167 {"bgtul", "s,I,p", 2, (int) M_BGTUL_I, INSN_MACRO },
168 {"bgtz", "s,p", 0x1c000000, 0xfc1f0000, CBD|RD_s, I1 },
169 {"bgtzl", "s,p", 0x5c000000, 0xfc1f0000, CBL|RD_s, I2|T3 },
170 {"ble", "s,t,p", 0, (int) M_BLE, INSN_MACRO },
171 {"ble", "s,I,p", 0, (int) M_BLE_I, INSN_MACRO },
172 {"blel", "s,t,p", 2, (int) M_BLEL, INSN_MACRO },
173 {"blel", "s,I,p", 2, (int) M_BLEL_I, INSN_MACRO },
174 {"bleu", "s,t,p", 0, (int) M_BLEU, INSN_MACRO },
175 {"bleu", "s,I,p", 0, (int) M_BLEU_I, INSN_MACRO },
176 {"bleul", "s,t,p", 2, (int) M_BLEUL, INSN_MACRO },
177 {"bleul", "s,I,p", 2, (int) M_BLEUL_I, INSN_MACRO },
178 {"blez", "s,p", 0x18000000, 0xfc1f0000, CBD|RD_s, I1 },
179 {"blezl", "s,p", 0x58000000, 0xfc1f0000, CBL|RD_s, I2|T3 },
180 {"blt", "s,t,p", 0, (int) M_BLT, INSN_MACRO },
181 {"blt", "s,I,p", 0, (int) M_BLT_I, INSN_MACRO },
182 {"bltl", "s,t,p", 2, (int) M_BLTL, INSN_MACRO },
183 {"bltl", "s,I,p", 2, (int) M_BLTL_I, INSN_MACRO },
184 {"bltu", "s,t,p", 0, (int) M_BLTU, INSN_MACRO },
185 {"bltu", "s,I,p", 0, (int) M_BLTU_I, INSN_MACRO },
186 {"bltul", "s,t,p", 2, (int) M_BLTUL, INSN_MACRO },
187 {"bltul", "s,I,p", 2, (int) M_BLTUL_I, INSN_MACRO },
188 {"bltz", "s,p", 0x04000000, 0xfc1f0000, CBD|RD_s, I1 },
189 {"bltzl", "s,p", 0x04020000, 0xfc1f0000, CBL|RD_s, I2|T3 },
190 {"bltzal", "s,p", 0x04100000, 0xfc1f0000, CBD|RD_s|WR_31, I1 },
191 {"bltzall", "s,p", 0x04120000, 0xfc1f0000, CBL|RD_s, I2|T3 },
192 {"bnez", "s,p", 0x14000000, 0xfc1f0000, CBD|RD_s, I1 },
193 {"bnezl", "s,p", 0x54000000, 0xfc1f0000, CBL|RD_s, I2 },
194 {"bne", "s,t,p", 0x14000000, 0xfc000000, CBD|RD_s|RD_t, I1 },
195 {"bne", "s,I,p", 0, (int) M_BNE_I, INSN_MACRO },
196 {"bnel", "s,t,p", 0x54000000, 0xfc000000, CBL|RD_s|RD_t, I2|T3 },
197 {"bnel", "s,I,p", 2, (int) M_BNEL_I, INSN_MACRO },
198 {"break", "", 0x0000000d, 0xffffffff, TRAP, I1 },
199 {"break", "c", 0x0000000d, 0xfc00003f, TRAP, I1 },
200 {"c.f.d", "S,T", 0x46200030, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, I1 },
201 {"c.f.d", "M,S,T", 0x46200030, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I4 },
202 {"c.f.s", "S,T", 0x46000030, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, I1 },
203 {"c.f.s", "M,S,T", 0x46000030, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, I4 },
204 {"c.un.d", "S,T", 0x46200031, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, I1 },
205 {"c.un.d", "M,S,T", 0x46200031, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I4 },
206 {"c.un.s", "S,T", 0x46000031, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, I1 },
207 {"c.un.s", "M,S,T", 0x46000031, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, I4 },
208 {"c.eq.d", "S,T", 0x46200032, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, I1 },
209 {"c.eq.d", "M,S,T", 0x46200032, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I4 },
210 {"c.eq.s", "S,T", 0x46000032, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, I1 },
211 {"c.eq.s", "M,S,T", 0x46000032, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, I4 },
212 {"c.ueq.d", "S,T", 0x46200033, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, I1 },
213 {"c.ueq.d", "M,S,T", 0x46200033, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I4 },
214 {"c.ueq.s", "S,T", 0x46000033, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, I1 },
215 {"c.ueq.s", "M,S,T", 0x46000033, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, I4 },
216 {"c.olt.d", "S,T", 0x46200034, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, I1 },
217 {"c.olt.d", "M,S,T", 0x46200034, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I4 },
218 {"c.olt.s", "S,T", 0x46000034, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, I1 },
219 {"c.olt.s", "M,S,T", 0x46000034, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, I4 },
220 {"c.ult.d", "S,T", 0x46200035, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, I1 },
221 {"c.ult.d", "M,S,T", 0x46200035, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I4 },
222 {"c.ult.s", "S,T", 0x46000035, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, I1 },
223 {"c.ult.s", "M,S,T", 0x46000035, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, I4 },
224 {"c.ole.d", "S,T", 0x46200036, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, I1 },
225 {"c.ole.d", "M,S,T", 0x46200036, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I4 },
226 {"c.ole.s", "S,T", 0x46000036, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, I1 },
227 {"c.ole.s", "M,S,T", 0x46000036, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, I4 },
228 {"c.ule.d", "S,T", 0x46200037, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, I1 },
229 {"c.ule.d", "M,S,T", 0x46200037, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I4 },
230 {"c.ule.s", "S,T", 0x46000037, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, I1 },
231 {"c.ule.s", "M,S,T", 0x46000037, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, I4 },
232 {"c.sf.d", "S,T", 0x46200038, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, I1 },
233 {"c.sf.d", "M,S,T", 0x46200038, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I4 },
234 {"c.sf.s", "S,T", 0x46000038, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, I1 },
235 {"c.sf.s", "M,S,T", 0x46000038, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, I4 },
236 {"c.ngle.d","S,T", 0x46200039, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, I1 },
237 {"c.ngle.d","M,S,T", 0x46200039, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I4 },
238 {"c.ngle.s","S,T", 0x46000039, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, I1 },
239 {"c.ngle.s","M,S,T", 0x46000039, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, I4 },
240 {"c.seq.d", "S,T", 0x4620003a, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, I1 },
241 {"c.seq.d", "M,S,T", 0x4620003a, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I4 },
242 {"c.seq.s", "S,T", 0x4600003a, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, I1 },
243 {"c.seq.s", "M,S,T", 0x4600003a, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, I4 },
244 {"c.ngl.d", "S,T", 0x4620003b, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, I1 },
245 {"c.ngl.d", "M,S,T", 0x4620003b, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I4 },
246 {"c.ngl.s", "S,T", 0x4600003b, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, I1 },
247 {"c.ngl.s", "M,S,T", 0x4600003b, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, I4 },
248 {"c.lt.d", "S,T", 0x4620003c, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, I1 },
249 {"c.lt.d", "M,S,T", 0x4620003c, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I4 },
250 {"c.lt.s", "S,T", 0x4600003c, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, I1 },
251 {"c.lt.s", "M,S,T", 0x4600003c, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, I4 },
252 {"c.nge.d", "S,T", 0x4620003d, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, I1 },
253 {"c.nge.d", "M,S,T", 0x4620003d, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I4 },
254 {"c.nge.s", "S,T", 0x4600003d, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, I1 },
255 {"c.nge.s", "M,S,T", 0x4600003d, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, I4 },
256 {"c.le.d", "S,T", 0x4620003e, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, I1 },
257 {"c.le.d", "M,S,T", 0x4620003e, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I4 },
258 {"c.le.s", "S,T", 0x4600003e, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, I1 },
259 {"c.le.s", "M,S,T", 0x4600003e, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, I4 },
260 {"c.ngt.d", "S,T", 0x4620003f, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, I1 },
261 {"c.ngt.d", "M,S,T", 0x4620003f, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I4 },
262 {"c.ngt.s", "S,T", 0x4600003f, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, I1 },
263 {"c.ngt.s", "M,S,T", 0x4600003f, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, I4 },
264 {"cache", "k,o(b)", 0xbc000000, 0xfc000000, RD_b, I3 },
265 {"ceil.l.d", "D,S", 0x4620000a, 0xffff003f, WR_D|RD_S|FP_D, I3 },
266 {"ceil.l.s", "D,S", 0x4600000a, 0xffff003f, WR_D|RD_S|FP_S, I3 },
267 {"ceil.w.d", "D,S", 0x4620000e, 0xffff003f, WR_D|RD_S|FP_D, I2 },
268 {"ceil.w.s", "D,S", 0x4600000e, 0xffff003f, WR_D|RD_S|FP_S, I2 },
269 {"cfc0", "t,G", 0x40400000, 0xffe007ff, LCD|WR_t|RD_C0, I1 },
270 {"cfc1", "t,G", 0x44400000, 0xffe007ff, LCD|WR_t|RD_C1|FP_S, I1 },
271 {"cfc1", "t,S", 0x44400000, 0xffe007ff, LCD|WR_t|RD_C1|FP_S, I1 },
272 {"cfc2", "t,G", 0x48400000, 0xffe007ff, LCD|WR_t|RD_C2, I1 },
273 {"cfc3", "t,G", 0x4c400000, 0xffe007ff, LCD|WR_t|RD_C3, I1 },
274 {"ctc0", "t,G", 0x40c00000, 0xffe007ff, COD|RD_t|WR_CC, I1 },
275 {"ctc1", "t,G", 0x44c00000, 0xffe007ff, COD|RD_t|WR_CC|FP_S, I1 },
276 {"ctc1", "t,S", 0x44c00000, 0xffe007ff, COD|RD_t|WR_CC|FP_S, I1 },
277 {"ctc2", "t,G", 0x48c00000, 0xffe007ff, COD|RD_t|WR_CC, I1 },
278 {"ctc3", "t,G", 0x4cc00000, 0xffe007ff, COD|RD_t|WR_CC, I1 },
279 {"cvt.d.l", "D,S", 0x46a00021, 0xffff003f, WR_D|RD_S|FP_D, I3 },
280 {"cvt.d.s", "D,S", 0x46000021, 0xffff003f, WR_D|RD_S|FP_D|FP_S, I1 },
281 {"cvt.d.w", "D,S", 0x46800021, 0xffff003f, WR_D|RD_S|FP_D, I1 },
282 {"cvt.l.d", "D,S", 0x46200025, 0xffff003f, WR_D|RD_S|FP_D, I3 },
283 {"cvt.l.s", "D,S", 0x46000025, 0xffff003f, WR_D|RD_S|FP_S, I3 },
284 {"cvt.s.l", "D,S", 0x46a00020, 0xffff003f, WR_D|RD_S|FP_S, I3 },
285 {"cvt.s.d", "D,S", 0x46200020, 0xffff003f, WR_D|RD_S|FP_S|FP_D, I1 },
286 {"cvt.s.w", "D,S", 0x46800020, 0xffff003f, WR_D|RD_S|FP_S, I1 },
287 {"cvt.w.d", "D,S", 0x46200024, 0xffff003f, WR_D|RD_S|FP_D, I1 },
288 {"cvt.w.s", "D,S", 0x46000024, 0xffff003f, WR_D|RD_S|FP_S, I1 },
289 {"dabs", "d,v", 3, (int) M_DABS, INSN_MACRO },
290 {"dadd", "d,v,t", 0x0000002c, 0xfc0007ff, WR_d|RD_s|RD_t, I3 },
291 {"dadd", "t,r,I", 3, (int) M_DADD_I, INSN_MACRO },
292 {"daddi", "t,r,j", 0x60000000, 0xfc000000, WR_t|RD_s, I3 },
293 {"daddiu", "t,r,j", 0x64000000, 0xfc000000, WR_t|RD_s, I3 },
294 {"daddu", "d,v,t", 0x0000002d, 0xfc0007ff, WR_d|RD_s|RD_t, I3 },
295 {"daddu", "t,r,I", 3, (int) M_DADDU_I, INSN_MACRO },
296 /* dctr and dctw are used on the r5000. */
297 {"dctr", "o(b)", 0xbc050000, 0xfc1f0000, RD_b, I3 },
298 {"dctw", "o(b)", 0xbc090000, 0xfc1f0000, RD_b, I3 },
299 {"deret", "", 0x4200001f, 0xffffffff, 0, T3 },
300 /* For ddiv, see the comments about div. */
301 {"ddiv", "z,s,t", 0x0000001e, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO, I3 },
302 {"ddiv", "d,v,t", 3, (int) M_DDIV_3, INSN_MACRO },
303 {"ddiv", "d,v,I", 3, (int) M_DDIV_3I, INSN_MACRO },
304 /* For ddivu, see the comments about div. */
305 {"ddivu", "z,s,t", 0x0000001f, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO, I3 },
306 {"ddivu", "d,v,t", 3, (int) M_DDIVU_3, INSN_MACRO },
307 {"ddivu", "d,v,I", 3, (int) M_DDIVU_3I, INSN_MACRO },
308 /* The MIPS assembler treats the div opcode with two operands as
309 though the first operand appeared twice (the first operand is both
310 a source and a destination). To get the div machine instruction,
311 you must use an explicit destination of $0. */
312 {"div", "z,s,t", 0x0000001a, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO, I1 },
313 {"div", "z,t", 0x0000001a, 0xffe0ffff, RD_s|RD_t|WR_HI|WR_LO, I1 },
314 {"div", "d,v,t", 0, (int) M_DIV_3, INSN_MACRO },
315 {"div", "d,v,I", 0, (int) M_DIV_3I, INSN_MACRO },
316 /* start-sanitize-r5900 */
317 {"div1", "s,t", 0x7000001a, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO, T5 },
318 /* end-sanitize-r5900 */
319 {"div.d", "D,V,T", 0x46200003, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, I1 },
320 {"div.s", "D,V,T", 0x46000003, 0xffe0003f, WR_D|RD_S|RD_T|FP_S, I1 },
321 /* For divu, see the comments about div. */
322 {"divu", "z,s,t", 0x0000001b, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO, I1 },
323 {"divu", "z,t", 0x0000001b, 0xffe0ffff, RD_s|RD_t|WR_HI|WR_LO, I1 },
324 {"divu", "d,v,t", 0, (int) M_DIVU_3, INSN_MACRO },
325 {"divu", "d,v,I", 0, (int) M_DIVU_3I, INSN_MACRO },
326 /* start-sanitize-r5900 */
327 {"divu1", "s,t", 0x7000001b, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO, T5 },
328 /* end-sanitize-r5900 */
329 {"dla", "t,A(b)", 3, (int) M_DLA_AB, INSN_MACRO },
330 {"dli", "t,j", 0x24000000, 0xffe00000, WR_t, I3 }, /* addiu */
331 {"dli", "t,i", 0x34000000, 0xffe00000, WR_t, I3 }, /* ori */
332 {"dli", "t,I", 3, (int) M_DLI, INSN_MACRO },
333 {"dmadd16", "s,t", 0x00000029, 0xfc00ffff, RD_s|RD_t|WR_LO|RD_LO, V1 },
334 {"dmfc0", "t,G", 0x40200000, 0xffe007ff, LCD|WR_t|RD_C0, I3 },
335 {"dmtc0", "t,G", 0x40a00000, 0xffe007ff, COD|RD_t|WR_C0|WR_CC, I3 },
336 {"dmfc1", "t,S", 0x44200000, 0xffe007ff, LCD|WR_t|RD_S|FP_S, I3 },
337 {"dmtc1", "t,S", 0x44a00000, 0xffe007ff, COD|RD_t|WR_S|FP_S, I3 },
338 {"dmul", "d,v,t", 3, (int) M_DMUL, INSN_MACRO },
339 {"dmul", "d,v,I", 3, (int) M_DMUL_I, INSN_MACRO },
340 {"dmulo", "d,v,t", 3, (int) M_DMULO, INSN_MACRO },
341 {"dmulo", "d,v,I", 3, (int) M_DMULO_I, INSN_MACRO },
342 {"dmulou", "d,v,t", 3, (int) M_DMULOU, INSN_MACRO },
343 {"dmulou", "d,v,I", 3, (int) M_DMULOU_I, INSN_MACRO },
344 {"dmult", "s,t", 0x0000001c, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO, I3 },
345 {"dmultu", "s,t", 0x0000001d, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO, I3 },
346 {"dneg", "d,w", 0x0000002e, 0xffe007ff, WR_d|RD_t, I3 }, /* dsub 0 */
347 {"dnegu", "d,w", 0x0000002f, 0xffe007ff, WR_d|RD_t, I3 }, /* dsubu 0*/
348 {"drem", "z,s,t", 0x0000001e, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO, I3 },
349 {"drem", "d,v,t", 3, (int) M_DREM_3, INSN_MACRO },
350 {"drem", "d,v,I", 3, (int) M_DREM_3I, INSN_MACRO },
351 {"dremu", "z,s,t", 0x0000001f, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO, I3 },
352 {"dremu", "d,v,t", 3, (int) M_DREMU_3, INSN_MACRO },
353 {"dremu", "d,v,I", 3, (int) M_DREMU_3I, INSN_MACRO },
354 {"dsllv", "d,t,s", 0x00000014, 0xfc0007ff, WR_d|RD_t|RD_s, I3 },
355 {"dsll32", "d,w,<", 0x0000003c, 0xffe0003f, WR_d|RD_t, I3 },
356 {"dsll", "d,w,s", 0x00000014, 0xfc0007ff, WR_d|RD_t|RD_s, I3 }, /* dsllv */
357 {"dsll", "d,w,>", 0x0000003c, 0xffe0003f, WR_d|RD_t, I3 }, /* dsll32 */
358 {"dsll", "d,w,<", 0x00000038, 0xffe0003f, WR_d|RD_t, I3 },
359 {"dsrav", "d,t,s", 0x00000017, 0xfc0007ff, WR_d|RD_t|RD_s, I3 },
360 {"dsra32", "d,w,<", 0x0000003f, 0xffe0003f, WR_d|RD_t, I3 },
361 {"dsra", "d,w,s", 0x00000017, 0xfc0007ff, WR_d|RD_t|RD_s, I3 }, /* dsrav */
362 {"dsra", "d,w,>", 0x0000003f, 0xffe0003f, WR_d|RD_t, I3 }, /* dsra32 */
363 {"dsra", "d,w,<", 0x0000003b, 0xffe0003f, WR_d|RD_t, I3 },
364 {"dsrlv", "d,t,s", 0x00000016, 0xfc0007ff, WR_d|RD_t|RD_s, I3 },
365 {"dsrl32", "d,w,<", 0x0000003e, 0xffe0003f, WR_d|RD_t, I3 },
366 {"dsrl", "d,w,s", 0x00000016, 0xfc0007ff, WR_d|RD_t|RD_s, I3 }, /* dsrlv */
367 {"dsrl", "d,w,>", 0x0000003e, 0xffe0003f, WR_d|RD_t, I3 }, /* dsrl32 */
368 {"dsrl", "d,w,<", 0x0000003a, 0xffe0003f, WR_d|RD_t, I3 },
369 {"dsub", "d,v,t", 0x0000002e, 0xfc0007ff, WR_d|RD_s|RD_t, I3 },
370 {"dsub", "d,v,I", 3, (int) M_DSUB_I, INSN_MACRO },
371 {"dsubu", "d,v,t", 0x0000002f, 0xfc0007ff, WR_d|RD_s|RD_t, I3 },
372 {"dsubu", "d,v,I", 3, (int) M_DSUBU_I, INSN_MACRO },
373 {"eret", "", 0x42000018, 0xffffffff, 0, I3 },
374 {"floor.l.d", "D,S", 0x4620000b, 0xffff003f, WR_D|RD_S|FP_D, I3 },
375 {"floor.l.s", "D,S", 0x4600000b, 0xffff003f, WR_D|RD_S|FP_S, I3 },
376 {"floor.w.d", "D,S", 0x4620000f, 0xffff003f, WR_D|RD_S|FP_D, I2 },
377 {"floor.w.s", "D,S", 0x4600000f, 0xffff003f, WR_D|RD_S|FP_S, I2 },
378 {"flushi", "", 0xbc010000, 0xffffffff, 0, L1 },
379 {"flushd", "", 0xbc020000, 0xffffffff, 0, L1 },
380 {"flushid", "", 0xbc030000, 0xffffffff, 0, L1 },
381 {"hibernate","", 0x42000023, 0xffffffff, 0, V1 },
382 {"jr", "s", 0x00000008, 0xfc1fffff, UBD|RD_s, I1 },
383 {"j", "s", 0x00000008, 0xfc1fffff, UBD|RD_s, I1 }, /* jr */
384 /* SVR4 PIC code requires special handling for j, so it must be a
385 macro. */
386 {"j", "a", 0, (int) M_J_A, INSN_MACRO },
387 /* This form of j is used by the disassembler and internally by the
388 assembler, but will never match user input (because the line above
389 will match first). */
390 {"j", "a", 0x08000000, 0xfc000000, UBD, I1 },
391 {"jalr", "s", 0x0000f809, 0xfc1fffff, UBD|RD_s|WR_d, I1 },
392 {"jalr", "d,s", 0x00000009, 0xfc1f07ff, UBD|RD_s|WR_d, I1 },
393 /* SVR4 PIC code requires special handling for jal, so it must be a
394 macro. */
395 {"jal", "d,s", 0, (int) M_JAL_2, INSN_MACRO },
396 {"jal", "s", 0, (int) M_JAL_1, INSN_MACRO },
397 {"jal", "a", 0, (int) M_JAL_A, INSN_MACRO },
398 /* This form of jal is used by the disassembler and internally by the
399 assembler, but will never match user input (because the line above
400 will match first). */
401 {"jal", "a", 0x0c000000, 0xfc000000, UBD|WR_31, I1 },
402 {"jalx", "a", 0x74000000, 0xfc000000, UBD|WR_31, I1 },
403 {"la", "t,A(b)", 0, (int) M_LA_AB, INSN_MACRO },
404 {"lb", "t,o(b)", 0x80000000, 0xfc000000, LDD|RD_b|WR_t, I1 },
405 {"lb", "t,A(b)", 0, (int) M_LB_AB, INSN_MACRO },
406 {"lbu", "t,o(b)", 0x90000000, 0xfc000000, LDD|RD_b|WR_t, I1 },
407 {"lbu", "t,A(b)", 0, (int) M_LBU_AB, INSN_MACRO },
408 {"ld", "t,o(b)", 0xdc000000, 0xfc000000, WR_t|RD_b, I3 },
409 {"ld", "t,o(b)", 0, (int) M_LD_OB, INSN_MACRO },
410 {"ld", "t,A(b)", 0, (int) M_LD_AB, INSN_MACRO },
411 {"ldc1", "T,o(b)", 0xd4000000, 0xfc000000, CLD|RD_b|WR_T|FP_D, I2 },
412 {"ldc1", "E,o(b)", 0xd4000000, 0xfc000000, CLD|RD_b|WR_T|FP_D, I2 },
413 {"ldc1", "T,A(b)", 2, (int) M_LDC1_AB, INSN_MACRO },
414 {"ldc1", "E,A(b)", 2, (int) M_LDC1_AB, INSN_MACRO },
415 {"l.d", "T,o(b)", 0xd4000000, 0xfc000000, CLD|RD_b|WR_T|FP_D, I2 }, /* ldc1 */
416 {"l.d", "T,o(b)", 0, (int) M_L_DOB, INSN_MACRO },
417 {"l.d", "T,A(b)", 0, (int) M_L_DAB, INSN_MACRO },
418 {"ldc2", "E,o(b)", 0xd8000000, 0xfc000000, CLD|RD_b|WR_CC, I2 },
419 {"ldc2", "E,A(b)", 2, (int) M_LDC2_AB, INSN_MACRO },
420 {"ldc3", "E,o(b)", 0xdc000000, 0xfc000000, CLD|RD_b|WR_CC, I2 },
421 {"ldc3", "E,A(b)", 2, (int) M_LDC3_AB, INSN_MACRO },
422 {"ldl", "t,o(b)", 0x68000000, 0xfc000000, LDD|WR_t|RD_b, I3 },
423 {"ldl", "t,A(b)", 3, (int) M_LDL_AB, INSN_MACRO },
424 {"ldr", "t,o(b)", 0x6c000000, 0xfc000000, LDD|WR_t|RD_b, I3 },
425 {"ldr", "t,A(b)", 3, (int) M_LDR_AB, INSN_MACRO },
426 {"ldxc1", "D,t(b)", 0x4c000001, 0xfc00f83f, LDD|WR_D|RD_t|RD_b, I4 },
427 {"lh", "t,o(b)", 0x84000000, 0xfc000000, LDD|RD_b|WR_t, I1 },
428 {"lh", "t,A(b)", 0, (int) M_LH_AB, INSN_MACRO },
429 {"lhu", "t,o(b)", 0x94000000, 0xfc000000, LDD|RD_b|WR_t, I1 },
430 {"lhu", "t,A(b)", 0, (int) M_LHU_AB, INSN_MACRO },
431 /* li is at the start of the table. */
432 {"li.d", "t,F", 0, (int) M_LI_D, INSN_MACRO },
433 {"li.d", "T,L", 0, (int) M_LI_DD, INSN_MACRO },
434 {"li.s", "t,f", 0, (int) M_LI_S, INSN_MACRO },
435 {"li.s", "T,l", 0, (int) M_LI_SS, INSN_MACRO },
436 {"ll", "t,o(b)", 0xc0000000, 0xfc000000, LDD|RD_b|WR_t, I2 },
437 {"ll", "t,A(b)", 2, (int) M_LL_AB, INSN_MACRO },
438 {"lld", "t,o(b)", 0xd0000000, 0xfc000000, LDD|RD_b|WR_t, I3 },
439 {"lld", "t,A(b)", 3, (int) M_LLD_AB, INSN_MACRO },
440 {"lui", "t,u", 0x3c000000, 0xffe00000, WR_t, I1 },
441 /* start-sanitize-r5900 */
442 {"lq", "t,o(b)", 0x78000000, 0xfc000000, WR_t|RD_b, T5 },
443 /* end-sanitize-r5900 */
444 {"lw", "t,o(b)", 0x8c000000, 0xfc000000, LDD|RD_b|WR_t, I1 },
445 {"lw", "t,A(b)", 0, (int) M_LW_AB, INSN_MACRO },
446 {"lwc0", "E,o(b)", 0xc0000000, 0xfc000000, CLD|RD_b|WR_CC, I1 },
447 {"lwc0", "E,A(b)", 0, (int) M_LWC0_AB, INSN_MACRO },
448 {"lwc1", "T,o(b)", 0xc4000000, 0xfc000000, CLD|RD_b|WR_T|FP_S, I1 },
449 {"lwc1", "E,o(b)", 0xc4000000, 0xfc000000, CLD|RD_b|WR_T|FP_S, I1 },
450 {"lwc1", "T,A(b)", 0, (int) M_LWC1_AB, INSN_MACRO },
451 {"lwc1", "E,A(b)", 0, (int) M_LWC1_AB, INSN_MACRO },
452 {"l.s", "T,o(b)", 0xc4000000, 0xfc000000, CLD|RD_b|WR_T|FP_S, I1 }, /* lwc1 */
453 {"l.s", "T,A(b)", 0, (int) M_LWC1_AB, INSN_MACRO },
454 {"lwc2", "E,o(b)", 0xc8000000, 0xfc000000, CLD|RD_b|WR_CC, I1 },
455 {"lwc2", "E,A(b)", 0, (int) M_LWC2_AB, INSN_MACRO },
456 {"lwc3", "E,o(b)", 0xcc000000, 0xfc000000, CLD|RD_b|WR_CC, I1 },
457 {"lwc3", "E,A(b)", 0, (int) M_LWC3_AB, INSN_MACRO },
458 {"lwl", "t,o(b)", 0x88000000, 0xfc000000, LDD|RD_b|WR_t, I1 },
459 {"lwl", "t,A(b)", 0, (int) M_LWL_AB, INSN_MACRO },
460 {"lcache", "t,o(b)", 0x88000000, 0xfc000000, LDD|RD_b|WR_t, I2 }, /* same */
461 {"lcache", "t,A(b)", 2, (int) M_LWL_AB, INSN_MACRO }, /* as lwl */
462 {"lwr", "t,o(b)", 0x98000000, 0xfc000000, LDD|RD_b|WR_t, I1 },
463 {"lwr", "t,A(b)", 0, (int) M_LWR_AB, INSN_MACRO },
464 {"flush", "t,o(b)", 0x98000000, 0xfc000000, LDD|RD_b|WR_t, I2 }, /* same */
465 {"flush", "t,A(b)", 2, (int) M_LWR_AB, INSN_MACRO }, /* as lwr */
466 {"lwu", "t,o(b)", 0x9c000000, 0xfc000000, LDD|RD_b|WR_t, I3 },
467 {"lwu", "t,A(b)", 3, (int) M_LWU_AB, INSN_MACRO },
468 {"lwxc1", "D,t(b)", 0x4c000000, 0xfc00f83f, LDD|WR_D|RD_t|RD_b, I4 },
469 {"mad", "s,t", 0x70000000, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO|RD_HI|RD_LO, P3 },
470 {"madu", "s,t", 0x70000001, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO|RD_HI|RD_LO, P3 },
471 {"addciu", "t,r,j", 0x70000000, 0xfc000000, WR_t|RD_s,L1 },
472 {"madd.d", "D,R,S,T", 0x4c000021, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D, I4 },
473 {"madd.s", "D,R,S,T", 0x4c000020, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_S, I4 },
474 /* start-sanitize-r5900 */
475 {"madd.s", "D,R,S,T", 0x4c000020, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_S, T5 },
476 /* end-sanitize-r5900 */
477 {"madd", "s,t", 0x0000001c, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO, L1 },
478 {"madd", "s,t", 0x70000000, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO, T3 },
479 {"madd", "d,s,t", 0x70000000, 0xfc0007ff, RD_s|RD_t|WR_HI|WR_LO|WR_d, T3 },
480 /* start-sanitize-r5900 */
481 {"madd", "s,t", 0x70000000, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO, T5 },
482 {"madd", "d,s,t", 0x70000000, 0xfc0007ff, RD_s|RD_t|WR_HI|WR_LO|WR_d, T5 },
483 {"madd1", "s,t", 0x70000020, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO, T5 },
484 {"madd1", "d,s,t", 0x70000020, 0xfc0007ff, RD_s|RD_t|WR_HI|WR_LO|WR_d, T5 },
485 /* end-sanitize-r5900 */
486 {"maddu", "s,t", 0x0000001d, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO, L1 },
487 {"maddu", "s,t", 0x70000001, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO, T3 },
488 {"maddu", "d,s,t", 0x70000001, 0xfc0007ff, RD_s|RD_t|WR_HI|WR_LO|WR_d, T3 },
489 /* start-sanitize-r5900 */
490 {"maddu", "s,t", 0x70000001, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO, T5 },
491 {"maddu", "d,s,t", 0x70000001, 0xfc0007ff, RD_s|RD_t|WR_HI|WR_LO|WR_d, T5 },
492 {"maddu1", "s,t", 0x70000021, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO, T5 },
493 {"maddu1", "d,s,t", 0x70000021, 0xfc0007ff, RD_s|RD_t|WR_HI|WR_LO|WR_d, T5 },
494 /* end-sanitize-r5900 */
495 {"madd16", "s,t", 0x00000028, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO|RD_HI|RD_LO, V1 },
496 {"mfc0", "t,G", 0x40000000, 0xffe007ff, LCD|WR_t|RD_C0, I1 },
497 {"mfc1", "t,S", 0x44000000, 0xffe007ff, LCD|WR_t|RD_S|FP_S, I1 },
498 {"mfc1", "t,G", 0x44000000, 0xffe007ff, LCD|WR_t|RD_S|FP_S, I1 },
499 {"mfc2", "t,G", 0x48000000, 0xffe007ff, LCD|WR_t|RD_C2, I1 },
500 {"mfc3", "t,G", 0x4c000000, 0xffe007ff, LCD|WR_t|RD_C3, I1 },
501 {"mfhi", "d", 0x00000010, 0xffff07ff, WR_d|RD_HI, I1 },
502 /* start-sanitize-r5900 */
503 {"mfhi1", "d", 0x70000010, 0xffff07ff, WR_d|RD_HI, T5 },
504 /* end-sanitize-r5900 */
505 {"mflo", "d", 0x00000012, 0xffff07ff, WR_d|RD_LO, I1 },
506 /* start-sanitize-r5900 */
507 {"mflo1", "d", 0x70000012, 0xffff07ff, WR_d|RD_LO, T5 },
508 {"mfsa", "d", 0x00000028, 0xffff07ff, WR_d, T5 },
509 /* end-sanitize-r5900 */
510 {"mov.d", "D,S", 0x46200006, 0xffff003f, WR_D|RD_S|FP_D, I1 },
511 {"mov.s", "D,S", 0x46000006, 0xffff003f, WR_D|RD_S|FP_S, I1 },
512 {"movf", "d,s,N", 0x00000001, 0xfc0307ff, WR_d|RD_s|RD_CC|FP_D|FP_S, I4 },
513 {"movf.d", "D,S,N", 0x46200011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_D, I4 },
514 {"movf.s", "D,S,N", 0x46000011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_S, I4 },
515 {"movn", "d,v,t", 0x0000000b, 0xfc0007ff, WR_d|RD_s|RD_t, I4 },
516 /* start-sanitize-r5900 */
517 {"movn", "d,v,t", 0x0000000b, 0xfc0007ff, WR_d|RD_s|RD_t, T5 },
518 /* end-sanitize-r5900 */
519 {"ffc", "d,v", 0x0000000b, 0xfc0007ff, WR_d|RD_s,L1 },
520 {"movn.d", "D,S,t", 0x46200013, 0xffe0003f, WR_D|RD_S|RD_t|FP_D, I4 },
521 {"movn.s", "D,S,t", 0x46000013, 0xffe0003f, WR_D|RD_S|RD_t|FP_S, I4 },
522 {"movt", "d,s,N", 0x00010001, 0xfc0307ff, WR_d|RD_s|RD_CC, I4 },
523 {"movt.d", "D,S,N", 0x46210011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_D, I4 },
524 {"movt.s", "D,S,N", 0x46010011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_S, I4 },
525 {"movz", "d,v,t", 0x0000000a, 0xfc0007ff, WR_d|RD_s|RD_t, I4 },
526 /* start-sanitize-r5900 */
527 {"movz", "d,v,t", 0x0000000a, 0xfc0007ff, WR_d|RD_s|RD_t, T5 },
528 /* end-sanitize-r5900 */
529 {"ffs", "d,v", 0x0000000a, 0xfc0007ff, WR_d|RD_s,L1 },
530 {"movz.d", "D,S,t", 0x46200012, 0xffe0003f, WR_D|RD_S|RD_t|FP_D, I4 },
531 {"movz.s", "D,S,t", 0x46000012, 0xffe0003f, WR_D|RD_S|RD_t|FP_S, I4 },
532 /* move is at the top of the table. */
533 {"msub.d", "D,R,S,T", 0x4c000029, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D, I4 },
534 {"msub.s", "D,R,S,T", 0x4c000028, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_S, I4 },
535 /* start-sanitize-r5900 */
536 {"msub.s", "D,R,S,T", 0x4c000028, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_S, T5 },
537 /* end-sanitize-r5900 */
538 {"msub", "s,t", 0x0000001e, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO,L1 },
539 {"msubu", "s,t", 0x0000001f, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO,L1 },
540 {"mtc0", "t,G", 0x40800000, 0xffe007ff, COD|RD_t|WR_C0|WR_CC, I1 },
541 {"mtc1", "t,S", 0x44800000, 0xffe007ff, COD|RD_t|WR_S|FP_S, I1 },
542 {"mtc1", "t,G", 0x44800000, 0xffe007ff, COD|RD_t|WR_S|FP_S, I1 },
543 {"mtc2", "t,G", 0x48800000, 0xffe007ff, COD|RD_t|WR_C2|WR_CC, I1 },
544 {"mtc3", "t,G", 0x4c800000, 0xffe007ff, COD|RD_t|WR_C3|WR_CC, I1 },
545 {"mthi", "s", 0x00000011, 0xfc1fffff, RD_s|WR_HI, I1 },
546 /* start-sanitize-r5900 */
547 {"mthi1", "s", 0x70000011, 0xfc1fffff, RD_s|WR_HI, T5 },
548 /* end-sanitize-r5900 */
549 {"mtlo", "s", 0x00000013, 0xfc1fffff, RD_s|WR_LO, I1 },
550 /* start-sanitize-r5900 */
551 {"mtlo1", "s", 0x70000013, 0xfc1fffff, RD_s|WR_LO, T5 },
552 {"mtsa", "s", 0x00000029, 0xfc1fffff, RD_s, T5 },
553 {"mtsab", "s,j", 0x04180000, 0xfc1f0000, RD_s, T5 },
554 {"mtsah", "s,j", 0x04190000, 0xfc1f0000, RD_s, T5 },
555 /* end-sanitize-r5900 */
556 {"mul.d", "D,V,T", 0x46200002, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, I1 },
557 {"mul.s", "D,V,T", 0x46000002, 0xffe0003f, WR_D|RD_S|RD_T|FP_S, I1 },
558 {"mul", "d,v,t", 0x70000002, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HI|WR_LO, P3 },
559 {"mul", "d,v,t", 0, (int) M_MUL, INSN_MACRO },
560 {"mul", "d,v,I", 0, (int) M_MUL_I, INSN_MACRO },
561 {"mulo", "d,v,t", 0, (int) M_MULO, INSN_MACRO },
562 {"mulo", "d,v,I", 0, (int) M_MULO_I, INSN_MACRO },
563 {"mulou", "d,v,t", 0, (int) M_MULOU, INSN_MACRO },
564 {"mulou", "d,v,I", 0, (int) M_MULOU_I, INSN_MACRO },
565 {"mult", "s,t", 0x00000018, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO, I1},
566 {"mult", "d,s,t", 0x00000018, 0xfc0007ff, RD_s|RD_t|WR_HI|WR_LO|WR_d, I1},
567 /* start-sanitize-r5900 */
568 {"mult1", "d,s,t", 0x70000018, 0xfc0007ff, RD_s|RD_t|WR_HI|WR_LO|WR_d, T5},
569 /* end-sanitize-r5900 */
570 {"multu", "s,t", 0x00000019, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO, I1},
571 {"multu", "d,s,t", 0x00000019, 0xfc0007ff, RD_s|RD_t|WR_HI|WR_LO|WR_d, I1},
572 /* start-sanitize-r5900 */
573 {"multu1", "d,s,t", 0x70000019, 0xfc0007ff, RD_s|RD_t|WR_HI|WR_LO|WR_d, T5},
574 /* end-sanitize-r5900 */
575 {"neg", "d,w", 0x00000022, 0xffe007ff, WR_d|RD_t, I1 }, /* sub 0 */
576 {"negu", "d,w", 0x00000023, 0xffe007ff, WR_d|RD_t, I1 }, /* subu 0 */
577 {"neg.d", "D,V", 0x46200007, 0xffff003f, WR_D|RD_S|FP_D, I1 },
578 {"neg.s", "D,V", 0x46000007, 0xffff003f, WR_D|RD_S|FP_S, I1 },
579 {"nmadd.d", "D,R,S,T", 0x4c000031, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D, I4 },
580 {"nmadd.s", "D,R,S,T", 0x4c000030, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_S, I4 },
581 {"nmsub.d", "D,R,S,T", 0x4c000039, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D, I4 },
582 {"nmsub.s", "D,R,S,T", 0x4c000038, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_S, I4 },
583 /* nop is at the start of the table. */
584 {"nor", "d,v,t", 0x00000027, 0xfc0007ff, WR_d|RD_s|RD_t, I1 },
585 {"nor", "t,r,I", 0, (int) M_NOR_I, INSN_MACRO },
586 {"not", "d,v", 0x00000027, 0xfc0007ff, WR_d|RD_s|RD_t, I1 },/*nor d,s,0*/
587 {"or", "d,v,t", 0x00000025, 0xfc0007ff, WR_d|RD_s|RD_t, I1 },
588 {"or", "t,r,I", 0, (int) M_OR_I, INSN_MACRO },
589 {"ori", "t,r,i", 0x34000000, 0xfc000000, WR_t|RD_s, I1 },
590
591 /* start-sanitize-r5900 */
592 {"pabsh", "d,t", 0x70000168, 0xffe007ff, WR_d|RD_t, T5 },
593 {"pabsw", "d,t", 0x70000068, 0xffe007ff, WR_d|RD_t, T5 },
594 {"paddb", "d,v,t", 0x70000208, 0xfc0007ff, WR_d|RD_s|RD_t, T5 },
595 {"paddh", "d,v,t", 0x70000108, 0xfc0007ff, WR_d|RD_s|RD_t, T5 },
596 {"paddw", "d,v,t", 0x70000008, 0xfc0007ff, WR_d|RD_s|RD_t, T5 },
597 {"paddsb", "d,v,t", 0x70000608, 0xfc0007ff, WR_d|RD_s|RD_t, T5 },
598 {"paddsh", "d,v,t", 0x70000508, 0xfc0007ff, WR_d|RD_s|RD_t, T5 },
599 {"paddsw", "d,v,t", 0x70000408, 0xfc0007ff, WR_d|RD_s|RD_t, T5 },
600 {"paddub", "d,v,t", 0x70000628, 0xfc0007ff, WR_d|RD_s|RD_t, T5 },
601 {"padduh", "d,v,t", 0x70000528, 0xfc0007ff, WR_d|RD_s|RD_t, T5 },
602 {"padduw", "d,v,t", 0x70000428, 0xfc0007ff, WR_d|RD_s|RD_t, T5 },
603 {"padsbh", "d,v,t", 0x70000128, 0xfc0007ff, WR_d|RD_s|RD_t, T5 },
604 {"pand", "d,v,t", 0x70000489, 0xfc0007ff, WR_d|RD_s|RD_t, T5 },
605 {"pceqb", "d,v,t", 0x700002a8, 0xfc0007ff, WR_d|RD_s|RD_t, T5 },
606 {"pceqh", "d,v,t", 0x700001a8, 0xfc0007ff, WR_d|RD_s|RD_t, T5 },
607 {"pceqw", "d,v,t", 0x700000a8, 0xfc0007ff, WR_d|RD_s|RD_t, T5 },
608
609 {"pcgtb", "d,v,t", 0x70000288, 0xfc0007ff, WR_d|RD_s|RD_t, T5 },
610 {"pcgth", "d,v,t", 0x70000188, 0xfc0007ff, WR_d|RD_s|RD_t, T5 },
611 {"pcgtw", "d,v,t", 0x70000088, 0xfc0007ff, WR_d|RD_s|RD_t, T5 },
612
613 {"pcpyh", "d,t", 0x700006e9, 0xffe007ff, WR_d|RD_t, T5 },
614
615 {"pcpyld", "d,v,t", 0x70000389, 0xfc0007ff, WR_d|RD_s|RD_t, T5 },
616 {"pcpyud", "d,v,t", 0x700003a9, 0xfc0007ff, WR_d|RD_s|RD_t, T5 },
617
618 {"pdivbw", "s,t", 0x70000749, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO, T5 },
619 {"pdivuw", "s,t", 0x70000369, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO, T5 },
620 {"pdivw", "s,t", 0x70000349, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO, T5 },
621
622 {"pexch", "d,t", 0x700006a9, 0xffe007ff, WR_d|RD_t, T5 },
623 {"pexcw", "d,t", 0x700007a9, 0xffe007ff, WR_d|RD_t, T5 },
624 {"pexeh", "d,t", 0x70000689, 0xffe007ff, WR_d|RD_t, T5 },
625 {"pexoh", "d,t", 0x70000689, 0xffe007ff, WR_d|RD_t, T5 },
626 {"pexew", "d,t", 0x70000789, 0xffe007ff, WR_d|RD_t, T5 },
627 {"pexow", "d,t", 0x70000789, 0xffe007ff, WR_d|RD_t, T5 },
628
629 {"pext5", "d,t", 0x70000788, 0xffe007ff, WR_d|RD_t, T5 },
630
631 {"pextlb", "d,v,t", 0x70000688, 0xfc0007ff, WR_d|RD_s|RD_t, T5 },
632 {"pextlh", "d,v,t", 0x70000588, 0xfc0007ff, WR_d|RD_s|RD_t, T5 },
633 {"pextlw", "d,v,t", 0x70000488, 0xfc0007ff, WR_d|RD_s|RD_t, T5 },
634 {"pextub", "d,v,t", 0x700006a8, 0xfc0007ff, WR_d|RD_s|RD_t, T5 },
635 {"pextuh", "d,v,t", 0x700005a8, 0xfc0007ff, WR_d|RD_s|RD_t, T5 },
636 {"pextuw", "d,v,t", 0x700004a8, 0xfc0007ff, WR_d|RD_s|RD_t, T5 },
637
638 {"phmaddh", "d,v,t", 0x70000449, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HI|WR_LO, T5 },
639 {"phmsubh", "d,v,t", 0x70000549, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HI|WR_LO, T5 },
640
641 {"pinth", "d,v,t", 0x70000289, 0xfc0007ff, WR_d|RD_s|RD_t, T5 },
642 {"pinteh", "d,v,t", 0x700002a9, 0xfc0007ff, WR_d|RD_s|RD_t, T5 },
643 {"pintoh", "d,v,t", 0x700002a9, 0xfc0007ff, WR_d|RD_s|RD_t, T5 },
644
645 {"plzcw", "d,v", 0x70000004, 0xfc1f07ff, WR_d|RD_s, T5 },
646
647 {"pmaddh", "d,v,t", 0x70000409, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HI|WR_LO, T5 },
648 {"pmadduw", "d,v,t", 0x70000029, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HI|WR_LO, T5 },
649 {"pmaddw", "d,v,t", 0x70000009, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HI|WR_LO, T5 },
650
651 {"pmaxh", "d,v,t", 0x700001c8, 0xfc0007ff, WR_d|RD_s|RD_t, T5 },
652 {"pmaxw", "d,v,t", 0x700000c8, 0xfc0007ff, WR_d|RD_s|RD_t, T5 },
653
654 {"pmfhi", "d", 0x70000209, 0xffff07ff, WR_d|RD_HI, T5 },
655 {"pmflo", "d", 0x70000249, 0xffff07ff, WR_d|RD_LO, T5 },
656
657 {"pmfhl.lw", "d", 0x70000030, 0xffff07ff, WR_d|RD_LO|RD_HI, T5 },
658 {"pmfhl.uw", "d", 0x70000070, 0xffff07ff, WR_d|RD_LO|RD_HI, T5 },
659 {"pmfhl.slw","d", 0x700000b0, 0xffff07ff, WR_d|RD_LO|RD_HI, T5 },
660 {"pmfhl.lh", "d", 0x700000f0, 0xffff07ff, WR_d|RD_LO|RD_HI, T5 },
661 {"pmfhl.sh", "d", 0x70000130, 0xffff07ff, WR_d|RD_LO|RD_HI, T5 },
662
663 {"pminh", "d,v,t", 0x700001e8, 0xfc0007ff, WR_d|RD_s|RD_t, T5 },
664 {"pminw", "d,v,t", 0x700000e8, 0xfc0007ff, WR_d|RD_s|RD_t, T5 },
665
666 {"pmsubh", "d,v,t", 0x70000509, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HI|WR_LO, T5 },
667 {"pmsubw", "d,v,t", 0x70000109, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HI|WR_LO, T5 },
668
669 {"pmthi", "v", 0x70000229, 0xfc1fffff, WR_HI|RD_s, T5 },
670 {"pmtlo", "v", 0x70000269, 0xfc1fffff, WR_LO|RD_s, T5 },
671
672 {"pmthl.lw", "v", 0x70000031, 0xfc1fffff, WR_HI|WR_LO|RD_s, T5 },
673
674 {"pmulth", "d,v,t", 0x70000709, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HI|WR_LO, T5 },
675 {"pmultuw", "d,v,t", 0x70000329, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HI|WR_LO, T5 },
676 {"pmultw", "d,v,t", 0x70000309, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HI|WR_LO, T5 },
677
678 {"pnor", "d,v,t", 0x700004e9, 0xfc0007ff, WR_d|RD_s|RD_t, T5 },
679 {"por", "d,v,t", 0x700004a9, 0xfc0007ff, WR_d|RD_s|RD_t, T5 },
680
681 {"ppac5", "d,t", 0x700007c8, 0xffe007ff, WR_d|RD_t, T5 },
682
683 {"ppacb", "d,v,t", 0x700006c8, 0xfc0007ff, WR_d|RD_s|RD_t, T5 },
684 {"ppach", "d,v,t", 0x700005c8, 0xfc0007ff, WR_d|RD_s|RD_t, T5 },
685 {"ppacw", "d,v,t", 0x700004c8, 0xfc0007ff, WR_d|RD_s|RD_t, T5 },
686
687 {"prevh", "d,t", 0x700006c9, 0xffe007ff, WR_d|RD_t, T5 },
688 {"prot3w", "d,t", 0x700007c9, 0xffe007ff, WR_d|RD_t, T5 },
689
690 {"psllh", "d,t,<", 0x70000034, 0xffe0003f, WR_d|RD_t, T5 },
691 {"psllvw", "d,t,s", 0x70000089, 0xfc0007ff, WR_d|RD_t|RD_s, T5 },
692 {"psllw", "d,t,<", 0x7000003c, 0xffe0003f, WR_d|RD_t, T5 },
693
694 {"psrah", "d,t,<", 0x70000037, 0xffe0003f, WR_d|RD_t, T5 },
695 {"psravw", "d,t,s", 0x700000e9, 0xfc0007ff, WR_d|RD_t|RD_s, T5 },
696 {"psraw", "d,t,<", 0x7000003f, 0xffe0003f, WR_d|RD_t, T5 },
697
698 {"psrlh", "d,t,<", 0x70000036, 0xffe0003f, WR_d|RD_t, T5 },
699 {"psrlvw", "d,t,s", 0x700000c9, 0xfc0007ff, WR_d|RD_t|RD_s, T5 },
700 {"psrlw", "d,t,<", 0x7000003e, 0xffe0003f, WR_d|RD_t, T5 },
701
702 {"psubb", "d,v,t", 0x70000248, 0xfc0007ff, WR_d|RD_s|RD_t, T5 },
703 {"psubh", "d,v,t", 0x70000148, 0xfc0007ff, WR_d|RD_s|RD_t, T5 },
704 {"psubsb", "d,v,t", 0x70000648, 0xfc0007ff, WR_d|RD_s|RD_t, T5 },
705 {"psubsh", "d,v,t", 0x70000548, 0xfc0007ff, WR_d|RD_s|RD_t, T5 },
706 {"psubsw", "d,v,t", 0x70000448, 0xfc0007ff, WR_d|RD_s|RD_t, T5 },
707 {"psubub", "d,v,t", 0x70000668, 0xfc0007ff, WR_d|RD_s|RD_t, T5 },
708 {"psubuh", "d,v,t", 0x70000568, 0xfc0007ff, WR_d|RD_s|RD_t, T5 },
709 {"psubuw", "d,v,t", 0x70000468, 0xfc0007ff, WR_d|RD_s|RD_t, T5 },
710 {"psubw", "d,v,t", 0x70000048, 0xfc0007ff, WR_d|RD_s|RD_t, T5 },
711
712 {"pxor", "d,v,t", 0x700004c9, 0xfc0007ff, WR_d|RD_s|RD_t, T5 },
713 /* end-sanitize-r5900 */
714
715 {"pref", "k,o(b)", 0xcc000000, 0xfc000000, RD_b, I4 },
716 {"prefx", "h,t(b)", 0x4c00000f, 0xfc0007ff, RD_b|RD_t, I4 },
717
718 /* start-sanitize-r5900 */
719 {"qfsrv", "d,v,t", 0x700006e8, 0xfc0007ff, WR_d|RD_s|RD_t, T5 },
720 /* end-sanitize-r5900 */
721
722 {"recip.d", "D,S", 0x46200015, 0xffff003f, WR_D|RD_S|FP_D, I4 },
723 {"recip.s", "D,S", 0x46000015, 0xffff003f, WR_D|RD_S|FP_S, I4 },
724 {"rem", "z,s,t", 0x0000001a, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO, I1 },
725 {"rem", "d,v,t", 0, (int) M_REM_3, INSN_MACRO },
726 {"rem", "d,v,I", 0, (int) M_REM_3I, INSN_MACRO },
727 {"remu", "z,s,t", 0x0000001b, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO, I1 },
728 {"remu", "d,v,t", 0, (int) M_REMU_3, INSN_MACRO },
729 {"remu", "d,v,I", 0, (int) M_REMU_3I, INSN_MACRO },
730 {"rfe", "", 0x42000010, 0xffffffff, 0, I1|T3 },
731 {"rol", "d,v,t", 0, (int) M_ROL, INSN_MACRO },
732 {"rol", "d,v,I", 0, (int) M_ROL_I, INSN_MACRO },
733 {"ror", "d,v,t", 0, (int) M_ROR, INSN_MACRO },
734 {"ror", "d,v,I", 0, (int) M_ROR_I, INSN_MACRO },
735 {"round.l.d", "D,S", 0x46200008, 0xffff003f, WR_D|RD_S|FP_D, I3 },
736 {"round.l.s", "D,S", 0x46000008, 0xffff003f, WR_D|RD_S|FP_S, I3 },
737 {"round.w.d", "D,S", 0x4620000c, 0xffff003f, WR_D|RD_S|FP_D, I2 },
738 {"round.w.s", "D,S", 0x4600000c, 0xffff003f, WR_D|RD_S|FP_S, I2 },
739 {"rsqrt.d", "D,S", 0x46200016, 0xffff003f, WR_D|RD_S|FP_D, I4 },
740 {"rsqrt.s", "D,S", 0x46000016, 0xffff003f, WR_D|RD_S|FP_S, I4 },
741 /* start-sanitize-r5900 */
742 {"rsqrt.s", "D,S", 0x46000016, 0xffff003f, WR_D|RD_S|FP_S, T5 },
743 /* end-sanitize-r5900 */
744 {"sb", "t,o(b)", 0xa0000000, 0xfc000000, SM|RD_t|RD_b, I1 },
745 {"sb", "t,A(b)", 0, (int) M_SB_AB, INSN_MACRO },
746 {"sc", "t,o(b)", 0xe0000000, 0xfc000000, SM|RD_t|WR_t|RD_b, I2 },
747 {"sc", "t,A(b)", 2, (int) M_SC_AB, INSN_MACRO },
748 {"scd", "t,o(b)", 0xf0000000, 0xfc000000, SM|RD_t|WR_t|RD_b, I3 },
749 {"scd", "t,A(b)", 3, (int) M_SCD_AB, INSN_MACRO },
750 {"sd", "t,o(b)", 0xfc000000, 0xfc000000, SM|RD_t|RD_b, I3 },
751 {"sd", "t,o(b)", 0, (int) M_SD_OB, INSN_MACRO },
752 {"sd", "t,A(b)", 0, (int) M_SD_AB, INSN_MACRO },
753 {"sdbbp", "", 0x0000000e, 0xffffffff, TRAP, T3 },
754 {"sdbbp", "c", 0x0000000e, 0xfc00003f, TRAP, T3 },
755 {"sdc1", "T,o(b)", 0xf4000000, 0xfc000000, SM|RD_T|RD_b|FP_D, I2 },
756 {"sdc1", "E,o(b)", 0xf4000000, 0xfc000000, SM|RD_T|RD_b|FP_D, I2 },
757 {"sdc1", "T,A(b)", 2, (int) M_SDC1_AB, INSN_MACRO },
758 {"sdc1", "E,A(b)", 2, (int) M_SDC1_AB, INSN_MACRO },
759 {"sdc2", "E,o(b)", 0xf8000000, 0xfc000000, SM|RD_C2|RD_b, I2 },
760 {"sdc2", "E,A(b)", 2, (int) M_SDC2_AB, INSN_MACRO },
761 {"sdc3", "E,o(b)", 0xfc000000, 0xfc000000, SM|RD_C3|RD_b, I2 },
762 {"sdc3", "E,A(b)", 2, (int) M_SDC3_AB, INSN_MACRO },
763 {"s.d", "T,o(b)", 0xf4000000, 0xfc000000, SM|RD_T|RD_b, I2 },
764 {"s.d", "T,o(b)", 0, (int) M_S_DOB, INSN_MACRO },
765 {"s.d", "T,A(b)", 0, (int) M_S_DAB, INSN_MACRO },
766 {"sdl", "t,o(b)", 0xb0000000, 0xfc000000, SM|RD_t|RD_b, I3 },
767 {"sdl", "t,A(b)", 3, (int) M_SDL_AB, INSN_MACRO },
768 {"sdr", "t,o(b)", 0xb4000000, 0xfc000000, SM|RD_t|RD_b, I3 },
769 {"sdr", "t,A(b)", 3, (int) M_SDR_AB, INSN_MACRO },
770 {"sdxc1", "S,t(b)", 0x4c000009, 0xfc0007ff, SM|RD_S|RD_t|RD_b, I4 },
771 {"selsl", "d,v,t", 0x00000005, 0xfc0007ff, WR_d|RD_s|RD_t,L1 },
772 {"selsr", "d,v,t", 0x00000001, 0xfc0007ff, WR_d|RD_s|RD_t,L1 },
773 {"seq", "d,v,t", 0, (int) M_SEQ, INSN_MACRO },
774 {"seq", "d,v,I", 0, (int) M_SEQ_I, INSN_MACRO },
775 {"sge", "d,v,t", 0, (int) M_SGE, INSN_MACRO },
776 {"sge", "d,v,I", 0, (int) M_SGE_I, INSN_MACRO },
777 {"sgeu", "d,v,t", 0, (int) M_SGEU, INSN_MACRO },
778 {"sgeu", "d,v,I", 0, (int) M_SGEU_I, INSN_MACRO },
779 {"sgt", "d,v,t", 0, (int) M_SGT, INSN_MACRO },
780 {"sgt", "d,v,I", 0, (int) M_SGT_I, INSN_MACRO },
781 {"sgtu", "d,v,t", 0, (int) M_SGTU, INSN_MACRO },
782 {"sgtu", "d,v,I", 0, (int) M_SGTU_I, INSN_MACRO },
783 {"sh", "t,o(b)", 0xa4000000, 0xfc000000, SM|RD_t|RD_b, I1 },
784 {"sh", "t,A(b)", 0, (int) M_SH_AB, INSN_MACRO },
785 {"sle", "d,v,t", 0, (int) M_SLE, INSN_MACRO },
786 {"sle", "d,v,I", 0, (int) M_SLE_I, INSN_MACRO },
787 {"sleu", "d,v,t", 0, (int) M_SLEU, INSN_MACRO },
788 {"sleu", "d,v,I", 0, (int) M_SLEU_I, INSN_MACRO },
789 {"sllv", "d,t,s", 0x00000004, 0xfc0007ff, WR_d|RD_t|RD_s, I1 },
790 {"sll", "d,w,s", 0x00000004, 0xfc0007ff, WR_d|RD_t|RD_s, I1 }, /* sllv */
791 {"sll", "d,w,<", 0x00000000, 0xffe0003f, WR_d|RD_t, I1 },
792 {"slt", "d,v,t", 0x0000002a, 0xfc0007ff, WR_d|RD_s|RD_t, I1 },
793 {"slt", "d,v,I", 0, (int) M_SLT_I, INSN_MACRO },
794 {"slti", "t,r,j", 0x28000000, 0xfc000000, WR_t|RD_s, I1 },
795 {"sltiu", "t,r,j", 0x2c000000, 0xfc000000, WR_t|RD_s, I1 },
796 {"sltu", "d,v,t", 0x0000002b, 0xfc0007ff, WR_d|RD_s|RD_t, I1 },
797 {"sltu", "d,v,I", 0, (int) M_SLTU_I, INSN_MACRO },
798 {"sne", "d,v,t", 0, (int) M_SNE, INSN_MACRO },
799 {"sne", "d,v,I", 0, (int) M_SNE_I, INSN_MACRO },
800 /* start-sanitize-r5900 */
801 {"sq", "t,o(b)", 0x7c000000, 0xfc000000, SM|RD_t|RD_b, T5 },
802 /* end-sanitize-r5900 */
803 {"sqrt.d", "D,S", 0x46200004, 0xffff003f, WR_D|RD_S|FP_D, I2 },
804 {"sqrt.s", "D,S", 0x46000004, 0xffff003f, WR_D|RD_S|FP_S, I2 },
805 {"srav", "d,t,s", 0x00000007, 0xfc0007ff, WR_d|RD_t|RD_s, I1 },
806 {"sra", "d,w,s", 0x00000007, 0xfc0007ff, WR_d|RD_t|RD_s, I1 }, /* srav */
807 {"sra", "d,w,<", 0x00000003, 0xffe0003f, WR_d|RD_t, I1 },
808 {"srlv", "d,t,s", 0x00000006, 0xfc0007ff, WR_d|RD_t|RD_s, I1 },
809 {"srl", "d,w,s", 0x00000006, 0xfc0007ff, WR_d|RD_t|RD_s, I1 }, /* srlv */
810 {"srl", "d,w,<", 0x00000002, 0xffe0003f, WR_d|RD_t, I1 },
811 {"standby", "", 0x42000021, 0xffffffff, 0, V1 },
812 {"sub", "d,v,t", 0x00000022, 0xfc0007ff, WR_d|RD_s|RD_t, I1 },
813 {"sub", "d,v,I", 0, (int) M_SUB_I, INSN_MACRO },
814 {"sub.d", "D,V,T", 0x46200001, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, I1 },
815 {"sub.s", "D,V,T", 0x46000001, 0xffe0003f, WR_D|RD_S|RD_T|FP_S, I1 },
816 {"subu", "d,v,t", 0x00000023, 0xfc0007ff, WR_d|RD_s|RD_t, I1 },
817 {"subu", "d,v,I", 0, (int) M_SUBU_I, INSN_MACRO },
818 {"suspend", "", 0x42000022, 0xffffffff, 0, V1 },
819 {"sw", "t,o(b)", 0xac000000, 0xfc000000, SM|RD_t|RD_b, I1 },
820 {"sw", "t,A(b)", 0, (int) M_SW_AB, INSN_MACRO },
821 {"swc0", "E,o(b)", 0xe0000000, 0xfc000000, SM|RD_C0|RD_b, I1 },
822 {"swc0", "E,A(b)", 0, (int) M_SWC0_AB, INSN_MACRO },
823 {"swc1", "T,o(b)", 0xe4000000, 0xfc000000, SM|RD_T|RD_b|FP_S, I1 },
824 {"swc1", "E,o(b)", 0xe4000000, 0xfc000000, SM|RD_T|RD_b|FP_S, I1 },
825 {"swc1", "T,A(b)", 0, (int) M_SWC1_AB, INSN_MACRO },
826 {"swc1", "E,A(b)", 0, (int) M_SWC1_AB, INSN_MACRO },
827 {"s.s", "T,o(b)", 0xe4000000, 0xfc000000, SM|RD_T|RD_b|FP_S, I1 }, /* swc1 */
828 {"s.s", "T,A(b)", 0, (int) M_SWC1_AB, INSN_MACRO },
829 {"swc2", "E,o(b)", 0xe8000000, 0xfc000000, SM|RD_C2|RD_b, I1 },
830 {"swc2", "E,A(b)", 0, (int) M_SWC2_AB, INSN_MACRO },
831 {"swc3", "E,o(b)", 0xec000000, 0xfc000000, SM|RD_C3|RD_b, I1 },
832 {"swc3", "E,A(b)", 0, (int) M_SWC3_AB, INSN_MACRO },
833 {"swl", "t,o(b)", 0xa8000000, 0xfc000000, SM|RD_t|RD_b, I1 },
834 {"swl", "t,A(b)", 0, (int) M_SWL_AB, INSN_MACRO },
835 {"scache", "t,o(b)", 0xa8000000, 0xfc000000, RD_t|RD_b, I2 }, /* same */
836 {"scache", "t,A(b)", 2, (int) M_SWL_AB, INSN_MACRO }, /* as swl */
837 {"swr", "t,o(b)", 0xb8000000, 0xfc000000, SM|RD_t|RD_b, I1 },
838 {"swr", "t,A(b)", 0, (int) M_SWR_AB, INSN_MACRO },
839 {"invalidate", "t,o(b)",0xb8000000, 0xfc000000, RD_t|RD_b, I2 }, /* same */
840 {"invalidate", "t,A(b)",2, (int) M_SWR_AB, INSN_MACRO }, /* as swr */
841 {"swxc1", "S,t(b)", 0x4c000008, 0xfc0007ff, SM|RD_S|RD_t|RD_b, I4 },
842 {"sync", "", 0x0000000f, 0xffffffff, 0, I2 },
843 {"syscall", "", 0x0000000c, 0xffffffff, TRAP, I1 },
844 {"syscall", "B", 0x0000000c, 0xfc00003f, TRAP, I1 },
845 {"teqi", "s,j", 0x040c0000, 0xfc1f0000, RD_s|TRAP, I2 },
846 {"teq", "s,t", 0x00000034, 0xfc00003f, RD_s|RD_t|TRAP, I2 },
847 {"teq", "s,j", 0x040c0000, 0xfc1f0000, RD_s|TRAP, I2 }, /* teqi */
848 {"teq", "s,I", 2, (int) M_TEQ_I, INSN_MACRO },
849 {"tgei", "s,j", 0x04080000, 0xfc1f0000, RD_s|TRAP, I2 },
850 {"tge", "s,t", 0x00000030, 0xfc00003f, RD_s|RD_t|TRAP, I2 },
851 {"tge", "s,j", 0x04080000, 0xfc1f0000, RD_s|TRAP, I2 }, /* tgei */
852 {"tge", "s,I", 2, (int) M_TGE_I, INSN_MACRO },
853 {"tgeiu", "s,j", 0x04090000, 0xfc1f0000, RD_s|TRAP, I2 },
854 {"tgeu", "s,t", 0x00000031, 0xfc00003f, RD_s|RD_t|TRAP, I2 },
855 {"tgeu", "s,j", 0x04090000, 0xfc1f0000, RD_s|TRAP, I2 }, /* tgeiu */
856 {"tgeu", "s,I", 2, (int) M_TGEU_I, INSN_MACRO },
857 {"tlbp", "", 0x42000008, 0xffffffff, INSN_TLB, I1 },
858 {"tlbr", "", 0x42000001, 0xffffffff, INSN_TLB, I1 },
859 {"tlbwi", "", 0x42000002, 0xffffffff, INSN_TLB, I1 },
860 {"tlbwr", "", 0x42000006, 0xffffffff, INSN_TLB, I1 },
861 {"tlti", "s,j", 0x040a0000, 0xfc1f0000, RD_s|TRAP, I2 },
862 {"tlt", "s,t", 0x00000032, 0xfc00003f, RD_s|RD_t|TRAP, I2 },
863 {"tlt", "s,j", 0x040a0000, 0xfc1f0000, RD_s|TRAP, I2 }, /* tlti */
864 {"tlt", "s,I", 2, (int) M_TLT_I, INSN_MACRO },
865 {"tltiu", "s,j", 0x040b0000, 0xfc1f0000, RD_s|TRAP, I2 },
866 {"tltu", "s,t", 0x00000033, 0xfc00003f, RD_s|RD_t|TRAP, I2 },
867 {"tltu", "s,j", 0x040b0000, 0xfc1f0000, RD_s|TRAP, I2 }, /* tltiu */
868 {"tltu", "s,I", 2, (int) M_TLTU_I, INSN_MACRO },
869 {"tnei", "s,j", 0x040e0000, 0xfc1f0000, RD_s|TRAP, I2 },
870 {"tne", "s,t", 0x00000036, 0xfc00003f, RD_s|RD_t|TRAP, I2 },
871 {"tne", "s,j", 0x040e0000, 0xfc1f0000, RD_s|TRAP, I2 }, /* tnei */
872 {"tne", "s,I", 2, (int) M_TNE_I, INSN_MACRO },
873 {"trunc.l.d", "D,S", 0x46200009, 0xffff003f, WR_D|RD_S|FP_D, I3 },
874 {"trunc.l.s", "D,S", 0x46000009, 0xffff003f, WR_D|RD_S|FP_S, I3 },
875 {"trunc.w.d", "D,S", 0x4620000d, 0xffff003f, WR_D|RD_S|FP_D, I2 },
876 {"trunc.w.d", "D,S,x", 0x4620000d, 0xffff003f, WR_D|RD_S|FP_D, I2 },
877 {"trunc.w.d", "D,S,t", 0, (int) M_TRUNCWD, INSN_MACRO },
878 {"trunc.w.s", "D,S", 0x4600000d, 0xffff003f, WR_D|RD_S|FP_S, I2 },
879 {"trunc.w.s", "D,S,x", 0x4600000d, 0xffff003f, WR_D|RD_S|FP_S, I2 },
880 {"trunc.w.s", "D,S,t", 0, (int) M_TRUNCWS, INSN_MACRO },
881 {"uld", "t,o(b)", 3, (int) M_ULD, INSN_MACRO },
882 {"uld", "t,A(b)", 3, (int) M_ULD_A, INSN_MACRO },
883 {"ulh", "t,o(b)", 0, (int) M_ULH, INSN_MACRO },
884 {"ulh", "t,A(b)", 0, (int) M_ULH_A, INSN_MACRO },
885 {"ulhu", "t,o(b)", 0, (int) M_ULHU, INSN_MACRO },
886 {"ulhu", "t,A(b)", 0, (int) M_ULHU_A, INSN_MACRO },
887 {"ulw", "t,o(b)", 0, (int) M_ULW, INSN_MACRO },
888 {"ulw", "t,A(b)", 0, (int) M_ULW_A, INSN_MACRO },
889 {"usd", "t,o(b)", 3, (int) M_USD, INSN_MACRO },
890 {"usd", "t,A(b)", 3, (int) M_USD_A, INSN_MACRO },
891 {"ush", "t,o(b)", 0, (int) M_USH, INSN_MACRO },
892 {"ush", "t,A(b)", 0, (int) M_USH_A, INSN_MACRO },
893 {"usw", "t,o(b)", 0, (int) M_USW, INSN_MACRO },
894 {"usw", "t,A(b)", 0, (int) M_USW_A, INSN_MACRO },
895 {"xor", "d,v,t", 0x00000026, 0xfc0007ff, WR_d|RD_s|RD_t, I1 },
896 {"xor", "t,r,I", 0, (int) M_XOR_I, INSN_MACRO },
897 {"xori", "t,r,i", 0x38000000, 0xfc000000, WR_t|RD_s, I1 },
898 {"wait", "", 0x42000020, 0xffffffff, TRAP, I3 },
899 {"waiti", "", 0x42000020, 0xffffffff, TRAP, L1 },
900 {"wb", "o(b)", 0xbc040000, 0xfc1f0000, SM|RD_b, L1 },
901 /* No hazard protection on coprocessor instructions--they shouldn't
902 change the state of the processor and if they do it's up to the
903 user to put in nops as necessary. These are at the end so that the
904 disasembler recognizes more specific versions first. */
905 {"c0", "C", 0x42000000, 0xfe000000, 0, I1 },
906 {"c1", "C", 0x46000000, 0xfe000000, 0, I1 },
907 {"c2", "C", 0x4a000000, 0xfe000000, 0, I1 },
908 {"c3", "C", 0x4e000000, 0xfe000000, 0, I1 },
909 {"cop0", "C", 0, (int) M_COP0, INSN_MACRO },
910 {"cop1", "C", 0, (int) M_COP1, INSN_MACRO },
911 {"cop2", "C", 0, (int) M_COP2, INSN_MACRO },
912 {"cop3", "C", 0, (int) M_COP3, INSN_MACRO },
913 };
914
915 #define MIPS_NUM_OPCODES \
916 ((sizeof mips_builtin_opcodes) / (sizeof (mips_builtin_opcodes[0])))
917 const int bfd_mips_num_builtin_opcodes = MIPS_NUM_OPCODES;
918
919 /* const removed from the following to allow for dynamic extensions to the
920 * built-in instruction set. */
921 struct mips_opcode *mips_opcodes =
922 (struct mips_opcode *) mips_builtin_opcodes;
923 int bfd_mips_num_opcodes = MIPS_NUM_OPCODES;
924 #undef MIPS_NUM_OPCODES
925
GDB Binutils - Deliverables
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