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Finish off adding MIPS32 instructions.
[deliverable/binutils-gdb.git] / opcodes / mips-opc.c
1 /* mips-opc.c -- MIPS opcode list.
2 Copyright 1993, 1994, 1995, 1996, 1997, 1998 Free Software Foundation, Inc.
3 Contributed by Ralph Campbell and OSF
4 Commented and modified by Ian Lance Taylor, Cygnus Support
5 Extended for MIPS32 support by Anders Norlander, and by SiByte, Inc.
6
7 This file is part of GDB, GAS, and the GNU binutils.
8
9 GDB, GAS, and the GNU binutils are free software; you can redistribute
10 them and/or modify them under the terms of the GNU General Public
11 License as published by the Free Software Foundation; either version
12 1, or (at your option) any later version.
13
14 GDB, GAS, and the GNU binutils are distributed in the hope that they
15 will be useful, but WITHOUT ANY WARRANTY; without even the implied
16 warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See
17 the GNU General Public License for more details.
18
19 You should have received a copy of the GNU General Public License
20 along with this file; see the file COPYING. If not, write to the Free
21 Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
22
23 #include <stdio.h>
24 #include "sysdep.h"
25 #include "opcode/mips.h"
26
27 /* Short hand so the lines aren't too long. */
28
29 #define LDD INSN_LOAD_MEMORY_DELAY
30 #define LCD INSN_LOAD_COPROC_DELAY
31 #define UBD INSN_UNCOND_BRANCH_DELAY
32 #define CBD INSN_COND_BRANCH_DELAY
33 #define COD INSN_COPROC_MOVE_DELAY
34 #define CLD INSN_COPROC_MEMORY_DELAY
35 #define CBL INSN_COND_BRANCH_LIKELY
36 #define TRAP INSN_TRAP
37 #define SM INSN_STORE_MEMORY
38
39 #define WR_d INSN_WRITE_GPR_D
40 #define WR_t INSN_WRITE_GPR_T
41 #define WR_31 INSN_WRITE_GPR_31
42 #define WR_D INSN_WRITE_FPR_D
43 #define WR_T INSN_WRITE_FPR_T
44 #define WR_S INSN_WRITE_FPR_S
45 #define RD_s INSN_READ_GPR_S
46 #define RD_b INSN_READ_GPR_S
47 #define RD_t INSN_READ_GPR_T
48 #define RD_S INSN_READ_FPR_S
49 #define RD_T INSN_READ_FPR_T
50 #define RD_R INSN_READ_FPR_R
51 #define WR_CC INSN_WRITE_COND_CODE
52 #define RD_CC INSN_READ_COND_CODE
53 #define RD_C0 INSN_COP
54 #define RD_C1 INSN_COP
55 #define RD_C2 INSN_COP
56 #define RD_C3 INSN_COP
57 #define WR_C0 INSN_COP
58 #define WR_C1 INSN_COP
59 #define WR_C2 INSN_COP
60 #define WR_C3 INSN_COP
61
62 #define WR_HI INSN_WRITE_HI
63 #define RD_HI INSN_READ_HI
64 #define MOD_HI WR_HI|RD_HI
65
66 #define WR_LO INSN_WRITE_LO
67 #define RD_LO INSN_READ_LO
68 #define MOD_LO WR_LO|RD_LO
69
70 #define WR_HILO WR_HI|WR_LO
71 #define RD_HILO RD_HI|RD_LO
72 #define MOD_HILO WR_HILO|RD_HILO
73
74 #define IS_M INSN_MULT
75
76 #define I1 INSN_ISA1
77 #define I2 INSN_ISA2
78 #define I3 INSN_ISA3
79 #define I4 INSN_ISA4
80 #define I5 INSN_ISA5
81 #define I32 INSN_ISA32
82 #define I64 INSN_ISA64
83
84 #define P3 INSN_4650
85 #define L1 INSN_4010
86 #define V1 INSN_4100
87 #define T3 INSN_3900
88
89 #define G1 (T3 \
90 )
91
92 #define G2 (T3 \
93 )
94
95 #define G3 (I4 \
96 )
97
98 #define G6 INSN_GP32
99
100 #define M1 0
101 #define M2 0
102
103 /* The order of overloaded instructions matters. Label arguments and
104 register arguments look the same. Instructions that can have either
105 for arguments must apear in the correct order in this table for the
106 assembler to pick the right one. In other words, entries with
107 immediate operands must apear after the same instruction with
108 registers.
109
110 Many instructions are short hand for other instructions (i.e., The
111 jal <register> instruction is short for jalr <register>). */
112
113 const struct mips_opcode mips_builtin_opcodes[] =
114 {
115 /* These instructions appear first so that the disassembler will find
116 them first. The assemblers uses a hash table based on the
117 instruction name anyhow. */
118 /* name, args, match, mask, pinfo, membership */
119 {"pref", "k,o(b)", 0xcc000000, 0xfc000000, RD_b, I32|G3|M1},
120 {"nop", "", 0x00000000, 0xffffffff, 0, I1 },
121 {"ssnop", "", 0x00000040, 0xffffffff, 0, I32|M1 },
122 {"li", "t,j", 0x24000000, 0xffe00000, WR_t, I1 }, /* addiu */
123 {"li", "t,i", 0x34000000, 0xffe00000, WR_t, I1 }, /* ori */
124 {"li", "t,I", 0, (int) M_LI, INSN_MACRO, I1 },
125 {"move", "d,s", 0x00000025, 0xfc1f07ff, WR_d|RD_s, I1|G6 },/* or */
126 {"move", "d,s", 0x0000002d, 0xfc1f07ff, WR_d|RD_s, I3 },/* daddu */
127 {"move", "d,s", 0x00000021, 0xfc1f07ff, WR_d|RD_s, I1 },/* addu */
128 {"move", "d,s", 0x00000025, 0xfc1f07ff, WR_d|RD_s, I1 },/* or */
129 {"b", "p", 0x10000000, 0xffff0000, UBD, I1 },/* beq 0,0 */
130 {"b", "p", 0x04010000, 0xffff0000, UBD, I1 },/* bgez 0 */
131 {"bal", "p", 0x04110000, 0xffff0000, UBD|WR_31, I1 },/* bgezal 0*/
132
133 {"abs", "d,v", 0, (int) M_ABS, INSN_MACRO, I1 },
134 {"abs.s", "D,V", 0x46000005, 0xffff003f, WR_D|RD_S|FP_S, I1 },
135 {"abs.d", "D,V", 0x46200005, 0xffff003f, WR_D|RD_S|FP_D, I1 },
136 {"abs.ps", "D,V", 0x46c00005, 0xffff003f, WR_D|RD_S|FP_D, I5 },
137 {"add", "d,v,t", 0x00000020, 0xfc0007ff, WR_d|RD_s|RD_t, I1 },
138 {"add", "t,r,I", 0, (int) M_ADD_I, INSN_MACRO, I1 },
139 {"add.s", "D,V,T", 0x46000000, 0xffe0003f, WR_D|RD_S|RD_T|FP_S, I1 },
140 {"add.d", "D,V,T", 0x46200000, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, I1 },
141 {"add.ps", "D,V,T", 0x46c00000, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, I5 },
142 {"addi", "t,r,j", 0x20000000, 0xfc000000, WR_t|RD_s, I1 },
143 {"addiu", "t,r,j", 0x24000000, 0xfc000000, WR_t|RD_s, I1 },
144 {"addu", "d,v,t", 0x00000021, 0xfc0007ff, WR_d|RD_s|RD_t, I1 },
145 {"addu", "t,r,I", 0, (int) M_ADDU_I, INSN_MACRO, I1 },
146 {"alnv.ps", "D,V,T,s", 0x4c00001e, 0xfc00003f, WR_D|RD_S|RD_T|FP_D, I5 },
147 {"and", "d,v,t", 0x00000024, 0xfc0007ff, WR_d|RD_s|RD_t, I1 },
148 {"and", "t,r,I", 0, (int) M_AND_I, INSN_MACRO, I1 },
149 {"andi", "t,r,i", 0x30000000, 0xfc000000, WR_t|RD_s, I1 },
150 /* b is at the top of the table. */
151 /* bal is at the top of the table. */
152 {"bc0f", "p", 0x41000000, 0xffff0000, CBD|RD_CC, I1 },
153 {"bc0fl", "p", 0x41020000, 0xffff0000, CBL|RD_CC, I2|T3 },
154 {"bc1f", "p", 0x45000000, 0xffff0000, CBD|RD_CC|FP_S, I1|M1 },
155 {"bc1f", "N,p", 0x45000000, 0xffe30000, CBD|RD_CC|FP_S, I4|I32|M1},
156 {"bc1fl", "p", 0x45020000, 0xffff0000, CBL|RD_CC|FP_S, I2|T3|M1},
157 {"bc1fl", "N,p", 0x45020000, 0xffe30000, CBL|RD_CC|FP_S, I4|I32|M1},
158 {"bc2f", "p", 0x49000000, 0xffff0000, CBD|RD_CC, I1 },
159 {"bc2fl", "p", 0x49020000, 0xffff0000, CBL|RD_CC, I2|T3 },
160 {"bc3f", "p", 0x4d000000, 0xffff0000, CBD|RD_CC, I1 },
161 {"bc3fl", "p", 0x4d020000, 0xffff0000, CBL|RD_CC, I2|T3 },
162 {"bc0t", "p", 0x41010000, 0xffff0000, CBD|RD_CC, I1 },
163 {"bc0tl", "p", 0x41030000, 0xffff0000, CBL|RD_CC, I2|T3 },
164 {"bc1t", "p", 0x45010000, 0xffff0000, CBD|RD_CC|FP_S, I1 },
165 {"bc1t", "N,p", 0x45010000, 0xffe30000, CBD|RD_CC|FP_S, I4|I32|M1},
166 {"bc1tl", "p", 0x45030000, 0xffff0000, CBL|RD_CC|FP_S, I2|T3 },
167 {"bc1tl", "N,p", 0x45030000, 0xffe30000, CBL|RD_CC|FP_S, I4|I32|M1},
168 {"bc2t", "p", 0x49010000, 0xffff0000, CBD|RD_CC, I1 },
169 {"bc2tl", "p", 0x49030000, 0xffff0000, CBL|RD_CC, I2|T3 },
170 {"bc3t", "p", 0x4d010000, 0xffff0000, CBD|RD_CC, I1 },
171 {"bc3tl", "p", 0x4d030000, 0xffff0000, CBL|RD_CC, I2|T3 },
172 {"beqz", "s,p", 0x10000000, 0xfc1f0000, CBD|RD_s, I1 },
173 {"beqzl", "s,p", 0x50000000, 0xfc1f0000, CBL|RD_s, I2|T3 },
174 {"beq", "s,t,p", 0x10000000, 0xfc000000, CBD|RD_s|RD_t, I1 },
175 {"beq", "s,I,p", 0, (int) M_BEQ_I, INSN_MACRO, I1 },
176 {"beql", "s,t,p", 0x50000000, 0xfc000000, CBL|RD_s|RD_t, I2|T3 },
177 {"beql", "s,I,p", 0, (int) M_BEQL_I, INSN_MACRO, I2 },
178 {"bge", "s,t,p", 0, (int) M_BGE, INSN_MACRO, I1 },
179 {"bge", "s,I,p", 0, (int) M_BGE_I, INSN_MACRO, I1 },
180 {"bgel", "s,t,p", 0, (int) M_BGEL, INSN_MACRO, I2 },
181 {"bgel", "s,I,p", 0, (int) M_BGEL_I, INSN_MACRO, I2 },
182 {"bgeu", "s,t,p", 0, (int) M_BGEU, INSN_MACRO, I1 },
183 {"bgeu", "s,I,p", 0, (int) M_BGEU_I, INSN_MACRO, I1 },
184 {"bgeul", "s,t,p", 0, (int) M_BGEUL, INSN_MACRO, I2 },
185 {"bgeul", "s,I,p", 0, (int) M_BGEUL_I, INSN_MACRO, I2 },
186 {"bgez", "s,p", 0x04010000, 0xfc1f0000, CBD|RD_s, I1 },
187 {"bgezl", "s,p", 0x04030000, 0xfc1f0000, CBL|RD_s, I2|T3 },
188 {"bgezal", "s,p", 0x04110000, 0xfc1f0000, CBD|RD_s|WR_31, I1 },
189 {"bgezall", "s,p", 0x04130000, 0xfc1f0000, CBL|RD_s, I2|T3 },
190 {"bgt", "s,t,p", 0, (int) M_BGT, INSN_MACRO, I1 },
191 {"bgt", "s,I,p", 0, (int) M_BGT_I, INSN_MACRO, I1 },
192 {"bgtl", "s,t,p", 0, (int) M_BGTL, INSN_MACRO, I2 },
193 {"bgtl", "s,I,p", 0, (int) M_BGTL_I, INSN_MACRO, I2 },
194 {"bgtu", "s,t,p", 0, (int) M_BGTU, INSN_MACRO, I1 },
195 {"bgtu", "s,I,p", 0, (int) M_BGTU_I, INSN_MACRO, I1 },
196 {"bgtul", "s,t,p", 0, (int) M_BGTUL, INSN_MACRO, I2 },
197 {"bgtul", "s,I,p", 0, (int) M_BGTUL_I, INSN_MACRO, I2 },
198 {"bgtz", "s,p", 0x1c000000, 0xfc1f0000, CBD|RD_s, I1 },
199 {"bgtzl", "s,p", 0x5c000000, 0xfc1f0000, CBL|RD_s, I2|T3 },
200 {"ble", "s,t,p", 0, (int) M_BLE, INSN_MACRO, I1 },
201 {"ble", "s,I,p", 0, (int) M_BLE_I, INSN_MACRO, I1 },
202 {"blel", "s,t,p", 0, (int) M_BLEL, INSN_MACRO, I2 },
203 {"blel", "s,I,p", 0, (int) M_BLEL_I, INSN_MACRO, I2 },
204 {"bleu", "s,t,p", 0, (int) M_BLEU, INSN_MACRO, I1 },
205 {"bleu", "s,I,p", 0, (int) M_BLEU_I, INSN_MACRO, I1 },
206 {"bleul", "s,t,p", 0, (int) M_BLEUL, INSN_MACRO, I2 },
207 {"bleul", "s,I,p", 0, (int) M_BLEUL_I, INSN_MACRO, I2 },
208 {"blez", "s,p", 0x18000000, 0xfc1f0000, CBD|RD_s, I1 },
209 {"blezl", "s,p", 0x58000000, 0xfc1f0000, CBL|RD_s, I2|T3 },
210 {"blt", "s,t,p", 0, (int) M_BLT, INSN_MACRO, I1 },
211 {"blt", "s,I,p", 0, (int) M_BLT_I, INSN_MACRO, I1 },
212 {"bltl", "s,t,p", 0, (int) M_BLTL, INSN_MACRO, I2 },
213 {"bltl", "s,I,p", 0, (int) M_BLTL_I, INSN_MACRO, I2 },
214 {"bltu", "s,t,p", 0, (int) M_BLTU, INSN_MACRO, I1 },
215 {"bltu", "s,I,p", 0, (int) M_BLTU_I, INSN_MACRO, I1 },
216 {"bltul", "s,t,p", 0, (int) M_BLTUL, INSN_MACRO, I2 },
217 {"bltul", "s,I,p", 0, (int) M_BLTUL_I, INSN_MACRO, I2 },
218 {"bltz", "s,p", 0x04000000, 0xfc1f0000, CBD|RD_s, I1 },
219 {"bltzl", "s,p", 0x04020000, 0xfc1f0000, CBL|RD_s, I2|T3 },
220 {"bltzal", "s,p", 0x04100000, 0xfc1f0000, CBD|RD_s|WR_31, I1 },
221 {"bltzall", "s,p", 0x04120000, 0xfc1f0000, CBL|RD_s, I2|T3 },
222 {"bnez", "s,p", 0x14000000, 0xfc1f0000, CBD|RD_s, I1 },
223 {"bnezl", "s,p", 0x54000000, 0xfc1f0000, CBL|RD_s, I2|T3 },
224 {"bne", "s,t,p", 0x14000000, 0xfc000000, CBD|RD_s|RD_t, I1 },
225 {"bne", "s,I,p", 0, (int) M_BNE_I, INSN_MACRO, I1 },
226 {"bnel", "s,t,p", 0x54000000, 0xfc000000, CBL|RD_s|RD_t, I2|T3 },
227 {"bnel", "s,I,p", 0, (int) M_BNEL_I, INSN_MACRO, I2 },
228 {"break", "", 0x0000000d, 0xffffffff, TRAP, I1 },
229 {"break", "B", 0x0000000d, 0xfc00003f, TRAP, I32 },
230 {"break", "c", 0x0000000d, 0xfc00ffff, TRAP, I1 },
231 {"break", "c,q", 0x0000000d, 0xfc00003f, TRAP, I1 },
232 {"c.f.d", "S,T", 0x46200030, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, I1 },
233 {"c.f.d", "M,S,T", 0x46200030, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I4|I32|M1},
234 {"c.f.s", "S,T", 0x46000030, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, I1 },
235 {"c.f.s", "M,S,T", 0x46000030, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, I4|I32|M1},
236 {"c.f.ps", "S,T", 0x46c00030, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, I5 },
237 {"c.f.ps", "M,S,T", 0x46c00030, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I5 },
238 {"c.un.d", "S,T", 0x46200031, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, I1 },
239 {"c.un.d", "M,S,T", 0x46200031, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I4|I32|M1},
240 {"c.un.s", "S,T", 0x46000031, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, I1 },
241 {"c.un.s", "M,S,T", 0x46000031, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, I4|I32|M1},
242 {"c.un.ps", "S,T", 0x46c00031, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, I5 },
243 {"c.un.ps", "M,S,T", 0x46c00031, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I5 },
244 {"c.eq.d", "S,T", 0x46200032, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, I1 },
245 {"c.eq.d", "M,S,T", 0x46200032, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I4|I32|M1},
246 {"c.eq.s", "S,T", 0x46000032, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, I1 },
247 {"c.eq.s", "M,S,T", 0x46000032, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, I4|I32|M1},
248 {"c.eq.ps", "S,T", 0x46c00032, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, I5 },
249 {"c.eq.ps", "M,S,T", 0x46c00032, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I5 },
250 {"c.ueq.d", "S,T", 0x46200033, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, I1 },
251 {"c.ueq.d", "M,S,T", 0x46200033, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I4|I32|M1},
252 {"c.ueq.s", "S,T", 0x46000033, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, I1 },
253 {"c.ueq.s", "M,S,T", 0x46000033, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, I4|I32|M1},
254 {"c.ueq.ps","S,T", 0x46c00033, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, I5 },
255 {"c.ueq.ps","M,S,T", 0x46c00033, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I5 },
256 {"c.lt.s", "S,T", 0x4600003c, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, I1 },
257 {"c.lt.s", "M,S,T", 0x4600003c, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, I4|I32|M1},
258 {"c.olt.d", "S,T", 0x46200034, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, I1 },
259 {"c.olt.d", "M,S,T", 0x46200034, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I4|I32|M1},
260 {"c.olt.s", "S,T", 0x46000034, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, I1 },
261 {"c.olt.s", "M,S,T", 0x46000034, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, I4|I32|M1},
262 {"c.olt.ps","S,T", 0x46c00034, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, I5 },
263 {"c.olt.ps","M,S,T", 0x46c00034, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I5 },
264 {"c.ult.d", "S,T", 0x46200035, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, I1 },
265 {"c.ult.d", "M,S,T", 0x46200035, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I4|I32|M1},
266 {"c.ult.s", "S,T", 0x46000035, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, I1 },
267 {"c.ult.s", "M,S,T", 0x46000035, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, I4|I32|M1},
268 {"c.ult.ps","S,T", 0x46c00035, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, I5 },
269 {"c.ult.ps","M,S,T", 0x46c00035, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I5 },
270 {"c.le.s", "S,T", 0x4600003e, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, I1 },
271 {"c.le.s", "M,S,T", 0x4600003e, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, I4|I32|M1},
272 {"c.ole.d", "S,T", 0x46200036, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, I1 },
273 {"c.ole.d", "M,S,T", 0x46200036, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I4|I32|M1},
274 {"c.ole.s", "S,T", 0x46000036, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, I1 },
275 {"c.ole.s", "M,S,T", 0x46000036, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, I4|I32|M1},
276 {"c.ole.ps","S,T", 0x46c00036, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, I5 },
277 {"c.ole.ps","M,S,T", 0x46c00036, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I5 },
278 {"c.ule.d", "S,T", 0x46200037, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, I1 },
279 {"c.ule.d", "M,S,T", 0x46200037, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I4|I32|M1},
280 {"c.ule.s", "S,T", 0x46000037, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, I1 },
281 {"c.ule.s", "M,S,T", 0x46000037, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, I4|I32|M1},
282 {"c.ule.ps","S,T", 0x46c00037, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, I5 },
283 {"c.ule.ps","M,S,T", 0x46c00037, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I5 },
284 {"c.sf.d", "S,T", 0x46200038, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, I1 },
285 {"c.sf.d", "M,S,T", 0x46200038, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I4|I32|M1},
286 {"c.sf.s", "S,T", 0x46000038, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, I1 },
287 {"c.sf.s", "M,S,T", 0x46000038, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, I4|I32|M1},
288 {"c.sf.ps", "S,T", 0x46c00038, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, I5 },
289 {"c.sf.ps", "M,S,T", 0x46c00038, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I5 },
290 {"c.ngle.d","S,T", 0x46200039, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, I1 },
291 {"c.ngle.d","M,S,T", 0x46200039, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I4|I32|M1},
292 {"c.ngle.s","S,T", 0x46000039, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, I1 },
293 {"c.ngle.s","M,S,T", 0x46000039, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, I4|I32|M1},
294 {"c.ngle.ps","S,T", 0x46c00039, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, I5 },
295 {"c.ngle.ps","M,S,T", 0x46c00039, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I5 },
296 {"c.seq.d", "S,T", 0x4620003a, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, I1 },
297 {"c.seq.d", "M,S,T", 0x4620003a, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I4|I32|M1},
298 {"c.seq.s", "S,T", 0x4600003a, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, I1 },
299 {"c.seq.s", "M,S,T", 0x4600003a, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, I4|I32|M1},
300 {"c.seq.ps","S,T", 0x46c0003a, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, I5 },
301 {"c.seq.ps","M,S,T", 0x46c0003a, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I5 },
302 {"c.ngl.d", "S,T", 0x4620003b, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, I1 },
303 {"c.ngl.d", "M,S,T", 0x4620003b, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I4|I32|M1},
304 {"c.ngl.s", "S,T", 0x4600003b, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, I1 },
305 {"c.ngl.s", "M,S,T", 0x4600003b, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, I4|I32|M1},
306 {"c.ngl.ps","S,T", 0x46c0003b, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, I5 },
307 {"c.ngl.ps","M,S,T", 0x46c0003b, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I5 },
308 {"c.lt.d", "S,T", 0x4620003c, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, I1 },
309 {"c.lt.d", "M,S,T", 0x4620003c, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I4|I32|M1},
310 {"c.lt.ps", "S,T", 0x46c0003c, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, I5 },
311 {"c.lt.ps", "M,S,T", 0x46c0003c, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I5 },
312 {"c.nge.d", "S,T", 0x4620003d, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, I1 },
313 {"c.nge.d", "M,S,T", 0x4620003d, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I4|I32|M1},
314 {"c.nge.s", "S,T", 0x4600003d, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, I1 },
315 {"c.nge.s", "M,S,T", 0x4600003d, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, I4|I32|M1},
316 {"c.nge.ps","S,T", 0x46c0003d, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, I5 },
317 {"c.nge.ps","M,S,T", 0x46c0003d, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I5 },
318 {"c.le.d", "S,T", 0x4620003e, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, I1 },
319 {"c.le.d", "M,S,T", 0x4620003e, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I4|I32|M1},
320 {"c.le.ps", "S,T", 0x46c0003e, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, I5 },
321 {"c.le.ps", "M,S,T", 0x46c0003e, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I5 },
322 {"c.ngt.d", "S,T", 0x4620003f, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, I1 },
323 {"c.ngt.d", "M,S,T", 0x4620003f, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I4|I32|M1},
324 {"c.ngt.s", "S,T", 0x4600003f, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, I1 },
325 {"c.ngt.s", "M,S,T", 0x4600003f, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, I4|I32|M1},
326 {"c.ngt.ps","S,T", 0x46c0003f, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, I5 },
327 {"c.ngt.ps","M,S,T", 0x46c0003f, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I5 },
328 {"cache", "k,o(b)", 0xbc000000, 0xfc000000, RD_b, I3|I32|T3|M1},
329 {"ceil.l.d", "D,S", 0x4620000a, 0xffff003f, WR_D|RD_S|FP_D, I3 },
330 {"ceil.l.s", "D,S", 0x4600000a, 0xffff003f, WR_D|RD_S|FP_S, I3 },
331 {"ceil.w.d", "D,S", 0x4620000e, 0xffff003f, WR_D|RD_S|FP_D, I2 },
332 {"ceil.w.s", "D,S", 0x4600000e, 0xffff003f, WR_D|RD_S|FP_S, I2 },
333 {"cfc0", "t,G", 0x40400000, 0xffe007ff, LCD|WR_t|RD_C0, I1 },
334 {"cfc1", "t,G", 0x44400000, 0xffe007ff, LCD|WR_t|RD_C1|FP_S, I1 },
335 {"cfc1", "t,S", 0x44400000, 0xffe007ff, LCD|WR_t|RD_C1|FP_S, I1 },
336 {"cfc2", "t,G", 0x48400000, 0xffe007ff, LCD|WR_t|RD_C2, I1 },
337 {"cfc3", "t,G", 0x4c400000, 0xffe007ff, LCD|WR_t|RD_C3, I1 },
338 {"clo", "U,s", 0x70000021, 0xfc0007ff, WR_d|WR_t|RD_s, I32 },
339 {"clz", "U,s", 0x70000020, 0xfc0007ff, WR_d|WR_t|RD_s, I32 },
340 {"ctc0", "t,G", 0x40c00000, 0xffe007ff, COD|RD_t|WR_CC, I1 },
341 {"ctc1", "t,G", 0x44c00000, 0xffe007ff, COD|RD_t|WR_CC|FP_S, I1 },
342 {"ctc1", "t,S", 0x44c00000, 0xffe007ff, COD|RD_t|WR_CC|FP_S, I1 },
343 {"ctc2", "t,G", 0x48c00000, 0xffe007ff, COD|RD_t|WR_CC, I1 },
344 {"ctc3", "t,G", 0x4cc00000, 0xffe007ff, COD|RD_t|WR_CC, I1 },
345 {"cvt.d.l", "D,S", 0x46a00021, 0xffff003f, WR_D|RD_S|FP_D, I3 },
346 {"cvt.d.s", "D,S", 0x46000021, 0xffff003f, WR_D|RD_S|FP_D|FP_S, I1 },
347 {"cvt.d.w", "D,S", 0x46800021, 0xffff003f, WR_D|RD_S|FP_D, I1 },
348 {"cvt.l.d", "D,S", 0x46200025, 0xffff003f, WR_D|RD_S|FP_D, I3 },
349 {"cvt.l.s", "D,S", 0x46000025, 0xffff003f, WR_D|RD_S|FP_S, I3 },
350 {"cvt.s.l", "D,S", 0x46a00020, 0xffff003f, WR_D|RD_S|FP_S, I3 },
351 {"cvt.s.d", "D,S", 0x46200020, 0xffff003f, WR_D|RD_S|FP_S|FP_D, I1 },
352 {"cvt.s.w", "D,S", 0x46800020, 0xffff003f, WR_D|RD_S|FP_S, I1 },
353 {"cvt.s.pl","D,S", 0x46c00028, 0xffff003f, WR_D|RD_S|FP_S|FP_D, I5 },
354 {"cvt.s.pu","D,S", 0x46c00020, 0xffff003f, WR_D|RD_S|FP_S|FP_D, I5 },
355 {"cvt.w.d", "D,S", 0x46200024, 0xffff003f, WR_D|RD_S|FP_D, I1 },
356 {"cvt.w.s", "D,S", 0x46000024, 0xffff003f, WR_D|RD_S|FP_S, I1 },
357 {"cvt.ps.s","D,V,T", 0x46000026, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, I5 },
358 {"dabs", "d,v", 0, (int) M_DABS, INSN_MACRO, I3 },
359 {"dadd", "d,v,t", 0x0000002c, 0xfc0007ff, WR_d|RD_s|RD_t, I3 },
360 {"dadd", "t,r,I", 0, (int) M_DADD_I, INSN_MACRO, I3 },
361 {"daddi", "t,r,j", 0x60000000, 0xfc000000, WR_t|RD_s, I3 },
362 {"daddiu", "t,r,j", 0x64000000, 0xfc000000, WR_t|RD_s, I3 },
363 {"daddu", "d,v,t", 0x0000002d, 0xfc0007ff, WR_d|RD_s|RD_t, I3 },
364 {"daddu", "t,r,I", 0, (int) M_DADDU_I, INSN_MACRO, I3 },
365 /* dctr and dctw are used on the r5000. */
366 {"dctr", "o(b)", 0xbc050000, 0xfc1f0000, RD_b, I3 },
367 {"dctw", "o(b)", 0xbc090000, 0xfc1f0000, RD_b, I3 },
368 {"deret", "", 0x4200001f, 0xffffffff, 0, I32|G2|M1},
369 /* For ddiv, see the comments about div. */
370 {"ddiv", "z,s,t", 0x0000001e, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO, I3 },
371 {"ddiv", "d,v,t", 0, (int) M_DDIV_3, INSN_MACRO, I3 },
372 {"ddiv", "d,v,I", 0, (int) M_DDIV_3I, INSN_MACRO, I3 },
373 /* For ddivu, see the comments about div. */
374 {"ddivu", "z,s,t", 0x0000001f, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO, I3 },
375 {"ddivu", "d,v,t", 0, (int) M_DDIVU_3, INSN_MACRO, I3 },
376 {"ddivu", "d,v,I", 0, (int) M_DDIVU_3I, INSN_MACRO, I3 },
377 /* The MIPS assembler treats the div opcode with two operands as
378 though the first operand appeared twice (the first operand is both
379 a source and a destination). To get the div machine instruction,
380 you must use an explicit destination of $0. */
381 {"div", "z,s,t", 0x0000001a, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO, I1 },
382 {"div", "z,t", 0x0000001a, 0xffe0ffff, RD_s|RD_t|WR_HI|WR_LO, I1 },
383 {"div", "d,v,t", 0, (int) M_DIV_3, INSN_MACRO, I1 },
384 {"div", "d,v,I", 0, (int) M_DIV_3I, INSN_MACRO, I1 },
385 {"div.d", "D,V,T", 0x46200003, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, I1 },
386 {"div.s", "D,V,T", 0x46000003, 0xffe0003f, WR_D|RD_S|RD_T|FP_S, I1 },
387 /* For divu, see the comments about div. */
388 {"divu", "z,s,t", 0x0000001b, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO, I1 },
389 {"divu", "z,t", 0x0000001b, 0xffe0ffff, RD_s|RD_t|WR_HI|WR_LO, I1 },
390 {"divu", "d,v,t", 0, (int) M_DIVU_3, INSN_MACRO, I1 },
391 {"divu", "d,v,I", 0, (int) M_DIVU_3I, INSN_MACRO, I1 },
392 {"dla", "t,o(b)", 0x64000000, 0xfc000000, WR_t|RD_s, I3 }, /* daddiu */
393 {"dla", "t,A(b)", 0, (int) M_DLA_AB, INSN_MACRO, I3 },
394 {"dli", "t,j", 0x24000000, 0xffe00000, WR_t, I3 }, /* addiu */
395 {"dli", "t,i", 0x34000000, 0xffe00000, WR_t, I3 }, /* ori */
396 {"dli", "t,I", 0, (int) M_DLI, INSN_MACRO, I3 },
397
398 {"dmadd16", "s,t", 0x00000029, 0xfc00ffff, RD_s|RD_t|WR_LO|RD_LO, V1 },
399 {"dmfc0", "t,G", 0x40200000, 0xffe007ff, LCD|WR_t|RD_C0, I3 },
400 {"dmtc0", "t,G", 0x40a00000, 0xffe007ff, COD|RD_t|WR_C0|WR_CC, I3 },
401 {"dmfc1", "t,S", 0x44200000, 0xffe007ff, LCD|WR_t|RD_S|FP_S, I3 },
402 {"dmtc1", "t,S", 0x44a00000, 0xffe007ff, COD|RD_t|WR_S|FP_S, I3 },
403 {"dmfc2", "t,S", 0x48200000, 0xffe007ff, LCD|WR_t|RD_S|FP_S, I3 },
404 {"dmtc2", "t,S", 0x48a00000, 0xffe007ff, COD|RD_t|WR_S|FP_S, I3 },
405 {"dmul", "d,v,t", 0, (int) M_DMUL, INSN_MACRO, I3 },
406 {"dmul", "d,v,I", 0, (int) M_DMUL_I, INSN_MACRO, I3 },
407 {"dmulo", "d,v,t", 0, (int) M_DMULO, INSN_MACRO, I3 },
408 {"dmulo", "d,v,I", 0, (int) M_DMULO_I, INSN_MACRO, I3 },
409 {"dmulou", "d,v,t", 0, (int) M_DMULOU, INSN_MACRO, I3 },
410 {"dmulou", "d,v,I", 0, (int) M_DMULOU_I, INSN_MACRO, I3 },
411 {"dmult", "s,t", 0x0000001c, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO, I3 },
412 {"dmultu", "s,t", 0x0000001d, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO, I3 },
413 {"dneg", "d,w", 0x0000002e, 0xffe007ff, WR_d|RD_t, I3 }, /* dsub 0 */
414 {"dnegu", "d,w", 0x0000002f, 0xffe007ff, WR_d|RD_t, I3 }, /* dsubu 0*/
415 {"drem", "z,s,t", 0x0000001e, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO, I3 },
416 {"drem", "d,v,t", 3, (int) M_DREM_3, INSN_MACRO, I3 },
417 {"drem", "d,v,I", 3, (int) M_DREM_3I, INSN_MACRO, I3 },
418 {"dremu", "z,s,t", 0x0000001f, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO, I3 },
419 {"dremu", "d,v,t", 3, (int) M_DREMU_3, INSN_MACRO, I3 },
420 {"dremu", "d,v,I", 3, (int) M_DREMU_3I, INSN_MACRO, I3 },
421 {"dsllv", "d,t,s", 0x00000014, 0xfc0007ff, WR_d|RD_t|RD_s, I3 },
422 {"dsll32", "d,w,<", 0x0000003c, 0xffe0003f, WR_d|RD_t, I3 },
423 {"dsll", "d,w,s", 0x00000014, 0xfc0007ff, WR_d|RD_t|RD_s, I3 }, /* dsllv */
424 {"dsll", "d,w,>", 0x0000003c, 0xffe0003f, WR_d|RD_t, I3 }, /* dsll32 */
425 {"dsll", "d,w,<", 0x00000038, 0xffe0003f, WR_d|RD_t, I3 },
426 {"dsrav", "d,t,s", 0x00000017, 0xfc0007ff, WR_d|RD_t|RD_s, I3 },
427 {"dsra32", "d,w,<", 0x0000003f, 0xffe0003f, WR_d|RD_t, I3 },
428 {"dsra", "d,w,s", 0x00000017, 0xfc0007ff, WR_d|RD_t|RD_s, I3 }, /* dsrav */
429 {"dsra", "d,w,>", 0x0000003f, 0xffe0003f, WR_d|RD_t, I3 }, /* dsra32 */
430 {"dsra", "d,w,<", 0x0000003b, 0xffe0003f, WR_d|RD_t, I3 },
431 {"dsrlv", "d,t,s", 0x00000016, 0xfc0007ff, WR_d|RD_t|RD_s, I3 },
432 {"dsrl32", "d,w,<", 0x0000003e, 0xffe0003f, WR_d|RD_t, I3 },
433 {"dsrl", "d,w,s", 0x00000016, 0xfc0007ff, WR_d|RD_t|RD_s, I3 }, /* dsrlv */
434 {"dsrl", "d,w,>", 0x0000003e, 0xffe0003f, WR_d|RD_t, I3 }, /* dsrl32 */
435 {"dsrl", "d,w,<", 0x0000003a, 0xffe0003f, WR_d|RD_t, I3 },
436 {"dsub", "d,v,t", 0x0000002e, 0xfc0007ff, WR_d|RD_s|RD_t, I3 },
437 {"dsub", "d,v,I", 0, (int) M_DSUB_I, INSN_MACRO, I3 },
438 {"dsubu", "d,v,t", 0x0000002f, 0xfc0007ff, WR_d|RD_s|RD_t, I3 },
439 {"dsubu", "d,v,I", 0, (int) M_DSUBU_I, INSN_MACRO, I3 },
440 {"eret", "", 0x42000018, 0xffffffff, 0, I3|I32|M1},
441 {"floor.l.d", "D,S", 0x4620000b, 0xffff003f, WR_D|RD_S|FP_D, I3 },
442 {"floor.l.s", "D,S", 0x4600000b, 0xffff003f, WR_D|RD_S|FP_S, I3 },
443 {"floor.w.d", "D,S", 0x4620000f, 0xffff003f, WR_D|RD_S|FP_D, I2 },
444 {"floor.w.s", "D,S", 0x4600000f, 0xffff003f, WR_D|RD_S|FP_S, I2 },
445 {"flushi", "", 0xbc010000, 0xffffffff, 0, L1 },
446 {"flushd", "", 0xbc020000, 0xffffffff, 0, L1 },
447 {"flushid", "", 0xbc030000, 0xffffffff, 0, L1 },
448 {"hibernate","", 0x42000023, 0xffffffff, 0, V1 },
449 {"jr", "s", 0x00000008, 0xfc1fffff, UBD|RD_s, I1 },
450 {"j", "s", 0x00000008, 0xfc1fffff, UBD|RD_s, I1 }, /* jr */
451 /* SVR4 PIC code requires special handling for j, so it must be a
452 macro. */
453 {"j", "a", 0, (int) M_J_A, INSN_MACRO, I1 },
454 /* This form of j is used by the disassembler and internally by the
455 assembler, but will never match user input (because the line above
456 will match first). */
457 {"j", "a", 0x08000000, 0xfc000000, UBD, I1 },
458 {"jalr", "s", 0x0000f809, 0xfc1fffff, UBD|RD_s|WR_d, I1 },
459 {"jalr", "d,s", 0x00000009, 0xfc1f07ff, UBD|RD_s|WR_d, I1 },
460 /* SVR4 PIC code requires special handling for jal, so it must be a
461 macro. */
462 {"jal", "d,s", 0, (int) M_JAL_2, INSN_MACRO, I1 },
463 {"jal", "s", 0, (int) M_JAL_1, INSN_MACRO, I1 },
464 {"jal", "a", 0, (int) M_JAL_A, INSN_MACRO, I1 },
465 /* This form of jal is used by the disassembler and internally by the
466 assembler, but will never match user input (because the line above
467 will match first). */
468 {"jal", "a", 0x0c000000, 0xfc000000, UBD|WR_31, I1 },
469 /* jalx really should only be avaliable if mips16 is available,
470 but for now make it I1. */
471 {"jalx", "a", 0x74000000, 0xfc000000, UBD|WR_31, I1 },
472 {"la", "t,o(b)", 0x24000000, 0xfc000000, WR_t|RD_s, I1 }, /* addiu */
473 {"la", "t,A(b)", 0, (int) M_LA_AB, INSN_MACRO, I1 },
474 {"lb", "t,o(b)", 0x80000000, 0xfc000000, LDD|RD_b|WR_t, I1 },
475 {"lb", "t,A(b)", 0, (int) M_LB_AB, INSN_MACRO, I1 },
476 {"lbu", "t,o(b)", 0x90000000, 0xfc000000, LDD|RD_b|WR_t, I1 },
477 {"lbu", "t,A(b)", 0, (int) M_LBU_AB, INSN_MACRO, I1 },
478 {"ld", "t,o(b)", 0xdc000000, 0xfc000000, WR_t|RD_b, I3 },
479 {"ld", "t,o(b)", 0, (int) M_LD_OB, INSN_MACRO, I1 },
480 {"ld", "t,A(b)", 0, (int) M_LD_AB, INSN_MACRO, I1 },
481 {"ldc1", "T,o(b)", 0xd4000000, 0xfc000000, CLD|RD_b|WR_T|FP_D, I2 },
482 {"ldc1", "E,o(b)", 0xd4000000, 0xfc000000, CLD|RD_b|WR_T|FP_D, I2 },
483 {"ldc1", "T,A(b)", 0, (int) M_LDC1_AB, INSN_MACRO, I2 },
484 {"ldc1", "E,A(b)", 0, (int) M_LDC1_AB, INSN_MACRO, I2 },
485 {"l.d", "T,o(b)", 0xd4000000, 0xfc000000, CLD|RD_b|WR_T|FP_D, I2 }, /* ldc1 */
486 {"l.d", "T,o(b)", 0, (int) M_L_DOB, INSN_MACRO, I1 },
487 {"l.d", "T,A(b)", 0, (int) M_L_DAB, INSN_MACRO, I1 },
488 {"ldc2", "E,o(b)", 0xd8000000, 0xfc000000, CLD|RD_b|WR_CC, I2 },
489 {"ldc2", "E,A(b)", 0, (int) M_LDC2_AB, INSN_MACRO, I2 },
490 {"ldc3", "E,o(b)", 0xdc000000, 0xfc000000, CLD|RD_b|WR_CC, I2 },
491 {"ldc3", "E,A(b)", 0, (int) M_LDC3_AB, INSN_MACRO, I2 },
492 {"ldl", "t,o(b)", 0x68000000, 0xfc000000, LDD|WR_t|RD_b, I3 },
493 {"ldl", "t,A(b)", 0, (int) M_LDL_AB, INSN_MACRO, I3 },
494 {"ldr", "t,o(b)", 0x6c000000, 0xfc000000, LDD|WR_t|RD_b, I3 },
495 {"ldr", "t,A(b)", 0, (int) M_LDR_AB, INSN_MACRO, I3 },
496 {"ldxc1", "D,t(b)", 0x4c000001, 0xfc00f83f, LDD|WR_D|RD_t|RD_b, I4 },
497 {"lh", "t,o(b)", 0x84000000, 0xfc000000, LDD|RD_b|WR_t, I1 },
498 {"lh", "t,A(b)", 0, (int) M_LH_AB, INSN_MACRO, I1 },
499 {"lhu", "t,o(b)", 0x94000000, 0xfc000000, LDD|RD_b|WR_t, I1 },
500 {"lhu", "t,A(b)", 0, (int) M_LHU_AB, INSN_MACRO, I1 },
501 /* li is at the start of the table. */
502 {"li.d", "t,F", 0, (int) M_LI_D, INSN_MACRO, I1 },
503 {"li.d", "T,L", 0, (int) M_LI_DD, INSN_MACRO, I1 },
504 {"li.s", "t,f", 0, (int) M_LI_S, INSN_MACRO, I1 },
505 {"li.s", "T,l", 0, (int) M_LI_SS, INSN_MACRO, I1 },
506 {"ll", "t,o(b)", 0xc0000000, 0xfc000000, LDD|RD_b|WR_t, I2 },
507 {"ll", "t,A(b)", 0, (int) M_LL_AB, INSN_MACRO, I2 },
508 {"lld", "t,o(b)", 0xd0000000, 0xfc000000, LDD|RD_b|WR_t, I3 },
509 {"lld", "t,A(b)", 0, (int) M_LLD_AB, INSN_MACRO, I3 },
510 {"lui", "t,u", 0x3c000000, 0xffe00000, WR_t, I1 },
511 {"luxc1", "D,t(b)", 0x4c000005, 0xfc00f83f, LDD|WR_D|RD_t|RD_b, I5 },
512 {"lw", "t,o(b)", 0x8c000000, 0xfc000000, LDD|RD_b|WR_t, I1 },
513 {"lw", "t,A(b)", 0, (int) M_LW_AB, INSN_MACRO, I1 },
514 {"lwc0", "E,o(b)", 0xc0000000, 0xfc000000, CLD|RD_b|WR_CC, I1 },
515 {"lwc0", "E,A(b)", 0, (int) M_LWC0_AB, INSN_MACRO, I1 },
516 {"lwc1", "T,o(b)", 0xc4000000, 0xfc000000, CLD|RD_b|WR_T|FP_S, I1 },
517 {"lwc1", "E,o(b)", 0xc4000000, 0xfc000000, CLD|RD_b|WR_T|FP_S, I1 },
518 {"lwc1", "T,A(b)", 0, (int) M_LWC1_AB, INSN_MACRO, I1 },
519 {"lwc1", "E,A(b)", 0, (int) M_LWC1_AB, INSN_MACRO, I1 },
520 {"l.s", "T,o(b)", 0xc4000000, 0xfc000000, CLD|RD_b|WR_T|FP_S, I1 }, /* lwc1 */
521 {"l.s", "T,A(b)", 0, (int) M_LWC1_AB, INSN_MACRO, I1 },
522 {"lwc2", "E,o(b)", 0xc8000000, 0xfc000000, CLD|RD_b|WR_CC, I1 },
523 {"lwc2", "E,A(b)", 0, (int) M_LWC2_AB, INSN_MACRO, I1 },
524 {"lwc3", "E,o(b)", 0xcc000000, 0xfc000000, CLD|RD_b|WR_CC, I1 },
525 {"lwc3", "E,A(b)", 0, (int) M_LWC3_AB, INSN_MACRO, I1 },
526 {"lwl", "t,o(b)", 0x88000000, 0xfc000000, LDD|RD_b|WR_t, I1 },
527 {"lwl", "t,A(b)", 0, (int) M_LWL_AB, INSN_MACRO, I1 },
528 {"lcache", "t,o(b)", 0x88000000, 0xfc000000, LDD|RD_b|WR_t, I2 }, /* same */
529 {"lcache", "t,A(b)", 0, (int) M_LWL_AB, INSN_MACRO, I2 }, /* as lwl */
530 {"lwr", "t,o(b)", 0x98000000, 0xfc000000, LDD|RD_b|WR_t, I1 },
531 {"lwr", "t,A(b)", 0, (int) M_LWR_AB, INSN_MACRO, I1 },
532 {"flush", "t,o(b)", 0x98000000, 0xfc000000, LDD|RD_b|WR_t, I2 }, /* same */
533 {"flush", "t,A(b)", 0, (int) M_LWR_AB, INSN_MACRO, I2 }, /* as lwr */
534 {"lwu", "t,o(b)", 0x9c000000, 0xfc000000, LDD|RD_b|WR_t, I3 },
535 {"lwu", "t,A(b)", 0, (int) M_LWU_AB, INSN_MACRO, I3 },
536 {"lwxc1", "D,t(b)", 0x4c000000, 0xfc00f83f, LDD|WR_D|RD_t|RD_b, I4 },
537 {"mad", "s,t", 0x70000000, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO|RD_HI|RD_LO, P3 },
538 {"madu", "s,t", 0x70000001, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO|RD_HI|RD_LO, P3 },
539 {"madd.d", "D,R,S,T", 0x4c000021, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D, I4 },
540 {"madd.s", "D,R,S,T", 0x4c000020, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_S, I4 },
541 {"madd.ps", "D,R,S,T", 0x4c000026, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D, I5 },
542 {"madd", "s,t", 0x0000001c, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO, L1 },
543 {"madd", "s,t", 0x70000000, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO|RD_HI|RD_LO, I32 },
544 {"madd", "s,t", 0x70000000, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO|IS_M, G1|M1 },
545 {"madd", "d,s,t", 0x70000000, 0xfc0007ff, RD_s|RD_t|WR_HI|WR_LO|WR_d|IS_M, G1 },
546 {"maddu", "s,t", 0x0000001d, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO, L1 },
547 {"maddu", "s,t", 0x70000001, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO|RD_HI|RD_LO, I32 },
548 {"maddu", "s,t", 0x70000001, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO|IS_M, G1|M1 },
549 {"maddu", "d,s,t", 0x70000001, 0xfc0007ff, RD_s|RD_t|WR_HI|WR_LO|WR_d|IS_M, G1 },
550 {"madd16", "s,t", 0x00000028, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO|RD_HI|RD_LO, V1 },
551 {"mfc0", "t,G", 0x40000000, 0xffe007ff, LCD|WR_t|RD_C0, I1 },
552 {"mfc0", "t,G,H", 0x40000000, 0xffe007f8, LCD|WR_t|RD_C0, I32 },
553 {"mfc1", "t,S", 0x44000000, 0xffe007ff, LCD|WR_t|RD_S|FP_S, I1 },
554 {"mfc1", "t,G", 0x44000000, 0xffe007ff, LCD|WR_t|RD_S|FP_S, I1 },
555 {"mfc1", "t,G,H", 0x44000000, 0xffe007f8, LCD|WR_t|RD_S|FP_S, I32 },
556 {"mfc2", "t,G", 0x48000000, 0xffe007ff, LCD|WR_t|RD_C2, I1 },
557 {"mfc2", "t,G,H", 0x48000000, 0xffe007f8, LCD|WR_t|RD_C2, I32 },
558 {"mfc3", "t,G", 0x4c000000, 0xffe007ff, LCD|WR_t|RD_C3, I1 },
559 {"mfc3", "t,G,H", 0x4c000000, 0xffe007f8, LCD|WR_t|RD_C3, I32 },
560 {"mfhi", "d", 0x00000010, 0xffff07ff, WR_d|RD_HI, I1 },
561 {"mflo", "d", 0x00000012, 0xffff07ff, WR_d|RD_LO, I1 },
562 {"mov.d", "D,S", 0x46200006, 0xffff003f, WR_D|RD_S|FP_D, I1 },
563 {"mov.s", "D,S", 0x46000006, 0xffff003f, WR_D|RD_S|FP_S, I1 },
564 {"mov.ps", "D,S", 0x46c00006, 0xffff003f, WR_D|RD_S|FP_D, I5 },
565 {"movf", "d,s,N", 0x00000001, 0xfc0307ff, WR_d|RD_s|RD_CC|FP_D|FP_S, I4|I32|M1},
566 {"movf.d", "D,S,N", 0x46200011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_D, I4|I32|M1},
567 {"movf.s", "D,S,N", 0x46000011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_S, I4|I32|M1},
568 {"movf.ps", "D,S,N", 0x46c00011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_D, I5 },
569 {"movn", "d,v,t", 0x0000000b, 0xfc0007ff, WR_d|RD_s|RD_t, I4|I32|M1},
570 {"ffc", "d,v", 0x0000000b, 0xfc1f07ff, WR_d|RD_s, L1 },
571 {"movn.d", "D,S,t", 0x46200013, 0xffe0003f, WR_D|RD_S|RD_t|FP_D, I4|I32|M1},
572 {"movn.s", "D,S,t", 0x46000013, 0xffe0003f, WR_D|RD_S|RD_t|FP_S, I4|I32|M1},
573 {"movt", "d,s,N", 0x00010001, 0xfc0307ff, WR_d|RD_s|RD_CC, I4|I32|M1},
574 {"movt.d", "D,S,N", 0x46210011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_D, I4|I32|M1},
575 {"movt.s", "D,S,N", 0x46010011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_S, I4|I32|M1},
576 {"movt.ps", "D,S,N", 0x46c10011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_D, I5 },
577 {"movz", "d,v,t", 0x0000000a, 0xfc0007ff, WR_d|RD_s|RD_t, I4|I32|M1},
578 {"ffs", "d,v", 0x0000000a, 0xfc1f07ff, WR_d|RD_s, L1 },
579 {"movz.d", "D,S,t", 0x46200012, 0xffe0003f, WR_D|RD_S|RD_t|FP_D, I4|I32|M1},
580 {"movz.s", "D,S,t", 0x46000012, 0xffe0003f, WR_D|RD_S|RD_t|FP_S, I4|I32|M1},
581 /* move is at the top of the table. */
582 {"msub.d", "D,R,S,T", 0x4c000029, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D, I4 },
583 {"msub.s", "D,R,S,T", 0x4c000028, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_S, I4 },
584 {"msub.ps", "D,R,S,T", 0x4c00002e, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D, I5 },
585 {"msub", "s,t", 0x0000001e, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO, L1 },
586 {"msub", "s,t", 0x70000004, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO|RD_HI|RD_LO, I32 },
587 {"msubu", "s,t", 0x0000001f, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO, L1 },
588 {"msubu", "s,t", 0x70000005, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO|RD_HI|RD_LO, I32 },
589 {"mtc0", "t,G", 0x40800000, 0xffe007ff, COD|RD_t|WR_C0|WR_CC, I1 },
590 {"mtc0", "t,G,H", 0x40800000, 0xffe007f8, COD|RD_t|WR_C0|WR_CC, I32 },
591 {"mtc1", "t,S", 0x44800000, 0xffe007ff, COD|RD_t|WR_S|FP_S, I1 },
592 {"mtc1", "t,G", 0x44800000, 0xffe007ff, COD|RD_t|WR_S|FP_S, I1 },
593 {"mtc1", "t,G,H", 0x44800000, 0xffe007f8, COD|RD_t|WR_S|FP_S, I32 },
594 {"mtc2", "t,G", 0x48800000, 0xffe007ff, COD|RD_t|WR_C2|WR_CC, I1 },
595 {"mtc2", "t,G,H", 0x48800000, 0xffe007f8, COD|RD_t|WR_C2|WR_CC, I32 },
596 {"mtc3", "t,G", 0x4c800000, 0xffe007ff, COD|RD_t|WR_C3|WR_CC, I1 },
597 {"mtc3", "t,G,H", 0x4c800000, 0xffe007f8, COD|RD_t|WR_C3|WR_CC, I32 },
598 {"mthi", "s", 0x00000011, 0xfc1fffff, RD_s|WR_HI, I1 },
599 {"mtlo", "s", 0x00000013, 0xfc1fffff, RD_s|WR_LO, I1 },
600 {"mul.d", "D,V,T", 0x46200002, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, I1 },
601 {"mul.s", "D,V,T", 0x46000002, 0xffe0003f, WR_D|RD_S|RD_T|FP_S, I1 },
602 {"mul.ps", "D,V,T", 0x46c00002, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, I5 },
603 {"mul", "d,v,t", 0x70000002, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HI|WR_LO, I32|P3 },
604 {"mul", "d,v,t", 0, (int) M_MUL, INSN_MACRO, I1 },
605 {"mul", "d,v,I", 0, (int) M_MUL_I, INSN_MACRO, I1 },
606 {"mulo", "d,v,t", 0, (int) M_MULO, INSN_MACRO, I1 },
607 {"mulo", "d,v,I", 0, (int) M_MULO_I, INSN_MACRO, I1 },
608 {"mulou", "d,v,t", 0, (int) M_MULOU, INSN_MACRO, I1 },
609 {"mulou", "d,v,I", 0, (int) M_MULOU_I, INSN_MACRO, I1 },
610 {"mult", "s,t", 0x00000018, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO|IS_M, I1},
611 {"mult", "d,s,t", 0x00000018, 0xfc0007ff, RD_s|RD_t|WR_HI|WR_LO|WR_d|IS_M, G1},
612 {"multu", "s,t", 0x00000019, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO|IS_M, I1},
613 {"multu", "d,s,t", 0x00000019, 0xfc0007ff, RD_s|RD_t|WR_HI|WR_LO|WR_d|IS_M, G1},
614 {"neg", "d,w", 0x00000022, 0xffe007ff, WR_d|RD_t, I1 }, /* sub 0 */
615 {"negu", "d,w", 0x00000023, 0xffe007ff, WR_d|RD_t, I1 }, /* subu 0 */
616 {"neg.d", "D,V", 0x46200007, 0xffff003f, WR_D|RD_S|FP_D, I1 },
617 {"neg.s", "D,V", 0x46000007, 0xffff003f, WR_D|RD_S|FP_S, I1 },
618 {"neg.ps", "D,V", 0x46c00007, 0xffff003f, WR_D|RD_S|FP_D, I5 },
619 {"nmadd.d", "D,R,S,T", 0x4c000031, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D, I4 },
620 {"nmadd.s", "D,R,S,T", 0x4c000030, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_S, I4 },
621 {"nmadd.ps","D,R,S,T", 0x4c000036, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D, I5 },
622 {"nmsub.d", "D,R,S,T", 0x4c000039, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D, I4 },
623 {"nmsub.s", "D,R,S,T", 0x4c000038, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_S, I4 },
624 {"nmsub.ps","D,R,S,T", 0x4c00003e, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D, I5 },
625 /* nop is at the start of the table. */
626 {"nor", "d,v,t", 0x00000027, 0xfc0007ff, WR_d|RD_s|RD_t, I1 },
627 {"nor", "t,r,I", 0, (int) M_NOR_I, INSN_MACRO, I1 },
628 {"not", "d,v", 0x00000027, 0xfc1f07ff, WR_d|RD_s|RD_t, I1 },/*nor d,s,0*/
629 {"or", "d,v,t", 0x00000025, 0xfc0007ff, WR_d|RD_s|RD_t, I1 },
630 {"or", "t,r,I", 0, (int) M_OR_I, INSN_MACRO, I1 },
631 {"ori", "t,r,i", 0x34000000, 0xfc000000, WR_t|RD_s, I1 },
632
633 {"pll.ps", "D,V,T", 0x46c0002c, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, I5 },
634 {"plu.ps", "D,V,T", 0x46c0002d, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, I5 },
635
636 /* pref is at the start of the table. */
637 {"prefx", "h,t(b)", 0x4c00000f, 0xfc0007ff, RD_b|RD_t, I4 },
638
639 {"pul.ps", "D,V,T", 0x46c0002e, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, I5 },
640 {"puu.ps", "D,V,T", 0x46c0002f, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, I5 },
641
642 {"recip.d", "D,S", 0x46200015, 0xffff003f, WR_D|RD_S|FP_D, I4 },
643 {"recip.s", "D,S", 0x46000015, 0xffff003f, WR_D|RD_S|FP_S, I4 },
644 {"rem", "z,s,t", 0x0000001a, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO, I1 },
645 {"rem", "d,v,t", 0, (int) M_REM_3, INSN_MACRO, I1 },
646 {"rem", "d,v,I", 0, (int) M_REM_3I, INSN_MACRO, I1 },
647 {"remu", "z,s,t", 0x0000001b, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO, I1 },
648 {"remu", "d,v,t", 0, (int) M_REMU_3, INSN_MACRO, I1 },
649 {"remu", "d,v,I", 0, (int) M_REMU_3I, INSN_MACRO, I1 },
650 {"rfe", "", 0x42000010, 0xffffffff, 0, I1|T3 },
651 {"rol", "d,v,t", 0, (int) M_ROL, INSN_MACRO, I1 },
652 {"rol", "d,v,I", 0, (int) M_ROL_I, INSN_MACRO, I1 },
653 {"ror", "d,v,t", 0, (int) M_ROR, INSN_MACRO, I1 },
654 {"ror", "d,v,I", 0, (int) M_ROR_I, INSN_MACRO, I1 },
655 {"round.l.d", "D,S", 0x46200008, 0xffff003f, WR_D|RD_S|FP_D, I3 },
656 {"round.l.s", "D,S", 0x46000008, 0xffff003f, WR_D|RD_S|FP_S, I3 },
657 {"round.w.d", "D,S", 0x4620000c, 0xffff003f, WR_D|RD_S|FP_D, I2 },
658 {"round.w.s", "D,S", 0x4600000c, 0xffff003f, WR_D|RD_S|FP_S, I2 },
659 {"rsqrt.d", "D,S", 0x46200016, 0xffff003f, WR_D|RD_S|FP_D, I4 },
660 {"rsqrt.s", "D,S", 0x46000016, 0xffff003f, WR_D|RD_S|FP_S, I4 },
661 {"sb", "t,o(b)", 0xa0000000, 0xfc000000, SM|RD_t|RD_b, I1 },
662 {"sb", "t,A(b)", 0, (int) M_SB_AB, INSN_MACRO, I1 },
663 {"sc", "t,o(b)", 0xe0000000, 0xfc000000, SM|RD_t|WR_t|RD_b, I2 },
664 {"sc", "t,A(b)", 0, (int) M_SC_AB, INSN_MACRO, I2 },
665 {"scd", "t,o(b)", 0xf0000000, 0xfc000000, SM|RD_t|WR_t|RD_b, I3 },
666 {"scd", "t,A(b)", 0, (int) M_SCD_AB, INSN_MACRO, I3 },
667 {"sd", "t,o(b)", 0xfc000000, 0xfc000000, SM|RD_t|RD_b, I3 },
668 {"sd", "t,o(b)", 0, (int) M_SD_OB, INSN_MACRO, I1 },
669 {"sd", "t,A(b)", 0, (int) M_SD_AB, INSN_MACRO, I1 },
670 {"sdbbp", "", 0x0000000e, 0xffffffff, TRAP, G2|M1 },
671 {"sdbbp", "c", 0x0000000e, 0xfc00ffff, TRAP, G2|M1 },
672 {"sdbbp", "c,q", 0x0000000e, 0xfc00003f, TRAP, G2|M1 },
673 {"sdbbp", "", 0x7000003f, 0xffffffff, TRAP, I32 },
674 {"sdbbp", "B", 0x7000003f, 0xfc00003f, TRAP, I32 },
675 {"sdc1", "T,o(b)", 0xf4000000, 0xfc000000, SM|RD_T|RD_b|FP_D, I2 },
676 {"sdc1", "E,o(b)", 0xf4000000, 0xfc000000, SM|RD_T|RD_b|FP_D, I2 },
677 {"sdc1", "T,A(b)", 0, (int) M_SDC1_AB, INSN_MACRO, I2 },
678 {"sdc1", "E,A(b)", 0, (int) M_SDC1_AB, INSN_MACRO, I2 },
679 {"sdc2", "E,o(b)", 0xf8000000, 0xfc000000, SM|RD_C2|RD_b, I2 },
680 {"sdc2", "E,A(b)", 0, (int) M_SDC2_AB, INSN_MACRO, I2 },
681 {"sdc3", "E,o(b)", 0xfc000000, 0xfc000000, SM|RD_C3|RD_b, I2 },
682 {"sdc3", "E,A(b)", 0, (int) M_SDC3_AB, INSN_MACRO, I2 },
683 {"s.d", "T,o(b)", 0xf4000000, 0xfc000000, SM|RD_T|RD_b|FP_D, I2 },
684 {"s.d", "T,o(b)", 0, (int) M_S_DOB, INSN_MACRO, I1 },
685 {"s.d", "T,A(b)", 0, (int) M_S_DAB, INSN_MACRO, I1 },
686 {"sdl", "t,o(b)", 0xb0000000, 0xfc000000, SM|RD_t|RD_b, I3 },
687 {"sdl", "t,A(b)", 0, (int) M_SDL_AB, INSN_MACRO, I3 },
688 {"sdr", "t,o(b)", 0xb4000000, 0xfc000000, SM|RD_t|RD_b, I3 },
689 {"sdr", "t,A(b)", 0, (int) M_SDR_AB, INSN_MACRO, I3 },
690 {"sdxc1", "S,t(b)", 0x4c000009, 0xfc0007ff, SM|RD_S|RD_t|RD_b, I4 },
691 {"selsl", "d,v,t", 0x00000005, 0xfc0007ff, WR_d|RD_s|RD_t,L1 },
692 {"selsr", "d,v,t", 0x00000001, 0xfc0007ff, WR_d|RD_s|RD_t,L1 },
693 {"seq", "d,v,t", 0, (int) M_SEQ, INSN_MACRO, I1 },
694 {"seq", "d,v,I", 0, (int) M_SEQ_I, INSN_MACRO, I1 },
695 {"sge", "d,v,t", 0, (int) M_SGE, INSN_MACRO, I1 },
696 {"sge", "d,v,I", 0, (int) M_SGE_I, INSN_MACRO, I1 },
697 {"sgeu", "d,v,t", 0, (int) M_SGEU, INSN_MACRO, I1 },
698 {"sgeu", "d,v,I", 0, (int) M_SGEU_I, INSN_MACRO, I1 },
699 {"sgt", "d,v,t", 0, (int) M_SGT, INSN_MACRO, I1 },
700 {"sgt", "d,v,I", 0, (int) M_SGT_I, INSN_MACRO, I1 },
701 {"sgtu", "d,v,t", 0, (int) M_SGTU, INSN_MACRO, I1 },
702 {"sgtu", "d,v,I", 0, (int) M_SGTU_I, INSN_MACRO, I1 },
703 {"sh", "t,o(b)", 0xa4000000, 0xfc000000, SM|RD_t|RD_b, I1 },
704 {"sh", "t,A(b)", 0, (int) M_SH_AB, INSN_MACRO, I1 },
705 {"sle", "d,v,t", 0, (int) M_SLE, INSN_MACRO, I1 },
706 {"sle", "d,v,I", 0, (int) M_SLE_I, INSN_MACRO, I1 },
707 {"sleu", "d,v,t", 0, (int) M_SLEU, INSN_MACRO, I1 },
708 {"sleu", "d,v,I", 0, (int) M_SLEU_I, INSN_MACRO, I1 },
709 {"sllv", "d,t,s", 0x00000004, 0xfc0007ff, WR_d|RD_t|RD_s, I1 },
710 {"sll", "d,w,s", 0x00000004, 0xfc0007ff, WR_d|RD_t|RD_s, I1 }, /* sllv */
711 {"sll", "d,w,<", 0x00000000, 0xffe0003f, WR_d|RD_t, I1 },
712 {"slt", "d,v,t", 0x0000002a, 0xfc0007ff, WR_d|RD_s|RD_t, I1 },
713 {"slt", "d,v,I", 0, (int) M_SLT_I, INSN_MACRO, I1 },
714 {"slti", "t,r,j", 0x28000000, 0xfc000000, WR_t|RD_s, I1 },
715 {"sltiu", "t,r,j", 0x2c000000, 0xfc000000, WR_t|RD_s, I1 },
716 {"sltu", "d,v,t", 0x0000002b, 0xfc0007ff, WR_d|RD_s|RD_t, I1 },
717 {"sltu", "d,v,I", 0, (int) M_SLTU_I, INSN_MACRO, I1 },
718 {"sne", "d,v,t", 0, (int) M_SNE, INSN_MACRO, I1 },
719 {"sne", "d,v,I", 0, (int) M_SNE_I, INSN_MACRO, I1 },
720 {"sqrt.d", "D,S", 0x46200004, 0xffff003f, WR_D|RD_S|FP_D, I2 },
721 {"sqrt.s", "D,S", 0x46000004, 0xffff003f, WR_D|RD_S|FP_S, I2 },
722 {"srav", "d,t,s", 0x00000007, 0xfc0007ff, WR_d|RD_t|RD_s, I1 },
723 {"sra", "d,w,s", 0x00000007, 0xfc0007ff, WR_d|RD_t|RD_s, I1 }, /* srav */
724 {"sra", "d,w,<", 0x00000003, 0xffe0003f, WR_d|RD_t, I1 },
725 {"srlv", "d,t,s", 0x00000006, 0xfc0007ff, WR_d|RD_t|RD_s, I1 },
726 {"srl", "d,w,s", 0x00000006, 0xfc0007ff, WR_d|RD_t|RD_s, I1 }, /* srlv */
727 {"srl", "d,w,<", 0x00000002, 0xffe0003f, WR_d|RD_t, I1 },
728 /* ssnop is at the start of the table. */
729 {"standby", "", 0x42000021, 0xffffffff, 0, V1 },
730 {"sub", "d,v,t", 0x00000022, 0xfc0007ff, WR_d|RD_s|RD_t, I1 },
731 {"sub", "d,v,I", 0, (int) M_SUB_I, INSN_MACRO, I1 },
732 {"sub.d", "D,V,T", 0x46200001, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, I1 },
733 {"sub.s", "D,V,T", 0x46000001, 0xffe0003f, WR_D|RD_S|RD_T|FP_S, I1 },
734 {"sub.ps", "D,V,T", 0x46c00001, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, I5 },
735 {"subu", "d,v,t", 0x00000023, 0xfc0007ff, WR_d|RD_s|RD_t, I1 },
736 {"subu", "d,v,I", 0, (int) M_SUBU_I, INSN_MACRO, I1 },
737 {"suspend", "", 0x42000022, 0xffffffff, 0, V1 },
738 {"suxc1", "S,t(b)", 0x4c00000d, 0xfc0007ff, SM|RD_S|RD_t|RD_b, I5 },
739 {"sw", "t,o(b)", 0xac000000, 0xfc000000, SM|RD_t|RD_b, I1 },
740 {"sw", "t,A(b)", 0, (int) M_SW_AB, INSN_MACRO, I1 },
741 {"swc0", "E,o(b)", 0xe0000000, 0xfc000000, SM|RD_C0|RD_b, I1 },
742 {"swc0", "E,A(b)", 0, (int) M_SWC0_AB, INSN_MACRO, I1 },
743 {"swc1", "T,o(b)", 0xe4000000, 0xfc000000, SM|RD_T|RD_b|FP_S, I1 },
744 {"swc1", "E,o(b)", 0xe4000000, 0xfc000000, SM|RD_T|RD_b|FP_S, I1 },
745 {"swc1", "T,A(b)", 0, (int) M_SWC1_AB, INSN_MACRO, I1 },
746 {"swc1", "E,A(b)", 0, (int) M_SWC1_AB, INSN_MACRO, I1 },
747 {"s.s", "T,o(b)", 0xe4000000, 0xfc000000, SM|RD_T|RD_b|FP_S, I1 }, /* swc1 */
748 {"s.s", "T,A(b)", 0, (int) M_SWC1_AB, INSN_MACRO, I1 },
749 {"swc2", "E,o(b)", 0xe8000000, 0xfc000000, SM|RD_C2|RD_b, I1 },
750 {"swc2", "E,A(b)", 0, (int) M_SWC2_AB, INSN_MACRO, I1 },
751 {"swc3", "E,o(b)", 0xec000000, 0xfc000000, SM|RD_C3|RD_b, I1 },
752 {"swc3", "E,A(b)", 0, (int) M_SWC3_AB, INSN_MACRO, I1 },
753 {"swl", "t,o(b)", 0xa8000000, 0xfc000000, SM|RD_t|RD_b, I1 },
754 {"swl", "t,A(b)", 0, (int) M_SWL_AB, INSN_MACRO, I1 },
755 {"scache", "t,o(b)", 0xa8000000, 0xfc000000, RD_t|RD_b, I2 }, /* same */
756 {"scache", "t,A(b)", 0, (int) M_SWL_AB, INSN_MACRO, I2 }, /* as swl */
757 {"swr", "t,o(b)", 0xb8000000, 0xfc000000, SM|RD_t|RD_b, I1 },
758 {"swr", "t,A(b)", 0, (int) M_SWR_AB, INSN_MACRO, I1 },
759 {"invalidate", "t,o(b)",0xb8000000, 0xfc000000, RD_t|RD_b, I2 }, /* same */
760 {"invalidate", "t,A(b)",0, (int) M_SWR_AB, INSN_MACRO, I2 }, /* as swr */
761 {"swxc1", "S,t(b)", 0x4c000008, 0xfc0007ff, SM|RD_S|RD_t|RD_b, I4 },
762 {"sync", "", 0x0000000f, 0xffffffff, INSN_SYNC, I2|G1 },
763 {"sync.p", "", 0x0000040f, 0xffffffff, INSN_SYNC, I2 },
764 {"sync.l", "", 0x0000000f, 0xffffffff, INSN_SYNC, I2 },
765 {"syscall", "", 0x0000000c, 0xffffffff, TRAP, I1 },
766 {"syscall", "B", 0x0000000c, 0xfc00003f, TRAP, I1 },
767 {"teqi", "s,j", 0x040c0000, 0xfc1f0000, RD_s|TRAP, I2 },
768 {"teq", "s,t", 0x00000034, 0xfc00ffff, RD_s|RD_t|TRAP, I2 },
769 {"teq", "s,t,q", 0x00000034, 0xfc00003f, RD_s|RD_t|TRAP, I2 },
770 {"teq", "s,j", 0x040c0000, 0xfc1f0000, RD_s|TRAP, I2 }, /* teqi */
771 {"teq", "s,I", 0, (int) M_TEQ_I, INSN_MACRO, I2 },
772 {"tgei", "s,j", 0x04080000, 0xfc1f0000, RD_s|TRAP, I2 },
773 {"tge", "s,t", 0x00000030, 0xfc00ffff, RD_s|RD_t|TRAP, I2 },
774 {"tge", "s,t,q", 0x00000030, 0xfc00003f, RD_s|RD_t|TRAP, I2 },
775 {"tge", "s,j", 0x04080000, 0xfc1f0000, RD_s|TRAP, I2 }, /* tgei */
776 {"tge", "s,I", 0, (int) M_TGE_I, INSN_MACRO, I2 },
777 {"tgeiu", "s,j", 0x04090000, 0xfc1f0000, RD_s|TRAP, I2 },
778 {"tgeu", "s,t", 0x00000031, 0xfc00ffff, RD_s|RD_t|TRAP, I2 },
779 {"tgeu", "s,t,q", 0x00000031, 0xfc00003f, RD_s|RD_t|TRAP, I2 },
780 {"tgeu", "s,j", 0x04090000, 0xfc1f0000, RD_s|TRAP, I2 }, /* tgeiu */
781 {"tgeu", "s,I", 0, (int) M_TGEU_I, INSN_MACRO, I2 },
782 {"tlbp", "", 0x42000008, 0xffffffff, INSN_TLB, I1|M1 },
783 {"tlbr", "", 0x42000001, 0xffffffff, INSN_TLB, I1|M1 },
784 {"tlbwi", "", 0x42000002, 0xffffffff, INSN_TLB, I1|M1 },
785 {"tlbwr", "", 0x42000006, 0xffffffff, INSN_TLB, I1|M1 },
786 {"tlti", "s,j", 0x040a0000, 0xfc1f0000, RD_s|TRAP, I2 },
787 {"tlt", "s,t", 0x00000032, 0xfc00ffff, RD_s|RD_t|TRAP, I2 },
788 {"tlt", "s,t,q", 0x00000032, 0xfc00003f, RD_s|RD_t|TRAP, I2 },
789 {"tlt", "s,j", 0x040a0000, 0xfc1f0000, RD_s|TRAP, I2 }, /* tlti */
790 {"tlt", "s,I", 0, (int) M_TLT_I, INSN_MACRO, I2 },
791 {"tltiu", "s,j", 0x040b0000, 0xfc1f0000, RD_s|TRAP, I2 },
792 {"tltu", "s,t", 0x00000033, 0xfc00ffff, RD_s|RD_t|TRAP, I2 },
793 {"tltu", "s,t,q", 0x00000033, 0xfc00003f, RD_s|RD_t|TRAP, I2 },
794 {"tltu", "s,j", 0x040b0000, 0xfc1f0000, RD_s|TRAP, I2 }, /* tltiu */
795 {"tltu", "s,I", 0, (int) M_TLTU_I, INSN_MACRO, I2 },
796 {"tnei", "s,j", 0x040e0000, 0xfc1f0000, RD_s|TRAP, I2 },
797 {"tne", "s,t", 0x00000036, 0xfc00ffff, RD_s|RD_t|TRAP, I2 },
798 {"tne", "s,t,q", 0x00000036, 0xfc00003f, RD_s|RD_t|TRAP, I2 },
799 {"tne", "s,j", 0x040e0000, 0xfc1f0000, RD_s|TRAP, I2 }, /* tnei */
800 {"tne", "s,I", 0, (int) M_TNE_I, INSN_MACRO, I2 },
801 {"trunc.l.d", "D,S", 0x46200009, 0xffff003f, WR_D|RD_S|FP_D, I3 },
802 {"trunc.l.s", "D,S", 0x46000009, 0xffff003f, WR_D|RD_S|FP_S, I3 },
803 {"trunc.w.d", "D,S", 0x4620000d, 0xffff003f, WR_D|RD_S|FP_D, I2 },
804 {"trunc.w.d", "D,S,x", 0x4620000d, 0xffff003f, WR_D|RD_S|FP_D, I2 },
805 {"trunc.w.d", "D,S,t", 0, (int) M_TRUNCWD, INSN_MACRO, I1 },
806 {"trunc.w.s", "D,S", 0x4600000d, 0xffff003f, WR_D|RD_S|FP_S, I2 },
807 {"trunc.w.s", "D,S,x", 0x4600000d, 0xffff003f, WR_D|RD_S|FP_S, I2 },
808 {"trunc.w.s", "D,S,t", 0, (int) M_TRUNCWS, INSN_MACRO, I1 },
809 {"uld", "t,o(b)", 0, (int) M_ULD, INSN_MACRO, I3 },
810 {"uld", "t,A(b)", 0, (int) M_ULD_A, INSN_MACRO, I3 },
811 {"ulh", "t,o(b)", 0, (int) M_ULH, INSN_MACRO, I1 },
812 {"ulh", "t,A(b)", 0, (int) M_ULH_A, INSN_MACRO, I1 },
813 {"ulhu", "t,o(b)", 0, (int) M_ULHU, INSN_MACRO, I1 },
814 {"ulhu", "t,A(b)", 0, (int) M_ULHU_A, INSN_MACRO, I1 },
815 {"ulw", "t,o(b)", 0, (int) M_ULW, INSN_MACRO, I1 },
816 {"ulw", "t,A(b)", 0, (int) M_ULW_A, INSN_MACRO, I1 },
817 {"usd", "t,o(b)", 0, (int) M_USD, INSN_MACRO, I3 },
818 {"usd", "t,A(b)", 0, (int) M_USD_A, INSN_MACRO, I3 },
819 {"ush", "t,o(b)", 0, (int) M_USH, INSN_MACRO, I1 },
820 {"ush", "t,A(b)", 0, (int) M_USH_A, INSN_MACRO, I1 },
821 {"usw", "t,o(b)", 0, (int) M_USW, INSN_MACRO, I1 },
822 {"usw", "t,A(b)", 0, (int) M_USW_A, INSN_MACRO, I1 },
823 {"xor", "d,v,t", 0x00000026, 0xfc0007ff, WR_d|RD_s|RD_t, I1 },
824 {"xor", "t,r,I", 0, (int) M_XOR_I, INSN_MACRO, I1 },
825 {"xori", "t,r,i", 0x38000000, 0xfc000000, WR_t|RD_s, I1 },
826 {"wait", "", 0x42000020, 0xffffffff, TRAP, I3|I32|M1},
827 {"wait", "J", 0x42000020, 0xfe00003f, TRAP, I32 },
828 {"waiti", "", 0x42000020, 0xffffffff, TRAP, L1 },
829 {"wb", "o(b)", 0xbc040000, 0xfc1f0000, SM|RD_b, L1 },
830 /* No hazard protection on coprocessor instructions--they shouldn't
831 change the state of the processor and if they do it's up to the
832 user to put in nops as necessary. These are at the end so that the
833 disasembler recognizes more specific versions first. */
834 {"c0", "C", 0x42000000, 0xfe000000, 0, I1 },
835 {"c1", "C", 0x46000000, 0xfe000000, 0, I1 },
836 {"c2", "C", 0x4a000000, 0xfe000000, 0, I1 },
837 {"c3", "C", 0x4e000000, 0xfe000000, 0, I1 },
838 {"cop0", "C", 0, (int) M_COP0, INSN_MACRO, I1 },
839 {"cop1", "C", 0, (int) M_COP1, INSN_MACRO, I1 },
840 {"cop2", "C", 0, (int) M_COP2, INSN_MACRO, I1 },
841 {"cop3", "C", 0, (int) M_COP3, INSN_MACRO, I1 },
842
843 /* Conflicts with the 4650's "mul" instruction. Nobody's using the
844 4010 any more, so move this insn out of the way. If the object
845 format gave us more info, we could do this right. */
846 {"addciu", "t,r,j", 0x70000000, 0xfc000000, WR_t|RD_s, L1 },
847 };
848
849 #define MIPS_NUM_OPCODES \
850 ((sizeof mips_builtin_opcodes) / (sizeof (mips_builtin_opcodes[0])))
851 const int bfd_mips_num_builtin_opcodes = MIPS_NUM_OPCODES;
852
853 /* const removed from the following to allow for dynamic extensions to the
854 * built-in instruction set. */
855 struct mips_opcode *mips_opcodes =
856 (struct mips_opcode *) mips_builtin_opcodes;
857 int bfd_mips_num_opcodes = MIPS_NUM_OPCODES;
858 #undef MIPS_NUM_OPCODES
859
GDB Binutils - Deliverables
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