opcodes/mn10300-opc.c

   1 /* Assemble Matsushita MN10300 instructions.
   2    Copyright (C) 1996 Free Software Foundation, Inc.
   3
   4 This program is free software; you can redistribute it and/or modify
   5 it under the terms of the GNU General Public License as published by
   6 the Free Software Foundation; either version 2 of the License, or
   7 (at your option) any later version.
   8
   9 This program is distributed in the hope that it will be useful,
  10 but WITHOUT ANY WARRANTY; without even the implied warranty of
  11 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12 GNU General Public License for more details.
  13
  14 You should have received a copy of the GNU General Public License
  15 along with this program; if not, write to the Free Software
  16 Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */
  17
  18 #include "ansidecl.h"
  19 #include "opcode/mn10300.h"
  20
  21 \f
  22 const struct mn10300_operand mn10300_operands[] = {
  23 #define UNUSED  0
  24   {0, 0, 0},
  25
  26 #define DN0      (UNUSED+1)
  27   {2, 0, MN10300_OPERAND_DREG},
  28
  29 #define DN1      (DN0+1)
  30   {2, 2, MN10300_OPERAND_DREG},
  31
  32 #define DN2      (DN1+1)
  33   {2, 4, MN10300_OPERAND_DREG},
  34
  35 #define DM0      (DN2+1)
  36   {2, 0, MN10300_OPERAND_DREG},
  37
  38 #define DM1      (DM0+1)
  39   {2, 2, MN10300_OPERAND_DREG},
  40
  41 #define DM2      (DM1+1)
  42   {2, 4, MN10300_OPERAND_DREG},
  43
  44 #define AN0      (DM2+1)
  45   {2, 0, MN10300_OPERAND_AREG},
  46
  47 #define AN1      (AN0+1)
  48   {2, 2, MN10300_OPERAND_AREG},
  49
  50 #define AN2      (AN1+1)
  51   {2, 4, MN10300_OPERAND_AREG},
  52
  53 #define AM0      (AN2+1)
  54   {2, 0, MN10300_OPERAND_AREG},
  55
  56 #define AM1      (AM0+1)
  57   {2, 2, MN10300_OPERAND_AREG},
  58
  59 #define AM2      (AM1+1)
  60   {2, 4, MN10300_OPERAND_AREG},
  61
  62 #define IMM8    (AM2+1)
  63   {8, 0, MN10300_OPERAND_PROMOTE},
  64
  65 #define IMM16    (IMM8+1)
  66   {16, 0, MN10300_OPERAND_PROMOTE},
  67
  68 /* 32bit immediate, high 16 bits in the main instruction
  69    word, 16bits in the extension word.
  70
  71    The "bits" field indicates how many bits are in the
  72    main instruction word for MN10300_OPERAND_SPLIT!  */
  73 #define IMM32    (IMM16+1)
  74   {16, 0, MN10300_OPERAND_SPLIT},
  75
  76 /* 32bit immediate, high 16 bits in the main instruction
  77    word, 16bits in the extension word, low 16bits are left
  78    shifted 8 places.
  79
  80    The "bits" field indicates how many bits are in the
  81    main instruction word for MN10300_OPERAND_SPLIT!  */
  82 #define IMM32_LOWSHIFT8    (IMM32+1)
  83   {16, 8, MN10300_OPERAND_SPLIT},
  84
  85 /* 32bit immediate, high 24 bits in the main instruction
  86    word, 8 in the extension word.
  87
  88    The "bits" field indicates how many bits are in the
  89    main instruction word for MN10300_OPERAND_SPLIT!  */
  90 #define IMM32_HIGH24    (IMM32_LOWSHIFT8+1)
  91   {24, 0, MN10300_OPERAND_SPLIT},
  92
  93 /* 32bit immediate, high 24 bits in the main instruction
  94    word, 8 in the extension word, low 8 bits are left
  95    shifted 16 places.
  96
  97    The "bits" field indicates how many bits are in the
  98    main instruction word for MN10300_OPERAND_SPLIT!  */
  99 #define IMM32_HIGH24_LOWSHIFT16    (IMM32_HIGH24+1)
 100   {24, 16, MN10300_OPERAND_SPLIT},
 101
 102 #define SP    (IMM32_HIGH24_LOWSHIFT16+1)
 103   {8, 0, MN10300_OPERAND_SP},
 104
 105 #define PSW    (SP+1)
 106   {0, 0, MN10300_OPERAND_PSW},
 107
 108 #define MDR    (PSW+1)
 109   {0, 0, MN10300_OPERAND_MDR},
 110
 111 #define DI (MDR+1)
 112   {2, 2, MN10300_OPERAND_DREG},
 113
 114 #define SD8    (DI+1)
 115   {8, 0, MN10300_OPERAND_SIGNED | MN10300_OPERAND_PROMOTE},
 116
 117 #define SD16    (SD8+1)
 118   {16, 0, MN10300_OPERAND_SIGNED | MN10300_OPERAND_PROMOTE},
 119
 120 #define SD8N    (SD16+1)
 121   {8, 0, MN10300_OPERAND_SIGNED},
 122
 123 #define SD8N_SHIFT8    (SD8N+1)
 124   {8, 8, MN10300_OPERAND_SIGNED},
 125
 126 #define SIMM8    (SD8N_SHIFT8+1)
 127   {8, 0, MN10300_OPERAND_SIGNED | MN10300_OPERAND_PROMOTE},
 128
 129 #define SIMM16    (SIMM8+1)
 130   {16, 0, MN10300_OPERAND_SIGNED | MN10300_OPERAND_PROMOTE},
 131
 132 #define PAREN   (SIMM16+1)
 133   {0, 0, MN10300_OPERAND_PAREN},
 134
 135 #define DN01     (PAREN+1)
 136   {2, 0, MN10300_OPERAND_DREG | MN10300_OPERAND_REPEATED},
 137
 138 #define AN01     (DN01+1)
 139   {2, 0, MN10300_OPERAND_AREG | MN10300_OPERAND_REPEATED},
 140
 141 #define D16_SHIFT (AN01+1)
 142   {16, 8, MN10300_OPERAND_PROMOTE},
 143
 144 #define IMM8E    (D16_SHIFT+1)
 145   {8, 0, MN10300_OPERAND_EXTENDED},
 146
 147 #define IMM8E_SHIFT8    (IMM8E+1)
 148   {8, 8, MN10300_OPERAND_EXTENDED},
 149
 150 #define IMM8_SHIFT8 (IMM8E_SHIFT8 + 1)
 151   {8, 8, 0},
 152
 153 } ;
 154
 155 #define MEM(ADDR) PAREN, ADDR, PAREN
 156 #define MEM2(ADDR1,ADDR2) PAREN, ADDR1, ADDR2, PAREN
 157 \f
 158 /* The opcode table.
 159
 160    The format of the opcode table is:
 161
 162    NAME         OPCODE          MASK            { OPERANDS }
 163
 164    NAME is the name of the instruction.
 165    OPCODE is the instruction opcode.
 166    MASK is the opcode mask; this is used to tell the disassembler
 167      which bits in the actual opcode must match OPCODE.
 168    OPERANDS is the list of operands.
 169
 170    The disassembler reads the table in order and prints the first
 171    instruction which matches, so this table is sorted to put more
 172    specific instructions before more general instructions.  It is also
 173    sorted by major opcode.  */
 174
 175 const struct mn10300_opcode mn10300_opcodes[] = {
 176 { "mov",        0x8000,         0xf000,         FMT_S1, {SIMM8, DN01}},
 177 { "mov",        0x80,           0xf0,           FMT_S0, {DM1, DN0}},
 178 { "mov",        0xf1e0,         0xfff0,         FMT_D0, {DM1, AN0}},
 179 { "mov",        0xf1d0,         0xfff0,         FMT_D0, {AM1, DN0}},
 180 { "mov",        0x9000,         0xf000,         FMT_S1, {IMM8, AN01}},
 181 { "mov",        0x90,           0xf0,           FMT_S0, {AM1, AN0}},
 182 { "mov",        0x3c,           0xfc,           FMT_S0, {SP, AN0}},
 183 { "mov",        0xf2f0,         0xfff3,         FMT_D0, {AM1, SP}},
 184 { "mov",        0xf2e4,         0xfffc,         FMT_D0, {PSW, DN0}},
 185 { "mov",        0xf2f3,         0xfff3,         FMT_D0, {DM1, PSW}},
 186 { "mov",        0xf2e0,         0xfffc,         FMT_D0, {MDR, DN0}},
 187 { "mov",        0xf2f2,         0xfff3,         FMT_D0, {DM1, MDR}},
 188 { "mov",        0x70,           0xf0,           FMT_S0, {MEM(AM0), DN1}},
 189 { "mov",        0xf80000,       0xfff000,       FMT_D1, {MEM2(SD8, AM0), DN1}},
 190 { "mov",        0xfa000000,     0xfff00000,     FMT_D2, {MEM2(SD16, AM0), DN1}},
 191 { "mov",        0xfc000000,     0xfff00000,     FMT_D4, {MEM2(IMM32,AM0), DN1}},
 192 { "mov",        0x5800,         0xfc00,         FMT_S1, {MEM2(IMM8, SP), DN0}},
 193 { "mov",        0xfab40000,     0xfffc0000,     FMT_D2, {MEM2(IMM16, SP), DN0}},
 194 { "mov",        0xfcb40000,     0xfffc0000,     FMT_D4, {MEM2(IMM32, SP), DN0}},
 195 { "mov",        0xf300,         0xffc0,         FMT_D0, {MEM2(DI, AM0), DN2}},
 196 { "mov",        0x300000,       0xfc0000,       FMT_S2, {MEM(IMM16), DN0}},
 197 { "mov",        0xfca40000,     0xfffc0000,     FMT_D4, {MEM(IMM32), DN0}},
 198 { "mov",        0xf000,         0xfff0,         FMT_D0, {MEM(AM0), AN1}},
 199 { "mov",        0xf82000,       0xfff000,       FMT_D1, {MEM2(SD8,AM0), AN1}},
 200 { "mov",        0xfa200000,     0xfff00000,     FMT_D2, {MEM2(SD16, AM0), AN1}},
 201 { "mov",        0xfc200000,     0xfff00000,     FMT_D4, {MEM2(IMM32,AM0), AN1}},
 202 { "mov",        0x5c00,         0xfc00,         FMT_S1, {MEM2(IMM8, SP), AN0}},
 203 { "mov",        0xfab00000,     0xfffc0000,     FMT_D2, {MEM2(IMM16, SP), AN0}},
 204 { "mov",        0xfcb00000,     0xfffc0000,     FMT_D4, {MEM2(IMM32, SP), AN0}},
 205 { "mov",        0xf380,         0xffc0,         FMT_D0, {MEM2(DI, AM0), AN2}},
 206 { "mov",        0xfaa00000,     0xfffc0000,     FMT_D2, {MEM(IMM16), AN0}},
 207 { "mov",        0xfca00000,     0xfffc0000,     FMT_D4, {MEM(IMM32), AN0}},
 208 { "mov",        0xf8f000,       0xfffc00,       FMT_D1, {MEM2(SD8N, AM0), SP}},
 209 { "mov",        0x60,           0xf0,           FMT_S0, {DM1, MEM(AN0)}},
 210 { "mov",        0xf81000,       0xfff000,       FMT_D1, {DM1, MEM2(SD8, AN0)}},
 211 { "mov",        0xfa100000,     0xfff00000,     FMT_D2, {DM1, MEM2(SD16, AN0)}},
 212 { "mov",        0xfc100000,     0xfff00000,     FMT_D4, {DM1, MEM2(IMM32,AN0)}},
 213 { "mov",        0x4200,         0xf300,         FMT_S1, {DM1, MEM2(IMM8, SP)}},
 214 { "mov",        0xfa910000,     0xfff30000,     FMT_D2, {DM1, MEM2(IMM16, SP)}},
 215 { "mov",        0xfc910000,     0xfff30000,     FMT_D4, {DM1, MEM2(IMM32, SP)}},
 216 { "mov",        0xf340,         0xffc0,         FMT_D0, {DM2, MEM2(DI, AN0)}},
 217 { "mov",        0x010000,       0xf30000,       FMT_S2, {DM1, MEM(IMM16)}},
 218 { "mov",        0xfc810000,     0xfff30000,     FMT_D4, {DM1, MEM(IMM32)}},
 219 { "mov",        0xf010,         0xfff0,         FMT_D0, {AM1, MEM(AN0)}},
 220 { "mov",        0xf83000,       0xfff000,       FMT_D1, {AM1, MEM2(SD8, AN0)}},
 221 { "mov",        0xfa300000,     0xfff00000,     FMT_D2, {AM1, MEM2(SD16, AN0)}},
 222 { "mov",        0xfc300000,     0xfff00000,     FMT_D4, {AM1, MEM2(IMM32,AN0)}},
 223 { "mov",        0x4300,         0xf300,         FMT_S1, {AM1, MEM2(IMM8, SP)}},
 224 { "mov",        0xfa900000,     0xfff30000,     FMT_D2, {AM1, MEM2(IMM16, SP)}},
 225 { "mov",        0xfc900000,     0xfc930000,     FMT_D4, {AM1, MEM2(IMM32, SP)}},
 226 { "mov",        0xf3c0,         0xffc0,         FMT_D0, {AM2, MEM2(DI, AN0)}},
 227 { "mov",        0xfa800000,     0xfff30000,     FMT_D2, {AM1, MEM(IMM16)}},
 228 { "mov",        0xfc800000,     0xfff30000,     FMT_D4, {AM1, MEM(IMM32)}},
 229 { "mov",        0xf8f400,       0xfffc00,       FMT_D1, {SP, MEM2(SD8N, AN0)}},
 230 { "mov",        0x2c0000,       0xfc0000,       FMT_S2, {SIMM16, DN0}},
 231 { "mov",        0xfccc0000,     0xfffc0000,     FMT_D4, {IMM32, DN0}},
 232 { "mov",        0x240000,       0xfc0000,       FMT_S2, {IMM16, AN0}},
 233 { "mov",        0xfcdc0000,     0xfffc0000,     FMT_D4, {IMM32, AN0}},
 234
 235 { "movbu",      0xf040,         0xfff0,         FMT_D0, {MEM(AM0), DN1}},
 236 { "movbu",      0xf84000,       0xfff000,       FMT_D1, {MEM2(SD8, AM0), DN1}},
 237 { "movbu",      0xfa400000,     0xfff00000,     FMT_D2, {MEM2(SD16, AM0), DN1}},
 238 { "movbu",      0xfc400000,     0xfff00000,     FMT_D4, {MEM2(IMM32,AM0), DN1}},
 239 { "movbu",      0xf8b800,       0xfffc00,       FMT_D1, {MEM2(IMM8, SP), DN0}},
 240 { "movbu",      0xfab80000,     0xfffc0000,     FMT_D2, {MEM2(IMM16, SP), DN0}},
 241 { "movbu",      0xfcb80000,     0xfffc0000,     FMT_D4, {MEM2(IMM32, SP), DN0}},
 242 { "movbu",      0xf400,         0xffc0,         FMT_D0, {MEM2(DI, AM0), DN2}},
 243 { "movbu",      0x340000,       0xfc0000,       FMT_S2, {MEM(IMM16), DN0}},
 244 { "movbu",      0xfca80000,     0xfffc0000,     FMT_D4, {MEM(IMM32), DN0}},
 245 { "movbu",      0xf050,         0xfff0,         FMT_D0, {DM1, MEM(AN0)}},
 246 { "movbu",      0xf85000,       0xfff000,       FMT_D1, {DM1, MEM2(SD8, AN0)}},
 247 { "movbu",      0xfa500000,     0xfff00000,     FMT_D2, {DM1, MEM2(SD16, AN0)}},
 248 { "movbu",      0xfc500000,     0xfff00000,     FMT_D4, {DM1, MEM2(IMM32,AN0)}},
 249 { "movbu",      0xf89200,       0xfff300,       FMT_D1, {DM1, MEM2(IMM8, SP)}},
 250 { "movbu",      0xfa920000,     0xfff30000,     FMT_D2, {DM1, MEM2(IMM16, SP)}},
 251 { "movbu",      0xfc920000,     0xfff30000,     FMT_D4, {DM1, MEM2(IMM32, SP)}},
 252 { "movbu",      0xf440,         0xffc0,         FMT_D0, {DM2, MEM2(DI, AN0)}},
 253 { "movbu",      0x020000,       0xf30000,       FMT_S2, {DM1, MEM(IMM16)}},
 254 { "movbu",      0xfc820000,     0xfff30000,     FMT_D4, {DM1, MEM(IMM32)}},
 255
 256 { "movhu",      0xf060,         0xfff0,         FMT_D0, {MEM(AM0), DN1}},
 257 { "movhu",      0xf86000,       0xfff000,       FMT_D1, {MEM2(SD8, AM0), DN1}},
 258 { "movhu",      0xfa600000,     0xfff00000,     FMT_D2, {MEM2(SD16, AM0), DN1}},
 259 { "movhu",      0xfc600000,     0xfff00000,     FMT_D4, {MEM2(IMM32,AM0), DN1}},
 260 { "movhu",      0xf8bc00,       0xfffc00,       FMT_D1, {MEM2(IMM8, SP), DN0}},
 261 { "movhu",      0xfabc0000,     0xfffc0000,     FMT_D2, {MEM2(IMM16, SP), DN0}},
 262 { "movhu",      0xfcbc0000,     0xfffc0000,     FMT_D4, {MEM2(IMM32, SP), DN0}},
 263 { "movhu",      0xf480,         0xffc0,         FMT_D0, {MEM2(DI, AM0), DN2}},
 264 { "movhu",      0x380000,       0xfc0000,       FMT_S2, {MEM(IMM16), DN0}},
 265 { "movhu",      0xfcac0000,     0xfffc0000,     FMT_D4, {MEM(IMM32), DN0}},
 266 { "movhu",      0xf070,         0xfff0,         FMT_D0, {DM1, MEM(AN0)}},
 267 { "movhu",      0xf87000,       0xfff000,       FMT_D1, {DM1, MEM2(SD8, AN0)}},
 268 { "movhu",      0xfa700000,     0xfff00000,     FMT_D2, {DM1, MEM2(SD16, AN0)}},
 269 { "movhu",      0xfc700000,     0xfff00000,     FMT_D4, {DM1, MEM2(IMM32,AN0)}},
 270 { "movhu",      0xf89300,       0xfff300,       FMT_D1, {DM1, MEM2(IMM8, SP)}},
 271 { "movhu",      0xfa930000,     0xfff30000,     FMT_D2, {DM1, MEM2(IMM16, SP)}},
 272 { "movhu",      0xfc930000,     0xfff30000,     FMT_D4, {DM1, MEM2(IMM32, SP)}},
 273 { "movhu",      0xf4c0,         0xffc0,         FMT_D0, {DM2, MEM2(DI, AN0)}},
 274 { "movhu",      0x030000,       0xf30000,       FMT_S2, {DM1, MEM(IMM16)}},
 275 { "movhu",      0xfc830000,     0xfff30000,     FMT_D4, {DM1, MEM(IMM32)}},
 276
 277 { "ext",        0xf2d0,         0xfffc,         FMT_D0, {DN0}},
 278 { "extb",       0x10,           0xfc,           FMT_S0, {DN0}},
 279 { "extbu",      0x14,           0xfc,           FMT_S0, {DN0}},
 280 { "exth",       0x18,           0xfc,           FMT_S0, {DN0}},
 281 { "exthu",      0x1c,           0xfc,           FMT_S0, {DN0}},
 282
 283 { "movm",       0xce00,         0xff00,         FMT_S1, {MEM(SP), IMM8}},
 284 { "movm",       0xcf00,         0xff00,         FMT_S1, {IMM8, MEM(SP)}},
 285
 286 { "clr",        0x00,           0xf3,           FMT_S0, {DN1}},
 287
 288 { "add",        0xe0,           0xf0,           FMT_S0, {DM1, DN0}},
 289 { "add",        0xf160,         0xfff0,         FMT_D0, {DM1, AN0}},
 290 { "add",        0xf150,         0xfff0,         FMT_D0, {AM1, DN0}},
 291 { "add",        0xf170,         0xfff0,         FMT_D0, {AM1, AN0}},
 292 { "add",        0x2800,         0xfc00,         FMT_S1, {SIMM8, DN0}},
 293 { "add",        0xfac00000,     0xfffc0000,     FMT_D2, {SIMM16, DN0}},
 294 { "add",        0xfcc00000,     0xfffc0000,     FMT_D4, {IMM32, DN0}},
 295 { "add",        0x2000,         0xfc00,         FMT_S1, {SIMM8, AN0}},
 296 { "add",        0xfad00000,     0xfffc0000,     FMT_D2, {SIMM16, AN0}},
 297 { "add",        0xfcd00000,     0xfffc0000,     FMT_D4, {IMM32, AN0}},
 298 { "add",        0xf8fe00,       0xffff00,       FMT_D1, {SIMM8, SP}},
 299 { "add",        0xfafe0000,     0xfffc0000,     FMT_D2, {SIMM16, SP}},
 300 { "add",        0xfcfe0000,     0xfff0000,      FMT_D4, {IMM32, SP}},
 301 { "addc",       0xf140,         0xfff0,         FMT_D0, {DM1, DN0}},
 302
 303 { "sub",        0xf100,         0xfff0,         FMT_D0, {DM1, DN0}},
 304 { "sub",        0xf120,         0xfff0,         FMT_D0, {DM1, AN0}},
 305 { "sub",        0xf110,         0xfff0,         FMT_D0, {AM1, DN0}},
 306 { "sub",        0xf130,         0xfff0,         FMT_D0, {AM1, AN0}},
 307 { "sub",        0xfcc40000,     0xfffc0000,     FMT_D4, {IMM32, DN0}},
 308 { "sub",        0xfcd40000,     0xfffc0000,     FMT_D4, {IMM32, AN0}},
 309 { "subc",       0xf180,         0xfff0,         FMT_D0, {DM1, DN0}},
 310
 311 { "mul",        0xf240,         0xfff0,         FMT_D0, {DM1, DN0}},
 312 { "mulu",       0xf250,         0xfff0,         FMT_D0, {DM1, DN0}},
 313
 314 { "div",        0xf260,         0xfff0,         FMT_D0, {DM1, DN0}},
 315 { "divu",       0xf270,         0xfff0,         FMT_D0, {DM1, DN0}},
 316
 317 { "inc",        0x40,           0xf3,           FMT_S0, {DN1}},
 318 { "inc",        0x41,           0xf3,           FMT_S0, {AN1}},
 319 { "inc4",       0x50,           0xfc,           FMT_S0, {AN0}},
 320
 321 { "cmp",        0xa000,         0xf000,         FMT_S1, {SIMM8, DN01}},
 322 { "cmp",        0xa0,           0xf0,           FMT_S0, {DM1, DN0}},
 323 { "cmp",        0xf1a0,         0xfff0,         FMT_D0, {DM1, AN0}},
 324 { "cmp",        0xf190,         0xfff0,         FMT_D0, {AM1, DN0}},
 325 { "cmp",        0xb000,         0xf000,         FMT_S1, {IMM8, AN01}},
 326 { "cmp",        0xb0,           0xf0,           FMT_S0, {AM1, AN0}},
 327 { "cmp",        0xfac80000,     0xfffc0000,     FMT_D2, {SIMM16, DN0}},
 328 { "cmp",        0xfcc80000,     0xfffc0000,     FMT_D4, {IMM32, DN0}},
 329 { "cmp",        0xfad80000,     0xfffc0000,     FMT_D2, {IMM16, AN0}},
 330 { "cmp",        0xfcd80000,     0xfffc0000,     FMT_D4, {IMM32, AN0}},
 331
 332 { "and",        0xf200,         0xfff0,         FMT_D0, {DM1, DN0}},
 333 { "and",        0xf8e000,       0xfffc00,       FMT_D1, {IMM8, DN0}},
 334 { "and",        0xfae00000,     0xfffc0000,     FMT_D2, {IMM16, DN0}},
 335 { "and",        0xfce00000,     0xfffc0000,     FMT_D4, {IMM32, DN0}},
 336 { "and",        0xfafc0000,     0xfffc0000,     FMT_D2, {IMM16, PSW}},
 337 { "or",         0xf210,         0xfff0,         FMT_D0, {DM1, DN0}},
 338 { "or",         0xf8e400,       0xfffc00,       FMT_D1, {IMM8, DN0}},
 339 { "or",         0xfae40000,     0xfffc0000,     FMT_D2, {IMM16, DN0}},
 340 { "or",         0xfce40000,     0xfffc0000,     FMT_D4, {IMM32, DN0}},
 341 { "or",         0xfafd0000,     0xfffc0000,     FMT_D2, {IMM16, PSW}},
 342 { "xor",        0xf220,         0xfff0,         FMT_D0, {DM1, DN0}},
 343 { "xor",        0xfae80000,     0xfffc0000,     FMT_D2, {IMM16, DN0}},
 344 { "xor",        0xfce80000,     0xfffc0000,     FMT_D4, {IMM32, DN0}},
 345 { "not",        0xf230,         0xfffc,         FMT_D0, {DN0}},
 346
 347 { "btst",       0xf8ec00,       0xfffc00,       FMT_D1, {IMM8, DN0}},
 348 { "btst",       0xfaec0000,     0xfffc0000,     FMT_D2, {IMM16, DN0}},
 349 { "btst",       0xfcec0000,     0xfffc0000,     FMT_D4, {IMM32, DN0}},
 350 { "btst",       0xfe020000,     0xffff0000,     FMT_D5, {IMM8E,
 351                                                          MEM(IMM32_LOWSHIFT8)}},
 352 { "btst",       0xfaf80000,     0xfffc0000,     FMT_D2,
 353                                         {IMM8, MEM2(SD8N_SHIFT8,AN0)}},
 354 { "bset",       0xf080,         0xfff0,         FMT_D0, {DM1, MEM(AN0)}},
 355 { "bset",       0xfe000000,     0xffff0000,     FMT_D5, {IMM8E,
 356                                                          MEM(IMM32_LOWSHIFT8)}},
 357 { "bset",       0xfaf00000,     0xfffc0000,     FMT_D2,
 358                                         {IMM8, MEM2(SD8N_SHIFT8,AN0)}},
 359 { "bclr",       0xf090,         0xfff0,         FMT_D0, {DM1, MEM(AN0)}},
 360 { "bclr",       0xfe010000,     0xffff0000,     FMT_D5, {IMM8E,
 361                                                          MEM(IMM32_LOWSHIFT8)}},
 362 { "bclr",       0xfaf40000,     0xfffc0000,     FMT_D2, {IMM8,
 363                                                 MEM2(SD8N_SHIFT8,AN0)}},
 364
 365 { "asr",        0xf2b0,         0xfff0,         FMT_D0, {DM1, DN0}},
 366 { "asr",        0xf8c800,       0xfffc00,       FMT_D1, {IMM8, DN0}},
 367 { "lsr",        0xf2a0,         0xfff0,         FMT_D0, {DM1, DN0}},
 368 { "lsr",        0xf8c400,       0xfffc00,       FMT_D1, {IMM8, DN0}},
 369 { "asl",        0xf290,         0xfff0,         FMT_D0, {DM1, DN0}},
 370 { "asl",        0xf8c000,       0xfffc00,       FMT_D1, {IMM8, DN0}},
 371 { "asl2",       0x54,           0xfc,           FMT_S0, {DN0}},
 372 { "ror",        0xf284,         0xfffc,         FMT_D0, {DN0}},
 373 { "rol",        0xf280,         0xfffc,         FMT_D0, {DN0}},
 374
 375 { "beq",        0xc800,         0xff00,         FMT_S1, {SD8N}},
 376 { "bne",        0xc900,         0xff00,         FMT_S1, {SD8N}},
 377 { "bgt",        0xc100,         0xff00,         FMT_S1, {SD8N}},
 378 { "bge",        0xc200,         0xff00,         FMT_S1, {SD8N}},
 379 { "ble",        0xc300,         0xff00,         FMT_S1, {SD8N}},
 380 { "blt",        0xc000,         0xff00,         FMT_S1, {SD8N}},
 381 { "bhi",        0xc500,         0xff00,         FMT_S1, {SD8N}},
 382 { "bcc",        0xc600,         0xff00,         FMT_S1, {SD8N}},
 383 { "bls",        0xc700,         0xff00,         FMT_S1, {SD8N}},
 384 { "bcs",        0xc400,         0xff00,         FMT_S1, {SD8N}},
 385 { "bvc",        0xf8e800,       0xffff00,       FMT_D1, {SD8N}},
 386 { "bvs",        0xf8e900,       0xffff00,       FMT_D1, {SD8N}},
 387 { "bnc",        0xf8ea00,       0xffff00,       FMT_D1, {SD8N}},
 388 { "bns",        0xf8eb00,       0xffff00,       FMT_D1, {SD8N}},
 389 { "bra",        0xca00,         0xff00,         FMT_S1, {SD8N}},
 390
 391 { "leq",        0xd8,           0xff,           FMT_S0, {UNUSED}},
 392 { "lne",        0xd9,           0xff,           FMT_S0, {UNUSED}},
 393 { "lgt",        0xd1,           0xff,           FMT_S0, {UNUSED}},
 394 { "lge",        0xd2,           0xff,           FMT_S0, {UNUSED}},
 395 { "lle",        0xd3,           0xff,           FMT_S0, {UNUSED}},
 396 { "llt",        0xd0,           0xff,           FMT_S0, {UNUSED}},
 397 { "lhi",        0xd5,           0xff,           FMT_S0, {UNUSED}},
 398 { "lcc",        0xd6,           0xff,           FMT_S0, {UNUSED}},
 399 { "lls",        0xd7,           0xff,           FMT_S0, {UNUSED}},
 400 { "lcs",        0xd4,           0xff,           FMT_S0, {UNUSED}},
 401 { "lra",        0xda,           0xff,           FMT_S0, {UNUSED}},
 402 { "lcc",        0xd6,           0xff,           FMT_S0, {UNUSED}},
 403 { "setlb",      0xdb,           0xff,           FMT_S0, {UNUSED}},
 404
 405 { "jmp",        0xf0f4,         0xfffc,         FMT_D0, {AN0}},
 406 { "jmp",        0xcc0000,       0xff0000,       FMT_S2, {IMM16}},
 407 { "jmp",        0xdc000000,     0xff000000,     FMT_S4, {IMM32_HIGH24}},
 408 { "call",       0xcd000000,     0xff000000,     FMT_S4, {D16_SHIFT,IMM8,IMM8E}},
 409 { "call",       0xdd000000,     0xff000000,     FMT_S6,
 410                                         {IMM32_HIGH24_LOWSHIFT16,IMM8E_SHIFT8,IMM8E}},
 411 { "calls",      0xf0f0,         0xfffc,         FMT_D0, {AN0}},
 412 { "calls",      0xfaff0000,     0xffff0000,     FMT_D2, {IMM16}},
 413 { "calls",      0xfcff0000,     0xffff0000,     FMT_D4, {IMM32}},
 414
 415 { "ret",        0xdf0000,       0xff00000,      FMT_S2, {IMM8_SHIFT8, IMM8}},
 416 { "retf",       0xde0000,       0xff00000,      FMT_S2, {IMM8_SHIFT8, IMM8}},
 417 { "rets",       0xf0fc,         0xffff,         FMT_D0, {UNUSED}},
 418 { "rti",        0xf0fd,         0xffff,         FMT_D0, {UNUSED}},
 419 { "trap",       0xf0fe,         0xffff,         FMT_D0, {UNUSED}},
 420 { "rtm",        0xf0ff,         0xffff,         FMT_D0, {UNUSED}},
 421 { "nop",        0xcb,           0xff,           FMT_S0, {UNUSED}},
 422 /* { "udf", 0, 0, {0}},  */
 423
 424 { "putx",       0xf500,         0xfff0,         FMT_D0, {DM0}},
 425 { "getx",       0xf6f0,         0xfff0,         FMT_D0, {DN0}},
 426 { "mulq",       0xf600,         0xfff0,         FMT_D0, {DM1, DN0}},
 427 { "mulq",       0xf90000,       0xfffc00,       FMT_D1, {SIMM8, DN0}},
 428 { "mulq",       0xfb000000,     0xfffc0000,     FMT_D2, {SIMM16, DN0}},
 429 { "mulq",       0xfd000000,     0xfffc0000,     FMT_D4, {IMM32, DN0}},
 430 { "mulqu",      0xf610,         0xfff0,         FMT_D0, {DM1, DN0}},
 431 { "mulqu",      0xf90400,       0xfffc00,       FMT_D1, {SIMM8, DN0}},
 432 { "mulqu",      0xfb040000,     0xfffc0000,     FMT_D2, {SIMM16, DN0}},
 433 { "mulqu",      0xfd040000,     0xfffc0000,     FMT_D4, {IMM32, DN0}},
 434 { "sat16",      0xf640,         0xfff0,         FMT_D0, {DM1, DN0}},
 435 { "sat24",      0xf650,         0xfff0,         FMT_D0, {DM1, DN0}},
 436 { "bsch",       0xf670,         0xfff0,         FMT_D0, {DM1, DN0}},
 437 { 0, 0, 0, 0, {0}},
 438
 439 } ;
 440
 441 const int mn10300_num_opcodes =
 442   sizeof (mn10300_opcodes) / sizeof (mn10300_opcodes[0]);
 443
 444 \f