1 /* NDS32-specific support for 32-bit ELF.
2 Copyright (C) 2012-2019 Free Software Foundation, Inc.
3 Contributed by Andes Technology Corporation.
5 This file is part of BFD, the Binary File Descriptor library.
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3 of the License, or
10 (at your option) any later version.
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this program; if not, write to the Free Software
19 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA
30 /* Constant values for assembler. */
33 /* Error code for assembling an instruction. */
38 NASM_ERR_OUT_OF_RANGE
,
42 /* Results of parse_operand. */
47 /* Flags for open description. */
48 NASM_OPEN_ARCH_V1
= 0x0,
49 NASM_OPEN_ARCH_V2
= 0x1,
50 NASM_OPEN_ARCH_V3
= 0x2,
51 NASM_OPEN_ARCH_V3M
= 0x3,
52 NASM_OPEN_ARCH_MASK
= 0xf,
53 NASM_OPEN_REDUCED_REG
= 0x10,
55 /* Common attributes. */
56 NASM_ATTR_ISA_V1
= 0x01,
57 NASM_ATTR_ISA_V2
= 0x02,
58 NASM_ATTR_ISA_V3
= 0x04,
59 NASM_ATTR_ISA_V3M
= 0x08,
60 NASM_ATTR_ISA_ALL
= 0x0f,
62 /* Attributes for instructions. */
63 NASM_ATTR_MAC
= 0x0000100,
64 NASM_ATTR_DIV
= 0x0000200,
65 NASM_ATTR_FPU
= 0x0000400,
66 NASM_ATTR_FPU_SP_EXT
= 0x0000800,
67 NASM_ATTR_FPU_DP_EXT
= 0x0001000,
68 NASM_ATTR_STR_EXT
= 0x0002000,
69 NASM_ATTR_PERF_EXT
= 0x0004000,
70 NASM_ATTR_PERF2_EXT
= 0x0008000,
71 NASM_ATTR_AUDIO_ISAEXT
= 0x0010000,
72 NASM_ATTR_IFC_EXT
= 0x0020000,
73 NASM_ATTR_EX9_EXT
= 0x0040000,
74 NASM_ATTR_FPU_FMA
= 0x0080000,
75 NASM_ATTR_DXREG
= 0x0100000,
76 NASM_ATTR_BRANCH
= 0x0200000,
77 NASM_ATTR_SATURATION_EXT
= 0x0400000,
78 NASM_ATTR_PCREL
= 0x0800000,
79 NASM_ATTR_GPREL
= 0x1000000,
80 NASM_ATTR_DSP_ISAEXT
= 0x2000000,
81 NASM_ATTR_ZOL
= (1 << 26),
83 /* Attributes for relocations. */
84 NASM_ATTR_HI20
= 0x10000000,
85 NASM_ATTR_LO12
= 0x20000000,
86 NASM_ATTR_LO20
= 0x40000000,
88 /* Attributes for registers. */
89 NASM_ATTR_RDREG
= 0x000100
92 /* We only support one core for now. */
93 #define NDS32_CORE_COUNT 1
94 #define NDS32_MAIN_CORE 0
98 /* This operand is used for input or output. (define or use) */
100 SYN_OUTPUT
= 0x20000,
104 /* Hardware resources:
105 Current set up allows up to 256 resources for each class
107 HW_GPR
= NDS32_MAIN_CORE
<< 8,
113 HW_CP
, /* Co-processor ID. */
114 HW_CPR
, /* Co-processor registers. */
115 HW_ABDIM
, /* [ab][di]m? flag for LSMWA?. */
116 HW_ABM
, /* [ab]m? flag for LSMWZB. */
142 /* for audio-extension. */
155 N32_AEXT_AMAWBS
= 0x0c,
169 /* Macro for instruction attribute. */
170 #define ATTR(attr) NASM_ATTR_ ## attr
172 #define ATTR_PCREL (ATTR (PCREL) | ATTR (BRANCH))
174 #define ATTR_ALL (ATTR (ISA_ALL))
175 #define ATTR_V2UP (ATTR_ALL & ~(ATTR (ISA_V1)))
176 #define ATTR_V3MUP (ATTR (ISA_V3) | ATTR (ISA_V3M))
177 #define ATTR_V3 (ATTR (ISA_V3))
178 #define ATTR_V3MEX_V1 (ATTR_ALL & ~(ATTR (ISA_V3M)))
179 #define ATTR_V3MEX_V2 (ATTR_V2UP & ~(ATTR (ISA_V3M)))
181 /* Lexical element in parsed syntax. */
184 /* Common header for hash entries. */
185 struct nds32_hash_entry
190 typedef struct nds32_keyword
197 typedef struct nds32_opcode
199 /* Opcode for the instruction. */
201 /* Human readable string of this instruction. */
202 const char *instruction
;
203 /* Base value of this instruction. */
205 /* The byte-size of the instruction. */
207 /* Attributes of this instruction. */
209 /* Implicit define/use. */
211 /* Parsed string for assembling. */
213 /* Number of variant. */
215 /* Next form of the same mnemonic. */
216 struct nds32_opcode
*next
;
218 /* TODO: Extra constrains and verification.
219 For example, `mov55 $sp, $sp' is not allowed in v3. */
222 typedef struct nds32_asm_insn
224 /* Assembled instruction bytes. */
226 /* The opcode structure for this instruction. */
227 struct nds32_opcode
*opcode
;
228 /* The field need special fix-up, used for relocation. */
229 const struct nds32_field
*field
;
230 /* Attributes for relocation. */
232 /* Application-dependent data, e.g., expression. */
234 /* Input/output registers. */
238 typedef struct nds32_asm_desc
240 /* The callback provided by assembler user for parse an operand,
241 e.g., parse integer. */
242 int (*parse_operand
) (struct nds32_asm_desc
*,
243 struct nds32_asm_insn
*,
246 /* Result of assembling. */
249 /* The mach for this assembling. */
255 /* The field information for an operand. */
256 typedef struct nds32_field
258 /* Name of the field. */
266 int (*parse
) (struct nds32_asm_desc
*,
267 struct nds32_asm_insn
*,
271 extern void nds32_assemble (nds32_asm_desc_t
*, nds32_asm_insn_t
*, char *);
272 extern void nds32_asm_init (nds32_asm_desc_t
*, int);
274 #define OP6(op6) (N32_OP6_ ## op6 << 25)
276 #define LSMW(sub) (OP6 (LSMW) | N32_LSMW_ ## sub)
277 #define JREG(sub) (OP6 (JREG) | N32_JREG_ ## sub)
278 #define JREG_RET (1 << 5)
279 #define JREG_IFC (1 << 6)
280 #define BR2(sub) (OP6 (BR2) | (N32_BR2_ ## sub << 16))
281 #define SIMD(sub) (OP6 (SIMD) | N32_SIMD_ ## sub)
282 #define ALU1(sub) (OP6 (ALU1) | N32_ALU1_ ## sub)
283 #define ALU2(sub) (OP6 (ALU2) | N32_ALU2_ ## sub)
284 #define ALU2_1(sub) (OP6 (ALU2) | N32_BIT (6) | N32_ALU2_ ## sub)
285 #define ALU2_2(sub) (OP6 (ALU2) | N32_BIT (7) | N32_ALU2_ ## sub)
286 #define ALU2_3(sub) (OP6 (ALU2) | N32_BIT (6) | N32_BIT (7) | N32_ALU2_ ## sub)
287 #define MISC(sub) (OP6 (MISC) | N32_MISC_ ## sub)
288 #define MEM(sub) (OP6 (MEM) | N32_MEM_ ## sub)
289 #define FPU_RA_IMMBI(sub) (OP6 (sub) | N32_BIT (12))
290 #define FS1(sub) (OP6 (COP) | N32_FPU_FS1 | (N32_FPU_FS1_ ## sub << 6))
291 #define FS1_F2OP(sub) (OP6 (COP) | N32_FPU_FS1 | (N32_FPU_FS1_F2OP << 6) \
292 | (N32_FPU_FS1_F2OP_ ## sub << 10))
293 #define FS2(sub) (OP6 (COP) | N32_FPU_FS2 | (N32_FPU_FS2_ ## sub << 6))
294 #define FD1(sub) (OP6 (COP) | N32_FPU_FD1 | (N32_FPU_FD1_ ## sub << 6))
295 #define FD1_F2OP(sub) (OP6 (COP) | N32_FPU_FD1 | (N32_FPU_FD1_F2OP << 6) \
296 | (N32_FPU_FD1_F2OP_ ## sub << 10))
297 #define FD2(sub) (OP6 (COP) | N32_FPU_FD2 | (N32_FPU_FD2_ ## sub << 6))
298 #define MFCP(sub) (OP6 (COP) | N32_FPU_MFCP | (N32_FPU_MFCP_ ## sub << 6))
299 #define MFCP_XR(sub) (OP6 (COP) | N32_FPU_MFCP | (N32_FPU_MFCP_XR << 6) \
300 | (N32_FPU_MFCP_XR_ ## sub << 10))
301 #define MTCP(sub) (OP6 (COP) | N32_FPU_MTCP | (N32_FPU_MTCP_ ## sub << 6))
302 #define MTCP_XR(sub) (OP6 (COP) | N32_FPU_MTCP | (N32_FPU_MTCP_XR << 6) \
303 | (N32_FPU_MTCP_XR_ ## sub << 10))
304 #define FPU_MEM(sub) (OP6 (COP) | N32_FPU_ ## sub)
305 #define FPU_MEMBI(sub) (OP6 (COP) | N32_FPU_ ## sub | 0x1 << 7)
306 #define AUDIO(sub) (OP6 (AEXT) | (N32_AEXT_ ## sub << 20))
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