1 /* Table of opcodes for the OpenRISC 1000 ISA.
2 Copyright 2002 Free Software Foundation, Inc.
3 Contributed by Damjan Lampret (lampret@opencores.org).
5 This file is part of gen_or1k_isa, or1k, GDB and GAS.
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2 of the License, or
10 (at your option) any later version.
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this program; if not, write to the Free Software
19 Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
21 /* We treat all letters the same in encode/decode routines so
22 we need to assign some characteristics to them like signess etc. */
26 #include "safe-ctype.h"
31 #include "opcode/or32.h"
33 static unsigned long insn_extract
PARAMS ((char, char *));
34 static unsigned long * cover_insn
PARAMS ((unsigned long *, int, unsigned int));
35 static int num_ones
PARAMS ((unsigned long));
36 static struct insn_op_struct
* parse_params
PARAMS ((const struct or32_opcode
*, struct insn_op_struct
*));
37 static unsigned long or32_extract
PARAMS ((char, char *, unsigned long));
38 static void or32_print_register
PARAMS ((char, char *, unsigned long));
39 static void or32_print_immediate
PARAMS ((char, char *, unsigned long));
40 static unsigned long extend_imm
PARAMS ((unsigned long, char));
42 const struct or32_letter or32_letters
[] =
44 { 'A', NUM_UNSIGNED
},
45 { 'B', NUM_UNSIGNED
},
46 { 'D', NUM_UNSIGNED
},
48 { 'K', NUM_UNSIGNED
},
49 { 'L', NUM_UNSIGNED
},
51 { '0', NUM_UNSIGNED
},
52 { '\0', 0 } /* Dummy entry. */
56 machine[31:30]: first two bits of opcode
57 00 - neither of source operands is GPR
58 01 - second source operand is GPR (rB)
59 10 - first source operand is GPR (rA)
60 11 - both source operands are GPRs (rA and rB)
61 machine[29:26]: next four bits of opcode
62 machine[25:00]: instruction operands (specific to individual instruction)
64 Recommendation: irrelevant instruction bits should be set with a value of
65 bits in same positions of instruction preceding current instruction in the
66 code (when assembling). */
71 #define EF(func) &(func)
72 #define EFI &l_invalid
73 #else /* HAS_EXECUTION */
76 #endif /* HAS_EXECUTION */
78 const struct or32_opcode or32_opcodes
[] =
80 { "l.j", "N", "00 0x0 NNNNN NNNNN NNNN NNNN NNNN NNNN", EF(l_j
), OR32_IF_DELAY
},
81 { "l.jal", "N", "00 0x1 NNNNN NNNNN NNNN NNNN NNNN NNNN", EF(l_jal
), OR32_IF_DELAY
},
82 { "l.bnf", "N", "00 0x3 NNNNN NNNNN NNNN NNNN NNNN NNNN", EF(l_bnf
), OR32_IF_DELAY
| OR32_R_FLAG
},
83 { "l.bf", "N", "00 0x4 NNNNN NNNNN NNNN NNNN NNNN NNNN", EF(l_bf
), OR32_IF_DELAY
| OR32_R_FLAG
},
84 { "l.nop", "K", "00 0x5 01--- ----- KKKK KKKK KKKK KKKK", EF(l_nop
), 0 },
85 { "l.movhi", "rD,K", "00 0x6 DDDDD ----0 KKKK KKKK KKKK KKKK", EF(l_movhi
), 0 }, /*MM*/
86 { "l.macrc", "rD", "00 0x6 DDDDD ----1 0000 0000 0000 0000", EF(l_macrc
), 0 }, /*MM*/
88 { "l.sys", "K", "00 0x8 00000 00000 KKKK KKKK KKKK KKKK", EF(l_sys
), 0 },
89 { "l.trap", "K", "00 0x8 01000 00000 KKKK KKKK KKKK KKKK", EF(l_trap
), 0 }, /* CZ 21/06/01 */
90 { "l.msync", "", "00 0x8 10000 00000 0000 0000 0000 0000", EFN
, 0 },
91 { "l.psync", "", "00 0x8 10100 00000 0000 0000 0000 0000", EFN
, 0 },
92 { "l.csync", "", "00 0x8 11000 00000 0000 0000 0000 0000", EFN
, 0 },
93 { "l.rfe", "", "00 0x9 ----- ----- ---- ---- ---- ----", EF(l_rfe
), OR32_IF_DELAY
},
95 { "lv.all_eq.b","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x1 0x0", EFI
, 0 },
96 { "lv.all_eq.h","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x1 0x1", EFI
, 0 },
97 { "lv.all_ge.b","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x1 0x2", EFI
, 0 },
98 { "lv.all_ge.h","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x1 0x3", EFI
, 0 },
99 { "lv.all_gt.b","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x1 0x4", EFI
, 0 },
100 { "lv.all_gt.h","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x1 0x5", EFI
, 0 },
101 { "lv.all_le.b","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x1 0x6", EFI
, 0 },
102 { "lv.all_le.h","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x1 0x7", EFI
, 0 },
103 { "lv.all_lt.b","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x1 0x8", EFI
, 0 },
104 { "lv.all_lt.h","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x1 0x9", EFI
, 0 },
105 { "lv.all_ne.b","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x1 0xA", EFI
, 0 },
106 { "lv.all_ne.h","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x1 0xB", EFI
, 0 },
107 { "lv.any_eq.b","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x2 0x0", EFI
, 0 },
108 { "lv.any_eq.h","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x2 0x1", EFI
, 0 },
109 { "lv.any_ge.b","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x2 0x2", EFI
, 0 },
110 { "lv.any_ge.h","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x2 0x3", EFI
, 0 },
111 { "lv.any_gt.b","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x2 0x4", EFI
, 0 },
112 { "lv.any_gt.h","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x2 0x5", EFI
, 0 },
113 { "lv.any_le.b","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x2 0x6", EFI
, 0 },
114 { "lv.any_le.h","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x2 0x7", EFI
, 0 },
115 { "lv.any_lt.b","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x2 0x8", EFI
, 0 },
116 { "lv.any_lt.h","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x2 0x9", EFI
, 0 },
117 { "lv.any_ne.b","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x2 0xA", EFI
, 0 },
118 { "lv.any_ne.h","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x2 0xB", EFI
, 0 },
119 { "lv.add.b", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x3 0x0", EFI
, 0 },
120 { "lv.add.h", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x3 0x1", EFI
, 0 },
121 { "lv.adds.b", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x3 0x2", EFI
, 0 },
122 { "lv.adds.h", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x3 0x3", EFI
, 0 },
123 { "lv.addu.b", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x3 0x4", EFI
, 0 },
124 { "lv.addu.h", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x3 0x5", EFI
, 0 },
125 { "lv.addus.b","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x3 0x6", EFI
, 0 },
126 { "lv.addus.h","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x3 0x7", EFI
, 0 },
127 { "lv.and", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x3 0x8", EFI
, 0 },
128 { "lv.avg.b", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x3 0x9", EFI
, 0 },
129 { "lv.avg.h", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x3 0xA", EFI
, 0 },
130 { "lv.cmp_eq.b","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x4 0x0", EFI
, 0 },
131 { "lv.cmp_eq.h","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x4 0x1", EFI
, 0 },
132 { "lv.cmp_ge.b","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x4 0x2", EFI
, 0 },
133 { "lv.cmp_ge.h","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x4 0x3", EFI
, 0 },
134 { "lv.cmp_gt.b","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x4 0x4", EFI
, 0 },
135 { "lv.cmp_gt.h","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x4 0x5", EFI
, 0 },
136 { "lv.cmp_le.b","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x4 0x6", EFI
, 0 },
137 { "lv.cmp_le.h","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x4 0x7", EFI
, 0 },
138 { "lv.cmp_lt.b","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x4 0x8", EFI
, 0 },
139 { "lv.cmp_lt.h","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x4 0x9", EFI
, 0 },
140 { "lv.cmp_ne.b","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x4 0xA", EFI
, 0 },
141 { "lv.cmp_ne.h","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x4 0xB", EFI
, 0 },
142 { "lv.madds.h","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x5 0x4", EFI
, 0 },
143 { "lv.max.b", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x5 0x5", EFI
, 0 },
144 { "lv.max.h", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x5 0x6", EFI
, 0 },
145 { "lv.merge.b","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x5 0x7", EFI
, 0 },
146 { "lv.merge.h","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x5 0x8", EFI
, 0 },
147 { "lv.min.b", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x5 0x9", EFI
, 0 },
148 { "lv.min.h", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x5 0xA", EFI
, 0 },
149 { "lv.msubs.h","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x5 0xB", EFI
, 0 },
150 { "lv.muls.h", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x5 0xC", EFI
, 0 },
151 { "lv.nand", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x5 0xD", EFI
, 0 },
152 { "lv.nor", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x5 0xE", EFI
, 0 },
153 { "lv.or", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x5 0xF", EFI
, 0 },
154 { "lv.pack.b", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x6 0x0", EFI
, 0 },
155 { "lv.pack.h", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x6 0x1", EFI
, 0 },
156 { "lv.packs.b","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x6 0x2", EFI
, 0 },
157 { "lv.packs.h","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x6 0x3", EFI
, 0 },
158 { "lv.packus.b","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x6 0x4", EFI
, 0 },
159 { "lv.packus.h","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x6 0x5", EFI
, 0 },
160 { "lv.perm.n", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x6 0x6", EFI
, 0 },
161 { "lv.rl.b", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x6 0x7", EFI
, 0 },
162 { "lv.rl.h", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x6 0x8", EFI
, 0 },
163 { "lv.sll.b", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x6 0x9", EFI
, 0 },
164 { "lv.sll.h", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x6 0xA", EFI
, 0 },
165 { "lv.sll", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x6 0xB", EFI
, 0 },
166 { "lv.srl.b", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x6 0xC", EFI
, 0 },
167 { "lv.srl.h", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x6 0xD", EFI
, 0 },
168 { "lv.sra.b", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x6 0xE", EFI
, 0 },
169 { "lv.sra.h", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x6 0xF", EFI
, 0 },
170 { "lv.srl", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x7 0x0", EFI
, 0 },
171 { "lv.sub.b", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x7 0x1", EFI
, 0 },
172 { "lv.sub.h", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x7 0x2", EFI
, 0 },
173 { "lv.subs.b", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x7 0x3", EFI
, 0 },
174 { "lv.subs.h", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x7 0x4", EFI
, 0 },
175 { "lv.subu.b", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x7 0x5", EFI
, 0 },
176 { "lv.subu.h", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x7 0x6", EFI
, 0 },
177 { "lv.subus.b","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x7 0x7", EFI
, 0 },
178 { "lv.subus.h","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x7 0x8", EFI
, 0 },
179 { "lv.unpack.b","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x7 0x9", EFI
, 0 },
180 { "lv.unpack.h","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x7 0xA", EFI
, 0 },
181 { "lv.xor", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x7 0xB", EFI
, 0 },
182 { "lv.cust1", "", "00 0xA ----- ----- ---- ---- 0xC ----", EFI
, 0 },
183 { "lv.cust2", "", "00 0xA ----- ----- ---- ---- 0xD ----", EFI
, 0 },
184 { "lv.cust3", "", "00 0xA ----- ----- ---- ---- 0xE ----", EFI
, 0 },
185 { "lv.cust4", "", "00 0xA ----- ----- ---- ---- 0xF ----", EFI
, 0 },
187 { "lf.add.s", "rD,rA,rB", "00 0xB DDDDD AAAAA BBBB B--- 0x1 0x0", EFI
, 0 },
188 { "lf.sub.s", "rD,rA,rB", "00 0xB DDDDD AAAAA BBBB B--- 0x1 0x1", EFI
, 0 },
189 { "lf.mul.s", "rD,rA,rB", "00 0xB DDDDD AAAAA BBBB B--- 0x1 0x2", EFI
, 0 },
190 { "lf.div.s", "rD,rA,rB", "00 0xB DDDDD AAAAA BBBB B--- 0x1 0x3", EFI
, 0 },
191 { "lf.itof.s", "rD,rA", "00 0xB DDDDD AAAAA BBBB B--- 0x1 0x4", EFI
, 0 },
192 { "lf.ftoi.s", "rD,rA", "00 0xB DDDDD AAAAA BBBB B--- 0x1 0x5", EFI
, 0 },
193 { "lf.rem.s", "rD,rA,rB", "00 0xB DDDDD AAAAA BBBB B--- 0x1 0x6", EFI
, 0 },
194 { "lf.madd.s", "rD,rA,rB", "00 0xB DDDDD AAAAA BBBB B--- 0x1 0x7", EFI
, 0 },
195 { "lf.sfeq.s", "rA,rB", "00 0xB ----- AAAAA BBBB B--- 0x1 0x8", EFI
, 0 },
196 { "lf.sfne.s", "rA,rB", "00 0xB ----- AAAAA BBBB B--- 0x1 0x9", EFI
, 0 },
197 { "lf.sfgt.s", "rA,rB", "00 0xB ----- AAAAA BBBB B--- 0x1 0xA", EFI
, 0 },
198 { "lf.sfge.s", "rA,rB", "00 0xB ----- AAAAA BBBB B--- 0x1 0xB", EFI
, 0 },
199 { "lf.sflt.s", "rA,rB", "00 0xB ----- AAAAA BBBB B--- 0x1 0xC", EFI
, 0 },
200 { "lf.sfle.s", "rA,rB", "00 0xB ----- AAAAA BBBB B--- 0x1 0xD", EFI
, 0 },
201 { "lf.cust1.s", "", "00 0xB ----- ----- ---- ---- 0xE ----", EFI
, 0 },
203 { "lf.add.d", "rD,rA,rB", "00 0xC DDDDD AAAAA BBBB B--- 0x1 0x0", EFI
, 0 },
204 { "lf.sub.d", "rD,rA,rB", "00 0xC DDDDD AAAAA BBBB B--- 0x1 0x1", EFI
, 0 },
205 { "lf.mul.d", "rD,rA,rB", "00 0xC DDDDD AAAAA BBBB B--- 0x1 0x2", EFI
, 0 },
206 { "lf.div.d", "rD,rA,rB", "00 0xC DDDDD AAAAA BBBB B--- 0x1 0x3", EFI
, 0 },
207 { "lf.itof.d", "rD,rA", "00 0xC DDDDD AAAAA BBBB B--- 0x1 0x4", EFI
, 0 },
208 { "lf.ftoi.d", "rD,rA", "00 0xC DDDDD AAAAA BBBB B--- 0x1 0x5", EFI
, 0 },
209 { "lf.rem.d", "rD,rA,rB", "00 0xC DDDDD AAAAA BBBB B--- 0x1 0x6", EFI
, 0 },
210 { "lf.madd.d", "rD,rA,rB", "00 0xC DDDDD AAAAA BBBB B--- 0x1 0x7", EFI
, 0 },
211 { "lf.sfeq.d", "rA,rB", "00 0xC ----- AAAAA BBBB B--- 0x1 0x8", EFI
, 0 },
212 { "lf.sfne.d", "rA,rB", "00 0xC ----- AAAAA BBBB B--- 0x1 0x9", EFI
, 0 },
213 { "lf.sfgt.d", "rA,rB", "00 0xC ----- AAAAA BBBB B--- 0x1 0xA", EFI
, 0 },
214 { "lf.sfge.d", "rA,rB", "00 0xC ----- AAAAA BBBB B--- 0x1 0xB", EFI
, 0 },
215 { "lf.sflt.d", "rA,rB", "00 0xC ----- AAAAA BBBB B--- 0x1 0xC", EFI
, 0 },
216 { "lf.sfle.d", "rA,rB", "00 0xC ----- AAAAA BBBB B--- 0x1 0xD", EFI
, 0 },
217 { "lf.cust1.d", "", "00 0xC ----- ----- ---- ---- 0xE ----", EFI
, 0 },
219 { "lvf.ld", "rD,0(rA)", "00 0xD DDDDD AAAAA ---- ---- 0x0 0x0", EFI
, 0 },
220 { "lvf.lw", "rD,0(rA)", "00 0xD DDDDD AAAAA ---- ---- 0x0 0x1", EFI
, 0 },
221 { "lvf.sd", "0(rA),rB", "00 0xD ----- AAAAA BBBB B--- 0x1 0x0", EFI
, 0 },
222 { "lvf.sw", "0(rA),rB", "00 0xD ----- AAAAA BBBB B--- 0x1 0x1", EFI
, 0 },
224 { "l.jr", "rB", "01 0x1 ----- ----- BBBB B--- ---- ----", EF(l_jr
), OR32_IF_DELAY
},
225 { "l.jalr", "rB", "01 0x2 ----- ----- BBBB B--- ---- ----", EF(l_jalr
), OR32_IF_DELAY
},
226 { "l.maci", "rB,I", "01 0x3 IIIII ----- BBBB BIII IIII IIII", EF(l_mac
), 0 },
227 { "l.cust1", "", "01 0xC ----- ----- ---- ---- ---- ----", EF(l_cust1
), 0 },
228 { "l.cust2", "", "01 0xD ----- ----- ---- ---- ---- ----", EF(l_cust2
), 0 },
229 { "l.cust3", "", "01 0xE ----- ----- ---- ---- ---- ----", EF(l_cust3
), 0 },
230 { "l.cust4", "", "01 0xF ----- ----- ---- ---- ---- ----", EF(l_cust4
), 0 },
232 { "l.ld", "rD,I(rA)", "10 0x0 DDDDD AAAAA IIII IIII IIII IIII", EFI
, 0 },
233 { "l.lwz", "rD,I(rA)", "10 0x1 DDDDD AAAAA IIII IIII IIII IIII", EF(l_lwz
), 0 },
234 { "l.lws", "rD,I(rA)", "10 0x2 DDDDD AAAAA IIII IIII IIII IIII", EFI
, 0 },
235 { "l.lbz", "rD,I(rA)", "10 0x3 DDDDD AAAAA IIII IIII IIII IIII", EF(l_lbz
), 0 },
236 { "l.lbs", "rD,I(rA)", "10 0x4 DDDDD AAAAA IIII IIII IIII IIII", EF(l_lbs
), 0 },
237 { "l.lhz", "rD,I(rA)", "10 0x5 DDDDD AAAAA IIII IIII IIII IIII", EF(l_lhz
), 0 },
238 { "l.lhs", "rD,I(rA)", "10 0x6 DDDDD AAAAA IIII IIII IIII IIII", EF(l_lhs
), 0 },
240 { "l.addi", "rD,rA,I", "10 0x7 DDDDD AAAAA IIII IIII IIII IIII", EF(l_add
), 0 },
241 { "l.addic", "rD,rA,I", "10 0x8 DDDDD AAAAA IIII IIII IIII IIII", EFI
, 0 },
242 { "l.andi", "rD,rA,K", "10 0x9 DDDDD AAAAA KKKK KKKK KKKK KKKK", EF(l_and
), 0 },
243 { "l.ori", "rD,rA,K", "10 0xA DDDDD AAAAA KKKK KKKK KKKK KKKK", EF(l_or
), 0 },
244 { "l.xori", "rD,rA,I", "10 0xB DDDDD AAAAA IIII IIII IIII IIII", EF(l_xor
), 0 },
245 { "l.muli", "rD,rA,I", "10 0xC DDDDD AAAAA IIII IIII IIII IIII", EFI
, 0 },
246 { "l.mfspr", "rD,rA,K", "10 0xD DDDDD AAAAA KKKK KKKK KKKK KKKK", EF(l_mfspr
), 0 },
247 { "l.slli", "rD,rA,L", "10 0xE DDDDD AAAAA ---- ---- 00LL LLLL", EF(l_sll
), 0 },
248 { "l.srli", "rD,rA,L", "10 0xE DDDDD AAAAA ---- ---- 01LL LLLL", EF(l_srl
), 0 },
249 { "l.srai", "rD,rA,L", "10 0xE DDDDD AAAAA ---- ---- 10LL LLLL", EF(l_sra
), 0 },
250 { "l.rori", "rD,rA,L", "10 0xE DDDDD AAAAA ---- ---- 11LL LLLL", EFI
, 0 },
252 { "l.sfeqi", "rA,I", "10 0xF 00000 AAAAA IIII IIII IIII IIII", EF(l_sfeq
), OR32_W_FLAG
},
253 { "l.sfnei", "rA,I", "10 0xF 00001 AAAAA IIII IIII IIII IIII", EF(l_sfne
), OR32_W_FLAG
},
254 { "l.sfgtui", "rA,I", "10 0xF 00010 AAAAA IIII IIII IIII IIII", EF(l_sfgtu
), OR32_W_FLAG
},
255 { "l.sfgeui", "rA,I", "10 0xF 00011 AAAAA IIII IIII IIII IIII", EF(l_sfgeu
), OR32_W_FLAG
},
256 { "l.sfltui", "rA,I", "10 0xF 00100 AAAAA IIII IIII IIII IIII", EF(l_sfltu
), OR32_W_FLAG
},
257 { "l.sfleui", "rA,I", "10 0xF 00101 AAAAA IIII IIII IIII IIII", EF(l_sfleu
), OR32_W_FLAG
},
258 { "l.sfgtsi", "rA,I", "10 0xF 01010 AAAAA IIII IIII IIII IIII", EF(l_sfgts
), OR32_W_FLAG
},
259 { "l.sfgesi", "rA,I", "10 0xF 01011 AAAAA IIII IIII IIII IIII", EF(l_sfges
), OR32_W_FLAG
},
260 { "l.sfltsi", "rA,I", "10 0xF 01100 AAAAA IIII IIII IIII IIII", EF(l_sflts
), OR32_W_FLAG
},
261 { "l.sflesi", "rA,I", "10 0xF 01101 AAAAA IIII IIII IIII IIII", EF(l_sfles
), OR32_W_FLAG
},
263 { "l.mtspr", "rA,rB,K", "11 0x0 KKKKK AAAAA BBBB BKKK KKKK KKKK", EF(l_mtspr
), 0 },
264 { "l.mac", "rA,rB", "11 0x1 ----- AAAAA BBBB B--- ---- 0x1", EF(l_mac
), 0 }, /*MM*/
265 { "l.msb", "rA,rB", "11 0x1 ----- AAAAA BBBB B--- ---- 0x2", EF(l_msb
), 0 }, /*MM*/
267 { "l.sd", "I(rA),rB", "11 0x4 IIIII AAAAA BBBB BIII IIII IIII", EFI
, 0 },
268 { "l.sw", "I(rA),rB", "11 0x5 IIIII AAAAA BBBB BIII IIII IIII", EF(l_sw
), 0 },
269 { "l.sb", "I(rA),rB", "11 0x6 IIIII AAAAA BBBB BIII IIII IIII", EF(l_sb
), 0 },
270 { "l.sh", "I(rA),rB", "11 0x7 IIIII AAAAA BBBB BIII IIII IIII", EF(l_sh
), 0 },
272 { "l.add", "rD,rA,rB", "11 0x8 DDDDD AAAAA BBBB B-00 ---- 0x0", EF(l_add
), 0 },
273 { "l.addc", "rD,rA,rB", "11 0x8 DDDDD AAAAA BBBB B-00 ---- 0x1", EFI
, 0 },
274 { "l.sub", "rD,rA,rB", "11 0x8 DDDDD AAAAA BBBB B-00 ---- 0x2", EF(l_sub
), 0 },
275 { "l.and", "rD,rA,rB", "11 0x8 DDDDD AAAAA BBBB B-00 ---- 0x3", EF(l_and
), 0 },
276 { "l.or", "rD,rA,rB", "11 0x8 DDDDD AAAAA BBBB B-00 ---- 0x4", EF(l_or
), 0 },
277 { "l.xor", "rD,rA,rB", "11 0x8 DDDDD AAAAA BBBB B-00 ---- 0x5", EF(l_xor
), 0 },
278 { "l.mul", "rD,rA,rB", "11 0x8 DDDDD AAAAA BBBB B-11 ---- 0x6", EF(l_mul
), 0 },
280 { "l.sll", "rD,rA,rB", "11 0x8 DDDDD AAAAA BBBB B-00 00-- 0x8", EF(l_sll
), 0 },
281 { "l.srl", "rD,rA,rB", "11 0x8 DDDDD AAAAA BBBB B-00 01-- 0x8", EF(l_srl
), 0 },
282 { "l.sra", "rD,rA,rB", "11 0x8 DDDDD AAAAA BBBB B-00 10-- 0x8", EF(l_sra
), 0 },
283 { "l.ror", "rD,rA,rB", "11 0x8 DDDDD AAAAA BBBB B-00 11-- 0x8", EFI
, 0 },
284 { "l.div", "rD,rA,rB", "11 0x8 DDDDD AAAAA BBBB B-00 ---- 0x9", EF(l_div
), 0 },
285 { "l.divu", "rD,rA,rB", "11 0x8 DDDDD AAAAA BBBB B-00 ---- 0xA", EF(l_divu
), 0 },
286 { "l.mulu", "rD,rA,rB", "11 0x8 DDDDD AAAAA BBBB B-11 ---- 0xB", EFI
, 0 },
287 { "l.exths", "rD,rA,rB", "11 0x8 DDDDD AAAAA BBBB B-00 00-- 0xC", EFI
, 0 },
288 { "l.extbs", "rD,rA,rB", "11 0x8 DDDDD AAAAA BBBB B-00 01-- 0xC", EFI
, 0 },
289 { "l.exthz", "rD,rA,rB", "11 0x8 DDDDD AAAAA BBBB B-00 10-- 0xC", EFI
, 0 },
290 { "l.extbz", "rD,rA,rB", "11 0x8 DDDDD AAAAA BBBB B-00 11-- 0xC", EFI
, 0 },
291 { "l.extws", "rD,rA,rB", "11 0x8 DDDDD AAAAA BBBB B-00 00-- 0xD", EFI
, 0 },
292 { "l.extwz", "rD,rA,rB", "11 0x8 DDDDD AAAAA BBBB B-00 01-- 0xD", EFI
, 0 },
293 { "l.cmov", "rD,rA,rB", "11 0x8 DDDDD AAAAA BBBB B-00 ---- 0xE", EFI
, 0 },
294 { "l.ff1", "rD,rA,rB", "11 0x8 DDDDD AAAAA BBBB B-00 ---- 0xF", EFI
, 0 },
296 { "l.sfeq", "rA,rB", "11 0x9 00000 AAAAA BBBB B--- ---- ----", EF(l_sfeq
), OR32_W_FLAG
},
297 { "l.sfne", "rA,rB", "11 0x9 00001 AAAAA BBBB B--- ---- ----", EF(l_sfne
), OR32_W_FLAG
},
298 { "l.sfgtu", "rA,rB", "11 0x9 00010 AAAAA BBBB B--- ---- ----", EF(l_sfgtu
), OR32_W_FLAG
},
299 { "l.sfgeu", "rA,rB", "11 0x9 00011 AAAAA BBBB B--- ---- ----", EF(l_sfgeu
), OR32_W_FLAG
},
300 { "l.sfltu", "rA,rB", "11 0x9 00100 AAAAA BBBB B--- ---- ----", EF(l_sfltu
), OR32_W_FLAG
},
301 { "l.sfleu", "rA,rB", "11 0x9 00101 AAAAA BBBB B--- ---- ----", EF(l_sfleu
), OR32_W_FLAG
},
302 { "l.sfgts", "rA,rB", "11 0x9 01010 AAAAA BBBB B--- ---- ----", EF(l_sfgts
), OR32_W_FLAG
},
303 { "l.sfges", "rA,rB", "11 0x9 01011 AAAAA BBBB B--- ---- ----", EF(l_sfges
), OR32_W_FLAG
},
304 { "l.sflts", "rA,rB", "11 0x9 01100 AAAAA BBBB B--- ---- ----", EF(l_sflts
), OR32_W_FLAG
},
305 { "l.sfles", "rA,rB", "11 0x9 01101 AAAAA BBBB B--- ---- ----", EF(l_sfles
), OR32_W_FLAG
},
307 { "l.cust5", "", "11 0xC ----- ----- ---- ---- ---- ----", EFI
, 0 },
308 { "l.cust6", "", "11 0xD ----- ----- ---- ---- ---- ----", EFI
, 0 },
309 { "l.cust7", "", "11 0xE ----- ----- ---- ---- ---- ----", EFI
, 0 },
310 { "l.cust8", "", "11 0xF ----- ----- ---- ---- ---- ----", EFI
, 0 },
312 /* This section should not be defined in or1ksim, since it contains duplicates,
313 which would cause machine builder to complain. */
315 { "l.cust5_1", "rD", "11 0xC DDDDD ----- ---- ---- ---- ----", EFI
, 0 },
316 { "l.cust5_2", "rD,rA" , "11 0xC DDDDD AAAAA ---- ---- ---- ----", EFI
, 0 },
317 { "l.cust5_3", "rD,rA,rB", "11 0xC DDDDD AAAAA BBBB B--- ---- ----", EFI
, 0 },
319 { "l.cust6_1", "rD", "11 0xD DDDDD ----- ---- ---- ---- ----", EFI
, 0 },
320 { "l.cust6_2", "rD,rA" , "11 0xD DDDDD AAAAA ---- ---- ---- ----", EFI
, 0 },
321 { "l.cust6_3", "rD,rA,rB", "11 0xD DDDDD AAAAA BBBB B--- ---- ----", EFI
, 0 },
323 { "l.cust7_1", "rD", "11 0xE DDDDD ----- ---- ---- ---- ----", EFI
, 0 },
324 { "l.cust7_2", "rD,rA" , "11 0xE DDDDD AAAAA ---- ---- ---- ----", EFI
, 0 },
325 { "l.cust7_3", "rD,rA,rB", "11 0xE DDDDD AAAAA BBBB B--- ---- ----", EFI
, 0 },
327 { "l.cust8_1", "rD", "11 0xF DDDDD ----- ---- ---- ---- ----", EFI
, 0 },
328 { "l.cust8_2", "rD,rA" , "11 0xF DDDDD AAAAA ---- ---- ---- ----", EFI
, 0 },
329 { "l.cust8_3", "rD,rA,rB", "11 0xF DDDDD AAAAA BBBB B--- ---- ----", EFI
, 0 },
332 /* Dummy entry, not included in num_opcodes. This
333 lets code examine entry i+1 without checking
334 if we've run off the end of the table. */
335 { "", "", "", EFI
, 0 }
342 /* Define dummy, if debug is not defined. */
344 #if !defined HAS_DEBUG
345 static void debug
PARAMS ((int, const char *, ...));
348 debug (int level
, const char *format
, ...)
350 /* Just to get rid of warnings. */
355 const unsigned int or32_num_opcodes
= ((sizeof(or32_opcodes
)) / (sizeof(struct or32_opcode
))) - 1;
357 /* Calculates instruction length in bytes. Always 4 for OR32. */
360 insn_len (insn_index
)
361 int insn_index ATTRIBUTE_UNUSED
;
366 /* Is individual insn's operand signed or unsigned? */
372 const struct or32_letter
*pletter
;
374 for (pletter
= or32_letters
; pletter
->letter
!= '\0'; pletter
++)
375 if (pletter
->letter
== l
)
376 return pletter
->sign
;
378 printf ("letter_signed(%c): Unknown letter.\n", l
);
382 /* Number of letters in the individual lettered operand. */
388 const struct or32_opcode
*pinsn
;
392 for (pinsn
= or32_opcodes
; strlen(pinsn
->name
); pinsn
++)
394 if (strchr (pinsn
->encoding
,l
))
396 for (enc
= pinsn
->encoding
; *enc
!= '\0'; enc
++)
397 if ((*enc
== '0') && (*(enc
+1) == 'x'))
405 printf ("\nABORT: letter_range(%c): Never used letter.\n", l
);
409 /* MM: Returns index of given instruction name. */
412 insn_index (char *insn
)
416 for (i
= 0; i
< or32_num_opcodes
; i
++)
417 if (!strcmp (or32_opcodes
[i
].name
, insn
))
429 if (index
>= 0 && index
< or32_num_opcodes
)
430 return or32_opcodes
[index
].name
;
440 /* Finite automata for instruction decoding building code. */
442 /* Find simbols in encoding. */
444 insn_extract (param_ch
, enc_initial
)
449 unsigned long ret
= 0;
450 unsigned opc_pos
= 32;
452 for (enc
= enc_initial
; *enc
!= '\0'; )
453 if ((*enc
== '0') && (*(enc
+ 1) == 'x'))
455 unsigned long tmp
= strtol (enc
+2, NULL
, 16);
458 if (param_ch
== '0' || param_ch
== '1')
462 ret
|= tmp
<< opc_pos
;
468 if (*enc
== '0' || *enc
== '1' || *enc
== '-' || ISALPHA (*enc
))
471 if (param_ch
== *enc
)
479 #define MAX_AUTOMATA_SIZE (1200)
480 #define MAX_OP_TABLE_SIZE (1200)
481 #define LEAF_FLAG (0x80000000)
485 # define MIN(x,y) ((x) < (y) ? (x) : (y))
488 unsigned long *automata
;
492 /* MM: Struct that hold runtime build information about instructions. */
493 struct temp_insn_struct
496 unsigned long insn_mask
;
500 struct insn_op_struct
*op_data
, **op_start
;
502 /* Recursive utility function used to find best match and to build automata. */
504 static unsigned long *
505 cover_insn (cur
, pass
, mask
)
510 int best_first
= 0, best_len
= 0, i
, last_match
= -1, ninstr
= 0;
511 unsigned long cur_mask
= mask
;
514 for (i
= 0; i
< or32_num_opcodes
; i
++)
515 if (ti
[i
].in_pass
== pass
)
517 cur_mask
&= ti
[i
].insn_mask
;
522 debug (8, "%08X %08X\n", mask
, cur_mask
);
529 /* Leaf holds instruction index. */
530 debug (8, "%i>I%i %s\n",
531 cur
- automata
, last_match
, or32_opcodes
[last_match
].name
);
533 *cur
= LEAF_FLAG
| last_match
;
539 /* Find longest match. */
540 for (i
= 0; i
< 32; i
++)
544 for (len
= best_len
+ 1; len
< MIN (MAX_LEN
, 33 - i
); len
++)
546 unsigned long m
= (1UL << ((unsigned long)len
)) - 1;
548 debug (9, " (%i(%08X & %08X>>%i = %08X, %08X)",
549 len
,m
, cur_mask
, i
, (cur_mask
>> (unsigned)i
),
550 (cur_mask
>> (unsigned)i
) & m
);
552 if ((m
& (cur_mask
>> (unsigned)i
)) == m
)
567 fprintf (stderr
, "%i instructions match mask 0x%08X:\n", ninstr
, mask
);
569 for (i
= 0; i
< or32_num_opcodes
; i
++)
570 if (ti
[i
].in_pass
== pass
)
571 fprintf (stderr
, "%s ", or32_opcodes
[i
].name
);
573 fprintf (stderr
, "\n");
577 debug (8, "%i> #### %i << %i (%i) ####\n",
578 cur
- automata
, best_len
, best_first
, ninstr
);
582 *cur
= (1 << best_len
) - 1;
586 /* Allocate space for pointers. */
587 cur
+= 1 << best_len
;
588 cur_mask
= (1 << (unsigned long)best_len
) - 1;
590 for (i
= 0; i
< (1 << (unsigned long)best_len
); i
++)
596 for (j
= 0; j
< or32_num_opcodes
; j
++)
597 if (ti
[j
].in_pass
== pass
598 && ((ti
[j
].insn
>> best_first
) & cur_mask
) == (unsigned long) i
599 && ((ti
[j
].insn_mask
>> best_first
) & cur_mask
) == cur_mask
)
600 ti
[j
].in_pass
= curpass
;
602 debug (9, "%08X %08X %i\n", mask
, cur_mask
, best_first
);
603 c
= cover_insn (cur
, curpass
, mask
& (~(cur_mask
<< best_first
)));
606 debug (8, "%i> #%X -> %u\n", next
- automata
, i
, cur
- automata
);
607 *next
= cur
- automata
;
612 debug (8, "%i> N/A\n", next
- automata
);
621 /* Returns number of nonzero bits. */
638 /* Utility function, which converts parameters from or32_opcode format to more binary form.
639 Parameters are stored in ti struct. */
641 static struct insn_op_struct
*
642 parse_params (opcode
, cur
)
643 const struct or32_opcode
* opcode
;
644 struct insn_op_struct
* cur
;
646 char *args
= opcode
->args
;
651 /* In case we don't have any parameters, we add dummy read from r0. */
655 cur
->type
= OPTYPE_REG
| OPTYPE_OP
| OPTYPE_LAST
;
657 debug (9, "#%08X %08X\n", cur
->type
, cur
->data
);
662 while (*args
!= '\0')
669 else if (ISALPHA (*args
))
673 arg
= insn_extract (*args
, opcode
->encoding
);
674 debug (9, "%s : %08X ------\n", opcode
->name
, arg
);
675 if (letter_signed (*args
))
678 type
|= ((num_ones (arg
) - 1) << OPTYPE_SBIT_SHR
) & OPTYPE_SBIT
;
681 /* Split argument to sequences of consecutive ones. */
685 unsigned long tmp
= arg
, mask
= 0;
687 while ((tmp
& 1) == 0)
697 cur
->type
= type
| shr
;
699 arg
&= ~(((1 << mask
) - 1) << shr
);
700 debug (6, "|%08X %08X\n", cur
->type
, cur
->data
);
705 else if (*args
== '(')
707 /* Next param is displacement. Later we will treat them as one operand. */
709 cur
->type
= type
| cur
->type
| OPTYPE_DIS
| OPTYPE_OP
;
710 debug (9, ">%08X %08X\n", cur
->type
, cur
->data
);
716 else if (*args
== OPERAND_DELIM
)
719 cur
->type
= type
| cur
->type
| OPTYPE_OP
;
720 debug (9, ">%08X %08X\n", cur
->type
, cur
->data
);
726 else if (*args
== '0')
730 debug (9, ">%08X %08X\n", cur
->type
, cur
->data
);
736 else if (*args
== ')')
740 fprintf (stderr
, "%s : parse error in args.\n", opcode
->name
);
746 cur
->type
= type
| cur
->type
| OPTYPE_OP
| OPTYPE_LAST
;
747 debug (9, "#%08X %08X\n", cur
->type
, cur
->data
);
753 /* Constructs new automata based on or32_opcodes array. */
760 struct insn_op_struct
*cur
;
762 automata
= (unsigned long *) malloc (MAX_AUTOMATA_SIZE
* sizeof (unsigned long));
763 ti
= (struct temp_insn_struct
*) malloc (sizeof (struct temp_insn_struct
) * or32_num_opcodes
);
765 nuncovered
= or32_num_opcodes
;
766 printf ("Building automata... ");
767 /* Build temporary information about instructions. */
768 for (i
= 0; i
< or32_num_opcodes
; i
++)
770 unsigned long ones
, zeros
;
771 char *encoding
= or32_opcodes
[i
].encoding
;
773 ones
= insn_extract('1', encoding
);
774 zeros
= insn_extract('0', encoding
);
776 ti
[i
].insn_mask
= ones
| zeros
;
778 ti
[i
].in_pass
= curpass
= 0;
780 /*debug(9, "%s: %s %08X %08X\n", or32_opcodes[i].name,
781 or32_opcodes[i].encoding, ti[i].insn_mask, ti[i].insn);*/
784 /* Until all are covered search for best criteria to separate them. */
785 end
= cover_insn (automata
, curpass
, 0xFFFFFFFF);
787 if (end
- automata
> MAX_AUTOMATA_SIZE
)
789 fprintf (stderr
, "Automata too large. Increase MAX_AUTOMATA_SIZE.");
793 printf ("done, num uncovered: %i/%i.\n", nuncovered
, or32_num_opcodes
);
794 printf ("Parsing operands data... ");
796 op_data
= (struct insn_op_struct
*) malloc (MAX_OP_TABLE_SIZE
* sizeof (struct insn_op_struct
));
797 op_start
= (struct insn_op_struct
**) malloc (or32_num_opcodes
* sizeof (struct insn_op_struct
*));
800 for (i
= 0; i
< or32_num_opcodes
; i
++)
803 cur
= parse_params (&or32_opcodes
[i
], cur
);
805 if (cur
- op_data
> MAX_OP_TABLE_SIZE
)
807 fprintf (stderr
, "Operands table too small, increase MAX_OP_TABLE_SIZE.\n");
823 /* Decodes instruction and returns instruction index. */
829 unsigned long *a
= automata
;
832 while (!(*a
& LEAF_FLAG
))
834 unsigned int first
= *a
;
836 debug (9, "%i ", a
- automata
);
839 i
= (insn
>> first
) & *a
;
843 /* Invalid instruction found? */
844 debug (9, "XXX\n", i
);
847 a
= automata
+ *(a
+ i
);
852 debug (9, "%i\n", i
);
854 /* Final check - do we have direct match?
855 (based on or32_opcodes this should be the only possibility,
856 but in case of invalid/missing instruction we must perform a check) */
857 if ((ti
[i
].insn_mask
& insn
) == ti
[i
].insn
)
863 static char disassembled_str
[50];
864 char *disassembled
= &disassembled_str
[0];
866 /* Automagically does zero- or sign- extension and also finds correct
867 sign bit position if sign extension is correct extension. Which extension
868 is proper is figured out from letter description. */
878 /* First truncate all bits above valid range for this letter
879 in case it is zero extend. */
880 letter_bits
= letter_range (l
);
881 mask
= (1 << letter_bits
) - 1;
884 /* Do sign extend if this is the right one. */
885 if (letter_signed(l
) && (imm
>> (letter_bits
- 1)))
892 or32_extract (param_ch
, enc_initial
, insn
)
898 unsigned long ret
= 0;
902 for (enc
= enc_initial
; *enc
!= '\0'; enc
++)
903 if (*enc
== param_ch
)
905 if (enc
- 2 >= enc_initial
&& (*(enc
- 2) == '0') && (*(enc
- 1) == 'x'))
912 printf ("or32_extract: %x ", param_pos
);
916 for (enc
= enc_initial
; *enc
!= '\0'; )
917 if ((*enc
== '0') && (*(enc
+ 1) == 'x'))
920 if ((param_ch
== '0') || (param_ch
== '1'))
922 unsigned long tmp
= strtol (enc
, NULL
, 16);
924 printf (" enc=%s, tmp=%x ", enc
, tmp
);
928 ret
|= tmp
<< opc_pos
;
932 else if ((*enc
== '0') || (*enc
== '1'))
935 if (param_ch
== *enc
)
939 else if (*enc
== param_ch
)
944 printf ("\n ret=%x opc_pos=%x, param_pos=%x\n", ret
, opc_pos
, param_pos
);
946 if (ISLOWER (param_ch
))
947 ret
-= ((insn
>> opc_pos
) & 0x1) << param_pos
;
949 ret
+= ((insn
>> opc_pos
) & 0x1) << param_pos
;
952 else if (ISALPHA (*enc
))
957 else if (*enc
== '-')
966 printf ("ret=%x\n", ret
);
971 /* Print register. Used only by print_insn. */
974 or32_print_register (param_ch
, encoding
, insn
)
979 int regnum
= or32_extract(param_ch
, encoding
, insn
);
981 sprintf (disassembled
, "%sr%d", disassembled
, regnum
);
984 /* Print immediate. Used only by print_insn. */
987 or32_print_immediate (param_ch
, encoding
, insn
)
992 int imm
= or32_extract (param_ch
, encoding
, insn
);
994 imm
= extend_imm (imm
, param_ch
);
996 if (letter_signed (param_ch
))
999 sprintf (disassembled
, "%s%d", disassembled
, imm
);
1001 sprintf (disassembled
, "%s0x%x", disassembled
, imm
);
1004 sprintf (disassembled
, "%s%#x", disassembled
, imm
);
1007 /* Disassemble one instruction from insn to disassemble.
1008 Return the size of the instruction. */
1011 disassemble_insn (insn
)
1015 index
= insn_decode (insn
);
1019 struct or32_opcode
const *opcode
= &or32_opcodes
[index
];
1022 sprintf (disassembled
, "%s ", opcode
->name
);
1023 for (s
= opcode
->args
; *s
!= '\0'; ++s
)
1031 or32_print_register (*++s
, opcode
->encoding
, insn
);
1035 if (strchr (opcode
->encoding
, *s
))
1036 or32_print_immediate (*s
, opcode
->encoding
, insn
);
1038 sprintf (disassembled
, "%s%c", disassembled
, *s
);
1044 /* This used to be %8x for binutils. */
1045 sprintf (disassembled
, "%s.word 0x%08lx", disassembled
, insn
);
1048 return insn_len (insn
);