1 /* ppc-dis.c -- Disassemble PowerPC instructions
2 Copyright (C) 1994-2018 Free Software Foundation, Inc.
3 Written by Ian Lance Taylor, Cygnus Support
5 This file is part of the GNU opcodes library.
7 This library is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3, or (at your option)
12 It is distributed in the hope that it will be useful, but WITHOUT
13 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
14 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
15 License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this file; see the file COPYING. If not, write to the
19 Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston,
20 MA 02110-1301, USA. */
24 #include "disassemble.h"
28 #include "opcode/ppc.h"
29 #include "libiberty.h"
31 /* This file provides several disassembler functions, all of which use
32 the disassembler interface defined in dis-asm.h. Several functions
33 are provided because this file handles disassembly for the PowerPC
34 in both big and little endian mode and also for the POWER (RS/6000)
36 static int print_insn_powerpc (bfd_vma
, struct disassemble_info
*, int,
41 /* Stash the result of parsing disassembler_options here. */
45 #define POWERPC_DIALECT(INFO) \
46 (((struct dis_private *) ((INFO)->private_data))->dialect)
49 /* Option string, without -m or -M prefix. */
51 /* CPU option flags. */
53 /* Flags that should stay on, even when combined with another cpu
54 option. This should only be used for generic options like
55 "-many" or "-maltivec" where it is reasonable to add some
56 capability to another cpu selection. The added flags are sticky
57 so that, for example, "-many -me500" and "-me500 -many" result in
58 the same assembler or disassembler behaviour. Do not use
59 "sticky" for specific cpus, as this will prevent that cpu's flags
60 from overriding the defaults set in powerpc_init_dialect or a
65 struct ppc_mopt ppc_opts
[] = {
66 { "403", PPC_OPCODE_PPC
| PPC_OPCODE_403
,
68 { "405", PPC_OPCODE_PPC
| PPC_OPCODE_403
| PPC_OPCODE_405
,
70 { "440", (PPC_OPCODE_PPC
| PPC_OPCODE_BOOKE
| PPC_OPCODE_440
71 | PPC_OPCODE_ISEL
| PPC_OPCODE_RFMCI
),
73 { "464", (PPC_OPCODE_PPC
| PPC_OPCODE_BOOKE
| PPC_OPCODE_440
74 | PPC_OPCODE_ISEL
| PPC_OPCODE_RFMCI
),
76 { "476", (PPC_OPCODE_PPC
| PPC_OPCODE_ISEL
| PPC_OPCODE_476
77 | PPC_OPCODE_POWER4
| PPC_OPCODE_POWER5
),
79 { "601", PPC_OPCODE_PPC
| PPC_OPCODE_601
,
81 { "603", PPC_OPCODE_PPC
,
83 { "604", PPC_OPCODE_PPC
,
85 { "620", PPC_OPCODE_PPC
| PPC_OPCODE_64
,
87 { "7400", PPC_OPCODE_PPC
| PPC_OPCODE_ALTIVEC
,
89 { "7410", PPC_OPCODE_PPC
| PPC_OPCODE_ALTIVEC
,
91 { "7450", PPC_OPCODE_PPC
| PPC_OPCODE_7450
| PPC_OPCODE_ALTIVEC
,
93 { "7455", PPC_OPCODE_PPC
| PPC_OPCODE_ALTIVEC
,
95 { "750cl", PPC_OPCODE_PPC
| PPC_OPCODE_750
| PPC_OPCODE_PPCPS
97 { "gekko", PPC_OPCODE_PPC
| PPC_OPCODE_750
| PPC_OPCODE_PPCPS
99 { "broadway", PPC_OPCODE_PPC
| PPC_OPCODE_750
| PPC_OPCODE_PPCPS
101 { "821", PPC_OPCODE_PPC
| PPC_OPCODE_860
,
103 { "850", PPC_OPCODE_PPC
| PPC_OPCODE_860
,
105 { "860", PPC_OPCODE_PPC
| PPC_OPCODE_860
,
107 { "a2", (PPC_OPCODE_PPC
| PPC_OPCODE_ISEL
| PPC_OPCODE_POWER4
108 | PPC_OPCODE_POWER5
| PPC_OPCODE_CACHELCK
| PPC_OPCODE_64
111 { "altivec", PPC_OPCODE_PPC
,
112 PPC_OPCODE_ALTIVEC
},
113 { "any", PPC_OPCODE_PPC
,
115 { "booke", PPC_OPCODE_PPC
| PPC_OPCODE_BOOKE
,
117 { "booke32", PPC_OPCODE_PPC
| PPC_OPCODE_BOOKE
,
119 { "cell", (PPC_OPCODE_PPC
| PPC_OPCODE_64
| PPC_OPCODE_POWER4
120 | PPC_OPCODE_CELL
| PPC_OPCODE_ALTIVEC
),
122 { "com", PPC_OPCODE_COMMON
,
124 { "e200z4", (PPC_OPCODE_PPC
| PPC_OPCODE_BOOKE
| PPC_OPCODE_SPE
125 | PPC_OPCODE_ISEL
| PPC_OPCODE_EFS
| PPC_OPCODE_BRLOCK
126 | PPC_OPCODE_PMR
| PPC_OPCODE_CACHELCK
| PPC_OPCODE_RFMCI
127 | PPC_OPCODE_E500
| PPC_OPCODE_VLE
| PPC_OPCODE_E200Z4
128 | PPC_OPCODE_EFS2
| PPC_OPCODE_LSP
),
130 { "e300", PPC_OPCODE_PPC
| PPC_OPCODE_E300
,
132 { "e500", (PPC_OPCODE_PPC
| PPC_OPCODE_BOOKE
| PPC_OPCODE_SPE
133 | PPC_OPCODE_ISEL
| PPC_OPCODE_EFS
| PPC_OPCODE_BRLOCK
134 | PPC_OPCODE_PMR
| PPC_OPCODE_CACHELCK
| PPC_OPCODE_RFMCI
137 { "e500mc", (PPC_OPCODE_PPC
| PPC_OPCODE_BOOKE
| PPC_OPCODE_ISEL
138 | PPC_OPCODE_PMR
| PPC_OPCODE_CACHELCK
| PPC_OPCODE_RFMCI
139 | PPC_OPCODE_E500MC
),
141 { "e500mc64", (PPC_OPCODE_PPC
| PPC_OPCODE_BOOKE
| PPC_OPCODE_ISEL
142 | PPC_OPCODE_PMR
| PPC_OPCODE_CACHELCK
| PPC_OPCODE_RFMCI
143 | PPC_OPCODE_E500MC
| PPC_OPCODE_64
| PPC_OPCODE_POWER5
144 | PPC_OPCODE_POWER6
| PPC_OPCODE_POWER7
),
146 { "e5500", (PPC_OPCODE_PPC
| PPC_OPCODE_BOOKE
| PPC_OPCODE_ISEL
147 | PPC_OPCODE_PMR
| PPC_OPCODE_CACHELCK
| PPC_OPCODE_RFMCI
148 | PPC_OPCODE_E500MC
| PPC_OPCODE_64
| PPC_OPCODE_POWER4
149 | PPC_OPCODE_POWER5
| PPC_OPCODE_POWER6
| PPC_OPCODE_POWER7
),
151 { "e6500", (PPC_OPCODE_PPC
| PPC_OPCODE_BOOKE
| PPC_OPCODE_ISEL
152 | PPC_OPCODE_PMR
| PPC_OPCODE_CACHELCK
| PPC_OPCODE_RFMCI
153 | PPC_OPCODE_E500MC
| PPC_OPCODE_64
| PPC_OPCODE_ALTIVEC
154 | PPC_OPCODE_E6500
| PPC_OPCODE_TMR
| PPC_OPCODE_POWER4
155 | PPC_OPCODE_POWER5
| PPC_OPCODE_POWER6
| PPC_OPCODE_POWER7
),
157 { "e500x2", (PPC_OPCODE_PPC
| PPC_OPCODE_BOOKE
| PPC_OPCODE_SPE
158 | PPC_OPCODE_ISEL
| PPC_OPCODE_EFS
| PPC_OPCODE_BRLOCK
159 | PPC_OPCODE_PMR
| PPC_OPCODE_CACHELCK
| PPC_OPCODE_RFMCI
162 { "efs", PPC_OPCODE_PPC
| PPC_OPCODE_EFS
,
164 { "efs2", PPC_OPCODE_PPC
| PPC_OPCODE_EFS
| PPC_OPCODE_EFS2
,
166 { "power4", PPC_OPCODE_PPC
| PPC_OPCODE_64
| PPC_OPCODE_POWER4
,
168 { "power5", (PPC_OPCODE_PPC
| PPC_OPCODE_64
| PPC_OPCODE_POWER4
169 | PPC_OPCODE_POWER5
),
171 { "power6", (PPC_OPCODE_PPC
| PPC_OPCODE_64
| PPC_OPCODE_POWER4
172 | PPC_OPCODE_POWER5
| PPC_OPCODE_POWER6
| PPC_OPCODE_ALTIVEC
),
174 { "power7", (PPC_OPCODE_PPC
| PPC_OPCODE_ISEL
| PPC_OPCODE_64
175 | PPC_OPCODE_POWER4
| PPC_OPCODE_POWER5
| PPC_OPCODE_POWER6
176 | PPC_OPCODE_POWER7
| PPC_OPCODE_ALTIVEC
| PPC_OPCODE_VSX
),
178 { "power8", (PPC_OPCODE_PPC
| PPC_OPCODE_ISEL
| PPC_OPCODE_64
179 | PPC_OPCODE_POWER4
| PPC_OPCODE_POWER5
| PPC_OPCODE_POWER6
180 | PPC_OPCODE_POWER7
| PPC_OPCODE_POWER8
181 | PPC_OPCODE_ALTIVEC
| PPC_OPCODE_VSX
),
183 { "power9", (PPC_OPCODE_PPC
| PPC_OPCODE_ISEL
| PPC_OPCODE_64
184 | PPC_OPCODE_POWER4
| PPC_OPCODE_POWER5
| PPC_OPCODE_POWER6
185 | PPC_OPCODE_POWER7
| PPC_OPCODE_POWER8
| PPC_OPCODE_POWER9
186 | PPC_OPCODE_ALTIVEC
| PPC_OPCODE_VSX
),
188 { "ppc", PPC_OPCODE_PPC
,
190 { "ppc32", PPC_OPCODE_PPC
,
192 { "32", PPC_OPCODE_PPC
,
194 { "ppc64", PPC_OPCODE_PPC
| PPC_OPCODE_64
,
196 { "64", PPC_OPCODE_PPC
| PPC_OPCODE_64
,
198 { "ppc64bridge", PPC_OPCODE_PPC
| PPC_OPCODE_64_BRIDGE
,
200 { "ppcps", PPC_OPCODE_PPC
| PPC_OPCODE_PPCPS
,
202 { "pwr", PPC_OPCODE_POWER
,
204 { "pwr2", PPC_OPCODE_POWER
| PPC_OPCODE_POWER2
,
206 { "pwr4", PPC_OPCODE_PPC
| PPC_OPCODE_64
| PPC_OPCODE_POWER4
,
208 { "pwr5", (PPC_OPCODE_PPC
| PPC_OPCODE_64
| PPC_OPCODE_POWER4
209 | PPC_OPCODE_POWER5
),
211 { "pwr5x", (PPC_OPCODE_PPC
| PPC_OPCODE_64
| PPC_OPCODE_POWER4
212 | PPC_OPCODE_POWER5
),
214 { "pwr6", (PPC_OPCODE_PPC
| PPC_OPCODE_64
| PPC_OPCODE_POWER4
215 | PPC_OPCODE_POWER5
| PPC_OPCODE_POWER6
| PPC_OPCODE_ALTIVEC
),
217 { "pwr7", (PPC_OPCODE_PPC
| PPC_OPCODE_ISEL
| PPC_OPCODE_64
218 | PPC_OPCODE_POWER4
| PPC_OPCODE_POWER5
| PPC_OPCODE_POWER6
219 | PPC_OPCODE_POWER7
| PPC_OPCODE_ALTIVEC
| PPC_OPCODE_VSX
),
221 { "pwr8", (PPC_OPCODE_PPC
| PPC_OPCODE_ISEL
| PPC_OPCODE_64
222 | PPC_OPCODE_POWER4
| PPC_OPCODE_POWER5
| PPC_OPCODE_POWER6
223 | PPC_OPCODE_POWER7
| PPC_OPCODE_POWER8
224 | PPC_OPCODE_ALTIVEC
| PPC_OPCODE_VSX
),
226 { "pwr9", (PPC_OPCODE_PPC
| PPC_OPCODE_ISEL
| PPC_OPCODE_64
227 | PPC_OPCODE_POWER4
| PPC_OPCODE_POWER5
| PPC_OPCODE_POWER6
228 | PPC_OPCODE_POWER7
| PPC_OPCODE_POWER8
| PPC_OPCODE_POWER9
229 | PPC_OPCODE_ALTIVEC
| PPC_OPCODE_VSX
),
231 { "pwrx", PPC_OPCODE_POWER
| PPC_OPCODE_POWER2
,
233 { "raw", PPC_OPCODE_PPC
,
235 { "spe", PPC_OPCODE_PPC
| PPC_OPCODE_EFS
,
237 { "spe2", PPC_OPCODE_PPC
| PPC_OPCODE_EFS
| PPC_OPCODE_EFS2
| PPC_OPCODE_SPE
,
239 { "titan", (PPC_OPCODE_PPC
| PPC_OPCODE_BOOKE
| PPC_OPCODE_PMR
240 | PPC_OPCODE_RFMCI
| PPC_OPCODE_TITAN
),
242 { "vle", (PPC_OPCODE_PPC
| PPC_OPCODE_BOOKE
| PPC_OPCODE_SPE
243 | PPC_OPCODE_ISEL
| PPC_OPCODE_EFS
| PPC_OPCODE_BRLOCK
244 | PPC_OPCODE_PMR
| PPC_OPCODE_CACHELCK
| PPC_OPCODE_RFMCI
245 | PPC_OPCODE_LSP
| PPC_OPCODE_EFS2
| PPC_OPCODE_SPE2
),
247 { "vsx", PPC_OPCODE_PPC
,
251 /* Switch between Booke and VLE dialects for interlinked dumps. */
253 get_powerpc_dialect (struct disassemble_info
*info
)
255 ppc_cpu_t dialect
= 0;
257 dialect
= POWERPC_DIALECT (info
);
259 /* Disassemble according to the section headers flags for VLE-mode. */
260 if (dialect
& PPC_OPCODE_VLE
261 && info
->section
!= NULL
&& info
->section
->owner
!= NULL
262 && bfd_get_flavour (info
->section
->owner
) == bfd_target_elf_flavour
263 && elf_object_id (info
->section
->owner
) == PPC32_ELF_DATA
264 && (elf_section_flags (info
->section
) & SHF_PPC_VLE
) != 0)
267 return dialect
& ~ PPC_OPCODE_VLE
;
270 /* Handle -m and -M options that set cpu type, and .machine arg. */
273 ppc_parse_cpu (ppc_cpu_t ppc_cpu
, ppc_cpu_t
*sticky
, const char *arg
)
277 for (i
= 0; i
< ARRAY_SIZE (ppc_opts
); i
++)
278 if (disassembler_options_cmp (ppc_opts
[i
].opt
, arg
) == 0)
280 if (ppc_opts
[i
].sticky
)
282 *sticky
|= ppc_opts
[i
].sticky
;
283 if ((ppc_cpu
& ~*sticky
) != 0)
286 ppc_cpu
= ppc_opts
[i
].cpu
;
289 if (i
>= ARRAY_SIZE (ppc_opts
))
296 /* Determine which set of machines to disassemble for. */
299 powerpc_init_dialect (struct disassemble_info
*info
)
301 ppc_cpu_t dialect
= 0;
302 ppc_cpu_t sticky
= 0;
303 struct dis_private
*priv
= calloc (sizeof (*priv
), 1);
310 case bfd_mach_ppc_403
:
311 case bfd_mach_ppc_403gc
:
312 dialect
= ppc_parse_cpu (dialect
, &sticky
, "403");
314 case bfd_mach_ppc_405
:
315 dialect
= ppc_parse_cpu (dialect
, &sticky
, "405");
317 case bfd_mach_ppc_601
:
318 dialect
= ppc_parse_cpu (dialect
, &sticky
, "601");
320 case bfd_mach_ppc_750
:
321 dialect
= ppc_parse_cpu (dialect
, &sticky
, "750cl");
323 case bfd_mach_ppc_a35
:
324 case bfd_mach_ppc_rs64ii
:
325 case bfd_mach_ppc_rs64iii
:
326 dialect
= ppc_parse_cpu (dialect
, &sticky
, "pwr2") | PPC_OPCODE_64
;
328 case bfd_mach_ppc_e500
:
329 dialect
= ppc_parse_cpu (dialect
, &sticky
, "e500");
331 case bfd_mach_ppc_e500mc
:
332 dialect
= ppc_parse_cpu (dialect
, &sticky
, "e500mc");
334 case bfd_mach_ppc_e500mc64
:
335 dialect
= ppc_parse_cpu (dialect
, &sticky
, "e500mc64");
337 case bfd_mach_ppc_e5500
:
338 dialect
= ppc_parse_cpu (dialect
, &sticky
, "e5500");
340 case bfd_mach_ppc_e6500
:
341 dialect
= ppc_parse_cpu (dialect
, &sticky
, "e6500");
343 case bfd_mach_ppc_titan
:
344 dialect
= ppc_parse_cpu (dialect
, &sticky
, "titan");
346 case bfd_mach_ppc_vle
:
347 dialect
= ppc_parse_cpu (dialect
, &sticky
, "vle");
350 if (info
->arch
== bfd_arch_powerpc
)
351 dialect
= ppc_parse_cpu (dialect
, &sticky
, "power9") | PPC_OPCODE_ANY
;
353 dialect
= ppc_parse_cpu (dialect
, &sticky
, "pwr");
358 FOR_EACH_DISASSEMBLER_OPTION (opt
, info
->disassembler_options
)
360 ppc_cpu_t new_cpu
= 0;
362 if (disassembler_options_cmp (opt
, "32") == 0)
363 dialect
&= ~(ppc_cpu_t
) PPC_OPCODE_64
;
364 else if (disassembler_options_cmp (opt
, "64") == 0)
365 dialect
|= PPC_OPCODE_64
;
366 else if ((new_cpu
= ppc_parse_cpu (dialect
, &sticky
, opt
)) != 0)
369 /* xgettext: c-format */
370 opcodes_error_handler (_("warning: ignoring unknown -M%s option"), opt
);
373 info
->private_data
= priv
;
374 POWERPC_DIALECT(info
) = dialect
;
377 #define PPC_OPCD_SEGS (1 + PPC_OP (-1))
378 static unsigned short powerpc_opcd_indices
[PPC_OPCD_SEGS
+ 1];
379 #define VLE_OPCD_SEGS (1 + VLE_OP_TO_SEG (VLE_OP (-1, 0xffff)))
380 static unsigned short vle_opcd_indices
[VLE_OPCD_SEGS
+ 1];
381 #define SPE2_OPCD_SEGS (1 + SPE2_XOP_TO_SEG (SPE2_XOP (-1)))
382 static unsigned short spe2_opcd_indices
[SPE2_OPCD_SEGS
+ 1];
384 /* Calculate opcode table indices to speed up disassembly,
388 disassemble_init_powerpc (struct disassemble_info
*info
)
390 if (powerpc_opcd_indices
[PPC_OPCD_SEGS
] == 0)
392 unsigned seg
, idx
, op
;
395 for (seg
= 0, idx
= 0; seg
<= PPC_OPCD_SEGS
; seg
++)
397 powerpc_opcd_indices
[seg
] = idx
;
398 for (; idx
< powerpc_num_opcodes
; idx
++)
399 if (seg
< PPC_OP (powerpc_opcodes
[idx
].opcode
))
404 for (seg
= 0, idx
= 0; seg
<= VLE_OPCD_SEGS
; seg
++)
406 vle_opcd_indices
[seg
] = idx
;
407 for (; idx
< vle_num_opcodes
; idx
++)
409 op
= VLE_OP (vle_opcodes
[idx
].opcode
, vle_opcodes
[idx
].mask
);
410 if (seg
< VLE_OP_TO_SEG (op
))
416 for (seg
= 0, idx
= 0; seg
<= SPE2_OPCD_SEGS
; seg
++)
418 spe2_opcd_indices
[seg
] = idx
;
419 for (; idx
< spe2_num_opcodes
; idx
++)
421 op
= SPE2_XOP (spe2_opcodes
[idx
].opcode
);
422 if (seg
< SPE2_XOP_TO_SEG (op
))
428 powerpc_init_dialect (info
);
431 /* Print a big endian PowerPC instruction. */
434 print_insn_big_powerpc (bfd_vma memaddr
, struct disassemble_info
*info
)
436 return print_insn_powerpc (memaddr
, info
, 1, get_powerpc_dialect (info
));
439 /* Print a little endian PowerPC instruction. */
442 print_insn_little_powerpc (bfd_vma memaddr
, struct disassemble_info
*info
)
444 return print_insn_powerpc (memaddr
, info
, 0, get_powerpc_dialect (info
));
447 /* Extract the operand value from the PowerPC or POWER instruction. */
450 operand_value_powerpc (const struct powerpc_operand
*operand
,
451 uint64_t insn
, ppc_cpu_t dialect
)
455 /* Extract the value from the instruction. */
456 if (operand
->extract
)
457 value
= (*operand
->extract
) (insn
, dialect
, &invalid
);
460 if (operand
->shift
>= 0)
461 value
= (insn
>> operand
->shift
) & operand
->bitm
;
463 value
= (insn
<< -operand
->shift
) & operand
->bitm
;
464 if ((operand
->flags
& PPC_OPERAND_SIGNED
) != 0)
466 /* BITM is always some number of zeros followed by some
467 number of ones, followed by some number of zeros. */
468 uint64_t top
= operand
->bitm
;
469 /* top & -top gives the rightmost 1 bit, so this
470 fills in any trailing zeros. */
471 top
|= (top
& -top
) - 1;
473 value
= (value
^ top
) - top
;
480 /* Determine whether the optional operand(s) should be printed. */
483 skip_optional_operands (const unsigned char *opindex
,
484 uint64_t insn
, ppc_cpu_t dialect
)
486 const struct powerpc_operand
*operand
;
488 for (; *opindex
!= 0; opindex
++)
490 operand
= &powerpc_operands
[*opindex
];
491 if ((operand
->flags
& PPC_OPERAND_NEXT
) != 0
492 || ((operand
->flags
& PPC_OPERAND_OPTIONAL
) != 0
493 && operand_value_powerpc (operand
, insn
, dialect
) !=
494 ppc_optional_operand_value (operand
)))
501 /* Find a match for INSN in the opcode table, given machine DIALECT. */
503 static const struct powerpc_opcode
*
504 lookup_powerpc (uint64_t insn
, ppc_cpu_t dialect
)
506 const struct powerpc_opcode
*opcode
, *opcode_end
, *last
;
509 /* Get the major opcode of the instruction. */
512 /* Find the first match in the opcode table for this major opcode. */
513 opcode_end
= powerpc_opcodes
+ powerpc_opcd_indices
[op
+ 1];
515 for (opcode
= powerpc_opcodes
+ powerpc_opcd_indices
[op
];
519 const unsigned char *opindex
;
520 const struct powerpc_operand
*operand
;
523 if ((insn
& opcode
->mask
) != opcode
->opcode
524 || ((dialect
& PPC_OPCODE_ANY
) == 0
525 && ((opcode
->flags
& dialect
) == 0
526 || (opcode
->deprecated
& dialect
) != 0)))
529 /* Check validity of operands. */
531 for (opindex
= opcode
->operands
; *opindex
!= 0; opindex
++)
533 operand
= powerpc_operands
+ *opindex
;
534 if (operand
->extract
)
535 (*operand
->extract
) (insn
, dialect
, &invalid
);
540 if ((dialect
& PPC_OPCODE_RAW
) == 0)
543 /* The raw machine insn is one that is not a specialization. */
545 || (last
->mask
& ~opcode
->mask
) != 0)
552 /* Find a match for INSN in the VLE opcode table. */
554 static const struct powerpc_opcode
*
555 lookup_vle (uint64_t insn
)
557 const struct powerpc_opcode
*opcode
;
558 const struct powerpc_opcode
*opcode_end
;
562 if (op
>= 0x20 && op
<= 0x37)
564 /* This insn has a 4-bit opcode. */
567 seg
= VLE_OP_TO_SEG (op
);
569 /* Find the first match in the opcode table for this major opcode. */
570 opcode_end
= vle_opcodes
+ vle_opcd_indices
[seg
+ 1];
571 for (opcode
= vle_opcodes
+ vle_opcd_indices
[seg
];
575 uint64_t table_opcd
= opcode
->opcode
;
576 uint64_t table_mask
= opcode
->mask
;
577 bfd_boolean table_op_is_short
= PPC_OP_SE_VLE(table_mask
);
579 const unsigned char *opindex
;
580 const struct powerpc_operand
*operand
;
584 if (table_op_is_short
)
586 if ((insn2
& table_mask
) != table_opcd
)
589 /* Check validity of operands. */
591 for (opindex
= opcode
->operands
; *opindex
!= 0; ++opindex
)
593 operand
= powerpc_operands
+ *opindex
;
594 if (operand
->extract
)
595 (*operand
->extract
) (insn
, (ppc_cpu_t
)0, &invalid
);
606 /* Find a match for INSN in the SPE2 opcode table. */
608 static const struct powerpc_opcode
*
609 lookup_spe2 (uint64_t insn
)
611 const struct powerpc_opcode
*opcode
, *opcode_end
;
612 unsigned op
, xop
, seg
;
617 /* This is not SPE2 insn.
618 * All SPE2 instructions have OP=4 and differs by XOP */
621 xop
= SPE2_XOP (insn
);
622 seg
= SPE2_XOP_TO_SEG (xop
);
624 /* Find the first match in the opcode table for this major opcode. */
625 opcode_end
= spe2_opcodes
+ spe2_opcd_indices
[seg
+ 1];
626 for (opcode
= spe2_opcodes
+ spe2_opcd_indices
[seg
];
630 uint64_t table_opcd
= opcode
->opcode
;
631 uint64_t table_mask
= opcode
->mask
;
633 const unsigned char *opindex
;
634 const struct powerpc_operand
*operand
;
638 if ((insn2
& table_mask
) != table_opcd
)
641 /* Check validity of operands. */
643 for (opindex
= opcode
->operands
; *opindex
!= 0; ++opindex
)
645 operand
= powerpc_operands
+ *opindex
;
646 if (operand
->extract
)
647 (*operand
->extract
) (insn
, (ppc_cpu_t
)0, &invalid
);
658 /* Print a PowerPC or POWER instruction. */
661 print_insn_powerpc (bfd_vma memaddr
,
662 struct disassemble_info
*info
,
669 const struct powerpc_opcode
*opcode
;
670 int insn_length
= 4; /* Assume we have a normal 4-byte instruction. */
672 status
= (*info
->read_memory_func
) (memaddr
, buffer
, 4, info
);
674 /* The final instruction may be a 2-byte VLE insn. */
675 if (status
!= 0 && (dialect
& PPC_OPCODE_VLE
) != 0)
677 /* Clear buffer so unused bytes will not have garbage in them. */
678 buffer
[0] = buffer
[1] = buffer
[2] = buffer
[3] = 0;
679 status
= (*info
->read_memory_func
) (memaddr
, buffer
, 2, info
);
684 (*info
->memory_error_func
) (status
, memaddr
, info
);
689 insn
= bfd_getb32 (buffer
);
691 insn
= bfd_getl32 (buffer
);
693 /* Get the major opcode of the insn. */
695 if ((dialect
& PPC_OPCODE_VLE
) != 0)
697 opcode
= lookup_vle (insn
);
698 if (opcode
!= NULL
&& PPC_OP_SE_VLE (opcode
->mask
))
700 /* The operands will be fetched out of the 16-bit instruction. */
705 if (opcode
== NULL
&& (dialect
& PPC_OPCODE_SPE2
) != 0)
706 opcode
= lookup_spe2 (insn
);
708 opcode
= lookup_powerpc (insn
, dialect
& ~PPC_OPCODE_ANY
);
709 if (opcode
== NULL
&& (dialect
& PPC_OPCODE_ANY
) != 0)
710 opcode
= lookup_powerpc (insn
, dialect
);
714 const unsigned char *opindex
;
715 const struct powerpc_operand
*operand
;
720 if (opcode
->operands
[0] != 0)
721 (*info
->fprintf_func
) (info
->stream
, "%-7s ", opcode
->name
);
723 (*info
->fprintf_func
) (info
->stream
, "%s", opcode
->name
);
725 /* Now extract and print the operands. */
729 for (opindex
= opcode
->operands
; *opindex
!= 0; opindex
++)
733 operand
= powerpc_operands
+ *opindex
;
735 /* If all of the optional operands have the value zero,
736 then don't print any of them. */
737 if ((operand
->flags
& PPC_OPERAND_OPTIONAL
) != 0)
739 if (skip_optional
< 0)
740 skip_optional
= skip_optional_operands (opindex
, insn
,
746 value
= operand_value_powerpc (operand
, insn
, dialect
);
750 (*info
->fprintf_func
) (info
->stream
, ",");
754 /* Print the operand as directed by the flags. */
755 if ((operand
->flags
& PPC_OPERAND_GPR
) != 0
756 || ((operand
->flags
& PPC_OPERAND_GPR_0
) != 0 && value
!= 0))
757 (*info
->fprintf_func
) (info
->stream
, "r%" PPC_INT_FMT
"d", value
);
758 else if ((operand
->flags
& PPC_OPERAND_FPR
) != 0)
759 (*info
->fprintf_func
) (info
->stream
, "f%" PPC_INT_FMT
"d", value
);
760 else if ((operand
->flags
& PPC_OPERAND_VR
) != 0)
761 (*info
->fprintf_func
) (info
->stream
, "v%" PPC_INT_FMT
"d", value
);
762 else if ((operand
->flags
& PPC_OPERAND_VSR
) != 0)
763 (*info
->fprintf_func
) (info
->stream
, "vs%" PPC_INT_FMT
"d", value
);
764 else if ((operand
->flags
& PPC_OPERAND_RELATIVE
) != 0)
765 (*info
->print_address_func
) (memaddr
+ value
, info
);
766 else if ((operand
->flags
& PPC_OPERAND_ABSOLUTE
) != 0)
767 (*info
->print_address_func
) ((bfd_vma
) value
& 0xffffffff, info
);
768 else if ((operand
->flags
& PPC_OPERAND_FSL
) != 0)
769 (*info
->fprintf_func
) (info
->stream
, "fsl%" PPC_INT_FMT
"d", value
);
770 else if ((operand
->flags
& PPC_OPERAND_FCR
) != 0)
771 (*info
->fprintf_func
) (info
->stream
, "fcr%" PPC_INT_FMT
"d", value
);
772 else if ((operand
->flags
& PPC_OPERAND_UDI
) != 0)
773 (*info
->fprintf_func
) (info
->stream
, "%" PPC_INT_FMT
"d", value
);
774 else if ((operand
->flags
& PPC_OPERAND_CR_REG
) != 0
775 && (((dialect
& PPC_OPCODE_PPC
) != 0)
776 || ((dialect
& PPC_OPCODE_VLE
) != 0)))
777 (*info
->fprintf_func
) (info
->stream
, "cr%" PPC_INT_FMT
"d", value
);
778 else if (((operand
->flags
& PPC_OPERAND_CR_BIT
) != 0)
779 && (((dialect
& PPC_OPCODE_PPC
) != 0)
780 || ((dialect
& PPC_OPCODE_VLE
) != 0)))
782 static const char *cbnames
[4] = { "lt", "gt", "eq", "so" };
788 (*info
->fprintf_func
) (info
->stream
, "4*cr%d+", cr
);
790 (*info
->fprintf_func
) (info
->stream
, "%s", cbnames
[cc
]);
793 (*info
->fprintf_func
) (info
->stream
, "%" PPC_INT_FMT
"d", value
);
797 (*info
->fprintf_func
) (info
->stream
, ")");
801 if ((operand
->flags
& PPC_OPERAND_PARENS
) == 0)
805 (*info
->fprintf_func
) (info
->stream
, "(");
810 /* We have found and printed an instruction. */
814 /* We could not find a match. */
815 (*info
->fprintf_func
) (info
->stream
, ".long 0x%" PPC_INT_FMT
"x", insn
);
820 const disasm_options_and_args_t
*
821 disassembler_options_powerpc (void)
823 static disasm_options_and_args_t
*opts_and_args
;
825 if (opts_and_args
== NULL
)
827 size_t i
, num_options
= ARRAY_SIZE (ppc_opts
);
828 disasm_options_t
*opts
;
830 opts_and_args
= XNEW (disasm_options_and_args_t
);
831 opts_and_args
->args
= NULL
;
833 opts
= &opts_and_args
->options
;
834 opts
->name
= XNEWVEC (const char *, num_options
+ 1);
835 opts
->description
= NULL
;
837 for (i
= 0; i
< num_options
; i
++)
838 opts
->name
[i
] = ppc_opts
[i
].opt
;
839 /* The array we return must be NULL terminated. */
840 opts
->name
[i
] = NULL
;
843 return opts_and_args
;
847 print_ppc_disassembler_options (FILE *stream
)
851 fprintf (stream
, _("\n\
852 The following PPC specific disassembler options are supported for use with\n\
855 for (col
= 0, i
= 0; i
< ARRAY_SIZE (ppc_opts
); i
++)
857 col
+= fprintf (stream
, " %s,", ppc_opts
[i
].opt
);
860 fprintf (stream
, "\n");
864 fprintf (stream
, "\n");