opcodes/ppc-dis.c

   1 /* ppc-dis.c -- Disassemble PowerPC instructions
   2    Copyright (C) 1994-2017 Free Software Foundation, Inc.
   3    Written by Ian Lance Taylor, Cygnus Support
   4
   5    This file is part of the GNU opcodes library.
   6
   7    This library is free software; you can redistribute it and/or modify
   8    it under the terms of the GNU General Public License as published by
   9    the Free Software Foundation; either version 3, or (at your option)
  10    any later version.
  11
  12    It is distributed in the hope that it will be useful, but WITHOUT
  13    ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  14    or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
  15    License for more details.
  16
  17    You should have received a copy of the GNU General Public License
  18    along with this file; see the file COPYING.  If not, write to the
  19    Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston,
  20    MA 02110-1301, USA.  */
  21
  22 #include "sysdep.h"
  23 #include <stdio.h>
  24 #include "disassemble.h"
  25 #include "elf-bfd.h"
  26 #include "elf/ppc.h"
  27 #include "opintl.h"
  28 #include "opcode/ppc.h"
  29 #include "libiberty.h"
  30
  31 /* This file provides several disassembler functions, all of which use
  32    the disassembler interface defined in dis-asm.h.  Several functions
  33    are provided because this file handles disassembly for the PowerPC
  34    in both big and little endian mode and also for the POWER (RS/6000)
  35    chip.  */
  36 static int print_insn_powerpc (bfd_vma, struct disassemble_info *, int,
  37                                ppc_cpu_t);
  38
  39 struct dis_private
  40 {
  41   /* Stash the result of parsing disassembler_options here.  */
  42   ppc_cpu_t dialect;
  43 } private;
  44
  45 #define POWERPC_DIALECT(INFO) \
  46   (((struct dis_private *) ((INFO)->private_data))->dialect)
  47
  48 struct ppc_mopt {
  49   /* Option string, without -m or -M prefix.  */
  50   const char *opt;
  51   /* CPU option flags.  */
  52   ppc_cpu_t cpu;
  53   /* Flags that should stay on, even when combined with another cpu
  54      option.  This should only be used for generic options like
  55      "-many" or "-maltivec" where it is reasonable to add some
  56      capability to another cpu selection.  The added flags are sticky
  57      so that, for example, "-many -me500" and "-me500 -many" result in
  58      the same assembler or disassembler behaviour.  Do not use
  59      "sticky" for specific cpus, as this will prevent that cpu's flags
  60      from overriding the defaults set in powerpc_init_dialect or a
  61      prior -m option.  */
  62   ppc_cpu_t sticky;
  63 };
  64
  65 struct ppc_mopt ppc_opts[] = {
  66   { "403",     PPC_OPCODE_PPC | PPC_OPCODE_403,
  67     0 },
  68   { "405",     PPC_OPCODE_PPC | PPC_OPCODE_403 | PPC_OPCODE_405,
  69     0 },
  70   { "440",     (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE | PPC_OPCODE_440
  71                 | PPC_OPCODE_ISEL | PPC_OPCODE_RFMCI),
  72     0 },
  73   { "464",     (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE | PPC_OPCODE_440
  74                 | PPC_OPCODE_ISEL | PPC_OPCODE_RFMCI),
  75     0 },
  76   { "476",     (PPC_OPCODE_PPC | PPC_OPCODE_ISEL | PPC_OPCODE_476
  77                 | PPC_OPCODE_POWER4 | PPC_OPCODE_POWER5),
  78     0 },
  79   { "601",     PPC_OPCODE_PPC | PPC_OPCODE_601,
  80     0 },
  81   { "603",     PPC_OPCODE_PPC,
  82     0 },
  83   { "604",     PPC_OPCODE_PPC,
  84     0 },
  85   { "620",     PPC_OPCODE_PPC | PPC_OPCODE_64,
  86     0 },
  87   { "7400",    PPC_OPCODE_PPC | PPC_OPCODE_ALTIVEC,
  88     0 },
  89   { "7410",    PPC_OPCODE_PPC | PPC_OPCODE_ALTIVEC,
  90     0 },
  91   { "7450",    PPC_OPCODE_PPC | PPC_OPCODE_7450 | PPC_OPCODE_ALTIVEC,
  92     0 },
  93   { "7455",    PPC_OPCODE_PPC | PPC_OPCODE_ALTIVEC,
  94     0 },
  95   { "750cl",   PPC_OPCODE_PPC | PPC_OPCODE_750 | PPC_OPCODE_PPCPS
  96     , 0 },
  97   { "821",     PPC_OPCODE_PPC | PPC_OPCODE_860,
  98     0 },
  99   { "850",     PPC_OPCODE_PPC | PPC_OPCODE_860,
 100     0 },
 101   { "860",     PPC_OPCODE_PPC | PPC_OPCODE_860,
 102     0 },
 103   { "a2",      (PPC_OPCODE_PPC | PPC_OPCODE_ISEL | PPC_OPCODE_POWER4
 104                 | PPC_OPCODE_POWER5 | PPC_OPCODE_CACHELCK | PPC_OPCODE_64
 105                 | PPC_OPCODE_A2),
 106     0 },
 107   { "altivec", PPC_OPCODE_PPC,
 108     PPC_OPCODE_ALTIVEC },
 109   { "any",     PPC_OPCODE_PPC,
 110     PPC_OPCODE_ANY },
 111   { "booke",   PPC_OPCODE_PPC | PPC_OPCODE_BOOKE,
 112     0 },
 113   { "booke32", PPC_OPCODE_PPC | PPC_OPCODE_BOOKE,
 114     0 },
 115   { "cell",    (PPC_OPCODE_PPC | PPC_OPCODE_64 | PPC_OPCODE_POWER4
 116                 | PPC_OPCODE_CELL | PPC_OPCODE_ALTIVEC),
 117     0 },
 118   { "com",     PPC_OPCODE_COMMON,
 119     0 },
 120   { "e200z4",  (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE| PPC_OPCODE_SPE
 121                 | PPC_OPCODE_ISEL | PPC_OPCODE_EFS | PPC_OPCODE_BRLOCK
 122                 | PPC_OPCODE_PMR | PPC_OPCODE_CACHELCK | PPC_OPCODE_RFMCI
 123                 | PPC_OPCODE_E500 | PPC_OPCODE_VLE | PPC_OPCODE_E200Z4
 124                 | PPC_OPCODE_EFS2 | PPC_OPCODE_LSP),
 125     0 },
 126   { "e300",    PPC_OPCODE_PPC | PPC_OPCODE_E300,
 127     0 },
 128   { "e500",    (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE | PPC_OPCODE_SPE
 129                 | PPC_OPCODE_ISEL | PPC_OPCODE_EFS | PPC_OPCODE_BRLOCK
 130                 | PPC_OPCODE_PMR | PPC_OPCODE_CACHELCK | PPC_OPCODE_RFMCI
 131                 | PPC_OPCODE_E500),
 132     0 },
 133   { "e500mc",  (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE | PPC_OPCODE_ISEL
 134                 | PPC_OPCODE_PMR | PPC_OPCODE_CACHELCK | PPC_OPCODE_RFMCI
 135                 | PPC_OPCODE_E500MC),
 136     0 },
 137   { "e500mc64",  (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE | PPC_OPCODE_ISEL
 138                 | PPC_OPCODE_PMR | PPC_OPCODE_CACHELCK | PPC_OPCODE_RFMCI
 139                 | PPC_OPCODE_E500MC | PPC_OPCODE_64 | PPC_OPCODE_POWER5
 140                 | PPC_OPCODE_POWER6 | PPC_OPCODE_POWER7),
 141     0 },
 142   { "e5500",    (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE | PPC_OPCODE_ISEL
 143                 | PPC_OPCODE_PMR | PPC_OPCODE_CACHELCK | PPC_OPCODE_RFMCI
 144                 | PPC_OPCODE_E500MC | PPC_OPCODE_64 | PPC_OPCODE_POWER4
 145                 | PPC_OPCODE_POWER5 | PPC_OPCODE_POWER6 | PPC_OPCODE_POWER7),
 146     0 },
 147   { "e6500",   (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE | PPC_OPCODE_ISEL
 148                 | PPC_OPCODE_PMR | PPC_OPCODE_CACHELCK | PPC_OPCODE_RFMCI
 149                 | PPC_OPCODE_E500MC | PPC_OPCODE_64 | PPC_OPCODE_ALTIVEC
 150                 | PPC_OPCODE_E6500 | PPC_OPCODE_TMR | PPC_OPCODE_POWER4
 151                 | PPC_OPCODE_POWER5 | PPC_OPCODE_POWER6 | PPC_OPCODE_POWER7),
 152     0 },
 153   { "e500x2",  (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE | PPC_OPCODE_SPE
 154                 | PPC_OPCODE_ISEL | PPC_OPCODE_EFS | PPC_OPCODE_BRLOCK
 155                 | PPC_OPCODE_PMR | PPC_OPCODE_CACHELCK | PPC_OPCODE_RFMCI
 156                 | PPC_OPCODE_E500),
 157     0 },
 158   { "efs",     PPC_OPCODE_PPC | PPC_OPCODE_EFS,
 159     0 },
 160   { "efs2",    PPC_OPCODE_PPC | PPC_OPCODE_EFS | PPC_OPCODE_EFS2,
 161     0 },
 162   { "power4",  PPC_OPCODE_PPC | PPC_OPCODE_64 | PPC_OPCODE_POWER4,
 163     0 },
 164   { "power5",  (PPC_OPCODE_PPC | PPC_OPCODE_64 | PPC_OPCODE_POWER4
 165                 | PPC_OPCODE_POWER5),
 166     0 },
 167   { "power6",  (PPC_OPCODE_PPC | PPC_OPCODE_64 | PPC_OPCODE_POWER4
 168                 | PPC_OPCODE_POWER5 | PPC_OPCODE_POWER6 | PPC_OPCODE_ALTIVEC),
 169     0 },
 170   { "power7",  (PPC_OPCODE_PPC | PPC_OPCODE_ISEL | PPC_OPCODE_64
 171                 | PPC_OPCODE_POWER4 | PPC_OPCODE_POWER5 | PPC_OPCODE_POWER6
 172                 | PPC_OPCODE_POWER7 | PPC_OPCODE_ALTIVEC | PPC_OPCODE_VSX),
 173     0 },
 174   { "power8",  (PPC_OPCODE_PPC | PPC_OPCODE_ISEL | PPC_OPCODE_64
 175                 | PPC_OPCODE_POWER4 | PPC_OPCODE_POWER5 | PPC_OPCODE_POWER6
 176                 | PPC_OPCODE_POWER7 | PPC_OPCODE_POWER8
 177                 | PPC_OPCODE_ALTIVEC | PPC_OPCODE_VSX),
 178     0 },
 179   { "power9",  (PPC_OPCODE_PPC | PPC_OPCODE_ISEL | PPC_OPCODE_64
 180                 | PPC_OPCODE_POWER4 | PPC_OPCODE_POWER5 | PPC_OPCODE_POWER6
 181                 | PPC_OPCODE_POWER7 | PPC_OPCODE_POWER8 | PPC_OPCODE_POWER9
 182                 | PPC_OPCODE_ALTIVEC | PPC_OPCODE_VSX),
 183     0 },
 184   { "ppc",     PPC_OPCODE_PPC,
 185     0 },
 186   { "ppc32",   PPC_OPCODE_PPC,
 187     0 },
 188   { "32",      PPC_OPCODE_PPC,
 189     0 },
 190   { "ppc64",   PPC_OPCODE_PPC | PPC_OPCODE_64,
 191     0 },
 192   { "64",      PPC_OPCODE_PPC | PPC_OPCODE_64,
 193     0 },
 194   { "ppc64bridge", PPC_OPCODE_PPC | PPC_OPCODE_64_BRIDGE,
 195     0 },
 196   { "ppcps",   PPC_OPCODE_PPC | PPC_OPCODE_PPCPS,
 197     0 },
 198   { "pwr",     PPC_OPCODE_POWER,
 199     0 },
 200   { "pwr2",    PPC_OPCODE_POWER | PPC_OPCODE_POWER2,
 201     0 },
 202   { "pwr4",    PPC_OPCODE_PPC | PPC_OPCODE_64 | PPC_OPCODE_POWER4,
 203     0 },
 204   { "pwr5",    (PPC_OPCODE_PPC | PPC_OPCODE_64 | PPC_OPCODE_POWER4
 205                 | PPC_OPCODE_POWER5),
 206     0 },
 207   { "pwr5x",   (PPC_OPCODE_PPC | PPC_OPCODE_64 | PPC_OPCODE_POWER4
 208                 | PPC_OPCODE_POWER5),
 209     0 },
 210   { "pwr6",    (PPC_OPCODE_PPC | PPC_OPCODE_64 | PPC_OPCODE_POWER4
 211                 | PPC_OPCODE_POWER5 | PPC_OPCODE_POWER6 | PPC_OPCODE_ALTIVEC),
 212     0 },
 213   { "pwr7",    (PPC_OPCODE_PPC | PPC_OPCODE_ISEL | PPC_OPCODE_64
 214                 | PPC_OPCODE_POWER4 | PPC_OPCODE_POWER5 | PPC_OPCODE_POWER6
 215                 | PPC_OPCODE_POWER7 | PPC_OPCODE_ALTIVEC | PPC_OPCODE_VSX),
 216     0 },
 217   { "pwr8",    (PPC_OPCODE_PPC | PPC_OPCODE_ISEL | PPC_OPCODE_64
 218                 | PPC_OPCODE_POWER4 | PPC_OPCODE_POWER5 | PPC_OPCODE_POWER6
 219                 | PPC_OPCODE_POWER7 | PPC_OPCODE_POWER8
 220                 | PPC_OPCODE_ALTIVEC | PPC_OPCODE_VSX),
 221     0 },
 222   { "pwr9",    (PPC_OPCODE_PPC | PPC_OPCODE_ISEL | PPC_OPCODE_64
 223                 | PPC_OPCODE_POWER4 | PPC_OPCODE_POWER5 | PPC_OPCODE_POWER6
 224                 | PPC_OPCODE_POWER7 | PPC_OPCODE_POWER8 | PPC_OPCODE_POWER9
 225                 | PPC_OPCODE_ALTIVEC | PPC_OPCODE_VSX),
 226     0 },
 227   { "pwrx",    PPC_OPCODE_POWER | PPC_OPCODE_POWER2,
 228     0 },
 229   { "raw",     PPC_OPCODE_PPC,
 230     PPC_OPCODE_RAW },
 231   { "spe",     PPC_OPCODE_PPC | PPC_OPCODE_EFS,
 232     PPC_OPCODE_SPE },
 233   { "spe2",     PPC_OPCODE_PPC | PPC_OPCODE_EFS | PPC_OPCODE_EFS2 | PPC_OPCODE_SPE,
 234     PPC_OPCODE_SPE2 },
 235   { "titan",   (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE | PPC_OPCODE_PMR
 236                 | PPC_OPCODE_RFMCI | PPC_OPCODE_TITAN),
 237     0 },
 238   { "vle",     (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE| PPC_OPCODE_SPE
 239                 | PPC_OPCODE_ISEL | PPC_OPCODE_EFS | PPC_OPCODE_BRLOCK
 240                 | PPC_OPCODE_PMR | PPC_OPCODE_CACHELCK | PPC_OPCODE_RFMCI
 241                 | PPC_OPCODE_LSP | PPC_OPCODE_EFS2 | PPC_OPCODE_SPE2),
 242     PPC_OPCODE_VLE },
 243   { "vsx",     PPC_OPCODE_PPC,
 244     PPC_OPCODE_VSX },
 245 };
 246
 247 /* Switch between Booke and VLE dialects for interlinked dumps.  */
 248 static ppc_cpu_t
 249 get_powerpc_dialect (struct disassemble_info *info)
 250 {
 251   ppc_cpu_t dialect = 0;
 252
 253   dialect = POWERPC_DIALECT (info);
 254
 255   /* Disassemble according to the section headers flags for VLE-mode.  */
 256   if (dialect & PPC_OPCODE_VLE
 257       && info->section != NULL && info->section->owner != NULL
 258       && bfd_get_flavour (info->section->owner) == bfd_target_elf_flavour
 259       && elf_object_id (info->section->owner) == PPC32_ELF_DATA
 260       && (elf_section_flags (info->section) & SHF_PPC_VLE) != 0)
 261     return dialect;
 262   else
 263     return dialect & ~ PPC_OPCODE_VLE;
 264 }
 265
 266 /* Handle -m and -M options that set cpu type, and .machine arg.  */
 267
 268 ppc_cpu_t
 269 ppc_parse_cpu (ppc_cpu_t ppc_cpu, ppc_cpu_t *sticky, const char *arg)
 270 {
 271   unsigned int i;
 272
 273   for (i = 0; i < ARRAY_SIZE (ppc_opts); i++)
 274     if (disassembler_options_cmp (ppc_opts[i].opt, arg) == 0)
 275       {
 276         if (ppc_opts[i].sticky)
 277           {
 278             *sticky |= ppc_opts[i].sticky;
 279             if ((ppc_cpu & ~*sticky) != 0)
 280               break;
 281           }
 282         ppc_cpu = ppc_opts[i].cpu;
 283         break;
 284       }
 285   if (i >= ARRAY_SIZE (ppc_opts))
 286     return 0;
 287
 288   ppc_cpu |= *sticky;
 289   return ppc_cpu;
 290 }
 291
 292 /* Determine which set of machines to disassemble for.  */
 293
 294 static void
 295 powerpc_init_dialect (struct disassemble_info *info)
 296 {
 297   ppc_cpu_t dialect = 0;
 298   ppc_cpu_t sticky = 0;
 299   struct dis_private *priv = calloc (sizeof (*priv), 1);
 300
 301   if (priv == NULL)
 302     priv = &private;
 303
 304   switch (info->mach)
 305     {
 306     case bfd_mach_ppc_403:
 307     case bfd_mach_ppc_403gc:
 308       dialect = ppc_parse_cpu (dialect, &sticky, "403");
 309       break;
 310     case bfd_mach_ppc_405:
 311       dialect = ppc_parse_cpu (dialect, &sticky, "405");
 312       break;
 313     case bfd_mach_ppc_601:
 314       dialect = ppc_parse_cpu (dialect, &sticky, "601");
 315       break;
 316     case bfd_mach_ppc_a35:
 317     case bfd_mach_ppc_rs64ii:
 318     case bfd_mach_ppc_rs64iii:
 319       dialect = ppc_parse_cpu (dialect, &sticky, "pwr2") | PPC_OPCODE_64;
 320       break;
 321     case bfd_mach_ppc_e500:
 322       dialect = ppc_parse_cpu (dialect, &sticky, "e500");
 323       break;
 324     case bfd_mach_ppc_e500mc:
 325       dialect = ppc_parse_cpu (dialect, &sticky, "e500mc");
 326       break;
 327     case bfd_mach_ppc_e500mc64:
 328       dialect = ppc_parse_cpu (dialect, &sticky, "e500mc64");
 329       break;
 330     case bfd_mach_ppc_e5500:
 331       dialect = ppc_parse_cpu (dialect, &sticky, "e5500");
 332       break;
 333     case bfd_mach_ppc_e6500:
 334       dialect = ppc_parse_cpu (dialect, &sticky, "e6500");
 335       break;
 336     case bfd_mach_ppc_titan:
 337       dialect = ppc_parse_cpu (dialect, &sticky, "titan");
 338       break;
 339     case bfd_mach_ppc_vle:
 340       dialect = ppc_parse_cpu (dialect, &sticky, "vle");
 341       break;
 342     default:
 343       dialect = ppc_parse_cpu (dialect, &sticky, "power9") | PPC_OPCODE_ANY;
 344       break;
 345     }
 346
 347   const char *opt;
 348   FOR_EACH_DISASSEMBLER_OPTION (opt, info->disassembler_options)
 349     {
 350       ppc_cpu_t new_cpu = 0;
 351
 352       if (disassembler_options_cmp (opt, "32") == 0)
 353         dialect &= ~(ppc_cpu_t) PPC_OPCODE_64;
 354       else if (disassembler_options_cmp (opt, "64") == 0)
 355         dialect |= PPC_OPCODE_64;
 356       else if ((new_cpu = ppc_parse_cpu (dialect, &sticky, opt)) != 0)
 357         dialect = new_cpu;
 358       else
 359         fprintf (stderr, _("warning: ignoring unknown -M%s option\n"), opt);
 360     }
 361
 362   info->private_data = priv;
 363   POWERPC_DIALECT(info) = dialect;
 364 }
 365
 366 #define PPC_OPCD_SEGS 64
 367 static unsigned short powerpc_opcd_indices[PPC_OPCD_SEGS+1];
 368 #define VLE_OPCD_SEGS 32
 369 static unsigned short vle_opcd_indices[VLE_OPCD_SEGS+1];
 370 #define SPE2_OPCD_SEGS 13
 371 static unsigned short spe2_opcd_indices[SPE2_OPCD_SEGS+1];
 372
 373 /* Calculate opcode table indices to speed up disassembly,
 374    and init dialect.  */
 375
 376 void
 377 disassemble_init_powerpc (struct disassemble_info *info)
 378 {
 379   int i;
 380   unsigned short last;
 381
 382   if (powerpc_opcd_indices[PPC_OPCD_SEGS] == 0)
 383     {
 384
 385       i = powerpc_num_opcodes;
 386       while (--i >= 0)
 387         {
 388           unsigned op = PPC_OP (powerpc_opcodes[i].opcode);
 389
 390           powerpc_opcd_indices[op] = i;
 391         }
 392
 393       last = powerpc_num_opcodes;
 394       for (i = PPC_OPCD_SEGS; i > 0; --i)
 395         {
 396           if (powerpc_opcd_indices[i] == 0)
 397             powerpc_opcd_indices[i] = last;
 398           last = powerpc_opcd_indices[i];
 399         }
 400
 401       i = vle_num_opcodes;
 402       while (--i >= 0)
 403         {
 404           unsigned op = VLE_OP (vle_opcodes[i].opcode, vle_opcodes[i].mask);
 405           unsigned seg = VLE_OP_TO_SEG (op);
 406
 407           vle_opcd_indices[seg] = i;
 408         }
 409
 410       last = vle_num_opcodes;
 411       for (i = VLE_OPCD_SEGS; i > 0; --i)
 412         {
 413           if (vle_opcd_indices[i] == 0)
 414             vle_opcd_indices[i] = last;
 415           last = vle_opcd_indices[i];
 416         }
 417     }
 418
 419   /* SPE2 opcodes */
 420   i = spe2_num_opcodes;
 421   while (--i >= 0)
 422     {
 423       unsigned xop = SPE2_XOP (spe2_opcodes[i].opcode);
 424       unsigned seg = SPE2_XOP_TO_SEG (xop);
 425
 426       spe2_opcd_indices[seg] = i;
 427     }
 428
 429   last = spe2_num_opcodes;
 430   for (i = SPE2_OPCD_SEGS; i > 1; --i)
 431     {
 432       if (spe2_opcd_indices[i] == 0)
 433         spe2_opcd_indices[i] = last;
 434       last = spe2_opcd_indices[i];
 435     }
 436
 437   if (info->arch == bfd_arch_powerpc)
 438     powerpc_init_dialect (info);
 439 }
 440
 441 /* Print a big endian PowerPC instruction.  */
 442
 443 int
 444 print_insn_big_powerpc (bfd_vma memaddr, struct disassemble_info *info)
 445 {
 446   return print_insn_powerpc (memaddr, info, 1, get_powerpc_dialect (info));
 447 }
 448
 449 /* Print a little endian PowerPC instruction.  */
 450
 451 int
 452 print_insn_little_powerpc (bfd_vma memaddr, struct disassemble_info *info)
 453 {
 454   return print_insn_powerpc (memaddr, info, 0, get_powerpc_dialect (info));
 455 }
 456
 457 /* Print a POWER (RS/6000) instruction.  */
 458
 459 int
 460 print_insn_rs6000 (bfd_vma memaddr, struct disassemble_info *info)
 461 {
 462   return print_insn_powerpc (memaddr, info, 1, PPC_OPCODE_POWER);
 463 }
 464
 465 /* Extract the operand value from the PowerPC or POWER instruction.  */
 466
 467 static long
 468 operand_value_powerpc (const struct powerpc_operand *operand,
 469                        unsigned long insn, ppc_cpu_t dialect)
 470 {
 471   long value;
 472   int invalid;
 473   /* Extract the value from the instruction.  */
 474   if (operand->extract)
 475     value = (*operand->extract) (insn, dialect, &invalid);
 476   else
 477     {
 478       if (operand->shift >= 0)
 479         value = (insn >> operand->shift) & operand->bitm;
 480       else
 481         value = (insn << -operand->shift) & operand->bitm;
 482       if ((operand->flags & PPC_OPERAND_SIGNED) != 0)
 483         {
 484           /* BITM is always some number of zeros followed by some
 485              number of ones, followed by some number of zeros.  */
 486           unsigned long top = operand->bitm;
 487           /* top & -top gives the rightmost 1 bit, so this
 488              fills in any trailing zeros.  */
 489           top |= (top & -top) - 1;
 490           top &= ~(top >> 1);
 491           value = (value ^ top) - top;
 492         }
 493     }
 494
 495   return value;
 496 }
 497
 498 /* Determine whether the optional operand(s) should be printed.  */
 499
 500 static int
 501 skip_optional_operands (const unsigned char *opindex,
 502                         unsigned long insn, ppc_cpu_t dialect)
 503 {
 504   const struct powerpc_operand *operand;
 505
 506   for (; *opindex != 0; opindex++)
 507     {
 508       operand = &powerpc_operands[*opindex];
 509       if ((operand->flags & PPC_OPERAND_NEXT) != 0
 510           || ((operand->flags & PPC_OPERAND_OPTIONAL) != 0
 511               && operand_value_powerpc (operand, insn, dialect) !=
 512                  ppc_optional_operand_value (operand)))
 513         return 0;
 514     }
 515
 516   return 1;
 517 }
 518
 519 /* Find a match for INSN in the opcode table, given machine DIALECT.  */
 520
 521 static const struct powerpc_opcode *
 522 lookup_powerpc (unsigned long insn, ppc_cpu_t dialect)
 523 {
 524   const struct powerpc_opcode *opcode, *opcode_end, *last;
 525   unsigned long op;
 526
 527   /* Get the major opcode of the instruction.  */
 528   op = PPC_OP (insn);
 529
 530   /* Find the first match in the opcode table for this major opcode.  */
 531   opcode_end = powerpc_opcodes + powerpc_opcd_indices[op + 1];
 532   last = NULL;
 533   for (opcode = powerpc_opcodes + powerpc_opcd_indices[op];
 534        opcode < opcode_end;
 535        ++opcode)
 536     {
 537       const unsigned char *opindex;
 538       const struct powerpc_operand *operand;
 539       int invalid;
 540
 541       if ((insn & opcode->mask) != opcode->opcode
 542           || ((dialect & PPC_OPCODE_ANY) == 0
 543               && ((opcode->flags & dialect) == 0
 544                   || (opcode->deprecated & dialect) != 0)))
 545         continue;
 546
 547       /* Check validity of operands.  */
 548       invalid = 0;
 549       for (opindex = opcode->operands; *opindex != 0; opindex++)
 550         {
 551           operand = powerpc_operands + *opindex;
 552           if (operand->extract)
 553             (*operand->extract) (insn, dialect, &invalid);
 554         }
 555       if (invalid)
 556         continue;
 557
 558       if ((dialect & PPC_OPCODE_RAW) == 0)
 559         return opcode;
 560
 561       /* The raw machine insn is one that is not a specialization.  */
 562       if (last == NULL
 563           || (last->mask & ~opcode->mask) != 0)
 564         last = opcode;
 565     }
 566
 567   return last;
 568 }
 569
 570 /* Find a match for INSN in the VLE opcode table.  */
 571
 572 static const struct powerpc_opcode *
 573 lookup_vle (unsigned long insn)
 574 {
 575   const struct powerpc_opcode *opcode;
 576   const struct powerpc_opcode *opcode_end;
 577   unsigned op, seg;
 578
 579   op = PPC_OP (insn);
 580   if (op >= 0x20 && op <= 0x37)
 581     {
 582       /* This insn has a 4-bit opcode.  */
 583       op &= 0x3c;
 584     }
 585   seg = VLE_OP_TO_SEG (op);
 586
 587   /* Find the first match in the opcode table for this major opcode.  */
 588   opcode_end = vle_opcodes + vle_opcd_indices[seg + 1];
 589   for (opcode = vle_opcodes + vle_opcd_indices[seg];
 590        opcode < opcode_end;
 591        ++opcode)
 592     {
 593       unsigned long table_opcd = opcode->opcode;
 594       unsigned long table_mask = opcode->mask;
 595       bfd_boolean table_op_is_short = PPC_OP_SE_VLE(table_mask);
 596       unsigned long insn2;
 597       const unsigned char *opindex;
 598       const struct powerpc_operand *operand;
 599       int invalid;
 600
 601       insn2 = insn;
 602       if (table_op_is_short)
 603         insn2 >>= 16;
 604       if ((insn2 & table_mask) != table_opcd)
 605         continue;
 606
 607       /* Check validity of operands.  */
 608       invalid = 0;
 609       for (opindex = opcode->operands; *opindex != 0; ++opindex)
 610         {
 611           operand = powerpc_operands + *opindex;
 612           if (operand->extract)
 613             (*operand->extract) (insn, (ppc_cpu_t)0, &invalid);
 614         }
 615       if (invalid)
 616         continue;
 617
 618       return opcode;
 619     }
 620
 621   return NULL;
 622 }
 623
 624 /* Find a match for INSN in the SPE2 opcode table.  */
 625
 626 static const struct powerpc_opcode *
 627 lookup_spe2 (unsigned long insn)
 628 {
 629   const struct powerpc_opcode *opcode, *opcode_end;
 630   unsigned op, xop, seg;
 631
 632   op = PPC_OP (insn);
 633   if (op != 0x4)
 634     {
 635       /* This is not SPE2 insn.
 636        * All SPE2 instructions have OP=4 and differs by XOP  */
 637       return NULL;
 638     }
 639   xop = SPE2_XOP (insn);
 640   seg = SPE2_XOP_TO_SEG (xop);
 641
 642   /* Find the first match in the opcode table for this major opcode.  */
 643   opcode_end = spe2_opcodes + spe2_opcd_indices[seg + 1];
 644   for (opcode = spe2_opcodes + spe2_opcd_indices[seg];
 645        opcode < opcode_end;
 646        ++opcode)
 647     {
 648       unsigned long table_opcd = opcode->opcode;
 649       unsigned long table_mask = opcode->mask;
 650       unsigned long insn2;
 651       const unsigned char *opindex;
 652       const struct powerpc_operand *operand;
 653       int invalid;
 654
 655       insn2 = insn;
 656       if ((insn2 & table_mask) != table_opcd)
 657         continue;
 658
 659       /* Check validity of operands.  */
 660       invalid = 0;
 661       for (opindex = opcode->operands; *opindex != 0; ++opindex)
 662         {
 663           operand = powerpc_operands + *opindex;
 664           if (operand->extract)
 665             (*operand->extract) (insn, (ppc_cpu_t)0, &invalid);
 666         }
 667       if (invalid)
 668         continue;
 669
 670       return opcode;
 671     }
 672
 673   return NULL;
 674 }
 675
 676 /* Print a PowerPC or POWER instruction.  */
 677
 678 static int
 679 print_insn_powerpc (bfd_vma memaddr,
 680                     struct disassemble_info *info,
 681                     int bigendian,
 682                     ppc_cpu_t dialect)
 683 {
 684   bfd_byte buffer[4];
 685   int status;
 686   unsigned long insn;
 687   const struct powerpc_opcode *opcode;
 688   bfd_boolean insn_is_short;
 689
 690   status = (*info->read_memory_func) (memaddr, buffer, 4, info);
 691   if (status != 0)
 692     {
 693       /* The final instruction may be a 2-byte VLE insn.  */
 694       if ((dialect & PPC_OPCODE_VLE) != 0)
 695         {
 696           /* Clear buffer so unused bytes will not have garbage in them.  */
 697           buffer[0] = buffer[1] = buffer[2] = buffer[3] = 0;
 698           status = (*info->read_memory_func) (memaddr, buffer, 2, info);
 699           if (status != 0)
 700             {
 701               (*info->memory_error_func) (status, memaddr, info);
 702               return -1;
 703             }
 704         }
 705       else
 706         {
 707           (*info->memory_error_func) (status, memaddr, info);
 708           return -1;
 709         }
 710     }
 711
 712   if (bigendian)
 713     insn = bfd_getb32 (buffer);
 714   else
 715     insn = bfd_getl32 (buffer);
 716
 717   /* Get the major opcode of the insn.  */
 718   opcode = NULL;
 719   insn_is_short = FALSE;
 720   if ((dialect & PPC_OPCODE_VLE) != 0)
 721     {
 722       opcode = lookup_vle (insn);
 723       if (opcode != NULL)
 724         insn_is_short = PPC_OP_SE_VLE(opcode->mask);
 725     }
 726   if (opcode == NULL && (dialect & PPC_OPCODE_SPE2) != 0)
 727     opcode = lookup_spe2 (insn);
 728   if (opcode == NULL)
 729     opcode = lookup_powerpc (insn, dialect & ~PPC_OPCODE_ANY);
 730   if (opcode == NULL && (dialect & PPC_OPCODE_ANY) != 0)
 731     opcode = lookup_powerpc (insn, dialect);
 732
 733   if (opcode != NULL)
 734     {
 735       const unsigned char *opindex;
 736       const struct powerpc_operand *operand;
 737       int need_comma;
 738       int need_paren;
 739       int skip_optional;
 740
 741       if (opcode->operands[0] != 0)
 742         (*info->fprintf_func) (info->stream, "%-7s ", opcode->name);
 743       else
 744         (*info->fprintf_func) (info->stream, "%s", opcode->name);
 745
 746       if (insn_is_short)
 747         /* The operands will be fetched out of the 16-bit instruction.  */
 748         insn >>= 16;
 749
 750       /* Now extract and print the operands.  */
 751       need_comma = 0;
 752       need_paren = 0;
 753       skip_optional = -1;
 754       for (opindex = opcode->operands; *opindex != 0; opindex++)
 755         {
 756           long value;
 757
 758           operand = powerpc_operands + *opindex;
 759
 760           /* Operands that are marked FAKE are simply ignored.  We
 761              already made sure that the extract function considered
 762              the instruction to be valid.  */
 763           if ((operand->flags & PPC_OPERAND_FAKE) != 0)
 764             continue;
 765
 766           /* If all of the optional operands have the value zero,
 767              then don't print any of them.  */
 768           if ((operand->flags & PPC_OPERAND_OPTIONAL) != 0)
 769             {
 770               if (skip_optional < 0)
 771                 skip_optional = skip_optional_operands (opindex, insn,
 772                                                         dialect);
 773               if (skip_optional)
 774                 continue;
 775             }
 776
 777           value = operand_value_powerpc (operand, insn, dialect);
 778
 779           if (need_comma)
 780             {
 781               (*info->fprintf_func) (info->stream, ",");
 782               need_comma = 0;
 783             }
 784
 785           /* Print the operand as directed by the flags.  */
 786           if ((operand->flags & PPC_OPERAND_GPR) != 0
 787               || ((operand->flags & PPC_OPERAND_GPR_0) != 0 && value != 0))
 788             (*info->fprintf_func) (info->stream, "r%ld", value);
 789           else if ((operand->flags & PPC_OPERAND_FPR) != 0)
 790             (*info->fprintf_func) (info->stream, "f%ld", value);
 791           else if ((operand->flags & PPC_OPERAND_VR) != 0)
 792             (*info->fprintf_func) (info->stream, "v%ld", value);
 793           else if ((operand->flags & PPC_OPERAND_VSR) != 0)
 794             (*info->fprintf_func) (info->stream, "vs%ld", value);
 795           else if ((operand->flags & PPC_OPERAND_RELATIVE) != 0)
 796             (*info->print_address_func) (memaddr + value, info);
 797           else if ((operand->flags & PPC_OPERAND_ABSOLUTE) != 0)
 798             (*info->print_address_func) ((bfd_vma) value & 0xffffffff, info);
 799           else if ((operand->flags & PPC_OPERAND_FSL) != 0)
 800             (*info->fprintf_func) (info->stream, "fsl%ld", value);
 801           else if ((operand->flags & PPC_OPERAND_FCR) != 0)
 802             (*info->fprintf_func) (info->stream, "fcr%ld", value);
 803           else if ((operand->flags & PPC_OPERAND_UDI) != 0)
 804             (*info->fprintf_func) (info->stream, "%ld", value);
 805           else if ((operand->flags & PPC_OPERAND_CR_REG) != 0
 806                    && (((dialect & PPC_OPCODE_PPC) != 0)
 807                        || ((dialect & PPC_OPCODE_VLE) != 0)))
 808             (*info->fprintf_func) (info->stream, "cr%ld", value);
 809           else if (((operand->flags & PPC_OPERAND_CR_BIT) != 0)
 810                    && (((dialect & PPC_OPCODE_PPC) != 0)
 811                        || ((dialect & PPC_OPCODE_VLE) != 0)))
 812             {
 813               static const char *cbnames[4] = { "lt", "gt", "eq", "so" };
 814               int cr;
 815               int cc;
 816
 817               cr = value >> 2;
 818               if (cr != 0)
 819                 (*info->fprintf_func) (info->stream, "4*cr%d+", cr);
 820               cc = value & 3;
 821               (*info->fprintf_func) (info->stream, "%s", cbnames[cc]);
 822             }
 823           else
 824             (*info->fprintf_func) (info->stream, "%d", (int) value);
 825
 826           if (need_paren)
 827             {
 828               (*info->fprintf_func) (info->stream, ")");
 829               need_paren = 0;
 830             }
 831
 832           if ((operand->flags & PPC_OPERAND_PARENS) == 0)
 833             need_comma = 1;
 834           else
 835             {
 836               (*info->fprintf_func) (info->stream, "(");
 837               need_paren = 1;
 838             }
 839         }
 840
 841       /* We have found and printed an instruction.
 842          If it was a short VLE instruction we have more to do.  */
 843       if (insn_is_short)
 844         {
 845           memaddr += 2;
 846           return 2;
 847         }
 848       else
 849         /* Otherwise, return.  */
 850         return 4;
 851     }
 852
 853   /* We could not find a match.  */
 854   (*info->fprintf_func) (info->stream, ".long 0x%lx", insn);
 855
 856   return 4;
 857 }
 858
 859 const disasm_options_t *
 860 disassembler_options_powerpc (void)
 861 {
 862   static disasm_options_t *opts = NULL;
 863
 864   if (opts == NULL)
 865     {
 866       size_t i, num_options = ARRAY_SIZE (ppc_opts);
 867       opts = XNEW (disasm_options_t);
 868       opts->name = XNEWVEC (const char *, num_options + 1);
 869       for (i = 0; i < num_options; i++)
 870         opts->name[i] = ppc_opts[i].opt;
 871       /* The array we return must be NULL terminated.  */
 872       opts->name[i] = NULL;
 873       opts->description = NULL;
 874     }
 875
 876   return opts;
 877 }
 878
 879 void
 880 print_ppc_disassembler_options (FILE *stream)
 881 {
 882   unsigned int i, col;
 883
 884   fprintf (stream, _("\n\
 885 The following PPC specific disassembler options are supported for use with\n\
 886 the -M switch:\n"));
 887
 888   for (col = 0, i = 0; i < ARRAY_SIZE (ppc_opts); i++)
 889     {
 890       col += fprintf (stream, " %s,", ppc_opts[i].opt);
 891       if (col > 66)
 892         {
 893           fprintf (stream, "\n");
 894           col = 0;
 895         }
 896     }
 897   fprintf (stream, "\n");
 898 }