opcodes/ppc-dis.c

   1 /* ppc-dis.c -- Disassemble PowerPC instructions
   2    Copyright 1994, 1995, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007,
   3    2008, 2009, 2010, 2011, 2012 Free Software Foundation, Inc.
   4    Written by Ian Lance Taylor, Cygnus Support
   5
   6    This file is part of the GNU opcodes library.
   7
   8    This library is free software; you can redistribute it and/or modify
   9    it under the terms of the GNU General Public License as published by
  10    the Free Software Foundation; either version 3, or (at your option)
  11    any later version.
  12
  13    It is distributed in the hope that it will be useful, but WITHOUT
  14    ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  15    or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
  16    License for more details.
  17
  18    You should have received a copy of the GNU General Public License
  19    along with this file; see the file COPYING.  If not, write to the
  20    Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston,
  21    MA 02110-1301, USA.  */
  22
  23 #include "sysdep.h"
  24 #include <stdio.h>
  25 #include "dis-asm.h"
  26 #include "elf-bfd.h"
  27 #include "elf/ppc.h"
  28 #include "opintl.h"
  29 #include "opcode/ppc.h"
  30
  31 /* This file provides several disassembler functions, all of which use
  32    the disassembler interface defined in dis-asm.h.  Several functions
  33    are provided because this file handles disassembly for the PowerPC
  34    in both big and little endian mode and also for the POWER (RS/6000)
  35    chip.  */
  36 static int print_insn_powerpc (bfd_vma, struct disassemble_info *, int,
  37                                ppc_cpu_t);
  38
  39 struct dis_private
  40 {
  41   /* Stash the result of parsing disassembler_options here.  */
  42   ppc_cpu_t dialect;
  43 } private;
  44
  45 #define POWERPC_DIALECT(INFO) \
  46   (((struct dis_private *) ((INFO)->private_data))->dialect)
  47
  48 struct ppc_mopt {
  49   const char *opt;
  50   ppc_cpu_t cpu;
  51   ppc_cpu_t sticky;
  52 };
  53
  54 struct ppc_mopt ppc_opts[] = {
  55   { "403",     (PPC_OPCODE_PPC | PPC_OPCODE_403),
  56     0 },
  57   { "405",     (PPC_OPCODE_PPC | PPC_OPCODE_403 | PPC_OPCODE_405),
  58     0 },
  59   { "440",     (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE | PPC_OPCODE_440
  60                 | PPC_OPCODE_ISEL | PPC_OPCODE_RFMCI),
  61     0 },
  62   { "464",     (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE | PPC_OPCODE_440
  63                 | PPC_OPCODE_ISEL | PPC_OPCODE_RFMCI),
  64     0 },
  65   { "476",     (PPC_OPCODE_PPC | PPC_OPCODE_ISEL | PPC_OPCODE_440
  66                 | PPC_OPCODE_476 | PPC_OPCODE_POWER4 | PPC_OPCODE_POWER5),
  67     0 },
  68   { "601",     (PPC_OPCODE_PPC | PPC_OPCODE_601),
  69     0 },
  70   { "603",     (PPC_OPCODE_PPC),
  71     0 },
  72   { "604",     (PPC_OPCODE_PPC),
  73     0 },
  74   { "620",     (PPC_OPCODE_PPC | PPC_OPCODE_64),
  75     0 },
  76   { "7400",    (PPC_OPCODE_PPC | PPC_OPCODE_ALTIVEC),
  77     0 },
  78   { "7410",    (PPC_OPCODE_PPC | PPC_OPCODE_ALTIVEC),
  79     0 },
  80   { "7450",    (PPC_OPCODE_PPC | PPC_OPCODE_ALTIVEC),
  81     0 },
  82   { "7455",    (PPC_OPCODE_PPC | PPC_OPCODE_ALTIVEC),
  83     0 },
  84   { "750cl",   (PPC_OPCODE_PPC | PPC_OPCODE_PPCPS)
  85     , 0 },
  86   { "a2",      (PPC_OPCODE_PPC | PPC_OPCODE_ISEL | PPC_OPCODE_POWER4
  87                 | PPC_OPCODE_POWER5 | PPC_OPCODE_CACHELCK | PPC_OPCODE_64
  88                 | PPC_OPCODE_A2),
  89     0 },
  90   { "altivec", (PPC_OPCODE_PPC),
  91     PPC_OPCODE_ALTIVEC | PPC_OPCODE_ALTIVEC2 },
  92   { "any",     0,
  93     PPC_OPCODE_ANY },
  94   { "booke",   (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE),
  95     0 },
  96   { "booke32", (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE),
  97     0 },
  98   { "cell",    (PPC_OPCODE_PPC | PPC_OPCODE_64 | PPC_OPCODE_POWER4
  99                 | PPC_OPCODE_CELL | PPC_OPCODE_ALTIVEC),
 100     0 },
 101   { "com",     (PPC_OPCODE_COMMON),
 102     0 },
 103   { "e300",    (PPC_OPCODE_PPC | PPC_OPCODE_E300),
 104     0 },
 105   { "e500",    (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE | PPC_OPCODE_SPE
 106                 | PPC_OPCODE_ISEL | PPC_OPCODE_EFS | PPC_OPCODE_BRLOCK
 107                 | PPC_OPCODE_PMR | PPC_OPCODE_CACHELCK | PPC_OPCODE_RFMCI
 108                 | PPC_OPCODE_E500),
 109     0 },
 110   { "e500mc",  (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE | PPC_OPCODE_ISEL
 111                 | PPC_OPCODE_PMR | PPC_OPCODE_CACHELCK | PPC_OPCODE_RFMCI
 112                 | PPC_OPCODE_E500MC),
 113     0 },
 114   { "e500mc64",  (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE | PPC_OPCODE_ISEL
 115                 | PPC_OPCODE_PMR | PPC_OPCODE_CACHELCK | PPC_OPCODE_RFMCI
 116                 | PPC_OPCODE_E500MC | PPC_OPCODE_64 | PPC_OPCODE_POWER5
 117                 | PPC_OPCODE_POWER6 | PPC_OPCODE_POWER7),
 118     0 },
 119   { "e5500",    (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE | PPC_OPCODE_ISEL
 120                 | PPC_OPCODE_PMR | PPC_OPCODE_CACHELCK | PPC_OPCODE_RFMCI
 121                 | PPC_OPCODE_E500MC | PPC_OPCODE_64 | PPC_OPCODE_POWER4
 122                 | PPC_OPCODE_POWER5 | PPC_OPCODE_POWER6
 123                 | PPC_OPCODE_POWER7),
 124     0 },
 125   { "e6500",   (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE | PPC_OPCODE_ISEL
 126                 | PPC_OPCODE_PMR | PPC_OPCODE_CACHELCK | PPC_OPCODE_RFMCI
 127                 | PPC_OPCODE_E500MC | PPC_OPCODE_64 | PPC_OPCODE_ALTIVEC
 128                 | PPC_OPCODE_ALTIVEC2 | PPC_OPCODE_E6500 | PPC_OPCODE_POWER4
 129                 | PPC_OPCODE_POWER5 | PPC_OPCODE_POWER6 | PPC_OPCODE_POWER7),
 130     0 },
 131   { "e500x2",  (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE | PPC_OPCODE_SPE
 132                 | PPC_OPCODE_ISEL | PPC_OPCODE_EFS | PPC_OPCODE_BRLOCK
 133                 | PPC_OPCODE_PMR | PPC_OPCODE_CACHELCK | PPC_OPCODE_RFMCI
 134                 | PPC_OPCODE_E500),
 135     0 },
 136   { "efs",     (PPC_OPCODE_PPC | PPC_OPCODE_EFS),
 137     0 },
 138   { "power4",  (PPC_OPCODE_PPC | PPC_OPCODE_64 | PPC_OPCODE_POWER4),
 139     0 },
 140   { "power5",  (PPC_OPCODE_PPC | PPC_OPCODE_64 | PPC_OPCODE_POWER4
 141                 | PPC_OPCODE_POWER5),
 142     0 },
 143   { "power6",  (PPC_OPCODE_PPC | PPC_OPCODE_64 | PPC_OPCODE_POWER4
 144                 | PPC_OPCODE_POWER5 | PPC_OPCODE_POWER6 | PPC_OPCODE_ALTIVEC),
 145     0 },
 146   { "power7",  (PPC_OPCODE_PPC | PPC_OPCODE_ISEL | PPC_OPCODE_64
 147                 | PPC_OPCODE_POWER4 | PPC_OPCODE_POWER5 | PPC_OPCODE_POWER6
 148                 | PPC_OPCODE_POWER7 | PPC_OPCODE_ALTIVEC | PPC_OPCODE_VSX),
 149     0 },
 150   { "power8",  (PPC_OPCODE_PPC | PPC_OPCODE_ISEL | PPC_OPCODE_64
 151                 | PPC_OPCODE_POWER4 | PPC_OPCODE_POWER5 | PPC_OPCODE_POWER6
 152                 | PPC_OPCODE_POWER7 | PPC_OPCODE_POWER8 | PPC_OPCODE_HTM
 153                 | PPC_OPCODE_ALTIVEC | PPC_OPCODE_ALTIVEC2 | PPC_OPCODE_VSX),
 154     0 },
 155   { "ppc",     (PPC_OPCODE_PPC),
 156     0 },
 157   { "ppc32",   (PPC_OPCODE_PPC),
 158     0 },
 159   { "ppc64",   (PPC_OPCODE_PPC | PPC_OPCODE_64),
 160     0 },
 161   { "ppc64bridge", (PPC_OPCODE_PPC | PPC_OPCODE_64_BRIDGE),
 162     0 },
 163   { "ppcps",   (PPC_OPCODE_PPC | PPC_OPCODE_PPCPS),
 164     0 },
 165   { "pwr",     (PPC_OPCODE_POWER),
 166     0 },
 167   { "pwr2",    (PPC_OPCODE_POWER | PPC_OPCODE_POWER2),
 168     0 },
 169   { "pwr4",    (PPC_OPCODE_PPC | PPC_OPCODE_64 | PPC_OPCODE_POWER4),
 170     0 },
 171   { "pwr5",    (PPC_OPCODE_PPC | PPC_OPCODE_64 | PPC_OPCODE_POWER4
 172                 | PPC_OPCODE_POWER5),
 173     0 },
 174   { "pwr5x",   (PPC_OPCODE_PPC | PPC_OPCODE_64 | PPC_OPCODE_POWER4
 175                 | PPC_OPCODE_POWER5),
 176     0 },
 177   { "pwr6",    (PPC_OPCODE_PPC | PPC_OPCODE_64 | PPC_OPCODE_POWER4
 178                 | PPC_OPCODE_POWER5 | PPC_OPCODE_POWER6 | PPC_OPCODE_ALTIVEC),
 179     0 },
 180   { "pwr7",    (PPC_OPCODE_PPC | PPC_OPCODE_ISEL | PPC_OPCODE_64
 181                 | PPC_OPCODE_POWER4 | PPC_OPCODE_POWER5 | PPC_OPCODE_POWER6
 182                 | PPC_OPCODE_POWER7 | PPC_OPCODE_ALTIVEC | PPC_OPCODE_VSX),
 183     0 },
 184   { "pwr8",    (PPC_OPCODE_PPC | PPC_OPCODE_ISEL | PPC_OPCODE_64
 185                 | PPC_OPCODE_POWER4 | PPC_OPCODE_POWER5 | PPC_OPCODE_POWER6
 186                 | PPC_OPCODE_POWER7 | PPC_OPCODE_POWER8 | PPC_OPCODE_HTM
 187                 | PPC_OPCODE_ALTIVEC | PPC_OPCODE_ALTIVEC2 | PPC_OPCODE_VSX),
 188     0 },
 189   { "pwrx",    (PPC_OPCODE_POWER | PPC_OPCODE_POWER2),
 190     0 },
 191   { "spe",     (PPC_OPCODE_PPC | PPC_OPCODE_EFS),
 192     PPC_OPCODE_SPE },
 193   { "titan",   (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE | PPC_OPCODE_PMR
 194                 | PPC_OPCODE_RFMCI | PPC_OPCODE_TITAN),
 195     0 },
 196   { "vle",     (PPC_OPCODE_PPC | PPC_OPCODE_ISEL | PPC_OPCODE_VLE),
 197     PPC_OPCODE_VLE },
 198   { "vsx",     (PPC_OPCODE_PPC),
 199     PPC_OPCODE_VSX },
 200   { "htm",     (PPC_OPCODE_PPC),
 201     PPC_OPCODE_HTM },
 202 };
 203
 204 /* Switch between Booke and VLE dialects for interlinked dumps.  */
 205 static ppc_cpu_t
 206 get_powerpc_dialect (struct disassemble_info *info)
 207 {
 208   ppc_cpu_t dialect = 0;
 209
 210   dialect = POWERPC_DIALECT (info);
 211
 212   /* Disassemble according to the section headers flags for VLE-mode.  */
 213   if (dialect & PPC_OPCODE_VLE
 214       && info->section->owner != NULL
 215       && bfd_get_flavour (info->section->owner) == bfd_target_elf_flavour
 216       && elf_object_id (info->section->owner) == PPC32_ELF_DATA
 217       && (elf_section_flags (info->section) & SHF_PPC_VLE) != 0)
 218     return dialect;
 219   else
 220     return dialect & ~ PPC_OPCODE_VLE;
 221 }
 222
 223 /* Handle -m and -M options that set cpu type, and .machine arg.  */
 224
 225 ppc_cpu_t
 226 ppc_parse_cpu (ppc_cpu_t ppc_cpu, ppc_cpu_t *sticky, const char *arg)
 227 {
 228   unsigned int i;
 229
 230   for (i = 0; i < sizeof (ppc_opts) / sizeof (ppc_opts[0]); i++)
 231     if (strcmp (ppc_opts[i].opt, arg) == 0)
 232       {
 233         if (ppc_opts[i].sticky)
 234           {
 235             *sticky |= ppc_opts[i].sticky;
 236             if ((ppc_cpu & ~*sticky) != 0)
 237               break;
 238           }
 239         ppc_cpu = ppc_opts[i].cpu;
 240         break;
 241       }
 242   if (i >= sizeof (ppc_opts) / sizeof (ppc_opts[0]))
 243     return 0;
 244
 245   ppc_cpu |= *sticky;
 246   return ppc_cpu;
 247 }
 248
 249 /* Determine which set of machines to disassemble for.  */
 250
 251 static void
 252 powerpc_init_dialect (struct disassemble_info *info)
 253 {
 254   ppc_cpu_t dialect = 0;
 255   ppc_cpu_t sticky = 0;
 256   char *arg;
 257   struct dis_private *priv = calloc (sizeof (*priv), 1);
 258
 259   if (priv == NULL)
 260     priv = &private;
 261
 262   switch (info->mach)
 263     {
 264     case bfd_mach_ppc_403:
 265     case bfd_mach_ppc_403gc:
 266       dialect = (PPC_OPCODE_PPC | PPC_OPCODE_403);
 267       break;
 268     case bfd_mach_ppc_405:
 269       dialect = (PPC_OPCODE_PPC | PPC_OPCODE_403 | PPC_OPCODE_405);
 270       break;
 271     case bfd_mach_ppc_601:
 272       dialect = (PPC_OPCODE_PPC | PPC_OPCODE_601);
 273       break;
 274     case bfd_mach_ppc_a35:
 275     case bfd_mach_ppc_rs64ii:
 276     case bfd_mach_ppc_rs64iii:
 277       dialect = (PPC_OPCODE_POWER | PPC_OPCODE_POWER2 | PPC_OPCODE_64);
 278       break;
 279     case bfd_mach_ppc_e500:
 280       dialect = (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE | PPC_OPCODE_SPE
 281                  | PPC_OPCODE_ISEL | PPC_OPCODE_EFS | PPC_OPCODE_BRLOCK
 282                  | PPC_OPCODE_PMR | PPC_OPCODE_CACHELCK | PPC_OPCODE_RFMCI
 283                  | PPC_OPCODE_E500);
 284       break;
 285     case bfd_mach_ppc_e500mc:
 286       dialect = (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE | PPC_OPCODE_ISEL
 287                  | PPC_OPCODE_PMR | PPC_OPCODE_CACHELCK | PPC_OPCODE_RFMCI
 288                  | PPC_OPCODE_E500MC);
 289       break;
 290     case bfd_mach_ppc_e500mc64:
 291       dialect = (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE | PPC_OPCODE_ISEL
 292                  | PPC_OPCODE_PMR | PPC_OPCODE_CACHELCK | PPC_OPCODE_RFMCI
 293                  | PPC_OPCODE_E500MC | PPC_OPCODE_64 | PPC_OPCODE_POWER5
 294                  | PPC_OPCODE_POWER6 | PPC_OPCODE_POWER7);
 295       break;
 296     case bfd_mach_ppc_e5500:
 297       dialect = (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE | PPC_OPCODE_ISEL
 298                  | PPC_OPCODE_PMR | PPC_OPCODE_CACHELCK | PPC_OPCODE_RFMCI
 299                  | PPC_OPCODE_E500MC | PPC_OPCODE_64 | PPC_OPCODE_POWER4
 300                  | PPC_OPCODE_POWER5 | PPC_OPCODE_POWER6
 301                  | PPC_OPCODE_POWER7);
 302       break;
 303     case bfd_mach_ppc_e6500:
 304       dialect = (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE | PPC_OPCODE_ISEL
 305                  | PPC_OPCODE_PMR | PPC_OPCODE_CACHELCK | PPC_OPCODE_RFMCI
 306                  | PPC_OPCODE_E500MC | PPC_OPCODE_64 | PPC_OPCODE_ALTIVEC
 307                  | PPC_OPCODE_ALTIVEC2 | PPC_OPCODE_E6500 | PPC_OPCODE_POWER4
 308                  | PPC_OPCODE_POWER5 | PPC_OPCODE_POWER6 | PPC_OPCODE_POWER7);
 309       break;
 310     case bfd_mach_ppc_titan:
 311       dialect = (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE | PPC_OPCODE_PMR
 312                  | PPC_OPCODE_RFMCI | PPC_OPCODE_TITAN);
 313       break;
 314     case bfd_mach_ppc_vle:
 315       dialect = (PPC_OPCODE_PPC | PPC_OPCODE_ISEL | PPC_OPCODE_VLE);
 316       break;
 317     default:
 318       dialect = ppc_parse_cpu (dialect, &sticky, "power8") | PPC_OPCODE_ANY;
 319     }
 320
 321   arg = info->disassembler_options;
 322   while (arg != NULL)
 323     {
 324       ppc_cpu_t new_cpu = 0;
 325       char *end = strchr (arg, ',');
 326
 327       if (end != NULL)
 328         *end = 0;
 329
 330       if ((new_cpu = ppc_parse_cpu (dialect, &sticky, arg)) != 0)
 331         dialect = new_cpu;
 332       else if (strcmp (arg, "32") == 0)
 333         dialect &= ~(ppc_cpu_t) PPC_OPCODE_64;
 334       else if (strcmp (arg, "64") == 0)
 335         dialect |= PPC_OPCODE_64;
 336       else
 337         fprintf (stderr, _("warning: ignoring unknown -M%s option\n"), arg);
 338
 339       if (end != NULL)
 340         *end++ = ',';
 341       arg = end;
 342     }
 343
 344   info->private_data = priv;
 345   POWERPC_DIALECT(info) = dialect;
 346 }
 347
 348 #define PPC_OPCD_SEGS 64
 349 static unsigned short powerpc_opcd_indices[PPC_OPCD_SEGS+1];
 350 #define VLE_OPCD_SEGS 32
 351 static unsigned short vle_opcd_indices[VLE_OPCD_SEGS+1];
 352
 353 /* Calculate opcode table indices to speed up disassembly,
 354    and init dialect.  */
 355
 356 void
 357 disassemble_init_powerpc (struct disassemble_info *info)
 358 {
 359   int i;
 360   unsigned short last;
 361
 362   i = powerpc_num_opcodes;
 363   while (--i >= 0)
 364     {
 365       unsigned op = PPC_OP (powerpc_opcodes[i].opcode);
 366
 367       powerpc_opcd_indices[op] = i;
 368     }
 369
 370   last = powerpc_num_opcodes;
 371   for (i = PPC_OPCD_SEGS; i > 0; --i)
 372     {
 373       if (powerpc_opcd_indices[i] == 0)
 374         powerpc_opcd_indices[i] = last;
 375       last = powerpc_opcd_indices[i];
 376     }
 377
 378   i = vle_num_opcodes;
 379   while (--i >= 0)
 380     {
 381       unsigned op = VLE_OP (vle_opcodes[i].opcode, vle_opcodes[i].mask);
 382       unsigned seg = VLE_OP_TO_SEG (op);
 383
 384       vle_opcd_indices[seg] = i;
 385     }
 386
 387   last = vle_num_opcodes;
 388   for (i = VLE_OPCD_SEGS; i > 0; --i)
 389     {
 390       if (vle_opcd_indices[i] == 0)
 391         vle_opcd_indices[i] = last;
 392       last = vle_opcd_indices[i];
 393     }
 394
 395   if (info->arch == bfd_arch_powerpc)
 396     powerpc_init_dialect (info);
 397 }
 398
 399 /* Print a big endian PowerPC instruction.  */
 400
 401 int
 402 print_insn_big_powerpc (bfd_vma memaddr, struct disassemble_info *info)
 403 {
 404   return print_insn_powerpc (memaddr, info, 1, get_powerpc_dialect (info));
 405 }
 406
 407 /* Print a little endian PowerPC instruction.  */
 408
 409 int
 410 print_insn_little_powerpc (bfd_vma memaddr, struct disassemble_info *info)
 411 {
 412   return print_insn_powerpc (memaddr, info, 0, get_powerpc_dialect (info));
 413 }
 414
 415 /* Print a POWER (RS/6000) instruction.  */
 416
 417 int
 418 print_insn_rs6000 (bfd_vma memaddr, struct disassemble_info *info)
 419 {
 420   return print_insn_powerpc (memaddr, info, 1, PPC_OPCODE_POWER);
 421 }
 422
 423 /* Extract the operand value from the PowerPC or POWER instruction.  */
 424
 425 static long
 426 operand_value_powerpc (const struct powerpc_operand *operand,
 427                        unsigned long insn, ppc_cpu_t dialect)
 428 {
 429   long value;
 430   int invalid;
 431   /* Extract the value from the instruction.  */
 432   if (operand->extract)
 433     value = (*operand->extract) (insn, dialect, &invalid);
 434   else
 435     {
 436       if (operand->shift >= 0)
 437         value = (insn >> operand->shift) & operand->bitm;
 438       else
 439         value = (insn << -operand->shift) & operand->bitm;
 440       if ((operand->flags & PPC_OPERAND_SIGNED) != 0)
 441         {
 442           /* BITM is always some number of zeros followed by some
 443              number of ones, followed by some number of zeros.  */
 444           unsigned long top = operand->bitm;
 445           /* top & -top gives the rightmost 1 bit, so this
 446              fills in any trailing zeros.  */
 447           top |= (top & -top) - 1;
 448           top &= ~(top >> 1);
 449           value = (value ^ top) - top;
 450         }
 451     }
 452
 453   return value;
 454 }
 455
 456 /* Determine whether the optional operand(s) should be printed.  */
 457
 458 static int
 459 skip_optional_operands (const unsigned char *opindex,
 460                         unsigned long insn, ppc_cpu_t dialect)
 461 {
 462   const struct powerpc_operand *operand;
 463
 464   for (; *opindex != 0; opindex++)
 465     {
 466       operand = &powerpc_operands[*opindex];
 467       if ((operand->flags & PPC_OPERAND_NEXT) != 0
 468           || ((operand->flags & PPC_OPERAND_OPTIONAL) != 0
 469               && operand_value_powerpc (operand, insn, dialect) != 0))
 470         return 0;
 471     }
 472
 473   return 1;
 474 }
 475
 476 /* Find a match for INSN in the opcode table, given machine DIALECT.
 477    A DIALECT of -1 is special, matching all machine opcode variations.  */
 478
 479 static const struct powerpc_opcode *
 480 lookup_powerpc (unsigned long insn, ppc_cpu_t dialect)
 481 {
 482   const struct powerpc_opcode *opcode;
 483   const struct powerpc_opcode *opcode_end;
 484   unsigned long op;
 485
 486   /* Get the major opcode of the instruction.  */
 487   op = PPC_OP (insn);
 488
 489   /* Find the first match in the opcode table for this major opcode.  */
 490   opcode_end = powerpc_opcodes + powerpc_opcd_indices[op + 1];
 491   for (opcode = powerpc_opcodes + powerpc_opcd_indices[op];
 492        opcode < opcode_end;
 493        ++opcode)
 494     {
 495       const unsigned char *opindex;
 496       const struct powerpc_operand *operand;
 497       int invalid;
 498
 499       if ((insn & opcode->mask) != opcode->opcode
 500           || (dialect != (ppc_cpu_t) -1
 501               && ((opcode->flags & dialect) == 0
 502                   || (opcode->deprecated & dialect) != 0)))
 503         continue;
 504
 505       /* Check validity of operands.  */
 506       invalid = 0;
 507       for (opindex = opcode->operands; *opindex != 0; opindex++)
 508         {
 509           operand = powerpc_operands + *opindex;
 510           if (operand->extract)
 511             (*operand->extract) (insn, dialect, &invalid);
 512         }
 513       if (invalid)
 514         continue;
 515
 516       return opcode;
 517     }
 518
 519   return NULL;
 520 }
 521
 522 /* Find a match for INSN in the VLE opcode table.  */
 523
 524 static const struct powerpc_opcode *
 525 lookup_vle (unsigned long insn)
 526 {
 527   const struct powerpc_opcode *opcode;
 528   const struct powerpc_opcode *opcode_end;
 529   unsigned op, seg;
 530
 531   op = PPC_OP (insn);
 532   if (op >= 0x20 && op <= 0x37)
 533     {
 534       /* This insn has a 4-bit opcode.  */
 535       op &= 0x3c;
 536     }
 537   seg = VLE_OP_TO_SEG (op);
 538
 539   /* Find the first match in the opcode table for this major opcode.  */
 540   opcode_end = vle_opcodes + vle_opcd_indices[seg + 1];
 541   for (opcode = vle_opcodes + vle_opcd_indices[seg];
 542        opcode < opcode_end;
 543        ++opcode)
 544     {
 545       unsigned long table_opcd = opcode->opcode;
 546       unsigned long table_mask = opcode->mask;
 547       bfd_boolean table_op_is_short = PPC_OP_SE_VLE(table_mask);
 548       unsigned long insn2;
 549       const unsigned char *opindex;
 550       const struct powerpc_operand *operand;
 551       int invalid;
 552
 553       insn2 = insn;
 554       if (table_op_is_short)
 555         insn2 >>= 16;
 556       if ((insn2 & table_mask) != table_opcd)
 557         continue;
 558
 559       /* Check validity of operands.  */
 560       invalid = 0;
 561       for (opindex = opcode->operands; *opindex != 0; ++opindex)
 562         {
 563           operand = powerpc_operands + *opindex;
 564           if (operand->extract)
 565             (*operand->extract) (insn, (ppc_cpu_t)0, &invalid);
 566         }
 567       if (invalid)
 568         continue;
 569
 570       return opcode;
 571     }
 572
 573   return NULL;
 574 }
 575
 576 /* Print a PowerPC or POWER instruction.  */
 577
 578 static int
 579 print_insn_powerpc (bfd_vma memaddr,
 580                     struct disassemble_info *info,
 581                     int bigendian,
 582                     ppc_cpu_t dialect)
 583 {
 584   bfd_byte buffer[4];
 585   int status;
 586   unsigned long insn;
 587   const struct powerpc_opcode *opcode;
 588   bfd_boolean insn_is_short;
 589
 590   status = (*info->read_memory_func) (memaddr, buffer, 4, info);
 591   if (status != 0)
 592     {
 593       /* The final instruction may be a 2-byte VLE insn.  */
 594       if ((dialect & PPC_OPCODE_VLE) != 0)
 595         {
 596           /* Clear buffer so unused bytes will not have garbage in them.  */
 597           buffer[0] = buffer[1] = buffer[2] = buffer[3] = 0;
 598           status = (*info->read_memory_func) (memaddr, buffer, 2, info);
 599           if (status != 0)
 600             {
 601               (*info->memory_error_func) (status, memaddr, info);
 602               return -1;
 603             }
 604         }
 605       else
 606         {
 607           (*info->memory_error_func) (status, memaddr, info);
 608           return -1;
 609         }
 610     }
 611
 612   if (bigendian)
 613     insn = bfd_getb32 (buffer);
 614   else
 615     insn = bfd_getl32 (buffer);
 616
 617   /* Get the major opcode of the insn.  */
 618   opcode = NULL;
 619   insn_is_short = FALSE;
 620   if ((dialect & PPC_OPCODE_VLE) != 0)
 621     {
 622       opcode = lookup_vle (insn);
 623       if (opcode != NULL)
 624         insn_is_short = PPC_OP_SE_VLE(opcode->mask);
 625     }
 626   if (opcode == NULL)
 627     opcode = lookup_powerpc (insn, dialect);
 628   if (opcode == NULL && (dialect & PPC_OPCODE_ANY) != 0)
 629     opcode = lookup_powerpc (insn, (ppc_cpu_t) -1);
 630
 631   if (opcode != NULL)
 632     {
 633       const unsigned char *opindex;
 634       const struct powerpc_operand *operand;
 635       int need_comma;
 636       int need_paren;
 637       int skip_optional;
 638
 639       if (opcode->operands[0] != 0)
 640         (*info->fprintf_func) (info->stream, "%-7s ", opcode->name);
 641       else
 642         (*info->fprintf_func) (info->stream, "%s", opcode->name);
 643
 644       if (insn_is_short)
 645         /* The operands will be fetched out of the 16-bit instruction.  */
 646         insn >>= 16;
 647
 648       /* Now extract and print the operands.  */
 649       need_comma = 0;
 650       need_paren = 0;
 651       skip_optional = -1;
 652       for (opindex = opcode->operands; *opindex != 0; opindex++)
 653         {
 654           long value;
 655
 656           operand = powerpc_operands + *opindex;
 657
 658           /* Operands that are marked FAKE are simply ignored.  We
 659              already made sure that the extract function considered
 660              the instruction to be valid.  */
 661           if ((operand->flags & PPC_OPERAND_FAKE) != 0)
 662             continue;
 663
 664           /* If all of the optional operands have the value zero,
 665              then don't print any of them.  */
 666           if ((operand->flags & PPC_OPERAND_OPTIONAL) != 0)
 667             {
 668               if (skip_optional < 0)
 669                 skip_optional = skip_optional_operands (opindex, insn,
 670                                                         dialect);
 671               if (skip_optional)
 672                 continue;
 673             }
 674
 675           value = operand_value_powerpc (operand, insn, dialect);
 676
 677           if (need_comma)
 678             {
 679               (*info->fprintf_func) (info->stream, ",");
 680               need_comma = 0;
 681             }
 682
 683           /* Print the operand as directed by the flags.  */
 684           if ((operand->flags & PPC_OPERAND_GPR) != 0
 685               || ((operand->flags & PPC_OPERAND_GPR_0) != 0 && value != 0))
 686             (*info->fprintf_func) (info->stream, "r%ld", value);
 687           else if ((operand->flags & PPC_OPERAND_FPR) != 0)
 688             (*info->fprintf_func) (info->stream, "f%ld", value);
 689           else if ((operand->flags & PPC_OPERAND_VR) != 0)
 690             (*info->fprintf_func) (info->stream, "v%ld", value);
 691           else if ((operand->flags & PPC_OPERAND_VSR) != 0)
 692             (*info->fprintf_func) (info->stream, "vs%ld", value);
 693           else if ((operand->flags & PPC_OPERAND_RELATIVE) != 0)
 694             (*info->print_address_func) (memaddr + value, info);
 695           else if ((operand->flags & PPC_OPERAND_ABSOLUTE) != 0)
 696             (*info->print_address_func) ((bfd_vma) value & 0xffffffff, info);
 697           else if ((operand->flags & PPC_OPERAND_FSL) != 0)
 698             (*info->fprintf_func) (info->stream, "fsl%ld", value);
 699           else if ((operand->flags & PPC_OPERAND_FCR) != 0)
 700             (*info->fprintf_func) (info->stream, "fcr%ld", value);
 701           else if ((operand->flags & PPC_OPERAND_UDI) != 0)
 702             (*info->fprintf_func) (info->stream, "%ld", value);
 703           else if ((operand->flags & PPC_OPERAND_CR_REG) != 0
 704                    && (((dialect & PPC_OPCODE_PPC) != 0)
 705                        || ((dialect & PPC_OPCODE_VLE) != 0)))
 706             (*info->fprintf_func) (info->stream, "cr%ld", value);
 707           else if (((operand->flags & PPC_OPERAND_CR_BIT) != 0)
 708                    && (((dialect & PPC_OPCODE_PPC) != 0)
 709                        || ((dialect & PPC_OPCODE_VLE) != 0)))
 710             {
 711               static const char *cbnames[4] = { "lt", "gt", "eq", "so" };
 712               int cr;
 713               int cc;
 714
 715               cr = value >> 2;
 716               if (cr != 0)
 717                 (*info->fprintf_func) (info->stream, "4*cr%d+", cr);
 718               cc = value & 3;
 719               (*info->fprintf_func) (info->stream, "%s", cbnames[cc]);
 720             }
 721           else
 722             (*info->fprintf_func) (info->stream, "%d", (int) value);
 723
 724           if (need_paren)
 725             {
 726               (*info->fprintf_func) (info->stream, ")");
 727               need_paren = 0;
 728             }
 729
 730           if ((operand->flags & PPC_OPERAND_PARENS) == 0)
 731             need_comma = 1;
 732           else
 733             {
 734               (*info->fprintf_func) (info->stream, "(");
 735               need_paren = 1;
 736             }
 737         }
 738
 739       /* We have found and printed an instruction.
 740          If it was a short VLE instruction we have more to do.  */
 741       if (insn_is_short)
 742         {
 743           memaddr += 2;
 744           return 2;
 745         }
 746       else
 747         /* Otherwise, return.  */
 748         return 4;
 749     }
 750
 751   /* We could not find a match.  */
 752   (*info->fprintf_func) (info->stream, ".long 0x%lx", insn);
 753
 754   return 4;
 755 }
 756
 757 void
 758 print_ppc_disassembler_options (FILE *stream)
 759 {
 760   unsigned int i, col;
 761
 762   fprintf (stream, _("\n\
 763 The following PPC specific disassembler options are supported for use with\n\
 764 the -M switch:\n"));
 765
 766   for (col = 0, i = 0; i < sizeof (ppc_opts) / sizeof (ppc_opts[0]); i++)
 767     {
 768       col += fprintf (stream, " %s,", ppc_opts[i].opt);
 769       if (col > 66)
 770         {
 771           fprintf (stream, "\n");
 772           col = 0;
 773         }
 774     }
 775   fprintf (stream, " 32, 64\n");
 776 }