1 /* ppc-dis.c -- Disassemble PowerPC instructions
2 Copyright 1994, 1995, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007,
3 2008, 2009, 2010, 2011, 2012 Free Software Foundation, Inc.
4 Written by Ian Lance Taylor, Cygnus Support
6 This file is part of the GNU opcodes library.
8 This library is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3, or (at your option)
13 It is distributed in the hope that it will be useful, but WITHOUT
14 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
15 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
16 License for more details.
18 You should have received a copy of the GNU General Public License
19 along with this file; see the file COPYING. If not, write to the
20 Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston,
21 MA 02110-1301, USA. */
29 #include "opcode/ppc.h"
31 /* This file provides several disassembler functions, all of which use
32 the disassembler interface defined in dis-asm.h. Several functions
33 are provided because this file handles disassembly for the PowerPC
34 in both big and little endian mode and also for the POWER (RS/6000)
36 static int print_insn_powerpc (bfd_vma
, struct disassemble_info
*, int,
41 /* Stash the result of parsing disassembler_options here. */
45 #define POWERPC_DIALECT(INFO) \
46 (((struct dis_private *) ((INFO)->private_data))->dialect)
54 struct ppc_mopt ppc_opts
[] = {
55 { "403", (PPC_OPCODE_PPC
| PPC_OPCODE_403
),
57 { "405", (PPC_OPCODE_PPC
| PPC_OPCODE_403
| PPC_OPCODE_405
),
59 { "440", (PPC_OPCODE_PPC
| PPC_OPCODE_BOOKE
| PPC_OPCODE_440
60 | PPC_OPCODE_ISEL
| PPC_OPCODE_RFMCI
),
62 { "464", (PPC_OPCODE_PPC
| PPC_OPCODE_BOOKE
| PPC_OPCODE_440
63 | PPC_OPCODE_ISEL
| PPC_OPCODE_RFMCI
),
65 { "476", (PPC_OPCODE_PPC
| PPC_OPCODE_ISEL
| PPC_OPCODE_440
66 | PPC_OPCODE_476
| PPC_OPCODE_POWER4
| PPC_OPCODE_POWER5
),
68 { "601", (PPC_OPCODE_PPC
| PPC_OPCODE_601
),
70 { "603", (PPC_OPCODE_PPC
),
72 { "604", (PPC_OPCODE_PPC
),
74 { "620", (PPC_OPCODE_PPC
| PPC_OPCODE_64
),
76 { "7400", (PPC_OPCODE_PPC
| PPC_OPCODE_ALTIVEC
),
78 { "7410", (PPC_OPCODE_PPC
| PPC_OPCODE_ALTIVEC
),
80 { "7450", (PPC_OPCODE_PPC
| PPC_OPCODE_ALTIVEC
),
82 { "7455", (PPC_OPCODE_PPC
| PPC_OPCODE_ALTIVEC
),
84 { "750cl", (PPC_OPCODE_PPC
| PPC_OPCODE_PPCPS
)
86 { "a2", (PPC_OPCODE_PPC
| PPC_OPCODE_ISEL
| PPC_OPCODE_POWER4
87 | PPC_OPCODE_POWER5
| PPC_OPCODE_CACHELCK
| PPC_OPCODE_64
90 { "altivec", (PPC_OPCODE_PPC
),
91 PPC_OPCODE_ALTIVEC
| PPC_OPCODE_ALTIVEC2
},
94 { "booke", (PPC_OPCODE_PPC
| PPC_OPCODE_BOOKE
),
96 { "booke32", (PPC_OPCODE_PPC
| PPC_OPCODE_BOOKE
),
98 { "cell", (PPC_OPCODE_PPC
| PPC_OPCODE_64
| PPC_OPCODE_POWER4
99 | PPC_OPCODE_CELL
| PPC_OPCODE_ALTIVEC
),
101 { "com", (PPC_OPCODE_COMMON
),
103 { "e300", (PPC_OPCODE_PPC
| PPC_OPCODE_E300
),
105 { "e500", (PPC_OPCODE_PPC
| PPC_OPCODE_BOOKE
| PPC_OPCODE_SPE
106 | PPC_OPCODE_ISEL
| PPC_OPCODE_EFS
| PPC_OPCODE_BRLOCK
107 | PPC_OPCODE_PMR
| PPC_OPCODE_CACHELCK
| PPC_OPCODE_RFMCI
110 { "e500mc", (PPC_OPCODE_PPC
| PPC_OPCODE_BOOKE
| PPC_OPCODE_ISEL
111 | PPC_OPCODE_PMR
| PPC_OPCODE_CACHELCK
| PPC_OPCODE_RFMCI
112 | PPC_OPCODE_E500MC
),
114 { "e500mc64", (PPC_OPCODE_PPC
| PPC_OPCODE_BOOKE
| PPC_OPCODE_ISEL
115 | PPC_OPCODE_PMR
| PPC_OPCODE_CACHELCK
| PPC_OPCODE_RFMCI
116 | PPC_OPCODE_E500MC
| PPC_OPCODE_64
| PPC_OPCODE_POWER5
117 | PPC_OPCODE_POWER6
| PPC_OPCODE_POWER7
),
119 { "e5500", (PPC_OPCODE_PPC
| PPC_OPCODE_BOOKE
| PPC_OPCODE_ISEL
120 | PPC_OPCODE_PMR
| PPC_OPCODE_CACHELCK
| PPC_OPCODE_RFMCI
121 | PPC_OPCODE_E500MC
| PPC_OPCODE_64
| PPC_OPCODE_POWER4
122 | PPC_OPCODE_POWER5
| PPC_OPCODE_POWER6
123 | PPC_OPCODE_POWER7
),
125 { "e6500", (PPC_OPCODE_PPC
| PPC_OPCODE_BOOKE
| PPC_OPCODE_ISEL
126 | PPC_OPCODE_PMR
| PPC_OPCODE_CACHELCK
| PPC_OPCODE_RFMCI
127 | PPC_OPCODE_E500MC
| PPC_OPCODE_64
| PPC_OPCODE_ALTIVEC
128 | PPC_OPCODE_ALTIVEC2
| PPC_OPCODE_E6500
| PPC_OPCODE_POWER4
129 | PPC_OPCODE_POWER5
| PPC_OPCODE_POWER6
| PPC_OPCODE_POWER7
),
131 { "e500x2", (PPC_OPCODE_PPC
| PPC_OPCODE_BOOKE
| PPC_OPCODE_SPE
132 | PPC_OPCODE_ISEL
| PPC_OPCODE_EFS
| PPC_OPCODE_BRLOCK
133 | PPC_OPCODE_PMR
| PPC_OPCODE_CACHELCK
| PPC_OPCODE_RFMCI
136 { "efs", (PPC_OPCODE_PPC
| PPC_OPCODE_EFS
),
138 { "power4", (PPC_OPCODE_PPC
| PPC_OPCODE_64
| PPC_OPCODE_POWER4
),
140 { "power5", (PPC_OPCODE_PPC
| PPC_OPCODE_64
| PPC_OPCODE_POWER4
141 | PPC_OPCODE_POWER5
),
143 { "power6", (PPC_OPCODE_PPC
| PPC_OPCODE_64
| PPC_OPCODE_POWER4
144 | PPC_OPCODE_POWER5
| PPC_OPCODE_POWER6
| PPC_OPCODE_ALTIVEC
),
146 { "power7", (PPC_OPCODE_PPC
| PPC_OPCODE_ISEL
| PPC_OPCODE_64
147 | PPC_OPCODE_POWER4
| PPC_OPCODE_POWER5
| PPC_OPCODE_POWER6
148 | PPC_OPCODE_POWER7
| PPC_OPCODE_ALTIVEC
| PPC_OPCODE_VSX
),
150 { "power8", (PPC_OPCODE_PPC
| PPC_OPCODE_ISEL
| PPC_OPCODE_64
151 | PPC_OPCODE_POWER4
| PPC_OPCODE_POWER5
| PPC_OPCODE_POWER6
152 | PPC_OPCODE_POWER7
| PPC_OPCODE_POWER8
| PPC_OPCODE_HTM
153 | PPC_OPCODE_ALTIVEC
| PPC_OPCODE_ALTIVEC2
| PPC_OPCODE_VSX
),
155 { "ppc", (PPC_OPCODE_PPC
),
157 { "ppc32", (PPC_OPCODE_PPC
),
159 { "ppc64", (PPC_OPCODE_PPC
| PPC_OPCODE_64
),
161 { "ppc64bridge", (PPC_OPCODE_PPC
| PPC_OPCODE_64_BRIDGE
),
163 { "ppcps", (PPC_OPCODE_PPC
| PPC_OPCODE_PPCPS
),
165 { "pwr", (PPC_OPCODE_POWER
),
167 { "pwr2", (PPC_OPCODE_POWER
| PPC_OPCODE_POWER2
),
169 { "pwr4", (PPC_OPCODE_PPC
| PPC_OPCODE_64
| PPC_OPCODE_POWER4
),
171 { "pwr5", (PPC_OPCODE_PPC
| PPC_OPCODE_64
| PPC_OPCODE_POWER4
172 | PPC_OPCODE_POWER5
),
174 { "pwr5x", (PPC_OPCODE_PPC
| PPC_OPCODE_64
| PPC_OPCODE_POWER4
175 | PPC_OPCODE_POWER5
),
177 { "pwr6", (PPC_OPCODE_PPC
| PPC_OPCODE_64
| PPC_OPCODE_POWER4
178 | PPC_OPCODE_POWER5
| PPC_OPCODE_POWER6
| PPC_OPCODE_ALTIVEC
),
180 { "pwr7", (PPC_OPCODE_PPC
| PPC_OPCODE_ISEL
| PPC_OPCODE_64
181 | PPC_OPCODE_POWER4
| PPC_OPCODE_POWER5
| PPC_OPCODE_POWER6
182 | PPC_OPCODE_POWER7
| PPC_OPCODE_ALTIVEC
| PPC_OPCODE_VSX
),
184 { "pwr8", (PPC_OPCODE_PPC
| PPC_OPCODE_ISEL
| PPC_OPCODE_64
185 | PPC_OPCODE_POWER4
| PPC_OPCODE_POWER5
| PPC_OPCODE_POWER6
186 | PPC_OPCODE_POWER7
| PPC_OPCODE_POWER8
| PPC_OPCODE_HTM
187 | PPC_OPCODE_ALTIVEC
| PPC_OPCODE_ALTIVEC2
| PPC_OPCODE_VSX
),
189 { "pwrx", (PPC_OPCODE_POWER
| PPC_OPCODE_POWER2
),
191 { "spe", (PPC_OPCODE_PPC
| PPC_OPCODE_EFS
),
193 { "titan", (PPC_OPCODE_PPC
| PPC_OPCODE_BOOKE
| PPC_OPCODE_PMR
194 | PPC_OPCODE_RFMCI
| PPC_OPCODE_TITAN
),
196 { "vle", (PPC_OPCODE_PPC
| PPC_OPCODE_ISEL
| PPC_OPCODE_VLE
),
198 { "vsx", (PPC_OPCODE_PPC
),
200 { "htm", (PPC_OPCODE_PPC
),
204 /* Switch between Booke and VLE dialects for interlinked dumps. */
206 get_powerpc_dialect (struct disassemble_info
*info
)
208 ppc_cpu_t dialect
= 0;
210 dialect
= POWERPC_DIALECT (info
);
212 /* Disassemble according to the section headers flags for VLE-mode. */
213 if (dialect
& PPC_OPCODE_VLE
214 && info
->section
->owner
!= NULL
215 && bfd_get_flavour (info
->section
->owner
) == bfd_target_elf_flavour
216 && elf_object_id (info
->section
->owner
) == PPC32_ELF_DATA
217 && (elf_section_flags (info
->section
) & SHF_PPC_VLE
) != 0)
220 return dialect
& ~ PPC_OPCODE_VLE
;
223 /* Handle -m and -M options that set cpu type, and .machine arg. */
226 ppc_parse_cpu (ppc_cpu_t ppc_cpu
, ppc_cpu_t
*sticky
, const char *arg
)
230 for (i
= 0; i
< sizeof (ppc_opts
) / sizeof (ppc_opts
[0]); i
++)
231 if (strcmp (ppc_opts
[i
].opt
, arg
) == 0)
233 if (ppc_opts
[i
].sticky
)
235 *sticky
|= ppc_opts
[i
].sticky
;
236 if ((ppc_cpu
& ~*sticky
) != 0)
239 ppc_cpu
= ppc_opts
[i
].cpu
;
242 if (i
>= sizeof (ppc_opts
) / sizeof (ppc_opts
[0]))
249 /* Determine which set of machines to disassemble for. */
252 powerpc_init_dialect (struct disassemble_info
*info
)
254 ppc_cpu_t dialect
= 0;
255 ppc_cpu_t sticky
= 0;
257 struct dis_private
*priv
= calloc (sizeof (*priv
), 1);
264 case bfd_mach_ppc_403
:
265 case bfd_mach_ppc_403gc
:
266 dialect
= (PPC_OPCODE_PPC
| PPC_OPCODE_403
);
268 case bfd_mach_ppc_405
:
269 dialect
= (PPC_OPCODE_PPC
| PPC_OPCODE_403
| PPC_OPCODE_405
);
271 case bfd_mach_ppc_601
:
272 dialect
= (PPC_OPCODE_PPC
| PPC_OPCODE_601
);
274 case bfd_mach_ppc_a35
:
275 case bfd_mach_ppc_rs64ii
:
276 case bfd_mach_ppc_rs64iii
:
277 dialect
= (PPC_OPCODE_POWER
| PPC_OPCODE_POWER2
| PPC_OPCODE_64
);
279 case bfd_mach_ppc_e500
:
280 dialect
= (PPC_OPCODE_PPC
| PPC_OPCODE_BOOKE
| PPC_OPCODE_SPE
281 | PPC_OPCODE_ISEL
| PPC_OPCODE_EFS
| PPC_OPCODE_BRLOCK
282 | PPC_OPCODE_PMR
| PPC_OPCODE_CACHELCK
| PPC_OPCODE_RFMCI
285 case bfd_mach_ppc_e500mc
:
286 dialect
= (PPC_OPCODE_PPC
| PPC_OPCODE_BOOKE
| PPC_OPCODE_ISEL
287 | PPC_OPCODE_PMR
| PPC_OPCODE_CACHELCK
| PPC_OPCODE_RFMCI
288 | PPC_OPCODE_E500MC
);
290 case bfd_mach_ppc_e500mc64
:
291 dialect
= (PPC_OPCODE_PPC
| PPC_OPCODE_BOOKE
| PPC_OPCODE_ISEL
292 | PPC_OPCODE_PMR
| PPC_OPCODE_CACHELCK
| PPC_OPCODE_RFMCI
293 | PPC_OPCODE_E500MC
| PPC_OPCODE_64
| PPC_OPCODE_POWER5
294 | PPC_OPCODE_POWER6
| PPC_OPCODE_POWER7
);
296 case bfd_mach_ppc_e5500
:
297 dialect
= (PPC_OPCODE_PPC
| PPC_OPCODE_BOOKE
| PPC_OPCODE_ISEL
298 | PPC_OPCODE_PMR
| PPC_OPCODE_CACHELCK
| PPC_OPCODE_RFMCI
299 | PPC_OPCODE_E500MC
| PPC_OPCODE_64
| PPC_OPCODE_POWER4
300 | PPC_OPCODE_POWER5
| PPC_OPCODE_POWER6
301 | PPC_OPCODE_POWER7
);
303 case bfd_mach_ppc_e6500
:
304 dialect
= (PPC_OPCODE_PPC
| PPC_OPCODE_BOOKE
| PPC_OPCODE_ISEL
305 | PPC_OPCODE_PMR
| PPC_OPCODE_CACHELCK
| PPC_OPCODE_RFMCI
306 | PPC_OPCODE_E500MC
| PPC_OPCODE_64
| PPC_OPCODE_ALTIVEC
307 | PPC_OPCODE_ALTIVEC2
| PPC_OPCODE_E6500
| PPC_OPCODE_POWER4
308 | PPC_OPCODE_POWER5
| PPC_OPCODE_POWER6
| PPC_OPCODE_POWER7
);
310 case bfd_mach_ppc_titan
:
311 dialect
= (PPC_OPCODE_PPC
| PPC_OPCODE_BOOKE
| PPC_OPCODE_PMR
312 | PPC_OPCODE_RFMCI
| PPC_OPCODE_TITAN
);
314 case bfd_mach_ppc_vle
:
315 dialect
= (PPC_OPCODE_PPC
| PPC_OPCODE_ISEL
| PPC_OPCODE_VLE
);
318 dialect
= ppc_parse_cpu (dialect
, &sticky
, "power8") | PPC_OPCODE_ANY
;
321 arg
= info
->disassembler_options
;
324 ppc_cpu_t new_cpu
= 0;
325 char *end
= strchr (arg
, ',');
330 if ((new_cpu
= ppc_parse_cpu (dialect
, &sticky
, arg
)) != 0)
332 else if (strcmp (arg
, "32") == 0)
333 dialect
&= ~(ppc_cpu_t
) PPC_OPCODE_64
;
334 else if (strcmp (arg
, "64") == 0)
335 dialect
|= PPC_OPCODE_64
;
337 fprintf (stderr
, _("warning: ignoring unknown -M%s option\n"), arg
);
344 info
->private_data
= priv
;
345 POWERPC_DIALECT(info
) = dialect
;
348 #define PPC_OPCD_SEGS 64
349 static unsigned short powerpc_opcd_indices
[PPC_OPCD_SEGS
+1];
350 #define VLE_OPCD_SEGS 32
351 static unsigned short vle_opcd_indices
[VLE_OPCD_SEGS
+1];
353 /* Calculate opcode table indices to speed up disassembly,
357 disassemble_init_powerpc (struct disassemble_info
*info
)
362 i
= powerpc_num_opcodes
;
365 unsigned op
= PPC_OP (powerpc_opcodes
[i
].opcode
);
367 powerpc_opcd_indices
[op
] = i
;
370 last
= powerpc_num_opcodes
;
371 for (i
= PPC_OPCD_SEGS
; i
> 0; --i
)
373 if (powerpc_opcd_indices
[i
] == 0)
374 powerpc_opcd_indices
[i
] = last
;
375 last
= powerpc_opcd_indices
[i
];
381 unsigned op
= VLE_OP (vle_opcodes
[i
].opcode
, vle_opcodes
[i
].mask
);
382 unsigned seg
= VLE_OP_TO_SEG (op
);
384 vle_opcd_indices
[seg
] = i
;
387 last
= vle_num_opcodes
;
388 for (i
= VLE_OPCD_SEGS
; i
> 0; --i
)
390 if (vle_opcd_indices
[i
] == 0)
391 vle_opcd_indices
[i
] = last
;
392 last
= vle_opcd_indices
[i
];
395 if (info
->arch
== bfd_arch_powerpc
)
396 powerpc_init_dialect (info
);
399 /* Print a big endian PowerPC instruction. */
402 print_insn_big_powerpc (bfd_vma memaddr
, struct disassemble_info
*info
)
404 return print_insn_powerpc (memaddr
, info
, 1, get_powerpc_dialect (info
));
407 /* Print a little endian PowerPC instruction. */
410 print_insn_little_powerpc (bfd_vma memaddr
, struct disassemble_info
*info
)
412 return print_insn_powerpc (memaddr
, info
, 0, get_powerpc_dialect (info
));
415 /* Print a POWER (RS/6000) instruction. */
418 print_insn_rs6000 (bfd_vma memaddr
, struct disassemble_info
*info
)
420 return print_insn_powerpc (memaddr
, info
, 1, PPC_OPCODE_POWER
);
423 /* Extract the operand value from the PowerPC or POWER instruction. */
426 operand_value_powerpc (const struct powerpc_operand
*operand
,
427 unsigned long insn
, ppc_cpu_t dialect
)
431 /* Extract the value from the instruction. */
432 if (operand
->extract
)
433 value
= (*operand
->extract
) (insn
, dialect
, &invalid
);
436 if (operand
->shift
>= 0)
437 value
= (insn
>> operand
->shift
) & operand
->bitm
;
439 value
= (insn
<< -operand
->shift
) & operand
->bitm
;
440 if ((operand
->flags
& PPC_OPERAND_SIGNED
) != 0)
442 /* BITM is always some number of zeros followed by some
443 number of ones, followed by some number of zeros. */
444 unsigned long top
= operand
->bitm
;
445 /* top & -top gives the rightmost 1 bit, so this
446 fills in any trailing zeros. */
447 top
|= (top
& -top
) - 1;
449 value
= (value
^ top
) - top
;
456 /* Determine whether the optional operand(s) should be printed. */
459 skip_optional_operands (const unsigned char *opindex
,
460 unsigned long insn
, ppc_cpu_t dialect
)
462 const struct powerpc_operand
*operand
;
464 for (; *opindex
!= 0; opindex
++)
466 operand
= &powerpc_operands
[*opindex
];
467 if ((operand
->flags
& PPC_OPERAND_NEXT
) != 0
468 || ((operand
->flags
& PPC_OPERAND_OPTIONAL
) != 0
469 && operand_value_powerpc (operand
, insn
, dialect
) != 0))
476 /* Find a match for INSN in the opcode table, given machine DIALECT.
477 A DIALECT of -1 is special, matching all machine opcode variations. */
479 static const struct powerpc_opcode
*
480 lookup_powerpc (unsigned long insn
, ppc_cpu_t dialect
)
482 const struct powerpc_opcode
*opcode
;
483 const struct powerpc_opcode
*opcode_end
;
486 /* Get the major opcode of the instruction. */
489 /* Find the first match in the opcode table for this major opcode. */
490 opcode_end
= powerpc_opcodes
+ powerpc_opcd_indices
[op
+ 1];
491 for (opcode
= powerpc_opcodes
+ powerpc_opcd_indices
[op
];
495 const unsigned char *opindex
;
496 const struct powerpc_operand
*operand
;
499 if ((insn
& opcode
->mask
) != opcode
->opcode
500 || (dialect
!= (ppc_cpu_t
) -1
501 && ((opcode
->flags
& dialect
) == 0
502 || (opcode
->deprecated
& dialect
) != 0)))
505 /* Check validity of operands. */
507 for (opindex
= opcode
->operands
; *opindex
!= 0; opindex
++)
509 operand
= powerpc_operands
+ *opindex
;
510 if (operand
->extract
)
511 (*operand
->extract
) (insn
, dialect
, &invalid
);
522 /* Find a match for INSN in the VLE opcode table. */
524 static const struct powerpc_opcode
*
525 lookup_vle (unsigned long insn
)
527 const struct powerpc_opcode
*opcode
;
528 const struct powerpc_opcode
*opcode_end
;
532 if (op
>= 0x20 && op
<= 0x37)
534 /* This insn has a 4-bit opcode. */
537 seg
= VLE_OP_TO_SEG (op
);
539 /* Find the first match in the opcode table for this major opcode. */
540 opcode_end
= vle_opcodes
+ vle_opcd_indices
[seg
+ 1];
541 for (opcode
= vle_opcodes
+ vle_opcd_indices
[seg
];
545 unsigned long table_opcd
= opcode
->opcode
;
546 unsigned long table_mask
= opcode
->mask
;
547 bfd_boolean table_op_is_short
= PPC_OP_SE_VLE(table_mask
);
549 const unsigned char *opindex
;
550 const struct powerpc_operand
*operand
;
554 if (table_op_is_short
)
556 if ((insn2
& table_mask
) != table_opcd
)
559 /* Check validity of operands. */
561 for (opindex
= opcode
->operands
; *opindex
!= 0; ++opindex
)
563 operand
= powerpc_operands
+ *opindex
;
564 if (operand
->extract
)
565 (*operand
->extract
) (insn
, (ppc_cpu_t
)0, &invalid
);
576 /* Print a PowerPC or POWER instruction. */
579 print_insn_powerpc (bfd_vma memaddr
,
580 struct disassemble_info
*info
,
587 const struct powerpc_opcode
*opcode
;
588 bfd_boolean insn_is_short
;
590 status
= (*info
->read_memory_func
) (memaddr
, buffer
, 4, info
);
593 /* The final instruction may be a 2-byte VLE insn. */
594 if ((dialect
& PPC_OPCODE_VLE
) != 0)
596 /* Clear buffer so unused bytes will not have garbage in them. */
597 buffer
[0] = buffer
[1] = buffer
[2] = buffer
[3] = 0;
598 status
= (*info
->read_memory_func
) (memaddr
, buffer
, 2, info
);
601 (*info
->memory_error_func
) (status
, memaddr
, info
);
607 (*info
->memory_error_func
) (status
, memaddr
, info
);
613 insn
= bfd_getb32 (buffer
);
615 insn
= bfd_getl32 (buffer
);
617 /* Get the major opcode of the insn. */
619 insn_is_short
= FALSE
;
620 if ((dialect
& PPC_OPCODE_VLE
) != 0)
622 opcode
= lookup_vle (insn
);
624 insn_is_short
= PPC_OP_SE_VLE(opcode
->mask
);
627 opcode
= lookup_powerpc (insn
, dialect
);
628 if (opcode
== NULL
&& (dialect
& PPC_OPCODE_ANY
) != 0)
629 opcode
= lookup_powerpc (insn
, (ppc_cpu_t
) -1);
633 const unsigned char *opindex
;
634 const struct powerpc_operand
*operand
;
639 if (opcode
->operands
[0] != 0)
640 (*info
->fprintf_func
) (info
->stream
, "%-7s ", opcode
->name
);
642 (*info
->fprintf_func
) (info
->stream
, "%s", opcode
->name
);
645 /* The operands will be fetched out of the 16-bit instruction. */
648 /* Now extract and print the operands. */
652 for (opindex
= opcode
->operands
; *opindex
!= 0; opindex
++)
656 operand
= powerpc_operands
+ *opindex
;
658 /* Operands that are marked FAKE are simply ignored. We
659 already made sure that the extract function considered
660 the instruction to be valid. */
661 if ((operand
->flags
& PPC_OPERAND_FAKE
) != 0)
664 /* If all of the optional operands have the value zero,
665 then don't print any of them. */
666 if ((operand
->flags
& PPC_OPERAND_OPTIONAL
) != 0)
668 if (skip_optional
< 0)
669 skip_optional
= skip_optional_operands (opindex
, insn
,
675 value
= operand_value_powerpc (operand
, insn
, dialect
);
679 (*info
->fprintf_func
) (info
->stream
, ",");
683 /* Print the operand as directed by the flags. */
684 if ((operand
->flags
& PPC_OPERAND_GPR
) != 0
685 || ((operand
->flags
& PPC_OPERAND_GPR_0
) != 0 && value
!= 0))
686 (*info
->fprintf_func
) (info
->stream
, "r%ld", value
);
687 else if ((operand
->flags
& PPC_OPERAND_FPR
) != 0)
688 (*info
->fprintf_func
) (info
->stream
, "f%ld", value
);
689 else if ((operand
->flags
& PPC_OPERAND_VR
) != 0)
690 (*info
->fprintf_func
) (info
->stream
, "v%ld", value
);
691 else if ((operand
->flags
& PPC_OPERAND_VSR
) != 0)
692 (*info
->fprintf_func
) (info
->stream
, "vs%ld", value
);
693 else if ((operand
->flags
& PPC_OPERAND_RELATIVE
) != 0)
694 (*info
->print_address_func
) (memaddr
+ value
, info
);
695 else if ((operand
->flags
& PPC_OPERAND_ABSOLUTE
) != 0)
696 (*info
->print_address_func
) ((bfd_vma
) value
& 0xffffffff, info
);
697 else if ((operand
->flags
& PPC_OPERAND_FSL
) != 0)
698 (*info
->fprintf_func
) (info
->stream
, "fsl%ld", value
);
699 else if ((operand
->flags
& PPC_OPERAND_FCR
) != 0)
700 (*info
->fprintf_func
) (info
->stream
, "fcr%ld", value
);
701 else if ((operand
->flags
& PPC_OPERAND_UDI
) != 0)
702 (*info
->fprintf_func
) (info
->stream
, "%ld", value
);
703 else if ((operand
->flags
& PPC_OPERAND_CR_REG
) != 0
704 && (((dialect
& PPC_OPCODE_PPC
) != 0)
705 || ((dialect
& PPC_OPCODE_VLE
) != 0)))
706 (*info
->fprintf_func
) (info
->stream
, "cr%ld", value
);
707 else if (((operand
->flags
& PPC_OPERAND_CR_BIT
) != 0)
708 && (((dialect
& PPC_OPCODE_PPC
) != 0)
709 || ((dialect
& PPC_OPCODE_VLE
) != 0)))
711 static const char *cbnames
[4] = { "lt", "gt", "eq", "so" };
717 (*info
->fprintf_func
) (info
->stream
, "4*cr%d+", cr
);
719 (*info
->fprintf_func
) (info
->stream
, "%s", cbnames
[cc
]);
722 (*info
->fprintf_func
) (info
->stream
, "%d", (int) value
);
726 (*info
->fprintf_func
) (info
->stream
, ")");
730 if ((operand
->flags
& PPC_OPERAND_PARENS
) == 0)
734 (*info
->fprintf_func
) (info
->stream
, "(");
739 /* We have found and printed an instruction.
740 If it was a short VLE instruction we have more to do. */
747 /* Otherwise, return. */
751 /* We could not find a match. */
752 (*info
->fprintf_func
) (info
->stream
, ".long 0x%lx", insn
);
758 print_ppc_disassembler_options (FILE *stream
)
762 fprintf (stream
, _("\n\
763 The following PPC specific disassembler options are supported for use with\n\
766 for (col
= 0, i
= 0; i
< sizeof (ppc_opts
) / sizeof (ppc_opts
[0]); i
++)
768 col
+= fprintf (stream
, " %s,", ppc_opts
[i
].opt
);
771 fprintf (stream
, "\n");
775 fprintf (stream
, " 32, 64\n");