1 /* ppc-dis.c -- Disassemble PowerPC instructions
2 Copyright (C) 1994-2015 Free Software Foundation, Inc.
3 Written by Ian Lance Taylor, Cygnus Support
5 This file is part of the GNU opcodes library.
7 This library is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3, or (at your option)
12 It is distributed in the hope that it will be useful, but WITHOUT
13 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
14 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
15 License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this file; see the file COPYING. If not, write to the
19 Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston,
20 MA 02110-1301, USA. */
28 #include "opcode/ppc.h"
30 /* This file provides several disassembler functions, all of which use
31 the disassembler interface defined in dis-asm.h. Several functions
32 are provided because this file handles disassembly for the PowerPC
33 in both big and little endian mode and also for the POWER (RS/6000)
35 static int print_insn_powerpc (bfd_vma
, struct disassemble_info
*, int,
40 /* Stash the result of parsing disassembler_options here. */
44 #define POWERPC_DIALECT(INFO) \
45 (((struct dis_private *) ((INFO)->private_data))->dialect)
53 struct ppc_mopt ppc_opts
[] = {
54 { "403", (PPC_OPCODE_PPC
| PPC_OPCODE_403
),
56 { "405", (PPC_OPCODE_PPC
| PPC_OPCODE_403
| PPC_OPCODE_405
),
58 { "440", (PPC_OPCODE_PPC
| PPC_OPCODE_BOOKE
| PPC_OPCODE_440
59 | PPC_OPCODE_ISEL
| PPC_OPCODE_RFMCI
),
61 { "464", (PPC_OPCODE_PPC
| PPC_OPCODE_BOOKE
| PPC_OPCODE_440
62 | PPC_OPCODE_ISEL
| PPC_OPCODE_RFMCI
),
64 { "476", (PPC_OPCODE_PPC
| PPC_OPCODE_ISEL
| PPC_OPCODE_440
65 | PPC_OPCODE_476
| PPC_OPCODE_POWER4
| PPC_OPCODE_POWER5
),
67 { "601", (PPC_OPCODE_PPC
| PPC_OPCODE_601
),
69 { "603", (PPC_OPCODE_PPC
),
71 { "604", (PPC_OPCODE_PPC
),
73 { "620", (PPC_OPCODE_PPC
| PPC_OPCODE_64
),
75 { "7400", (PPC_OPCODE_PPC
| PPC_OPCODE_ALTIVEC
),
77 { "7410", (PPC_OPCODE_PPC
| PPC_OPCODE_ALTIVEC
),
79 { "7450", (PPC_OPCODE_PPC
| PPC_OPCODE_7450
| PPC_OPCODE_ALTIVEC
),
81 { "7455", (PPC_OPCODE_PPC
| PPC_OPCODE_ALTIVEC
),
83 { "750cl", (PPC_OPCODE_PPC
| PPC_OPCODE_750
| PPC_OPCODE_PPCPS
)
85 { "821", (PPC_OPCODE_PPC
| PPC_OPCODE_860
),
87 { "850", (PPC_OPCODE_PPC
| PPC_OPCODE_860
),
89 { "860", (PPC_OPCODE_PPC
| PPC_OPCODE_860
),
91 { "a2", (PPC_OPCODE_PPC
| PPC_OPCODE_ISEL
| PPC_OPCODE_POWER4
92 | PPC_OPCODE_POWER5
| PPC_OPCODE_CACHELCK
| PPC_OPCODE_64
95 { "altivec", (PPC_OPCODE_PPC
),
96 PPC_OPCODE_ALTIVEC
| PPC_OPCODE_ALTIVEC2
},
99 { "booke", (PPC_OPCODE_PPC
| PPC_OPCODE_BOOKE
),
101 { "booke32", (PPC_OPCODE_PPC
| PPC_OPCODE_BOOKE
),
103 { "cell", (PPC_OPCODE_PPC
| PPC_OPCODE_64
| PPC_OPCODE_POWER4
104 | PPC_OPCODE_CELL
| PPC_OPCODE_ALTIVEC
),
106 { "com", (PPC_OPCODE_COMMON
),
108 { "e300", (PPC_OPCODE_PPC
| PPC_OPCODE_E300
),
110 { "e500", (PPC_OPCODE_PPC
| PPC_OPCODE_BOOKE
| PPC_OPCODE_SPE
111 | PPC_OPCODE_ISEL
| PPC_OPCODE_EFS
| PPC_OPCODE_BRLOCK
112 | PPC_OPCODE_PMR
| PPC_OPCODE_CACHELCK
| PPC_OPCODE_RFMCI
115 { "e500mc", (PPC_OPCODE_PPC
| PPC_OPCODE_BOOKE
| PPC_OPCODE_ISEL
116 | PPC_OPCODE_PMR
| PPC_OPCODE_CACHELCK
| PPC_OPCODE_RFMCI
117 | PPC_OPCODE_E500MC
),
119 { "e500mc64", (PPC_OPCODE_PPC
| PPC_OPCODE_BOOKE
| PPC_OPCODE_ISEL
120 | PPC_OPCODE_PMR
| PPC_OPCODE_CACHELCK
| PPC_OPCODE_RFMCI
121 | PPC_OPCODE_E500MC
| PPC_OPCODE_64
| PPC_OPCODE_POWER5
122 | PPC_OPCODE_POWER6
| PPC_OPCODE_POWER7
),
124 { "e5500", (PPC_OPCODE_PPC
| PPC_OPCODE_BOOKE
| PPC_OPCODE_ISEL
125 | PPC_OPCODE_PMR
| PPC_OPCODE_CACHELCK
| PPC_OPCODE_RFMCI
126 | PPC_OPCODE_E500MC
| PPC_OPCODE_64
| PPC_OPCODE_POWER4
127 | PPC_OPCODE_POWER5
| PPC_OPCODE_POWER6
128 | PPC_OPCODE_POWER7
),
130 { "e6500", (PPC_OPCODE_PPC
| PPC_OPCODE_BOOKE
| PPC_OPCODE_ISEL
131 | PPC_OPCODE_PMR
| PPC_OPCODE_CACHELCK
| PPC_OPCODE_RFMCI
132 | PPC_OPCODE_E500MC
| PPC_OPCODE_64
| PPC_OPCODE_ALTIVEC
133 | PPC_OPCODE_ALTIVEC2
| PPC_OPCODE_E6500
| PPC_OPCODE_POWER4
134 | PPC_OPCODE_POWER5
| PPC_OPCODE_POWER6
| PPC_OPCODE_POWER7
),
136 { "e500x2", (PPC_OPCODE_PPC
| PPC_OPCODE_BOOKE
| PPC_OPCODE_SPE
137 | PPC_OPCODE_ISEL
| PPC_OPCODE_EFS
| PPC_OPCODE_BRLOCK
138 | PPC_OPCODE_PMR
| PPC_OPCODE_CACHELCK
| PPC_OPCODE_RFMCI
141 { "efs", (PPC_OPCODE_PPC
| PPC_OPCODE_EFS
),
143 { "power4", (PPC_OPCODE_PPC
| PPC_OPCODE_64
| PPC_OPCODE_POWER4
),
145 { "power5", (PPC_OPCODE_PPC
| PPC_OPCODE_64
| PPC_OPCODE_POWER4
146 | PPC_OPCODE_POWER5
),
148 { "power6", (PPC_OPCODE_PPC
| PPC_OPCODE_64
| PPC_OPCODE_POWER4
149 | PPC_OPCODE_POWER5
| PPC_OPCODE_POWER6
| PPC_OPCODE_ALTIVEC
),
151 { "power7", (PPC_OPCODE_PPC
| PPC_OPCODE_ISEL
| PPC_OPCODE_64
152 | PPC_OPCODE_POWER4
| PPC_OPCODE_POWER5
| PPC_OPCODE_POWER6
153 | PPC_OPCODE_POWER7
| PPC_OPCODE_ALTIVEC
| PPC_OPCODE_VSX
),
155 { "power8", (PPC_OPCODE_PPC
| PPC_OPCODE_ISEL
| PPC_OPCODE_64
156 | PPC_OPCODE_POWER4
| PPC_OPCODE_POWER5
| PPC_OPCODE_POWER6
157 | PPC_OPCODE_POWER7
| PPC_OPCODE_POWER8
| PPC_OPCODE_HTM
158 | PPC_OPCODE_ALTIVEC
| PPC_OPCODE_ALTIVEC2
| PPC_OPCODE_VSX
),
160 { "ppc", (PPC_OPCODE_PPC
),
162 { "ppc32", (PPC_OPCODE_PPC
),
164 { "ppc64", (PPC_OPCODE_PPC
| PPC_OPCODE_64
),
166 { "ppc64bridge", (PPC_OPCODE_PPC
| PPC_OPCODE_64_BRIDGE
),
168 { "ppcps", (PPC_OPCODE_PPC
| PPC_OPCODE_PPCPS
),
170 { "pwr", (PPC_OPCODE_POWER
),
172 { "pwr2", (PPC_OPCODE_POWER
| PPC_OPCODE_POWER2
),
174 { "pwr4", (PPC_OPCODE_PPC
| PPC_OPCODE_64
| PPC_OPCODE_POWER4
),
176 { "pwr5", (PPC_OPCODE_PPC
| PPC_OPCODE_64
| PPC_OPCODE_POWER4
177 | PPC_OPCODE_POWER5
),
179 { "pwr5x", (PPC_OPCODE_PPC
| PPC_OPCODE_64
| PPC_OPCODE_POWER4
180 | PPC_OPCODE_POWER5
),
182 { "pwr6", (PPC_OPCODE_PPC
| PPC_OPCODE_64
| PPC_OPCODE_POWER4
183 | PPC_OPCODE_POWER5
| PPC_OPCODE_POWER6
| PPC_OPCODE_ALTIVEC
),
185 { "pwr7", (PPC_OPCODE_PPC
| PPC_OPCODE_ISEL
| PPC_OPCODE_64
186 | PPC_OPCODE_POWER4
| PPC_OPCODE_POWER5
| PPC_OPCODE_POWER6
187 | PPC_OPCODE_POWER7
| PPC_OPCODE_ALTIVEC
| PPC_OPCODE_VSX
),
189 { "pwr8", (PPC_OPCODE_PPC
| PPC_OPCODE_ISEL
| PPC_OPCODE_64
190 | PPC_OPCODE_POWER4
| PPC_OPCODE_POWER5
| PPC_OPCODE_POWER6
191 | PPC_OPCODE_POWER7
| PPC_OPCODE_POWER8
| PPC_OPCODE_HTM
192 | PPC_OPCODE_ALTIVEC
| PPC_OPCODE_ALTIVEC2
| PPC_OPCODE_VSX
),
194 { "pwrx", (PPC_OPCODE_POWER
| PPC_OPCODE_POWER2
),
196 { "spe", (PPC_OPCODE_PPC
| PPC_OPCODE_EFS
),
198 { "titan", (PPC_OPCODE_PPC
| PPC_OPCODE_BOOKE
| PPC_OPCODE_PMR
199 | PPC_OPCODE_RFMCI
| PPC_OPCODE_TITAN
),
201 { "vle", (PPC_OPCODE_PPC
| PPC_OPCODE_ISEL
| PPC_OPCODE_VLE
),
203 { "vsx", (PPC_OPCODE_PPC
),
205 { "htm", (PPC_OPCODE_PPC
),
209 /* Switch between Booke and VLE dialects for interlinked dumps. */
211 get_powerpc_dialect (struct disassemble_info
*info
)
213 ppc_cpu_t dialect
= 0;
215 dialect
= POWERPC_DIALECT (info
);
217 /* Disassemble according to the section headers flags for VLE-mode. */
218 if (dialect
& PPC_OPCODE_VLE
219 && info
->section
->owner
!= NULL
220 && bfd_get_flavour (info
->section
->owner
) == bfd_target_elf_flavour
221 && elf_object_id (info
->section
->owner
) == PPC32_ELF_DATA
222 && (elf_section_flags (info
->section
) & SHF_PPC_VLE
) != 0)
225 return dialect
& ~ PPC_OPCODE_VLE
;
228 /* Handle -m and -M options that set cpu type, and .machine arg. */
231 ppc_parse_cpu (ppc_cpu_t ppc_cpu
, ppc_cpu_t
*sticky
, const char *arg
)
235 for (i
= 0; i
< sizeof (ppc_opts
) / sizeof (ppc_opts
[0]); i
++)
236 if (strcmp (ppc_opts
[i
].opt
, arg
) == 0)
238 if (ppc_opts
[i
].sticky
)
240 *sticky
|= ppc_opts
[i
].sticky
;
241 if ((ppc_cpu
& ~*sticky
) != 0)
244 ppc_cpu
= ppc_opts
[i
].cpu
;
247 if (i
>= sizeof (ppc_opts
) / sizeof (ppc_opts
[0]))
254 /* Determine which set of machines to disassemble for. */
257 powerpc_init_dialect (struct disassemble_info
*info
)
259 ppc_cpu_t dialect
= 0;
260 ppc_cpu_t sticky
= 0;
262 struct dis_private
*priv
= calloc (sizeof (*priv
), 1);
269 case bfd_mach_ppc_403
:
270 case bfd_mach_ppc_403gc
:
271 dialect
= ppc_parse_cpu (dialect
, &sticky
, "403");
273 case bfd_mach_ppc_405
:
274 dialect
= ppc_parse_cpu (dialect
, &sticky
, "405");
276 case bfd_mach_ppc_601
:
277 dialect
= ppc_parse_cpu (dialect
, &sticky
, "601");
279 case bfd_mach_ppc_a35
:
280 case bfd_mach_ppc_rs64ii
:
281 case bfd_mach_ppc_rs64iii
:
282 dialect
= ppc_parse_cpu (dialect
, &sticky
, "pwr2") | PPC_OPCODE_64
;
284 case bfd_mach_ppc_e500
:
285 dialect
= ppc_parse_cpu (dialect
, &sticky
, "e500");
287 case bfd_mach_ppc_e500mc
:
288 dialect
= ppc_parse_cpu (dialect
, &sticky
, "e500mc");
290 case bfd_mach_ppc_e500mc64
:
291 dialect
= ppc_parse_cpu (dialect
, &sticky
, "e500mc64");
293 case bfd_mach_ppc_e5500
:
294 dialect
= ppc_parse_cpu (dialect
, &sticky
, "e5500");
296 case bfd_mach_ppc_e6500
:
297 dialect
= ppc_parse_cpu (dialect
, &sticky
, "e6500");
299 case bfd_mach_ppc_titan
:
300 dialect
= ppc_parse_cpu (dialect
, &sticky
, "titan");
302 case bfd_mach_ppc_vle
:
303 dialect
= ppc_parse_cpu (dialect
, &sticky
, "vle");
306 dialect
= ppc_parse_cpu (dialect
, &sticky
, "power8") | PPC_OPCODE_ANY
;
309 arg
= info
->disassembler_options
;
312 ppc_cpu_t new_cpu
= 0;
313 char *end
= strchr (arg
, ',');
318 if ((new_cpu
= ppc_parse_cpu (dialect
, &sticky
, arg
)) != 0)
320 else if (strcmp (arg
, "32") == 0)
321 dialect
&= ~(ppc_cpu_t
) PPC_OPCODE_64
;
322 else if (strcmp (arg
, "64") == 0)
323 dialect
|= PPC_OPCODE_64
;
325 fprintf (stderr
, _("warning: ignoring unknown -M%s option\n"), arg
);
332 info
->private_data
= priv
;
333 POWERPC_DIALECT(info
) = dialect
;
336 #define PPC_OPCD_SEGS 64
337 static unsigned short powerpc_opcd_indices
[PPC_OPCD_SEGS
+1];
338 #define VLE_OPCD_SEGS 32
339 static unsigned short vle_opcd_indices
[VLE_OPCD_SEGS
+1];
341 /* Calculate opcode table indices to speed up disassembly,
345 disassemble_init_powerpc (struct disassemble_info
*info
)
350 if (powerpc_opcd_indices
[PPC_OPCD_SEGS
] == 0)
353 i
= powerpc_num_opcodes
;
356 unsigned op
= PPC_OP (powerpc_opcodes
[i
].opcode
);
358 powerpc_opcd_indices
[op
] = i
;
361 last
= powerpc_num_opcodes
;
362 for (i
= PPC_OPCD_SEGS
; i
> 0; --i
)
364 if (powerpc_opcd_indices
[i
] == 0)
365 powerpc_opcd_indices
[i
] = last
;
366 last
= powerpc_opcd_indices
[i
];
372 unsigned op
= VLE_OP (vle_opcodes
[i
].opcode
, vle_opcodes
[i
].mask
);
373 unsigned seg
= VLE_OP_TO_SEG (op
);
375 vle_opcd_indices
[seg
] = i
;
378 last
= vle_num_opcodes
;
379 for (i
= VLE_OPCD_SEGS
; i
> 0; --i
)
381 if (vle_opcd_indices
[i
] == 0)
382 vle_opcd_indices
[i
] = last
;
383 last
= vle_opcd_indices
[i
];
387 if (info
->arch
== bfd_arch_powerpc
)
388 powerpc_init_dialect (info
);
391 /* Print a big endian PowerPC instruction. */
394 print_insn_big_powerpc (bfd_vma memaddr
, struct disassemble_info
*info
)
396 return print_insn_powerpc (memaddr
, info
, 1, get_powerpc_dialect (info
));
399 /* Print a little endian PowerPC instruction. */
402 print_insn_little_powerpc (bfd_vma memaddr
, struct disassemble_info
*info
)
404 return print_insn_powerpc (memaddr
, info
, 0, get_powerpc_dialect (info
));
407 /* Print a POWER (RS/6000) instruction. */
410 print_insn_rs6000 (bfd_vma memaddr
, struct disassemble_info
*info
)
412 return print_insn_powerpc (memaddr
, info
, 1, PPC_OPCODE_POWER
);
415 /* Extract the operand value from the PowerPC or POWER instruction. */
418 operand_value_powerpc (const struct powerpc_operand
*operand
,
419 unsigned long insn
, ppc_cpu_t dialect
)
423 /* Extract the value from the instruction. */
424 if (operand
->extract
)
425 value
= (*operand
->extract
) (insn
, dialect
, &invalid
);
428 if (operand
->shift
>= 0)
429 value
= (insn
>> operand
->shift
) & operand
->bitm
;
431 value
= (insn
<< -operand
->shift
) & operand
->bitm
;
432 if ((operand
->flags
& PPC_OPERAND_SIGNED
) != 0)
434 /* BITM is always some number of zeros followed by some
435 number of ones, followed by some number of zeros. */
436 unsigned long top
= operand
->bitm
;
437 /* top & -top gives the rightmost 1 bit, so this
438 fills in any trailing zeros. */
439 top
|= (top
& -top
) - 1;
441 value
= (value
^ top
) - top
;
448 /* Determine whether the optional operand(s) should be printed. */
451 skip_optional_operands (const unsigned char *opindex
,
452 unsigned long insn
, ppc_cpu_t dialect
)
454 const struct powerpc_operand
*operand
;
456 for (; *opindex
!= 0; opindex
++)
458 operand
= &powerpc_operands
[*opindex
];
459 if ((operand
->flags
& PPC_OPERAND_NEXT
) != 0
460 || ((operand
->flags
& PPC_OPERAND_OPTIONAL
) != 0
461 && operand_value_powerpc (operand
, insn
, dialect
) !=
462 ppc_optional_operand_value (operand
)))
469 /* Find a match for INSN in the opcode table, given machine DIALECT.
470 A DIALECT of -1 is special, matching all machine opcode variations. */
472 static const struct powerpc_opcode
*
473 lookup_powerpc (unsigned long insn
, ppc_cpu_t dialect
)
475 const struct powerpc_opcode
*opcode
;
476 const struct powerpc_opcode
*opcode_end
;
479 /* Get the major opcode of the instruction. */
482 /* Find the first match in the opcode table for this major opcode. */
483 opcode_end
= powerpc_opcodes
+ powerpc_opcd_indices
[op
+ 1];
484 for (opcode
= powerpc_opcodes
+ powerpc_opcd_indices
[op
];
488 const unsigned char *opindex
;
489 const struct powerpc_operand
*operand
;
492 if ((insn
& opcode
->mask
) != opcode
->opcode
493 || (dialect
!= (ppc_cpu_t
) -1
494 && ((opcode
->flags
& dialect
) == 0
495 || (opcode
->deprecated
& dialect
) != 0)))
498 /* Check validity of operands. */
500 for (opindex
= opcode
->operands
; *opindex
!= 0; opindex
++)
502 operand
= powerpc_operands
+ *opindex
;
503 if (operand
->extract
)
504 (*operand
->extract
) (insn
, dialect
, &invalid
);
515 /* Find a match for INSN in the VLE opcode table. */
517 static const struct powerpc_opcode
*
518 lookup_vle (unsigned long insn
)
520 const struct powerpc_opcode
*opcode
;
521 const struct powerpc_opcode
*opcode_end
;
525 if (op
>= 0x20 && op
<= 0x37)
527 /* This insn has a 4-bit opcode. */
530 seg
= VLE_OP_TO_SEG (op
);
532 /* Find the first match in the opcode table for this major opcode. */
533 opcode_end
= vle_opcodes
+ vle_opcd_indices
[seg
+ 1];
534 for (opcode
= vle_opcodes
+ vle_opcd_indices
[seg
];
538 unsigned long table_opcd
= opcode
->opcode
;
539 unsigned long table_mask
= opcode
->mask
;
540 bfd_boolean table_op_is_short
= PPC_OP_SE_VLE(table_mask
);
542 const unsigned char *opindex
;
543 const struct powerpc_operand
*operand
;
547 if (table_op_is_short
)
549 if ((insn2
& table_mask
) != table_opcd
)
552 /* Check validity of operands. */
554 for (opindex
= opcode
->operands
; *opindex
!= 0; ++opindex
)
556 operand
= powerpc_operands
+ *opindex
;
557 if (operand
->extract
)
558 (*operand
->extract
) (insn
, (ppc_cpu_t
)0, &invalid
);
569 /* Print a PowerPC or POWER instruction. */
572 print_insn_powerpc (bfd_vma memaddr
,
573 struct disassemble_info
*info
,
580 const struct powerpc_opcode
*opcode
;
581 bfd_boolean insn_is_short
;
583 status
= (*info
->read_memory_func
) (memaddr
, buffer
, 4, info
);
586 /* The final instruction may be a 2-byte VLE insn. */
587 if ((dialect
& PPC_OPCODE_VLE
) != 0)
589 /* Clear buffer so unused bytes will not have garbage in them. */
590 buffer
[0] = buffer
[1] = buffer
[2] = buffer
[3] = 0;
591 status
= (*info
->read_memory_func
) (memaddr
, buffer
, 2, info
);
594 (*info
->memory_error_func
) (status
, memaddr
, info
);
600 (*info
->memory_error_func
) (status
, memaddr
, info
);
606 insn
= bfd_getb32 (buffer
);
608 insn
= bfd_getl32 (buffer
);
610 /* Get the major opcode of the insn. */
612 insn_is_short
= FALSE
;
613 if ((dialect
& PPC_OPCODE_VLE
) != 0)
615 opcode
= lookup_vle (insn
);
617 insn_is_short
= PPC_OP_SE_VLE(opcode
->mask
);
620 opcode
= lookup_powerpc (insn
, dialect
);
621 if (opcode
== NULL
&& (dialect
& PPC_OPCODE_ANY
) != 0)
622 opcode
= lookup_powerpc (insn
, (ppc_cpu_t
) -1);
626 const unsigned char *opindex
;
627 const struct powerpc_operand
*operand
;
632 if (opcode
->operands
[0] != 0)
633 (*info
->fprintf_func
) (info
->stream
, "%-7s ", opcode
->name
);
635 (*info
->fprintf_func
) (info
->stream
, "%s", opcode
->name
);
638 /* The operands will be fetched out of the 16-bit instruction. */
641 /* Now extract and print the operands. */
645 for (opindex
= opcode
->operands
; *opindex
!= 0; opindex
++)
649 operand
= powerpc_operands
+ *opindex
;
651 /* Operands that are marked FAKE are simply ignored. We
652 already made sure that the extract function considered
653 the instruction to be valid. */
654 if ((operand
->flags
& PPC_OPERAND_FAKE
) != 0)
657 /* If all of the optional operands have the value zero,
658 then don't print any of them. */
659 if ((operand
->flags
& PPC_OPERAND_OPTIONAL
) != 0)
661 if (skip_optional
< 0)
662 skip_optional
= skip_optional_operands (opindex
, insn
,
668 value
= operand_value_powerpc (operand
, insn
, dialect
);
672 (*info
->fprintf_func
) (info
->stream
, ",");
676 /* Print the operand as directed by the flags. */
677 if ((operand
->flags
& PPC_OPERAND_GPR
) != 0
678 || ((operand
->flags
& PPC_OPERAND_GPR_0
) != 0 && value
!= 0))
679 (*info
->fprintf_func
) (info
->stream
, "r%ld", value
);
680 else if ((operand
->flags
& PPC_OPERAND_FPR
) != 0)
681 (*info
->fprintf_func
) (info
->stream
, "f%ld", value
);
682 else if ((operand
->flags
& PPC_OPERAND_VR
) != 0)
683 (*info
->fprintf_func
) (info
->stream
, "v%ld", value
);
684 else if ((operand
->flags
& PPC_OPERAND_VSR
) != 0)
685 (*info
->fprintf_func
) (info
->stream
, "vs%ld", value
);
686 else if ((operand
->flags
& PPC_OPERAND_RELATIVE
) != 0)
687 (*info
->print_address_func
) (memaddr
+ value
, info
);
688 else if ((operand
->flags
& PPC_OPERAND_ABSOLUTE
) != 0)
689 (*info
->print_address_func
) ((bfd_vma
) value
& 0xffffffff, info
);
690 else if ((operand
->flags
& PPC_OPERAND_FSL
) != 0)
691 (*info
->fprintf_func
) (info
->stream
, "fsl%ld", value
);
692 else if ((operand
->flags
& PPC_OPERAND_FCR
) != 0)
693 (*info
->fprintf_func
) (info
->stream
, "fcr%ld", value
);
694 else if ((operand
->flags
& PPC_OPERAND_UDI
) != 0)
695 (*info
->fprintf_func
) (info
->stream
, "%ld", value
);
696 else if ((operand
->flags
& PPC_OPERAND_CR_REG
) != 0
697 && (((dialect
& PPC_OPCODE_PPC
) != 0)
698 || ((dialect
& PPC_OPCODE_VLE
) != 0)))
699 (*info
->fprintf_func
) (info
->stream
, "cr%ld", value
);
700 else if (((operand
->flags
& PPC_OPERAND_CR_BIT
) != 0)
701 && (((dialect
& PPC_OPCODE_PPC
) != 0)
702 || ((dialect
& PPC_OPCODE_VLE
) != 0)))
704 static const char *cbnames
[4] = { "lt", "gt", "eq", "so" };
710 (*info
->fprintf_func
) (info
->stream
, "4*cr%d+", cr
);
712 (*info
->fprintf_func
) (info
->stream
, "%s", cbnames
[cc
]);
715 (*info
->fprintf_func
) (info
->stream
, "%d", (int) value
);
719 (*info
->fprintf_func
) (info
->stream
, ")");
723 if ((operand
->flags
& PPC_OPERAND_PARENS
) == 0)
727 (*info
->fprintf_func
) (info
->stream
, "(");
732 /* We have found and printed an instruction.
733 If it was a short VLE instruction we have more to do. */
740 /* Otherwise, return. */
744 /* We could not find a match. */
745 (*info
->fprintf_func
) (info
->stream
, ".long 0x%lx", insn
);
751 print_ppc_disassembler_options (FILE *stream
)
755 fprintf (stream
, _("\n\
756 The following PPC specific disassembler options are supported for use with\n\
759 for (col
= 0, i
= 0; i
< sizeof (ppc_opts
) / sizeof (ppc_opts
[0]); i
++)
761 col
+= fprintf (stream
, " %s,", ppc_opts
[i
].opt
);
764 fprintf (stream
, "\n");
768 fprintf (stream
, " 32, 64\n");