1 /* ppc-dis.c -- Disassemble PowerPC instructions
2 Copyright 1994, 1995, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007,
3 2008, 2009, 2010, 2011, 2012 Free Software Foundation, Inc.
4 Written by Ian Lance Taylor, Cygnus Support
6 This file is part of the GNU opcodes library.
8 This library is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3, or (at your option)
13 It is distributed in the hope that it will be useful, but WITHOUT
14 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
15 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
16 License for more details.
18 You should have received a copy of the GNU General Public License
19 along with this file; see the file COPYING. If not, write to the
20 Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston,
21 MA 02110-1301, USA. */
27 #include "elf32-ppc.h"
29 #include "opcode/ppc.h"
31 /* This file provides several disassembler functions, all of which use
32 the disassembler interface defined in dis-asm.h. Several functions
33 are provided because this file handles disassembly for the PowerPC
34 in both big and little endian mode and also for the POWER (RS/6000)
36 static int print_insn_powerpc (bfd_vma
, struct disassemble_info
*, int,
41 /* Stash the result of parsing disassembler_options here. */
45 #define POWERPC_DIALECT(INFO) \
46 (((struct dis_private *) ((INFO)->private_data))->dialect)
54 struct ppc_mopt ppc_opts
[] = {
55 { "403", (PPC_OPCODE_PPC
| PPC_OPCODE_403
),
57 { "405", (PPC_OPCODE_PPC
| PPC_OPCODE_403
| PPC_OPCODE_405
),
59 { "440", (PPC_OPCODE_PPC
| PPC_OPCODE_BOOKE
| PPC_OPCODE_440
60 | PPC_OPCODE_ISEL
| PPC_OPCODE_RFMCI
),
62 { "464", (PPC_OPCODE_PPC
| PPC_OPCODE_BOOKE
| PPC_OPCODE_440
63 | PPC_OPCODE_ISEL
| PPC_OPCODE_RFMCI
),
65 { "476", (PPC_OPCODE_PPC
| PPC_OPCODE_ISEL
| PPC_OPCODE_440
66 | PPC_OPCODE_476
| PPC_OPCODE_POWER4
| PPC_OPCODE_POWER5
),
68 { "601", (PPC_OPCODE_PPC
| PPC_OPCODE_601
),
70 { "603", (PPC_OPCODE_PPC
),
72 { "604", (PPC_OPCODE_PPC
),
74 { "620", (PPC_OPCODE_PPC
| PPC_OPCODE_64
),
76 { "7400", (PPC_OPCODE_PPC
| PPC_OPCODE_ALTIVEC
),
78 { "7410", (PPC_OPCODE_PPC
| PPC_OPCODE_ALTIVEC
),
80 { "7450", (PPC_OPCODE_PPC
| PPC_OPCODE_ALTIVEC
),
82 { "7455", (PPC_OPCODE_PPC
| PPC_OPCODE_ALTIVEC
),
84 { "750cl", (PPC_OPCODE_PPC
| PPC_OPCODE_PPCPS
)
86 { "a2", (PPC_OPCODE_PPC
| PPC_OPCODE_ISEL
| PPC_OPCODE_POWER4
87 | PPC_OPCODE_POWER5
| PPC_OPCODE_CACHELCK
| PPC_OPCODE_64
90 { "altivec", (PPC_OPCODE_PPC
),
94 { "booke", (PPC_OPCODE_PPC
| PPC_OPCODE_BOOKE
),
96 { "booke32", (PPC_OPCODE_PPC
| PPC_OPCODE_BOOKE
),
98 { "cell", (PPC_OPCODE_PPC
| PPC_OPCODE_64
| PPC_OPCODE_POWER4
99 | PPC_OPCODE_CELL
| PPC_OPCODE_ALTIVEC
),
101 { "com", (PPC_OPCODE_COMMON
),
103 { "e300", (PPC_OPCODE_PPC
| PPC_OPCODE_E300
),
105 { "e500", (PPC_OPCODE_PPC
| PPC_OPCODE_BOOKE
| PPC_OPCODE_SPE
106 | PPC_OPCODE_ISEL
| PPC_OPCODE_EFS
| PPC_OPCODE_BRLOCK
107 | PPC_OPCODE_PMR
| PPC_OPCODE_CACHELCK
| PPC_OPCODE_RFMCI
110 { "e500mc", (PPC_OPCODE_PPC
| PPC_OPCODE_BOOKE
| PPC_OPCODE_ISEL
111 | PPC_OPCODE_PMR
| PPC_OPCODE_CACHELCK
| PPC_OPCODE_RFMCI
112 | PPC_OPCODE_E500MC
),
114 { "e500mc64", (PPC_OPCODE_PPC
| PPC_OPCODE_BOOKE
| PPC_OPCODE_ISEL
115 | PPC_OPCODE_PMR
| PPC_OPCODE_CACHELCK
| PPC_OPCODE_RFMCI
116 | PPC_OPCODE_E500MC
| PPC_OPCODE_64
| PPC_OPCODE_POWER5
117 | PPC_OPCODE_POWER6
| PPC_OPCODE_POWER7
),
119 { "e5500", (PPC_OPCODE_PPC
| PPC_OPCODE_BOOKE
| PPC_OPCODE_ISEL
120 | PPC_OPCODE_PMR
| PPC_OPCODE_CACHELCK
| PPC_OPCODE_RFMCI
121 | PPC_OPCODE_E500MC
| PPC_OPCODE_64
| PPC_OPCODE_POWER4
122 | PPC_OPCODE_POWER5
| PPC_OPCODE_POWER6
123 | PPC_OPCODE_POWER7
),
125 { "e6500", (PPC_OPCODE_PPC
| PPC_OPCODE_BOOKE
| PPC_OPCODE_ISEL
126 | PPC_OPCODE_PMR
| PPC_OPCODE_CACHELCK
| PPC_OPCODE_RFMCI
127 | PPC_OPCODE_E500MC
| PPC_OPCODE_64
| PPC_OPCODE_ALTIVEC
128 | PPC_OPCODE_ALTIVEC2
| PPC_OPCODE_E6500
| PPC_OPCODE_POWER4
129 | PPC_OPCODE_POWER5
| PPC_OPCODE_POWER6
| PPC_OPCODE_POWER7
),
131 { "e500x2", (PPC_OPCODE_PPC
| PPC_OPCODE_BOOKE
| PPC_OPCODE_SPE
132 | PPC_OPCODE_ISEL
| PPC_OPCODE_EFS
| PPC_OPCODE_BRLOCK
133 | PPC_OPCODE_PMR
| PPC_OPCODE_CACHELCK
| PPC_OPCODE_RFMCI
136 { "efs", (PPC_OPCODE_PPC
| PPC_OPCODE_EFS
),
138 { "power4", (PPC_OPCODE_PPC
| PPC_OPCODE_64
| PPC_OPCODE_POWER4
),
140 { "power5", (PPC_OPCODE_PPC
| PPC_OPCODE_64
| PPC_OPCODE_POWER4
141 | PPC_OPCODE_POWER5
),
143 { "power6", (PPC_OPCODE_PPC
| PPC_OPCODE_64
| PPC_OPCODE_POWER4
144 | PPC_OPCODE_POWER5
| PPC_OPCODE_POWER6
| PPC_OPCODE_ALTIVEC
),
146 { "power7", (PPC_OPCODE_PPC
| PPC_OPCODE_ISEL
| PPC_OPCODE_64
147 | PPC_OPCODE_POWER4
| PPC_OPCODE_POWER5
| PPC_OPCODE_POWER6
148 | PPC_OPCODE_POWER7
| PPC_OPCODE_ALTIVEC
| PPC_OPCODE_VSX
),
150 { "ppc", (PPC_OPCODE_PPC
),
152 { "ppc32", (PPC_OPCODE_PPC
),
154 { "ppc64", (PPC_OPCODE_PPC
| PPC_OPCODE_64
),
156 { "ppc64bridge", (PPC_OPCODE_PPC
| PPC_OPCODE_64_BRIDGE
),
158 { "ppcps", (PPC_OPCODE_PPC
| PPC_OPCODE_PPCPS
),
160 { "pwr", (PPC_OPCODE_POWER
),
162 { "pwr2", (PPC_OPCODE_POWER
| PPC_OPCODE_POWER2
),
164 { "pwr4", (PPC_OPCODE_PPC
| PPC_OPCODE_64
| PPC_OPCODE_POWER4
),
166 { "pwr5", (PPC_OPCODE_PPC
| PPC_OPCODE_64
| PPC_OPCODE_POWER4
167 | PPC_OPCODE_POWER5
),
169 { "pwr5x", (PPC_OPCODE_PPC
| PPC_OPCODE_64
| PPC_OPCODE_POWER4
170 | PPC_OPCODE_POWER5
),
172 { "pwr6", (PPC_OPCODE_PPC
| PPC_OPCODE_64
| PPC_OPCODE_POWER4
173 | PPC_OPCODE_POWER5
| PPC_OPCODE_POWER6
| PPC_OPCODE_ALTIVEC
),
175 { "pwr7", (PPC_OPCODE_PPC
| PPC_OPCODE_ISEL
| PPC_OPCODE_64
176 | PPC_OPCODE_POWER4
| PPC_OPCODE_POWER5
| PPC_OPCODE_POWER6
177 | PPC_OPCODE_POWER7
| PPC_OPCODE_ALTIVEC
| PPC_OPCODE_VSX
),
179 { "pwrx", (PPC_OPCODE_POWER
| PPC_OPCODE_POWER2
),
181 { "spe", (PPC_OPCODE_PPC
| PPC_OPCODE_EFS
),
183 { "titan", (PPC_OPCODE_PPC
| PPC_OPCODE_BOOKE
| PPC_OPCODE_PMR
184 | PPC_OPCODE_RFMCI
| PPC_OPCODE_TITAN
),
186 { "vle", (PPC_OPCODE_PPC
| PPC_OPCODE_ISEL
| PPC_OPCODE_VLE
),
188 { "vsx", (PPC_OPCODE_PPC
),
192 /* Switch between Booke and VLE dialects for interlinked dumps. */
194 get_powerpc_dialect (struct disassemble_info
*info
)
196 ppc_cpu_t dialect
= 0;
198 dialect
= POWERPC_DIALECT (info
);
200 /* Disassemble according to the section headers flags for VLE-mode. */
201 if (dialect
& PPC_OPCODE_VLE
202 && is_ppc_vle (info
->section
))
205 return dialect
& ~ PPC_OPCODE_VLE
;
208 /* Handle -m and -M options that set cpu type, and .machine arg. */
211 ppc_parse_cpu (ppc_cpu_t ppc_cpu
, const char *arg
)
213 const ppc_cpu_t retain_mask
= (PPC_OPCODE_ALTIVEC
| PPC_OPCODE_VSX
214 | PPC_OPCODE_SPE
| PPC_OPCODE_ANY
215 | PPC_OPCODE_VLE
| PPC_OPCODE_PMR
);
217 ppc_cpu_t retain_flags
= ppc_cpu
& retain_mask
;
220 for (i
= 0; i
< sizeof (ppc_opts
) / sizeof (ppc_opts
[0]); i
++)
221 if (strcmp (ppc_opts
[i
].opt
, arg
) == 0)
223 if (ppc_opts
[i
].sticky
)
225 retain_flags
|= ppc_opts
[i
].sticky
;
226 if ((ppc_cpu
& ~retain_mask
) != 0)
229 ppc_cpu
= ppc_opts
[i
].cpu
;
232 if (i
>= sizeof (ppc_opts
) / sizeof (ppc_opts
[0]))
235 ppc_cpu
|= retain_flags
;
239 /* Determine which set of machines to disassemble for. */
242 powerpc_init_dialect (struct disassemble_info
*info
)
244 ppc_cpu_t dialect
= 0;
246 struct dis_private
*priv
= calloc (sizeof (*priv
), 1);
251 arg
= info
->disassembler_options
;
254 ppc_cpu_t new_cpu
= 0;
255 char *end
= strchr (arg
, ',');
260 if ((new_cpu
= ppc_parse_cpu (dialect
, arg
)) != 0)
262 else if (strcmp (arg
, "32") == 0)
263 dialect
&= ~(ppc_cpu_t
) PPC_OPCODE_64
;
264 else if (strcmp (arg
, "64") == 0)
265 dialect
|= PPC_OPCODE_64
;
267 fprintf (stderr
, _("warning: ignoring unknown -M%s option\n"), arg
);
274 if ((dialect
& ~(ppc_cpu_t
) PPC_OPCODE_64
) == 0)
276 if (info
->mach
== bfd_mach_ppc64
)
277 dialect
|= PPC_OPCODE_64
;
279 dialect
&= ~(ppc_cpu_t
) PPC_OPCODE_64
;
280 if (info
->mach
== bfd_mach_ppc_vle
)
281 dialect
|= PPC_OPCODE_PPC
| PPC_OPCODE_VLE
;
283 /* Choose a reasonable default. */
284 dialect
|= (PPC_OPCODE_PPC
| PPC_OPCODE_COMMON
| PPC_OPCODE_601
285 | PPC_OPCODE_ALTIVEC
);
288 info
->private_data
= priv
;
289 POWERPC_DIALECT(info
) = dialect
;
292 #define PPC_OPCD_SEGS 64
293 static unsigned short powerpc_opcd_indices
[PPC_OPCD_SEGS
+1];
294 #define VLE_OPCD_SEGS 32
295 static unsigned short vle_opcd_indices
[VLE_OPCD_SEGS
+1];
297 /* Calculate opcode table indices to speed up disassembly,
301 disassemble_init_powerpc (struct disassemble_info
*info
)
306 i
= powerpc_num_opcodes
;
309 unsigned op
= PPC_OP (powerpc_opcodes
[i
].opcode
);
311 powerpc_opcd_indices
[op
] = i
;
314 last
= powerpc_num_opcodes
;
315 for (i
= PPC_OPCD_SEGS
; i
> 0; --i
)
317 if (powerpc_opcd_indices
[i
] == 0)
318 powerpc_opcd_indices
[i
] = last
;
319 last
= powerpc_opcd_indices
[i
];
325 unsigned op
= VLE_OP (vle_opcodes
[i
].opcode
, vle_opcodes
[i
].mask
);
326 unsigned seg
= VLE_OP_TO_SEG (op
);
328 vle_opcd_indices
[seg
] = i
;
331 last
= vle_num_opcodes
;
332 for (i
= VLE_OPCD_SEGS
; i
> 0; --i
)
334 if (vle_opcd_indices
[i
] == 0)
335 vle_opcd_indices
[i
] = last
;
336 last
= vle_opcd_indices
[i
];
339 if (info
->arch
== bfd_arch_powerpc
)
340 powerpc_init_dialect (info
);
343 /* Print a big endian PowerPC instruction. */
346 print_insn_big_powerpc (bfd_vma memaddr
, struct disassemble_info
*info
)
348 return print_insn_powerpc (memaddr
, info
, 1, get_powerpc_dialect (info
));
351 /* Print a little endian PowerPC instruction. */
354 print_insn_little_powerpc (bfd_vma memaddr
, struct disassemble_info
*info
)
356 return print_insn_powerpc (memaddr
, info
, 0, get_powerpc_dialect (info
));
359 /* Print a POWER (RS/6000) instruction. */
362 print_insn_rs6000 (bfd_vma memaddr
, struct disassemble_info
*info
)
364 return print_insn_powerpc (memaddr
, info
, 1, PPC_OPCODE_POWER
);
367 /* Extract the operand value from the PowerPC or POWER instruction. */
370 operand_value_powerpc (const struct powerpc_operand
*operand
,
371 unsigned long insn
, ppc_cpu_t dialect
)
375 /* Extract the value from the instruction. */
376 if (operand
->extract
)
377 value
= (*operand
->extract
) (insn
, dialect
, &invalid
);
380 if (operand
->shift
>= 0)
381 value
= (insn
>> operand
->shift
) & operand
->bitm
;
383 value
= (insn
<< -operand
->shift
) & operand
->bitm
;
384 if ((operand
->flags
& PPC_OPERAND_SIGNED
) != 0)
386 /* BITM is always some number of zeros followed by some
387 number of ones, followed by some number of zeros. */
388 unsigned long top
= operand
->bitm
;
389 /* top & -top gives the rightmost 1 bit, so this
390 fills in any trailing zeros. */
391 top
|= (top
& -top
) - 1;
393 value
= (value
^ top
) - top
;
400 /* Determine whether the optional operand(s) should be printed. */
403 skip_optional_operands (const unsigned char *opindex
,
404 unsigned long insn
, ppc_cpu_t dialect
)
406 const struct powerpc_operand
*operand
;
408 for (; *opindex
!= 0; opindex
++)
410 operand
= &powerpc_operands
[*opindex
];
411 if ((operand
->flags
& PPC_OPERAND_NEXT
) != 0
412 || ((operand
->flags
& PPC_OPERAND_OPTIONAL
) != 0
413 && operand_value_powerpc (operand
, insn
, dialect
) != 0))
420 /* Find a match for INSN in the opcode table, given machine DIALECT.
421 A DIALECT of -1 is special, matching all machine opcode variations. */
423 static const struct powerpc_opcode
*
424 lookup_powerpc (unsigned long insn
, ppc_cpu_t dialect
)
426 const struct powerpc_opcode
*opcode
;
427 const struct powerpc_opcode
*opcode_end
;
430 /* Get the major opcode of the instruction. */
433 /* Find the first match in the opcode table for this major opcode. */
434 opcode_end
= powerpc_opcodes
+ powerpc_opcd_indices
[op
+ 1];
435 for (opcode
= powerpc_opcodes
+ powerpc_opcd_indices
[op
];
439 const unsigned char *opindex
;
440 const struct powerpc_operand
*operand
;
443 if ((insn
& opcode
->mask
) != opcode
->opcode
444 || (dialect
!= (ppc_cpu_t
) -1
445 && ((opcode
->flags
& dialect
) == 0
446 || (opcode
->deprecated
& dialect
) != 0)))
449 /* Check validity of operands. */
451 for (opindex
= opcode
->operands
; *opindex
!= 0; opindex
++)
453 operand
= powerpc_operands
+ *opindex
;
454 if (operand
->extract
)
455 (*operand
->extract
) (insn
, dialect
, &invalid
);
466 /* Find a match for INSN in the VLE opcode table. */
468 static const struct powerpc_opcode
*
469 lookup_vle (unsigned long insn
)
471 const struct powerpc_opcode
*opcode
;
472 const struct powerpc_opcode
*opcode_end
;
476 if (op
>= 0x20 && op
<= 0x37)
478 /* This insn has a 4-bit opcode. */
481 seg
= VLE_OP_TO_SEG (op
);
483 /* Find the first match in the opcode table for this major opcode. */
484 opcode_end
= vle_opcodes
+ vle_opcd_indices
[seg
+ 1];
485 for (opcode
= vle_opcodes
+ vle_opcd_indices
[seg
];
489 unsigned long table_opcd
= opcode
->opcode
;
490 unsigned long table_mask
= opcode
->mask
;
491 bfd_boolean table_op_is_short
= PPC_OP_SE_VLE(table_mask
);
493 const unsigned char *opindex
;
494 const struct powerpc_operand
*operand
;
498 if (table_op_is_short
)
500 if ((insn2
& table_mask
) != table_opcd
)
503 /* Check validity of operands. */
505 for (opindex
= opcode
->operands
; *opindex
!= 0; ++opindex
)
507 operand
= powerpc_operands
+ *opindex
;
508 if (operand
->extract
)
509 (*operand
->extract
) (insn
, (ppc_cpu_t
)0, &invalid
);
520 /* Print a PowerPC or POWER instruction. */
523 print_insn_powerpc (bfd_vma memaddr
,
524 struct disassemble_info
*info
,
531 const struct powerpc_opcode
*opcode
;
532 bfd_boolean insn_is_short
;
534 status
= (*info
->read_memory_func
) (memaddr
, buffer
, 4, info
);
537 /* The final instruction may be a 2-byte VLE insn. */
538 if ((dialect
& PPC_OPCODE_VLE
) != 0)
540 /* Clear buffer so unused bytes will not have garbage in them. */
541 buffer
[0] = buffer
[1] = buffer
[2] = buffer
[3] = 0;
542 status
= (*info
->read_memory_func
) (memaddr
, buffer
, 2, info
);
545 (*info
->memory_error_func
) (status
, memaddr
, info
);
551 (*info
->memory_error_func
) (status
, memaddr
, info
);
557 insn
= bfd_getb32 (buffer
);
559 insn
= bfd_getl32 (buffer
);
561 /* Get the major opcode of the insn. */
563 insn_is_short
= FALSE
;
564 if ((dialect
& PPC_OPCODE_VLE
) != 0)
566 opcode
= lookup_vle (insn
);
568 insn_is_short
= PPC_OP_SE_VLE(opcode
->mask
);
571 opcode
= lookup_powerpc (insn
, dialect
);
572 if (opcode
== NULL
&& (dialect
& PPC_OPCODE_ANY
) != 0)
573 opcode
= lookup_powerpc (insn
, (ppc_cpu_t
) -1);
577 const unsigned char *opindex
;
578 const struct powerpc_operand
*operand
;
583 if (opcode
->operands
[0] != 0)
584 (*info
->fprintf_func
) (info
->stream
, "%-7s ", opcode
->name
);
586 (*info
->fprintf_func
) (info
->stream
, "%s", opcode
->name
);
589 /* The operands will be fetched out of the 16-bit instruction. */
592 /* Now extract and print the operands. */
596 for (opindex
= opcode
->operands
; *opindex
!= 0; opindex
++)
600 operand
= powerpc_operands
+ *opindex
;
602 /* Operands that are marked FAKE are simply ignored. We
603 already made sure that the extract function considered
604 the instruction to be valid. */
605 if ((operand
->flags
& PPC_OPERAND_FAKE
) != 0)
608 /* If all of the optional operands have the value zero,
609 then don't print any of them. */
610 if ((operand
->flags
& PPC_OPERAND_OPTIONAL
) != 0)
612 if (skip_optional
< 0)
613 skip_optional
= skip_optional_operands (opindex
, insn
,
619 value
= operand_value_powerpc (operand
, insn
, dialect
);
623 (*info
->fprintf_func
) (info
->stream
, ",");
627 /* Print the operand as directed by the flags. */
628 if ((operand
->flags
& PPC_OPERAND_GPR
) != 0
629 || ((operand
->flags
& PPC_OPERAND_GPR_0
) != 0 && value
!= 0))
630 (*info
->fprintf_func
) (info
->stream
, "r%ld", value
);
631 else if ((operand
->flags
& PPC_OPERAND_FPR
) != 0)
632 (*info
->fprintf_func
) (info
->stream
, "f%ld", value
);
633 else if ((operand
->flags
& PPC_OPERAND_VR
) != 0)
634 (*info
->fprintf_func
) (info
->stream
, "v%ld", value
);
635 else if ((operand
->flags
& PPC_OPERAND_VSR
) != 0)
636 (*info
->fprintf_func
) (info
->stream
, "vs%ld", value
);
637 else if ((operand
->flags
& PPC_OPERAND_RELATIVE
) != 0)
638 (*info
->print_address_func
) (memaddr
+ value
, info
);
639 else if ((operand
->flags
& PPC_OPERAND_ABSOLUTE
) != 0)
640 (*info
->print_address_func
) ((bfd_vma
) value
& 0xffffffff, info
);
641 else if ((operand
->flags
& PPC_OPERAND_FSL
) != 0)
642 (*info
->fprintf_func
) (info
->stream
, "fsl%ld", value
);
643 else if ((operand
->flags
& PPC_OPERAND_FCR
) != 0)
644 (*info
->fprintf_func
) (info
->stream
, "fcr%ld", value
);
645 else if ((operand
->flags
& PPC_OPERAND_UDI
) != 0)
646 (*info
->fprintf_func
) (info
->stream
, "%ld", value
);
647 else if ((operand
->flags
& PPC_OPERAND_CR_REG
) != 0
648 && (((dialect
& PPC_OPCODE_PPC
) != 0)
649 || ((dialect
& PPC_OPCODE_VLE
) != 0)))
650 (*info
->fprintf_func
) (info
->stream
, "cr%ld", value
);
651 else if (((operand
->flags
& PPC_OPERAND_CR_BIT
) != 0)
652 && (((dialect
& PPC_OPCODE_PPC
) != 0)
653 || ((dialect
& PPC_OPCODE_VLE
) != 0)))
655 static const char *cbnames
[4] = { "lt", "gt", "eq", "so" };
661 (*info
->fprintf_func
) (info
->stream
, "4*cr%d+", cr
);
663 (*info
->fprintf_func
) (info
->stream
, "%s", cbnames
[cc
]);
666 (*info
->fprintf_func
) (info
->stream
, "%d", value
);
670 (*info
->fprintf_func
) (info
->stream
, ")");
674 if ((operand
->flags
& PPC_OPERAND_PARENS
) == 0)
678 (*info
->fprintf_func
) (info
->stream
, "(");
683 /* We have found and printed an instruction.
684 If it was a short VLE instruction we have more to do. */
691 /* Otherwise, return. */
695 /* We could not find a match. */
696 (*info
->fprintf_func
) (info
->stream
, ".long 0x%lx", insn
);
702 print_ppc_disassembler_options (FILE *stream
)
706 fprintf (stream
, _("\n\
707 The following PPC specific disassembler options are supported for use with\n\
710 for (col
= 0, i
= 0; i
< sizeof (ppc_opts
) / sizeof (ppc_opts
[0]); i
++)
712 col
+= fprintf (stream
, " %s,", ppc_opts
[i
].opt
);
715 fprintf (stream
, "\n");
719 fprintf (stream
, " 32, 64\n");