1 /* ppc-dis.c -- Disassemble PowerPC instructions
2 Copyright (C) 1994-2020 Free Software Foundation, Inc.
3 Written by Ian Lance Taylor, Cygnus Support
5 This file is part of the GNU opcodes library.
7 This library is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3, or (at your option)
12 It is distributed in the hope that it will be useful, but WITHOUT
13 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
14 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
15 License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this file; see the file COPYING. If not, write to the
19 Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston,
20 MA 02110-1301, USA. */
24 #include "disassemble.h"
28 #include "opcode/ppc.h"
29 #include "libiberty.h"
31 /* This file provides several disassembler functions, all of which use
32 the disassembler interface defined in dis-asm.h. Several functions
33 are provided because this file handles disassembly for the PowerPC
34 in both big and little endian mode and also for the POWER (RS/6000)
36 static int print_insn_powerpc (bfd_vma
, struct disassemble_info
*, int,
41 /* Stash the result of parsing disassembler_options here. */
45 #define POWERPC_DIALECT(INFO) \
46 (((struct dis_private *) ((INFO)->private_data))->dialect)
49 /* Option string, without -m or -M prefix. */
51 /* CPU option flags. */
53 /* Flags that should stay on, even when combined with another cpu
54 option. This should only be used for generic options like
55 "-many" or "-maltivec" where it is reasonable to add some
56 capability to another cpu selection. The added flags are sticky
57 so that, for example, "-many -me500" and "-me500 -many" result in
58 the same assembler or disassembler behaviour. Do not use
59 "sticky" for specific cpus, as this will prevent that cpu's flags
60 from overriding the defaults set in powerpc_init_dialect or a
65 struct ppc_mopt ppc_opts
[] = {
66 { "403", PPC_OPCODE_PPC
| PPC_OPCODE_403
,
68 { "405", PPC_OPCODE_PPC
| PPC_OPCODE_403
| PPC_OPCODE_405
,
70 { "440", (PPC_OPCODE_PPC
| PPC_OPCODE_BOOKE
| PPC_OPCODE_440
71 | PPC_OPCODE_ISEL
| PPC_OPCODE_RFMCI
),
73 { "464", (PPC_OPCODE_PPC
| PPC_OPCODE_BOOKE
| PPC_OPCODE_440
74 | PPC_OPCODE_ISEL
| PPC_OPCODE_RFMCI
),
76 { "476", (PPC_OPCODE_PPC
| PPC_OPCODE_ISEL
| PPC_OPCODE_476
77 | PPC_OPCODE_POWER4
| PPC_OPCODE_POWER5
),
79 { "601", PPC_OPCODE_PPC
| PPC_OPCODE_601
,
81 { "603", PPC_OPCODE_PPC
,
83 { "604", PPC_OPCODE_PPC
,
85 { "620", PPC_OPCODE_PPC
| PPC_OPCODE_64
,
87 { "7400", PPC_OPCODE_PPC
| PPC_OPCODE_ALTIVEC
,
89 { "7410", PPC_OPCODE_PPC
| PPC_OPCODE_ALTIVEC
,
91 { "7450", PPC_OPCODE_PPC
| PPC_OPCODE_7450
| PPC_OPCODE_ALTIVEC
,
93 { "7455", PPC_OPCODE_PPC
| PPC_OPCODE_ALTIVEC
,
95 { "750cl", PPC_OPCODE_PPC
| PPC_OPCODE_750
| PPC_OPCODE_PPCPS
97 { "gekko", PPC_OPCODE_PPC
| PPC_OPCODE_750
| PPC_OPCODE_PPCPS
99 { "broadway", PPC_OPCODE_PPC
| PPC_OPCODE_750
| PPC_OPCODE_PPCPS
101 { "821", PPC_OPCODE_PPC
| PPC_OPCODE_860
,
103 { "850", PPC_OPCODE_PPC
| PPC_OPCODE_860
,
105 { "860", PPC_OPCODE_PPC
| PPC_OPCODE_860
,
107 { "a2", (PPC_OPCODE_PPC
| PPC_OPCODE_ISEL
| PPC_OPCODE_POWER4
108 | PPC_OPCODE_POWER5
| PPC_OPCODE_CACHELCK
| PPC_OPCODE_64
111 { "altivec", PPC_OPCODE_PPC
,
112 PPC_OPCODE_ALTIVEC
},
113 { "any", PPC_OPCODE_PPC
,
115 { "booke", PPC_OPCODE_PPC
| PPC_OPCODE_BOOKE
,
117 { "booke32", PPC_OPCODE_PPC
| PPC_OPCODE_BOOKE
,
119 { "cell", (PPC_OPCODE_PPC
| PPC_OPCODE_64
| PPC_OPCODE_POWER4
120 | PPC_OPCODE_CELL
| PPC_OPCODE_ALTIVEC
),
122 { "com", PPC_OPCODE_COMMON
,
124 { "e200z4", (PPC_OPCODE_PPC
| PPC_OPCODE_BOOKE
| PPC_OPCODE_SPE
125 | PPC_OPCODE_ISEL
| PPC_OPCODE_EFS
| PPC_OPCODE_BRLOCK
126 | PPC_OPCODE_PMR
| PPC_OPCODE_CACHELCK
| PPC_OPCODE_RFMCI
127 | PPC_OPCODE_E500
| PPC_OPCODE_VLE
| PPC_OPCODE_E200Z4
128 | PPC_OPCODE_EFS2
| PPC_OPCODE_LSP
),
130 { "e300", PPC_OPCODE_PPC
| PPC_OPCODE_E300
,
132 { "e500", (PPC_OPCODE_PPC
| PPC_OPCODE_BOOKE
| PPC_OPCODE_SPE
133 | PPC_OPCODE_ISEL
| PPC_OPCODE_EFS
| PPC_OPCODE_BRLOCK
134 | PPC_OPCODE_PMR
| PPC_OPCODE_CACHELCK
| PPC_OPCODE_RFMCI
137 { "e500mc", (PPC_OPCODE_PPC
| PPC_OPCODE_BOOKE
| PPC_OPCODE_ISEL
138 | PPC_OPCODE_PMR
| PPC_OPCODE_CACHELCK
| PPC_OPCODE_RFMCI
139 | PPC_OPCODE_E500MC
),
141 { "e500mc64", (PPC_OPCODE_PPC
| PPC_OPCODE_BOOKE
| PPC_OPCODE_ISEL
142 | PPC_OPCODE_PMR
| PPC_OPCODE_CACHELCK
| PPC_OPCODE_RFMCI
143 | PPC_OPCODE_E500MC
| PPC_OPCODE_64
| PPC_OPCODE_POWER5
144 | PPC_OPCODE_POWER6
| PPC_OPCODE_POWER7
),
146 { "e5500", (PPC_OPCODE_PPC
| PPC_OPCODE_BOOKE
| PPC_OPCODE_ISEL
147 | PPC_OPCODE_PMR
| PPC_OPCODE_CACHELCK
| PPC_OPCODE_RFMCI
148 | PPC_OPCODE_E500MC
| PPC_OPCODE_64
| PPC_OPCODE_POWER4
149 | PPC_OPCODE_POWER5
| PPC_OPCODE_POWER6
| PPC_OPCODE_POWER7
),
151 { "e6500", (PPC_OPCODE_PPC
| PPC_OPCODE_BOOKE
| PPC_OPCODE_ISEL
152 | PPC_OPCODE_PMR
| PPC_OPCODE_CACHELCK
| PPC_OPCODE_RFMCI
153 | PPC_OPCODE_E500MC
| PPC_OPCODE_64
| PPC_OPCODE_ALTIVEC
154 | PPC_OPCODE_E6500
| PPC_OPCODE_TMR
| PPC_OPCODE_POWER4
155 | PPC_OPCODE_POWER5
| PPC_OPCODE_POWER6
| PPC_OPCODE_POWER7
),
157 { "e500x2", (PPC_OPCODE_PPC
| PPC_OPCODE_BOOKE
| PPC_OPCODE_SPE
158 | PPC_OPCODE_ISEL
| PPC_OPCODE_EFS
| PPC_OPCODE_BRLOCK
159 | PPC_OPCODE_PMR
| PPC_OPCODE_CACHELCK
| PPC_OPCODE_RFMCI
162 { "efs", PPC_OPCODE_PPC
| PPC_OPCODE_EFS
,
164 { "efs2", PPC_OPCODE_PPC
| PPC_OPCODE_EFS
| PPC_OPCODE_EFS2
,
166 { "power4", PPC_OPCODE_PPC
| PPC_OPCODE_64
| PPC_OPCODE_POWER4
,
168 { "power5", (PPC_OPCODE_PPC
| PPC_OPCODE_64
| PPC_OPCODE_POWER4
169 | PPC_OPCODE_POWER5
),
171 { "power6", (PPC_OPCODE_PPC
| PPC_OPCODE_64
| PPC_OPCODE_POWER4
172 | PPC_OPCODE_POWER5
| PPC_OPCODE_POWER6
| PPC_OPCODE_ALTIVEC
),
174 { "power7", (PPC_OPCODE_PPC
| PPC_OPCODE_ISEL
| PPC_OPCODE_64
175 | PPC_OPCODE_POWER4
| PPC_OPCODE_POWER5
| PPC_OPCODE_POWER6
176 | PPC_OPCODE_POWER7
| PPC_OPCODE_ALTIVEC
| PPC_OPCODE_VSX
),
178 { "power8", (PPC_OPCODE_PPC
| PPC_OPCODE_ISEL
| PPC_OPCODE_64
179 | PPC_OPCODE_POWER4
| PPC_OPCODE_POWER5
| PPC_OPCODE_POWER6
180 | PPC_OPCODE_POWER7
| PPC_OPCODE_POWER8
181 | PPC_OPCODE_ALTIVEC
| PPC_OPCODE_VSX
),
183 { "power9", (PPC_OPCODE_PPC
| PPC_OPCODE_ISEL
| PPC_OPCODE_64
184 | PPC_OPCODE_POWER4
| PPC_OPCODE_POWER5
| PPC_OPCODE_POWER6
185 | PPC_OPCODE_POWER7
| PPC_OPCODE_POWER8
| PPC_OPCODE_POWER9
186 | PPC_OPCODE_ALTIVEC
| PPC_OPCODE_VSX
),
188 { "power10", (PPC_OPCODE_PPC
| PPC_OPCODE_ISEL
| PPC_OPCODE_64
189 | PPC_OPCODE_POWER4
| PPC_OPCODE_POWER5
| PPC_OPCODE_POWER6
190 | PPC_OPCODE_POWER7
| PPC_OPCODE_POWER8
| PPC_OPCODE_POWER9
191 | PPC_OPCODE_POWER10
| PPC_OPCODE_ALTIVEC
| PPC_OPCODE_VSX
),
193 { "future", (PPC_OPCODE_PPC
| PPC_OPCODE_ISEL
| PPC_OPCODE_64
194 | PPC_OPCODE_POWER4
| PPC_OPCODE_POWER5
| PPC_OPCODE_POWER6
195 | PPC_OPCODE_POWER7
| PPC_OPCODE_POWER8
| PPC_OPCODE_POWER9
196 | PPC_OPCODE_POWER10
| PPC_OPCODE_ALTIVEC
| PPC_OPCODE_VSX
),
198 { "ppc", PPC_OPCODE_PPC
,
200 { "ppc32", PPC_OPCODE_PPC
,
202 { "32", PPC_OPCODE_PPC
,
204 { "ppc64", PPC_OPCODE_PPC
| PPC_OPCODE_64
,
206 { "64", PPC_OPCODE_PPC
| PPC_OPCODE_64
,
208 { "ppc64bridge", PPC_OPCODE_PPC
| PPC_OPCODE_64_BRIDGE
,
210 { "ppcps", PPC_OPCODE_PPC
| PPC_OPCODE_PPCPS
,
212 { "pwr", PPC_OPCODE_POWER
,
214 { "pwr2", PPC_OPCODE_POWER
| PPC_OPCODE_POWER2
,
216 { "pwr4", PPC_OPCODE_PPC
| PPC_OPCODE_64
| PPC_OPCODE_POWER4
,
218 { "pwr5", (PPC_OPCODE_PPC
| PPC_OPCODE_64
| PPC_OPCODE_POWER4
219 | PPC_OPCODE_POWER5
),
221 { "pwr5x", (PPC_OPCODE_PPC
| PPC_OPCODE_64
| PPC_OPCODE_POWER4
222 | PPC_OPCODE_POWER5
),
224 { "pwr6", (PPC_OPCODE_PPC
| PPC_OPCODE_64
| PPC_OPCODE_POWER4
225 | PPC_OPCODE_POWER5
| PPC_OPCODE_POWER6
| PPC_OPCODE_ALTIVEC
),
227 { "pwr7", (PPC_OPCODE_PPC
| PPC_OPCODE_ISEL
| PPC_OPCODE_64
228 | PPC_OPCODE_POWER4
| PPC_OPCODE_POWER5
| PPC_OPCODE_POWER6
229 | PPC_OPCODE_POWER7
| PPC_OPCODE_ALTIVEC
| PPC_OPCODE_VSX
),
231 { "pwr8", (PPC_OPCODE_PPC
| PPC_OPCODE_ISEL
| PPC_OPCODE_64
232 | PPC_OPCODE_POWER4
| PPC_OPCODE_POWER5
| PPC_OPCODE_POWER6
233 | PPC_OPCODE_POWER7
| PPC_OPCODE_POWER8
234 | PPC_OPCODE_ALTIVEC
| PPC_OPCODE_VSX
),
236 { "pwr9", (PPC_OPCODE_PPC
| PPC_OPCODE_ISEL
| PPC_OPCODE_64
237 | PPC_OPCODE_POWER4
| PPC_OPCODE_POWER5
| PPC_OPCODE_POWER6
238 | PPC_OPCODE_POWER7
| PPC_OPCODE_POWER8
| PPC_OPCODE_POWER9
239 | PPC_OPCODE_ALTIVEC
| PPC_OPCODE_VSX
),
241 { "pwr10", (PPC_OPCODE_PPC
| PPC_OPCODE_ISEL
| PPC_OPCODE_64
242 | PPC_OPCODE_POWER4
| PPC_OPCODE_POWER5
| PPC_OPCODE_POWER6
243 | PPC_OPCODE_POWER7
| PPC_OPCODE_POWER8
| PPC_OPCODE_POWER9
244 | PPC_OPCODE_POWER10
| PPC_OPCODE_ALTIVEC
| PPC_OPCODE_VSX
),
246 { "pwrx", PPC_OPCODE_POWER
| PPC_OPCODE_POWER2
,
248 { "raw", PPC_OPCODE_PPC
,
250 { "spe", PPC_OPCODE_PPC
| PPC_OPCODE_EFS
,
252 { "spe2", PPC_OPCODE_PPC
| PPC_OPCODE_EFS
| PPC_OPCODE_EFS2
| PPC_OPCODE_SPE
,
254 { "titan", (PPC_OPCODE_PPC
| PPC_OPCODE_BOOKE
| PPC_OPCODE_PMR
255 | PPC_OPCODE_RFMCI
| PPC_OPCODE_TITAN
),
257 { "vle", (PPC_OPCODE_PPC
| PPC_OPCODE_BOOKE
| PPC_OPCODE_SPE
258 | PPC_OPCODE_ISEL
| PPC_OPCODE_EFS
| PPC_OPCODE_BRLOCK
259 | PPC_OPCODE_PMR
| PPC_OPCODE_CACHELCK
| PPC_OPCODE_RFMCI
260 | PPC_OPCODE_LSP
| PPC_OPCODE_EFS2
| PPC_OPCODE_SPE2
),
262 { "vsx", PPC_OPCODE_PPC
,
266 /* Switch between Booke and VLE dialects for interlinked dumps. */
268 get_powerpc_dialect (struct disassemble_info
*info
)
270 ppc_cpu_t dialect
= 0;
272 if (info
->private_data
)
273 dialect
= POWERPC_DIALECT (info
);
275 /* Disassemble according to the section headers flags for VLE-mode. */
276 if (dialect
& PPC_OPCODE_VLE
277 && info
->section
!= NULL
&& info
->section
->owner
!= NULL
278 && bfd_get_flavour (info
->section
->owner
) == bfd_target_elf_flavour
279 && elf_object_id (info
->section
->owner
) == PPC32_ELF_DATA
280 && (elf_section_flags (info
->section
) & SHF_PPC_VLE
) != 0)
283 return dialect
& ~ PPC_OPCODE_VLE
;
286 /* Handle -m and -M options that set cpu type, and .machine arg. */
289 ppc_parse_cpu (ppc_cpu_t ppc_cpu
, ppc_cpu_t
*sticky
, const char *arg
)
293 for (i
= 0; i
< ARRAY_SIZE (ppc_opts
); i
++)
294 if (disassembler_options_cmp (ppc_opts
[i
].opt
, arg
) == 0)
296 if (ppc_opts
[i
].sticky
)
298 *sticky
|= ppc_opts
[i
].sticky
;
299 if ((ppc_cpu
& ~*sticky
) != 0)
302 ppc_cpu
= ppc_opts
[i
].cpu
;
305 if (i
>= ARRAY_SIZE (ppc_opts
))
312 /* Determine which set of machines to disassemble for. */
315 powerpc_init_dialect (struct disassemble_info
*info
)
317 ppc_cpu_t dialect
= 0;
318 ppc_cpu_t sticky
= 0;
319 struct dis_private
*priv
= calloc (sizeof (*priv
), 1);
326 case bfd_mach_ppc_403
:
327 case bfd_mach_ppc_403gc
:
328 dialect
= ppc_parse_cpu (dialect
, &sticky
, "403");
330 case bfd_mach_ppc_405
:
331 dialect
= ppc_parse_cpu (dialect
, &sticky
, "405");
333 case bfd_mach_ppc_601
:
334 dialect
= ppc_parse_cpu (dialect
, &sticky
, "601");
336 case bfd_mach_ppc_750
:
337 dialect
= ppc_parse_cpu (dialect
, &sticky
, "750cl");
339 case bfd_mach_ppc_a35
:
340 case bfd_mach_ppc_rs64ii
:
341 case bfd_mach_ppc_rs64iii
:
342 dialect
= ppc_parse_cpu (dialect
, &sticky
, "pwr2") | PPC_OPCODE_64
;
344 case bfd_mach_ppc_e500
:
345 dialect
= ppc_parse_cpu (dialect
, &sticky
, "e500");
347 case bfd_mach_ppc_e500mc
:
348 dialect
= ppc_parse_cpu (dialect
, &sticky
, "e500mc");
350 case bfd_mach_ppc_e500mc64
:
351 dialect
= ppc_parse_cpu (dialect
, &sticky
, "e500mc64");
353 case bfd_mach_ppc_e5500
:
354 dialect
= ppc_parse_cpu (dialect
, &sticky
, "e5500");
356 case bfd_mach_ppc_e6500
:
357 dialect
= ppc_parse_cpu (dialect
, &sticky
, "e6500");
359 case bfd_mach_ppc_titan
:
360 dialect
= ppc_parse_cpu (dialect
, &sticky
, "titan");
362 case bfd_mach_ppc_vle
:
363 dialect
= ppc_parse_cpu (dialect
, &sticky
, "vle");
366 if (info
->arch
== bfd_arch_powerpc
)
367 dialect
= ppc_parse_cpu (dialect
, &sticky
, "power10") | PPC_OPCODE_ANY
;
369 dialect
= ppc_parse_cpu (dialect
, &sticky
, "pwr");
374 FOR_EACH_DISASSEMBLER_OPTION (opt
, info
->disassembler_options
)
376 ppc_cpu_t new_cpu
= 0;
378 if (disassembler_options_cmp (opt
, "32") == 0)
379 dialect
&= ~(ppc_cpu_t
) PPC_OPCODE_64
;
380 else if (disassembler_options_cmp (opt
, "64") == 0)
381 dialect
|= PPC_OPCODE_64
;
382 else if ((new_cpu
= ppc_parse_cpu (dialect
, &sticky
, opt
)) != 0)
385 /* xgettext: c-format */
386 opcodes_error_handler (_("warning: ignoring unknown -M%s option"), opt
);
389 info
->private_data
= priv
;
390 POWERPC_DIALECT(info
) = dialect
;
393 #define PPC_OPCD_SEGS (1 + PPC_OP (-1))
394 static unsigned short powerpc_opcd_indices
[PPC_OPCD_SEGS
+ 1];
395 #define PREFIX_OPCD_SEGS (1 + PPC_PREFIX_SEG (-1))
396 static unsigned short prefix_opcd_indices
[PREFIX_OPCD_SEGS
+ 1];
397 #define VLE_OPCD_SEGS (1 + VLE_OP_TO_SEG (VLE_OP (-1, 0xffff)))
398 static unsigned short vle_opcd_indices
[VLE_OPCD_SEGS
+ 1];
399 #define SPE2_OPCD_SEGS (1 + SPE2_XOP_TO_SEG (SPE2_XOP (-1)))
400 static unsigned short spe2_opcd_indices
[SPE2_OPCD_SEGS
+ 1];
402 /* Calculate opcode table indices to speed up disassembly,
406 disassemble_init_powerpc (struct disassemble_info
*info
)
408 if (powerpc_opcd_indices
[PPC_OPCD_SEGS
] == 0)
410 unsigned seg
, idx
, op
;
413 for (seg
= 0, idx
= 0; seg
<= PPC_OPCD_SEGS
; seg
++)
415 powerpc_opcd_indices
[seg
] = idx
;
416 for (; idx
< powerpc_num_opcodes
; idx
++)
417 if (seg
< PPC_OP (powerpc_opcodes
[idx
].opcode
))
421 /* 64-bit prefix opcodes */
422 for (seg
= 0, idx
= 0; seg
<= PREFIX_OPCD_SEGS
; seg
++)
424 prefix_opcd_indices
[seg
] = idx
;
425 for (; idx
< prefix_num_opcodes
; idx
++)
426 if (seg
< PPC_PREFIX_SEG (prefix_opcodes
[idx
].opcode
))
431 for (seg
= 0, idx
= 0; seg
<= VLE_OPCD_SEGS
; seg
++)
433 vle_opcd_indices
[seg
] = idx
;
434 for (; idx
< vle_num_opcodes
; idx
++)
436 op
= VLE_OP (vle_opcodes
[idx
].opcode
, vle_opcodes
[idx
].mask
);
437 if (seg
< VLE_OP_TO_SEG (op
))
443 for (seg
= 0, idx
= 0; seg
<= SPE2_OPCD_SEGS
; seg
++)
445 spe2_opcd_indices
[seg
] = idx
;
446 for (; idx
< spe2_num_opcodes
; idx
++)
448 op
= SPE2_XOP (spe2_opcodes
[idx
].opcode
);
449 if (seg
< SPE2_XOP_TO_SEG (op
))
455 powerpc_init_dialect (info
);
458 /* Print a big endian PowerPC instruction. */
461 print_insn_big_powerpc (bfd_vma memaddr
, struct disassemble_info
*info
)
463 return print_insn_powerpc (memaddr
, info
, 1, get_powerpc_dialect (info
));
466 /* Print a little endian PowerPC instruction. */
469 print_insn_little_powerpc (bfd_vma memaddr
, struct disassemble_info
*info
)
471 return print_insn_powerpc (memaddr
, info
, 0, get_powerpc_dialect (info
));
474 /* Extract the operand value from the PowerPC or POWER instruction. */
477 operand_value_powerpc (const struct powerpc_operand
*operand
,
478 uint64_t insn
, ppc_cpu_t dialect
)
482 /* Extract the value from the instruction. */
483 if (operand
->extract
)
484 value
= (*operand
->extract
) (insn
, dialect
, &invalid
);
487 if (operand
->shift
>= 0)
488 value
= (insn
>> operand
->shift
) & operand
->bitm
;
490 value
= (insn
<< -operand
->shift
) & operand
->bitm
;
491 if ((operand
->flags
& PPC_OPERAND_SIGNED
) != 0)
493 /* BITM is always some number of zeros followed by some
494 number of ones, followed by some number of zeros. */
495 uint64_t top
= operand
->bitm
;
496 /* top & -top gives the rightmost 1 bit, so this
497 fills in any trailing zeros. */
498 top
|= (top
& -top
) - 1;
500 value
= (value
^ top
) - top
;
507 /* Determine whether the optional operand(s) should be printed. */
510 skip_optional_operands (const unsigned char *opindex
,
511 uint64_t insn
, ppc_cpu_t dialect
)
513 const struct powerpc_operand
*operand
;
516 for (num_optional
= 0; *opindex
!= 0; opindex
++)
518 operand
= &powerpc_operands
[*opindex
];
519 if ((operand
->flags
& PPC_OPERAND_NEXT
) != 0)
521 if ((operand
->flags
& PPC_OPERAND_OPTIONAL
) != 0)
523 /* Negative count is used as a flag to extract function. */
525 if (operand_value_powerpc (operand
, insn
, dialect
)
526 != ppc_optional_operand_value (operand
, insn
, dialect
,
535 /* Find a match for INSN in the opcode table, given machine DIALECT. */
537 static const struct powerpc_opcode
*
538 lookup_powerpc (uint64_t insn
, ppc_cpu_t dialect
)
540 const struct powerpc_opcode
*opcode
, *opcode_end
, *last
;
543 /* Get the major opcode of the instruction. */
546 /* Find the first match in the opcode table for this major opcode. */
547 opcode_end
= powerpc_opcodes
+ powerpc_opcd_indices
[op
+ 1];
549 for (opcode
= powerpc_opcodes
+ powerpc_opcd_indices
[op
];
553 const unsigned char *opindex
;
554 const struct powerpc_operand
*operand
;
557 if ((insn
& opcode
->mask
) != opcode
->opcode
558 || ((dialect
& PPC_OPCODE_ANY
) == 0
559 && ((opcode
->flags
& dialect
) == 0
560 || (opcode
->deprecated
& dialect
) != 0)))
563 /* Check validity of operands. */
565 for (opindex
= opcode
->operands
; *opindex
!= 0; opindex
++)
567 operand
= powerpc_operands
+ *opindex
;
568 if (operand
->extract
)
569 (*operand
->extract
) (insn
, dialect
, &invalid
);
574 if ((dialect
& PPC_OPCODE_RAW
) == 0)
577 /* The raw machine insn is one that is not a specialization. */
579 || (last
->mask
& ~opcode
->mask
) != 0)
586 /* Find a match for INSN in the PREFIX opcode table. */
588 static const struct powerpc_opcode
*
589 lookup_prefix (uint64_t insn
, ppc_cpu_t dialect
)
591 const struct powerpc_opcode
*opcode
, *opcode_end
, *last
;
594 /* Get the opcode segment of the instruction. */
595 seg
= PPC_PREFIX_SEG (insn
);
597 /* Find the first match in the opcode table for this major opcode. */
598 opcode_end
= prefix_opcodes
+ prefix_opcd_indices
[seg
+ 1];
600 for (opcode
= prefix_opcodes
+ prefix_opcd_indices
[seg
];
604 const unsigned char *opindex
;
605 const struct powerpc_operand
*operand
;
608 if ((insn
& opcode
->mask
) != opcode
->opcode
609 || ((dialect
& PPC_OPCODE_ANY
) == 0
610 && ((opcode
->flags
& dialect
) == 0
611 || (opcode
->deprecated
& dialect
) != 0)))
614 /* Check validity of operands. */
616 for (opindex
= opcode
->operands
; *opindex
!= 0; opindex
++)
618 operand
= powerpc_operands
+ *opindex
;
619 if (operand
->extract
)
620 (*operand
->extract
) (insn
, dialect
, &invalid
);
625 if ((dialect
& PPC_OPCODE_RAW
) == 0)
628 /* The raw machine insn is one that is not a specialization. */
630 || (last
->mask
& ~opcode
->mask
) != 0)
637 /* Find a match for INSN in the VLE opcode table. */
639 static const struct powerpc_opcode
*
640 lookup_vle (uint64_t insn
)
642 const struct powerpc_opcode
*opcode
;
643 const struct powerpc_opcode
*opcode_end
;
647 if (op
>= 0x20 && op
<= 0x37)
649 /* This insn has a 4-bit opcode. */
652 seg
= VLE_OP_TO_SEG (op
);
654 /* Find the first match in the opcode table for this major opcode. */
655 opcode_end
= vle_opcodes
+ vle_opcd_indices
[seg
+ 1];
656 for (opcode
= vle_opcodes
+ vle_opcd_indices
[seg
];
660 uint64_t table_opcd
= opcode
->opcode
;
661 uint64_t table_mask
= opcode
->mask
;
662 bfd_boolean table_op_is_short
= PPC_OP_SE_VLE(table_mask
);
664 const unsigned char *opindex
;
665 const struct powerpc_operand
*operand
;
669 if (table_op_is_short
)
671 if ((insn2
& table_mask
) != table_opcd
)
674 /* Check validity of operands. */
676 for (opindex
= opcode
->operands
; *opindex
!= 0; ++opindex
)
678 operand
= powerpc_operands
+ *opindex
;
679 if (operand
->extract
)
680 (*operand
->extract
) (insn
, (ppc_cpu_t
)0, &invalid
);
691 /* Find a match for INSN in the SPE2 opcode table. */
693 static const struct powerpc_opcode
*
694 lookup_spe2 (uint64_t insn
)
696 const struct powerpc_opcode
*opcode
, *opcode_end
;
697 unsigned op
, xop
, seg
;
702 /* This is not SPE2 insn.
703 * All SPE2 instructions have OP=4 and differs by XOP */
706 xop
= SPE2_XOP (insn
);
707 seg
= SPE2_XOP_TO_SEG (xop
);
709 /* Find the first match in the opcode table for this major opcode. */
710 opcode_end
= spe2_opcodes
+ spe2_opcd_indices
[seg
+ 1];
711 for (opcode
= spe2_opcodes
+ spe2_opcd_indices
[seg
];
715 uint64_t table_opcd
= opcode
->opcode
;
716 uint64_t table_mask
= opcode
->mask
;
718 const unsigned char *opindex
;
719 const struct powerpc_operand
*operand
;
723 if ((insn2
& table_mask
) != table_opcd
)
726 /* Check validity of operands. */
728 for (opindex
= opcode
->operands
; *opindex
!= 0; ++opindex
)
730 operand
= powerpc_operands
+ *opindex
;
731 if (operand
->extract
)
732 (*operand
->extract
) (insn
, (ppc_cpu_t
)0, &invalid
);
743 /* Print a PowerPC or POWER instruction. */
746 print_insn_powerpc (bfd_vma memaddr
,
747 struct disassemble_info
*info
,
754 const struct powerpc_opcode
*opcode
;
755 int insn_length
= 4; /* Assume we have a normal 4-byte instruction. */
757 status
= (*info
->read_memory_func
) (memaddr
, buffer
, 4, info
);
759 /* The final instruction may be a 2-byte VLE insn. */
760 if (status
!= 0 && (dialect
& PPC_OPCODE_VLE
) != 0)
762 /* Clear buffer so unused bytes will not have garbage in them. */
763 buffer
[2] = buffer
[3] = 0;
764 status
= (*info
->read_memory_func
) (memaddr
, buffer
, 2, info
);
770 (*info
->memory_error_func
) (status
, memaddr
, info
);
775 insn
= bfd_getb32 (buffer
);
777 insn
= bfd_getl32 (buffer
);
779 /* Get the major opcode of the insn. */
781 if ((dialect
& PPC_OPCODE_POWER10
) != 0
782 && PPC_OP (insn
) == 0x1)
784 uint64_t temp_insn
, suffix
;
785 status
= (*info
->read_memory_func
) (memaddr
+ 4, buffer
, 4, info
);
789 suffix
= bfd_getb32 (buffer
);
791 suffix
= bfd_getl32 (buffer
);
792 temp_insn
= (insn
<< 32) | suffix
;
793 opcode
= lookup_prefix (temp_insn
, dialect
& ~PPC_OPCODE_ANY
);
794 if (opcode
== NULL
&& (dialect
& PPC_OPCODE_ANY
) != 0)
795 opcode
= lookup_prefix (temp_insn
, dialect
);
800 if ((info
->flags
& WIDE_OUTPUT
) != 0)
801 info
->bytes_per_line
= 8;
805 if (opcode
== NULL
&& (dialect
& PPC_OPCODE_VLE
) != 0)
807 opcode
= lookup_vle (insn
);
808 if (opcode
!= NULL
&& PPC_OP_SE_VLE (opcode
->mask
))
810 /* The operands will be fetched out of the 16-bit instruction. */
815 if (opcode
== NULL
&& insn_length
== 4)
817 if ((dialect
& PPC_OPCODE_SPE2
) != 0)
818 opcode
= lookup_spe2 (insn
);
820 opcode
= lookup_powerpc (insn
, dialect
& ~PPC_OPCODE_ANY
);
821 if (opcode
== NULL
&& (dialect
& PPC_OPCODE_ANY
) != 0)
822 opcode
= lookup_powerpc (insn
, dialect
);
827 const unsigned char *opindex
;
828 const struct powerpc_operand
*operand
;
840 bfd_boolean skip_optional
;
843 (*info
->fprintf_func
) (info
->stream
, "%s", opcode
->name
);
844 /* gdb fprintf_func doesn't return count printed. */
845 blanks
= 8 - strlen (opcode
->name
);
849 /* Now extract and print the operands. */
850 op_separator
= blanks
;
851 skip_optional
= FALSE
;
852 for (opindex
= opcode
->operands
; *opindex
!= 0; opindex
++)
856 operand
= powerpc_operands
+ *opindex
;
858 /* If all of the optional operands past this one have their
859 default value, then don't print any of them. Except in
860 raw mode, print them all. */
861 if ((operand
->flags
& PPC_OPERAND_OPTIONAL
) != 0
862 && (dialect
& PPC_OPCODE_RAW
) == 0)
865 skip_optional
= skip_optional_operands (opindex
, insn
, dialect
);
870 value
= operand_value_powerpc (operand
, insn
, dialect
);
872 if (op_separator
== need_comma
)
873 (*info
->fprintf_func
) (info
->stream
, ",");
874 else if (op_separator
== need_paren
)
875 (*info
->fprintf_func
) (info
->stream
, "(");
877 (*info
->fprintf_func
) (info
->stream
, "%*s", op_separator
, " ");
879 /* Print the operand as directed by the flags. */
880 if ((operand
->flags
& PPC_OPERAND_GPR
) != 0
881 || ((operand
->flags
& PPC_OPERAND_GPR_0
) != 0 && value
!= 0))
882 (*info
->fprintf_func
) (info
->stream
, "r%" PRId64
, value
);
883 else if ((operand
->flags
& PPC_OPERAND_FPR
) != 0)
884 (*info
->fprintf_func
) (info
->stream
, "f%" PRId64
, value
);
885 else if ((operand
->flags
& PPC_OPERAND_VR
) != 0)
886 (*info
->fprintf_func
) (info
->stream
, "v%" PRId64
, value
);
887 else if ((operand
->flags
& PPC_OPERAND_VSR
) != 0)
888 (*info
->fprintf_func
) (info
->stream
, "vs%" PRId64
, value
);
889 else if ((operand
->flags
& PPC_OPERAND_ACC
) != 0)
890 (*info
->fprintf_func
) (info
->stream
, "a%" PRId64
, value
);
891 else if ((operand
->flags
& PPC_OPERAND_RELATIVE
) != 0)
892 (*info
->print_address_func
) (memaddr
+ value
, info
);
893 else if ((operand
->flags
& PPC_OPERAND_ABSOLUTE
) != 0)
894 (*info
->print_address_func
) ((bfd_vma
) value
& 0xffffffff, info
);
895 else if ((operand
->flags
& PPC_OPERAND_FSL
) != 0)
896 (*info
->fprintf_func
) (info
->stream
, "fsl%" PRId64
, value
);
897 else if ((operand
->flags
& PPC_OPERAND_FCR
) != 0)
898 (*info
->fprintf_func
) (info
->stream
, "fcr%" PRId64
, value
);
899 else if ((operand
->flags
& PPC_OPERAND_UDI
) != 0)
900 (*info
->fprintf_func
) (info
->stream
, "%" PRId64
, value
);
901 else if ((operand
->flags
& PPC_OPERAND_CR_REG
) != 0
902 && (operand
->flags
& PPC_OPERAND_CR_BIT
) == 0
903 && (((dialect
& PPC_OPCODE_PPC
) != 0)
904 || ((dialect
& PPC_OPCODE_VLE
) != 0)))
905 (*info
->fprintf_func
) (info
->stream
, "cr%" PRId64
, value
);
906 else if ((operand
->flags
& PPC_OPERAND_CR_BIT
) != 0
907 && (operand
->flags
& PPC_OPERAND_CR_REG
) == 0
908 && (((dialect
& PPC_OPCODE_PPC
) != 0)
909 || ((dialect
& PPC_OPCODE_VLE
) != 0)))
911 static const char *cbnames
[4] = { "lt", "gt", "eq", "so" };
917 (*info
->fprintf_func
) (info
->stream
, "4*cr%d+", cr
);
919 (*info
->fprintf_func
) (info
->stream
, "%s", cbnames
[cc
]);
922 (*info
->fprintf_func
) (info
->stream
, "%" PRId64
, value
);
924 if (op_separator
== need_paren
)
925 (*info
->fprintf_func
) (info
->stream
, ")");
927 op_separator
= need_comma
;
928 if ((operand
->flags
& PPC_OPERAND_PARENS
) != 0)
929 op_separator
= need_paren
;
932 /* We have found and printed an instruction. */
936 /* We could not find a match. */
937 if (insn_length
== 4)
938 (*info
->fprintf_func
) (info
->stream
, ".long 0x%x",
939 (unsigned int) insn
);
941 (*info
->fprintf_func
) (info
->stream
, ".word 0x%x",
942 (unsigned int) insn
>> 16);
946 const disasm_options_and_args_t
*
947 disassembler_options_powerpc (void)
949 static disasm_options_and_args_t
*opts_and_args
;
951 if (opts_and_args
== NULL
)
953 size_t i
, num_options
= ARRAY_SIZE (ppc_opts
);
954 disasm_options_t
*opts
;
956 opts_and_args
= XNEW (disasm_options_and_args_t
);
957 opts_and_args
->args
= NULL
;
959 opts
= &opts_and_args
->options
;
960 opts
->name
= XNEWVEC (const char *, num_options
+ 1);
961 opts
->description
= NULL
;
963 for (i
= 0; i
< num_options
; i
++)
964 opts
->name
[i
] = ppc_opts
[i
].opt
;
965 /* The array we return must be NULL terminated. */
966 opts
->name
[i
] = NULL
;
969 return opts_and_args
;
973 print_ppc_disassembler_options (FILE *stream
)
977 fprintf (stream
, _("\n\
978 The following PPC specific disassembler options are supported for use with\n\
981 for (col
= 0, i
= 0; i
< ARRAY_SIZE (ppc_opts
); i
++)
983 col
+= fprintf (stream
, " %s,", ppc_opts
[i
].opt
);
986 fprintf (stream
, "\n");
990 fprintf (stream
, "\n");