1 /* ppc-dis.c -- Disassemble PowerPC instructions
2 Copyright (C) 1994-2020 Free Software Foundation, Inc.
3 Written by Ian Lance Taylor, Cygnus Support
5 This file is part of the GNU opcodes library.
7 This library is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3, or (at your option)
12 It is distributed in the hope that it will be useful, but WITHOUT
13 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
14 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
15 License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this file; see the file COPYING. If not, write to the
19 Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston,
20 MA 02110-1301, USA. */
24 #include "disassemble.h"
28 #include "opcode/ppc.h"
29 #include "libiberty.h"
31 /* This file provides several disassembler functions, all of which use
32 the disassembler interface defined in dis-asm.h. Several functions
33 are provided because this file handles disassembly for the PowerPC
34 in both big and little endian mode and also for the POWER (RS/6000)
36 static int print_insn_powerpc (bfd_vma
, struct disassemble_info
*, int,
41 /* Stash the result of parsing disassembler_options here. */
45 #define POWERPC_DIALECT(INFO) \
46 (((struct dis_private *) ((INFO)->private_data))->dialect)
49 /* Option string, without -m or -M prefix. */
51 /* CPU option flags. */
53 /* Flags that should stay on, even when combined with another cpu
54 option. This should only be used for generic options like
55 "-many" or "-maltivec" where it is reasonable to add some
56 capability to another cpu selection. The added flags are sticky
57 so that, for example, "-many -me500" and "-me500 -many" result in
58 the same assembler or disassembler behaviour. Do not use
59 "sticky" for specific cpus, as this will prevent that cpu's flags
60 from overriding the defaults set in powerpc_init_dialect or a
65 struct ppc_mopt ppc_opts
[] = {
66 { "403", PPC_OPCODE_PPC
| PPC_OPCODE_403
,
68 { "405", PPC_OPCODE_PPC
| PPC_OPCODE_403
| PPC_OPCODE_405
,
70 { "440", (PPC_OPCODE_PPC
| PPC_OPCODE_BOOKE
| PPC_OPCODE_440
71 | PPC_OPCODE_ISEL
| PPC_OPCODE_RFMCI
),
73 { "464", (PPC_OPCODE_PPC
| PPC_OPCODE_BOOKE
| PPC_OPCODE_440
74 | PPC_OPCODE_ISEL
| PPC_OPCODE_RFMCI
),
76 { "476", (PPC_OPCODE_PPC
| PPC_OPCODE_ISEL
| PPC_OPCODE_476
77 | PPC_OPCODE_POWER4
| PPC_OPCODE_POWER5
),
79 { "601", PPC_OPCODE_PPC
| PPC_OPCODE_601
,
81 { "603", PPC_OPCODE_PPC
,
83 { "604", PPC_OPCODE_PPC
,
85 { "620", PPC_OPCODE_PPC
| PPC_OPCODE_64
,
87 { "7400", PPC_OPCODE_PPC
| PPC_OPCODE_ALTIVEC
,
89 { "7410", PPC_OPCODE_PPC
| PPC_OPCODE_ALTIVEC
,
91 { "7450", PPC_OPCODE_PPC
| PPC_OPCODE_7450
| PPC_OPCODE_ALTIVEC
,
93 { "7455", PPC_OPCODE_PPC
| PPC_OPCODE_ALTIVEC
,
95 { "750cl", PPC_OPCODE_PPC
| PPC_OPCODE_750
| PPC_OPCODE_PPCPS
97 { "gekko", PPC_OPCODE_PPC
| PPC_OPCODE_750
| PPC_OPCODE_PPCPS
99 { "broadway", PPC_OPCODE_PPC
| PPC_OPCODE_750
| PPC_OPCODE_PPCPS
101 { "821", PPC_OPCODE_PPC
| PPC_OPCODE_860
,
103 { "850", PPC_OPCODE_PPC
| PPC_OPCODE_860
,
105 { "860", PPC_OPCODE_PPC
| PPC_OPCODE_860
,
107 { "a2", (PPC_OPCODE_PPC
| PPC_OPCODE_ISEL
| PPC_OPCODE_POWER4
108 | PPC_OPCODE_POWER5
| PPC_OPCODE_CACHELCK
| PPC_OPCODE_64
111 { "altivec", PPC_OPCODE_PPC
,
112 PPC_OPCODE_ALTIVEC
},
113 { "any", PPC_OPCODE_PPC
,
115 { "booke", PPC_OPCODE_PPC
| PPC_OPCODE_BOOKE
,
117 { "booke32", PPC_OPCODE_PPC
| PPC_OPCODE_BOOKE
,
119 { "cell", (PPC_OPCODE_PPC
| PPC_OPCODE_64
| PPC_OPCODE_POWER4
120 | PPC_OPCODE_CELL
| PPC_OPCODE_ALTIVEC
),
122 { "com", PPC_OPCODE_COMMON
,
124 { "e200z4", (PPC_OPCODE_PPC
| PPC_OPCODE_BOOKE
| PPC_OPCODE_SPE
125 | PPC_OPCODE_ISEL
| PPC_OPCODE_EFS
| PPC_OPCODE_BRLOCK
126 | PPC_OPCODE_PMR
| PPC_OPCODE_CACHELCK
| PPC_OPCODE_RFMCI
127 | PPC_OPCODE_E500
| PPC_OPCODE_VLE
| PPC_OPCODE_E200Z4
128 | PPC_OPCODE_EFS2
| PPC_OPCODE_LSP
),
130 { "e300", PPC_OPCODE_PPC
| PPC_OPCODE_E300
,
132 { "e500", (PPC_OPCODE_PPC
| PPC_OPCODE_BOOKE
| PPC_OPCODE_SPE
133 | PPC_OPCODE_ISEL
| PPC_OPCODE_EFS
| PPC_OPCODE_BRLOCK
134 | PPC_OPCODE_PMR
| PPC_OPCODE_CACHELCK
| PPC_OPCODE_RFMCI
137 { "e500mc", (PPC_OPCODE_PPC
| PPC_OPCODE_BOOKE
| PPC_OPCODE_ISEL
138 | PPC_OPCODE_PMR
| PPC_OPCODE_CACHELCK
| PPC_OPCODE_RFMCI
139 | PPC_OPCODE_E500MC
),
141 { "e500mc64", (PPC_OPCODE_PPC
| PPC_OPCODE_BOOKE
| PPC_OPCODE_ISEL
142 | PPC_OPCODE_PMR
| PPC_OPCODE_CACHELCK
| PPC_OPCODE_RFMCI
143 | PPC_OPCODE_E500MC
| PPC_OPCODE_64
| PPC_OPCODE_POWER5
144 | PPC_OPCODE_POWER6
| PPC_OPCODE_POWER7
),
146 { "e5500", (PPC_OPCODE_PPC
| PPC_OPCODE_BOOKE
| PPC_OPCODE_ISEL
147 | PPC_OPCODE_PMR
| PPC_OPCODE_CACHELCK
| PPC_OPCODE_RFMCI
148 | PPC_OPCODE_E500MC
| PPC_OPCODE_64
| PPC_OPCODE_POWER4
149 | PPC_OPCODE_POWER5
| PPC_OPCODE_POWER6
| PPC_OPCODE_POWER7
),
151 { "e6500", (PPC_OPCODE_PPC
| PPC_OPCODE_BOOKE
| PPC_OPCODE_ISEL
152 | PPC_OPCODE_PMR
| PPC_OPCODE_CACHELCK
| PPC_OPCODE_RFMCI
153 | PPC_OPCODE_E500MC
| PPC_OPCODE_64
| PPC_OPCODE_ALTIVEC
154 | PPC_OPCODE_E6500
| PPC_OPCODE_TMR
| PPC_OPCODE_POWER4
155 | PPC_OPCODE_POWER5
| PPC_OPCODE_POWER6
| PPC_OPCODE_POWER7
),
157 { "e500x2", (PPC_OPCODE_PPC
| PPC_OPCODE_BOOKE
| PPC_OPCODE_SPE
158 | PPC_OPCODE_ISEL
| PPC_OPCODE_EFS
| PPC_OPCODE_BRLOCK
159 | PPC_OPCODE_PMR
| PPC_OPCODE_CACHELCK
| PPC_OPCODE_RFMCI
162 { "efs", PPC_OPCODE_PPC
| PPC_OPCODE_EFS
,
164 { "efs2", PPC_OPCODE_PPC
| PPC_OPCODE_EFS
| PPC_OPCODE_EFS2
,
166 { "power4", PPC_OPCODE_PPC
| PPC_OPCODE_64
| PPC_OPCODE_POWER4
,
168 { "power5", (PPC_OPCODE_PPC
| PPC_OPCODE_64
| PPC_OPCODE_POWER4
169 | PPC_OPCODE_POWER5
),
171 { "power6", (PPC_OPCODE_PPC
| PPC_OPCODE_64
| PPC_OPCODE_POWER4
172 | PPC_OPCODE_POWER5
| PPC_OPCODE_POWER6
| PPC_OPCODE_ALTIVEC
),
174 { "power7", (PPC_OPCODE_PPC
| PPC_OPCODE_ISEL
| PPC_OPCODE_64
175 | PPC_OPCODE_POWER4
| PPC_OPCODE_POWER5
| PPC_OPCODE_POWER6
176 | PPC_OPCODE_POWER7
| PPC_OPCODE_ALTIVEC
| PPC_OPCODE_VSX
),
178 { "power8", (PPC_OPCODE_PPC
| PPC_OPCODE_ISEL
| PPC_OPCODE_64
179 | PPC_OPCODE_POWER4
| PPC_OPCODE_POWER5
| PPC_OPCODE_POWER6
180 | PPC_OPCODE_POWER7
| PPC_OPCODE_POWER8
181 | PPC_OPCODE_ALTIVEC
| PPC_OPCODE_VSX
),
183 { "power9", (PPC_OPCODE_PPC
| PPC_OPCODE_ISEL
| PPC_OPCODE_64
184 | PPC_OPCODE_POWER4
| PPC_OPCODE_POWER5
| PPC_OPCODE_POWER6
185 | PPC_OPCODE_POWER7
| PPC_OPCODE_POWER8
| PPC_OPCODE_POWER9
186 | PPC_OPCODE_ALTIVEC
| PPC_OPCODE_VSX
),
188 { "power10", (PPC_OPCODE_PPC
| PPC_OPCODE_ISEL
| PPC_OPCODE_64
189 | PPC_OPCODE_POWER4
| PPC_OPCODE_POWER5
| PPC_OPCODE_POWER6
190 | PPC_OPCODE_POWER7
| PPC_OPCODE_POWER8
| PPC_OPCODE_POWER9
191 | PPC_OPCODE_POWER10
| PPC_OPCODE_ALTIVEC
| PPC_OPCODE_VSX
),
193 { "future", (PPC_OPCODE_PPC
| PPC_OPCODE_ISEL
| PPC_OPCODE_64
194 | PPC_OPCODE_POWER4
| PPC_OPCODE_POWER5
| PPC_OPCODE_POWER6
195 | PPC_OPCODE_POWER7
| PPC_OPCODE_POWER8
| PPC_OPCODE_POWER9
196 | PPC_OPCODE_POWER10
| PPC_OPCODE_ALTIVEC
| PPC_OPCODE_VSX
),
198 { "ppc", PPC_OPCODE_PPC
,
200 { "ppc32", PPC_OPCODE_PPC
,
202 { "32", PPC_OPCODE_PPC
,
204 { "ppc64", PPC_OPCODE_PPC
| PPC_OPCODE_64
,
206 { "64", PPC_OPCODE_PPC
| PPC_OPCODE_64
,
208 { "ppc64bridge", PPC_OPCODE_PPC
| PPC_OPCODE_64_BRIDGE
,
210 { "ppcps", PPC_OPCODE_PPC
| PPC_OPCODE_PPCPS
,
212 { "pwr", PPC_OPCODE_POWER
,
214 { "pwr2", PPC_OPCODE_POWER
| PPC_OPCODE_POWER2
,
216 { "pwr4", PPC_OPCODE_PPC
| PPC_OPCODE_64
| PPC_OPCODE_POWER4
,
218 { "pwr5", (PPC_OPCODE_PPC
| PPC_OPCODE_64
| PPC_OPCODE_POWER4
219 | PPC_OPCODE_POWER5
),
221 { "pwr5x", (PPC_OPCODE_PPC
| PPC_OPCODE_64
| PPC_OPCODE_POWER4
222 | PPC_OPCODE_POWER5
),
224 { "pwr6", (PPC_OPCODE_PPC
| PPC_OPCODE_64
| PPC_OPCODE_POWER4
225 | PPC_OPCODE_POWER5
| PPC_OPCODE_POWER6
| PPC_OPCODE_ALTIVEC
),
227 { "pwr7", (PPC_OPCODE_PPC
| PPC_OPCODE_ISEL
| PPC_OPCODE_64
228 | PPC_OPCODE_POWER4
| PPC_OPCODE_POWER5
| PPC_OPCODE_POWER6
229 | PPC_OPCODE_POWER7
| PPC_OPCODE_ALTIVEC
| PPC_OPCODE_VSX
),
231 { "pwr8", (PPC_OPCODE_PPC
| PPC_OPCODE_ISEL
| PPC_OPCODE_64
232 | PPC_OPCODE_POWER4
| PPC_OPCODE_POWER5
| PPC_OPCODE_POWER6
233 | PPC_OPCODE_POWER7
| PPC_OPCODE_POWER8
234 | PPC_OPCODE_ALTIVEC
| PPC_OPCODE_VSX
),
236 { "pwr9", (PPC_OPCODE_PPC
| PPC_OPCODE_ISEL
| PPC_OPCODE_64
237 | PPC_OPCODE_POWER4
| PPC_OPCODE_POWER5
| PPC_OPCODE_POWER6
238 | PPC_OPCODE_POWER7
| PPC_OPCODE_POWER8
| PPC_OPCODE_POWER9
239 | PPC_OPCODE_ALTIVEC
| PPC_OPCODE_VSX
),
241 { "pwr10", (PPC_OPCODE_PPC
| PPC_OPCODE_ISEL
| PPC_OPCODE_64
242 | PPC_OPCODE_POWER4
| PPC_OPCODE_POWER5
| PPC_OPCODE_POWER6
243 | PPC_OPCODE_POWER7
| PPC_OPCODE_POWER8
| PPC_OPCODE_POWER9
244 | PPC_OPCODE_POWER10
| PPC_OPCODE_ALTIVEC
| PPC_OPCODE_VSX
),
246 { "pwrx", PPC_OPCODE_POWER
| PPC_OPCODE_POWER2
,
248 { "raw", PPC_OPCODE_PPC
,
250 { "spe", PPC_OPCODE_PPC
| PPC_OPCODE_EFS
,
252 { "spe2", PPC_OPCODE_PPC
| PPC_OPCODE_EFS
| PPC_OPCODE_EFS2
| PPC_OPCODE_SPE
,
254 { "titan", (PPC_OPCODE_PPC
| PPC_OPCODE_BOOKE
| PPC_OPCODE_PMR
255 | PPC_OPCODE_RFMCI
| PPC_OPCODE_TITAN
),
257 { "vle", (PPC_OPCODE_PPC
| PPC_OPCODE_BOOKE
| PPC_OPCODE_SPE
258 | PPC_OPCODE_ISEL
| PPC_OPCODE_EFS
| PPC_OPCODE_BRLOCK
259 | PPC_OPCODE_PMR
| PPC_OPCODE_CACHELCK
| PPC_OPCODE_RFMCI
260 | PPC_OPCODE_LSP
| PPC_OPCODE_EFS2
| PPC_OPCODE_SPE2
),
262 { "vsx", PPC_OPCODE_PPC
,
266 /* Switch between Booke and VLE dialects for interlinked dumps. */
268 get_powerpc_dialect (struct disassemble_info
*info
)
270 ppc_cpu_t dialect
= 0;
272 if (info
->private_data
)
273 dialect
= POWERPC_DIALECT (info
);
275 /* Disassemble according to the section headers flags for VLE-mode. */
276 if (dialect
& PPC_OPCODE_VLE
277 && info
->section
!= NULL
&& info
->section
->owner
!= NULL
278 && bfd_get_flavour (info
->section
->owner
) == bfd_target_elf_flavour
279 && elf_object_id (info
->section
->owner
) == PPC32_ELF_DATA
280 && (elf_section_flags (info
->section
) & SHF_PPC_VLE
) != 0)
283 return dialect
& ~ PPC_OPCODE_VLE
;
286 /* Handle -m and -M options that set cpu type, and .machine arg. */
289 ppc_parse_cpu (ppc_cpu_t ppc_cpu
, ppc_cpu_t
*sticky
, const char *arg
)
293 for (i
= 0; i
< ARRAY_SIZE (ppc_opts
); i
++)
294 if (disassembler_options_cmp (ppc_opts
[i
].opt
, arg
) == 0)
296 if (ppc_opts
[i
].sticky
)
298 *sticky
|= ppc_opts
[i
].sticky
;
299 if ((ppc_cpu
& ~*sticky
) != 0)
302 ppc_cpu
= ppc_opts
[i
].cpu
;
305 if (i
>= ARRAY_SIZE (ppc_opts
))
312 /* Determine which set of machines to disassemble for. */
315 powerpc_init_dialect (struct disassemble_info
*info
)
317 ppc_cpu_t dialect
= 0;
318 ppc_cpu_t sticky
= 0;
319 struct dis_private
*priv
= calloc (sizeof (*priv
), 1);
326 case bfd_mach_ppc_403
:
327 case bfd_mach_ppc_403gc
:
328 dialect
= ppc_parse_cpu (dialect
, &sticky
, "403");
330 case bfd_mach_ppc_405
:
331 dialect
= ppc_parse_cpu (dialect
, &sticky
, "405");
333 case bfd_mach_ppc_601
:
334 dialect
= ppc_parse_cpu (dialect
, &sticky
, "601");
336 case bfd_mach_ppc_750
:
337 dialect
= ppc_parse_cpu (dialect
, &sticky
, "750cl");
339 case bfd_mach_ppc_a35
:
340 case bfd_mach_ppc_rs64ii
:
341 case bfd_mach_ppc_rs64iii
:
342 dialect
= ppc_parse_cpu (dialect
, &sticky
, "pwr2") | PPC_OPCODE_64
;
344 case bfd_mach_ppc_e500
:
345 dialect
= ppc_parse_cpu (dialect
, &sticky
, "e500");
347 case bfd_mach_ppc_e500mc
:
348 dialect
= ppc_parse_cpu (dialect
, &sticky
, "e500mc");
350 case bfd_mach_ppc_e500mc64
:
351 dialect
= ppc_parse_cpu (dialect
, &sticky
, "e500mc64");
353 case bfd_mach_ppc_e5500
:
354 dialect
= ppc_parse_cpu (dialect
, &sticky
, "e5500");
356 case bfd_mach_ppc_e6500
:
357 dialect
= ppc_parse_cpu (dialect
, &sticky
, "e6500");
359 case bfd_mach_ppc_titan
:
360 dialect
= ppc_parse_cpu (dialect
, &sticky
, "titan");
362 case bfd_mach_ppc_vle
:
363 dialect
= ppc_parse_cpu (dialect
, &sticky
, "vle");
366 if (info
->arch
== bfd_arch_powerpc
)
367 dialect
= ppc_parse_cpu (dialect
, &sticky
, "power10") | PPC_OPCODE_ANY
;
369 dialect
= ppc_parse_cpu (dialect
, &sticky
, "pwr");
374 FOR_EACH_DISASSEMBLER_OPTION (opt
, info
->disassembler_options
)
376 ppc_cpu_t new_cpu
= 0;
378 if (disassembler_options_cmp (opt
, "32") == 0)
379 dialect
&= ~(ppc_cpu_t
) PPC_OPCODE_64
;
380 else if (disassembler_options_cmp (opt
, "64") == 0)
381 dialect
|= PPC_OPCODE_64
;
382 else if ((new_cpu
= ppc_parse_cpu (dialect
, &sticky
, opt
)) != 0)
385 /* xgettext: c-format */
386 opcodes_error_handler (_("warning: ignoring unknown -M%s option"), opt
);
389 info
->private_data
= priv
;
390 POWERPC_DIALECT(info
) = dialect
;
393 #define PPC_OPCD_SEGS (1 + PPC_OP (-1))
394 static unsigned short powerpc_opcd_indices
[PPC_OPCD_SEGS
+ 1];
395 #define PREFIX_OPCD_SEGS (1 + PPC_PREFIX_SEG (-1))
396 static unsigned short prefix_opcd_indices
[PREFIX_OPCD_SEGS
+ 1];
397 #define VLE_OPCD_SEGS (1 + VLE_OP_TO_SEG (VLE_OP (-1, 0xffff)))
398 static unsigned short vle_opcd_indices
[VLE_OPCD_SEGS
+ 1];
399 #define SPE2_OPCD_SEGS (1 + SPE2_XOP_TO_SEG (SPE2_XOP (-1)))
400 static unsigned short spe2_opcd_indices
[SPE2_OPCD_SEGS
+ 1];
403 ppc_symbol_is_valid (asymbol
*sym
,
404 struct disassemble_info
*info ATTRIBUTE_UNUSED
)
406 elf_symbol_type
* est
;
411 est
= elf_symbol_from (sym
);
413 /* Ignore ELF hidden, local, no-type symbols.
414 These are generated by annobin. */
416 && ELF_ST_VISIBILITY (est
->internal_elf_sym
.st_other
) == STV_HIDDEN
417 && ELF_ST_BIND (est
->internal_elf_sym
.st_info
) == STB_LOCAL
418 && ELF_ST_TYPE (est
->internal_elf_sym
.st_info
) == STT_NOTYPE
)
424 /* Calculate opcode table indices to speed up disassembly,
428 disassemble_init_powerpc (struct disassemble_info
*info
)
430 info
->symbol_is_valid
= ppc_symbol_is_valid
;
432 if (powerpc_opcd_indices
[PPC_OPCD_SEGS
] == 0)
434 unsigned seg
, idx
, op
;
437 for (seg
= 0, idx
= 0; seg
<= PPC_OPCD_SEGS
; seg
++)
439 powerpc_opcd_indices
[seg
] = idx
;
440 for (; idx
< powerpc_num_opcodes
; idx
++)
441 if (seg
< PPC_OP (powerpc_opcodes
[idx
].opcode
))
445 /* 64-bit prefix opcodes */
446 for (seg
= 0, idx
= 0; seg
<= PREFIX_OPCD_SEGS
; seg
++)
448 prefix_opcd_indices
[seg
] = idx
;
449 for (; idx
< prefix_num_opcodes
; idx
++)
450 if (seg
< PPC_PREFIX_SEG (prefix_opcodes
[idx
].opcode
))
455 for (seg
= 0, idx
= 0; seg
<= VLE_OPCD_SEGS
; seg
++)
457 vle_opcd_indices
[seg
] = idx
;
458 for (; idx
< vle_num_opcodes
; idx
++)
460 op
= VLE_OP (vle_opcodes
[idx
].opcode
, vle_opcodes
[idx
].mask
);
461 if (seg
< VLE_OP_TO_SEG (op
))
467 for (seg
= 0, idx
= 0; seg
<= SPE2_OPCD_SEGS
; seg
++)
469 spe2_opcd_indices
[seg
] = idx
;
470 for (; idx
< spe2_num_opcodes
; idx
++)
472 op
= SPE2_XOP (spe2_opcodes
[idx
].opcode
);
473 if (seg
< SPE2_XOP_TO_SEG (op
))
479 powerpc_init_dialect (info
);
482 /* Print a big endian PowerPC instruction. */
485 print_insn_big_powerpc (bfd_vma memaddr
, struct disassemble_info
*info
)
487 return print_insn_powerpc (memaddr
, info
, 1, get_powerpc_dialect (info
));
490 /* Print a little endian PowerPC instruction. */
493 print_insn_little_powerpc (bfd_vma memaddr
, struct disassemble_info
*info
)
495 return print_insn_powerpc (memaddr
, info
, 0, get_powerpc_dialect (info
));
498 /* Extract the operand value from the PowerPC or POWER instruction. */
501 operand_value_powerpc (const struct powerpc_operand
*operand
,
502 uint64_t insn
, ppc_cpu_t dialect
)
506 /* Extract the value from the instruction. */
507 if (operand
->extract
)
508 value
= (*operand
->extract
) (insn
, dialect
, &invalid
);
511 if (operand
->shift
>= 0)
512 value
= (insn
>> operand
->shift
) & operand
->bitm
;
514 value
= (insn
<< -operand
->shift
) & operand
->bitm
;
515 if ((operand
->flags
& PPC_OPERAND_SIGNED
) != 0)
517 /* BITM is always some number of zeros followed by some
518 number of ones, followed by some number of zeros. */
519 uint64_t top
= operand
->bitm
;
520 /* top & -top gives the rightmost 1 bit, so this
521 fills in any trailing zeros. */
522 top
|= (top
& -top
) - 1;
524 value
= (value
^ top
) - top
;
531 /* Determine whether the optional operand(s) should be printed. */
534 skip_optional_operands (const unsigned char *opindex
,
535 uint64_t insn
, ppc_cpu_t dialect
)
537 const struct powerpc_operand
*operand
;
540 for (num_optional
= 0; *opindex
!= 0; opindex
++)
542 operand
= &powerpc_operands
[*opindex
];
543 if ((operand
->flags
& PPC_OPERAND_NEXT
) != 0)
545 if ((operand
->flags
& PPC_OPERAND_OPTIONAL
) != 0)
547 /* Negative count is used as a flag to extract function. */
549 if (operand_value_powerpc (operand
, insn
, dialect
)
550 != ppc_optional_operand_value (operand
, insn
, dialect
,
559 /* Find a match for INSN in the opcode table, given machine DIALECT. */
561 static const struct powerpc_opcode
*
562 lookup_powerpc (uint64_t insn
, ppc_cpu_t dialect
)
564 const struct powerpc_opcode
*opcode
, *opcode_end
, *last
;
567 /* Get the major opcode of the instruction. */
570 /* Find the first match in the opcode table for this major opcode. */
571 opcode_end
= powerpc_opcodes
+ powerpc_opcd_indices
[op
+ 1];
573 for (opcode
= powerpc_opcodes
+ powerpc_opcd_indices
[op
];
577 const unsigned char *opindex
;
578 const struct powerpc_operand
*operand
;
581 if ((insn
& opcode
->mask
) != opcode
->opcode
582 || ((dialect
& PPC_OPCODE_ANY
) == 0
583 && ((opcode
->flags
& dialect
) == 0
584 || (opcode
->deprecated
& dialect
) != 0)))
587 /* Check validity of operands. */
589 for (opindex
= opcode
->operands
; *opindex
!= 0; opindex
++)
591 operand
= powerpc_operands
+ *opindex
;
592 if (operand
->extract
)
593 (*operand
->extract
) (insn
, dialect
, &invalid
);
598 if ((dialect
& PPC_OPCODE_RAW
) == 0)
601 /* The raw machine insn is one that is not a specialization. */
603 || (last
->mask
& ~opcode
->mask
) != 0)
610 /* Find a match for INSN in the PREFIX opcode table. */
612 static const struct powerpc_opcode
*
613 lookup_prefix (uint64_t insn
, ppc_cpu_t dialect
)
615 const struct powerpc_opcode
*opcode
, *opcode_end
, *last
;
618 /* Get the opcode segment of the instruction. */
619 seg
= PPC_PREFIX_SEG (insn
);
621 /* Find the first match in the opcode table for this major opcode. */
622 opcode_end
= prefix_opcodes
+ prefix_opcd_indices
[seg
+ 1];
624 for (opcode
= prefix_opcodes
+ prefix_opcd_indices
[seg
];
628 const unsigned char *opindex
;
629 const struct powerpc_operand
*operand
;
632 if ((insn
& opcode
->mask
) != opcode
->opcode
633 || ((dialect
& PPC_OPCODE_ANY
) == 0
634 && ((opcode
->flags
& dialect
) == 0
635 || (opcode
->deprecated
& dialect
) != 0)))
638 /* Check validity of operands. */
640 for (opindex
= opcode
->operands
; *opindex
!= 0; opindex
++)
642 operand
= powerpc_operands
+ *opindex
;
643 if (operand
->extract
)
644 (*operand
->extract
) (insn
, dialect
, &invalid
);
649 if ((dialect
& PPC_OPCODE_RAW
) == 0)
652 /* The raw machine insn is one that is not a specialization. */
654 || (last
->mask
& ~opcode
->mask
) != 0)
661 /* Find a match for INSN in the VLE opcode table. */
663 static const struct powerpc_opcode
*
664 lookup_vle (uint64_t insn
)
666 const struct powerpc_opcode
*opcode
;
667 const struct powerpc_opcode
*opcode_end
;
671 if (op
>= 0x20 && op
<= 0x37)
673 /* This insn has a 4-bit opcode. */
676 seg
= VLE_OP_TO_SEG (op
);
678 /* Find the first match in the opcode table for this major opcode. */
679 opcode_end
= vle_opcodes
+ vle_opcd_indices
[seg
+ 1];
680 for (opcode
= vle_opcodes
+ vle_opcd_indices
[seg
];
684 uint64_t table_opcd
= opcode
->opcode
;
685 uint64_t table_mask
= opcode
->mask
;
686 bfd_boolean table_op_is_short
= PPC_OP_SE_VLE(table_mask
);
688 const unsigned char *opindex
;
689 const struct powerpc_operand
*operand
;
693 if (table_op_is_short
)
695 if ((insn2
& table_mask
) != table_opcd
)
698 /* Check validity of operands. */
700 for (opindex
= opcode
->operands
; *opindex
!= 0; ++opindex
)
702 operand
= powerpc_operands
+ *opindex
;
703 if (operand
->extract
)
704 (*operand
->extract
) (insn
, (ppc_cpu_t
)0, &invalid
);
715 /* Find a match for INSN in the SPE2 opcode table. */
717 static const struct powerpc_opcode
*
718 lookup_spe2 (uint64_t insn
)
720 const struct powerpc_opcode
*opcode
, *opcode_end
;
721 unsigned op
, xop
, seg
;
726 /* This is not SPE2 insn.
727 * All SPE2 instructions have OP=4 and differs by XOP */
730 xop
= SPE2_XOP (insn
);
731 seg
= SPE2_XOP_TO_SEG (xop
);
733 /* Find the first match in the opcode table for this major opcode. */
734 opcode_end
= spe2_opcodes
+ spe2_opcd_indices
[seg
+ 1];
735 for (opcode
= spe2_opcodes
+ spe2_opcd_indices
[seg
];
739 uint64_t table_opcd
= opcode
->opcode
;
740 uint64_t table_mask
= opcode
->mask
;
742 const unsigned char *opindex
;
743 const struct powerpc_operand
*operand
;
747 if ((insn2
& table_mask
) != table_opcd
)
750 /* Check validity of operands. */
752 for (opindex
= opcode
->operands
; *opindex
!= 0; ++opindex
)
754 operand
= powerpc_operands
+ *opindex
;
755 if (operand
->extract
)
756 (*operand
->extract
) (insn
, (ppc_cpu_t
)0, &invalid
);
767 /* Print a PowerPC or POWER instruction. */
770 print_insn_powerpc (bfd_vma memaddr
,
771 struct disassemble_info
*info
,
778 const struct powerpc_opcode
*opcode
;
779 int insn_length
= 4; /* Assume we have a normal 4-byte instruction. */
781 status
= (*info
->read_memory_func
) (memaddr
, buffer
, 4, info
);
783 /* The final instruction may be a 2-byte VLE insn. */
784 if (status
!= 0 && (dialect
& PPC_OPCODE_VLE
) != 0)
786 /* Clear buffer so unused bytes will not have garbage in them. */
787 buffer
[2] = buffer
[3] = 0;
788 status
= (*info
->read_memory_func
) (memaddr
, buffer
, 2, info
);
794 (*info
->memory_error_func
) (status
, memaddr
, info
);
799 insn
= bfd_getb32 (buffer
);
801 insn
= bfd_getl32 (buffer
);
803 /* Get the major opcode of the insn. */
805 if ((dialect
& PPC_OPCODE_POWER10
) != 0
806 && PPC_OP (insn
) == 0x1)
808 uint64_t temp_insn
, suffix
;
809 status
= (*info
->read_memory_func
) (memaddr
+ 4, buffer
, 4, info
);
813 suffix
= bfd_getb32 (buffer
);
815 suffix
= bfd_getl32 (buffer
);
816 temp_insn
= (insn
<< 32) | suffix
;
817 opcode
= lookup_prefix (temp_insn
, dialect
& ~PPC_OPCODE_ANY
);
818 if (opcode
== NULL
&& (dialect
& PPC_OPCODE_ANY
) != 0)
819 opcode
= lookup_prefix (temp_insn
, dialect
);
824 if ((info
->flags
& WIDE_OUTPUT
) != 0)
825 info
->bytes_per_line
= 8;
829 if (opcode
== NULL
&& (dialect
& PPC_OPCODE_VLE
) != 0)
831 opcode
= lookup_vle (insn
);
832 if (opcode
!= NULL
&& PPC_OP_SE_VLE (opcode
->mask
))
834 /* The operands will be fetched out of the 16-bit instruction. */
839 if (opcode
== NULL
&& insn_length
== 4)
841 if ((dialect
& PPC_OPCODE_SPE2
) != 0)
842 opcode
= lookup_spe2 (insn
);
844 opcode
= lookup_powerpc (insn
, dialect
& ~PPC_OPCODE_ANY
);
845 if (opcode
== NULL
&& (dialect
& PPC_OPCODE_ANY
) != 0)
846 opcode
= lookup_powerpc (insn
, dialect
);
851 const unsigned char *opindex
;
852 const struct powerpc_operand
*operand
;
864 bfd_boolean skip_optional
;
867 (*info
->fprintf_func
) (info
->stream
, "%s", opcode
->name
);
868 /* gdb fprintf_func doesn't return count printed. */
869 blanks
= 8 - strlen (opcode
->name
);
873 /* Now extract and print the operands. */
874 op_separator
= blanks
;
875 skip_optional
= FALSE
;
876 for (opindex
= opcode
->operands
; *opindex
!= 0; opindex
++)
880 operand
= powerpc_operands
+ *opindex
;
882 /* If all of the optional operands past this one have their
883 default value, then don't print any of them. Except in
884 raw mode, print them all. */
885 if ((operand
->flags
& PPC_OPERAND_OPTIONAL
) != 0
886 && (dialect
& PPC_OPCODE_RAW
) == 0)
889 skip_optional
= skip_optional_operands (opindex
, insn
, dialect
);
894 value
= operand_value_powerpc (operand
, insn
, dialect
);
896 if (op_separator
== need_comma
)
897 (*info
->fprintf_func
) (info
->stream
, ",");
898 else if (op_separator
== need_paren
)
899 (*info
->fprintf_func
) (info
->stream
, "(");
901 (*info
->fprintf_func
) (info
->stream
, "%*s", op_separator
, " ");
903 /* Print the operand as directed by the flags. */
904 if ((operand
->flags
& PPC_OPERAND_GPR
) != 0
905 || ((operand
->flags
& PPC_OPERAND_GPR_0
) != 0 && value
!= 0))
906 (*info
->fprintf_func
) (info
->stream
, "r%" PRId64
, value
);
907 else if ((operand
->flags
& PPC_OPERAND_FPR
) != 0)
908 (*info
->fprintf_func
) (info
->stream
, "f%" PRId64
, value
);
909 else if ((operand
->flags
& PPC_OPERAND_VR
) != 0)
910 (*info
->fprintf_func
) (info
->stream
, "v%" PRId64
, value
);
911 else if ((operand
->flags
& PPC_OPERAND_VSR
) != 0)
912 (*info
->fprintf_func
) (info
->stream
, "vs%" PRId64
, value
);
913 else if ((operand
->flags
& PPC_OPERAND_ACC
) != 0)
914 (*info
->fprintf_func
) (info
->stream
, "a%" PRId64
, value
);
915 else if ((operand
->flags
& PPC_OPERAND_RELATIVE
) != 0)
916 (*info
->print_address_func
) (memaddr
+ value
, info
);
917 else if ((operand
->flags
& PPC_OPERAND_ABSOLUTE
) != 0)
918 (*info
->print_address_func
) ((bfd_vma
) value
& 0xffffffff, info
);
919 else if ((operand
->flags
& PPC_OPERAND_FSL
) != 0)
920 (*info
->fprintf_func
) (info
->stream
, "fsl%" PRId64
, value
);
921 else if ((operand
->flags
& PPC_OPERAND_FCR
) != 0)
922 (*info
->fprintf_func
) (info
->stream
, "fcr%" PRId64
, value
);
923 else if ((operand
->flags
& PPC_OPERAND_UDI
) != 0)
924 (*info
->fprintf_func
) (info
->stream
, "%" PRId64
, value
);
925 else if ((operand
->flags
& PPC_OPERAND_CR_REG
) != 0
926 && (operand
->flags
& PPC_OPERAND_CR_BIT
) == 0
927 && (((dialect
& PPC_OPCODE_PPC
) != 0)
928 || ((dialect
& PPC_OPCODE_VLE
) != 0)))
929 (*info
->fprintf_func
) (info
->stream
, "cr%" PRId64
, value
);
930 else if ((operand
->flags
& PPC_OPERAND_CR_BIT
) != 0
931 && (operand
->flags
& PPC_OPERAND_CR_REG
) == 0
932 && (((dialect
& PPC_OPCODE_PPC
) != 0)
933 || ((dialect
& PPC_OPCODE_VLE
) != 0)))
935 static const char *cbnames
[4] = { "lt", "gt", "eq", "so" };
941 (*info
->fprintf_func
) (info
->stream
, "4*cr%d+", cr
);
943 (*info
->fprintf_func
) (info
->stream
, "%s", cbnames
[cc
]);
946 (*info
->fprintf_func
) (info
->stream
, "%" PRId64
, value
);
948 if (op_separator
== need_paren
)
949 (*info
->fprintf_func
) (info
->stream
, ")");
951 op_separator
= need_comma
;
952 if ((operand
->flags
& PPC_OPERAND_PARENS
) != 0)
953 op_separator
= need_paren
;
956 /* We have found and printed an instruction. */
960 /* We could not find a match. */
961 if (insn_length
== 4)
962 (*info
->fprintf_func
) (info
->stream
, ".long 0x%x",
963 (unsigned int) insn
);
965 (*info
->fprintf_func
) (info
->stream
, ".word 0x%x",
966 (unsigned int) insn
>> 16);
970 const disasm_options_and_args_t
*
971 disassembler_options_powerpc (void)
973 static disasm_options_and_args_t
*opts_and_args
;
975 if (opts_and_args
== NULL
)
977 size_t i
, num_options
= ARRAY_SIZE (ppc_opts
);
978 disasm_options_t
*opts
;
980 opts_and_args
= XNEW (disasm_options_and_args_t
);
981 opts_and_args
->args
= NULL
;
983 opts
= &opts_and_args
->options
;
984 opts
->name
= XNEWVEC (const char *, num_options
+ 1);
985 opts
->description
= NULL
;
987 for (i
= 0; i
< num_options
; i
++)
988 opts
->name
[i
] = ppc_opts
[i
].opt
;
989 /* The array we return must be NULL terminated. */
990 opts
->name
[i
] = NULL
;
993 return opts_and_args
;
997 print_ppc_disassembler_options (FILE *stream
)
1001 fprintf (stream
, _("\n\
1002 The following PPC specific disassembler options are supported for use with\n\
1003 the -M switch:\n"));
1005 for (col
= 0, i
= 0; i
< ARRAY_SIZE (ppc_opts
); i
++)
1007 col
+= fprintf (stream
, " %s,", ppc_opts
[i
].opt
);
1010 fprintf (stream
, "\n");
1014 fprintf (stream
, "\n");