opcodes/ppc-dis.c

   1 /* ppc-dis.c -- Disassemble PowerPC instructions
   2    Copyright (C) 1994-2018 Free Software Foundation, Inc.
   3    Written by Ian Lance Taylor, Cygnus Support
   4
   5    This file is part of the GNU opcodes library.
   6
   7    This library is free software; you can redistribute it and/or modify
   8    it under the terms of the GNU General Public License as published by
   9    the Free Software Foundation; either version 3, or (at your option)
  10    any later version.
  11
  12    It is distributed in the hope that it will be useful, but WITHOUT
  13    ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  14    or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
  15    License for more details.
  16
  17    You should have received a copy of the GNU General Public License
  18    along with this file; see the file COPYING.  If not, write to the
  19    Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston,
  20    MA 02110-1301, USA.  */
  21
  22 #include "sysdep.h"
  23 #include <stdio.h>
  24 #include "disassemble.h"
  25 #include "elf-bfd.h"
  26 #include "elf/ppc.h"
  27 #include "opintl.h"
  28 #include "opcode/ppc.h"
  29 #include "libiberty.h"
  30
  31 /* This file provides several disassembler functions, all of which use
  32    the disassembler interface defined in dis-asm.h.  Several functions
  33    are provided because this file handles disassembly for the PowerPC
  34    in both big and little endian mode and also for the POWER (RS/6000)
  35    chip.  */
  36 static int print_insn_powerpc (bfd_vma, struct disassemble_info *, int,
  37                                ppc_cpu_t);
  38
  39 struct dis_private
  40 {
  41   /* Stash the result of parsing disassembler_options here.  */
  42   ppc_cpu_t dialect;
  43 } private;
  44
  45 #define POWERPC_DIALECT(INFO) \
  46   (((struct dis_private *) ((INFO)->private_data))->dialect)
  47
  48 struct ppc_mopt {
  49   /* Option string, without -m or -M prefix.  */
  50   const char *opt;
  51   /* CPU option flags.  */
  52   ppc_cpu_t cpu;
  53   /* Flags that should stay on, even when combined with another cpu
  54      option.  This should only be used for generic options like
  55      "-many" or "-maltivec" where it is reasonable to add some
  56      capability to another cpu selection.  The added flags are sticky
  57      so that, for example, "-many -me500" and "-me500 -many" result in
  58      the same assembler or disassembler behaviour.  Do not use
  59      "sticky" for specific cpus, as this will prevent that cpu's flags
  60      from overriding the defaults set in powerpc_init_dialect or a
  61      prior -m option.  */
  62   ppc_cpu_t sticky;
  63 };
  64
  65 struct ppc_mopt ppc_opts[] = {
  66   { "403",     PPC_OPCODE_PPC | PPC_OPCODE_403,
  67     0 },
  68   { "405",     PPC_OPCODE_PPC | PPC_OPCODE_403 | PPC_OPCODE_405,
  69     0 },
  70   { "440",     (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE | PPC_OPCODE_440
  71                 | PPC_OPCODE_ISEL | PPC_OPCODE_RFMCI),
  72     0 },
  73   { "464",     (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE | PPC_OPCODE_440
  74                 | PPC_OPCODE_ISEL | PPC_OPCODE_RFMCI),
  75     0 },
  76   { "476",     (PPC_OPCODE_PPC | PPC_OPCODE_ISEL | PPC_OPCODE_476
  77                 | PPC_OPCODE_POWER4 | PPC_OPCODE_POWER5),
  78     0 },
  79   { "601",     PPC_OPCODE_PPC | PPC_OPCODE_601,
  80     0 },
  81   { "603",     PPC_OPCODE_PPC,
  82     0 },
  83   { "604",     PPC_OPCODE_PPC,
  84     0 },
  85   { "620",     PPC_OPCODE_PPC | PPC_OPCODE_64,
  86     0 },
  87   { "7400",    PPC_OPCODE_PPC | PPC_OPCODE_ALTIVEC,
  88     0 },
  89   { "7410",    PPC_OPCODE_PPC | PPC_OPCODE_ALTIVEC,
  90     0 },
  91   { "7450",    PPC_OPCODE_PPC | PPC_OPCODE_7450 | PPC_OPCODE_ALTIVEC,
  92     0 },
  93   { "7455",    PPC_OPCODE_PPC | PPC_OPCODE_ALTIVEC,
  94     0 },
  95   { "750cl",   PPC_OPCODE_PPC | PPC_OPCODE_750 | PPC_OPCODE_PPCPS
  96     , 0 },
  97   { "821",     PPC_OPCODE_PPC | PPC_OPCODE_860,
  98     0 },
  99   { "850",     PPC_OPCODE_PPC | PPC_OPCODE_860,
 100     0 },
 101   { "860",     PPC_OPCODE_PPC | PPC_OPCODE_860,
 102     0 },
 103   { "a2",      (PPC_OPCODE_PPC | PPC_OPCODE_ISEL | PPC_OPCODE_POWER4
 104                 | PPC_OPCODE_POWER5 | PPC_OPCODE_CACHELCK | PPC_OPCODE_64
 105                 | PPC_OPCODE_A2),
 106     0 },
 107   { "altivec", PPC_OPCODE_PPC,
 108     PPC_OPCODE_ALTIVEC },
 109   { "any",     PPC_OPCODE_PPC,
 110     PPC_OPCODE_ANY },
 111   { "booke",   PPC_OPCODE_PPC | PPC_OPCODE_BOOKE,
 112     0 },
 113   { "booke32", PPC_OPCODE_PPC | PPC_OPCODE_BOOKE,
 114     0 },
 115   { "cell",    (PPC_OPCODE_PPC | PPC_OPCODE_64 | PPC_OPCODE_POWER4
 116                 | PPC_OPCODE_CELL | PPC_OPCODE_ALTIVEC),
 117     0 },
 118   { "com",     PPC_OPCODE_COMMON,
 119     0 },
 120   { "e200z4",  (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE| PPC_OPCODE_SPE
 121                 | PPC_OPCODE_ISEL | PPC_OPCODE_EFS | PPC_OPCODE_BRLOCK
 122                 | PPC_OPCODE_PMR | PPC_OPCODE_CACHELCK | PPC_OPCODE_RFMCI
 123                 | PPC_OPCODE_E500 | PPC_OPCODE_VLE | PPC_OPCODE_E200Z4
 124                 | PPC_OPCODE_EFS2 | PPC_OPCODE_LSP),
 125     0 },
 126   { "e300",    PPC_OPCODE_PPC | PPC_OPCODE_E300,
 127     0 },
 128   { "e500",    (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE | PPC_OPCODE_SPE
 129                 | PPC_OPCODE_ISEL | PPC_OPCODE_EFS | PPC_OPCODE_BRLOCK
 130                 | PPC_OPCODE_PMR | PPC_OPCODE_CACHELCK | PPC_OPCODE_RFMCI
 131                 | PPC_OPCODE_E500),
 132     0 },
 133   { "e500mc",  (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE | PPC_OPCODE_ISEL
 134                 | PPC_OPCODE_PMR | PPC_OPCODE_CACHELCK | PPC_OPCODE_RFMCI
 135                 | PPC_OPCODE_E500MC),
 136     0 },
 137   { "e500mc64",  (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE | PPC_OPCODE_ISEL
 138                 | PPC_OPCODE_PMR | PPC_OPCODE_CACHELCK | PPC_OPCODE_RFMCI
 139                 | PPC_OPCODE_E500MC | PPC_OPCODE_64 | PPC_OPCODE_POWER5
 140                 | PPC_OPCODE_POWER6 | PPC_OPCODE_POWER7),
 141     0 },
 142   { "e5500",    (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE | PPC_OPCODE_ISEL
 143                 | PPC_OPCODE_PMR | PPC_OPCODE_CACHELCK | PPC_OPCODE_RFMCI
 144                 | PPC_OPCODE_E500MC | PPC_OPCODE_64 | PPC_OPCODE_POWER4
 145                 | PPC_OPCODE_POWER5 | PPC_OPCODE_POWER6 | PPC_OPCODE_POWER7),
 146     0 },
 147   { "e6500",   (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE | PPC_OPCODE_ISEL
 148                 | PPC_OPCODE_PMR | PPC_OPCODE_CACHELCK | PPC_OPCODE_RFMCI
 149                 | PPC_OPCODE_E500MC | PPC_OPCODE_64 | PPC_OPCODE_ALTIVEC
 150                 | PPC_OPCODE_E6500 | PPC_OPCODE_TMR | PPC_OPCODE_POWER4
 151                 | PPC_OPCODE_POWER5 | PPC_OPCODE_POWER6 | PPC_OPCODE_POWER7),
 152     0 },
 153   { "e500x2",  (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE | PPC_OPCODE_SPE
 154                 | PPC_OPCODE_ISEL | PPC_OPCODE_EFS | PPC_OPCODE_BRLOCK
 155                 | PPC_OPCODE_PMR | PPC_OPCODE_CACHELCK | PPC_OPCODE_RFMCI
 156                 | PPC_OPCODE_E500),
 157     0 },
 158   { "efs",     PPC_OPCODE_PPC | PPC_OPCODE_EFS,
 159     0 },
 160   { "efs2",    PPC_OPCODE_PPC | PPC_OPCODE_EFS | PPC_OPCODE_EFS2,
 161     0 },
 162   { "power4",  PPC_OPCODE_PPC | PPC_OPCODE_64 | PPC_OPCODE_POWER4,
 163     0 },
 164   { "power5",  (PPC_OPCODE_PPC | PPC_OPCODE_64 | PPC_OPCODE_POWER4
 165                 | PPC_OPCODE_POWER5),
 166     0 },
 167   { "power6",  (PPC_OPCODE_PPC | PPC_OPCODE_64 | PPC_OPCODE_POWER4
 168                 | PPC_OPCODE_POWER5 | PPC_OPCODE_POWER6 | PPC_OPCODE_ALTIVEC),
 169     0 },
 170   { "power7",  (PPC_OPCODE_PPC | PPC_OPCODE_ISEL | PPC_OPCODE_64
 171                 | PPC_OPCODE_POWER4 | PPC_OPCODE_POWER5 | PPC_OPCODE_POWER6
 172                 | PPC_OPCODE_POWER7 | PPC_OPCODE_ALTIVEC | PPC_OPCODE_VSX),
 173     0 },
 174   { "power8",  (PPC_OPCODE_PPC | PPC_OPCODE_ISEL | PPC_OPCODE_64
 175                 | PPC_OPCODE_POWER4 | PPC_OPCODE_POWER5 | PPC_OPCODE_POWER6
 176                 | PPC_OPCODE_POWER7 | PPC_OPCODE_POWER8
 177                 | PPC_OPCODE_ALTIVEC | PPC_OPCODE_VSX),
 178     0 },
 179   { "power9",  (PPC_OPCODE_PPC | PPC_OPCODE_ISEL | PPC_OPCODE_64
 180                 | PPC_OPCODE_POWER4 | PPC_OPCODE_POWER5 | PPC_OPCODE_POWER6
 181                 | PPC_OPCODE_POWER7 | PPC_OPCODE_POWER8 | PPC_OPCODE_POWER9
 182                 | PPC_OPCODE_ALTIVEC | PPC_OPCODE_VSX),
 183     0 },
 184   { "ppc",     PPC_OPCODE_PPC,
 185     0 },
 186   { "ppc32",   PPC_OPCODE_PPC,
 187     0 },
 188   { "32",      PPC_OPCODE_PPC,
 189     0 },
 190   { "ppc64",   PPC_OPCODE_PPC | PPC_OPCODE_64,
 191     0 },
 192   { "64",      PPC_OPCODE_PPC | PPC_OPCODE_64,
 193     0 },
 194   { "ppc64bridge", PPC_OPCODE_PPC | PPC_OPCODE_64_BRIDGE,
 195     0 },
 196   { "ppcps",   PPC_OPCODE_PPC | PPC_OPCODE_PPCPS,
 197     0 },
 198   { "pwr",     PPC_OPCODE_POWER,
 199     0 },
 200   { "pwr2",    PPC_OPCODE_POWER | PPC_OPCODE_POWER2,
 201     0 },
 202   { "pwr4",    PPC_OPCODE_PPC | PPC_OPCODE_64 | PPC_OPCODE_POWER4,
 203     0 },
 204   { "pwr5",    (PPC_OPCODE_PPC | PPC_OPCODE_64 | PPC_OPCODE_POWER4
 205                 | PPC_OPCODE_POWER5),
 206     0 },
 207   { "pwr5x",   (PPC_OPCODE_PPC | PPC_OPCODE_64 | PPC_OPCODE_POWER4
 208                 | PPC_OPCODE_POWER5),
 209     0 },
 210   { "pwr6",    (PPC_OPCODE_PPC | PPC_OPCODE_64 | PPC_OPCODE_POWER4
 211                 | PPC_OPCODE_POWER5 | PPC_OPCODE_POWER6 | PPC_OPCODE_ALTIVEC),
 212     0 },
 213   { "pwr7",    (PPC_OPCODE_PPC | PPC_OPCODE_ISEL | PPC_OPCODE_64
 214                 | PPC_OPCODE_POWER4 | PPC_OPCODE_POWER5 | PPC_OPCODE_POWER6
 215                 | PPC_OPCODE_POWER7 | PPC_OPCODE_ALTIVEC | PPC_OPCODE_VSX),
 216     0 },
 217   { "pwr8",    (PPC_OPCODE_PPC | PPC_OPCODE_ISEL | PPC_OPCODE_64
 218                 | PPC_OPCODE_POWER4 | PPC_OPCODE_POWER5 | PPC_OPCODE_POWER6
 219                 | PPC_OPCODE_POWER7 | PPC_OPCODE_POWER8
 220                 | PPC_OPCODE_ALTIVEC | PPC_OPCODE_VSX),
 221     0 },
 222   { "pwr9",    (PPC_OPCODE_PPC | PPC_OPCODE_ISEL | PPC_OPCODE_64
 223                 | PPC_OPCODE_POWER4 | PPC_OPCODE_POWER5 | PPC_OPCODE_POWER6
 224                 | PPC_OPCODE_POWER7 | PPC_OPCODE_POWER8 | PPC_OPCODE_POWER9
 225                 | PPC_OPCODE_ALTIVEC | PPC_OPCODE_VSX),
 226     0 },
 227   { "pwrx",    PPC_OPCODE_POWER | PPC_OPCODE_POWER2,
 228     0 },
 229   { "raw",     PPC_OPCODE_PPC,
 230     PPC_OPCODE_RAW },
 231   { "spe",     PPC_OPCODE_PPC | PPC_OPCODE_EFS,
 232     PPC_OPCODE_SPE },
 233   { "spe2",     PPC_OPCODE_PPC | PPC_OPCODE_EFS | PPC_OPCODE_EFS2 | PPC_OPCODE_SPE,
 234     PPC_OPCODE_SPE2 },
 235   { "titan",   (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE | PPC_OPCODE_PMR
 236                 | PPC_OPCODE_RFMCI | PPC_OPCODE_TITAN),
 237     0 },
 238   { "vle",     (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE| PPC_OPCODE_SPE
 239                 | PPC_OPCODE_ISEL | PPC_OPCODE_EFS | PPC_OPCODE_BRLOCK
 240                 | PPC_OPCODE_PMR | PPC_OPCODE_CACHELCK | PPC_OPCODE_RFMCI
 241                 | PPC_OPCODE_LSP | PPC_OPCODE_EFS2 | PPC_OPCODE_SPE2),
 242     PPC_OPCODE_VLE },
 243   { "vsx",     PPC_OPCODE_PPC,
 244     PPC_OPCODE_VSX },
 245 };
 246
 247 /* Switch between Booke and VLE dialects for interlinked dumps.  */
 248 static ppc_cpu_t
 249 get_powerpc_dialect (struct disassemble_info *info)
 250 {
 251   ppc_cpu_t dialect = 0;
 252
 253   dialect = POWERPC_DIALECT (info);
 254
 255   /* Disassemble according to the section headers flags for VLE-mode.  */
 256   if (dialect & PPC_OPCODE_VLE
 257       && info->section != NULL && info->section->owner != NULL
 258       && bfd_get_flavour (info->section->owner) == bfd_target_elf_flavour
 259       && elf_object_id (info->section->owner) == PPC32_ELF_DATA
 260       && (elf_section_flags (info->section) & SHF_PPC_VLE) != 0)
 261     return dialect;
 262   else
 263     return dialect & ~ PPC_OPCODE_VLE;
 264 }
 265
 266 /* Handle -m and -M options that set cpu type, and .machine arg.  */
 267
 268 ppc_cpu_t
 269 ppc_parse_cpu (ppc_cpu_t ppc_cpu, ppc_cpu_t *sticky, const char *arg)
 270 {
 271   unsigned int i;
 272
 273   for (i = 0; i < ARRAY_SIZE (ppc_opts); i++)
 274     if (disassembler_options_cmp (ppc_opts[i].opt, arg) == 0)
 275       {
 276         if (ppc_opts[i].sticky)
 277           {
 278             *sticky |= ppc_opts[i].sticky;
 279             if ((ppc_cpu & ~*sticky) != 0)
 280               break;
 281           }
 282         ppc_cpu = ppc_opts[i].cpu;
 283         break;
 284       }
 285   if (i >= ARRAY_SIZE (ppc_opts))
 286     return 0;
 287
 288   ppc_cpu |= *sticky;
 289   return ppc_cpu;
 290 }
 291
 292 /* Determine which set of machines to disassemble for.  */
 293
 294 static void
 295 powerpc_init_dialect (struct disassemble_info *info)
 296 {
 297   ppc_cpu_t dialect = 0;
 298   ppc_cpu_t sticky = 0;
 299   struct dis_private *priv = calloc (sizeof (*priv), 1);
 300
 301   if (priv == NULL)
 302     priv = &private;
 303
 304   switch (info->mach)
 305     {
 306     case bfd_mach_ppc_403:
 307     case bfd_mach_ppc_403gc:
 308       dialect = ppc_parse_cpu (dialect, &sticky, "403");
 309       break;
 310     case bfd_mach_ppc_405:
 311       dialect = ppc_parse_cpu (dialect, &sticky, "405");
 312       break;
 313     case bfd_mach_ppc_601:
 314       dialect = ppc_parse_cpu (dialect, &sticky, "601");
 315       break;
 316     case bfd_mach_ppc_a35:
 317     case bfd_mach_ppc_rs64ii:
 318     case bfd_mach_ppc_rs64iii:
 319       dialect = ppc_parse_cpu (dialect, &sticky, "pwr2") | PPC_OPCODE_64;
 320       break;
 321     case bfd_mach_ppc_e500:
 322       dialect = ppc_parse_cpu (dialect, &sticky, "e500");
 323       break;
 324     case bfd_mach_ppc_e500mc:
 325       dialect = ppc_parse_cpu (dialect, &sticky, "e500mc");
 326       break;
 327     case bfd_mach_ppc_e500mc64:
 328       dialect = ppc_parse_cpu (dialect, &sticky, "e500mc64");
 329       break;
 330     case bfd_mach_ppc_e5500:
 331       dialect = ppc_parse_cpu (dialect, &sticky, "e5500");
 332       break;
 333     case bfd_mach_ppc_e6500:
 334       dialect = ppc_parse_cpu (dialect, &sticky, "e6500");
 335       break;
 336     case bfd_mach_ppc_titan:
 337       dialect = ppc_parse_cpu (dialect, &sticky, "titan");
 338       break;
 339     case bfd_mach_ppc_vle:
 340       dialect = ppc_parse_cpu (dialect, &sticky, "vle");
 341       break;
 342     default:
 343       dialect = ppc_parse_cpu (dialect, &sticky, "power9") | PPC_OPCODE_ANY;
 344       break;
 345     }
 346
 347   const char *opt;
 348   FOR_EACH_DISASSEMBLER_OPTION (opt, info->disassembler_options)
 349     {
 350       ppc_cpu_t new_cpu = 0;
 351
 352       if (disassembler_options_cmp (opt, "32") == 0)
 353         dialect &= ~(ppc_cpu_t) PPC_OPCODE_64;
 354       else if (disassembler_options_cmp (opt, "64") == 0)
 355         dialect |= PPC_OPCODE_64;
 356       else if ((new_cpu = ppc_parse_cpu (dialect, &sticky, opt)) != 0)
 357         dialect = new_cpu;
 358       else
 359         /* xgettext: c-format */
 360         opcodes_error_handler (_("warning: ignoring unknown -M%s option"), opt);
 361     }
 362
 363   info->private_data = priv;
 364   POWERPC_DIALECT(info) = dialect;
 365 }
 366
 367 #define PPC_OPCD_SEGS 64
 368 static unsigned short powerpc_opcd_indices[PPC_OPCD_SEGS+1];
 369 #define VLE_OPCD_SEGS 32
 370 static unsigned short vle_opcd_indices[VLE_OPCD_SEGS+1];
 371 #define SPE2_OPCD_SEGS 13
 372 static unsigned short spe2_opcd_indices[SPE2_OPCD_SEGS+1];
 373
 374 /* Calculate opcode table indices to speed up disassembly,
 375    and init dialect.  */
 376
 377 void
 378 disassemble_init_powerpc (struct disassemble_info *info)
 379 {
 380   int i;
 381   unsigned short last;
 382
 383   if (powerpc_opcd_indices[PPC_OPCD_SEGS] == 0)
 384     {
 385       i = powerpc_num_opcodes;
 386       while (--i >= 0)
 387         {
 388           unsigned op = PPC_OP (powerpc_opcodes[i].opcode);
 389           powerpc_opcd_indices[op] = i;
 390         }
 391
 392       last = powerpc_num_opcodes;
 393       for (i = PPC_OPCD_SEGS; i > 0; --i)
 394         {
 395           if (powerpc_opcd_indices[i] == 0)
 396             powerpc_opcd_indices[i] = last;
 397           last = powerpc_opcd_indices[i];
 398         }
 399
 400       i = vle_num_opcodes;
 401       while (--i >= 0)
 402         {
 403           unsigned op = VLE_OP (vle_opcodes[i].opcode, vle_opcodes[i].mask);
 404           unsigned seg = VLE_OP_TO_SEG (op);
 405           vle_opcd_indices[seg] = i;
 406         }
 407
 408       last = vle_num_opcodes;
 409       for (i = VLE_OPCD_SEGS; i > 0; --i)
 410         {
 411           if (vle_opcd_indices[i] == 0)
 412             vle_opcd_indices[i] = last;
 413           last = vle_opcd_indices[i];
 414         }
 415     }
 416
 417   /* SPE2 opcodes */
 418   i = spe2_num_opcodes;
 419   while (--i >= 0)
 420     {
 421       unsigned xop = SPE2_XOP (spe2_opcodes[i].opcode);
 422       unsigned seg = SPE2_XOP_TO_SEG (xop);
 423       spe2_opcd_indices[seg] = i;
 424     }
 425
 426   last = spe2_num_opcodes;
 427   for (i = SPE2_OPCD_SEGS; i > 1; --i)
 428     {
 429       if (spe2_opcd_indices[i] == 0)
 430         spe2_opcd_indices[i] = last;
 431       last = spe2_opcd_indices[i];
 432     }
 433
 434   if (info->arch == bfd_arch_powerpc)
 435     powerpc_init_dialect (info);
 436 }
 437
 438 /* Print a big endian PowerPC instruction.  */
 439
 440 int
 441 print_insn_big_powerpc (bfd_vma memaddr, struct disassemble_info *info)
 442 {
 443   return print_insn_powerpc (memaddr, info, 1, get_powerpc_dialect (info));
 444 }
 445
 446 /* Print a little endian PowerPC instruction.  */
 447
 448 int
 449 print_insn_little_powerpc (bfd_vma memaddr, struct disassemble_info *info)
 450 {
 451   return print_insn_powerpc (memaddr, info, 0, get_powerpc_dialect (info));
 452 }
 453
 454 /* Print a POWER (RS/6000) instruction.  */
 455
 456 int
 457 print_insn_rs6000 (bfd_vma memaddr, struct disassemble_info *info)
 458 {
 459   return print_insn_powerpc (memaddr, info, 1, PPC_OPCODE_POWER);
 460 }
 461
 462 /* Extract the operand value from the PowerPC or POWER instruction.  */
 463
 464 static int64_t
 465 operand_value_powerpc (const struct powerpc_operand *operand,
 466                        uint64_t insn, ppc_cpu_t dialect)
 467 {
 468   int64_t value;
 469   int invalid;
 470   /* Extract the value from the instruction.  */
 471   if (operand->extract)
 472     value = (*operand->extract) (insn, dialect, &invalid);
 473   else
 474     {
 475       if (operand->shift >= 0)
 476         value = (insn >> operand->shift) & operand->bitm;
 477       else
 478         value = (insn << -operand->shift) & operand->bitm;
 479       if ((operand->flags & PPC_OPERAND_SIGNED) != 0)
 480         {
 481           /* BITM is always some number of zeros followed by some
 482              number of ones, followed by some number of zeros.  */
 483           uint64_t top = operand->bitm;
 484           /* top & -top gives the rightmost 1 bit, so this
 485              fills in any trailing zeros.  */
 486           top |= (top & -top) - 1;
 487           top &= ~(top >> 1);
 488           value = (value ^ top) - top;
 489         }
 490     }
 491
 492   return value;
 493 }
 494
 495 /* Determine whether the optional operand(s) should be printed.  */
 496
 497 static int
 498 skip_optional_operands (const unsigned char *opindex,
 499                         uint64_t insn, ppc_cpu_t dialect)
 500 {
 501   const struct powerpc_operand *operand;
 502
 503   for (; *opindex != 0; opindex++)
 504     {
 505       operand = &powerpc_operands[*opindex];
 506       if ((operand->flags & PPC_OPERAND_NEXT) != 0
 507           || ((operand->flags & PPC_OPERAND_OPTIONAL) != 0
 508               && operand_value_powerpc (operand, insn, dialect) !=
 509                  ppc_optional_operand_value (operand)))
 510         return 0;
 511     }
 512
 513   return 1;
 514 }
 515
 516 /* Find a match for INSN in the opcode table, given machine DIALECT.  */
 517
 518 static const struct powerpc_opcode *
 519 lookup_powerpc (uint64_t insn, ppc_cpu_t dialect)
 520 {
 521   const struct powerpc_opcode *opcode, *opcode_end, *last;
 522   unsigned long op;
 523
 524   /* Get the major opcode of the instruction.  */
 525   op = PPC_OP (insn);
 526
 527   /* Find the first match in the opcode table for this major opcode.  */
 528   opcode_end = powerpc_opcodes + powerpc_opcd_indices[op + 1];
 529   last = NULL;
 530   for (opcode = powerpc_opcodes + powerpc_opcd_indices[op];
 531        opcode < opcode_end;
 532        ++opcode)
 533     {
 534       const unsigned char *opindex;
 535       const struct powerpc_operand *operand;
 536       int invalid;
 537
 538       if ((insn & opcode->mask) != opcode->opcode
 539           || ((dialect & PPC_OPCODE_ANY) == 0
 540               && ((opcode->flags & dialect) == 0
 541                   || (opcode->deprecated & dialect) != 0)))
 542         continue;
 543
 544       /* Check validity of operands.  */
 545       invalid = 0;
 546       for (opindex = opcode->operands; *opindex != 0; opindex++)
 547         {
 548           operand = powerpc_operands + *opindex;
 549           if (operand->extract)
 550             (*operand->extract) (insn, dialect, &invalid);
 551         }
 552       if (invalid)
 553         continue;
 554
 555       if ((dialect & PPC_OPCODE_RAW) == 0)
 556         return opcode;
 557
 558       /* The raw machine insn is one that is not a specialization.  */
 559       if (last == NULL
 560           || (last->mask & ~opcode->mask) != 0)
 561         last = opcode;
 562     }
 563
 564   return last;
 565 }
 566
 567 /* Find a match for INSN in the VLE opcode table.  */
 568
 569 static const struct powerpc_opcode *
 570 lookup_vle (uint64_t insn)
 571 {
 572   const struct powerpc_opcode *opcode;
 573   const struct powerpc_opcode *opcode_end;
 574   unsigned op, seg;
 575
 576   op = PPC_OP (insn);
 577   if (op >= 0x20 && op <= 0x37)
 578     {
 579       /* This insn has a 4-bit opcode.  */
 580       op &= 0x3c;
 581     }
 582   seg = VLE_OP_TO_SEG (op);
 583
 584   /* Find the first match in the opcode table for this major opcode.  */
 585   opcode_end = vle_opcodes + vle_opcd_indices[seg + 1];
 586   for (opcode = vle_opcodes + vle_opcd_indices[seg];
 587        opcode < opcode_end;
 588        ++opcode)
 589     {
 590       uint64_t table_opcd = opcode->opcode;
 591       uint64_t table_mask = opcode->mask;
 592       bfd_boolean table_op_is_short = PPC_OP_SE_VLE(table_mask);
 593       uint64_t insn2;
 594       const unsigned char *opindex;
 595       const struct powerpc_operand *operand;
 596       int invalid;
 597
 598       insn2 = insn;
 599       if (table_op_is_short)
 600         insn2 >>= 16;
 601       if ((insn2 & table_mask) != table_opcd)
 602         continue;
 603
 604       /* Check validity of operands.  */
 605       invalid = 0;
 606       for (opindex = opcode->operands; *opindex != 0; ++opindex)
 607         {
 608           operand = powerpc_operands + *opindex;
 609           if (operand->extract)
 610             (*operand->extract) (insn, (ppc_cpu_t)0, &invalid);
 611         }
 612       if (invalid)
 613         continue;
 614
 615       return opcode;
 616     }
 617
 618   return NULL;
 619 }
 620
 621 /* Find a match for INSN in the SPE2 opcode table.  */
 622
 623 static const struct powerpc_opcode *
 624 lookup_spe2 (uint64_t insn)
 625 {
 626   const struct powerpc_opcode *opcode, *opcode_end;
 627   unsigned op, xop, seg;
 628
 629   op = PPC_OP (insn);
 630   if (op != 0x4)
 631     {
 632       /* This is not SPE2 insn.
 633        * All SPE2 instructions have OP=4 and differs by XOP  */
 634       return NULL;
 635     }
 636   xop = SPE2_XOP (insn);
 637   seg = SPE2_XOP_TO_SEG (xop);
 638
 639   /* Find the first match in the opcode table for this major opcode.  */
 640   opcode_end = spe2_opcodes + spe2_opcd_indices[seg + 1];
 641   for (opcode = spe2_opcodes + spe2_opcd_indices[seg];
 642        opcode < opcode_end;
 643        ++opcode)
 644     {
 645       uint64_t table_opcd = opcode->opcode;
 646       uint64_t table_mask = opcode->mask;
 647       uint64_t insn2;
 648       const unsigned char *opindex;
 649       const struct powerpc_operand *operand;
 650       int invalid;
 651
 652       insn2 = insn;
 653       if ((insn2 & table_mask) != table_opcd)
 654         continue;
 655
 656       /* Check validity of operands.  */
 657       invalid = 0;
 658       for (opindex = opcode->operands; *opindex != 0; ++opindex)
 659         {
 660           operand = powerpc_operands + *opindex;
 661           if (operand->extract)
 662             (*operand->extract) (insn, (ppc_cpu_t)0, &invalid);
 663         }
 664       if (invalid)
 665         continue;
 666
 667       return opcode;
 668     }
 669
 670   return NULL;
 671 }
 672
 673 /* Print a PowerPC or POWER instruction.  */
 674
 675 static int
 676 print_insn_powerpc (bfd_vma memaddr,
 677                     struct disassemble_info *info,
 678                     int bigendian,
 679                     ppc_cpu_t dialect)
 680 {
 681   bfd_byte buffer[4];
 682   int status;
 683   uint64_t insn;
 684   const struct powerpc_opcode *opcode;
 685   bfd_boolean insn_is_short;
 686
 687   status = (*info->read_memory_func) (memaddr, buffer, 4, info);
 688   if (status != 0)
 689     {
 690       /* The final instruction may be a 2-byte VLE insn.  */
 691       if ((dialect & PPC_OPCODE_VLE) != 0)
 692         {
 693           /* Clear buffer so unused bytes will not have garbage in them.  */
 694           buffer[0] = buffer[1] = buffer[2] = buffer[3] = 0;
 695           status = (*info->read_memory_func) (memaddr, buffer, 2, info);
 696           if (status != 0)
 697             {
 698               (*info->memory_error_func) (status, memaddr, info);
 699               return -1;
 700             }
 701         }
 702       else
 703         {
 704           (*info->memory_error_func) (status, memaddr, info);
 705           return -1;
 706         }
 707     }
 708
 709   if (bigendian)
 710     insn = bfd_getb32 (buffer);
 711   else
 712     insn = bfd_getl32 (buffer);
 713
 714   /* Get the major opcode of the insn.  */
 715   opcode = NULL;
 716   insn_is_short = FALSE;
 717   if ((dialect & PPC_OPCODE_VLE) != 0)
 718     {
 719       opcode = lookup_vle (insn);
 720       if (opcode != NULL)
 721         insn_is_short = PPC_OP_SE_VLE(opcode->mask);
 722     }
 723   if (opcode == NULL && (dialect & PPC_OPCODE_SPE2) != 0)
 724     opcode = lookup_spe2 (insn);
 725   if (opcode == NULL)
 726     opcode = lookup_powerpc (insn, dialect & ~PPC_OPCODE_ANY);
 727   if (opcode == NULL && (dialect & PPC_OPCODE_ANY) != 0)
 728     opcode = lookup_powerpc (insn, dialect);
 729
 730   if (opcode != NULL)
 731     {
 732       const unsigned char *opindex;
 733       const struct powerpc_operand *operand;
 734       int need_comma;
 735       int need_paren;
 736       int skip_optional;
 737
 738       if (opcode->operands[0] != 0)
 739         (*info->fprintf_func) (info->stream, "%-7s ", opcode->name);
 740       else
 741         (*info->fprintf_func) (info->stream, "%s", opcode->name);
 742
 743       if (insn_is_short)
 744         /* The operands will be fetched out of the 16-bit instruction.  */
 745         insn >>= 16;
 746
 747       /* Now extract and print the operands.  */
 748       need_comma = 0;
 749       need_paren = 0;
 750       skip_optional = -1;
 751       for (opindex = opcode->operands; *opindex != 0; opindex++)
 752         {
 753           int64_t value;
 754
 755           operand = powerpc_operands + *opindex;
 756
 757           /* Operands that are marked FAKE are simply ignored.  We
 758              already made sure that the extract function considered
 759              the instruction to be valid.  */
 760           if ((operand->flags & PPC_OPERAND_FAKE) != 0)
 761             continue;
 762
 763           /* If all of the optional operands have the value zero,
 764              then don't print any of them.  */
 765           if ((operand->flags & PPC_OPERAND_OPTIONAL) != 0)
 766             {
 767               if (skip_optional < 0)
 768                 skip_optional = skip_optional_operands (opindex, insn,
 769                                                         dialect);
 770               if (skip_optional)
 771                 continue;
 772             }
 773
 774           value = operand_value_powerpc (operand, insn, dialect);
 775
 776           if (need_comma)
 777             {
 778               (*info->fprintf_func) (info->stream, ",");
 779               need_comma = 0;
 780             }
 781
 782           /* Print the operand as directed by the flags.  */
 783           if ((operand->flags & PPC_OPERAND_GPR) != 0
 784               || ((operand->flags & PPC_OPERAND_GPR_0) != 0 && value != 0))
 785             (*info->fprintf_func) (info->stream, "r%" PPC_INT_FMT "d", value);
 786           else if ((operand->flags & PPC_OPERAND_FPR) != 0)
 787             (*info->fprintf_func) (info->stream, "f%" PPC_INT_FMT "d", value);
 788           else if ((operand->flags & PPC_OPERAND_VR) != 0)
 789             (*info->fprintf_func) (info->stream, "v%" PPC_INT_FMT "d", value);
 790           else if ((operand->flags & PPC_OPERAND_VSR) != 0)
 791             (*info->fprintf_func) (info->stream, "vs%" PPC_INT_FMT "d", value);
 792           else if ((operand->flags & PPC_OPERAND_RELATIVE) != 0)
 793             (*info->print_address_func) (memaddr + value, info);
 794           else if ((operand->flags & PPC_OPERAND_ABSOLUTE) != 0)
 795             (*info->print_address_func) ((bfd_vma) value & 0xffffffff, info);
 796           else if ((operand->flags & PPC_OPERAND_FSL) != 0)
 797             (*info->fprintf_func) (info->stream, "fsl%" PPC_INT_FMT "d", value);
 798           else if ((operand->flags & PPC_OPERAND_FCR) != 0)
 799             (*info->fprintf_func) (info->stream, "fcr%" PPC_INT_FMT "d", value);
 800           else if ((operand->flags & PPC_OPERAND_UDI) != 0)
 801             (*info->fprintf_func) (info->stream, "%" PPC_INT_FMT "d", value);
 802           else if ((operand->flags & PPC_OPERAND_CR_REG) != 0
 803                    && (((dialect & PPC_OPCODE_PPC) != 0)
 804                        || ((dialect & PPC_OPCODE_VLE) != 0)))
 805             (*info->fprintf_func) (info->stream, "cr%" PPC_INT_FMT "d", value);
 806           else if (((operand->flags & PPC_OPERAND_CR_BIT) != 0)
 807                    && (((dialect & PPC_OPCODE_PPC) != 0)
 808                        || ((dialect & PPC_OPCODE_VLE) != 0)))
 809             {
 810               static const char *cbnames[4] = { "lt", "gt", "eq", "so" };
 811               int cr;
 812               int cc;
 813
 814               cr = value >> 2;
 815               if (cr != 0)
 816                 (*info->fprintf_func) (info->stream, "4*cr%d+", cr);
 817               cc = value & 3;
 818               (*info->fprintf_func) (info->stream, "%s", cbnames[cc]);
 819             }
 820           else
 821             (*info->fprintf_func) (info->stream, "%" PPC_INT_FMT "d", value);
 822
 823           if (need_paren)
 824             {
 825               (*info->fprintf_func) (info->stream, ")");
 826               need_paren = 0;
 827             }
 828
 829           if ((operand->flags & PPC_OPERAND_PARENS) == 0)
 830             need_comma = 1;
 831           else
 832             {
 833               (*info->fprintf_func) (info->stream, "(");
 834               need_paren = 1;
 835             }
 836         }
 837
 838       /* We have found and printed an instruction.
 839          If it was a short VLE instruction we have more to do.  */
 840       if (insn_is_short)
 841         {
 842           memaddr += 2;
 843           return 2;
 844         }
 845       else
 846         /* Otherwise, return.  */
 847         return 4;
 848     }
 849
 850   /* We could not find a match.  */
 851   (*info->fprintf_func) (info->stream, ".long 0x%" PPC_INT_FMT "x", insn);
 852
 853   return 4;
 854 }
 855
 856 const disasm_options_t *
 857 disassembler_options_powerpc (void)
 858 {
 859   static disasm_options_t *opts = NULL;
 860
 861   if (opts == NULL)
 862     {
 863       size_t i, num_options = ARRAY_SIZE (ppc_opts);
 864       opts = XNEW (disasm_options_t);
 865       opts->name = XNEWVEC (const char *, num_options + 1);
 866       for (i = 0; i < num_options; i++)
 867         opts->name[i] = ppc_opts[i].opt;
 868       /* The array we return must be NULL terminated.  */
 869       opts->name[i] = NULL;
 870       opts->description = NULL;
 871     }
 872
 873   return opts;
 874 }
 875
 876 void
 877 print_ppc_disassembler_options (FILE *stream)
 878 {
 879   unsigned int i, col;
 880
 881   fprintf (stream, _("\n\
 882 The following PPC specific disassembler options are supported for use with\n\
 883 the -M switch:\n"));
 884
 885   for (col = 0, i = 0; i < ARRAY_SIZE (ppc_opts); i++)
 886     {
 887       col += fprintf (stream, " %s,", ppc_opts[i].opt);
 888       if (col > 66)
 889         {
 890           fprintf (stream, "\n");
 891           col = 0;
 892         }
 893     }
 894   fprintf (stream, "\n");
 895 }