opcodes/ppc-opc.c

   1 /* ppc-opc.c -- PowerPC opcode list
   2    Copyright 1994, 1995, 1996, 1997, 1998, 2000, 2001
   3    Free Software Foundation, Inc.
   4    Written by Ian Lance Taylor, Cygnus Support
   5
   6 This file is part of GDB, GAS, and the GNU binutils.
   7
   8 GDB, GAS, and the GNU binutils are free software; you can redistribute
   9 them and/or modify them under the terms of the GNU General Public
  10 License as published by the Free Software Foundation; either version
  11 2, or (at your option) any later version.
  12
  13 GDB, GAS, and the GNU binutils are distributed in the hope that they
  14 will be useful, but WITHOUT ANY WARRANTY; without even the implied
  15 warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See
  16 the GNU General Public License for more details.
  17
  18 You should have received a copy of the GNU General Public License
  19 along with this file; see the file COPYING.  If not, write to the Free
  20 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
  21 02111-1307, USA.  */
  22
  23 #include <stdio.h>
  24 #include "sysdep.h"
  25 #include "opcode/ppc.h"
  26 #include "opintl.h"
  27
  28 /* This file holds the PowerPC opcode table.  The opcode table
  29    includes almost all of the extended instruction mnemonics.  This
  30    permits the disassembler to use them, and simplifies the assembler
  31    logic, at the cost of increasing the table size.  The table is
  32    strictly constant data, so the compiler should be able to put it in
  33    the .text section.
  34
  35    This file also holds the operand table.  All knowledge about
  36    inserting operands into instructions and vice-versa is kept in this
  37    file.  */
  38 \f
  39 /* Local insertion and extraction functions.  */
  40
  41 static unsigned long insert_bat PARAMS ((unsigned long, long, const char **));
  42 static long extract_bat PARAMS ((unsigned long, int *));
  43 static unsigned long insert_bba PARAMS ((unsigned long, long, const char **));
  44 static long extract_bba PARAMS ((unsigned long, int *));
  45 static unsigned long insert_bd PARAMS ((unsigned long, long, const char **));
  46 static long extract_bd PARAMS ((unsigned long, int *));
  47 static unsigned long insert_bdm PARAMS ((unsigned long, long, const char **));
  48 static long extract_bdm PARAMS ((unsigned long, int *));
  49 static unsigned long insert_bdp PARAMS ((unsigned long, long, const char **));
  50 static long extract_bdp PARAMS ((unsigned long, int *));
  51 static int valid_bo PARAMS ((long));
  52 static unsigned long insert_bo PARAMS ((unsigned long, long, const char **));
  53 static long extract_bo PARAMS ((unsigned long, int *));
  54 static unsigned long insert_boe PARAMS ((unsigned long, long, const char **));
  55 static long extract_boe PARAMS ((unsigned long, int *));
  56 static unsigned long insert_ds PARAMS ((unsigned long, long, const char **));
  57 static long extract_ds PARAMS ((unsigned long, int *));
  58 static unsigned long insert_de PARAMS ((unsigned long, long, const char **));
  59 static long extract_de PARAMS ((unsigned long, int *));
  60 static unsigned long insert_des PARAMS ((unsigned long, long, const char **));
  61 static long extract_des PARAMS ((unsigned long, int *));
  62 static unsigned long insert_li PARAMS ((unsigned long, long, const char **));
  63 static long extract_li PARAMS ((unsigned long, int *));
  64 static unsigned long insert_mbe PARAMS ((unsigned long, long, const char **));
  65 static long extract_mbe PARAMS ((unsigned long, int *));
  66 static unsigned long insert_mb6 PARAMS ((unsigned long, long, const char **));
  67 static long extract_mb6 PARAMS ((unsigned long, int *));
  68 static unsigned long insert_nb PARAMS ((unsigned long, long, const char **));
  69 static long extract_nb PARAMS ((unsigned long, int *));
  70 static unsigned long insert_nsi PARAMS ((unsigned long, long, const char **));
  71 static long extract_nsi PARAMS ((unsigned long, int *));
  72 static unsigned long insert_ral PARAMS ((unsigned long, long, const char **));
  73 static unsigned long insert_ram PARAMS ((unsigned long, long, const char **));
  74 static unsigned long insert_ras PARAMS ((unsigned long, long, const char **));
  75 static unsigned long insert_rbs PARAMS ((unsigned long, long, const char **));
  76 static long extract_rbs PARAMS ((unsigned long, int *));
  77 static unsigned long insert_sh6 PARAMS ((unsigned long, long, const char **));
  78 static long extract_sh6 PARAMS ((unsigned long, int *));
  79 static unsigned long insert_spr PARAMS ((unsigned long, long, const char **));
  80 static long extract_spr PARAMS ((unsigned long, int *));
  81 static unsigned long insert_tbr PARAMS ((unsigned long, long, const char **));
  82 static long extract_tbr PARAMS ((unsigned long, int *));
  83 \f
  84 /* The operands table.
  85
  86    The fields are bits, shift, insert, extract, flags.
  87
  88    We used to put parens around the various additions, like the one
  89    for BA just below.  However, that caused trouble with feeble
  90    compilers with a limit on depth of a parenthesized expression, like
  91    (reportedly) the compiler in Microsoft Developer Studio 5.  So we
  92    omit the parens, since the macros are never used in a context where
  93    the addition will be ambiguous.  */
  94
  95 const struct powerpc_operand powerpc_operands[] =
  96 {
  97   /* The zero index is used to indicate the end of the list of
  98      operands.  */
  99 #define UNUSED 0
 100   { 0, 0, 0, 0, 0 },
 101
 102   /* The BA field in an XL form instruction.  */
 103 #define BA UNUSED + 1
 104 #define BA_MASK (0x1f << 16)
 105   { 5, 16, 0, 0, PPC_OPERAND_CR },
 106
 107   /* The BA field in an XL form instruction when it must be the same
 108      as the BT field in the same instruction.  */
 109 #define BAT BA + 1
 110   { 5, 16, insert_bat, extract_bat, PPC_OPERAND_FAKE },
 111
 112   /* The BB field in an XL form instruction.  */
 113 #define BB BAT + 1
 114 #define BB_MASK (0x1f << 11)
 115   { 5, 11, 0, 0, PPC_OPERAND_CR },
 116
 117   /* The BB field in an XL form instruction when it must be the same
 118      as the BA field in the same instruction.  */
 119 #define BBA BB + 1
 120   { 5, 11, insert_bba, extract_bba, PPC_OPERAND_FAKE },
 121
 122   /* The BD field in a B form instruction.  The lower two bits are
 123      forced to zero.  */
 124 #define BD BBA + 1
 125   { 16, 0, insert_bd, extract_bd, PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED },
 126
 127   /* The BD field in a B form instruction when absolute addressing is
 128      used.  */
 129 #define BDA BD + 1
 130   { 16, 0, insert_bd, extract_bd, PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED },
 131
 132   /* The BD field in a B form instruction when the - modifier is used.
 133      This sets the y bit of the BO field appropriately.  */
 134 #define BDM BDA + 1
 135   { 16, 0, insert_bdm, extract_bdm,
 136       PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED },
 137
 138   /* The BD field in a B form instruction when the - modifier is used
 139      and absolute address is used.  */
 140 #define BDMA BDM + 1
 141   { 16, 0, insert_bdm, extract_bdm,
 142       PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED },
 143
 144   /* The BD field in a B form instruction when the + modifier is used.
 145      This sets the y bit of the BO field appropriately.  */
 146 #define BDP BDMA + 1
 147   { 16, 0, insert_bdp, extract_bdp,
 148       PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED },
 149
 150   /* The BD field in a B form instruction when the + modifier is used
 151      and absolute addressing is used.  */
 152 #define BDPA BDP + 1
 153   { 16, 0, insert_bdp, extract_bdp,
 154       PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED },
 155
 156   /* The BF field in an X or XL form instruction.  */
 157 #define BF BDPA + 1
 158   { 3, 23, 0, 0, PPC_OPERAND_CR },
 159
 160   /* An optional BF field.  This is used for comparison instructions,
 161      in which an omitted BF field is taken as zero.  */
 162 #define OBF BF + 1
 163   { 3, 23, 0, 0, PPC_OPERAND_CR | PPC_OPERAND_OPTIONAL },
 164
 165   /* The BFA field in an X or XL form instruction.  */
 166 #define BFA OBF + 1
 167   { 3, 18, 0, 0, PPC_OPERAND_CR },
 168
 169   /* The BI field in a B form or XL form instruction.  */
 170 #define BI BFA + 1
 171 #define BI_MASK (0x1f << 16)
 172   { 5, 16, 0, 0, PPC_OPERAND_CR },
 173
 174   /* The BO field in a B form instruction.  Certain values are
 175      illegal.  */
 176 #define BO BI + 1
 177 #define BO_MASK (0x1f << 21)
 178   { 5, 21, insert_bo, extract_bo, 0 },
 179
 180   /* The BO field in a B form instruction when the + or - modifier is
 181      used.  This is like the BO field, but it must be even.  */
 182 #define BOE BO + 1
 183   { 5, 21, insert_boe, extract_boe, 0 },
 184
 185   /* The BT field in an X or XL form instruction.  */
 186 #define BT BOE + 1
 187   { 5, 21, 0, 0, PPC_OPERAND_CR },
 188
 189   /* The condition register number portion of the BI field in a B form
 190      or XL form instruction.  This is used for the extended
 191      conditional branch mnemonics, which set the lower two bits of the
 192      BI field.  This field is optional.  */
 193 #define CR BT + 1
 194   { 3, 18, 0, 0, PPC_OPERAND_CR | PPC_OPERAND_OPTIONAL },
 195
 196   /* The CT field in an X form instruction.  */
 197 #define CT CR + 1
 198   { 5, 21, 0, 0, 0 },
 199
 200   /* The D field in a D form instruction.  This is a displacement off
 201      a register, and implies that the next operand is a register in
 202      parentheses.  */
 203 #define D CT + 1
 204   { 16, 0, 0, 0, PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED },
 205
 206   /* The DE field in a DE form instruction.  This is like D, but is 12
 207      bits only.  */
 208 #define DE D + 1
 209   { 14, 0, insert_de, extract_de, PPC_OPERAND_PARENS },
 210
 211   /* The DES field in a DES form instruction.  This is like DS, but is 14
 212      bits only (12 stored.)  */
 213 #define DES DE + 1
 214   { 14, 0, insert_des, extract_des, PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED },
 215
 216   /* The DS field in a DS form instruction.  This is like D, but the
 217      lower two bits are forced to zero.  */
 218 #define DS DES + 1
 219   { 16, 0, insert_ds, extract_ds,
 220       PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED | PPC_OPERAND_DS },
 221
 222   /* The E field in a wrteei instruction.  */
 223 #define E DS + 1
 224   { 1, 15, 0, 0, 0 },
 225
 226   /* The FL1 field in a POWER SC form instruction.  */
 227 #define FL1 E + 1
 228   { 4, 12, 0, 0, 0 },
 229
 230   /* The FL2 field in a POWER SC form instruction.  */
 231 #define FL2 FL1 + 1
 232   { 3, 2, 0, 0, 0 },
 233
 234   /* The FLM field in an XFL form instruction.  */
 235 #define FLM FL2 + 1
 236   { 8, 17, 0, 0, 0 },
 237
 238   /* The FRA field in an X or A form instruction.  */
 239 #define FRA FLM + 1
 240 #define FRA_MASK (0x1f << 16)
 241   { 5, 16, 0, 0, PPC_OPERAND_FPR },
 242
 243   /* The FRB field in an X or A form instruction.  */
 244 #define FRB FRA + 1
 245 #define FRB_MASK (0x1f << 11)
 246   { 5, 11, 0, 0, PPC_OPERAND_FPR },
 247
 248   /* The FRC field in an A form instruction.  */
 249 #define FRC FRB + 1
 250 #define FRC_MASK (0x1f << 6)
 251   { 5, 6, 0, 0, PPC_OPERAND_FPR },
 252
 253   /* The FRS field in an X form instruction or the FRT field in a D, X
 254      or A form instruction.  */
 255 #define FRS FRC + 1
 256 #define FRT FRS
 257   { 5, 21, 0, 0, PPC_OPERAND_FPR },
 258
 259   /* The FXM field in an XFX instruction.  */
 260 #define FXM FRS + 1
 261 #define FXM_MASK (0xff << 12)
 262   { 8, 12, 0, 0, 0 },
 263
 264   /* The L field in a D or X form instruction.  */
 265 #define L FXM + 1
 266   { 1, 21, 0, 0, PPC_OPERAND_OPTIONAL },
 267
 268   /* The LEV field in a POWER SC form instruction.  */
 269 #define LEV L + 1
 270   { 7, 5, 0, 0, 0 },
 271
 272   /* The LI field in an I form instruction.  The lower two bits are
 273      forced to zero.  */
 274 #define LI LEV + 1
 275   { 26, 0, insert_li, extract_li, PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED },
 276
 277   /* The LI field in an I form instruction when used as an absolute
 278      address.  */
 279 #define LIA LI + 1
 280   { 26, 0, insert_li, extract_li, PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED },
 281
 282   /* The LS field in an X (sync) form instruction.  */
 283 #define LS LIA + 1
 284   { 2, 21, 0, 0, PPC_OPERAND_OPTIONAL },
 285
 286   /* The MB field in an M form instruction.  */
 287 #define MB LS + 1
 288 #define MB_MASK (0x1f << 6)
 289   { 5, 6, 0, 0, 0 },
 290
 291   /* The ME field in an M form instruction.  */
 292 #define ME MB + 1
 293 #define ME_MASK (0x1f << 1)
 294   { 5, 1, 0, 0, 0 },
 295
 296   /* The MB and ME fields in an M form instruction expressed a single
 297      operand which is a bitmask indicating which bits to select.  This
 298      is a two operand form using PPC_OPERAND_NEXT.  See the
 299      description in opcode/ppc.h for what this means.  */
 300 #define MBE ME + 1
 301   { 5, 6, 0, 0, PPC_OPERAND_OPTIONAL | PPC_OPERAND_NEXT },
 302   { 32, 0, insert_mbe, extract_mbe, 0 },
 303
 304   /* The MB or ME field in an MD or MDS form instruction.  The high
 305      bit is wrapped to the low end.  */
 306 #define MB6 MBE + 2
 307 #define ME6 MB6
 308 #define MB6_MASK (0x3f << 5)
 309   { 6, 5, insert_mb6, extract_mb6, 0 },
 310
 311   /* The NB field in an X form instruction.  The value 32 is stored as
 312      0.  */
 313 #define NB MB6 + 1
 314   { 6, 11, insert_nb, extract_nb, 0 },
 315
 316   /* The NSI field in a D form instruction.  This is the same as the
 317      SI field, only negated.  */
 318 #define NSI NB + 1
 319   { 16, 0, insert_nsi, extract_nsi,
 320       PPC_OPERAND_NEGATIVE | PPC_OPERAND_SIGNED },
 321
 322   /* The RA field in an D, DS, X, XO, M, or MDS form instruction.  */
 323 #define RA NSI + 1
 324 #define RA_MASK (0x1f << 16)
 325   { 5, 16, 0, 0, PPC_OPERAND_GPR },
 326
 327   /* The RA field in a D or X form instruction which is an updating
 328      load, which means that the RA field may not be zero and may not
 329      equal the RT field.  */
 330 #define RAL RA + 1
 331   { 5, 16, insert_ral, 0, PPC_OPERAND_GPR },
 332
 333   /* The RA field in an lmw instruction, which has special value
 334      restrictions.  */
 335 #define RAM RAL + 1
 336   { 5, 16, insert_ram, 0, PPC_OPERAND_GPR },
 337
 338   /* The RA field in a D or X form instruction which is an updating
 339      store or an updating floating point load, which means that the RA
 340      field may not be zero.  */
 341 #define RAS RAM + 1
 342   { 5, 16, insert_ras, 0, PPC_OPERAND_GPR },
 343
 344   /* The RB field in an X, XO, M, or MDS form instruction.  */
 345 #define RB RAS + 1
 346 #define RB_MASK (0x1f << 11)
 347   { 5, 11, 0, 0, PPC_OPERAND_GPR },
 348
 349   /* The RB field in an X form instruction when it must be the same as
 350      the RS field in the instruction.  This is used for extended
 351      mnemonics like mr.  */
 352 #define RBS RB + 1
 353   { 5, 1, insert_rbs, extract_rbs, PPC_OPERAND_FAKE },
 354
 355   /* The RS field in a D, DS, X, XFX, XS, M, MD or MDS form
 356      instruction or the RT field in a D, DS, X, XFX or XO form
 357      instruction.  */
 358 #define RS RBS + 1
 359 #define RT RS
 360 #define RT_MASK (0x1f << 21)
 361   { 5, 21, 0, 0, PPC_OPERAND_GPR },
 362
 363   /* The SH field in an X or M form instruction.  */
 364 #define SH RS + 1
 365 #define SH_MASK (0x1f << 11)
 366   { 5, 11, 0, 0, 0 },
 367
 368   /* The SH field in an MD form instruction.  This is split.  */
 369 #define SH6 SH + 1
 370 #define SH6_MASK ((0x1f << 11) | (1 << 1))
 371   { 6, 1, insert_sh6, extract_sh6, 0 },
 372
 373   /* The SI field in a D form instruction.  */
 374 #define SI SH6 + 1
 375   { 16, 0, 0, 0, PPC_OPERAND_SIGNED },
 376
 377   /* The SI field in a D form instruction when we accept a wide range
 378      of positive values.  */
 379 #define SISIGNOPT SI + 1
 380   { 16, 0, 0, 0, PPC_OPERAND_SIGNED | PPC_OPERAND_SIGNOPT },
 381
 382   /* The SPR field in an XFX form instruction.  This is flipped--the
 383      lower 5 bits are stored in the upper 5 and vice- versa.  */
 384 #define SPR SISIGNOPT + 1
 385 #define SPR_MASK (0x3ff << 11)
 386   { 10, 11, insert_spr, extract_spr, 0 },
 387
 388   /* The BAT index number in an XFX form m[ft]ibat[lu] instruction.  */
 389 #define SPRBAT SPR + 1
 390 #define SPRBAT_MASK (0x3 << 17)
 391   { 2, 17, 0, 0, 0 },
 392
 393   /* The SPRG register number in an XFX form m[ft]sprg instruction.  */
 394 #define SPRG SPRBAT + 1
 395 #define SPRG_MASK (0x3 << 16)
 396   { 2, 16, 0, 0, 0 },
 397
 398   /* The SR field in an X form instruction.  */
 399 #define SR SPRG + 1
 400   { 4, 16, 0, 0, 0 },
 401
 402   /* The SV field in a POWER SC form instruction.  */
 403 #define SV SR + 1
 404   { 14, 2, 0, 0, 0 },
 405
 406   /* The TBR field in an XFX form instruction.  This is like the SPR
 407      field, but it is optional.  */
 408 #define TBR SV + 1
 409   { 10, 11, insert_tbr, extract_tbr, PPC_OPERAND_OPTIONAL },
 410
 411   /* The TO field in a D or X form instruction.  */
 412 #define TO TBR + 1
 413 #define TO_MASK (0x1f << 21)
 414   { 5, 21, 0, 0, 0 },
 415
 416   /* The U field in an X form instruction.  */
 417 #define U TO + 1
 418   { 4, 12, 0, 0, 0 },
 419
 420   /* The UI field in a D form instruction.  */
 421 #define UI U + 1
 422   { 16, 0, 0, 0, 0 },
 423
 424   /* The VA field in a VA, VX or VXR form instruction. */
 425 #define VA UI + 1
 426 #define VA_MASK (0x1f << 16)
 427   { 5, 16, 0, 0, PPC_OPERAND_VR },
 428
 429   /* The VB field in a VA, VX or VXR form instruction. */
 430 #define VB VA + 1
 431 #define VB_MASK (0x1f << 11)
 432   { 5, 11, 0, 0, PPC_OPERAND_VR },
 433
 434   /* The VC field in a VA form instruction. */
 435 #define VC VB + 1
 436 #define VC_MASK (0x1f << 6)
 437   { 5, 6, 0, 0, PPC_OPERAND_VR },
 438
 439   /* The VD or VS field in a VA, VX, VXR or X form instruction. */
 440 #define VD VC + 1
 441 #define VS VD
 442 #define VD_MASK (0x1f << 21)
 443   { 5, 21, 0, 0, PPC_OPERAND_VR },
 444
 445   /* The SIMM field in a VX form instruction. */
 446 #define SIMM VD + 1
 447   { 5, 16, 0, 0, PPC_OPERAND_SIGNED},
 448
 449   /* The UIMM field in a VX form instruction. */
 450 #define UIMM SIMM + 1
 451   { 5, 16, 0, 0, 0 },
 452
 453   /* The SHB field in a VA form instruction. */
 454 #define SHB UIMM + 1
 455   { 4, 6, 0, 0, 0 },
 456 };
 457
 458 /* The functions used to insert and extract complicated operands.  */
 459
 460 /* The BA field in an XL form instruction when it must be the same as
 461    the BT field in the same instruction.  This operand is marked FAKE.
 462    The insertion function just copies the BT field into the BA field,
 463    and the extraction function just checks that the fields are the
 464    same.  */
 465
 466 /*ARGSUSED*/
 467 static unsigned long
 468 insert_bat (insn, value, errmsg)
 469      unsigned long insn;
 470      long value ATTRIBUTE_UNUSED;
 471      const char **errmsg ATTRIBUTE_UNUSED;
 472 {
 473   return insn | (((insn >> 21) & 0x1f) << 16);
 474 }
 475
 476 static long
 477 extract_bat (insn, invalid)
 478      unsigned long insn;
 479      int *invalid;
 480 {
 481   if (invalid != (int *) NULL
 482       && ((insn >> 21) & 0x1f) != ((insn >> 16) & 0x1f))
 483     *invalid = 1;
 484   return 0;
 485 }
 486
 487 /* The BB field in an XL form instruction when it must be the same as
 488    the BA field in the same instruction.  This operand is marked FAKE.
 489    The insertion function just copies the BA field into the BB field,
 490    and the extraction function just checks that the fields are the
 491    same.  */
 492
 493 /*ARGSUSED*/
 494 static unsigned long
 495 insert_bba (insn, value, errmsg)
 496      unsigned long insn;
 497      long value ATTRIBUTE_UNUSED;
 498      const char **errmsg ATTRIBUTE_UNUSED;
 499 {
 500   return insn | (((insn >> 16) & 0x1f) << 11);
 501 }
 502
 503 static long
 504 extract_bba (insn, invalid)
 505      unsigned long insn;
 506      int *invalid;
 507 {
 508   if (invalid != (int *) NULL
 509       && ((insn >> 16) & 0x1f) != ((insn >> 11) & 0x1f))
 510     *invalid = 1;
 511   return 0;
 512 }
 513
 514 /* The BD field in a B form instruction.  The lower two bits are
 515    forced to zero.  */
 516
 517 /*ARGSUSED*/
 518 static unsigned long
 519 insert_bd (insn, value, errmsg)
 520      unsigned long insn;
 521      long value;
 522      const char **errmsg ATTRIBUTE_UNUSED;
 523 {
 524   return insn | (value & 0xfffc);
 525 }
 526
 527 /*ARGSUSED*/
 528 static long
 529 extract_bd (insn, invalid)
 530      unsigned long insn;
 531      int *invalid ATTRIBUTE_UNUSED;
 532 {
 533   if ((insn & 0x8000) != 0)
 534     return (insn & 0xfffc) - 0x10000;
 535   else
 536     return insn & 0xfffc;
 537 }
 538
 539 /* The BD field in a B form instruction when the - modifier is used.
 540    This modifier means that the branch is not expected to be taken.
 541    We must set the y bit of the BO field to 1 if the offset is
 542    negative.  When extracting, we require that the y bit be 1 and that
 543    the offset be positive, since if the y bit is 0 we just want to
 544    print the normal form of the instruction.  */
 545
 546 /*ARGSUSED*/
 547 static unsigned long
 548 insert_bdm (insn, value, errmsg)
 549      unsigned long insn;
 550      long value;
 551      const char **errmsg ATTRIBUTE_UNUSED;
 552 {
 553   if ((value & 0x8000) != 0)
 554     insn |= 1 << 21;
 555   return insn | (value & 0xfffc);
 556 }
 557
 558 static long
 559 extract_bdm (insn, invalid)
 560      unsigned long insn;
 561      int *invalid;
 562 {
 563   if (invalid != (int *) NULL
 564       && ((insn & (1 << 21)) == 0
 565           || (insn & (1 << 15)) == 0))
 566     *invalid = 1;
 567   if ((insn & 0x8000) != 0)
 568     return (insn & 0xfffc) - 0x10000;
 569   else
 570     return insn & 0xfffc;
 571 }
 572
 573 /* The BD field in a B form instruction when the + modifier is used.
 574    This is like BDM, above, except that the branch is expected to be
 575    taken.  */
 576
 577 /*ARGSUSED*/
 578 static unsigned long
 579 insert_bdp (insn, value, errmsg)
 580      unsigned long insn;
 581      long value;
 582      const char **errmsg ATTRIBUTE_UNUSED;
 583 {
 584   if ((value & 0x8000) == 0)
 585     insn |= 1 << 21;
 586   return insn | (value & 0xfffc);
 587 }
 588
 589 static long
 590 extract_bdp (insn, invalid)
 591      unsigned long insn;
 592      int *invalid;
 593 {
 594   if (invalid != (int *) NULL
 595       && ((insn & (1 << 21)) == 0
 596           || (insn & (1 << 15)) != 0))
 597     *invalid = 1;
 598   if ((insn & 0x8000) != 0)
 599     return (insn & 0xfffc) - 0x10000;
 600   else
 601     return insn & 0xfffc;
 602 }
 603
 604 /* Check for legal values of a BO field.  */
 605
 606 static int
 607 valid_bo (value)
 608      long value;
 609 {
 610   /* Certain encodings have bits that are required to be zero.  These
 611      are (z must be zero, y may be anything):
 612          001zy
 613          011zy
 614          1z00y
 615          1z01y
 616          1z1zz
 617      */
 618   switch (value & 0x14)
 619     {
 620     default:
 621     case 0:
 622       return 1;
 623     case 0x4:
 624       return (value & 0x2) == 0;
 625     case 0x10:
 626       return (value & 0x8) == 0;
 627     case 0x14:
 628       return value == 0x14;
 629     }
 630 }
 631
 632 /* The BO field in a B form instruction.  Warn about attempts to set
 633    the field to an illegal value.  */
 634
 635 static unsigned long
 636 insert_bo (insn, value, errmsg)
 637      unsigned long insn;
 638      long value;
 639      const char **errmsg;
 640 {
 641   if (errmsg != (const char **) NULL
 642       && ! valid_bo (value))
 643     *errmsg = _("invalid conditional option");
 644   return insn | ((value & 0x1f) << 21);
 645 }
 646
 647 static long
 648 extract_bo (insn, invalid)
 649      unsigned long insn;
 650      int *invalid;
 651 {
 652   long value;
 653
 654   value = (insn >> 21) & 0x1f;
 655   if (invalid != (int *) NULL
 656       && ! valid_bo (value))
 657     *invalid = 1;
 658   return value;
 659 }
 660
 661 /* The BO field in a B form instruction when the + or - modifier is
 662    used.  This is like the BO field, but it must be even.  When
 663    extracting it, we force it to be even.  */
 664
 665 static unsigned long
 666 insert_boe (insn, value, errmsg)
 667      unsigned long insn;
 668      long value;
 669      const char **errmsg;
 670 {
 671   if (errmsg != (const char **) NULL)
 672     {
 673       if (! valid_bo (value))
 674         *errmsg = _("invalid conditional option");
 675       else if ((value & 1) != 0)
 676         *errmsg = _("attempt to set y bit when using + or - modifier");
 677     }
 678   return insn | ((value & 0x1f) << 21);
 679 }
 680
 681 static long
 682 extract_boe (insn, invalid)
 683      unsigned long insn;
 684      int *invalid;
 685 {
 686   long value;
 687
 688   value = (insn >> 21) & 0x1f;
 689   if (invalid != (int *) NULL
 690       && ! valid_bo (value))
 691     *invalid = 1;
 692   return value & 0x1e;
 693 }
 694
 695 /* The DS field in a DS form instruction.  This is like D, but the
 696    lower two bits are forced to zero.  */
 697
 698 /*ARGSUSED*/
 699 static unsigned long
 700 insert_ds (insn, value, errmsg)
 701      unsigned long insn;
 702      long value;
 703      const char **errmsg;
 704 {
 705   if ((value & 3) != 0 && errmsg != NULL)
 706     *errmsg = _("offset not a multiple of 4");
 707   return insn | (value & 0xfffc);
 708 }
 709
 710 /*ARGSUSED*/
 711 static long
 712 extract_ds (insn, invalid)
 713      unsigned long insn;
 714      int *invalid ATTRIBUTE_UNUSED;
 715 {
 716   if ((insn & 0x8000) != 0)
 717     return (insn & 0xfffc) - 0x10000;
 718   else
 719     return insn & 0xfffc;
 720 }
 721
 722 /* The DE field in a DE form instruction.  */
 723
 724 /*ARGSUSED*/
 725 static unsigned long
 726 insert_de (insn, value, errmsg)
 727      unsigned long insn;
 728      long value;
 729      const char **errmsg;
 730 {
 731   if ((value > 2047 || value < -2048) && errmsg != NULL)
 732     *errmsg = _("offset not between -2048 and 2047");
 733   return insn | ((value << 4) & 0xfff0);
 734 }
 735
 736 /*ARGSUSED*/
 737 static long
 738 extract_de (insn, invalid)
 739      unsigned long insn;
 740      int *invalid ATTRIBUTE_UNUSED;
 741 {
 742   return (insn & 0xfff0) >> 4;
 743 }
 744
 745 /* The DES field in a DES form instruction.  */
 746
 747 /*ARGSUSED*/
 748 static unsigned long
 749 insert_des (insn, value, errmsg)
 750      unsigned long insn;
 751      long value;
 752      const char **errmsg;
 753 {
 754   if ((value > 8191 || value < -8192) && errmsg != NULL)
 755     *errmsg = _("offset not between -8192 and 8191");
 756   else if ((value & 3) != 0 && errmsg != NULL)
 757     *errmsg = _("offset not a multiple of 4");
 758   return insn | ((value << 2) & 0xfff0);
 759 }
 760
 761 /*ARGSUSED*/
 762 static long
 763 extract_des (insn, invalid)
 764      unsigned long insn;
 765      int *invalid ATTRIBUTE_UNUSED;
 766 {
 767   if ((insn & 0x8000) != 0)
 768     return ((insn & 0xfff0) >> 2) - 0x4000;
 769   else
 770     return (insn & 0xfff0) >> 2;
 771 }
 772
 773 /* The LI field in an I form instruction.  The lower two bits are
 774    forced to zero.  */
 775
 776 /*ARGSUSED*/
 777 static unsigned long
 778 insert_li (insn, value, errmsg)
 779      unsigned long insn;
 780      long value;
 781      const char **errmsg;
 782 {
 783   if ((value & 3) != 0 && errmsg != (const char **) NULL)
 784     *errmsg = _("ignoring least significant bits in branch offset");
 785   return insn | (value & 0x3fffffc);
 786 }
 787
 788 /*ARGSUSED*/
 789 static long
 790 extract_li (insn, invalid)
 791      unsigned long insn;
 792      int *invalid ATTRIBUTE_UNUSED;
 793 {
 794   if ((insn & 0x2000000) != 0)
 795     return (insn & 0x3fffffc) - 0x4000000;
 796   else
 797     return insn & 0x3fffffc;
 798 }
 799
 800 /* The MB and ME fields in an M form instruction expressed as a single
 801    operand which is itself a bitmask.  The extraction function always
 802    marks it as invalid, since we never want to recognize an
 803    instruction which uses a field of this type.  */
 804
 805 static unsigned long
 806 insert_mbe (insn, value, errmsg)
 807      unsigned long insn;
 808      long value;
 809      const char **errmsg;
 810 {
 811   unsigned long uval, mask;
 812   int mb, me, mx, count, last;
 813
 814   uval = value;
 815
 816   if (uval == 0)
 817     {
 818       if (errmsg != (const char **) NULL)
 819         *errmsg = _("illegal bitmask");
 820       return insn;
 821     }
 822
 823   mb = 0;
 824   me = 32;
 825   if ((uval & 1) != 0)
 826     last = 1;
 827   else
 828     last = 0;
 829   count = 0;
 830
 831   /* mb: location of last 0->1 transition */
 832   /* me: location of last 1->0 transition */
 833   /* count: # transitions */
 834
 835   for (mx = 0, mask = (long) 1 << 31; mx < 32; ++mx, mask >>= 1)
 836     {
 837       if ((uval & mask) && !last)
 838         {
 839           ++count;
 840           mb = mx;
 841           last = 1;
 842         }
 843       else if (!(uval & mask) && last)
 844         {
 845           ++count;
 846           me = mx;
 847           last = 0;
 848         }
 849     }
 850   if (me == 0)
 851     me = 32;
 852
 853   if (count != 2 && (count != 0 || ! last))
 854     {
 855       if (errmsg != (const char **) NULL)
 856         *errmsg = _("illegal bitmask");
 857     }
 858
 859   return insn | (mb << 6) | ((me - 1) << 1);
 860 }
 861
 862 static long
 863 extract_mbe (insn, invalid)
 864      unsigned long insn;
 865      int *invalid;
 866 {
 867   long ret;
 868   int mb, me;
 869   int i;
 870
 871   if (invalid != (int *) NULL)
 872     *invalid = 1;
 873
 874   mb = (insn >> 6) & 0x1f;
 875   me = (insn >> 1) & 0x1f;
 876   if (mb < me + 1)
 877     {
 878       ret = 0;
 879       for (i = mb; i <= me; i++)
 880         ret |= (long) 1 << (31 - i);
 881     }
 882   else if (mb == me + 1)
 883     ret = ~0;
 884   else /* (mb > me + 1) */
 885     {
 886       ret = ~ (long) 0;
 887       for (i = me + 1; i < mb; i++)
 888         ret &= ~ ((long) 1 << (31 - i));
 889     }
 890   return ret;
 891 }
 892
 893 /* The MB or ME field in an MD or MDS form instruction.  The high bit
 894    is wrapped to the low end.  */
 895
 896 /*ARGSUSED*/
 897 static unsigned long
 898 insert_mb6 (insn, value, errmsg)
 899      unsigned long insn;
 900      long value;
 901      const char **errmsg ATTRIBUTE_UNUSED;
 902 {
 903   return insn | ((value & 0x1f) << 6) | (value & 0x20);
 904 }
 905
 906 /*ARGSUSED*/
 907 static long
 908 extract_mb6 (insn, invalid)
 909      unsigned long insn;
 910      int *invalid ATTRIBUTE_UNUSED;
 911 {
 912   return ((insn >> 6) & 0x1f) | (insn & 0x20);
 913 }
 914
 915 /* The NB field in an X form instruction.  The value 32 is stored as
 916    0.  */
 917
 918 static unsigned long
 919 insert_nb (insn, value, errmsg)
 920      unsigned long insn;
 921      long value;
 922      const char **errmsg;
 923 {
 924   if (value < 0 || value > 32)
 925     *errmsg = _("value out of range");
 926   if (value == 32)
 927     value = 0;
 928   return insn | ((value & 0x1f) << 11);
 929 }
 930
 931 /*ARGSUSED*/
 932 static long
 933 extract_nb (insn, invalid)
 934      unsigned long insn;
 935      int *invalid ATTRIBUTE_UNUSED;
 936 {
 937   long ret;
 938
 939   ret = (insn >> 11) & 0x1f;
 940   if (ret == 0)
 941     ret = 32;
 942   return ret;
 943 }
 944
 945 /* The NSI field in a D form instruction.  This is the same as the SI
 946    field, only negated.  The extraction function always marks it as
 947    invalid, since we never want to recognize an instruction which uses
 948    a field of this type.  */
 949
 950 /*ARGSUSED*/
 951 static unsigned long
 952 insert_nsi (insn, value, errmsg)
 953      unsigned long insn;
 954      long value;
 955      const char **errmsg ATTRIBUTE_UNUSED;
 956 {
 957   return insn | ((- value) & 0xffff);
 958 }
 959
 960 static long
 961 extract_nsi (insn, invalid)
 962      unsigned long insn;
 963      int *invalid;
 964 {
 965   if (invalid != (int *) NULL)
 966     *invalid = 1;
 967   if ((insn & 0x8000) != 0)
 968     return - ((long)(insn & 0xffff) - 0x10000);
 969   else
 970     return - (long)(insn & 0xffff);
 971 }
 972
 973 /* The RA field in a D or X form instruction which is an updating
 974    load, which means that the RA field may not be zero and may not
 975    equal the RT field.  */
 976
 977 static unsigned long
 978 insert_ral (insn, value, errmsg)
 979      unsigned long insn;
 980      long value;
 981      const char **errmsg;
 982 {
 983   if (value == 0
 984       || (unsigned long) value == ((insn >> 21) & 0x1f))
 985     *errmsg = "invalid register operand when updating";
 986   return insn | ((value & 0x1f) << 16);
 987 }
 988
 989 /* The RA field in an lmw instruction, which has special value
 990    restrictions.  */
 991
 992 static unsigned long
 993 insert_ram (insn, value, errmsg)
 994      unsigned long insn;
 995      long value;
 996      const char **errmsg;
 997 {
 998   if ((unsigned long) value >= ((insn >> 21) & 0x1f))
 999     *errmsg = _("index register in load range");
1000   return insn | ((value & 0x1f) << 16);
1001 }
1002
1003 /* The RA field in a D or X form instruction which is an updating
1004    store or an updating floating point load, which means that the RA
1005    field may not be zero.  */
1006
1007 static unsigned long
1008 insert_ras (insn, value, errmsg)
1009      unsigned long insn;
1010      long value;
1011      const char **errmsg;
1012 {
1013   if (value == 0)
1014     *errmsg = _("invalid register operand when updating");
1015   return insn | ((value & 0x1f) << 16);
1016 }
1017
1018 /* The RB field in an X form instruction when it must be the same as
1019    the RS field in the instruction.  This is used for extended
1020    mnemonics like mr.  This operand is marked FAKE.  The insertion
1021    function just copies the BT field into the BA field, and the
1022    extraction function just checks that the fields are the same.  */
1023
1024 /*ARGSUSED*/
1025 static unsigned long
1026 insert_rbs (insn, value, errmsg)
1027      unsigned long insn;
1028      long value ATTRIBUTE_UNUSED;
1029      const char **errmsg ATTRIBUTE_UNUSED;
1030 {
1031   return insn | (((insn >> 21) & 0x1f) << 11);
1032 }
1033
1034 static long
1035 extract_rbs (insn, invalid)
1036      unsigned long insn;
1037      int *invalid;
1038 {
1039   if (invalid != (int *) NULL
1040       && ((insn >> 21) & 0x1f) != ((insn >> 11) & 0x1f))
1041     *invalid = 1;
1042   return 0;
1043 }
1044
1045 /* The SH field in an MD form instruction.  This is split.  */
1046
1047 /*ARGSUSED*/
1048 static unsigned long
1049 insert_sh6 (insn, value, errmsg)
1050      unsigned long insn;
1051      long value;
1052      const char **errmsg ATTRIBUTE_UNUSED;
1053 {
1054   return insn | ((value & 0x1f) << 11) | ((value & 0x20) >> 4);
1055 }
1056
1057 /*ARGSUSED*/
1058 static long
1059 extract_sh6 (insn, invalid)
1060      unsigned long insn;
1061      int *invalid ATTRIBUTE_UNUSED;
1062 {
1063   return ((insn >> 11) & 0x1f) | ((insn << 4) & 0x20);
1064 }
1065
1066 /* The SPR field in an XFX form instruction.  This is flipped--the
1067    lower 5 bits are stored in the upper 5 and vice- versa.  */
1068
1069 static unsigned long
1070 insert_spr (insn, value, errmsg)
1071      unsigned long insn;
1072      long value;
1073      const char **errmsg ATTRIBUTE_UNUSED;
1074 {
1075   return insn | ((value & 0x1f) << 16) | ((value & 0x3e0) << 6);
1076 }
1077
1078 static long
1079 extract_spr (insn, invalid)
1080      unsigned long insn;
1081      int *invalid ATTRIBUTE_UNUSED;
1082 {
1083   return ((insn >> 16) & 0x1f) | ((insn >> 6) & 0x3e0);
1084 }
1085
1086 /* The TBR field in an XFX instruction.  This is just like SPR, but it
1087    is optional.  When TBR is omitted, it must be inserted as 268 (the
1088    magic number of the TB register).  These functions treat 0
1089    (indicating an omitted optional operand) as 268.  This means that
1090    ``mftb 4,0'' is not handled correctly.  This does not matter very
1091    much, since the architecture manual does not define mftb as
1092    accepting any values other than 268 or 269.  */
1093
1094 #define TB (268)
1095
1096 static unsigned long
1097 insert_tbr (insn, value, errmsg)
1098      unsigned long insn;
1099      long value;
1100      const char **errmsg ATTRIBUTE_UNUSED;
1101 {
1102   if (value == 0)
1103     value = TB;
1104   return insn | ((value & 0x1f) << 16) | ((value & 0x3e0) << 6);
1105 }
1106
1107 static long
1108 extract_tbr (insn, invalid)
1109      unsigned long insn;
1110      int *invalid ATTRIBUTE_UNUSED;
1111 {
1112   long ret;
1113
1114   ret = ((insn >> 16) & 0x1f) | ((insn >> 6) & 0x3e0);
1115   if (ret == TB)
1116     ret = 0;
1117   return ret;
1118 }
1119 \f
1120 /* Macros used to form opcodes.  */
1121
1122 /* The main opcode.  */
1123 #define OP(x) ((((unsigned long)(x)) & 0x3f) << 26)
1124 #define OP_MASK OP (0x3f)
1125
1126 /* The main opcode combined with a trap code in the TO field of a D
1127    form instruction.  Used for extended mnemonics for the trap
1128    instructions.  */
1129 #define OPTO(x,to) (OP (x) | ((((unsigned long)(to)) & 0x1f) << 21))
1130 #define OPTO_MASK (OP_MASK | TO_MASK)
1131
1132 /* The main opcode combined with a comparison size bit in the L field
1133    of a D form or X form instruction.  Used for extended mnemonics for
1134    the comparison instructions.  */
1135 #define OPL(x,l) (OP (x) | ((((unsigned long)(l)) & 1) << 21))
1136 #define OPL_MASK OPL (0x3f,1)
1137
1138 /* An A form instruction.  */
1139 #define A(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0x1f) << 1) | (((unsigned long)(rc)) & 1))
1140 #define A_MASK A (0x3f, 0x1f, 1)
1141
1142 /* An A_MASK with the FRB field fixed.  */
1143 #define AFRB_MASK (A_MASK | FRB_MASK)
1144
1145 /* An A_MASK with the FRC field fixed.  */
1146 #define AFRC_MASK (A_MASK | FRC_MASK)
1147
1148 /* An A_MASK with the FRA and FRC fields fixed.  */
1149 #define AFRAFRC_MASK (A_MASK | FRA_MASK | FRC_MASK)
1150
1151 /* A B form instruction.  */
1152 #define B(op, aa, lk) (OP (op) | ((((unsigned long)(aa)) & 1) << 1) | ((lk) & 1))
1153 #define B_MASK B (0x3f, 1, 1)
1154
1155 /* A B form instruction setting the BO field.  */
1156 #define BBO(op, bo, aa, lk) (B ((op), (aa), (lk)) | ((((unsigned long)(bo)) & 0x1f) << 21))
1157 #define BBO_MASK BBO (0x3f, 0x1f, 1, 1)
1158
1159 /* A BBO_MASK with the y bit of the BO field removed.  This permits
1160    matching a conditional branch regardless of the setting of the y
1161    bit.  */
1162 #define Y_MASK (((unsigned long)1) << 21)
1163 #define BBOY_MASK (BBO_MASK &~ Y_MASK)
1164
1165 /* A B form instruction setting the BO field and the condition bits of
1166    the BI field.  */
1167 #define BBOCB(op, bo, cb, aa, lk) \
1168   (BBO ((op), (bo), (aa), (lk)) | ((((unsigned long)(cb)) & 0x3) << 16))
1169 #define BBOCB_MASK BBOCB (0x3f, 0x1f, 0x3, 1, 1)
1170
1171 /* A BBOCB_MASK with the y bit of the BO field removed.  */
1172 #define BBOYCB_MASK (BBOCB_MASK &~ Y_MASK)
1173
1174 /* A BBOYCB_MASK in which the BI field is fixed.  */
1175 #define BBOYBI_MASK (BBOYCB_MASK | BI_MASK)
1176
1177 /* The main opcode mask with the RA field clear.  */
1178 #define DRA_MASK (OP_MASK | RA_MASK)
1179
1180 /* A DS form instruction.  */
1181 #define DSO(op, xop) (OP (op) | ((xop) & 0x3))
1182 #define DS_MASK DSO (0x3f, 3)
1183
1184 /* A DE form instruction.  */
1185 #define DEO(op, xop) (OP (op) | ((xop) & 0xf))
1186 #define DE_MASK DEO (0x3e, 0xf)
1187
1188 /* An M form instruction.  */
1189 #define M(op, rc) (OP (op) | ((rc) & 1))
1190 #define M_MASK M (0x3f, 1)
1191
1192 /* An M form instruction with the ME field specified.  */
1193 #define MME(op, me, rc) (M ((op), (rc)) | ((((unsigned long)(me)) & 0x1f) << 1))
1194
1195 /* An M_MASK with the MB and ME fields fixed.  */
1196 #define MMBME_MASK (M_MASK | MB_MASK | ME_MASK)
1197
1198 /* An M_MASK with the SH and ME fields fixed.  */
1199 #define MSHME_MASK (M_MASK | SH_MASK | ME_MASK)
1200
1201 /* An MD form instruction.  */
1202 #define MD(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0x7) << 2) | ((rc) & 1))
1203 #define MD_MASK MD (0x3f, 0x7, 1)
1204
1205 /* An MD_MASK with the MB field fixed.  */
1206 #define MDMB_MASK (MD_MASK | MB6_MASK)
1207
1208 /* An MD_MASK with the SH field fixed.  */
1209 #define MDSH_MASK (MD_MASK | SH6_MASK)
1210
1211 /* An MDS form instruction.  */
1212 #define MDS(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0xf) << 1) | ((rc) & 1))
1213 #define MDS_MASK MDS (0x3f, 0xf, 1)
1214
1215 /* An MDS_MASK with the MB field fixed.  */
1216 #define MDSMB_MASK (MDS_MASK | MB6_MASK)
1217
1218 /* An SC form instruction.  */
1219 #define SC(op, sa, lk) (OP (op) | ((((unsigned long)(sa)) & 1) << 1) | ((lk) & 1))
1220 #define SC_MASK (OP_MASK | (((unsigned long)0x3ff) << 16) | (((unsigned long)1) << 1) | 1)
1221
1222 /* An VX form instruction. */
1223 #define VX(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x7ff))
1224
1225 /* The mask for an VX form instruction. */
1226 #define VX_MASK VX(0x3f, 0x7ff)
1227
1228 /* An VA form instruction. */
1229 #define VXA(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x03f))
1230
1231 /* The mask for an VA form instruction. */
1232 #define VXA_MASK VXA(0x3f, 0x3f)
1233
1234 /* An VXR form instruction. */
1235 #define VXR(op, xop, rc) (OP (op) | (((rc) & 1) << 10) | (((unsigned long)(xop)) & 0x3ff))
1236
1237 /* The mask for a VXR form instruction. */
1238 #define VXR_MASK VXR(0x3f, 0x3ff, 1)
1239
1240 /* An X form instruction.  */
1241 #define X(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x3ff) << 1))
1242
1243 /* An X form instruction with the RC bit specified.  */
1244 #define XRC(op, xop, rc) (X ((op), (xop)) | ((rc) & 1))
1245
1246 /* The mask for an X form instruction.  */
1247 #define X_MASK XRC (0x3f, 0x3ff, 1)
1248
1249 /* An X_MASK with the RA field fixed.  */
1250 #define XRA_MASK (X_MASK | RA_MASK)
1251
1252 /* An X_MASK with the RB field fixed.  */
1253 #define XRB_MASK (X_MASK | RB_MASK)
1254
1255 /* An X_MASK with the RT field fixed.  */
1256 #define XRT_MASK (X_MASK | RT_MASK)
1257
1258 /* An X_MASK with the RA and RB fields fixed.  */
1259 #define XRARB_MASK (X_MASK | RA_MASK | RB_MASK)
1260
1261 /* An X_MASK with the RT and RA fields fixed.  */
1262 #define XRTRA_MASK (X_MASK | RT_MASK | RA_MASK)
1263
1264 /* An X form comparison instruction.  */
1265 #define XCMPL(op, xop, l) (X ((op), (xop)) | ((((unsigned long)(l)) & 1) << 21))
1266
1267 /* The mask for an X form comparison instruction.  */
1268 #define XCMP_MASK (X_MASK | (((unsigned long)1) << 22))
1269
1270 /* The mask for an X form comparison instruction with the L field
1271    fixed.  */
1272 #define XCMPL_MASK (XCMP_MASK | (((unsigned long)1) << 21))
1273
1274 /* An X form trap instruction with the TO field specified.  */
1275 #define XTO(op, xop, to) (X ((op), (xop)) | ((((unsigned long)(to)) & 0x1f) << 21))
1276 #define XTO_MASK (X_MASK | TO_MASK)
1277
1278 /* An X form tlb instruction with the SH field specified.  */
1279 #define XTLB(op, xop, sh) (X ((op), (xop)) | ((((unsigned long)(sh)) & 0x1f) << 11))
1280 #define XTLB_MASK (X_MASK | SH_MASK)
1281
1282 /* An X form sync instruction.  */
1283 #define XSYNC(op, xop, l) (X ((op), (xop)) | ((((unsigned long)(l)) & 3) << 21))
1284
1285 /* An X form sync instruction with everything filled in except the LS field.  */
1286 #define XSYNC_MASK (0xff9fffff)
1287
1288 /* An XFL form instruction.  */
1289 #define XFL(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0x3ff) << 1) | (((unsigned long)(rc)) & 1))
1290 #define XFL_MASK (XFL (0x3f, 0x3ff, 1) | (((unsigned long)1) << 25) | (((unsigned long)1) << 16))
1291
1292 /* An XL form instruction with the LK field set to 0.  */
1293 #define XL(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x3ff) << 1))
1294
1295 /* An XL form instruction which uses the LK field.  */
1296 #define XLLK(op, xop, lk) (XL ((op), (xop)) | ((lk) & 1))
1297
1298 /* The mask for an XL form instruction.  */
1299 #define XL_MASK XLLK (0x3f, 0x3ff, 1)
1300
1301 /* An XL form instruction which explicitly sets the BO field.  */
1302 #define XLO(op, bo, xop, lk) \
1303   (XLLK ((op), (xop), (lk)) | ((((unsigned long)(bo)) & 0x1f) << 21))
1304 #define XLO_MASK (XL_MASK | BO_MASK)
1305
1306 /* An XL form instruction which explicitly sets the y bit of the BO
1307    field.  */
1308 #define XLYLK(op, xop, y, lk) (XLLK ((op), (xop), (lk)) | ((((unsigned long)(y)) & 1) << 21))
1309 #define XLYLK_MASK (XL_MASK | Y_MASK)
1310
1311 /* An XL form instruction which sets the BO field and the condition
1312    bits of the BI field.  */
1313 #define XLOCB(op, bo, cb, xop, lk) \
1314   (XLO ((op), (bo), (xop), (lk)) | ((((unsigned long)(cb)) & 3) << 16))
1315 #define XLOCB_MASK XLOCB (0x3f, 0x1f, 0x3, 0x3ff, 1)
1316
1317 /* An XL_MASK or XLYLK_MASK or XLOCB_MASK with the BB field fixed.  */
1318 #define XLBB_MASK (XL_MASK | BB_MASK)
1319 #define XLYBB_MASK (XLYLK_MASK | BB_MASK)
1320 #define XLBOCBBB_MASK (XLOCB_MASK | BB_MASK)
1321
1322 /* An XL_MASK with the BO and BB fields fixed.  */
1323 #define XLBOBB_MASK (XL_MASK | BO_MASK | BB_MASK)
1324
1325 /* An XL_MASK with the BO, BI and BB fields fixed.  */
1326 #define XLBOBIBB_MASK (XL_MASK | BO_MASK | BI_MASK | BB_MASK)
1327
1328 /* An XO form instruction.  */
1329 #define XO(op, xop, oe, rc) \
1330   (OP (op) | ((((unsigned long)(xop)) & 0x1ff) << 1) | ((((unsigned long)(oe)) & 1) << 10) | (((unsigned long)(rc)) & 1))
1331 #define XO_MASK XO (0x3f, 0x1ff, 1, 1)
1332
1333 /* An XO_MASK with the RB field fixed.  */
1334 #define XORB_MASK (XO_MASK | RB_MASK)
1335
1336 /* An XS form instruction.  */
1337 #define XS(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0x1ff) << 2) | (((unsigned long)(rc)) & 1))
1338 #define XS_MASK XS (0x3f, 0x1ff, 1)
1339
1340 /* A mask for the FXM version of an XFX form instruction.  */
1341 #define XFXFXM_MASK (X_MASK | (((unsigned long)1) << 20) | (((unsigned long)1) << 11))
1342
1343 /* An XFX form instruction with the FXM field filled in.  */
1344 #define XFXM(op, xop, fxm) \
1345   (X ((op), (xop)) | ((((unsigned long)(fxm)) & 0xff) << 12))
1346
1347 /* An XFX form instruction with the SPR field filled in.  */
1348 #define XSPR(op, xop, spr) \
1349   (X ((op), (xop)) | ((((unsigned long)(spr)) & 0x1f) << 16) | ((((unsigned long)(spr)) & 0x3e0) << 6))
1350 #define XSPR_MASK (X_MASK | SPR_MASK)
1351
1352 /* An XFX form instruction with the SPR field filled in except for the
1353    SPRBAT field.  */
1354 #define XSPRBAT_MASK (XSPR_MASK &~ SPRBAT_MASK)
1355
1356 /* An XFX form instruction with the SPR field filled in except for the
1357    SPRG field.  */
1358 #define XSPRG_MASK (XSPR_MASK &~ SPRG_MASK)
1359
1360 /* An X form instruction with everything filled in except the E field.  */
1361 #define XE_MASK (0xffff7fff)
1362
1363 /* The BO encodings used in extended conditional branch mnemonics.  */
1364 #define BODNZF  (0x0)
1365 #define BODNZFP (0x1)
1366 #define BODZF   (0x2)
1367 #define BODZFP  (0x3)
1368 #define BOF     (0x4)
1369 #define BOFP    (0x5)
1370 #define BODNZT  (0x8)
1371 #define BODNZTP (0x9)
1372 #define BODZT   (0xa)
1373 #define BODZTP  (0xb)
1374 #define BOT     (0xc)
1375 #define BOTP    (0xd)
1376 #define BODNZ   (0x10)
1377 #define BODNZP  (0x11)
1378 #define BODZ    (0x12)
1379 #define BODZP   (0x13)
1380 #define BOU     (0x14)
1381
1382 /* The BI condition bit encodings used in extended conditional branch
1383    mnemonics.  */
1384 #define CBLT    (0)
1385 #define CBGT    (1)
1386 #define CBEQ    (2)
1387 #define CBSO    (3)
1388
1389 /* The TO encodings used in extended trap mnemonics.  */
1390 #define TOLGT   (0x1)
1391 #define TOLLT   (0x2)
1392 #define TOEQ    (0x4)
1393 #define TOLGE   (0x5)
1394 #define TOLNL   (0x5)
1395 #define TOLLE   (0x6)
1396 #define TOLNG   (0x6)
1397 #define TOGT    (0x8)
1398 #define TOGE    (0xc)
1399 #define TONL    (0xc)
1400 #define TOLT    (0x10)
1401 #define TOLE    (0x14)
1402 #define TONG    (0x14)
1403 #define TONE    (0x18)
1404 #define TOU     (0x1f)
1405 \f
1406 /* Smaller names for the flags so each entry in the opcodes table will
1407    fit on a single line.  */
1408 #undef  PPC
1409 #define PPC     PPC_OPCODE_PPC | PPC_OPCODE_ANY
1410 #define PPCCOM  PPC_OPCODE_PPC | PPC_OPCODE_COMMON | PPC_OPCODE_ANY
1411 #define PPC32   PPC_OPCODE_PPC | PPC_OPCODE_32 | PPC_OPCODE_ANY
1412 #define PPC64   PPC_OPCODE_64 | PPC_OPCODE_ANY
1413 #define PPCONLY PPC_OPCODE_PPC
1414 #define PPC403  PPC_OPCODE_403
1415 #define PPC405  PPC403
1416 #define PPC750  PPC
1417 #define PPC860  PPC
1418 #define PPCVEC  PPC_OPCODE_ALTIVEC | PPC_OPCODE_ANY
1419 #define POWER   PPC_OPCODE_POWER | PPC_OPCODE_ANY
1420 #define POWER2  PPC_OPCODE_POWER | PPC_OPCODE_POWER2 | PPC_OPCODE_ANY
1421 #define PPCPWR2 PPC_OPCODE_PPC | PPC_OPCODE_POWER | PPC_OPCODE_POWER2 | PPC_OPCODE_ANY
1422 #define POWER32 PPC_OPCODE_POWER | PPC_OPCODE_ANY | PPC_OPCODE_32
1423 #define COM     PPC_OPCODE_POWER | PPC_OPCODE_PPC | PPC_OPCODE_COMMON | PPC_OPCODE_ANY
1424 #define COM32   PPC_OPCODE_POWER | PPC_OPCODE_PPC | PPC_OPCODE_COMMON | PPC_OPCODE_ANY | PPC_OPCODE_32
1425 #define M601    PPC_OPCODE_POWER | PPC_OPCODE_601 | PPC_OPCODE_ANY
1426 #define PWRCOM  PPC_OPCODE_POWER | PPC_OPCODE_601 | PPC_OPCODE_COMMON | PPC_OPCODE_ANY
1427 #define MFDEC1  PPC_OPCODE_POWER
1428 #define MFDEC2  PPC_OPCODE_PPC | PPC_OPCODE_601
1429 #define BOOKE   PPC_OPCODE_BOOKE
1430 #define BOOKE64 PPC_OPCODE_BOOKE64
1431 \f
1432 /* The opcode table.
1433
1434    The format of the opcode table is:
1435
1436    NAME      OPCODE     MASK            FLAGS           { OPERANDS }
1437
1438    NAME is the name of the instruction.
1439    OPCODE is the instruction opcode.
1440    MASK is the opcode mask; this is used to tell the disassembler
1441      which bits in the actual opcode must match OPCODE.
1442    FLAGS are flags indicated what processors support the instruction.
1443    OPERANDS is the list of operands.
1444
1445    The disassembler reads the table in order and prints the first
1446    instruction which matches, so this table is sorted to put more
1447    specific instructions before more general instructions.  It is also
1448    sorted by major opcode.  */
1449
1450 const struct powerpc_opcode powerpc_opcodes[] = {
1451 { "tdlgti",  OPTO(2,TOLGT), OPTO_MASK,  PPC64,          { RA, SI } },
1452 { "tdllti",  OPTO(2,TOLLT), OPTO_MASK,  PPC64,          { RA, SI } },
1453 { "tdeqi",   OPTO(2,TOEQ), OPTO_MASK,   PPC64,          { RA, SI } },
1454 { "tdlgei",  OPTO(2,TOLGE), OPTO_MASK,  PPC64,          { RA, SI } },
1455 { "tdlnli",  OPTO(2,TOLNL), OPTO_MASK,  PPC64,          { RA, SI } },
1456 { "tdllei",  OPTO(2,TOLLE), OPTO_MASK,  PPC64,          { RA, SI } },
1457 { "tdlngi",  OPTO(2,TOLNG), OPTO_MASK,  PPC64,          { RA, SI } },
1458 { "tdgti",   OPTO(2,TOGT), OPTO_MASK,   PPC64,          { RA, SI } },
1459 { "tdgei",   OPTO(2,TOGE), OPTO_MASK,   PPC64,          { RA, SI } },
1460 { "tdnli",   OPTO(2,TONL), OPTO_MASK,   PPC64,          { RA, SI } },
1461 { "tdlti",   OPTO(2,TOLT), OPTO_MASK,   PPC64,          { RA, SI } },
1462 { "tdlei",   OPTO(2,TOLE), OPTO_MASK,   PPC64,          { RA, SI } },
1463 { "tdngi",   OPTO(2,TONG), OPTO_MASK,   PPC64,          { RA, SI } },
1464 { "tdnei",   OPTO(2,TONE), OPTO_MASK,   PPC64,          { RA, SI } },
1465 { "tdi",     OP(2),     OP_MASK,        PPC64,          { TO, RA, SI } },
1466
1467 { "twlgti",  OPTO(3,TOLGT), OPTO_MASK,  PPCCOM,         { RA, SI } },
1468 { "tlgti",   OPTO(3,TOLGT), OPTO_MASK,  PWRCOM,         { RA, SI } },
1469 { "twllti",  OPTO(3,TOLLT), OPTO_MASK,  PPCCOM,         { RA, SI } },
1470 { "tllti",   OPTO(3,TOLLT), OPTO_MASK,  PWRCOM,         { RA, SI } },
1471 { "tweqi",   OPTO(3,TOEQ), OPTO_MASK,   PPCCOM,         { RA, SI } },
1472 { "teqi",    OPTO(3,TOEQ), OPTO_MASK,   PWRCOM,         { RA, SI } },
1473 { "twlgei",  OPTO(3,TOLGE), OPTO_MASK,  PPCCOM,         { RA, SI } },
1474 { "tlgei",   OPTO(3,TOLGE), OPTO_MASK,  PWRCOM,         { RA, SI } },
1475 { "twlnli",  OPTO(3,TOLNL), OPTO_MASK,  PPCCOM,         { RA, SI } },
1476 { "tlnli",   OPTO(3,TOLNL), OPTO_MASK,  PWRCOM,         { RA, SI } },
1477 { "twllei",  OPTO(3,TOLLE), OPTO_MASK,  PPCCOM,         { RA, SI } },
1478 { "tllei",   OPTO(3,TOLLE), OPTO_MASK,  PWRCOM,         { RA, SI } },
1479 { "twlngi",  OPTO(3,TOLNG), OPTO_MASK,  PPCCOM,         { RA, SI } },
1480 { "tlngi",   OPTO(3,TOLNG), OPTO_MASK,  PWRCOM,         { RA, SI } },
1481 { "twgti",   OPTO(3,TOGT), OPTO_MASK,   PPCCOM,         { RA, SI } },
1482 { "tgti",    OPTO(3,TOGT), OPTO_MASK,   PWRCOM,         { RA, SI } },
1483 { "twgei",   OPTO(3,TOGE), OPTO_MASK,   PPCCOM,         { RA, SI } },
1484 { "tgei",    OPTO(3,TOGE), OPTO_MASK,   PWRCOM,         { RA, SI } },
1485 { "twnli",   OPTO(3,TONL), OPTO_MASK,   PPCCOM,         { RA, SI } },
1486 { "tnli",    OPTO(3,TONL), OPTO_MASK,   PWRCOM,         { RA, SI } },
1487 { "twlti",   OPTO(3,TOLT), OPTO_MASK,   PPCCOM,         { RA, SI } },
1488 { "tlti",    OPTO(3,TOLT), OPTO_MASK,   PWRCOM,         { RA, SI } },
1489 { "twlei",   OPTO(3,TOLE), OPTO_MASK,   PPCCOM,         { RA, SI } },
1490 { "tlei",    OPTO(3,TOLE), OPTO_MASK,   PWRCOM,         { RA, SI } },
1491 { "twngi",   OPTO(3,TONG), OPTO_MASK,   PPCCOM,         { RA, SI } },
1492 { "tngi",    OPTO(3,TONG), OPTO_MASK,   PWRCOM,         { RA, SI } },
1493 { "twnei",   OPTO(3,TONE), OPTO_MASK,   PPCCOM,         { RA, SI } },
1494 { "tnei",    OPTO(3,TONE), OPTO_MASK,   PWRCOM,         { RA, SI } },
1495 { "twi",     OP(3),     OP_MASK,        PPCCOM,         { TO, RA, SI } },
1496 { "ti",      OP(3),     OP_MASK,        PWRCOM,         { TO, RA, SI } },
1497
1498 { "macchw",     XO(4,172,0,0), XO_MASK, PPC405,         { RT, RA, RB } },
1499 { "macchw.",    XO(4,172,0,1), XO_MASK, PPC405,         { RT, RA, RB } },
1500 { "macchwo",    XO(4,172,1,0), XO_MASK, PPC405,         { RT, RA, RB } },
1501 { "macchwo.",   XO(4,172,1,1), XO_MASK, PPC405,         { RT, RA, RB } },
1502 { "macchws",    XO(4,236,0,0), XO_MASK, PPC405,         { RT, RA, RB } },
1503 { "macchws.",   XO(4,236,0,1), XO_MASK, PPC405,         { RT, RA, RB } },
1504 { "macchwso",   XO(4,236,1,0), XO_MASK, PPC405,         { RT, RA, RB } },
1505 { "macchwso.",  XO(4,236,1,1), XO_MASK, PPC405,         { RT, RA, RB } },
1506 { "macchwsu",   XO(4,204,0,0), XO_MASK, PPC405,         { RT, RA, RB } },
1507 { "macchwsu.",  XO(4,204,0,1), XO_MASK, PPC405,         { RT, RA, RB } },
1508 { "macchwsuo",  XO(4,204,1,0), XO_MASK, PPC405,         { RT, RA, RB } },
1509 { "macchwsuo.", XO(4,204,1,1), XO_MASK, PPC405,         { RT, RA, RB } },
1510 { "macchwu",    XO(4,140,0,0), XO_MASK, PPC405,         { RT, RA, RB } },
1511 { "macchwu.",   XO(4,140,0,1), XO_MASK, PPC405,         { RT, RA, RB } },
1512 { "macchwuo",   XO(4,140,1,0), XO_MASK, PPC405,         { RT, RA, RB } },
1513 { "macchwuo.",  XO(4,140,1,1), XO_MASK, PPC405,         { RT, RA, RB } },
1514 { "machhw",     XO(4,44,0,0),  XO_MASK, PPC405,         { RT, RA, RB } },
1515 { "machhw.",    XO(4,44,0,1),  XO_MASK, PPC405,         { RT, RA, RB } },
1516 { "machhwo",    XO(4,44,1,0),  XO_MASK, PPC405,         { RT, RA, RB } },
1517 { "machhwo.",   XO(4,44,1,1),  XO_MASK, PPC405,         { RT, RA, RB } },
1518 { "machhws",    XO(4,108,0,0), XO_MASK, PPC405,         { RT, RA, RB } },
1519 { "machhws.",   XO(4,108,0,1), XO_MASK, PPC405,         { RT, RA, RB } },
1520 { "machhwso",   XO(4,108,1,0), XO_MASK, PPC405,         { RT, RA, RB } },
1521 { "machhwso.",  XO(4,108,1,1), XO_MASK, PPC405,         { RT, RA, RB } },
1522 { "machhwsu",   XO(4,76,0,0),  XO_MASK, PPC405,         { RT, RA, RB } },
1523 { "machhwsu.",  XO(4,76,0,1),  XO_MASK, PPC405,         { RT, RA, RB } },
1524 { "machhwsuo",  XO(4,76,1,0),  XO_MASK, PPC405,         { RT, RA, RB } },
1525 { "machhwsuo.", XO(4,76,1,1),  XO_MASK, PPC405,         { RT, RA, RB } },
1526 { "machhwu",    XO(4,12,0,0),  XO_MASK, PPC405,         { RT, RA, RB } },
1527 { "machhwu.",   XO(4,12,0,1),  XO_MASK, PPC405,         { RT, RA, RB } },
1528 { "machhwuo",   XO(4,12,1,0),  XO_MASK, PPC405,         { RT, RA, RB } },
1529 { "machhwuo.",  XO(4,12,1,1),  XO_MASK, PPC405,         { RT, RA, RB } },
1530 { "maclhw",     XO(4,428,0,0), XO_MASK, PPC405,         { RT, RA, RB } },
1531 { "maclhw.",    XO(4,428,0,1), XO_MASK, PPC405,         { RT, RA, RB } },
1532 { "maclhwo",    XO(4,428,1,0), XO_MASK, PPC405,         { RT, RA, RB } },
1533 { "maclhwo.",   XO(4,428,1,1), XO_MASK, PPC405,         { RT, RA, RB } },
1534 { "maclhws",    XO(4,492,0,0), XO_MASK, PPC405,         { RT, RA, RB } },
1535 { "maclhws.",   XO(4,492,0,1), XO_MASK, PPC405,         { RT, RA, RB } },
1536 { "maclhwso",   XO(4,492,1,0), XO_MASK, PPC405,         { RT, RA, RB } },
1537 { "maclhwso.",  XO(4,492,1,1), XO_MASK, PPC405,         { RT, RA, RB } },
1538 { "maclhwsu",   XO(4,460,0,0), XO_MASK, PPC405,         { RT, RA, RB } },
1539 { "maclhwsu.",  XO(4,460,0,1), XO_MASK, PPC405,         { RT, RA, RB } },
1540 { "maclhwsuo",  XO(4,460,1,0), XO_MASK, PPC405,         { RT, RA, RB } },
1541 { "maclhwsuo.", XO(4,460,1,1), XO_MASK, PPC405,         { RT, RA, RB } },
1542 { "maclhwu",    XO(4,396,0,0), XO_MASK, PPC405,         { RT, RA, RB } },
1543 { "maclhwu.",   XO(4,396,0,1), XO_MASK, PPC405,         { RT, RA, RB } },
1544 { "maclhwuo",   XO(4,396,1,0), XO_MASK, PPC405,         { RT, RA, RB } },
1545 { "maclhwuo.",  XO(4,396,1,1), XO_MASK, PPC405,         { RT, RA, RB } },
1546 { "mulchw",     XRC(4,168,0),  X_MASK,  PPC405,         { RT, RA, RB } },
1547 { "mulchw.",    XRC(4,168,1),  X_MASK,  PPC405,         { RT, RA, RB } },
1548 { "mulchwu",    XRC(4,136,0),  X_MASK,  PPC405,         { RT, RA, RB } },
1549 { "mulchwu.",   XRC(4,136,1),  X_MASK,  PPC405,         { RT, RA, RB } },
1550 { "mulhhw",     XRC(4,40,0),   X_MASK,  PPC405,         { RT, RA, RB } },
1551 { "mulhhw.",    XRC(4,40,1),   X_MASK,  PPC405,         { RT, RA, RB } },
1552 { "mulhhwu",    XRC(4,8,0),    X_MASK,  PPC405,         { RT, RA, RB } },
1553 { "mulhhwu.",   XRC(4,8,1),    X_MASK,  PPC405,         { RT, RA, RB } },
1554 { "mullhw",     XRC(4,424,0),  X_MASK,  PPC405,         { RT, RA, RB } },
1555 { "mullhw.",    XRC(4,424,1),  X_MASK,  PPC405,         { RT, RA, RB } },
1556 { "mullhwu",    XRC(4,392,0),  X_MASK,  PPC405,         { RT, RA, RB } },
1557 { "mullhwu.",   XRC(4,392,1),  X_MASK,  PPC405,         { RT, RA, RB } },
1558 { "nmacchw",    XO(4,174,0,0), XO_MASK, PPC405,         { RT, RA, RB } },
1559 { "nmacchw.",   XO(4,174,0,1), XO_MASK, PPC405,         { RT, RA, RB } },
1560 { "nmacchwo",   XO(4,174,1,0), XO_MASK, PPC405,         { RT, RA, RB } },
1561 { "nmacchwo.",  XO(4,174,1,1), XO_MASK, PPC405,         { RT, RA, RB } },
1562 { "nmacchws",   XO(4,238,0,0), XO_MASK, PPC405,         { RT, RA, RB } },
1563 { "nmacchws.",  XO(4,238,0,1), XO_MASK, PPC405,         { RT, RA, RB } },
1564 { "nmacchwso",  XO(4,238,1,0), XO_MASK, PPC405,         { RT, RA, RB } },
1565 { "nmacchwso.", XO(4,238,1,1), XO_MASK, PPC405,         { RT, RA, RB } },
1566 { "nmachhw",    XO(4,46,0,0),  XO_MASK, PPC405,         { RT, RA, RB } },
1567 { "nmachhw.",   XO(4,46,0,1),  XO_MASK, PPC405,         { RT, RA, RB } },
1568 { "nmachhwo",   XO(4,46,1,0),  XO_MASK, PPC405,         { RT, RA, RB } },
1569 { "nmachhwo.",  XO(4,46,1,1),  XO_MASK, PPC405,         { RT, RA, RB } },
1570 { "nmachhws",   XO(4,110,0,0), XO_MASK, PPC405,         { RT, RA, RB } },
1571 { "nmachhws.",  XO(4,110,0,1), XO_MASK, PPC405,         { RT, RA, RB } },
1572 { "nmachhwso",  XO(4,110,1,0), XO_MASK, PPC405,         { RT, RA, RB } },
1573 { "nmachhwso.", XO(4,110,1,1), XO_MASK, PPC405,         { RT, RA, RB } },
1574 { "nmaclhw",    XO(4,430,0,0), XO_MASK, PPC405,         { RT, RA, RB } },
1575 { "nmaclhw.",   XO(4,430,0,1), XO_MASK, PPC405,         { RT, RA, RB } },
1576 { "nmaclhwo",   XO(4,430,1,0), XO_MASK, PPC405,         { RT, RA, RB } },
1577 { "nmaclhwo.",  XO(4,430,1,1), XO_MASK, PPC405,         { RT, RA, RB } },
1578 { "nmaclhws",   XO(4,494,0,0), XO_MASK, PPC405,         { RT, RA, RB } },
1579 { "nmaclhws.",  XO(4,494,0,1), XO_MASK, PPC405,         { RT, RA, RB } },
1580 { "nmaclhwso",  XO(4,494,1,0), XO_MASK, PPC405,         { RT, RA, RB } },
1581 { "nmaclhwso.", XO(4,494,1,1), XO_MASK, PPC405,         { RT, RA, RB } },
1582 { "mfvscr",  VX(4, 1540), VX_MASK,      PPCVEC,         { VD } },
1583 { "mtvscr",  VX(4, 1604), VX_MASK,      PPCVEC,         { VD } },
1584 { "vaddcuw", VX(4,  384), VX_MASK,      PPCVEC,         { VD, VA, VB } },
1585 { "vaddfp",  VX(4,   10), VX_MASK,      PPCVEC,         { VD, VA, VB } },
1586 { "vaddsbs", VX(4,  768), VX_MASK,      PPCVEC,         { VD, VA, VB } },
1587 { "vaddshs", VX(4,  832), VX_MASK,      PPCVEC,         { VD, VA, VB } },
1588 { "vaddsws", VX(4,  896), VX_MASK,      PPCVEC,         { VD, VA, VB } },
1589 { "vaddubm", VX(4,    0), VX_MASK,      PPCVEC,         { VD, VA, VB } },
1590 { "vaddubs", VX(4,  512), VX_MASK,      PPCVEC,         { VD, VA, VB } },
1591 { "vadduhm", VX(4,   64), VX_MASK,      PPCVEC,         { VD, VA, VB } },
1592 { "vadduhs", VX(4,  576), VX_MASK,      PPCVEC,         { VD, VA, VB } },
1593 { "vadduwm", VX(4,  128), VX_MASK,      PPCVEC,         { VD, VA, VB } },
1594 { "vadduws", VX(4,  640), VX_MASK,      PPCVEC,         { VD, VA, VB } },
1595 { "vand",    VX(4, 1028), VX_MASK,      PPCVEC,         { VD, VA, VB } },
1596 { "vandc",   VX(4, 1092), VX_MASK,      PPCVEC,         { VD, VA, VB } },
1597 { "vavgsb",  VX(4, 1282), VX_MASK,      PPCVEC,         { VD, VA, VB } },
1598 { "vavgsh",  VX(4, 1346), VX_MASK,      PPCVEC,         { VD, VA, VB } },
1599 { "vavgsw",  VX(4, 1410), VX_MASK,      PPCVEC,         { VD, VA, VB } },
1600 { "vavgub",  VX(4, 1026), VX_MASK,      PPCVEC,         { VD, VA, VB } },
1601 { "vavguh",  VX(4, 1090), VX_MASK,      PPCVEC,         { VD, VA, VB } },
1602 { "vavguw",  VX(4, 1154), VX_MASK,      PPCVEC,         { VD, VA, VB } },
1603 { "vcfsx",   VX(4,  842), VX_MASK,      PPCVEC,         { VD, VB, UIMM } },
1604 { "vcfux",   VX(4,  778), VX_MASK,      PPCVEC,         { VD, VB, UIMM } },
1605 { "vcmpbfp",   VXR(4, 966, 0), VXR_MASK, PPCVEC,        { VD, VA, VB } },
1606 { "vcmpbfp.",  VXR(4, 966, 1), VXR_MASK, PPCVEC,        { VD, VA, VB } },
1607 { "vcmpeqfp",  VXR(4, 198, 0), VXR_MASK, PPCVEC,        { VD, VA, VB } },
1608 { "vcmpeqfp.", VXR(4, 198, 1), VXR_MASK, PPCVEC,        { VD, VA, VB } },
1609 { "vcmpequb",  VXR(4,   6, 0), VXR_MASK, PPCVEC,        { VD, VA, VB } },
1610 { "vcmpequb.", VXR(4,   6, 1), VXR_MASK, PPCVEC,        { VD, VA, VB } },
1611 { "vcmpequh",  VXR(4,  70, 0), VXR_MASK, PPCVEC,        { VD, VA, VB } },
1612 { "vcmpequh.", VXR(4,  70, 1), VXR_MASK, PPCVEC,        { VD, VA, VB } },
1613 { "vcmpequw",  VXR(4, 134, 0), VXR_MASK, PPCVEC,        { VD, VA, VB } },
1614 { "vcmpequw.", VXR(4, 134, 1), VXR_MASK, PPCVEC,        { VD, VA, VB } },
1615 { "vcmpgefp",  VXR(4, 454, 0), VXR_MASK, PPCVEC,        { VD, VA, VB } },
1616 { "vcmpgefp.", VXR(4, 454, 1), VXR_MASK, PPCVEC,        { VD, VA, VB } },
1617 { "vcmpgtfp",  VXR(4, 710, 0), VXR_MASK, PPCVEC,        { VD, VA, VB } },
1618 { "vcmpgtfp.", VXR(4, 710, 1), VXR_MASK, PPCVEC,        { VD, VA, VB } },
1619 { "vcmpgtsb",  VXR(4, 774, 0), VXR_MASK, PPCVEC,        { VD, VA, VB } },
1620 { "vcmpgtsb.", VXR(4, 774, 1), VXR_MASK, PPCVEC,        { VD, VA, VB } },
1621 { "vcmpgtsh",  VXR(4, 838, 0), VXR_MASK, PPCVEC,        { VD, VA, VB } },
1622 { "vcmpgtsh.", VXR(4, 838, 1), VXR_MASK, PPCVEC,        { VD, VA, VB } },
1623 { "vcmpgtsw",  VXR(4, 902, 0), VXR_MASK, PPCVEC,        { VD, VA, VB } },
1624 { "vcmpgtsw.", VXR(4, 902, 1), VXR_MASK, PPCVEC,        { VD, VA, VB } },
1625 { "vcmpgtub",  VXR(4, 518, 0), VXR_MASK, PPCVEC,        { VD, VA, VB } },
1626 { "vcmpgtub.", VXR(4, 518, 1), VXR_MASK, PPCVEC,        { VD, VA, VB } },
1627 { "vcmpgtuh",  VXR(4, 582, 0), VXR_MASK, PPCVEC,        { VD, VA, VB } },
1628 { "vcmpgtuh.", VXR(4, 582, 1), VXR_MASK, PPCVEC,        { VD, VA, VB } },
1629 { "vcmpgtuw",  VXR(4, 646, 0), VXR_MASK, PPCVEC,        { VD, VA, VB } },
1630 { "vcmpgtuw.", VXR(4, 646, 1), VXR_MASK, PPCVEC,        { VD, VA, VB } },
1631 { "vctsxs",    VX(4,  970), VX_MASK,    PPCVEC,         { VD, VB, UIMM } },
1632 { "vctuxs",    VX(4,  906), VX_MASK,    PPCVEC,         { VD, VB, UIMM } },
1633 { "vexptefp",  VX(4,  394), VX_MASK,    PPCVEC,         { VD, VB } },
1634 { "vlogefp",   VX(4,  458), VX_MASK,    PPCVEC,         { VD, VB } },
1635 { "vmaddfp",   VXA(4,  46), VXA_MASK,   PPCVEC,         { VD, VA, VB, VC } },
1636 { "vmaxfp",    VX(4, 1034), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1637 { "vmaxsb",    VX(4,  258), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1638 { "vmaxsh",    VX(4,  322), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1639 { "vmaxsw",    VX(4,  386), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1640 { "vmaxub",    VX(4,    2), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1641 { "vmaxuh",    VX(4,   66), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1642 { "vmaxuw",    VX(4,  130), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1643 { "vmhaddshs", VXA(4,  32), VXA_MASK,   PPCVEC,         { VD, VA, VB, VC } },
1644 { "vmhraddshs", VXA(4, 33), VXA_MASK,   PPCVEC,         { VD, VA, VB, VC } },
1645 { "vminfp",    VX(4, 1098), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1646 { "vminsb",    VX(4,  770), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1647 { "vminsh",    VX(4,  834), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1648 { "vminsw",    VX(4,  898), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1649 { "vminub",    VX(4,  514), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1650 { "vminuh",    VX(4,  578), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1651 { "vminuw",    VX(4,  642), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1652 { "vmladduhm", VXA(4,  34), VXA_MASK,   PPCVEC,         { VD, VA, VB, VC } },
1653 { "vmrghb",    VX(4,   12), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1654 { "vmrghh",    VX(4,   76), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1655 { "vmrghw",    VX(4,  140), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1656 { "vmrglb",    VX(4,  268), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1657 { "vmrglh",    VX(4,  332), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1658 { "vmrglw",    VX(4,  396), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1659 { "vmsummbm",  VXA(4,  37), VXA_MASK,   PPCVEC,         { VD, VA, VB, VC } },
1660 { "vmsumshm",  VXA(4,  40), VXA_MASK,   PPCVEC,         { VD, VA, VB, VC } },
1661 { "vmsumshs",  VXA(4,  41), VXA_MASK,   PPCVEC,         { VD, VA, VB, VC } },
1662 { "vmsumubm",  VXA(4,  36), VXA_MASK,   PPCVEC,         { VD, VA, VB, VC } },
1663 { "vmsumuhm",  VXA(4,  38), VXA_MASK,   PPCVEC,         { VD, VA, VB, VC } },
1664 { "vmsumuhs",  VXA(4,  39), VXA_MASK,   PPCVEC,         { VD, VA, VB, VC } },
1665 { "vmulesb",   VX(4,  776), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1666 { "vmulesh",   VX(4,  840), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1667 { "vmuleub",   VX(4,  520), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1668 { "vmuleuh",   VX(4,  584), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1669 { "vmulosb",   VX(4,  264), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1670 { "vmulosh",   VX(4,  328), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1671 { "vmuloub",   VX(4,    8), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1672 { "vmulouh",   VX(4,   72), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1673 { "vnmsubfp",  VXA(4,  47), VXA_MASK,   PPCVEC,         { VD, VA, VC, VB } },
1674 { "vnor",      VX(4, 1284), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1675 { "vor",       VX(4, 1156), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1676 { "vperm",     VXA(4,  43), VXA_MASK,   PPCVEC,         { VD, VA, VB, VC } },
1677 { "vpkpx",     VX(4,  782), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1678 { "vpkshss",   VX(4,  398), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1679 { "vpkshus",   VX(4,  270), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1680 { "vpkswss",   VX(4,  462), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1681 { "vpkswus",   VX(4,  334), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1682 { "vpkuhum",   VX(4,   14), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1683 { "vpkuhus",   VX(4,  142), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1684 { "vpkuwum",   VX(4,   78), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1685 { "vpkuwus",   VX(4,  206), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1686 { "vrefp",     VX(4,  266), VX_MASK,    PPCVEC,         { VD, VB } },
1687 { "vrfim",     VX(4,  714), VX_MASK,    PPCVEC,         { VD, VB } },
1688 { "vrfin",     VX(4,  522), VX_MASK,    PPCVEC,         { VD, VB } },
1689 { "vrfip",     VX(4,  650), VX_MASK,    PPCVEC,         { VD, VB } },
1690 { "vrfiz",     VX(4,  586), VX_MASK,    PPCVEC,         { VD, VB } },
1691 { "vrlb",      VX(4,    4), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1692 { "vrlh",      VX(4,   68), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1693 { "vrlw",      VX(4,  132), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1694 { "vrsqrtefp", VX(4,  330), VX_MASK,    PPCVEC,         { VD, VB } },
1695 { "vsel",      VXA(4,  42), VXA_MASK,   PPCVEC,         { VD, VA, VB, VC } },
1696 { "vsl",       VX(4,  452), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1697 { "vslb",      VX(4,  260), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1698 { "vsldoi",    VXA(4,  44), VXA_MASK,   PPCVEC,         { VD, VA, VB, SHB } },
1699 { "vslh",      VX(4,  324), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1700 { "vslo",      VX(4, 1036), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1701 { "vslw",      VX(4,  388), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1702 { "vspltb",    VX(4,  524), VX_MASK,    PPCVEC,         { VD, VB, UIMM } },
1703 { "vsplth",    VX(4,  588), VX_MASK,    PPCVEC,         { VD, VB, UIMM } },
1704 { "vspltisb",  VX(4,  780), VX_MASK,    PPCVEC,         { VD, SIMM } },
1705 { "vspltish",  VX(4,  844), VX_MASK,    PPCVEC,         { VD, SIMM } },
1706 { "vspltisw",  VX(4,  908), VX_MASK,    PPCVEC,         { VD, SIMM } },
1707 { "vspltw",    VX(4,  652), VX_MASK,    PPCVEC,         { VD, VB, UIMM } },
1708 { "vsr",       VX(4,  708), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1709 { "vsrab",     VX(4,  772), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1710 { "vsrah",     VX(4,  836), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1711 { "vsraw",     VX(4,  900), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1712 { "vsrb",      VX(4,  516), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1713 { "vsrh",      VX(4,  580), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1714 { "vsro",      VX(4, 1100), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1715 { "vsrw",      VX(4,  644), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1716 { "vsubcuw",   VX(4, 1408), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1717 { "vsubfp",    VX(4,   74), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1718 { "vsubsbs",   VX(4, 1792), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1719 { "vsubshs",   VX(4, 1856), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1720 { "vsubsws",   VX(4, 1920), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1721 { "vsububm",   VX(4, 1024), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1722 { "vsububs",   VX(4, 1536), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1723 { "vsubuhm",   VX(4, 1088), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1724 { "vsubuhs",   VX(4, 1600), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1725 { "vsubuwm",   VX(4, 1152), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1726 { "vsubuws",   VX(4, 1664), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1727 { "vsumsws",   VX(4, 1928), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1728 { "vsum2sws",  VX(4, 1672), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1729 { "vsum4sbs",  VX(4, 1800), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1730 { "vsum4shs",  VX(4, 1608), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1731 { "vsum4ubs",  VX(4, 1544), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1732 { "vupkhpx",   VX(4,  846), VX_MASK,    PPCVEC,         { VD, VB } },
1733 { "vupkhsb",   VX(4,  526), VX_MASK,    PPCVEC,         { VD, VB } },
1734 { "vupkhsh",   VX(4,  590), VX_MASK,    PPCVEC,         { VD, VB } },
1735 { "vupklpx",   VX(4,  974), VX_MASK,    PPCVEC,         { VD, VB } },
1736 { "vupklsb",   VX(4,  654), VX_MASK,    PPCVEC,         { VD, VB } },
1737 { "vupklsh",   VX(4,  718), VX_MASK,    PPCVEC,         { VD, VB } },
1738 { "vxor",      VX(4, 1220), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1739
1740 { "mulli",   OP(7),     OP_MASK,        PPCCOM,         { RT, RA, SI } },
1741 { "muli",    OP(7),     OP_MASK,        PWRCOM,         { RT, RA, SI } },
1742
1743 { "subfic",  OP(8),     OP_MASK,        PPCCOM,         { RT, RA, SI } },
1744 { "sfi",     OP(8),     OP_MASK,        PWRCOM,         { RT, RA, SI } },
1745
1746 { "dozi",    OP(9),     OP_MASK,        M601,           { RT, RA, SI } },
1747
1748 { "bce",     B(9,0,0),  B_MASK,         BOOKE64,        { BO, BI, BD } },
1749 { "bcel",    B(9,0,1),  B_MASK,         BOOKE64,        { BO, BI, BD } },
1750 { "bcea",    B(9,1,0),  B_MASK,         BOOKE64,        { BO, BI, BDA } },
1751 { "bcela",   B(9,1,1),  B_MASK,         BOOKE64,        { BO, BI, BDA } },
1752
1753 { "cmplwi",  OPL(10,0), OPL_MASK,       PPCCOM,         { OBF, RA, UI } },
1754 { "cmpldi",  OPL(10,1), OPL_MASK,       PPC64,          { OBF, RA, UI } },
1755 { "cmpli",   OP(10),    OP_MASK,        PPCONLY,        { BF, L, RA, UI } },
1756 { "cmpli",   OP(10),    OP_MASK,        PWRCOM,         { BF, RA, UI } },
1757
1758 { "cmpwi",   OPL(11,0), OPL_MASK,       PPCCOM,         { OBF, RA, SI } },
1759 { "cmpdi",   OPL(11,1), OPL_MASK,       PPC64,          { OBF, RA, SI } },
1760 { "cmpi",    OP(11),    OP_MASK,        PPCONLY,        { BF, L, RA, SI } },
1761 { "cmpi",    OP(11),    OP_MASK,        PWRCOM,         { BF, RA, SI } },
1762
1763 { "addic",   OP(12),    OP_MASK,        PPCCOM,         { RT, RA, SI } },
1764 { "ai",      OP(12),    OP_MASK,        PWRCOM,         { RT, RA, SI } },
1765 { "subic",   OP(12),    OP_MASK,        PPCCOM,         { RT, RA, NSI } },
1766
1767 { "addic.",  OP(13),    OP_MASK,        PPCCOM,         { RT, RA, SI } },
1768 { "ai.",     OP(13),    OP_MASK,        PWRCOM,         { RT, RA, SI } },
1769 { "subic.",  OP(13),    OP_MASK,        PPCCOM,         { RT, RA, NSI } },
1770
1771 { "li",      OP(14),    DRA_MASK,       PPCCOM,         { RT, SI } },
1772 { "lil",     OP(14),    DRA_MASK,       PWRCOM,         { RT, SI } },
1773 { "addi",    OP(14),    OP_MASK,        PPCCOM,         { RT, RA, SI } },
1774 { "cal",     OP(14),    OP_MASK,        PWRCOM,         { RT, D, RA } },
1775 { "subi",    OP(14),    OP_MASK,        PPCCOM,         { RT, RA, NSI } },
1776 { "la",      OP(14),    OP_MASK,        PPCCOM,         { RT, D, RA } },
1777
1778 { "lis",     OP(15),    DRA_MASK,       PPCCOM,         { RT, SISIGNOPT } },
1779 { "liu",     OP(15),    DRA_MASK,       PWRCOM,         { RT, SISIGNOPT } },
1780 { "addis",   OP(15),    OP_MASK,        PPCCOM,         { RT,RA,SISIGNOPT } },
1781 { "cau",     OP(15),    OP_MASK,        PWRCOM,         { RT,RA,SISIGNOPT } },
1782 { "subis",   OP(15),    OP_MASK,        PPCCOM,         { RT, RA, NSI } },
1783
1784 { "bdnz-",   BBO(16,BODNZ,0,0), BBOYBI_MASK, PPCCOM,    { BDM } },
1785 { "bdnz+",   BBO(16,BODNZ,0,0), BBOYBI_MASK, PPCCOM,    { BDP } },
1786 { "bdnz",    BBO(16,BODNZ,0,0), BBOYBI_MASK, PPCCOM,    { BD } },
1787 { "bdn",     BBO(16,BODNZ,0,0), BBOYBI_MASK, PWRCOM,    { BD } },
1788 { "bdnzl-",  BBO(16,BODNZ,0,1), BBOYBI_MASK, PPCCOM,    { BDM } },
1789 { "bdnzl+",  BBO(16,BODNZ,0,1), BBOYBI_MASK, PPCCOM,    { BDP } },
1790 { "bdnzl",   BBO(16,BODNZ,0,1), BBOYBI_MASK, PPCCOM,    { BD } },
1791 { "bdnl",    BBO(16,BODNZ,0,1), BBOYBI_MASK, PWRCOM,    { BD } },
1792 { "bdnza-",  BBO(16,BODNZ,1,0), BBOYBI_MASK, PPCCOM,    { BDMA } },
1793 { "bdnza+",  BBO(16,BODNZ,1,0), BBOYBI_MASK, PPCCOM,    { BDPA } },
1794 { "bdnza",   BBO(16,BODNZ,1,0), BBOYBI_MASK, PPCCOM,    { BDA } },
1795 { "bdna",    BBO(16,BODNZ,1,0), BBOYBI_MASK, PWRCOM,    { BDA } },
1796 { "bdnzla-", BBO(16,BODNZ,1,1), BBOYBI_MASK, PPCCOM,    { BDMA } },
1797 { "bdnzla+", BBO(16,BODNZ,1,1), BBOYBI_MASK, PPCCOM,    { BDPA } },
1798 { "bdnzla",  BBO(16,BODNZ,1,1), BBOYBI_MASK, PPCCOM,    { BDA } },
1799 { "bdnla",   BBO(16,BODNZ,1,1), BBOYBI_MASK, PWRCOM,    { BDA } },
1800 { "bdz-",    BBO(16,BODZ,0,0),  BBOYBI_MASK, PPCCOM,    { BDM } },
1801 { "bdz+",    BBO(16,BODZ,0,0),  BBOYBI_MASK, PPCCOM,    { BDP } },
1802 { "bdz",     BBO(16,BODZ,0,0),  BBOYBI_MASK, COM,       { BD } },
1803 { "bdzl-",   BBO(16,BODZ,0,1),  BBOYBI_MASK, PPCCOM,    { BDM } },
1804 { "bdzl+",   BBO(16,BODZ,0,1),  BBOYBI_MASK, PPCCOM,    { BDP } },
1805 { "bdzl",    BBO(16,BODZ,0,1),  BBOYBI_MASK, COM,       { BD } },
1806 { "bdza-",   BBO(16,BODZ,1,0),  BBOYBI_MASK, PPCCOM,    { BDMA } },
1807 { "bdza+",   BBO(16,BODZ,1,0),  BBOYBI_MASK, PPCCOM,    { BDPA } },
1808 { "bdza",    BBO(16,BODZ,1,0),  BBOYBI_MASK, COM,       { BDA } },
1809 { "bdzla-",  BBO(16,BODZ,1,1),  BBOYBI_MASK, PPCCOM,    { BDMA } },
1810 { "bdzla+",  BBO(16,BODZ,1,1),  BBOYBI_MASK, PPCCOM,    { BDPA } },
1811 { "bdzla",   BBO(16,BODZ,1,1),  BBOYBI_MASK, COM,       { BDA } },
1812 { "blt-",    BBOCB(16,BOT,CBLT,0,0), BBOYCB_MASK, PPCCOM,       { CR, BDM } },
1813 { "blt+",    BBOCB(16,BOT,CBLT,0,0), BBOYCB_MASK, PPCCOM,       { CR, BDP } },
1814 { "blt",     BBOCB(16,BOT,CBLT,0,0), BBOYCB_MASK, COM,          { CR, BD } },
1815 { "bltl-",   BBOCB(16,BOT,CBLT,0,1), BBOYCB_MASK, PPCCOM,       { CR, BDM } },
1816 { "bltl+",   BBOCB(16,BOT,CBLT,0,1), BBOYCB_MASK, PPCCOM,       { CR, BDP } },
1817 { "bltl",    BBOCB(16,BOT,CBLT,0,1), BBOYCB_MASK, COM,          { CR, BD } },
1818 { "blta-",   BBOCB(16,BOT,CBLT,1,0), BBOYCB_MASK, PPCCOM,       { CR, BDMA } },
1819 { "blta+",   BBOCB(16,BOT,CBLT,1,0), BBOYCB_MASK, PPCCOM,       { CR, BDPA } },
1820 { "blta",    BBOCB(16,BOT,CBLT,1,0), BBOYCB_MASK, COM,          { CR, BDA } },
1821 { "bltla-",  BBOCB(16,BOT,CBLT,1,1), BBOYCB_MASK, PPCCOM,       { CR, BDMA } },
1822 { "bltla+",  BBOCB(16,BOT,CBLT,1,1), BBOYCB_MASK, PPCCOM,       { CR, BDPA } },
1823 { "bltla",   BBOCB(16,BOT,CBLT,1,1), BBOYCB_MASK, COM,          { CR, BDA } },
1824 { "bgt-",    BBOCB(16,BOT,CBGT,0,0), BBOYCB_MASK, PPCCOM,       { CR, BDM } },
1825 { "bgt+",    BBOCB(16,BOT,CBGT,0,0), BBOYCB_MASK, PPCCOM,       { CR, BDP } },
1826 { "bgt",     BBOCB(16,BOT,CBGT,0,0), BBOYCB_MASK, COM,          { CR, BD } },
1827 { "bgtl-",   BBOCB(16,BOT,CBGT,0,1), BBOYCB_MASK, PPCCOM,       { CR, BDM } },
1828 { "bgtl+",   BBOCB(16,BOT,CBGT,0,1), BBOYCB_MASK, PPCCOM,       { CR, BDP } },
1829 { "bgtl",    BBOCB(16,BOT,CBGT,0,1), BBOYCB_MASK, COM,          { CR, BD } },
1830 { "bgta-",   BBOCB(16,BOT,CBGT,1,0), BBOYCB_MASK, PPCCOM,       { CR, BDMA } },
1831 { "bgta+",   BBOCB(16,BOT,CBGT,1,0), BBOYCB_MASK, PPCCOM,       { CR, BDPA } },
1832 { "bgta",    BBOCB(16,BOT,CBGT,1,0), BBOYCB_MASK, COM,          { CR, BDA } },
1833 { "bgtla-",  BBOCB(16,BOT,CBGT,1,1), BBOYCB_MASK, PPCCOM,       { CR, BDMA } },
1834 { "bgtla+",  BBOCB(16,BOT,CBGT,1,1), BBOYCB_MASK, PPCCOM,       { CR, BDPA } },
1835 { "bgtla",   BBOCB(16,BOT,CBGT,1,1), BBOYCB_MASK, COM,          { CR, BDA } },
1836 { "beq-",    BBOCB(16,BOT,CBEQ,0,0), BBOYCB_MASK, PPCCOM,       { CR, BDM } },
1837 { "beq+",    BBOCB(16,BOT,CBEQ,0,0), BBOYCB_MASK, PPCCOM,       { CR, BDP } },
1838 { "beq",     BBOCB(16,BOT,CBEQ,0,0), BBOYCB_MASK, COM,          { CR, BD } },
1839 { "beql-",   BBOCB(16,BOT,CBEQ,0,1), BBOYCB_MASK, PPCCOM,       { CR, BDM } },
1840 { "beql+",   BBOCB(16,BOT,CBEQ,0,1), BBOYCB_MASK, PPCCOM,       { CR, BDP } },
1841 { "beql",    BBOCB(16,BOT,CBEQ,0,1), BBOYCB_MASK, COM,          { CR, BD } },
1842 { "beqa-",   BBOCB(16,BOT,CBEQ,1,0), BBOYCB_MASK, PPCCOM,       { CR, BDMA } },
1843 { "beqa+",   BBOCB(16,BOT,CBEQ,1,0), BBOYCB_MASK, PPCCOM,       { CR, BDPA } },
1844 { "beqa",    BBOCB(16,BOT,CBEQ,1,0), BBOYCB_MASK, COM,          { CR, BDA } },
1845 { "beqla-",  BBOCB(16,BOT,CBEQ,1,1), BBOYCB_MASK, PPCCOM,       { CR, BDMA } },
1846 { "beqla+",  BBOCB(16,BOT,CBEQ,1,1), BBOYCB_MASK, PPCCOM,       { CR, BDPA } },
1847 { "beqla",   BBOCB(16,BOT,CBEQ,1,1), BBOYCB_MASK, COM,          { CR, BDA } },
1848 { "bso-",    BBOCB(16,BOT,CBSO,0,0), BBOYCB_MASK, PPCCOM,       { CR, BDM } },
1849 { "bso+",    BBOCB(16,BOT,CBSO,0,0), BBOYCB_MASK, PPCCOM,       { CR, BDP } },
1850 { "bso",     BBOCB(16,BOT,CBSO,0,0), BBOYCB_MASK, COM,          { CR, BD } },
1851 { "bsol-",   BBOCB(16,BOT,CBSO,0,1), BBOYCB_MASK, PPCCOM,       { CR, BDM } },
1852 { "bsol+",   BBOCB(16,BOT,CBSO,0,1), BBOYCB_MASK, PPCCOM,       { CR, BDP } },
1853 { "bsol",    BBOCB(16,BOT,CBSO,0,1), BBOYCB_MASK, COM,          { CR, BD } },
1854 { "bsoa-",   BBOCB(16,BOT,CBSO,1,0), BBOYCB_MASK, PPCCOM,       { CR, BDMA } },
1855 { "bsoa+",   BBOCB(16,BOT,CBSO,1,0), BBOYCB_MASK, PPCCOM,       { CR, BDPA } },
1856 { "bsoa",    BBOCB(16,BOT,CBSO,1,0), BBOYCB_MASK, COM,          { CR, BDA } },
1857 { "bsola-",  BBOCB(16,BOT,CBSO,1,1), BBOYCB_MASK, PPCCOM,       { CR, BDMA } },
1858 { "bsola+",  BBOCB(16,BOT,CBSO,1,1), BBOYCB_MASK, PPCCOM,       { CR, BDPA } },
1859 { "bsola",   BBOCB(16,BOT,CBSO,1,1), BBOYCB_MASK, COM,          { CR, BDA } },
1860 { "bun-",    BBOCB(16,BOT,CBSO,0,0), BBOYCB_MASK, PPCCOM,       { CR, BDM } },
1861 { "bun+",    BBOCB(16,BOT,CBSO,0,0), BBOYCB_MASK, PPCCOM,       { CR, BDP } },
1862 { "bun",     BBOCB(16,BOT,CBSO,0,0), BBOYCB_MASK, PPCCOM,       { CR, BD } },
1863 { "bunl-",   BBOCB(16,BOT,CBSO,0,1), BBOYCB_MASK, PPCCOM,       { CR, BDM } },
1864 { "bunl+",   BBOCB(16,BOT,CBSO,0,1), BBOYCB_MASK, PPCCOM,       { CR, BDP } },
1865 { "bunl",    BBOCB(16,BOT,CBSO,0,1), BBOYCB_MASK, PPCCOM,       { CR, BD } },
1866 { "buna-",   BBOCB(16,BOT,CBSO,1,0), BBOYCB_MASK, PPCCOM,       { CR, BDMA } },
1867 { "buna+",   BBOCB(16,BOT,CBSO,1,0), BBOYCB_MASK, PPCCOM,       { CR, BDPA } },
1868 { "buna",    BBOCB(16,BOT,CBSO,1,0), BBOYCB_MASK, PPCCOM,       { CR, BDA } },
1869 { "bunla-",  BBOCB(16,BOT,CBSO,1,1), BBOYCB_MASK, PPCCOM,       { CR, BDMA } },
1870 { "bunla+",  BBOCB(16,BOT,CBSO,1,1), BBOYCB_MASK, PPCCOM,       { CR, BDPA } },
1871 { "bunla",   BBOCB(16,BOT,CBSO,1,1), BBOYCB_MASK, PPCCOM,       { CR, BDA } },
1872 { "bge-",    BBOCB(16,BOF,CBLT,0,0), BBOYCB_MASK, PPCCOM,       { CR, BDM } },
1873 { "bge+",    BBOCB(16,BOF,CBLT,0,0), BBOYCB_MASK, PPCCOM,       { CR, BDP } },
1874 { "bge",     BBOCB(16,BOF,CBLT,0,0), BBOYCB_MASK, COM,          { CR, BD } },
1875 { "bgel-",   BBOCB(16,BOF,CBLT,0,1), BBOYCB_MASK, PPCCOM,       { CR, BDM } },
1876 { "bgel+",   BBOCB(16,BOF,CBLT,0,1), BBOYCB_MASK, PPCCOM,       { CR, BDP } },
1877 { "bgel",    BBOCB(16,BOF,CBLT,0,1), BBOYCB_MASK, COM,          { CR, BD } },
1878 { "bgea-",   BBOCB(16,BOF,CBLT,1,0), BBOYCB_MASK, PPCCOM,       { CR, BDMA } },
1879 { "bgea+",   BBOCB(16,BOF,CBLT,1,0), BBOYCB_MASK, PPCCOM,       { CR, BDPA } },
1880 { "bgea",    BBOCB(16,BOF,CBLT,1,0), BBOYCB_MASK, COM,          { CR, BDA } },
1881 { "bgela-",  BBOCB(16,BOF,CBLT,1,1), BBOYCB_MASK, PPCCOM,       { CR, BDMA } },
1882 { "bgela+",  BBOCB(16,BOF,CBLT,1,1), BBOYCB_MASK, PPCCOM,       { CR, BDPA } },
1883 { "bgela",   BBOCB(16,BOF,CBLT,1,1), BBOYCB_MASK, COM,          { CR, BDA } },
1884 { "bnl-",    BBOCB(16,BOF,CBLT,0,0), BBOYCB_MASK, PPCCOM,       { CR, BDM } },
1885 { "bnl+",    BBOCB(16,BOF,CBLT,0,0), BBOYCB_MASK, PPCCOM,       { CR, BDP } },
1886 { "bnl",     BBOCB(16,BOF,CBLT,0,0), BBOYCB_MASK, COM,          { CR, BD } },
1887 { "bnll-",   BBOCB(16,BOF,CBLT,0,1), BBOYCB_MASK, PPCCOM,       { CR, BDM } },
1888 { "bnll+",   BBOCB(16,BOF,CBLT,0,1), BBOYCB_MASK, PPCCOM,       { CR, BDP } },
1889 { "bnll",    BBOCB(16,BOF,CBLT,0,1), BBOYCB_MASK, COM,          { CR, BD } },
1890 { "bnla-",   BBOCB(16,BOF,CBLT,1,0), BBOYCB_MASK, PPCCOM,       { CR, BDMA } },
1891 { "bnla+",   BBOCB(16,BOF,CBLT,1,0), BBOYCB_MASK, PPCCOM,       { CR, BDPA } },
1892 { "bnla",    BBOCB(16,BOF,CBLT,1,0), BBOYCB_MASK, COM,          { CR, BDA } },
1893 { "bnlla-",  BBOCB(16,BOF,CBLT,1,1), BBOYCB_MASK, PPCCOM,       { CR, BDMA } },
1894 { "bnlla+",  BBOCB(16,BOF,CBLT,1,1), BBOYCB_MASK, PPCCOM,       { CR, BDPA } },
1895 { "bnlla",   BBOCB(16,BOF,CBLT,1,1), BBOYCB_MASK, COM,          { CR, BDA } },
1896 { "ble-",    BBOCB(16,BOF,CBGT,0,0), BBOYCB_MASK, PPCCOM,       { CR, BDM } },
1897 { "ble+",    BBOCB(16,BOF,CBGT,0,0), BBOYCB_MASK, PPCCOM,       { CR, BDP } },
1898 { "ble",     BBOCB(16,BOF,CBGT,0,0), BBOYCB_MASK, COM,          { CR, BD } },
1899 { "blel-",   BBOCB(16,BOF,CBGT,0,1), BBOYCB_MASK, PPCCOM,       { CR, BDM } },
1900 { "blel+",   BBOCB(16,BOF,CBGT,0,1), BBOYCB_MASK, PPCCOM,       { CR, BDP } },
1901 { "blel",    BBOCB(16,BOF,CBGT,0,1), BBOYCB_MASK, COM,          { CR, BD } },
1902 { "blea-",   BBOCB(16,BOF,CBGT,1,0), BBOYCB_MASK, PPCCOM,       { CR, BDMA } },
1903 { "blea+",   BBOCB(16,BOF,CBGT,1,0), BBOYCB_MASK, PPCCOM,       { CR, BDPA } },
1904 { "blea",    BBOCB(16,BOF,CBGT,1,0), BBOYCB_MASK, COM,          { CR, BDA } },
1905 { "blela-",  BBOCB(16,BOF,CBGT,1,1), BBOYCB_MASK, PPCCOM,       { CR, BDMA } },
1906 { "blela+",  BBOCB(16,BOF,CBGT,1,1), BBOYCB_MASK, PPCCOM,       { CR, BDPA } },
1907 { "blela",   BBOCB(16,BOF,CBGT,1,1), BBOYCB_MASK, COM,          { CR, BDA } },
1908 { "bng-",    BBOCB(16,BOF,CBGT,0,0), BBOYCB_MASK, PPCCOM,       { CR, BDM } },
1909 { "bng+",    BBOCB(16,BOF,CBGT,0,0), BBOYCB_MASK, PPCCOM,       { CR, BDP } },
1910 { "bng",     BBOCB(16,BOF,CBGT,0,0), BBOYCB_MASK, COM,          { CR, BD } },
1911 { "bngl-",   BBOCB(16,BOF,CBGT,0,1), BBOYCB_MASK, PPCCOM,       { CR, BDM } },
1912 { "bngl+",   BBOCB(16,BOF,CBGT,0,1), BBOYCB_MASK, PPCCOM,       { CR, BDP } },
1913 { "bngl",    BBOCB(16,BOF,CBGT,0,1), BBOYCB_MASK, COM,          { CR, BD } },
1914 { "bnga-",   BBOCB(16,BOF,CBGT,1,0), BBOYCB_MASK, PPCCOM,       { CR, BDMA } },
1915 { "bnga+",   BBOCB(16,BOF,CBGT,1,0), BBOYCB_MASK, PPCCOM,       { CR, BDPA } },
1916 { "bnga",    BBOCB(16,BOF,CBGT,1,0), BBOYCB_MASK, COM,          { CR, BDA } },
1917 { "bngla-",  BBOCB(16,BOF,CBGT,1,1), BBOYCB_MASK, PPCCOM,       { CR, BDMA } },
1918 { "bngla+",  BBOCB(16,BOF,CBGT,1,1), BBOYCB_MASK, PPCCOM,       { CR, BDPA } },
1919 { "bngla",   BBOCB(16,BOF,CBGT,1,1), BBOYCB_MASK, COM,          { CR, BDA } },
1920 { "bne-",    BBOCB(16,BOF,CBEQ,0,0), BBOYCB_MASK, PPCCOM,       { CR, BDM } },
1921 { "bne+",    BBOCB(16,BOF,CBEQ,0,0), BBOYCB_MASK, PPCCOM,       { CR, BDP } },
1922 { "bne",     BBOCB(16,BOF,CBEQ,0,0), BBOYCB_MASK, COM,          { CR, BD } },
1923 { "bnel-",   BBOCB(16,BOF,CBEQ,0,1), BBOYCB_MASK, PPCCOM,       { CR, BDM } },
1924 { "bnel+",   BBOCB(16,BOF,CBEQ,0,1), BBOYCB_MASK, PPCCOM,       { CR, BDP } },
1925 { "bnel",    BBOCB(16,BOF,CBEQ,0,1), BBOYCB_MASK, COM,          { CR, BD } },
1926 { "bnea-",   BBOCB(16,BOF,CBEQ,1,0), BBOYCB_MASK, PPCCOM,       { CR, BDMA } },
1927 { "bnea+",   BBOCB(16,BOF,CBEQ,1,0), BBOYCB_MASK, PPCCOM,       { CR, BDPA } },
1928 { "bnea",    BBOCB(16,BOF,CBEQ,1,0), BBOYCB_MASK, COM,          { CR, BDA } },
1929 { "bnela-",  BBOCB(16,BOF,CBEQ,1,1), BBOYCB_MASK, PPCCOM,       { CR, BDMA } },
1930 { "bnela+",  BBOCB(16,BOF,CBEQ,1,1), BBOYCB_MASK, PPCCOM,       { CR, BDPA } },
1931 { "bnela",   BBOCB(16,BOF,CBEQ,1,1), BBOYCB_MASK, COM,          { CR, BDA } },
1932 { "bns-",    BBOCB(16,BOF,CBSO,0,0), BBOYCB_MASK, PPCCOM,       { CR, BDM } },
1933 { "bns+",    BBOCB(16,BOF,CBSO,0,0), BBOYCB_MASK, PPCCOM,       { CR, BDP } },
1934 { "bns",     BBOCB(16,BOF,CBSO,0,0), BBOYCB_MASK, COM,          { CR, BD } },
1935 { "bnsl-",   BBOCB(16,BOF,CBSO,0,1), BBOYCB_MASK, PPCCOM,       { CR, BDM } },
1936 { "bnsl+",   BBOCB(16,BOF,CBSO,0,1), BBOYCB_MASK, PPCCOM,       { CR, BDP } },
1937 { "bnsl",    BBOCB(16,BOF,CBSO,0,1), BBOYCB_MASK, COM,          { CR, BD } },
1938 { "bnsa-",   BBOCB(16,BOF,CBSO,1,0), BBOYCB_MASK, PPCCOM,       { CR, BDMA } },
1939 { "bnsa+",   BBOCB(16,BOF,CBSO,1,0), BBOYCB_MASK, PPCCOM,       { CR, BDPA } },
1940 { "bnsa",    BBOCB(16,BOF,CBSO,1,0), BBOYCB_MASK, COM,          { CR, BDA } },
1941 { "bnsla-",  BBOCB(16,BOF,CBSO,1,1), BBOYCB_MASK, PPCCOM,       { CR, BDMA } },
1942 { "bnsla+",  BBOCB(16,BOF,CBSO,1,1), BBOYCB_MASK, PPCCOM,       { CR, BDPA } },
1943 { "bnsla",   BBOCB(16,BOF,CBSO,1,1), BBOYCB_MASK, COM,          { CR, BDA } },
1944 { "bnu-",    BBOCB(16,BOF,CBSO,0,0), BBOYCB_MASK, PPCCOM,       { CR, BDM } },
1945 { "bnu+",    BBOCB(16,BOF,CBSO,0,0), BBOYCB_MASK, PPCCOM,       { CR, BDP } },
1946 { "bnu",     BBOCB(16,BOF,CBSO,0,0), BBOYCB_MASK, PPCCOM,       { CR, BD } },
1947 { "bnul-",   BBOCB(16,BOF,CBSO,0,1), BBOYCB_MASK, PPCCOM,       { CR, BDM } },
1948 { "bnul+",   BBOCB(16,BOF,CBSO,0,1), BBOYCB_MASK, PPCCOM,       { CR, BDP } },
1949 { "bnul",    BBOCB(16,BOF,CBSO,0,1), BBOYCB_MASK, PPCCOM,       { CR, BD } },
1950 { "bnua-",   BBOCB(16,BOF,CBSO,1,0), BBOYCB_MASK, PPCCOM,       { CR, BDMA } },
1951 { "bnua+",   BBOCB(16,BOF,CBSO,1,0), BBOYCB_MASK, PPCCOM,       { CR, BDPA } },
1952 { "bnua",    BBOCB(16,BOF,CBSO,1,0), BBOYCB_MASK, PPCCOM,       { CR, BDA } },
1953 { "bnula-",  BBOCB(16,BOF,CBSO,1,1), BBOYCB_MASK, PPCCOM,       { CR, BDMA } },
1954 { "bnula+",  BBOCB(16,BOF,CBSO,1,1), BBOYCB_MASK, PPCCOM,       { CR, BDPA } },
1955 { "bnula",   BBOCB(16,BOF,CBSO,1,1), BBOYCB_MASK, PPCCOM,       { CR, BDA } },
1956 { "bdnzt-",  BBO(16,BODNZT,0,0), BBOY_MASK, PPCCOM,     { BI, BDM } },
1957 { "bdnzt+",  BBO(16,BODNZT,0,0), BBOY_MASK, PPCCOM,     { BI, BDP } },
1958 { "bdnzt",   BBO(16,BODNZT,0,0), BBOY_MASK, PPCCOM,     { BI, BD } },
1959 { "bdnztl-", BBO(16,BODNZT,0,1), BBOY_MASK, PPCCOM,     { BI, BDM } },
1960 { "bdnztl+", BBO(16,BODNZT,0,1), BBOY_MASK, PPCCOM,     { BI, BDP } },
1961 { "bdnztl",  BBO(16,BODNZT,0,1), BBOY_MASK, PPCCOM,     { BI, BD } },
1962 { "bdnzta-", BBO(16,BODNZT,1,0), BBOY_MASK, PPCCOM,     { BI, BDMA } },
1963 { "bdnzta+", BBO(16,BODNZT,1,0), BBOY_MASK, PPCCOM,     { BI, BDPA } },
1964 { "bdnzta",  BBO(16,BODNZT,1,0), BBOY_MASK, PPCCOM,     { BI, BDA } },
1965 { "bdnztla-",BBO(16,BODNZT,1,1), BBOY_MASK, PPCCOM,     { BI, BDMA } },
1966 { "bdnztla+",BBO(16,BODNZT,1,1), BBOY_MASK, PPCCOM,     { BI, BDPA } },
1967 { "bdnztla", BBO(16,BODNZT,1,1), BBOY_MASK, PPCCOM,     { BI, BDA } },
1968 { "bdnzf-",  BBO(16,BODNZF,0,0), BBOY_MASK, PPCCOM,     { BI, BDM } },
1969 { "bdnzf+",  BBO(16,BODNZF,0,0), BBOY_MASK, PPCCOM,     { BI, BDP } },
1970 { "bdnzf",   BBO(16,BODNZF,0,0), BBOY_MASK, PPCCOM,     { BI, BD } },
1971 { "bdnzfl-", BBO(16,BODNZF,0,1), BBOY_MASK, PPCCOM,     { BI, BDM } },
1972 { "bdnzfl+", BBO(16,BODNZF,0,1), BBOY_MASK, PPCCOM,     { BI, BDP } },
1973 { "bdnzfl",  BBO(16,BODNZF,0,1), BBOY_MASK, PPCCOM,     { BI, BD } },
1974 { "bdnzfa-", BBO(16,BODNZF,1,0), BBOY_MASK, PPCCOM,     { BI, BDMA } },
1975 { "bdnzfa+", BBO(16,BODNZF,1,0), BBOY_MASK, PPCCOM,     { BI, BDPA } },
1976 { "bdnzfa",  BBO(16,BODNZF,1,0), BBOY_MASK, PPCCOM,     { BI, BDA } },
1977 { "bdnzfla-",BBO(16,BODNZF,1,1), BBOY_MASK, PPCCOM,     { BI, BDMA } },
1978 { "bdnzfla+",BBO(16,BODNZF,1,1), BBOY_MASK, PPCCOM,     { BI, BDPA } },
1979 { "bdnzfla", BBO(16,BODNZF,1,1), BBOY_MASK, PPCCOM,     { BI, BDA } },
1980 { "bt-",     BBO(16,BOT,0,0), BBOY_MASK, PPCCOM,        { BI, BDM } },
1981 { "bt+",     BBO(16,BOT,0,0), BBOY_MASK, PPCCOM,        { BI, BDP } },
1982 { "bt",      BBO(16,BOT,0,0), BBOY_MASK, PPCCOM,        { BI, BD } },
1983 { "bbt",     BBO(16,BOT,0,0), BBOY_MASK, PWRCOM,        { BI, BD } },
1984 { "btl-",    BBO(16,BOT,0,1), BBOY_MASK, PPCCOM,        { BI, BDM } },
1985 { "btl+",    BBO(16,BOT,0,1), BBOY_MASK, PPCCOM,        { BI, BDP } },
1986 { "btl",     BBO(16,BOT,0,1), BBOY_MASK, PPCCOM,        { BI, BD } },
1987 { "bbtl",    BBO(16,BOT,0,1), BBOY_MASK, PWRCOM,        { BI, BD } },
1988 { "bta-",    BBO(16,BOT,1,0), BBOY_MASK, PPCCOM,        { BI, BDMA } },
1989 { "bta+",    BBO(16,BOT,1,0), BBOY_MASK, PPCCOM,        { BI, BDPA } },
1990 { "bta",     BBO(16,BOT,1,0), BBOY_MASK, PPCCOM,        { BI, BDA } },
1991 { "bbta",    BBO(16,BOT,1,0), BBOY_MASK, PWRCOM,        { BI, BDA } },
1992 { "btla-",   BBO(16,BOT,1,1), BBOY_MASK, PPCCOM,        { BI, BDMA } },
1993 { "btla+",   BBO(16,BOT,1,1), BBOY_MASK, PPCCOM,        { BI, BDPA } },
1994 { "btla",    BBO(16,BOT,1,1), BBOY_MASK, PPCCOM,        { BI, BDA } },
1995 { "bbtla",   BBO(16,BOT,1,1), BBOY_MASK, PWRCOM,        { BI, BDA } },
1996 { "bf-",     BBO(16,BOF,0,0), BBOY_MASK, PPCCOM,        { BI, BDM } },
1997 { "bf+",     BBO(16,BOF,0,0), BBOY_MASK, PPCCOM,        { BI, BDP } },
1998 { "bf",      BBO(16,BOF,0,0), BBOY_MASK, PPCCOM,        { BI, BD } },
1999 { "bbf",     BBO(16,BOF,0,0), BBOY_MASK, PWRCOM,        { BI, BD } },
2000 { "bfl-",    BBO(16,BOF,0,1), BBOY_MASK, PPCCOM,        { BI, BDM } },
2001 { "bfl+",    BBO(16,BOF,0,1), BBOY_MASK, PPCCOM,        { BI, BDP } },
2002 { "bfl",     BBO(16,BOF,0,1), BBOY_MASK, PPCCOM,        { BI, BD } },
2003 { "bbfl",    BBO(16,BOF,0,1), BBOY_MASK, PWRCOM,        { BI, BD } },
2004 { "bfa-",    BBO(16,BOF,1,0), BBOY_MASK, PPCCOM,        { BI, BDMA } },
2005 { "bfa+",    BBO(16,BOF,1,0), BBOY_MASK, PPCCOM,        { BI, BDPA } },
2006 { "bfa",     BBO(16,BOF,1,0), BBOY_MASK, PPCCOM,        { BI, BDA } },
2007 { "bbfa",    BBO(16,BOF,1,0), BBOY_MASK, PWRCOM,        { BI, BDA } },
2008 { "bfla-",   BBO(16,BOF,1,1), BBOY_MASK, PPCCOM,        { BI, BDMA } },
2009 { "bfla+",   BBO(16,BOF,1,1), BBOY_MASK, PPCCOM,        { BI, BDPA } },
2010 { "bfla",    BBO(16,BOF,1,1), BBOY_MASK, PPCCOM,        { BI, BDA } },
2011 { "bbfla",   BBO(16,BOF,1,1), BBOY_MASK, PWRCOM,        { BI, BDA } },
2012 { "bdzt-",   BBO(16,BODZT,0,0), BBOY_MASK, PPCCOM,      { BI, BDM } },
2013 { "bdzt+",   BBO(16,BODZT,0,0), BBOY_MASK, PPCCOM,      { BI, BDP } },
2014 { "bdzt",    BBO(16,BODZT,0,0), BBOY_MASK, PPCCOM,      { BI, BD } },
2015 { "bdztl-",  BBO(16,BODZT,0,1), BBOY_MASK, PPCCOM,      { BI, BDM } },
2016 { "bdztl+",  BBO(16,BODZT,0,1), BBOY_MASK, PPCCOM,      { BI, BDP } },
2017 { "bdztl",   BBO(16,BODZT,0,1), BBOY_MASK, PPCCOM,      { BI, BD } },
2018 { "bdzta-",  BBO(16,BODZT,1,0), BBOY_MASK, PPCCOM,      { BI, BDMA } },
2019 { "bdzta+",  BBO(16,BODZT,1,0), BBOY_MASK, PPCCOM,      { BI, BDPA } },
2020 { "bdzta",   BBO(16,BODZT,1,0), BBOY_MASK, PPCCOM,      { BI, BDA } },
2021 { "bdztla-", BBO(16,BODZT,1,1), BBOY_MASK, PPCCOM,      { BI, BDMA } },
2022 { "bdztla+", BBO(16,BODZT,1,1), BBOY_MASK, PPCCOM,      { BI, BDPA } },
2023 { "bdztla",  BBO(16,BODZT,1,1), BBOY_MASK, PPCCOM,      { BI, BDA } },
2024 { "bdzf-",   BBO(16,BODZF,0,0), BBOY_MASK, PPCCOM,      { BI, BDM } },
2025 { "bdzf+",   BBO(16,BODZF,0,0), BBOY_MASK, PPCCOM,      { BI, BDP } },
2026 { "bdzf",    BBO(16,BODZF,0,0), BBOY_MASK, PPCCOM,      { BI, BD } },
2027 { "bdzfl-",  BBO(16,BODZF,0,1), BBOY_MASK, PPCCOM,      { BI, BDM } },
2028 { "bdzfl+",  BBO(16,BODZF,0,1), BBOY_MASK, PPCCOM,      { BI, BDP } },
2029 { "bdzfl",   BBO(16,BODZF,0,1), BBOY_MASK, PPCCOM,      { BI, BD } },
2030 { "bdzfa-",  BBO(16,BODZF,1,0), BBOY_MASK, PPCCOM,      { BI, BDMA } },
2031 { "bdzfa+",  BBO(16,BODZF,1,0), BBOY_MASK, PPCCOM,      { BI, BDPA } },
2032 { "bdzfa",   BBO(16,BODZF,1,0), BBOY_MASK, PPCCOM,      { BI, BDA } },
2033 { "bdzfla-", BBO(16,BODZF,1,1), BBOY_MASK, PPCCOM,      { BI, BDMA } },
2034 { "bdzfla+", BBO(16,BODZF,1,1), BBOY_MASK, PPCCOM,      { BI, BDPA } },
2035 { "bdzfla",  BBO(16,BODZF,1,1), BBOY_MASK, PPCCOM,      { BI, BDA } },
2036 { "bc-",     B(16,0,0), B_MASK,         PPCCOM,         { BOE, BI, BDM } },
2037 { "bc+",     B(16,0,0), B_MASK,         PPCCOM,         { BOE, BI, BDP } },
2038 { "bc",      B(16,0,0), B_MASK,         COM,            { BO, BI, BD } },
2039 { "bcl-",    B(16,0,1), B_MASK,         PPCCOM,         { BOE, BI, BDM } },
2040 { "bcl+",    B(16,0,1), B_MASK,         PPCCOM,         { BOE, BI, BDP } },
2041 { "bcl",     B(16,0,1), B_MASK,         COM,            { BO, BI, BD } },
2042 { "bca-",    B(16,1,0), B_MASK,         PPCCOM,         { BOE, BI, BDMA } },
2043 { "bca+",    B(16,1,0), B_MASK,         PPCCOM,         { BOE, BI, BDPA } },
2044 { "bca",     B(16,1,0), B_MASK,         COM,            { BO, BI, BDA } },
2045 { "bcla-",   B(16,1,1), B_MASK,         PPCCOM,         { BOE, BI, BDMA } },
2046 { "bcla+",   B(16,1,1), B_MASK,         PPCCOM,         { BOE, BI, BDPA } },
2047 { "bcla",    B(16,1,1), B_MASK,         COM,            { BO, BI, BDA } },
2048
2049 { "sc",      SC(17,1,0), 0xffffffff,    PPC,            { 0 } },
2050 { "svc",     SC(17,0,0), SC_MASK,       POWER,          { LEV, FL1, FL2 } },
2051 { "svcl",    SC(17,0,1), SC_MASK,       POWER,          { LEV, FL1, FL2 } },
2052 { "svca",    SC(17,1,0), SC_MASK,       PWRCOM,         { SV } },
2053 { "svcla",   SC(17,1,1), SC_MASK,       POWER,          { SV } },
2054
2055 { "b",       B(18,0,0), B_MASK,         COM,            { LI } },
2056 { "bl",      B(18,0,1), B_MASK,         COM,            { LI } },
2057 { "ba",      B(18,1,0), B_MASK,         COM,            { LIA } },
2058 { "bla",     B(18,1,1), B_MASK,         COM,            { LIA } },
2059
2060 { "mcrf",    XL(19,0),  XLBB_MASK|(3<<21)|(3<<16), COM, { BF, BFA } },
2061
2062 { "blr",     XLO(19,BOU,16,0), XLBOBIBB_MASK, PPCCOM,   { 0 } },
2063 { "br",      XLO(19,BOU,16,0), XLBOBIBB_MASK, PWRCOM,   { 0 } },
2064 { "blrl",    XLO(19,BOU,16,1), XLBOBIBB_MASK, PPCCOM,   { 0 } },
2065 { "brl",     XLO(19,BOU,16,1), XLBOBIBB_MASK, PWRCOM,   { 0 } },
2066 { "bdnzlr",  XLO(19,BODNZ,16,0), XLBOBIBB_MASK, PPCCOM, { 0 } },
2067 { "bdnzlr-", XLO(19,BODNZ,16,0), XLBOBIBB_MASK, PPCCOM, { 0 } },
2068 { "bdnzlr+", XLO(19,BODNZP,16,0), XLBOBIBB_MASK, PPCCOM,        { 0 } },
2069 { "bdnzlrl", XLO(19,BODNZ,16,1), XLBOBIBB_MASK, PPCCOM, { 0 } },
2070 { "bdnzlrl-",XLO(19,BODNZ,16,1), XLBOBIBB_MASK, PPCCOM, { 0 } },
2071 { "bdnzlrl+",XLO(19,BODNZP,16,1), XLBOBIBB_MASK, PPCCOM,        { 0 } },
2072 { "bdzlr",   XLO(19,BODZ,16,0), XLBOBIBB_MASK, PPCCOM,  { 0 } },
2073 { "bdzlr-",  XLO(19,BODZ,16,0), XLBOBIBB_MASK, PPCCOM,  { 0 } },
2074 { "bdzlr+",  XLO(19,BODZP,16,0), XLBOBIBB_MASK, PPCCOM, { 0 } },
2075 { "bdzlrl",  XLO(19,BODZ,16,1), XLBOBIBB_MASK, PPCCOM,  { 0 } },
2076 { "bdzlrl-", XLO(19,BODZ,16,1), XLBOBIBB_MASK, PPCCOM,  { 0 } },
2077 { "bdzlrl+", XLO(19,BODZP,16,1), XLBOBIBB_MASK, PPCCOM, { 0 } },
2078 { "bltlr",   XLOCB(19,BOT,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2079 { "bltlr-",  XLOCB(19,BOT,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2080 { "bltlr+",  XLOCB(19,BOTP,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2081 { "bltr",    XLOCB(19,BOT,CBLT,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
2082 { "bltlrl",  XLOCB(19,BOT,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2083 { "bltlrl-", XLOCB(19,BOT,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2084 { "bltlrl+", XLOCB(19,BOTP,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2085 { "bltrl",   XLOCB(19,BOT,CBLT,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
2086 { "bgtlr",   XLOCB(19,BOT,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2087 { "bgtlr-",  XLOCB(19,BOT,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2088 { "bgtlr+",  XLOCB(19,BOTP,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2089 { "bgtr",    XLOCB(19,BOT,CBGT,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
2090 { "bgtlrl",  XLOCB(19,BOT,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2091 { "bgtlrl-", XLOCB(19,BOT,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2092 { "bgtlrl+", XLOCB(19,BOTP,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2093 { "bgtrl",   XLOCB(19,BOT,CBGT,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
2094 { "beqlr",   XLOCB(19,BOT,CBEQ,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2095 { "beqlr-",  XLOCB(19,BOT,CBEQ,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2096 { "beqlr+",  XLOCB(19,BOTP,CBEQ,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2097 { "beqr",    XLOCB(19,BOT,CBEQ,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
2098 { "beqlrl",  XLOCB(19,BOT,CBEQ,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2099 { "beqlrl-", XLOCB(19,BOT,CBEQ,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2100 { "beqlrl+", XLOCB(19,BOTP,CBEQ,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2101 { "beqrl",   XLOCB(19,BOT,CBEQ,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
2102 { "bsolr",   XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2103 { "bsolr-",  XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2104 { "bsolr+",  XLOCB(19,BOTP,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2105 { "bsor",    XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
2106 { "bsolrl",  XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2107 { "bsolrl-", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2108 { "bsolrl+", XLOCB(19,BOTP,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2109 { "bsorl",   XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
2110 { "bunlr",   XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2111 { "bunlr-",  XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2112 { "bunlr+",  XLOCB(19,BOTP,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2113 { "bunlrl",  XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2114 { "bunlrl-", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2115 { "bunlrl+", XLOCB(19,BOTP,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2116 { "bgelr",   XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2117 { "bgelr-",  XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2118 { "bgelr+",  XLOCB(19,BOFP,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2119 { "bger",    XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
2120 { "bgelrl",  XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2121 { "bgelrl-", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2122 { "bgelrl+", XLOCB(19,BOFP,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2123 { "bgerl",   XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
2124 { "bnllr",   XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2125 { "bnllr-",  XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2126 { "bnllr+",  XLOCB(19,BOFP,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2127 { "bnlr",    XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
2128 { "bnllrl",  XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2129 { "bnllrl-", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2130 { "bnllrl+", XLOCB(19,BOFP,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2131 { "bnlrl",   XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
2132 { "blelr",   XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2133 { "blelr-",  XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2134 { "blelr+",  XLOCB(19,BOFP,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2135 { "bler",    XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
2136 { "blelrl",  XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2137 { "blelrl-", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2138 { "blelrl+", XLOCB(19,BOFP,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2139 { "blerl",   XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
2140 { "bnglr",   XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2141 { "bnglr-",  XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2142 { "bnglr+",  XLOCB(19,BOFP,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2143 { "bngr",    XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
2144 { "bnglrl",  XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2145 { "bnglrl-", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2146 { "bnglrl+", XLOCB(19,BOFP,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2147 { "bngrl",   XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
2148 { "bnelr",   XLOCB(19,BOF,CBEQ,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2149 { "bnelr-",  XLOCB(19,BOF,CBEQ,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2150 { "bnelr+",  XLOCB(19,BOFP,CBEQ,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2151 { "bner",    XLOCB(19,BOF,CBEQ,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
2152 { "bnelrl",  XLOCB(19,BOF,CBEQ,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2153 { "bnelrl-", XLOCB(19,BOF,CBEQ,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2154 { "bnelrl+", XLOCB(19,BOFP,CBEQ,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2155 { "bnerl",   XLOCB(19,BOF,CBEQ,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
2156 { "bnslr",   XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2157 { "bnslr-",  XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2158 { "bnslr+",  XLOCB(19,BOFP,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2159 { "bnsr",    XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
2160 { "bnslrl",  XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2161 { "bnslrl-", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2162 { "bnslrl+", XLOCB(19,BOFP,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2163 { "bnsrl",   XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
2164 { "bnulr",   XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2165 { "bnulr-",  XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2166 { "bnulr+",  XLOCB(19,BOFP,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2167 { "bnulrl",  XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2168 { "bnulrl-", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2169 { "bnulrl+", XLOCB(19,BOFP,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2170 { "btlr",    XLO(19,BOT,16,0), XLBOBB_MASK, PPCCOM,     { BI } },
2171 { "btlr-",   XLO(19,BOT,16,0), XLBOBB_MASK, PPCCOM,     { BI } },
2172 { "btlr+",   XLO(19,BOTP,16,0), XLBOBB_MASK, PPCCOM,    { BI } },
2173 { "bbtr",    XLO(19,BOT,16,0), XLBOBB_MASK, PWRCOM,     { BI } },
2174 { "btlrl",   XLO(19,BOT,16,1), XLBOBB_MASK, PPCCOM,     { BI } },
2175 { "btlrl-",  XLO(19,BOT,16,1), XLBOBB_MASK, PPCCOM,     { BI } },
2176 { "btlrl+",  XLO(19,BOTP,16,1), XLBOBB_MASK, PPCCOM,    { BI } },
2177 { "bbtrl",   XLO(19,BOT,16,1), XLBOBB_MASK, PWRCOM,     { BI } },
2178 { "bflr",    XLO(19,BOF,16,0), XLBOBB_MASK, PPCCOM,     { BI } },
2179 { "bflr-",   XLO(19,BOF,16,0), XLBOBB_MASK, PPCCOM,     { BI } },
2180 { "bflr+",   XLO(19,BOFP,16,0), XLBOBB_MASK, PPCCOM,    { BI } },
2181 { "bbfr",    XLO(19,BOF,16,0), XLBOBB_MASK, PWRCOM,     { BI } },
2182 { "bflrl",   XLO(19,BOF,16,1), XLBOBB_MASK, PPCCOM,     { BI } },
2183 { "bflrl-",  XLO(19,BOF,16,1), XLBOBB_MASK, PPCCOM,     { BI } },
2184 { "bflrl+",  XLO(19,BOFP,16,1), XLBOBB_MASK, PPCCOM,    { BI } },
2185 { "bbfrl",   XLO(19,BOF,16,1), XLBOBB_MASK, PWRCOM,     { BI } },
2186 { "bdnztlr", XLO(19,BODNZT,16,0), XLBOBB_MASK, PPCCOM,  { BI } },
2187 { "bdnztlr-",XLO(19,BODNZT,16,0), XLBOBB_MASK, PPCCOM,  { BI } },
2188 { "bdnztlr+",XLO(19,BODNZTP,16,0), XLBOBB_MASK, PPCCOM, { BI } },
2189 { "bdnztlrl",XLO(19,BODNZT,16,1), XLBOBB_MASK, PPCCOM,  { BI } },
2190 { "bdnztlrl-",XLO(19,BODNZT,16,1), XLBOBB_MASK, PPCCOM, { BI } },
2191 { "bdnztlrl+",XLO(19,BODNZTP,16,1), XLBOBB_MASK, PPCCOM,{ BI } },
2192 { "bdnzflr", XLO(19,BODNZF,16,0), XLBOBB_MASK, PPCCOM,  { BI } },
2193 { "bdnzflr-",XLO(19,BODNZF,16,0), XLBOBB_MASK, PPCCOM,  { BI } },
2194 { "bdnzflr+",XLO(19,BODNZFP,16,0), XLBOBB_MASK, PPCCOM, { BI } },
2195 { "bdnzflrl",XLO(19,BODNZF,16,1), XLBOBB_MASK, PPCCOM,  { BI } },
2196 { "bdnzflrl-",XLO(19,BODNZF,16,1), XLBOBB_MASK, PPCCOM, { BI } },
2197 { "bdnzflrl+",XLO(19,BODNZFP,16,1), XLBOBB_MASK, PPCCOM,{ BI } },
2198 { "bdztlr",  XLO(19,BODZT,16,0), XLBOBB_MASK, PPCCOM,   { BI } },
2199 { "bdztlr-", XLO(19,BODZT,16,0), XLBOBB_MASK, PPCCOM,   { BI } },
2200 { "bdztlr+", XLO(19,BODZTP,16,0), XLBOBB_MASK, PPCCOM,  { BI } },
2201 { "bdztlrl", XLO(19,BODZT,16,1), XLBOBB_MASK, PPCCOM,   { BI } },
2202 { "bdztlrl-",XLO(19,BODZT,16,1), XLBOBB_MASK, PPCCOM,   { BI } },
2203 { "bdztlrl+",XLO(19,BODZTP,16,1), XLBOBB_MASK, PPCCOM,  { BI } },
2204 { "bdzflr",  XLO(19,BODZF,16,0), XLBOBB_MASK, PPCCOM,   { BI } },
2205 { "bdzflr-", XLO(19,BODZF,16,0), XLBOBB_MASK, PPCCOM,   { BI } },
2206 { "bdzflr+", XLO(19,BODZFP,16,0), XLBOBB_MASK, PPCCOM,  { BI } },
2207 { "bdzflrl", XLO(19,BODZF,16,1), XLBOBB_MASK, PPCCOM,   { BI } },
2208 { "bdzflrl-",XLO(19,BODZF,16,1), XLBOBB_MASK, PPCCOM,   { BI } },
2209 { "bdzflrl+",XLO(19,BODZFP,16,1), XLBOBB_MASK, PPCCOM,  { BI } },
2210 { "bclr",    XLLK(19,16,0), XLYBB_MASK, PPCCOM,         { BO, BI } },
2211 { "bclrl",   XLLK(19,16,1), XLYBB_MASK, PPCCOM,         { BO, BI } },
2212 { "bclr+",   XLYLK(19,16,1,0), XLYBB_MASK, PPCCOM,      { BOE, BI } },
2213 { "bclrl+",  XLYLK(19,16,1,1), XLYBB_MASK, PPCCOM,      { BOE, BI } },
2214 { "bclr-",   XLYLK(19,16,0,0), XLYBB_MASK, PPCCOM,      { BOE, BI } },
2215 { "bclrl-",  XLYLK(19,16,0,1), XLYBB_MASK, PPCCOM,      { BOE, BI } },
2216 { "bcr",     XLLK(19,16,0), XLBB_MASK,  PWRCOM,         { BO, BI } },
2217 { "bcrl",    XLLK(19,16,1), XLBB_MASK,  PWRCOM,         { BO, BI } },
2218 { "bclre",   XLLK(19,17,0), XLBB_MASK,  BOOKE64,        { BO, BI } },
2219 { "bclrel",  XLLK(19,17,1), XLBB_MASK,  BOOKE64,        { BO, BI } },
2220
2221 { "rfid",    XL(19,18), 0xffffffff,     PPC64,          { 0 } },
2222
2223 { "crnot",   XL(19,33), XL_MASK,        PPCCOM,         { BT, BA, BBA } },
2224 { "crnor",   XL(19,33), XL_MASK,        COM,            { BT, BA, BB } },
2225
2226 { "rfi",     XL(19,50), 0xffffffff,     COM,            { 0 } },
2227 { "rfci",    XL(19,51), 0xffffffff,     PPC403,         { 0 } },
2228
2229 { "rfsvc",   XL(19,82), 0xffffffff,     POWER,          { 0 } },
2230
2231 { "crandc",  XL(19,129), XL_MASK,       COM,            { BT, BA, BB } },
2232
2233 { "isync",   XL(19,150), 0xffffffff,    PPCCOM,         { 0 } },
2234 { "ics",     XL(19,150), 0xffffffff,    PWRCOM,         { 0 } },
2235
2236 { "crclr",   XL(19,193), XL_MASK,       PPCCOM,         { BT, BAT, BBA } },
2237 { "crxor",   XL(19,193), XL_MASK,       COM,            { BT, BA, BB } },
2238
2239 { "crnand",  XL(19,225), XL_MASK,       COM,            { BT, BA, BB } },
2240
2241 { "crand",   XL(19,257), XL_MASK,       COM,            { BT, BA, BB } },
2242
2243 { "crset",   XL(19,289), XL_MASK,       PPCCOM,         { BT, BAT, BBA } },
2244 { "creqv",   XL(19,289), XL_MASK,       COM,            { BT, BA, BB } },
2245
2246 { "crorc",   XL(19,417), XL_MASK,       COM,            { BT, BA, BB } },
2247
2248 { "crmove",  XL(19,449), XL_MASK,       PPCCOM,         { BT, BA, BBA } },
2249 { "cror",    XL(19,449), XL_MASK,       COM,            { BT, BA, BB } },
2250
2251 { "bctr",    XLO(19,BOU,528,0), XLBOBIBB_MASK, COM,     { 0 } },
2252 { "bctrl",   XLO(19,BOU,528,1), XLBOBIBB_MASK, COM,     { 0 } },
2253 { "bltctr",  XLOCB(19,BOT,CBLT,528,0),  XLBOCBBB_MASK, PPCCOM,  { CR } },
2254 { "bltctr-", XLOCB(19,BOT,CBLT,528,0),  XLBOCBBB_MASK, PPCCOM,  { CR } },
2255 { "bltctr+", XLOCB(19,BOTP,CBLT,528,0), XLBOCBBB_MASK, PPCCOM,  { CR } },
2256 { "bltctrl", XLOCB(19,BOT,CBLT,528,1),  XLBOCBBB_MASK, PPCCOM,  { CR } },
2257 { "bltctrl-",XLOCB(19,BOT,CBLT,528,1),  XLBOCBBB_MASK, PPCCOM,  { CR } },
2258 { "bltctrl+",XLOCB(19,BOTP,CBLT,528,1), XLBOCBBB_MASK, PPCCOM,  { CR } },
2259 { "bgtctr",  XLOCB(19,BOT,CBGT,528,0),  XLBOCBBB_MASK, PPCCOM,  { CR } },
2260 { "bgtctr-", XLOCB(19,BOT,CBGT,528,0),  XLBOCBBB_MASK, PPCCOM,  { CR } },
2261 { "bgtctr+", XLOCB(19,BOTP,CBGT,528,0), XLBOCBBB_MASK, PPCCOM,  { CR } },
2262 { "bgtctrl", XLOCB(19,BOT,CBGT,528,1),  XLBOCBBB_MASK, PPCCOM,  { CR } },
2263 { "bgtctrl-",XLOCB(19,BOT,CBGT,528,1),  XLBOCBBB_MASK, PPCCOM,  { CR } },
2264 { "bgtctrl+",XLOCB(19,BOTP,CBGT,528,1), XLBOCBBB_MASK, PPCCOM,  { CR } },
2265 { "beqctr",  XLOCB(19,BOT,CBEQ,528,0),  XLBOCBBB_MASK, PPCCOM,  { CR } },
2266 { "beqctr-", XLOCB(19,BOT,CBEQ,528,0),  XLBOCBBB_MASK, PPCCOM,  { CR } },
2267 { "beqctr+", XLOCB(19,BOTP,CBEQ,528,0), XLBOCBBB_MASK, PPCCOM,  { CR } },
2268 { "beqctrl", XLOCB(19,BOT,CBEQ,528,1),  XLBOCBBB_MASK, PPCCOM,  { CR } },
2269 { "beqctrl-",XLOCB(19,BOT,CBEQ,528,1),  XLBOCBBB_MASK, PPCCOM,  { CR } },
2270 { "beqctrl+",XLOCB(19,BOTP,CBEQ,528,1), XLBOCBBB_MASK, PPCCOM,  { CR } },
2271 { "bsoctr",  XLOCB(19,BOT,CBSO,528,0),  XLBOCBBB_MASK, PPCCOM,  { CR } },
2272 { "bsoctr-", XLOCB(19,BOT,CBSO,528,0),  XLBOCBBB_MASK, PPCCOM,  { CR } },
2273 { "bsoctr+", XLOCB(19,BOTP,CBSO,528,0), XLBOCBBB_MASK, PPCCOM,  { CR } },
2274 { "bsoctrl", XLOCB(19,BOT,CBSO,528,1),  XLBOCBBB_MASK, PPCCOM,  { CR } },
2275 { "bsoctrl-",XLOCB(19,BOT,CBSO,528,1),  XLBOCBBB_MASK, PPCCOM,  { CR } },
2276 { "bsoctrl+",XLOCB(19,BOTP,CBSO,528,1), XLBOCBBB_MASK, PPCCOM,  { CR } },
2277 { "bunctr",  XLOCB(19,BOT,CBSO,528,0),  XLBOCBBB_MASK, PPCCOM,  { CR } },
2278 { "bunctr-", XLOCB(19,BOT,CBSO,528,0),  XLBOCBBB_MASK, PPCCOM,  { CR } },
2279 { "bunctr+", XLOCB(19,BOTP,CBSO,528,0), XLBOCBBB_MASK, PPCCOM,  { CR } },
2280 { "bunctrl", XLOCB(19,BOT,CBSO,528,1),  XLBOCBBB_MASK, PPCCOM,  { CR } },
2281 { "bunctrl-",XLOCB(19,BOT,CBSO,528,1),  XLBOCBBB_MASK, PPCCOM,  { CR } },
2282 { "bunctrl+",XLOCB(19,BOTP,CBSO,528,1), XLBOCBBB_MASK, PPCCOM,  { CR } },
2283 { "bgectr",  XLOCB(19,BOF,CBLT,528,0),  XLBOCBBB_MASK, PPCCOM,  { CR } },
2284 { "bgectr-", XLOCB(19,BOF,CBLT,528,0),  XLBOCBBB_MASK, PPCCOM,  { CR } },
2285 { "bgectr+", XLOCB(19,BOFP,CBLT,528,0), XLBOCBBB_MASK, PPCCOM,  { CR } },
2286 { "bgectrl", XLOCB(19,BOF,CBLT,528,1),  XLBOCBBB_MASK, PPCCOM,  { CR } },
2287 { "bgectrl-",XLOCB(19,BOF,CBLT,528,1),  XLBOCBBB_MASK, PPCCOM,  { CR } },
2288 { "bgectrl+",XLOCB(19,BOFP,CBLT,528,1), XLBOCBBB_MASK, PPCCOM,  { CR } },
2289 { "bnlctr",  XLOCB(19,BOF,CBLT,528,0),  XLBOCBBB_MASK, PPCCOM,  { CR } },
2290 { "bnlctr-", XLOCB(19,BOF,CBLT,528,0),  XLBOCBBB_MASK, PPCCOM,  { CR } },
2291 { "bnlctr+", XLOCB(19,BOFP,CBLT,528,0), XLBOCBBB_MASK, PPCCOM,  { CR } },
2292 { "bnlctrl", XLOCB(19,BOF,CBLT,528,1),  XLBOCBBB_MASK, PPCCOM,  { CR } },
2293 { "bnlctrl-",XLOCB(19,BOF,CBLT,528,1),  XLBOCBBB_MASK, PPCCOM,  { CR } },
2294 { "bnlctrl+",XLOCB(19,BOFP,CBLT,528,1), XLBOCBBB_MASK, PPCCOM,  { CR } },
2295 { "blectr",  XLOCB(19,BOF,CBGT,528,0),  XLBOCBBB_MASK, PPCCOM,  { CR } },
2296 { "blectr-", XLOCB(19,BOF,CBGT,528,0),  XLBOCBBB_MASK, PPCCOM,  { CR } },
2297 { "blectr+", XLOCB(19,BOFP,CBGT,528,0), XLBOCBBB_MASK, PPCCOM,  { CR } },
2298 { "blectrl", XLOCB(19,BOF,CBGT,528,1),  XLBOCBBB_MASK, PPCCOM,  { CR } },
2299 { "blectrl-",XLOCB(19,BOF,CBGT,528,1),  XLBOCBBB_MASK, PPCCOM,  { CR } },
2300 { "blectrl+",XLOCB(19,BOFP,CBGT,528,1), XLBOCBBB_MASK, PPCCOM,  { CR } },
2301 { "bngctr",  XLOCB(19,BOF,CBGT,528,0),  XLBOCBBB_MASK, PPCCOM,  { CR } },
2302 { "bngctr-", XLOCB(19,BOF,CBGT,528,0),  XLBOCBBB_MASK, PPCCOM,  { CR } },
2303 { "bngctr+", XLOCB(19,BOFP,CBGT,528,0), XLBOCBBB_MASK, PPCCOM,  { CR } },
2304 { "bngctrl", XLOCB(19,BOF,CBGT,528,1),  XLBOCBBB_MASK, PPCCOM,  { CR } },
2305 { "bngctrl-",XLOCB(19,BOF,CBGT,528,1),  XLBOCBBB_MASK, PPCCOM,  { CR } },
2306 { "bngctrl+",XLOCB(19,BOFP,CBGT,528,1), XLBOCBBB_MASK, PPCCOM,  { CR } },
2307 { "bnectr",  XLOCB(19,BOF,CBEQ,528,0),  XLBOCBBB_MASK, PPCCOM,  { CR } },
2308 { "bnectr-", XLOCB(19,BOF,CBEQ,528,0),  XLBOCBBB_MASK, PPCCOM,  { CR } },
2309 { "bnectr+", XLOCB(19,BOFP,CBEQ,528,0), XLBOCBBB_MASK, PPCCOM,  { CR } },
2310 { "bnectrl", XLOCB(19,BOF,CBEQ,528,1),  XLBOCBBB_MASK, PPCCOM,  { CR } },
2311 { "bnectrl-",XLOCB(19,BOF,CBEQ,528,1),  XLBOCBBB_MASK, PPCCOM,  { CR } },
2312 { "bnectrl+",XLOCB(19,BOFP,CBEQ,528,1), XLBOCBBB_MASK, PPCCOM,  { CR } },
2313 { "bnsctr",  XLOCB(19,BOF,CBSO,528,0),  XLBOCBBB_MASK, PPCCOM,  { CR } },
2314 { "bnsctr-", XLOCB(19,BOF,CBSO,528,0),  XLBOCBBB_MASK, PPCCOM,  { CR } },
2315 { "bnsctr+", XLOCB(19,BOFP,CBSO,528,0), XLBOCBBB_MASK, PPCCOM,  { CR } },
2316 { "bnsctrl", XLOCB(19,BOF,CBSO,528,1),  XLBOCBBB_MASK, PPCCOM,  { CR } },
2317 { "bnsctrl-",XLOCB(19,BOF,CBSO,528,1),  XLBOCBBB_MASK, PPCCOM,  { CR } },
2318 { "bnsctrl+",XLOCB(19,BOFP,CBSO,528,1), XLBOCBBB_MASK, PPCCOM,  { CR } },
2319 { "bnuctr",  XLOCB(19,BOF,CBSO,528,0),  XLBOCBBB_MASK, PPCCOM,  { CR } },
2320 { "bnuctr-", XLOCB(19,BOF,CBSO,528,0),  XLBOCBBB_MASK, PPCCOM,  { CR } },
2321 { "bnuctr+", XLOCB(19,BOFP,CBSO,528,0), XLBOCBBB_MASK, PPCCOM,  { CR } },
2322 { "bnuctrl", XLOCB(19,BOF,CBSO,528,1),  XLBOCBBB_MASK, PPCCOM,  { CR } },
2323 { "bnuctrl-",XLOCB(19,BOF,CBSO,528,1),  XLBOCBBB_MASK, PPCCOM,  { CR } },
2324 { "bnuctrl+",XLOCB(19,BOFP,CBSO,528,1), XLBOCBBB_MASK, PPCCOM,  { CR } },
2325 { "btctr",   XLO(19,BOT,528,0),  XLBOBB_MASK, PPCCOM,   { BI } },
2326 { "btctr-",  XLO(19,BOT,528,0),  XLBOBB_MASK, PPCCOM,   { BI } },
2327 { "btctr+",  XLO(19,BOTP,528,0), XLBOBB_MASK, PPCCOM,   { BI } },
2328 { "btctrl",  XLO(19,BOT,528,1),  XLBOBB_MASK, PPCCOM,   { BI } },
2329 { "btctrl-", XLO(19,BOT,528,1),  XLBOBB_MASK, PPCCOM,   { BI } },
2330 { "btctrl+", XLO(19,BOTP,528,1), XLBOBB_MASK, PPCCOM,   { BI } },
2331 { "bfctr",   XLO(19,BOF,528,0),  XLBOBB_MASK, PPCCOM,   { BI } },
2332 { "bfctr-",  XLO(19,BOF,528,0),  XLBOBB_MASK, PPCCOM,   { BI } },
2333 { "bfctr+",  XLO(19,BOFP,528,0), XLBOBB_MASK, PPCCOM,   { BI } },
2334 { "bfctrl",  XLO(19,BOF,528,1),  XLBOBB_MASK, PPCCOM,   { BI } },
2335 { "bfctrl-", XLO(19,BOF,528,1),  XLBOBB_MASK, PPCCOM,   { BI } },
2336 { "bfctrl+", XLO(19,BOFP,528,1), XLBOBB_MASK, PPCCOM,   { BI } },
2337 { "bcctr",   XLLK(19,528,0),     XLYBB_MASK,  PPCCOM,   { BO, BI } },
2338 { "bcctr-",  XLYLK(19,528,0,0),  XLYBB_MASK,  PPCCOM,   { BOE, BI } },
2339 { "bcctr+",  XLYLK(19,528,1,0),  XLYBB_MASK,  PPCCOM,   { BOE, BI } },
2340 { "bcctrl",  XLLK(19,528,1),     XLYBB_MASK,  PPCCOM,   { BO, BI } },
2341 { "bcctrl-", XLYLK(19,528,0,1),  XLYBB_MASK,  PPCCOM,   { BOE, BI } },
2342 { "bcctrl+", XLYLK(19,528,1,1),  XLYBB_MASK,  PPCCOM,   { BOE, BI } },
2343 { "bcc",     XLLK(19,528,0),     XLBB_MASK,   PWRCOM,   { BO, BI } },
2344 { "bccl",    XLLK(19,528,1),     XLBB_MASK,   PWRCOM,   { BO, BI } },
2345 { "bcctre",  XLLK(19,529,0),     XLYBB_MASK,  BOOKE64,  { BO, BI } },
2346 { "bcctrel", XLLK(19,529,1),     XLYBB_MASK,  BOOKE64,  { BO, BI } },
2347
2348 { "rlwimi",  M(20,0),   M_MASK,         PPCCOM,         { RA,RS,SH,MBE,ME } },
2349 { "rlimi",   M(20,0),   M_MASK,         PWRCOM,         { RA,RS,SH,MBE,ME } },
2350
2351 { "rlwimi.", M(20,1),   M_MASK,         PPCCOM,         { RA,RS,SH,MBE,ME } },
2352 { "rlimi.",  M(20,1),   M_MASK,         PWRCOM,         { RA,RS,SH,MBE,ME } },
2353
2354 { "rotlwi",  MME(21,31,0), MMBME_MASK,  PPCCOM,         { RA, RS, SH } },
2355 { "clrlwi",  MME(21,31,0), MSHME_MASK,  PPCCOM,         { RA, RS, MB } },
2356 { "rlwinm",  M(21,0),   M_MASK,         PPCCOM,         { RA,RS,SH,MBE,ME } },
2357 { "rlinm",   M(21,0),   M_MASK,         PWRCOM,         { RA,RS,SH,MBE,ME } },
2358 { "rotlwi.", MME(21,31,1), MMBME_MASK,  PPCCOM,         { RA,RS,SH } },
2359 { "clrlwi.", MME(21,31,1), MSHME_MASK,  PPCCOM,         { RA, RS, MB } },
2360 { "rlwinm.", M(21,1),   M_MASK,         PPCCOM,         { RA,RS,SH,MBE,ME } },
2361 { "rlinm.",  M(21,1),   M_MASK,         PWRCOM,         { RA,RS,SH,MBE,ME } },
2362
2363 { "rlmi",    M(22,0),   M_MASK,         M601,           { RA,RS,RB,MBE,ME } },
2364 { "rlmi.",   M(22,1),   M_MASK,         M601,           { RA,RS,RB,MBE,ME } },
2365
2366 { "be",      B(22,0,0), B_MASK,         BOOKE64,        { LI } },
2367 { "bel",     B(22,0,1), B_MASK,         BOOKE64,        { LI } },
2368 { "bea",     B(22,1,0), B_MASK,         BOOKE64,        { LIA } },
2369 { "bela",    B(22,1,1), B_MASK,         BOOKE64,        { LIA } },
2370
2371 { "rotlw",   MME(23,31,0), MMBME_MASK,  PPCCOM,         { RA, RS, RB } },
2372 { "rlwnm",   M(23,0),   M_MASK,         PPCCOM,         { RA,RS,RB,MBE,ME } },
2373 { "rlnm",    M(23,0),   M_MASK,         PWRCOM,         { RA,RS,RB,MBE,ME } },
2374 { "rotlw.",  MME(23,31,1), MMBME_MASK,  PPCCOM,         { RA, RS, RB } },
2375 { "rlwnm.",  M(23,1),   M_MASK,         PPCCOM,         { RA,RS,RB,MBE,ME } },
2376 { "rlnm.",   M(23,1),   M_MASK,         PWRCOM,         { RA,RS,RB,MBE,ME } },
2377
2378 { "nop",     OP(24),    0xffffffff,     PPCCOM,         { 0 } },
2379 { "ori",     OP(24),    OP_MASK,        PPCCOM,         { RA, RS, UI } },
2380 { "oril",    OP(24),    OP_MASK,        PWRCOM,         { RA, RS, UI } },
2381
2382 { "oris",    OP(25),    OP_MASK,        PPCCOM,         { RA, RS, UI } },
2383 { "oriu",    OP(25),    OP_MASK,        PWRCOM,         { RA, RS, UI } },
2384
2385 { "xori",    OP(26),    OP_MASK,        PPCCOM,         { RA, RS, UI } },
2386 { "xoril",   OP(26),    OP_MASK,        PWRCOM,         { RA, RS, UI } },
2387
2388 { "xoris",   OP(27),    OP_MASK,        PPCCOM,         { RA, RS, UI } },
2389 { "xoriu",   OP(27),    OP_MASK,        PWRCOM,         { RA, RS, UI } },
2390
2391 { "andi.",   OP(28),    OP_MASK,        PPCCOM,         { RA, RS, UI } },
2392 { "andil.",  OP(28),    OP_MASK,        PWRCOM,         { RA, RS, UI } },
2393
2394 { "andis.",  OP(29),    OP_MASK,        PPCCOM,         { RA, RS, UI } },
2395 { "andiu.",  OP(29),    OP_MASK,        PWRCOM,         { RA, RS, UI } },
2396
2397 { "rotldi",  MD(30,0,0), MDMB_MASK,     PPC64,          { RA, RS, SH6 } },
2398 { "clrldi",  MD(30,0,0), MDSH_MASK,     PPC64,          { RA, RS, MB6 } },
2399 { "rldicl",  MD(30,0,0), MD_MASK,       PPC64,          { RA, RS, SH6, MB6 } },
2400 { "rotldi.", MD(30,0,1), MDMB_MASK,     PPC64,          { RA, RS, SH6 } },
2401 { "clrldi.", MD(30,0,1), MDSH_MASK,     PPC64,          { RA, RS, MB6 } },
2402 { "rldicl.", MD(30,0,1), MD_MASK,       PPC64,          { RA, RS, SH6, MB6 } },
2403
2404 { "rldicr",  MD(30,1,0), MD_MASK,       PPC64,          { RA, RS, SH6, ME6 } },
2405 { "rldicr.", MD(30,1,1), MD_MASK,       PPC64,          { RA, RS, SH6, ME6 } },
2406
2407 { "rldic",   MD(30,2,0), MD_MASK,       PPC64,          { RA, RS, SH6, MB6 } },
2408 { "rldic.",  MD(30,2,1), MD_MASK,       PPC64,          { RA, RS, SH6, MB6 } },
2409
2410 { "rldimi",  MD(30,3,0), MD_MASK,       PPC64,          { RA, RS, SH6, MB6 } },
2411 { "rldimi.", MD(30,3,1), MD_MASK,       PPC64,          { RA, RS, SH6, MB6 } },
2412
2413 { "rotld",   MDS(30,8,0), MDSMB_MASK,   PPC64,          { RA, RS, RB } },
2414 { "rldcl",   MDS(30,8,0), MDS_MASK,     PPC64,          { RA, RS, RB, MB6 } },
2415 { "rotld.",  MDS(30,8,1), MDSMB_MASK,   PPC64,          { RA, RS, RB } },
2416 { "rldcl.",  MDS(30,8,1), MDS_MASK,     PPC64,          { RA, RS, RB, MB6 } },
2417
2418 { "rldcr",   MDS(30,9,0), MDS_MASK,     PPC64,          { RA, RS, RB, ME6 } },
2419 { "rldcr.",  MDS(30,9,1), MDS_MASK,     PPC64,          { RA, RS, RB, ME6 } },
2420
2421 { "cmpw",    XCMPL(31,0,0), XCMPL_MASK, PPCCOM,         { OBF, RA, RB } },
2422 { "cmpd",    XCMPL(31,0,1), XCMPL_MASK, PPC64,          { OBF, RA, RB } },
2423 { "cmp",     X(31,0),   XCMP_MASK,      PPCONLY,        { BF, L, RA, RB } },
2424 { "cmp",     X(31,0),   XCMPL_MASK,     PWRCOM,         { BF, RA, RB } },
2425
2426 { "twlgt",   XTO(31,4,TOLGT), XTO_MASK, PPCCOM,         { RA, RB } },
2427 { "tlgt",    XTO(31,4,TOLGT), XTO_MASK, PWRCOM,         { RA, RB } },
2428 { "twllt",   XTO(31,4,TOLLT), XTO_MASK, PPCCOM,         { RA, RB } },
2429 { "tllt",    XTO(31,4,TOLLT), XTO_MASK, PWRCOM,         { RA, RB } },
2430 { "tweq",    XTO(31,4,TOEQ), XTO_MASK,  PPCCOM,         { RA, RB } },
2431 { "teq",     XTO(31,4,TOEQ), XTO_MASK,  PWRCOM,         { RA, RB } },
2432 { "twlge",   XTO(31,4,TOLGE), XTO_MASK, PPCCOM,         { RA, RB } },
2433 { "tlge",    XTO(31,4,TOLGE), XTO_MASK, PWRCOM,         { RA, RB } },
2434 { "twlnl",   XTO(31,4,TOLNL), XTO_MASK, PPCCOM,         { RA, RB } },
2435 { "tlnl",    XTO(31,4,TOLNL), XTO_MASK, PWRCOM,         { RA, RB } },
2436 { "twlle",   XTO(31,4,TOLLE), XTO_MASK, PPCCOM,         { RA, RB } },
2437 { "tlle",    XTO(31,4,TOLLE), XTO_MASK, PWRCOM,         { RA, RB } },
2438 { "twlng",   XTO(31,4,TOLNG), XTO_MASK, PPCCOM,         { RA, RB } },
2439 { "tlng",    XTO(31,4,TOLNG), XTO_MASK, PWRCOM,         { RA, RB } },
2440 { "twgt",    XTO(31,4,TOGT), XTO_MASK,  PPCCOM,         { RA, RB } },
2441 { "tgt",     XTO(31,4,TOGT), XTO_MASK,  PWRCOM,         { RA, RB } },
2442 { "twge",    XTO(31,4,TOGE), XTO_MASK,  PPCCOM,         { RA, RB } },
2443 { "tge",     XTO(31,4,TOGE), XTO_MASK,  PWRCOM,         { RA, RB } },
2444 { "twnl",    XTO(31,4,TONL), XTO_MASK,  PPCCOM,         { RA, RB } },
2445 { "tnl",     XTO(31,4,TONL), XTO_MASK,  PWRCOM,         { RA, RB } },
2446 { "twlt",    XTO(31,4,TOLT), XTO_MASK,  PPCCOM,         { RA, RB } },
2447 { "tlt",     XTO(31,4,TOLT), XTO_MASK,  PWRCOM,         { RA, RB } },
2448 { "twle",    XTO(31,4,TOLE), XTO_MASK,  PPCCOM,         { RA, RB } },
2449 { "tle",     XTO(31,4,TOLE), XTO_MASK,  PWRCOM,         { RA, RB } },
2450 { "twng",    XTO(31,4,TONG), XTO_MASK,  PPCCOM,         { RA, RB } },
2451 { "tng",     XTO(31,4,TONG), XTO_MASK,  PWRCOM,         { RA, RB } },
2452 { "twne",    XTO(31,4,TONE), XTO_MASK,  PPCCOM,         { RA, RB } },
2453 { "tne",     XTO(31,4,TONE), XTO_MASK,  PWRCOM,         { RA, RB } },
2454 { "trap",    XTO(31,4,TOU), 0xffffffff, PPCCOM,         { 0 } },
2455 { "tw",      X(31,4),   X_MASK,         PPCCOM,         { TO, RA, RB } },
2456 { "t",       X(31,4),   X_MASK,         PWRCOM,         { TO, RA, RB } },
2457
2458 { "subfc",   XO(31,8,0,0), XO_MASK,     PPCCOM,         { RT, RA, RB } },
2459 { "sf",      XO(31,8,0,0), XO_MASK,     PWRCOM,         { RT, RA, RB } },
2460 { "subc",    XO(31,8,0,0), XO_MASK,     PPC,            { RT, RB, RA } },
2461 { "subfc.",  XO(31,8,0,1), XO_MASK,     PPCCOM,         { RT, RA, RB } },
2462 { "sf.",     XO(31,8,0,1), XO_MASK,     PWRCOM,         { RT, RA, RB } },
2463 { "subc.",   XO(31,8,0,1), XO_MASK,     PPCCOM,         { RT, RB, RA } },
2464 { "subfco",  XO(31,8,1,0), XO_MASK,     PPCCOM,         { RT, RA, RB } },
2465 { "sfo",     XO(31,8,1,0), XO_MASK,     PWRCOM,         { RT, RA, RB } },
2466 { "subco",   XO(31,8,1,0), XO_MASK,     PPC,            { RT, RB, RA } },
2467 { "subfco.", XO(31,8,1,1), XO_MASK,     PPCCOM,         { RT, RA, RB } },
2468 { "sfo.",    XO(31,8,1,1), XO_MASK,     PWRCOM,         { RT, RA, RB } },
2469 { "subco.",  XO(31,8,1,1), XO_MASK,     PPC,            { RT, RB, RA } },
2470
2471 { "mulhdu",  XO(31,9,0,0), XO_MASK,     PPC64,          { RT, RA, RB } },
2472 { "mulhdu.", XO(31,9,0,1), XO_MASK,     PPC64,          { RT, RA, RB } },
2473
2474 { "addc",    XO(31,10,0,0), XO_MASK,    PPCCOM,         { RT, RA, RB } },
2475 { "a",       XO(31,10,0,0), XO_MASK,    PWRCOM,         { RT, RA, RB } },
2476 { "addc.",   XO(31,10,0,1), XO_MASK,    PPCCOM,         { RT, RA, RB } },
2477 { "a.",      XO(31,10,0,1), XO_MASK,    PWRCOM,         { RT, RA, RB } },
2478 { "addco",   XO(31,10,1,0), XO_MASK,    PPCCOM,         { RT, RA, RB } },
2479 { "ao",      XO(31,10,1,0), XO_MASK,    PWRCOM,         { RT, RA, RB } },
2480 { "addco.",  XO(31,10,1,1), XO_MASK,    PPCCOM,         { RT, RA, RB } },
2481 { "ao.",     XO(31,10,1,1), XO_MASK,    PWRCOM,         { RT, RA, RB } },
2482
2483 { "mulhwu",  XO(31,11,0,0), XO_MASK,    PPC,            { RT, RA, RB } },
2484 { "mulhwu.", XO(31,11,0,1), XO_MASK,    PPC,            { RT, RA, RB } },
2485
2486 { "mfcr",    X(31,19),  XRARB_MASK,     COM,            { RT } },
2487
2488 { "lwarx",   X(31,20),  X_MASK,         PPC,            { RT, RA, RB } },
2489
2490 { "ldx",     X(31,21),  X_MASK,         PPC64,          { RT, RA, RB } },
2491
2492 { "icbt",    X(31,22),  X_MASK,         BOOKE,          { CT, RA, RB } },
2493
2494 { "lwzx",    X(31,23),  X_MASK,         PPCCOM,         { RT, RA, RB } },
2495 { "lx",      X(31,23),  X_MASK,         PWRCOM,         { RT, RA, RB } },
2496
2497 { "slw",     XRC(31,24,0), X_MASK,      PPCCOM,         { RA, RS, RB } },
2498 { "sl",      XRC(31,24,0), X_MASK,      PWRCOM,         { RA, RS, RB } },
2499 { "slw.",    XRC(31,24,1), X_MASK,      PPCCOM,         { RA, RS, RB } },
2500 { "sl.",     XRC(31,24,1), X_MASK,      PWRCOM,         { RA, RS, RB } },
2501
2502 { "cntlzw",  XRC(31,26,0), XRB_MASK,    PPCCOM,         { RA, RS } },
2503 { "cntlz",   XRC(31,26,0), XRB_MASK,    PWRCOM,         { RA, RS } },
2504 { "cntlzw.", XRC(31,26,1), XRB_MASK,    PPCCOM,         { RA, RS } },
2505 { "cntlz.",  XRC(31,26,1), XRB_MASK,    PWRCOM,         { RA, RS } },
2506
2507 { "sld",     XRC(31,27,0), X_MASK,      PPC64,          { RA, RS, RB } },
2508 { "sld.",    XRC(31,27,1), X_MASK,      PPC64,          { RA, RS, RB } },
2509
2510 { "and",     XRC(31,28,0), X_MASK,      COM,            { RA, RS, RB } },
2511 { "and.",    XRC(31,28,1), X_MASK,      COM,            { RA, RS, RB } },
2512
2513 { "maskg",   XRC(31,29,0), X_MASK,      M601,           { RA, RS, RB } },
2514 { "maskg.",  XRC(31,29,1), X_MASK,      M601,           { RA, RS, RB } },
2515
2516 { "icbte",   X(31,30),  X_MASK,         BOOKE64,        { CT, RA, RB } },
2517
2518 { "lwzxe",   X(31,31),  X_MASK,         BOOKE64,        { RT, RA, RB } },
2519
2520 { "cmplw",   XCMPL(31,32,0), XCMPL_MASK, PPCCOM,        { OBF, RA, RB } },
2521 { "cmpld",   XCMPL(31,32,1), XCMPL_MASK, PPC64,         { OBF, RA, RB } },
2522 { "cmpl",    X(31,32),  XCMP_MASK,       PPCONLY,       { BF, L, RA, RB } },
2523 { "cmpl",    X(31,32),  XCMPL_MASK,      PWRCOM,        { BF, RA, RB } },
2524
2525 { "subf",    XO(31,40,0,0), XO_MASK,    PPC,            { RT, RA, RB } },
2526 { "sub",     XO(31,40,0,0), XO_MASK,    PPC,            { RT, RB, RA } },
2527 { "subf.",   XO(31,40,0,1), XO_MASK,    PPC,            { RT, RA, RB } },
2528 { "sub.",    XO(31,40,0,1), XO_MASK,    PPC,            { RT, RB, RA } },
2529 { "subfo",   XO(31,40,1,0), XO_MASK,    PPC,            { RT, RA, RB } },
2530 { "subo",    XO(31,40,1,0), XO_MASK,    PPC,            { RT, RB, RA } },
2531 { "subfo.",  XO(31,40,1,1), XO_MASK,    PPC,            { RT, RA, RB } },
2532 { "subo.",   XO(31,40,1,1), XO_MASK,    PPC,            { RT, RB, RA } },
2533
2534 { "ldux",    X(31,53),  X_MASK,         PPC64,          { RT, RAL, RB } },
2535
2536 { "dcbst",   X(31,54),  XRT_MASK,       PPC,            { RA, RB } },
2537
2538 { "lwzux",   X(31,55),  X_MASK,         PPCCOM,         { RT, RAL, RB } },
2539 { "lux",     X(31,55),  X_MASK,         PWRCOM,         { RT, RA, RB } },
2540
2541 { "dcbste",  X(31,62),  XRT_MASK,       BOOKE64,        { RA, RB } },
2542
2543 { "lwzuxe",  X(31,63),  X_MASK,         BOOKE64,        { RT, RAL, RB } },
2544
2545 { "cntlzd",  XRC(31,58,0), XRB_MASK,    PPC64,          { RA, RS } },
2546 { "cntlzd.", XRC(31,58,1), XRB_MASK,    PPC64,          { RA, RS } },
2547
2548 { "andc",    XRC(31,60,0), X_MASK,      COM,            { RA, RS, RB } },
2549 { "andc.",   XRC(31,60,1), X_MASK,      COM,            { RA, RS, RB } },
2550
2551 { "tdlgt",   XTO(31,68,TOLGT), XTO_MASK, PPC64,         { RA, RB } },
2552 { "tdllt",   XTO(31,68,TOLLT), XTO_MASK, PPC64,         { RA, RB } },
2553 { "tdeq",    XTO(31,68,TOEQ), XTO_MASK,  PPC64,         { RA, RB } },
2554 { "tdlge",   XTO(31,68,TOLGE), XTO_MASK, PPC64,         { RA, RB } },
2555 { "tdlnl",   XTO(31,68,TOLNL), XTO_MASK, PPC64,         { RA, RB } },
2556 { "tdlle",   XTO(31,68,TOLLE), XTO_MASK, PPC64,         { RA, RB } },
2557 { "tdlng",   XTO(31,68,TOLNG), XTO_MASK, PPC64,         { RA, RB } },
2558 { "tdgt",    XTO(31,68,TOGT), XTO_MASK,  PPC64,         { RA, RB } },
2559 { "tdge",    XTO(31,68,TOGE), XTO_MASK,  PPC64,         { RA, RB } },
2560 { "tdnl",    XTO(31,68,TONL), XTO_MASK,  PPC64,         { RA, RB } },
2561 { "tdlt",    XTO(31,68,TOLT), XTO_MASK,  PPC64,         { RA, RB } },
2562 { "tdle",    XTO(31,68,TOLE), XTO_MASK,  PPC64,         { RA, RB } },
2563 { "tdng",    XTO(31,68,TONG), XTO_MASK,  PPC64,         { RA, RB } },
2564 { "tdne",    XTO(31,68,TONE), XTO_MASK,  PPC64,         { RA, RB } },
2565 { "td",      X(31,68),  X_MASK,          PPC64,         { TO, RA, RB } },
2566
2567 { "mulhd",   XO(31,73,0,0), XO_MASK,     PPC64,         { RT, RA, RB } },
2568 { "mulhd.",  XO(31,73,0,1), XO_MASK,     PPC64,         { RT, RA, RB } },
2569
2570 { "mulhw",   XO(31,75,0,0), XO_MASK,    PPC,            { RT, RA, RB } },
2571 { "mulhw.",  XO(31,75,0,1), XO_MASK,    PPC,            { RT, RA, RB } },
2572
2573 { "mtsrd",   X(31,82),  XRB_MASK|(1<<20), PPC64,        { SR, RS } },
2574
2575 { "mfmsr",   X(31,83),  XRARB_MASK,     COM,            { RT } },
2576
2577 { "ldarx",   X(31,84),  X_MASK,         PPC64,          { RT, RA, RB } },
2578
2579 { "dcbf",    X(31,86),  XRT_MASK,       PPC,            { RA, RB } },
2580
2581 { "lbzx",    X(31,87),  X_MASK,         COM,            { RT, RA, RB } },
2582
2583 { "dcbfe",   X(31,94),  XRT_MASK,       BOOKE64,        { RA, RB } },
2584
2585 { "lbzxe",   X(31,95),  X_MASK,         BOOKE64,        { RT, RA, RB } },
2586
2587 { "neg",     XO(31,104,0,0), XORB_MASK, COM,            { RT, RA } },
2588 { "neg.",    XO(31,104,0,1), XORB_MASK, COM,            { RT, RA } },
2589 { "nego",    XO(31,104,1,0), XORB_MASK, COM,            { RT, RA } },
2590 { "nego.",   XO(31,104,1,1), XORB_MASK, COM,            { RT, RA } },
2591
2592 { "mul",     XO(31,107,0,0), XO_MASK,   M601,           { RT, RA, RB } },
2593 { "mul.",    XO(31,107,0,1), XO_MASK,   M601,           { RT, RA, RB } },
2594 { "mulo",    XO(31,107,1,0), XO_MASK,   M601,           { RT, RA, RB } },
2595 { "mulo.",   XO(31,107,1,1), XO_MASK,   M601,           { RT, RA, RB } },
2596
2597 { "mtsrdin", X(31,114), XRA_MASK,       PPC64,          { RS, RB } },
2598
2599 { "clf",     X(31,118), XTO_MASK,       POWER,          { RA, RB } },
2600
2601 { "lbzux",   X(31,119), X_MASK,         COM,            { RT, RAL, RB } },
2602
2603 { "not",     XRC(31,124,0), X_MASK,     COM,            { RA, RS, RBS } },
2604 { "nor",     XRC(31,124,0), X_MASK,     COM,            { RA, RS, RB } },
2605 { "not.",    XRC(31,124,1), X_MASK,     COM,            { RA, RS, RBS } },
2606 { "nor.",    XRC(31,124,1), X_MASK,     COM,            { RA, RS, RB } },
2607
2608 { "lwarxe",  X(31,126), X_MASK,         BOOKE64,        { RT, RA, RB } },
2609
2610 { "lbzuxe",  X(31,127), X_MASK,         BOOKE64,        { RT, RAL, RB } },
2611
2612 { "wrtee",   X(31,131), XRARB_MASK,     PPC403,         { RS } },
2613
2614 { "subfe",   XO(31,136,0,0), XO_MASK,   PPCCOM,         { RT, RA, RB } },
2615 { "sfe",     XO(31,136,0,0), XO_MASK,   PWRCOM,         { RT, RA, RB } },
2616 { "subfe.",  XO(31,136,0,1), XO_MASK,   PPCCOM,         { RT, RA, RB } },
2617 { "sfe.",    XO(31,136,0,1), XO_MASK,   PWRCOM,         { RT, RA, RB } },
2618 { "subfeo",  XO(31,136,1,0), XO_MASK,   PPCCOM,         { RT, RA, RB } },
2619 { "sfeo",    XO(31,136,1,0), XO_MASK,   PWRCOM,         { RT, RA, RB } },
2620 { "subfeo.", XO(31,136,1,1), XO_MASK,   PPCCOM,         { RT, RA, RB } },
2621 { "sfeo.",   XO(31,136,1,1), XO_MASK,   PWRCOM,         { RT, RA, RB } },
2622
2623 { "adde",    XO(31,138,0,0), XO_MASK,   PPCCOM,         { RT, RA, RB } },
2624 { "ae",      XO(31,138,0,0), XO_MASK,   PWRCOM,         { RT, RA, RB } },
2625 { "adde.",   XO(31,138,0,1), XO_MASK,   PPCCOM,         { RT, RA, RB } },
2626 { "ae.",     XO(31,138,0,1), XO_MASK,   PWRCOM,         { RT, RA, RB } },
2627 { "addeo",   XO(31,138,1,0), XO_MASK,   PPCCOM,         { RT, RA, RB } },
2628 { "aeo",     XO(31,138,1,0), XO_MASK,   PWRCOM,         { RT, RA, RB } },
2629 { "addeo.",  XO(31,138,1,1), XO_MASK,   PPCCOM,         { RT, RA, RB } },
2630 { "aeo.",    XO(31,138,1,1), XO_MASK,   PWRCOM,         { RT, RA, RB } },
2631
2632 { "mtcr",    XFXM(31,144,0xff), XFXFXM_MASK|FXM_MASK, COM,      { RS }},
2633 { "mtcrf",   X(31,144), XFXFXM_MASK,    COM,            { FXM, RS } },
2634
2635 { "mtmsr",   X(31,146), XRARB_MASK,     COM,            { RS } },
2636
2637 { "stdx",    X(31,149), X_MASK,         PPC64,          { RS, RA, RB } },
2638
2639 { "stwcx.",  XRC(31,150,1), X_MASK,     PPC,            { RS, RA, RB } },
2640
2641 { "stwx",    X(31,151), X_MASK,         PPCCOM,         { RS, RA, RB } },
2642 { "stx",     X(31,151), X_MASK,         PWRCOM,         { RS, RA, RB } },
2643
2644 { "stwcxe.", XRC(31,158,1), X_MASK,     BOOKE64,        { RS, RA, RB } },
2645
2646 { "stwxe",   X(31,159), X_MASK,         BOOKE64,        { RS, RA, RB } },
2647
2648 { "slq",     XRC(31,152,0), X_MASK,     M601,           { RA, RS, RB } },
2649 { "slq.",    XRC(31,152,1), X_MASK,     M601,           { RA, RS, RB } },
2650
2651 { "sle",     XRC(31,153,0), X_MASK,     M601,           { RA, RS, RB } },
2652 { "sle.",    XRC(31,153,1), X_MASK,     M601,           { RA, RS, RB } },
2653
2654 { "wrteei",  X(31,163), XE_MASK,        PPC403,         { E } },
2655
2656 { "mtmsrd",  X(31,178), XRARB_MASK,     PPC64,          { RS } },
2657
2658 { "stdux",   X(31,181), X_MASK,         PPC64,          { RS, RAS, RB } },
2659
2660 { "stwux",   X(31,183), X_MASK,         PPCCOM,         { RS, RAS, RB } },
2661 { "stux",    X(31,183), X_MASK,         PWRCOM,         { RS, RA, RB } },
2662
2663 { "sliq",    XRC(31,184,0), X_MASK,     M601,           { RA, RS, SH } },
2664 { "sliq.",   XRC(31,184,1), X_MASK,     M601,           { RA, RS, SH } },
2665
2666 { "stwuxe",  X(31,191), X_MASK,         BOOKE64,        { RS, RAS, RB } },
2667
2668 { "subfze",  XO(31,200,0,0), XORB_MASK, PPCCOM,         { RT, RA } },
2669 { "sfze",    XO(31,200,0,0), XORB_MASK, PWRCOM,         { RT, RA } },
2670 { "subfze.", XO(31,200,0,1), XORB_MASK, PPCCOM,         { RT, RA } },
2671 { "sfze.",   XO(31,200,0,1), XORB_MASK, PWRCOM,         { RT, RA } },
2672 { "subfzeo", XO(31,200,1,0), XORB_MASK, PPCCOM,         { RT, RA } },
2673 { "sfzeo",   XO(31,200,1,0), XORB_MASK, PWRCOM,         { RT, RA } },
2674 { "subfzeo.",XO(31,200,1,1), XORB_MASK, PPCCOM,         { RT, RA } },
2675 { "sfzeo.",  XO(31,200,1,1), XORB_MASK, PWRCOM,         { RT, RA } },
2676
2677 { "addze",   XO(31,202,0,0), XORB_MASK, PPCCOM,         { RT, RA } },
2678 { "aze",     XO(31,202,0,0), XORB_MASK, PWRCOM,         { RT, RA } },
2679 { "addze.",  XO(31,202,0,1), XORB_MASK, PPCCOM,         { RT, RA } },
2680 { "aze.",    XO(31,202,0,1), XORB_MASK, PWRCOM,         { RT, RA } },
2681 { "addzeo",  XO(31,202,1,0), XORB_MASK, PPCCOM,         { RT, RA } },
2682 { "azeo",    XO(31,202,1,0), XORB_MASK, PWRCOM,         { RT, RA } },
2683 { "addzeo.", XO(31,202,1,1), XORB_MASK, PPCCOM,         { RT, RA } },
2684 { "azeo.",   XO(31,202,1,1), XORB_MASK, PWRCOM,         { RT, RA } },
2685
2686 { "mtsr",    X(31,210), XRB_MASK|(1<<20), COM32,        { SR, RS } },
2687
2688 { "stdcx.",  XRC(31,214,1), X_MASK,     PPC64,          { RS, RA, RB } },
2689
2690 { "stbx",    X(31,215), X_MASK,         COM,            { RS, RA, RB } },
2691
2692 { "sllq",    XRC(31,216,0), X_MASK,     M601,           { RA, RS, RB } },
2693 { "sllq.",   XRC(31,216,1), X_MASK,     M601,           { RA, RS, RB } },
2694
2695 { "sleq",    XRC(31,217,0), X_MASK,     M601,           { RA, RS, RB } },
2696 { "sleq.",   XRC(31,217,1), X_MASK,     M601,           { RA, RS, RB } },
2697
2698 { "stbxe",   X(31,223), X_MASK,         BOOKE64,        { RS, RA, RB } },
2699
2700 { "subfme",  XO(31,232,0,0), XORB_MASK, PPCCOM,         { RT, RA } },
2701 { "sfme",    XO(31,232,0,0), XORB_MASK, PWRCOM,         { RT, RA } },
2702 { "subfme.", XO(31,232,0,1), XORB_MASK, PPCCOM,         { RT, RA } },
2703 { "sfme.",   XO(31,232,0,1), XORB_MASK, PWRCOM,         { RT, RA } },
2704 { "subfmeo", XO(31,232,1,0), XORB_MASK, PPCCOM,         { RT, RA } },
2705 { "sfmeo",   XO(31,232,1,0), XORB_MASK, PWRCOM,         { RT, RA } },
2706 { "subfmeo.",XO(31,232,1,1), XORB_MASK, PPCCOM,         { RT, RA } },
2707 { "sfmeo.",  XO(31,232,1,1), XORB_MASK, PWRCOM,         { RT, RA } },
2708
2709 { "mulld",   XO(31,233,0,0), XO_MASK,   PPC64,          { RT, RA, RB } },
2710 { "mulld.",  XO(31,233,0,1), XO_MASK,   PPC64,          { RT, RA, RB } },
2711 { "mulldo",  XO(31,233,1,0), XO_MASK,   PPC64,          { RT, RA, RB } },
2712 { "mulldo.", XO(31,233,1,1), XO_MASK,   PPC64,          { RT, RA, RB } },
2713
2714 { "addme",   XO(31,234,0,0), XORB_MASK, PPCCOM,         { RT, RA } },
2715 { "ame",     XO(31,234,0,0), XORB_MASK, PWRCOM,         { RT, RA } },
2716 { "addme.",  XO(31,234,0,1), XORB_MASK, PPCCOM,         { RT, RA } },
2717 { "ame.",    XO(31,234,0,1), XORB_MASK, PWRCOM,         { RT, RA } },
2718 { "addmeo",  XO(31,234,1,0), XORB_MASK, PPCCOM,         { RT, RA } },
2719 { "ameo",    XO(31,234,1,0), XORB_MASK, PWRCOM,         { RT, RA } },
2720 { "addmeo.", XO(31,234,1,1), XORB_MASK, PPCCOM,         { RT, RA } },
2721 { "ameo.",   XO(31,234,1,1), XORB_MASK, PWRCOM,         { RT, RA } },
2722
2723 { "mullw",   XO(31,235,0,0), XO_MASK,   PPCCOM,         { RT, RA, RB } },
2724 { "muls",    XO(31,235,0,0), XO_MASK,   PWRCOM,         { RT, RA, RB } },
2725 { "mullw.",  XO(31,235,0,1), XO_MASK,   PPCCOM,         { RT, RA, RB } },
2726 { "muls.",   XO(31,235,0,1), XO_MASK,   PWRCOM,         { RT, RA, RB } },
2727 { "mullwo",  XO(31,235,1,0), XO_MASK,   PPCCOM,         { RT, RA, RB } },
2728 { "mulso",   XO(31,235,1,0), XO_MASK,   PWRCOM,         { RT, RA, RB } },
2729 { "mullwo.", XO(31,235,1,1), XO_MASK,   PPCCOM,         { RT, RA, RB } },
2730 { "mulso.",  XO(31,235,1,1), XO_MASK,   PWRCOM,         { RT, RA, RB } },
2731
2732 { "mtsrin",  X(31,242), XRA_MASK,       PPC32,          { RS, RB } },
2733 { "mtsri",   X(31,242), XRA_MASK,       POWER32,        { RS, RB } },
2734
2735 { "dcbtst",  X(31,246), XRT_MASK,       PPC,            { CT, RA, RB } },
2736
2737 { "stbux",   X(31,247), X_MASK,         COM,            { RS, RAS, RB } },
2738
2739 { "slliq",   XRC(31,248,0), X_MASK,     M601,           { RA, RS, SH } },
2740 { "slliq.",  XRC(31,248,1), X_MASK,     M601,           { RA, RS, SH } },
2741
2742 { "dcbtste", X(31,253), X_MASK,         BOOKE64,        { CT, RA, RB } },
2743
2744 { "stbuxe",  X(31,255), X_MASK,         BOOKE64,        { RS, RAS, RB } },
2745
2746 { "icbt",    X(31,262), XRT_MASK,       PPC403,         { RA, RB } },
2747
2748 { "doz",     XO(31,264,0,0), XO_MASK,   M601,           { RT, RA, RB } },
2749 { "doz.",    XO(31,264,0,1), XO_MASK,   M601,           { RT, RA, RB } },
2750 { "dozo",    XO(31,264,1,0), XO_MASK,   M601,           { RT, RA, RB } },
2751 { "dozo.",   XO(31,264,1,1), XO_MASK,   M601,           { RT, RA, RB } },
2752
2753 { "add",     XO(31,266,0,0), XO_MASK,   PPCCOM,         { RT, RA, RB } },
2754 { "cax",     XO(31,266,0,0), XO_MASK,   PWRCOM,         { RT, RA, RB } },
2755 { "add.",    XO(31,266,0,1), XO_MASK,   PPCCOM,         { RT, RA, RB } },
2756 { "cax.",    XO(31,266,0,1), XO_MASK,   PWRCOM,         { RT, RA, RB } },
2757 { "addo",    XO(31,266,1,0), XO_MASK,   PPCCOM,         { RT, RA, RB } },
2758 { "caxo",    XO(31,266,1,0), XO_MASK,   PWRCOM,         { RT, RA, RB } },
2759 { "addo.",   XO(31,266,1,1), XO_MASK,   PPCCOM,         { RT, RA, RB } },
2760 { "caxo.",   XO(31,266,1,1), XO_MASK,   PWRCOM,         { RT, RA, RB } },
2761
2762 { "mfapidi", X(31,275), X_MASK,         BOOKE,          { RT, RA } },
2763
2764 { "lscbx",   XRC(31,277,0), X_MASK,     M601,           { RT, RA, RB } },
2765 { "lscbx.",  XRC(31,277,1), X_MASK,     M601,           { RT, RA, RB } },
2766
2767 { "dcbt",    X(31,278), XRT_MASK,       PPC,            { CT, RA, RB } },
2768
2769 { "lhzx",    X(31,279), X_MASK,         COM,            { RT, RA, RB } },
2770
2771 { "eqv",     XRC(31,284,0), X_MASK,     COM,            { RA, RS, RB } },
2772 { "eqv.",    XRC(31,284,1), X_MASK,     COM,            { RA, RS, RB } },
2773
2774 { "dcbte",   X(31,286), X_MASK,         BOOKE64,        { CT, RA, RB } },
2775
2776 { "lhzxe",   X(31,287), X_MASK,         BOOKE64,        { RT, RA, RB } },
2777
2778 { "tlbie",   X(31,306), XRTRA_MASK,     PPC,            { RB } },
2779 { "tlbi",    X(31,306), XRT_MASK,       POWER,          { RA, RB } },
2780
2781 { "eciwx",   X(31,310), X_MASK,         PPC,            { RT, RA, RB } },
2782
2783 { "lhzux",   X(31,311), X_MASK,         COM,            { RT, RAL, RB } },
2784
2785 { "xor",     XRC(31,316,0), X_MASK,     COM,            { RA, RS, RB } },
2786 { "xor.",    XRC(31,316,1), X_MASK,     COM,            { RA, RS, RB } },
2787
2788 { "lhzuxe",  X(31,319), X_MASK,         BOOKE64,        { RT, RAL, RB } },
2789
2790 { "mfexisr", XSPR(31,323,64), XSPR_MASK, PPC403,        { RT } },
2791 { "mfexier", XSPR(31,323,66), XSPR_MASK, PPC403,        { RT } },
2792 { "mfbr0",   XSPR(31,323,128), XSPR_MASK, PPC403,       { RT } },
2793 { "mfbr1",   XSPR(31,323,129), XSPR_MASK, PPC403,       { RT } },
2794 { "mfbr2",   XSPR(31,323,130), XSPR_MASK, PPC403,       { RT } },
2795 { "mfbr3",   XSPR(31,323,131), XSPR_MASK, PPC403,       { RT } },
2796 { "mfbr4",   XSPR(31,323,132), XSPR_MASK, PPC403,       { RT } },
2797 { "mfbr5",   XSPR(31,323,133), XSPR_MASK, PPC403,       { RT } },
2798 { "mfbr6",   XSPR(31,323,134), XSPR_MASK, PPC403,       { RT } },
2799 { "mfbr7",   XSPR(31,323,135), XSPR_MASK, PPC403,       { RT } },
2800 { "mfbear",  XSPR(31,323,144), XSPR_MASK, PPC403,       { RT } },
2801 { "mfbesr",  XSPR(31,323,145), XSPR_MASK, PPC403,       { RT } },
2802 { "mfiocr",  XSPR(31,323,160), XSPR_MASK, PPC403,       { RT } },
2803 { "mfdmacr0", XSPR(31,323,192), XSPR_MASK, PPC403,      { RT } },
2804 { "mfdmact0", XSPR(31,323,193), XSPR_MASK, PPC403,      { RT } },
2805 { "mfdmada0", XSPR(31,323,194), XSPR_MASK, PPC403,      { RT } },
2806 { "mfdmasa0", XSPR(31,323,195), XSPR_MASK, PPC403,      { RT } },
2807 { "mfdmacc0", XSPR(31,323,196), XSPR_MASK, PPC403,      { RT } },
2808 { "mfdmacr1", XSPR(31,323,200), XSPR_MASK, PPC403,      { RT } },
2809 { "mfdmact1", XSPR(31,323,201), XSPR_MASK, PPC403,      { RT } },
2810 { "mfdmada1", XSPR(31,323,202), XSPR_MASK, PPC403,      { RT } },
2811 { "mfdmasa1", XSPR(31,323,203), XSPR_MASK, PPC403,      { RT } },
2812 { "mfdmacc1", XSPR(31,323,204), XSPR_MASK, PPC403,      { RT } },
2813 { "mfdmacr2", XSPR(31,323,208), XSPR_MASK, PPC403,      { RT } },
2814 { "mfdmact2", XSPR(31,323,209), XSPR_MASK, PPC403,      { RT } },
2815 { "mfdmada2", XSPR(31,323,210), XSPR_MASK, PPC403,      { RT } },
2816 { "mfdmasa2", XSPR(31,323,211), XSPR_MASK, PPC403,      { RT } },
2817 { "mfdmacc2", XSPR(31,323,212), XSPR_MASK, PPC403,      { RT } },
2818 { "mfdmacr3", XSPR(31,323,216), XSPR_MASK, PPC403,      { RT } },
2819 { "mfdmact3", XSPR(31,323,217), XSPR_MASK, PPC403,      { RT } },
2820 { "mfdmada3", XSPR(31,323,218), XSPR_MASK, PPC403,      { RT } },
2821 { "mfdmasa3", XSPR(31,323,219), XSPR_MASK, PPC403,      { RT } },
2822 { "mfdmacc3", XSPR(31,323,220), XSPR_MASK, PPC403,      { RT } },
2823 { "mfdmasr", XSPR(31,323,224), XSPR_MASK, PPC403,       { RT } },
2824 { "mfdcr",   X(31,323), X_MASK,         PPC403,         { RT, SPR } },
2825
2826 { "div",     XO(31,331,0,0), XO_MASK,   M601,           { RT, RA, RB } },
2827 { "div.",    XO(31,331,0,1), XO_MASK,   M601,           { RT, RA, RB } },
2828 { "divo",    XO(31,331,1,0), XO_MASK,   M601,           { RT, RA, RB } },
2829 { "divo.",   XO(31,331,1,1), XO_MASK,   M601,           { RT, RA, RB } },
2830
2831 { "mfmq",     XSPR(31,339,0),   XSPR_MASK, M601,        { RT } },
2832 { "mfxer",    XSPR(31,339,1),   XSPR_MASK, COM,         { RT } },
2833 { "mfrtcu",   XSPR(31,339,4),   XSPR_MASK, COM,         { RT } },
2834 { "mfrtcl",   XSPR(31,339,5),   XSPR_MASK, COM,         { RT } },
2835 { "mfdec",    XSPR(31,339,6),   XSPR_MASK, MFDEC1,      { RT } },
2836 { "mflr",     XSPR(31,339,8),   XSPR_MASK, COM,         { RT } },
2837 { "mfctr",    XSPR(31,339,9),   XSPR_MASK, COM,         { RT } },
2838 { "mftid",    XSPR(31,339,17),  XSPR_MASK, POWER,       { RT } },
2839 { "mfdsisr",  XSPR(31,339,18),  XSPR_MASK, COM,         { RT } },
2840 { "mfdar",    XSPR(31,339,19),  XSPR_MASK, COM,         { RT } },
2841 { "mfdec",    XSPR(31,339,22),  XSPR_MASK, MFDEC2,      { RT } },
2842 { "mfsdr0",   XSPR(31,339,24),  XSPR_MASK, POWER,       { RT } },
2843 { "mfsdr1",   XSPR(31,339,25),  XSPR_MASK, COM,         { RT } },
2844 { "mfsrr0",   XSPR(31,339,26),  XSPR_MASK, COM,         { RT } },
2845 { "mfsrr1",   XSPR(31,339,27),  XSPR_MASK, COM,         { RT } },
2846 { "mfcmpa",   XSPR(31,339,144), XSPR_MASK, PPC860,      { RT } },
2847 { "mfcmpb",   XSPR(31,339,145), XSPR_MASK, PPC860,      { RT } },
2848 { "mfcmpc",   XSPR(31,339,146), XSPR_MASK, PPC860,      { RT } },
2849 { "mfcmpd",   XSPR(31,339,147), XSPR_MASK, PPC860,      { RT } },
2850 { "mficr",    XSPR(31,339,148), XSPR_MASK, PPC860,      { RT } },
2851 { "mfder",    XSPR(31,339,149), XSPR_MASK, PPC860,      { RT } },
2852 { "mfcounta", XSPR(31,339,150), XSPR_MASK, PPC860,      { RT } },
2853 { "mfcountb", XSPR(31,339,151), XSPR_MASK, PPC860,      { RT } },
2854 { "mfcmpe",   XSPR(31,339,152), XSPR_MASK, PPC860,      { RT } },
2855 { "mfcmpf",   XSPR(31,339,153), XSPR_MASK, PPC860,      { RT } },
2856 { "mfcmpg",   XSPR(31,339,154), XSPR_MASK, PPC860,      { RT } },
2857 { "mfcmph",   XSPR(31,339,155), XSPR_MASK, PPC860,      { RT } },
2858 { "mflctrl1", XSPR(31,339,156), XSPR_MASK, PPC860,      { RT } },
2859 { "mflctrl2", XSPR(31,339,157), XSPR_MASK, PPC860,      { RT } },
2860 { "mfictrl",  XSPR(31,339,158), XSPR_MASK, PPC860,      { RT } },
2861 { "mfbar",    XSPR(31,339,159), XSPR_MASK, PPC860,      { RT } },
2862 { "mfsprg4",  XSPR(31,339,260), XSPR_MASK, PPC405,      { RT } },
2863 { "mfsprg5",  XSPR(31,339,261), XSPR_MASK, PPC405,      { RT } },
2864 { "mfsprg6",  XSPR(31,339,262), XSPR_MASK, PPC405,      { RT } },
2865 { "mfsprg7",  XSPR(31,339,263), XSPR_MASK, PPC405,      { RT } },
2866 { "mfsprg",   XSPR(31,339,272), XSPRG_MASK, PPC,        { RT, SPRG } },
2867 { "mfsprg0",  XSPR(31,339,272), XSPR_MASK, PPC,         { RT } },
2868 { "mfsprg1",  XSPR(31,339,273), XSPR_MASK, PPC,         { RT } },
2869 { "mfsprg2",  XSPR(31,339,274), XSPR_MASK, PPC,         { RT } },
2870 { "mfsprg3",  XSPR(31,339,275), XSPR_MASK, PPC,         { RT } },
2871 { "mfasr",    XSPR(31,339,280), XSPR_MASK, PPC64,       { RT } },
2872 { "mfear",    XSPR(31,339,282), XSPR_MASK, PPC,         { RT } },
2873 { "mfpvr",    XSPR(31,339,287), XSPR_MASK, PPC,         { RT } },
2874 { "mfibatu",  XSPR(31,339,528), XSPRBAT_MASK, PPC,      { RT, SPRBAT } },
2875 { "mfibatl",  XSPR(31,339,529), XSPRBAT_MASK, PPC,      { RT, SPRBAT } },
2876 { "mfdbatu",  XSPR(31,339,536), XSPRBAT_MASK, PPC,      { RT, SPRBAT } },
2877 { "mfdbatl",  XSPR(31,339,537), XSPRBAT_MASK, PPC,      { RT, SPRBAT } },
2878 { "mfic_cst", XSPR(31,339,560), XSPR_MASK, PPC860,      { RT } },
2879 { "mfic_adr", XSPR(31,339,561), XSPR_MASK, PPC860,      { RT } },
2880 { "mfic_dat", XSPR(31,339,562), XSPR_MASK, PPC860,      { RT } },
2881 { "mfdc_cst", XSPR(31,339,568), XSPR_MASK, PPC860,      { RT } },
2882 { "mfdc_adr", XSPR(31,339,569), XSPR_MASK, PPC860,      { RT } },
2883 { "mfdc_dat", XSPR(31,339,570), XSPR_MASK, PPC860,      { RT } },
2884 { "mfdpdr",   XSPR(31,339,630), XSPR_MASK, PPC860,      { RT } },
2885 { "mfdpir",   XSPR(31,339,631), XSPR_MASK, PPC860,      { RT } },
2886 { "mfimmr",   XSPR(31,339,638), XSPR_MASK, PPC860,      { RT } },
2887 { "mfmi_ctr", XSPR(31,339,784), XSPR_MASK, PPC860,      { RT } },
2888 { "mfmi_ap",  XSPR(31,339,786), XSPR_MASK, PPC860,      { RT } },
2889 { "mfmi_epn", XSPR(31,339,787), XSPR_MASK, PPC860,      { RT } },
2890 { "mfmi_twc", XSPR(31,339,789), XSPR_MASK, PPC860,      { RT } },
2891 { "mfmi_rpn", XSPR(31,339,790), XSPR_MASK, PPC860,      { RT } },
2892 { "mfmd_ctr", XSPR(31,339,792), XSPR_MASK, PPC860,      { RT } },
2893 { "mfm_casid",XSPR(31,339,793), XSPR_MASK, PPC860,      { RT } },
2894 { "mfmd_ap",  XSPR(31,339,794), XSPR_MASK, PPC860,      { RT } },
2895 { "mfmd_epn", XSPR(31,339,795), XSPR_MASK, PPC860,      { RT } },
2896 { "mfmd_twb", XSPR(31,339,796), XSPR_MASK, PPC860,      { RT } },
2897 { "mfmd_twc", XSPR(31,339,797), XSPR_MASK, PPC860,      { RT } },
2898 { "mfmd_rpn", XSPR(31,339,798), XSPR_MASK, PPC860,      { RT } },
2899 { "mfm_tw",   XSPR(31,339,799), XSPR_MASK, PPC860,      { RT } },
2900 { "mfmi_dbcam",XSPR(31,339,816), XSPR_MASK, PPC860,     { RT } },
2901 { "mfmi_dbram0",XSPR(31,339,817), XSPR_MASK, PPC860,    { RT } },
2902 { "mfmi_dbram1",XSPR(31,339,818), XSPR_MASK, PPC860,    { RT } },
2903 { "mfmd_dbcam", XSPR(31,339,824), XSPR_MASK, PPC860,    { RT } },
2904 { "mfmd_dbram0",XSPR(31,339,825), XSPR_MASK, PPC860,    { RT } },
2905 { "mfmd_dbram1",XSPR(31,339,826), XSPR_MASK, PPC860,    { RT } },
2906 { "mfzpr",      XSPR(31,339,944), XSPR_MASK, PPC403,    { RT } },
2907 { "mfpid",      XSPR(31,339,945), XSPR_MASK, PPC403,    { RT } },
2908 { "mfccr0",     XSPR(31,339,947), XSPR_MASK, PPC405,    { RT } },
2909 { "mficdbdr",   XSPR(31,339,979), XSPR_MASK, PPC403,    { RT } },
2910 { "mfummcr0",   XSPR(31,339,936),  XSPR_MASK, PPC750,   { RT } },
2911 { "mfupmc1",    XSPR(31,339,937),  XSPR_MASK, PPC750,   { RT } },
2912 { "mfupmc2",    XSPR(31,339,938),  XSPR_MASK, PPC750,   { RT } },
2913 { "mfusia",     XSPR(31,339,939),  XSPR_MASK, PPC750,   { RT } },
2914 { "mfummcr1",   XSPR(31,339,940),  XSPR_MASK, PPC750,   { RT } },
2915 { "mfupmc3",    XSPR(31,339,941),  XSPR_MASK, PPC750,   { RT } },
2916 { "mfupmc4",    XSPR(31,339,942),  XSPR_MASK, PPC750,   { RT } },
2917 { "mfiac3",     XSPR(31,339,948),  XSPR_MASK, PPC405,   { RT } },
2918 { "mfiac4",     XSPR(31,339,949),  XSPR_MASK, PPC405,   { RT } },
2919 { "mfdvc1",     XSPR(31,339,950),  XSPR_MASK, PPC405,   { RT } },
2920 { "mfdvc2",     XSPR(31,339,951),  XSPR_MASK, PPC405,   { RT } },
2921 { "mfmmcr0",    XSPR(31,339,952),  XSPR_MASK, PPC750,   { RT } },
2922 { "mfpmc1",     XSPR(31,339,953),  XSPR_MASK, PPC750,   { RT } },
2923 { "mfsgr",      XSPR(31,339,953),  XSPR_MASK, PPC403,   { RT } },
2924 { "mfpmc2",     XSPR(31,339,954),  XSPR_MASK, PPC750,   { RT } },
2925 { "mfdcwr",     XSPR(31,339,954),  XSPR_MASK, PPC403,   { RT } },
2926 { "mfsia",      XSPR(31,339,955),  XSPR_MASK, PPC750,   { RT } },
2927 { "mfsler",     XSPR(31,339,955),  XSPR_MASK, PPC405,   { RT } },
2928 { "mfmmcr1",    XSPR(31,339,956),  XSPR_MASK, PPC750,   { RT } },
2929 { "mfsu0r",     XSPR(31,339,956),  XSPR_MASK, PPC405,   { RT } },
2930 { "mfpmc3",     XSPR(31,339,957),  XSPR_MASK, PPC750,   { RT } },
2931 { "mfdbcr1",    XSPR(31,339,957),  XSPR_MASK, PPC405,   { RT } },
2932 { "mfpmc4",     XSPR(31,339,958),  XSPR_MASK, PPC750,   { RT } },
2933 { "mfesr",   XSPR(31,339,980), XSPR_MASK, PPC403,       { RT } },
2934 { "mfdear",  XSPR(31,339,981), XSPR_MASK, PPC403,       { RT } },
2935 { "mfevpr",  XSPR(31,339,982), XSPR_MASK, PPC403,       { RT } },
2936 { "mfcdbcr", XSPR(31,339,983), XSPR_MASK, PPC403,       { RT } },
2937 { "mftsr",   XSPR(31,339,984), XSPR_MASK, PPC403,       { RT } },
2938 { "mftcr",   XSPR(31,339,986), XSPR_MASK, PPC403,       { RT } },
2939 { "mfpit",   XSPR(31,339,987), XSPR_MASK, PPC403,       { RT } },
2940 { "mftbhi",  XSPR(31,339,988), XSPR_MASK, PPC403,       { RT } },
2941 { "mftblo",  XSPR(31,339,989), XSPR_MASK, PPC403,       { RT } },
2942 { "mfsrr2",  XSPR(31,339,990), XSPR_MASK, PPC403,       { RT } },
2943 { "mfsrr3",  XSPR(31,339,991), XSPR_MASK, PPC403,       { RT } },
2944 { "mfdbsr",  XSPR(31,339,1008), XSPR_MASK, PPC403,      { RT } },
2945 { "mfdbcr0", XSPR(31,339,1010), XSPR_MASK, PPC405,      { RT } },
2946 { "mfiac1",  XSPR(31,339,1012), XSPR_MASK, PPC403,      { RT } },
2947 { "mfiac2",  XSPR(31,339,1013), XSPR_MASK, PPC403,      { RT } },
2948 { "mfdac1",  XSPR(31,339,1014), XSPR_MASK, PPC403,      { RT } },
2949 { "mfdac2",  XSPR(31,339,1015), XSPR_MASK, PPC403,      { RT } },
2950 { "mfdccr",  XSPR(31,339,1018), XSPR_MASK, PPC403,      { RT } },
2951 { "mficcr",  XSPR(31,339,1019), XSPR_MASK, PPC403,      { RT } },
2952 { "mfpbl1",  XSPR(31,339,1020), XSPR_MASK, PPC403,      { RT } },
2953 { "mfpbu1",  XSPR(31,339,1021), XSPR_MASK, PPC403,      { RT } },
2954 { "mfpbl2",  XSPR(31,339,1022), XSPR_MASK, PPC403,      { RT } },
2955 { "mfpbu2",  XSPR(31,339,1023), XSPR_MASK, PPC403,      { RT } },
2956 { "mfl2cr",     XSPR(31,339,1017), XSPR_MASK, PPC750,   { RT } },
2957 { "mfictc",     XSPR(31,339,1019), XSPR_MASK, PPC750,   { RT } },
2958 { "mfthrm1",    XSPR(31,339,1020), XSPR_MASK, PPC750,   { RT } },
2959 { "mfthrm2",    XSPR(31,339,1021), XSPR_MASK, PPC750,   { RT } },
2960 { "mfthrm3",    XSPR(31,339,1022), XSPR_MASK, PPC750,   { RT } },
2961 { "mfspr",   X(31,339), X_MASK,         COM,            { RT, SPR } },
2962
2963 { "lwax",    X(31,341), X_MASK,         PPC64,          { RT, RA, RB } },
2964
2965 { "lhax",    X(31,343), X_MASK,         COM,            { RT, RA, RB } },
2966
2967 { "lhaxe",   X(31,351), X_MASK,         BOOKE64,        { RT, RA, RB } },
2968
2969 { "dccci",   X(31,454), XRT_MASK,       PPC403,         { RA, RB } },
2970
2971 { "abs",     XO(31,360,0,0), XORB_MASK, M601,           { RT, RA } },
2972 { "abs.",    XO(31,360,0,1), XORB_MASK, M601,           { RT, RA } },
2973 { "abso",    XO(31,360,1,0), XORB_MASK, M601,           { RT, RA } },
2974 { "abso.",   XO(31,360,1,1), XORB_MASK, M601,           { RT, RA } },
2975
2976 { "divs",    XO(31,363,0,0), XO_MASK,   M601,           { RT, RA, RB } },
2977 { "divs.",   XO(31,363,0,1), XO_MASK,   M601,           { RT, RA, RB } },
2978 { "divso",   XO(31,363,1,0), XO_MASK,   M601,           { RT, RA, RB } },
2979 { "divso.",  XO(31,363,1,1), XO_MASK,   M601,           { RT, RA, RB } },
2980
2981 { "tlbia",   X(31,370), 0xffffffff,     PPC,            { 0 } },
2982
2983 { "mftbl",   XSPR(31,371,268), XSPR_MASK, PPC,          { RT } },
2984 { "mftbu",   XSPR(31,371,269), XSPR_MASK, PPC,          { RT } },
2985 { "mftb",    X(31,371), X_MASK,         PPC,            { RT, TBR } },
2986
2987 { "lwaux",   X(31,373), X_MASK,         PPC64,          { RT, RAL, RB } },
2988
2989 { "lhaux",   X(31,375), X_MASK,         COM,            { RT, RAL, RB } },
2990
2991 { "lhauxe",  X(31,383), X_MASK,         BOOKE64,        { RT, RAL, RB } },
2992
2993 { "subfe64", XO(31,392,0,0), XO_MASK,   BOOKE64,        { RT, RA, RB } },
2994 { "subfe64o",XO(31,392,1,0), XO_MASK,   BOOKE64,        { RT, RA, RB } },
2995
2996 { "adde64",  XO(31,394,0,0), XO_MASK,   BOOKE64,        { RT, RA, RB } },
2997 { "adde64o", XO(31,394,1,0), XO_MASK,   BOOKE64,        { RT, RA, RB } },
2998
2999 { "slbmte",  X(31,402), XRA_MASK,       PPC64,          { RS, RB } },
3000
3001 { "sthx",    X(31,407), X_MASK,         COM,            { RS, RA, RB } },
3002
3003 { "lfqx",    X(31,791), X_MASK,         POWER2,         { FRT, RA, RB } },
3004
3005 { "lfqux",   X(31,823), X_MASK,         POWER2,         { FRT, RA, RB } },
3006
3007 { "stfqx",   X(31,919), X_MASK,         POWER2,         { FRS, RA, RB } },
3008
3009 { "stfqux",  X(31,951), X_MASK,         POWER2,         { FRS, RA, RB } },
3010
3011 { "orc",     XRC(31,412,0), X_MASK,     COM,            { RA, RS, RB } },
3012 { "orc.",    XRC(31,412,1), X_MASK,     COM,            { RA, RS, RB } },
3013
3014 { "sradi",   XS(31,413,0), XS_MASK,     PPC64,          { RA, RS, SH6 } },
3015 { "sradi.",  XS(31,413,1), XS_MASK,     PPC64,          { RA, RS, SH6 } },
3016
3017 { "sthxe",   X(31,415), X_MASK,         BOOKE64,        { RS, RA, RB } },
3018
3019 { "slbie",   X(31,434), XRTRA_MASK,     PPC64,          { RB } },
3020
3021 { "ecowx",   X(31,438), X_MASK,         PPC,            { RT, RA, RB } },
3022
3023 { "sthux",   X(31,439), X_MASK,         COM,            { RS, RAS, RB } },
3024
3025 { "sthuxe",  X(31,447), X_MASK,         BOOKE64,        { RS, RAS, RB } },
3026
3027 { "mr",      XRC(31,444,0), X_MASK,     COM,            { RA, RS, RBS } },
3028 { "or",      XRC(31,444,0), X_MASK,     COM,            { RA, RS, RB } },
3029 { "mr.",     XRC(31,444,1), X_MASK,     COM,            { RA, RS, RBS } },
3030 { "or.",     XRC(31,444,1), X_MASK,     COM,            { RA, RS, RB } },
3031
3032 { "mtexisr", XSPR(31,451,64), XSPR_MASK, PPC403,        { RT } },
3033 { "mtexier", XSPR(31,451,66), XSPR_MASK, PPC403,        { RT } },
3034 { "mtbr0",   XSPR(31,451,128), XSPR_MASK, PPC403,       { RT } },
3035 { "mtbr1",   XSPR(31,451,129), XSPR_MASK, PPC403,       { RT } },
3036 { "mtbr2",   XSPR(31,451,130), XSPR_MASK, PPC403,       { RT } },
3037 { "mtbr3",   XSPR(31,451,131), XSPR_MASK, PPC403,       { RT } },
3038 { "mtbr4",   XSPR(31,451,132), XSPR_MASK, PPC403,       { RT } },
3039 { "mtbr5",   XSPR(31,451,133), XSPR_MASK, PPC403,       { RT } },
3040 { "mtbr6",   XSPR(31,451,134), XSPR_MASK, PPC403,       { RT } },
3041 { "mtbr7",   XSPR(31,451,135), XSPR_MASK, PPC403,       { RT } },
3042 { "mtbear",  XSPR(31,451,144), XSPR_MASK, PPC403,       { RT } },
3043 { "mtbesr",  XSPR(31,451,145), XSPR_MASK, PPC403,       { RT } },
3044 { "mtiocr",  XSPR(31,451,160), XSPR_MASK, PPC403,       { RT } },
3045 { "mtdmacr0", XSPR(31,451,192), XSPR_MASK, PPC403,      { RT } },
3046 { "mtdmact0", XSPR(31,451,193), XSPR_MASK, PPC403,      { RT } },
3047 { "mtdmada0", XSPR(31,451,194), XSPR_MASK, PPC403,      { RT } },
3048 { "mtdmasa0", XSPR(31,451,195), XSPR_MASK, PPC403,      { RT } },
3049 { "mtdmacc0", XSPR(31,451,196), XSPR_MASK, PPC403,      { RT } },
3050 { "mtdmacr1", XSPR(31,451,200), XSPR_MASK, PPC403,      { RT } },
3051 { "mtdmact1", XSPR(31,451,201), XSPR_MASK, PPC403,      { RT } },
3052 { "mtdmada1", XSPR(31,451,202), XSPR_MASK, PPC403,      { RT } },
3053 { "mtdmasa1", XSPR(31,451,203), XSPR_MASK, PPC403,      { RT } },
3054 { "mtdmacc1", XSPR(31,451,204), XSPR_MASK, PPC403,      { RT } },
3055 { "mtdmacr2", XSPR(31,451,208), XSPR_MASK, PPC403,      { RT } },
3056 { "mtdmact2", XSPR(31,451,209), XSPR_MASK, PPC403,      { RT } },
3057 { "mtdmada2", XSPR(31,451,210), XSPR_MASK, PPC403,      { RT } },
3058 { "mtdmasa2", XSPR(31,451,211), XSPR_MASK, PPC403,      { RT } },
3059 { "mtdmacc2", XSPR(31,451,212), XSPR_MASK, PPC403,      { RT } },
3060 { "mtdmacr3", XSPR(31,451,216), XSPR_MASK, PPC403,      { RT } },
3061 { "mtdmact3", XSPR(31,451,217), XSPR_MASK, PPC403,      { RT } },
3062 { "mtdmada3", XSPR(31,451,218), XSPR_MASK, PPC403,      { RT } },
3063 { "mtdmasa3", XSPR(31,451,219), XSPR_MASK, PPC403,      { RT } },
3064 { "mtdmacc3", XSPR(31,451,220), XSPR_MASK, PPC403,      { RT } },
3065 { "mtdmasr", XSPR(31,451,224), XSPR_MASK, PPC403,       { RT } },
3066 { "mtdcr",   X(31,451), X_MASK,         PPC403,         { SPR, RS } },
3067
3068 { "subfze64",XO(31,456,0,0), XORB_MASK, BOOKE64,        { RT, RA } },
3069 { "subfze64o",XO(31,456,1,0), XORB_MASK, BOOKE64,       { RT, RA } },
3070
3071 { "divdu",   XO(31,457,0,0), XO_MASK,   PPC64,          { RT, RA, RB } },
3072 { "divdu.",  XO(31,457,0,1), XO_MASK,   PPC64,          { RT, RA, RB } },
3073 { "divduo",  XO(31,457,1,0), XO_MASK,   PPC64,          { RT, RA, RB } },
3074 { "divduo.", XO(31,457,1,1), XO_MASK,   PPC64,          { RT, RA, RB } },
3075
3076 { "addze64", XO(31,458,0,0), XORB_MASK, BOOKE64,        { RT, RA } },
3077 { "addze64o",XO(31,458,1,0), XORB_MASK, BOOKE64,        { RT, RA } },
3078
3079 { "divwu",   XO(31,459,0,0), XO_MASK,   PPC,            { RT, RA, RB } },
3080 { "divwu.",  XO(31,459,0,1), XO_MASK,   PPC,            { RT, RA, RB } },
3081 { "divwuo",  XO(31,459,1,0), XO_MASK,   PPC,            { RT, RA, RB } },
3082 { "divwuo.", XO(31,459,1,1), XO_MASK,   PPC,            { RT, RA, RB } },
3083
3084 { "mtmq",    XSPR(31,467,0),   XSPR_MASK,    M601,      { RS } },
3085 { "mtxer",   XSPR(31,467,1),   XSPR_MASK,    COM,       { RS } },
3086 { "mtlr",    XSPR(31,467,8),   XSPR_MASK,    COM,       { RS } },
3087 { "mtctr",   XSPR(31,467,9),   XSPR_MASK,    COM,       { RS } },
3088 { "mttid",   XSPR(31,467,17),  XSPR_MASK,    POWER,     { RS } },
3089 { "mtdsisr", XSPR(31,467,18),  XSPR_MASK,    COM,       { RS } },
3090 { "mtdar",   XSPR(31,467,19),  XSPR_MASK,    COM,       { RS } },
3091 { "mtrtcu",  XSPR(31,467,20),  XSPR_MASK,    COM,       { RS } },
3092 { "mtrtcl",  XSPR(31,467,21),  XSPR_MASK,    COM,       { RS } },
3093 { "mtdec",   XSPR(31,467,22),  XSPR_MASK,    COM,       { RS } },
3094 { "mtsdr0",  XSPR(31,467,24),  XSPR_MASK,    POWER,     { RS } },
3095 { "mtsdr1",  XSPR(31,467,25),  XSPR_MASK,    COM,       { RS } },
3096 { "mtsrr0",  XSPR(31,467,26),  XSPR_MASK,    COM,       { RS } },
3097 { "mtsrr1",  XSPR(31,467,27),  XSPR_MASK,    COM,       { RS } },
3098 { "mtcmpa",   XSPR(31,467,144), XSPR_MASK, PPC860,      { RT } },
3099 { "mtcmpb",   XSPR(31,467,145), XSPR_MASK, PPC860,      { RT } },
3100 { "mtcmpc",   XSPR(31,467,146), XSPR_MASK, PPC860,      { RT } },
3101 { "mtcmpd",   XSPR(31,467,147), XSPR_MASK, PPC860,      { RT } },
3102 { "mticr",    XSPR(31,467,148), XSPR_MASK, PPC860,      { RT } },
3103 { "mtder",    XSPR(31,467,149), XSPR_MASK, PPC860,      { RT } },
3104 { "mtcounta", XSPR(31,467,150), XSPR_MASK, PPC860,      { RT } },
3105 { "mtcountb", XSPR(31,467,151), XSPR_MASK, PPC860,      { RT } },
3106 { "mtcmpe",   XSPR(31,467,152), XSPR_MASK, PPC860,      { RT } },
3107 { "mtcmpf",   XSPR(31,467,153), XSPR_MASK, PPC860,      { RT } },
3108 { "mtcmpg",   XSPR(31,467,154), XSPR_MASK, PPC860,      { RT } },
3109 { "mtcmph",   XSPR(31,467,155), XSPR_MASK, PPC860,      { RT } },
3110 { "mtlctrl1", XSPR(31,467,156), XSPR_MASK, PPC860,      { RT } },
3111 { "mtlctrl2", XSPR(31,467,157), XSPR_MASK, PPC860,      { RT } },
3112 { "mtictrl",  XSPR(31,467,158), XSPR_MASK, PPC860,      { RT } },
3113 { "mtbar",    XSPR(31,467,159), XSPR_MASK, PPC860,      { RT } },
3114 { "mtsprg",  XSPR(31,467,272), XSPRG_MASK,   PPC,       { SPRG, RS } },
3115 { "mtsprg0", XSPR(31,467,272), XSPR_MASK,    PPC,       { RT } },
3116 { "mtsprg1", XSPR(31,467,273), XSPR_MASK,    PPC,       { RT } },
3117 { "mtsprg2", XSPR(31,467,274), XSPR_MASK,    PPC,       { RT } },
3118 { "mtsprg3", XSPR(31,467,275), XSPR_MASK,    PPC,       { RT } },
3119 { "mtsprg4", XSPR(31,467,276), XSPR_MASK,    PPC405,    { RT } },
3120 { "mtsprg5", XSPR(31,467,277), XSPR_MASK,    PPC405,    { RT } },
3121 { "mtsprg6", XSPR(31,467,278), XSPR_MASK,    PPC405,    { RT } },
3122 { "mtsprg7", XSPR(31,467,279), XSPR_MASK,    PPC405,    { RT } },
3123 { "mtasr",   XSPR(31,467,280), XSPR_MASK,    PPC64,     { RS } },
3124 { "mtear",   XSPR(31,467,282), XSPR_MASK,    PPC,       { RS } },
3125 { "mttbl",   XSPR(31,467,284), XSPR_MASK,    PPC,       { RS } },
3126 { "mttbu",   XSPR(31,467,285), XSPR_MASK,    PPC,       { RS } },
3127 { "mtibatu", XSPR(31,467,528), XSPRBAT_MASK, PPC,       { SPRBAT, RS } },
3128 { "mtibatl", XSPR(31,467,529), XSPRBAT_MASK, PPC,       { SPRBAT, RS } },
3129 { "mtdbatu", XSPR(31,467,536), XSPRBAT_MASK, PPC,       { SPRBAT, RS } },
3130 { "mtdbatl", XSPR(31,467,537), XSPRBAT_MASK, PPC,       { SPRBAT, RS } },
3131 { "mtzpr",   XSPR(31,467,944), XSPR_MASK, PPC403,       { RT } },
3132 { "mtpid",   XSPR(31,467,945), XSPR_MASK, PPC403,       { RT } },
3133 { "mtccr0",  XSPR(31,467,947), XSPR_MASK, PPC405,       { RT } },
3134 { "mtiac3",  XSPR(31,467,948), XSPR_MASK, PPC405,       { RT } },
3135 { "mtiac4",  XSPR(31,467,949), XSPR_MASK, PPC405,       { RT } },
3136 { "mtdvc1",  XSPR(31,467,950), XSPR_MASK, PPC405,       { RT } },
3137 { "mtdvc2",  XSPR(31,467,951), XSPR_MASK, PPC405,       { RT } },
3138 { "mtsgr",   XSPR(31,467,953), XSPR_MASK, PPC403,       { RT } },
3139 { "mtdcwr",  XSPR(31,467,954), XSPR_MASK, PPC403,       { RT } },
3140 { "mtsler",  XSPR(31,467,955), XSPR_MASK, PPC405,       { RT } },
3141 { "mtsu0r",  XSPR(31,467,956), XSPR_MASK, PPC405,       { RT } },
3142 { "mtdbcr1", XSPR(31,467,957), XSPR_MASK, PPC405,       { RT } },
3143 { "mticdbdr",XSPR(31,467,979), XSPR_MASK, PPC403,       { RT } },
3144 { "mtesr",   XSPR(31,467,980), XSPR_MASK, PPC403,       { RT } },
3145 { "mtdear",  XSPR(31,467,981), XSPR_MASK, PPC403,       { RT } },
3146 { "mtevpr",  XSPR(31,467,982), XSPR_MASK, PPC403,       { RT } },
3147 { "mtcdbcr", XSPR(31,467,983), XSPR_MASK, PPC403,       { RT } },
3148 { "mttsr",   XSPR(31,467,984), XSPR_MASK, PPC403,       { RT } },
3149 { "mttcr",   XSPR(31,467,986), XSPR_MASK, PPC403,       { RT } },
3150 { "mtpit",   XSPR(31,467,987), XSPR_MASK, PPC403,       { RT } },
3151 { "mttbhi",  XSPR(31,467,988), XSPR_MASK, PPC403,       { RT } },
3152 { "mttblo",  XSPR(31,467,989), XSPR_MASK, PPC403,       { RT } },
3153 { "mtsrr2",  XSPR(31,467,990), XSPR_MASK, PPC403,       { RT } },
3154 { "mtsrr3",  XSPR(31,467,991), XSPR_MASK, PPC403,       { RT } },
3155 { "mtdbsr",  XSPR(31,467,1008), XSPR_MASK, PPC403,      { RT } },
3156 { "mtdbcr0", XSPR(31,467,1010), XSPR_MASK, PPC405,      { RT } },
3157 { "mtiac1",  XSPR(31,467,1012), XSPR_MASK, PPC403,      { RT } },
3158 { "mtiac2",  XSPR(31,467,1013), XSPR_MASK, PPC403,      { RT } },
3159 { "mtdac1",  XSPR(31,467,1014), XSPR_MASK, PPC403,      { RT } },
3160 { "mtdac2",  XSPR(31,467,1015), XSPR_MASK, PPC403,      { RT } },
3161 { "mtdccr",  XSPR(31,467,1018), XSPR_MASK, PPC403,      { RT } },
3162 { "mticcr",  XSPR(31,467,1019), XSPR_MASK, PPC403,      { RT } },
3163 { "mtpbl1",  XSPR(31,467,1020), XSPR_MASK, PPC403,      { RT } },
3164 { "mtpbu1",  XSPR(31,467,1021), XSPR_MASK, PPC403,      { RT } },
3165 { "mtpbl2",  XSPR(31,467,1022), XSPR_MASK, PPC403,      { RT } },
3166 { "mtpbu2",  XSPR(31,467,1023), XSPR_MASK, PPC403,      { RT } },
3167 { "mtummcr0",   XSPR(31,467,936),  XSPR_MASK, PPC750,   { RT } },
3168 { "mtupmc1",    XSPR(31,467,937),  XSPR_MASK, PPC750,   { RT } },
3169 { "mtupmc2",    XSPR(31,467,938),  XSPR_MASK, PPC750,   { RT } },
3170 { "mtusia",     XSPR(31,467,939),  XSPR_MASK, PPC750,   { RT } },
3171 { "mtummcr1",   XSPR(31,467,940),  XSPR_MASK, PPC750,   { RT } },
3172 { "mtupmc3",    XSPR(31,467,941),  XSPR_MASK, PPC750,   { RT } },
3173 { "mtupmc4",    XSPR(31,467,942),  XSPR_MASK, PPC750,   { RT } },
3174 { "mtmmcr0",    XSPR(31,467,952),  XSPR_MASK, PPC750,   { RT } },
3175 { "mtpmc1",     XSPR(31,467,953),  XSPR_MASK, PPC750,   { RT } },
3176 { "mtpmc2",     XSPR(31,467,954),  XSPR_MASK, PPC750,   { RT } },
3177 { "mtsia",      XSPR(31,467,955),  XSPR_MASK, PPC750,   { RT } },
3178 { "mtmmcr1",    XSPR(31,467,956),  XSPR_MASK, PPC750,   { RT } },
3179 { "mtpmc3",     XSPR(31,467,957),  XSPR_MASK, PPC750,   { RT } },
3180 { "mtpmc4",     XSPR(31,467,958),  XSPR_MASK, PPC750,   { RT } },
3181 { "mtl2cr",     XSPR(31,467,1017), XSPR_MASK, PPC750,   { RT } },
3182 { "mtictc",     XSPR(31,467,1019), XSPR_MASK, PPC750,   { RT } },
3183 { "mtthrm1",    XSPR(31,467,1020), XSPR_MASK, PPC750,   { RT } },
3184 { "mtthrm2",    XSPR(31,467,1021), XSPR_MASK, PPC750,   { RT } },
3185 { "mtthrm3",    XSPR(31,467,1022), XSPR_MASK, PPC750,   { RT } },
3186 { "mtspr",   X(31,467),        X_MASK,       COM,       { SPR, RS } },
3187
3188 { "dcbi",    X(31,470), XRT_MASK,       PPC,            { RA, RB } },
3189
3190 { "nand",    XRC(31,476,0), X_MASK,     COM,            { RA, RS, RB } },
3191 { "nand.",   XRC(31,476,1), X_MASK,     COM,            { RA, RS, RB } },
3192
3193 { "dcbie",   X(31,478), XRT_MASK,       BOOKE64,        { RA, RB } },
3194
3195 { "dcread",  X(31,486), X_MASK,         PPC403,         { RT, RA, RB }},
3196
3197 { "nabs",    XO(31,488,0,0), XORB_MASK, M601,           { RT, RA } },
3198 { "subfme64",XO(31,488,0,0), XORB_MASK, BOOKE64,        { RT, RA } },
3199 { "nabs.",   XO(31,488,0,1), XORB_MASK, M601,           { RT, RA } },
3200 { "nabso",   XO(31,488,1,0), XORB_MASK, M601,           { RT, RA } },
3201 { "subfme64o",XO(31,488,1,0), XORB_MASK, BOOKE64,       { RT, RA } },
3202 { "nabso.",  XO(31,488,1,1), XORB_MASK, M601,           { RT, RA } },
3203
3204 { "divd",    XO(31,489,0,0), XO_MASK,   PPC64,          { RT, RA, RB } },
3205 { "divd.",   XO(31,489,0,1), XO_MASK,   PPC64,          { RT, RA, RB } },
3206 { "divdo",   XO(31,489,1,0), XO_MASK,   PPC64,          { RT, RA, RB } },
3207 { "divdo.",  XO(31,489,1,1), XO_MASK,   PPC64,          { RT, RA, RB } },
3208
3209 { "addme64", XO(31,490,0,0), XORB_MASK, BOOKE64,        { RT, RA } },
3210 { "addme64o",XO(31,490,1,0), XORB_MASK, BOOKE64,        { RT, RA } },
3211
3212 { "divw",    XO(31,491,0,0), XO_MASK,   PPC,            { RT, RA, RB } },
3213 { "divw.",   XO(31,491,0,1), XO_MASK,   PPC,            { RT, RA, RB } },
3214 { "divwo",   XO(31,491,1,0), XO_MASK,   PPC,            { RT, RA, RB } },
3215 { "divwo.",  XO(31,491,1,1), XO_MASK,   PPC,            { RT, RA, RB } },
3216
3217 { "slbia",   X(31,498), 0xffffffff,     PPC64,          { 0 } },
3218
3219 { "cli",     X(31,502), XRB_MASK,       POWER,          { RT, RA } },
3220
3221 { "stdcxe.", XRC(31,511,1), X_MASK,     BOOKE64,        { RS, RA, RB } },
3222
3223 { "mcrxr",   X(31,512), XRARB_MASK|(3<<21), COM,        { BF } },
3224
3225 { "mcrxr64", X(31,544), XRARB_MASK|(3<<21), BOOKE,      { BF } },
3226
3227 { "clcs",    X(31,531), XRB_MASK,       M601,           { RT, RA } },
3228
3229 { "lswx",    X(31,533), X_MASK,         PPCCOM,         { RT, RA, RB } },
3230 { "lsx",     X(31,533), X_MASK,         PWRCOM,         { RT, RA, RB } },
3231
3232 { "lwbrx",   X(31,534), X_MASK,         PPCCOM,         { RT, RA, RB } },
3233 { "lbrx",    X(31,534), X_MASK,         PWRCOM,         { RT, RA, RB } },
3234
3235 { "lfsx",    X(31,535), X_MASK,         COM,            { FRT, RA, RB } },
3236
3237 { "srw",     XRC(31,536,0), X_MASK,     PPCCOM,         { RA, RS, RB } },
3238 { "sr",      XRC(31,536,0), X_MASK,     PWRCOM,         { RA, RS, RB } },
3239 { "srw.",    XRC(31,536,1), X_MASK,     PPCCOM,         { RA, RS, RB } },
3240 { "sr.",     XRC(31,536,1), X_MASK,     PWRCOM,         { RA, RS, RB } },
3241
3242 { "rrib",    XRC(31,537,0), X_MASK,     M601,           { RA, RS, RB } },
3243 { "rrib.",   XRC(31,537,1), X_MASK,     M601,           { RA, RS, RB } },
3244
3245 { "srd",     XRC(31,539,0), X_MASK,     PPC64,          { RA, RS, RB } },
3246 { "srd.",    XRC(31,539,1), X_MASK,     PPC64,          { RA, RS, RB } },
3247
3248 { "maskir",  XRC(31,541,0), X_MASK,     M601,           { RA, RS, RB } },
3249 { "maskir.", XRC(31,541,1), X_MASK,     M601,           { RA, RS, RB } },
3250
3251 { "lwbrxe",  X(31,542), X_MASK,         BOOKE64,        { RT, RA, RB } },
3252
3253 { "lfsxe",   X(31,543), X_MASK,         BOOKE64,        { FRT, RA, RB } },
3254
3255 { "tlbsync", X(31,566), 0xffffffff,     PPC,            { 0 } },
3256
3257 { "lfsux",   X(31,567), X_MASK,         COM,            { FRT, RAS, RB } },
3258
3259 { "lfsuxe",  X(31,575), X_MASK,         BOOKE64,        { FRT, RAS, RB } },
3260
3261 { "mfsr",    X(31,595), XRB_MASK|(1<<20), COM32,        { RT, SR } },
3262
3263 { "lswi",    X(31,597), X_MASK,         PPCCOM,         { RT, RA, NB } },
3264 { "lsi",     X(31,597), X_MASK,         PWRCOM,         { RT, RA, NB } },
3265
3266 { "lwsync",  XSYNC(31,598,1), 0xffffffff, PPCONLY,      { 0 } },
3267 { "ptesync", XSYNC(31,598,2), 0xffffffff, PPC64,        { 0 } },
3268 { "sync",    X(31,598), XSYNC_MASK,     PPCCOM,         { LS } },
3269 { "dcs",     X(31,598), 0xffffffff,     PWRCOM,         { 0 } },
3270
3271 { "lfdx",    X(31,599), X_MASK,         COM,            { FRT, RA, RB } },
3272
3273 { "lfdxe",   X(31,607), X_MASK,         BOOKE64,        { FRT, RA, RB } },
3274
3275 { "mfsri",   X(31,627), X_MASK,         PWRCOM,         { RT, RA, RB } },
3276
3277 { "dclst",   X(31,630), XRB_MASK,       PWRCOM,         { RS, RA } },
3278
3279 { "lfdux",   X(31,631), X_MASK,         COM,            { FRT, RAS, RB } },
3280
3281 { "lfduxe",  X(31,639), X_MASK,         BOOKE64,        { FRT, RAS, RB } },
3282
3283 { "mfsrin",  X(31,659), XRA_MASK,       PPC32,          { RT, RB } },
3284
3285 { "stswx",   X(31,661), X_MASK,         PPCCOM,         { RS, RA, RB } },
3286 { "stsx",    X(31,661), X_MASK,         PWRCOM,         { RS, RA, RB } },
3287
3288 { "stwbrx",  X(31,662), X_MASK,         PPCCOM,         { RS, RA, RB } },
3289 { "stbrx",   X(31,662), X_MASK,         PWRCOM,         { RS, RA, RB } },
3290
3291 { "stfsx",   X(31,663), X_MASK,         COM,            { FRS, RA, RB } },
3292
3293 { "srq",     XRC(31,664,0), X_MASK,     M601,           { RA, RS, RB } },
3294 { "srq.",    XRC(31,664,1), X_MASK,     M601,           { RA, RS, RB } },
3295
3296 { "sre",     XRC(31,665,0), X_MASK,     M601,           { RA, RS, RB } },
3297 { "sre.",    XRC(31,665,1), X_MASK,     M601,           { RA, RS, RB } },
3298
3299 { "stwbrxe", X(31,670), X_MASK,         BOOKE64,        { RS, RA, RB } },
3300
3301 { "stfsxe",  X(31,671), X_MASK,         BOOKE64,        { FRS, RA, RB } },
3302
3303 { "stfsux",  X(31,695), X_MASK,         COM,            { FRS, RAS, RB } },
3304
3305 { "sriq",    XRC(31,696,0), X_MASK,     M601,           { RA, RS, SH } },
3306 { "sriq.",   XRC(31,696,1), X_MASK,     M601,           { RA, RS, SH } },
3307
3308 { "stfsuxe", X(31,703), X_MASK,         BOOKE64,        { FRS, RAS, RB } },
3309
3310 { "stswi",   X(31,725), X_MASK,         PPCCOM,         { RS, RA, NB } },
3311 { "stsi",    X(31,725), X_MASK,         PWRCOM,         { RS, RA, NB } },
3312
3313 { "stfdx",   X(31,727), X_MASK,         COM,            { FRS, RA, RB } },
3314
3315 { "srlq",    XRC(31,728,0), X_MASK,     M601,           { RA, RS, RB } },
3316 { "srlq.",   XRC(31,728,1), X_MASK,     M601,           { RA, RS, RB } },
3317
3318 { "sreq",    XRC(31,729,0), X_MASK,     M601,           { RA, RS, RB } },
3319 { "sreq.",   XRC(31,729,1), X_MASK,     M601,           { RA, RS, RB } },
3320
3321 { "stfdxe",  X(31,735), X_MASK,         BOOKE64,        { FRS, RA, RB } },
3322
3323 { "dcba",    X(31,758), XRT_MASK,       PPC405,         { RA, RB } },
3324
3325 { "stfdux",  X(31,759), X_MASK,         COM,            { FRS, RAS, RB } },
3326
3327 { "srliq",   XRC(31,760,0), X_MASK,     M601,           { RA, RS, SH } },
3328 { "srliq.",  XRC(31,760,1), X_MASK,     M601,           { RA, RS, SH } },
3329
3330 { "dcbae",   X(31,766), XRT_MASK,       BOOKE64,        { RA, RB } },
3331
3332 { "stfduxe", X(31,767), X_MASK,         BOOKE64,        { FRS, RAS, RB } },
3333
3334 { "tlbivax", X(31,786), XRT_MASK,       BOOKE,          { RA, RB } },
3335 { "tlbivaxe",X(31,787), XRT_MASK,       BOOKE,          { RA, RB } },
3336
3337 { "lhbrx",   X(31,790), X_MASK,         COM,            { RT, RA, RB } },
3338
3339 { "sraw",    XRC(31,792,0), X_MASK,     PPCCOM,         { RA, RS, RB } },
3340 { "sra",     XRC(31,792,0), X_MASK,     PWRCOM,         { RA, RS, RB } },
3341 { "sraw.",   XRC(31,792,1), X_MASK,     PPCCOM,         { RA, RS, RB } },
3342 { "sra.",    XRC(31,792,1), X_MASK,     PWRCOM,         { RA, RS, RB } },
3343
3344 { "srad",    XRC(31,794,0), X_MASK,     PPC64,          { RA, RS, RB } },
3345 { "srad.",   XRC(31,794,1), X_MASK,     PPC64,          { RA, RS, RB } },
3346
3347 { "lhbrxe",  X(31,798), X_MASK,         BOOKE64,        { RT, RA, RB } },
3348
3349 { "ldxe",    X(31,799), X_MASK,         BOOKE64,        { RT, RA, RB } },
3350 { "lduxe",   X(31,831), X_MASK,         BOOKE64,        { RT, RA, RB } },
3351
3352 { "rac",     X(31,818), X_MASK,         PWRCOM,         { RT, RA, RB } },
3353
3354 { "srawi",   XRC(31,824,0), X_MASK,     PPCCOM,         { RA, RS, SH } },
3355 { "srai",    XRC(31,824,0), X_MASK,     PWRCOM,         { RA, RS, SH } },
3356 { "srawi.",  XRC(31,824,1), X_MASK,     PPCCOM,         { RA, RS, SH } },
3357 { "srai.",   XRC(31,824,1), X_MASK,     PWRCOM,         { RA, RS, SH } },
3358
3359 { "slbmfev", X(31,851), XRA_MASK,       PPC64,          { RT, RB } },
3360
3361 { "eieio",   X(31,854), 0xffffffff,     PPC,            { 0 } },
3362
3363 { "tlbsx",   XRC(31,914,0), X_MASK, PPC403,     { RT, RA, RB } },
3364 { "tlbsx.",  XRC(31,914,1), X_MASK, PPC403,     { RT, RA, RB } },
3365
3366 { "tlbsx",   XRC(31,914,0), X_MASK,      BOOKE, { RA, RB } },
3367 { "tlbsxe",  XRC(31,915,0), X_MASK,      BOOKE, { RA, RB } },
3368
3369 { "slbmfee", X(31,915), XRA_MASK,       PPC64,          { RT, RB } },
3370
3371 { "sthbrx",  X(31,918), X_MASK,         COM,            { RS, RA, RB } },
3372
3373 { "sraq",    XRC(31,920,0), X_MASK,     M601,           { RA, RS, RB } },
3374 { "sraq.",   XRC(31,920,1), X_MASK,     M601,           { RA, RS, RB } },
3375
3376 { "srea",    XRC(31,921,0), X_MASK,     M601,           { RA, RS, RB } },
3377 { "srea.",   XRC(31,921,1), X_MASK,     M601,           { RA, RS, RB } },
3378
3379 { "extsh",   XRC(31,922,0), XRB_MASK,   PPCCOM,         { RA, RS } },
3380 { "exts",    XRC(31,922,0), XRB_MASK,   PWRCOM,         { RA, RS } },
3381 { "extsh.",  XRC(31,922,1), XRB_MASK,   PPCCOM,         { RA, RS } },
3382 { "exts.",   XRC(31,922,1), XRB_MASK,   PWRCOM,         { RA, RS } },
3383
3384 { "sthbrxe", X(31,926), X_MASK,         BOOKE64,        { RS, RA, RB } },
3385
3386 { "stdxe",   X(31,927), X_MASK,         BOOKE64,        { RS, RA, RB } },
3387
3388 { "tlbre",   X(31,946), X_MASK,         BOOKE,          { RT, RA, SH } },
3389
3390 { "tlbrehi", XTLB(31,946,0), XTLB_MASK, PPC403,         { RT, RA } },
3391 { "tlbrelo", XTLB(31,946,1), XTLB_MASK, PPC403,         { RT, RA } },
3392
3393 { "sraiq",   XRC(31,952,0), X_MASK,     M601,           { RA, RS, SH } },
3394 { "sraiq.",  XRC(31,952,1), X_MASK,     M601,           { RA, RS, SH } },
3395
3396 { "extsb",   XRC(31,954,0), XRB_MASK,   PPC,            { RA, RS} },
3397 { "extsb.",  XRC(31,954,1), XRB_MASK,   PPC,            { RA, RS} },
3398
3399 { "stduxe",  X(31,959), X_MASK,         BOOKE64,        { RS, RAS, RB } },
3400
3401 { "iccci",   X(31,966), XRT_MASK,       PPC403,         { RA, RB } },
3402
3403 { "tlbld",   X(31,978), XRTRA_MASK,     PPC,            { RB } },
3404
3405 { "tlbwehi", XTLB(31,978,0), XTLB_MASK, PPC403,         { RT, RA } },
3406 { "tlbwelo", XTLB(31,978,1), XTLB_MASK, PPC403,         { RT, RA } },
3407 { "tlbwe",   X(31,978), X_MASK,         PPC403,         { RS, RA, SH } },
3408
3409 { "icbi",    X(31,982), XRT_MASK,       PPC,            { RA, RB } },
3410
3411 { "stfiwx",  X(31,983), X_MASK,         PPC,            { FRS, RA, RB } },
3412
3413 { "extsw",   XRC(31,986,0), XRB_MASK,   PPC,            { RA, RS } },
3414 { "extsw.",  XRC(31,986,1), XRB_MASK,   PPC,            { RA, RS } },
3415
3416 { "icread",  X(31,998), XRT_MASK,       PPC403,         { RA, RB } },
3417
3418 { "icbie",   X(31,990), XRT_MASK,       BOOKE64,        { RA, RB } },
3419 { "stfiwxe", X(31,991), X_MASK,         BOOKE64,        { FRS, RA, RB } },
3420
3421 { "tlbli",   X(31,1010), XRTRA_MASK,    PPC,            { RB } },
3422
3423 { "dcbz",    X(31,1014), XRT_MASK,      PPC,            { RA, RB } },
3424 { "dclz",    X(31,1014), XRT_MASK,      PPC,            { RA, RB } },
3425
3426 { "dcbze",   X(31,1022), XRT_MASK,      BOOKE64,        { RA, RB } },
3427
3428 { "lvebx",   X(31,   7), X_MASK,        PPCVEC,         { VD, RA, RB } },
3429 { "lvehx",   X(31,  39), X_MASK,        PPCVEC,         { VD, RA, RB } },
3430 { "lvewx",   X(31,  71), X_MASK,        PPCVEC,         { VD, RA, RB } },
3431 { "lvsl",    X(31,   6), X_MASK,        PPCVEC,         { VD, RA, RB } },
3432 { "lvsr",    X(31,  38), X_MASK,        PPCVEC,         { VD, RA, RB } },
3433 { "lvx",     X(31, 103), X_MASK,        PPCVEC,         { VD, RA, RB } },
3434 { "lvxl",    X(31, 359), X_MASK,        PPCVEC,         { VD, RA, RB } },
3435 { "stvebx",  X(31, 135), X_MASK,        PPCVEC,         { VS, RA, RB } },
3436 { "stvehx",  X(31, 167), X_MASK,        PPCVEC,         { VS, RA, RB } },
3437 { "stvewx",  X(31, 199), X_MASK,        PPCVEC,         { VS, RA, RB } },
3438 { "stvx",    X(31, 231), X_MASK,        PPCVEC,         { VS, RA, RB } },
3439 { "stvxl",   X(31, 487), X_MASK,        PPCVEC,         { VS, RA, RB } },
3440
3441 { "lwz",     OP(32),    OP_MASK,        PPCCOM,         { RT, D, RA } },
3442 { "l",       OP(32),    OP_MASK,        PWRCOM,         { RT, D, RA } },
3443
3444 { "lwzu",    OP(33),    OP_MASK,        PPCCOM,         { RT, D, RAL } },
3445 { "lu",      OP(33),    OP_MASK,        PWRCOM,         { RT, D, RA } },
3446
3447 { "lbz",     OP(34),    OP_MASK,        COM,            { RT, D, RA } },
3448
3449 { "lbzu",    OP(35),    OP_MASK,        COM,            { RT, D, RAL } },
3450
3451 { "stw",     OP(36),    OP_MASK,        PPCCOM,         { RS, D, RA } },
3452 { "st",      OP(36),    OP_MASK,        PWRCOM,         { RS, D, RA } },
3453
3454 { "stwu",    OP(37),    OP_MASK,        PPCCOM,         { RS, D, RAS } },
3455 { "stu",     OP(37),    OP_MASK,        PWRCOM,         { RS, D, RA } },
3456
3457 { "stb",     OP(38),    OP_MASK,        COM,            { RS, D, RA } },
3458
3459 { "stbu",    OP(39),    OP_MASK,        COM,            { RS, D, RAS } },
3460
3461 { "lhz",     OP(40),    OP_MASK,        COM,            { RT, D, RA } },
3462
3463 { "lhzu",    OP(41),    OP_MASK,        COM,            { RT, D, RAL } },
3464
3465 { "lha",     OP(42),    OP_MASK,        COM,            { RT, D, RA } },
3466
3467 { "lhau",    OP(43),    OP_MASK,        COM,            { RT, D, RAL } },
3468
3469 { "sth",     OP(44),    OP_MASK,        COM,            { RS, D, RA } },
3470
3471 { "sthu",    OP(45),    OP_MASK,        COM,            { RS, D, RAS } },
3472
3473 { "lmw",     OP(46),    OP_MASK,        PPCCOM,         { RT, D, RAM } },
3474 { "lm",      OP(46),    OP_MASK,        PWRCOM,         { RT, D, RA } },
3475
3476 { "stmw",    OP(47),    OP_MASK,        PPCCOM,         { RS, D, RA } },
3477 { "stm",     OP(47),    OP_MASK,        PWRCOM,         { RS, D, RA } },
3478
3479 { "lfs",     OP(48),    OP_MASK,        COM,            { FRT, D, RA } },
3480
3481 { "lfsu",    OP(49),    OP_MASK,        COM,            { FRT, D, RAS } },
3482
3483 { "lfd",     OP(50),    OP_MASK,        COM,            { FRT, D, RA } },
3484
3485 { "lfdu",    OP(51),    OP_MASK,        COM,            { FRT, D, RAS } },
3486
3487 { "stfs",    OP(52),    OP_MASK,        COM,            { FRS, D, RA } },
3488
3489 { "stfsu",   OP(53),    OP_MASK,        COM,            { FRS, D, RAS } },
3490
3491 { "stfd",    OP(54),    OP_MASK,        COM,            { FRS, D, RA } },
3492
3493 { "stfdu",   OP(55),    OP_MASK,        COM,            { FRS, D, RAS } },
3494
3495 { "lfq",     OP(56),    OP_MASK,        POWER2,         { FRT, D, RA } },
3496
3497 { "lfqu",    OP(57),    OP_MASK,        POWER2,         { FRT, D, RA } },
3498
3499 { "ld",      DSO(58,0), DS_MASK,        PPC64,          { RT, DS, RA } },
3500
3501 { "ldu",     DSO(58,1), DS_MASK,        PPC64,          { RT, DS, RAL } },
3502
3503 { "lwa",     DSO(58,2), DS_MASK,        PPC64,          { RT, DS, RA } },
3504
3505 { "lbze",    DEO(58,0), DE_MASK,        BOOKE64,        { RT, DE, RA } },
3506 { "lbzue",   DEO(58,1), DE_MASK,        BOOKE64,        { RT, DE, RAL } },
3507 { "lhze",    DEO(58,2), DE_MASK,        BOOKE64,        { RT, DE, RA } },
3508 { "lhzue",   DEO(58,3), DE_MASK,        BOOKE64,        { RT, DE, RAL } },
3509 { "lhae",    DEO(58,4), DE_MASK,        BOOKE64,        { RT, DE, RA } },
3510 { "lhaue",   DEO(58,5), DE_MASK,        BOOKE64,        { RT, DE, RAL } },
3511 { "lwze",    DEO(58,6), DE_MASK,        BOOKE64,        { RT, DE, RA } },
3512 { "lwzue",   DEO(58,7), DE_MASK,        BOOKE64,        { RT, DE, RAL } },
3513 { "stbe",    DEO(58,8), DE_MASK,        BOOKE64,        { RS, DE, RA } },
3514 { "stbue",   DEO(58,9), DE_MASK,        BOOKE64,        { RS, DE, RAS } },
3515 { "sthe",    DEO(58,10), DE_MASK,       BOOKE64,        { RS, DE, RA } },
3516 { "sthue",   DEO(58,11), DE_MASK,       BOOKE64,        { RS, DE, RAS } },
3517 { "stwe",    DEO(58,14), DE_MASK,       BOOKE64,        { RS, DE, RA } },
3518 { "stwue",   DEO(58,15), DE_MASK,       BOOKE64,        { RS, DE, RAS } },
3519
3520 { "fdivs",   A(59,18,0), AFRC_MASK,     PPC,            { FRT, FRA, FRB } },
3521 { "fdivs.",  A(59,18,1), AFRC_MASK,     PPC,            { FRT, FRA, FRB } },
3522
3523 { "fsubs",   A(59,20,0), AFRC_MASK,     PPC,            { FRT, FRA, FRB } },
3524 { "fsubs.",  A(59,20,1), AFRC_MASK,     PPC,            { FRT, FRA, FRB } },
3525
3526 { "fadds",   A(59,21,0), AFRC_MASK,     PPC,            { FRT, FRA, FRB } },
3527 { "fadds.",  A(59,21,1), AFRC_MASK,     PPC,            { FRT, FRA, FRB } },
3528
3529 { "fsqrts",  A(59,22,0), AFRAFRC_MASK,  PPC,            { FRT, FRB } },
3530 { "fsqrts.", A(59,22,1), AFRAFRC_MASK,  PPC,            { FRT, FRB } },
3531
3532 { "fres",    A(59,24,0), AFRAFRC_MASK,  PPC,            { FRT, FRB } },
3533 { "fres.",   A(59,24,1), AFRAFRC_MASK,  PPC,            { FRT, FRB } },
3534
3535 { "fmuls",   A(59,25,0), AFRB_MASK,     PPC,            { FRT, FRA, FRC } },
3536 { "fmuls.",  A(59,25,1), AFRB_MASK,     PPC,            { FRT, FRA, FRC } },
3537
3538 { "fmsubs",  A(59,28,0), A_MASK,        PPC,            { FRT,FRA,FRC,FRB } },
3539 { "fmsubs.", A(59,28,1), A_MASK,        PPC,            { FRT,FRA,FRC,FRB } },
3540
3541 { "fmadds",  A(59,29,0), A_MASK,        PPC,            { FRT,FRA,FRC,FRB } },
3542 { "fmadds.", A(59,29,1), A_MASK,        PPC,            { FRT,FRA,FRC,FRB } },
3543
3544 { "fnmsubs", A(59,30,0), A_MASK,        PPC,            { FRT,FRA,FRC,FRB } },
3545 { "fnmsubs.",A(59,30,1), A_MASK,        PPC,            { FRT,FRA,FRC,FRB } },
3546
3547 { "fnmadds", A(59,31,0), A_MASK,        PPC,            { FRT,FRA,FRC,FRB } },
3548 { "fnmadds.",A(59,31,1), A_MASK,        PPC,            { FRT,FRA,FRC,FRB } },
3549
3550 { "stfq",    OP(60),    OP_MASK,        POWER2,         { FRS, D, RA } },
3551
3552 { "stfqu",   OP(61),    OP_MASK,        POWER2,         { FRS, D, RA } },
3553
3554 { "lde",     DEO(62,0), DE_MASK,        BOOKE64,        { RT, DES, RA } },
3555
3556 { "std",     DSO(62,0), DS_MASK,        PPC64,          { RS, DS, RA } },
3557
3558 { "ldue",    DEO(62,1), DE_MASK,        BOOKE64,        { RT, DES, RA } },
3559
3560 { "stdu",    DSO(62,1), DS_MASK,        PPC64,          { RS, DS, RAS } },
3561
3562 { "lfse",    DEO(62,4), DE_MASK,        BOOKE64,        { FRT, DES, RA } },
3563 { "lfsue",   DEO(62,5), DE_MASK,        BOOKE64,        { FRT, DES, RAS } },
3564 { "lfde",    DEO(62,6), DE_MASK,        BOOKE64,        { FRT, DES, RA } },
3565 { "lfdue",   DEO(62,7), DE_MASK,        BOOKE64,        { FRT, DES, RAS } },
3566 { "stde",    DEO(62,8), DE_MASK,        BOOKE64,        { RS, DES, RA } },
3567 { "stdue",   DEO(62,9), DE_MASK,        BOOKE64,        { RS, DES, RAS } },
3568 { "stfse",   DEO(62,12), DE_MASK,       BOOKE64,        { FRS, DES, RA } },
3569 { "stfsue",  DEO(62,13), DE_MASK,       BOOKE64,        { FRS, DES, RAS } },
3570 { "stfde",   DEO(62,14), DE_MASK,       BOOKE64,        { FRS, DES, RA } },
3571 { "stfdue",  DEO(62,15), DE_MASK,       BOOKE64,        { FRS, DES, RAS } },
3572
3573 { "fcmpu",   X(63,0),   X_MASK|(3<<21), COM,            { BF, FRA, FRB } },
3574
3575 { "frsp",    XRC(63,12,0), XRA_MASK,    COM,            { FRT, FRB } },
3576 { "frsp.",   XRC(63,12,1), XRA_MASK,    COM,            { FRT, FRB } },
3577
3578 { "fctiw",   XRC(63,14,0), XRA_MASK,    PPCCOM,         { FRT, FRB } },
3579 { "fcir",    XRC(63,14,0), XRA_MASK,    POWER2,         { FRT, FRB } },
3580 { "fctiw.",  XRC(63,14,1), XRA_MASK,    PPCCOM,         { FRT, FRB } },
3581 { "fcir.",   XRC(63,14,1), XRA_MASK,    POWER2,         { FRT, FRB } },
3582
3583 { "fctiwz",  XRC(63,15,0), XRA_MASK,    PPCCOM,         { FRT, FRB } },
3584 { "fcirz",   XRC(63,15,0), XRA_MASK,    POWER2,         { FRT, FRB } },
3585 { "fctiwz.", XRC(63,15,1), XRA_MASK,    PPCCOM,         { FRT, FRB } },
3586 { "fcirz.",  XRC(63,15,1), XRA_MASK,    POWER2,         { FRT, FRB } },
3587
3588 { "fdiv",    A(63,18,0), AFRC_MASK,     PPCCOM,         { FRT, FRA, FRB } },
3589 { "fd",      A(63,18,0), AFRC_MASK,     PWRCOM,         { FRT, FRA, FRB } },
3590 { "fdiv.",   A(63,18,1), AFRC_MASK,     PPCCOM,         { FRT, FRA, FRB } },
3591 { "fd.",     A(63,18,1), AFRC_MASK,     PWRCOM,         { FRT, FRA, FRB } },
3592
3593 { "fsub",    A(63,20,0), AFRC_MASK,     PPCCOM,         { FRT, FRA, FRB } },
3594 { "fs",      A(63,20,0), AFRC_MASK,     PWRCOM,         { FRT, FRA, FRB } },
3595 { "fsub.",   A(63,20,1), AFRC_MASK,     PPCCOM,         { FRT, FRA, FRB } },
3596 { "fs.",     A(63,20,1), AFRC_MASK,     PWRCOM,         { FRT, FRA, FRB } },
3597
3598 { "fadd",    A(63,21,0), AFRC_MASK,     PPCCOM,         { FRT, FRA, FRB } },
3599 { "fa",      A(63,21,0), AFRC_MASK,     PWRCOM,         { FRT, FRA, FRB } },
3600 { "fadd.",   A(63,21,1), AFRC_MASK,     PPCCOM,         { FRT, FRA, FRB } },
3601 { "fa.",     A(63,21,1), AFRC_MASK,     PWRCOM,         { FRT, FRA, FRB } },
3602
3603 { "fsqrt",   A(63,22,0), AFRAFRC_MASK,  PPCPWR2,        { FRT, FRB } },
3604 { "fsqrt.",  A(63,22,1), AFRAFRC_MASK,  PPCPWR2,        { FRT, FRB } },
3605
3606 { "fsel",    A(63,23,0), A_MASK,        PPC,            { FRT,FRA,FRC,FRB } },
3607 { "fsel.",   A(63,23,1), A_MASK,        PPC,            { FRT,FRA,FRC,FRB } },
3608
3609 { "fmul",    A(63,25,0), AFRB_MASK,     PPCCOM,         { FRT, FRA, FRC } },
3610 { "fm",      A(63,25,0), AFRB_MASK,     PWRCOM,         { FRT, FRA, FRC } },
3611 { "fmul.",   A(63,25,1), AFRB_MASK,     PPCCOM,         { FRT, FRA, FRC } },
3612 { "fm.",     A(63,25,1), AFRB_MASK,     PWRCOM,         { FRT, FRA, FRC } },
3613
3614 { "frsqrte", A(63,26,0), AFRAFRC_MASK,  PPC,            { FRT, FRB } },
3615 { "frsqrte.",A(63,26,1), AFRAFRC_MASK,  PPC,            { FRT, FRB } },
3616
3617 { "fmsub",   A(63,28,0), A_MASK,        PPCCOM,         { FRT,FRA,FRC,FRB } },
3618 { "fms",     A(63,28,0), A_MASK,        PWRCOM,         { FRT,FRA,FRC,FRB } },
3619 { "fmsub.",  A(63,28,1), A_MASK,        PPCCOM,         { FRT,FRA,FRC,FRB } },
3620 { "fms.",    A(63,28,1), A_MASK,        PWRCOM,         { FRT,FRA,FRC,FRB } },
3621
3622 { "fmadd",   A(63,29,0), A_MASK,        PPCCOM,         { FRT,FRA,FRC,FRB } },
3623 { "fma",     A(63,29,0), A_MASK,        PWRCOM,         { FRT,FRA,FRC,FRB } },
3624 { "fmadd.",  A(63,29,1), A_MASK,        PPCCOM,         { FRT,FRA,FRC,FRB } },
3625 { "fma.",    A(63,29,1), A_MASK,        PWRCOM,         { FRT,FRA,FRC,FRB } },
3626
3627 { "fnmsub",  A(63,30,0), A_MASK,        PPCCOM,         { FRT,FRA,FRC,FRB } },
3628 { "fnms",    A(63,30,0), A_MASK,        PWRCOM,         { FRT,FRA,FRC,FRB } },
3629 { "fnmsub.", A(63,30,1), A_MASK,        PPCCOM,         { FRT,FRA,FRC,FRB } },
3630 { "fnms.",   A(63,30,1), A_MASK,        PWRCOM,         { FRT,FRA,FRC,FRB } },
3631
3632 { "fnmadd",  A(63,31,0), A_MASK,        PPCCOM,         { FRT,FRA,FRC,FRB } },
3633 { "fnma",    A(63,31,0), A_MASK,        PWRCOM,         { FRT,FRA,FRC,FRB } },
3634 { "fnmadd.", A(63,31,1), A_MASK,        PPCCOM,         { FRT,FRA,FRC,FRB } },
3635 { "fnma.",   A(63,31,1), A_MASK,        PWRCOM,         { FRT,FRA,FRC,FRB } },
3636
3637 { "fcmpo",   X(63,32),  X_MASK|(3<<21), COM,            { BF, FRA, FRB } },
3638
3639 { "mtfsb1",  XRC(63,38,0), XRARB_MASK,  COM,            { BT } },
3640 { "mtfsb1.", XRC(63,38,1), XRARB_MASK,  COM,            { BT } },
3641
3642 { "fneg",    XRC(63,40,0), XRA_MASK,    COM,            { FRT, FRB } },
3643 { "fneg.",   XRC(63,40,1), XRA_MASK,    COM,            { FRT, FRB } },
3644
3645 { "mcrfs",   X(63,64),  XRB_MASK|(3<<21)|(3<<16), COM,  { BF, BFA } },
3646
3647 { "mtfsb0",  XRC(63,70,0), XRARB_MASK,  COM,            { BT } },
3648 { "mtfsb0.", XRC(63,70,1), XRARB_MASK,  COM,            { BT } },
3649
3650 { "fmr",     XRC(63,72,0), XRA_MASK,    COM,            { FRT, FRB } },
3651 { "fmr.",    XRC(63,72,1), XRA_MASK,    COM,            { FRT, FRB } },
3652
3653 { "mtfsfi",  XRC(63,134,0), XRA_MASK|(3<<21)|(1<<11), COM, { BF, U } },
3654 { "mtfsfi.", XRC(63,134,1), XRA_MASK|(3<<21)|(1<<11), COM, { BF, U } },
3655
3656 { "fnabs",   XRC(63,136,0), XRA_MASK,   COM,            { FRT, FRB } },
3657 { "fnabs.",  XRC(63,136,1), XRA_MASK,   COM,            { FRT, FRB } },
3658
3659 { "fabs",    XRC(63,264,0), XRA_MASK,   COM,            { FRT, FRB } },
3660 { "fabs.",   XRC(63,264,1), XRA_MASK,   COM,            { FRT, FRB } },
3661
3662 { "mffs",    XRC(63,583,0), XRARB_MASK, COM,            { FRT } },
3663 { "mffs.",   XRC(63,583,1), XRARB_MASK, COM,            { FRT } },
3664
3665 { "mtfsf",   XFL(63,711,0), XFL_MASK,   COM,            { FLM, FRB } },
3666 { "mtfsf.",  XFL(63,711,1), XFL_MASK,   COM,            { FLM, FRB } },
3667
3668 { "fctid",   XRC(63,814,0), XRA_MASK,   PPC64,          { FRT, FRB } },
3669 { "fctid.",  XRC(63,814,1), XRA_MASK,   PPC64,          { FRT, FRB } },
3670
3671 { "fctidz",  XRC(63,815,0), XRA_MASK,   PPC64,          { FRT, FRB } },
3672 { "fctidz.", XRC(63,815,1), XRA_MASK,   PPC64,          { FRT, FRB } },
3673
3674 { "fcfid",   XRC(63,846,0), XRA_MASK,   PPC64,          { FRT, FRB } },
3675 { "fcfid.",  XRC(63,846,1), XRA_MASK,   PPC64,          { FRT, FRB } },
3676
3677 };
3678
3679 const int powerpc_num_opcodes =
3680   sizeof (powerpc_opcodes) / sizeof (powerpc_opcodes[0]);
3681 \f
3682 /* The macro table.  This is only used by the assembler.  */
3683
3684 /* The expressions of the form (-x ! 31) & (x | 31) have the value 0
3685    when x=0; 32-x when x is between 1 and 31; are negative if x is
3686    negative; and are 32 or more otherwise.  This is what you want
3687    when, for instance, you are emulating a right shift by a
3688    rotate-left-and-mask, because the underlying instructions support
3689    shifts of size 0 but not shifts of size 32.  By comparison, when
3690    extracting x bits from some word you want to use just 32-x, because
3691    the underlying instructions don't support extracting 0 bits but do
3692    support extracting the whole word (32 bits in this case).  */
3693
3694 const struct powerpc_macro powerpc_macros[] = {
3695 { "extldi",  4,   PPC64,        "rldicr %0,%1,%3,(%2)-1" },
3696 { "extldi.", 4,   PPC64,        "rldicr. %0,%1,%3,(%2)-1" },
3697 { "extrdi",  4,   PPC64,        "rldicl %0,%1,(%2)+(%3),64-(%2)" },
3698 { "extrdi.", 4,   PPC64,        "rldicl. %0,%1,(%2)+(%3),64-(%2)" },
3699 { "insrdi",  4,   PPC64,        "rldimi %0,%1,64-((%2)+(%3)),%3" },
3700 { "insrdi.", 4,   PPC64,        "rldimi. %0,%1,64-((%2)+(%3)),%3" },
3701 { "rotrdi",  3,   PPC64,        "rldicl %0,%1,(-(%2)!63)&((%2)|63),0" },
3702 { "rotrdi.", 3,   PPC64,        "rldicl. %0,%1,(-(%2)!63)&((%2)|63),0" },
3703 { "sldi",    3,   PPC64,        "rldicr %0,%1,%2,63-(%2)" },
3704 { "sldi.",   3,   PPC64,        "rldicr. %0,%1,%2,63-(%2)" },
3705 { "srdi",    3,   PPC64,        "rldicl %0,%1,(-(%2)!63)&((%2)|63),%2" },
3706 { "srdi.",   3,   PPC64,        "rldicl. %0,%1,(-(%2)!63)&((%2)|63),%2" },
3707 { "clrrdi",  3,   PPC64,        "rldicr %0,%1,0,63-(%2)" },
3708 { "clrrdi.", 3,   PPC64,        "rldicr. %0,%1,0,63-(%2)" },
3709 { "clrlsldi",4,   PPC64,        "rldic %0,%1,%3,(%2)-(%3)" },
3710 { "clrlsldi.",4,  PPC64,        "rldic. %0,%1,%3,(%2)-(%3)" },
3711
3712 { "extlwi",  4,   PPCCOM,       "rlwinm %0,%1,%3,0,(%2)-1" },
3713 { "extlwi.", 4,   PPCCOM,       "rlwinm. %0,%1,%3,0,(%2)-1" },
3714 { "extrwi",  4,   PPCCOM,       "rlwinm %0,%1,(%2)+(%3),32-(%2),31" },
3715 { "extrwi.", 4,   PPCCOM,       "rlwinm. %0,%1,(%2)+(%3),32-(%2),31" },
3716 { "inslwi",  4,   PPCCOM,       "rlwimi %0,%1,(-(%3)!31)&((%3)|31),%3,(%2)+(%3)-1" },
3717 { "inslwi.", 4,   PPCCOM,       "rlwimi. %0,%1,(-(%3)!31)&((%3)|31),%3,(%2)+(%3)-1"},
3718 { "insrwi",  4,   PPCCOM,       "rlwimi %0,%1,32-((%2)+(%3)),%3,(%2)+(%3)-1" },
3719 { "insrwi.", 4,   PPCCOM,       "rlwimi. %0,%1,32-((%2)+(%3)),%3,(%2)+(%3)-1"},
3720 { "rotrwi",  3,   PPCCOM,       "rlwinm %0,%1,(-(%2)!31)&((%2)|31),0,31" },
3721 { "rotrwi.", 3,   PPCCOM,       "rlwinm. %0,%1,(-(%2)!31)&((%2)|31),0,31" },
3722 { "slwi",    3,   PPCCOM,       "rlwinm %0,%1,%2,0,31-(%2)" },
3723 { "sli",     3,   PWRCOM,       "rlinm %0,%1,%2,0,31-(%2)" },
3724 { "slwi.",   3,   PPCCOM,       "rlwinm. %0,%1,%2,0,31-(%2)" },
3725 { "sli.",    3,   PWRCOM,       "rlinm. %0,%1,%2,0,31-(%2)" },
3726 { "srwi",    3,   PPCCOM,       "rlwinm %0,%1,(-(%2)!31)&((%2)|31),%2,31" },
3727 { "sri",     3,   PWRCOM,       "rlinm %0,%1,(-(%2)!31)&((%2)|31),%2,31" },
3728 { "srwi.",   3,   PPCCOM,       "rlwinm. %0,%1,(-(%2)!31)&((%2)|31),%2,31" },
3729 { "sri.",    3,   PWRCOM,       "rlinm. %0,%1,(-(%2)!31)&((%2)|31),%2,31" },
3730 { "clrrwi",  3,   PPCCOM,       "rlwinm %0,%1,0,0,31-(%2)" },
3731 { "clrrwi.", 3,   PPCCOM,       "rlwinm. %0,%1,0,0,31-(%2)" },
3732 { "clrlslwi",4,   PPCCOM,       "rlwinm %0,%1,%3,(%2)-(%3),31-(%3)" },
3733 { "clrlslwi.",4,  PPCCOM,       "rlwinm. %0,%1,%3,(%2)-(%3),31-(%3)" },
3734
3735 };
3736
3737 const int powerpc_num_macros =
3738   sizeof (powerpc_macros) / sizeof (powerpc_macros[0]);