1 /* ppc-opc.c -- PowerPC opcode list
2 Copyright (C) 1994-2014 Free Software Foundation, Inc.
3 Written by Ian Lance Taylor, Cygnus Support
5 This file is part of the GNU opcodes library.
7 This library is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3, or (at your option)
12 It is distributed in the hope that it will be useful, but WITHOUT
13 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
14 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
15 License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this file; see the file COPYING. If not, write to the
19 Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston,
20 MA 02110-1301, USA. */
24 #include "opcode/ppc.h"
27 /* This file holds the PowerPC opcode table. The opcode table
28 includes almost all of the extended instruction mnemonics. This
29 permits the disassembler to use them, and simplifies the assembler
30 logic, at the cost of increasing the table size. The table is
31 strictly constant data, so the compiler should be able to put it in
34 This file also holds the operand table. All knowledge about
35 inserting operands into instructions and vice-versa is kept in this
38 /* Local insertion and extraction functions. */
40 static unsigned long insert_arx (unsigned long, long, ppc_cpu_t
, const char **);
41 static long extract_arx (unsigned long, ppc_cpu_t
, int *);
42 static unsigned long insert_ary (unsigned long, long, ppc_cpu_t
, const char **);
43 static long extract_ary (unsigned long, ppc_cpu_t
, int *);
44 static unsigned long insert_bat (unsigned long, long, ppc_cpu_t
, const char **);
45 static long extract_bat (unsigned long, ppc_cpu_t
, int *);
46 static unsigned long insert_bba (unsigned long, long, ppc_cpu_t
, const char **);
47 static long extract_bba (unsigned long, ppc_cpu_t
, int *);
48 static unsigned long insert_bdm (unsigned long, long, ppc_cpu_t
, const char **);
49 static long extract_bdm (unsigned long, ppc_cpu_t
, int *);
50 static unsigned long insert_bdp (unsigned long, long, ppc_cpu_t
, const char **);
51 static long extract_bdp (unsigned long, ppc_cpu_t
, int *);
52 static unsigned long insert_bo (unsigned long, long, ppc_cpu_t
, const char **);
53 static long extract_bo (unsigned long, ppc_cpu_t
, int *);
54 static unsigned long insert_boe (unsigned long, long, ppc_cpu_t
, const char **);
55 static long extract_boe (unsigned long, ppc_cpu_t
, int *);
56 static unsigned long insert_fxm (unsigned long, long, ppc_cpu_t
, const char **);
57 static long extract_fxm (unsigned long, ppc_cpu_t
, int *);
58 static unsigned long insert_li20 (unsigned long, long, ppc_cpu_t
, const char **);
59 static long extract_li20 (unsigned long, ppc_cpu_t
, int *);
60 static unsigned long insert_ls (unsigned long, long, ppc_cpu_t
, const char **);
61 static unsigned long insert_mbe (unsigned long, long, ppc_cpu_t
, const char **);
62 static long extract_mbe (unsigned long, ppc_cpu_t
, int *);
63 static unsigned long insert_mb6 (unsigned long, long, ppc_cpu_t
, const char **);
64 static long extract_mb6 (unsigned long, ppc_cpu_t
, int *);
65 static long extract_nb (unsigned long, ppc_cpu_t
, int *);
66 static unsigned long insert_nbi (unsigned long, long, ppc_cpu_t
, const char **);
67 static unsigned long insert_nsi (unsigned long, long, ppc_cpu_t
, const char **);
68 static long extract_nsi (unsigned long, ppc_cpu_t
, int *);
69 static unsigned long insert_oimm (unsigned long, long, ppc_cpu_t
, const char **);
70 static long extract_oimm (unsigned long, ppc_cpu_t
, int *);
71 static unsigned long insert_ral (unsigned long, long, ppc_cpu_t
, const char **);
72 static unsigned long insert_ram (unsigned long, long, ppc_cpu_t
, const char **);
73 static unsigned long insert_raq (unsigned long, long, ppc_cpu_t
, const char **);
74 static unsigned long insert_ras (unsigned long, long, ppc_cpu_t
, const char **);
75 static unsigned long insert_rbs (unsigned long, long, ppc_cpu_t
, const char **);
76 static long extract_rbs (unsigned long, ppc_cpu_t
, int *);
77 static unsigned long insert_rbx (unsigned long, long, ppc_cpu_t
, const char **);
78 static unsigned long insert_rx (unsigned long, long, ppc_cpu_t
, const char **);
79 static long extract_rx (unsigned long, ppc_cpu_t
, int *);
80 static unsigned long insert_ry (unsigned long, long, ppc_cpu_t
, const char **);
81 static long extract_ry (unsigned long, ppc_cpu_t
, int *);
82 static unsigned long insert_sh6 (unsigned long, long, ppc_cpu_t
, const char **);
83 static long extract_sh6 (unsigned long, ppc_cpu_t
, int *);
84 static unsigned long insert_sci8 (unsigned long, long, ppc_cpu_t
, const char **);
85 static long extract_sci8 (unsigned long, ppc_cpu_t
, int *);
86 static unsigned long insert_sci8n (unsigned long, long, ppc_cpu_t
, const char **);
87 static long extract_sci8n (unsigned long, ppc_cpu_t
, int *);
88 static unsigned long insert_sd4h (unsigned long, long, ppc_cpu_t
, const char **);
89 static long extract_sd4h (unsigned long, ppc_cpu_t
, int *);
90 static unsigned long insert_sd4w (unsigned long, long, ppc_cpu_t
, const char **);
91 static long extract_sd4w (unsigned long, ppc_cpu_t
, int *);
92 static unsigned long insert_spr (unsigned long, long, ppc_cpu_t
, const char **);
93 static long extract_spr (unsigned long, ppc_cpu_t
, int *);
94 static unsigned long insert_sprg (unsigned long, long, ppc_cpu_t
, const char **);
95 static long extract_sprg (unsigned long, ppc_cpu_t
, int *);
96 static unsigned long insert_tbr (unsigned long, long, ppc_cpu_t
, const char **);
97 static long extract_tbr (unsigned long, ppc_cpu_t
, int *);
98 static unsigned long insert_xt6 (unsigned long, long, ppc_cpu_t
, const char **);
99 static long extract_xt6 (unsigned long, ppc_cpu_t
, int *);
100 static unsigned long insert_xa6 (unsigned long, long, ppc_cpu_t
, const char **);
101 static long extract_xa6 (unsigned long, ppc_cpu_t
, int *);
102 static unsigned long insert_xb6 (unsigned long, long, ppc_cpu_t
, const char **);
103 static long extract_xb6 (unsigned long, ppc_cpu_t
, int *);
104 static unsigned long insert_xb6s (unsigned long, long, ppc_cpu_t
, const char **);
105 static long extract_xb6s (unsigned long, ppc_cpu_t
, int *);
106 static unsigned long insert_xc6 (unsigned long, long, ppc_cpu_t
, const char **);
107 static long extract_xc6 (unsigned long, ppc_cpu_t
, int *);
108 static unsigned long insert_dm (unsigned long, long, ppc_cpu_t
, const char **);
109 static long extract_dm (unsigned long, ppc_cpu_t
, int *);
110 static unsigned long insert_vlesi (unsigned long, long, ppc_cpu_t
, const char **);
111 static long extract_vlesi (unsigned long, ppc_cpu_t
, int *);
112 static unsigned long insert_vlensi (unsigned long, long, ppc_cpu_t
, const char **);
113 static long extract_vlensi (unsigned long, ppc_cpu_t
, int *);
114 static unsigned long insert_vleui (unsigned long, long, ppc_cpu_t
, const char **);
115 static long extract_vleui (unsigned long, ppc_cpu_t
, int *);
116 static unsigned long insert_vleil (unsigned long, long, ppc_cpu_t
, const char **);
117 static long extract_vleil (unsigned long, ppc_cpu_t
, int *);
119 /* The operands table.
121 The fields are bitm, shift, insert, extract, flags.
123 We used to put parens around the various additions, like the one
124 for BA just below. However, that caused trouble with feeble
125 compilers with a limit on depth of a parenthesized expression, like
126 (reportedly) the compiler in Microsoft Developer Studio 5. So we
127 omit the parens, since the macros are never used in a context where
128 the addition will be ambiguous. */
130 const struct powerpc_operand powerpc_operands
[] =
132 /* The zero index is used to indicate the end of the list of
135 { 0, 0, NULL
, NULL
, 0 },
137 /* The BA field in an XL form instruction. */
138 #define BA UNUSED + 1
139 /* The BI field in a B form or XL form instruction. */
141 #define BI_MASK (0x1f << 16)
142 { 0x1f, 16, NULL
, NULL
, PPC_OPERAND_CR_BIT
},
144 /* The BA field in an XL form instruction when it must be the same
145 as the BT field in the same instruction. */
147 { 0x1f, 16, insert_bat
, extract_bat
, PPC_OPERAND_FAKE
},
149 /* The BB field in an XL form instruction. */
151 #define BB_MASK (0x1f << 11)
152 { 0x1f, 11, NULL
, NULL
, PPC_OPERAND_CR_BIT
},
154 /* The BB field in an XL form instruction when it must be the same
155 as the BA field in the same instruction. */
157 /* The VB field in a VX form instruction when it must be the same
158 as the VA field in the same instruction. */
160 { 0x1f, 11, insert_bba
, extract_bba
, PPC_OPERAND_FAKE
},
162 /* The BD field in a B form instruction. The lower two bits are
165 { 0xfffc, 0, NULL
, NULL
, PPC_OPERAND_RELATIVE
| PPC_OPERAND_SIGNED
},
167 /* The BD field in a B form instruction when absolute addressing is
170 { 0xfffc, 0, NULL
, NULL
, PPC_OPERAND_ABSOLUTE
| PPC_OPERAND_SIGNED
},
172 /* The BD field in a B form instruction when the - modifier is used.
173 This sets the y bit of the BO field appropriately. */
175 { 0xfffc, 0, insert_bdm
, extract_bdm
,
176 PPC_OPERAND_RELATIVE
| PPC_OPERAND_SIGNED
},
178 /* The BD field in a B form instruction when the - modifier is used
179 and absolute address is used. */
181 { 0xfffc, 0, insert_bdm
, extract_bdm
,
182 PPC_OPERAND_ABSOLUTE
| PPC_OPERAND_SIGNED
},
184 /* The BD field in a B form instruction when the + modifier is used.
185 This sets the y bit of the BO field appropriately. */
187 { 0xfffc, 0, insert_bdp
, extract_bdp
,
188 PPC_OPERAND_RELATIVE
| PPC_OPERAND_SIGNED
},
190 /* The BD field in a B form instruction when the + modifier is used
191 and absolute addressing is used. */
193 { 0xfffc, 0, insert_bdp
, extract_bdp
,
194 PPC_OPERAND_ABSOLUTE
| PPC_OPERAND_SIGNED
},
196 /* The BF field in an X or XL form instruction. */
198 /* The CRFD field in an X form instruction. */
200 /* The CRD field in an XL form instruction. */
202 { 0x7, 23, NULL
, NULL
, PPC_OPERAND_CR_REG
},
204 /* The BF field in an X or XL form instruction. */
206 { 0x7, 23, NULL
, NULL
, 0 },
208 /* An optional BF field. This is used for comparison instructions,
209 in which an omitted BF field is taken as zero. */
211 { 0x7, 23, NULL
, NULL
, PPC_OPERAND_CR_REG
| PPC_OPERAND_OPTIONAL
},
213 /* The BFA field in an X or XL form instruction. */
215 { 0x7, 18, NULL
, NULL
, PPC_OPERAND_CR_REG
},
217 /* The BO field in a B form instruction. Certain values are
220 #define BO_MASK (0x1f << 21)
221 { 0x1f, 21, insert_bo
, extract_bo
, 0 },
223 /* The BO field in a B form instruction when the + or - modifier is
224 used. This is like the BO field, but it must be even. */
226 { 0x1e, 21, insert_boe
, extract_boe
, 0 },
229 { 0x3, 11, NULL
, NULL
, PPC_OPERAND_OPTIONAL
},
231 /* The BT field in an X or XL form instruction. */
233 { 0x1f, 21, NULL
, NULL
, PPC_OPERAND_CR_BIT
},
235 /* The BI16 field in a BD8 form instruction. */
237 { 0x3, 8, NULL
, NULL
, PPC_OPERAND_CR_BIT
},
239 /* The BI32 field in a BD15 form instruction. */
240 #define BI32 BI16 + 1
241 { 0xf, 16, NULL
, NULL
, PPC_OPERAND_CR_BIT
},
243 /* The BO32 field in a BD15 form instruction. */
244 #define BO32 BI32 + 1
245 { 0x3, 20, NULL
, NULL
, 0 },
247 /* The B8 field in a BD8 form instruction. */
249 { 0x1fe, -1, NULL
, NULL
, PPC_OPERAND_RELATIVE
| PPC_OPERAND_SIGNED
},
251 /* The B15 field in a BD15 form instruction. The lowest bit is
254 { 0xfffe, 0, NULL
, NULL
, PPC_OPERAND_RELATIVE
| PPC_OPERAND_SIGNED
},
256 /* The B24 field in a BD24 form instruction. The lowest bit is
259 { 0x1fffffe, 0, NULL
, NULL
, PPC_OPERAND_RELATIVE
| PPC_OPERAND_SIGNED
},
261 /* The condition register number portion of the BI field in a B form
262 or XL form instruction. This is used for the extended
263 conditional branch mnemonics, which set the lower two bits of the
264 BI field. This field is optional. */
266 { 0x7, 18, NULL
, NULL
, PPC_OPERAND_CR_REG
| PPC_OPERAND_OPTIONAL
},
268 /* The CRB field in an X form instruction. */
270 /* The MB field in an M form instruction. */
272 #define MB_MASK (0x1f << 6)
273 { 0x1f, 6, NULL
, NULL
, 0 },
275 /* The CRD32 field in an XL form instruction. */
276 #define CRD32 CRB + 1
277 { 0x3, 21, NULL
, NULL
, PPC_OPERAND_CR_REG
},
279 /* The CRFS field in an X form instruction. */
280 #define CRFS CRD32 + 1
281 { 0x7, 0, NULL
, NULL
, PPC_OPERAND_CR_REG
},
284 { 0x3, 18, NULL
, NULL
, PPC_OPERAND_CR_REG
| PPC_OPERAND_OPTIONAL
},
286 /* The CT field in an X form instruction. */
288 /* The MO field in an mbar instruction. */
290 { 0x1f, 21, NULL
, NULL
, PPC_OPERAND_OPTIONAL
},
292 /* The D field in a D form instruction. This is a displacement off
293 a register, and implies that the next operand is a register in
296 { 0xffff, 0, NULL
, NULL
, PPC_OPERAND_PARENS
| PPC_OPERAND_SIGNED
},
298 /* The D8 field in a D form instruction. This is a displacement off
299 a register, and implies that the next operand is a register in
302 { 0xff, 0, NULL
, NULL
, PPC_OPERAND_PARENS
| PPC_OPERAND_SIGNED
},
304 /* The DQ field in a DQ form instruction. This is like D, but the
305 lower four bits are forced to zero. */
307 { 0xfff0, 0, NULL
, NULL
,
308 PPC_OPERAND_PARENS
| PPC_OPERAND_SIGNED
| PPC_OPERAND_DQ
},
310 /* The DS field in a DS form instruction. This is like D, but the
311 lower two bits are forced to zero. */
313 { 0xfffc, 0, NULL
, NULL
,
314 PPC_OPERAND_PARENS
| PPC_OPERAND_SIGNED
| PPC_OPERAND_DS
},
316 /* The DUIS or BHRBE fields in a XFX form instruction, 10 bits
320 { 0x3ff, 11, NULL
, NULL
, 0 },
322 /* The E field in a wrteei instruction. */
323 /* And the W bit in the pair singles instructions. */
324 /* And the ST field in a VX form instruction. */
328 { 0x1, 15, NULL
, NULL
, 0 },
330 /* The FL1 field in a POWER SC form instruction. */
332 /* The U field in an X form instruction. */
334 { 0xf, 12, NULL
, NULL
, 0 },
336 /* The FL2 field in a POWER SC form instruction. */
338 { 0x7, 2, NULL
, NULL
, 0 },
340 /* The FLM field in an XFL form instruction. */
342 { 0xff, 17, NULL
, NULL
, 0 },
344 /* The FRA field in an X or A form instruction. */
346 #define FRA_MASK (0x1f << 16)
347 { 0x1f, 16, NULL
, NULL
, PPC_OPERAND_FPR
},
349 /* The FRAp field of DFP instructions. */
351 { 0x1e, 16, NULL
, NULL
, PPC_OPERAND_FPR
},
353 /* The FRB field in an X or A form instruction. */
355 #define FRB_MASK (0x1f << 11)
356 { 0x1f, 11, NULL
, NULL
, PPC_OPERAND_FPR
},
358 /* The FRBp field of DFP instructions. */
360 { 0x1e, 11, NULL
, NULL
, PPC_OPERAND_FPR
},
362 /* The FRC field in an A form instruction. */
364 #define FRC_MASK (0x1f << 6)
365 { 0x1f, 6, NULL
, NULL
, PPC_OPERAND_FPR
},
367 /* The FRS field in an X form instruction or the FRT field in a D, X
368 or A form instruction. */
371 { 0x1f, 21, NULL
, NULL
, PPC_OPERAND_FPR
},
373 /* The FRSp field of stfdp or the FRTp field of lfdp and DFP
377 { 0x1e, 21, NULL
, NULL
, PPC_OPERAND_FPR
},
379 /* The FXM field in an XFX instruction. */
381 { 0xff, 12, insert_fxm
, extract_fxm
, 0 },
383 /* Power4 version for mfcr. */
385 { 0xff, 12, insert_fxm
, extract_fxm
, PPC_OPERAND_OPTIONAL
},
387 /* The IMM20 field in an LI instruction. */
388 #define IMM20 FXM4 + 1
389 { 0xfffff, PPC_OPSHIFT_INV
, insert_li20
, extract_li20
, PPC_OPERAND_SIGNED
},
391 /* The L field in a D or X form instruction. */
393 /* The R field in a HTM X form instruction. */
395 { 0x1, 21, NULL
, NULL
, PPC_OPERAND_OPTIONAL
},
397 /* The LEV field in a POWER SVC form instruction. */
398 #define SVC_LEV L + 1
399 { 0x7f, 5, NULL
, NULL
, 0 },
401 /* The LEV field in an SC form instruction. */
402 #define LEV SVC_LEV + 1
403 { 0x7f, 5, NULL
, NULL
, PPC_OPERAND_OPTIONAL
},
405 /* The LI field in an I form instruction. The lower two bits are
408 { 0x3fffffc, 0, NULL
, NULL
, PPC_OPERAND_RELATIVE
| PPC_OPERAND_SIGNED
},
410 /* The LI field in an I form instruction when used as an absolute
413 { 0x3fffffc, 0, NULL
, NULL
, PPC_OPERAND_ABSOLUTE
| PPC_OPERAND_SIGNED
},
415 /* The LS or WC field in an X (sync or wait) form instruction. */
418 { 0x3, 21, NULL
, NULL
, PPC_OPERAND_OPTIONAL
},
420 /* The ME field in an M form instruction. */
422 #define ME_MASK (0x1f << 1)
423 { 0x1f, 1, NULL
, NULL
, 0 },
425 /* The MB and ME fields in an M form instruction expressed a single
426 operand which is a bitmask indicating which bits to select. This
427 is a two operand form using PPC_OPERAND_NEXT. See the
428 description in opcode/ppc.h for what this means. */
430 { 0x1f, 6, NULL
, NULL
, PPC_OPERAND_OPTIONAL
| PPC_OPERAND_NEXT
},
431 { -1, 0, insert_mbe
, extract_mbe
, 0 },
433 /* The MB or ME field in an MD or MDS form instruction. The high
434 bit is wrapped to the low end. */
437 #define MB6_MASK (0x3f << 5)
438 { 0x3f, 5, insert_mb6
, extract_mb6
, 0 },
440 /* The NB field in an X form instruction. The value 32 is stored as
443 { 0x1f, 11, NULL
, extract_nb
, PPC_OPERAND_PLUS1
},
445 /* The NBI field in an lswi instruction, which has special value
446 restrictions. The value 32 is stored as 0. */
448 { 0x1f, 11, insert_nbi
, extract_nb
, PPC_OPERAND_PLUS1
},
450 /* The NSI field in a D form instruction. This is the same as the
451 SI field, only negated. */
453 { 0xffff, 0, insert_nsi
, extract_nsi
,
454 PPC_OPERAND_NEGATIVE
| PPC_OPERAND_SIGNED
},
456 /* The RA field in an D, DS, DQ, X, XO, M, or MDS form instruction. */
458 #define RA_MASK (0x1f << 16)
459 { 0x1f, 16, NULL
, NULL
, PPC_OPERAND_GPR
},
461 /* As above, but 0 in the RA field means zero, not r0. */
463 { 0x1f, 16, NULL
, NULL
, PPC_OPERAND_GPR_0
},
465 /* The RA field in the DQ form lq or an lswx instruction, which have special
466 value restrictions. */
469 { 0x1f, 16, insert_raq
, NULL
, PPC_OPERAND_GPR_0
},
471 /* The RA field in a D or X form instruction which is an updating
472 load, which means that the RA field may not be zero and may not
473 equal the RT field. */
475 { 0x1f, 16, insert_ral
, NULL
, PPC_OPERAND_GPR_0
},
477 /* The RA field in an lmw instruction, which has special value
480 { 0x1f, 16, insert_ram
, NULL
, PPC_OPERAND_GPR_0
},
482 /* The RA field in a D or X form instruction which is an updating
483 store or an updating floating point load, which means that the RA
484 field may not be zero. */
486 { 0x1f, 16, insert_ras
, NULL
, PPC_OPERAND_GPR_0
},
488 /* The RA field of the tlbwe, dccci and iccci instructions,
489 which are optional. */
490 #define RAOPT RAS + 1
491 { 0x1f, 16, NULL
, NULL
, PPC_OPERAND_GPR
| PPC_OPERAND_OPTIONAL
},
493 /* The RB field in an X, XO, M, or MDS form instruction. */
495 #define RB_MASK (0x1f << 11)
496 { 0x1f, 11, NULL
, NULL
, PPC_OPERAND_GPR
},
498 /* The RB field in an X form instruction when it must be the same as
499 the RS field in the instruction. This is used for extended
500 mnemonics like mr. */
502 { 0x1f, 11, insert_rbs
, extract_rbs
, PPC_OPERAND_FAKE
},
504 /* The RB field in an lswx instruction, which has special value
507 { 0x1f, 11, insert_rbx
, NULL
, PPC_OPERAND_GPR
},
509 /* The RB field of the dccci and iccci instructions, which are optional. */
510 #define RBOPT RBX + 1
511 { 0x1f, 11, NULL
, NULL
, PPC_OPERAND_GPR
| PPC_OPERAND_OPTIONAL
},
513 /* The RS field in a D, DS, X, XFX, XS, M, MD or MDS form
514 instruction or the RT field in a D, DS, X, XFX or XO form
518 #define RT_MASK (0x1f << 21)
520 { 0x1f, 21, NULL
, NULL
, PPC_OPERAND_GPR
},
522 /* The RS and RT fields of the DS form stq and DQ form lq instructions,
523 which have special value restrictions. */
526 { 0x1e, 21, NULL
, NULL
, PPC_OPERAND_GPR
},
528 /* The RS field of the tlbwe instruction, which is optional. */
531 { 0x1f, 21, NULL
, NULL
, PPC_OPERAND_GPR
| PPC_OPERAND_OPTIONAL
},
533 /* The RX field of the SE_RR form instruction. */
535 { 0x1f, PPC_OPSHIFT_INV
, insert_rx
, extract_rx
, PPC_OPERAND_GPR
},
537 /* The ARX field of the SE_RR form instruction. */
539 { 0x1f, PPC_OPSHIFT_INV
, insert_arx
, extract_arx
, PPC_OPERAND_GPR
},
541 /* The RY field of the SE_RR form instruction. */
544 { 0x1f, PPC_OPSHIFT_INV
, insert_ry
, extract_ry
, PPC_OPERAND_GPR
},
546 /* The ARY field of the SE_RR form instruction. */
548 { 0x1f, PPC_OPSHIFT_INV
, insert_ary
, extract_ary
, PPC_OPERAND_GPR
},
550 /* The SCLSCI8 field in a D form instruction. */
551 #define SCLSCI8 ARY + 1
552 { 0xffffffff, PPC_OPSHIFT_INV
, insert_sci8
, extract_sci8
, 0 },
554 /* The SCLSCI8N field in a D form instruction. This is the same as the
555 SCLSCI8 field, only negated. */
556 #define SCLSCI8N SCLSCI8 + 1
557 { 0xffffffff, PPC_OPSHIFT_INV
, insert_sci8n
, extract_sci8n
,
558 PPC_OPERAND_NEGATIVE
| PPC_OPERAND_SIGNED
},
560 /* The SD field of the SD4 form instruction. */
561 #define SE_SD SCLSCI8N + 1
562 { 0xf, 8, NULL
, NULL
, PPC_OPERAND_PARENS
},
564 /* The SD field of the SD4 form instruction, for halfword. */
565 #define SE_SDH SE_SD + 1
566 { 0x1e, PPC_OPSHIFT_INV
, insert_sd4h
, extract_sd4h
, PPC_OPERAND_PARENS
},
568 /* The SD field of the SD4 form instruction, for word. */
569 #define SE_SDW SE_SDH + 1
570 { 0x3c, PPC_OPSHIFT_INV
, insert_sd4w
, extract_sd4w
, PPC_OPERAND_PARENS
},
572 /* The SH field in an X or M form instruction. */
573 #define SH SE_SDW + 1
574 #define SH_MASK (0x1f << 11)
575 /* The other UIMM field in a EVX form instruction. */
577 { 0x1f, 11, NULL
, NULL
, 0 },
579 /* The SI field in a HTM X form instruction. */
580 #define HTM_SI SH + 1
581 { 0x1f, 11, NULL
, NULL
, PPC_OPERAND_SIGNED
},
583 /* The SH field in an MD form instruction. This is split. */
584 #define SH6 HTM_SI + 1
585 #define SH6_MASK ((0x1f << 11) | (1 << 1))
586 { 0x3f, PPC_OPSHIFT_INV
, insert_sh6
, extract_sh6
, 0 },
588 /* The SH field of the tlbwe instruction, which is optional. */
590 { 0x1f, 11, NULL
, NULL
, PPC_OPERAND_OPTIONAL
},
592 /* The SI field in a D form instruction. */
594 { 0xffff, 0, NULL
, NULL
, PPC_OPERAND_SIGNED
},
596 /* The SI field in a D form instruction when we accept a wide range
597 of positive values. */
598 #define SISIGNOPT SI + 1
599 { 0xffff, 0, NULL
, NULL
, PPC_OPERAND_SIGNED
| PPC_OPERAND_SIGNOPT
},
601 /* The SI8 field in a D form instruction. */
602 #define SI8 SISIGNOPT + 1
603 { 0xff, 0, NULL
, NULL
, PPC_OPERAND_SIGNED
},
605 /* The SPR field in an XFX form instruction. This is flipped--the
606 lower 5 bits are stored in the upper 5 and vice- versa. */
610 #define SPR_MASK (0x3ff << 11)
611 { 0x3ff, 11, insert_spr
, extract_spr
, 0 },
613 /* The BAT index number in an XFX form m[ft]ibat[lu] instruction. */
614 #define SPRBAT SPR + 1
615 #define SPRBAT_MASK (0x3 << 17)
616 { 0x3, 17, NULL
, NULL
, 0 },
618 /* The SPRG register number in an XFX form m[ft]sprg instruction. */
619 #define SPRG SPRBAT + 1
620 { 0x1f, 16, insert_sprg
, extract_sprg
, 0 },
622 /* The SR field in an X form instruction. */
624 /* The 4-bit UIMM field in a VX form instruction. */
626 { 0xf, 16, NULL
, NULL
, 0 },
628 /* The STRM field in an X AltiVec form instruction. */
630 /* The T field in a tlbilx form instruction. */
632 { 0x3, 21, NULL
, NULL
, 0 },
634 /* The ESYNC field in an X (sync) form instruction. */
635 #define ESYNC STRM + 1
636 { 0xf, 16, insert_ls
, NULL
, PPC_OPERAND_OPTIONAL
},
638 /* The SV field in a POWER SC form instruction. */
640 { 0x3fff, 2, NULL
, NULL
, 0 },
642 /* The TBR field in an XFX form instruction. This is like the SPR
643 field, but it is optional. */
645 { 0x3ff, 11, insert_tbr
, extract_tbr
, PPC_OPERAND_OPTIONAL
},
647 /* The TO field in a D or X form instruction. */
650 #define TO_MASK (0x1f << 21)
651 { 0x1f, 21, NULL
, NULL
, 0 },
653 /* The UI field in a D form instruction. */
655 { 0xffff, 0, NULL
, NULL
, 0 },
657 /* The IMM field in an SE_IM5 instruction. */
659 { 0x1f, 4, NULL
, NULL
, 0 },
661 /* The OIMM field in an SE_OIM5 instruction. */
662 #define OIMM5 UI5 + 1
663 { 0x1f, PPC_OPSHIFT_INV
, insert_oimm
, extract_oimm
, PPC_OPERAND_PLUS1
},
665 /* The UI7 field in an SE_LI instruction. */
666 #define UI7 OIMM5 + 1
667 { 0x7f, 4, NULL
, NULL
, 0 },
669 /* The VA field in a VA, VX or VXR form instruction. */
671 { 0x1f, 16, NULL
, NULL
, PPC_OPERAND_VR
},
673 /* The VB field in a VA, VX or VXR form instruction. */
675 { 0x1f, 11, NULL
, NULL
, PPC_OPERAND_VR
},
677 /* The VC field in a VA form instruction. */
679 { 0x1f, 6, NULL
, NULL
, PPC_OPERAND_VR
},
681 /* The VD or VS field in a VA, VX, VXR or X form instruction. */
684 { 0x1f, 21, NULL
, NULL
, PPC_OPERAND_VR
},
686 /* The SIMM field in a VX form instruction, and TE in Z form. */
689 { 0x1f, 16, NULL
, NULL
, PPC_OPERAND_SIGNED
},
691 /* The UIMM field in a VX form instruction. */
692 #define UIMM SIMM + 1
694 { 0x1f, 16, NULL
, NULL
, 0 },
696 /* The 3-bit UIMM field in a VX form instruction. */
697 #define UIMM3 UIMM + 1
698 { 0x7, 16, NULL
, NULL
, 0 },
700 /* The SIX field in a VX form instruction. */
701 #define SIX UIMM3 + 1
702 { 0xf, 11, NULL
, NULL
, 0 },
704 /* The PS field in a VX form instruction. */
706 { 0x1, 9, NULL
, NULL
, 0 },
708 /* The SHB field in a VA form instruction. */
710 { 0xf, 6, NULL
, NULL
, 0 },
712 /* The other UIMM field in a half word EVX form instruction. */
713 #define EVUIMM_2 SHB + 1
714 { 0x3e, 10, NULL
, NULL
, PPC_OPERAND_PARENS
},
716 /* The other UIMM field in a word EVX form instruction. */
717 #define EVUIMM_4 EVUIMM_2 + 1
718 { 0x7c, 9, NULL
, NULL
, PPC_OPERAND_PARENS
},
720 /* The other UIMM field in a double EVX form instruction. */
721 #define EVUIMM_8 EVUIMM_4 + 1
722 { 0xf8, 8, NULL
, NULL
, PPC_OPERAND_PARENS
},
725 #define WS EVUIMM_8 + 1
726 { 0x7, 11, NULL
, NULL
, 0 },
728 /* PowerPC paired singles extensions. */
729 /* W bit in the pair singles instructions for x type instructions. */
731 /* The BO16 field in a BD8 form instruction. */
733 { 0x1, 10, 0, 0, 0 },
735 /* IDX bits for quantization in the pair singles instructions. */
737 { 0x7, 12, 0, 0, 0 },
739 /* IDX bits for quantization in the pair singles x-type instructions. */
743 /* Smaller D field for quantization in the pair singles instructions. */
745 { 0xfff, 0, 0, 0, PPC_OPERAND_PARENS
| PPC_OPERAND_SIGNED
},
750 { 0x1, 16, NULL
, NULL
, PPC_OPERAND_OPTIONAL
},
752 #define RMC MTMSRD_L + 1
753 { 0x3, 9, NULL
, NULL
, 0 },
756 { 0x1, 16, NULL
, NULL
, 0 },
759 { 0x3, 19, NULL
, NULL
, 0 },
762 { 0x1, 20, NULL
, NULL
, 0 },
764 /* The S field in a XL form instruction. */
766 { 0x1, 11, NULL
, NULL
, PPC_OPERAND_OPTIONAL
},
768 /* SH field starting at bit position 16. */
770 /* The DCM and DGM fields in a Z form instruction. */
773 { 0x3f, 10, NULL
, NULL
, 0 },
775 /* The EH field in larx instruction. */
777 { 0x1, 0, NULL
, NULL
, PPC_OPERAND_OPTIONAL
},
779 /* The L field in an mtfsf or XFL form instruction. */
780 /* The A field in a HTM X form instruction. */
783 { 0x1, 25, NULL
, NULL
, PPC_OPERAND_OPTIONAL
},
785 /* Xilinx APU related masks and macros */
786 #define FCRT XFL_L + 1
787 #define FCRT_MASK (0x1f << 21)
788 { 0x1f, 21, 0, 0, PPC_OPERAND_FCR
},
790 /* Xilinx FSL related masks and macros */
792 #define FSL_MASK (0x1f << 11)
793 { 0x1f, 11, 0, 0, PPC_OPERAND_FSL
},
795 /* Xilinx UDI related masks and macros */
797 { 0x1f, 21, 0, 0, PPC_OPERAND_UDI
},
800 { 0x1f, 16, 0, 0, PPC_OPERAND_UDI
},
803 { 0x1f, 11, 0, 0, PPC_OPERAND_UDI
},
806 { 0x1f, 6, 0, 0, PPC_OPERAND_UDI
},
808 /* The VLESIMM field in a D form instruction. */
809 #define VLESIMM URC + 1
810 { 0xffff, PPC_OPSHIFT_INV
, insert_vlesi
, extract_vlesi
,
811 PPC_OPERAND_SIGNED
| PPC_OPERAND_SIGNOPT
},
813 /* The VLENSIMM field in a D form instruction. */
814 #define VLENSIMM VLESIMM + 1
815 { 0xffff, PPC_OPSHIFT_INV
, insert_vlensi
, extract_vlensi
,
816 PPC_OPERAND_NEGATIVE
| PPC_OPERAND_SIGNED
| PPC_OPERAND_SIGNOPT
},
818 /* The VLEUIMM field in a D form instruction. */
819 #define VLEUIMM VLENSIMM + 1
820 { 0xffff, PPC_OPSHIFT_INV
, insert_vleui
, extract_vleui
, 0 },
822 /* The VLEUIMML field in a D form instruction. */
823 #define VLEUIMML VLEUIMM + 1
824 { 0xffff, PPC_OPSHIFT_INV
, insert_vleil
, extract_vleil
, 0 },
826 /* The XT and XS fields in an XX1 or XX3 form instruction. This is split. */
827 #define XS6 VLEUIMML + 1
829 { 0x3f, PPC_OPSHIFT_INV
, insert_xt6
, extract_xt6
, PPC_OPERAND_VSR
},
831 /* The XA field in an XX3 form instruction. This is split. */
833 { 0x3f, PPC_OPSHIFT_INV
, insert_xa6
, extract_xa6
, PPC_OPERAND_VSR
},
835 /* The XB field in an XX2 or XX3 form instruction. This is split. */
837 { 0x3f, PPC_OPSHIFT_INV
, insert_xb6
, extract_xb6
, PPC_OPERAND_VSR
},
839 /* The XB field in an XX3 form instruction when it must be the same as
840 the XA field in the instruction. This is used in extended mnemonics
841 like xvmovdp. This is split. */
843 { 0x3f, PPC_OPSHIFT_INV
, insert_xb6s
, extract_xb6s
, PPC_OPERAND_FAKE
},
845 /* The XC field in an XX4 form instruction. This is split. */
847 { 0x3f, PPC_OPSHIFT_INV
, insert_xc6
, extract_xc6
, PPC_OPERAND_VSR
},
849 /* The DM or SHW field in an XX3 form instruction. */
852 { 0x3, 8, NULL
, NULL
, 0 },
854 /* The DM field in an extended mnemonic XX3 form instruction. */
856 { 0x3, 8, insert_dm
, extract_dm
, 0 },
858 /* The UIM field in an XX2 form instruction. */
860 /* The 2-bit UIMM field in a VX form instruction. */
862 { 0x3, 16, NULL
, NULL
, 0 },
864 #define ERAT_T UIM + 1
865 { 0x7, 21, NULL
, NULL
, 0 },
868 const unsigned int num_powerpc_operands
= (sizeof (powerpc_operands
)
869 / sizeof (powerpc_operands
[0]));
871 /* The functions used to insert and extract complicated operands. */
873 /* The ARX, ARY, RX and RY operands are alternate encodings of GPRs. */
876 insert_arx (unsigned long insn
,
878 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
879 const char **errmsg ATTRIBUTE_UNUSED
)
881 if (value
>= 8 && value
< 24)
882 return insn
| ((value
- 8) & 0xf);
885 *errmsg
= _("invalid register");
891 extract_arx (unsigned long insn
,
892 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
893 int *invalid ATTRIBUTE_UNUSED
)
895 return (insn
& 0xf) + 8;
899 insert_ary (unsigned long insn
,
901 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
902 const char **errmsg ATTRIBUTE_UNUSED
)
904 if (value
>= 8 && value
< 24)
905 return insn
| (((value
- 8) & 0xf) << 4);
908 *errmsg
= _("invalid register");
914 extract_ary (unsigned long insn
,
915 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
916 int *invalid ATTRIBUTE_UNUSED
)
918 return ((insn
>> 4) & 0xf) + 8;
922 insert_rx (unsigned long insn
,
924 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
927 if (value
>= 0 && value
< 8)
929 else if (value
>= 24 && value
<= 31)
930 return insn
| (value
- 16);
933 *errmsg
= _("invalid register");
939 extract_rx (unsigned long insn
,
940 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
941 int *invalid ATTRIBUTE_UNUSED
)
943 int value
= insn
& 0xf;
944 if (value
>= 0 && value
< 8)
951 insert_ry (unsigned long insn
,
953 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
956 if (value
>= 0 && value
< 8)
957 return insn
| (value
<< 4);
958 else if (value
>= 24 && value
<= 31)
959 return insn
| ((value
- 16) << 4);
962 *errmsg
= _("invalid register");
968 extract_ry (unsigned long insn
,
969 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
970 int *invalid ATTRIBUTE_UNUSED
)
972 int value
= (insn
>> 4) & 0xf;
973 if (value
>= 0 && value
< 8)
979 /* The BA field in an XL form instruction when it must be the same as
980 the BT field in the same instruction. This operand is marked FAKE.
981 The insertion function just copies the BT field into the BA field,
982 and the extraction function just checks that the fields are the
986 insert_bat (unsigned long insn
,
987 long value ATTRIBUTE_UNUSED
,
988 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
989 const char **errmsg ATTRIBUTE_UNUSED
)
991 return insn
| (((insn
>> 21) & 0x1f) << 16);
995 extract_bat (unsigned long insn
,
996 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
999 if (((insn
>> 21) & 0x1f) != ((insn
>> 16) & 0x1f))
1004 /* The BB field in an XL form instruction when it must be the same as
1005 the BA field in the same instruction. This operand is marked FAKE.
1006 The insertion function just copies the BA field into the BB field,
1007 and the extraction function just checks that the fields are the
1010 static unsigned long
1011 insert_bba (unsigned long insn
,
1012 long value ATTRIBUTE_UNUSED
,
1013 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1014 const char **errmsg ATTRIBUTE_UNUSED
)
1016 return insn
| (((insn
>> 16) & 0x1f) << 11);
1020 extract_bba (unsigned long insn
,
1021 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1024 if (((insn
>> 16) & 0x1f) != ((insn
>> 11) & 0x1f))
1029 /* The BD field in a B form instruction when the - modifier is used.
1030 This modifier means that the branch is not expected to be taken.
1031 For chips built to versions of the architecture prior to version 2
1032 (ie. not Power4 compatible), we set the y bit of the BO field to 1
1033 if the offset is negative. When extracting, we require that the y
1034 bit be 1 and that the offset be positive, since if the y bit is 0
1035 we just want to print the normal form of the instruction.
1036 Power4 compatible targets use two bits, "a", and "t", instead of
1037 the "y" bit. "at" == 00 => no hint, "at" == 01 => unpredictable,
1038 "at" == 10 => not taken, "at" == 11 => taken. The "t" bit is 00001
1039 in BO field, the "a" bit is 00010 for branch on CR(BI) and 01000
1040 for branch on CTR. We only handle the taken/not-taken hint here.
1041 Note that we don't relax the conditions tested here when
1042 disassembling with -Many because insns using extract_bdm and
1043 extract_bdp always occur in pairs. One or the other will always
1046 #define ISA_V2 (PPC_OPCODE_POWER4 | PPC_OPCODE_E500MC | PPC_OPCODE_TITAN)
1048 static unsigned long
1049 insert_bdm (unsigned long insn
,
1052 const char **errmsg ATTRIBUTE_UNUSED
)
1054 if ((dialect
& ISA_V2
) == 0)
1056 if ((value
& 0x8000) != 0)
1061 if ((insn
& (0x14 << 21)) == (0x04 << 21))
1063 else if ((insn
& (0x14 << 21)) == (0x10 << 21))
1066 return insn
| (value
& 0xfffc);
1070 extract_bdm (unsigned long insn
,
1074 if ((dialect
& ISA_V2
) == 0)
1076 if (((insn
& (1 << 21)) == 0) != ((insn
& (1 << 15)) == 0))
1081 if ((insn
& (0x17 << 21)) != (0x06 << 21)
1082 && (insn
& (0x1d << 21)) != (0x18 << 21))
1086 return ((insn
& 0xfffc) ^ 0x8000) - 0x8000;
1089 /* The BD field in a B form instruction when the + modifier is used.
1090 This is like BDM, above, except that the branch is expected to be
1093 static unsigned long
1094 insert_bdp (unsigned long insn
,
1097 const char **errmsg ATTRIBUTE_UNUSED
)
1099 if ((dialect
& ISA_V2
) == 0)
1101 if ((value
& 0x8000) == 0)
1106 if ((insn
& (0x14 << 21)) == (0x04 << 21))
1108 else if ((insn
& (0x14 << 21)) == (0x10 << 21))
1111 return insn
| (value
& 0xfffc);
1115 extract_bdp (unsigned long insn
,
1119 if ((dialect
& ISA_V2
) == 0)
1121 if (((insn
& (1 << 21)) == 0) == ((insn
& (1 << 15)) == 0))
1126 if ((insn
& (0x17 << 21)) != (0x07 << 21)
1127 && (insn
& (0x1d << 21)) != (0x19 << 21))
1131 return ((insn
& 0xfffc) ^ 0x8000) - 0x8000;
1135 valid_bo_pre_v2 (long value
)
1137 /* Certain encodings have bits that are required to be zero.
1138 These are (z must be zero, y may be anything):
1149 if ((value
& 0x14) == 0)
1151 else if ((value
& 0x14) == 0x4)
1152 return (value
& 0x2) == 0;
1153 else if ((value
& 0x14) == 0x10)
1154 return (value
& 0x8) == 0;
1156 return value
== 0x14;
1160 valid_bo_post_v2 (long value
)
1162 /* Certain encodings have bits that are required to be zero.
1163 These are (z must be zero, a & t may be anything):
1174 if ((value
& 0x14) == 0)
1175 return (value
& 0x1) == 0;
1176 else if ((value
& 0x14) == 0x14)
1177 return value
== 0x14;
1182 /* Check for legal values of a BO field. */
1185 valid_bo (long value
, ppc_cpu_t dialect
, int extract
)
1187 int valid_y
= valid_bo_pre_v2 (value
);
1188 int valid_at
= valid_bo_post_v2 (value
);
1190 /* When disassembling with -Many, accept either encoding on the
1191 second pass through opcodes. */
1192 if (extract
&& dialect
== ~(ppc_cpu_t
) PPC_OPCODE_ANY
)
1193 return valid_y
|| valid_at
;
1194 if ((dialect
& ISA_V2
) == 0)
1200 /* The BO field in a B form instruction. Warn about attempts to set
1201 the field to an illegal value. */
1203 static unsigned long
1204 insert_bo (unsigned long insn
,
1207 const char **errmsg
)
1209 if (!valid_bo (value
, dialect
, 0))
1210 *errmsg
= _("invalid conditional option");
1211 else if (PPC_OP (insn
) == 19 && (insn
& 0x400) && ! (value
& 4))
1212 *errmsg
= _("invalid counter access");
1213 return insn
| ((value
& 0x1f) << 21);
1217 extract_bo (unsigned long insn
,
1223 value
= (insn
>> 21) & 0x1f;
1224 if (!valid_bo (value
, dialect
, 1))
1229 /* The BO field in a B form instruction when the + or - modifier is
1230 used. This is like the BO field, but it must be even. When
1231 extracting it, we force it to be even. */
1233 static unsigned long
1234 insert_boe (unsigned long insn
,
1237 const char **errmsg
)
1239 if (!valid_bo (value
, dialect
, 0))
1240 *errmsg
= _("invalid conditional option");
1241 else if (PPC_OP (insn
) == 19 && (insn
& 0x400) && ! (value
& 4))
1242 *errmsg
= _("invalid counter access");
1243 else if ((value
& 1) != 0)
1244 *errmsg
= _("attempt to set y bit when using + or - modifier");
1246 return insn
| ((value
& 0x1f) << 21);
1250 extract_boe (unsigned long insn
,
1256 value
= (insn
>> 21) & 0x1f;
1257 if (!valid_bo (value
, dialect
, 1))
1259 return value
& 0x1e;
1262 /* FXM mask in mfcr and mtcrf instructions. */
1264 static unsigned long
1265 insert_fxm (unsigned long insn
,
1268 const char **errmsg
)
1270 /* If we're handling the mfocrf and mtocrf insns ensure that exactly
1271 one bit of the mask field is set. */
1272 if ((insn
& (1 << 20)) != 0)
1274 if (value
== 0 || (value
& -value
) != value
)
1276 *errmsg
= _("invalid mask field");
1281 /* If the optional field on mfcr is missing that means we want to use
1282 the old form of the instruction that moves the whole cr. In that
1283 case we'll have VALUE zero. There doesn't seem to be a way to
1284 distinguish this from the case where someone writes mfcr %r3,0. */
1285 else if (value
== 0)
1288 /* If only one bit of the FXM field is set, we can use the new form
1289 of the instruction, which is faster. Unlike the Power4 branch hint
1290 encoding, this is not backward compatible. Do not generate the
1291 new form unless -mpower4 has been given, or -many and the two
1292 operand form of mfcr was used. */
1293 else if ((value
& -value
) == value
1294 && ((dialect
& PPC_OPCODE_POWER4
) != 0
1295 || ((dialect
& PPC_OPCODE_ANY
) != 0
1296 && (insn
& (0x3ff << 1)) == 19 << 1)))
1299 /* Any other value on mfcr is an error. */
1300 else if ((insn
& (0x3ff << 1)) == 19 << 1)
1302 *errmsg
= _("ignoring invalid mfcr mask");
1306 return insn
| ((value
& 0xff) << 12);
1310 extract_fxm (unsigned long insn
,
1311 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1314 long mask
= (insn
>> 12) & 0xff;
1316 /* Is this a Power4 insn? */
1317 if ((insn
& (1 << 20)) != 0)
1319 /* Exactly one bit of MASK should be set. */
1320 if (mask
== 0 || (mask
& -mask
) != mask
)
1324 /* Check that non-power4 form of mfcr has a zero MASK. */
1325 else if ((insn
& (0x3ff << 1)) == 19 << 1)
1334 static unsigned long
1335 insert_li20 (unsigned long insn
,
1337 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1338 const char **errmsg ATTRIBUTE_UNUSED
)
1340 return insn
| ((value
& 0xf0000) >> 5) | ((value
& 0x0f800) << 5) | (value
& 0x7ff);
1344 extract_li20 (unsigned long insn
,
1345 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1346 int *invalid ATTRIBUTE_UNUSED
)
1348 long ext
= ((insn
& 0x4000) == 0x4000) ? 0xfff00000 : 0x00000000;
1351 | (((insn
>> 11) & 0xf) << 16)
1352 | (((insn
>> 17) & 0xf) << 12)
1353 | (((insn
>> 16) & 0x1) << 11)
1357 /* The LS field in a sync instruction that accepts 2 operands
1358 Values 2 and 3 are reserved,
1359 must be treated as 0 for future compatibility
1360 Values 0 and 1 can be accepted, if field ESYNC is zero
1361 Otherwise L = complement of ESYNC-bit2 (1<<18) */
1363 static unsigned long
1364 insert_ls (unsigned long insn
,
1366 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1367 const char **errmsg ATTRIBUTE_UNUSED
)
1371 ls
= (insn
>> 21) & 0x03;
1375 return insn
& ~(0x3 << 21);
1378 if ((value
& 0x2) != 0)
1379 return (insn
& ~(0x3 << 21)) | ((value
& 0xf) << 16);
1380 return (insn
& ~(0x3 << 21)) | (0x1 << 21) | ((value
& 0xf) << 16);
1383 /* The MB and ME fields in an M form instruction expressed as a single
1384 operand which is itself a bitmask. The extraction function always
1385 marks it as invalid, since we never want to recognize an
1386 instruction which uses a field of this type. */
1388 static unsigned long
1389 insert_mbe (unsigned long insn
,
1391 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1392 const char **errmsg
)
1394 unsigned long uval
, mask
;
1395 int mb
, me
, mx
, count
, last
;
1401 *errmsg
= _("illegal bitmask");
1407 if ((uval
& 1) != 0)
1413 /* mb: location of last 0->1 transition */
1414 /* me: location of last 1->0 transition */
1415 /* count: # transitions */
1417 for (mx
= 0, mask
= 1L << 31; mx
< 32; ++mx
, mask
>>= 1)
1419 if ((uval
& mask
) && !last
)
1425 else if (!(uval
& mask
) && last
)
1435 if (count
!= 2 && (count
!= 0 || ! last
))
1436 *errmsg
= _("illegal bitmask");
1438 return insn
| (mb
<< 6) | ((me
- 1) << 1);
1442 extract_mbe (unsigned long insn
,
1443 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1452 mb
= (insn
>> 6) & 0x1f;
1453 me
= (insn
>> 1) & 0x1f;
1457 for (i
= mb
; i
<= me
; i
++)
1458 ret
|= 1L << (31 - i
);
1460 else if (mb
== me
+ 1)
1462 else /* (mb > me + 1) */
1465 for (i
= me
+ 1; i
< mb
; i
++)
1466 ret
&= ~(1L << (31 - i
));
1471 /* The MB or ME field in an MD or MDS form instruction. The high bit
1472 is wrapped to the low end. */
1474 static unsigned long
1475 insert_mb6 (unsigned long insn
,
1477 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1478 const char **errmsg ATTRIBUTE_UNUSED
)
1480 return insn
| ((value
& 0x1f) << 6) | (value
& 0x20);
1484 extract_mb6 (unsigned long insn
,
1485 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1486 int *invalid ATTRIBUTE_UNUSED
)
1488 return ((insn
>> 6) & 0x1f) | (insn
& 0x20);
1491 /* The NB field in an X form instruction. The value 32 is stored as
1495 extract_nb (unsigned long insn
,
1496 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1497 int *invalid ATTRIBUTE_UNUSED
)
1501 ret
= (insn
>> 11) & 0x1f;
1507 /* The NB field in an lswi instruction, which has special value
1508 restrictions. The value 32 is stored as 0. */
1510 static unsigned long
1511 insert_nbi (unsigned long insn
,
1513 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1514 const char **errmsg ATTRIBUTE_UNUSED
)
1516 long rtvalue
= (insn
& RT_MASK
) >> 21;
1517 long ravalue
= (insn
& RA_MASK
) >> 16;
1521 if (rtvalue
+ (value
+ 3) / 4 > (rtvalue
> ravalue
? ravalue
+ 32
1523 *errmsg
= _("address register in load range");
1524 return insn
| ((value
& 0x1f) << 11);
1527 /* The NSI field in a D form instruction. This is the same as the SI
1528 field, only negated. The extraction function always marks it as
1529 invalid, since we never want to recognize an instruction which uses
1530 a field of this type. */
1532 static unsigned long
1533 insert_nsi (unsigned long insn
,
1535 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1536 const char **errmsg ATTRIBUTE_UNUSED
)
1538 return insn
| (-value
& 0xffff);
1542 extract_nsi (unsigned long insn
,
1543 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1547 return -(((insn
& 0xffff) ^ 0x8000) - 0x8000);
1550 /* The RA field in a D or X form instruction which is an updating
1551 load, which means that the RA field may not be zero and may not
1552 equal the RT field. */
1554 static unsigned long
1555 insert_ral (unsigned long insn
,
1557 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1558 const char **errmsg
)
1561 || (unsigned long) value
== ((insn
>> 21) & 0x1f))
1562 *errmsg
= "invalid register operand when updating";
1563 return insn
| ((value
& 0x1f) << 16);
1566 /* The RA field in an lmw instruction, which has special value
1569 static unsigned long
1570 insert_ram (unsigned long insn
,
1572 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1573 const char **errmsg
)
1575 if ((unsigned long) value
>= ((insn
>> 21) & 0x1f))
1576 *errmsg
= _("index register in load range");
1577 return insn
| ((value
& 0x1f) << 16);
1580 /* The RA field in the DQ form lq or an lswx instruction, which have special
1581 value restrictions. */
1583 static unsigned long
1584 insert_raq (unsigned long insn
,
1586 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1587 const char **errmsg
)
1589 long rtvalue
= (insn
& RT_MASK
) >> 21;
1591 if (value
== rtvalue
)
1592 *errmsg
= _("source and target register operands must be different");
1593 return insn
| ((value
& 0x1f) << 16);
1596 /* The RA field in a D or X form instruction which is an updating
1597 store or an updating floating point load, which means that the RA
1598 field may not be zero. */
1600 static unsigned long
1601 insert_ras (unsigned long insn
,
1603 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1604 const char **errmsg
)
1607 *errmsg
= _("invalid register operand when updating");
1608 return insn
| ((value
& 0x1f) << 16);
1611 /* The RB field in an X form instruction when it must be the same as
1612 the RS field in the instruction. This is used for extended
1613 mnemonics like mr. This operand is marked FAKE. The insertion
1614 function just copies the BT field into the BA field, and the
1615 extraction function just checks that the fields are the same. */
1617 static unsigned long
1618 insert_rbs (unsigned long insn
,
1619 long value ATTRIBUTE_UNUSED
,
1620 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1621 const char **errmsg ATTRIBUTE_UNUSED
)
1623 return insn
| (((insn
>> 21) & 0x1f) << 11);
1627 extract_rbs (unsigned long insn
,
1628 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1631 if (((insn
>> 21) & 0x1f) != ((insn
>> 11) & 0x1f))
1636 /* The RB field in an lswx instruction, which has special value
1639 static unsigned long
1640 insert_rbx (unsigned long insn
,
1642 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1643 const char **errmsg
)
1645 long rtvalue
= (insn
& RT_MASK
) >> 21;
1647 if (value
== rtvalue
)
1648 *errmsg
= _("source and target register operands must be different");
1649 return insn
| ((value
& 0x1f) << 11);
1652 /* The SCI8 field is made up of SCL and {U,N}I8 fields. */
1653 static unsigned long
1654 insert_sci8 (unsigned long insn
,
1656 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1657 const char **errmsg
)
1659 unsigned int fill_scale
= 0;
1660 unsigned long ui8
= value
;
1662 if ((ui8
& 0xffffff00) == 0)
1664 else if ((ui8
& 0xffffff00) == 0xffffff00)
1666 else if ((ui8
& 0xffff00ff) == 0)
1668 fill_scale
= 1 << 8;
1671 else if ((ui8
& 0xffff00ff) == 0xffff00ff)
1673 fill_scale
= 0x400 | (1 << 8);
1676 else if ((ui8
& 0xff00ffff) == 0)
1678 fill_scale
= 2 << 8;
1681 else if ((ui8
& 0xff00ffff) == 0xff00ffff)
1683 fill_scale
= 0x400 | (2 << 8);
1686 else if ((ui8
& 0x00ffffff) == 0)
1688 fill_scale
= 3 << 8;
1691 else if ((ui8
& 0x00ffffff) == 0x00ffffff)
1693 fill_scale
= 0x400 | (3 << 8);
1698 *errmsg
= _("illegal immediate value");
1702 return insn
| fill_scale
| (ui8
& 0xff);
1706 extract_sci8 (unsigned long insn
,
1707 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1708 int *invalid ATTRIBUTE_UNUSED
)
1710 int fill
= insn
& 0x400;
1711 int scale_factor
= (insn
& 0x300) >> 5;
1712 long value
= (insn
& 0xff) << scale_factor
;
1715 value
|= ~((long) 0xff << scale_factor
);
1719 static unsigned long
1720 insert_sci8n (unsigned long insn
,
1723 const char **errmsg
)
1725 return insert_sci8 (insn
, -value
, dialect
, errmsg
);
1729 extract_sci8n (unsigned long insn
,
1733 return -extract_sci8 (insn
, dialect
, invalid
);
1736 static unsigned long
1737 insert_sd4h (unsigned long insn
,
1739 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1740 const char **errmsg ATTRIBUTE_UNUSED
)
1742 return insn
| ((value
& 0x1e) << 7);
1746 extract_sd4h (unsigned long insn
,
1747 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1748 int *invalid ATTRIBUTE_UNUSED
)
1750 return ((insn
>> 8) & 0xf) << 1;
1753 static unsigned long
1754 insert_sd4w (unsigned long insn
,
1756 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1757 const char **errmsg ATTRIBUTE_UNUSED
)
1759 return insn
| ((value
& 0x3c) << 6);
1763 extract_sd4w (unsigned long insn
,
1764 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1765 int *invalid ATTRIBUTE_UNUSED
)
1767 return ((insn
>> 8) & 0xf) << 2;
1770 static unsigned long
1771 insert_oimm (unsigned long insn
,
1773 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1774 const char **errmsg ATTRIBUTE_UNUSED
)
1776 return insn
| (((value
- 1) & 0x1f) << 4);
1780 extract_oimm (unsigned long insn
,
1781 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1782 int *invalid ATTRIBUTE_UNUSED
)
1784 return ((insn
>> 4) & 0x1f) + 1;
1787 /* The SH field in an MD form instruction. This is split. */
1789 static unsigned long
1790 insert_sh6 (unsigned long insn
,
1792 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1793 const char **errmsg ATTRIBUTE_UNUSED
)
1795 return insn
| ((value
& 0x1f) << 11) | ((value
& 0x20) >> 4);
1799 extract_sh6 (unsigned long insn
,
1800 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1801 int *invalid ATTRIBUTE_UNUSED
)
1803 return ((insn
>> 11) & 0x1f) | ((insn
<< 4) & 0x20);
1806 /* The SPR field in an XFX form instruction. This is flipped--the
1807 lower 5 bits are stored in the upper 5 and vice- versa. */
1809 static unsigned long
1810 insert_spr (unsigned long insn
,
1812 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1813 const char **errmsg ATTRIBUTE_UNUSED
)
1815 return insn
| ((value
& 0x1f) << 16) | ((value
& 0x3e0) << 6);
1819 extract_spr (unsigned long insn
,
1820 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1821 int *invalid ATTRIBUTE_UNUSED
)
1823 return ((insn
>> 16) & 0x1f) | ((insn
>> 6) & 0x3e0);
1826 /* Some dialects have 8 SPRG registers instead of the standard 4. */
1827 #define ALLOW8_SPRG (PPC_OPCODE_BOOKE | PPC_OPCODE_405 | PPC_OPCODE_VLE)
1829 static unsigned long
1830 insert_sprg (unsigned long insn
,
1833 const char **errmsg
)
1836 || (value
> 3 && (dialect
& ALLOW8_SPRG
) == 0))
1837 *errmsg
= _("invalid sprg number");
1839 /* If this is mfsprg4..7 then use spr 260..263 which can be read in
1840 user mode. Anything else must use spr 272..279. */
1841 if (value
<= 3 || (insn
& 0x100) != 0)
1844 return insn
| ((value
& 0x17) << 16);
1848 extract_sprg (unsigned long insn
,
1852 unsigned long val
= (insn
>> 16) & 0x1f;
1854 /* mfsprg can use 260..263 and 272..279. mtsprg only uses spr 272..279
1855 If not BOOKE, 405 or VLE, then both use only 272..275. */
1856 if ((val
- 0x10 > 3 && (dialect
& ALLOW8_SPRG
) == 0)
1857 || (val
- 0x10 > 7 && (insn
& 0x100) != 0)
1864 /* The TBR field in an XFX instruction. This is just like SPR, but it
1865 is optional. When TBR is omitted, it must be inserted as 268 (the
1866 magic number of the TB register). These functions treat 0
1867 (indicating an omitted optional operand) as 268. This means that
1868 ``mftb 4,0'' is not handled correctly. This does not matter very
1869 much, since the architecture manual does not define mftb as
1870 accepting any values other than 268 or 269. */
1874 static unsigned long
1875 insert_tbr (unsigned long insn
,
1877 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1878 const char **errmsg ATTRIBUTE_UNUSED
)
1882 return insn
| ((value
& 0x1f) << 16) | ((value
& 0x3e0) << 6);
1886 extract_tbr (unsigned long insn
,
1887 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1888 int *invalid ATTRIBUTE_UNUSED
)
1892 ret
= ((insn
>> 16) & 0x1f) | ((insn
>> 6) & 0x3e0);
1898 /* The XT and XS fields in an XX1 or XX3 form instruction. This is split. */
1900 static unsigned long
1901 insert_xt6 (unsigned long insn
,
1903 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1904 const char **errmsg ATTRIBUTE_UNUSED
)
1906 return insn
| ((value
& 0x1f) << 21) | ((value
& 0x20) >> 5);
1910 extract_xt6 (unsigned long insn
,
1911 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1912 int *invalid ATTRIBUTE_UNUSED
)
1914 return ((insn
<< 5) & 0x20) | ((insn
>> 21) & 0x1f);
1917 /* The XA field in an XX3 form instruction. This is split. */
1919 static unsigned long
1920 insert_xa6 (unsigned long insn
,
1922 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1923 const char **errmsg ATTRIBUTE_UNUSED
)
1925 return insn
| ((value
& 0x1f) << 16) | ((value
& 0x20) >> 3);
1929 extract_xa6 (unsigned long insn
,
1930 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1931 int *invalid ATTRIBUTE_UNUSED
)
1933 return ((insn
<< 3) & 0x20) | ((insn
>> 16) & 0x1f);
1936 /* The XB field in an XX3 form instruction. This is split. */
1938 static unsigned long
1939 insert_xb6 (unsigned long insn
,
1941 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1942 const char **errmsg ATTRIBUTE_UNUSED
)
1944 return insn
| ((value
& 0x1f) << 11) | ((value
& 0x20) >> 4);
1948 extract_xb6 (unsigned long insn
,
1949 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1950 int *invalid ATTRIBUTE_UNUSED
)
1952 return ((insn
<< 4) & 0x20) | ((insn
>> 11) & 0x1f);
1955 /* The XB field in an XX3 form instruction when it must be the same as
1956 the XA field in the instruction. This is used for extended
1957 mnemonics like xvmovdp. This operand is marked FAKE. The insertion
1958 function just copies the XA field into the XB field, and the
1959 extraction function just checks that the fields are the same. */
1961 static unsigned long
1962 insert_xb6s (unsigned long insn
,
1963 long value ATTRIBUTE_UNUSED
,
1964 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1965 const char **errmsg ATTRIBUTE_UNUSED
)
1967 return insn
| (((insn
>> 16) & 0x1f) << 11) | (((insn
>> 2) & 0x1) << 1);
1971 extract_xb6s (unsigned long insn
,
1972 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1975 if ((((insn
>> 16) & 0x1f) != ((insn
>> 11) & 0x1f))
1976 || (((insn
>> 2) & 0x1) != ((insn
>> 1) & 0x1)))
1981 /* The XC field in an XX4 form instruction. This is split. */
1983 static unsigned long
1984 insert_xc6 (unsigned long insn
,
1986 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1987 const char **errmsg ATTRIBUTE_UNUSED
)
1989 return insn
| ((value
& 0x1f) << 6) | ((value
& 0x20) >> 2);
1993 extract_xc6 (unsigned long insn
,
1994 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1995 int *invalid ATTRIBUTE_UNUSED
)
1997 return ((insn
<< 2) & 0x20) | ((insn
>> 6) & 0x1f);
2000 static unsigned long
2001 insert_dm (unsigned long insn
,
2003 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
2004 const char **errmsg
)
2006 if (value
!= 0 && value
!= 1)
2007 *errmsg
= _("invalid constant");
2008 return insn
| (((value
) ? 3 : 0) << 8);
2012 extract_dm (unsigned long insn
,
2013 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
2018 value
= (insn
>> 8) & 3;
2019 if (value
!= 0 && value
!= 3)
2021 return (value
) ? 1 : 0;
2023 /* The VLESIMM field in an I16A form instruction. This is split. */
2025 static unsigned long
2026 insert_vlesi (unsigned long insn
,
2028 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
2029 const char **errmsg ATTRIBUTE_UNUSED
)
2031 return insn
| ((value
& 0xf800) << 10) | (value
& 0x7ff);
2035 extract_vlesi (unsigned long insn
,
2036 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
2037 int *invalid ATTRIBUTE_UNUSED
)
2039 long value
= ((insn
>> 10) & 0xf800) | (insn
& 0x7ff);
2040 value
= (value
^ 0x8000) - 0x8000;
2044 static unsigned long
2045 insert_vlensi (unsigned long insn
,
2047 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
2048 const char **errmsg ATTRIBUTE_UNUSED
)
2051 return insn
| ((value
& 0xf800) << 10) | (value
& 0x7ff);
2054 extract_vlensi (unsigned long insn
,
2055 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
2056 int *invalid ATTRIBUTE_UNUSED
)
2058 long value
= ((insn
>> 10) & 0xf800) | (insn
& 0x7ff);
2059 value
= (value
^ 0x8000) - 0x8000;
2060 /* Don't use for disassembly. */
2065 /* The VLEUIMM field in an I16A form instruction. This is split. */
2067 static unsigned long
2068 insert_vleui (unsigned long insn
,
2070 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
2071 const char **errmsg ATTRIBUTE_UNUSED
)
2073 return insn
| ((value
& 0xf800) << 10) | (value
& 0x7ff);
2077 extract_vleui (unsigned long insn
,
2078 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
2079 int *invalid ATTRIBUTE_UNUSED
)
2081 return ((insn
>> 10) & 0xf800) | (insn
& 0x7ff);
2084 /* The VLEUIMML field in an I16L form instruction. This is split. */
2086 static unsigned long
2087 insert_vleil (unsigned long insn
,
2089 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
2090 const char **errmsg ATTRIBUTE_UNUSED
)
2092 return insn
| ((value
& 0xf800) << 5) | (value
& 0x7ff);
2096 extract_vleil (unsigned long insn
,
2097 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
2098 int *invalid ATTRIBUTE_UNUSED
)
2100 return ((insn
>> 5) & 0xf800) | (insn
& 0x7ff);
2104 /* Macros used to form opcodes. */
2106 /* The main opcode. */
2107 #define OP(x) ((((unsigned long)(x)) & 0x3f) << 26)
2108 #define OP_MASK OP (0x3f)
2110 /* The main opcode combined with a trap code in the TO field of a D
2111 form instruction. Used for extended mnemonics for the trap
2113 #define OPTO(x,to) (OP (x) | ((((unsigned long)(to)) & 0x1f) << 21))
2114 #define OPTO_MASK (OP_MASK | TO_MASK)
2116 /* The main opcode combined with a comparison size bit in the L field
2117 of a D form or X form instruction. Used for extended mnemonics for
2118 the comparison instructions. */
2119 #define OPL(x,l) (OP (x) | ((((unsigned long)(l)) & 1) << 21))
2120 #define OPL_MASK OPL (0x3f,1)
2122 /* The main opcode combined with an update code in D form instruction.
2123 Used for extended mnemonics for VLE memory instructions. */
2124 #define OPVUP(x,vup) (OP (x) | ((((unsigned long)(vup)) & 0xff) << 8))
2125 #define OPVUP_MASK OPVUP (0x3f, 0xff)
2127 /* An A form instruction. */
2128 #define A(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0x1f) << 1) | (((unsigned long)(rc)) & 1))
2129 #define A_MASK A (0x3f, 0x1f, 1)
2131 /* An A_MASK with the FRB field fixed. */
2132 #define AFRB_MASK (A_MASK | FRB_MASK)
2134 /* An A_MASK with the FRC field fixed. */
2135 #define AFRC_MASK (A_MASK | FRC_MASK)
2137 /* An A_MASK with the FRA and FRC fields fixed. */
2138 #define AFRAFRC_MASK (A_MASK | FRA_MASK | FRC_MASK)
2140 /* An AFRAFRC_MASK, but with L bit clear. */
2141 #define AFRALFRC_MASK (AFRAFRC_MASK & ~((unsigned long) 1 << 16))
2143 /* A B form instruction. */
2144 #define B(op, aa, lk) (OP (op) | ((((unsigned long)(aa)) & 1) << 1) | ((lk) & 1))
2145 #define B_MASK B (0x3f, 1, 1)
2147 /* A BD8 form instruction. This is a 16-bit instruction. */
2148 #define BD8(op, aa, lk) (((((unsigned long)(op)) & 0x3f) << 10) | (((aa) & 1) << 9) | (((lk) & 1) << 8))
2149 #define BD8_MASK BD8 (0x3f, 1, 1)
2151 /* Another BD8 form instruction. This is a 16-bit instruction. */
2152 #define BD8IO(op) ((((unsigned long)(op)) & 0x1f) << 11)
2153 #define BD8IO_MASK BD8IO (0x1f)
2155 /* A BD8 form instruction for simplified mnemonics. */
2156 #define EBD8IO(op, bo, bi) (BD8IO ((op)) | ((bo) << 10) | ((bi) << 8))
2157 /* A mask that excludes BO32 and BI32. */
2158 #define EBD8IO1_MASK 0xf800
2159 /* A mask that includes BO32 and excludes BI32. */
2160 #define EBD8IO2_MASK 0xfc00
2161 /* A mask that include BO32 AND BI32. */
2162 #define EBD8IO3_MASK 0xff00
2164 /* A BD15 form instruction. */
2165 #define BD15(op, aa, lk) (OP (op) | ((((unsigned long)(aa)) & 0xf) << 22) | ((lk) & 1))
2166 #define BD15_MASK BD15 (0x3f, 0xf, 1)
2168 /* A BD15 form instruction for extended conditional branch mnemonics. */
2169 #define EBD15(op, aa, bo, lk) (((op) & 0x3f) << 26) | (((aa) & 0xf) << 22) | (((bo) & 0x3) << 20) | ((lk) & 1)
2170 #define EBD15_MASK 0xfff00001
2172 /* A BD15 form instruction for extended conditional branch mnemonics with BI. */
2173 #define EBD15BI(op, aa, bo, bi, lk) (((op) & 0x3f) << 26) \
2174 | (((aa) & 0xf) << 22) \
2175 | (((bo) & 0x3) << 20) \
2176 | (((bi) & 0x3) << 16) \
2178 #define EBD15BI_MASK 0xfff30001
2180 /* A BD24 form instruction. */
2181 #define BD24(op, aa, lk) (OP (op) | ((((unsigned long)(aa)) & 1) << 25) | ((lk) & 1))
2182 #define BD24_MASK BD24 (0x3f, 1, 1)
2184 /* A B form instruction setting the BO field. */
2185 #define BBO(op, bo, aa, lk) (B ((op), (aa), (lk)) | ((((unsigned long)(bo)) & 0x1f) << 21))
2186 #define BBO_MASK BBO (0x3f, 0x1f, 1, 1)
2188 /* A BBO_MASK with the y bit of the BO field removed. This permits
2189 matching a conditional branch regardless of the setting of the y
2190 bit. Similarly for the 'at' bits used for power4 branch hints. */
2191 #define Y_MASK (((unsigned long) 1) << 21)
2192 #define AT1_MASK (((unsigned long) 3) << 21)
2193 #define AT2_MASK (((unsigned long) 9) << 21)
2194 #define BBOY_MASK (BBO_MASK &~ Y_MASK)
2195 #define BBOAT_MASK (BBO_MASK &~ AT1_MASK)
2197 /* A B form instruction setting the BO field and the condition bits of
2199 #define BBOCB(op, bo, cb, aa, lk) \
2200 (BBO ((op), (bo), (aa), (lk)) | ((((unsigned long)(cb)) & 0x3) << 16))
2201 #define BBOCB_MASK BBOCB (0x3f, 0x1f, 0x3, 1, 1)
2203 /* A BBOCB_MASK with the y bit of the BO field removed. */
2204 #define BBOYCB_MASK (BBOCB_MASK &~ Y_MASK)
2205 #define BBOATCB_MASK (BBOCB_MASK &~ AT1_MASK)
2206 #define BBOAT2CB_MASK (BBOCB_MASK &~ AT2_MASK)
2208 /* A BBOYCB_MASK in which the BI field is fixed. */
2209 #define BBOYBI_MASK (BBOYCB_MASK | BI_MASK)
2210 #define BBOATBI_MASK (BBOAT2CB_MASK | BI_MASK)
2212 /* A VLE C form instruction. */
2213 #define C_LK(x, lk) (((((unsigned long)(x)) & 0x7fff) << 1) | ((lk) & 1))
2214 #define C_LK_MASK C_LK(0x7fff, 1)
2215 #define C(x) ((((unsigned long)(x)) & 0xffff))
2216 #define C_MASK C(0xffff)
2218 /* An Context form instruction. */
2219 #define CTX(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x7))
2220 #define CTX_MASK CTX(0x3f, 0x7)
2222 /* An User Context form instruction. */
2223 #define UCTX(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x1f))
2224 #define UCTX_MASK UCTX(0x3f, 0x1f)
2226 /* The main opcode mask with the RA field clear. */
2227 #define DRA_MASK (OP_MASK | RA_MASK)
2229 /* A DS form instruction. */
2230 #define DSO(op, xop) (OP (op) | ((xop) & 0x3))
2231 #define DS_MASK DSO (0x3f, 3)
2233 /* An EVSEL form instruction. */
2234 #define EVSEL(op, xop) (OP (op) | (((unsigned long)(xop)) & 0xff) << 3)
2235 #define EVSEL_MASK EVSEL(0x3f, 0xff)
2237 /* An IA16 form instruction. */
2238 #define IA16(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x1f) << 11)
2239 #define IA16_MASK IA16(0x3f, 0x1f)
2241 /* An I16A form instruction. */
2242 #define I16A(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x1f) << 11)
2243 #define I16A_MASK I16A(0x3f, 0x1f)
2245 /* An I16L form instruction. */
2246 #define I16L(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x1f) << 11)
2247 #define I16L_MASK I16L(0x3f, 0x1f)
2249 /* An IM7 form instruction. */
2250 #define IM7(op) ((((unsigned long)(op)) & 0x1f) << 11)
2251 #define IM7_MASK IM7(0x1f)
2253 /* An M form instruction. */
2254 #define M(op, rc) (OP (op) | ((rc) & 1))
2255 #define M_MASK M (0x3f, 1)
2257 /* An LI20 form instruction. */
2258 #define LI20(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x1) << 15)
2259 #define LI20_MASK LI20(0x3f, 0x1)
2261 /* An M form instruction with the ME field specified. */
2262 #define MME(op, me, rc) (M ((op), (rc)) | ((((unsigned long)(me)) & 0x1f) << 1))
2264 /* An M_MASK with the MB and ME fields fixed. */
2265 #define MMBME_MASK (M_MASK | MB_MASK | ME_MASK)
2267 /* An M_MASK with the SH and ME fields fixed. */
2268 #define MSHME_MASK (M_MASK | SH_MASK | ME_MASK)
2270 /* An MD form instruction. */
2271 #define MD(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0x7) << 2) | ((rc) & 1))
2272 #define MD_MASK MD (0x3f, 0x7, 1)
2274 /* An MD_MASK with the MB field fixed. */
2275 #define MDMB_MASK (MD_MASK | MB6_MASK)
2277 /* An MD_MASK with the SH field fixed. */
2278 #define MDSH_MASK (MD_MASK | SH6_MASK)
2280 /* An MDS form instruction. */
2281 #define MDS(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0xf) << 1) | ((rc) & 1))
2282 #define MDS_MASK MDS (0x3f, 0xf, 1)
2284 /* An MDS_MASK with the MB field fixed. */
2285 #define MDSMB_MASK (MDS_MASK | MB6_MASK)
2287 /* An SC form instruction. */
2288 #define SC(op, sa, lk) (OP (op) | ((((unsigned long)(sa)) & 1) << 1) | ((lk) & 1))
2289 #define SC_MASK (OP_MASK | (((unsigned long)0x3ff) << 16) | (((unsigned long)1) << 1) | 1)
2291 /* An SCI8 form instruction. */
2292 #define SCI8(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x1f) << 11))
2293 #define SCI8_MASK SCI8(0x3f, 0x1f)
2295 /* An SCI8 form instruction. */
2296 #define SCI8BF(op, fop, xop) (OP (op) | ((((unsigned long)(xop)) & 0x1f) << 11) | (((fop) & 7) << 23))
2297 #define SCI8BF_MASK SCI8BF(0x3f, 7, 0x1f)
2299 /* An SD4 form instruction. This is a 16-bit instruction. */
2300 #define SD4(op) ((((unsigned long)(op)) & 0xf) << 12)
2301 #define SD4_MASK SD4(0xf)
2303 /* An SE_IM5 form instruction. This is a 16-bit instruction. */
2304 #define SE_IM5(op, xop) (((((unsigned long)(op)) & 0x3f) << 10) | (((xop) & 0x1) << 9))
2305 #define SE_IM5_MASK SE_IM5(0x3f, 1)
2307 /* An SE_R form instruction. This is a 16-bit instruction. */
2308 #define SE_R(op, xop) (((((unsigned long)(op)) & 0x3f) << 10) | (((xop) & 0x3f) << 4))
2309 #define SE_R_MASK SE_R(0x3f, 0x3f)
2311 /* An SE_RR form instruction. This is a 16-bit instruction. */
2312 #define SE_RR(op, xop) (((((unsigned long)(op)) & 0x3f) << 10) | (((xop) & 0x3) << 8))
2313 #define SE_RR_MASK SE_RR(0x3f, 3)
2315 /* A VX form instruction. */
2316 #define VX(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x7ff))
2318 /* The mask for an VX form instruction. */
2319 #define VX_MASK VX(0x3f, 0x7ff)
2321 /* A VX_MASK with the VA field fixed. */
2322 #define VXVA_MASK (VX_MASK | (0x1f << 16))
2324 /* A VX_MASK with the VB field fixed. */
2325 #define VXVB_MASK (VX_MASK | (0x1f << 11))
2327 /* A VX_MASK with the VA and VB fields fixed. */
2328 #define VXVAVB_MASK (VX_MASK | (0x1f << 16) | (0x1f << 11))
2330 /* A VX_MASK with the VD and VA fields fixed. */
2331 #define VXVDVA_MASK (VX_MASK | (0x1f << 21) | (0x1f << 16))
2333 /* A VX_MASK with a UIMM4 field. */
2334 #define VXUIMM4_MASK (VX_MASK | (0x1 << 20))
2336 /* A VX_MASK with a UIMM3 field. */
2337 #define VXUIMM3_MASK (VX_MASK | (0x3 << 19))
2339 /* A VX_MASK with a UIMM2 field. */
2340 #define VXUIMM2_MASK (VX_MASK | (0x7 << 18))
2342 /* A VX_MASK with a PS field. */
2343 #define VXPS_MASK (VX_MASK & ~(0x1 << 9))
2345 /* A VA form instruction. */
2346 #define VXA(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x03f))
2348 /* The mask for an VA form instruction. */
2349 #define VXA_MASK VXA(0x3f, 0x3f)
2351 /* A VXA_MASK with a SHB field. */
2352 #define VXASHB_MASK (VXA_MASK | (1 << 10))
2354 /* A VXR form instruction. */
2355 #define VXR(op, xop, rc) (OP (op) | (((rc) & 1) << 10) | (((unsigned long)(xop)) & 0x3ff))
2357 /* The mask for a VXR form instruction. */
2358 #define VXR_MASK VXR(0x3f, 0x3ff, 1)
2360 /* An X form instruction. */
2361 #define X(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x3ff) << 1))
2363 /* An EX form instruction. */
2364 #define EX(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x7ff))
2366 /* The mask for an EX form instruction. */
2367 #define EX_MASK EX (0x3f, 0x7ff)
2369 /* An XX2 form instruction. */
2370 #define XX2(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x1ff) << 2))
2372 /* An XX3 form instruction. */
2373 #define XX3(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0xff) << 3))
2375 /* An XX3 form instruction with the RC bit specified. */
2376 #define XX3RC(op, xop, rc) (OP (op) | (((rc) & 1) << 10) | ((((unsigned long)(xop)) & 0x7f) << 3))
2378 /* An XX4 form instruction. */
2379 #define XX4(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x3) << 4))
2381 /* A Z form instruction. */
2382 #define Z(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x1ff) << 1))
2384 /* An X form instruction with the RC bit specified. */
2385 #define XRC(op, xop, rc) (X ((op), (xop)) | ((rc) & 1))
2387 /* A Z form instruction with the RC bit specified. */
2388 #define ZRC(op, xop, rc) (Z ((op), (xop)) | ((rc) & 1))
2390 /* The mask for an X form instruction. */
2391 #define X_MASK XRC (0x3f, 0x3ff, 1)
2393 /* An X form wait instruction with everything filled in except the WC field. */
2394 #define XWC_MASK (XRC (0x3f, 0x3ff, 1) | (7 << 23) | RA_MASK | RB_MASK)
2396 /* The mask for an XX1 form instruction. */
2397 #define XX1_MASK X (0x3f, 0x3ff)
2399 /* An XX1_MASK with the RB field fixed. */
2400 #define XX1RB_MASK (XX1_MASK | RB_MASK)
2402 /* The mask for an XX2 form instruction. */
2403 #define XX2_MASK (XX2 (0x3f, 0x1ff) | (0x1f << 16))
2405 /* The mask for an XX2 form instruction with the UIM bits specified. */
2406 #define XX2UIM_MASK (XX2 (0x3f, 0x1ff) | (7 << 18))
2408 /* The mask for an XX2 form instruction with the BF bits specified. */
2409 #define XX2BF_MASK (XX2_MASK | (3 << 21) | (1))
2411 /* The mask for an XX3 form instruction. */
2412 #define XX3_MASK XX3 (0x3f, 0xff)
2414 /* The mask for an XX3 form instruction with the BF bits specified. */
2415 #define XX3BF_MASK (XX3 (0x3f, 0xff) | (3 << 21) | (1))
2417 /* The mask for an XX3 form instruction with the DM or SHW bits specified. */
2418 #define XX3DM_MASK (XX3 (0x3f, 0x1f) | (1 << 10))
2419 #define XX3SHW_MASK XX3DM_MASK
2421 /* The mask for an XX4 form instruction. */
2422 #define XX4_MASK XX4 (0x3f, 0x3)
2424 /* An X form wait instruction with everything filled in except the WC field. */
2425 #define XWC_MASK (XRC (0x3f, 0x3ff, 1) | (7 << 23) | RA_MASK | RB_MASK)
2427 /* The mask for a Z form instruction. */
2428 #define Z_MASK ZRC (0x3f, 0x1ff, 1)
2429 #define Z2_MASK ZRC (0x3f, 0xff, 1)
2431 /* An X_MASK with the RA field fixed. */
2432 #define XRA_MASK (X_MASK | RA_MASK)
2434 /* An XRA_MASK with the W field clear. */
2435 #define XWRA_MASK (XRA_MASK & ~((unsigned long) 1 << 16))
2437 /* An X_MASK with the RB field fixed. */
2438 #define XRB_MASK (X_MASK | RB_MASK)
2440 /* An X_MASK with the RT field fixed. */
2441 #define XRT_MASK (X_MASK | RT_MASK)
2443 /* An XRT_MASK mask with the L bits clear. */
2444 #define XLRT_MASK (XRT_MASK & ~((unsigned long) 0x3 << 21))
2446 /* An X_MASK with the RA and RB fields fixed. */
2447 #define XRARB_MASK (X_MASK | RA_MASK | RB_MASK)
2449 /* An XRARB_MASK, but with the L bit clear. */
2450 #define XRLARB_MASK (XRARB_MASK & ~((unsigned long) 1 << 16))
2452 /* An X_MASK with the RT and RA fields fixed. */
2453 #define XRTRA_MASK (X_MASK | RT_MASK | RA_MASK)
2455 /* An X_MASK with the RT and RB fields fixed. */
2456 #define XRTRB_MASK (X_MASK | RT_MASK | RB_MASK)
2458 /* An XRTRA_MASK, but with L bit clear. */
2459 #define XRTLRA_MASK (XRTRA_MASK & ~((unsigned long) 1 << 21))
2461 /* An X_MASK with the RT, RA and RB fields fixed. */
2462 #define XRTRARB_MASK (X_MASK | RT_MASK | RA_MASK | RB_MASK)
2464 /* An XRTRARB_MASK, but with L bit clear. */
2465 #define XRTLRARB_MASK (XRTRARB_MASK & ~((unsigned long) 1 << 21))
2467 /* An XRTRARB_MASK, but with A bit clear. */
2468 #define XRTARARB_MASK (XRTRARB_MASK & ~((unsigned long) 1 << 25))
2470 /* An XRTRARB_MASK, but with BF bits clear. */
2471 #define XRTBFRARB_MASK (XRTRARB_MASK & ~((unsigned long) 7 << 23))
2473 /* An X form instruction with the L bit specified. */
2474 #define XOPL(op, xop, l) (X ((op), (xop)) | ((((unsigned long)(l)) & 1) << 21))
2476 /* An X form instruction with the L bits specified. */
2477 #define XOPL2(op, xop, l) (X ((op), (xop)) | ((((unsigned long)(l)) & 3) << 21))
2479 /* An X form instruction with the L bit and RC bit specified. */
2480 #define XRCL(op, xop, l, rc) (XRC ((op), (xop), (rc)) | ((((unsigned long)(l)) & 1) << 21))
2482 /* An X form instruction with RT fields specified */
2483 #define XRT(op, xop, rt) (X ((op), (xop)) \
2484 | ((((unsigned long)(rt)) & 0x1f) << 21))
2486 /* An X form instruction with RT and RA fields specified */
2487 #define XRTRA(op, xop, rt, ra) (X ((op), (xop)) \
2488 | ((((unsigned long)(rt)) & 0x1f) << 21) \
2489 | ((((unsigned long)(ra)) & 0x1f) << 16))
2491 /* The mask for an X form comparison instruction. */
2492 #define XCMP_MASK (X_MASK | (((unsigned long)1) << 22))
2494 /* The mask for an X form comparison instruction with the L field
2496 #define XCMPL_MASK (XCMP_MASK | (((unsigned long)1) << 21))
2498 /* An X form trap instruction with the TO field specified. */
2499 #define XTO(op, xop, to) (X ((op), (xop)) | ((((unsigned long)(to)) & 0x1f) << 21))
2500 #define XTO_MASK (X_MASK | TO_MASK)
2502 /* An X form tlb instruction with the SH field specified. */
2503 #define XTLB(op, xop, sh) (X ((op), (xop)) | ((((unsigned long)(sh)) & 0x1f) << 11))
2504 #define XTLB_MASK (X_MASK | SH_MASK)
2506 /* An X form sync instruction. */
2507 #define XSYNC(op, xop, l) (X ((op), (xop)) | ((((unsigned long)(l)) & 3) << 21))
2509 /* An X form sync instruction with everything filled in except the LS field. */
2510 #define XSYNC_MASK (0xff9fffff)
2512 /* An X form sync instruction with everything filled in except the L and E fields. */
2513 #define XSYNCLE_MASK (0xff90ffff)
2515 /* An X_MASK, but with the EH bit clear. */
2516 #define XEH_MASK (X_MASK & ~((unsigned long )1))
2518 /* An X form AltiVec dss instruction. */
2519 #define XDSS(op, xop, a) (X ((op), (xop)) | ((((unsigned long)(a)) & 1) << 25))
2520 #define XDSS_MASK XDSS(0x3f, 0x3ff, 1)
2522 /* An XFL form instruction. */
2523 #define XFL(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0x3ff) << 1) | (((unsigned long)(rc)) & 1))
2524 #define XFL_MASK XFL (0x3f, 0x3ff, 1)
2526 /* An X form isel instruction. */
2527 #define XISEL(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x1f) << 1))
2528 #define XISEL_MASK XISEL(0x3f, 0x1f)
2530 /* An XL form instruction with the LK field set to 0. */
2531 #define XL(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x3ff) << 1))
2533 /* An XL form instruction which uses the LK field. */
2534 #define XLLK(op, xop, lk) (XL ((op), (xop)) | ((lk) & 1))
2536 /* The mask for an XL form instruction. */
2537 #define XL_MASK XLLK (0x3f, 0x3ff, 1)
2539 /* An XL_MASK with the RT, RA and RB fields fixed, but S bit clear. */
2540 #define XLS_MASK ((XL_MASK | RT_MASK | RA_MASK | RB_MASK) & ~(1 << 11))
2542 /* An XL form instruction which explicitly sets the BO field. */
2543 #define XLO(op, bo, xop, lk) \
2544 (XLLK ((op), (xop), (lk)) | ((((unsigned long)(bo)) & 0x1f) << 21))
2545 #define XLO_MASK (XL_MASK | BO_MASK)
2547 /* An XL form instruction which explicitly sets the y bit of the BO
2549 #define XLYLK(op, xop, y, lk) (XLLK ((op), (xop), (lk)) | ((((unsigned long)(y)) & 1) << 21))
2550 #define XLYLK_MASK (XL_MASK | Y_MASK)
2552 /* An XL form instruction which sets the BO field and the condition
2553 bits of the BI field. */
2554 #define XLOCB(op, bo, cb, xop, lk) \
2555 (XLO ((op), (bo), (xop), (lk)) | ((((unsigned long)(cb)) & 3) << 16))
2556 #define XLOCB_MASK XLOCB (0x3f, 0x1f, 0x3, 0x3ff, 1)
2558 /* An XL_MASK or XLYLK_MASK or XLOCB_MASK with the BB field fixed. */
2559 #define XLBB_MASK (XL_MASK | BB_MASK)
2560 #define XLYBB_MASK (XLYLK_MASK | BB_MASK)
2561 #define XLBOCBBB_MASK (XLOCB_MASK | BB_MASK)
2563 /* A mask for branch instructions using the BH field. */
2564 #define XLBH_MASK (XL_MASK | (0x1c << 11))
2566 /* An XL_MASK with the BO and BB fields fixed. */
2567 #define XLBOBB_MASK (XL_MASK | BO_MASK | BB_MASK)
2569 /* An XL_MASK with the BO, BI and BB fields fixed. */
2570 #define XLBOBIBB_MASK (XL_MASK | BO_MASK | BI_MASK | BB_MASK)
2572 /* An X form mbar instruction with MO field. */
2573 #define XMBAR(op, xop, mo) (X ((op), (xop)) | ((((unsigned long)(mo)) & 1) << 21))
2575 /* An XO form instruction. */
2576 #define XO(op, xop, oe, rc) \
2577 (OP (op) | ((((unsigned long)(xop)) & 0x1ff) << 1) | ((((unsigned long)(oe)) & 1) << 10) | (((unsigned long)(rc)) & 1))
2578 #define XO_MASK XO (0x3f, 0x1ff, 1, 1)
2580 /* An XO_MASK with the RB field fixed. */
2581 #define XORB_MASK (XO_MASK | RB_MASK)
2583 /* An XOPS form instruction for paired singles. */
2584 #define XOPS(op, xop, rc) \
2585 (OP (op) | ((((unsigned long)(xop)) & 0x3ff) << 1) | (((unsigned long)(rc)) & 1))
2586 #define XOPS_MASK XOPS (0x3f, 0x3ff, 1)
2589 /* An XS form instruction. */
2590 #define XS(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0x1ff) << 2) | (((unsigned long)(rc)) & 1))
2591 #define XS_MASK XS (0x3f, 0x1ff, 1)
2593 /* A mask for the FXM version of an XFX form instruction. */
2594 #define XFXFXM_MASK (X_MASK | (1 << 11) | (1 << 20))
2596 /* An XFX form instruction with the FXM field filled in. */
2597 #define XFXM(op, xop, fxm, p4) \
2598 (X ((op), (xop)) | ((((unsigned long)(fxm)) & 0xff) << 12) \
2599 | ((unsigned long)(p4) << 20))
2601 /* An XFX form instruction with the SPR field filled in. */
2602 #define XSPR(op, xop, spr) \
2603 (X ((op), (xop)) | ((((unsigned long)(spr)) & 0x1f) << 16) | ((((unsigned long)(spr)) & 0x3e0) << 6))
2604 #define XSPR_MASK (X_MASK | SPR_MASK)
2606 /* An XFX form instruction with the SPR field filled in except for the
2608 #define XSPRBAT_MASK (XSPR_MASK &~ SPRBAT_MASK)
2610 /* An XFX form instruction with the SPR field filled in except for the
2612 #define XSPRG_MASK (XSPR_MASK & ~(0x1f << 16))
2614 /* An X form instruction with everything filled in except the E field. */
2615 #define XE_MASK (0xffff7fff)
2617 /* An X form user context instruction. */
2618 #define XUC(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x1f))
2619 #define XUC_MASK XUC(0x3f, 0x1f)
2621 /* An XW form instruction. */
2622 #define XW(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0x3f) << 1) | ((rc) & 1))
2623 /* The mask for a G form instruction. rc not supported at present. */
2624 #define XW_MASK XW (0x3f, 0x3f, 0)
2626 /* An APU form instruction. */
2627 #define APU(op, xop, rc) (OP (op) | (((unsigned long)(xop)) & 0x3ff) << 1 | ((rc) & 1))
2629 /* The mask for an APU form instruction. */
2630 #define APU_MASK APU (0x3f, 0x3ff, 1)
2631 #define APU_RT_MASK (APU_MASK | RT_MASK)
2632 #define APU_RA_MASK (APU_MASK | RA_MASK)
2634 /* The BO encodings used in extended conditional branch mnemonics. */
2635 #define BODNZF (0x0)
2636 #define BODNZFP (0x1)
2638 #define BODZFP (0x3)
2639 #define BODNZT (0x8)
2640 #define BODNZTP (0x9)
2642 #define BODZTP (0xb)
2653 #define BODNZ (0x10)
2654 #define BODNZP (0x11)
2656 #define BODZP (0x13)
2657 #define BODNZM4 (0x18)
2658 #define BODNZP4 (0x19)
2659 #define BODZM4 (0x1a)
2660 #define BODZP4 (0x1b)
2664 /* The BO16 encodings used in extended VLE conditional branch mnemonics. */
2668 /* The BO32 encodings used in extended VLE conditional branch mnemonics. */
2671 #define BO32DNZ (0x2)
2672 #define BO32DZ (0x3)
2674 /* The BI condition bit encodings used in extended conditional branch
2681 /* The TO encodings used in extended trap mnemonics. */
2698 /* Smaller names for the flags so each entry in the opcodes table will
2699 fit on a single line. */
2702 #define PPC PPC_OPCODE_PPC
2703 #define PPCCOM PPC_OPCODE_PPC | PPC_OPCODE_COMMON
2704 #define POWER4 PPC_OPCODE_POWER4
2705 #define POWER5 PPC_OPCODE_POWER5
2706 #define POWER6 PPC_OPCODE_POWER6
2707 #define POWER7 PPC_OPCODE_POWER7
2708 #define POWER8 PPC_OPCODE_POWER8
2709 #define CELL PPC_OPCODE_CELL
2710 #define PPC64 PPC_OPCODE_64 | PPC_OPCODE_64_BRIDGE
2711 #define NON32 (PPC_OPCODE_64 | PPC_OPCODE_POWER4 \
2712 | PPC_OPCODE_EFS | PPC_OPCODE_E500MC | PPC_OPCODE_TITAN)
2713 #define PPC403 PPC_OPCODE_403
2714 #define PPC405 PPC_OPCODE_405
2715 #define PPC440 PPC_OPCODE_440
2716 #define PPC464 PPC440
2717 #define PPC476 PPC_OPCODE_476
2721 #define PPCPS PPC_OPCODE_PPCPS
2722 #define PPCVEC PPC_OPCODE_ALTIVEC
2723 #define PPCVEC2 PPC_OPCODE_ALTIVEC2
2724 #define PPCVSX PPC_OPCODE_VSX
2725 #define PPCVSX2 PPC_OPCODE_VSX
2726 #define POWER PPC_OPCODE_POWER
2727 #define POWER2 PPC_OPCODE_POWER | PPC_OPCODE_POWER2
2728 #define PWR2COM PPC_OPCODE_POWER | PPC_OPCODE_POWER2 | PPC_OPCODE_COMMON
2729 #define PPCPWR2 PPC_OPCODE_PPC | PPC_OPCODE_POWER | PPC_OPCODE_POWER2 | PPC_OPCODE_COMMON
2730 #define COM PPC_OPCODE_POWER | PPC_OPCODE_PPC | PPC_OPCODE_COMMON
2731 #define M601 PPC_OPCODE_POWER | PPC_OPCODE_601
2732 #define PWRCOM PPC_OPCODE_POWER | PPC_OPCODE_601 | PPC_OPCODE_COMMON
2733 #define MFDEC1 PPC_OPCODE_POWER
2734 #define MFDEC2 PPC_OPCODE_PPC | PPC_OPCODE_601 | PPC_OPCODE_BOOKE | PPC_OPCODE_TITAN
2735 #define BOOKE PPC_OPCODE_BOOKE
2736 #define NO371 PPC_OPCODE_BOOKE | PPC_OPCODE_PPCPS | PPC_OPCODE_EFS | PPC_OPCODE_VLE
2737 #define PPCE300 PPC_OPCODE_E300
2738 #define PPCSPE PPC_OPCODE_SPE | PPC_OPCODE_VLE
2739 #define PPCISEL PPC_OPCODE_ISEL | PPC_OPCODE_VLE
2740 #define PPCEFS PPC_OPCODE_EFS | PPC_OPCODE_VLE
2741 #define PPCBRLK PPC_OPCODE_BRLOCK
2742 #define PPCPMR PPC_OPCODE_PMR
2743 #define PPCTMR PPC_OPCODE_TMR
2744 #define PPCCHLK PPC_OPCODE_CACHELCK
2745 #define PPCRFMCI PPC_OPCODE_RFMCI
2746 #define E500MC PPC_OPCODE_E500MC
2747 #define PPCA2 PPC_OPCODE_A2
2748 #define TITAN PPC_OPCODE_TITAN
2749 #define MULHW PPC_OPCODE_405 | PPC_OPCODE_440 | TITAN | PPC_OPCODE_VLE
2750 #define E500 PPC_OPCODE_E500
2751 #define E6500 PPC_OPCODE_E6500
2752 #define PPCVLE PPC_OPCODE_VLE
2753 #define PPCHTM PPC_OPCODE_HTM
2755 /* The opcode table.
2757 The format of the opcode table is:
2759 NAME OPCODE MASK FLAGS ANTI {OPERANDS}
2761 NAME is the name of the instruction.
2762 OPCODE is the instruction opcode.
2763 MASK is the opcode mask; this is used to tell the disassembler
2764 which bits in the actual opcode must match OPCODE.
2765 FLAGS are flags indicating which processors support the instruction.
2766 ANTI indicates which processors don't support the instruction.
2767 OPERANDS is the list of operands.
2769 The disassembler reads the table in order and prints the first
2770 instruction which matches, so this table is sorted to put more
2771 specific instructions before more general instructions.
2773 This table must be sorted by major opcode. Please try to keep it
2774 vaguely sorted within major opcode too, except of course where
2775 constrained otherwise by disassembler operation. */
2777 const struct powerpc_opcode powerpc_opcodes
[] = {
2778 {"attn", X(0,256), X_MASK
, POWER4
|PPCA2
, PPC476
, {0}},
2779 {"tdlgti", OPTO(2,TOLGT
), OPTO_MASK
, PPC64
, PPCNONE
, {RA
, SI
}},
2780 {"tdllti", OPTO(2,TOLLT
), OPTO_MASK
, PPC64
, PPCNONE
, {RA
, SI
}},
2781 {"tdeqi", OPTO(2,TOEQ
), OPTO_MASK
, PPC64
, PPCNONE
, {RA
, SI
}},
2782 {"tdlgei", OPTO(2,TOLGE
), OPTO_MASK
, PPC64
, PPCNONE
, {RA
, SI
}},
2783 {"tdlnli", OPTO(2,TOLNL
), OPTO_MASK
, PPC64
, PPCNONE
, {RA
, SI
}},
2784 {"tdllei", OPTO(2,TOLLE
), OPTO_MASK
, PPC64
, PPCNONE
, {RA
, SI
}},
2785 {"tdlngi", OPTO(2,TOLNG
), OPTO_MASK
, PPC64
, PPCNONE
, {RA
, SI
}},
2786 {"tdgti", OPTO(2,TOGT
), OPTO_MASK
, PPC64
, PPCNONE
, {RA
, SI
}},
2787 {"tdgei", OPTO(2,TOGE
), OPTO_MASK
, PPC64
, PPCNONE
, {RA
, SI
}},
2788 {"tdnli", OPTO(2,TONL
), OPTO_MASK
, PPC64
, PPCNONE
, {RA
, SI
}},
2789 {"tdlti", OPTO(2,TOLT
), OPTO_MASK
, PPC64
, PPCNONE
, {RA
, SI
}},
2790 {"tdlei", OPTO(2,TOLE
), OPTO_MASK
, PPC64
, PPCNONE
, {RA
, SI
}},
2791 {"tdngi", OPTO(2,TONG
), OPTO_MASK
, PPC64
, PPCNONE
, {RA
, SI
}},
2792 {"tdnei", OPTO(2,TONE
), OPTO_MASK
, PPC64
, PPCNONE
, {RA
, SI
}},
2793 {"tdui", OPTO(2,TOU
), OPTO_MASK
, PPC64
, PPCNONE
, {RA
, SI
}},
2794 {"tdi", OP(2), OP_MASK
, PPC64
, PPCNONE
, {TO
, RA
, SI
}},
2796 {"twlgti", OPTO(3,TOLGT
), OPTO_MASK
, PPCCOM
, PPCNONE
, {RA
, SI
}},
2797 {"tlgti", OPTO(3,TOLGT
), OPTO_MASK
, PWRCOM
, PPCNONE
, {RA
, SI
}},
2798 {"twllti", OPTO(3,TOLLT
), OPTO_MASK
, PPCCOM
, PPCNONE
, {RA
, SI
}},
2799 {"tllti", OPTO(3,TOLLT
), OPTO_MASK
, PWRCOM
, PPCNONE
, {RA
, SI
}},
2800 {"tweqi", OPTO(3,TOEQ
), OPTO_MASK
, PPCCOM
, PPCNONE
, {RA
, SI
}},
2801 {"teqi", OPTO(3,TOEQ
), OPTO_MASK
, PWRCOM
, PPCNONE
, {RA
, SI
}},
2802 {"twlgei", OPTO(3,TOLGE
), OPTO_MASK
, PPCCOM
, PPCNONE
, {RA
, SI
}},
2803 {"tlgei", OPTO(3,TOLGE
), OPTO_MASK
, PWRCOM
, PPCNONE
, {RA
, SI
}},
2804 {"twlnli", OPTO(3,TOLNL
), OPTO_MASK
, PPCCOM
, PPCNONE
, {RA
, SI
}},
2805 {"tlnli", OPTO(3,TOLNL
), OPTO_MASK
, PWRCOM
, PPCNONE
, {RA
, SI
}},
2806 {"twllei", OPTO(3,TOLLE
), OPTO_MASK
, PPCCOM
, PPCNONE
, {RA
, SI
}},
2807 {"tllei", OPTO(3,TOLLE
), OPTO_MASK
, PWRCOM
, PPCNONE
, {RA
, SI
}},
2808 {"twlngi", OPTO(3,TOLNG
), OPTO_MASK
, PPCCOM
, PPCNONE
, {RA
, SI
}},
2809 {"tlngi", OPTO(3,TOLNG
), OPTO_MASK
, PWRCOM
, PPCNONE
, {RA
, SI
}},
2810 {"twgti", OPTO(3,TOGT
), OPTO_MASK
, PPCCOM
, PPCNONE
, {RA
, SI
}},
2811 {"tgti", OPTO(3,TOGT
), OPTO_MASK
, PWRCOM
, PPCNONE
, {RA
, SI
}},
2812 {"twgei", OPTO(3,TOGE
), OPTO_MASK
, PPCCOM
, PPCNONE
, {RA
, SI
}},
2813 {"tgei", OPTO(3,TOGE
), OPTO_MASK
, PWRCOM
, PPCNONE
, {RA
, SI
}},
2814 {"twnli", OPTO(3,TONL
), OPTO_MASK
, PPCCOM
, PPCNONE
, {RA
, SI
}},
2815 {"tnli", OPTO(3,TONL
), OPTO_MASK
, PWRCOM
, PPCNONE
, {RA
, SI
}},
2816 {"twlti", OPTO(3,TOLT
), OPTO_MASK
, PPCCOM
, PPCNONE
, {RA
, SI
}},
2817 {"tlti", OPTO(3,TOLT
), OPTO_MASK
, PWRCOM
, PPCNONE
, {RA
, SI
}},
2818 {"twlei", OPTO(3,TOLE
), OPTO_MASK
, PPCCOM
, PPCNONE
, {RA
, SI
}},
2819 {"tlei", OPTO(3,TOLE
), OPTO_MASK
, PWRCOM
, PPCNONE
, {RA
, SI
}},
2820 {"twngi", OPTO(3,TONG
), OPTO_MASK
, PPCCOM
, PPCNONE
, {RA
, SI
}},
2821 {"tngi", OPTO(3,TONG
), OPTO_MASK
, PWRCOM
, PPCNONE
, {RA
, SI
}},
2822 {"twnei", OPTO(3,TONE
), OPTO_MASK
, PPCCOM
, PPCNONE
, {RA
, SI
}},
2823 {"tnei", OPTO(3,TONE
), OPTO_MASK
, PWRCOM
, PPCNONE
, {RA
, SI
}},
2824 {"twui", OPTO(3,TOU
), OPTO_MASK
, PPCCOM
, PPCNONE
, {RA
, SI
}},
2825 {"tui", OPTO(3,TOU
), OPTO_MASK
, PWRCOM
, PPCNONE
, {RA
, SI
}},
2826 {"twi", OP(3), OP_MASK
, PPCCOM
, PPCNONE
, {TO
, RA
, SI
}},
2827 {"ti", OP(3), OP_MASK
, PWRCOM
, PPCNONE
, {TO
, RA
, SI
}},
2829 {"ps_cmpu0", X (4, 0), X_MASK
|(3<<21), PPCPS
, PPCNONE
, {BF
, FRA
, FRB
}},
2830 {"vaddubm", VX (4, 0), VX_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
2831 {"vmaxub", VX (4, 2), VX_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
2832 {"vrlb", VX (4, 4), VX_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
2833 {"vcmpequb", VXR(4, 6,0), VXR_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
2834 {"vmuloub", VX (4, 8), VX_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
2835 {"vaddfp", VX (4, 10), VX_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
2836 {"psq_lx", XW (4, 6,0), XW_MASK
, PPCPS
, PPCNONE
, {FRT
,RA
,RB
,PSWM
,PSQM
}},
2837 {"vmrghb", VX (4, 12), VX_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
2838 {"psq_stx", XW (4, 7,0), XW_MASK
, PPCPS
, PPCNONE
, {FRS
,RA
,RB
,PSWM
,PSQM
}},
2839 {"vpkuhum", VX (4, 14), VX_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
2840 {"mulhhwu", XRC(4, 8,0), X_MASK
, MULHW
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
2841 {"mulhhwu.", XRC(4, 8,1), X_MASK
, MULHW
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
2842 {"ps_sum0", A (4, 10,0), A_MASK
, PPCPS
, PPCNONE
, {FRT
, FRA
, FRC
, FRB
}},
2843 {"ps_sum0.", A (4, 10,1), A_MASK
, PPCPS
, PPCNONE
, {FRT
, FRA
, FRC
, FRB
}},
2844 {"ps_sum1", A (4, 11,0), A_MASK
, PPCPS
, PPCNONE
, {FRT
, FRA
, FRC
, FRB
}},
2845 {"ps_sum1.", A (4, 11,1), A_MASK
, PPCPS
, PPCNONE
, {FRT
, FRA
, FRC
, FRB
}},
2846 {"ps_muls0", A (4, 12,0), AFRB_MASK
, PPCPS
, PPCNONE
, {FRT
, FRA
, FRC
}},
2847 {"machhwu", XO (4, 12,0,0),XO_MASK
, MULHW
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
2848 {"ps_muls0.", A (4, 12,1), AFRB_MASK
, PPCPS
, PPCNONE
, {FRT
, FRA
, FRC
}},
2849 {"machhwu.", XO (4, 12,0,1),XO_MASK
, MULHW
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
2850 {"ps_muls1", A (4, 13,0), AFRB_MASK
, PPCPS
, PPCNONE
, {FRT
, FRA
, FRC
}},
2851 {"ps_muls1.", A (4, 13,1), AFRB_MASK
, PPCPS
, PPCNONE
, {FRT
, FRA
, FRC
}},
2852 {"ps_madds0", A (4, 14,0), A_MASK
, PPCPS
, PPCNONE
, {FRT
, FRA
, FRC
, FRB
}},
2853 {"ps_madds0.", A (4, 14,1), A_MASK
, PPCPS
, PPCNONE
, {FRT
, FRA
, FRC
, FRB
}},
2854 {"ps_madds1", A (4, 15,0), A_MASK
, PPCPS
, PPCNONE
, {FRT
, FRA
, FRC
, FRB
}},
2855 {"ps_madds1.", A (4, 15,1), A_MASK
, PPCPS
, PPCNONE
, {FRT
, FRA
, FRC
, FRB
}},
2856 {"vmhaddshs", VXA(4, 32), VXA_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
, VC
}},
2857 {"vmhraddshs", VXA(4, 33), VXA_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
, VC
}},
2858 {"vmladduhm", VXA(4, 34), VXA_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
, VC
}},
2859 {"ps_div", A (4, 18,0), AFRC_MASK
, PPCPS
, PPCNONE
, {FRT
, FRA
, FRB
}},
2860 {"vmsumubm", VXA(4, 36), VXA_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
, VC
}},
2861 {"ps_div.", A (4, 18,1), AFRC_MASK
, PPCPS
, PPCNONE
, {FRT
, FRA
, FRB
}},
2862 {"vmsummbm", VXA(4, 37), VXA_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
, VC
}},
2863 {"vmsumuhm", VXA(4, 38), VXA_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
, VC
}},
2864 {"vmsumuhs", VXA(4, 39), VXA_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
, VC
}},
2865 {"ps_sub", A (4, 20,0), AFRC_MASK
, PPCPS
, PPCNONE
, {FRT
, FRA
, FRB
}},
2866 {"vmsumshm", VXA(4, 40), VXA_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
, VC
}},
2867 {"ps_sub.", A (4, 20,1), AFRC_MASK
, PPCPS
, PPCNONE
, {FRT
, FRA
, FRB
}},
2868 {"vmsumshs", VXA(4, 41), VXA_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
, VC
}},
2869 {"ps_add", A (4, 21,0), AFRC_MASK
, PPCPS
, PPCNONE
, {FRT
, FRA
, FRB
}},
2870 {"vsel", VXA(4, 42), VXA_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
, VC
}},
2871 {"ps_add.", A (4, 21,1), AFRC_MASK
, PPCPS
, PPCNONE
, {FRT
, FRA
, FRB
}},
2872 {"vperm", VXA(4, 43), VXA_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
, VC
}},
2873 {"vsldoi", VXA(4, 44), VXASHB_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
, SHB
}},
2874 {"ps_sel", A (4, 23,0), A_MASK
, PPCPS
, PPCNONE
, {FRT
, FRA
, FRC
, FRB
}},
2875 {"vpermxor", VXA(4, 45), VXA_MASK
, PPCVEC2
, PPCNONE
, {VD
, VA
, VB
, VC
}},
2876 {"vmaddfp", VXA(4, 46), VXA_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VC
, VB
}},
2877 {"ps_sel.", A (4, 23,1), A_MASK
, PPCPS
, PPCNONE
, {FRT
, FRA
, FRC
, FRB
}},
2878 {"vnmsubfp", VXA(4, 47), VXA_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VC
, VB
}},
2879 {"ps_res", A (4, 24,0), AFRAFRC_MASK
, PPCPS
, PPCNONE
, {FRT
, FRB
}},
2880 {"ps_res.", A (4, 24,1), AFRAFRC_MASK
, PPCPS
, PPCNONE
, {FRT
, FRB
}},
2881 {"ps_mul", A (4, 25,0), AFRB_MASK
, PPCPS
, PPCNONE
, {FRT
, FRA
, FRC
}},
2882 {"ps_mul.", A (4, 25,1), AFRB_MASK
, PPCPS
, PPCNONE
, {FRT
, FRA
, FRC
}},
2883 {"ps_rsqrte", A (4, 26,0), AFRAFRC_MASK
, PPCPS
, PPCNONE
, {FRT
, FRB
}},
2884 {"ps_rsqrte.", A (4, 26,1), AFRAFRC_MASK
, PPCPS
, PPCNONE
, {FRT
, FRB
}},
2885 {"ps_msub", A (4, 28,0), A_MASK
, PPCPS
, PPCNONE
, {FRT
, FRA
, FRC
, FRB
}},
2886 {"ps_msub.", A (4, 28,1), A_MASK
, PPCPS
, PPCNONE
, {FRT
, FRA
, FRC
, FRB
}},
2887 {"ps_madd", A (4, 29,0), A_MASK
, PPCPS
, PPCNONE
, {FRT
, FRA
, FRC
, FRB
}},
2888 {"ps_madd.", A (4, 29,1), A_MASK
, PPCPS
, PPCNONE
, {FRT
, FRA
, FRC
, FRB
}},
2889 {"ps_nmsub", A (4, 30,0), A_MASK
, PPCPS
, PPCNONE
, {FRT
, FRA
, FRC
, FRB
}},
2890 {"ps_nmsub.", A (4, 30,1), A_MASK
, PPCPS
, PPCNONE
, {FRT
, FRA
, FRC
, FRB
}},
2891 {"ps_nmadd", A (4, 31,0), A_MASK
, PPCPS
, PPCNONE
, {FRT
, FRA
, FRC
, FRB
}},
2892 {"ps_nmadd.", A (4, 31,1), A_MASK
, PPCPS
, PPCNONE
, {FRT
, FRA
, FRC
, FRB
}},
2893 {"ps_cmpo0", X (4, 32), X_MASK
|(3<<21), PPCPS
, PPCNONE
, {BF
, FRA
, FRB
}},
2894 {"vaddeuqm", VXA(4, 60), VXA_MASK
, PPCVEC2
, PPCNONE
, {VD
, VA
, VB
, VC
}},
2895 {"vaddecuq", VXA(4, 61), VXA_MASK
, PPCVEC2
, PPCNONE
, {VD
, VA
, VB
, VC
}},
2896 {"vsubeuqm", VXA(4, 62), VXA_MASK
, PPCVEC2
, PPCNONE
, {VD
, VA
, VB
, VC
}},
2897 {"vsubecuq", VXA(4, 63), VXA_MASK
, PPCVEC2
, PPCNONE
, {VD
, VA
, VB
, VC
}},
2898 {"vadduhm", VX (4, 64), VX_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
2899 {"vmaxuh", VX (4, 66), VX_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
2900 {"vrlh", VX (4, 68), VX_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
2901 {"vcmpequh", VXR(4, 70,0), VXR_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
2902 {"vmulouh", VX (4, 72), VX_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
2903 {"vsubfp", VX (4, 74), VX_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
2904 {"psq_lux", XW (4, 38,0), XW_MASK
, PPCPS
, PPCNONE
, {FRT
,RA
,RB
,PSWM
,PSQM
}},
2905 {"vmrghh", VX (4, 76), VX_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
2906 {"psq_stux", XW (4, 39,0), XW_MASK
, PPCPS
, PPCNONE
, {FRS
,RA
,RB
,PSWM
,PSQM
}},
2907 {"vpkuwum", VX (4, 78), VX_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
2908 {"ps_neg", XRC(4, 40,0), XRA_MASK
, PPCPS
, PPCNONE
, {FRT
, FRB
}},
2909 {"mulhhw", XRC(4, 40,0), X_MASK
, MULHW
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
2910 {"ps_neg.", XRC(4, 40,1), XRA_MASK
, PPCPS
, PPCNONE
, {FRT
, FRB
}},
2911 {"mulhhw.", XRC(4, 40,1), X_MASK
, MULHW
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
2912 {"machhw", XO (4, 44,0,0),XO_MASK
, MULHW
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
2913 {"machhw.", XO (4, 44,0,1),XO_MASK
, MULHW
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
2914 {"nmachhw", XO (4, 46,0,0),XO_MASK
, MULHW
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
2915 {"nmachhw.", XO (4, 46,0,1),XO_MASK
, MULHW
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
2916 {"ps_cmpu1", X (4, 64), X_MASK
|(3<<21), PPCPS
, PPCNONE
, {BF
, FRA
, FRB
}},
2917 {"vadduwm", VX (4, 128), VX_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
2918 {"vmaxuw", VX (4, 130), VX_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
2919 {"vrlw", VX (4, 132), VX_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
2920 {"vcmpequw", VXR(4, 134,0), VXR_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
2921 {"vmulouw", VX (4, 136), VX_MASK
, PPCVEC2
, PPCNONE
, {VD
, VA
, VB
}},
2922 {"vmuluwm", VX (4, 137), VX_MASK
, PPCVEC2
, PPCNONE
, {VD
, VA
, VB
}},
2923 {"vmrghw", VX (4, 140), VX_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
2924 {"vpkuhus", VX (4, 142), VX_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
2925 {"ps_mr", XRC(4, 72,0), XRA_MASK
, PPCPS
, PPCNONE
, {FRT
, FRB
}},
2926 {"ps_mr.", XRC(4, 72,1), XRA_MASK
, PPCPS
, PPCNONE
, {FRT
, FRB
}},
2927 {"machhwsu", XO (4, 76,0,0),XO_MASK
, MULHW
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
2928 {"machhwsu.", XO (4, 76,0,1),XO_MASK
, MULHW
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
2929 {"ps_cmpo1", X (4, 96), X_MASK
|(3<<21), PPCPS
, PPCNONE
, {BF
, FRA
, FRB
}},
2930 {"vaddudm", VX (4, 192), VX_MASK
, PPCVEC2
, PPCNONE
, {VD
, VA
, VB
}},
2931 {"vmaxud", VX (4, 194), VX_MASK
, PPCVEC2
, PPCNONE
, {VD
, VA
, VB
}},
2932 {"vrld", VX (4, 196), VX_MASK
, PPCVEC2
, PPCNONE
, {VD
, VA
, VB
}},
2933 {"vcmpeqfp", VXR(4, 198,0), VXR_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
2934 {"vcmpequd", VXR(4, 199,0), VXR_MASK
, PPCVEC2
, PPCNONE
, {VD
, VA
, VB
}},
2935 {"vpkuwus", VX (4, 206), VX_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
2936 {"machhws", XO (4, 108,0,0),XO_MASK
, MULHW
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
2937 {"machhws.", XO (4, 108,0,1),XO_MASK
, MULHW
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
2938 {"nmachhws", XO (4, 110,0,0),XO_MASK
, MULHW
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
2939 {"nmachhws.", XO (4, 110,0,1),XO_MASK
, MULHW
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
2940 {"vadduqm", VX (4, 256), VX_MASK
, PPCVEC2
, PPCNONE
, {VD
, VA
, VB
}},
2941 {"vmaxsb", VX (4, 258), VX_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
2942 {"vslb", VX (4, 260), VX_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
2943 {"vmulosb", VX (4, 264), VX_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
2944 {"vrefp", VX (4, 266), VXVA_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VB
}},
2945 {"vmrglb", VX (4, 268), VX_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
2946 {"vpkshus", VX (4, 270), VX_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
2947 {"ps_nabs", XRC(4, 136,0), XRA_MASK
, PPCPS
, PPCNONE
, {FRT
, FRB
}},
2948 {"mulchwu", XRC(4, 136,0), X_MASK
, MULHW
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
2949 {"ps_nabs.", XRC(4, 136,1), XRA_MASK
, PPCPS
, PPCNONE
, {FRT
, FRB
}},
2950 {"mulchwu.", XRC(4, 136,1), X_MASK
, MULHW
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
2951 {"macchwu", XO (4, 140,0,0),XO_MASK
, MULHW
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
2952 {"macchwu.", XO (4, 140,0,1),XO_MASK
, MULHW
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
2953 {"vaddcuq", VX (4, 320), VX_MASK
, PPCVEC2
, PPCNONE
, {VD
, VA
, VB
}},
2954 {"vmaxsh", VX (4, 322), VX_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
2955 {"vslh", VX (4, 324), VX_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
2956 {"vmulosh", VX (4, 328), VX_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
2957 {"vrsqrtefp", VX (4, 330), VXVA_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VB
}},
2958 {"vmrglh", VX (4, 332), VX_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
2959 {"vpkswus", VX (4, 334), VX_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
2960 {"mulchw", XRC(4, 168,0), X_MASK
, MULHW
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
2961 {"mulchw.", XRC(4, 168,1), X_MASK
, MULHW
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
2962 {"macchw", XO (4, 172,0,0),XO_MASK
, MULHW
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
2963 {"macchw.", XO (4, 172,0,1),XO_MASK
, MULHW
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
2964 {"nmacchw", XO (4, 174,0,0),XO_MASK
, MULHW
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
2965 {"nmacchw.", XO (4, 174,0,1),XO_MASK
, MULHW
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
2966 {"vaddcuw", VX (4, 384), VX_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
2967 {"vmaxsw", VX (4, 386), VX_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
2968 {"vslw", VX (4, 388), VX_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
2969 {"vmulosw", VX (4, 392), VX_MASK
, PPCVEC2
, PPCNONE
, {VD
, VA
, VB
}},
2970 {"vexptefp", VX (4, 394), VXVA_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VB
}},
2971 {"vmrglw", VX (4, 396), VX_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
2972 {"vpkshss", VX (4, 398), VX_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
2973 {"macchwsu", XO (4, 204,0,0),XO_MASK
, MULHW
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
2974 {"macchwsu.", XO (4, 204,0,1),XO_MASK
, MULHW
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
2975 {"vmaxsd", VX (4, 450), VX_MASK
, PPCVEC2
, PPCNONE
, {VD
, VA
, VB
}},
2976 {"vsl", VX (4, 452), VX_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
2977 {"vcmpgefp", VXR(4, 454,0), VXR_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
2978 {"vlogefp", VX (4, 458), VXVA_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VB
}},
2979 {"vpkswss", VX (4, 462), VX_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
2980 {"macchws", XO (4, 236,0,0),XO_MASK
, MULHW
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
2981 {"macchws.", XO (4, 236,0,1),XO_MASK
, MULHW
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
2982 {"nmacchws", XO (4, 238,0,0),XO_MASK
, MULHW
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
2983 {"nmacchws.", XO (4, 238,0,1),XO_MASK
, MULHW
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
2984 {"evaddw", VX (4, 512), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
2985 {"vaddubs", VX (4, 512), VX_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
2986 {"evaddiw", VX (4, 514), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RB
, UIMM
}},
2987 {"vminub", VX (4, 514), VX_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
2988 {"evsubfw", VX (4, 516), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
2989 {"evsubw", VX (4, 516), VX_MASK
, PPCSPE
, PPCNONE
, {RS
, RB
, RA
}},
2990 {"vsrb", VX (4, 516), VX_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
2991 {"evsubifw", VX (4, 518), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, UIMM
, RB
}},
2992 {"evsubiw", VX (4, 518), VX_MASK
, PPCSPE
, PPCNONE
, {RS
, RB
, UIMM
}},
2993 {"vcmpgtub", VXR(4, 518,0), VXR_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
2994 {"evabs", VX (4, 520), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
}},
2995 {"vmuleub", VX (4, 520), VX_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
2996 {"evneg", VX (4, 521), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
}},
2997 {"evextsb", VX (4, 522), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
}},
2998 {"vrfin", VX (4, 522), VXVA_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VB
}},
2999 {"evextsh", VX (4, 523), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
}},
3000 {"evrndw", VX (4, 524), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
}},
3001 {"vspltb", VX (4, 524), VXUIMM4_MASK
,PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VB
, UIMM4
}},
3002 {"evcntlzw", VX (4, 525), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
}},
3003 {"evcntlsw", VX (4, 526), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
}},
3004 {"vupkhsb", VX (4, 526), VXVA_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VB
}},
3005 {"brinc", VX (4, 527), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3006 {"ps_abs", XRC(4, 264,0), XRA_MASK
, PPCPS
, PPCNONE
, {FRT
, FRB
}},
3007 {"ps_abs.", XRC(4, 264,1), XRA_MASK
, PPCPS
, PPCNONE
, {FRT
, FRB
}},
3008 {"evand", VX (4, 529), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3009 {"evandc", VX (4, 530), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3010 {"evxor", VX (4, 534), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3011 {"evmr", VX (4, 535), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, BBA
}},
3012 {"evor", VX (4, 535), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3013 {"evnor", VX (4, 536), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3014 {"evnot", VX (4, 536), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, BBA
}},
3015 {"get", APU(4, 268,0), APU_RA_MASK
, PPC405
, PPCNONE
, {RT
, FSL
}},
3016 {"eveqv", VX (4, 537), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3017 {"evorc", VX (4, 539), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3018 {"evnand", VX (4, 542), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3019 {"evsrwu", VX (4, 544), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3020 {"evsrws", VX (4, 545), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3021 {"evsrwiu", VX (4, 546), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, EVUIMM
}},
3022 {"evsrwis", VX (4, 547), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, EVUIMM
}},
3023 {"evslw", VX (4, 548), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3024 {"evslwi", VX (4, 550), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, EVUIMM
}},
3025 {"evrlw", VX (4, 552), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3026 {"evsplati", VX (4, 553), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, SIMM
}},
3027 {"evrlwi", VX (4, 554), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, EVUIMM
}},
3028 {"evsplatfi", VX (4, 555), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, SIMM
}},
3029 {"evmergehi", VX (4, 556), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3030 {"evmergelo", VX (4, 557), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3031 {"evmergehilo", VX (4, 558), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3032 {"evmergelohi", VX (4, 559), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3033 {"evcmpgtu", VX (4, 560), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {CRFD
, RA
, RB
}},
3034 {"evcmpgts", VX (4, 561), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {CRFD
, RA
, RB
}},
3035 {"evcmpltu", VX (4, 562), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {CRFD
, RA
, RB
}},
3036 {"evcmplts", VX (4, 563), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {CRFD
, RA
, RB
}},
3037 {"evcmpeq", VX (4, 564), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {CRFD
, RA
, RB
}},
3038 {"cget", APU(4, 284,0), APU_RA_MASK
, PPC405
, PPCNONE
, {RT
, FSL
}},
3039 {"vadduhs", VX (4, 576), VX_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
3040 {"vminuh", VX (4, 578), VX_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
3041 {"vsrh", VX (4, 580), VX_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
3042 {"vcmpgtuh", VXR(4, 582,0), VXR_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
3043 {"vmuleuh", VX (4, 584), VX_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
3044 {"vrfiz", VX (4, 586), VXVA_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VB
}},
3045 {"vsplth", VX (4, 588), VXUIMM3_MASK
,PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VB
, UIMM3
}},
3046 {"vupkhsh", VX (4, 590), VXVA_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VB
}},
3047 {"nget", APU(4, 300,0), APU_RA_MASK
, PPC405
, PPCNONE
, {RT
, FSL
}},
3048 {"evsel", EVSEL(4,79), EVSEL_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
, CRFS
}},
3049 {"ncget", APU(4, 316,0), APU_RA_MASK
, PPC405
, PPCNONE
, {RT
, FSL
}},
3050 {"evfsadd", VX (4, 640), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3051 {"vadduws", VX (4, 640), VX_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
3052 {"evfssub", VX (4, 641), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3053 {"vminuw", VX (4, 642), VX_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
3054 {"evfsabs", VX (4, 644), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
}},
3055 {"vsrw", VX (4, 644), VX_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
3056 {"evfsnabs", VX (4, 645), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
}},
3057 {"evfsneg", VX (4, 646), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
}},
3058 {"vcmpgtuw", VXR(4, 646,0), VXR_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
3059 {"vmuleuw", VX (4, 648), VX_MASK
, PPCVEC2
, PPCNONE
, {VD
, VA
, VB
}},
3060 {"evfsmul", VX (4, 648), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3061 {"evfsdiv", VX (4, 649), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3062 {"vrfip", VX (4, 650), VXVA_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VB
}},
3063 {"evfscmpgt", VX (4, 652), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {CRFD
, RA
, RB
}},
3064 {"vspltw", VX (4, 652), VXUIMM2_MASK
,PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VB
, UIMM2
}},
3065 {"evfscmplt", VX (4, 653), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {CRFD
, RA
, RB
}},
3066 {"evfscmpeq", VX (4, 654), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {CRFD
, RA
, RB
}},
3067 {"vupklsb", VX (4, 654), VXVA_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VB
}},
3068 {"evfscfui", VX (4, 656), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RB
}},
3069 {"evfscfsi", VX (4, 657), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RB
}},
3070 {"evfscfuf", VX (4, 658), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RB
}},
3071 {"evfscfsf", VX (4, 659), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RB
}},
3072 {"evfsctui", VX (4, 660), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RB
}},
3073 {"evfsctsi", VX (4, 661), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RB
}},
3074 {"evfsctuf", VX (4, 662), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RB
}},
3075 {"evfsctsf", VX (4, 663), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RB
}},
3076 {"evfsctuiz", VX (4, 664), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RB
}},
3077 {"put", APU(4, 332,0), APU_RT_MASK
, PPC405
, PPCNONE
, {RA
, FSL
}},
3078 {"evfsctsiz", VX (4, 666), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RB
}},
3079 {"evfststgt", VX (4, 668), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {CRFD
, RA
, RB
}},
3080 {"evfststlt", VX (4, 669), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {CRFD
, RA
, RB
}},
3081 {"evfststeq", VX (4, 670), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {CRFD
, RA
, RB
}},
3082 {"cput", APU(4, 348,0), APU_RT_MASK
, PPC405
, PPCNONE
, {RA
, FSL
}},
3083 {"efsadd", VX (4, 704), VX_MASK
, PPCEFS
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3084 {"efssub", VX (4, 705), VX_MASK
, PPCEFS
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3085 {"vminud", VX (4, 706), VX_MASK
, PPCVEC2
, PPCNONE
, {VD
, VA
, VB
}},
3086 {"efsabs", VX (4, 708), VX_MASK
, PPCEFS
|PPCVLE
, PPCNONE
, {RS
, RA
}},
3087 {"vsr", VX (4, 708), VX_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
3088 {"efsnabs", VX (4, 709), VX_MASK
, PPCEFS
|PPCVLE
, PPCNONE
, {RS
, RA
}},
3089 {"efsneg", VX (4, 710), VX_MASK
, PPCEFS
|PPCVLE
, PPCNONE
, {RS
, RA
}},
3090 {"vcmpgtfp", VXR(4, 710,0), VXR_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
3091 {"vcmpgtud", VXR(4, 711,0), VXR_MASK
, PPCVEC2
, PPCNONE
, {VD
, VA
, VB
}},
3092 {"efsmul", VX (4, 712), VX_MASK
, PPCEFS
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3093 {"efsdiv", VX (4, 713), VX_MASK
, PPCEFS
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3094 {"vrfim", VX (4, 714), VXVA_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VB
}},
3095 {"efscmpgt", VX (4, 716), VX_MASK
, PPCEFS
|PPCVLE
, PPCNONE
, {CRFD
, RA
, RB
}},
3096 {"efscmplt", VX (4, 717), VX_MASK
, PPCEFS
|PPCVLE
, PPCNONE
, {CRFD
, RA
, RB
}},
3097 {"efscmpeq", VX (4, 718), VX_MASK
, PPCEFS
|PPCVLE
, PPCNONE
, {CRFD
, RA
, RB
}},
3098 {"vupklsh", VX (4, 718), VXVA_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VB
}},
3099 {"efscfd", VX (4, 719), VX_MASK
, PPCEFS
|PPCVLE
, PPCNONE
, {RS
, RB
}},
3100 {"efscfui", VX (4, 720), VX_MASK
, PPCEFS
|PPCVLE
, PPCNONE
, {RS
, RB
}},
3101 {"efscfsi", VX (4, 721), VX_MASK
, PPCEFS
|PPCVLE
, PPCNONE
, {RS
, RB
}},
3102 {"efscfuf", VX (4, 722), VX_MASK
, PPCEFS
|PPCVLE
, PPCNONE
, {RS
, RB
}},
3103 {"efscfsf", VX (4, 723), VX_MASK
, PPCEFS
|PPCVLE
, PPCNONE
, {RS
, RB
}},
3104 {"efsctui", VX (4, 724), VX_MASK
, PPCEFS
|PPCVLE
, PPCNONE
, {RS
, RB
}},
3105 {"efsctsi", VX (4, 725), VX_MASK
, PPCEFS
|PPCVLE
, PPCNONE
, {RS
, RB
}},
3106 {"efsctuf", VX (4, 726), VX_MASK
, PPCEFS
|PPCVLE
, PPCNONE
, {RS
, RB
}},
3107 {"efsctsf", VX (4, 727), VX_MASK
, PPCEFS
|PPCVLE
, PPCNONE
, {RS
, RB
}},
3108 {"efsctuiz", VX (4, 728), VX_MASK
, PPCEFS
|PPCVLE
, PPCNONE
, {RS
, RB
}},
3109 {"nput", APU(4, 364,0), APU_RT_MASK
, PPC405
, PPCNONE
, {RA
, FSL
}},
3110 {"efsctsiz", VX (4, 730), VX_MASK
, PPCEFS
|PPCVLE
, PPCNONE
, {RS
, RB
}},
3111 {"efststgt", VX (4, 732), VX_MASK
, PPCEFS
|PPCVLE
, PPCNONE
, {CRFD
, RA
, RB
}},
3112 {"efststlt", VX (4, 733), VX_MASK
, PPCEFS
|PPCVLE
, PPCNONE
, {CRFD
, RA
, RB
}},
3113 {"efststeq", VX (4, 734), VX_MASK
, PPCEFS
|PPCVLE
, PPCNONE
, {CRFD
, RA
, RB
}},
3114 {"efdadd", VX (4, 736), VX_MASK
, PPCEFS
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3115 {"efdsub", VX (4, 737), VX_MASK
, PPCEFS
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3116 {"efdcfuid", VX (4, 738), VX_MASK
, PPCEFS
|PPCVLE
, PPCNONE
, {RS
, RB
}},
3117 {"efdcfsid", VX (4, 739), VX_MASK
, PPCEFS
|PPCVLE
, PPCNONE
, {RS
, RB
}},
3118 {"efdabs", VX (4, 740), VX_MASK
, PPCEFS
|PPCVLE
, PPCNONE
, {RS
, RA
}},
3119 {"efdnabs", VX (4, 741), VX_MASK
, PPCEFS
|PPCVLE
, PPCNONE
, {RS
, RA
}},
3120 {"efdneg", VX (4, 742), VX_MASK
, PPCEFS
|PPCVLE
, PPCNONE
, {RS
, RA
}},
3121 {"efdmul", VX (4, 744), VX_MASK
, PPCEFS
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3122 {"efddiv", VX (4, 745), VX_MASK
, PPCEFS
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3123 {"efdctuidz", VX (4, 746), VX_MASK
, PPCEFS
|PPCVLE
, PPCNONE
, {RS
, RB
}},
3124 {"efdctsidz", VX (4, 747), VX_MASK
, PPCEFS
|PPCVLE
, PPCNONE
, {RS
, RB
}},
3125 {"efdcmpgt", VX (4, 748), VX_MASK
, PPCEFS
|PPCVLE
, PPCNONE
, {CRFD
, RA
, RB
}},
3126 {"efdcmplt", VX (4, 749), VX_MASK
, PPCEFS
|PPCVLE
, PPCNONE
, {CRFD
, RA
, RB
}},
3127 {"efdcmpeq", VX (4, 750), VX_MASK
, PPCEFS
|PPCVLE
, PPCNONE
, {CRFD
, RA
, RB
}},
3128 {"efdcfs", VX (4, 751), VX_MASK
, PPCEFS
|PPCVLE
, PPCNONE
, {RS
, RB
}},
3129 {"efdcfui", VX (4, 752), VX_MASK
, PPCEFS
|PPCVLE
, PPCNONE
, {RS
, RB
}},
3130 {"efdcfsi", VX (4, 753), VX_MASK
, PPCEFS
|PPCVLE
, PPCNONE
, {RS
, RB
}},
3131 {"efdcfuf", VX (4, 754), VX_MASK
, PPCEFS
|PPCVLE
, PPCNONE
, {RS
, RB
}},
3132 {"efdcfsf", VX (4, 755), VX_MASK
, PPCEFS
|PPCVLE
, PPCNONE
, {RS
, RB
}},
3133 {"efdctui", VX (4, 756), VX_MASK
, PPCEFS
|PPCVLE
, PPCNONE
, {RS
, RB
}},
3134 {"efdctsi", VX (4, 757), VX_MASK
, PPCEFS
|PPCVLE
, PPCNONE
, {RS
, RB
}},
3135 {"efdctuf", VX (4, 758), VX_MASK
, PPCEFS
|PPCVLE
, PPCNONE
, {RS
, RB
}},
3136 {"efdctsf", VX (4, 759), VX_MASK
, PPCEFS
|PPCVLE
, PPCNONE
, {RS
, RB
}},
3137 {"efdctuiz", VX (4, 760), VX_MASK
, PPCEFS
|PPCVLE
, PPCNONE
, {RS
, RB
}},
3138 {"ncput", APU(4, 380,0), APU_RT_MASK
, PPC405
, PPCNONE
, {RA
, FSL
}},
3139 {"efdctsiz", VX (4, 762), VX_MASK
, PPCEFS
|PPCVLE
, PPCNONE
, {RS
, RB
}},
3140 {"efdtstgt", VX (4, 764), VX_MASK
, PPCEFS
|PPCVLE
, PPCNONE
, {CRFD
, RA
, RB
}},
3141 {"efdtstlt", VX (4, 765), VX_MASK
, PPCEFS
|PPCVLE
, PPCNONE
, {CRFD
, RA
, RB
}},
3142 {"efdtsteq", VX (4, 766), VX_MASK
, PPCEFS
|PPCVLE
, PPCNONE
, {CRFD
, RA
, RB
}},
3143 {"evlddx", VX (4, 768), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3144 {"vaddsbs", VX (4, 768), VX_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
3145 {"evldd", VX (4, 769), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, EVUIMM_8
, RA
}},
3146 {"evldwx", VX (4, 770), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3147 {"vminsb", VX (4, 770), VX_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
3148 {"evldw", VX (4, 771), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, EVUIMM_8
, RA
}},
3149 {"evldhx", VX (4, 772), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3150 {"vsrab", VX (4, 772), VX_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
3151 {"evldh", VX (4, 773), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, EVUIMM_8
, RA
}},
3152 {"vcmpgtsb", VXR(4, 774,0), VXR_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
3153 {"evlhhesplatx",VX (4, 776), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3154 {"vmulesb", VX (4, 776), VX_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
3155 {"evlhhesplat", VX (4, 777), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, EVUIMM_2
, RA
}},
3156 {"vcfux", VX (4, 778), VX_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VB
, UIMM
}},
3157 {"vcuxwfp", VX (4, 778), VX_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VB
, UIMM
}},
3158 {"evlhhousplatx",VX(4, 780), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3159 {"vspltisb", VX (4, 780), VXVB_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, SIMM
}},
3160 {"evlhhousplat",VX (4, 781), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, EVUIMM_2
, RA
}},
3161 {"evlhhossplatx",VX(4, 782), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3162 {"vpkpx", VX (4, 782), VX_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
3163 {"evlhhossplat",VX (4, 783), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, EVUIMM_2
, RA
}},
3164 {"mullhwu", XRC(4, 392,0), X_MASK
, MULHW
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
3165 {"evlwhex", VX (4, 784), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3166 {"mullhwu.", XRC(4, 392,1), X_MASK
, MULHW
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
3167 {"evlwhe", VX (4, 785), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, EVUIMM_4
, RA
}},
3168 {"evlwhoux", VX (4, 788), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3169 {"evlwhou", VX (4, 789), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, EVUIMM_4
, RA
}},
3170 {"evlwhosx", VX (4, 790), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3171 {"evlwhos", VX (4, 791), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, EVUIMM_4
, RA
}},
3172 {"maclhwu", XO (4, 396,0,0),XO_MASK
, MULHW
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
3173 {"evlwwsplatx", VX (4, 792), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3174 {"maclhwu.", XO (4, 396,0,1),XO_MASK
, MULHW
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
3175 {"evlwwsplat", VX (4, 793), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, EVUIMM_4
, RA
}},
3176 {"evlwhsplatx", VX (4, 796), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3177 {"evlwhsplat", VX (4, 797), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, EVUIMM_4
, RA
}},
3178 {"evstddx", VX (4, 800), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3179 {"evstdd", VX (4, 801), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, EVUIMM_8
, RA
}},
3180 {"evstdwx", VX (4, 802), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3181 {"evstdw", VX (4, 803), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, EVUIMM_8
, RA
}},
3182 {"evstdhx", VX (4, 804), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3183 {"evstdh", VX (4, 805), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, EVUIMM_8
, RA
}},
3184 {"evstwhex", VX (4, 816), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3185 {"evstwhe", VX (4, 817), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, EVUIMM_4
, RA
}},
3186 {"evstwhox", VX (4, 820), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3187 {"evstwho", VX (4, 821), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, EVUIMM_4
, RA
}},
3188 {"evstwwex", VX (4, 824), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3189 {"evstwwe", VX (4, 825), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, EVUIMM_4
, RA
}},
3190 {"evstwwox", VX (4, 828), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3191 {"evstwwo", VX (4, 829), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, EVUIMM_4
, RA
}},
3192 {"vaddshs", VX (4, 832), VX_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
3193 {"vminsh", VX (4, 834), VX_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
3194 {"vsrah", VX (4, 836), VX_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
3195 {"vcmpgtsh", VXR(4, 838,0), VXR_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
3196 {"vmulesh", VX (4, 840), VX_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
3197 {"vcfsx", VX (4, 842), VX_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VB
, UIMM
}},
3198 {"vcsxwfp", VX (4, 842), VX_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VB
, UIMM
}},
3199 {"vspltish", VX (4, 844), VXVB_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, SIMM
}},
3200 {"vupkhpx", VX (4, 846), VXVA_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VB
}},
3201 {"mullhw", XRC(4, 424,0), X_MASK
, MULHW
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
3202 {"mullhw.", XRC(4, 424,1), X_MASK
, MULHW
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
3203 {"maclhw", XO (4, 428,0,0),XO_MASK
, MULHW
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
3204 {"maclhw.", XO (4, 428,0,1),XO_MASK
, MULHW
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
3205 {"nmaclhw", XO (4, 430,0,0),XO_MASK
, MULHW
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
3206 {"nmaclhw.", XO (4, 430,0,1),XO_MASK
, MULHW
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
3207 {"vaddsws", VX (4, 896), VX_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
3208 {"vminsw", VX (4, 898), VX_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
3209 {"vsraw", VX (4, 900), VX_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
3210 {"vcmpgtsw", VXR(4, 902,0), VXR_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
3211 {"vmulesw", VX (4, 904), VX_MASK
, PPCVEC2
, PPCNONE
, {VD
, VA
, VB
}},
3212 {"vctuxs", VX (4, 906), VX_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VB
, UIMM
}},
3213 {"vcfpuxws", VX (4, 906), VX_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VB
, UIMM
}},
3214 {"vspltisw", VX (4, 908), VXVB_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, SIMM
}},
3215 {"maclhwsu", XO (4, 460,0,0),XO_MASK
, MULHW
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
3216 {"maclhwsu.", XO (4, 460,0,1),XO_MASK
, MULHW
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
3217 {"vminsd", VX (4, 962), VX_MASK
, PPCVEC2
, PPCNONE
, {VD
, VA
, VB
}},
3218 {"vsrad", VX (4, 964), VX_MASK
, PPCVEC2
, PPCNONE
, {VD
, VA
, VB
}},
3219 {"vcmpbfp", VXR(4, 966,0), VXR_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
3220 {"vcmpgtsd", VXR(4, 967,0), VXR_MASK
, PPCVEC2
, PPCNONE
, {VD
, VA
, VB
}},
3221 {"vctsxs", VX (4, 970), VX_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VB
, UIMM
}},
3222 {"vcfpsxws", VX (4, 970), VX_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VB
, UIMM
}},
3223 {"vupklpx", VX (4, 974), VXVA_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VB
}},
3224 {"maclhws", XO (4, 492,0,0),XO_MASK
, MULHW
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
3225 {"maclhws.", XO (4, 492,0,1),XO_MASK
, MULHW
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
3226 {"nmaclhws", XO (4, 494,0,0),XO_MASK
, MULHW
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
3227 {"nmaclhws.", XO (4, 494,0,1),XO_MASK
, MULHW
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
3228 {"vsububm", VX (4,1024), VX_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
3229 {"bcdadd.", VX (4,1025), VXPS_MASK
, PPCVEC2
, PPCNONE
, {VD
, VA
, VB
, PS
}},
3230 {"vavgub", VX (4,1026), VX_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
3231 {"vabsdub", VX (4,1027), VX_MASK
, PPCVEC2
, PPCNONE
, {VD
, VA
, VB
}},
3232 {"evmhessf", VX (4,1027), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3233 {"vand", VX (4,1028), VX_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
3234 {"vcmpequb.", VXR(4, 6,1), VXR_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
3235 {"udi0fcm.", APU(4, 515,0), APU_MASK
, PPC405
|PPC440
, PPC476
, {URT
, URA
, URB
}},
3236 {"udi0fcm", APU(4, 515,1), APU_MASK
, PPC405
|PPC440
, PPC476
, {URT
, URA
, URB
}},
3237 {"evmhossf", VX (4,1031), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3238 {"vpmsumb", VX (4,1032), VX_MASK
, PPCVEC2
, PPCNONE
, {VD
, VA
, VB
}},
3239 {"evmheumi", VX (4,1032), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3240 {"evmhesmi", VX (4,1033), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3241 {"vmaxfp", VX (4,1034), VX_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
3242 {"evmhesmf", VX (4,1035), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3243 {"evmhoumi", VX (4,1036), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3244 {"vslo", VX (4,1036), VX_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
3245 {"evmhosmi", VX (4,1037), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3246 {"evmhosmf", VX (4,1039), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3247 {"machhwuo", XO (4, 12,1,0),XO_MASK
, MULHW
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
3248 {"machhwuo.", XO (4, 12,1,1),XO_MASK
, MULHW
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
3249 {"ps_merge00", XOPS(4,528,0), XOPS_MASK
, PPCPS
, PPCNONE
, {FRT
, FRA
, FRB
}},
3250 {"ps_merge00.", XOPS(4,528,1), XOPS_MASK
, PPCPS
, PPCNONE
, {FRT
, FRA
, FRB
}},
3251 {"evmhessfa", VX (4,1059), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3252 {"evmhossfa", VX (4,1063), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3253 {"evmheumia", VX (4,1064), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3254 {"evmhesmia", VX (4,1065), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3255 {"evmhesmfa", VX (4,1067), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3256 {"evmhoumia", VX (4,1068), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3257 {"evmhosmia", VX (4,1069), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3258 {"evmhosmfa", VX (4,1071), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3259 {"vsubuhm", VX (4,1088), VX_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
3260 {"bcdsub.", VX (4,1089), VXPS_MASK
, PPCVEC2
, PPCNONE
, {VD
, VA
, VB
, PS
}},
3261 {"vavguh", VX (4,1090), VX_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
3262 {"vabsduh", VX (4,1091), VX_MASK
, PPCVEC2
, PPCNONE
, {VD
, VA
, VB
}},
3263 {"vandc", VX (4,1092), VX_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
3264 {"vcmpequh.", VXR(4, 70,1), VXR_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
3265 {"udi1fcm.", APU(4, 547,0), APU_MASK
, PPC405
|PPC440
, PPC476
, {URT
, URA
, URB
}},
3266 {"udi1fcm", APU(4, 547,1), APU_MASK
, PPC405
|PPC440
, PPC476
, {URT
, URA
, URB
}},
3267 {"evmwhssf", VX (4,1095), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3268 {"vpmsumh", VX (4,1096), VX_MASK
, PPCVEC2
, PPCNONE
, {VD
, VA
, VB
}},
3269 {"evmwlumi", VX (4,1096), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3270 {"vminfp", VX (4,1098), VX_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
3271 {"evmwhumi", VX (4,1100), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3272 {"vsro", VX (4,1100), VX_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
3273 {"evmwhsmi", VX (4,1101), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3274 {"vpkudum", VX (4,1102), VX_MASK
, PPCVEC2
, PPCNONE
, {VD
, VA
, VB
}},
3275 {"evmwhsmf", VX (4,1103), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3276 {"evmwssf", VX (4,1107), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3277 {"machhwo", XO (4, 44,1,0),XO_MASK
, MULHW
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
3278 {"evmwumi", VX (4,1112), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3279 {"machhwo.", XO (4, 44,1,1),XO_MASK
, MULHW
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
3280 {"evmwsmi", VX (4,1113), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3281 {"evmwsmf", VX (4,1115), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3282 {"nmachhwo", XO (4, 46,1,0),XO_MASK
, MULHW
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
3283 {"nmachhwo.", XO (4, 46,1,1),XO_MASK
, MULHW
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
3284 {"ps_merge01", XOPS(4,560,0), XOPS_MASK
, PPCPS
, PPCNONE
, {FRT
, FRA
, FRB
}},
3285 {"ps_merge01.", XOPS(4,560,1), XOPS_MASK
, PPCPS
, PPCNONE
, {FRT
, FRA
, FRB
}},
3286 {"evmwhssfa", VX (4,1127), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3287 {"evmwlumia", VX (4,1128), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3288 {"evmwhumia", VX (4,1132), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3289 {"evmwhsmia", VX (4,1133), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3290 {"evmwhsmfa", VX (4,1135), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3291 {"evmwssfa", VX (4,1139), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3292 {"evmwumia", VX (4,1144), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3293 {"evmwsmia", VX (4,1145), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3294 {"evmwsmfa", VX (4,1147), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3295 {"vsubuwm", VX (4,1152), VX_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
3296 {"vavguw", VX (4,1154), VX_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
3297 {"vabsduw", VX (4,1155), VX_MASK
, PPCVEC2
, PPCNONE
, {VD
, VA
, VB
}},
3298 {"vmr", VX (4,1156), VX_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VBA
}},
3299 {"vor", VX (4,1156), VX_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
3300 {"vpmsumw", VX (4,1160), VX_MASK
, PPCVEC2
, PPCNONE
, {VD
, VA
, VB
}},
3301 {"vcmpequw.", VXR(4, 134,1), VXR_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
3302 {"udi2fcm.", APU(4, 579,0), APU_MASK
, PPC405
|PPC440
, PPC476
, {URT
, URA
, URB
}},
3303 {"udi2fcm", APU(4, 579,1), APU_MASK
, PPC405
|PPC440
, PPC476
, {URT
, URA
, URB
}},
3304 {"machhwsuo", XO (4, 76,1,0),XO_MASK
, MULHW
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
3305 {"machhwsuo.", XO (4, 76,1,1),XO_MASK
, MULHW
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
3306 {"ps_merge10", XOPS(4,592,0), XOPS_MASK
, PPCPS
, PPCNONE
, {FRT
, FRA
, FRB
}},
3307 {"ps_merge10.", XOPS(4,592,1), XOPS_MASK
, PPCPS
, PPCNONE
, {FRT
, FRA
, FRB
}},
3308 {"vsubudm", VX (4,1216), VX_MASK
, PPCVEC2
, PPCNONE
, {VD
, VA
, VB
}},
3309 {"evaddusiaaw", VX (4,1216), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
}},
3310 {"evaddssiaaw", VX (4,1217), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
}},
3311 {"evsubfusiaaw",VX (4,1218), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
}},
3312 {"evsubfssiaaw",VX (4,1219), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
}},
3313 {"evmra", VX (4,1220), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
}},
3314 {"vxor", VX (4,1220), VX_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
3315 {"evdivws", VX (4,1222), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3316 {"vcmpeqfp.", VXR(4, 198,1), VXR_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
3317 {"udi3fcm.", APU(4, 611,0), APU_MASK
, PPC405
|PPC440
, PPC476
, {URT
, URA
, URB
}},
3318 {"vcmpequd.", VXR(4, 199,1), VXR_MASK
, PPCVEC2
, PPCNONE
, {VD
, VA
, VB
}},
3319 {"udi3fcm", APU(4, 611,1), APU_MASK
, PPC405
|PPC440
, PPC476
, {URT
, URA
, URB
}},
3320 {"evdivwu", VX (4,1223), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3321 {"vpmsumd", VX (4,1224), VX_MASK
, PPCVEC2
, PPCNONE
, {VD
, VA
, VB
}},
3322 {"evaddumiaaw", VX (4,1224), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
}},
3323 {"evaddsmiaaw", VX (4,1225), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
}},
3324 {"evsubfumiaaw",VX (4,1226), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
}},
3325 {"evsubfsmiaaw",VX (4,1227), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
}},
3326 {"vpkudus", VX (4,1230), VX_MASK
, PPCVEC2
, PPCNONE
, {VD
, VA
, VB
}},
3327 {"machhwso", XO (4, 108,1,0),XO_MASK
, MULHW
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
3328 {"machhwso.", XO (4, 108,1,1),XO_MASK
, MULHW
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
3329 {"nmachhwso", XO (4, 110,1,0),XO_MASK
, MULHW
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
3330 {"nmachhwso.", XO (4, 110,1,1),XO_MASK
, MULHW
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
3331 {"ps_merge11", XOPS(4,624,0), XOPS_MASK
, PPCPS
, PPCNONE
, {FRT
, FRA
, FRB
}},
3332 {"ps_merge11.", XOPS(4,624,1), XOPS_MASK
, PPCPS
, PPCNONE
, {FRT
, FRA
, FRB
}},
3333 {"vsubuqm", VX (4,1280), VX_MASK
, PPCVEC2
, PPCNONE
, {VD
, VA
, VB
}},
3334 {"evmheusiaaw", VX (4,1280), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3335 {"evmhessiaaw", VX (4,1281), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3336 {"vavgsb", VX (4,1282), VX_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
3337 {"evmhessfaaw", VX (4,1283), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3338 {"evmhousiaaw", VX (4,1284), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3339 {"vnot", VX (4,1284), VX_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VBA
}},
3340 {"vnor", VX (4,1284), VX_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
3341 {"evmhossiaaw", VX (4,1285), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3342 {"udi4fcm.", APU(4, 643,0), APU_MASK
, PPC405
|PPC440
, PPC476
, {URT
, URA
, URB
}},
3343 {"udi4fcm", APU(4, 643,1), APU_MASK
, PPC405
|PPC440
, PPC476
, {URT
, URA
, URB
}},
3344 {"evmhossfaaw", VX (4,1287), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3345 {"evmheumiaaw", VX (4,1288), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3346 {"vcipher", VX (4,1288), VX_MASK
, PPCVEC2
, PPCNONE
, {VD
, VA
, VB
}},
3347 {"vcipherlast", VX (4,1289), VX_MASK
, PPCVEC2
, PPCNONE
, {VD
, VA
, VB
}},
3348 {"evmhesmiaaw", VX (4,1289), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3349 {"evmhesmfaaw", VX (4,1291), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3350 {"vgbbd", VX (4,1292), VXVA_MASK
, PPCVEC2
, PPCNONE
, {VD
, VB
}},
3351 {"evmhoumiaaw", VX (4,1292), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3352 {"evmhosmiaaw", VX (4,1293), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3353 {"evmhosmfaaw", VX (4,1295), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3354 {"macchwuo", XO (4, 140,1,0),XO_MASK
, MULHW
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
3355 {"macchwuo.", XO (4, 140,1,1),XO_MASK
, MULHW
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
3356 {"evmhegumiaa", VX (4,1320), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3357 {"evmhegsmiaa", VX (4,1321), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3358 {"evmhegsmfaa", VX (4,1323), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3359 {"evmhogumiaa", VX (4,1324), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3360 {"evmhogsmiaa", VX (4,1325), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3361 {"evmhogsmfaa", VX (4,1327), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3362 {"vsubcuq", VX (4,1344), VX_MASK
, PPCVEC2
, PPCNONE
, {VD
, VA
, VB
}},
3363 {"evmwlusiaaw", VX (4,1344), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3364 {"evmwlssiaaw", VX (4,1345), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3365 {"vavgsh", VX (4,1346), VX_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
3366 {"vorc", VX (4,1348), VX_MASK
, PPCVEC2
, PPCNONE
, {VD
, VA
, VB
}},
3367 {"udi5fcm.", APU(4, 675,0), APU_MASK
, PPC405
|PPC440
, PPC476
, {URT
, URA
, URB
}},
3368 {"udi5fcm", APU(4, 675,1), APU_MASK
, PPC405
|PPC440
, PPC476
, {URT
, URA
, URB
}},
3369 {"vncipher", VX (4,1352), VX_MASK
, PPCVEC2
, PPCNONE
, {VD
, VA
, VB
}},
3370 {"evmwlumiaaw", VX (4,1352), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3371 {"vncipherlast",VX (4,1353), VX_MASK
, PPCVEC2
, PPCNONE
, {VD
, VA
, VB
}},
3372 {"evmwlsmiaaw", VX (4,1353), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3373 {"vbpermq", VX (4,1356), VX_MASK
, PPCVEC2
, PPCNONE
, {VD
, VA
, VB
}},
3374 {"vpksdus", VX (4,1358), VX_MASK
, PPCVEC2
, PPCNONE
, {VD
, VA
, VB
}},
3375 {"evmwssfaa", VX (4,1363), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3376 {"macchwo", XO (4, 172,1,0),XO_MASK
, MULHW
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
3377 {"evmwumiaa", VX (4,1368), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3378 {"macchwo.", XO (4, 172,1,1),XO_MASK
, MULHW
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
3379 {"evmwsmiaa", VX (4,1369), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3380 {"evmwsmfaa", VX (4,1371), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3381 {"nmacchwo", XO (4, 174,1,0),XO_MASK
, MULHW
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
3382 {"nmacchwo.", XO (4, 174,1,1),XO_MASK
, MULHW
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
3383 {"evmheusianw", VX (4,1408), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3384 {"vsubcuw", VX (4,1408), VX_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
3385 {"evmhessianw", VX (4,1409), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3386 {"vavgsw", VX (4,1410), VX_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
3387 {"evmhessfanw", VX (4,1411), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3388 {"vnand", VX (4,1412), VX_MASK
, PPCVEC2
, PPCNONE
, {VD
, VA
, VB
}},
3389 {"evmhousianw", VX (4,1412), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3390 {"evmhossianw", VX (4,1413), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3391 {"udi6fcm.", APU(4, 707,0), APU_MASK
, PPC405
|PPC440
, PPC476
, {URT
, URA
, URB
}},
3392 {"udi6fcm", APU(4, 707,1), APU_MASK
, PPC405
|PPC440
, PPC476
, {URT
, URA
, URB
}},
3393 {"evmhossfanw", VX (4,1415), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3394 {"evmheumianw", VX (4,1416), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3395 {"evmhesmianw", VX (4,1417), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3396 {"evmhesmfanw", VX (4,1419), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3397 {"evmhoumianw", VX (4,1420), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3398 {"evmhosmianw", VX (4,1421), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3399 {"evmhosmfanw", VX (4,1423), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3400 {"macchwsuo", XO (4, 204,1,0),XO_MASK
, MULHW
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
3401 {"macchwsuo.", XO (4, 204,1,1),XO_MASK
, MULHW
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
3402 {"evmhegumian", VX (4,1448), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3403 {"evmhegsmian", VX (4,1449), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3404 {"evmhegsmfan", VX (4,1451), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3405 {"evmhogumian", VX (4,1452), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3406 {"evmhogsmian", VX (4,1453), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3407 {"evmhogsmfan", VX (4,1455), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3408 {"evmwlusianw", VX (4,1472), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3409 {"evmwlssianw", VX (4,1473), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3410 {"vsld", VX (4,1476), VX_MASK
, PPCVEC2
, PPCNONE
, {VD
, VA
, VB
}},
3411 {"vcmpgefp.", VXR(4, 454,1), VXR_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
3412 {"udi7fcm.", APU(4, 739,0), APU_MASK
, PPC405
|PPC440
, PPC476
, {URT
, URA
, URB
}},
3413 {"udi7fcm", APU(4, 739,1), APU_MASK
, PPC405
|PPC440
, PPC476
, {URT
, URA
, URB
}},
3414 {"vsbox", VX (4,1480), VXVB_MASK
, PPCVEC2
, PPCNONE
, {VD
, VA
}},
3415 {"evmwlumianw", VX (4,1480), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3416 {"evmwlsmianw", VX (4,1481), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3417 {"vpksdss", VX (4,1486), VX_MASK
, PPCVEC2
, PPCNONE
, {VD
, VA
, VB
}},
3418 {"evmwssfan", VX (4,1491), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3419 {"macchwso", XO (4, 236,1,0),XO_MASK
, MULHW
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
3420 {"evmwumian", VX (4,1496), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3421 {"macchwso.", XO (4, 236,1,1),XO_MASK
, MULHW
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
3422 {"evmwsmian", VX (4,1497), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3423 {"evmwsmfan", VX (4,1499), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3424 {"nmacchwso", XO (4, 238,1,0),XO_MASK
, MULHW
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
3425 {"nmacchwso.", XO (4, 238,1,1),XO_MASK
, MULHW
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
3426 {"vsububs", VX (4,1536), VX_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
3427 {"mfvscr", VX (4,1540), VXVAVB_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
}},
3428 {"vcmpgtub.", VXR(4, 518,1), VXR_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
3429 {"udi8fcm.", APU(4, 771,0), APU_MASK
, PPC440
, PPC476
, {URT
, URA
, URB
}},
3430 {"udi8fcm", APU(4, 771,1), APU_MASK
, PPC440
, PPC476
, {URT
, URA
, URB
}},
3431 {"vsum4ubs", VX (4,1544), VX_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
3432 {"vsubuhs", VX (4,1600), VX_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
3433 {"mtvscr", VX (4,1604), VXVDVA_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VB
}},
3434 {"vcmpgtuh.", VXR(4, 582,1), VXR_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
3435 {"vsum4shs", VX (4,1608), VX_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
3436 {"udi9fcm.", APU(4, 804,0), APU_MASK
, PPC440
, PPC476
, {URT
, URA
, URB
}},
3437 {"udi9fcm", APU(4, 804,1), APU_MASK
, PPC440
, PPC476
, {URT
, URA
, URB
}},
3438 {"vupkhsw", VX (4,1614), VXVA_MASK
, PPCVEC2
, PPCNONE
, {VD
, VB
}},
3439 {"vsubuws", VX (4,1664), VX_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
3440 {"vshasigmaw", VX (4,1666), VX_MASK
, PPCVEC2
, PPCNONE
, {VD
, VA
, ST
, SIX
}},
3441 {"veqv", VX (4,1668), VX_MASK
, PPCVEC2
, PPCNONE
, {VD
, VA
, VB
}},
3442 {"vcmpgtuw.", VXR(4, 646,1), VXR_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
3443 {"udi10fcm.", APU(4, 835,0), APU_MASK
, PPC440
, PPC476
, {URT
, URA
, URB
}},
3444 {"udi10fcm", APU(4, 835,1), APU_MASK
, PPC440
, PPC476
, {URT
, URA
, URB
}},
3445 {"vsum2sws", VX (4,1672), VX_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
3446 {"vmrgow", VX (4,1676), VX_MASK
, PPCVEC2
, PPCNONE
, {VD
, VA
, VB
}},
3447 {"vshasigmad", VX (4,1730), VX_MASK
, PPCVEC2
, PPCNONE
, {VD
, VA
, ST
, SIX
}},
3448 {"vsrd", VX (4,1732), VX_MASK
, PPCVEC2
, PPCNONE
, {VD
, VA
, VB
}},
3449 {"vcmpgtfp.", VXR(4, 710,1), VXR_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
3450 {"udi11fcm.", APU(4, 867,0), APU_MASK
, PPC440
, PPC476
, {URT
, URA
, URB
}},
3451 {"vcmpgtud.", VXR(4, 711,1), VXR_MASK
, PPCVEC2
, PPCNONE
, {VD
, VA
, VB
}},
3452 {"udi11fcm", APU(4, 867,1), APU_MASK
, PPC440
, PPC476
, {URT
, URA
, URB
}},
3453 {"vupklsw", VX (4,1742), VXVA_MASK
, PPCVEC2
, PPCNONE
, {VD
, VB
}},
3454 {"vsubsbs", VX (4,1792), VX_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
3455 {"vclzb", VX (4,1794), VXVA_MASK
, PPCVEC2
, PPCNONE
, {VD
, VB
}},
3456 {"vpopcntb", VX (4,1795), VXVA_MASK
, PPCVEC2
, PPCNONE
, {VD
, VB
}},
3457 {"vcmpgtsb.", VXR(4, 774,1), VXR_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
3458 {"udi12fcm.", APU(4, 899,0), APU_MASK
, PPC440
, PPC476
, {URT
, URA
, URB
}},
3459 {"udi12fcm", APU(4, 899,1), APU_MASK
, PPC440
, PPC476
, {URT
, URA
, URB
}},
3460 {"vsum4sbs", VX (4,1800), VX_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
3461 {"maclhwuo", XO (4, 396,1,0),XO_MASK
, MULHW
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
3462 {"maclhwuo.", XO (4, 396,1,1),XO_MASK
, MULHW
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
3463 {"vsubshs", VX (4,1856), VX_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
3464 {"vclzh", VX (4,1858), VXVA_MASK
, PPCVEC2
, PPCNONE
, {VD
, VB
}},
3465 {"vpopcnth", VX (4,1859), VXVA_MASK
, PPCVEC2
, PPCNONE
, {VD
, VB
}},
3466 {"vcmpgtsh.", VXR(4, 838,1), VXR_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
3467 {"udi13fcm.", APU(4, 931,0), APU_MASK
, PPC440
, PPC476
, {URT
, URA
, URB
}},
3468 {"udi13fcm", APU(4, 931,1), APU_MASK
, PPC440
, PPC476
, {URT
, URA
, URB
}},
3469 {"maclhwo", XO (4, 428,1,0),XO_MASK
, MULHW
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
3470 {"maclhwo.", XO (4, 428,1,1),XO_MASK
, MULHW
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
3471 {"nmaclhwo", XO (4, 430,1,0),XO_MASK
, MULHW
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
3472 {"nmaclhwo.", XO (4, 430,1,1),XO_MASK
, MULHW
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
3473 {"vsubsws", VX (4,1920), VX_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
3474 {"vclzw", VX (4,1922), VXVA_MASK
, PPCVEC2
, PPCNONE
, {VD
, VB
}},
3475 {"vpopcntw", VX (4,1923), VXVA_MASK
, PPCVEC2
, PPCNONE
, {VD
, VB
}},
3476 {"vcmpgtsw.", VXR(4, 902,1), VXR_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
3477 {"udi14fcm.", APU(4, 963,0), APU_MASK
, PPC440
, PPC476
, {URT
, URA
, URB
}},
3478 {"udi14fcm", APU(4, 963,1), APU_MASK
, PPC440
, PPC476
, {URT
, URA
, URB
}},
3479 {"vsumsws", VX (4,1928), VX_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
3480 {"vmrgew", VX (4,1932), VX_MASK
, PPCVEC2
, PPCNONE
, {VD
, VA
, VB
}},
3481 {"maclhwsuo", XO (4, 460,1,0),XO_MASK
, MULHW
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
3482 {"maclhwsuo.", XO (4, 460,1,1),XO_MASK
, MULHW
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
3483 {"vclzd", VX (4,1986), VXVA_MASK
, PPCVEC2
, PPCNONE
, {VD
, VB
}},
3484 {"vpopcntd", VX (4,1987), VXVA_MASK
, PPCVEC2
, PPCNONE
, {VD
, VB
}},
3485 {"vcmpbfp.", VXR(4, 966,1), VXR_MASK
, PPCVEC
, PPCNONE
, {VD
, VA
, VB
}},
3486 {"udi15fcm.", APU(4, 995,0), APU_MASK
, PPC440
, PPC476
, {URT
, URA
, URB
}},
3487 {"vcmpgtsd.", VXR(4, 967,1), VXR_MASK
, PPCVEC2
, PPCNONE
, {VD
, VA
, VB
}},
3488 {"udi15fcm", APU(4, 995,1), APU_MASK
, PPC440
, PPC476
, {URT
, URA
, URB
}},
3489 {"maclhwso", XO (4, 492,1,0),XO_MASK
, MULHW
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
3490 {"maclhwso.", XO (4, 492,1,1),XO_MASK
, MULHW
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
3491 {"nmaclhwso", XO (4, 494,1,0),XO_MASK
, MULHW
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
3492 {"nmaclhwso.", XO (4, 494,1,1),XO_MASK
, MULHW
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
3493 {"dcbz_l", X (4,1014), XRT_MASK
, PPCPS
, PPCNONE
, {RA
, RB
}},
3495 {"mulli", OP(7), OP_MASK
, PPCCOM
, PPCNONE
, {RT
, RA
, SI
}},
3496 {"muli", OP(7), OP_MASK
, PWRCOM
, PPCNONE
, {RT
, RA
, SI
}},
3498 {"subfic", OP(8), OP_MASK
, PPCCOM
, PPCNONE
, {RT
, RA
, SI
}},
3499 {"sfi", OP(8), OP_MASK
, PWRCOM
, PPCNONE
, {RT
, RA
, SI
}},
3501 {"dozi", OP(9), OP_MASK
, M601
, PPCNONE
, {RT
, RA
, SI
}},
3503 {"cmplwi", OPL(10,0), OPL_MASK
, PPCCOM
, PPCNONE
, {OBF
, RA
, UI
}},
3504 {"cmpldi", OPL(10,1), OPL_MASK
, PPC64
, PPCNONE
, {OBF
, RA
, UI
}},
3505 {"cmpli", OP(10), OP_MASK
, PPC
, PPCNONE
, {BF
, L
, RA
, UI
}},
3506 {"cmpli", OP(10), OP_MASK
, PWRCOM
, PPC
, {BF
, RA
, UI
}},
3508 {"cmpwi", OPL(11,0), OPL_MASK
, PPCCOM
, PPCNONE
, {OBF
, RA
, SI
}},
3509 {"cmpdi", OPL(11,1), OPL_MASK
, PPC64
, PPCNONE
, {OBF
, RA
, SI
}},
3510 {"cmpi", OP(11), OP_MASK
, PPC
, PPCNONE
, {BF
, L
, RA
, SI
}},
3511 {"cmpi", OP(11), OP_MASK
, PWRCOM
, PPC
, {BF
, RA
, SI
}},
3513 {"addic", OP(12), OP_MASK
, PPCCOM
, PPCNONE
, {RT
, RA
, SI
}},
3514 {"ai", OP(12), OP_MASK
, PWRCOM
, PPCNONE
, {RT
, RA
, SI
}},
3515 {"subic", OP(12), OP_MASK
, PPCCOM
, PPCNONE
, {RT
, RA
, NSI
}},
3517 {"addic.", OP(13), OP_MASK
, PPCCOM
, PPCNONE
, {RT
, RA
, SI
}},
3518 {"ai.", OP(13), OP_MASK
, PWRCOM
, PPCNONE
, {RT
, RA
, SI
}},
3519 {"subic.", OP(13), OP_MASK
, PPCCOM
, PPCNONE
, {RT
, RA
, NSI
}},
3521 {"li", OP(14), DRA_MASK
, PPCCOM
, PPCNONE
, {RT
, SI
}},
3522 {"lil", OP(14), DRA_MASK
, PWRCOM
, PPCNONE
, {RT
, SI
}},
3523 {"addi", OP(14), OP_MASK
, PPCCOM
, PPCNONE
, {RT
, RA0
, SI
}},
3524 {"cal", OP(14), OP_MASK
, PWRCOM
, PPCNONE
, {RT
, D
, RA0
}},
3525 {"subi", OP(14), OP_MASK
, PPCCOM
, PPCNONE
, {RT
, RA0
, NSI
}},
3526 {"la", OP(14), OP_MASK
, PPCCOM
, PPCNONE
, {RT
, D
, RA0
}},
3528 {"lis", OP(15), DRA_MASK
, PPCCOM
, PPCNONE
, {RT
, SISIGNOPT
}},
3529 {"liu", OP(15), DRA_MASK
, PWRCOM
, PPCNONE
, {RT
, SISIGNOPT
}},
3530 {"addis", OP(15), OP_MASK
, PPCCOM
, PPCNONE
, {RT
, RA0
, SISIGNOPT
}},
3531 {"cau", OP(15), OP_MASK
, PWRCOM
, PPCNONE
, {RT
, RA0
, SISIGNOPT
}},
3532 {"subis", OP(15), OP_MASK
, PPCCOM
, PPCNONE
, {RT
, RA0
, NSI
}},
3534 {"bdnz-", BBO(16,BODNZ
,0,0), BBOATBI_MASK
, PPCCOM
, PPCNONE
, {BDM
}},
3535 {"bdnz+", BBO(16,BODNZ
,0,0), BBOATBI_MASK
, PPCCOM
, PPCNONE
, {BDP
}},
3536 {"bdnz", BBO(16,BODNZ
,0,0), BBOATBI_MASK
, PPCCOM
, PPCNONE
, {BD
}},
3537 {"bdn", BBO(16,BODNZ
,0,0), BBOATBI_MASK
, PWRCOM
, PPCNONE
, {BD
}},
3538 {"bdnzl-", BBO(16,BODNZ
,0,1), BBOATBI_MASK
, PPCCOM
, PPCNONE
, {BDM
}},
3539 {"bdnzl+", BBO(16,BODNZ
,0,1), BBOATBI_MASK
, PPCCOM
, PPCNONE
, {BDP
}},
3540 {"bdnzl", BBO(16,BODNZ
,0,1), BBOATBI_MASK
, PPCCOM
, PPCNONE
, {BD
}},
3541 {"bdnl", BBO(16,BODNZ
,0,1), BBOATBI_MASK
, PWRCOM
, PPCNONE
, {BD
}},
3542 {"bdnza-", BBO(16,BODNZ
,1,0), BBOATBI_MASK
, PPCCOM
, PPCNONE
, {BDMA
}},
3543 {"bdnza+", BBO(16,BODNZ
,1,0), BBOATBI_MASK
, PPCCOM
, PPCNONE
, {BDPA
}},
3544 {"bdnza", BBO(16,BODNZ
,1,0), BBOATBI_MASK
, PPCCOM
, PPCNONE
, {BDA
}},
3545 {"bdna", BBO(16,BODNZ
,1,0), BBOATBI_MASK
, PWRCOM
, PPCNONE
, {BDA
}},
3546 {"bdnzla-", BBO(16,BODNZ
,1,1), BBOATBI_MASK
, PPCCOM
, PPCNONE
, {BDMA
}},
3547 {"bdnzla+", BBO(16,BODNZ
,1,1), BBOATBI_MASK
, PPCCOM
, PPCNONE
, {BDPA
}},
3548 {"bdnzla", BBO(16,BODNZ
,1,1), BBOATBI_MASK
, PPCCOM
, PPCNONE
, {BDA
}},
3549 {"bdnla", BBO(16,BODNZ
,1,1), BBOATBI_MASK
, PWRCOM
, PPCNONE
, {BDA
}},
3550 {"bdz-", BBO(16,BODZ
,0,0), BBOATBI_MASK
, PPCCOM
, PPCNONE
, {BDM
}},
3551 {"bdz+", BBO(16,BODZ
,0,0), BBOATBI_MASK
, PPCCOM
, PPCNONE
, {BDP
}},
3552 {"bdz", BBO(16,BODZ
,0,0), BBOATBI_MASK
, COM
, PPCNONE
, {BD
}},
3553 {"bdzl-", BBO(16,BODZ
,0,1), BBOATBI_MASK
, PPCCOM
, PPCNONE
, {BDM
}},
3554 {"bdzl+", BBO(16,BODZ
,0,1), BBOATBI_MASK
, PPCCOM
, PPCNONE
, {BDP
}},
3555 {"bdzl", BBO(16,BODZ
,0,1), BBOATBI_MASK
, COM
, PPCNONE
, {BD
}},
3556 {"bdza-", BBO(16,BODZ
,1,0), BBOATBI_MASK
, PPCCOM
, PPCNONE
, {BDMA
}},
3557 {"bdza+", BBO(16,BODZ
,1,0), BBOATBI_MASK
, PPCCOM
, PPCNONE
, {BDPA
}},
3558 {"bdza", BBO(16,BODZ
,1,0), BBOATBI_MASK
, COM
, PPCNONE
, {BDA
}},
3559 {"bdzla-", BBO(16,BODZ
,1,1), BBOATBI_MASK
, PPCCOM
, PPCNONE
, {BDMA
}},
3560 {"bdzla+", BBO(16,BODZ
,1,1), BBOATBI_MASK
, PPCCOM
, PPCNONE
, {BDPA
}},
3561 {"bdzla", BBO(16,BODZ
,1,1), BBOATBI_MASK
, COM
, PPCNONE
, {BDA
}},
3563 {"bge-", BBOCB(16,BOF
,CBLT
,0,0), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BDM
}},
3564 {"bge+", BBOCB(16,BOF
,CBLT
,0,0), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BDP
}},
3565 {"bge", BBOCB(16,BOF
,CBLT
,0,0), BBOATCB_MASK
, COM
, PPCNONE
, {CR
, BD
}},
3566 {"bnl-", BBOCB(16,BOF
,CBLT
,0,0), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BDM
}},
3567 {"bnl+", BBOCB(16,BOF
,CBLT
,0,0), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BDP
}},
3568 {"bnl", BBOCB(16,BOF
,CBLT
,0,0), BBOATCB_MASK
, COM
, PPCNONE
, {CR
, BD
}},
3569 {"bgel-", BBOCB(16,BOF
,CBLT
,0,1), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BDM
}},
3570 {"bgel+", BBOCB(16,BOF
,CBLT
,0,1), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BDP
}},
3571 {"bgel", BBOCB(16,BOF
,CBLT
,0,1), BBOATCB_MASK
, COM
, PPCNONE
, {CR
, BD
}},
3572 {"bnll-", BBOCB(16,BOF
,CBLT
,0,1), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BDM
}},
3573 {"bnll+", BBOCB(16,BOF
,CBLT
,0,1), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BDP
}},
3574 {"bnll", BBOCB(16,BOF
,CBLT
,0,1), BBOATCB_MASK
, COM
, PPCNONE
, {CR
, BD
}},
3575 {"bgea-", BBOCB(16,BOF
,CBLT
,1,0), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BDMA
}},
3576 {"bgea+", BBOCB(16,BOF
,CBLT
,1,0), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BDPA
}},
3577 {"bgea", BBOCB(16,BOF
,CBLT
,1,0), BBOATCB_MASK
, COM
, PPCNONE
, {CR
, BDA
}},
3578 {"bnla-", BBOCB(16,BOF
,CBLT
,1,0), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BDMA
}},
3579 {"bnla+", BBOCB(16,BOF
,CBLT
,1,0), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BDPA
}},
3580 {"bnla", BBOCB(16,BOF
,CBLT
,1,0), BBOATCB_MASK
, COM
, PPCNONE
, {CR
, BDA
}},
3581 {"bgela-", BBOCB(16,BOF
,CBLT
,1,1), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BDMA
}},
3582 {"bgela+", BBOCB(16,BOF
,CBLT
,1,1), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BDPA
}},
3583 {"bgela", BBOCB(16,BOF
,CBLT
,1,1), BBOATCB_MASK
, COM
, PPCNONE
, {CR
, BDA
}},
3584 {"bnlla-", BBOCB(16,BOF
,CBLT
,1,1), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BDMA
}},
3585 {"bnlla+", BBOCB(16,BOF
,CBLT
,1,1), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BDPA
}},
3586 {"bnlla", BBOCB(16,BOF
,CBLT
,1,1), BBOATCB_MASK
, COM
, PPCNONE
, {CR
, BDA
}},
3587 {"ble-", BBOCB(16,BOF
,CBGT
,0,0), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BDM
}},
3588 {"ble+", BBOCB(16,BOF
,CBGT
,0,0), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BDP
}},
3589 {"ble", BBOCB(16,BOF
,CBGT
,0,0), BBOATCB_MASK
, COM
, PPCNONE
, {CR
, BD
}},
3590 {"bng-", BBOCB(16,BOF
,CBGT
,0,0), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BDM
}},
3591 {"bng+", BBOCB(16,BOF
,CBGT
,0,0), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BDP
}},
3592 {"bng", BBOCB(16,BOF
,CBGT
,0,0), BBOATCB_MASK
, COM
, PPCNONE
, {CR
, BD
}},
3593 {"blel-", BBOCB(16,BOF
,CBGT
,0,1), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BDM
}},
3594 {"blel+", BBOCB(16,BOF
,CBGT
,0,1), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BDP
}},
3595 {"blel", BBOCB(16,BOF
,CBGT
,0,1), BBOATCB_MASK
, COM
, PPCNONE
, {CR
, BD
}},
3596 {"bngl-", BBOCB(16,BOF
,CBGT
,0,1), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BDM
}},
3597 {"bngl+", BBOCB(16,BOF
,CBGT
,0,1), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BDP
}},
3598 {"bngl", BBOCB(16,BOF
,CBGT
,0,1), BBOATCB_MASK
, COM
, PPCNONE
, {CR
, BD
}},
3599 {"blea-", BBOCB(16,BOF
,CBGT
,1,0), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BDMA
}},
3600 {"blea+", BBOCB(16,BOF
,CBGT
,1,0), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BDPA
}},
3601 {"blea", BBOCB(16,BOF
,CBGT
,1,0), BBOATCB_MASK
, COM
, PPCNONE
, {CR
, BDA
}},
3602 {"bnga-", BBOCB(16,BOF
,CBGT
,1,0), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BDMA
}},
3603 {"bnga+", BBOCB(16,BOF
,CBGT
,1,0), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BDPA
}},
3604 {"bnga", BBOCB(16,BOF
,CBGT
,1,0), BBOATCB_MASK
, COM
, PPCNONE
, {CR
, BDA
}},
3605 {"blela-", BBOCB(16,BOF
,CBGT
,1,1), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BDMA
}},
3606 {"blela+", BBOCB(16,BOF
,CBGT
,1,1), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BDPA
}},
3607 {"blela", BBOCB(16,BOF
,CBGT
,1,1), BBOATCB_MASK
, COM
, PPCNONE
, {CR
, BDA
}},
3608 {"bngla-", BBOCB(16,BOF
,CBGT
,1,1), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BDMA
}},
3609 {"bngla+", BBOCB(16,BOF
,CBGT
,1,1), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BDPA
}},
3610 {"bngla", BBOCB(16,BOF
,CBGT
,1,1), BBOATCB_MASK
, COM
, PPCNONE
, {CR
, BDA
}},
3611 {"bne-", BBOCB(16,BOF
,CBEQ
,0,0), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BDM
}},
3612 {"bne+", BBOCB(16,BOF
,CBEQ
,0,0), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BDP
}},
3613 {"bne", BBOCB(16,BOF
,CBEQ
,0,0), BBOATCB_MASK
, COM
, PPCNONE
, {CR
, BD
}},
3614 {"bnel-", BBOCB(16,BOF
,CBEQ
,0,1), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BDM
}},
3615 {"bnel+", BBOCB(16,BOF
,CBEQ
,0,1), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BDP
}},
3616 {"bnel", BBOCB(16,BOF
,CBEQ
,0,1), BBOATCB_MASK
, COM
, PPCNONE
, {CR
, BD
}},
3617 {"bnea-", BBOCB(16,BOF
,CBEQ
,1,0), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BDMA
}},
3618 {"bnea+", BBOCB(16,BOF
,CBEQ
,1,0), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BDPA
}},
3619 {"bnea", BBOCB(16,BOF
,CBEQ
,1,0), BBOATCB_MASK
, COM
, PPCNONE
, {CR
, BDA
}},
3620 {"bnela-", BBOCB(16,BOF
,CBEQ
,1,1), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BDMA
}},
3621 {"bnela+", BBOCB(16,BOF
,CBEQ
,1,1), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BDPA
}},
3622 {"bnela", BBOCB(16,BOF
,CBEQ
,1,1), BBOATCB_MASK
, COM
, PPCNONE
, {CR
, BDA
}},
3623 {"bns-", BBOCB(16,BOF
,CBSO
,0,0), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BDM
}},
3624 {"bns+", BBOCB(16,BOF
,CBSO
,0,0), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BDP
}},
3625 {"bns", BBOCB(16,BOF
,CBSO
,0,0), BBOATCB_MASK
, COM
, PPCNONE
, {CR
, BD
}},
3626 {"bnu-", BBOCB(16,BOF
,CBSO
,0,0), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BDM
}},
3627 {"bnu+", BBOCB(16,BOF
,CBSO
,0,0), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BDP
}},
3628 {"bnu", BBOCB(16,BOF
,CBSO
,0,0), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BD
}},
3629 {"bnsl-", BBOCB(16,BOF
,CBSO
,0,1), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BDM
}},
3630 {"bnsl+", BBOCB(16,BOF
,CBSO
,0,1), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BDP
}},
3631 {"bnsl", BBOCB(16,BOF
,CBSO
,0,1), BBOATCB_MASK
, COM
, PPCNONE
, {CR
, BD
}},
3632 {"bnul-", BBOCB(16,BOF
,CBSO
,0,1), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BDM
}},
3633 {"bnul+", BBOCB(16,BOF
,CBSO
,0,1), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BDP
}},
3634 {"bnul", BBOCB(16,BOF
,CBSO
,0,1), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BD
}},
3635 {"bnsa-", BBOCB(16,BOF
,CBSO
,1,0), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BDMA
}},
3636 {"bnsa+", BBOCB(16,BOF
,CBSO
,1,0), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BDPA
}},
3637 {"bnsa", BBOCB(16,BOF
,CBSO
,1,0), BBOATCB_MASK
, COM
, PPCNONE
, {CR
, BDA
}},
3638 {"bnua-", BBOCB(16,BOF
,CBSO
,1,0), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BDMA
}},
3639 {"bnua+", BBOCB(16,BOF
,CBSO
,1,0), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BDPA
}},
3640 {"bnua", BBOCB(16,BOF
,CBSO
,1,0), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BDA
}},
3641 {"bnsla-", BBOCB(16,BOF
,CBSO
,1,1), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BDMA
}},
3642 {"bnsla+", BBOCB(16,BOF
,CBSO
,1,1), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BDPA
}},
3643 {"bnsla", BBOCB(16,BOF
,CBSO
,1,1), BBOATCB_MASK
, COM
, PPCNONE
, {CR
, BDA
}},
3644 {"bnula-", BBOCB(16,BOF
,CBSO
,1,1), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BDMA
}},
3645 {"bnula+", BBOCB(16,BOF
,CBSO
,1,1), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BDPA
}},
3646 {"bnula", BBOCB(16,BOF
,CBSO
,1,1), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BDA
}},
3648 {"blt-", BBOCB(16,BOT
,CBLT
,0,0), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BDM
}},
3649 {"blt+", BBOCB(16,BOT
,CBLT
,0,0), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BDP
}},
3650 {"blt", BBOCB(16,BOT
,CBLT
,0,0), BBOATCB_MASK
, COM
, PPCNONE
, {CR
, BD
}},
3651 {"bltl-", BBOCB(16,BOT
,CBLT
,0,1), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BDM
}},
3652 {"bltl+", BBOCB(16,BOT
,CBLT
,0,1), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BDP
}},
3653 {"bltl", BBOCB(16,BOT
,CBLT
,0,1), BBOATCB_MASK
, COM
, PPCNONE
, {CR
, BD
}},
3654 {"blta-", BBOCB(16,BOT
,CBLT
,1,0), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BDMA
}},
3655 {"blta+", BBOCB(16,BOT
,CBLT
,1,0), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BDPA
}},
3656 {"blta", BBOCB(16,BOT
,CBLT
,1,0), BBOATCB_MASK
, COM
, PPCNONE
, {CR
, BDA
}},
3657 {"bltla-", BBOCB(16,BOT
,CBLT
,1,1), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BDMA
}},
3658 {"bltla+", BBOCB(16,BOT
,CBLT
,1,1), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BDPA
}},
3659 {"bltla", BBOCB(16,BOT
,CBLT
,1,1), BBOATCB_MASK
, COM
, PPCNONE
, {CR
, BDA
}},
3660 {"bgt-", BBOCB(16,BOT
,CBGT
,0,0), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BDM
}},
3661 {"bgt+", BBOCB(16,BOT
,CBGT
,0,0), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BDP
}},
3662 {"bgt", BBOCB(16,BOT
,CBGT
,0,0), BBOATCB_MASK
, COM
, PPCNONE
, {CR
, BD
}},
3663 {"bgtl-", BBOCB(16,BOT
,CBGT
,0,1), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BDM
}},
3664 {"bgtl+", BBOCB(16,BOT
,CBGT
,0,1), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BDP
}},
3665 {"bgtl", BBOCB(16,BOT
,CBGT
,0,1), BBOATCB_MASK
, COM
, PPCNONE
, {CR
, BD
}},
3666 {"bgta-", BBOCB(16,BOT
,CBGT
,1,0), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BDMA
}},
3667 {"bgta+", BBOCB(16,BOT
,CBGT
,1,0), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BDPA
}},
3668 {"bgta", BBOCB(16,BOT
,CBGT
,1,0), BBOATCB_MASK
, COM
, PPCNONE
, {CR
, BDA
}},
3669 {"bgtla-", BBOCB(16,BOT
,CBGT
,1,1), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BDMA
}},
3670 {"bgtla+", BBOCB(16,BOT
,CBGT
,1,1), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BDPA
}},
3671 {"bgtla", BBOCB(16,BOT
,CBGT
,1,1), BBOATCB_MASK
, COM
, PPCNONE
, {CR
, BDA
}},
3672 {"beq-", BBOCB(16,BOT
,CBEQ
,0,0), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BDM
}},
3673 {"beq+", BBOCB(16,BOT
,CBEQ
,0,0), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BDP
}},
3674 {"beq", BBOCB(16,BOT
,CBEQ
,0,0), BBOATCB_MASK
, COM
, PPCNONE
, {CR
, BD
}},
3675 {"beql-", BBOCB(16,BOT
,CBEQ
,0,1), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BDM
}},
3676 {"beql+", BBOCB(16,BOT
,CBEQ
,0,1), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BDP
}},
3677 {"beql", BBOCB(16,BOT
,CBEQ
,0,1), BBOATCB_MASK
, COM
, PPCNONE
, {CR
, BD
}},
3678 {"beqa-", BBOCB(16,BOT
,CBEQ
,1,0), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BDMA
}},
3679 {"beqa+", BBOCB(16,BOT
,CBEQ
,1,0), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BDPA
}},
3680 {"beqa", BBOCB(16,BOT
,CBEQ
,1,0), BBOATCB_MASK
, COM
, PPCNONE
, {CR
, BDA
}},
3681 {"beqla-", BBOCB(16,BOT
,CBEQ
,1,1), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BDMA
}},
3682 {"beqla+", BBOCB(16,BOT
,CBEQ
,1,1), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BDPA
}},
3683 {"beqla", BBOCB(16,BOT
,CBEQ
,1,1), BBOATCB_MASK
, COM
, PPCNONE
, {CR
, BDA
}},
3684 {"bso-", BBOCB(16,BOT
,CBSO
,0,0), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BDM
}},
3685 {"bso+", BBOCB(16,BOT
,CBSO
,0,0), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BDP
}},
3686 {"bso", BBOCB(16,BOT
,CBSO
,0,0), BBOATCB_MASK
, COM
, PPCNONE
, {CR
, BD
}},
3687 {"bun-", BBOCB(16,BOT
,CBSO
,0,0), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BDM
}},
3688 {"bun+", BBOCB(16,BOT
,CBSO
,0,0), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BDP
}},
3689 {"bun", BBOCB(16,BOT
,CBSO
,0,0), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BD
}},
3690 {"bsol-", BBOCB(16,BOT
,CBSO
,0,1), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BDM
}},
3691 {"bsol+", BBOCB(16,BOT
,CBSO
,0,1), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BDP
}},
3692 {"bsol", BBOCB(16,BOT
,CBSO
,0,1), BBOATCB_MASK
, COM
, PPCNONE
, {CR
, BD
}},
3693 {"bunl-", BBOCB(16,BOT
,CBSO
,0,1), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BDM
}},
3694 {"bunl+", BBOCB(16,BOT
,CBSO
,0,1), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BDP
}},
3695 {"bunl", BBOCB(16,BOT
,CBSO
,0,1), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BD
}},
3696 {"bsoa-", BBOCB(16,BOT
,CBSO
,1,0), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BDMA
}},
3697 {"bsoa+", BBOCB(16,BOT
,CBSO
,1,0), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BDPA
}},
3698 {"bsoa", BBOCB(16,BOT
,CBSO
,1,0), BBOATCB_MASK
, COM
, PPCNONE
, {CR
, BDA
}},
3699 {"buna-", BBOCB(16,BOT
,CBSO
,1,0), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BDMA
}},
3700 {"buna+", BBOCB(16,BOT
,CBSO
,1,0), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BDPA
}},
3701 {"buna", BBOCB(16,BOT
,CBSO
,1,0), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BDA
}},
3702 {"bsola-", BBOCB(16,BOT
,CBSO
,1,1), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BDMA
}},
3703 {"bsola+", BBOCB(16,BOT
,CBSO
,1,1), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BDPA
}},
3704 {"bsola", BBOCB(16,BOT
,CBSO
,1,1), BBOATCB_MASK
, COM
, PPCNONE
, {CR
, BDA
}},
3705 {"bunla-", BBOCB(16,BOT
,CBSO
,1,1), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BDMA
}},
3706 {"bunla+", BBOCB(16,BOT
,CBSO
,1,1), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BDPA
}},
3707 {"bunla", BBOCB(16,BOT
,CBSO
,1,1), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BDA
}},
3709 {"bdnzf-", BBO(16,BODNZF
,0,0), BBOY_MASK
, PPCCOM
, ISA_V2
, {BI
, BDM
}},
3710 {"bdnzf+", BBO(16,BODNZF
,0,0), BBOY_MASK
, PPCCOM
, ISA_V2
, {BI
, BDP
}},
3711 {"bdnzf", BBO(16,BODNZF
,0,0), BBOY_MASK
, PPCCOM
, PPCNONE
, {BI
, BD
}},
3712 {"bdnzfl-", BBO(16,BODNZF
,0,1), BBOY_MASK
, PPCCOM
, ISA_V2
, {BI
, BDM
}},
3713 {"bdnzfl+", BBO(16,BODNZF
,0,1), BBOY_MASK
, PPCCOM
, ISA_V2
, {BI
, BDP
}},
3714 {"bdnzfl", BBO(16,BODNZF
,0,1), BBOY_MASK
, PPCCOM
, PPCNONE
, {BI
, BD
}},
3715 {"bdnzfa-", BBO(16,BODNZF
,1,0), BBOY_MASK
, PPCCOM
, ISA_V2
, {BI
, BDMA
}},
3716 {"bdnzfa+", BBO(16,BODNZF
,1,0), BBOY_MASK
, PPCCOM
, ISA_V2
, {BI
, BDPA
}},
3717 {"bdnzfa", BBO(16,BODNZF
,1,0), BBOY_MASK
, PPCCOM
, PPCNONE
, {BI
, BDA
}},
3718 {"bdnzfla-", BBO(16,BODNZF
,1,1), BBOY_MASK
, PPCCOM
, ISA_V2
, {BI
, BDMA
}},
3719 {"bdnzfla+", BBO(16,BODNZF
,1,1), BBOY_MASK
, PPCCOM
, ISA_V2
, {BI
, BDPA
}},
3720 {"bdnzfla", BBO(16,BODNZF
,1,1), BBOY_MASK
, PPCCOM
, PPCNONE
, {BI
, BDA
}},
3721 {"bdzf-", BBO(16,BODZF
,0,0), BBOY_MASK
, PPCCOM
, ISA_V2
, {BI
, BDM
}},
3722 {"bdzf+", BBO(16,BODZF
,0,0), BBOY_MASK
, PPCCOM
, ISA_V2
, {BI
, BDP
}},
3723 {"bdzf", BBO(16,BODZF
,0,0), BBOY_MASK
, PPCCOM
, PPCNONE
, {BI
, BD
}},
3724 {"bdzfl-", BBO(16,BODZF
,0,1), BBOY_MASK
, PPCCOM
, ISA_V2
, {BI
, BDM
}},
3725 {"bdzfl+", BBO(16,BODZF
,0,1), BBOY_MASK
, PPCCOM
, ISA_V2
, {BI
, BDP
}},
3726 {"bdzfl", BBO(16,BODZF
,0,1), BBOY_MASK
, PPCCOM
, PPCNONE
, {BI
, BD
}},
3727 {"bdzfa-", BBO(16,BODZF
,1,0), BBOY_MASK
, PPCCOM
, ISA_V2
, {BI
, BDMA
}},
3728 {"bdzfa+", BBO(16,BODZF
,1,0), BBOY_MASK
, PPCCOM
, ISA_V2
, {BI
, BDPA
}},
3729 {"bdzfa", BBO(16,BODZF
,1,0), BBOY_MASK
, PPCCOM
, PPCNONE
, {BI
, BDA
}},
3730 {"bdzfla-", BBO(16,BODZF
,1,1), BBOY_MASK
, PPCCOM
, ISA_V2
, {BI
, BDMA
}},
3731 {"bdzfla+", BBO(16,BODZF
,1,1), BBOY_MASK
, PPCCOM
, ISA_V2
, {BI
, BDPA
}},
3732 {"bdzfla", BBO(16,BODZF
,1,1), BBOY_MASK
, PPCCOM
, PPCNONE
, {BI
, BDA
}},
3734 {"bf-", BBO(16,BOF
,0,0), BBOAT_MASK
, PPCCOM
, PPCNONE
, {BI
, BDM
}},
3735 {"bf+", BBO(16,BOF
,0,0), BBOAT_MASK
, PPCCOM
, PPCNONE
, {BI
, BDP
}},
3736 {"bf", BBO(16,BOF
,0,0), BBOAT_MASK
, PPCCOM
, PPCNONE
, {BI
, BD
}},
3737 {"bbf", BBO(16,BOF
,0,0), BBOAT_MASK
, PWRCOM
, PPCNONE
, {BI
, BD
}},
3738 {"bfl-", BBO(16,BOF
,0,1), BBOAT_MASK
, PPCCOM
, PPCNONE
, {BI
, BDM
}},
3739 {"bfl+", BBO(16,BOF
,0,1), BBOAT_MASK
, PPCCOM
, PPCNONE
, {BI
, BDP
}},
3740 {"bfl", BBO(16,BOF
,0,1), BBOAT_MASK
, PPCCOM
, PPCNONE
, {BI
, BD
}},
3741 {"bbfl", BBO(16,BOF
,0,1), BBOAT_MASK
, PWRCOM
, PPCNONE
, {BI
, BD
}},
3742 {"bfa-", BBO(16,BOF
,1,0), BBOAT_MASK
, PPCCOM
, PPCNONE
, {BI
, BDMA
}},
3743 {"bfa+", BBO(16,BOF
,1,0), BBOAT_MASK
, PPCCOM
, PPCNONE
, {BI
, BDPA
}},
3744 {"bfa", BBO(16,BOF
,1,0), BBOAT_MASK
, PPCCOM
, PPCNONE
, {BI
, BDA
}},
3745 {"bbfa", BBO(16,BOF
,1,0), BBOAT_MASK
, PWRCOM
, PPCNONE
, {BI
, BDA
}},
3746 {"bfla-", BBO(16,BOF
,1,1), BBOAT_MASK
, PPCCOM
, PPCNONE
, {BI
, BDMA
}},
3747 {"bfla+", BBO(16,BOF
,1,1), BBOAT_MASK
, PPCCOM
, PPCNONE
, {BI
, BDPA
}},
3748 {"bfla", BBO(16,BOF
,1,1), BBOAT_MASK
, PPCCOM
, PPCNONE
, {BI
, BDA
}},
3749 {"bbfla", BBO(16,BOF
,1,1), BBOAT_MASK
, PWRCOM
, PPCNONE
, {BI
, BDA
}},
3751 {"bdnzt-", BBO(16,BODNZT
,0,0), BBOY_MASK
, PPCCOM
, ISA_V2
, {BI
, BDM
}},
3752 {"bdnzt+", BBO(16,BODNZT
,0,0), BBOY_MASK
, PPCCOM
, ISA_V2
, {BI
, BDP
}},
3753 {"bdnzt", BBO(16,BODNZT
,0,0), BBOY_MASK
, PPCCOM
, PPCNONE
, {BI
, BD
}},
3754 {"bdnztl-", BBO(16,BODNZT
,0,1), BBOY_MASK
, PPCCOM
, ISA_V2
, {BI
, BDM
}},
3755 {"bdnztl+", BBO(16,BODNZT
,0,1), BBOY_MASK
, PPCCOM
, ISA_V2
, {BI
, BDP
}},
3756 {"bdnztl", BBO(16,BODNZT
,0,1), BBOY_MASK
, PPCCOM
, PPCNONE
, {BI
, BD
}},
3757 {"bdnzta-", BBO(16,BODNZT
,1,0), BBOY_MASK
, PPCCOM
, ISA_V2
, {BI
, BDMA
}},
3758 {"bdnzta+", BBO(16,BODNZT
,1,0), BBOY_MASK
, PPCCOM
, ISA_V2
, {BI
, BDPA
}},
3759 {"bdnzta", BBO(16,BODNZT
,1,0), BBOY_MASK
, PPCCOM
, PPCNONE
, {BI
, BDA
}},
3760 {"bdnztla-", BBO(16,BODNZT
,1,1), BBOY_MASK
, PPCCOM
, ISA_V2
, {BI
, BDMA
}},
3761 {"bdnztla+", BBO(16,BODNZT
,1,1), BBOY_MASK
, PPCCOM
, ISA_V2
, {BI
, BDPA
}},
3762 {"bdnztla", BBO(16,BODNZT
,1,1), BBOY_MASK
, PPCCOM
, PPCNONE
, {BI
, BDA
}},
3763 {"bdzt-", BBO(16,BODZT
,0,0), BBOY_MASK
, PPCCOM
, ISA_V2
, {BI
, BDM
}},
3764 {"bdzt+", BBO(16,BODZT
,0,0), BBOY_MASK
, PPCCOM
, ISA_V2
, {BI
, BDP
}},
3765 {"bdzt", BBO(16,BODZT
,0,0), BBOY_MASK
, PPCCOM
, PPCNONE
, {BI
, BD
}},
3766 {"bdztl-", BBO(16,BODZT
,0,1), BBOY_MASK
, PPCCOM
, ISA_V2
, {BI
, BDM
}},
3767 {"bdztl+", BBO(16,BODZT
,0,1), BBOY_MASK
, PPCCOM
, ISA_V2
, {BI
, BDP
}},
3768 {"bdztl", BBO(16,BODZT
,0,1), BBOY_MASK
, PPCCOM
, PPCNONE
, {BI
, BD
}},
3769 {"bdzta-", BBO(16,BODZT
,1,0), BBOY_MASK
, PPCCOM
, ISA_V2
, {BI
, BDMA
}},
3770 {"bdzta+", BBO(16,BODZT
,1,0), BBOY_MASK
, PPCCOM
, ISA_V2
, {BI
, BDPA
}},
3771 {"bdzta", BBO(16,BODZT
,1,0), BBOY_MASK
, PPCCOM
, PPCNONE
, {BI
, BDA
}},
3772 {"bdztla-", BBO(16,BODZT
,1,1), BBOY_MASK
, PPCCOM
, ISA_V2
, {BI
, BDMA
}},
3773 {"bdztla+", BBO(16,BODZT
,1,1), BBOY_MASK
, PPCCOM
, ISA_V2
, {BI
, BDPA
}},
3774 {"bdztla", BBO(16,BODZT
,1,1), BBOY_MASK
, PPCCOM
, PPCNONE
, {BI
, BDA
}},
3776 {"bt-", BBO(16,BOT
,0,0), BBOAT_MASK
, PPCCOM
, PPCNONE
, {BI
, BDM
}},
3777 {"bt+", BBO(16,BOT
,0,0), BBOAT_MASK
, PPCCOM
, PPCNONE
, {BI
, BDP
}},
3778 {"bt", BBO(16,BOT
,0,0), BBOAT_MASK
, PPCCOM
, PPCNONE
, {BI
, BD
}},
3779 {"bbt", BBO(16,BOT
,0,0), BBOAT_MASK
, PWRCOM
, PPCNONE
, {BI
, BD
}},
3780 {"btl-", BBO(16,BOT
,0,1), BBOAT_MASK
, PPCCOM
, PPCNONE
, {BI
, BDM
}},
3781 {"btl+", BBO(16,BOT
,0,1), BBOAT_MASK
, PPCCOM
, PPCNONE
, {BI
, BDP
}},
3782 {"btl", BBO(16,BOT
,0,1), BBOAT_MASK
, PPCCOM
, PPCNONE
, {BI
, BD
}},
3783 {"bbtl", BBO(16,BOT
,0,1), BBOAT_MASK
, PWRCOM
, PPCNONE
, {BI
, BD
}},
3784 {"bta-", BBO(16,BOT
,1,0), BBOAT_MASK
, PPCCOM
, PPCNONE
, {BI
, BDMA
}},
3785 {"bta+", BBO(16,BOT
,1,0), BBOAT_MASK
, PPCCOM
, PPCNONE
, {BI
, BDPA
}},
3786 {"bta", BBO(16,BOT
,1,0), BBOAT_MASK
, PPCCOM
, PPCNONE
, {BI
, BDA
}},
3787 {"bbta", BBO(16,BOT
,1,0), BBOAT_MASK
, PWRCOM
, PPCNONE
, {BI
, BDA
}},
3788 {"btla-", BBO(16,BOT
,1,1), BBOAT_MASK
, PPCCOM
, PPCNONE
, {BI
, BDMA
}},
3789 {"btla+", BBO(16,BOT
,1,1), BBOAT_MASK
, PPCCOM
, PPCNONE
, {BI
, BDPA
}},
3790 {"btla", BBO(16,BOT
,1,1), BBOAT_MASK
, PPCCOM
, PPCNONE
, {BI
, BDA
}},
3791 {"bbtla", BBO(16,BOT
,1,1), BBOAT_MASK
, PWRCOM
, PPCNONE
, {BI
, BDA
}},
3793 {"bc-", B(16,0,0), B_MASK
, PPCCOM
, PPCNONE
, {BOE
, BI
, BDM
}},
3794 {"bc+", B(16,0,0), B_MASK
, PPCCOM
, PPCNONE
, {BOE
, BI
, BDP
}},
3795 {"bc", B(16,0,0), B_MASK
, COM
, PPCNONE
, {BO
, BI
, BD
}},
3796 {"bcl-", B(16,0,1), B_MASK
, PPCCOM
, PPCNONE
, {BOE
, BI
, BDM
}},
3797 {"bcl+", B(16,0,1), B_MASK
, PPCCOM
, PPCNONE
, {BOE
, BI
, BDP
}},
3798 {"bcl", B(16,0,1), B_MASK
, COM
, PPCNONE
, {BO
, BI
, BD
}},
3799 {"bca-", B(16,1,0), B_MASK
, PPCCOM
, PPCNONE
, {BOE
, BI
, BDMA
}},
3800 {"bca+", B(16,1,0), B_MASK
, PPCCOM
, PPCNONE
, {BOE
, BI
, BDPA
}},
3801 {"bca", B(16,1,0), B_MASK
, COM
, PPCNONE
, {BO
, BI
, BDA
}},
3802 {"bcla-", B(16,1,1), B_MASK
, PPCCOM
, PPCNONE
, {BOE
, BI
, BDMA
}},
3803 {"bcla+", B(16,1,1), B_MASK
, PPCCOM
, PPCNONE
, {BOE
, BI
, BDPA
}},
3804 {"bcla", B(16,1,1), B_MASK
, COM
, PPCNONE
, {BO
, BI
, BDA
}},
3806 {"svc", SC(17,0,0), SC_MASK
, POWER
, PPCNONE
, {SVC_LEV
, FL1
, FL2
}},
3807 {"svcl", SC(17,0,1), SC_MASK
, POWER
, PPCNONE
, {SVC_LEV
, FL1
, FL2
}},
3808 {"sc", SC(17,1,0), SC_MASK
, PPC
, PPCNONE
, {LEV
}},
3809 {"svca", SC(17,1,0), SC_MASK
, PWRCOM
, PPCNONE
, {SV
}},
3810 {"svcla", SC(17,1,1), SC_MASK
, POWER
, PPCNONE
, {SV
}},
3812 {"b", B(18,0,0), B_MASK
, COM
, PPCNONE
, {LI
}},
3813 {"bl", B(18,0,1), B_MASK
, COM
, PPCNONE
, {LI
}},
3814 {"ba", B(18,1,0), B_MASK
, COM
, PPCNONE
, {LIA
}},
3815 {"bla", B(18,1,1), B_MASK
, COM
, PPCNONE
, {LIA
}},
3817 {"mcrf", XL(19,0), XLBB_MASK
|(3<<21)|(3<<16), COM
, PPCNONE
, {BF
, BFA
}},
3819 {"bdnzlr", XLO(19,BODNZ
,16,0), XLBOBIBB_MASK
, PPCCOM
, PPCNONE
, {0}},
3820 {"bdnzlr-", XLO(19,BODNZ
,16,0), XLBOBIBB_MASK
, PPCCOM
, ISA_V2
, {0}},
3821 {"bdnzlrl", XLO(19,BODNZ
,16,1), XLBOBIBB_MASK
, PPCCOM
, PPCNONE
, {0}},
3822 {"bdnzlrl-", XLO(19,BODNZ
,16,1), XLBOBIBB_MASK
, PPCCOM
, ISA_V2
, {0}},
3823 {"bdnzlr+", XLO(19,BODNZP
,16,0), XLBOBIBB_MASK
, PPCCOM
, ISA_V2
, {0}},
3824 {"bdnzlrl+", XLO(19,BODNZP
,16,1), XLBOBIBB_MASK
, PPCCOM
, ISA_V2
, {0}},
3825 {"bdzlr", XLO(19,BODZ
,16,0), XLBOBIBB_MASK
, PPCCOM
, PPCNONE
, {0}},
3826 {"bdzlr-", XLO(19,BODZ
,16,0), XLBOBIBB_MASK
, PPCCOM
, ISA_V2
, {0}},
3827 {"bdzlrl", XLO(19,BODZ
,16,1), XLBOBIBB_MASK
, PPCCOM
, PPCNONE
, {0}},
3828 {"bdzlrl-", XLO(19,BODZ
,16,1), XLBOBIBB_MASK
, PPCCOM
, ISA_V2
, {0}},
3829 {"bdzlr+", XLO(19,BODZP
,16,0), XLBOBIBB_MASK
, PPCCOM
, ISA_V2
, {0}},
3830 {"bdzlrl+", XLO(19,BODZP
,16,1), XLBOBIBB_MASK
, PPCCOM
, ISA_V2
, {0}},
3831 {"blr", XLO(19,BOU
,16,0), XLBOBIBB_MASK
, PPCCOM
, PPCNONE
, {0}},
3832 {"br", XLO(19,BOU
,16,0), XLBOBIBB_MASK
, PWRCOM
, PPCNONE
, {0}},
3833 {"blrl", XLO(19,BOU
,16,1), XLBOBIBB_MASK
, PPCCOM
, PPCNONE
, {0}},
3834 {"brl", XLO(19,BOU
,16,1), XLBOBIBB_MASK
, PWRCOM
, PPCNONE
, {0}},
3835 {"bdnzlr-", XLO(19,BODNZM4
,16,0), XLBOBIBB_MASK
, ISA_V2
, PPCNONE
, {0}},
3836 {"bdnzlrl-", XLO(19,BODNZM4
,16,1), XLBOBIBB_MASK
, ISA_V2
, PPCNONE
, {0}},
3837 {"bdnzlr+", XLO(19,BODNZP4
,16,0), XLBOBIBB_MASK
, ISA_V2
, PPCNONE
, {0}},
3838 {"bdnzlrl+", XLO(19,BODNZP4
,16,1), XLBOBIBB_MASK
, ISA_V2
, PPCNONE
, {0}},
3839 {"bdzlr-", XLO(19,BODZM4
,16,0), XLBOBIBB_MASK
, ISA_V2
, PPCNONE
, {0}},
3840 {"bdzlrl-", XLO(19,BODZM4
,16,1), XLBOBIBB_MASK
, ISA_V2
, PPCNONE
, {0}},
3841 {"bdzlr+", XLO(19,BODZP4
,16,0), XLBOBIBB_MASK
, ISA_V2
, PPCNONE
, {0}},
3842 {"bdzlrl+", XLO(19,BODZP4
,16,1), XLBOBIBB_MASK
, ISA_V2
, PPCNONE
, {0}},
3844 {"bgelr", XLOCB(19,BOF
,CBLT
,16,0), XLBOCBBB_MASK
, PPCCOM
, PPCNONE
, {CR
}},
3845 {"bgelr-", XLOCB(19,BOF
,CBLT
,16,0), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
, {CR
}},
3846 {"bger", XLOCB(19,BOF
,CBLT
,16,0), XLBOCBBB_MASK
, PWRCOM
, PPCNONE
, {CR
}},
3847 {"bnllr", XLOCB(19,BOF
,CBLT
,16,0), XLBOCBBB_MASK
, PPCCOM
, PPCNONE
, {CR
}},
3848 {"bnllr-", XLOCB(19,BOF
,CBLT
,16,0), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
, {CR
}},
3849 {"bnlr", XLOCB(19,BOF
,CBLT
,16,0), XLBOCBBB_MASK
, PWRCOM
, PPCNONE
, {CR
}},
3850 {"bgelrl", XLOCB(19,BOF
,CBLT
,16,1), XLBOCBBB_MASK
, PPCCOM
, PPCNONE
, {CR
}},
3851 {"bgelrl-", XLOCB(19,BOF
,CBLT
,16,1), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
, {CR
}},
3852 {"bgerl", XLOCB(19,BOF
,CBLT
,16,1), XLBOCBBB_MASK
, PWRCOM
, PPCNONE
, {CR
}},
3853 {"bnllrl", XLOCB(19,BOF
,CBLT
,16,1), XLBOCBBB_MASK
, PPCCOM
, PPCNONE
, {CR
}},
3854 {"bnllrl-", XLOCB(19,BOF
,CBLT
,16,1), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
, {CR
}},
3855 {"bnlrl", XLOCB(19,BOF
,CBLT
,16,1), XLBOCBBB_MASK
, PWRCOM
, PPCNONE
, {CR
}},
3856 {"blelr", XLOCB(19,BOF
,CBGT
,16,0), XLBOCBBB_MASK
, PPCCOM
, PPCNONE
, {CR
}},
3857 {"blelr-", XLOCB(19,BOF
,CBGT
,16,0), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
, {CR
}},
3858 {"bler", XLOCB(19,BOF
,CBGT
,16,0), XLBOCBBB_MASK
, PWRCOM
, PPCNONE
, {CR
}},
3859 {"bnglr", XLOCB(19,BOF
,CBGT
,16,0), XLBOCBBB_MASK
, PPCCOM
, PPCNONE
, {CR
}},
3860 {"bnglr-", XLOCB(19,BOF
,CBGT
,16,0), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
, {CR
}},
3861 {"bngr", XLOCB(19,BOF
,CBGT
,16,0), XLBOCBBB_MASK
, PWRCOM
, PPCNONE
, {CR
}},
3862 {"blelrl", XLOCB(19,BOF
,CBGT
,16,1), XLBOCBBB_MASK
, PPCCOM
, PPCNONE
, {CR
}},
3863 {"blelrl-", XLOCB(19,BOF
,CBGT
,16,1), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
, {CR
}},
3864 {"blerl", XLOCB(19,BOF
,CBGT
,16,1), XLBOCBBB_MASK
, PWRCOM
, PPCNONE
, {CR
}},
3865 {"bnglrl", XLOCB(19,BOF
,CBGT
,16,1), XLBOCBBB_MASK
, PPCCOM
, PPCNONE
, {CR
}},
3866 {"bnglrl-", XLOCB(19,BOF
,CBGT
,16,1), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
, {CR
}},
3867 {"bngrl", XLOCB(19,BOF
,CBGT
,16,1), XLBOCBBB_MASK
, PWRCOM
, PPCNONE
, {CR
}},
3868 {"bnelr", XLOCB(19,BOF
,CBEQ
,16,0), XLBOCBBB_MASK
, PPCCOM
, PPCNONE
, {CR
}},
3869 {"bnelr-", XLOCB(19,BOF
,CBEQ
,16,0), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
, {CR
}},
3870 {"bner", XLOCB(19,BOF
,CBEQ
,16,0), XLBOCBBB_MASK
, PWRCOM
, PPCNONE
, {CR
}},
3871 {"bnelrl", XLOCB(19,BOF
,CBEQ
,16,1), XLBOCBBB_MASK
, PPCCOM
, PPCNONE
, {CR
}},
3872 {"bnelrl-", XLOCB(19,BOF
,CBEQ
,16,1), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
, {CR
}},
3873 {"bnerl", XLOCB(19,BOF
,CBEQ
,16,1), XLBOCBBB_MASK
, PWRCOM
, PPCNONE
, {CR
}},
3874 {"bnslr", XLOCB(19,BOF
,CBSO
,16,0), XLBOCBBB_MASK
, PPCCOM
, PPCNONE
, {CR
}},
3875 {"bnslr-", XLOCB(19,BOF
,CBSO
,16,0), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
, {CR
}},
3876 {"bnsr", XLOCB(19,BOF
,CBSO
,16,0), XLBOCBBB_MASK
, PWRCOM
, PPCNONE
, {CR
}},
3877 {"bnulr", XLOCB(19,BOF
,CBSO
,16,0), XLBOCBBB_MASK
, PPCCOM
, PPCNONE
, {CR
}},
3878 {"bnulr-", XLOCB(19,BOF
,CBSO
,16,0), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
, {CR
}},
3879 {"bnslrl", XLOCB(19,BOF
,CBSO
,16,1), XLBOCBBB_MASK
, PPCCOM
, PPCNONE
, {CR
}},
3880 {"bnslrl-", XLOCB(19,BOF
,CBSO
,16,1), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
, {CR
}},
3881 {"bnsrl", XLOCB(19,BOF
,CBSO
,16,1), XLBOCBBB_MASK
, PWRCOM
, PPCNONE
, {CR
}},
3882 {"bnulrl", XLOCB(19,BOF
,CBSO
,16,1), XLBOCBBB_MASK
, PPCCOM
, PPCNONE
, {CR
}},
3883 {"bnulrl-", XLOCB(19,BOF
,CBSO
,16,1), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
, {CR
}},
3884 {"bgelr+", XLOCB(19,BOFP
,CBLT
,16,0), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
, {CR
}},
3885 {"bnllr+", XLOCB(19,BOFP
,CBLT
,16,0), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
, {CR
}},
3886 {"bgelrl+", XLOCB(19,BOFP
,CBLT
,16,1), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
, {CR
}},
3887 {"bnllrl+", XLOCB(19,BOFP
,CBLT
,16,1), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
, {CR
}},
3888 {"blelr+", XLOCB(19,BOFP
,CBGT
,16,0), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
, {CR
}},
3889 {"bnglr+", XLOCB(19,BOFP
,CBGT
,16,0), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
, {CR
}},
3890 {"blelrl+", XLOCB(19,BOFP
,CBGT
,16,1), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
, {CR
}},
3891 {"bnglrl+", XLOCB(19,BOFP
,CBGT
,16,1), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
, {CR
}},
3892 {"bnelr+", XLOCB(19,BOFP
,CBEQ
,16,0), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
, {CR
}},
3893 {"bnelrl+", XLOCB(19,BOFP
,CBEQ
,16,1), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
, {CR
}},
3894 {"bnslr+", XLOCB(19,BOFP
,CBSO
,16,0), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
, {CR
}},
3895 {"bnulr+", XLOCB(19,BOFP
,CBSO
,16,0), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
, {CR
}},
3896 {"bnslrl+", XLOCB(19,BOFP
,CBSO
,16,1), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
, {CR
}},
3897 {"bnulrl+", XLOCB(19,BOFP
,CBSO
,16,1), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
, {CR
}},
3898 {"bgelr-", XLOCB(19,BOFM4
,CBLT
,16,0), XLBOCBBB_MASK
, ISA_V2
, PPCNONE
, {CR
}},
3899 {"bnllr-", XLOCB(19,BOFM4
,CBLT
,16,0), XLBOCBBB_MASK
, ISA_V2
, PPCNONE
, {CR
}},
3900 {"bgelrl-", XLOCB(19,BOFM4
,CBLT
,16,1), XLBOCBBB_MASK
, ISA_V2
, PPCNONE
, {CR
}},
3901 {"bnllrl-", XLOCB(19,BOFM4
,CBLT
,16,1), XLBOCBBB_MASK
, ISA_V2
, PPCNONE
, {CR
}},
3902 {"blelr-", XLOCB(19,BOFM4
,CBGT
,16,0), XLBOCBBB_MASK
, ISA_V2
, PPCNONE
, {CR
}},
3903 {"bnglr-", XLOCB(19,BOFM4
,CBGT
,16,0), XLBOCBBB_MASK
, ISA_V2
, PPCNONE
, {CR
}},
3904 {"blelrl-", XLOCB(19,BOFM4
,CBGT
,16,1), XLBOCBBB_MASK
, ISA_V2
, PPCNONE
, {CR
}},
3905 {"bnglrl-", XLOCB(19,BOFM4
,CBGT
,16,1), XLBOCBBB_MASK
, ISA_V2
, PPCNONE
, {CR
}},
3906 {"bnelr-", XLOCB(19,BOFM4
,CBEQ
,16,0), XLBOCBBB_MASK
, ISA_V2
, PPCNONE
, {CR
}},
3907 {"bnelrl-", XLOCB(19,BOFM4
,CBEQ
,16,1), XLBOCBBB_MASK
, ISA_V2
, PPCNONE
, {CR
}},
3908 {"bnslr-", XLOCB(19,BOFM4
,CBSO
,16,0), XLBOCBBB_MASK
, ISA_V2
, PPCNONE
, {CR
}},
3909 {"bnulr-", XLOCB(19,BOFM4
,CBSO
,16,0), XLBOCBBB_MASK
, ISA_V2
, PPCNONE
, {CR
}},
3910 {"bnslrl-", XLOCB(19,BOFM4
,CBSO
,16,1), XLBOCBBB_MASK
, ISA_V2
, PPCNONE
, {CR
}},
3911 {"bnulrl-", XLOCB(19,BOFM4
,CBSO
,16,1), XLBOCBBB_MASK
, ISA_V2
, PPCNONE
, {CR
}},
3912 {"bgelr+", XLOCB(19,BOFP4
,CBLT
,16,0), XLBOCBBB_MASK
, ISA_V2
, PPCNONE
, {CR
}},
3913 {"bnllr+", XLOCB(19,BOFP4
,CBLT
,16,0), XLBOCBBB_MASK
, ISA_V2
, PPCNONE
, {CR
}},
3914 {"bgelrl+", XLOCB(19,BOFP4
,CBLT
,16,1), XLBOCBBB_MASK
, ISA_V2
, PPCNONE
, {CR
}},
3915 {"bnllrl+", XLOCB(19,BOFP4
,CBLT
,16,1), XLBOCBBB_MASK
, ISA_V2
, PPCNONE
, {CR
}},
3916 {"blelr+", XLOCB(19,BOFP4
,CBGT
,16,0), XLBOCBBB_MASK
, ISA_V2
, PPCNONE
, {CR
}},
3917 {"bnglr+", XLOCB(19,BOFP4
,CBGT
,16,0), XLBOCBBB_MASK
, ISA_V2
, PPCNONE
, {CR
}},
3918 {"blelrl+", XLOCB(19,BOFP4
,CBGT
,16,1), XLBOCBBB_MASK
, ISA_V2
, PPCNONE
, {CR
}},
3919 {"bnglrl+", XLOCB(19,BOFP4
,CBGT
,16,1), XLBOCBBB_MASK
, ISA_V2
, PPCNONE
, {CR
}},
3920 {"bnelr+", XLOCB(19,BOFP4
,CBEQ
,16,0), XLBOCBBB_MASK
, ISA_V2
, PPCNONE
, {CR
}},
3921 {"bnelrl+", XLOCB(19,BOFP4
,CBEQ
,16,1), XLBOCBBB_MASK
, ISA_V2
, PPCNONE
, {CR
}},
3922 {"bnslr+", XLOCB(19,BOFP4
,CBSO
,16,0), XLBOCBBB_MASK
, ISA_V2
, PPCNONE
, {CR
}},
3923 {"bnulr+", XLOCB(19,BOFP4
,CBSO
,16,0), XLBOCBBB_MASK
, ISA_V2
, PPCNONE
, {CR
}},
3924 {"bnslrl+", XLOCB(19,BOFP4
,CBSO
,16,1), XLBOCBBB_MASK
, ISA_V2
, PPCNONE
, {CR
}},
3925 {"bnulrl+", XLOCB(19,BOFP4
,CBSO
,16,1), XLBOCBBB_MASK
, ISA_V2
, PPCNONE
, {CR
}},
3926 {"bltlr", XLOCB(19,BOT
,CBLT
,16,0), XLBOCBBB_MASK
, PPCCOM
, PPCNONE
, {CR
}},
3927 {"bltlr-", XLOCB(19,BOT
,CBLT
,16,0), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
, {CR
}},
3928 {"bltr", XLOCB(19,BOT
,CBLT
,16,0), XLBOCBBB_MASK
, PWRCOM
, PPCNONE
, {CR
}},
3929 {"bltlrl", XLOCB(19,BOT
,CBLT
,16,1), XLBOCBBB_MASK
, PPCCOM
, PPCNONE
, {CR
}},
3930 {"bltlrl-", XLOCB(19,BOT
,CBLT
,16,1), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
, {CR
}},
3931 {"bltrl", XLOCB(19,BOT
,CBLT
,16,1), XLBOCBBB_MASK
, PWRCOM
, PPCNONE
, {CR
}},
3932 {"bgtlr", XLOCB(19,BOT
,CBGT
,16,0), XLBOCBBB_MASK
, PPCCOM
, PPCNONE
, {CR
}},
3933 {"bgtlr-", XLOCB(19,BOT
,CBGT
,16,0), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
, {CR
}},
3934 {"bgtr", XLOCB(19,BOT
,CBGT
,16,0), XLBOCBBB_MASK
, PWRCOM
, PPCNONE
, {CR
}},
3935 {"bgtlrl", XLOCB(19,BOT
,CBGT
,16,1), XLBOCBBB_MASK
, PPCCOM
, PPCNONE
, {CR
}},
3936 {"bgtlrl-", XLOCB(19,BOT
,CBGT
,16,1), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
, {CR
}},
3937 {"bgtrl", XLOCB(19,BOT
,CBGT
,16,1), XLBOCBBB_MASK
, PWRCOM
, PPCNONE
, {CR
}},
3938 {"beqlr", XLOCB(19,BOT
,CBEQ
,16,0), XLBOCBBB_MASK
, PPCCOM
, PPCNONE
, {CR
}},
3939 {"beqlr-", XLOCB(19,BOT
,CBEQ
,16,0), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
, {CR
}},
3940 {"beqr", XLOCB(19,BOT
,CBEQ
,16,0), XLBOCBBB_MASK
, PWRCOM
, PPCNONE
, {CR
}},
3941 {"beqlrl", XLOCB(19,BOT
,CBEQ
,16,1), XLBOCBBB_MASK
, PPCCOM
, PPCNONE
, {CR
}},
3942 {"beqlrl-", XLOCB(19,BOT
,CBEQ
,16,1), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
, {CR
}},
3943 {"beqrl", XLOCB(19,BOT
,CBEQ
,16,1), XLBOCBBB_MASK
, PWRCOM
, PPCNONE
, {CR
}},
3944 {"bsolr", XLOCB(19,BOT
,CBSO
,16,0), XLBOCBBB_MASK
, PPCCOM
, PPCNONE
, {CR
}},
3945 {"bsolr-", XLOCB(19,BOT
,CBSO
,16,0), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
, {CR
}},
3946 {"bsor", XLOCB(19,BOT
,CBSO
,16,0), XLBOCBBB_MASK
, PWRCOM
, PPCNONE
, {CR
}},
3947 {"bunlr", XLOCB(19,BOT
,CBSO
,16,0), XLBOCBBB_MASK
, PPCCOM
, PPCNONE
, {CR
}},
3948 {"bunlr-", XLOCB(19,BOT
,CBSO
,16,0), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
, {CR
}},
3949 {"bsolrl", XLOCB(19,BOT
,CBSO
,16,1), XLBOCBBB_MASK
, PPCCOM
, PPCNONE
, {CR
}},
3950 {"bsolrl-", XLOCB(19,BOT
,CBSO
,16,1), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
, {CR
}},
3951 {"bsorl", XLOCB(19,BOT
,CBSO
,16,1), XLBOCBBB_MASK
, PWRCOM
, PPCNONE
, {CR
}},
3952 {"bunlrl", XLOCB(19,BOT
,CBSO
,16,1), XLBOCBBB_MASK
, PPCCOM
, PPCNONE
, {CR
}},
3953 {"bunlrl-", XLOCB(19,BOT
,CBSO
,16,1), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
, {CR
}},
3954 {"bltlr+", XLOCB(19,BOTP
,CBLT
,16,0), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
, {CR
}},
3955 {"bltlrl+", XLOCB(19,BOTP
,CBLT
,16,1), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
, {CR
}},
3956 {"bgtlr+", XLOCB(19,BOTP
,CBGT
,16,0), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
, {CR
}},
3957 {"bgtlrl+", XLOCB(19,BOTP
,CBGT
,16,1), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
, {CR
}},
3958 {"beqlr+", XLOCB(19,BOTP
,CBEQ
,16,0), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
, {CR
}},
3959 {"beqlrl+", XLOCB(19,BOTP
,CBEQ
,16,1), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
, {CR
}},
3960 {"bsolr+", XLOCB(19,BOTP
,CBSO
,16,0), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
, {CR
}},
3961 {"bunlr+", XLOCB(19,BOTP
,CBSO
,16,0), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
, {CR
}},
3962 {"bsolrl+", XLOCB(19,BOTP
,CBSO
,16,1), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
, {CR
}},
3963 {"bunlrl+", XLOCB(19,BOTP
,CBSO
,16,1), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
, {CR
}},
3964 {"bltlr-", XLOCB(19,BOTM4
,CBLT
,16,0), XLBOCBBB_MASK
, ISA_V2
, PPCNONE
, {CR
}},
3965 {"bltlrl-", XLOCB(19,BOTM4
,CBLT
,16,1), XLBOCBBB_MASK
, ISA_V2
, PPCNONE
, {CR
}},
3966 {"bgtlr-", XLOCB(19,BOTM4
,CBGT
,16,0), XLBOCBBB_MASK
, ISA_V2
, PPCNONE
, {CR
}},
3967 {"bgtlrl-", XLOCB(19,BOTM4
,CBGT
,16,1), XLBOCBBB_MASK
, ISA_V2
, PPCNONE
, {CR
}},
3968 {"beqlr-", XLOCB(19,BOTM4
,CBEQ
,16,0), XLBOCBBB_MASK
, ISA_V2
, PPCNONE
, {CR
}},
3969 {"beqlrl-", XLOCB(19,BOTM4
,CBEQ
,16,1), XLBOCBBB_MASK
, ISA_V2
, PPCNONE
, {CR
}},
3970 {"bsolr-", XLOCB(19,BOTM4
,CBSO
,16,0), XLBOCBBB_MASK
, ISA_V2
, PPCNONE
, {CR
}},
3971 {"bunlr-", XLOCB(19,BOTM4
,CBSO
,16,0), XLBOCBBB_MASK
, ISA_V2
, PPCNONE
, {CR
}},
3972 {"bsolrl-", XLOCB(19,BOTM4
,CBSO
,16,1), XLBOCBBB_MASK
, ISA_V2
, PPCNONE
, {CR
}},
3973 {"bunlrl-", XLOCB(19,BOTM4
,CBSO
,16,1), XLBOCBBB_MASK
, ISA_V2
, PPCNONE
, {CR
}},
3974 {"bltlr+", XLOCB(19,BOTP4
,CBLT
,16,0), XLBOCBBB_MASK
, ISA_V2
, PPCNONE
, {CR
}},
3975 {"bltlrl+", XLOCB(19,BOTP4
,CBLT
,16,1), XLBOCBBB_MASK
, ISA_V2
, PPCNONE
, {CR
}},
3976 {"bgtlr+", XLOCB(19,BOTP4
,CBGT
,16,0), XLBOCBBB_MASK
, ISA_V2
, PPCNONE
, {CR
}},
3977 {"bgtlrl+", XLOCB(19,BOTP4
,CBGT
,16,1), XLBOCBBB_MASK
, ISA_V2
, PPCNONE
, {CR
}},
3978 {"beqlr+", XLOCB(19,BOTP4
,CBEQ
,16,0), XLBOCBBB_MASK
, ISA_V2
, PPCNONE
, {CR
}},
3979 {"beqlrl+", XLOCB(19,BOTP4
,CBEQ
,16,1), XLBOCBBB_MASK
, ISA_V2
, PPCNONE
, {CR
}},
3980 {"bsolr+", XLOCB(19,BOTP4
,CBSO
,16,0), XLBOCBBB_MASK
, ISA_V2
, PPCNONE
, {CR
}},
3981 {"bunlr+", XLOCB(19,BOTP4
,CBSO
,16,0), XLBOCBBB_MASK
, ISA_V2
, PPCNONE
, {CR
}},
3982 {"bsolrl+", XLOCB(19,BOTP4
,CBSO
,16,1), XLBOCBBB_MASK
, ISA_V2
, PPCNONE
, {CR
}},
3983 {"bunlrl+", XLOCB(19,BOTP4
,CBSO
,16,1), XLBOCBBB_MASK
, ISA_V2
, PPCNONE
, {CR
}},
3985 {"bdnzflr", XLO(19,BODNZF
,16,0), XLBOBB_MASK
, PPCCOM
, PPCNONE
, {BI
}},
3986 {"bdnzflr-", XLO(19,BODNZF
,16,0), XLBOBB_MASK
, PPCCOM
, ISA_V2
, {BI
}},
3987 {"bdnzflrl", XLO(19,BODNZF
,16,1), XLBOBB_MASK
, PPCCOM
, PPCNONE
, {BI
}},
3988 {"bdnzflrl-",XLO(19,BODNZF
,16,1), XLBOBB_MASK
, PPCCOM
, ISA_V2
, {BI
}},
3989 {"bdnzflr+", XLO(19,BODNZFP
,16,0), XLBOBB_MASK
, PPCCOM
, ISA_V2
, {BI
}},
3990 {"bdnzflrl+",XLO(19,BODNZFP
,16,1), XLBOBB_MASK
, PPCCOM
, ISA_V2
, {BI
}},
3991 {"bdzflr", XLO(19,BODZF
,16,0), XLBOBB_MASK
, PPCCOM
, PPCNONE
, {BI
}},
3992 {"bdzflr-", XLO(19,BODZF
,16,0), XLBOBB_MASK
, PPCCOM
, ISA_V2
, {BI
}},
3993 {"bdzflrl", XLO(19,BODZF
,16,1), XLBOBB_MASK
, PPCCOM
, PPCNONE
, {BI
}},
3994 {"bdzflrl-", XLO(19,BODZF
,16,1), XLBOBB_MASK
, PPCCOM
, ISA_V2
, {BI
}},
3995 {"bdzflr+", XLO(19,BODZFP
,16,0), XLBOBB_MASK
, PPCCOM
, ISA_V2
, {BI
}},
3996 {"bdzflrl+", XLO(19,BODZFP
,16,1), XLBOBB_MASK
, PPCCOM
, ISA_V2
, {BI
}},
3997 {"bflr", XLO(19,BOF
,16,0), XLBOBB_MASK
, PPCCOM
, PPCNONE
, {BI
}},
3998 {"bflr-", XLO(19,BOF
,16,0), XLBOBB_MASK
, PPCCOM
, ISA_V2
, {BI
}},
3999 {"bbfr", XLO(19,BOF
,16,0), XLBOBB_MASK
, PWRCOM
, PPCNONE
, {BI
}},
4000 {"bflrl", XLO(19,BOF
,16,1), XLBOBB_MASK
, PPCCOM
, PPCNONE
, {BI
}},
4001 {"bflrl-", XLO(19,BOF
,16,1), XLBOBB_MASK
, PPCCOM
, ISA_V2
, {BI
}},
4002 {"bbfrl", XLO(19,BOF
,16,1), XLBOBB_MASK
, PWRCOM
, PPCNONE
, {BI
}},
4003 {"bflr+", XLO(19,BOFP
,16,0), XLBOBB_MASK
, PPCCOM
, ISA_V2
, {BI
}},
4004 {"bflrl+", XLO(19,BOFP
,16,1), XLBOBB_MASK
, PPCCOM
, ISA_V2
, {BI
}},
4005 {"bflr-", XLO(19,BOFM4
,16,0), XLBOBB_MASK
, ISA_V2
, PPCNONE
, {BI
}},
4006 {"bflrl-", XLO(19,BOFM4
,16,1), XLBOBB_MASK
, ISA_V2
, PPCNONE
, {BI
}},
4007 {"bflr+", XLO(19,BOFP4
,16,0), XLBOBB_MASK
, ISA_V2
, PPCNONE
, {BI
}},
4008 {"bflrl+", XLO(19,BOFP4
,16,1), XLBOBB_MASK
, ISA_V2
, PPCNONE
, {BI
}},
4009 {"bdnztlr", XLO(19,BODNZT
,16,0), XLBOBB_MASK
, PPCCOM
, PPCNONE
, {BI
}},
4010 {"bdnztlr-", XLO(19,BODNZT
,16,0), XLBOBB_MASK
, PPCCOM
, ISA_V2
, {BI
}},
4011 {"bdnztlrl", XLO(19,BODNZT
,16,1), XLBOBB_MASK
, PPCCOM
, PPCNONE
, {BI
}},
4012 {"bdnztlrl-",XLO(19,BODNZT
,16,1), XLBOBB_MASK
, PPCCOM
, ISA_V2
, {BI
}},
4013 {"bdnztlr+", XLO(19,BODNZTP
,16,0), XLBOBB_MASK
, PPCCOM
, ISA_V2
, {BI
}},
4014 {"bdnztlrl+",XLO(19,BODNZTP
,16,1), XLBOBB_MASK
, PPCCOM
, ISA_V2
, {BI
}},
4015 {"bdztlr", XLO(19,BODZT
,16,0), XLBOBB_MASK
, PPCCOM
, PPCNONE
, {BI
}},
4016 {"bdztlr-", XLO(19,BODZT
,16,0), XLBOBB_MASK
, PPCCOM
, ISA_V2
, {BI
}},
4017 {"bdztlrl", XLO(19,BODZT
,16,1), XLBOBB_MASK
, PPCCOM
, PPCNONE
, {BI
}},
4018 {"bdztlrl-", XLO(19,BODZT
,16,1), XLBOBB_MASK
, PPCCOM
, ISA_V2
, {BI
}},
4019 {"bdztlr+", XLO(19,BODZTP
,16,0), XLBOBB_MASK
, PPCCOM
, ISA_V2
, {BI
}},
4020 {"bdztlrl+", XLO(19,BODZTP
,16,1), XLBOBB_MASK
, PPCCOM
, ISA_V2
, {BI
}},
4021 {"btlr", XLO(19,BOT
,16,0), XLBOBB_MASK
, PPCCOM
, PPCNONE
, {BI
}},
4022 {"btlr-", XLO(19,BOT
,16,0), XLBOBB_MASK
, PPCCOM
, ISA_V2
, {BI
}},
4023 {"bbtr", XLO(19,BOT
,16,0), XLBOBB_MASK
, PWRCOM
, PPCNONE
, {BI
}},
4024 {"btlrl", XLO(19,BOT
,16,1), XLBOBB_MASK
, PPCCOM
, PPCNONE
, {BI
}},
4025 {"btlrl-", XLO(19,BOT
,16,1), XLBOBB_MASK
, PPCCOM
, ISA_V2
, {BI
}},
4026 {"bbtrl", XLO(19,BOT
,16,1), XLBOBB_MASK
, PWRCOM
, PPCNONE
, {BI
}},
4027 {"btlr+", XLO(19,BOTP
,16,0), XLBOBB_MASK
, PPCCOM
, ISA_V2
, {BI
}},
4028 {"btlrl+", XLO(19,BOTP
,16,1), XLBOBB_MASK
, PPCCOM
, ISA_V2
, {BI
}},
4029 {"btlr-", XLO(19,BOTM4
,16,0), XLBOBB_MASK
, ISA_V2
, PPCNONE
, {BI
}},
4030 {"btlrl-", XLO(19,BOTM4
,16,1), XLBOBB_MASK
, ISA_V2
, PPCNONE
, {BI
}},
4031 {"btlr+", XLO(19,BOTP4
,16,0), XLBOBB_MASK
, ISA_V2
, PPCNONE
, {BI
}},
4032 {"btlrl+", XLO(19,BOTP4
,16,1), XLBOBB_MASK
, ISA_V2
, PPCNONE
, {BI
}},
4034 {"bclr-", XLYLK(19,16,0,0), XLYBB_MASK
, PPCCOM
, PPCNONE
, {BOE
, BI
}},
4035 {"bclrl-", XLYLK(19,16,0,1), XLYBB_MASK
, PPCCOM
, PPCNONE
, {BOE
, BI
}},
4036 {"bclr+", XLYLK(19,16,1,0), XLYBB_MASK
, PPCCOM
, PPCNONE
, {BOE
, BI
}},
4037 {"bclrl+", XLYLK(19,16,1,1), XLYBB_MASK
, PPCCOM
, PPCNONE
, {BOE
, BI
}},
4038 {"bclr", XLLK(19,16,0), XLBH_MASK
, PPCCOM
, PPCNONE
, {BO
, BI
, BH
}},
4039 {"bcr", XLLK(19,16,0), XLBB_MASK
, PWRCOM
, PPCNONE
, {BO
, BI
}},
4040 {"bclrl", XLLK(19,16,1), XLBH_MASK
, PPCCOM
, PPCNONE
, {BO
, BI
, BH
}},
4041 {"bcrl", XLLK(19,16,1), XLBB_MASK
, PWRCOM
, PPCNONE
, {BO
, BI
}},
4043 {"rfid", XL(19,18), 0xffffffff, PPC64
, PPCNONE
, {0}},
4045 {"crnot", XL(19,33), XL_MASK
, PPCCOM
, PPCNONE
, {BT
, BA
, BBA
}},
4046 {"crnor", XL(19,33), XL_MASK
, COM
, PPCNONE
, {BT
, BA
, BB
}},
4047 {"rfmci", X(19,38), 0xffffffff, PPCRFMCI
|PPCA2
|PPC476
, PPCNONE
, {0}},
4049 {"rfdi", XL(19,39), 0xffffffff, E500MC
, PPCNONE
, {0}},
4050 {"rfi", XL(19,50), 0xffffffff, COM
, PPCNONE
, {0}},
4051 {"rfci", XL(19,51), 0xffffffff, PPC403
|BOOKE
|PPCE300
|PPCA2
|PPC476
, PPCNONE
, {0}},
4053 {"rfsvc", XL(19,82), 0xffffffff, POWER
, PPCNONE
, {0}},
4055 {"rfgi", XL(19,102), 0xffffffff, E500MC
|PPCA2
, PPCNONE
, {0}},
4057 {"crandc", XL(19,129), XL_MASK
, COM
, PPCNONE
, {BT
, BA
, BB
}},
4059 {"rfebb", XL(19,146), XLS_MASK
, POWER8
, PPCNONE
, {SXL
}},
4061 {"isync", XL(19,150), 0xffffffff, PPCCOM
, PPCNONE
, {0}},
4062 {"ics", XL(19,150), 0xffffffff, PWRCOM
, PPCNONE
, {0}},
4064 {"crclr", XL(19,193), XL_MASK
, PPCCOM
, PPCNONE
, {BT
, BAT
, BBA
}},
4065 {"crxor", XL(19,193), XL_MASK
, COM
, PPCNONE
, {BT
, BA
, BB
}},
4067 {"dnh", X(19,198), X_MASK
, E500MC
, PPCNONE
, {DUI
, DUIS
}},
4069 {"crnand", XL(19,225), XL_MASK
, COM
, PPCNONE
, {BT
, BA
, BB
}},
4071 {"crand", XL(19,257), XL_MASK
, COM
, PPCNONE
, {BT
, BA
, BB
}},
4073 {"hrfid", XL(19,274), 0xffffffff, POWER5
|CELL
, PPC476
, {0}},
4075 {"crset", XL(19,289), XL_MASK
, PPCCOM
, PPCNONE
, {BT
, BAT
, BBA
}},
4076 {"creqv", XL(19,289), XL_MASK
, COM
, PPCNONE
, {BT
, BA
, BB
}},
4078 {"doze", XL(19,402), 0xffffffff, POWER6
, PPCNONE
, {0}},
4080 {"crorc", XL(19,417), XL_MASK
, COM
, PPCNONE
, {BT
, BA
, BB
}},
4082 {"nap", XL(19,434), 0xffffffff, POWER6
, PPCNONE
, {0}},
4084 {"crmove", XL(19,449), XL_MASK
, PPCCOM
, PPCNONE
, {BT
, BA
, BBA
}},
4085 {"cror", XL(19,449), XL_MASK
, COM
, PPCNONE
, {BT
, BA
, BB
}},
4087 {"sleep", XL(19,466), 0xffffffff, POWER6
, PPCNONE
, {0}},
4088 {"rvwinkle", XL(19,498), 0xffffffff, POWER6
, PPCNONE
, {0}},
4090 {"bctr", XLO(19,BOU
,528,0), XLBOBIBB_MASK
, COM
, PPCNONE
, {0}},
4091 {"bctrl", XLO(19,BOU
,528,1), XLBOBIBB_MASK
, COM
, PPCNONE
, {0}},
4093 {"bgectr", XLOCB(19,BOF
,CBLT
,528,0), XLBOCBBB_MASK
, PPCCOM
, PPCNONE
, {CR
}},
4094 {"bgectr-", XLOCB(19,BOF
,CBLT
,528,0), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
, {CR
}},
4095 {"bnlctr", XLOCB(19,BOF
,CBLT
,528,0), XLBOCBBB_MASK
, PPCCOM
, PPCNONE
, {CR
}},
4096 {"bnlctr-", XLOCB(19,BOF
,CBLT
,528,0), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
, {CR
}},
4097 {"bgectrl", XLOCB(19,BOF
,CBLT
,528,1), XLBOCBBB_MASK
, PPCCOM
, PPCNONE
, {CR
}},
4098 {"bgectrl-",XLOCB(19,BOF
,CBLT
,528,1), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
, {CR
}},
4099 {"bnlctrl", XLOCB(19,BOF
,CBLT
,528,1), XLBOCBBB_MASK
, PPCCOM
, PPCNONE
, {CR
}},
4100 {"bnlctrl-",XLOCB(19,BOF
,CBLT
,528,1), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
, {CR
}},
4101 {"blectr", XLOCB(19,BOF
,CBGT
,528,0), XLBOCBBB_MASK
, PPCCOM
, PPCNONE
, {CR
}},
4102 {"blectr-", XLOCB(19,BOF
,CBGT
,528,0), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
, {CR
}},
4103 {"bngctr", XLOCB(19,BOF
,CBGT
,528,0), XLBOCBBB_MASK
, PPCCOM
, PPCNONE
, {CR
}},
4104 {"bngctr-", XLOCB(19,BOF
,CBGT
,528,0), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
, {CR
}},
4105 {"blectrl", XLOCB(19,BOF
,CBGT
,528,1), XLBOCBBB_MASK
, PPCCOM
, PPCNONE
, {CR
}},
4106 {"blectrl-",XLOCB(19,BOF
,CBGT
,528,1), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
, {CR
}},
4107 {"bngctrl", XLOCB(19,BOF
,CBGT
,528,1), XLBOCBBB_MASK
, PPCCOM
, PPCNONE
, {CR
}},
4108 {"bngctrl-",XLOCB(19,BOF
,CBGT
,528,1), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
, {CR
}},
4109 {"bnectr", XLOCB(19,BOF
,CBEQ
,528,0), XLBOCBBB_MASK
, PPCCOM
, PPCNONE
, {CR
}},
4110 {"bnectr-", XLOCB(19,BOF
,CBEQ
,528,0), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
, {CR
}},
4111 {"bnectrl", XLOCB(19,BOF
,CBEQ
,528,1), XLBOCBBB_MASK
, PPCCOM
, PPCNONE
, {CR
}},
4112 {"bnectrl-",XLOCB(19,BOF
,CBEQ
,528,1), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
, {CR
}},
4113 {"bnsctr", XLOCB(19,BOF
,CBSO
,528,0), XLBOCBBB_MASK
, PPCCOM
, PPCNONE
, {CR
}},
4114 {"bnsctr-", XLOCB(19,BOF
,CBSO
,528,0), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
, {CR
}},
4115 {"bnuctr", XLOCB(19,BOF
,CBSO
,528,0), XLBOCBBB_MASK
, PPCCOM
, PPCNONE
, {CR
}},
4116 {"bnuctr-", XLOCB(19,BOF
,CBSO
,528,0), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
, {CR
}},
4117 {"bnsctrl", XLOCB(19,BOF
,CBSO
,528,1), XLBOCBBB_MASK
, PPCCOM
, PPCNONE
, {CR
}},
4118 {"bnsctrl-",XLOCB(19,BOF
,CBSO
,528,1), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
, {CR
}},
4119 {"bnuctrl", XLOCB(19,BOF
,CBSO
,528,1), XLBOCBBB_MASK
, PPCCOM
, PPCNONE
, {CR
}},
4120 {"bnuctrl-",XLOCB(19,BOF
,CBSO
,528,1), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
, {CR
}},
4121 {"bgectr+", XLOCB(19,BOFP
,CBLT
,528,0), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
, {CR
}},
4122 {"bnlctr+", XLOCB(19,BOFP
,CBLT
,528,0), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
, {CR
}},
4123 {"bgectrl+",XLOCB(19,BOFP
,CBLT
,528,1), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
, {CR
}},
4124 {"bnlctrl+",XLOCB(19,BOFP
,CBLT
,528,1), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
, {CR
}},
4125 {"blectr+", XLOCB(19,BOFP
,CBGT
,528,0), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
, {CR
}},
4126 {"bngctr+", XLOCB(19,BOFP
,CBGT
,528,0), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
, {CR
}},
4127 {"blectrl+",XLOCB(19,BOFP
,CBGT
,528,1), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
, {CR
}},
4128 {"bngctrl+",XLOCB(19,BOFP
,CBGT
,528,1), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
, {CR
}},
4129 {"bnectr+", XLOCB(19,BOFP
,CBEQ
,528,0), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
, {CR
}},
4130 {"bnectrl+",XLOCB(19,BOFP
,CBEQ
,528,1), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
, {CR
}},
4131 {"bnsctr+", XLOCB(19,BOFP
,CBSO
,528,0), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
, {CR
}},
4132 {"bnuctr+", XLOCB(19,BOFP
,CBSO
,528,0), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
, {CR
}},
4133 {"bnsctrl+",XLOCB(19,BOFP
,CBSO
,528,1), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
, {CR
}},
4134 {"bnuctrl+",XLOCB(19,BOFP
,CBSO
,528,1), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
, {CR
}},
4135 {"bgectr-", XLOCB(19,BOFM4
,CBLT
,528,0), XLBOCBBB_MASK
, ISA_V2
, PPCNONE
, {CR
}},
4136 {"bnlctr-", XLOCB(19,BOFM4
,CBLT
,528,0), XLBOCBBB_MASK
, ISA_V2
, PPCNONE
, {CR
}},
4137 {"bgectrl-",XLOCB(19,BOFM4
,CBLT
,528,1), XLBOCBBB_MASK
, ISA_V2
, PPCNONE
, {CR
}},
4138 {"bnlctrl-",XLOCB(19,BOFM4
,CBLT
,528,1), XLBOCBBB_MASK
, ISA_V2
, PPCNONE
, {CR
}},
4139 {"blectr-", XLOCB(19,BOFM4
,CBGT
,528,0), XLBOCBBB_MASK
, ISA_V2
, PPCNONE
, {CR
}},
4140 {"bngctr-", XLOCB(19,BOFM4
,CBGT
,528,0), XLBOCBBB_MASK
, ISA_V2
, PPCNONE
, {CR
}},
4141 {"blectrl-",XLOCB(19,BOFM4
,CBGT
,528,1), XLBOCBBB_MASK
, ISA_V2
, PPCNONE
, {CR
}},
4142 {"bngctrl-",XLOCB(19,BOFM4
,CBGT
,528,1), XLBOCBBB_MASK
, ISA_V2
, PPCNONE
, {CR
}},
4143 {"bnectr-", XLOCB(19,BOFM4
,CBEQ
,528,0), XLBOCBBB_MASK
, ISA_V2
, PPCNONE
, {CR
}},
4144 {"bnectrl-",XLOCB(19,BOFM4
,CBEQ
,528,1), XLBOCBBB_MASK
, ISA_V2
, PPCNONE
, {CR
}},
4145 {"bnsctr-", XLOCB(19,BOFM4
,CBSO
,528,0), XLBOCBBB_MASK
, ISA_V2
, PPCNONE
, {CR
}},
4146 {"bnuctr-", XLOCB(19,BOFM4
,CBSO
,528,0), XLBOCBBB_MASK
, ISA_V2
, PPCNONE
, {CR
}},
4147 {"bnsctrl-",XLOCB(19,BOFM4
,CBSO
,528,1), XLBOCBBB_MASK
, ISA_V2
, PPCNONE
, {CR
}},
4148 {"bnuctrl-",XLOCB(19,BOFM4
,CBSO
,528,1), XLBOCBBB_MASK
, ISA_V2
, PPCNONE
, {CR
}},
4149 {"bgectr+", XLOCB(19,BOFP4
,CBLT
,528,0), XLBOCBBB_MASK
, ISA_V2
, PPCNONE
, {CR
}},
4150 {"bnlctr+", XLOCB(19,BOFP4
,CBLT
,528,0), XLBOCBBB_MASK
, ISA_V2
, PPCNONE
, {CR
}},
4151 {"bgectrl+",XLOCB(19,BOFP4
,CBLT
,528,1), XLBOCBBB_MASK
, ISA_V2
, PPCNONE
, {CR
}},
4152 {"bnlctrl+",XLOCB(19,BOFP4
,CBLT
,528,1), XLBOCBBB_MASK
, ISA_V2
, PPCNONE
, {CR
}},
4153 {"blectr+", XLOCB(19,BOFP4
,CBGT
,528,0), XLBOCBBB_MASK
, ISA_V2
, PPCNONE
, {CR
}},
4154 {"bngctr+", XLOCB(19,BOFP4
,CBGT
,528,0), XLBOCBBB_MASK
, ISA_V2
, PPCNONE
, {CR
}},
4155 {"blectrl+",XLOCB(19,BOFP4
,CBGT
,528,1), XLBOCBBB_MASK
, ISA_V2
, PPCNONE
, {CR
}},
4156 {"bngctrl+",XLOCB(19,BOFP4
,CBGT
,528,1), XLBOCBBB_MASK
, ISA_V2
, PPCNONE
, {CR
}},
4157 {"bnectr+", XLOCB(19,BOFP4
,CBEQ
,528,0), XLBOCBBB_MASK
, ISA_V2
, PPCNONE
, {CR
}},
4158 {"bnectrl+",XLOCB(19,BOFP4
,CBEQ
,528,1), XLBOCBBB_MASK
, ISA_V2
, PPCNONE
, {CR
}},
4159 {"bnsctr+", XLOCB(19,BOFP4
,CBSO
,528,0), XLBOCBBB_MASK
, ISA_V2
, PPCNONE
, {CR
}},
4160 {"bnuctr+", XLOCB(19,BOFP4
,CBSO
,528,0), XLBOCBBB_MASK
, ISA_V2
, PPCNONE
, {CR
}},
4161 {"bnsctrl+",XLOCB(19,BOFP4
,CBSO
,528,1), XLBOCBBB_MASK
, ISA_V2
, PPCNONE
, {CR
}},
4162 {"bnuctrl+",XLOCB(19,BOFP4
,CBSO
,528,1), XLBOCBBB_MASK
, ISA_V2
, PPCNONE
, {CR
}},
4163 {"bltctr", XLOCB(19,BOT
,CBLT
,528,0), XLBOCBBB_MASK
, PPCCOM
, PPCNONE
, {CR
}},
4164 {"bltctr-", XLOCB(19,BOT
,CBLT
,528,0), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
, {CR
}},
4165 {"bltctrl", XLOCB(19,BOT
,CBLT
,528,1), XLBOCBBB_MASK
, PPCCOM
, PPCNONE
, {CR
}},
4166 {"bltctrl-",XLOCB(19,BOT
,CBLT
,528,1), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
, {CR
}},
4167 {"bgtctr", XLOCB(19,BOT
,CBGT
,528,0), XLBOCBBB_MASK
, PPCCOM
, PPCNONE
, {CR
}},
4168 {"bgtctr-", XLOCB(19,BOT
,CBGT
,528,0), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
, {CR
}},
4169 {"bgtctrl", XLOCB(19,BOT
,CBGT
,528,1), XLBOCBBB_MASK
, PPCCOM
, PPCNONE
, {CR
}},
4170 {"bgtctrl-",XLOCB(19,BOT
,CBGT
,528,1), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
, {CR
}},
4171 {"beqctr", XLOCB(19,BOT
,CBEQ
,528,0), XLBOCBBB_MASK
, PPCCOM
, PPCNONE
, {CR
}},
4172 {"beqctr-", XLOCB(19,BOT
,CBEQ
,528,0), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
, {CR
}},
4173 {"beqctrl", XLOCB(19,BOT
,CBEQ
,528,1), XLBOCBBB_MASK
, PPCCOM
, PPCNONE
, {CR
}},
4174 {"beqctrl-",XLOCB(19,BOT
,CBEQ
,528,1), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
, {CR
}},
4175 {"bsoctr", XLOCB(19,BOT
,CBSO
,528,0), XLBOCBBB_MASK
, PPCCOM
, PPCNONE
, {CR
}},
4176 {"bsoctr-", XLOCB(19,BOT
,CBSO
,528,0), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
, {CR
}},
4177 {"bunctr", XLOCB(19,BOT
,CBSO
,528,0), XLBOCBBB_MASK
, PPCCOM
, PPCNONE
, {CR
}},
4178 {"bunctr-", XLOCB(19,BOT
,CBSO
,528,0), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
, {CR
}},
4179 {"bsoctrl", XLOCB(19,BOT
,CBSO
,528,1), XLBOCBBB_MASK
, PPCCOM
, PPCNONE
, {CR
}},
4180 {"bsoctrl-",XLOCB(19,BOT
,CBSO
,528,1), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
, {CR
}},
4181 {"bunctrl", XLOCB(19,BOT
,CBSO
,528,1), XLBOCBBB_MASK
, PPCCOM
, PPCNONE
, {CR
}},
4182 {"bunctrl-",XLOCB(19,BOT
,CBSO
,528,1), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
, {CR
}},
4183 {"bltctr+", XLOCB(19,BOTP
,CBLT
,528,0), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
, {CR
}},
4184 {"bltctrl+",XLOCB(19,BOTP
,CBLT
,528,1), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
, {CR
}},
4185 {"bgtctr+", XLOCB(19,BOTP
,CBGT
,528,0), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
, {CR
}},
4186 {"bgtctrl+",XLOCB(19,BOTP
,CBGT
,528,1), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
, {CR
}},
4187 {"beqctr+", XLOCB(19,BOTP
,CBEQ
,528,0), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
, {CR
}},
4188 {"beqctrl+",XLOCB(19,BOTP
,CBEQ
,528,1), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
, {CR
}},
4189 {"bsoctr+", XLOCB(19,BOTP
,CBSO
,528,0), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
, {CR
}},
4190 {"bunctr+", XLOCB(19,BOTP
,CBSO
,528,0), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
, {CR
}},
4191 {"bsoctrl+",XLOCB(19,BOTP
,CBSO
,528,1), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
, {CR
}},
4192 {"bunctrl+",XLOCB(19,BOTP
,CBSO
,528,1), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
, {CR
}},
4193 {"bltctr-", XLOCB(19,BOTM4
,CBLT
,528,0), XLBOCBBB_MASK
, ISA_V2
, PPCNONE
, {CR
}},
4194 {"bltctrl-",XLOCB(19,BOTM4
,CBLT
,528,1), XLBOCBBB_MASK
, ISA_V2
, PPCNONE
, {CR
}},
4195 {"bgtctr-", XLOCB(19,BOTM4
,CBGT
,528,0), XLBOCBBB_MASK
, ISA_V2
, PPCNONE
, {CR
}},
4196 {"bgtctrl-",XLOCB(19,BOTM4
,CBGT
,528,1), XLBOCBBB_MASK
, ISA_V2
, PPCNONE
, {CR
}},
4197 {"beqctr-", XLOCB(19,BOTM4
,CBEQ
,528,0), XLBOCBBB_MASK
, ISA_V2
, PPCNONE
, {CR
}},
4198 {"beqctrl-",XLOCB(19,BOTM4
,CBEQ
,528,1), XLBOCBBB_MASK
, ISA_V2
, PPCNONE
, {CR
}},
4199 {"bsoctr-", XLOCB(19,BOTM4
,CBSO
,528,0), XLBOCBBB_MASK
, ISA_V2
, PPCNONE
, {CR
}},
4200 {"bunctr-", XLOCB(19,BOTM4
,CBSO
,528,0), XLBOCBBB_MASK
, ISA_V2
, PPCNONE
, {CR
}},
4201 {"bsoctrl-",XLOCB(19,BOTM4
,CBSO
,528,1), XLBOCBBB_MASK
, ISA_V2
, PPCNONE
, {CR
}},
4202 {"bunctrl-",XLOCB(19,BOTM4
,CBSO
,528,1), XLBOCBBB_MASK
, ISA_V2
, PPCNONE
, {CR
}},
4203 {"bltctr+", XLOCB(19,BOTP4
,CBLT
,528,0), XLBOCBBB_MASK
, ISA_V2
, PPCNONE
, {CR
}},
4204 {"bltctrl+",XLOCB(19,BOTP4
,CBLT
,528,1), XLBOCBBB_MASK
, ISA_V2
, PPCNONE
, {CR
}},
4205 {"bgtctr+", XLOCB(19,BOTP4
,CBGT
,528,0), XLBOCBBB_MASK
, ISA_V2
, PPCNONE
, {CR
}},
4206 {"bgtctrl+",XLOCB(19,BOTP4
,CBGT
,528,1), XLBOCBBB_MASK
, ISA_V2
, PPCNONE
, {CR
}},
4207 {"beqctr+", XLOCB(19,BOTP4
,CBEQ
,528,0), XLBOCBBB_MASK
, ISA_V2
, PPCNONE
, {CR
}},
4208 {"beqctrl+",XLOCB(19,BOTP4
,CBEQ
,528,1), XLBOCBBB_MASK
, ISA_V2
, PPCNONE
, {CR
}},
4209 {"bsoctr+", XLOCB(19,BOTP4
,CBSO
,528,0), XLBOCBBB_MASK
, ISA_V2
, PPCNONE
, {CR
}},
4210 {"bunctr+", XLOCB(19,BOTP4
,CBSO
,528,0), XLBOCBBB_MASK
, ISA_V2
, PPCNONE
, {CR
}},
4211 {"bsoctrl+",XLOCB(19,BOTP4
,CBSO
,528,1), XLBOCBBB_MASK
, ISA_V2
, PPCNONE
, {CR
}},
4212 {"bunctrl+",XLOCB(19,BOTP4
,CBSO
,528,1), XLBOCBBB_MASK
, ISA_V2
, PPCNONE
, {CR
}},
4214 {"bfctr", XLO(19,BOF
,528,0), XLBOBB_MASK
, PPCCOM
, PPCNONE
, {BI
}},
4215 {"bfctr-", XLO(19,BOF
,528,0), XLBOBB_MASK
, PPCCOM
, ISA_V2
, {BI
}},
4216 {"bfctrl", XLO(19,BOF
,528,1), XLBOBB_MASK
, PPCCOM
, PPCNONE
, {BI
}},
4217 {"bfctrl-", XLO(19,BOF
,528,1), XLBOBB_MASK
, PPCCOM
, ISA_V2
, {BI
}},
4218 {"bfctr+", XLO(19,BOFP
,528,0), XLBOBB_MASK
, PPCCOM
, ISA_V2
, {BI
}},
4219 {"bfctrl+", XLO(19,BOFP
,528,1), XLBOBB_MASK
, PPCCOM
, ISA_V2
, {BI
}},
4220 {"bfctr-", XLO(19,BOFM4
,528,0), XLBOBB_MASK
, ISA_V2
, PPCNONE
, {BI
}},
4221 {"bfctrl-", XLO(19,BOFM4
,528,1), XLBOBB_MASK
, ISA_V2
, PPCNONE
, {BI
}},
4222 {"bfctr+", XLO(19,BOFP4
,528,0), XLBOBB_MASK
, ISA_V2
, PPCNONE
, {BI
}},
4223 {"bfctrl+", XLO(19,BOFP4
,528,1), XLBOBB_MASK
, ISA_V2
, PPCNONE
, {BI
}},
4224 {"btctr", XLO(19,BOT
,528,0), XLBOBB_MASK
, PPCCOM
, PPCNONE
, {BI
}},
4225 {"btctr-", XLO(19,BOT
,528,0), XLBOBB_MASK
, PPCCOM
, ISA_V2
, {BI
}},
4226 {"btctrl", XLO(19,BOT
,528,1), XLBOBB_MASK
, PPCCOM
, PPCNONE
, {BI
}},
4227 {"btctrl-", XLO(19,BOT
,528,1), XLBOBB_MASK
, PPCCOM
, ISA_V2
, {BI
}},
4228 {"btctr+", XLO(19,BOTP
,528,0), XLBOBB_MASK
, PPCCOM
, ISA_V2
, {BI
}},
4229 {"btctrl+", XLO(19,BOTP
,528,1), XLBOBB_MASK
, PPCCOM
, ISA_V2
, {BI
}},
4230 {"btctr-", XLO(19,BOTM4
,528,0), XLBOBB_MASK
, ISA_V2
, PPCNONE
, {BI
}},
4231 {"btctrl-", XLO(19,BOTM4
,528,1), XLBOBB_MASK
, ISA_V2
, PPCNONE
, {BI
}},
4232 {"btctr+", XLO(19,BOTP4
,528,0), XLBOBB_MASK
, ISA_V2
, PPCNONE
, {BI
}},
4233 {"btctrl+", XLO(19,BOTP4
,528,1), XLBOBB_MASK
, ISA_V2
, PPCNONE
, {BI
}},
4235 {"bcctr-", XLYLK(19,528,0,0), XLYBB_MASK
, PPCCOM
, PPCNONE
, {BOE
, BI
}},
4236 {"bcctrl-", XLYLK(19,528,0,1), XLYBB_MASK
, PPCCOM
, PPCNONE
, {BOE
, BI
}},
4237 {"bcctr+", XLYLK(19,528,1,0), XLYBB_MASK
, PPCCOM
, PPCNONE
, {BOE
, BI
}},
4238 {"bcctrl+", XLYLK(19,528,1,1), XLYBB_MASK
, PPCCOM
, PPCNONE
, {BOE
, BI
}},
4239 {"bcctr", XLLK(19,528,0), XLBH_MASK
, PPCCOM
, PPCNONE
, {BO
, BI
, BH
}},
4240 {"bcc", XLLK(19,528,0), XLBB_MASK
, PWRCOM
, PPCNONE
, {BO
, BI
}},
4241 {"bcctrl", XLLK(19,528,1), XLBH_MASK
, PPCCOM
, PPCNONE
, {BO
, BI
, BH
}},
4242 {"bccl", XLLK(19,528,1), XLBB_MASK
, PWRCOM
, PPCNONE
, {BO
, BI
}},
4244 {"bctar-", XLYLK(19,560,0,0), XLYBB_MASK
, POWER8
, PPCNONE
, {BOE
, BI
}},
4245 {"bctarl-", XLYLK(19,560,0,1), XLYBB_MASK
, POWER8
, PPCNONE
, {BOE
, BI
}},
4246 {"bctar+", XLYLK(19,560,1,0), XLYBB_MASK
, POWER8
, PPCNONE
, {BOE
, BI
}},
4247 {"bctarl+", XLYLK(19,560,1,1), XLYBB_MASK
, POWER8
, PPCNONE
, {BOE
, BI
}},
4248 {"bctar", XLLK(19,560,0), XLBH_MASK
, POWER8
, PPCNONE
, {BO
, BI
, BH
}},
4249 {"bctarl", XLLK(19,560,1), XLBH_MASK
, POWER8
, PPCNONE
, {BO
, BI
, BH
}},
4251 {"rlwimi", M(20,0), M_MASK
, PPCCOM
, PPCNONE
, {RA
, RS
, SH
, MBE
, ME
}},
4252 {"rlimi", M(20,0), M_MASK
, PWRCOM
, PPCNONE
, {RA
, RS
, SH
, MBE
, ME
}},
4254 {"rlwimi.", M(20,1), M_MASK
, PPCCOM
, PPCNONE
, {RA
, RS
, SH
, MBE
, ME
}},
4255 {"rlimi.", M(20,1), M_MASK
, PWRCOM
, PPCNONE
, {RA
, RS
, SH
, MBE
, ME
}},
4257 {"rotlwi", MME(21,31,0), MMBME_MASK
, PPCCOM
, PPCNONE
, {RA
, RS
, SH
}},
4258 {"clrlwi", MME(21,31,0), MSHME_MASK
, PPCCOM
, PPCNONE
, {RA
, RS
, MB
}},
4259 {"rlwinm", M(21,0), M_MASK
, PPCCOM
, PPCNONE
, {RA
, RS
, SH
, MBE
, ME
}},
4260 {"rlinm", M(21,0), M_MASK
, PWRCOM
, PPCNONE
, {RA
, RS
, SH
, MBE
, ME
}},
4261 {"rotlwi.", MME(21,31,1), MMBME_MASK
, PPCCOM
, PPCNONE
, {RA
, RS
, SH
}},
4262 {"clrlwi.", MME(21,31,1), MSHME_MASK
, PPCCOM
, PPCNONE
, {RA
, RS
, MB
}},
4263 {"rlwinm.", M(21,1), M_MASK
, PPCCOM
, PPCNONE
, {RA
, RS
, SH
, MBE
, ME
}},
4264 {"rlinm.", M(21,1), M_MASK
, PWRCOM
, PPCNONE
, {RA
, RS
, SH
, MBE
, ME
}},
4266 {"rlmi", M(22,0), M_MASK
, M601
, PPCNONE
, {RA
, RS
, RB
, MBE
, ME
}},
4267 {"rlmi.", M(22,1), M_MASK
, M601
, PPCNONE
, {RA
, RS
, RB
, MBE
, ME
}},
4269 {"rotlw", MME(23,31,0), MMBME_MASK
, PPCCOM
, PPCNONE
, {RA
, RS
, RB
}},
4270 {"rlwnm", M(23,0), M_MASK
, PPCCOM
, PPCNONE
, {RA
, RS
, RB
, MBE
, ME
}},
4271 {"rlnm", M(23,0), M_MASK
, PWRCOM
, PPCNONE
, {RA
, RS
, RB
, MBE
, ME
}},
4272 {"rotlw.", MME(23,31,1), MMBME_MASK
, PPCCOM
, PPCNONE
, {RA
, RS
, RB
}},
4273 {"rlwnm.", M(23,1), M_MASK
, PPCCOM
, PPCNONE
, {RA
, RS
, RB
, MBE
, ME
}},
4274 {"rlnm.", M(23,1), M_MASK
, PWRCOM
, PPCNONE
, {RA
, RS
, RB
, MBE
, ME
}},
4276 {"nop", OP(24), 0xffffffff, PPCCOM
, PPCNONE
, {0}},
4277 {"ori", OP(24), OP_MASK
, PPCCOM
, PPCNONE
, {RA
, RS
, UI
}},
4278 {"oril", OP(24), OP_MASK
, PWRCOM
, PPCNONE
, {RA
, RS
, UI
}},
4280 {"oris", OP(25), OP_MASK
, PPCCOM
, PPCNONE
, {RA
, RS
, UI
}},
4281 {"oriu", OP(25), OP_MASK
, PWRCOM
, PPCNONE
, {RA
, RS
, UI
}},
4283 {"xnop", OP(26), 0xffffffff, PPCCOM
, PPCNONE
, {0}},
4284 {"xori", OP(26), OP_MASK
, PPCCOM
, PPCNONE
, {RA
, RS
, UI
}},
4285 {"xoril", OP(26), OP_MASK
, PWRCOM
, PPCNONE
, {RA
, RS
, UI
}},
4287 {"xoris", OP(27), OP_MASK
, PPCCOM
, PPCNONE
, {RA
, RS
, UI
}},
4288 {"xoriu", OP(27), OP_MASK
, PWRCOM
, PPCNONE
, {RA
, RS
, UI
}},
4290 {"andi.", OP(28), OP_MASK
, PPCCOM
, PPCNONE
, {RA
, RS
, UI
}},
4291 {"andil.", OP(28), OP_MASK
, PWRCOM
, PPCNONE
, {RA
, RS
, UI
}},
4293 {"andis.", OP(29), OP_MASK
, PPCCOM
, PPCNONE
, {RA
, RS
, UI
}},
4294 {"andiu.", OP(29), OP_MASK
, PWRCOM
, PPCNONE
, {RA
, RS
, UI
}},
4296 {"rotldi", MD(30,0,0), MDMB_MASK
, PPC64
, PPCNONE
, {RA
, RS
, SH6
}},
4297 {"clrldi", MD(30,0,0), MDSH_MASK
, PPC64
, PPCNONE
, {RA
, RS
, MB6
}},
4298 {"rldicl", MD(30,0,0), MD_MASK
, PPC64
, PPCNONE
, {RA
, RS
, SH6
, MB6
}},
4299 {"rotldi.", MD(30,0,1), MDMB_MASK
, PPC64
, PPCNONE
, {RA
, RS
, SH6
}},
4300 {"clrldi.", MD(30,0,1), MDSH_MASK
, PPC64
, PPCNONE
, {RA
, RS
, MB6
}},
4301 {"rldicl.", MD(30,0,1), MD_MASK
, PPC64
, PPCNONE
, {RA
, RS
, SH6
, MB6
}},
4303 {"rldicr", MD(30,1,0), MD_MASK
, PPC64
, PPCNONE
, {RA
, RS
, SH6
, ME6
}},
4304 {"rldicr.", MD(30,1,1), MD_MASK
, PPC64
, PPCNONE
, {RA
, RS
, SH6
, ME6
}},
4306 {"rldic", MD(30,2,0), MD_MASK
, PPC64
, PPCNONE
, {RA
, RS
, SH6
, MB6
}},
4307 {"rldic.", MD(30,2,1), MD_MASK
, PPC64
, PPCNONE
, {RA
, RS
, SH6
, MB6
}},
4309 {"rldimi", MD(30,3,0), MD_MASK
, PPC64
, PPCNONE
, {RA
, RS
, SH6
, MB6
}},
4310 {"rldimi.", MD(30,3,1), MD_MASK
, PPC64
, PPCNONE
, {RA
, RS
, SH6
, MB6
}},
4312 {"rotld", MDS(30,8,0), MDSMB_MASK
, PPC64
, PPCNONE
, {RA
, RS
, RB
}},
4313 {"rldcl", MDS(30,8,0), MDS_MASK
, PPC64
, PPCNONE
, {RA
, RS
, RB
, MB6
}},
4314 {"rotld.", MDS(30,8,1), MDSMB_MASK
, PPC64
, PPCNONE
, {RA
, RS
, RB
}},
4315 {"rldcl.", MDS(30,8,1), MDS_MASK
, PPC64
, PPCNONE
, {RA
, RS
, RB
, MB6
}},
4317 {"rldcr", MDS(30,9,0), MDS_MASK
, PPC64
, PPCNONE
, {RA
, RS
, RB
, ME6
}},
4318 {"rldcr.", MDS(30,9,1), MDS_MASK
, PPC64
, PPCNONE
, {RA
, RS
, RB
, ME6
}},
4320 {"cmpw", XOPL(31,0,0), XCMPL_MASK
, PPCCOM
, PPCNONE
, {OBF
, RA
, RB
}},
4321 {"cmpd", XOPL(31,0,1), XCMPL_MASK
, PPC64
, PPCNONE
, {OBF
, RA
, RB
}},
4322 {"cmp", X(31,0), XCMP_MASK
, PPC
|PPCVLE
, PPCNONE
, {BF
, L
, RA
, RB
}},
4323 {"cmp", X(31,0), XCMPL_MASK
, PWRCOM
, PPC
, {BF
, RA
, RB
}},
4325 {"twlgt", XTO(31,4,TOLGT
), XTO_MASK
, PPCCOM
|PPCVLE
, PPCNONE
, {RA
, RB
}},
4326 {"tlgt", XTO(31,4,TOLGT
), XTO_MASK
, PWRCOM
, PPCNONE
, {RA
, RB
}},
4327 {"twllt", XTO(31,4,TOLLT
), XTO_MASK
, PPCCOM
|PPCVLE
, PPCNONE
, {RA
, RB
}},
4328 {"tllt", XTO(31,4,TOLLT
), XTO_MASK
, PWRCOM
, PPCNONE
, {RA
, RB
}},
4329 {"tweq", XTO(31,4,TOEQ
), XTO_MASK
, PPCCOM
|PPCVLE
, PPCNONE
, {RA
, RB
}},
4330 {"teq", XTO(31,4,TOEQ
), XTO_MASK
, PWRCOM
, PPCNONE
, {RA
, RB
}},
4331 {"twlge", XTO(31,4,TOLGE
), XTO_MASK
, PPCCOM
|PPCVLE
, PPCNONE
, {RA
, RB
}},
4332 {"tlge", XTO(31,4,TOLGE
), XTO_MASK
, PWRCOM
, PPCNONE
, {RA
, RB
}},
4333 {"twlnl", XTO(31,4,TOLNL
), XTO_MASK
, PPCCOM
|PPCVLE
, PPCNONE
, {RA
, RB
}},
4334 {"tlnl", XTO(31,4,TOLNL
), XTO_MASK
, PWRCOM
, PPCNONE
, {RA
, RB
}},
4335 {"twlle", XTO(31,4,TOLLE
), XTO_MASK
, PPCCOM
|PPCVLE
, PPCNONE
, {RA
, RB
}},
4336 {"tlle", XTO(31,4,TOLLE
), XTO_MASK
, PWRCOM
, PPCNONE
, {RA
, RB
}},
4337 {"twlng", XTO(31,4,TOLNG
), XTO_MASK
, PPCCOM
|PPCVLE
, PPCNONE
, {RA
, RB
}},
4338 {"tlng", XTO(31,4,TOLNG
), XTO_MASK
, PWRCOM
, PPCNONE
, {RA
, RB
}},
4339 {"twgt", XTO(31,4,TOGT
), XTO_MASK
, PPCCOM
|PPCVLE
, PPCNONE
, {RA
, RB
}},
4340 {"tgt", XTO(31,4,TOGT
), XTO_MASK
, PWRCOM
, PPCNONE
, {RA
, RB
}},
4341 {"twge", XTO(31,4,TOGE
), XTO_MASK
, PPCCOM
|PPCVLE
, PPCNONE
, {RA
, RB
}},
4342 {"tge", XTO(31,4,TOGE
), XTO_MASK
, PWRCOM
, PPCNONE
, {RA
, RB
}},
4343 {"twnl", XTO(31,4,TONL
), XTO_MASK
, PPCCOM
|PPCVLE
, PPCNONE
, {RA
, RB
}},
4344 {"tnl", XTO(31,4,TONL
), XTO_MASK
, PWRCOM
, PPCNONE
, {RA
, RB
}},
4345 {"twlt", XTO(31,4,TOLT
), XTO_MASK
, PPCCOM
|PPCVLE
, PPCNONE
, {RA
, RB
}},
4346 {"tlt", XTO(31,4,TOLT
), XTO_MASK
, PWRCOM
, PPCNONE
, {RA
, RB
}},
4347 {"twle", XTO(31,4,TOLE
), XTO_MASK
, PPCCOM
|PPCVLE
, PPCNONE
, {RA
, RB
}},
4348 {"tle", XTO(31,4,TOLE
), XTO_MASK
, PWRCOM
, PPCNONE
, {RA
, RB
}},
4349 {"twng", XTO(31,4,TONG
), XTO_MASK
, PPCCOM
|PPCVLE
, PPCNONE
, {RA
, RB
}},
4350 {"tng", XTO(31,4,TONG
), XTO_MASK
, PWRCOM
, PPCNONE
, {RA
, RB
}},
4351 {"twne", XTO(31,4,TONE
), XTO_MASK
, PPCCOM
|PPCVLE
, PPCNONE
, {RA
, RB
}},
4352 {"tne", XTO(31,4,TONE
), XTO_MASK
, PWRCOM
, PPCNONE
, {RA
, RB
}},
4353 {"trap", XTO(31,4,TOU
), 0xffffffff, PPCCOM
|PPCVLE
, PPCNONE
, {0}},
4354 {"twu", XTO(31,4,TOU
), XTO_MASK
, PPCCOM
|PPCVLE
, PPCNONE
, {RA
, RB
}},
4355 {"tu", XTO(31,4,TOU
), XTO_MASK
, PWRCOM
, PPCNONE
, {RA
, RB
}},
4356 {"tw", X(31,4), X_MASK
, PPCCOM
|PPCVLE
, PPCNONE
, {TO
, RA
, RB
}},
4357 {"t", X(31,4), X_MASK
, PWRCOM
, PPCNONE
, {TO
, RA
, RB
}},
4359 {"lvsl", X(31,6), X_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, RA0
, RB
}},
4360 {"lvebx", X(31,7), X_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, RA0
, RB
}},
4361 {"lbfcmx", APU(31,7,0), APU_MASK
, PPC405
, PPCNONE
, {FCRT
, RA
, RB
}},
4363 {"subfc", XO(31,8,0,0), XO_MASK
, PPCCOM
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
4364 {"sf", XO(31,8,0,0), XO_MASK
, PWRCOM
, PPCNONE
, {RT
, RA
, RB
}},
4365 {"subc", XO(31,8,0,0), XO_MASK
, PPCCOM
|PPCVLE
, PPCNONE
, {RT
, RB
, RA
}},
4366 {"subfc.", XO(31,8,0,1), XO_MASK
, PPCCOM
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
4367 {"sf.", XO(31,8,0,1), XO_MASK
, PWRCOM
, PPCNONE
, {RT
, RA
, RB
}},
4368 {"subc.", XO(31,8,0,1), XO_MASK
, PPCCOM
|PPCVLE
, PPCNONE
, {RT
, RB
, RA
}},
4370 {"mulhdu", XO(31,9,0,0), XO_MASK
, PPC64
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
4371 {"mulhdu.", XO(31,9,0,1), XO_MASK
, PPC64
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
4373 {"addc", XO(31,10,0,0), XO_MASK
, PPCCOM
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
4374 {"a", XO(31,10,0,0), XO_MASK
, PWRCOM
, PPCNONE
, {RT
, RA
, RB
}},
4375 {"addc.", XO(31,10,0,1), XO_MASK
, PPCCOM
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
4376 {"a.", XO(31,10,0,1), XO_MASK
, PWRCOM
, PPCNONE
, {RT
, RA
, RB
}},
4378 {"mulhwu", XO(31,11,0,0), XO_MASK
, PPC
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
4379 {"mulhwu.", XO(31,11,0,1), XO_MASK
, PPC
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
4381 {"lxsiwzx", X(31,12), XX1_MASK
, PPCVSX2
, PPCNONE
, {XT6
, RA0
, RB
}},
4383 {"isellt", X(31,15), X_MASK
, PPCISEL
, PPCNONE
, {RT
, RA0
, RB
}},
4385 {"tlbilxlpid", XTO(31,18,0), XTO_MASK
, E500MC
|PPCA2
, PPCNONE
, {0}},
4386 {"tlbilxpid", XTO(31,18,1), XTO_MASK
, E500MC
|PPCA2
, PPCNONE
, {0}},
4387 {"tlbilxva", XTO(31,18,3), XTO_MASK
, E500MC
|PPCA2
, PPCNONE
, {RA0
, RB
}},
4388 {"tlbilx", X(31,18), X_MASK
, E500MC
|PPCA2
, PPCNONE
, {T
, RA0
, RB
}},
4390 {"mfcr", XFXM(31,19,0,0), XFXFXM_MASK
, POWER4
, PPCNONE
, {RT
, FXM4
}},
4391 {"mfcr", XFXM(31,19,0,0), XRARB_MASK
, COM
|PPCVLE
, POWER4
, {RT
}},
4392 {"mfocrf", XFXM(31,19,0,1), XFXFXM_MASK
, COM
|PPCVLE
, PPCNONE
, {RT
, FXM
}},
4394 {"lwarx", X(31,20), XEH_MASK
, PPC
|PPCVLE
, PPCNONE
, {RT
, RA0
, RB
, EH
}},
4396 {"ldx", X(31,21), X_MASK
, PPC64
|PPCVLE
, PPCNONE
, {RT
, RA0
, RB
}},
4398 {"icbt", X(31,22), X_MASK
, BOOKE
|PPCE300
|PPCA2
|PPC476
|PPCVLE
, PPCNONE
, {CT
, RA0
, RB
}},
4400 {"lwzx", X(31,23), X_MASK
, PPCCOM
|PPCVLE
, PPCNONE
, {RT
, RA0
, RB
}},
4401 {"lx", X(31,23), X_MASK
, PWRCOM
, PPCNONE
, {RT
, RA
, RB
}},
4403 {"slw", XRC(31,24,0), X_MASK
, PPCCOM
|PPCVLE
, PPCNONE
, {RA
, RS
, RB
}},
4404 {"sl", XRC(31,24,0), X_MASK
, PWRCOM
, PPCNONE
, {RA
, RS
, RB
}},
4405 {"slw.", XRC(31,24,1), X_MASK
, PPCCOM
|PPCVLE
, PPCNONE
, {RA
, RS
, RB
}},
4406 {"sl.", XRC(31,24,1), X_MASK
, PWRCOM
, PPCNONE
, {RA
, RS
, RB
}},
4408 {"cntlzw", XRC(31,26,0), XRB_MASK
, PPCCOM
|PPCVLE
, PPCNONE
, {RA
, RS
}},
4409 {"cntlz", XRC(31,26,0), XRB_MASK
, PWRCOM
, PPCNONE
, {RA
, RS
}},
4410 {"cntlzw.", XRC(31,26,1), XRB_MASK
, PPCCOM
|PPCVLE
, PPCNONE
, {RA
, RS
}},
4411 {"cntlz.", XRC(31,26,1), XRB_MASK
, PWRCOM
, PPCNONE
, {RA
, RS
}},
4413 {"sld", XRC(31,27,0), X_MASK
, PPC64
, PPCNONE
, {RA
, RS
, RB
}},
4414 {"sld.", XRC(31,27,1), X_MASK
, PPC64
, PPCNONE
, {RA
, RS
, RB
}},
4416 {"and", XRC(31,28,0), X_MASK
, COM
|PPCVLE
, PPCNONE
, {RA
, RS
, RB
}},
4417 {"and.", XRC(31,28,1), X_MASK
, COM
|PPCVLE
, PPCNONE
, {RA
, RS
, RB
}},
4419 {"maskg", XRC(31,29,0), X_MASK
, M601
, PPCA2
, {RA
, RS
, RB
}},
4420 {"maskg.", XRC(31,29,1), X_MASK
, M601
, PPCA2
, {RA
, RS
, RB
}},
4422 {"ldepx", X(31,29), X_MASK
, E500MC
|PPCA2
|PPCVLE
, PPCNONE
, {RT
, RA0
, RB
}},
4424 {"waitasec", X(31,30), XRTRARB_MASK
,POWER8
, PPCNONE
, {0}},
4426 {"lwepx", X(31,31), X_MASK
, E500MC
|PPCA2
|PPCVLE
, PPCNONE
, {RT
, RA0
, RB
}},
4428 {"cmplw", XOPL(31,32,0), XCMPL_MASK
, PPCCOM
|PPCVLE
, PPCNONE
, {OBF
, RA
, RB
}},
4429 {"cmpld", XOPL(31,32,1), XCMPL_MASK
, PPC64
, PPCNONE
, {OBF
, RA
, RB
}},
4430 {"cmpl", X(31,32), XCMP_MASK
, PPC
|PPCVLE
, PPCNONE
, {BF
, L
, RA
, RB
}},
4431 {"cmpl", X(31,32), XCMPL_MASK
, PWRCOM
, PPC
, {BF
, RA
, RB
}},
4433 {"lvsr", X(31,38), X_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, RA0
, RB
}},
4434 {"lvehx", X(31,39), X_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, RA0
, RB
}},
4435 {"lhfcmx", APU(31,39,0), APU_MASK
, PPC405
, PPCNONE
, {FCRT
, RA
, RB
}},
4437 {"mviwsplt", X(31,46), X_MASK
, PPCVEC2
, PPCNONE
, {VD
, RA
, RB
}},
4439 {"iselgt", X(31,47), X_MASK
, PPCISEL
, PPCNONE
, {RT
, RA0
, RB
}},
4441 {"lvewx", X(31,71), X_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, RA0
, RB
}},
4443 {"addg6s", XO(31,74,0,0), XO_MASK
, POWER6
, PPCNONE
, {RT
, RA
, RB
}},
4445 {"lxsiwax", X(31,76), XX1_MASK
, PPCVSX2
, PPCNONE
, {XT6
, RA0
, RB
}},
4447 {"iseleq", X(31,79), X_MASK
, PPCISEL
, PPCNONE
, {RT
, RA0
, RB
}},
4449 {"isel", XISEL(31,15), XISEL_MASK
, PPCISEL
|TITAN
|PPCVLE
, PPCNONE
, {RT
, RA0
, RB
, CRB
}},
4451 {"subf", XO(31,40,0,0), XO_MASK
, PPC
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
4452 {"sub", XO(31,40,0,0), XO_MASK
, PPC
|PPCVLE
, PPCNONE
, {RT
, RB
, RA
}},
4453 {"subf.", XO(31,40,0,1), XO_MASK
, PPC
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
4454 {"sub.", XO(31,40,0,1), XO_MASK
, PPC
|PPCVLE
, PPCNONE
, {RT
, RB
, RA
}},
4456 {"mfvsrd", X(31,51), XX1RB_MASK
, PPCVSX2
, PPCNONE
, {RA
, XS6
}},
4457 {"mffprd", X(31,51), XX1RB_MASK
|1, PPCVSX2
, PPCNONE
, {RA
, FRS
}},
4458 {"mfvrd", X(31,51)|1, XX1RB_MASK
|1, PPCVSX2
, PPCNONE
, {RA
, VS
}},
4459 {"eratilx", X(31,51), X_MASK
, PPCA2
, PPCNONE
, {ERAT_T
, RA
, RB
}},
4461 {"lbarx", X(31,52), XEH_MASK
, POWER7
|PPCVLE
, PPCNONE
, {RT
, RA0
, RB
, EH
}},
4463 {"ldux", X(31,53), X_MASK
, PPC64
|PPCVLE
, PPCNONE
, {RT
, RAL
, RB
}},
4465 {"dcbst", X(31,54), XRT_MASK
, PPC
|PPCVLE
, PPCNONE
, {RA0
, RB
}},
4467 {"lwzux", X(31,55), X_MASK
, PPCCOM
|PPCVLE
, PPCNONE
, {RT
, RAL
, RB
}},
4468 {"lux", X(31,55), X_MASK
, PWRCOM
, PPCNONE
, {RT
, RA
, RB
}},
4470 {"cntlzd", XRC(31,58,0), XRB_MASK
, PPC64
|PPCVLE
, PPCNONE
, {RA
, RS
}},
4471 {"cntlzd.", XRC(31,58,1), XRB_MASK
, PPC64
|PPCVLE
, PPCNONE
, {RA
, RS
}},
4473 {"andc", XRC(31,60,0), X_MASK
, COM
|PPCVLE
, PPCNONE
, {RA
, RS
, RB
}},
4474 {"andc.", XRC(31,60,1), X_MASK
, COM
|PPCVLE
, PPCNONE
, {RA
, RS
, RB
}},
4476 {"waitrsv", X(31,62)|(1<<21), 0xffffffff, POWER7
|E500MC
|PPCA2
, PPCNONE
, {0}},
4477 {"waitimpl", X(31,62)|(2<<21), 0xffffffff, POWER7
|E500MC
|PPCA2
, PPCNONE
, {0}},
4478 {"wait", X(31,62), XWC_MASK
, POWER7
|E500MC
|PPCA2
|PPCVLE
, PPCNONE
, {WC
}},
4480 {"dcbstep", XRT(31,63,0), XRT_MASK
, E500MC
|PPCA2
|PPCVLE
, PPCNONE
, {RA0
, RB
}},
4482 {"tdlgt", XTO(31,68,TOLGT
), XTO_MASK
, PPC64
, PPCNONE
, {RA
, RB
}},
4483 {"tdllt", XTO(31,68,TOLLT
), XTO_MASK
, PPC64
, PPCNONE
, {RA
, RB
}},
4484 {"tdeq", XTO(31,68,TOEQ
), XTO_MASK
, PPC64
, PPCNONE
, {RA
, RB
}},
4485 {"tdlge", XTO(31,68,TOLGE
), XTO_MASK
, PPC64
, PPCNONE
, {RA
, RB
}},
4486 {"tdlnl", XTO(31,68,TOLNL
), XTO_MASK
, PPC64
, PPCNONE
, {RA
, RB
}},
4487 {"tdlle", XTO(31,68,TOLLE
), XTO_MASK
, PPC64
, PPCNONE
, {RA
, RB
}},
4488 {"tdlng", XTO(31,68,TOLNG
), XTO_MASK
, PPC64
, PPCNONE
, {RA
, RB
}},
4489 {"tdgt", XTO(31,68,TOGT
), XTO_MASK
, PPC64
, PPCNONE
, {RA
, RB
}},
4490 {"tdge", XTO(31,68,TOGE
), XTO_MASK
, PPC64
, PPCNONE
, {RA
, RB
}},
4491 {"tdnl", XTO(31,68,TONL
), XTO_MASK
, PPC64
, PPCNONE
, {RA
, RB
}},
4492 {"tdlt", XTO(31,68,TOLT
), XTO_MASK
, PPC64
, PPCNONE
, {RA
, RB
}},
4493 {"tdle", XTO(31,68,TOLE
), XTO_MASK
, PPC64
, PPCNONE
, {RA
, RB
}},
4494 {"tdng", XTO(31,68,TONG
), XTO_MASK
, PPC64
, PPCNONE
, {RA
, RB
}},
4495 {"tdne", XTO(31,68,TONE
), XTO_MASK
, PPC64
, PPCNONE
, {RA
, RB
}},
4496 {"tdu", XTO(31,68,TOU
), XTO_MASK
, PPC64
, PPCNONE
, {RA
, RB
}},
4497 {"td", X(31,68), X_MASK
, PPC64
|PPCVLE
, PPCNONE
, {TO
, RA
, RB
}},
4499 {"lwfcmx", APU(31,71,0), APU_MASK
, PPC405
, PPCNONE
, {FCRT
, RA
, RB
}},
4500 {"mulhd", XO(31,73,0,0), XO_MASK
, PPC64
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
4501 {"mulhd.", XO(31,73,0,1), XO_MASK
, PPC64
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
4503 {"mulhw", XO(31,75,0,0), XO_MASK
, PPC
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
4504 {"mulhw.", XO(31,75,0,1), XO_MASK
, PPC
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
4506 {"dlmzb", XRC(31,78,0), X_MASK
, PPC403
|PPC440
|TITAN
|PPCVLE
, PPCNONE
, {RA
, RS
, RB
}},
4507 {"dlmzb.", XRC(31,78,1), X_MASK
, PPC403
|PPC440
|TITAN
|PPCVLE
, PPCNONE
, {RA
, RS
, RB
}},
4509 {"mtsrd", X(31,82), XRB_MASK
|(1<<20), PPC64
, PPCNONE
, {SR
, RS
}},
4511 {"mfmsr", X(31,83), XRARB_MASK
, COM
|PPCVLE
, PPCNONE
, {RT
}},
4513 {"ldarx", X(31,84), XEH_MASK
, PPC64
|PPCVLE
, PPCNONE
, {RT
, RA0
, RB
, EH
}},
4515 {"dcbfl", XOPL(31,86,1), XRT_MASK
, POWER5
, PPC476
, {RA0
, RB
}},
4516 {"dcbf", X(31,86), XLRT_MASK
, PPC
|PPCVLE
, PPCNONE
, {RA0
, RB
, L
}},
4518 {"lbzx", X(31,87), X_MASK
, COM
|PPCVLE
, PPCNONE
, {RT
, RA0
, RB
}},
4520 {"lbepx", X(31,95), X_MASK
, E500MC
|PPCA2
|PPCVLE
, PPCNONE
, {RT
, RA0
, RB
}},
4522 {"dni", XRC(31,97,1), XRB_MASK
, E6500
, PPCNONE
, {DUI
, DCTL
}},
4524 {"lvx", X(31,103), X_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, RA0
, RB
}},
4525 {"lqfcmx", APU(31,103,0), APU_MASK
, PPC405
, PPCNONE
, {FCRT
, RA
, RB
}},
4527 {"neg", XO(31,104,0,0), XORB_MASK
, COM
|PPCVLE
, PPCNONE
, {RT
, RA
}},
4528 {"neg.", XO(31,104,0,1), XORB_MASK
, COM
|PPCVLE
, PPCNONE
, {RT
, RA
}},
4530 {"mul", XO(31,107,0,0), XO_MASK
, M601
, PPCNONE
, {RT
, RA
, RB
}},
4531 {"mul.", XO(31,107,0,1), XO_MASK
, M601
, PPCNONE
, {RT
, RA
, RB
}},
4533 {"mvidsplt", X(31,110), X_MASK
, PPCVEC2
, PPCNONE
, {VD
, RA
, RB
}},
4535 {"mtsrdin", X(31,114), XRA_MASK
, PPC64
, PPCNONE
, {RS
, RB
}},
4537 {"mffprwz", X(31,115), XX1RB_MASK
|1, PPCVSX2
, PPCNONE
, {RA
, FRS
}},
4538 {"mfvrwz", X(31,115)|1, XX1RB_MASK
|1, PPCVSX2
, PPCNONE
, {RA
, VS
}},
4539 {"mfvsrwz", X(31,115), XX1RB_MASK
, PPCVSX2
, PPCNONE
, {RA
, XS6
}},
4541 {"lharx", X(31,116), XEH_MASK
, POWER7
|PPCVLE
, PPCNONE
, {RT
, RA0
, RB
, EH
}},
4543 {"clf", X(31,118), XTO_MASK
, POWER
, PPCNONE
, {RA
, RB
}},
4545 {"lbzux", X(31,119), X_MASK
, COM
|PPCVLE
, PPCNONE
, {RT
, RAL
, RB
}},
4547 {"popcntb", X(31,122), XRB_MASK
, POWER5
|PPCVLE
, PPCNONE
, {RA
, RS
}},
4549 {"not", XRC(31,124,0), X_MASK
, COM
, PPCNONE
, {RA
, RS
, RBS
}},
4550 {"nor", XRC(31,124,0), X_MASK
, COM
|PPCVLE
, PPCNONE
, {RA
, RS
, RB
}},
4551 {"not.", XRC(31,124,1), X_MASK
, COM
, PPCNONE
, {RA
, RS
, RBS
}},
4552 {"nor.", XRC(31,124,1), X_MASK
, COM
|PPCVLE
, PPCNONE
, {RA
, RS
, RB
}},
4554 {"dcbfep", XRT(31,127,0), XRT_MASK
, E500MC
|PPCA2
|PPCVLE
, PPCNONE
, {RA0
, RB
}},
4556 {"wrtee", X(31,131), XRARB_MASK
, PPC403
|BOOKE
|PPCA2
|PPC476
|PPCVLE
, PPCNONE
, {RS
}},
4558 {"dcbtstls", X(31,134), X_MASK
, PPCCHLK
|PPC476
|TITAN
|PPCVLE
, PPCNONE
, {CT
, RA0
, RB
}},
4560 {"stvebx", X(31,135), X_MASK
, PPCVEC
, PPCNONE
, {VS
, RA0
, RB
}},
4561 {"stbfcmx", APU(31,135,0), APU_MASK
, PPC405
, PPCNONE
, {FCRT
, RA
, RB
}},
4563 {"subfe", XO(31,136,0,0), XO_MASK
, PPCCOM
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
4564 {"sfe", XO(31,136,0,0), XO_MASK
, PWRCOM
, PPCNONE
, {RT
, RA
, RB
}},
4565 {"subfe.", XO(31,136,0,1), XO_MASK
, PPCCOM
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
4566 {"sfe.", XO(31,136,0,1), XO_MASK
, PWRCOM
, PPCNONE
, {RT
, RA
, RB
}},
4568 {"adde", XO(31,138,0,0), XO_MASK
, PPCCOM
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
4569 {"ae", XO(31,138,0,0), XO_MASK
, PWRCOM
, PPCNONE
, {RT
, RA
, RB
}},
4570 {"adde.", XO(31,138,0,1), XO_MASK
, PPCCOM
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
4571 {"ae.", XO(31,138,0,1), XO_MASK
, PWRCOM
, PPCNONE
, {RT
, RA
, RB
}},
4573 {"stxsiwx", X(31,140), XX1_MASK
, PPCVSX2
, PPCNONE
, {XS6
, RA0
, RB
}},
4575 {"msgsndp", XRTRA(31,142,0,0), XRTRA_MASK
, POWER8
, PPCNONE
, {RB
}},
4576 {"dcbtstlse", X(31,142), X_MASK
, PPCCHLK
, E500MC
, {CT
, RA0
, RB
}},
4578 {"mtcr", XFXM(31,144,0xff,0), XRARB_MASK
, COM
, PPCNONE
, {RS
}},
4579 {"mtcrf", XFXM(31,144,0,0), XFXFXM_MASK
, COM
|PPCVLE
, PPCNONE
, {FXM
, RS
}},
4580 {"mtocrf", XFXM(31,144,0,1), XFXFXM_MASK
, COM
|PPCVLE
, PPCNONE
, {FXM
, RS
}},
4582 {"mtmsr", X(31,146), XRLARB_MASK
, COM
|PPCVLE
, PPCNONE
, {RS
, A_L
}},
4584 {"mtsle", X(31,147), XRTLRARB_MASK
, POWER8
, PPCNONE
, {L
}},
4586 {"eratsx", XRC(31,147,0), X_MASK
, PPCA2
, PPCNONE
, {RT
, RA0
, RB
}},
4587 {"eratsx.", XRC(31,147,1), X_MASK
, PPCA2
, PPCNONE
, {RT
, RA0
, RB
}},
4589 {"stdx", X(31,149), X_MASK
, PPC64
|PPCVLE
, PPCNONE
, {RS
, RA0
, RB
}},
4591 {"stwcx.", XRC(31,150,1), X_MASK
, PPC
|PPCVLE
, PPCNONE
, {RS
, RA0
, RB
}},
4593 {"stwx", X(31,151), X_MASK
, PPCCOM
|PPCVLE
, PPCNONE
, {RS
, RA0
, RB
}},
4594 {"stx", X(31,151), X_MASK
, PWRCOM
, PPCNONE
, {RS
, RA
, RB
}},
4596 {"slq", XRC(31,152,0), X_MASK
, M601
, PPCNONE
, {RA
, RS
, RB
}},
4597 {"slq.", XRC(31,152,1), X_MASK
, M601
, PPCNONE
, {RA
, RS
, RB
}},
4599 {"sle", XRC(31,153,0), X_MASK
, M601
, PPCNONE
, {RA
, RS
, RB
}},
4600 {"sle.", XRC(31,153,1), X_MASK
, M601
, PPCNONE
, {RA
, RS
, RB
}},
4602 {"prtyw", X(31,154), XRB_MASK
, POWER6
|PPCA2
|PPC476
, PPCNONE
, {RA
, RS
}},
4604 {"stdepx", X(31,157), X_MASK
, E500MC
|PPCA2
|PPCVLE
, PPCNONE
, {RS
, RA0
, RB
}},
4606 {"stwepx", X(31,159), X_MASK
, E500MC
|PPCA2
|PPCVLE
, PPCNONE
, {RS
, RA0
, RB
}},
4608 {"wrteei", X(31,163), XE_MASK
, PPC403
|BOOKE
|PPCA2
|PPC476
|PPCVLE
, PPCNONE
, {E
}},
4610 {"dcbtls", X(31,166), X_MASK
, PPCCHLK
|PPC476
|TITAN
|PPCVLE
, PPCNONE
, {CT
, RA0
, RB
}},
4612 {"stvehx", X(31,167), X_MASK
, PPCVEC
, PPCNONE
, {VS
, RA0
, RB
}},
4613 {"sthfcmx", APU(31,167,0), APU_MASK
, PPC405
, PPCNONE
, {FCRT
, RA
, RB
}},
4615 {"msgclrp", XRTRA(31,174,0,0), XRTRA_MASK
, POWER8
, PPCNONE
, {RB
}},
4616 {"dcbtlse", X(31,174), X_MASK
, PPCCHLK
, E500MC
, {CT
, RA0
, RB
}},
4618 {"mtmsrd", X(31,178), XRLARB_MASK
, PPC64
, PPCNONE
, {RS
, A_L
}},
4620 {"mtvsrd", X(31,179), XX1RB_MASK
, PPCVSX2
, PPCNONE
, {XT6
, RA
}},
4621 {"mtfprd", X(31,179), XX1RB_MASK
|1, PPCVSX2
, PPCNONE
, {FRT
, RA
}},
4622 {"mtvrd", X(31,179)|1, XX1RB_MASK
|1, PPCVSX2
, PPCNONE
, {VD
, RA
}},
4623 {"eratre", X(31,179), X_MASK
, PPCA2
, PPCNONE
, {RT
, RA
, WS
}},
4625 {"stdux", X(31,181), X_MASK
, PPC64
|PPCVLE
, PPCNONE
, {RS
, RAS
, RB
}},
4627 {"stqcx.", XRC(31,182,1), X_MASK
, POWER8
, PPCNONE
, {RSQ
, RA0
, RB
}},
4628 {"wchkall", X(31,182), X_MASK
, PPCA2
, PPCNONE
, {OBF
}},
4630 {"stwux", X(31,183), X_MASK
, PPCCOM
|PPCVLE
, PPCNONE
, {RS
, RAS
, RB
}},
4631 {"stux", X(31,183), X_MASK
, PWRCOM
, PPCNONE
, {RS
, RA0
, RB
}},
4633 {"sliq", XRC(31,184,0), X_MASK
, M601
, PPCNONE
, {RA
, RS
, SH
}},
4634 {"sliq.", XRC(31,184,1), X_MASK
, M601
, PPCNONE
, {RA
, RS
, SH
}},
4636 {"prtyd", X(31,186), XRB_MASK
, POWER6
|PPCA2
, PPCNONE
, {RA
, RS
}},
4638 {"icblq.", XRC(31,198,1), X_MASK
, E6500
, PPCNONE
, {CT
, RA0
, RB
}},
4640 {"stvewx", X(31,199), X_MASK
, PPCVEC
, PPCNONE
, {VS
, RA0
, RB
}},
4641 {"stwfcmx", APU(31,199,0), APU_MASK
, PPC405
, PPCNONE
, {FCRT
, RA
, RB
}},
4643 {"subfze", XO(31,200,0,0), XORB_MASK
, PPCCOM
|PPCVLE
, PPCNONE
, {RT
, RA
}},
4644 {"sfze", XO(31,200,0,0), XORB_MASK
, PWRCOM
, PPCNONE
, {RT
, RA
}},
4645 {"subfze.", XO(31,200,0,1), XORB_MASK
, PPCCOM
|PPCVLE
, PPCNONE
, {RT
, RA
}},
4646 {"sfze.", XO(31,200,0,1), XORB_MASK
, PWRCOM
, PPCNONE
, {RT
, RA
}},
4648 {"addze", XO(31,202,0,0), XORB_MASK
, PPCCOM
|PPCVLE
, PPCNONE
, {RT
, RA
}},
4649 {"aze", XO(31,202,0,0), XORB_MASK
, PWRCOM
, PPCNONE
, {RT
, RA
}},
4650 {"addze.", XO(31,202,0,1), XORB_MASK
, PPCCOM
|PPCVLE
, PPCNONE
, {RT
, RA
}},
4651 {"aze.", XO(31,202,0,1), XORB_MASK
, PWRCOM
, PPCNONE
, {RT
, RA
}},
4653 {"msgsnd", XRTRA(31,206,0,0), XRTRA_MASK
, E500MC
|PPCA2
|PPCVLE
, PPCNONE
, {RB
}},
4655 {"mtsr", X(31,210), XRB_MASK
|(1<<20), COM
, NON32
, {SR
, RS
}},
4657 {"mtfprwa", X(31,211), XX1RB_MASK
|1, PPCVSX2
, PPCNONE
, {FRT
, RA
}},
4658 {"mtvrwa", X(31,211)|1, XX1RB_MASK
|1, PPCVSX2
, PPCNONE
, {VD
, RA
}},
4659 {"mtvsrwa", X(31,211), XX1RB_MASK
, PPCVSX2
, PPCNONE
, {XT6
, RA
}},
4660 {"eratwe", X(31,211), X_MASK
, PPCA2
, PPCNONE
, {RS
, RA
, WS
}},
4662 {"ldawx.", XRC(31,212,1), X_MASK
, PPCA2
, PPCNONE
, {RT
, RA0
, RB
}},
4664 {"stdcx.", XRC(31,214,1), X_MASK
, PPC64
|PPCVLE
, PPCNONE
, {RS
, RA0
, RB
}},
4666 {"stbx", X(31,215), X_MASK
, COM
|PPCVLE
, PPCNONE
, {RS
, RA0
, RB
}},
4668 {"sllq", XRC(31,216,0), X_MASK
, M601
, PPCNONE
, {RA
, RS
, RB
}},
4669 {"sllq.", XRC(31,216,1), X_MASK
, M601
, PPCNONE
, {RA
, RS
, RB
}},
4671 {"sleq", XRC(31,217,0), X_MASK
, M601
, PPCNONE
, {RA
, RS
, RB
}},
4672 {"sleq.", XRC(31,217,1), X_MASK
, M601
, PPCNONE
, {RA
, RS
, RB
}},
4674 {"stbepx", X(31,223), X_MASK
, E500MC
|PPCA2
|PPCVLE
, PPCNONE
, {RS
, RA0
, RB
}},
4676 {"icblc", X(31,230), X_MASK
, PPCCHLK
|PPC476
|TITAN
|PPCVLE
, PPCNONE
, {CT
, RA0
, RB
}},
4678 {"stvx", X(31,231), X_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VS
, RA0
, RB
}},
4679 {"stqfcmx", APU(31,231,0), APU_MASK
, PPC405
, PPCNONE
, {FCRT
, RA
, RB
}},
4681 {"subfme", XO(31,232,0,0), XORB_MASK
, PPCCOM
|PPCVLE
, PPCNONE
, {RT
, RA
}},
4682 {"sfme", XO(31,232,0,0), XORB_MASK
, PWRCOM
, PPCNONE
, {RT
, RA
}},
4683 {"subfme.", XO(31,232,0,1), XORB_MASK
, PPCCOM
|PPCVLE
, PPCNONE
, {RT
, RA
}},
4684 {"sfme.", XO(31,232,0,1), XORB_MASK
, PWRCOM
, PPCNONE
, {RT
, RA
}},
4686 {"mulld", XO(31,233,0,0), XO_MASK
, PPC64
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
4687 {"mulld.", XO(31,233,0,1), XO_MASK
, PPC64
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
4689 {"addme", XO(31,234,0,0), XORB_MASK
, PPCCOM
|PPCVLE
, PPCNONE
, {RT
, RA
}},
4690 {"ame", XO(31,234,0,0), XORB_MASK
, PWRCOM
, PPCNONE
, {RT
, RA
}},
4691 {"addme.", XO(31,234,0,1), XORB_MASK
, PPCCOM
|PPCVLE
, PPCNONE
, {RT
, RA
}},
4692 {"ame.", XO(31,234,0,1), XORB_MASK
, PWRCOM
, PPCNONE
, {RT
, RA
}},
4694 {"mullw", XO(31,235,0,0), XO_MASK
, PPCCOM
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
4695 {"muls", XO(31,235,0,0), XO_MASK
, PWRCOM
, PPCNONE
, {RT
, RA
, RB
}},
4696 {"mullw.", XO(31,235,0,1), XO_MASK
, PPCCOM
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
4697 {"muls.", XO(31,235,0,1), XO_MASK
, PWRCOM
, PPCNONE
, {RT
, RA
, RB
}},
4699 {"icblce", X(31,238), X_MASK
, PPCCHLK
, E500MC
|PPCA2
, {CT
, RA
, RB
}},
4700 {"msgclr", XRTRA(31,238,0,0),XRTRA_MASK
, E500MC
|PPCA2
|PPCVLE
, PPCNONE
, {RB
}},
4701 {"mtsrin", X(31,242), XRA_MASK
, PPC
, NON32
, {RS
, RB
}},
4702 {"mtsri", X(31,242), XRA_MASK
, POWER
, NON32
, {RS
, RB
}},
4704 {"mtfprwz", X(31,243), XX1RB_MASK
|1, PPCVSX2
, PPCNONE
, {FRT
, RA
}},
4705 {"mtvrwz", X(31,243)|1, XX1RB_MASK
|1, PPCVSX2
, PPCNONE
, {VD
, RA
}},
4706 {"mtvsrwz", X(31,243), XX1RB_MASK
, PPCVSX2
, PPCNONE
, {XT6
, RA
}},
4708 {"dcbtstt", XRT(31,246,0x10), XRT_MASK
, POWER7
, PPCNONE
, {RA0
, RB
}},
4709 {"dcbtst", X(31,246), X_MASK
, POWER4
, PPCNONE
, {RA0
, RB
, CT
}},
4710 {"dcbtst", X(31,246), X_MASK
, PPC
|PPCVLE
, POWER4
, {CT
, RA0
, RB
}},
4712 {"stbux", X(31,247), X_MASK
, COM
|PPCVLE
, PPCNONE
, {RS
, RAS
, RB
}},
4714 {"slliq", XRC(31,248,0), X_MASK
, M601
, PPCNONE
, {RA
, RS
, SH
}},
4715 {"slliq.", XRC(31,248,1), X_MASK
, M601
, PPCNONE
, {RA
, RS
, SH
}},
4717 {"bpermd", X(31,252), X_MASK
, POWER7
|PPCA2
, PPCNONE
, {RA
, RS
, RB
}},
4719 {"dcbtstep", XRT(31,255,0), X_MASK
, E500MC
|PPCA2
|PPCVLE
, PPCNONE
, {RT
, RA0
, RB
}},
4721 {"mfdcrx", X(31,259), X_MASK
, BOOKE
|PPCA2
|PPC476
|PPCVLE
, TITAN
, {RS
, RA
}},
4722 {"mfdcrx.", XRC(31,259,1), X_MASK
, PPCA2
, PPCNONE
, {RS
, RA
}},
4724 {"lvexbx", X(31,261), X_MASK
, PPCVEC2
, PPCNONE
, {VD
, RA0
, RB
}},
4726 {"icbt", X(31,262), XRT_MASK
, PPC403
, PPCNONE
, {RA
, RB
}},
4728 {"lvepxl", X(31,263), X_MASK
, PPCVEC2
|PPCVLE
, PPCNONE
, {VD
, RA0
, RB
}},
4730 {"ldfcmx", APU(31,263,0), APU_MASK
, PPC405
, PPCNONE
, {FCRT
, RA
, RB
}},
4731 {"doz", XO(31,264,0,0), XO_MASK
, M601
, PPCNONE
, {RT
, RA
, RB
}},
4732 {"doz.", XO(31,264,0,1), XO_MASK
, M601
, PPCNONE
, {RT
, RA
, RB
}},
4734 {"add", XO(31,266,0,0), XO_MASK
, PPCCOM
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
4735 {"cax", XO(31,266,0,0), XO_MASK
, PWRCOM
, PPCNONE
, {RT
, RA
, RB
}},
4736 {"add.", XO(31,266,0,1), XO_MASK
, PPCCOM
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
4737 {"cax.", XO(31,266,0,1), XO_MASK
, PWRCOM
, PPCNONE
, {RT
, RA
, RB
}},
4739 {"ehpriv", X(31,270), 0xffffffff, E500MC
|PPCA2
|PPCVLE
, PPCNONE
, {0}},
4741 {"tlbiel", X(31,274), XRTLRA_MASK
, POWER4
, PPC476
, {RB
, L
}},
4743 {"mfapidi", X(31,275), X_MASK
, BOOKE
, TITAN
, {RT
, RA
}},
4745 {"lqarx", X(31,276), XEH_MASK
, POWER8
, PPCNONE
, {RTQ
, RAX
, RBX
, EH
}},
4747 {"lscbx", XRC(31,277,0), X_MASK
, M601
, PPCNONE
, {RT
, RA
, RB
}},
4748 {"lscbx.", XRC(31,277,1), X_MASK
, M601
, PPCNONE
, {RT
, RA
, RB
}},
4750 {"dcbtt", XRT(31,278,0x10), XRT_MASK
, POWER7
, PPCNONE
, {RA0
, RB
}},
4751 {"dcbt", X(31,278), X_MASK
, POWER4
, PPCNONE
, {RA0
, RB
, CT
}},
4752 {"dcbt", X(31,278), X_MASK
, PPC
|PPCVLE
, POWER4
, {CT
, RA0
, RB
}},
4754 {"lhzx", X(31,279), X_MASK
, COM
|PPCVLE
, PPCNONE
, {RT
, RA0
, RB
}},
4756 {"cdtbcd", X(31,282), XRB_MASK
, POWER6
, PPCNONE
, {RA
, RS
}},
4758 {"eqv", XRC(31,284,0), X_MASK
, COM
|PPCVLE
, PPCNONE
, {RA
, RS
, RB
}},
4759 {"eqv.", XRC(31,284,1), X_MASK
, COM
|PPCVLE
, PPCNONE
, {RA
, RS
, RB
}},
4761 {"lhepx", X(31,287), X_MASK
, E500MC
|PPCA2
|PPCVLE
, PPCNONE
, {RT
, RA0
, RB
}},
4763 {"mfdcrux", X(31,291), X_MASK
, PPC464
|PPCVLE
, PPCNONE
, {RS
, RA
}},
4765 {"lvexhx", X(31,293), X_MASK
, PPCVEC2
, PPCNONE
, {VD
, RA0
, RB
}},
4766 {"lvepx", X(31,295), X_MASK
, PPCVEC2
|PPCVLE
, PPCNONE
, {VD
, RA0
, RB
}},
4768 {"mfbhrbe", X(31,302), X_MASK
, POWER8
, PPCNONE
, {RT
, BHRBE
}},
4770 {"tlbie", X(31,306), XRTLRA_MASK
, PPC
, TITAN
, {RB
, L
}},
4771 {"tlbi", X(31,306), XRT_MASK
, POWER
, PPCNONE
, {RA0
, RB
}},
4773 {"eciwx", X(31,310), X_MASK
, PPC
, TITAN
, {RT
, RA0
, RB
}},
4775 {"lhzux", X(31,311), X_MASK
, COM
|PPCVLE
, PPCNONE
, {RT
, RAL
, RB
}},
4777 {"cbcdtd", X(31,314), XRB_MASK
, POWER6
, PPCNONE
, {RA
, RS
}},
4779 {"xor", XRC(31,316,0), X_MASK
, COM
|PPCVLE
, PPCNONE
, {RA
, RS
, RB
}},
4780 {"xor.", XRC(31,316,1), X_MASK
, COM
|PPCVLE
, PPCNONE
, {RA
, RS
, RB
}},
4782 {"dcbtep", XRT(31,319,0), X_MASK
, E500MC
|PPCA2
|PPCVLE
, PPCNONE
, {RT
, RA0
, RB
}},
4784 {"mfexisr", XSPR(31,323, 64), XSPR_MASK
, PPC403
, PPCNONE
, {RT
}},
4785 {"mfexier", XSPR(31,323, 66), XSPR_MASK
, PPC403
, PPCNONE
, {RT
}},
4786 {"mfbr0", XSPR(31,323,128), XSPR_MASK
, PPC403
, PPCNONE
, {RT
}},
4787 {"mfbr1", XSPR(31,323,129), XSPR_MASK
, PPC403
, PPCNONE
, {RT
}},
4788 {"mfbr2", XSPR(31,323,130), XSPR_MASK
, PPC403
, PPCNONE
, {RT
}},
4789 {"mfbr3", XSPR(31,323,131), XSPR_MASK
, PPC403
, PPCNONE
, {RT
}},
4790 {"mfbr4", XSPR(31,323,132), XSPR_MASK
, PPC403
, PPCNONE
, {RT
}},
4791 {"mfbr5", XSPR(31,323,133), XSPR_MASK
, PPC403
, PPCNONE
, {RT
}},
4792 {"mfbr6", XSPR(31,323,134), XSPR_MASK
, PPC403
, PPCNONE
, {RT
}},
4793 {"mfbr7", XSPR(31,323,135), XSPR_MASK
, PPC403
, PPCNONE
, {RT
}},
4794 {"mfbear", XSPR(31,323,144), XSPR_MASK
, PPC403
, PPCNONE
, {RT
}},
4795 {"mfbesr", XSPR(31,323,145), XSPR_MASK
, PPC403
, PPCNONE
, {RT
}},
4796 {"mfiocr", XSPR(31,323,160), XSPR_MASK
, PPC403
, PPCNONE
, {RT
}},
4797 {"mfdmacr0", XSPR(31,323,192), XSPR_MASK
, PPC403
, PPCNONE
, {RT
}},
4798 {"mfdmact0", XSPR(31,323,193), XSPR_MASK
, PPC403
, PPCNONE
, {RT
}},
4799 {"mfdmada0", XSPR(31,323,194), XSPR_MASK
, PPC403
, PPCNONE
, {RT
}},
4800 {"mfdmasa0", XSPR(31,323,195), XSPR_MASK
, PPC403
, PPCNONE
, {RT
}},
4801 {"mfdmacc0", XSPR(31,323,196), XSPR_MASK
, PPC403
, PPCNONE
, {RT
}},
4802 {"mfdmacr1", XSPR(31,323,200), XSPR_MASK
, PPC403
, PPCNONE
, {RT
}},
4803 {"mfdmact1", XSPR(31,323,201), XSPR_MASK
, PPC403
, PPCNONE
, {RT
}},
4804 {"mfdmada1", XSPR(31,323,202), XSPR_MASK
, PPC403
, PPCNONE
, {RT
}},
4805 {"mfdmasa1", XSPR(31,323,203), XSPR_MASK
, PPC403
, PPCNONE
, {RT
}},
4806 {"mfdmacc1", XSPR(31,323,204), XSPR_MASK
, PPC403
, PPCNONE
, {RT
}},
4807 {"mfdmacr2", XSPR(31,323,208), XSPR_MASK
, PPC403
, PPCNONE
, {RT
}},
4808 {"mfdmact2", XSPR(31,323,209), XSPR_MASK
, PPC403
, PPCNONE
, {RT
}},
4809 {"mfdmada2", XSPR(31,323,210), XSPR_MASK
, PPC403
, PPCNONE
, {RT
}},
4810 {"mfdmasa2", XSPR(31,323,211), XSPR_MASK
, PPC403
, PPCNONE
, {RT
}},
4811 {"mfdmacc2", XSPR(31,323,212), XSPR_MASK
, PPC403
, PPCNONE
, {RT
}},
4812 {"mfdmacr3", XSPR(31,323,216), XSPR_MASK
, PPC403
, PPCNONE
, {RT
}},
4813 {"mfdmact3", XSPR(31,323,217), XSPR_MASK
, PPC403
, PPCNONE
, {RT
}},
4814 {"mfdmada3", XSPR(31,323,218), XSPR_MASK
, PPC403
, PPCNONE
, {RT
}},
4815 {"mfdmasa3", XSPR(31,323,219), XSPR_MASK
, PPC403
, PPCNONE
, {RT
}},
4816 {"mfdmacc3", XSPR(31,323,220), XSPR_MASK
, PPC403
, PPCNONE
, {RT
}},
4817 {"mfdmasr", XSPR(31,323,224), XSPR_MASK
, PPC403
, PPCNONE
, {RT
}},
4818 {"mfdcr", X(31,323), X_MASK
, PPC403
|BOOKE
|PPCA2
|PPC476
|PPCVLE
, TITAN
, {RT
, SPR
}},
4819 {"mfdcr.", XRC(31,323,1), X_MASK
, PPCA2
, PPCNONE
, {RT
, SPR
}},
4821 {"lvexwx", X(31,325), X_MASK
, PPCVEC2
, PPCNONE
, {VD
, RA0
, RB
}},
4823 {"dcread", X(31,326), X_MASK
, PPC476
|TITAN
, PPCNONE
, {RT
, RA0
, RB
}},
4825 {"div", XO(31,331,0,0), XO_MASK
, M601
, PPCNONE
, {RT
, RA
, RB
}},
4826 {"div.", XO(31,331,0,1), XO_MASK
, M601
, PPCNONE
, {RT
, RA
, RB
}},
4828 {"lxvdsx", X(31,332), XX1_MASK
, PPCVSX
, PPCNONE
, {XT6
, RA0
, RB
}},
4830 {"mfpmr", X(31,334), X_MASK
, PPCPMR
|PPCE300
|PPCVLE
, PPCNONE
, {RT
, PMR
}},
4831 {"mftmr", X(31,366), X_MASK
, PPCTMR
|E6500
, PPCNONE
, {RT
, TMR
}},
4833 {"mfmq", XSPR(31,339, 0), XSPR_MASK
, M601
, PPCNONE
, {RT
}},
4834 {"mfxer", XSPR(31,339, 1), XSPR_MASK
, COM
|PPCVLE
, PPCNONE
, {RT
}},
4835 {"mfrtcu", XSPR(31,339, 4), XSPR_MASK
, COM
, TITAN
, {RT
}},
4836 {"mfrtcl", XSPR(31,339, 5), XSPR_MASK
, COM
, TITAN
, {RT
}},
4837 {"mfdec", XSPR(31,339, 6), XSPR_MASK
, MFDEC1
, PPCNONE
, {RT
}},
4838 {"mflr", XSPR(31,339, 8), XSPR_MASK
, COM
|PPCVLE
, PPCNONE
, {RT
}},
4839 {"mfctr", XSPR(31,339, 9), XSPR_MASK
, COM
|PPCVLE
, PPCNONE
, {RT
}},
4840 {"mftid", XSPR(31,339, 17), XSPR_MASK
, POWER
, PPCNONE
, {RT
}},
4841 {"mfdsisr", XSPR(31,339, 18), XSPR_MASK
, COM
, TITAN
, {RT
}},
4842 {"mfdar", XSPR(31,339, 19), XSPR_MASK
, COM
, TITAN
, {RT
}},
4843 {"mfdec", XSPR(31,339, 22), XSPR_MASK
, MFDEC2
, MFDEC1
, {RT
}},
4844 {"mfsdr0", XSPR(31,339, 24), XSPR_MASK
, POWER
, PPCNONE
, {RT
}},
4845 {"mfsdr1", XSPR(31,339, 25), XSPR_MASK
, COM
, TITAN
, {RT
}},
4846 {"mfsrr0", XSPR(31,339, 26), XSPR_MASK
, COM
, PPCNONE
, {RT
}},
4847 {"mfsrr1", XSPR(31,339, 27), XSPR_MASK
, COM
, PPCNONE
, {RT
}},
4848 {"mfcfar", XSPR(31,339, 28), XSPR_MASK
, POWER6
, PPCNONE
, {RT
}},
4849 {"mfpid", XSPR(31,339, 48), XSPR_MASK
, BOOKE
|PPCVLE
, PPCNONE
, {RT
}},
4850 {"mfcsrr0", XSPR(31,339, 58), XSPR_MASK
, BOOKE
|PPCVLE
, PPCNONE
, {RT
}},
4851 {"mfcsrr1", XSPR(31,339, 59), XSPR_MASK
, BOOKE
|PPCVLE
, PPCNONE
, {RT
}},
4852 {"mfdear", XSPR(31,339, 61), XSPR_MASK
, BOOKE
|PPCVLE
, PPCNONE
, {RT
}},
4853 {"mfesr", XSPR(31,339, 62), XSPR_MASK
, BOOKE
|PPCVLE
, PPCNONE
, {RT
}},
4854 {"mfivpr", XSPR(31,339, 63), XSPR_MASK
, BOOKE
|PPCVLE
, PPCNONE
, {RT
}},
4855 {"mfcmpa", XSPR(31,339,144), XSPR_MASK
, PPC860
, PPCNONE
, {RT
}},
4856 {"mfcmpb", XSPR(31,339,145), XSPR_MASK
, PPC860
, PPCNONE
, {RT
}},
4857 {"mfcmpc", XSPR(31,339,146), XSPR_MASK
, PPC860
, PPCNONE
, {RT
}},
4858 {"mfcmpd", XSPR(31,339,147), XSPR_MASK
, PPC860
, PPCNONE
, {RT
}},
4859 {"mficr", XSPR(31,339,148), XSPR_MASK
, PPC860
, PPCNONE
, {RT
}},
4860 {"mfder", XSPR(31,339,149), XSPR_MASK
, PPC860
, PPCNONE
, {RT
}},
4861 {"mfcounta", XSPR(31,339,150), XSPR_MASK
, PPC860
, PPCNONE
, {RT
}},
4862 {"mfcountb", XSPR(31,339,151), XSPR_MASK
, PPC860
, PPCNONE
, {RT
}},
4863 {"mfcmpe", XSPR(31,339,152), XSPR_MASK
, PPC860
, PPCNONE
, {RT
}},
4864 {"mfcmpf", XSPR(31,339,153), XSPR_MASK
, PPC860
, PPCNONE
, {RT
}},
4865 {"mfcmpg", XSPR(31,339,154), XSPR_MASK
, PPC860
, PPCNONE
, {RT
}},
4866 {"mfcmph", XSPR(31,339,155), XSPR_MASK
, PPC860
, PPCNONE
, {RT
}},
4867 {"mflctrl1", XSPR(31,339,156), XSPR_MASK
, PPC860
, PPCNONE
, {RT
}},
4868 {"mflctrl2", XSPR(31,339,157), XSPR_MASK
, PPC860
, PPCNONE
, {RT
}},
4869 {"mfictrl", XSPR(31,339,158), XSPR_MASK
, PPC860
, PPCNONE
, {RT
}},
4870 {"mfbar", XSPR(31,339,159), XSPR_MASK
, PPC860
, PPCNONE
, {RT
}},
4871 {"mfvrsave", XSPR(31,339,256), XSPR_MASK
, PPCVEC
, PPCNONE
, {RT
}},
4872 {"mfusprg0", XSPR(31,339,256), XSPR_MASK
, BOOKE
|PPCVLE
, PPCNONE
, {RT
}},
4873 {"mfsprg", XSPR(31,339,256), XSPRG_MASK
, PPC
|PPCVLE
, PPCNONE
, {RT
, SPRG
}},
4874 {"mfsprg4", XSPR(31,339,260), XSPR_MASK
, PPC405
|BOOKE
|PPCVLE
, PPCNONE
, {RT
}},
4875 {"mfsprg5", XSPR(31,339,261), XSPR_MASK
, PPC405
|BOOKE
|PPCVLE
, PPCNONE
, {RT
}},
4876 {"mfsprg6", XSPR(31,339,262), XSPR_MASK
, PPC405
|BOOKE
|PPCVLE
, PPCNONE
, {RT
}},
4877 {"mfsprg7", XSPR(31,339,263), XSPR_MASK
, PPC405
|BOOKE
|PPCVLE
, PPCNONE
, {RT
}},
4878 {"mftb", XSPR(31,339,268), XSPR_MASK
, BOOKE
|PPCVLE
, PPCNONE
, {RT
}},
4879 {"mftbl", XSPR(31,339,268), XSPR_MASK
, BOOKE
|PPCVLE
, PPCNONE
, {RT
}},
4880 {"mftbu", XSPR(31,339,269), XSPR_MASK
, BOOKE
|PPCVLE
, PPCNONE
, {RT
}},
4881 {"mfsprg0", XSPR(31,339,272), XSPR_MASK
, PPC
|PPCVLE
, PPCNONE
, {RT
}},
4882 {"mfsprg1", XSPR(31,339,273), XSPR_MASK
, PPC
|PPCVLE
, PPCNONE
, {RT
}},
4883 {"mfsprg2", XSPR(31,339,274), XSPR_MASK
, PPC
|PPCVLE
, PPCNONE
, {RT
}},
4884 {"mfsprg3", XSPR(31,339,275), XSPR_MASK
, PPC
|PPCVLE
, PPCNONE
, {RT
}},
4885 {"mfasr", XSPR(31,339,280), XSPR_MASK
, PPC64
, PPCNONE
, {RT
}},
4886 {"mfear", XSPR(31,339,282), XSPR_MASK
, PPC
, TITAN
, {RT
}},
4887 {"mfpir", XSPR(31,339,286), XSPR_MASK
, BOOKE
|PPCVLE
, PPCNONE
, {RT
}},
4888 {"mfpvr", XSPR(31,339,287), XSPR_MASK
, PPC
|PPCVLE
, PPCNONE
, {RT
}},
4889 {"mfdbsr", XSPR(31,339,304), XSPR_MASK
, BOOKE
|PPCVLE
, PPCNONE
, {RT
}},
4890 {"mfdbcr0", XSPR(31,339,308), XSPR_MASK
, BOOKE
|PPCVLE
, PPCNONE
, {RT
}},
4891 {"mfdbcr1", XSPR(31,339,309), XSPR_MASK
, BOOKE
|PPCVLE
, PPCNONE
, {RT
}},
4892 {"mfdbcr2", XSPR(31,339,310), XSPR_MASK
, BOOKE
|PPCVLE
, PPCNONE
, {RT
}},
4893 {"mfiac1", XSPR(31,339,312), XSPR_MASK
, BOOKE
|PPCVLE
, PPCNONE
, {RT
}},
4894 {"mfiac2", XSPR(31,339,313), XSPR_MASK
, BOOKE
|PPCVLE
, PPCNONE
, {RT
}},
4895 {"mfiac3", XSPR(31,339,314), XSPR_MASK
, BOOKE
|PPCVLE
, PPCNONE
, {RT
}},
4896 {"mfiac4", XSPR(31,339,315), XSPR_MASK
, BOOKE
|PPCVLE
, PPCNONE
, {RT
}},
4897 {"mfdac1", XSPR(31,339,316), XSPR_MASK
, BOOKE
|PPCVLE
, PPCNONE
, {RT
}},
4898 {"mfdac2", XSPR(31,339,317), XSPR_MASK
, BOOKE
|PPCVLE
, PPCNONE
, {RT
}},
4899 {"mfdvc1", XSPR(31,339,318), XSPR_MASK
, BOOKE
|PPCVLE
, PPCNONE
, {RT
}},
4900 {"mfdvc2", XSPR(31,339,319), XSPR_MASK
, BOOKE
|PPCVLE
, PPCNONE
, {RT
}},
4901 {"mftsr", XSPR(31,339,336), XSPR_MASK
, BOOKE
|PPCVLE
, PPCNONE
, {RT
}},
4902 {"mftcr", XSPR(31,339,340), XSPR_MASK
, BOOKE
|PPCVLE
, PPCNONE
, {RT
}},
4903 {"mfivor0", XSPR(31,339,400), XSPR_MASK
, BOOKE
|PPCVLE
, PPCNONE
, {RT
}},
4904 {"mfivor1", XSPR(31,339,401), XSPR_MASK
, BOOKE
|PPCVLE
, PPCNONE
, {RT
}},
4905 {"mfivor2", XSPR(31,339,402), XSPR_MASK
, BOOKE
|PPCVLE
, PPCNONE
, {RT
}},
4906 {"mfivor3", XSPR(31,339,403), XSPR_MASK
, BOOKE
|PPCVLE
, PPCNONE
, {RT
}},
4907 {"mfivor4", XSPR(31,339,404), XSPR_MASK
, BOOKE
|PPCVLE
, PPCNONE
, {RT
}},
4908 {"mfivor5", XSPR(31,339,405), XSPR_MASK
, BOOKE
|PPCVLE
, PPCNONE
, {RT
}},
4909 {"mfivor6", XSPR(31,339,406), XSPR_MASK
, BOOKE
|PPCVLE
, PPCNONE
, {RT
}},
4910 {"mfivor7", XSPR(31,339,407), XSPR_MASK
, BOOKE
|PPCVLE
, PPCNONE
, {RT
}},
4911 {"mfivor8", XSPR(31,339,408), XSPR_MASK
, BOOKE
|PPCVLE
, PPCNONE
, {RT
}},
4912 {"mfivor9", XSPR(31,339,409), XSPR_MASK
, BOOKE
|PPCVLE
, PPCNONE
, {RT
}},
4913 {"mfivor10", XSPR(31,339,410), XSPR_MASK
, BOOKE
|PPCVLE
, PPCNONE
, {RT
}},
4914 {"mfivor11", XSPR(31,339,411), XSPR_MASK
, BOOKE
|PPCVLE
, PPCNONE
, {RT
}},
4915 {"mfivor12", XSPR(31,339,412), XSPR_MASK
, BOOKE
|PPCVLE
, PPCNONE
, {RT
}},
4916 {"mfivor13", XSPR(31,339,413), XSPR_MASK
, BOOKE
|PPCVLE
, PPCNONE
, {RT
}},
4917 {"mfivor14", XSPR(31,339,414), XSPR_MASK
, BOOKE
|PPCVLE
, PPCNONE
, {RT
}},
4918 {"mfivor15", XSPR(31,339,415), XSPR_MASK
, BOOKE
|PPCVLE
, PPCNONE
, {RT
}},
4919 {"mfspefscr", XSPR(31,339,512), XSPR_MASK
, PPCSPE
, PPCNONE
, {RT
}},
4920 {"mfbbear", XSPR(31,339,513), XSPR_MASK
, PPCBRLK
, PPCNONE
, {RT
}},
4921 {"mfbbtar", XSPR(31,339,514), XSPR_MASK
, PPCBRLK
, PPCNONE
, {RT
}},
4922 {"mfivor32", XSPR(31,339,528), XSPR_MASK
, PPCSPE
, PPCNONE
, {RT
}},
4923 {"mfibatu", XSPR(31,339,528), XSPRBAT_MASK
, PPC
, TITAN
, {RT
, SPRBAT
}},
4924 {"mfivor33", XSPR(31,339,529), XSPR_MASK
, PPCSPE
, PPCNONE
, {RT
}},
4925 {"mfibatl", XSPR(31,339,529), XSPRBAT_MASK
, PPC
, TITAN
, {RT
, SPRBAT
}},
4926 {"mfivor34", XSPR(31,339,530), XSPR_MASK
, PPCSPE
, PPCNONE
, {RT
}},
4927 {"mfivor35", XSPR(31,339,531), XSPR_MASK
, PPCPMR
, PPCNONE
, {RT
}},
4928 {"mfdbatu", XSPR(31,339,536), XSPRBAT_MASK
, PPC
, TITAN
, {RT
, SPRBAT
}},
4929 {"mfdbatl", XSPR(31,339,537), XSPRBAT_MASK
, PPC
, TITAN
, {RT
, SPRBAT
}},
4930 {"mfic_cst", XSPR(31,339,560), XSPR_MASK
, PPC860
, PPCNONE
, {RT
}},
4931 {"mfic_adr", XSPR(31,339,561), XSPR_MASK
, PPC860
, PPCNONE
, {RT
}},
4932 {"mfic_dat", XSPR(31,339,562), XSPR_MASK
, PPC860
, PPCNONE
, {RT
}},
4933 {"mfdc_cst", XSPR(31,339,568), XSPR_MASK
, PPC860
, PPCNONE
, {RT
}},
4934 {"mfdc_adr", XSPR(31,339,569), XSPR_MASK
, PPC860
, PPCNONE
, {RT
}},
4935 {"mfdc_dat", XSPR(31,339,570), XSPR_MASK
, PPC860
, PPCNONE
, {RT
}},
4936 {"mfmcsrr0", XSPR(31,339,570), XSPR_MASK
, PPCRFMCI
, PPCNONE
, {RT
}},
4937 {"mfmcsrr1", XSPR(31,339,571), XSPR_MASK
, PPCRFMCI
, PPCNONE
, {RT
}},
4938 {"mfmcsr", XSPR(31,339,572), XSPR_MASK
, PPCRFMCI
, PPCNONE
, {RT
}},
4939 {"mfmcar", XSPR(31,339,573), XSPR_MASK
, PPCRFMCI
, TITAN
, {RT
}},
4940 {"mfdpdr", XSPR(31,339,630), XSPR_MASK
, PPC860
, PPCNONE
, {RT
}},
4941 {"mfdpir", XSPR(31,339,631), XSPR_MASK
, PPC860
, PPCNONE
, {RT
}},
4942 {"mfimmr", XSPR(31,339,638), XSPR_MASK
, PPC860
, PPCNONE
, {RT
}},
4943 {"mfmi_ctr", XSPR(31,339,784), XSPR_MASK
, PPC860
, PPCNONE
, {RT
}},
4944 {"mfmi_ap", XSPR(31,339,786), XSPR_MASK
, PPC860
, PPCNONE
, {RT
}},
4945 {"mfmi_epn", XSPR(31,339,787), XSPR_MASK
, PPC860
, PPCNONE
, {RT
}},
4946 {"mfmi_twc", XSPR(31,339,789), XSPR_MASK
, PPC860
, PPCNONE
, {RT
}},
4947 {"mfmi_rpn", XSPR(31,339,790), XSPR_MASK
, PPC860
, PPCNONE
, {RT
}},
4948 {"mfmd_ctr", XSPR(31,339,792), XSPR_MASK
, PPC860
, PPCNONE
, {RT
}},
4949 {"mfm_casid", XSPR(31,339,793), XSPR_MASK
, PPC860
, PPCNONE
, {RT
}},
4950 {"mfmd_ap", XSPR(31,339,794), XSPR_MASK
, PPC860
, PPCNONE
, {RT
}},
4951 {"mfmd_epn", XSPR(31,339,795), XSPR_MASK
, PPC860
, PPCNONE
, {RT
}},
4952 {"mfmd_twb", XSPR(31,339,796), XSPR_MASK
, PPC860
, PPCNONE
, {RT
}},
4953 {"mfmd_twc", XSPR(31,339,797), XSPR_MASK
, PPC860
, PPCNONE
, {RT
}},
4954 {"mfmd_rpn", XSPR(31,339,798), XSPR_MASK
, PPC860
, PPCNONE
, {RT
}},
4955 {"mfm_tw", XSPR(31,339,799), XSPR_MASK
, PPC860
, PPCNONE
, {RT
}},
4956 {"mfmi_dbcam", XSPR(31,339,816), XSPR_MASK
, PPC860
, PPCNONE
, {RT
}},
4957 {"mfmi_dbram0", XSPR(31,339,817), XSPR_MASK
, PPC860
, PPCNONE
, {RT
}},
4958 {"mfmi_dbram1", XSPR(31,339,818), XSPR_MASK
, PPC860
, PPCNONE
, {RT
}},
4959 {"mfmd_dbcam", XSPR(31,339,824), XSPR_MASK
, PPC860
, PPCNONE
, {RT
}},
4960 {"mfmd_dbram0", XSPR(31,339,825), XSPR_MASK
, PPC860
, PPCNONE
, {RT
}},
4961 {"mfmd_dbram1", XSPR(31,339,826), XSPR_MASK
, PPC860
, PPCNONE
, {RT
}},
4962 {"mfivndx", XSPR(31,339,880), XSPR_MASK
, TITAN
, PPCNONE
, {RT
}},
4963 {"mfdvndx", XSPR(31,339,881), XSPR_MASK
, TITAN
, PPCNONE
, {RT
}},
4964 {"mfivlim", XSPR(31,339,882), XSPR_MASK
, TITAN
, PPCNONE
, {RT
}},
4965 {"mfdvlim", XSPR(31,339,883), XSPR_MASK
, TITAN
, PPCNONE
, {RT
}},
4966 {"mfclcsr", XSPR(31,339,884), XSPR_MASK
, TITAN
, PPCNONE
, {RT
}},
4967 {"mfccr1", XSPR(31,339,888), XSPR_MASK
, TITAN
, PPCNONE
, {RT
}},
4968 {"mfppr", XSPR(31,339,896), XSPR_MASK
, POWER7
, PPCNONE
, {RT
}},
4969 {"mfppr32", XSPR(31,339,898), XSPR_MASK
, POWER7
, PPCNONE
, {RT
}},
4970 {"mfrstcfg", XSPR(31,339,923), XSPR_MASK
, TITAN
, PPCNONE
, {RT
}},
4971 {"mfdcdbtrl", XSPR(31,339,924), XSPR_MASK
, TITAN
, PPCNONE
, {RT
}},
4972 {"mfdcdbtrh", XSPR(31,339,925), XSPR_MASK
, TITAN
, PPCNONE
, {RT
}},
4973 {"mficdbtr", XSPR(31,339,927), XSPR_MASK
, TITAN
, PPCNONE
, {RT
}},
4974 {"mfummcr0", XSPR(31,339,936), XSPR_MASK
, PPC750
, PPCNONE
, {RT
}},
4975 {"mfupmc1", XSPR(31,339,937), XSPR_MASK
, PPC750
, PPCNONE
, {RT
}},
4976 {"mfupmc2", XSPR(31,339,938), XSPR_MASK
, PPC750
, PPCNONE
, {RT
}},
4977 {"mfusia", XSPR(31,339,939), XSPR_MASK
, PPC750
, PPCNONE
, {RT
}},
4978 {"mfummcr1", XSPR(31,339,940), XSPR_MASK
, PPC750
, PPCNONE
, {RT
}},
4979 {"mfupmc3", XSPR(31,339,941), XSPR_MASK
, PPC750
, PPCNONE
, {RT
}},
4980 {"mfupmc4", XSPR(31,339,942), XSPR_MASK
, PPC750
, PPCNONE
, {RT
}},
4981 {"mfzpr", XSPR(31,339,944), XSPR_MASK
, PPC403
, PPCNONE
, {RT
}},
4982 {"mfpid", XSPR(31,339,945), XSPR_MASK
, PPC403
, PPCNONE
, {RT
}},
4983 {"mfmmucr", XSPR(31,339,946), XSPR_MASK
, TITAN
, PPCNONE
, {RT
}},
4984 {"mfccr0", XSPR(31,339,947), XSPR_MASK
, PPC405
|TITAN
, PPCNONE
, {RT
}},
4985 {"mfiac3", XSPR(31,339,948), XSPR_MASK
, PPC405
, PPCNONE
, {RT
}},
4986 {"mfiac4", XSPR(31,339,949), XSPR_MASK
, PPC405
, PPCNONE
, {RT
}},
4987 {"mfdvc1", XSPR(31,339,950), XSPR_MASK
, PPC405
, PPCNONE
, {RT
}},
4988 {"mfdvc2", XSPR(31,339,951), XSPR_MASK
, PPC405
, PPCNONE
, {RT
}},
4989 {"mfmmcr0", XSPR(31,339,952), XSPR_MASK
, PPC750
, PPCNONE
, {RT
}},
4990 {"mfpmc1", XSPR(31,339,953), XSPR_MASK
, PPC750
, PPCNONE
, {RT
}},
4991 {"mfsgr", XSPR(31,339,953), XSPR_MASK
, PPC403
, PPCNONE
, {RT
}},
4992 {"mfdcwr", XSPR(31,339,954), XSPR_MASK
, PPC403
, PPCNONE
, {RT
}},
4993 {"mfpmc2", XSPR(31,339,954), XSPR_MASK
, PPC750
, PPCNONE
, {RT
}},
4994 {"mfsia", XSPR(31,339,955), XSPR_MASK
, PPC750
, PPCNONE
, {RT
}},
4995 {"mfsler", XSPR(31,339,955), XSPR_MASK
, PPC405
, PPCNONE
, {RT
}},
4996 {"mfmmcr1", XSPR(31,339,956), XSPR_MASK
, PPC750
, PPCNONE
, {RT
}},
4997 {"mfsu0r", XSPR(31,339,956), XSPR_MASK
, PPC405
, PPCNONE
, {RT
}},
4998 {"mfdbcr1", XSPR(31,339,957), XSPR_MASK
, PPC405
, PPCNONE
, {RT
}},
4999 {"mfpmc3", XSPR(31,339,957), XSPR_MASK
, PPC750
, PPCNONE
, {RT
}},
5000 {"mfpmc4", XSPR(31,339,958), XSPR_MASK
, PPC750
, PPCNONE
, {RT
}},
5001 {"mficdbdr", XSPR(31,339,979), XSPR_MASK
, PPC403
|TITAN
, PPCNONE
, {RT
}},
5002 {"mfesr", XSPR(31,339,980), XSPR_MASK
, PPC403
, PPCNONE
, {RT
}},
5003 {"mfdear", XSPR(31,339,981), XSPR_MASK
, PPC403
, PPCNONE
, {RT
}},
5004 {"mfevpr", XSPR(31,339,982), XSPR_MASK
, PPC403
, PPCNONE
, {RT
}},
5005 {"mfcdbcr", XSPR(31,339,983), XSPR_MASK
, PPC403
, PPCNONE
, {RT
}},
5006 {"mftsr", XSPR(31,339,984), XSPR_MASK
, PPC403
, PPCNONE
, {RT
}},
5007 {"mftcr", XSPR(31,339,986), XSPR_MASK
, PPC403
, PPCNONE
, {RT
}},
5008 {"mfpit", XSPR(31,339,987), XSPR_MASK
, PPC403
, PPCNONE
, {RT
}},
5009 {"mftbhi", XSPR(31,339,988), XSPR_MASK
, PPC403
, PPCNONE
, {RT
}},
5010 {"mftblo", XSPR(31,339,989), XSPR_MASK
, PPC403
, PPCNONE
, {RT
}},
5011 {"mfsrr2", XSPR(31,339,990), XSPR_MASK
, PPC403
, PPCNONE
, {RT
}},
5012 {"mfsrr3", XSPR(31,339,991), XSPR_MASK
, PPC403
, PPCNONE
, {RT
}},
5013 {"mfdbsr", XSPR(31,339,1008), XSPR_MASK
, PPC403
, PPCNONE
, {RT
}},
5014 {"mfdbcr0", XSPR(31,339,1010), XSPR_MASK
, PPC405
, PPCNONE
, {RT
}},
5015 {"mfdbdr", XSPR(31,339,1011), XSPR_MASK
, TITAN
, PPCNONE
, {RS
}},
5016 {"mfiac1", XSPR(31,339,1012), XSPR_MASK
, PPC403
, PPCNONE
, {RT
}},
5017 {"mfiac2", XSPR(31,339,1013), XSPR_MASK
, PPC403
, PPCNONE
, {RT
}},
5018 {"mfdac1", XSPR(31,339,1014), XSPR_MASK
, PPC403
, PPCNONE
, {RT
}},
5019 {"mfdac2", XSPR(31,339,1015), XSPR_MASK
, PPC403
, PPCNONE
, {RT
}},
5020 {"mfl2cr", XSPR(31,339,1017), XSPR_MASK
, PPC750
, PPCNONE
, {RT
}},
5021 {"mfdccr", XSPR(31,339,1018), XSPR_MASK
, PPC403
, PPCNONE
, {RT
}},
5022 {"mficcr", XSPR(31,339,1019), XSPR_MASK
, PPC403
, PPCNONE
, {RT
}},
5023 {"mfictc", XSPR(31,339,1019), XSPR_MASK
, PPC750
, PPCNONE
, {RT
}},
5024 {"mfpbl1", XSPR(31,339,1020), XSPR_MASK
, PPC403
, PPCNONE
, {RT
}},
5025 {"mfthrm1", XSPR(31,339,1020), XSPR_MASK
, PPC750
, PPCNONE
, {RT
}},
5026 {"mfpbu1", XSPR(31,339,1021), XSPR_MASK
, PPC403
, PPCNONE
, {RT
}},
5027 {"mfthrm2", XSPR(31,339,1021), XSPR_MASK
, PPC750
, PPCNONE
, {RT
}},
5028 {"mfpbl2", XSPR(31,339,1022), XSPR_MASK
, PPC403
, PPCNONE
, {RT
}},
5029 {"mfthrm3", XSPR(31,339,1022), XSPR_MASK
, PPC750
, PPCNONE
, {RT
}},
5030 {"mfpbu2", XSPR(31,339,1023), XSPR_MASK
, PPC403
, PPCNONE
, {RT
}},
5031 {"mfspr", X(31,339), X_MASK
, COM
|PPCVLE
, PPCNONE
, {RT
, SPR
}},
5033 {"lwax", X(31,341), X_MASK
, PPC64
|PPCVLE
, PPCNONE
, {RT
, RA0
, RB
}},
5035 {"dst", XDSS(31,342,0), XDSS_MASK
, PPCVEC
, PPCNONE
, {RA
, RB
, STRM
}},
5037 {"lhax", X(31,343), X_MASK
, COM
|PPCVLE
, PPCNONE
, {RT
, RA0
, RB
}},
5039 {"lvxl", X(31,359), X_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, RA0
, RB
}},
5041 {"abs", XO(31,360,0,0), XORB_MASK
, M601
, PPCNONE
, {RT
, RA
}},
5042 {"abs.", XO(31,360,0,1), XORB_MASK
, M601
, PPCNONE
, {RT
, RA
}},
5044 {"divs", XO(31,363,0,0), XO_MASK
, M601
, PPCNONE
, {RT
, RA
, RB
}},
5045 {"divs.", XO(31,363,0,1), XO_MASK
, M601
, PPCNONE
, {RT
, RA
, RB
}},
5047 {"tlbia", X(31,370), 0xffffffff, PPC
, TITAN
, {0}},
5049 {"mftbl", XSPR(31,371,268), XSPR_MASK
, PPC
, NO371
, {RT
}},
5050 {"mftbu", XSPR(31,371,269), XSPR_MASK
, PPC
, NO371
, {RT
}},
5051 {"mftb", X(31,371), X_MASK
, PPC
|PPCA2
, NO371
|POWER7
, {RT
, TBR
}},
5053 {"lwaux", X(31,373), X_MASK
, PPC64
|PPCVLE
, PPCNONE
, {RT
, RAL
, RB
}},
5055 {"dstst", XDSS(31,374,0), XDSS_MASK
, PPCVEC
, PPCNONE
, {RA
, RB
, STRM
}},
5057 {"lhaux", X(31,375), X_MASK
, COM
|PPCVLE
, PPCNONE
, {RT
, RAL
, RB
}},
5059 {"popcntw", X(31,378), XRB_MASK
, POWER7
|PPCA2
, PPCNONE
, {RA
, RS
}},
5061 {"mtdcrx", X(31,387), X_MASK
, BOOKE
|PPCA2
|PPC476
|PPCVLE
, TITAN
, {RA
, RS
}},
5062 {"mtdcrx.", XRC(31,387,1), X_MASK
, PPCA2
, PPCNONE
, {RA
, RS
}},
5064 {"stvexbx", X(31,389), X_MASK
, PPCVEC2
, PPCNONE
, {VS
, RA0
, RB
}},
5066 {"dcblc", X(31,390), X_MASK
, PPCCHLK
|PPC476
|TITAN
|PPCVLE
, PPCNONE
, {CT
, RA0
, RB
}},
5067 {"stdfcmx", APU(31,391,0), APU_MASK
, PPC405
, PPCNONE
, {FCRT
, RA
, RB
}},
5069 {"divdeu", XO(31,393,0,0), XO_MASK
, POWER7
|PPCA2
, PPCNONE
, {RT
, RA
, RB
}},
5070 {"divdeu.", XO(31,393,0,1), XO_MASK
, POWER7
|PPCA2
, PPCNONE
, {RT
, RA
, RB
}},
5071 {"divweu", XO(31,395,0,0), XO_MASK
, POWER7
|PPCA2
, PPCNONE
, {RT
, RA
, RB
}},
5072 {"divweu.", XO(31,395,0,1), XO_MASK
, POWER7
|PPCA2
, PPCNONE
, {RT
, RA
, RB
}},
5074 {"dcblce", X(31,398), X_MASK
, PPCCHLK
, E500MC
, {CT
, RA
, RB
}},
5076 {"slbmte", X(31,402), XRA_MASK
, PPC64
, PPCNONE
, {RS
, RB
}},
5078 {"pbt.", XRC(31,404,1), X_MASK
, POWER8
, PPCNONE
, {RS
, RA0
, RB
}},
5080 {"icswx", XRC(31,406,0), X_MASK
, POWER7
|PPCA2
, PPCNONE
, {RS
, RA
, RB
}},
5081 {"icswx.", XRC(31,406,1), X_MASK
, POWER7
|PPCA2
, PPCNONE
, {RS
, RA
, RB
}},
5083 {"sthx", X(31,407), X_MASK
, COM
|PPCVLE
, PPCNONE
, {RS
, RA0
, RB
}},
5085 {"orc", XRC(31,412,0), X_MASK
, COM
|PPCVLE
, PPCNONE
, {RA
, RS
, RB
}},
5086 {"orc.", XRC(31,412,1), X_MASK
, COM
|PPCVLE
, PPCNONE
, {RA
, RS
, RB
}},
5088 {"sthepx", X(31,415), X_MASK
, E500MC
|PPCA2
|PPCVLE
, PPCNONE
, {RS
, RA0
, RB
}},
5090 {"mtdcrux", X(31,419), X_MASK
, PPC464
|PPCVLE
, PPCNONE
, {RA
, RS
}},
5092 {"stvexhx", X(31,421), X_MASK
, PPCVEC2
, PPCNONE
, {VS
, RA0
, RB
}},
5094 {"dcblq.", XRC(31,422,1), X_MASK
, E6500
, PPCNONE
, {CT
, RA0
, RB
}},
5096 {"divde", XO(31,425,0,0), XO_MASK
, POWER7
|PPCA2
, PPCNONE
, {RT
, RA
, RB
}},
5097 {"divde.", XO(31,425,0,1), XO_MASK
, POWER7
|PPCA2
, PPCNONE
, {RT
, RA
, RB
}},
5098 {"divwe", XO(31,427,0,0), XO_MASK
, POWER7
|PPCA2
, PPCNONE
, {RT
, RA
, RB
}},
5099 {"divwe.", XO(31,427,0,1), XO_MASK
, POWER7
|PPCA2
, PPCNONE
, {RT
, RA
, RB
}},
5101 {"clrbhrb", X(31,430), 0xffffffff, POWER8
, PPCNONE
, {0}},
5103 {"slbie", X(31,434), XRTRA_MASK
, PPC64
, PPCNONE
, {RB
}},
5105 {"ecowx", X(31,438), X_MASK
, PPC
, TITAN
, {RT
, RA0
, RB
}},
5107 {"sthux", X(31,439), X_MASK
, COM
|PPCVLE
, PPCNONE
, {RS
, RAS
, RB
}},
5109 {"mdors", 0x7f9ce378, 0xffffffff, E500MC
, PPCNONE
, {0}},
5111 {"miso", 0x7f5ad378, 0xffffffff, E6500
, PPCNONE
, {0}},
5113 /* The "yield", "mdoio" and "mdoom" instructions are extended mnemonics for
5114 "or rX,rX,rX", with rX being r27, r29 and r30 respectively. */
5115 {"yield", 0x7f7bdb78, 0xffffffff, POWER7
, PPCNONE
, {0}},
5116 {"mdoio", 0x7fbdeb78, 0xffffffff, POWER7
, PPCNONE
, {0}},
5117 {"mdoom", 0x7fdef378, 0xffffffff, POWER7
, PPCNONE
, {0}},
5118 {"mr", XRC(31,444,0), X_MASK
, COM
|PPCVLE
, PPCNONE
, {RA
, RS
, RBS
}},
5119 {"or", XRC(31,444,0), X_MASK
, COM
|PPCVLE
, PPCNONE
, {RA
, RS
, RB
}},
5120 {"mr.", XRC(31,444,1), X_MASK
, COM
|PPCVLE
, PPCNONE
, {RA
, RS
, RBS
}},
5121 {"or.", XRC(31,444,1), X_MASK
, COM
|PPCVLE
, PPCNONE
, {RA
, RS
, RB
}},
5123 {"mtexisr", XSPR(31,451, 64), XSPR_MASK
, PPC403
, PPCNONE
, {RS
}},
5124 {"mtexier", XSPR(31,451, 66), XSPR_MASK
, PPC403
, PPCNONE
, {RS
}},
5125 {"mtbr0", XSPR(31,451,128), XSPR_MASK
, PPC403
, PPCNONE
, {RS
}},
5126 {"mtbr1", XSPR(31,451,129), XSPR_MASK
, PPC403
, PPCNONE
, {RS
}},
5127 {"mtbr2", XSPR(31,451,130), XSPR_MASK
, PPC403
, PPCNONE
, {RS
}},
5128 {"mtbr3", XSPR(31,451,131), XSPR_MASK
, PPC403
, PPCNONE
, {RS
}},
5129 {"mtbr4", XSPR(31,451,132), XSPR_MASK
, PPC403
, PPCNONE
, {RS
}},
5130 {"mtbr5", XSPR(31,451,133), XSPR_MASK
, PPC403
, PPCNONE
, {RS
}},
5131 {"mtbr6", XSPR(31,451,134), XSPR_MASK
, PPC403
, PPCNONE
, {RS
}},
5132 {"mtbr7", XSPR(31,451,135), XSPR_MASK
, PPC403
, PPCNONE
, {RS
}},
5133 {"mtbear", XSPR(31,451,144), XSPR_MASK
, PPC403
, PPCNONE
, {RS
}},
5134 {"mtbesr", XSPR(31,451,145), XSPR_MASK
, PPC403
, PPCNONE
, {RS
}},
5135 {"mtiocr", XSPR(31,451,160), XSPR_MASK
, PPC403
, PPCNONE
, {RS
}},
5136 {"mtdmacr0", XSPR(31,451,192), XSPR_MASK
, PPC403
, PPCNONE
, {RS
}},
5137 {"mtdmact0", XSPR(31,451,193), XSPR_MASK
, PPC403
, PPCNONE
, {RS
}},
5138 {"mtdmada0", XSPR(31,451,194), XSPR_MASK
, PPC403
, PPCNONE
, {RS
}},
5139 {"mtdmasa0", XSPR(31,451,195), XSPR_MASK
, PPC403
, PPCNONE
, {RS
}},
5140 {"mtdmacc0", XSPR(31,451,196), XSPR_MASK
, PPC403
, PPCNONE
, {RS
}},
5141 {"mtdmacr1", XSPR(31,451,200), XSPR_MASK
, PPC403
, PPCNONE
, {RS
}},
5142 {"mtdmact1", XSPR(31,451,201), XSPR_MASK
, PPC403
, PPCNONE
, {RS
}},
5143 {"mtdmada1", XSPR(31,451,202), XSPR_MASK
, PPC403
, PPCNONE
, {RS
}},
5144 {"mtdmasa1", XSPR(31,451,203), XSPR_MASK
, PPC403
, PPCNONE
, {RS
}},
5145 {"mtdmacc1", XSPR(31,451,204), XSPR_MASK
, PPC403
, PPCNONE
, {RS
}},
5146 {"mtdmacr2", XSPR(31,451,208), XSPR_MASK
, PPC403
, PPCNONE
, {RS
}},
5147 {"mtdmact2", XSPR(31,451,209), XSPR_MASK
, PPC403
, PPCNONE
, {RS
}},
5148 {"mtdmada2", XSPR(31,451,210), XSPR_MASK
, PPC403
, PPCNONE
, {RS
}},
5149 {"mtdmasa2", XSPR(31,451,211), XSPR_MASK
, PPC403
, PPCNONE
, {RS
}},
5150 {"mtdmacc2", XSPR(31,451,212), XSPR_MASK
, PPC403
, PPCNONE
, {RS
}},
5151 {"mtdmacr3", XSPR(31,451,216), XSPR_MASK
, PPC403
, PPCNONE
, {RS
}},
5152 {"mtdmact3", XSPR(31,451,217), XSPR_MASK
, PPC403
, PPCNONE
, {RS
}},
5153 {"mtdmada3", XSPR(31,451,218), XSPR_MASK
, PPC403
, PPCNONE
, {RS
}},
5154 {"mtdmasa3", XSPR(31,451,219), XSPR_MASK
, PPC403
, PPCNONE
, {RS
}},
5155 {"mtdmacc3", XSPR(31,451,220), XSPR_MASK
, PPC403
, PPCNONE
, {RS
}},
5156 {"mtdmasr", XSPR(31,451,224), XSPR_MASK
, PPC403
, PPCNONE
, {RS
}},
5157 {"mtdcr", X(31,451), X_MASK
, PPC403
|BOOKE
|PPCA2
|PPC476
|PPCVLE
, TITAN
, {SPR
, RS
}},
5158 {"mtdcr.", XRC(31,451,1), X_MASK
, PPCA2
, PPCNONE
, {SPR
, RS
}},
5160 {"stvexwx", X(31,453), X_MASK
, PPCVEC2
, PPCNONE
, {VS
, RA0
, RB
}},
5162 {"dccci", X(31,454), XRT_MASK
, PPC403
|PPC440
|TITAN
|PPCA2
, PPCNONE
, {RAOPT
, RBOPT
}},
5163 {"dci", X(31,454), XRARB_MASK
, PPCA2
|PPC476
|PPCVLE
, PPCNONE
, {CT
}},
5165 {"divdu", XO(31,457,0,0), XO_MASK
, PPC64
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
5166 {"divdu.", XO(31,457,0,1), XO_MASK
, PPC64
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
5168 {"divwu", XO(31,459,0,0), XO_MASK
, PPC
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
5169 {"divwu.", XO(31,459,0,1), XO_MASK
, PPC
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
5171 {"mtpmr", X(31,462), X_MASK
, PPCPMR
|PPCE300
|PPCVLE
, PPCNONE
, {PMR
, RS
}},
5172 {"mttmr", X(31,494), X_MASK
, PPCTMR
|E6500
, PPCNONE
, {TMR
, RS
}},
5174 {"mtmq", XSPR(31,467, 0), XSPR_MASK
, M601
, PPCNONE
, {RS
}},
5175 {"mtxer", XSPR(31,467, 1), XSPR_MASK
, COM
|PPCVLE
, PPCNONE
, {RS
}},
5176 {"mtlr", XSPR(31,467, 8), XSPR_MASK
, COM
|PPCVLE
, PPCNONE
, {RS
}},
5177 {"mtctr", XSPR(31,467, 9), XSPR_MASK
, COM
|PPCVLE
, PPCNONE
, {RS
}},
5178 {"mttid", XSPR(31,467, 17), XSPR_MASK
, POWER
, PPCNONE
, {RS
}},
5179 {"mtdsisr", XSPR(31,467, 18), XSPR_MASK
, COM
, TITAN
, {RS
}},
5180 {"mtdar", XSPR(31,467, 19), XSPR_MASK
, COM
, TITAN
, {RS
}},
5181 {"mtrtcu", XSPR(31,467, 20), XSPR_MASK
, COM
, TITAN
, {RS
}},
5182 {"mtrtcl", XSPR(31,467, 21), XSPR_MASK
, COM
, TITAN
, {RS
}},
5183 {"mtdec", XSPR(31,467, 22), XSPR_MASK
, COM
, PPCNONE
, {RS
}},
5184 {"mtsdr0", XSPR(31,467, 24), XSPR_MASK
, POWER
, PPCNONE
, {RS
}},
5185 {"mtsdr1", XSPR(31,467, 25), XSPR_MASK
, COM
, TITAN
, {RS
}},
5186 {"mtsrr0", XSPR(31,467, 26), XSPR_MASK
, COM
|PPCVLE
, PPCNONE
, {RS
}},
5187 {"mtsrr1", XSPR(31,467, 27), XSPR_MASK
, COM
|PPCVLE
, PPCNONE
, {RS
}},
5188 {"mtcfar", XSPR(31,467, 28), XSPR_MASK
, POWER6
, PPCNONE
, {RS
}},
5189 {"mtpid", XSPR(31,467, 48), XSPR_MASK
, BOOKE
|PPCVLE
, PPCNONE
, {RS
}},
5190 {"mtdecar", XSPR(31,467, 54), XSPR_MASK
, BOOKE
|PPCVLE
, PPCNONE
, {RS
}},
5191 {"mtcsrr0", XSPR(31,467, 58), XSPR_MASK
, BOOKE
|PPCVLE
, PPCNONE
, {RS
}},
5192 {"mtcsrr1", XSPR(31,467, 59), XSPR_MASK
, BOOKE
|PPCVLE
, PPCNONE
, {RS
}},
5193 {"mtdear", XSPR(31,467, 61), XSPR_MASK
, BOOKE
|PPCVLE
, PPCNONE
, {RS
}},
5194 {"mtesr", XSPR(31,467, 62), XSPR_MASK
, BOOKE
|PPCVLE
, PPCNONE
, {RS
}},
5195 {"mtivpr", XSPR(31,467, 63), XSPR_MASK
, BOOKE
|PPCVLE
, PPCNONE
, {RS
}},
5196 {"mtcmpa", XSPR(31,467,144), XSPR_MASK
, PPC860
, PPCNONE
, {RS
}},
5197 {"mtcmpb", XSPR(31,467,145), XSPR_MASK
, PPC860
, PPCNONE
, {RS
}},
5198 {"mtcmpc", XSPR(31,467,146), XSPR_MASK
, PPC860
, PPCNONE
, {RS
}},
5199 {"mtcmpd", XSPR(31,467,147), XSPR_MASK
, PPC860
, PPCNONE
, {RS
}},
5200 {"mticr", XSPR(31,467,148), XSPR_MASK
, PPC860
, PPCNONE
, {RS
}},
5201 {"mtder", XSPR(31,467,149), XSPR_MASK
, PPC860
, PPCNONE
, {RS
}},
5202 {"mtcounta", XSPR(31,467,150), XSPR_MASK
, PPC860
, PPCNONE
, {RS
}},
5203 {"mtcountb", XSPR(31,467,151), XSPR_MASK
, PPC860
, PPCNONE
, {RS
}},
5204 {"mtcmpe", XSPR(31,467,152), XSPR_MASK
, PPC860
, PPCNONE
, {RS
}},
5205 {"mtcmpf", XSPR(31,467,153), XSPR_MASK
, PPC860
, PPCNONE
, {RS
}},
5206 {"mtcmpg", XSPR(31,467,154), XSPR_MASK
, PPC860
, PPCNONE
, {RS
}},
5207 {"mtcmph", XSPR(31,467,155), XSPR_MASK
, PPC860
, PPCNONE
, {RS
}},
5208 {"mtlctrl1", XSPR(31,467,156), XSPR_MASK
, PPC860
, PPCNONE
, {RS
}},
5209 {"mtlctrl2", XSPR(31,467,157), XSPR_MASK
, PPC860
, PPCNONE
, {RS
}},
5210 {"mtictrl", XSPR(31,467,158), XSPR_MASK
, PPC860
, PPCNONE
, {RS
}},
5211 {"mtbar", XSPR(31,467,159), XSPR_MASK
, PPC860
, PPCNONE
, {RS
}},
5212 {"mtvrsave", XSPR(31,467,256), XSPR_MASK
, PPCVEC
, PPCNONE
, {RS
}},
5213 {"mtusprg0", XSPR(31,467,256), XSPR_MASK
, BOOKE
|PPCVLE
, PPCNONE
, {RS
}},
5214 {"mtsprg", XSPR(31,467,256), XSPRG_MASK
, PPC
|PPCVLE
, PPCNONE
, {SPRG
, RS
}},
5215 {"mtsprg0", XSPR(31,467,272), XSPR_MASK
, PPC
|PPCVLE
, PPCNONE
, {RS
}},
5216 {"mtsprg1", XSPR(31,467,273), XSPR_MASK
, PPC
|PPCVLE
, PPCNONE
, {RS
}},
5217 {"mtsprg2", XSPR(31,467,274), XSPR_MASK
, PPC
|PPCVLE
, PPCNONE
, {RS
}},
5218 {"mtsprg3", XSPR(31,467,275), XSPR_MASK
, PPC
|PPCVLE
, PPCNONE
, {RS
}},
5219 {"mtsprg4", XSPR(31,467,276), XSPR_MASK
, PPC405
|BOOKE
|PPCVLE
, PPCNONE
, {RS
}},
5220 {"mtsprg5", XSPR(31,467,277), XSPR_MASK
, PPC405
|BOOKE
|PPCVLE
, PPCNONE
, {RS
}},
5221 {"mtsprg6", XSPR(31,467,278), XSPR_MASK
, PPC405
|BOOKE
|PPCVLE
, PPCNONE
, {RS
}},
5222 {"mtsprg7", XSPR(31,467,279), XSPR_MASK
, PPC405
|BOOKE
|PPCVLE
, PPCNONE
, {RS
}},
5223 {"mtasr", XSPR(31,467,280), XSPR_MASK
, PPC64
, PPCNONE
, {RS
}},
5224 {"mtear", XSPR(31,467,282), XSPR_MASK
, PPC
, TITAN
, {RS
}},
5225 {"mttbl", XSPR(31,467,284), XSPR_MASK
, PPC
, PPCNONE
, {RS
}},
5226 {"mttbu", XSPR(31,467,285), XSPR_MASK
, PPC
, PPCNONE
, {RS
}},
5227 {"mtdbsr", XSPR(31,467,304), XSPR_MASK
, BOOKE
|PPCVLE
, PPCNONE
, {RS
}},
5228 {"mtdbcr0", XSPR(31,467,308), XSPR_MASK
, BOOKE
|PPCVLE
, PPCNONE
, {RS
}},
5229 {"mtdbcr1", XSPR(31,467,309), XSPR_MASK
, BOOKE
|PPCVLE
, PPCNONE
, {RS
}},
5230 {"mtdbcr2", XSPR(31,467,310), XSPR_MASK
, BOOKE
|PPCVLE
, PPCNONE
, {RS
}},
5231 {"mtiac1", XSPR(31,467,312), XSPR_MASK
, BOOKE
|PPCVLE
, PPCNONE
, {RS
}},
5232 {"mtiac2", XSPR(31,467,313), XSPR_MASK
, BOOKE
|PPCVLE
, PPCNONE
, {RS
}},
5233 {"mtiac3", XSPR(31,467,314), XSPR_MASK
, BOOKE
|PPCVLE
, PPCNONE
, {RS
}},
5234 {"mtiac4", XSPR(31,467,315), XSPR_MASK
, BOOKE
|PPCVLE
, PPCNONE
, {RS
}},
5235 {"mtdac1", XSPR(31,467,316), XSPR_MASK
, BOOKE
|PPCVLE
, PPCNONE
, {RS
}},
5236 {"mtdac2", XSPR(31,467,317), XSPR_MASK
, BOOKE
|PPCVLE
, PPCNONE
, {RS
}},
5237 {"mtdvc1", XSPR(31,467,318), XSPR_MASK
, BOOKE
|PPCVLE
, PPCNONE
, {RS
}},
5238 {"mtdvc2", XSPR(31,467,319), XSPR_MASK
, BOOKE
|PPCVLE
, PPCNONE
, {RS
}},
5239 {"mttsr", XSPR(31,467,336), XSPR_MASK
, BOOKE
|PPCVLE
, PPCNONE
, {RS
}},
5240 {"mttcr", XSPR(31,467,340), XSPR_MASK
, BOOKE
|PPCVLE
, PPCNONE
, {RS
}},
5241 {"mtivor0", XSPR(31,467,400), XSPR_MASK
, BOOKE
|PPCVLE
, PPCNONE
, {RS
}},
5242 {"mtivor1", XSPR(31,467,401), XSPR_MASK
, BOOKE
|PPCVLE
, PPCNONE
, {RS
}},
5243 {"mtivor2", XSPR(31,467,402), XSPR_MASK
, BOOKE
|PPCVLE
, PPCNONE
, {RS
}},
5244 {"mtivor3", XSPR(31,467,403), XSPR_MASK
, BOOKE
|PPCVLE
, PPCNONE
, {RS
}},
5245 {"mtivor4", XSPR(31,467,404), XSPR_MASK
, BOOKE
|PPCVLE
, PPCNONE
, {RS
}},
5246 {"mtivor5", XSPR(31,467,405), XSPR_MASK
, BOOKE
|PPCVLE
, PPCNONE
, {RS
}},
5247 {"mtivor6", XSPR(31,467,406), XSPR_MASK
, BOOKE
|PPCVLE
, PPCNONE
, {RS
}},
5248 {"mtivor7", XSPR(31,467,407), XSPR_MASK
, BOOKE
|PPCVLE
, PPCNONE
, {RS
}},
5249 {"mtivor8", XSPR(31,467,408), XSPR_MASK
, BOOKE
|PPCVLE
, PPCNONE
, {RS
}},
5250 {"mtivor9", XSPR(31,467,409), XSPR_MASK
, BOOKE
|PPCVLE
, PPCNONE
, {RS
}},
5251 {"mtivor10", XSPR(31,467,410), XSPR_MASK
, BOOKE
|PPCVLE
, PPCNONE
, {RS
}},
5252 {"mtivor11", XSPR(31,467,411), XSPR_MASK
, BOOKE
|PPCVLE
, PPCNONE
, {RS
}},
5253 {"mtivor12", XSPR(31,467,412), XSPR_MASK
, BOOKE
|PPCVLE
, PPCNONE
, {RS
}},
5254 {"mtivor13", XSPR(31,467,413), XSPR_MASK
, BOOKE
|PPCVLE
, PPCNONE
, {RS
}},
5255 {"mtivor14", XSPR(31,467,414), XSPR_MASK
, BOOKE
|PPCVLE
, PPCNONE
, {RS
}},
5256 {"mtivor15", XSPR(31,467,415), XSPR_MASK
, BOOKE
|PPCVLE
, PPCNONE
, {RS
}},
5257 {"mtspefscr", XSPR(31,467,512), XSPR_MASK
, PPCSPE
, PPCNONE
, {RS
}},
5258 {"mtbbear", XSPR(31,467,513), XSPR_MASK
, PPCBRLK
, PPCNONE
, {RS
}},
5259 {"mtbbtar", XSPR(31,467,514), XSPR_MASK
, PPCBRLK
, PPCNONE
, {RS
}},
5260 {"mtivor32", XSPR(31,467,528), XSPR_MASK
, PPCSPE
, PPCNONE
, {RS
}},
5261 {"mtibatu", XSPR(31,467,528), XSPRBAT_MASK
, PPC
, TITAN
, {SPRBAT
, RS
}},
5262 {"mtivor33", XSPR(31,467,529), XSPR_MASK
, PPCSPE
, PPCNONE
, {RS
}},
5263 {"mtibatl", XSPR(31,467,529), XSPRBAT_MASK
, PPC
, TITAN
, {SPRBAT
, RS
}},
5264 {"mtivor34", XSPR(31,467,530), XSPR_MASK
, PPCSPE
, PPCNONE
, {RS
}},
5265 {"mtivor35", XSPR(31,467,531), XSPR_MASK
, PPCPMR
, PPCNONE
, {RS
}},
5266 {"mtdbatu", XSPR(31,467,536), XSPRBAT_MASK
, PPC
, TITAN
, {SPRBAT
, RS
}},
5267 {"mtdbatl", XSPR(31,467,537), XSPRBAT_MASK
, PPC
, TITAN
, {SPRBAT
, RS
}},
5268 {"mtmcsrr0", XSPR(31,467,570), XSPR_MASK
, PPCRFMCI
|PPCVLE
, PPCNONE
, {RS
}},
5269 {"mtmcsrr1", XSPR(31,467,571), XSPR_MASK
, PPCRFMCI
|PPCVLE
, PPCNONE
, {RS
}},
5270 {"mtmcsr", XSPR(31,467,572), XSPR_MASK
, PPCRFMCI
, PPCNONE
, {RS
}},
5271 {"mtivndx", XSPR(31,467,880), XSPR_MASK
, TITAN
, PPCNONE
, {RS
}},
5272 {"mtdvndx", XSPR(31,467,881), XSPR_MASK
, TITAN
, PPCNONE
, {RS
}},
5273 {"mtivlim", XSPR(31,467,882), XSPR_MASK
, TITAN
, PPCNONE
, {RS
}},
5274 {"mtdvlim", XSPR(31,467,883), XSPR_MASK
, TITAN
, PPCNONE
, {RS
}},
5275 {"mtclcsr", XSPR(31,467,884), XSPR_MASK
, TITAN
, PPCNONE
, {RS
}},
5276 {"mtccr1", XSPR(31,467,888), XSPR_MASK
, TITAN
, PPCNONE
, {RS
}},
5277 {"mtppr", XSPR(31,467,896), XSPR_MASK
, POWER7
, PPCNONE
, {RS
}},
5278 {"mtppr32", XSPR(31,467,898), XSPR_MASK
, POWER7
, PPCNONE
, {RS
}},
5279 {"mtummcr0", XSPR(31,467,936), XSPR_MASK
, PPC750
, PPCNONE
, {RS
}},
5280 {"mtupmc1", XSPR(31,467,937), XSPR_MASK
, PPC750
, PPCNONE
, {RS
}},
5281 {"mtupmc2", XSPR(31,467,938), XSPR_MASK
, PPC750
, PPCNONE
, {RS
}},
5282 {"mtusia", XSPR(31,467,939), XSPR_MASK
, PPC750
, PPCNONE
, {RS
}},
5283 {"mtummcr1", XSPR(31,467,940), XSPR_MASK
, PPC750
, PPCNONE
, {RS
}},
5284 {"mtupmc3", XSPR(31,467,941), XSPR_MASK
, PPC750
, PPCNONE
, {RS
}},
5285 {"mtupmc4", XSPR(31,467,942), XSPR_MASK
, PPC750
, PPCNONE
, {RS
}},
5286 {"mtzpr", XSPR(31,467,944), XSPR_MASK
, PPC403
, PPCNONE
, {RS
}},
5287 {"mtpid", XSPR(31,467,945), XSPR_MASK
, PPC403
, PPCNONE
, {RS
}},
5288 {"mtrmmucr", XSPR(31,467,946), XSPR_MASK
, TITAN
, PPCNONE
, {RS
}},
5289 {"mtccr0", XSPR(31,467,947), XSPR_MASK
, PPC405
|TITAN
, PPCNONE
, {RS
}},
5290 {"mtiac3", XSPR(31,467,948), XSPR_MASK
, PPC405
, PPCNONE
, {RS
}},
5291 {"mtiac4", XSPR(31,467,949), XSPR_MASK
, PPC405
, PPCNONE
, {RS
}},
5292 {"mtdvc1", XSPR(31,467,950), XSPR_MASK
, PPC405
, PPCNONE
, {RS
}},
5293 {"mtdvc2", XSPR(31,467,951), XSPR_MASK
, PPC405
, PPCNONE
, {RS
}},
5294 {"mtmmcr0", XSPR(31,467,952), XSPR_MASK
, PPC750
, PPCNONE
, {RS
}},
5295 {"mtpmc1", XSPR(31,467,953), XSPR_MASK
, PPC750
, PPCNONE
, {RS
}},
5296 {"mtsgr", XSPR(31,467,953), XSPR_MASK
, PPC403
, PPCNONE
, {RS
}},
5297 {"mtdcwr", XSPR(31,467,954), XSPR_MASK
, PPC403
, PPCNONE
, {RS
}},
5298 {"mtpmc2", XSPR(31,467,954), XSPR_MASK
, PPC750
, PPCNONE
, {RS
}},
5299 {"mtsia", XSPR(31,467,955), XSPR_MASK
, PPC750
, PPCNONE
, {RS
}},
5300 {"mtsler", XSPR(31,467,955), XSPR_MASK
, PPC405
, PPCNONE
, {RS
}},
5301 {"mtmmcr1", XSPR(31,467,956), XSPR_MASK
, PPC750
, PPCNONE
, {RS
}},
5302 {"mtsu0r", XSPR(31,467,956), XSPR_MASK
, PPC405
, PPCNONE
, {RS
}},
5303 {"mtdbcr1", XSPR(31,467,957), XSPR_MASK
, PPC405
, PPCNONE
, {RS
}},
5304 {"mtpmc3", XSPR(31,467,957), XSPR_MASK
, PPC750
, PPCNONE
, {RS
}},
5305 {"mtpmc4", XSPR(31,467,958), XSPR_MASK
, PPC750
, PPCNONE
, {RS
}},
5306 {"mticdbdr", XSPR(31,467,979), XSPR_MASK
, PPC403
, PPCNONE
, {RS
}},
5307 {"mtesr", XSPR(31,467,980), XSPR_MASK
, PPC403
, PPCNONE
, {RS
}},
5308 {"mtdear", XSPR(31,467,981), XSPR_MASK
, PPC403
, PPCNONE
, {RS
}},
5309 {"mtevpr", XSPR(31,467,982), XSPR_MASK
, PPC403
, PPCNONE
, {RS
}},
5310 {"mtcdbcr", XSPR(31,467,983), XSPR_MASK
, PPC403
, PPCNONE
, {RS
}},
5311 {"mttsr", XSPR(31,467,984), XSPR_MASK
, PPC403
, PPCNONE
, {RS
}},
5312 {"mttcr", XSPR(31,467,986), XSPR_MASK
, PPC403
, PPCNONE
, {RS
}},
5313 {"mtpit", XSPR(31,467,987), XSPR_MASK
, PPC403
, PPCNONE
, {RS
}},
5314 {"mttbhi", XSPR(31,467,988), XSPR_MASK
, PPC403
, PPCNONE
, {RS
}},
5315 {"mttblo", XSPR(31,467,989), XSPR_MASK
, PPC403
, PPCNONE
, {RS
}},
5316 {"mtsrr2", XSPR(31,467,990), XSPR_MASK
, PPC403
, PPCNONE
, {RS
}},
5317 {"mtsrr3", XSPR(31,467,991), XSPR_MASK
, PPC403
, PPCNONE
, {RS
}},
5318 {"mtdbsr", XSPR(31,467,1008), XSPR_MASK
, PPC403
, PPCNONE
, {RS
}},
5319 {"mtdbdr", XSPR(31,467,1011), XSPR_MASK
, TITAN
, PPCNONE
, {RS
}},
5320 {"mtdbcr0", XSPR(31,467,1010), XSPR_MASK
, PPC405
, PPCNONE
, {RS
}},
5321 {"mtiac1", XSPR(31,467,1012), XSPR_MASK
, PPC403
, PPCNONE
, {RS
}},
5322 {"mtiac2", XSPR(31,467,1013), XSPR_MASK
, PPC403
, PPCNONE
, {RS
}},
5323 {"mtdac1", XSPR(31,467,1014), XSPR_MASK
, PPC403
, PPCNONE
, {RS
}},
5324 {"mtdac2", XSPR(31,467,1015), XSPR_MASK
, PPC403
, PPCNONE
, {RS
}},
5325 {"mtl2cr", XSPR(31,467,1017), XSPR_MASK
, PPC750
, PPCNONE
, {RS
}},
5326 {"mtdccr", XSPR(31,467,1018), XSPR_MASK
, PPC403
, PPCNONE
, {RS
}},
5327 {"mticcr", XSPR(31,467,1019), XSPR_MASK
, PPC403
, PPCNONE
, {RS
}},
5328 {"mtictc", XSPR(31,467,1019), XSPR_MASK
, PPC750
, PPCNONE
, {RS
}},
5329 {"mtpbl1", XSPR(31,467,1020), XSPR_MASK
, PPC403
, PPCNONE
, {RS
}},
5330 {"mtthrm1", XSPR(31,467,1020), XSPR_MASK
, PPC750
, PPCNONE
, {RS
}},
5331 {"mtpbu1", XSPR(31,467,1021), XSPR_MASK
, PPC403
, PPCNONE
, {RS
}},
5332 {"mtthrm2", XSPR(31,467,1021), XSPR_MASK
, PPC750
, PPCNONE
, {RS
}},
5333 {"mtpbl2", XSPR(31,467,1022), XSPR_MASK
, PPC403
, PPCNONE
, {RS
}},
5334 {"mtthrm3", XSPR(31,467,1022), XSPR_MASK
, PPC750
, PPCNONE
, {RS
}},
5335 {"mtpbu2", XSPR(31,467,1023), XSPR_MASK
, PPC403
, PPCNONE
, {RS
}},
5336 {"mtspr", X(31,467), X_MASK
, COM
|PPCVLE
, PPCNONE
, {SPR
, RS
}},
5338 {"dcbi", X(31,470), XRT_MASK
, PPC
|PPCVLE
, PPCNONE
, {RA0
, RB
}},
5340 {"nand", XRC(31,476,0), X_MASK
, COM
|PPCVLE
, PPCNONE
, {RA
, RS
, RB
}},
5341 {"nand.", XRC(31,476,1), X_MASK
, COM
|PPCVLE
, PPCNONE
, {RA
, RS
, RB
}},
5343 {"dsn", X(31,483), XRT_MASK
, E500MC
|PPCVLE
, PPCNONE
, {RA
, RB
}},
5345 {"dcread", X(31,486), X_MASK
, PPC403
|PPC440
|PPCVLE
, PPCA2
|PPC476
, {RT
, RA0
, RB
}},
5347 {"icbtls", X(31,486), X_MASK
, PPCCHLK
|PPC476
|TITAN
|PPCVLE
, PPCNONE
, {CT
, RA0
, RB
}},
5349 {"stvxl", X(31,487), X_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VS
, RA0
, RB
}},
5351 {"nabs", XO(31,488,0,0), XORB_MASK
, M601
, PPCNONE
, {RT
, RA
}},
5352 {"nabs.", XO(31,488,0,1), XORB_MASK
, M601
, PPCNONE
, {RT
, RA
}},
5354 {"divd", XO(31,489,0,0), XO_MASK
, PPC64
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
5355 {"divd.", XO(31,489,0,1), XO_MASK
, PPC64
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
5357 {"divw", XO(31,491,0,0), XO_MASK
, PPC
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
5358 {"divw.", XO(31,491,0,1), XO_MASK
, PPC
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
5360 {"icbtlse", X(31,494), X_MASK
, PPCCHLK
, E500MC
, {CT
, RA
, RB
}},
5362 {"slbia", X(31,498), 0xffffffff, PPC64
, PPCNONE
, {0}},
5364 {"cli", X(31,502), XRB_MASK
, POWER
, PPCNONE
, {RT
, RA
}},
5366 {"popcntd", X(31,506), XRB_MASK
, POWER7
|PPCA2
, PPCNONE
, {RA
, RS
}},
5368 {"cmpb", X(31,508), X_MASK
, POWER6
|PPCA2
|PPC476
, PPCNONE
, {RA
, RS
, RB
}},
5370 {"mcrxr", X(31,512), XRARB_MASK
|(3<<21), COM
|PPCVLE
, POWER7
, {BF
}},
5372 {"lbdx", X(31,515), X_MASK
, E500MC
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
5374 {"bblels", X(31,518), X_MASK
, PPCBRLK
, PPCNONE
, {0}},
5376 {"lvlx", X(31,519), X_MASK
, CELL
, PPCNONE
, {VD
, RA0
, RB
}},
5377 {"lbfcmux", APU(31,519,0), APU_MASK
, PPC405
, PPCNONE
, {FCRT
, RA
, RB
}},
5379 {"subfco", XO(31,8,1,0), XO_MASK
, PPCCOM
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
5380 {"sfo", XO(31,8,1,0), XO_MASK
, PWRCOM
, PPCNONE
, {RT
, RA
, RB
}},
5381 {"subco", XO(31,8,1,0), XO_MASK
, PPCCOM
|PPCVLE
, PPCNONE
, {RT
, RB
, RA
}},
5382 {"subfco.", XO(31,8,1,1), XO_MASK
, PPCCOM
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
5383 {"sfo.", XO(31,8,1,1), XO_MASK
, PWRCOM
, PPCNONE
, {RT
, RA
, RB
}},
5384 {"subco.", XO(31,8,1,1), XO_MASK
, PPCCOM
|PPCVLE
, PPCNONE
, {RT
, RB
, RA
}},
5386 {"addco", XO(31,10,1,0), XO_MASK
, PPCCOM
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
5387 {"ao", XO(31,10,1,0), XO_MASK
, PWRCOM
, PPCNONE
, {RT
, RA
, RB
}},
5388 {"addco.", XO(31,10,1,1), XO_MASK
, PPCCOM
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
5389 {"ao.", XO(31,10,1,1), XO_MASK
, PWRCOM
, PPCNONE
, {RT
, RA
, RB
}},
5391 {"lxsspx", X(31,524), XX1_MASK
, PPCVSX2
, PPCNONE
, {XT6
, RA0
, RB
}},
5393 {"clcs", X(31,531), XRB_MASK
, M601
, PPCNONE
, {RT
, RA
}},
5395 {"ldbrx", X(31,532), X_MASK
, CELL
|POWER7
|PPCA2
, PPCNONE
, {RT
, RA0
, RB
}},
5397 {"lswx", X(31,533), X_MASK
, PPCCOM
|PPCVLE
, E500
|E500MC
, {RT
, RAX
, RBX
}},
5398 {"lsx", X(31,533), X_MASK
, PWRCOM
, PPCNONE
, {RT
, RA
, RB
}},
5400 {"lwbrx", X(31,534), X_MASK
, PPCCOM
|PPCVLE
, PPCNONE
, {RT
, RA0
, RB
}},
5401 {"lbrx", X(31,534), X_MASK
, PWRCOM
, PPCNONE
, {RT
, RA
, RB
}},
5403 {"lfsx", X(31,535), X_MASK
, COM
, PPCEFS
, {FRT
, RA0
, RB
}},
5405 {"srw", XRC(31,536,0), X_MASK
, PPCCOM
|PPCVLE
, PPCNONE
, {RA
, RS
, RB
}},
5406 {"sr", XRC(31,536,0), X_MASK
, PWRCOM
, PPCNONE
, {RA
, RS
, RB
}},
5407 {"srw.", XRC(31,536,1), X_MASK
, PPCCOM
|PPCVLE
, PPCNONE
, {RA
, RS
, RB
}},
5408 {"sr.", XRC(31,536,1), X_MASK
, PWRCOM
, PPCNONE
, {RA
, RS
, RB
}},
5410 {"rrib", XRC(31,537,0), X_MASK
, M601
, PPCNONE
, {RA
, RS
, RB
}},
5411 {"rrib.", XRC(31,537,1), X_MASK
, M601
, PPCNONE
, {RA
, RS
, RB
}},
5413 {"srd", XRC(31,539,0), X_MASK
, PPC64
, PPCNONE
, {RA
, RS
, RB
}},
5414 {"srd.", XRC(31,539,1), X_MASK
, PPC64
, PPCNONE
, {RA
, RS
, RB
}},
5416 {"maskir", XRC(31,541,0), X_MASK
, M601
, PPCNONE
, {RA
, RS
, RB
}},
5417 {"maskir.", XRC(31,541,1), X_MASK
, M601
, PPCNONE
, {RA
, RS
, RB
}},
5419 {"lhdx", X(31,547), X_MASK
, E500MC
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
5421 {"lvtrx", X(31,549), X_MASK
, PPCVEC2
, PPCNONE
, {VD
, RA0
, RB
}},
5423 {"bbelr", X(31,550), X_MASK
, PPCBRLK
, PPCNONE
, {0}},
5425 {"lvrx", X(31,551), X_MASK
, CELL
, PPCNONE
, {VD
, RA0
, RB
}},
5426 {"lhfcmux", APU(31,551,0), APU_MASK
, PPC405
, PPCNONE
, {FCRT
, RA
, RB
}},
5428 {"subfo", XO(31,40,1,0), XO_MASK
, PPC
, PPCNONE
, {RT
, RA
, RB
}},
5429 {"subo", XO(31,40,1,0), XO_MASK
, PPC
, PPCNONE
, {RT
, RB
, RA
}},
5430 {"subfo.", XO(31,40,1,1), XO_MASK
, PPC
, PPCNONE
, {RT
, RA
, RB
}},
5431 {"subo.", XO(31,40,1,1), XO_MASK
, PPC
, PPCNONE
, {RT
, RB
, RA
}},
5433 {"tlbsync", X(31,566), 0xffffffff, PPC
|PPCVLE
, PPCNONE
, {0}},
5435 {"lfsux", X(31,567), X_MASK
, COM
, PPCEFS
, {FRT
, RAS
, RB
}},
5437 {"lwdx", X(31,579), X_MASK
, E500MC
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
5439 {"lvtlx", X(31,581), X_MASK
, PPCVEC2
, PPCNONE
, {VD
, RA0
, RB
}},
5441 {"lwfcmux", APU(31,583,0), APU_MASK
, PPC405
, PPCNONE
, {FCRT
, RA
, RB
}},
5443 {"lxsdx", X(31,588), XX1_MASK
, PPCVSX
, PPCNONE
, {XT6
, RA0
, RB
}},
5445 {"mfsr", X(31,595), XRB_MASK
|(1<<20), COM
, NON32
, {RT
, SR
}},
5447 {"lswi", X(31,597), X_MASK
, PPCCOM
|PPCVLE
, E500
|E500MC
, {RT
, RAX
, NBI
}},
5448 {"lsi", X(31,597), X_MASK
, PWRCOM
, PPCNONE
, {RT
, RA0
, NB
}},
5450 {"lwsync", XSYNC(31,598,1), 0xffffffff, PPC
, E500
, {0}},
5451 {"ptesync", XSYNC(31,598,2), 0xffffffff, PPC64
, PPCNONE
, {0}},
5452 {"sync", X(31,598), XSYNCLE_MASK
,E6500
, PPCNONE
, {LS
, ESYNC
}},
5453 {"sync", X(31,598), XSYNC_MASK
, PPCCOM
|PPCVLE
, BOOKE
|PPC476
, {LS
}},
5454 {"msync", X(31,598), 0xffffffff, BOOKE
|PPCA2
|PPC476
, PPCNONE
, {0}},
5455 {"sync", X(31,598), 0xffffffff, BOOKE
|PPC476
, E6500
, {0}},
5456 {"lwsync", X(31,598), 0xffffffff, E500
, PPCNONE
, {0}},
5457 {"dcs", X(31,598), 0xffffffff, PWRCOM
, PPCNONE
, {0}},
5459 {"lfdx", X(31,599), X_MASK
, COM
, PPCEFS
, {FRT
, RA0
, RB
}},
5461 {"mffgpr", XRC(31,607,0), XRA_MASK
, POWER6
, POWER7
, {FRT
, RB
}},
5462 {"lfdepx", X(31,607), X_MASK
, E500MC
|PPCA2
|PPCVLE
, PPCNONE
, {FRT
, RA0
, RB
}},
5464 {"lddx", X(31,611), X_MASK
, E500MC
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
5466 {"lvswx", X(31,613), X_MASK
, PPCVEC2
, PPCNONE
, {VD
, RA0
, RB
}},
5468 {"lqfcmux", APU(31,615,0), APU_MASK
, PPC405
, PPCNONE
, {FCRT
, RA
, RB
}},
5470 {"nego", XO(31,104,1,0), XORB_MASK
, COM
|PPCVLE
, PPCNONE
, {RT
, RA
}},
5471 {"nego.", XO(31,104,1,1), XORB_MASK
, COM
|PPCVLE
, PPCNONE
, {RT
, RA
}},
5473 {"mulo", XO(31,107,1,0), XO_MASK
, M601
, PPCNONE
, {RT
, RA
, RB
}},
5474 {"mulo.", XO(31,107,1,1), XO_MASK
, M601
, PPCNONE
, {RT
, RA
, RB
}},
5476 {"mfsri", X(31,627), X_MASK
, M601
, PPCNONE
, {RT
, RA
, RB
}},
5478 {"dclst", X(31,630), XRB_MASK
, M601
, PPCNONE
, {RS
, RA
}},
5480 {"lfdux", X(31,631), X_MASK
, COM
, PPCEFS
, {FRT
, RAS
, RB
}},
5482 {"stbdx", X(31,643), X_MASK
, E500MC
, PPCNONE
, {RS
, RA
, RB
}},
5484 {"stvlx", X(31,647), X_MASK
, CELL
, PPCNONE
, {VS
, RA0
, RB
}},
5485 {"stbfcmux", APU(31,647,0), APU_MASK
, PPC405
, PPCNONE
, {FCRT
, RA
, RB
}},
5487 {"stxsspx", X(31,652), XX1_MASK
, PPCVSX2
, PPCNONE
, {XS6
, RA0
, RB
}},
5489 {"tbegin.", XRC(31,654,1), XRTLRARB_MASK
,PPCHTM
, PPCNONE
, {HTM_R
}},
5491 {"subfeo", XO(31,136,1,0), XO_MASK
, PPCCOM
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
5492 {"sfeo", XO(31,136,1,0), XO_MASK
, PWRCOM
, PPCNONE
, {RT
, RA
, RB
}},
5493 {"subfeo.", XO(31,136,1,1), XO_MASK
, PPCCOM
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
5494 {"sfeo.", XO(31,136,1,1), XO_MASK
, PWRCOM
, PPCNONE
, {RT
, RA
, RB
}},
5496 {"addeo", XO(31,138,1,0), XO_MASK
, PPCCOM
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
5497 {"aeo", XO(31,138,1,0), XO_MASK
, PWRCOM
, PPCNONE
, {RT
, RA
, RB
}},
5498 {"addeo.", XO(31,138,1,1), XO_MASK
, PPCCOM
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
5499 {"aeo.", XO(31,138,1,1), XO_MASK
, PWRCOM
, PPCNONE
, {RT
, RA
, RB
}},
5501 {"mfsrin", X(31,659), XRA_MASK
, PPC
, NON32
, {RT
, RB
}},
5503 {"stdbrx", X(31,660), X_MASK
, CELL
|POWER7
|PPCA2
, PPCNONE
, {RS
, RA0
, RB
}},
5505 {"stswx", X(31,661), X_MASK
, PPCCOM
|PPCVLE
, E500
|E500MC
, {RS
, RA0
, RB
}},
5506 {"stsx", X(31,661), X_MASK
, PWRCOM
, PPCNONE
, {RS
, RA0
, RB
}},
5508 {"stwbrx", X(31,662), X_MASK
, PPCCOM
|PPCVLE
, PPCNONE
, {RS
, RA0
, RB
}},
5509 {"stbrx", X(31,662), X_MASK
, PWRCOM
, PPCNONE
, {RS
, RA0
, RB
}},
5511 {"stfsx", X(31,663), X_MASK
, COM
, PPCEFS
, {FRS
, RA0
, RB
}},
5513 {"srq", XRC(31,664,0), X_MASK
, M601
, PPCNONE
, {RA
, RS
, RB
}},
5514 {"srq.", XRC(31,664,1), X_MASK
, M601
, PPCNONE
, {RA
, RS
, RB
}},
5516 {"sre", XRC(31,665,0), X_MASK
, M601
, PPCNONE
, {RA
, RS
, RB
}},
5517 {"sre.", XRC(31,665,1), X_MASK
, M601
, PPCNONE
, {RA
, RS
, RB
}},
5519 {"sthdx", X(31,675), X_MASK
, E500MC
, PPCNONE
, {RS
, RA
, RB
}},
5521 {"stvfrx", X(31,677), X_MASK
, PPCVEC2
, PPCNONE
, {VS
, RA0
, RB
}},
5523 {"stvrx", X(31,679), X_MASK
, CELL
, PPCNONE
, {VS
, RA0
, RB
}},
5524 {"sthfcmux", APU(31,679,0), APU_MASK
, PPC405
, PPCNONE
, {FCRT
, RA
, RB
}},
5526 {"tendall.", XRC(31,686,1)|(1<<25), XRTRARB_MASK
, PPCHTM
, PPCNONE
, {0}},
5527 {"tend.", XRC(31,686,1), XRTARARB_MASK
, PPCHTM
, PPCNONE
, {HTM_A
}},
5529 {"stbcx.", XRC(31,694,1), X_MASK
, POWER7
, PPCNONE
, {RS
, RA0
, RB
}},
5531 {"stfsux", X(31,695), X_MASK
, COM
, PPCEFS
, {FRS
, RAS
, RB
}},
5533 {"sriq", XRC(31,696,0), X_MASK
, M601
, PPCNONE
, {RA
, RS
, SH
}},
5534 {"sriq.", XRC(31,696,1), X_MASK
, M601
, PPCNONE
, {RA
, RS
, SH
}},
5536 {"stwdx", X(31,707), X_MASK
, E500MC
, PPCNONE
, {RS
, RA
, RB
}},
5538 {"stvflx", X(31,709), X_MASK
, PPCVEC2
, PPCNONE
, {VS
, RA0
, RB
}},
5540 {"stwfcmux", APU(31,711,0), APU_MASK
, PPC405
, PPCNONE
, {FCRT
, RA
, RB
}},
5542 {"stxsdx", X(31,716), XX1_MASK
, PPCVSX
, PPCNONE
, {XS6
, RA0
, RB
}},
5544 {"tcheck", X(31,718), XRTBFRARB_MASK
, PPCHTM
, PPCNONE
, {BF
}},
5546 {"subfzeo", XO(31,200,1,0), XORB_MASK
, PPCCOM
|PPCVLE
, PPCNONE
, {RT
, RA
}},
5547 {"sfzeo", XO(31,200,1,0), XORB_MASK
, PWRCOM
, PPCNONE
, {RT
, RA
}},
5548 {"subfzeo.", XO(31,200,1,1), XORB_MASK
, PPCCOM
|PPCVLE
, PPCNONE
, {RT
, RA
}},
5549 {"sfzeo.", XO(31,200,1,1), XORB_MASK
, PWRCOM
, PPCNONE
, {RT
, RA
}},
5551 {"addzeo", XO(31,202,1,0), XORB_MASK
, PPCCOM
|PPCVLE
, PPCNONE
, {RT
, RA
}},
5552 {"azeo", XO(31,202,1,0), XORB_MASK
, PWRCOM
, PPCNONE
, {RT
, RA
}},
5553 {"addzeo.", XO(31,202,1,1), XORB_MASK
, PPCCOM
|PPCVLE
, PPCNONE
, {RT
, RA
}},
5554 {"azeo.", XO(31,202,1,1), XORB_MASK
, PWRCOM
, PPCNONE
, {RT
, RA
}},
5556 {"stswi", X(31,725), X_MASK
, PPCCOM
|PPCVLE
, E500
|E500MC
, {RS
, RA0
, NB
}},
5557 {"stsi", X(31,725), X_MASK
, PWRCOM
, PPCNONE
, {RS
, RA0
, NB
}},
5559 {"sthcx.", XRC(31,726,1), X_MASK
, POWER7
, PPCNONE
, {RS
, RA0
, RB
}},
5561 {"stfdx", X(31,727), X_MASK
, COM
, PPCEFS
, {FRS
, RA0
, RB
}},
5563 {"srlq", XRC(31,728,0), X_MASK
, M601
, PPCNONE
, {RA
, RS
, RB
}},
5564 {"srlq.", XRC(31,728,1), X_MASK
, M601
, PPCNONE
, {RA
, RS
, RB
}},
5566 {"sreq", XRC(31,729,0), X_MASK
, M601
, PPCNONE
, {RA
, RS
, RB
}},
5567 {"sreq.", XRC(31,729,1), X_MASK
, M601
, PPCNONE
, {RA
, RS
, RB
}},
5569 {"mftgpr", XRC(31,735,0), XRA_MASK
, POWER6
, POWER7
, {RT
, FRB
}},
5570 {"stfdepx", X(31,735), X_MASK
, E500MC
|PPCA2
|PPCVLE
, PPCNONE
, {FRS
, RA0
, RB
}},
5572 {"stddx", X(31,739), X_MASK
, E500MC
, PPCNONE
, {RS
, RA
, RB
}},
5574 {"stvswx", X(31,741), X_MASK
, PPCVEC2
, PPCNONE
, {VS
, RA0
, RB
}},
5576 {"stqfcmux", APU(31,743,0), APU_MASK
, PPC405
, PPCNONE
, {FCRT
, RA
, RB
}},
5578 {"subfmeo", XO(31,232,1,0), XORB_MASK
, PPCCOM
, PPCNONE
, {RT
, RA
}},
5579 {"sfmeo", XO(31,232,1,0), XORB_MASK
, PWRCOM
, PPCNONE
, {RT
, RA
}},
5580 {"subfmeo.", XO(31,232,1,1), XORB_MASK
, PPCCOM
, PPCNONE
, {RT
, RA
}},
5581 {"sfmeo.", XO(31,232,1,1), XORB_MASK
, PWRCOM
, PPCNONE
, {RT
, RA
}},
5583 {"mulldo", XO(31,233,1,0), XO_MASK
, PPC64
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
5584 {"mulldo.", XO(31,233,1,1), XO_MASK
, PPC64
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
5586 {"addmeo", XO(31,234,1,0), XORB_MASK
, PPCCOM
|PPCVLE
, PPCNONE
, {RT
, RA
}},
5587 {"ameo", XO(31,234,1,0), XORB_MASK
, PWRCOM
, PPCNONE
, {RT
, RA
}},
5588 {"addmeo.", XO(31,234,1,1), XORB_MASK
, PPCCOM
|PPCVLE
, PPCNONE
, {RT
, RA
}},
5589 {"ameo.", XO(31,234,1,1), XORB_MASK
, PWRCOM
, PPCNONE
, {RT
, RA
}},
5591 {"mullwo", XO(31,235,1,0), XO_MASK
, PPCCOM
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
5592 {"mulso", XO(31,235,1,0), XO_MASK
, PWRCOM
, PPCNONE
, {RT
, RA
, RB
}},
5593 {"mullwo.", XO(31,235,1,1), XO_MASK
, PPCCOM
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
5594 {"mulso.", XO(31,235,1,1), XO_MASK
, PWRCOM
, PPCNONE
, {RT
, RA
, RB
}},
5596 {"tsuspend.", XRCL(31,750,0,1), XRTRARB_MASK
,PPCHTM
, PPCNONE
, {0}},
5597 {"tresume.", XRCL(31,750,1,1), XRTRARB_MASK
,PPCHTM
, PPCNONE
, {0}},
5598 {"tsr.", XRC(31,750,1), XRTLRARB_MASK
,PPCHTM
, PPCNONE
, {L
}},
5600 {"dcba", X(31,758), XRT_MASK
, PPC405
|PPC7450
|BOOKE
|PPCA2
|PPC476
|PPCVLE
, PPCNONE
, {RA0
, RB
}},
5601 {"dcbal", XOPL(31,758,1), XRT_MASK
, E500MC
, PPCNONE
, {RA0
, RB
}},
5603 {"stfdux", X(31,759), X_MASK
, COM
, PPCEFS
, {FRS
, RAS
, RB
}},
5605 {"srliq", XRC(31,760,0), X_MASK
, M601
, PPCNONE
, {RA
, RS
, SH
}},
5606 {"srliq.", XRC(31,760,1), X_MASK
, M601
, PPCNONE
, {RA
, RS
, SH
}},
5608 {"lvsm", X(31,773), X_MASK
, PPCVEC2
, PPCNONE
, {VD
, RA0
, RB
}},
5609 {"stvepxl", X(31,775), X_MASK
, PPCVEC2
, PPCNONE
, {VS
, RA0
, RB
}},
5610 {"lvlxl", X(31,775), X_MASK
, CELL
, PPCNONE
, {VD
, RA0
, RB
}},
5611 {"ldfcmux", APU(31,775,0), APU_MASK
, PPC405
, PPCNONE
, {FCRT
, RA
, RB
}},
5613 {"dozo", XO(31,264,1,0), XO_MASK
, M601
, PPCNONE
, {RT
, RA
, RB
}},
5614 {"dozo.", XO(31,264,1,1), XO_MASK
, M601
, PPCNONE
, {RT
, RA
, RB
}},
5616 {"addo", XO(31,266,1,0), XO_MASK
, PPCCOM
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
5617 {"caxo", XO(31,266,1,0), XO_MASK
, PWRCOM
, PPCNONE
, {RT
, RA
, RB
}},
5618 {"addo.", XO(31,266,1,1), XO_MASK
, PPCCOM
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
5619 {"caxo.", XO(31,266,1,1), XO_MASK
, PWRCOM
, PPCNONE
, {RT
, RA
, RB
}},
5621 {"lxvw4x", X(31,780), XX1_MASK
, PPCVSX
, PPCNONE
, {XT6
, RA0
, RB
}},
5623 {"tabortwc.", XRC(31,782,1), X_MASK
, PPCHTM
, PPCNONE
, {TO
, RA
, RB
}},
5625 {"tlbivax", X(31,786), XRT_MASK
, BOOKE
|PPCA2
|PPC476
|PPCVLE
, PPCNONE
, {RA0
, RB
}},
5627 {"lwzcix", X(31,789), X_MASK
, POWER6
, PPCNONE
, {RT
, RA0
, RB
}},
5629 {"lhbrx", X(31,790), X_MASK
, COM
|PPCVLE
, PPCNONE
, {RT
, RA0
, RB
}},
5631 {"lfdpx", X(31,791), X_MASK
, POWER6
, POWER7
, {FRTp
, RA0
, RB
}},
5632 {"lfqx", X(31,791), X_MASK
, POWER2
, PPCNONE
, {FRT
, RA
, RB
}},
5634 {"sraw", XRC(31,792,0), X_MASK
, PPCCOM
|PPCVLE
, PPCNONE
, {RA
, RS
, RB
}},
5635 {"sra", XRC(31,792,0), X_MASK
, PWRCOM
, PPCNONE
, {RA
, RS
, RB
}},
5636 {"sraw.", XRC(31,792,1), X_MASK
, PPCCOM
|PPCVLE
, PPCNONE
, {RA
, RS
, RB
}},
5637 {"sra.", XRC(31,792,1), X_MASK
, PWRCOM
, PPCNONE
, {RA
, RS
, RB
}},
5639 {"srad", XRC(31,794,0), X_MASK
, PPC64
, PPCNONE
, {RA
, RS
, RB
}},
5640 {"srad.", XRC(31,794,1), X_MASK
, PPC64
, PPCNONE
, {RA
, RS
, RB
}},
5642 {"lfddx", X(31,803), X_MASK
, E500MC
|PPCVLE
, PPCNONE
, {FRT
, RA
, RB
}},
5644 {"lvtrxl", X(31,805), X_MASK
, PPCVEC2
, PPCNONE
, {VD
, RA0
, RB
}},
5645 {"stvepx", X(31,807), X_MASK
, PPCVEC2
, PPCNONE
, {VS
, RA0
, RB
}},
5646 {"lvrxl", X(31,807), X_MASK
, CELL
, PPCNONE
, {VD
, RA0
, RB
}},
5648 {"tabortdc.", XRC(31,814,1), X_MASK
, PPCHTM
, PPCNONE
, {TO
, RA
, RB
}},
5650 {"rac", X(31,818), X_MASK
, M601
, PPCNONE
, {RT
, RA
, RB
}},
5652 {"erativax", X(31,819), X_MASK
, PPCA2
, PPCNONE
, {RS
, RA0
, RB
}},
5654 {"lhzcix", X(31,821), X_MASK
, POWER6
, PPCNONE
, {RT
, RA0
, RB
}},
5656 {"dss", XDSS(31,822,0), XDSS_MASK
, PPCVEC
, PPCNONE
, {STRM
}},
5658 {"lfqux", X(31,823), X_MASK
, POWER2
, PPCNONE
, {FRT
, RA
, RB
}},
5660 {"srawi", XRC(31,824,0), X_MASK
, PPCCOM
|PPCVLE
, PPCNONE
, {RA
, RS
, SH
}},
5661 {"srai", XRC(31,824,0), X_MASK
, PWRCOM
, PPCNONE
, {RA
, RS
, SH
}},
5662 {"srawi.", XRC(31,824,1), X_MASK
, PPCCOM
|PPCVLE
, PPCNONE
, {RA
, RS
, SH
}},
5663 {"srai.", XRC(31,824,1), X_MASK
, PWRCOM
, PPCNONE
, {RA
, RS
, SH
}},
5665 {"sradi", XS(31,413,0), XS_MASK
, PPC64
|PPCVLE
, PPCNONE
, {RA
, RS
, SH6
}},
5666 {"sradi.", XS(31,413,1), XS_MASK
, PPC64
|PPCVLE
, PPCNONE
, {RA
, RS
, SH6
}},
5668 {"lvtlxl", X(31,837), X_MASK
, PPCVEC2
, PPCNONE
, {VD
, RA0
, RB
}},
5670 {"divo", XO(31,331,1,0), XO_MASK
, M601
, PPCNONE
, {RT
, RA
, RB
}},
5671 {"divo.", XO(31,331,1,1), XO_MASK
, M601
, PPCNONE
, {RT
, RA
, RB
}},
5673 {"lxvd2x", X(31,844), XX1_MASK
, PPCVSX
, PPCNONE
, {XT6
, RA0
, RB
}},
5674 {"lxvx", X(31,844), XX1_MASK
, PPCVSX
, PPCNONE
, {XT6
, RA0
, RB
}},
5676 {"tabortwci.", XRC(31,846,1), X_MASK
, PPCHTM
, PPCNONE
, {TO
, RA
, HTM_SI
}},
5678 {"tlbsrx.", XRC(31,850,1), XRT_MASK
, PPCA2
, PPCNONE
, {RA0
, RB
}},
5680 {"slbmfev", X(31,851), XRA_MASK
, PPC64
, PPCNONE
, {RT
, RB
}},
5682 {"lbzcix", X(31,853), X_MASK
, POWER6
, PPCNONE
, {RT
, RA0
, RB
}},
5684 {"eieio", X(31,854), 0xffffffff, PPC
, BOOKE
|PPCA2
|PPC476
, {0}},
5685 {"mbar", X(31,854), X_MASK
, BOOKE
|PPCA2
|PPC476
|PPCVLE
, PPCNONE
, {MO
}},
5686 {"eieio", XMBAR(31,854,1),0xffffffff, E500
, PPCNONE
, {0}},
5687 {"eieio", X(31,854), 0xffffffff, PPCA2
|PPC476
, PPCNONE
, {0}},
5689 {"lfiwax", X(31,855), X_MASK
, POWER6
|PPCA2
|PPC476
, PPCNONE
, {FRT
, RA0
, RB
}},
5691 {"lvswxl", X(31,869), X_MASK
, PPCVEC2
, PPCNONE
, {VD
, RA0
, RB
}},
5693 {"abso", XO(31,360,1,0), XORB_MASK
, M601
, PPCNONE
, {RT
, RA
}},
5694 {"abso.", XO(31,360,1,1), XORB_MASK
, M601
, PPCNONE
, {RT
, RA
}},
5696 {"divso", XO(31,363,1,0), XO_MASK
, M601
, PPCNONE
, {RT
, RA
, RB
}},
5697 {"divso.", XO(31,363,1,1), XO_MASK
, M601
, PPCNONE
, {RT
, RA
, RB
}},
5699 {"tabortdci.", XRC(31,878,1), X_MASK
, PPCHTM
, PPCNONE
, {TO
, RA
, HTM_SI
}},
5701 {"ldcix", X(31,885), X_MASK
, POWER6
, PPCNONE
, {RT
, RA0
, RB
}},
5703 {"lfiwzx", X(31,887), X_MASK
, POWER7
|PPCA2
, PPCNONE
, {FRT
, RA0
, RB
}},
5705 {"stvlxl", X(31,903), X_MASK
, CELL
, PPCNONE
, {VS
, RA0
, RB
}},
5706 {"stdfcmux", APU(31,903,0), APU_MASK
, PPC405
, PPCNONE
, {FCRT
, RA
, RB
}},
5708 {"divdeuo", XO(31,393,1,0), XO_MASK
, POWER7
|PPCA2
, PPCNONE
, {RT
, RA
, RB
}},
5709 {"divdeuo.", XO(31,393,1,1), XO_MASK
, POWER7
|PPCA2
, PPCNONE
, {RT
, RA
, RB
}},
5710 {"divweuo", XO(31,395,1,0), XO_MASK
, POWER7
|PPCA2
, PPCNONE
, {RT
, RA
, RB
}},
5711 {"divweuo.", XO(31,395,1,1), XO_MASK
, POWER7
|PPCA2
, PPCNONE
, {RT
, RA
, RB
}},
5713 {"stxvw4x", X(31,908), XX1_MASK
, PPCVSX
, PPCNONE
, {XS6
, RA0
, RB
}},
5715 {"tabort.", XRC(31,910,1), XRTRB_MASK
, PPCHTM
, PPCNONE
, {RA
}},
5717 {"tlbsx", XRC(31,914,0), X_MASK
, PPC403
|BOOKE
|PPCA2
|PPC476
, PPCNONE
, {RTO
, RA0
, RB
}},
5718 {"tlbsx.", XRC(31,914,1), X_MASK
, PPC403
|BOOKE
|PPCA2
|PPC476
, PPCNONE
, {RTO
, RA0
, RB
}},
5720 {"slbmfee", X(31,915), XRA_MASK
, PPC64
, PPCNONE
, {RT
, RB
}},
5722 {"stwcix", X(31,917), X_MASK
, POWER6
, PPCNONE
, {RS
, RA0
, RB
}},
5724 {"sthbrx", X(31,918), X_MASK
, COM
, PPCNONE
, {RS
, RA0
, RB
}},
5726 {"stfdpx", X(31,919), X_MASK
, POWER6
, POWER7
, {FRSp
, RA0
, RB
}},
5727 {"stfqx", X(31,919), X_MASK
, POWER2
, PPCNONE
, {FRS
, RA0
, RB
}},
5729 {"sraq", XRC(31,920,0), X_MASK
, M601
, PPCNONE
, {RA
, RS
, RB
}},
5730 {"sraq.", XRC(31,920,1), X_MASK
, M601
, PPCNONE
, {RA
, RS
, RB
}},
5732 {"srea", XRC(31,921,0), X_MASK
, M601
, PPCNONE
, {RA
, RS
, RB
}},
5733 {"srea.", XRC(31,921,1), X_MASK
, M601
, PPCNONE
, {RA
, RS
, RB
}},
5735 {"extsh", XRC(31,922,0), XRB_MASK
, PPCCOM
|PPCVLE
, PPCNONE
, {RA
, RS
}},
5736 {"exts", XRC(31,922,0), XRB_MASK
, PWRCOM
, PPCNONE
, {RA
, RS
}},
5737 {"extsh.", XRC(31,922,1), XRB_MASK
, PPCCOM
|PPCVLE
, PPCNONE
, {RA
, RS
}},
5738 {"exts.", XRC(31,922,1), XRB_MASK
, PWRCOM
, PPCNONE
, {RA
, RS
}},
5740 {"stfddx", X(31,931), X_MASK
, E500MC
, PPCNONE
, {FRS
, RA
, RB
}},
5742 {"stvfrxl", X(31,933), X_MASK
, PPCVEC2
, PPCNONE
, {VS
, RA0
, RB
}},
5744 {"wclrone", XOPL2(31,934,2),XRT_MASK
, PPCA2
, PPCNONE
, {RA0
, RB
}},
5745 {"wclrall", X(31,934), XRARB_MASK
, PPCA2
, PPCNONE
, {L
}},
5746 {"wclr", X(31,934), X_MASK
, PPCA2
, PPCNONE
, {L
, RA0
, RB
}},
5748 {"stvrxl", X(31,935), X_MASK
, CELL
, PPCNONE
, {VS
, RA0
, RB
}},
5750 {"divdeo", XO(31,425,1,0), XO_MASK
, POWER7
|PPCA2
, PPCNONE
, {RT
, RA
, RB
}},
5751 {"divdeo.", XO(31,425,1,1), XO_MASK
, POWER7
|PPCA2
, PPCNONE
, {RT
, RA
, RB
}},
5752 {"divweo", XO(31,427,1,0), XO_MASK
, POWER7
|PPCA2
, PPCNONE
, {RT
, RA
, RB
}},
5753 {"divweo.", XO(31,427,1,1), XO_MASK
, POWER7
|PPCA2
, PPCNONE
, {RT
, RA
, RB
}},
5755 {"treclaim.", XRC(31,942,1), XRTRB_MASK
, PPCHTM
, PPCNONE
, {RA
}},
5757 {"tlbrehi", XTLB(31,946,0), XTLB_MASK
, PPC403
, PPCA2
, {RT
, RA
}},
5758 {"tlbrelo", XTLB(31,946,1), XTLB_MASK
, PPC403
, PPCA2
, {RT
, RA
}},
5759 {"tlbre", X(31,946), X_MASK
, PPC403
|BOOKE
|PPCA2
|PPC476
, PPCNONE
, {RSO
, RAOPT
, SHO
}},
5761 {"sthcix", X(31,949), X_MASK
, POWER6
, PPCNONE
, {RS
, RA0
, RB
}},
5763 {"icswepx", XRC(31,950,0), X_MASK
, PPCA2
, PPCNONE
, {RS
, RA
, RB
}},
5764 {"icswepx.", XRC(31,950,1), X_MASK
, PPCA2
, PPCNONE
, {RS
, RA
, RB
}},
5766 {"stfqux", X(31,951), X_MASK
, POWER2
, PPCNONE
, {FRS
, RA
, RB
}},
5768 {"sraiq", XRC(31,952,0), X_MASK
, M601
, PPCNONE
, {RA
, RS
, SH
}},
5769 {"sraiq.", XRC(31,952,1), X_MASK
, M601
, PPCNONE
, {RA
, RS
, SH
}},
5771 {"extsb", XRC(31,954,0), XRB_MASK
, PPC
|PPCVLE
, PPCNONE
, {RA
, RS
}},
5772 {"extsb.", XRC(31,954,1), XRB_MASK
, PPC
|PPCVLE
, PPCNONE
, {RA
, RS
}},
5774 {"stvflxl", X(31,965), X_MASK
, PPCVEC2
, PPCNONE
, {VS
, RA0
, RB
}},
5776 {"iccci", X(31,966), XRT_MASK
, PPC403
|PPC440
|TITAN
|PPCA2
, PPCNONE
, {RAOPT
, RBOPT
}},
5777 {"ici", X(31,966), XRARB_MASK
, PPCA2
|PPC476
|PPCVLE
, PPCNONE
, {CT
}},
5779 {"divduo", XO(31,457,1,0), XO_MASK
, PPC64
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
5780 {"divduo.", XO(31,457,1,1), XO_MASK
, PPC64
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
5782 {"divwuo", XO(31,459,1,0), XO_MASK
, PPC
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
5783 {"divwuo.", XO(31,459,1,1), XO_MASK
, PPC
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
5785 {"stxvd2x", X(31,972), XX1_MASK
, PPCVSX
, PPCNONE
, {XS6
, RA0
, RB
}},
5786 {"stxvx", X(31,972), XX1_MASK
, PPCVSX
, PPCNONE
, {XS6
, RA0
, RB
}},
5788 {"tlbld", X(31,978), XRTRA_MASK
, PPC
, PPC403
|BOOKE
|PPCA2
|PPC476
, {RB
}},
5789 {"tlbwehi", XTLB(31,978,0), XTLB_MASK
, PPC403
, PPCNONE
, {RT
, RA
}},
5790 {"tlbwelo", XTLB(31,978,1), XTLB_MASK
, PPC403
, PPCNONE
, {RT
, RA
}},
5791 {"tlbwe", X(31,978), X_MASK
, PPC403
|BOOKE
|PPCA2
|PPC476
, PPCNONE
, {RSO
, RAOPT
, SHO
}},
5793 {"stbcix", X(31,981), X_MASK
, POWER6
, PPCNONE
, {RS
, RA0
, RB
}},
5795 {"icbi", X(31,982), XRT_MASK
, PPC
|PPCVLE
, PPCNONE
, {RA0
, RB
}},
5797 {"stfiwx", X(31,983), X_MASK
, PPC
, PPCEFS
, {FRS
, RA0
, RB
}},
5799 {"extsw", XRC(31,986,0), XRB_MASK
, PPC64
|PPCVLE
, PPCNONE
, {RA
, RS
}},
5800 {"extsw.", XRC(31,986,1), XRB_MASK
, PPC64
|PPCVLE
, PPCNONE
, {RA
, RS
}},
5802 {"icbiep", XRT(31,991,0), XRT_MASK
, E500MC
|PPCA2
|PPCVLE
, PPCNONE
, {RA0
, RB
}},
5804 {"stvswxl", X(31,997), X_MASK
, PPCVEC2
, PPCNONE
, {VS
, RA0
, RB
}},
5806 {"icread", X(31,998), XRT_MASK
, PPC403
|PPC440
|PPC476
|TITAN
|PPCVLE
, PPCNONE
, {RA0
, RB
}},
5808 {"nabso", XO(31,488,1,0), XORB_MASK
, M601
, PPCNONE
, {RT
, RA
}},
5809 {"nabso.", XO(31,488,1,1), XORB_MASK
, M601
, PPCNONE
, {RT
, RA
}},
5811 {"divdo", XO(31,489,1,0), XO_MASK
, PPC64
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
5812 {"divdo.", XO(31,489,1,1), XO_MASK
, PPC64
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
5814 {"divwo", XO(31,491,1,0), XO_MASK
, PPC
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
5815 {"divwo.", XO(31,491,1,1), XO_MASK
, PPC
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
5817 {"trechkpt.", XRC(31,1006,1), XRTRARB_MASK
,PPCHTM
, PPCNONE
, {0}},
5819 {"tlbli", X(31,1010), XRTRA_MASK
, PPC
, TITAN
, {RB
}},
5821 {"stdcix", X(31,1013), X_MASK
, POWER6
, PPCNONE
, {RS
, RA0
, RB
}},
5823 {"dcbz", X(31,1014), XRT_MASK
, PPC
|PPCVLE
, PPCNONE
, {RA0
, RB
}},
5824 {"dclz", X(31,1014), XRT_MASK
, PPC
, PPCNONE
, {RA0
, RB
}},
5826 {"dcbzep", XRT(31,1023,0), XRT_MASK
, E500MC
|PPCA2
|PPCVLE
, PPCNONE
, {RA0
, RB
}},
5828 {"dcbzl", XOPL(31,1014,1), XRT_MASK
, POWER4
|E500MC
, PPC476
, {RA0
, RB
}},
5830 {"cctpl", 0x7c210b78, 0xffffffff, CELL
, PPCNONE
, {0}},
5831 {"cctpm", 0x7c421378, 0xffffffff, CELL
, PPCNONE
, {0}},
5832 {"cctph", 0x7c631b78, 0xffffffff, CELL
, PPCNONE
, {0}},
5834 {"dstt", XDSS(31,342,1), XDSS_MASK
, PPCVEC
, PPCNONE
, {RA
, RB
, STRM
}},
5835 {"dststt", XDSS(31,374,1), XDSS_MASK
, PPCVEC
, PPCNONE
, {RA
, RB
, STRM
}},
5836 {"dssall", XDSS(31,822,1), XDSS_MASK
, PPCVEC
, PPCNONE
, {0}},
5838 {"db8cyc", 0x7f9ce378, 0xffffffff, CELL
, PPCNONE
, {0}},
5839 {"db10cyc", 0x7fbdeb78, 0xffffffff, CELL
, PPCNONE
, {0}},
5840 {"db12cyc", 0x7fdef378, 0xffffffff, CELL
, PPCNONE
, {0}},
5841 {"db16cyc", 0x7ffffb78, 0xffffffff, CELL
, PPCNONE
, {0}},
5843 {"lwz", OP(32), OP_MASK
, PPCCOM
, PPCNONE
, {RT
, D
, RA0
}},
5844 {"l", OP(32), OP_MASK
, PWRCOM
, PPCNONE
, {RT
, D
, RA0
}},
5846 {"lwzu", OP(33), OP_MASK
, PPCCOM
, PPCNONE
, {RT
, D
, RAL
}},
5847 {"lu", OP(33), OP_MASK
, PWRCOM
, PPCNONE
, {RT
, D
, RA0
}},
5849 {"lbz", OP(34), OP_MASK
, COM
, PPCNONE
, {RT
, D
, RA0
}},
5851 {"lbzu", OP(35), OP_MASK
, COM
, PPCNONE
, {RT
, D
, RAL
}},
5853 {"stw", OP(36), OP_MASK
, PPCCOM
, PPCNONE
, {RS
, D
, RA0
}},
5854 {"st", OP(36), OP_MASK
, PWRCOM
, PPCNONE
, {RS
, D
, RA0
}},
5856 {"stwu", OP(37), OP_MASK
, PPCCOM
, PPCNONE
, {RS
, D
, RAS
}},
5857 {"stu", OP(37), OP_MASK
, PWRCOM
, PPCNONE
, {RS
, D
, RA0
}},
5859 {"stb", OP(38), OP_MASK
, COM
, PPCNONE
, {RS
, D
, RA0
}},
5861 {"stbu", OP(39), OP_MASK
, COM
, PPCNONE
, {RS
, D
, RAS
}},
5863 {"lhz", OP(40), OP_MASK
, COM
, PPCNONE
, {RT
, D
, RA0
}},
5865 {"lhzu", OP(41), OP_MASK
, COM
, PPCNONE
, {RT
, D
, RAL
}},
5867 {"lha", OP(42), OP_MASK
, COM
, PPCNONE
, {RT
, D
, RA0
}},
5869 {"lhau", OP(43), OP_MASK
, COM
, PPCNONE
, {RT
, D
, RAL
}},
5871 {"sth", OP(44), OP_MASK
, COM
, PPCNONE
, {RS
, D
, RA0
}},
5873 {"sthu", OP(45), OP_MASK
, COM
, PPCNONE
, {RS
, D
, RAS
}},
5875 {"lmw", OP(46), OP_MASK
, PPCCOM
, PPCNONE
, {RT
, D
, RAM
}},
5876 {"lm", OP(46), OP_MASK
, PWRCOM
, PPCNONE
, {RT
, D
, RA0
}},
5878 {"stmw", OP(47), OP_MASK
, PPCCOM
, PPCNONE
, {RS
, D
, RA0
}},
5879 {"stm", OP(47), OP_MASK
, PWRCOM
, PPCNONE
, {RS
, D
, RA0
}},
5881 {"lfs", OP(48), OP_MASK
, COM
, PPCEFS
, {FRT
, D
, RA0
}},
5883 {"lfsu", OP(49), OP_MASK
, COM
, PPCEFS
, {FRT
, D
, RAS
}},
5885 {"lfd", OP(50), OP_MASK
, COM
, PPCEFS
, {FRT
, D
, RA0
}},
5887 {"lfdu", OP(51), OP_MASK
, COM
, PPCEFS
, {FRT
, D
, RAS
}},
5889 {"stfs", OP(52), OP_MASK
, COM
, PPCEFS
, {FRS
, D
, RA0
}},
5891 {"stfsu", OP(53), OP_MASK
, COM
, PPCEFS
, {FRS
, D
, RAS
}},
5893 {"stfd", OP(54), OP_MASK
, COM
, PPCEFS
, {FRS
, D
, RA0
}},
5895 {"stfdu", OP(55), OP_MASK
, COM
, PPCEFS
, {FRS
, D
, RAS
}},
5897 {"lq", OP(56), OP_MASK
, POWER4
, PPC476
, {RTQ
, DQ
, RAQ
}},
5898 {"psq_l", OP(56), OP_MASK
, PPCPS
, PPCNONE
, {FRT
,PSD
,RA
,PSW
,PSQ
}},
5899 {"lfq", OP(56), OP_MASK
, POWER2
, PPCNONE
, {FRT
, D
, RA0
}},
5901 {"lfdp", OP(57), OP_MASK
, POWER6
, POWER7
, {FRTp
, DS
, RA0
}},
5902 {"psq_lu", OP(57), OP_MASK
, PPCPS
, PPCNONE
, {FRT
,PSD
,RA
,PSW
,PSQ
}},
5903 {"lfqu", OP(57), OP_MASK
, POWER2
, PPCNONE
, {FRT
, D
, RA0
}},
5905 {"ld", DSO(58,0), DS_MASK
, PPC64
, PPCNONE
, {RT
, DS
, RA0
}},
5906 {"ldu", DSO(58,1), DS_MASK
, PPC64
, PPCNONE
, {RT
, DS
, RAL
}},
5907 {"lwa", DSO(58,2), DS_MASK
, PPC64
, PPCNONE
, {RT
, DS
, RA0
}},
5909 {"dadd", XRC(59,2,0), X_MASK
, POWER6
, PPCNONE
, {FRT
, FRA
, FRB
}},
5910 {"dadd.", XRC(59,2,1), X_MASK
, POWER6
, PPCNONE
, {FRT
, FRA
, FRB
}},
5912 {"dqua", ZRC(59,3,0), Z2_MASK
, POWER6
, PPCNONE
, {FRT
,FRA
,FRB
,RMC
}},
5913 {"dqua.", ZRC(59,3,1), Z2_MASK
, POWER6
, PPCNONE
, {FRT
,FRA
,FRB
,RMC
}},
5915 {"fdivs", A(59,18,0), AFRC_MASK
, PPC
, PPCEFS
, {FRT
, FRA
, FRB
}},
5916 {"fdivs.", A(59,18,1), AFRC_MASK
, PPC
, PPCEFS
, {FRT
, FRA
, FRB
}},
5918 {"fsubs", A(59,20,0), AFRC_MASK
, PPC
, PPCEFS
, {FRT
, FRA
, FRB
}},
5919 {"fsubs.", A(59,20,1), AFRC_MASK
, PPC
, PPCEFS
, {FRT
, FRA
, FRB
}},
5921 {"fadds", A(59,21,0), AFRC_MASK
, PPC
, PPCEFS
, {FRT
, FRA
, FRB
}},
5922 {"fadds.", A(59,21,1), AFRC_MASK
, PPC
, PPCEFS
, {FRT
, FRA
, FRB
}},
5924 {"fsqrts", A(59,22,0), AFRAFRC_MASK
, PPC
, TITAN
, {FRT
, FRB
}},
5925 {"fsqrts.", A(59,22,1), AFRAFRC_MASK
, PPC
, TITAN
, {FRT
, FRB
}},
5927 {"fres", A(59,24,0), AFRAFRC_MASK
, POWER7
, PPCNONE
, {FRT
, FRB
}},
5928 {"fres", A(59,24,0), AFRALFRC_MASK
, PPC
, POWER7
, {FRT
, FRB
, A_L
}},
5929 {"fres.", A(59,24,1), AFRAFRC_MASK
, POWER7
, PPCNONE
, {FRT
, FRB
}},
5930 {"fres.", A(59,24,1), AFRALFRC_MASK
, PPC
, POWER7
, {FRT
, FRB
, A_L
}},
5932 {"fmuls", A(59,25,0), AFRB_MASK
, PPC
, PPCEFS
, {FRT
, FRA
, FRC
}},
5933 {"fmuls.", A(59,25,1), AFRB_MASK
, PPC
, PPCEFS
, {FRT
, FRA
, FRC
}},
5935 {"frsqrtes", A(59,26,0), AFRAFRC_MASK
, POWER7
, PPCNONE
, {FRT
, FRB
}},
5936 {"frsqrtes", A(59,26,0), AFRALFRC_MASK
, POWER5
, POWER7
, {FRT
, FRB
, A_L
}},
5937 {"frsqrtes.", A(59,26,1), AFRAFRC_MASK
, POWER7
, PPCNONE
, {FRT
, FRB
}},
5938 {"frsqrtes.", A(59,26,1), AFRALFRC_MASK
, POWER5
, POWER7
, {FRT
, FRB
, A_L
}},
5940 {"fmsubs", A(59,28,0), A_MASK
, PPC
, PPCEFS
, {FRT
, FRA
, FRC
, FRB
}},
5941 {"fmsubs.", A(59,28,1), A_MASK
, PPC
, PPCEFS
, {FRT
, FRA
, FRC
, FRB
}},
5943 {"fmadds", A(59,29,0), A_MASK
, PPC
, PPCEFS
, {FRT
, FRA
, FRC
, FRB
}},
5944 {"fmadds.", A(59,29,1), A_MASK
, PPC
, PPCEFS
, {FRT
, FRA
, FRC
, FRB
}},
5946 {"fnmsubs", A(59,30,0), A_MASK
, PPC
, PPCEFS
, {FRT
, FRA
, FRC
, FRB
}},
5947 {"fnmsubs.", A(59,30,1), A_MASK
, PPC
, PPCEFS
, {FRT
, FRA
, FRC
, FRB
}},
5949 {"fnmadds", A(59,31,0), A_MASK
, PPC
, PPCEFS
, {FRT
, FRA
, FRC
, FRB
}},
5950 {"fnmadds.", A(59,31,1), A_MASK
, PPC
, PPCEFS
, {FRT
, FRA
, FRC
, FRB
}},
5952 {"dmul", XRC(59,34,0), X_MASK
, POWER6
, PPCNONE
, {FRT
, FRA
, FRB
}},
5953 {"dmul.", XRC(59,34,1), X_MASK
, POWER6
, PPCNONE
, {FRT
, FRA
, FRB
}},
5955 {"drrnd", ZRC(59,35,0), Z2_MASK
, POWER6
, PPCNONE
, {FRT
, FRA
, FRB
, RMC
}},
5956 {"drrnd.", ZRC(59,35,1), Z2_MASK
, POWER6
, PPCNONE
, {FRT
, FRA
, FRB
, RMC
}},
5958 {"dscli", ZRC(59,66,0), Z_MASK
, POWER6
, PPCNONE
, {FRT
, FRA
, SH16
}},
5959 {"dscli.", ZRC(59,66,1), Z_MASK
, POWER6
, PPCNONE
, {FRT
, FRA
, SH16
}},
5961 {"dquai", ZRC(59,67,0), Z2_MASK
, POWER6
, PPCNONE
, {TE
, FRT
,FRB
,RMC
}},
5962 {"dquai.", ZRC(59,67,1), Z2_MASK
, POWER6
, PPCNONE
, {TE
, FRT
,FRB
,RMC
}},
5964 {"dscri", ZRC(59,98,0), Z_MASK
, POWER6
, PPCNONE
, {FRT
, FRA
, SH16
}},
5965 {"dscri.", ZRC(59,98,1), Z_MASK
, POWER6
, PPCNONE
, {FRT
, FRA
, SH16
}},
5967 {"drintx", ZRC(59,99,0), Z2_MASK
, POWER6
, PPCNONE
, {R
, FRT
, FRB
, RMC
}},
5968 {"drintx.", ZRC(59,99,1), Z2_MASK
, POWER6
, PPCNONE
, {R
, FRT
, FRB
, RMC
}},
5970 {"dcmpo", X(59,130), X_MASK
, POWER6
, PPCNONE
, {BF
, FRA
, FRB
}},
5972 {"dtstex", X(59,162), X_MASK
, POWER6
, PPCNONE
, {BF
, FRA
, FRB
}},
5973 {"dtstdc", Z(59,194), Z_MASK
, POWER6
, PPCNONE
, {BF
, FRA
, DCM
}},
5974 {"dtstdg", Z(59,226), Z_MASK
, POWER6
, PPCNONE
, {BF
, FRA
, DGM
}},
5976 {"drintn", ZRC(59,227,0), Z2_MASK
, POWER6
, PPCNONE
, {R
, FRT
, FRB
, RMC
}},
5977 {"drintn.", ZRC(59,227,1), Z2_MASK
, POWER6
, PPCNONE
, {R
, FRT
, FRB
, RMC
}},
5979 {"dctdp", XRC(59,258,0), X_MASK
, POWER6
, PPCNONE
, {FRT
, FRB
}},
5980 {"dctdp.", XRC(59,258,1), X_MASK
, POWER6
, PPCNONE
, {FRT
, FRB
}},
5982 {"dctfix", XRC(59,290,0), X_MASK
, POWER6
, PPCNONE
, {FRT
, FRB
}},
5983 {"dctfix.", XRC(59,290,1), X_MASK
, POWER6
, PPCNONE
, {FRT
, FRB
}},
5985 {"ddedpd", XRC(59,322,0), X_MASK
, POWER6
, PPCNONE
, {SP
, FRT
, FRB
}},
5986 {"ddedpd.", XRC(59,322,1), X_MASK
, POWER6
, PPCNONE
, {SP
, FRT
, FRB
}},
5988 {"dxex", XRC(59,354,0), X_MASK
, POWER6
, PPCNONE
, {FRT
, FRB
}},
5989 {"dxex.", XRC(59,354,1), X_MASK
, POWER6
, PPCNONE
, {FRT
, FRB
}},
5991 {"dsub", XRC(59,514,0), X_MASK
, POWER6
, PPCNONE
, {FRT
, FRA
, FRB
}},
5992 {"dsub.", XRC(59,514,1), X_MASK
, POWER6
, PPCNONE
, {FRT
, FRA
, FRB
}},
5994 {"ddiv", XRC(59,546,0), X_MASK
, POWER6
, PPCNONE
, {FRT
, FRA
, FRB
}},
5995 {"ddiv.", XRC(59,546,1), X_MASK
, POWER6
, PPCNONE
, {FRT
, FRA
, FRB
}},
5997 {"dcmpu", X(59,642), X_MASK
, POWER6
, PPCNONE
, {BF
, FRA
, FRB
}},
5999 {"dtstsf", X(59,674), X_MASK
, POWER6
, PPCNONE
, {BF
, FRA
, FRB
}},
6001 {"drsp", XRC(59,770,0), X_MASK
, POWER6
, PPCNONE
, {FRT
, FRB
}},
6002 {"drsp.", XRC(59,770,1), X_MASK
, POWER6
, PPCNONE
, {FRT
, FRB
}},
6004 {"dcffix", XRC(59,802,0), X_MASK
|FRA_MASK
, POWER7
, PPCNONE
, {FRT
, FRB
}},
6005 {"dcffix.", XRC(59,802,1), X_MASK
|FRA_MASK
, POWER7
, PPCNONE
, {FRT
, FRB
}},
6007 {"denbcd", XRC(59,834,0), X_MASK
, POWER6
, PPCNONE
, {S
, FRT
, FRB
}},
6008 {"denbcd.", XRC(59,834,1), X_MASK
, POWER6
, PPCNONE
, {S
, FRT
, FRB
}},
6010 {"fcfids", XRC(59,846,0), XRA_MASK
, POWER7
|PPCA2
, PPCNONE
, {FRT
, FRB
}},
6011 {"fcfids.", XRC(59,846,1), XRA_MASK
, POWER7
|PPCA2
, PPCNONE
, {FRT
, FRB
}},
6013 {"diex", XRC(59,866,0), X_MASK
, POWER6
, PPCNONE
, {FRT
, FRA
, FRB
}},
6014 {"diex.", XRC(59,866,1), X_MASK
, POWER6
, PPCNONE
, {FRT
, FRA
, FRB
}},
6016 {"fcfidus", XRC(59,974,0), XRA_MASK
, POWER7
|PPCA2
, PPCNONE
, {FRT
, FRB
}},
6017 {"fcfidus.", XRC(59,974,1), XRA_MASK
, POWER7
|PPCA2
, PPCNONE
, {FRT
, FRB
}},
6019 {"xsaddsp", XX3(60,0), XX3_MASK
, PPCVSX2
, PPCNONE
, {XT6
, XA6
, XB6
}},
6020 {"xsmaddasp", XX3(60,1), XX3_MASK
, PPCVSX2
, PPCNONE
, {XT6
, XA6
, XB6
}},
6021 {"xxsldwi", XX3(60,2), XX3SHW_MASK
, PPCVSX
, PPCNONE
, {XT6
, XA6
, XB6
, SHW
}},
6022 {"xxsel", XX4(60,3), XX4_MASK
, PPCVSX
, PPCNONE
, {XT6
, XA6
, XB6
, XC6
}},
6023 {"xssubsp", XX3(60,8), XX3_MASK
, PPCVSX2
, PPCNONE
, {XT6
, XA6
, XB6
}},
6024 {"xsmaddmsp", XX3(60,9), XX3_MASK
, PPCVSX2
, PPCNONE
, {XT6
, XA6
, XB6
}},
6025 {"xxspltd", XX3(60,10), XX3DM_MASK
, PPCVSX
, PPCNONE
, {XT6
, XA6
, XB6S
, DMEX
}},
6026 {"xxmrghd", XX3(60,10), XX3_MASK
, PPCVSX
, PPCNONE
, {XT6
, XA6
, XB6
}},
6027 {"xxswapd", XX3(60,10)|(2<<8), XX3_MASK
, PPCVSX
, PPCNONE
, {XT6
, XA6
, XB6S
}},
6028 {"xxmrgld", XX3(60,10)|(3<<8), XX3_MASK
, PPCVSX
, PPCNONE
, {XT6
, XA6
, XB6
}},
6029 {"xxpermdi", XX3(60,10), XX3DM_MASK
, PPCVSX
, PPCNONE
, {XT6
, XA6
, XB6
, DM
}},
6030 {"xsrsqrtesp", XX2(60,10), XX2_MASK
, PPCVSX2
, PPCNONE
, {XT6
, XB6
}},
6031 {"xssqrtsp", XX2(60,11), XX2_MASK
, PPCVSX2
, PPCNONE
, {XT6
, XB6
}},
6032 {"xsmulsp", XX3(60,16), XX3_MASK
, PPCVSX2
, PPCNONE
, {XT6
, XA6
, XB6
}},
6033 {"xsmsubasp", XX3(60,17), XX3_MASK
, PPCVSX2
, PPCNONE
, {XT6
, XA6
, XB6
}},
6034 {"xxmrghw", XX3(60,18), XX3_MASK
, PPCVSX
, PPCNONE
, {XT6
, XA6
, XB6
}},
6035 {"xsdivsp", XX3(60,24), XX3_MASK
, PPCVSX2
, PPCNONE
, {XT6
, XA6
, XB6
}},
6036 {"xsmsubmsp", XX3(60,25), XX3_MASK
, PPCVSX2
, PPCNONE
, {XT6
, XA6
, XB6
}},
6037 {"xsresp", XX2(60,26), XX2_MASK
, PPCVSX2
, PPCNONE
, {XT6
, XB6
}},
6038 {"xsadddp", XX3(60,32), XX3_MASK
, PPCVSX
, PPCNONE
, {XT6
, XA6
, XB6
}},
6039 {"xsmaddadp", XX3(60,33), XX3_MASK
, PPCVSX
, PPCNONE
, {XT6
, XA6
, XB6
}},
6040 {"xscmpudp", XX3(60,35), XX3BF_MASK
, PPCVSX
, PPCNONE
, {BF
, XA6
, XB6
}},
6041 {"xssubdp", XX3(60,40), XX3_MASK
, PPCVSX
, PPCNONE
, {XT6
, XA6
, XB6
}},
6042 {"xsmaddmdp", XX3(60,41), XX3_MASK
, PPCVSX
, PPCNONE
, {XT6
, XA6
, XB6
}},
6043 {"xscmpodp", XX3(60,43), XX3BF_MASK
, PPCVSX
, PPCNONE
, {BF
, XA6
, XB6
}},
6044 {"xsmuldp", XX3(60,48), XX3_MASK
, PPCVSX
, PPCNONE
, {XT6
, XA6
, XB6
}},
6045 {"xsmsubadp", XX3(60,49), XX3_MASK
, PPCVSX
, PPCNONE
, {XT6
, XA6
, XB6
}},
6046 {"xxmrglw", XX3(60,50), XX3_MASK
, PPCVSX
, PPCNONE
, {XT6
, XA6
, XB6
}},
6047 {"xsdivdp", XX3(60,56), XX3_MASK
, PPCVSX
, PPCNONE
, {XT6
, XA6
, XB6
}},
6048 {"xsmsubmdp", XX3(60,57), XX3_MASK
, PPCVSX
, PPCNONE
, {XT6
, XA6
, XB6
}},
6049 {"xstdivdp", XX3(60,61), XX3BF_MASK
, PPCVSX
, PPCNONE
, {BF
, XA6
, XB6
}},
6050 {"xvaddsp", XX3(60,64), XX3_MASK
, PPCVSX
, PPCNONE
, {XT6
, XA6
, XB6
}},
6051 {"xvmaddasp", XX3(60,65), XX3_MASK
, PPCVSX
, PPCNONE
, {XT6
, XA6
, XB6
}},
6052 {"xvcmpeqsp", XX3RC(60,67,0), XX3_MASK
, PPCVSX
, PPCNONE
, {XT6
, XA6
, XB6
}},
6053 {"xvcmpeqsp.", XX3RC(60,67,1), XX3_MASK
, PPCVSX
, PPCNONE
, {XT6
, XA6
, XB6
}},
6054 {"xvsubsp", XX3(60,72), XX3_MASK
, PPCVSX
, PPCNONE
, {XT6
, XA6
, XB6
}},
6055 {"xscvdpuxws", XX2(60,72), XX2_MASK
, PPCVSX
, PPCNONE
, {XT6
, XB6
}},
6056 {"xvmaddmsp", XX3(60,73), XX3_MASK
, PPCVSX
, PPCNONE
, {XT6
, XA6
, XB6
}},
6057 {"xsrdpi", XX2(60,73), XX2_MASK
, PPCVSX
, PPCNONE
, {XT6
, XB6
}},
6058 {"xsrsqrtedp", XX2(60,74), XX2_MASK
, PPCVSX
, PPCNONE
, {XT6
, XB6
}},
6059 {"xssqrtdp", XX2(60,75), XX2_MASK
, PPCVSX
, PPCNONE
, {XT6
, XB6
}},
6060 {"xvcmpgtsp", XX3RC(60,75,0), XX3_MASK
, PPCVSX
, PPCNONE
, {XT6
, XA6
, XB6
}},
6061 {"xvcmpgtsp.", XX3RC(60,75,1), XX3_MASK
, PPCVSX
, PPCNONE
, {XT6
, XA6
, XB6
}},
6062 {"xvmulsp", XX3(60,80), XX3_MASK
, PPCVSX
, PPCNONE
, {XT6
, XA6
, XB6
}},
6063 {"xvmsubasp", XX3(60,81), XX3_MASK
, PPCVSX
, PPCNONE
, {XT6
, XA6
, XB6
}},
6064 {"xvcmpgesp", XX3RC(60,83,0), XX3_MASK
, PPCVSX
, PPCNONE
, {XT6
, XA6
, XB6
}},
6065 {"xvcmpgesp.", XX3RC(60,83,1), XX3_MASK
, PPCVSX
, PPCNONE
, {XT6
, XA6
, XB6
}},
6066 {"xvdivsp", XX3(60,88), XX3_MASK
, PPCVSX
, PPCNONE
, {XT6
, XA6
, XB6
}},
6067 {"xscvdpsxws", XX2(60,88), XX2_MASK
, PPCVSX
, PPCNONE
, {XT6
, XB6
}},
6068 {"xvmsubmsp", XX3(60,89), XX3_MASK
, PPCVSX
, PPCNONE
, {XT6
, XA6
, XB6
}},
6069 {"xsrdpiz", XX2(60,89), XX2_MASK
, PPCVSX
, PPCNONE
, {XT6
, XB6
}},
6070 {"xsredp", XX2(60,90), XX2_MASK
, PPCVSX
, PPCNONE
, {XT6
, XB6
}},
6071 {"xvtdivsp", XX3(60,93), XX3BF_MASK
, PPCVSX
, PPCNONE
, {BF
, XA6
, XB6
}},
6072 {"xvadddp", XX3(60,96), XX3_MASK
, PPCVSX
, PPCNONE
, {XT6
, XA6
, XB6
}},
6073 {"xvmaddadp", XX3(60,97), XX3_MASK
, PPCVSX
, PPCNONE
, {XT6
, XA6
, XB6
}},
6074 {"xvcmpeqdp", XX3RC(60,99,0), XX3_MASK
, PPCVSX
, PPCNONE
, {XT6
, XA6
, XB6
}},
6075 {"xvcmpeqdp.", XX3RC(60,99,1), XX3_MASK
, PPCVSX
, PPCNONE
, {XT6
, XA6
, XB6
}},
6076 {"xvsubdp", XX3(60,104), XX3_MASK
, PPCVSX
, PPCNONE
, {XT6
, XA6
, XB6
}},
6077 {"xvmaddmdp", XX3(60,105), XX3_MASK
, PPCVSX
, PPCNONE
, {XT6
, XA6
, XB6
}},
6078 {"xsrdpip", XX2(60,105), XX2_MASK
, PPCVSX
, PPCNONE
, {XT6
, XB6
}},
6079 {"xstsqrtdp", XX2(60,106), XX2BF_MASK
, PPCVSX
, PPCNONE
, {BF
, XB6
}},
6080 {"xsrdpic", XX2(60,107), XX2_MASK
, PPCVSX
, PPCNONE
, {XT6
, XB6
}},
6081 {"xvcmpgtdp", XX3RC(60,107,0), XX3_MASK
, PPCVSX
, PPCNONE
, {XT6
, XA6
, XB6
}},
6082 {"xvcmpgtdp.", XX3RC(60,107,1), XX3_MASK
, PPCVSX
, PPCNONE
, {XT6
, XA6
, XB6
}},
6083 {"xvmuldp", XX3(60,112), XX3_MASK
, PPCVSX
, PPCNONE
, {XT6
, XA6
, XB6
}},
6084 {"xvmsubadp", XX3(60,113), XX3_MASK
, PPCVSX
, PPCNONE
, {XT6
, XA6
, XB6
}},
6085 {"xvcmpgedp", XX3RC(60,115,0), XX3_MASK
, PPCVSX
, PPCNONE
, {XT6
, XA6
, XB6
}},
6086 {"xvcmpgedp.", XX3RC(60,115,1), XX3_MASK
, PPCVSX
, PPCNONE
, {XT6
, XA6
, XB6
}},
6087 {"xvdivdp", XX3(60,120), XX3_MASK
, PPCVSX
, PPCNONE
, {XT6
, XA6
, XB6
}},
6088 {"xvmsubmdp", XX3(60,121), XX3_MASK
, PPCVSX
, PPCNONE
, {XT6
, XA6
, XB6
}},
6089 {"xsrdpim", XX2(60,121), XX2_MASK
, PPCVSX
, PPCNONE
, {XT6
, XB6
}},
6090 {"xvtdivdp", XX3(60,125), XX3BF_MASK
, PPCVSX
, PPCNONE
, {BF
, XA6
, XB6
}},
6091 {"xsnmaddasp", XX3(60,129), XX3_MASK
, PPCVSX2
, PPCNONE
, {XT6
, XA6
, XB6
}},
6092 {"xxland", XX3(60,130), XX3_MASK
, PPCVSX
, PPCNONE
, {XT6
, XA6
, XB6
}},
6093 {"xvcvspuxws", XX2(60,136), XX2_MASK
, PPCVSX
, PPCNONE
, {XT6
, XB6
}},
6094 {"xsnmaddmsp", XX3(60,137), XX3_MASK
, PPCVSX2
, PPCNONE
, {XT6
, XA6
, XB6
}},
6095 {"xvrspi", XX2(60,137), XX2_MASK
, PPCVSX
, PPCNONE
, {XT6
, XB6
}},
6096 {"xxlandc", XX3(60,138), XX3_MASK
, PPCVSX
, PPCNONE
, {XT6
, XA6
, XB6
}},
6097 {"xvrsqrtesp", XX2(60,138), XX2_MASK
, PPCVSX
, PPCNONE
, {XT6
, XB6
}},
6098 {"xvsqrtsp", XX2(60,139), XX2_MASK
, PPCVSX
, PPCNONE
, {XT6
, XB6
}},
6099 {"xsnmsubasp", XX3(60,145), XX3_MASK
, PPCVSX2
, PPCNONE
, {XT6
, XA6
, XB6
}},
6100 {"xxlor", XX3(60,146), XX3_MASK
, PPCVSX
, PPCNONE
, {XT6
, XA6
, XB6
}},
6101 {"xvcvspsxws", XX2(60,152), XX2_MASK
, PPCVSX
, PPCNONE
, {XT6
, XB6
}},
6102 {"xsnmsubmsp", XX3(60,153), XX3_MASK
, PPCVSX2
, PPCNONE
, {XT6
, XA6
, XB6
}},
6103 {"xvrspiz", XX2(60,153), XX2_MASK
, PPCVSX
, PPCNONE
, {XT6
, XB6
}},
6104 {"xxlxor", XX3(60,154), XX3_MASK
, PPCVSX
, PPCNONE
, {XT6
, XA6
, XB6
}},
6105 {"xvresp", XX2(60,154), XX2_MASK
, PPCVSX
, PPCNONE
, {XT6
, XB6
}},
6106 {"xsmaxdp", XX3(60,160), XX3_MASK
, PPCVSX
, PPCNONE
, {XT6
, XA6
, XB6
}},
6107 {"xsnmaddadp", XX3(60,161), XX3_MASK
, PPCVSX
, PPCNONE
, {XT6
, XA6
, XB6
}},
6108 {"xxlnor", XX3(60,162), XX3_MASK
, PPCVSX
, PPCNONE
, {XT6
, XA6
, XB6
}},
6109 {"xxspltw", XX2(60,164), XX2UIM_MASK
, PPCVSX
, PPCNONE
, {XT6
, XB6
, UIM
}},
6110 {"xsmindp", XX3(60,168), XX3_MASK
, PPCVSX
, PPCNONE
, {XT6
, XA6
, XB6
}},
6111 {"xvcvuxwsp", XX2(60,168), XX2_MASK
, PPCVSX
, PPCNONE
, {XT6
, XB6
}},
6112 {"xsnmaddmdp", XX3(60,169), XX3_MASK
, PPCVSX
, PPCNONE
, {XT6
, XA6
, XB6
}},
6113 {"xvrspip", XX2(60,169), XX2_MASK
, PPCVSX
, PPCNONE
, {XT6
, XB6
}},
6114 {"xvtsqrtsp", XX2(60,170), XX2BF_MASK
, PPCVSX
, PPCNONE
, {BF
, XB6
}},
6115 {"xxlorc", XX3(60,170), XX3_MASK
, PPCVSX2
, PPCNONE
, {XT6
, XA6
, XB6
}},
6116 {"xvrspic", XX2(60,171), XX2_MASK
, PPCVSX
, PPCNONE
, {XT6
, XB6
}},
6117 {"xscpsgndp", XX3(60,176), XX3_MASK
, PPCVSX
, PPCNONE
, {XT6
, XA6
, XB6
}},
6118 {"xsnmsubadp", XX3(60,177), XX3_MASK
, PPCVSX
, PPCNONE
, {XT6
, XA6
, XB6
}},
6119 {"xxlnand", XX3(60,178), XX3_MASK
, PPCVSX2
, PPCNONE
, {XT6
, XA6
, XB6
}},
6120 {"xvcvsxwsp", XX2(60,184), XX2_MASK
, PPCVSX
, PPCNONE
, {XT6
, XB6
}},
6121 {"xsnmsubmdp", XX3(60,185), XX3_MASK
, PPCVSX
, PPCNONE
, {XT6
, XA6
, XB6
}},
6122 {"xvrspim", XX2(60,185), XX2_MASK
, PPCVSX
, PPCNONE
, {XT6
, XB6
}},
6123 {"xxleqv", XX3(60,186), XX3_MASK
, PPCVSX2
, PPCNONE
, {XT6
, XA6
, XB6
}},
6124 {"xvmaxsp", XX3(60,192), XX3_MASK
, PPCVSX
, PPCNONE
, {XT6
, XA6
, XB6
}},
6125 {"xvnmaddasp", XX3(60,193), XX3_MASK
, PPCVSX
, PPCNONE
, {XT6
, XA6
, XB6
}},
6126 {"xvminsp", XX3(60,200), XX3_MASK
, PPCVSX
, PPCNONE
, {XT6
, XA6
, XB6
}},
6127 {"xvcvdpuxws", XX2(60,200), XX2_MASK
, PPCVSX
, PPCNONE
, {XT6
, XB6
}},
6128 {"xvnmaddmsp", XX3(60,201), XX3_MASK
, PPCVSX
, PPCNONE
, {XT6
, XA6
, XB6
}},
6129 {"xvrdpi", XX2(60,201), XX2_MASK
, PPCVSX
, PPCNONE
, {XT6
, XB6
}},
6130 {"xvrsqrtedp", XX2(60,202), XX2_MASK
, PPCVSX
, PPCNONE
, {XT6
, XB6
}},
6131 {"xvsqrtdp", XX2(60,203), XX2_MASK
, PPCVSX
, PPCNONE
, {XT6
, XB6
}},
6132 {"xvmovsp", XX3(60,208), XX3_MASK
, PPCVSX
, PPCNONE
, {XT6
, XA6
, XB6S
}},
6133 {"xvcpsgnsp", XX3(60,208), XX3_MASK
, PPCVSX
, PPCNONE
, {XT6
, XA6
, XB6
}},
6134 {"xvnmsubasp", XX3(60,209), XX3_MASK
, PPCVSX
, PPCNONE
, {XT6
, XA6
, XB6
}},
6135 {"xvcvdpsxws", XX2(60,216), XX2_MASK
, PPCVSX
, PPCNONE
, {XT6
, XB6
}},
6136 {"xvnmsubmsp", XX3(60,217), XX3_MASK
, PPCVSX
, PPCNONE
, {XT6
, XA6
, XB6
}},
6137 {"xvrdpiz", XX2(60,217), XX2_MASK
, PPCVSX
, PPCNONE
, {XT6
, XB6
}},
6138 {"xvredp", XX2(60,218), XX2_MASK
, PPCVSX
, PPCNONE
, {XT6
, XB6
}},
6139 {"xvmaxdp", XX3(60,224), XX3_MASK
, PPCVSX
, PPCNONE
, {XT6
, XA6
, XB6
}},
6140 {"xvnmaddadp", XX3(60,225), XX3_MASK
, PPCVSX
, PPCNONE
, {XT6
, XA6
, XB6
}},
6141 {"xvmindp", XX3(60,232), XX3_MASK
, PPCVSX
, PPCNONE
, {XT6
, XA6
, XB6
}},
6142 {"xvnmaddmdp", XX3(60,233), XX3_MASK
, PPCVSX
, PPCNONE
, {XT6
, XA6
, XB6
}},
6143 {"xvcvuxwdp", XX2(60,232), XX2_MASK
, PPCVSX
, PPCNONE
, {XT6
, XB6
}},
6144 {"xvrdpip", XX2(60,233), XX2_MASK
, PPCVSX
, PPCNONE
, {XT6
, XB6
}},
6145 {"xvtsqrtdp", XX2(60,234), XX2BF_MASK
, PPCVSX
, PPCNONE
, {BF
, XB6
}},
6146 {"xvrdpic", XX2(60,235), XX2_MASK
, PPCVSX
, PPCNONE
, {XT6
, XB6
}},
6147 {"xvmovdp", XX3(60,240), XX3_MASK
, PPCVSX
, PPCNONE
, {XT6
, XA6
, XB6S
}},
6148 {"xvcpsgndp", XX3(60,240), XX3_MASK
, PPCVSX
, PPCNONE
, {XT6
, XA6
, XB6
}},
6149 {"xvnmsubadp", XX3(60,241), XX3_MASK
, PPCVSX
, PPCNONE
, {XT6
, XA6
, XB6
}},
6150 {"xvcvsxwdp", XX2(60,248), XX2_MASK
, PPCVSX
, PPCNONE
, {XT6
, XB6
}},
6151 {"xvnmsubmdp", XX3(60,249), XX3_MASK
, PPCVSX
, PPCNONE
, {XT6
, XA6
, XB6
}},
6152 {"xvrdpim", XX2(60,249), XX2_MASK
, PPCVSX
, PPCNONE
, {XT6
, XB6
}},
6153 {"xscvdpsp", XX2(60,265), XX2_MASK
, PPCVSX
, PPCNONE
, {XT6
, XB6
}},
6154 {"xscvdpspn", XX2(60,267), XX2_MASK
, PPCVSX2
, PPCNONE
, {XT6
, XB6
}},
6155 {"xsrsp", XX2(60,281), XX2_MASK
, PPCVSX2
, PPCNONE
, {XT6
, XB6
}},
6156 {"xscvuxdsp", XX2(60,296), XX2_MASK
, PPCVSX2
, PPCNONE
, {XT6
, XB6
}},
6157 {"xscvsxdsp", XX2(60,312), XX2_MASK
, PPCVSX2
, PPCNONE
, {XT6
, XB6
}},
6158 {"xscvdpuxds", XX2(60,328), XX2_MASK
, PPCVSX
, PPCNONE
, {XT6
, XB6
}},
6159 {"xscvspdp", XX2(60,329), XX2_MASK
, PPCVSX
, PPCNONE
, {XT6
, XB6
}},
6160 {"xscvspdpn", XX2(60,331), XX2_MASK
, PPCVSX2
, PPCNONE
, {XT6
, XB6
}},
6161 {"xscvdpsxds", XX2(60,344), XX2_MASK
, PPCVSX
, PPCNONE
, {XT6
, XB6
}},
6162 {"xsabsdp", XX2(60,345), XX2_MASK
, PPCVSX
, PPCNONE
, {XT6
, XB6
}},
6163 {"xscvuxddp", XX2(60,360), XX2_MASK
, PPCVSX
, PPCNONE
, {XT6
, XB6
}},
6164 {"xsnabsdp", XX2(60,361), XX2_MASK
, PPCVSX
, PPCNONE
, {XT6
, XB6
}},
6165 {"xscvsxddp", XX2(60,376), XX2_MASK
, PPCVSX
, PPCNONE
, {XT6
, XB6
}},
6166 {"xsnegdp", XX2(60,377), XX2_MASK
, PPCVSX
, PPCNONE
, {XT6
, XB6
}},
6167 {"xvcvspuxds", XX2(60,392), XX2_MASK
, PPCVSX
, PPCNONE
, {XT6
, XB6
}},
6168 {"xvcvdpsp", XX2(60,393), XX2_MASK
, PPCVSX
, PPCNONE
, {XT6
, XB6
}},
6169 {"xvcvspsxds", XX2(60,408), XX2_MASK
, PPCVSX
, PPCNONE
, {XT6
, XB6
}},
6170 {"xvabssp", XX2(60,409), XX2_MASK
, PPCVSX
, PPCNONE
, {XT6
, XB6
}},
6171 {"xvcvuxdsp", XX2(60,424), XX2_MASK
, PPCVSX
, PPCNONE
, {XT6
, XB6
}},
6172 {"xvnabssp", XX2(60,425), XX2_MASK
, PPCVSX
, PPCNONE
, {XT6
, XB6
}},
6173 {"xvcvsxdsp", XX2(60,440), XX2_MASK
, PPCVSX
, PPCNONE
, {XT6
, XB6
}},
6174 {"xvnegsp", XX2(60,441), XX2_MASK
, PPCVSX
, PPCNONE
, {XT6
, XB6
}},
6175 {"xvcvdpuxds", XX2(60,456), XX2_MASK
, PPCVSX
, PPCNONE
, {XT6
, XB6
}},
6176 {"xvcvspdp", XX2(60,457), XX2_MASK
, PPCVSX
, PPCNONE
, {XT6
, XB6
}},
6177 {"xvcvdpsxds", XX2(60,472), XX2_MASK
, PPCVSX
, PPCNONE
, {XT6
, XB6
}},
6178 {"xvabsdp", XX2(60,473), XX2_MASK
, PPCVSX
, PPCNONE
, {XT6
, XB6
}},
6179 {"xvcvuxddp", XX2(60,488), XX2_MASK
, PPCVSX
, PPCNONE
, {XT6
, XB6
}},
6180 {"xvnabsdp", XX2(60,489), XX2_MASK
, PPCVSX
, PPCNONE
, {XT6
, XB6
}},
6181 {"xvcvsxddp", XX2(60,504), XX2_MASK
, PPCVSX
, PPCNONE
, {XT6
, XB6
}},
6182 {"xvnegdp", XX2(60,505), XX2_MASK
, PPCVSX
, PPCNONE
, {XT6
, XB6
}},
6184 {"psq_st", OP(60), OP_MASK
, PPCPS
, PPCNONE
, {FRS
,PSD
,RA
,PSW
,PSQ
}},
6185 {"stfq", OP(60), OP_MASK
, POWER2
, PPCNONE
, {FRS
, D
, RA
}},
6187 {"stfdp", OP(61), OP_MASK
, POWER6
, POWER7
, {FRSp
, DS
, RA0
}},
6188 {"psq_stu", OP(61), OP_MASK
, PPCPS
, PPCNONE
, {FRS
,PSD
,RA
,PSW
,PSQ
}},
6189 {"stfqu", OP(61), OP_MASK
, POWER2
, PPCNONE
, {FRS
, D
, RA
}},
6191 {"std", DSO(62,0), DS_MASK
, PPC64
, PPCNONE
, {RS
, DS
, RA0
}},
6192 {"stdu", DSO(62,1), DS_MASK
, PPC64
, PPCNONE
, {RS
, DS
, RAS
}},
6193 {"stq", DSO(62,2), DS_MASK
, POWER4
, PPC476
, {RSQ
, DS
, RA0
}},
6195 {"fcmpu", X(63,0), X_MASK
|(3<<21), COM
, PPCEFS
, {BF
, FRA
, FRB
}},
6197 {"daddq", XRC(63,2,0), X_MASK
, POWER6
, PPCNONE
, {FRTp
, FRAp
, FRBp
}},
6198 {"daddq.", XRC(63,2,1), X_MASK
, POWER6
, PPCNONE
, {FRTp
, FRAp
, FRBp
}},
6200 {"dquaq", ZRC(63,3,0), Z2_MASK
, POWER6
, PPCNONE
, {FRTp
, FRAp
, FRBp
, RMC
}},
6201 {"dquaq.", ZRC(63,3,1), Z2_MASK
, POWER6
, PPCNONE
, {FRTp
, FRAp
, FRBp
, RMC
}},
6203 {"fcpsgn", XRC(63,8,0), X_MASK
, POWER6
|PPCA2
|PPC476
, PPCNONE
, {FRT
, FRA
, FRB
}},
6204 {"fcpsgn.", XRC(63,8,1), X_MASK
, POWER6
|PPCA2
|PPC476
, PPCNONE
, {FRT
, FRA
, FRB
}},
6206 {"frsp", XRC(63,12,0), XRA_MASK
, COM
, PPCEFS
, {FRT
, FRB
}},
6207 {"frsp.", XRC(63,12,1), XRA_MASK
, COM
, PPCEFS
, {FRT
, FRB
}},
6209 {"fctiw", XRC(63,14,0), XRA_MASK
, PPCCOM
, PPCEFS
, {FRT
, FRB
}},
6210 {"fcir", XRC(63,14,0), XRA_MASK
, PWR2COM
, PPCNONE
, {FRT
, FRB
}},
6211 {"fctiw.", XRC(63,14,1), XRA_MASK
, PPCCOM
, PPCEFS
, {FRT
, FRB
}},
6212 {"fcir.", XRC(63,14,1), XRA_MASK
, PWR2COM
, PPCNONE
, {FRT
, FRB
}},
6214 {"fctiwz", XRC(63,15,0), XRA_MASK
, PPCCOM
, PPCEFS
, {FRT
, FRB
}},
6215 {"fcirz", XRC(63,15,0), XRA_MASK
, PWR2COM
, PPCNONE
, {FRT
, FRB
}},
6216 {"fctiwz.", XRC(63,15,1), XRA_MASK
, PPCCOM
, PPCEFS
, {FRT
, FRB
}},
6217 {"fcirz.", XRC(63,15,1), XRA_MASK
, PWR2COM
, PPCNONE
, {FRT
, FRB
}},
6219 {"fdiv", A(63,18,0), AFRC_MASK
, PPCCOM
, PPCEFS
, {FRT
, FRA
, FRB
}},
6220 {"fd", A(63,18,0), AFRC_MASK
, PWRCOM
, PPCNONE
, {FRT
, FRA
, FRB
}},
6221 {"fdiv.", A(63,18,1), AFRC_MASK
, PPCCOM
, PPCEFS
, {FRT
, FRA
, FRB
}},
6222 {"fd.", A(63,18,1), AFRC_MASK
, PWRCOM
, PPCNONE
, {FRT
, FRA
, FRB
}},
6224 {"fsub", A(63,20,0), AFRC_MASK
, PPCCOM
, PPCEFS
, {FRT
, FRA
, FRB
}},
6225 {"fs", A(63,20,0), AFRC_MASK
, PWRCOM
, PPCNONE
, {FRT
, FRA
, FRB
}},
6226 {"fsub.", A(63,20,1), AFRC_MASK
, PPCCOM
, PPCEFS
, {FRT
, FRA
, FRB
}},
6227 {"fs.", A(63,20,1), AFRC_MASK
, PWRCOM
, PPCNONE
, {FRT
, FRA
, FRB
}},
6229 {"fadd", A(63,21,0), AFRC_MASK
, PPCCOM
, PPCEFS
, {FRT
, FRA
, FRB
}},
6230 {"fa", A(63,21,0), AFRC_MASK
, PWRCOM
, PPCNONE
, {FRT
, FRA
, FRB
}},
6231 {"fadd.", A(63,21,1), AFRC_MASK
, PPCCOM
, PPCEFS
, {FRT
, FRA
, FRB
}},
6232 {"fa.", A(63,21,1), AFRC_MASK
, PWRCOM
, PPCNONE
, {FRT
, FRA
, FRB
}},
6234 {"fsqrt", A(63,22,0), AFRAFRC_MASK
, PPCPWR2
, TITAN
, {FRT
, FRB
}},
6235 {"fsqrt.", A(63,22,1), AFRAFRC_MASK
, PPCPWR2
, TITAN
, {FRT
, FRB
}},
6237 {"fsel", A(63,23,0), A_MASK
, PPC
, PPCEFS
, {FRT
, FRA
, FRC
, FRB
}},
6238 {"fsel.", A(63,23,1), A_MASK
, PPC
, PPCEFS
, {FRT
, FRA
, FRC
, FRB
}},
6240 {"fre", A(63,24,0), AFRAFRC_MASK
, POWER7
, PPCNONE
, {FRT
, FRB
}},
6241 {"fre", A(63,24,0), AFRALFRC_MASK
, POWER5
, POWER7
, {FRT
, FRB
, A_L
}},
6242 {"fre.", A(63,24,1), AFRAFRC_MASK
, POWER7
, PPCNONE
, {FRT
, FRB
}},
6243 {"fre.", A(63,24,1), AFRALFRC_MASK
, POWER5
, POWER7
, {FRT
, FRB
, A_L
}},
6245 {"fmul", A(63,25,0), AFRB_MASK
, PPCCOM
, PPCEFS
, {FRT
, FRA
, FRC
}},
6246 {"fm", A(63,25,0), AFRB_MASK
, PWRCOM
, PPCNONE
, {FRT
, FRA
, FRC
}},
6247 {"fmul.", A(63,25,1), AFRB_MASK
, PPCCOM
, PPCEFS
, {FRT
, FRA
, FRC
}},
6248 {"fm.", A(63,25,1), AFRB_MASK
, PWRCOM
, PPCNONE
, {FRT
, FRA
, FRC
}},
6250 {"frsqrte", A(63,26,0), AFRAFRC_MASK
, POWER7
, PPCNONE
, {FRT
, FRB
}},
6251 {"frsqrte", A(63,26,0), AFRALFRC_MASK
, PPC
, POWER7
, {FRT
, FRB
, A_L
}},
6252 {"frsqrte.", A(63,26,1), AFRAFRC_MASK
, POWER7
, PPCNONE
, {FRT
, FRB
}},
6253 {"frsqrte.", A(63,26,1), AFRALFRC_MASK
, PPC
, POWER7
, {FRT
, FRB
, A_L
}},
6255 {"fmsub", A(63,28,0), A_MASK
, PPCCOM
, PPCEFS
, {FRT
, FRA
, FRC
, FRB
}},
6256 {"fms", A(63,28,0), A_MASK
, PWRCOM
, PPCNONE
, {FRT
, FRA
, FRC
, FRB
}},
6257 {"fmsub.", A(63,28,1), A_MASK
, PPCCOM
, PPCEFS
, {FRT
, FRA
, FRC
, FRB
}},
6258 {"fms.", A(63,28,1), A_MASK
, PWRCOM
, PPCNONE
, {FRT
, FRA
, FRC
, FRB
}},
6260 {"fmadd", A(63,29,0), A_MASK
, PPCCOM
, PPCEFS
, {FRT
, FRA
, FRC
, FRB
}},
6261 {"fma", A(63,29,0), A_MASK
, PWRCOM
, PPCNONE
, {FRT
, FRA
, FRC
, FRB
}},
6262 {"fmadd.", A(63,29,1), A_MASK
, PPCCOM
, PPCEFS
, {FRT
, FRA
, FRC
, FRB
}},
6263 {"fma.", A(63,29,1), A_MASK
, PWRCOM
, PPCNONE
, {FRT
, FRA
, FRC
, FRB
}},
6265 {"fnmsub", A(63,30,0), A_MASK
, PPCCOM
, PPCEFS
, {FRT
, FRA
, FRC
, FRB
}},
6266 {"fnms", A(63,30,0), A_MASK
, PWRCOM
, PPCNONE
, {FRT
, FRA
, FRC
, FRB
}},
6267 {"fnmsub.", A(63,30,1), A_MASK
, PPCCOM
, PPCEFS
, {FRT
, FRA
, FRC
, FRB
}},
6268 {"fnms.", A(63,30,1), A_MASK
, PWRCOM
, PPCNONE
, {FRT
, FRA
, FRC
, FRB
}},
6270 {"fnmadd", A(63,31,0), A_MASK
, PPCCOM
, PPCEFS
, {FRT
, FRA
, FRC
, FRB
}},
6271 {"fnma", A(63,31,0), A_MASK
, PWRCOM
, PPCNONE
, {FRT
, FRA
, FRC
, FRB
}},
6272 {"fnmadd.", A(63,31,1), A_MASK
, PPCCOM
, PPCEFS
, {FRT
, FRA
, FRC
, FRB
}},
6273 {"fnma.", A(63,31,1), A_MASK
, PWRCOM
, PPCNONE
, {FRT
, FRA
, FRC
, FRB
}},
6275 {"fcmpo", X(63,32), X_MASK
|(3<<21), COM
, PPCEFS
, {BF
, FRA
, FRB
}},
6277 {"dmulq", XRC(63,34,0), X_MASK
, POWER6
, PPCNONE
, {FRTp
, FRAp
, FRBp
}},
6278 {"dmulq.", XRC(63,34,1), X_MASK
, POWER6
, PPCNONE
, {FRTp
, FRAp
, FRBp
}},
6280 {"drrndq", ZRC(63,35,0), Z2_MASK
, POWER6
, PPCNONE
, {FRTp
, FRA
, FRBp
, RMC
}},
6281 {"drrndq.", ZRC(63,35,1), Z2_MASK
, POWER6
, PPCNONE
, {FRTp
, FRA
, FRBp
, RMC
}},
6283 {"mtfsb1", XRC(63,38,0), XRARB_MASK
, COM
, PPCNONE
, {BT
}},
6284 {"mtfsb1.", XRC(63,38,1), XRARB_MASK
, COM
, PPCNONE
, {BT
}},
6286 {"fneg", XRC(63,40,0), XRA_MASK
, COM
, PPCEFS
, {FRT
, FRB
}},
6287 {"fneg.", XRC(63,40,1), XRA_MASK
, COM
, PPCEFS
, {FRT
, FRB
}},
6289 {"mcrfs", X(63,64), XRB_MASK
|(3<<21)|(3<<16), COM
, PPCNONE
, {BF
, BFA
}},
6291 {"dscliq", ZRC(63,66,0), Z_MASK
, POWER6
, PPCNONE
, {FRTp
, FRAp
, SH16
}},
6292 {"dscliq.", ZRC(63,66,1), Z_MASK
, POWER6
, PPCNONE
, {FRTp
, FRAp
, SH16
}},
6294 {"dquaiq", ZRC(63,67,0), Z2_MASK
, POWER6
, PPCNONE
, {TE
, FRTp
, FRBp
, RMC
}},
6295 {"dquaiq.", ZRC(63,67,1), Z2_MASK
, POWER6
, PPCNONE
, {TE
, FRTp
, FRBp
, RMC
}},
6297 {"mtfsb0", XRC(63,70,0), XRARB_MASK
, COM
, PPCNONE
, {BT
}},
6298 {"mtfsb0.", XRC(63,70,1), XRARB_MASK
, COM
, PPCNONE
, {BT
}},
6300 {"fmr", XRC(63,72,0), XRA_MASK
, COM
, PPCEFS
, {FRT
, FRB
}},
6301 {"fmr.", XRC(63,72,1), XRA_MASK
, COM
, PPCEFS
, {FRT
, FRB
}},
6303 {"dscriq", ZRC(63,98,0), Z_MASK
, POWER6
, PPCNONE
, {FRTp
, FRAp
, SH16
}},
6304 {"dscriq.", ZRC(63,98,1), Z_MASK
, POWER6
, PPCNONE
, {FRTp
, FRAp
, SH16
}},
6306 {"drintxq", ZRC(63,99,0), Z2_MASK
, POWER6
, PPCNONE
, {R
, FRTp
, FRBp
, RMC
}},
6307 {"drintxq.", ZRC(63,99,1), Z2_MASK
, POWER6
, PPCNONE
, {R
, FRTp
, FRBp
, RMC
}},
6309 {"ftdiv", X(63,128), X_MASK
|(3<<21), POWER7
, PPCNONE
, {BF
, FRA
, FRB
}},
6311 {"dcmpoq", X(63,130), X_MASK
, POWER6
, PPCNONE
, {BF
, FRAp
, FRBp
}},
6313 {"mtfsfi", XRC(63,134,0), XWRA_MASK
|(3<<21)|(1<<11), POWER6
|PPCA2
|PPC476
, PPCNONE
, {BFF
, U
, W
}},
6314 {"mtfsfi", XRC(63,134,0), XRA_MASK
|(3<<21)|(1<<11), COM
, POWER6
|PPCA2
|PPC476
, {BFF
, U
}},
6315 {"mtfsfi.", XRC(63,134,1), XWRA_MASK
|(3<<21)|(1<<11), POWER6
|PPCA2
|PPC476
, PPCNONE
, {BFF
, U
, W
}},
6316 {"mtfsfi.", XRC(63,134,1), XRA_MASK
|(3<<21)|(1<<11), COM
, POWER6
|PPCA2
|PPC476
, {BFF
, U
}},
6318 {"fnabs", XRC(63,136,0), XRA_MASK
, COM
, PPCEFS
, {FRT
, FRB
}},
6319 {"fnabs.", XRC(63,136,1), XRA_MASK
, COM
, PPCEFS
, {FRT
, FRB
}},
6321 {"fctiwu", XRC(63,142,0), XRA_MASK
, POWER7
, PPCNONE
, {FRT
, FRB
}},
6322 {"fctiwu.", XRC(63,142,1), XRA_MASK
, POWER7
, PPCNONE
, {FRT
, FRB
}},
6323 {"fctiwuz", XRC(63,143,0), XRA_MASK
, POWER7
, PPCNONE
, {FRT
, FRB
}},
6324 {"fctiwuz.", XRC(63,143,1), XRA_MASK
, POWER7
, PPCNONE
, {FRT
, FRB
}},
6326 {"ftsqrt", X(63,160), X_MASK
|(3<<21|FRA_MASK
), POWER7
, PPCNONE
, {BF
, FRB
}},
6328 {"dtstexq", X(63,162), X_MASK
, POWER6
, PPCNONE
, {BF
, FRAp
, FRBp
}},
6329 {"dtstdcq", Z(63,194), Z_MASK
, POWER6
, PPCNONE
, {BF
, FRAp
, DCM
}},
6330 {"dtstdgq", Z(63,226), Z_MASK
, POWER6
, PPCNONE
, {BF
, FRAp
, DGM
}},
6332 {"drintnq", ZRC(63,227,0), Z2_MASK
, POWER6
, PPCNONE
, {R
, FRTp
, FRBp
, RMC
}},
6333 {"drintnq.", ZRC(63,227,1), Z2_MASK
, POWER6
, PPCNONE
, {R
, FRTp
, FRBp
, RMC
}},
6335 {"dctqpq", XRC(63,258,0), X_MASK
, POWER6
, PPCNONE
, {FRTp
, FRB
}},
6336 {"dctqpq.", XRC(63,258,1), X_MASK
, POWER6
, PPCNONE
, {FRTp
, FRB
}},
6338 {"fabs", XRC(63,264,0), XRA_MASK
, COM
, PPCEFS
, {FRT
, FRB
}},
6339 {"fabs.", XRC(63,264,1), XRA_MASK
, COM
, PPCEFS
, {FRT
, FRB
}},
6341 {"dctfixq", XRC(63,290,0), X_MASK
, POWER6
, PPCNONE
, {FRT
, FRBp
}},
6342 {"dctfixq.", XRC(63,290,1), X_MASK
, POWER6
, PPCNONE
, {FRT
, FRBp
}},
6344 {"ddedpdq", XRC(63,322,0), X_MASK
, POWER6
, PPCNONE
, {SP
, FRTp
, FRBp
}},
6345 {"ddedpdq.", XRC(63,322,1), X_MASK
, POWER6
, PPCNONE
, {SP
, FRTp
, FRBp
}},
6347 {"dxexq", XRC(63,354,0), X_MASK
, POWER6
, PPCNONE
, {FRT
, FRBp
}},
6348 {"dxexq.", XRC(63,354,1), X_MASK
, POWER6
, PPCNONE
, {FRT
, FRBp
}},
6350 {"frin", XRC(63,392,0), XRA_MASK
, POWER5
, PPCNONE
, {FRT
, FRB
}},
6351 {"frin.", XRC(63,392,1), XRA_MASK
, POWER5
, PPCNONE
, {FRT
, FRB
}},
6352 {"friz", XRC(63,424,0), XRA_MASK
, POWER5
, PPCNONE
, {FRT
, FRB
}},
6353 {"friz.", XRC(63,424,1), XRA_MASK
, POWER5
, PPCNONE
, {FRT
, FRB
}},
6354 {"frip", XRC(63,456,0), XRA_MASK
, POWER5
, PPCNONE
, {FRT
, FRB
}},
6355 {"frip.", XRC(63,456,1), XRA_MASK
, POWER5
, PPCNONE
, {FRT
, FRB
}},
6356 {"frim", XRC(63,488,0), XRA_MASK
, POWER5
, PPCNONE
, {FRT
, FRB
}},
6357 {"frim.", XRC(63,488,1), XRA_MASK
, POWER5
, PPCNONE
, {FRT
, FRB
}},
6359 {"dsubq", XRC(63,514,0), X_MASK
, POWER6
, PPCNONE
, {FRTp
, FRAp
, FRBp
}},
6360 {"dsubq.", XRC(63,514,1), X_MASK
, POWER6
, PPCNONE
, {FRTp
, FRAp
, FRBp
}},
6362 {"ddivq", XRC(63,546,0), X_MASK
, POWER6
, PPCNONE
, {FRTp
, FRAp
, FRBp
}},
6363 {"ddivq.", XRC(63,546,1), X_MASK
, POWER6
, PPCNONE
, {FRTp
, FRAp
, FRBp
}},
6365 {"mffs", XRC(63,583,0), XRARB_MASK
, COM
, PPCEFS
, {FRT
}},
6366 {"mffs.", XRC(63,583,1), XRARB_MASK
, COM
, PPCEFS
, {FRT
}},
6368 {"dcmpuq", X(63,642), X_MASK
, POWER6
, PPCNONE
, {BF
, FRAp
, FRBp
}},
6370 {"dtstsfq", X(63,674), X_MASK
, POWER6
, PPCNONE
, {BF
, FRA
, FRBp
}},
6372 {"mtfsf", XFL(63,711,0), XFL_MASK
, POWER6
|PPCA2
|PPC476
, PPCNONE
, {FLM
, FRB
, XFL_L
, W
}},
6373 {"mtfsf", XFL(63,711,0), XFL_MASK
, COM
, POWER6
|PPCA2
|PPC476
|PPCEFS
, {FLM
, FRB
}},
6374 {"mtfsf.", XFL(63,711,1), XFL_MASK
, POWER6
|PPCA2
|PPC476
, PPCNONE
, {FLM
, FRB
, XFL_L
, W
}},
6375 {"mtfsf.", XFL(63,711,1), XFL_MASK
, COM
, POWER6
|PPCA2
|PPC476
|PPCEFS
, {FLM
, FRB
}},
6377 {"drdpq", XRC(63,770,0), X_MASK
, POWER6
, PPCNONE
, {FRTp
, FRBp
}},
6378 {"drdpq.", XRC(63,770,1), X_MASK
, POWER6
, PPCNONE
, {FRTp
, FRBp
}},
6380 {"dcffixq", XRC(63,802,0), X_MASK
, POWER6
, PPCNONE
, {FRTp
, FRB
}},
6381 {"dcffixq.", XRC(63,802,1), X_MASK
, POWER6
, PPCNONE
, {FRTp
, FRB
}},
6383 {"fctid", XRC(63,814,0), XRA_MASK
, PPC64
, PPCNONE
, {FRT
, FRB
}},
6384 {"fctid", XRC(63,814,0), XRA_MASK
, PPC476
, PPCNONE
, {FRT
, FRB
}},
6385 {"fctid.", XRC(63,814,1), XRA_MASK
, PPC64
, PPCNONE
, {FRT
, FRB
}},
6386 {"fctid.", XRC(63,814,1), XRA_MASK
, PPC476
, PPCNONE
, {FRT
, FRB
}},
6388 {"fctidz", XRC(63,815,0), XRA_MASK
, PPC64
, PPCNONE
, {FRT
, FRB
}},
6389 {"fctidz", XRC(63,815,0), XRA_MASK
, PPC476
, PPCNONE
, {FRT
, FRB
}},
6390 {"fctidz.", XRC(63,815,1), XRA_MASK
, PPC64
, PPCNONE
, {FRT
, FRB
}},
6391 {"fctidz.", XRC(63,815,1), XRA_MASK
, PPC476
, PPCNONE
, {FRT
, FRB
}},
6393 {"denbcdq", XRC(63,834,0), X_MASK
, POWER6
, PPCNONE
, {S
, FRTp
, FRBp
}},
6394 {"denbcdq.", XRC(63,834,1), X_MASK
, POWER6
, PPCNONE
, {S
, FRTp
, FRBp
}},
6396 {"fmrgow", X(63,838), X_MASK
, PPCVSX2
, PPCNONE
, {FRT
, FRA
, FRB
}},
6398 {"fcfid", XRC(63,846,0), XRA_MASK
, PPC64
, PPCNONE
, {FRT
, FRB
}},
6399 {"fcfid", XRC(63,846,0), XRA_MASK
, PPC476
, PPCNONE
, {FRT
, FRB
}},
6400 {"fcfid.", XRC(63,846,1), XRA_MASK
, PPC64
, PPCNONE
, {FRT
, FRB
}},
6401 {"fcfid.", XRC(63,846,1), XRA_MASK
, PPC476
, PPCNONE
, {FRT
, FRB
}},
6403 {"diexq", XRC(63,866,0), X_MASK
, POWER6
, PPCNONE
, {FRTp
, FRA
, FRBp
}},
6404 {"diexq.", XRC(63,866,1), X_MASK
, POWER6
, PPCNONE
, {FRTp
, FRA
, FRBp
}},
6406 {"fctidu", XRC(63,942,0), XRA_MASK
, POWER7
|PPCA2
, PPCNONE
, {FRT
, FRB
}},
6407 {"fctidu.", XRC(63,942,1), XRA_MASK
, POWER7
|PPCA2
, PPCNONE
, {FRT
, FRB
}},
6409 {"fctiduz", XRC(63,943,0), XRA_MASK
, POWER7
|PPCA2
, PPCNONE
, {FRT
, FRB
}},
6410 {"fctiduz.", XRC(63,943,1), XRA_MASK
, POWER7
|PPCA2
, PPCNONE
, {FRT
, FRB
}},
6412 {"fmrgew", X(63,966), X_MASK
, PPCVSX2
, PPCNONE
, {FRT
, FRA
, FRB
}},
6414 {"fcfidu", XRC(63,974,0), XRA_MASK
, POWER7
|PPCA2
, PPCNONE
, {FRT
, FRB
}},
6415 {"fcfidu.", XRC(63,974,1), XRA_MASK
, POWER7
|PPCA2
, PPCNONE
, {FRT
, FRB
}},
6418 const int powerpc_num_opcodes
=
6419 sizeof (powerpc_opcodes
) / sizeof (powerpc_opcodes
[0]);
6421 /* The VLE opcode table.
6423 The format of this opcode table is the same as the main opcode table. */
6425 const struct powerpc_opcode vle_opcodes
[] = {
6427 {"se_illegal", C(0), C_MASK
, PPCVLE
, PPCNONE
, {}},
6428 {"se_isync", C(1), C_MASK
, PPCVLE
, PPCNONE
, {}},
6429 {"se_sc", C(2), C_MASK
, PPCVLE
, PPCNONE
, {}},
6430 {"se_blr", C_LK(2,0), C_LK_MASK
, PPCVLE
, PPCNONE
, {}},
6431 {"se_blrl", C_LK(2,1), C_LK_MASK
, PPCVLE
, PPCNONE
, {}},
6432 {"se_bctr", C_LK(3,0), C_LK_MASK
, PPCVLE
, PPCNONE
, {}},
6433 {"se_bctrl", C_LK(3,1), C_LK_MASK
, PPCVLE
, PPCNONE
, {}},
6434 {"se_rfi", C(8), C_MASK
, PPCVLE
, PPCNONE
, {}},
6435 {"se_rfci", C(9), C_MASK
, PPCVLE
, PPCNONE
, {}},
6436 {"se_rfdi", C(10), C_MASK
, PPCVLE
, PPCNONE
, {}},
6437 {"se_rfmci", C(11), C_MASK
, PPCVLE
, PPCNONE
, {}},
6438 {"se_not", SE_R(0,2), SE_R_MASK
, PPCVLE
, PPCNONE
, {RX
}},
6439 {"se_neg", SE_R(0,3), SE_R_MASK
, PPCVLE
, PPCNONE
, {RX
}},
6440 {"se_mflr", SE_R(0,8), SE_R_MASK
, PPCVLE
, PPCNONE
, {RX
}},
6441 {"se_mtlr", SE_R(0,9), SE_R_MASK
, PPCVLE
, PPCNONE
, {RX
}},
6442 {"se_mfctr", SE_R(0,10), SE_R_MASK
, PPCVLE
, PPCNONE
, {RX
}},
6443 {"se_mtctr", SE_R(0,11), SE_R_MASK
, PPCVLE
, PPCNONE
, {RX
}},
6444 {"se_extzb", SE_R(0,12), SE_R_MASK
, PPCVLE
, PPCNONE
, {RX
}},
6445 {"se_extsb", SE_R(0,13), SE_R_MASK
, PPCVLE
, PPCNONE
, {RX
}},
6446 {"se_extzh", SE_R(0,14), SE_R_MASK
, PPCVLE
, PPCNONE
, {RX
}},
6447 {"se_extsh", SE_R(0,15), SE_R_MASK
, PPCVLE
, PPCNONE
, {RX
}},
6448 {"se_mr", SE_RR(0,1), SE_RR_MASK
, PPCVLE
, PPCNONE
, {RX
, RY
}},
6449 {"se_mtar", SE_RR(0,2), SE_RR_MASK
, PPCVLE
, PPCNONE
, {ARX
, RY
}},
6450 {"se_mfar", SE_RR(0,3), SE_RR_MASK
, PPCVLE
, PPCNONE
, {RX
, ARY
}},
6451 {"se_add", SE_RR(1,0), SE_RR_MASK
, PPCVLE
, PPCNONE
, {RX
, RY
}},
6452 {"se_mullw", SE_RR(1,1), SE_RR_MASK
, PPCVLE
, PPCNONE
, {RX
, RY
}},
6453 {"se_sub", SE_RR(1,2), SE_RR_MASK
, PPCVLE
, PPCNONE
, {RX
, RY
}},
6454 {"se_subf", SE_RR(1,3), SE_RR_MASK
, PPCVLE
, PPCNONE
, {RX
, RY
}},
6455 {"se_cmp", SE_RR(3,0), SE_RR_MASK
, PPCVLE
, PPCNONE
, {RX
, RY
}},
6456 {"se_cmpl", SE_RR(3,1), SE_RR_MASK
, PPCVLE
, PPCNONE
, {RX
, RY
}},
6457 {"se_cmph", SE_RR(3,2), SE_RR_MASK
, PPCVLE
, PPCNONE
, {RX
, RY
}},
6458 {"se_cmphl", SE_RR(3,3), SE_RR_MASK
, PPCVLE
, PPCNONE
, {RX
, RY
}},
6460 {"e_cmpi", SCI8BF(6,0,21), SCI8BF_MASK
, PPCVLE
, PPCNONE
, {CRD32
, RA
, SCLSCI8
}},
6461 {"e_cmpli", SCI8BF(6,1,21), SCI8BF_MASK
, PPCVLE
, PPCNONE
, {CRD32
, RA
, SCLSCI8
}},
6462 {"e_addi", SCI8(6,16), SCI8_MASK
, PPCVLE
, PPCNONE
, {RT
, RA
, SCLSCI8
}},
6463 {"e_subi", SCI8(6,16), SCI8_MASK
, PPCVLE
, PPCNONE
, {RT
, RA
, SCLSCI8N
}},
6464 {"e_addi.", SCI8(6,17), SCI8_MASK
, PPCVLE
, PPCNONE
, {RT
, RA
, SCLSCI8
}},
6465 {"e_addic", SCI8(6,18), SCI8_MASK
, PPCVLE
, PPCNONE
, {RT
, RA
, SCLSCI8
}},
6466 {"e_subic", SCI8(6,18), SCI8_MASK
, PPCVLE
, PPCNONE
, {RT
, RA
, SCLSCI8N
}},
6467 {"e_addic.", SCI8(6,19), SCI8_MASK
, PPCVLE
, PPCNONE
, {RT
, RA
, SCLSCI8
}},
6468 {"e_subic.", SCI8(6,19), SCI8_MASK
, PPCVLE
, PPCNONE
, {RT
, RA
, SCLSCI8N
}},
6469 {"e_mulli", SCI8(6,20), SCI8_MASK
, PPCVLE
, PPCNONE
, {RT
, RA
, SCLSCI8
}},
6470 {"e_subfic", SCI8(6,22), SCI8_MASK
, PPCVLE
, PPCNONE
, {RT
, RA
, SCLSCI8
}},
6471 {"e_subfic.", SCI8(6,23), SCI8_MASK
, PPCVLE
, PPCNONE
, {RT
, RA
, SCLSCI8
}},
6472 {"e_andi", SCI8(6,24), SCI8_MASK
, PPCVLE
, PPCNONE
, {RA
, RS
, SCLSCI8
}},
6473 {"e_andi.", SCI8(6,25), SCI8_MASK
, PPCVLE
, PPCNONE
, {RA
, RS
, SCLSCI8
}},
6474 {"e_nop", SCI8(6,26), 0xffffffff, PPCVLE
, PPCNONE
, {0}},
6475 {"e_ori", SCI8(6,26), SCI8_MASK
, PPCVLE
, PPCNONE
, {RA
, RS
, SCLSCI8
}},
6476 {"e_ori.", SCI8(6,27), SCI8_MASK
, PPCVLE
, PPCNONE
, {RA
, RS
, SCLSCI8
}},
6477 {"e_xori", SCI8(6,28), SCI8_MASK
, PPCVLE
, PPCNONE
, {RA
, RS
, SCLSCI8
}},
6478 {"e_xori.", SCI8(6,29), SCI8_MASK
, PPCVLE
, PPCNONE
, {RA
, RS
, SCLSCI8
}},
6479 {"e_lbzu", OPVUP(6,0), OPVUP_MASK
, PPCVLE
, PPCNONE
, {RT
, D8
, RA0
}},
6480 {"e_lhau", OPVUP(6,3), OPVUP_MASK
, PPCVLE
, PPCNONE
, {RT
, D8
, RA0
}},
6481 {"e_lhzu", OPVUP(6,1), OPVUP_MASK
, PPCVLE
, PPCNONE
, {RT
, D8
, RA0
}},
6482 {"e_lmw", OPVUP(6,8), OPVUP_MASK
, PPCVLE
, PPCNONE
, {RT
, D8
, RA0
}},
6483 {"e_lwzu", OPVUP(6,2), OPVUP_MASK
, PPCVLE
, PPCNONE
, {RT
, D8
, RA0
}},
6484 {"e_stbu", OPVUP(6,4), OPVUP_MASK
, PPCVLE
, PPCNONE
, {RT
, D8
, RA0
}},
6485 {"e_sthu", OPVUP(6,5), OPVUP_MASK
, PPCVLE
, PPCNONE
, {RT
, D8
, RA0
}},
6486 {"e_stwu", OPVUP(6,6), OPVUP_MASK
, PPCVLE
, PPCNONE
, {RT
, D8
, RA0
}},
6487 {"e_stmw", OPVUP(6,9), OPVUP_MASK
, PPCVLE
, PPCNONE
, {RT
, D8
, RA0
}},
6488 {"e_add16i", OP(7), OP_MASK
, PPCVLE
, PPCNONE
, {RT
, RA
, SI
}},
6489 {"e_la", OP(7), OP_MASK
, PPCVLE
, PPCNONE
, {RT
, D
, RA0
}},
6490 {"e_sub16i", OP(7), OP_MASK
, PPCVLE
, PPCNONE
, {RT
, RA
, NSI
}},
6492 {"se_addi", SE_IM5(8,0), SE_IM5_MASK
, PPCVLE
, PPCNONE
, {RX
, OIMM5
}},
6493 {"se_cmpli", SE_IM5(8,1), SE_IM5_MASK
, PPCVLE
, PPCNONE
, {RX
, OIMM5
}},
6494 {"se_subi", SE_IM5(9,0), SE_IM5_MASK
, PPCVLE
, PPCNONE
, {RX
, OIMM5
}},
6495 {"se_subi.", SE_IM5(9,1), SE_IM5_MASK
, PPCVLE
, PPCNONE
, {RX
, OIMM5
}},
6496 {"se_cmpi", SE_IM5(10,1), SE_IM5_MASK
, PPCVLE
, PPCNONE
, {RX
, UI5
}},
6497 {"se_bmaski", SE_IM5(11,0), SE_IM5_MASK
, PPCVLE
, PPCNONE
, {RX
, UI5
}},
6498 {"se_andi", SE_IM5(11,1), SE_IM5_MASK
, PPCVLE
, PPCNONE
, {RX
, UI5
}},
6500 {"e_lbz", OP(12), OP_MASK
, PPCVLE
, PPCNONE
, {RT
, D
, RA0
}},
6501 {"e_stb", OP(13), OP_MASK
, PPCVLE
, PPCNONE
, {RT
, D
, RA0
}},
6502 {"e_lha", OP(14), OP_MASK
, PPCVLE
, PPCNONE
, {RT
, D
, RA0
}},
6504 {"se_srw", SE_RR(16,0), SE_RR_MASK
, PPCVLE
, PPCNONE
, {RX
, RY
}},
6505 {"se_sraw", SE_RR(16,1), SE_RR_MASK
, PPCVLE
, PPCNONE
, {RX
, RY
}},
6506 {"se_slw", SE_RR(16,2), SE_RR_MASK
, PPCVLE
, PPCNONE
, {RX
, RY
}},
6507 {"se_nop", SE_RR(17,0), 0xffff, PPCVLE
, PPCNONE
, {0}},
6508 {"se_or", SE_RR(17,0), SE_RR_MASK
, PPCVLE
, PPCNONE
, {RX
, RY
}},
6509 {"se_andc", SE_RR(17,1), SE_RR_MASK
, PPCVLE
, PPCNONE
, {RX
, RY
}},
6510 {"se_and", SE_RR(17,2), SE_RR_MASK
, PPCVLE
, PPCNONE
, {RX
, RY
}},
6511 {"se_and.", SE_RR(17,3), SE_RR_MASK
, PPCVLE
, PPCNONE
, {RX
, RY
}},
6512 {"se_li", IM7(9), IM7_MASK
, PPCVLE
, PPCNONE
, {RX
, UI7
}},
6514 {"e_lwz", OP(20), OP_MASK
, PPCVLE
, PPCNONE
, {RT
, D
, RA0
}},
6515 {"e_stw", OP(21), OP_MASK
, PPCVLE
, PPCNONE
, {RT
, D
, RA0
}},
6516 {"e_lhz", OP(22), OP_MASK
, PPCVLE
, PPCNONE
, {RT
, D
, RA0
}},
6517 {"e_sth", OP(23), OP_MASK
, PPCVLE
, PPCNONE
, {RT
, D
, RA0
}},
6519 {"se_bclri", SE_IM5(24,0), SE_IM5_MASK
, PPCVLE
, PPCNONE
, {RX
, UI5
}},
6520 {"se_bgeni", SE_IM5(24,1), SE_IM5_MASK
, PPCVLE
, PPCNONE
, {RX
, UI5
}},
6521 {"se_bseti", SE_IM5(25,0), SE_IM5_MASK
, PPCVLE
, PPCNONE
, {RX
, UI5
}},
6522 {"se_btsti", SE_IM5(25,1), SE_IM5_MASK
, PPCVLE
, PPCNONE
, {RX
, UI5
}},
6523 {"se_srwi", SE_IM5(26,0), SE_IM5_MASK
, PPCVLE
, PPCNONE
, {RX
, UI5
}},
6524 {"se_srawi", SE_IM5(26,1), SE_IM5_MASK
, PPCVLE
, PPCNONE
, {RX
, UI5
}},
6525 {"se_slwi", SE_IM5(27,0), SE_IM5_MASK
, PPCVLE
, PPCNONE
, {RX
, UI5
}},
6527 {"e_lis", I16L(28,28), I16L_MASK
, PPCVLE
, PPCNONE
, {RD
, VLEUIMML
}},
6528 {"e_and2is.", I16L(28,29), I16L_MASK
, PPCVLE
, PPCNONE
, {RD
, VLEUIMML
}},
6529 {"e_or2is", I16L(28,26), I16L_MASK
, PPCVLE
, PPCNONE
, {RD
, VLEUIMML
}},
6530 {"e_and2i.", I16L(28,25), I16L_MASK
, PPCVLE
, PPCNONE
, {RD
, VLEUIMML
}},
6531 {"e_or2i", I16L(28,24), I16L_MASK
, PPCVLE
, PPCNONE
, {RD
, VLEUIMML
}},
6532 {"e_cmphl16i", IA16(28,23), IA16_MASK
, PPCVLE
, PPCNONE
, {RA
, VLEUIMM
}},
6533 {"e_cmph16i", IA16(28,22), IA16_MASK
, PPCVLE
, PPCNONE
, {RA
, VLESIMM
}},
6534 {"e_cmpl16i", I16A(28,21), I16A_MASK
, PPCVLE
, PPCNONE
, {RA
, VLEUIMM
}},
6535 {"e_cmplwi", I16A(28,21), I16A_MASK
, PPCVLE
, PPCNONE
, {RA
, VLESIMM
}},
6536 {"e_mull2i", I16A(28,20), I16A_MASK
, PPCVLE
, PPCNONE
, {RA
, VLESIMM
}},
6537 {"e_cmp16i", IA16(28,19), IA16_MASK
, PPCVLE
, PPCNONE
, {RA
, VLESIMM
}},
6538 {"e_cmpwi", IA16(28,19), IA16_MASK
, PPCVLE
, PPCNONE
, {RA
, VLESIMM
}},
6539 {"e_sub2is", I16A(28,18), I16A_MASK
, PPCVLE
, PPCNONE
, {RA
, VLENSIMM
}},
6540 {"e_add2is", I16A(28,18), I16A_MASK
, PPCVLE
, PPCNONE
, {RA
, VLESIMM
}},
6541 {"e_sub2i.", I16A(28,17), I16A_MASK
, PPCVLE
, PPCNONE
, {RA
, VLENSIMM
}},
6542 {"e_add2i.", I16A(28,17), I16A_MASK
, PPCVLE
, PPCNONE
, {RA
, VLESIMM
}},
6543 {"e_li", LI20(28,0), LI20_MASK
, PPCVLE
, PPCNONE
, {RT
, IMM20
}},
6544 {"e_rlwimi", M(29,0), M_MASK
, PPCVLE
, PPCNONE
, {RA
, RS
, SH
, MB
, ME
}},
6545 {"e_rlwinm", M(29,1), M_MASK
, PPCVLE
, PPCNONE
, {RA
, RT
, SH
, MBE
, ME
}},
6546 {"e_b", BD24(30,0,0), BD24_MASK
, PPCVLE
, PPCNONE
, {B24
}},
6547 {"e_bl", BD24(30,0,1), BD24_MASK
, PPCVLE
, PPCNONE
, {B24
}},
6548 {"e_bdnz", EBD15(30,8,BO32DNZ
,0), EBD15_MASK
, PPCVLE
, PPCNONE
, {B15
}},
6549 {"e_bdnzl", EBD15(30,8,BO32DNZ
,1), EBD15_MASK
, PPCVLE
, PPCNONE
, {B15
}},
6550 {"e_bdz", EBD15(30,8,BO32DZ
,0), EBD15_MASK
, PPCVLE
, PPCNONE
, {B15
}},
6551 {"e_bdzl", EBD15(30,8,BO32DZ
,1), EBD15_MASK
, PPCVLE
, PPCNONE
, {B15
}},
6552 {"e_bge", EBD15BI(30,8,BO32F
,CBLT
,0), EBD15BI_MASK
, PPCVLE
, PPCNONE
, {CRS
,B15
}},
6553 {"e_bgel", EBD15BI(30,8,BO32F
,CBLT
,1), EBD15BI_MASK
, PPCVLE
, PPCNONE
, {CRS
,B15
}},
6554 {"e_bnl", EBD15BI(30,8,BO32F
,CBLT
,0), EBD15BI_MASK
, PPCVLE
, PPCNONE
, {CRS
,B15
}},
6555 {"e_bnll", EBD15BI(30,8,BO32F
,CBLT
,1), EBD15BI_MASK
, PPCVLE
, PPCNONE
, {CRS
,B15
}},
6556 {"e_blt", EBD15BI(30,8,BO32T
,CBLT
,0), EBD15BI_MASK
, PPCVLE
, PPCNONE
, {CRS
,B15
}},
6557 {"e_bltl", EBD15BI(30,8,BO32T
,CBLT
,1), EBD15BI_MASK
, PPCVLE
, PPCNONE
, {CRS
,B15
}},
6558 {"e_bgt", EBD15BI(30,8,BO32T
,CBGT
,0), EBD15BI_MASK
, PPCVLE
, PPCNONE
, {CRS
,B15
}},
6559 {"e_bgtl", EBD15BI(30,8,BO32T
,CBGT
,1), EBD15BI_MASK
, PPCVLE
, PPCNONE
, {CRS
,B15
}},
6560 {"e_ble", EBD15BI(30,8,BO32F
,CBGT
,0), EBD15BI_MASK
, PPCVLE
, PPCNONE
, {CRS
,B15
}},
6561 {"e_blel", EBD15BI(30,8,BO32F
,CBGT
,1), EBD15BI_MASK
, PPCVLE
, PPCNONE
, {CRS
,B15
}},
6562 {"e_bng", EBD15BI(30,8,BO32F
,CBGT
,0), EBD15BI_MASK
, PPCVLE
, PPCNONE
, {CRS
,B15
}},
6563 {"e_bngl", EBD15BI(30,8,BO32F
,CBGT
,1), EBD15BI_MASK
, PPCVLE
, PPCNONE
, {CRS
,B15
}},
6564 {"e_bne", EBD15BI(30,8,BO32F
,CBEQ
,0), EBD15BI_MASK
, PPCVLE
, PPCNONE
, {CRS
,B15
}},
6565 {"e_bnel", EBD15BI(30,8,BO32F
,CBEQ
,1), EBD15BI_MASK
, PPCVLE
, PPCNONE
, {CRS
,B15
}},
6566 {"e_beq", EBD15BI(30,8,BO32T
,CBEQ
,0), EBD15BI_MASK
, PPCVLE
, PPCNONE
, {CRS
,B15
}},
6567 {"e_beql", EBD15BI(30,8,BO32T
,CBEQ
,1), EBD15BI_MASK
, PPCVLE
, PPCNONE
, {CRS
,B15
}},
6568 {"e_bso", EBD15BI(30,8,BO32T
,CBSO
,0), EBD15BI_MASK
, PPCVLE
, PPCNONE
, {CRS
,B15
}},
6569 {"e_bsol", EBD15BI(30,8,BO32T
,CBSO
,1), EBD15BI_MASK
, PPCVLE
, PPCNONE
, {CRS
,B15
}},
6570 {"e_bun", EBD15BI(30,8,BO32T
,CBSO
,0), EBD15BI_MASK
, PPCVLE
, PPCNONE
, {CRS
,B15
}},
6571 {"e_bunl", EBD15BI(30,8,BO32T
,CBSO
,1), EBD15BI_MASK
, PPCVLE
, PPCNONE
, {CRS
,B15
}},
6572 {"e_bns", EBD15BI(30,8,BO32F
,CBSO
,0), EBD15BI_MASK
, PPCVLE
, PPCNONE
, {CRS
,B15
}},
6573 {"e_bnsl", EBD15BI(30,8,BO32F
,CBSO
,1), EBD15BI_MASK
, PPCVLE
, PPCNONE
, {CRS
,B15
}},
6574 {"e_bnu", EBD15BI(30,8,BO32F
,CBSO
,0), EBD15BI_MASK
, PPCVLE
, PPCNONE
, {CRS
,B15
}},
6575 {"e_bnul", EBD15BI(30,8,BO32F
,CBSO
,1), EBD15BI_MASK
, PPCVLE
, PPCNONE
, {CRS
,B15
}},
6576 {"e_bc", BD15(30,8,0), BD15_MASK
, PPCVLE
, PPCNONE
, {BO32
, BI32
, B15
}},
6577 {"e_bcl", BD15(30,8,1), BD15_MASK
, PPCVLE
, PPCNONE
, {BO32
, BI32
, B15
}},
6579 {"e_bf", EBD15(30,8,BO32F
,0), EBD15_MASK
, PPCVLE
, PPCNONE
, {BI32
,B15
}},
6580 {"e_bfl", EBD15(30,8,BO32F
,1), EBD15_MASK
, PPCVLE
, PPCNONE
, {BI32
,B15
}},
6581 {"e_bt", EBD15(30,8,BO32T
,0), EBD15_MASK
, PPCVLE
, PPCNONE
, {BI32
,B15
}},
6582 {"e_btl", EBD15(30,8,BO32T
,1), EBD15_MASK
, PPCVLE
, PPCNONE
, {BI32
,B15
}},
6584 {"e_cmph", X(31,14), X_MASK
, PPCVLE
, PPCNONE
, {CRD
, RA
, RB
}},
6585 {"e_cmphl", X(31,46), X_MASK
, PPCVLE
, PPCNONE
, {CRD
, RA
, RB
}},
6586 {"e_crandc", XL(31,129), XL_MASK
, PPCVLE
, PPCNONE
, {BT
, BA
, BB
}},
6587 {"e_crnand", XL(31,225), XL_MASK
, PPCVLE
, PPCNONE
, {BT
, BA
, BB
}},
6588 {"e_crnot", XL(31,33), XL_MASK
, PPCVLE
, PPCNONE
, {BT
, BA
, BBA
}},
6589 {"e_crnor", XL(31,33), XL_MASK
, PPCVLE
, PPCNONE
, {BT
, BA
, BB
}},
6590 {"e_crclr", XL(31,193), XL_MASK
, PPCVLE
, PPCNONE
, {BT
, BAT
, BBA
}},
6591 {"e_crxor", XL(31,193), XL_MASK
, PPCVLE
, PPCNONE
, {BT
, BA
, BB
}},
6592 {"e_mcrf", XL(31,16), XL_MASK
, PPCVLE
, PPCNONE
, {CRD
, CR
}},
6593 {"e_slwi", EX(31,112), EX_MASK
, PPCVLE
, PPCNONE
, {RA
, RS
, SH
}},
6594 {"e_slwi.", EX(31,113), EX_MASK
, PPCVLE
, PPCNONE
, {RA
, RS
, SH
}},
6596 {"e_crand", XL(31,257), XL_MASK
, PPCVLE
, PPCNONE
, {BT
, BA
, BB
}},
6598 {"e_rlw", EX(31,560), EX_MASK
, PPCVLE
, PPCNONE
, {RA
, RS
, RB
}},
6599 {"e_rlw.", EX(31,561), EX_MASK
, PPCVLE
, PPCNONE
, {RA
, RS
, RB
}},
6601 {"e_crset", XL(31,289), XL_MASK
, PPCVLE
, PPCNONE
, {BT
, BAT
, BBA
}},
6602 {"e_creqv", XL(31,289), XL_MASK
, PPCVLE
, PPCNONE
, {BT
, BA
, BB
}},
6604 {"e_rlwi", EX(31,624), EX_MASK
, PPCVLE
, PPCNONE
, {RA
, RS
, SH
}},
6605 {"e_rlwi.", EX(31,625), EX_MASK
, PPCVLE
, PPCNONE
, {RA
, RS
, SH
}},
6607 {"e_crorc", XL(31,417), XL_MASK
, PPCVLE
, PPCNONE
, {BT
, BA
, BB
}},
6609 {"e_crmove", XL(31,449), XL_MASK
, PPCVLE
, PPCNONE
, {BT
, BA
, BBA
}},
6610 {"e_cror", XL(31,449), XL_MASK
, PPCVLE
, PPCNONE
, {BT
, BA
, BB
}},
6612 {"mtmas1", XSPR(31,467,625), XSPR_MASK
, PPCVLE
, PPCNONE
, {RS
}},
6614 {"e_srwi", EX(31,1136), EX_MASK
, PPCVLE
, PPCNONE
, {RA
, RS
, SH
}},
6615 {"e_srwi.", EX(31,1137), EX_MASK
, PPCVLE
, PPCNONE
, {RA
, RS
, SH
}},
6617 {"se_lbz", SD4(8), SD4_MASK
, PPCVLE
, PPCNONE
, {RZ
, SE_SD
, RX
}},
6619 {"se_stb", SD4(9), SD4_MASK
, PPCVLE
, PPCNONE
, {RZ
, SE_SD
, RX
}},
6621 {"se_lhz", SD4(10), SD4_MASK
, PPCVLE
, PPCNONE
, {RZ
, SE_SDH
, RX
}},
6623 {"se_sth", SD4(11), SD4_MASK
, PPCVLE
, PPCNONE
, {RZ
, SE_SDH
, RX
}},
6625 {"se_lwz", SD4(12), SD4_MASK
, PPCVLE
, PPCNONE
, {RZ
, SE_SDW
, RX
}},
6627 {"se_stw", SD4(13), SD4_MASK
, PPCVLE
, PPCNONE
, {RZ
, SE_SDW
, RX
}},
6629 {"se_bge", EBD8IO(28,0,0), EBD8IO3_MASK
, PPCVLE
, PPCNONE
, {B8
}},
6630 {"se_bnl", EBD8IO(28,0,0), EBD8IO3_MASK
, PPCVLE
, PPCNONE
, {B8
}},
6631 {"se_ble", EBD8IO(28,0,1), EBD8IO3_MASK
, PPCVLE
, PPCNONE
, {B8
}},
6632 {"se_bng", EBD8IO(28,0,1), EBD8IO3_MASK
, PPCVLE
, PPCNONE
, {B8
}},
6633 {"se_bne", EBD8IO(28,0,2), EBD8IO3_MASK
, PPCVLE
, PPCNONE
, {B8
}},
6634 {"se_bns", EBD8IO(28,0,3), EBD8IO3_MASK
, PPCVLE
, PPCNONE
, {B8
}},
6635 {"se_bnu", EBD8IO(28,0,3), EBD8IO3_MASK
, PPCVLE
, PPCNONE
, {B8
}},
6636 {"se_bf", EBD8IO(28,0,0), EBD8IO2_MASK
, PPCVLE
, PPCNONE
, {BI16
, B8
}},
6637 {"se_blt", EBD8IO(28,1,0), EBD8IO3_MASK
, PPCVLE
, PPCNONE
, {B8
}},
6638 {"se_bgt", EBD8IO(28,1,1), EBD8IO3_MASK
, PPCVLE
, PPCNONE
, {B8
}},
6639 {"se_beq", EBD8IO(28,1,2), EBD8IO3_MASK
, PPCVLE
, PPCNONE
, {B8
}},
6640 {"se_bso", EBD8IO(28,1,3), EBD8IO3_MASK
, PPCVLE
, PPCNONE
, {B8
}},
6641 {"se_bun", EBD8IO(28,1,3), EBD8IO3_MASK
, PPCVLE
, PPCNONE
, {B8
}},
6642 {"se_bt", EBD8IO(28,1,0), EBD8IO2_MASK
, PPCVLE
, PPCNONE
, {BI16
, B8
}},
6643 {"se_bc", BD8IO(28), BD8IO_MASK
, PPCVLE
, PPCNONE
, {BO16
, BI16
, B8
}},
6644 {"se_b", BD8(58,0,0), BD8_MASK
, PPCVLE
, PPCNONE
, {B8
}},
6645 {"se_bl", BD8(58,0,1), BD8_MASK
, PPCVLE
, PPCNONE
, {B8
}},
6648 const int vle_num_opcodes
=
6649 sizeof (vle_opcodes
) / sizeof (vle_opcodes
[0]);
6651 /* The macro table. This is only used by the assembler. */
6653 /* The expressions of the form (-x ! 31) & (x | 31) have the value 0
6654 when x=0; 32-x when x is between 1 and 31; are negative if x is
6655 negative; and are 32 or more otherwise. This is what you want
6656 when, for instance, you are emulating a right shift by a
6657 rotate-left-and-mask, because the underlying instructions support
6658 shifts of size 0 but not shifts of size 32. By comparison, when
6659 extracting x bits from some word you want to use just 32-x, because
6660 the underlying instructions don't support extracting 0 bits but do
6661 support extracting the whole word (32 bits in this case). */
6663 const struct powerpc_macro powerpc_macros
[] = {
6664 {"extldi", 4, PPC64
, "rldicr %0,%1,%3,(%2)-1"},
6665 {"extldi.", 4, PPC64
, "rldicr. %0,%1,%3,(%2)-1"},
6666 {"extrdi", 4, PPC64
, "rldicl %0,%1,((%2)+(%3))&((%2)+(%3)<>64),64-(%2)"},
6667 {"extrdi.", 4, PPC64
, "rldicl. %0,%1,((%2)+(%3))&((%2)+(%3)<>64),64-(%2)"},
6668 {"insrdi", 4, PPC64
, "rldimi %0,%1,64-((%2)+(%3)),%3"},
6669 {"insrdi.", 4, PPC64
, "rldimi. %0,%1,64-((%2)+(%3)),%3"},
6670 {"rotrdi", 3, PPC64
, "rldicl %0,%1,(-(%2)!63)&((%2)|63),0"},
6671 {"rotrdi.", 3, PPC64
, "rldicl. %0,%1,(-(%2)!63)&((%2)|63),0"},
6672 {"sldi", 3, PPC64
, "rldicr %0,%1,%2,63-(%2)"},
6673 {"sldi.", 3, PPC64
, "rldicr. %0,%1,%2,63-(%2)"},
6674 {"srdi", 3, PPC64
, "rldicl %0,%1,(-(%2)!63)&((%2)|63),%2"},
6675 {"srdi.", 3, PPC64
, "rldicl. %0,%1,(-(%2)!63)&((%2)|63),%2"},
6676 {"clrrdi", 3, PPC64
, "rldicr %0,%1,0,63-(%2)"},
6677 {"clrrdi.", 3, PPC64
, "rldicr. %0,%1,0,63-(%2)"},
6678 {"clrlsldi", 4, PPC64
, "rldic %0,%1,%3,(%2)-(%3)"},
6679 {"clrlsldi.",4, PPC64
, "rldic. %0,%1,%3,(%2)-(%3)"},
6681 {"extlwi", 4, PPCCOM
, "rlwinm %0,%1,%3,0,(%2)-1"},
6682 {"extlwi.", 4, PPCCOM
, "rlwinm. %0,%1,%3,0,(%2)-1"},
6683 {"extrwi", 4, PPCCOM
, "rlwinm %0,%1,((%2)+(%3))&((%2)+(%3)<>32),32-(%2),31"},
6684 {"extrwi.", 4, PPCCOM
, "rlwinm. %0,%1,((%2)+(%3))&((%2)+(%3)<>32),32-(%2),31"},
6685 {"inslwi", 4, PPCCOM
, "rlwimi %0,%1,(-(%3)!31)&((%3)|31),%3,(%2)+(%3)-1"},
6686 {"inslwi.", 4, PPCCOM
, "rlwimi. %0,%1,(-(%3)!31)&((%3)|31),%3,(%2)+(%3)-1"},
6687 {"insrwi", 4, PPCCOM
, "rlwimi %0,%1,32-((%2)+(%3)),%3,(%2)+(%3)-1"},
6688 {"insrwi.", 4, PPCCOM
, "rlwimi. %0,%1,32-((%2)+(%3)),%3,(%2)+(%3)-1"},
6689 {"rotrwi", 3, PPCCOM
, "rlwinm %0,%1,(-(%2)!31)&((%2)|31),0,31"},
6690 {"rotrwi.", 3, PPCCOM
, "rlwinm. %0,%1,(-(%2)!31)&((%2)|31),0,31"},
6691 {"slwi", 3, PPCCOM
, "rlwinm %0,%1,%2,0,31-(%2)"},
6692 {"sli", 3, PWRCOM
, "rlinm %0,%1,%2,0,31-(%2)"},
6693 {"slwi.", 3, PPCCOM
, "rlwinm. %0,%1,%2,0,31-(%2)"},
6694 {"sli.", 3, PWRCOM
, "rlinm. %0,%1,%2,0,31-(%2)"},
6695 {"srwi", 3, PPCCOM
, "rlwinm %0,%1,(-(%2)!31)&((%2)|31),%2,31"},
6696 {"sri", 3, PWRCOM
, "rlinm %0,%1,(-(%2)!31)&((%2)|31),%2,31"},
6697 {"srwi.", 3, PPCCOM
, "rlwinm. %0,%1,(-(%2)!31)&((%2)|31),%2,31"},
6698 {"sri.", 3, PWRCOM
, "rlinm. %0,%1,(-(%2)!31)&((%2)|31),%2,31"},
6699 {"clrrwi", 3, PPCCOM
, "rlwinm %0,%1,0,0,31-(%2)"},
6700 {"clrrwi.", 3, PPCCOM
, "rlwinm. %0,%1,0,0,31-(%2)"},
6701 {"clrlslwi", 4, PPCCOM
, "rlwinm %0,%1,%3,(%2)-(%3),31-(%3)"},
6702 {"clrlslwi.",4, PPCCOM
, "rlwinm. %0,%1,%3,(%2)-(%3),31-(%3)"},
6704 {"e_extlwi", 4, PPCVLE
, "e_rlwinm %0,%1,%3,0,(%2)-1"},
6705 {"e_extrwi", 4, PPCVLE
, "e_rlwinm %0,%1,((%2)+(%3))&((%2)+(%3)<>32),32-(%2),31"},
6706 {"e_inslwi", 4, PPCVLE
, "e_rlwimi %0,%1,(-(%3)!31)&((%3)|31),%3,(%2)+(%3)-1"},
6707 {"e_insrwi", 4, PPCVLE
, "e_rlwimi %0,%1,32-((%2)+(%3)),%3,(%2)+(%3)-1"},
6708 {"e_rotlwi", 3, PPCVLE
, "e_rlwinm %0,%1,%2,0,31"},
6709 {"e_rotrwi", 3, PPCVLE
, "e_rlwinm %0,%1,(-(%2)!31)&((%2)|31),0,31"},
6710 {"e_slwi", 3, PPCVLE
, "e_rlwinm %0,%1,%2,0,31-(%2)"},
6711 {"e_srwi", 3, PPCVLE
, "e_rlwinm %0,%1,(-(%2)!31)&((%2)|31),%2,31"},
6712 {"e_clrlwi", 3, PPCVLE
, "e_rlwinm %0,%1,0,%2,31"},
6713 {"e_clrrwi", 3, PPCVLE
, "e_rlwinm %0,%1,0,0,31-(%2)"},
6714 {"e_clrlslwi",4, PPCVLE
, "e_rlwinm %0,%1,%3,(%2)-(%3),31-(%3)"},
6717 const int powerpc_num_macros
=
6718 sizeof (powerpc_macros
) / sizeof (powerpc_macros
[0]);