1 /* ppc-opc.c -- PowerPC opcode list
2 Copyright 1994, 1995, 1996, 1997, 1998, 2000, 2001, 2002
3 Free Software Foundation, Inc.
4 Written by Ian Lance Taylor, Cygnus Support
6 This file is part of GDB, GAS, and the GNU binutils.
8 GDB, GAS, and the GNU binutils are free software; you can redistribute
9 them and/or modify them under the terms of the GNU General Public
10 License as published by the Free Software Foundation; either version
11 2, or (at your option) any later version.
13 GDB, GAS, and the GNU binutils are distributed in the hope that they
14 will be useful, but WITHOUT ANY WARRANTY; without even the implied
15 warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See
16 the GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with this file; see the file COPYING. If not, write to the Free
20 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
25 #include "opcode/ppc.h"
28 /* This file holds the PowerPC opcode table. The opcode table
29 includes almost all of the extended instruction mnemonics. This
30 permits the disassembler to use them, and simplifies the assembler
31 logic, at the cost of increasing the table size. The table is
32 strictly constant data, so the compiler should be able to put it in
35 This file also holds the operand table. All knowledge about
36 inserting operands into instructions and vice-versa is kept in this
39 /* Local insertion and extraction functions. */
41 static unsigned long insert_bat
42 PARAMS ((unsigned long, long, int, const char **));
43 static long extract_bat
44 PARAMS ((unsigned long, int, int *));
45 static unsigned long insert_bba
46 PARAMS ((unsigned long, long, int, const char **));
47 static long extract_bba
48 PARAMS ((unsigned long, int, int *));
49 static unsigned long insert_bd
50 PARAMS ((unsigned long, long, int, const char **));
51 static long extract_bd
52 PARAMS ((unsigned long, int, int *));
53 static unsigned long insert_bdm
54 PARAMS ((unsigned long, long, int, const char **));
55 static long extract_bdm
56 PARAMS ((unsigned long, int, int *));
57 static unsigned long insert_bdp
58 PARAMS ((unsigned long, long, int, const char **));
59 static long extract_bdp
60 PARAMS ((unsigned long, int, int *));
63 static unsigned long insert_bo
64 PARAMS ((unsigned long, long, int, const char **));
65 static long extract_bo
66 PARAMS ((unsigned long, int, int *));
67 static unsigned long insert_boe
68 PARAMS ((unsigned long, long, int, const char **));
69 static long extract_boe
70 PARAMS ((unsigned long, int, int *));
71 static unsigned long insert_ds
72 PARAMS ((unsigned long, long, int, const char **));
73 static long extract_ds
74 PARAMS ((unsigned long, int, int *));
75 static unsigned long insert_de
76 PARAMS ((unsigned long, long, int, const char **));
77 static long extract_de
78 PARAMS ((unsigned long, int, int *));
79 static unsigned long insert_des
80 PARAMS ((unsigned long, long, int, const char **));
81 static long extract_des
82 PARAMS ((unsigned long, int, int *));
83 static unsigned long insert_li
84 PARAMS ((unsigned long, long, int, const char **));
85 static long extract_li
86 PARAMS ((unsigned long, int, int *));
87 static unsigned long insert_mbe
88 PARAMS ((unsigned long, long, int, const char **));
89 static long extract_mbe
90 PARAMS ((unsigned long, int, int *));
91 static unsigned long insert_mb6
92 PARAMS ((unsigned long, long, int, const char **));
93 static long extract_mb6
94 PARAMS ((unsigned long, int, int *));
95 static unsigned long insert_nb
96 PARAMS ((unsigned long, long, int, const char **));
97 static long extract_nb
98 PARAMS ((unsigned long, int, int *));
99 static unsigned long insert_nsi
100 PARAMS ((unsigned long, long, int, const char **));
101 static long extract_nsi
102 PARAMS ((unsigned long, int, int *));
103 static unsigned long insert_ral
104 PARAMS ((unsigned long, long, int, const char **));
105 static unsigned long insert_ram
106 PARAMS ((unsigned long, long, int, const char **));
107 static unsigned long insert_ras
108 PARAMS ((unsigned long, long, int, const char **));
109 static unsigned long insert_rbs
110 PARAMS ((unsigned long, long, int, const char **));
111 static long extract_rbs
112 PARAMS ((unsigned long, int, int *));
113 static unsigned long insert_sh6
114 PARAMS ((unsigned long, long, int, const char **));
115 static long extract_sh6
116 PARAMS ((unsigned long, int, int *));
117 static unsigned long insert_spr
118 PARAMS ((unsigned long, long, int, const char **));
119 static long extract_spr
120 PARAMS ((unsigned long, int, int *));
121 static unsigned long insert_tbr
122 PARAMS ((unsigned long, long, int, const char **));
123 static long extract_tbr
124 PARAMS ((unsigned long, int, int *));
126 /* The operands table.
128 The fields are bits, shift, insert, extract, flags.
130 We used to put parens around the various additions, like the one
131 for BA just below. However, that caused trouble with feeble
132 compilers with a limit on depth of a parenthesized expression, like
133 (reportedly) the compiler in Microsoft Developer Studio 5. So we
134 omit the parens, since the macros are never used in a context where
135 the addition will be ambiguous. */
137 const struct powerpc_operand powerpc_operands
[] =
139 /* The zero index is used to indicate the end of the list of
144 /* The BA field in an XL form instruction. */
145 #define BA UNUSED + 1
146 #define BA_MASK (0x1f << 16)
147 { 5, 16, 0, 0, PPC_OPERAND_CR
},
149 /* The BA field in an XL form instruction when it must be the same
150 as the BT field in the same instruction. */
152 { 5, 16, insert_bat
, extract_bat
, PPC_OPERAND_FAKE
},
154 /* The BB field in an XL form instruction. */
156 #define BB_MASK (0x1f << 11)
157 { 5, 11, 0, 0, PPC_OPERAND_CR
},
159 /* The BB field in an XL form instruction when it must be the same
160 as the BA field in the same instruction. */
162 { 5, 11, insert_bba
, extract_bba
, PPC_OPERAND_FAKE
},
164 /* The BD field in a B form instruction. The lower two bits are
167 { 16, 0, insert_bd
, extract_bd
, PPC_OPERAND_RELATIVE
| PPC_OPERAND_SIGNED
},
169 /* The BD field in a B form instruction when absolute addressing is
172 { 16, 0, insert_bd
, extract_bd
, PPC_OPERAND_ABSOLUTE
| PPC_OPERAND_SIGNED
},
174 /* The BD field in a B form instruction when the - modifier is used.
175 This sets the y bit of the BO field appropriately. */
177 { 16, 0, insert_bdm
, extract_bdm
,
178 PPC_OPERAND_RELATIVE
| PPC_OPERAND_SIGNED
},
180 /* The BD field in a B form instruction when the - modifier is used
181 and absolute address is used. */
183 { 16, 0, insert_bdm
, extract_bdm
,
184 PPC_OPERAND_ABSOLUTE
| PPC_OPERAND_SIGNED
},
186 /* The BD field in a B form instruction when the + modifier is used.
187 This sets the y bit of the BO field appropriately. */
189 { 16, 0, insert_bdp
, extract_bdp
,
190 PPC_OPERAND_RELATIVE
| PPC_OPERAND_SIGNED
},
192 /* The BD field in a B form instruction when the + modifier is used
193 and absolute addressing is used. */
195 { 16, 0, insert_bdp
, extract_bdp
,
196 PPC_OPERAND_ABSOLUTE
| PPC_OPERAND_SIGNED
},
198 /* The BF field in an X or XL form instruction. */
200 { 3, 23, 0, 0, PPC_OPERAND_CR
},
202 /* An optional BF field. This is used for comparison instructions,
203 in which an omitted BF field is taken as zero. */
205 { 3, 23, 0, 0, PPC_OPERAND_CR
| PPC_OPERAND_OPTIONAL
},
207 /* The BFA field in an X or XL form instruction. */
209 { 3, 18, 0, 0, PPC_OPERAND_CR
},
211 /* The BI field in a B form or XL form instruction. */
213 #define BI_MASK (0x1f << 16)
214 { 5, 16, 0, 0, PPC_OPERAND_CR
},
216 /* The BO field in a B form instruction. Certain values are
219 #define BO_MASK (0x1f << 21)
220 { 5, 21, insert_bo
, extract_bo
, 0 },
222 /* The BO field in a B form instruction when the + or - modifier is
223 used. This is like the BO field, but it must be even. */
225 { 5, 21, insert_boe
, extract_boe
, 0 },
227 /* The BT field in an X or XL form instruction. */
229 { 5, 21, 0, 0, PPC_OPERAND_CR
},
231 /* The condition register number portion of the BI field in a B form
232 or XL form instruction. This is used for the extended
233 conditional branch mnemonics, which set the lower two bits of the
234 BI field. This field is optional. */
236 { 3, 18, 0, 0, PPC_OPERAND_CR
| PPC_OPERAND_OPTIONAL
},
238 /* The CT field in an X form instruction. */
240 { 5, 21, 0, 0, PPC_OPERAND_OPTIONAL
},
242 /* The D field in a D form instruction. This is a displacement off
243 a register, and implies that the next operand is a register in
246 { 16, 0, 0, 0, PPC_OPERAND_PARENS
| PPC_OPERAND_SIGNED
},
248 /* The DE field in a DE form instruction. This is like D, but is 12
251 { 14, 0, insert_de
, extract_de
, PPC_OPERAND_PARENS
},
253 /* The DES field in a DES form instruction. This is like DS, but is 14
254 bits only (12 stored.) */
256 { 14, 0, insert_des
, extract_des
, PPC_OPERAND_PARENS
| PPC_OPERAND_SIGNED
},
258 /* The DS field in a DS form instruction. This is like D, but the
259 lower two bits are forced to zero. */
261 { 16, 0, insert_ds
, extract_ds
,
262 PPC_OPERAND_PARENS
| PPC_OPERAND_SIGNED
| PPC_OPERAND_DS
},
264 /* The E field in a wrteei instruction. */
268 /* The FL1 field in a POWER SC form instruction. */
272 /* The FL2 field in a POWER SC form instruction. */
276 /* The FLM field in an XFL form instruction. */
280 /* The FRA field in an X or A form instruction. */
282 #define FRA_MASK (0x1f << 16)
283 { 5, 16, 0, 0, PPC_OPERAND_FPR
},
285 /* The FRB field in an X or A form instruction. */
287 #define FRB_MASK (0x1f << 11)
288 { 5, 11, 0, 0, PPC_OPERAND_FPR
},
290 /* The FRC field in an A form instruction. */
292 #define FRC_MASK (0x1f << 6)
293 { 5, 6, 0, 0, PPC_OPERAND_FPR
},
295 /* The FRS field in an X form instruction or the FRT field in a D, X
296 or A form instruction. */
299 { 5, 21, 0, 0, PPC_OPERAND_FPR
},
301 /* The FXM field in an XFX instruction. */
303 #define FXM_MASK (0xff << 12)
306 /* The L field in a D or X form instruction. */
308 { 1, 21, 0, 0, PPC_OPERAND_OPTIONAL
},
310 /* The LEV field in a POWER SC form instruction. */
314 /* The LI field in an I form instruction. The lower two bits are
317 { 26, 0, insert_li
, extract_li
, PPC_OPERAND_RELATIVE
| PPC_OPERAND_SIGNED
},
319 /* The LI field in an I form instruction when used as an absolute
322 { 26, 0, insert_li
, extract_li
, PPC_OPERAND_ABSOLUTE
| PPC_OPERAND_SIGNED
},
324 /* The LS field in an X (sync) form instruction. */
326 { 2, 21, 0, 0, PPC_OPERAND_OPTIONAL
},
328 /* The MB field in an M form instruction. */
330 #define MB_MASK (0x1f << 6)
333 /* The ME field in an M form instruction. */
335 #define ME_MASK (0x1f << 1)
338 /* The MB and ME fields in an M form instruction expressed a single
339 operand which is a bitmask indicating which bits to select. This
340 is a two operand form using PPC_OPERAND_NEXT. See the
341 description in opcode/ppc.h for what this means. */
343 { 5, 6, 0, 0, PPC_OPERAND_OPTIONAL
| PPC_OPERAND_NEXT
},
344 { 32, 0, insert_mbe
, extract_mbe
, 0 },
346 /* The MB or ME field in an MD or MDS form instruction. The high
347 bit is wrapped to the low end. */
350 #define MB6_MASK (0x3f << 5)
351 { 6, 5, insert_mb6
, extract_mb6
, 0 },
353 /* The MO field in an mbar instruction. */
357 /* The NB field in an X form instruction. The value 32 is stored as
360 { 6, 11, insert_nb
, extract_nb
, 0 },
362 /* The NSI field in a D form instruction. This is the same as the
363 SI field, only negated. */
365 { 16, 0, insert_nsi
, extract_nsi
,
366 PPC_OPERAND_NEGATIVE
| PPC_OPERAND_SIGNED
},
368 /* The RA field in an D, DS, X, XO, M, or MDS form instruction. */
370 #define RA_MASK (0x1f << 16)
371 { 5, 16, 0, 0, PPC_OPERAND_GPR
},
373 /* The RA field in a D or X form instruction which is an updating
374 load, which means that the RA field may not be zero and may not
375 equal the RT field. */
377 { 5, 16, insert_ral
, 0, PPC_OPERAND_GPR
},
379 /* The RA field in an lmw instruction, which has special value
382 { 5, 16, insert_ram
, 0, PPC_OPERAND_GPR
},
384 /* The RA field in a D or X form instruction which is an updating
385 store or an updating floating point load, which means that the RA
386 field may not be zero. */
388 { 5, 16, insert_ras
, 0, PPC_OPERAND_GPR
},
390 /* The RB field in an X, XO, M, or MDS form instruction. */
392 #define RB_MASK (0x1f << 11)
393 { 5, 11, 0, 0, PPC_OPERAND_GPR
},
395 /* The RB field in an X form instruction when it must be the same as
396 the RS field in the instruction. This is used for extended
397 mnemonics like mr. */
399 { 5, 1, insert_rbs
, extract_rbs
, PPC_OPERAND_FAKE
},
401 /* The RS field in a D, DS, X, XFX, XS, M, MD or MDS form
402 instruction or the RT field in a D, DS, X, XFX or XO form
406 #define RT_MASK (0x1f << 21)
407 { 5, 21, 0, 0, PPC_OPERAND_GPR
},
409 /* The SH field in an X or M form instruction. */
411 #define SH_MASK (0x1f << 11)
414 /* The SH field in an MD form instruction. This is split. */
416 #define SH6_MASK ((0x1f << 11) | (1 << 1))
417 { 6, 1, insert_sh6
, extract_sh6
, 0 },
419 /* The SI field in a D form instruction. */
421 { 16, 0, 0, 0, PPC_OPERAND_SIGNED
},
423 /* The SI field in a D form instruction when we accept a wide range
424 of positive values. */
425 #define SISIGNOPT SI + 1
426 { 16, 0, 0, 0, PPC_OPERAND_SIGNED
| PPC_OPERAND_SIGNOPT
},
428 /* The SPR field in an XFX form instruction. This is flipped--the
429 lower 5 bits are stored in the upper 5 and vice- versa. */
430 #define SPR SISIGNOPT + 1
431 #define SPR_MASK (0x3ff << 11)
432 { 10, 11, insert_spr
, extract_spr
, 0 },
434 /* The BAT index number in an XFX form m[ft]ibat[lu] instruction. */
435 #define SPRBAT SPR + 1
436 #define SPRBAT_MASK (0x3 << 17)
439 /* The SPRG register number in an XFX form m[ft]sprg instruction. */
440 #define SPRG SPRBAT + 1
441 #define SPRG_MASK (0x3 << 16)
444 /* The SR field in an X form instruction. */
448 /* The STRM field in an X AltiVec form instruction. */
450 #define STRM_MASK (0x3 << 21)
453 /* The SV field in a POWER SC form instruction. */
457 /* The TBR field in an XFX form instruction. This is like the SPR
458 field, but it is optional. */
460 { 10, 11, insert_tbr
, extract_tbr
, PPC_OPERAND_OPTIONAL
},
462 /* The TO field in a D or X form instruction. */
464 #define TO_MASK (0x1f << 21)
467 /* The U field in an X form instruction. */
471 /* The UI field in a D form instruction. */
475 /* The VA field in a VA, VX or VXR form instruction. */
477 #define VA_MASK (0x1f << 16)
478 { 5, 16, 0, 0, PPC_OPERAND_VR
},
480 /* The VB field in a VA, VX or VXR form instruction. */
482 #define VB_MASK (0x1f << 11)
483 { 5, 11, 0, 0, PPC_OPERAND_VR
},
485 /* The VC field in a VA form instruction. */
487 #define VC_MASK (0x1f << 6)
488 { 5, 6, 0, 0, PPC_OPERAND_VR
},
490 /* The VD or VS field in a VA, VX, VXR or X form instruction. */
493 #define VD_MASK (0x1f << 21)
494 { 5, 21, 0, 0, PPC_OPERAND_VR
},
496 /* The SIMM field in a VX form instruction. */
498 { 5, 16, 0, 0, PPC_OPERAND_SIGNED
},
500 /* The UIMM field in a VX form instruction. */
501 #define UIMM SIMM + 1
504 /* The SHB field in a VA form instruction. */
510 #define WS_MASK (0x7 << 11)
513 /* The L field in an mtmsrd instruction */
514 #define MTMSRD_L WS + 1
515 { 1, 16, 0, 0, PPC_OPERAND_OPTIONAL
},
519 /* The functions used to insert and extract complicated operands. */
521 /* The BA field in an XL form instruction when it must be the same as
522 the BT field in the same instruction. This operand is marked FAKE.
523 The insertion function just copies the BT field into the BA field,
524 and the extraction function just checks that the fields are the
529 insert_bat (insn
, value
, dialect
, errmsg
)
531 long value ATTRIBUTE_UNUSED
;
532 int dialect ATTRIBUTE_UNUSED
;
533 const char **errmsg ATTRIBUTE_UNUSED
;
535 return insn
| (((insn
>> 21) & 0x1f) << 16);
539 extract_bat (insn
, dialect
, invalid
)
541 int dialect ATTRIBUTE_UNUSED
;
544 if (invalid
!= (int *) NULL
545 && ((insn
>> 21) & 0x1f) != ((insn
>> 16) & 0x1f))
550 /* The BB field in an XL form instruction when it must be the same as
551 the BA field in the same instruction. This operand is marked FAKE.
552 The insertion function just copies the BA field into the BB field,
553 and the extraction function just checks that the fields are the
558 insert_bba (insn
, value
, dialect
, errmsg
)
560 long value ATTRIBUTE_UNUSED
;
561 int dialect ATTRIBUTE_UNUSED
;
562 const char **errmsg ATTRIBUTE_UNUSED
;
564 return insn
| (((insn
>> 16) & 0x1f) << 11);
568 extract_bba (insn
, dialect
, invalid
)
570 int dialect ATTRIBUTE_UNUSED
;
573 if (invalid
!= (int *) NULL
574 && ((insn
>> 16) & 0x1f) != ((insn
>> 11) & 0x1f))
579 /* The BD field in a B form instruction. The lower two bits are
584 insert_bd (insn
, value
, dialect
, errmsg
)
587 int dialect ATTRIBUTE_UNUSED
;
588 const char **errmsg ATTRIBUTE_UNUSED
;
590 return insn
| (value
& 0xfffc);
595 extract_bd (insn
, dialect
, invalid
)
597 int dialect ATTRIBUTE_UNUSED
;
598 int *invalid ATTRIBUTE_UNUSED
;
600 return ((insn
& 0xfffc) ^ 0x8000) - 0x8000;
603 /* The BD field in a B form instruction when the - modifier is used.
604 This modifier means that the branch is not expected to be taken.
605 For chips built to versions of the architecture prior to version 2
606 (ie. not Power4 compatible), we set the y bit of the BO field to 1
607 if the offset is negative. When extracting, we require that the y
608 bit be 1 and that the offset be positive, since if the y bit is 0
609 we just want to print the normal form of the instruction.
610 Power4 compatible targets use two bits, "a", and "t", instead of
611 the "y" bit. "at" == 00 => no hint, "at" == 01 => unpredictable,
612 "at" == 10 => not taken, "at" == 11 => taken. The "t" bit is 00001
613 in BO field, the "a" bit is 00010 for branch on CR(BI) and 01000
614 for branch on CTR. We only handle the taken/not-taken hint here. */
618 insert_bdm (insn
, value
, dialect
, errmsg
)
622 const char **errmsg ATTRIBUTE_UNUSED
;
624 if ((dialect
& PPC_OPCODE_POWER4
) == 0)
626 if ((value
& 0x8000) != 0)
631 if ((insn
& (0x14 << 21)) == (0x04 << 21))
633 else if ((insn
& (0x14 << 21)) == (0x10 << 21))
636 return insn
| (value
& 0xfffc);
640 extract_bdm (insn
, dialect
, invalid
)
645 if (invalid
!= (int *) NULL
)
647 if ((dialect
& PPC_OPCODE_POWER4
) == 0)
649 if (((insn
& (1 << 21)) == 0) != ((insn
& (1 << 15)) == 0))
654 if ((insn
& (0x17 << 21)) != (0x06 << 21)
655 && (insn
& (0x1d << 21)) != (0x18 << 21))
659 return ((insn
& 0xfffc) ^ 0x8000) - 0x8000;
662 /* The BD field in a B form instruction when the + modifier is used.
663 This is like BDM, above, except that the branch is expected to be
668 insert_bdp (insn
, value
, dialect
, errmsg
)
672 const char **errmsg ATTRIBUTE_UNUSED
;
674 if ((dialect
& PPC_OPCODE_POWER4
) == 0)
676 if ((value
& 0x8000) == 0)
681 if ((insn
& (0x14 << 21)) == (0x04 << 21))
683 else if ((insn
& (0x14 << 21)) == (0x10 << 21))
686 return insn
| (value
& 0xfffc);
690 extract_bdp (insn
, dialect
, invalid
)
695 if (invalid
!= (int *) NULL
)
697 if ((dialect
& PPC_OPCODE_POWER4
) == 0)
699 if (((insn
& (1 << 21)) == 0) == ((insn
& (1 << 15)) == 0))
704 if ((insn
& (0x17 << 21)) != (0x07 << 21)
705 && (insn
& (0x1d << 21)) != (0x19 << 21))
709 return ((insn
& 0xfffc) ^ 0x8000) - 0x8000;
712 /* Check for legal values of a BO field. */
715 valid_bo (value
, dialect
)
719 if ((dialect
& PPC_OPCODE_POWER4
) == 0)
721 /* Certain encodings have bits that are required to be zero.
722 These are (z must be zero, y may be anything):
729 switch (value
& 0x14)
735 return (value
& 0x2) == 0;
737 return (value
& 0x8) == 0;
739 return value
== 0x14;
744 /* Certain encodings have bits that are required to be zero.
745 These are (z must be zero, a & t may be anything):
756 if ((value
& 0x14) == 0)
757 return (value
& 0x1) == 0;
758 else if ((value
& 0x14) == 0x14)
759 return value
== 0x14;
765 /* The BO field in a B form instruction. Warn about attempts to set
766 the field to an illegal value. */
769 insert_bo (insn
, value
, dialect
, errmsg
)
775 if (errmsg
!= (const char **) NULL
776 && ! valid_bo (value
, dialect
))
777 *errmsg
= _("invalid conditional option");
778 return insn
| ((value
& 0x1f) << 21);
782 extract_bo (insn
, dialect
, invalid
)
789 value
= (insn
>> 21) & 0x1f;
790 if (invalid
!= (int *) NULL
791 && ! valid_bo (value
, dialect
))
796 /* The BO field in a B form instruction when the + or - modifier is
797 used. This is like the BO field, but it must be even. When
798 extracting it, we force it to be even. */
801 insert_boe (insn
, value
, dialect
, errmsg
)
807 if (errmsg
!= (const char **) NULL
)
809 if (! valid_bo (value
, dialect
))
810 *errmsg
= _("invalid conditional option");
811 else if ((value
& 1) != 0)
812 *errmsg
= _("attempt to set y bit when using + or - modifier");
814 return insn
| ((value
& 0x1f) << 21);
818 extract_boe (insn
, dialect
, invalid
)
825 value
= (insn
>> 21) & 0x1f;
826 if (invalid
!= (int *) NULL
827 && ! valid_bo (value
, dialect
))
832 /* The DS field in a DS form instruction. This is like D, but the
833 lower two bits are forced to zero. */
837 insert_ds (insn
, value
, dialect
, errmsg
)
840 int dialect ATTRIBUTE_UNUSED
;
843 if ((value
& 3) != 0 && errmsg
!= NULL
)
844 *errmsg
= _("offset not a multiple of 4");
845 return insn
| (value
& 0xfffc);
850 extract_ds (insn
, dialect
, invalid
)
852 int dialect ATTRIBUTE_UNUSED
;
853 int *invalid ATTRIBUTE_UNUSED
;
855 return ((insn
& 0xfffc) ^ 0x8000) - 0x8000;
858 /* The DE field in a DE form instruction. */
862 insert_de (insn
, value
, dialect
, errmsg
)
865 int dialect ATTRIBUTE_UNUSED
;
868 if ((value
> 2047 || value
< -2048) && errmsg
!= NULL
)
869 *errmsg
= _("offset not between -2048 and 2047");
870 return insn
| ((value
<< 4) & 0xfff0);
875 extract_de (insn
, dialect
, invalid
)
877 int dialect ATTRIBUTE_UNUSED
;
878 int *invalid ATTRIBUTE_UNUSED
;
880 return (insn
& 0xfff0) >> 4;
883 /* The DES field in a DES form instruction. */
887 insert_des (insn
, value
, dialect
, errmsg
)
890 int dialect ATTRIBUTE_UNUSED
;
893 if ((value
> 8191 || value
< -8192) && errmsg
!= NULL
)
894 *errmsg
= _("offset not between -8192 and 8191");
895 else if ((value
& 3) != 0 && errmsg
!= NULL
)
896 *errmsg
= _("offset not a multiple of 4");
897 return insn
| ((value
<< 2) & 0xfff0);
902 extract_des (insn
, dialect
, invalid
)
904 int dialect ATTRIBUTE_UNUSED
;
905 int *invalid ATTRIBUTE_UNUSED
;
907 return (((insn
>> 2) & 0x3ffc) ^ 0x2000) - 0x2000;
910 /* The LI field in an I form instruction. The lower two bits are
915 insert_li (insn
, value
, dialect
, errmsg
)
918 int dialect ATTRIBUTE_UNUSED
;
921 if ((value
& 3) != 0 && errmsg
!= (const char **) NULL
)
922 *errmsg
= _("ignoring least significant bits in branch offset");
923 return insn
| (value
& 0x3fffffc);
928 extract_li (insn
, dialect
, invalid
)
930 int dialect ATTRIBUTE_UNUSED
;
931 int *invalid ATTRIBUTE_UNUSED
;
933 return ((insn
& 0x3fffffc) ^ 0x2000000) - 0x2000000;
936 /* The MB and ME fields in an M form instruction expressed as a single
937 operand which is itself a bitmask. The extraction function always
938 marks it as invalid, since we never want to recognize an
939 instruction which uses a field of this type. */
942 insert_mbe (insn
, value
, dialect
, errmsg
)
945 int dialect ATTRIBUTE_UNUSED
;
948 unsigned long uval
, mask
;
949 int mb
, me
, mx
, count
, last
;
955 if (errmsg
!= (const char **) NULL
)
956 *errmsg
= _("illegal bitmask");
968 /* mb: location of last 0->1 transition */
969 /* me: location of last 1->0 transition */
970 /* count: # transitions */
972 for (mx
= 0, mask
= (long) 1 << 31; mx
< 32; ++mx
, mask
>>= 1)
974 if ((uval
& mask
) && !last
)
980 else if (!(uval
& mask
) && last
)
990 if (count
!= 2 && (count
!= 0 || ! last
))
992 if (errmsg
!= (const char **) NULL
)
993 *errmsg
= _("illegal bitmask");
996 return insn
| (mb
<< 6) | ((me
- 1) << 1);
1000 extract_mbe (insn
, dialect
, invalid
)
1002 int dialect ATTRIBUTE_UNUSED
;
1009 if (invalid
!= (int *) NULL
)
1012 mb
= (insn
>> 6) & 0x1f;
1013 me
= (insn
>> 1) & 0x1f;
1017 for (i
= mb
; i
<= me
; i
++)
1018 ret
|= (long) 1 << (31 - i
);
1020 else if (mb
== me
+ 1)
1022 else /* (mb > me + 1) */
1025 for (i
= me
+ 1; i
< mb
; i
++)
1026 ret
&= ~ ((long) 1 << (31 - i
));
1031 /* The MB or ME field in an MD or MDS form instruction. The high bit
1032 is wrapped to the low end. */
1035 static unsigned long
1036 insert_mb6 (insn
, value
, dialect
, errmsg
)
1039 int dialect ATTRIBUTE_UNUSED
;
1040 const char **errmsg ATTRIBUTE_UNUSED
;
1042 return insn
| ((value
& 0x1f) << 6) | (value
& 0x20);
1047 extract_mb6 (insn
, dialect
, invalid
)
1049 int dialect ATTRIBUTE_UNUSED
;
1050 int *invalid ATTRIBUTE_UNUSED
;
1052 return ((insn
>> 6) & 0x1f) | (insn
& 0x20);
1055 /* The NB field in an X form instruction. The value 32 is stored as
1058 static unsigned long
1059 insert_nb (insn
, value
, dialect
, errmsg
)
1062 int dialect ATTRIBUTE_UNUSED
;
1063 const char **errmsg
;
1065 if (value
< 0 || value
> 32)
1066 *errmsg
= _("value out of range");
1069 return insn
| ((value
& 0x1f) << 11);
1074 extract_nb (insn
, dialect
, invalid
)
1076 int dialect ATTRIBUTE_UNUSED
;
1077 int *invalid ATTRIBUTE_UNUSED
;
1081 ret
= (insn
>> 11) & 0x1f;
1087 /* The NSI field in a D form instruction. This is the same as the SI
1088 field, only negated. The extraction function always marks it as
1089 invalid, since we never want to recognize an instruction which uses
1090 a field of this type. */
1093 static unsigned long
1094 insert_nsi (insn
, value
, dialect
, errmsg
)
1097 int dialect ATTRIBUTE_UNUSED
;
1098 const char **errmsg ATTRIBUTE_UNUSED
;
1100 return insn
| ((- value
) & 0xffff);
1104 extract_nsi (insn
, dialect
, invalid
)
1106 int dialect ATTRIBUTE_UNUSED
;
1109 if (invalid
!= (int *) NULL
)
1111 return - (((insn
& 0xffff) ^ 0x8000) - 0x8000);
1114 /* The RA field in a D or X form instruction which is an updating
1115 load, which means that the RA field may not be zero and may not
1116 equal the RT field. */
1118 static unsigned long
1119 insert_ral (insn
, value
, dialect
, errmsg
)
1122 int dialect ATTRIBUTE_UNUSED
;
1123 const char **errmsg
;
1126 || (unsigned long) value
== ((insn
>> 21) & 0x1f))
1127 *errmsg
= "invalid register operand when updating";
1128 return insn
| ((value
& 0x1f) << 16);
1131 /* The RA field in an lmw instruction, which has special value
1134 static unsigned long
1135 insert_ram (insn
, value
, dialect
, errmsg
)
1138 int dialect ATTRIBUTE_UNUSED
;
1139 const char **errmsg
;
1141 if ((unsigned long) value
>= ((insn
>> 21) & 0x1f))
1142 *errmsg
= _("index register in load range");
1143 return insn
| ((value
& 0x1f) << 16);
1146 /* The RA field in a D or X form instruction which is an updating
1147 store or an updating floating point load, which means that the RA
1148 field may not be zero. */
1150 static unsigned long
1151 insert_ras (insn
, value
, dialect
, errmsg
)
1154 int dialect ATTRIBUTE_UNUSED
;
1155 const char **errmsg
;
1158 *errmsg
= _("invalid register operand when updating");
1159 return insn
| ((value
& 0x1f) << 16);
1162 /* The RB field in an X form instruction when it must be the same as
1163 the RS field in the instruction. This is used for extended
1164 mnemonics like mr. This operand is marked FAKE. The insertion
1165 function just copies the BT field into the BA field, and the
1166 extraction function just checks that the fields are the same. */
1169 static unsigned long
1170 insert_rbs (insn
, value
, dialect
, errmsg
)
1172 long value ATTRIBUTE_UNUSED
;
1173 int dialect ATTRIBUTE_UNUSED
;
1174 const char **errmsg ATTRIBUTE_UNUSED
;
1176 return insn
| (((insn
>> 21) & 0x1f) << 11);
1180 extract_rbs (insn
, dialect
, invalid
)
1182 int dialect ATTRIBUTE_UNUSED
;
1185 if (invalid
!= (int *) NULL
1186 && ((insn
>> 21) & 0x1f) != ((insn
>> 11) & 0x1f))
1191 /* The SH field in an MD form instruction. This is split. */
1194 static unsigned long
1195 insert_sh6 (insn
, value
, dialect
, errmsg
)
1198 int dialect ATTRIBUTE_UNUSED
;
1199 const char **errmsg ATTRIBUTE_UNUSED
;
1201 return insn
| ((value
& 0x1f) << 11) | ((value
& 0x20) >> 4);
1206 extract_sh6 (insn
, dialect
, invalid
)
1208 int dialect ATTRIBUTE_UNUSED
;
1209 int *invalid ATTRIBUTE_UNUSED
;
1211 return ((insn
>> 11) & 0x1f) | ((insn
<< 4) & 0x20);
1214 /* The SPR field in an XFX form instruction. This is flipped--the
1215 lower 5 bits are stored in the upper 5 and vice- versa. */
1217 static unsigned long
1218 insert_spr (insn
, value
, dialect
, errmsg
)
1221 int dialect ATTRIBUTE_UNUSED
;
1222 const char **errmsg ATTRIBUTE_UNUSED
;
1224 return insn
| ((value
& 0x1f) << 16) | ((value
& 0x3e0) << 6);
1228 extract_spr (insn
, dialect
, invalid
)
1230 int dialect ATTRIBUTE_UNUSED
;
1231 int *invalid ATTRIBUTE_UNUSED
;
1233 return ((insn
>> 16) & 0x1f) | ((insn
>> 6) & 0x3e0);
1236 /* The TBR field in an XFX instruction. This is just like SPR, but it
1237 is optional. When TBR is omitted, it must be inserted as 268 (the
1238 magic number of the TB register). These functions treat 0
1239 (indicating an omitted optional operand) as 268. This means that
1240 ``mftb 4,0'' is not handled correctly. This does not matter very
1241 much, since the architecture manual does not define mftb as
1242 accepting any values other than 268 or 269. */
1246 static unsigned long
1247 insert_tbr (insn
, value
, dialect
, errmsg
)
1250 int dialect ATTRIBUTE_UNUSED
;
1251 const char **errmsg ATTRIBUTE_UNUSED
;
1255 return insn
| ((value
& 0x1f) << 16) | ((value
& 0x3e0) << 6);
1259 extract_tbr (insn
, dialect
, invalid
)
1261 int dialect ATTRIBUTE_UNUSED
;
1262 int *invalid ATTRIBUTE_UNUSED
;
1266 ret
= ((insn
>> 16) & 0x1f) | ((insn
>> 6) & 0x3e0);
1272 /* Macros used to form opcodes. */
1274 /* The main opcode. */
1275 #define OP(x) ((((unsigned long)(x)) & 0x3f) << 26)
1276 #define OP_MASK OP (0x3f)
1278 /* The main opcode combined with a trap code in the TO field of a D
1279 form instruction. Used for extended mnemonics for the trap
1281 #define OPTO(x,to) (OP (x) | ((((unsigned long)(to)) & 0x1f) << 21))
1282 #define OPTO_MASK (OP_MASK | TO_MASK)
1284 /* The main opcode combined with a comparison size bit in the L field
1285 of a D form or X form instruction. Used for extended mnemonics for
1286 the comparison instructions. */
1287 #define OPL(x,l) (OP (x) | ((((unsigned long)(l)) & 1) << 21))
1288 #define OPL_MASK OPL (0x3f,1)
1290 /* An A form instruction. */
1291 #define A(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0x1f) << 1) | (((unsigned long)(rc)) & 1))
1292 #define A_MASK A (0x3f, 0x1f, 1)
1294 /* An A_MASK with the FRB field fixed. */
1295 #define AFRB_MASK (A_MASK | FRB_MASK)
1297 /* An A_MASK with the FRC field fixed. */
1298 #define AFRC_MASK (A_MASK | FRC_MASK)
1300 /* An A_MASK with the FRA and FRC fields fixed. */
1301 #define AFRAFRC_MASK (A_MASK | FRA_MASK | FRC_MASK)
1303 /* A B form instruction. */
1304 #define B(op, aa, lk) (OP (op) | ((((unsigned long)(aa)) & 1) << 1) | ((lk) & 1))
1305 #define B_MASK B (0x3f, 1, 1)
1307 /* A B form instruction setting the BO field. */
1308 #define BBO(op, bo, aa, lk) (B ((op), (aa), (lk)) | ((((unsigned long)(bo)) & 0x1f) << 21))
1309 #define BBO_MASK BBO (0x3f, 0x1f, 1, 1)
1311 /* A BBO_MASK with the y bit of the BO field removed. This permits
1312 matching a conditional branch regardless of the setting of the y
1313 bit. Similarly for the 'at' bits used for power4 branch hints. */
1314 #define Y_MASK (((unsigned long) 1) << 21)
1315 #define AT1_MASK (((unsigned long) 3) << 21)
1316 #define AT2_MASK (((unsigned long) 9) << 21)
1317 #define BBOY_MASK (BBO_MASK &~ Y_MASK)
1318 #define BBOAT_MASK (BBO_MASK &~ AT1_MASK)
1320 /* A B form instruction setting the BO field and the condition bits of
1322 #define BBOCB(op, bo, cb, aa, lk) \
1323 (BBO ((op), (bo), (aa), (lk)) | ((((unsigned long)(cb)) & 0x3) << 16))
1324 #define BBOCB_MASK BBOCB (0x3f, 0x1f, 0x3, 1, 1)
1326 /* A BBOCB_MASK with the y bit of the BO field removed. */
1327 #define BBOYCB_MASK (BBOCB_MASK &~ Y_MASK)
1328 #define BBOATCB_MASK (BBOCB_MASK &~ AT1_MASK)
1329 #define BBOAT2CB_MASK (BBOCB_MASK &~ AT2_MASK)
1331 /* A BBOYCB_MASK in which the BI field is fixed. */
1332 #define BBOYBI_MASK (BBOYCB_MASK | BI_MASK)
1333 #define BBOATBI_MASK (BBOAT2CB_MASK | BI_MASK)
1335 /* The main opcode mask with the RA field clear. */
1336 #define DRA_MASK (OP_MASK | RA_MASK)
1338 /* A DS form instruction. */
1339 #define DSO(op, xop) (OP (op) | ((xop) & 0x3))
1340 #define DS_MASK DSO (0x3f, 3)
1342 /* A DE form instruction. */
1343 #define DEO(op, xop) (OP (op) | ((xop) & 0xf))
1344 #define DE_MASK DEO (0x3e, 0xf)
1346 /* An M form instruction. */
1347 #define M(op, rc) (OP (op) | ((rc) & 1))
1348 #define M_MASK M (0x3f, 1)
1350 /* An M form instruction with the ME field specified. */
1351 #define MME(op, me, rc) (M ((op), (rc)) | ((((unsigned long)(me)) & 0x1f) << 1))
1353 /* An M_MASK with the MB and ME fields fixed. */
1354 #define MMBME_MASK (M_MASK | MB_MASK | ME_MASK)
1356 /* An M_MASK with the SH and ME fields fixed. */
1357 #define MSHME_MASK (M_MASK | SH_MASK | ME_MASK)
1359 /* An MD form instruction. */
1360 #define MD(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0x7) << 2) | ((rc) & 1))
1361 #define MD_MASK MD (0x3f, 0x7, 1)
1363 /* An MD_MASK with the MB field fixed. */
1364 #define MDMB_MASK (MD_MASK | MB6_MASK)
1366 /* An MD_MASK with the SH field fixed. */
1367 #define MDSH_MASK (MD_MASK | SH6_MASK)
1369 /* An MDS form instruction. */
1370 #define MDS(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0xf) << 1) | ((rc) & 1))
1371 #define MDS_MASK MDS (0x3f, 0xf, 1)
1373 /* An MDS_MASK with the MB field fixed. */
1374 #define MDSMB_MASK (MDS_MASK | MB6_MASK)
1376 /* An SC form instruction. */
1377 #define SC(op, sa, lk) (OP (op) | ((((unsigned long)(sa)) & 1) << 1) | ((lk) & 1))
1378 #define SC_MASK (OP_MASK | (((unsigned long)0x3ff) << 16) | (((unsigned long)1) << 1) | 1)
1380 /* An VX form instruction. */
1381 #define VX(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x7ff))
1383 /* The mask for an VX form instruction. */
1384 #define VX_MASK VX(0x3f, 0x7ff)
1386 /* An VA form instruction. */
1387 #define VXA(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x03f))
1389 /* The mask for an VA form instruction. */
1390 #define VXA_MASK VXA(0x3f, 0x3f)
1392 /* An VXR form instruction. */
1393 #define VXR(op, xop, rc) (OP (op) | (((rc) & 1) << 10) | (((unsigned long)(xop)) & 0x3ff))
1395 /* The mask for a VXR form instruction. */
1396 #define VXR_MASK VXR(0x3f, 0x3ff, 1)
1398 /* An X form instruction. */
1399 #define X(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x3ff) << 1))
1401 /* An X form instruction with the RC bit specified. */
1402 #define XRC(op, xop, rc) (X ((op), (xop)) | ((rc) & 1))
1404 /* The mask for an X form instruction. */
1405 #define X_MASK XRC (0x3f, 0x3ff, 1)
1407 /* An X_MASK with the RA field fixed. */
1408 #define XRA_MASK (X_MASK | RA_MASK)
1410 /* An X_MASK with the RB field fixed. */
1411 #define XRB_MASK (X_MASK | RB_MASK)
1413 /* An X_MASK with the RT field fixed. */
1414 #define XRT_MASK (X_MASK | RT_MASK)
1416 /* An X_MASK with the RA and RB fields fixed. */
1417 #define XRARB_MASK (X_MASK | RA_MASK | RB_MASK)
1419 /* An XRARB_MASK, but with the L bit clear. */
1420 #define XRLARB_MASK (XRARB_MASK & ~((unsigned long) 1 << 16))
1422 /* An X_MASK with the RT and RA fields fixed. */
1423 #define XRTRA_MASK (X_MASK | RT_MASK | RA_MASK)
1425 /* An XRTRA_MASK, but with L bit clear. */
1426 #define XRTLRA_MASK (XRTRA_MASK & ~((unsigned long) 1 << 21))
1428 /* An X form comparison instruction. */
1429 #define XCMPL(op, xop, l) (X ((op), (xop)) | ((((unsigned long)(l)) & 1) << 21))
1431 /* The mask for an X form comparison instruction. */
1432 #define XCMP_MASK (X_MASK | (((unsigned long)1) << 22))
1434 /* The mask for an X form comparison instruction with the L field
1436 #define XCMPL_MASK (XCMP_MASK | (((unsigned long)1) << 21))
1438 /* An X form trap instruction with the TO field specified. */
1439 #define XTO(op, xop, to) (X ((op), (xop)) | ((((unsigned long)(to)) & 0x1f) << 21))
1440 #define XTO_MASK (X_MASK | TO_MASK)
1442 /* An X form tlb instruction with the SH field specified. */
1443 #define XTLB(op, xop, sh) (X ((op), (xop)) | ((((unsigned long)(sh)) & 0x1f) << 11))
1444 #define XTLB_MASK (X_MASK | SH_MASK)
1446 /* An X form sync instruction. */
1447 #define XSYNC(op, xop, l) (X ((op), (xop)) | ((((unsigned long)(l)) & 3) << 21))
1449 /* An X form sync instruction with everything filled in except the LS field. */
1450 #define XSYNC_MASK (0xff9fffff)
1452 /* An X form AltiVec dss instruction. */
1453 #define XDSS(op, xop, a) (X ((op), (xop)) | ((((unsigned long)(a)) & 1) << 25))
1454 #define XDSS_MASK XDSS(0x3f, 0x3ff, 1)
1456 /* An XFL form instruction. */
1457 #define XFL(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0x3ff) << 1) | (((unsigned long)(rc)) & 1))
1458 #define XFL_MASK (XFL (0x3f, 0x3ff, 1) | (((unsigned long)1) << 25) | (((unsigned long)1) << 16))
1460 /* An XL form instruction with the LK field set to 0. */
1461 #define XL(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x3ff) << 1))
1463 /* An XL form instruction which uses the LK field. */
1464 #define XLLK(op, xop, lk) (XL ((op), (xop)) | ((lk) & 1))
1466 /* The mask for an XL form instruction. */
1467 #define XL_MASK XLLK (0x3f, 0x3ff, 1)
1469 /* An XL form instruction which explicitly sets the BO field. */
1470 #define XLO(op, bo, xop, lk) \
1471 (XLLK ((op), (xop), (lk)) | ((((unsigned long)(bo)) & 0x1f) << 21))
1472 #define XLO_MASK (XL_MASK | BO_MASK)
1474 /* An XL form instruction which explicitly sets the y bit of the BO
1476 #define XLYLK(op, xop, y, lk) (XLLK ((op), (xop), (lk)) | ((((unsigned long)(y)) & 1) << 21))
1477 #define XLYLK_MASK (XL_MASK | Y_MASK)
1479 /* An XL form instruction which sets the BO field and the condition
1480 bits of the BI field. */
1481 #define XLOCB(op, bo, cb, xop, lk) \
1482 (XLO ((op), (bo), (xop), (lk)) | ((((unsigned long)(cb)) & 3) << 16))
1483 #define XLOCB_MASK XLOCB (0x3f, 0x1f, 0x3, 0x3ff, 1)
1485 /* An XL_MASK or XLYLK_MASK or XLOCB_MASK with the BB field fixed. */
1486 #define XLBB_MASK (XL_MASK | BB_MASK)
1487 #define XLYBB_MASK (XLYLK_MASK | BB_MASK)
1488 #define XLBOCBBB_MASK (XLOCB_MASK | BB_MASK)
1490 /* An XL_MASK with the BO and BB fields fixed. */
1491 #define XLBOBB_MASK (XL_MASK | BO_MASK | BB_MASK)
1493 /* An XL_MASK with the BO, BI and BB fields fixed. */
1494 #define XLBOBIBB_MASK (XL_MASK | BO_MASK | BI_MASK | BB_MASK)
1496 /* An XO form instruction. */
1497 #define XO(op, xop, oe, rc) \
1498 (OP (op) | ((((unsigned long)(xop)) & 0x1ff) << 1) | ((((unsigned long)(oe)) & 1) << 10) | (((unsigned long)(rc)) & 1))
1499 #define XO_MASK XO (0x3f, 0x1ff, 1, 1)
1501 /* An XO_MASK with the RB field fixed. */
1502 #define XORB_MASK (XO_MASK | RB_MASK)
1504 /* An XS form instruction. */
1505 #define XS(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0x1ff) << 2) | (((unsigned long)(rc)) & 1))
1506 #define XS_MASK XS (0x3f, 0x1ff, 1)
1508 /* A mask for the FXM version of an XFX form instruction. */
1509 #define XFXFXM_MASK (X_MASK | (((unsigned long)1) << 20) | (((unsigned long)1) << 11))
1511 /* An XFX form instruction with the FXM field filled in. */
1512 #define XFXM(op, xop, fxm) \
1513 (X ((op), (xop)) | ((((unsigned long)(fxm)) & 0xff) << 12))
1515 /* An XFX form instruction with the SPR field filled in. */
1516 #define XSPR(op, xop, spr) \
1517 (X ((op), (xop)) | ((((unsigned long)(spr)) & 0x1f) << 16) | ((((unsigned long)(spr)) & 0x3e0) << 6))
1518 #define XSPR_MASK (X_MASK | SPR_MASK)
1520 /* An XFX form instruction with the SPR field filled in except for the
1522 #define XSPRBAT_MASK (XSPR_MASK &~ SPRBAT_MASK)
1524 /* An XFX form instruction with the SPR field filled in except for the
1526 #define XSPRG_MASK (XSPR_MASK &~ SPRG_MASK)
1528 /* An X form instruction with everything filled in except the E field. */
1529 #define XE_MASK (0xffff7fff)
1531 /* The BO encodings used in extended conditional branch mnemonics. */
1532 #define BODNZF (0x0)
1533 #define BODNZFP (0x1)
1535 #define BODZFP (0x3)
1536 #define BODNZT (0x8)
1537 #define BODNZTP (0x9)
1539 #define BODZTP (0xb)
1550 #define BODNZ (0x10)
1551 #define BODNZP (0x11)
1553 #define BODZP (0x13)
1554 #define BODNZM4 (0x18)
1555 #define BODNZP4 (0x19)
1556 #define BODZM4 (0x1a)
1557 #define BODZP4 (0x1b)
1561 /* The BI condition bit encodings used in extended conditional branch
1568 /* The TO encodings used in extended trap mnemonics. */
1585 /* Smaller names for the flags so each entry in the opcodes table will
1586 fit on a single line. */
1588 #define PPC PPC_OPCODE_PPC | PPC_OPCODE_ANY
1589 #define PPCCOM PPC_OPCODE_PPC | PPC_OPCODE_COMMON | PPC_OPCODE_ANY
1590 #define NOPOWER4 PPC_OPCODE_NOPOWER4 | PPCCOM
1591 #define POWER4 PPC_OPCODE_POWER4 | PPCCOM
1592 #define PPC32 PPC_OPCODE_32 | PPC_OPCODE_PPC | PPC_OPCODE_ANY
1593 #define PPC64 PPC_OPCODE_64 | PPC_OPCODE_PPC | PPC_OPCODE_ANY
1594 #define PPCONLY PPC_OPCODE_PPC
1595 #define PPC403 PPC_OPCODE_403
1596 #define PPC405 PPC403
1599 #define PPCVEC PPC_OPCODE_ALTIVEC | PPC_OPCODE_ANY | PPC_OPCODE_PPC
1600 #define POWER PPC_OPCODE_POWER | PPC_OPCODE_ANY
1601 #define POWER2 PPC_OPCODE_POWER | PPC_OPCODE_POWER2 | PPC_OPCODE_ANY
1602 #define PPCPWR2 PPC_OPCODE_PPC | PPC_OPCODE_POWER | PPC_OPCODE_POWER2 | PPC_OPCODE_ANY
1603 #define POWER32 PPC_OPCODE_POWER | PPC_OPCODE_ANY | PPC_OPCODE_32
1604 #define COM PPC_OPCODE_POWER | PPC_OPCODE_PPC | PPC_OPCODE_COMMON | PPC_OPCODE_ANY
1605 #define COM32 PPC_OPCODE_POWER | PPC_OPCODE_PPC | PPC_OPCODE_COMMON | PPC_OPCODE_ANY | PPC_OPCODE_32
1606 #define M601 PPC_OPCODE_POWER | PPC_OPCODE_601 | PPC_OPCODE_ANY
1607 #define PWRCOM PPC_OPCODE_POWER | PPC_OPCODE_601 | PPC_OPCODE_COMMON | PPC_OPCODE_ANY
1608 #define MFDEC1 PPC_OPCODE_POWER
1609 #define MFDEC2 PPC_OPCODE_PPC | PPC_OPCODE_601
1610 #define BOOKE PPC_OPCODE_BOOKE
1611 #define BOOKE64 PPC_OPCODE_BOOKE64
1613 /* The opcode table.
1615 The format of the opcode table is:
1617 NAME OPCODE MASK FLAGS { OPERANDS }
1619 NAME is the name of the instruction.
1620 OPCODE is the instruction opcode.
1621 MASK is the opcode mask; this is used to tell the disassembler
1622 which bits in the actual opcode must match OPCODE.
1623 FLAGS are flags indicated what processors support the instruction.
1624 OPERANDS is the list of operands.
1626 The disassembler reads the table in order and prints the first
1627 instruction which matches, so this table is sorted to put more
1628 specific instructions before more general instructions. It is also
1629 sorted by major opcode. */
1631 const struct powerpc_opcode powerpc_opcodes
[] = {
1632 { "tdlgti", OPTO(2,TOLGT
), OPTO_MASK
, PPC64
, { RA
, SI
} },
1633 { "tdllti", OPTO(2,TOLLT
), OPTO_MASK
, PPC64
, { RA
, SI
} },
1634 { "tdeqi", OPTO(2,TOEQ
), OPTO_MASK
, PPC64
, { RA
, SI
} },
1635 { "tdlgei", OPTO(2,TOLGE
), OPTO_MASK
, PPC64
, { RA
, SI
} },
1636 { "tdlnli", OPTO(2,TOLNL
), OPTO_MASK
, PPC64
, { RA
, SI
} },
1637 { "tdllei", OPTO(2,TOLLE
), OPTO_MASK
, PPC64
, { RA
, SI
} },
1638 { "tdlngi", OPTO(2,TOLNG
), OPTO_MASK
, PPC64
, { RA
, SI
} },
1639 { "tdgti", OPTO(2,TOGT
), OPTO_MASK
, PPC64
, { RA
, SI
} },
1640 { "tdgei", OPTO(2,TOGE
), OPTO_MASK
, PPC64
, { RA
, SI
} },
1641 { "tdnli", OPTO(2,TONL
), OPTO_MASK
, PPC64
, { RA
, SI
} },
1642 { "tdlti", OPTO(2,TOLT
), OPTO_MASK
, PPC64
, { RA
, SI
} },
1643 { "tdlei", OPTO(2,TOLE
), OPTO_MASK
, PPC64
, { RA
, SI
} },
1644 { "tdngi", OPTO(2,TONG
), OPTO_MASK
, PPC64
, { RA
, SI
} },
1645 { "tdnei", OPTO(2,TONE
), OPTO_MASK
, PPC64
, { RA
, SI
} },
1646 { "tdi", OP(2), OP_MASK
, PPC64
, { TO
, RA
, SI
} },
1648 { "twlgti", OPTO(3,TOLGT
), OPTO_MASK
, PPCCOM
, { RA
, SI
} },
1649 { "tlgti", OPTO(3,TOLGT
), OPTO_MASK
, PWRCOM
, { RA
, SI
} },
1650 { "twllti", OPTO(3,TOLLT
), OPTO_MASK
, PPCCOM
, { RA
, SI
} },
1651 { "tllti", OPTO(3,TOLLT
), OPTO_MASK
, PWRCOM
, { RA
, SI
} },
1652 { "tweqi", OPTO(3,TOEQ
), OPTO_MASK
, PPCCOM
, { RA
, SI
} },
1653 { "teqi", OPTO(3,TOEQ
), OPTO_MASK
, PWRCOM
, { RA
, SI
} },
1654 { "twlgei", OPTO(3,TOLGE
), OPTO_MASK
, PPCCOM
, { RA
, SI
} },
1655 { "tlgei", OPTO(3,TOLGE
), OPTO_MASK
, PWRCOM
, { RA
, SI
} },
1656 { "twlnli", OPTO(3,TOLNL
), OPTO_MASK
, PPCCOM
, { RA
, SI
} },
1657 { "tlnli", OPTO(3,TOLNL
), OPTO_MASK
, PWRCOM
, { RA
, SI
} },
1658 { "twllei", OPTO(3,TOLLE
), OPTO_MASK
, PPCCOM
, { RA
, SI
} },
1659 { "tllei", OPTO(3,TOLLE
), OPTO_MASK
, PWRCOM
, { RA
, SI
} },
1660 { "twlngi", OPTO(3,TOLNG
), OPTO_MASK
, PPCCOM
, { RA
, SI
} },
1661 { "tlngi", OPTO(3,TOLNG
), OPTO_MASK
, PWRCOM
, { RA
, SI
} },
1662 { "twgti", OPTO(3,TOGT
), OPTO_MASK
, PPCCOM
, { RA
, SI
} },
1663 { "tgti", OPTO(3,TOGT
), OPTO_MASK
, PWRCOM
, { RA
, SI
} },
1664 { "twgei", OPTO(3,TOGE
), OPTO_MASK
, PPCCOM
, { RA
, SI
} },
1665 { "tgei", OPTO(3,TOGE
), OPTO_MASK
, PWRCOM
, { RA
, SI
} },
1666 { "twnli", OPTO(3,TONL
), OPTO_MASK
, PPCCOM
, { RA
, SI
} },
1667 { "tnli", OPTO(3,TONL
), OPTO_MASK
, PWRCOM
, { RA
, SI
} },
1668 { "twlti", OPTO(3,TOLT
), OPTO_MASK
, PPCCOM
, { RA
, SI
} },
1669 { "tlti", OPTO(3,TOLT
), OPTO_MASK
, PWRCOM
, { RA
, SI
} },
1670 { "twlei", OPTO(3,TOLE
), OPTO_MASK
, PPCCOM
, { RA
, SI
} },
1671 { "tlei", OPTO(3,TOLE
), OPTO_MASK
, PWRCOM
, { RA
, SI
} },
1672 { "twngi", OPTO(3,TONG
), OPTO_MASK
, PPCCOM
, { RA
, SI
} },
1673 { "tngi", OPTO(3,TONG
), OPTO_MASK
, PWRCOM
, { RA
, SI
} },
1674 { "twnei", OPTO(3,TONE
), OPTO_MASK
, PPCCOM
, { RA
, SI
} },
1675 { "tnei", OPTO(3,TONE
), OPTO_MASK
, PWRCOM
, { RA
, SI
} },
1676 { "twi", OP(3), OP_MASK
, PPCCOM
, { TO
, RA
, SI
} },
1677 { "ti", OP(3), OP_MASK
, PWRCOM
, { TO
, RA
, SI
} },
1679 { "macchw", XO(4,172,0,0), XO_MASK
, PPC405
, { RT
, RA
, RB
} },
1680 { "macchw.", XO(4,172,0,1), XO_MASK
, PPC405
, { RT
, RA
, RB
} },
1681 { "macchwo", XO(4,172,1,0), XO_MASK
, PPC405
, { RT
, RA
, RB
} },
1682 { "macchwo.", XO(4,172,1,1), XO_MASK
, PPC405
, { RT
, RA
, RB
} },
1683 { "macchws", XO(4,236,0,0), XO_MASK
, PPC405
, { RT
, RA
, RB
} },
1684 { "macchws.", XO(4,236,0,1), XO_MASK
, PPC405
, { RT
, RA
, RB
} },
1685 { "macchwso", XO(4,236,1,0), XO_MASK
, PPC405
, { RT
, RA
, RB
} },
1686 { "macchwso.", XO(4,236,1,1), XO_MASK
, PPC405
, { RT
, RA
, RB
} },
1687 { "macchwsu", XO(4,204,0,0), XO_MASK
, PPC405
, { RT
, RA
, RB
} },
1688 { "macchwsu.", XO(4,204,0,1), XO_MASK
, PPC405
, { RT
, RA
, RB
} },
1689 { "macchwsuo", XO(4,204,1,0), XO_MASK
, PPC405
, { RT
, RA
, RB
} },
1690 { "macchwsuo.", XO(4,204,1,1), XO_MASK
, PPC405
, { RT
, RA
, RB
} },
1691 { "macchwu", XO(4,140,0,0), XO_MASK
, PPC405
, { RT
, RA
, RB
} },
1692 { "macchwu.", XO(4,140,0,1), XO_MASK
, PPC405
, { RT
, RA
, RB
} },
1693 { "macchwuo", XO(4,140,1,0), XO_MASK
, PPC405
, { RT
, RA
, RB
} },
1694 { "macchwuo.", XO(4,140,1,1), XO_MASK
, PPC405
, { RT
, RA
, RB
} },
1695 { "machhw", XO(4,44,0,0), XO_MASK
, PPC405
, { RT
, RA
, RB
} },
1696 { "machhw.", XO(4,44,0,1), XO_MASK
, PPC405
, { RT
, RA
, RB
} },
1697 { "machhwo", XO(4,44,1,0), XO_MASK
, PPC405
, { RT
, RA
, RB
} },
1698 { "machhwo.", XO(4,44,1,1), XO_MASK
, PPC405
, { RT
, RA
, RB
} },
1699 { "machhws", XO(4,108,0,0), XO_MASK
, PPC405
, { RT
, RA
, RB
} },
1700 { "machhws.", XO(4,108,0,1), XO_MASK
, PPC405
, { RT
, RA
, RB
} },
1701 { "machhwso", XO(4,108,1,0), XO_MASK
, PPC405
, { RT
, RA
, RB
} },
1702 { "machhwso.", XO(4,108,1,1), XO_MASK
, PPC405
, { RT
, RA
, RB
} },
1703 { "machhwsu", XO(4,76,0,0), XO_MASK
, PPC405
, { RT
, RA
, RB
} },
1704 { "machhwsu.", XO(4,76,0,1), XO_MASK
, PPC405
, { RT
, RA
, RB
} },
1705 { "machhwsuo", XO(4,76,1,0), XO_MASK
, PPC405
, { RT
, RA
, RB
} },
1706 { "machhwsuo.", XO(4,76,1,1), XO_MASK
, PPC405
, { RT
, RA
, RB
} },
1707 { "machhwu", XO(4,12,0,0), XO_MASK
, PPC405
, { RT
, RA
, RB
} },
1708 { "machhwu.", XO(4,12,0,1), XO_MASK
, PPC405
, { RT
, RA
, RB
} },
1709 { "machhwuo", XO(4,12,1,0), XO_MASK
, PPC405
, { RT
, RA
, RB
} },
1710 { "machhwuo.", XO(4,12,1,1), XO_MASK
, PPC405
, { RT
, RA
, RB
} },
1711 { "maclhw", XO(4,428,0,0), XO_MASK
, PPC405
, { RT
, RA
, RB
} },
1712 { "maclhw.", XO(4,428,0,1), XO_MASK
, PPC405
, { RT
, RA
, RB
} },
1713 { "maclhwo", XO(4,428,1,0), XO_MASK
, PPC405
, { RT
, RA
, RB
} },
1714 { "maclhwo.", XO(4,428,1,1), XO_MASK
, PPC405
, { RT
, RA
, RB
} },
1715 { "maclhws", XO(4,492,0,0), XO_MASK
, PPC405
, { RT
, RA
, RB
} },
1716 { "maclhws.", XO(4,492,0,1), XO_MASK
, PPC405
, { RT
, RA
, RB
} },
1717 { "maclhwso", XO(4,492,1,0), XO_MASK
, PPC405
, { RT
, RA
, RB
} },
1718 { "maclhwso.", XO(4,492,1,1), XO_MASK
, PPC405
, { RT
, RA
, RB
} },
1719 { "maclhwsu", XO(4,460,0,0), XO_MASK
, PPC405
, { RT
, RA
, RB
} },
1720 { "maclhwsu.", XO(4,460,0,1), XO_MASK
, PPC405
, { RT
, RA
, RB
} },
1721 { "maclhwsuo", XO(4,460,1,0), XO_MASK
, PPC405
, { RT
, RA
, RB
} },
1722 { "maclhwsuo.", XO(4,460,1,1), XO_MASK
, PPC405
, { RT
, RA
, RB
} },
1723 { "maclhwu", XO(4,396,0,0), XO_MASK
, PPC405
, { RT
, RA
, RB
} },
1724 { "maclhwu.", XO(4,396,0,1), XO_MASK
, PPC405
, { RT
, RA
, RB
} },
1725 { "maclhwuo", XO(4,396,1,0), XO_MASK
, PPC405
, { RT
, RA
, RB
} },
1726 { "maclhwuo.", XO(4,396,1,1), XO_MASK
, PPC405
, { RT
, RA
, RB
} },
1727 { "mulchw", XRC(4,168,0), X_MASK
, PPC405
, { RT
, RA
, RB
} },
1728 { "mulchw.", XRC(4,168,1), X_MASK
, PPC405
, { RT
, RA
, RB
} },
1729 { "mulchwu", XRC(4,136,0), X_MASK
, PPC405
, { RT
, RA
, RB
} },
1730 { "mulchwu.", XRC(4,136,1), X_MASK
, PPC405
, { RT
, RA
, RB
} },
1731 { "mulhhw", XRC(4,40,0), X_MASK
, PPC405
, { RT
, RA
, RB
} },
1732 { "mulhhw.", XRC(4,40,1), X_MASK
, PPC405
, { RT
, RA
, RB
} },
1733 { "mulhhwu", XRC(4,8,0), X_MASK
, PPC405
, { RT
, RA
, RB
} },
1734 { "mulhhwu.", XRC(4,8,1), X_MASK
, PPC405
, { RT
, RA
, RB
} },
1735 { "mullhw", XRC(4,424,0), X_MASK
, PPC405
, { RT
, RA
, RB
} },
1736 { "mullhw.", XRC(4,424,1), X_MASK
, PPC405
, { RT
, RA
, RB
} },
1737 { "mullhwu", XRC(4,392,0), X_MASK
, PPC405
, { RT
, RA
, RB
} },
1738 { "mullhwu.", XRC(4,392,1), X_MASK
, PPC405
, { RT
, RA
, RB
} },
1739 { "nmacchw", XO(4,174,0,0), XO_MASK
, PPC405
, { RT
, RA
, RB
} },
1740 { "nmacchw.", XO(4,174,0,1), XO_MASK
, PPC405
, { RT
, RA
, RB
} },
1741 { "nmacchwo", XO(4,174,1,0), XO_MASK
, PPC405
, { RT
, RA
, RB
} },
1742 { "nmacchwo.", XO(4,174,1,1), XO_MASK
, PPC405
, { RT
, RA
, RB
} },
1743 { "nmacchws", XO(4,238,0,0), XO_MASK
, PPC405
, { RT
, RA
, RB
} },
1744 { "nmacchws.", XO(4,238,0,1), XO_MASK
, PPC405
, { RT
, RA
, RB
} },
1745 { "nmacchwso", XO(4,238,1,0), XO_MASK
, PPC405
, { RT
, RA
, RB
} },
1746 { "nmacchwso.", XO(4,238,1,1), XO_MASK
, PPC405
, { RT
, RA
, RB
} },
1747 { "nmachhw", XO(4,46,0,0), XO_MASK
, PPC405
, { RT
, RA
, RB
} },
1748 { "nmachhw.", XO(4,46,0,1), XO_MASK
, PPC405
, { RT
, RA
, RB
} },
1749 { "nmachhwo", XO(4,46,1,0), XO_MASK
, PPC405
, { RT
, RA
, RB
} },
1750 { "nmachhwo.", XO(4,46,1,1), XO_MASK
, PPC405
, { RT
, RA
, RB
} },
1751 { "nmachhws", XO(4,110,0,0), XO_MASK
, PPC405
, { RT
, RA
, RB
} },
1752 { "nmachhws.", XO(4,110,0,1), XO_MASK
, PPC405
, { RT
, RA
, RB
} },
1753 { "nmachhwso", XO(4,110,1,0), XO_MASK
, PPC405
, { RT
, RA
, RB
} },
1754 { "nmachhwso.", XO(4,110,1,1), XO_MASK
, PPC405
, { RT
, RA
, RB
} },
1755 { "nmaclhw", XO(4,430,0,0), XO_MASK
, PPC405
, { RT
, RA
, RB
} },
1756 { "nmaclhw.", XO(4,430,0,1), XO_MASK
, PPC405
, { RT
, RA
, RB
} },
1757 { "nmaclhwo", XO(4,430,1,0), XO_MASK
, PPC405
, { RT
, RA
, RB
} },
1758 { "nmaclhwo.", XO(4,430,1,1), XO_MASK
, PPC405
, { RT
, RA
, RB
} },
1759 { "nmaclhws", XO(4,494,0,0), XO_MASK
, PPC405
, { RT
, RA
, RB
} },
1760 { "nmaclhws.", XO(4,494,0,1), XO_MASK
, PPC405
, { RT
, RA
, RB
} },
1761 { "nmaclhwso", XO(4,494,1,0), XO_MASK
, PPC405
, { RT
, RA
, RB
} },
1762 { "nmaclhwso.", XO(4,494,1,1), XO_MASK
, PPC405
, { RT
, RA
, RB
} },
1763 { "mfvscr", VX(4, 1540), VX_MASK
, PPCVEC
, { VD
} },
1764 { "mtvscr", VX(4, 1604), VX_MASK
, PPCVEC
, { VB
} },
1765 { "vaddcuw", VX(4, 384), VX_MASK
, PPCVEC
, { VD
, VA
, VB
} },
1766 { "vaddfp", VX(4, 10), VX_MASK
, PPCVEC
, { VD
, VA
, VB
} },
1767 { "vaddsbs", VX(4, 768), VX_MASK
, PPCVEC
, { VD
, VA
, VB
} },
1768 { "vaddshs", VX(4, 832), VX_MASK
, PPCVEC
, { VD
, VA
, VB
} },
1769 { "vaddsws", VX(4, 896), VX_MASK
, PPCVEC
, { VD
, VA
, VB
} },
1770 { "vaddubm", VX(4, 0), VX_MASK
, PPCVEC
, { VD
, VA
, VB
} },
1771 { "vaddubs", VX(4, 512), VX_MASK
, PPCVEC
, { VD
, VA
, VB
} },
1772 { "vadduhm", VX(4, 64), VX_MASK
, PPCVEC
, { VD
, VA
, VB
} },
1773 { "vadduhs", VX(4, 576), VX_MASK
, PPCVEC
, { VD
, VA
, VB
} },
1774 { "vadduwm", VX(4, 128), VX_MASK
, PPCVEC
, { VD
, VA
, VB
} },
1775 { "vadduws", VX(4, 640), VX_MASK
, PPCVEC
, { VD
, VA
, VB
} },
1776 { "vand", VX(4, 1028), VX_MASK
, PPCVEC
, { VD
, VA
, VB
} },
1777 { "vandc", VX(4, 1092), VX_MASK
, PPCVEC
, { VD
, VA
, VB
} },
1778 { "vavgsb", VX(4, 1282), VX_MASK
, PPCVEC
, { VD
, VA
, VB
} },
1779 { "vavgsh", VX(4, 1346), VX_MASK
, PPCVEC
, { VD
, VA
, VB
} },
1780 { "vavgsw", VX(4, 1410), VX_MASK
, PPCVEC
, { VD
, VA
, VB
} },
1781 { "vavgub", VX(4, 1026), VX_MASK
, PPCVEC
, { VD
, VA
, VB
} },
1782 { "vavguh", VX(4, 1090), VX_MASK
, PPCVEC
, { VD
, VA
, VB
} },
1783 { "vavguw", VX(4, 1154), VX_MASK
, PPCVEC
, { VD
, VA
, VB
} },
1784 { "vcfsx", VX(4, 842), VX_MASK
, PPCVEC
, { VD
, VB
, UIMM
} },
1785 { "vcfux", VX(4, 778), VX_MASK
, PPCVEC
, { VD
, VB
, UIMM
} },
1786 { "vcmpbfp", VXR(4, 966, 0), VXR_MASK
, PPCVEC
, { VD
, VA
, VB
} },
1787 { "vcmpbfp.", VXR(4, 966, 1), VXR_MASK
, PPCVEC
, { VD
, VA
, VB
} },
1788 { "vcmpeqfp", VXR(4, 198, 0), VXR_MASK
, PPCVEC
, { VD
, VA
, VB
} },
1789 { "vcmpeqfp.", VXR(4, 198, 1), VXR_MASK
, PPCVEC
, { VD
, VA
, VB
} },
1790 { "vcmpequb", VXR(4, 6, 0), VXR_MASK
, PPCVEC
, { VD
, VA
, VB
} },
1791 { "vcmpequb.", VXR(4, 6, 1), VXR_MASK
, PPCVEC
, { VD
, VA
, VB
} },
1792 { "vcmpequh", VXR(4, 70, 0), VXR_MASK
, PPCVEC
, { VD
, VA
, VB
} },
1793 { "vcmpequh.", VXR(4, 70, 1), VXR_MASK
, PPCVEC
, { VD
, VA
, VB
} },
1794 { "vcmpequw", VXR(4, 134, 0), VXR_MASK
, PPCVEC
, { VD
, VA
, VB
} },
1795 { "vcmpequw.", VXR(4, 134, 1), VXR_MASK
, PPCVEC
, { VD
, VA
, VB
} },
1796 { "vcmpgefp", VXR(4, 454, 0), VXR_MASK
, PPCVEC
, { VD
, VA
, VB
} },
1797 { "vcmpgefp.", VXR(4, 454, 1), VXR_MASK
, PPCVEC
, { VD
, VA
, VB
} },
1798 { "vcmpgtfp", VXR(4, 710, 0), VXR_MASK
, PPCVEC
, { VD
, VA
, VB
} },
1799 { "vcmpgtfp.", VXR(4, 710, 1), VXR_MASK
, PPCVEC
, { VD
, VA
, VB
} },
1800 { "vcmpgtsb", VXR(4, 774, 0), VXR_MASK
, PPCVEC
, { VD
, VA
, VB
} },
1801 { "vcmpgtsb.", VXR(4, 774, 1), VXR_MASK
, PPCVEC
, { VD
, VA
, VB
} },
1802 { "vcmpgtsh", VXR(4, 838, 0), VXR_MASK
, PPCVEC
, { VD
, VA
, VB
} },
1803 { "vcmpgtsh.", VXR(4, 838, 1), VXR_MASK
, PPCVEC
, { VD
, VA
, VB
} },
1804 { "vcmpgtsw", VXR(4, 902, 0), VXR_MASK
, PPCVEC
, { VD
, VA
, VB
} },
1805 { "vcmpgtsw.", VXR(4, 902, 1), VXR_MASK
, PPCVEC
, { VD
, VA
, VB
} },
1806 { "vcmpgtub", VXR(4, 518, 0), VXR_MASK
, PPCVEC
, { VD
, VA
, VB
} },
1807 { "vcmpgtub.", VXR(4, 518, 1), VXR_MASK
, PPCVEC
, { VD
, VA
, VB
} },
1808 { "vcmpgtuh", VXR(4, 582, 0), VXR_MASK
, PPCVEC
, { VD
, VA
, VB
} },
1809 { "vcmpgtuh.", VXR(4, 582, 1), VXR_MASK
, PPCVEC
, { VD
, VA
, VB
} },
1810 { "vcmpgtuw", VXR(4, 646, 0), VXR_MASK
, PPCVEC
, { VD
, VA
, VB
} },
1811 { "vcmpgtuw.", VXR(4, 646, 1), VXR_MASK
, PPCVEC
, { VD
, VA
, VB
} },
1812 { "vctsxs", VX(4, 970), VX_MASK
, PPCVEC
, { VD
, VB
, UIMM
} },
1813 { "vctuxs", VX(4, 906), VX_MASK
, PPCVEC
, { VD
, VB
, UIMM
} },
1814 { "vexptefp", VX(4, 394), VX_MASK
, PPCVEC
, { VD
, VB
} },
1815 { "vlogefp", VX(4, 458), VX_MASK
, PPCVEC
, { VD
, VB
} },
1816 { "vmaddfp", VXA(4, 46), VXA_MASK
, PPCVEC
, { VD
, VA
, VC
, VB
} },
1817 { "vmaxfp", VX(4, 1034), VX_MASK
, PPCVEC
, { VD
, VA
, VB
} },
1818 { "vmaxsb", VX(4, 258), VX_MASK
, PPCVEC
, { VD
, VA
, VB
} },
1819 { "vmaxsh", VX(4, 322), VX_MASK
, PPCVEC
, { VD
, VA
, VB
} },
1820 { "vmaxsw", VX(4, 386), VX_MASK
, PPCVEC
, { VD
, VA
, VB
} },
1821 { "vmaxub", VX(4, 2), VX_MASK
, PPCVEC
, { VD
, VA
, VB
} },
1822 { "vmaxuh", VX(4, 66), VX_MASK
, PPCVEC
, { VD
, VA
, VB
} },
1823 { "vmaxuw", VX(4, 130), VX_MASK
, PPCVEC
, { VD
, VA
, VB
} },
1824 { "vmhaddshs", VXA(4, 32), VXA_MASK
, PPCVEC
, { VD
, VA
, VB
, VC
} },
1825 { "vmhraddshs", VXA(4, 33), VXA_MASK
, PPCVEC
, { VD
, VA
, VB
, VC
} },
1826 { "vminfp", VX(4, 1098), VX_MASK
, PPCVEC
, { VD
, VA
, VB
} },
1827 { "vminsb", VX(4, 770), VX_MASK
, PPCVEC
, { VD
, VA
, VB
} },
1828 { "vminsh", VX(4, 834), VX_MASK
, PPCVEC
, { VD
, VA
, VB
} },
1829 { "vminsw", VX(4, 898), VX_MASK
, PPCVEC
, { VD
, VA
, VB
} },
1830 { "vminub", VX(4, 514), VX_MASK
, PPCVEC
, { VD
, VA
, VB
} },
1831 { "vminuh", VX(4, 578), VX_MASK
, PPCVEC
, { VD
, VA
, VB
} },
1832 { "vminuw", VX(4, 642), VX_MASK
, PPCVEC
, { VD
, VA
, VB
} },
1833 { "vmladduhm", VXA(4, 34), VXA_MASK
, PPCVEC
, { VD
, VA
, VB
, VC
} },
1834 { "vmrghb", VX(4, 12), VX_MASK
, PPCVEC
, { VD
, VA
, VB
} },
1835 { "vmrghh", VX(4, 76), VX_MASK
, PPCVEC
, { VD
, VA
, VB
} },
1836 { "vmrghw", VX(4, 140), VX_MASK
, PPCVEC
, { VD
, VA
, VB
} },
1837 { "vmrglb", VX(4, 268), VX_MASK
, PPCVEC
, { VD
, VA
, VB
} },
1838 { "vmrglh", VX(4, 332), VX_MASK
, PPCVEC
, { VD
, VA
, VB
} },
1839 { "vmrglw", VX(4, 396), VX_MASK
, PPCVEC
, { VD
, VA
, VB
} },
1840 { "vmsummbm", VXA(4, 37), VXA_MASK
, PPCVEC
, { VD
, VA
, VB
, VC
} },
1841 { "vmsumshm", VXA(4, 40), VXA_MASK
, PPCVEC
, { VD
, VA
, VB
, VC
} },
1842 { "vmsumshs", VXA(4, 41), VXA_MASK
, PPCVEC
, { VD
, VA
, VB
, VC
} },
1843 { "vmsumubm", VXA(4, 36), VXA_MASK
, PPCVEC
, { VD
, VA
, VB
, VC
} },
1844 { "vmsumuhm", VXA(4, 38), VXA_MASK
, PPCVEC
, { VD
, VA
, VB
, VC
} },
1845 { "vmsumuhs", VXA(4, 39), VXA_MASK
, PPCVEC
, { VD
, VA
, VB
, VC
} },
1846 { "vmulesb", VX(4, 776), VX_MASK
, PPCVEC
, { VD
, VA
, VB
} },
1847 { "vmulesh", VX(4, 840), VX_MASK
, PPCVEC
, { VD
, VA
, VB
} },
1848 { "vmuleub", VX(4, 520), VX_MASK
, PPCVEC
, { VD
, VA
, VB
} },
1849 { "vmuleuh", VX(4, 584), VX_MASK
, PPCVEC
, { VD
, VA
, VB
} },
1850 { "vmulosb", VX(4, 264), VX_MASK
, PPCVEC
, { VD
, VA
, VB
} },
1851 { "vmulosh", VX(4, 328), VX_MASK
, PPCVEC
, { VD
, VA
, VB
} },
1852 { "vmuloub", VX(4, 8), VX_MASK
, PPCVEC
, { VD
, VA
, VB
} },
1853 { "vmulouh", VX(4, 72), VX_MASK
, PPCVEC
, { VD
, VA
, VB
} },
1854 { "vnmsubfp", VXA(4, 47), VXA_MASK
, PPCVEC
, { VD
, VA
, VC
, VB
} },
1855 { "vnor", VX(4, 1284), VX_MASK
, PPCVEC
, { VD
, VA
, VB
} },
1856 { "vor", VX(4, 1156), VX_MASK
, PPCVEC
, { VD
, VA
, VB
} },
1857 { "vperm", VXA(4, 43), VXA_MASK
, PPCVEC
, { VD
, VA
, VB
, VC
} },
1858 { "vpkpx", VX(4, 782), VX_MASK
, PPCVEC
, { VD
, VA
, VB
} },
1859 { "vpkshss", VX(4, 398), VX_MASK
, PPCVEC
, { VD
, VA
, VB
} },
1860 { "vpkshus", VX(4, 270), VX_MASK
, PPCVEC
, { VD
, VA
, VB
} },
1861 { "vpkswss", VX(4, 462), VX_MASK
, PPCVEC
, { VD
, VA
, VB
} },
1862 { "vpkswus", VX(4, 334), VX_MASK
, PPCVEC
, { VD
, VA
, VB
} },
1863 { "vpkuhum", VX(4, 14), VX_MASK
, PPCVEC
, { VD
, VA
, VB
} },
1864 { "vpkuhus", VX(4, 142), VX_MASK
, PPCVEC
, { VD
, VA
, VB
} },
1865 { "vpkuwum", VX(4, 78), VX_MASK
, PPCVEC
, { VD
, VA
, VB
} },
1866 { "vpkuwus", VX(4, 206), VX_MASK
, PPCVEC
, { VD
, VA
, VB
} },
1867 { "vrefp", VX(4, 266), VX_MASK
, PPCVEC
, { VD
, VB
} },
1868 { "vrfim", VX(4, 714), VX_MASK
, PPCVEC
, { VD
, VB
} },
1869 { "vrfin", VX(4, 522), VX_MASK
, PPCVEC
, { VD
, VB
} },
1870 { "vrfip", VX(4, 650), VX_MASK
, PPCVEC
, { VD
, VB
} },
1871 { "vrfiz", VX(4, 586), VX_MASK
, PPCVEC
, { VD
, VB
} },
1872 { "vrlb", VX(4, 4), VX_MASK
, PPCVEC
, { VD
, VA
, VB
} },
1873 { "vrlh", VX(4, 68), VX_MASK
, PPCVEC
, { VD
, VA
, VB
} },
1874 { "vrlw", VX(4, 132), VX_MASK
, PPCVEC
, { VD
, VA
, VB
} },
1875 { "vrsqrtefp", VX(4, 330), VX_MASK
, PPCVEC
, { VD
, VB
} },
1876 { "vsel", VXA(4, 42), VXA_MASK
, PPCVEC
, { VD
, VA
, VB
, VC
} },
1877 { "vsl", VX(4, 452), VX_MASK
, PPCVEC
, { VD
, VA
, VB
} },
1878 { "vslb", VX(4, 260), VX_MASK
, PPCVEC
, { VD
, VA
, VB
} },
1879 { "vsldoi", VXA(4, 44), VXA_MASK
, PPCVEC
, { VD
, VA
, VB
, SHB
} },
1880 { "vslh", VX(4, 324), VX_MASK
, PPCVEC
, { VD
, VA
, VB
} },
1881 { "vslo", VX(4, 1036), VX_MASK
, PPCVEC
, { VD
, VA
, VB
} },
1882 { "vslw", VX(4, 388), VX_MASK
, PPCVEC
, { VD
, VA
, VB
} },
1883 { "vspltb", VX(4, 524), VX_MASK
, PPCVEC
, { VD
, VB
, UIMM
} },
1884 { "vsplth", VX(4, 588), VX_MASK
, PPCVEC
, { VD
, VB
, UIMM
} },
1885 { "vspltisb", VX(4, 780), VX_MASK
, PPCVEC
, { VD
, SIMM
} },
1886 { "vspltish", VX(4, 844), VX_MASK
, PPCVEC
, { VD
, SIMM
} },
1887 { "vspltisw", VX(4, 908), VX_MASK
, PPCVEC
, { VD
, SIMM
} },
1888 { "vspltw", VX(4, 652), VX_MASK
, PPCVEC
, { VD
, VB
, UIMM
} },
1889 { "vsr", VX(4, 708), VX_MASK
, PPCVEC
, { VD
, VA
, VB
} },
1890 { "vsrab", VX(4, 772), VX_MASK
, PPCVEC
, { VD
, VA
, VB
} },
1891 { "vsrah", VX(4, 836), VX_MASK
, PPCVEC
, { VD
, VA
, VB
} },
1892 { "vsraw", VX(4, 900), VX_MASK
, PPCVEC
, { VD
, VA
, VB
} },
1893 { "vsrb", VX(4, 516), VX_MASK
, PPCVEC
, { VD
, VA
, VB
} },
1894 { "vsrh", VX(4, 580), VX_MASK
, PPCVEC
, { VD
, VA
, VB
} },
1895 { "vsro", VX(4, 1100), VX_MASK
, PPCVEC
, { VD
, VA
, VB
} },
1896 { "vsrw", VX(4, 644), VX_MASK
, PPCVEC
, { VD
, VA
, VB
} },
1897 { "vsubcuw", VX(4, 1408), VX_MASK
, PPCVEC
, { VD
, VA
, VB
} },
1898 { "vsubfp", VX(4, 74), VX_MASK
, PPCVEC
, { VD
, VA
, VB
} },
1899 { "vsubsbs", VX(4, 1792), VX_MASK
, PPCVEC
, { VD
, VA
, VB
} },
1900 { "vsubshs", VX(4, 1856), VX_MASK
, PPCVEC
, { VD
, VA
, VB
} },
1901 { "vsubsws", VX(4, 1920), VX_MASK
, PPCVEC
, { VD
, VA
, VB
} },
1902 { "vsububm", VX(4, 1024), VX_MASK
, PPCVEC
, { VD
, VA
, VB
} },
1903 { "vsububs", VX(4, 1536), VX_MASK
, PPCVEC
, { VD
, VA
, VB
} },
1904 { "vsubuhm", VX(4, 1088), VX_MASK
, PPCVEC
, { VD
, VA
, VB
} },
1905 { "vsubuhs", VX(4, 1600), VX_MASK
, PPCVEC
, { VD
, VA
, VB
} },
1906 { "vsubuwm", VX(4, 1152), VX_MASK
, PPCVEC
, { VD
, VA
, VB
} },
1907 { "vsubuws", VX(4, 1664), VX_MASK
, PPCVEC
, { VD
, VA
, VB
} },
1908 { "vsumsws", VX(4, 1928), VX_MASK
, PPCVEC
, { VD
, VA
, VB
} },
1909 { "vsum2sws", VX(4, 1672), VX_MASK
, PPCVEC
, { VD
, VA
, VB
} },
1910 { "vsum4sbs", VX(4, 1800), VX_MASK
, PPCVEC
, { VD
, VA
, VB
} },
1911 { "vsum4shs", VX(4, 1608), VX_MASK
, PPCVEC
, { VD
, VA
, VB
} },
1912 { "vsum4ubs", VX(4, 1544), VX_MASK
, PPCVEC
, { VD
, VA
, VB
} },
1913 { "vupkhpx", VX(4, 846), VX_MASK
, PPCVEC
, { VD
, VB
} },
1914 { "vupkhsb", VX(4, 526), VX_MASK
, PPCVEC
, { VD
, VB
} },
1915 { "vupkhsh", VX(4, 590), VX_MASK
, PPCVEC
, { VD
, VB
} },
1916 { "vupklpx", VX(4, 974), VX_MASK
, PPCVEC
, { VD
, VB
} },
1917 { "vupklsb", VX(4, 654), VX_MASK
, PPCVEC
, { VD
, VB
} },
1918 { "vupklsh", VX(4, 718), VX_MASK
, PPCVEC
, { VD
, VB
} },
1919 { "vxor", VX(4, 1220), VX_MASK
, PPCVEC
, { VD
, VA
, VB
} },
1921 { "mulli", OP(7), OP_MASK
, PPCCOM
, { RT
, RA
, SI
} },
1922 { "muli", OP(7), OP_MASK
, PWRCOM
, { RT
, RA
, SI
} },
1924 { "subfic", OP(8), OP_MASK
, PPCCOM
, { RT
, RA
, SI
} },
1925 { "sfi", OP(8), OP_MASK
, PWRCOM
, { RT
, RA
, SI
} },
1927 { "dozi", OP(9), OP_MASK
, M601
, { RT
, RA
, SI
} },
1929 { "bce", B(9,0,0), B_MASK
, BOOKE64
, { BO
, BI
, BD
} },
1930 { "bcel", B(9,0,1), B_MASK
, BOOKE64
, { BO
, BI
, BD
} },
1931 { "bcea", B(9,1,0), B_MASK
, BOOKE64
, { BO
, BI
, BDA
} },
1932 { "bcela", B(9,1,1), B_MASK
, BOOKE64
, { BO
, BI
, BDA
} },
1934 { "cmplwi", OPL(10,0), OPL_MASK
, PPCCOM
, { OBF
, RA
, UI
} },
1935 { "cmpldi", OPL(10,1), OPL_MASK
, PPC64
, { OBF
, RA
, UI
} },
1936 { "cmpli", OP(10), OP_MASK
, PPCONLY
, { BF
, L
, RA
, UI
} },
1937 { "cmpli", OP(10), OP_MASK
, PWRCOM
, { BF
, RA
, UI
} },
1939 { "cmpwi", OPL(11,0), OPL_MASK
, PPCCOM
, { OBF
, RA
, SI
} },
1940 { "cmpdi", OPL(11,1), OPL_MASK
, PPC64
, { OBF
, RA
, SI
} },
1941 { "cmpi", OP(11), OP_MASK
, PPCONLY
, { BF
, L
, RA
, SI
} },
1942 { "cmpi", OP(11), OP_MASK
, PWRCOM
, { BF
, RA
, SI
} },
1944 { "addic", OP(12), OP_MASK
, PPCCOM
, { RT
, RA
, SI
} },
1945 { "ai", OP(12), OP_MASK
, PWRCOM
, { RT
, RA
, SI
} },
1946 { "subic", OP(12), OP_MASK
, PPCCOM
, { RT
, RA
, NSI
} },
1948 { "addic.", OP(13), OP_MASK
, PPCCOM
, { RT
, RA
, SI
} },
1949 { "ai.", OP(13), OP_MASK
, PWRCOM
, { RT
, RA
, SI
} },
1950 { "subic.", OP(13), OP_MASK
, PPCCOM
, { RT
, RA
, NSI
} },
1952 { "li", OP(14), DRA_MASK
, PPCCOM
, { RT
, SI
} },
1953 { "lil", OP(14), DRA_MASK
, PWRCOM
, { RT
, SI
} },
1954 { "addi", OP(14), OP_MASK
, PPCCOM
, { RT
, RA
, SI
} },
1955 { "cal", OP(14), OP_MASK
, PWRCOM
, { RT
, D
, RA
} },
1956 { "subi", OP(14), OP_MASK
, PPCCOM
, { RT
, RA
, NSI
} },
1957 { "la", OP(14), OP_MASK
, PPCCOM
, { RT
, D
, RA
} },
1959 { "lis", OP(15), DRA_MASK
, PPCCOM
, { RT
, SISIGNOPT
} },
1960 { "liu", OP(15), DRA_MASK
, PWRCOM
, { RT
, SISIGNOPT
} },
1961 { "addis", OP(15), OP_MASK
, PPCCOM
, { RT
,RA
,SISIGNOPT
} },
1962 { "cau", OP(15), OP_MASK
, PWRCOM
, { RT
,RA
,SISIGNOPT
} },
1963 { "subis", OP(15), OP_MASK
, PPCCOM
, { RT
, RA
, NSI
} },
1965 { "bdnz-", BBO(16,BODNZ
,0,0), BBOATBI_MASK
, PPCCOM
, { BDM
} },
1966 { "bdnz+", BBO(16,BODNZ
,0,0), BBOATBI_MASK
, PPCCOM
, { BDP
} },
1967 { "bdnz", BBO(16,BODNZ
,0,0), BBOATBI_MASK
, PPCCOM
, { BD
} },
1968 { "bdn", BBO(16,BODNZ
,0,0), BBOATBI_MASK
, PWRCOM
, { BD
} },
1969 { "bdnzl-", BBO(16,BODNZ
,0,1), BBOATBI_MASK
, PPCCOM
, { BDM
} },
1970 { "bdnzl+", BBO(16,BODNZ
,0,1), BBOATBI_MASK
, PPCCOM
, { BDP
} },
1971 { "bdnzl", BBO(16,BODNZ
,0,1), BBOATBI_MASK
, PPCCOM
, { BD
} },
1972 { "bdnl", BBO(16,BODNZ
,0,1), BBOATBI_MASK
, PWRCOM
, { BD
} },
1973 { "bdnza-", BBO(16,BODNZ
,1,0), BBOATBI_MASK
, PPCCOM
, { BDMA
} },
1974 { "bdnza+", BBO(16,BODNZ
,1,0), BBOATBI_MASK
, PPCCOM
, { BDPA
} },
1975 { "bdnza", BBO(16,BODNZ
,1,0), BBOATBI_MASK
, PPCCOM
, { BDA
} },
1976 { "bdna", BBO(16,BODNZ
,1,0), BBOATBI_MASK
, PWRCOM
, { BDA
} },
1977 { "bdnzla-", BBO(16,BODNZ
,1,1), BBOATBI_MASK
, PPCCOM
, { BDMA
} },
1978 { "bdnzla+", BBO(16,BODNZ
,1,1), BBOATBI_MASK
, PPCCOM
, { BDPA
} },
1979 { "bdnzla", BBO(16,BODNZ
,1,1), BBOATBI_MASK
, PPCCOM
, { BDA
} },
1980 { "bdnla", BBO(16,BODNZ
,1,1), BBOATBI_MASK
, PWRCOM
, { BDA
} },
1981 { "bdz-", BBO(16,BODZ
,0,0), BBOATBI_MASK
, PPCCOM
, { BDM
} },
1982 { "bdz+", BBO(16,BODZ
,0,0), BBOATBI_MASK
, PPCCOM
, { BDP
} },
1983 { "bdz", BBO(16,BODZ
,0,0), BBOATBI_MASK
, COM
, { BD
} },
1984 { "bdzl-", BBO(16,BODZ
,0,1), BBOATBI_MASK
, PPCCOM
, { BDM
} },
1985 { "bdzl+", BBO(16,BODZ
,0,1), BBOATBI_MASK
, PPCCOM
, { BDP
} },
1986 { "bdzl", BBO(16,BODZ
,0,1), BBOATBI_MASK
, COM
, { BD
} },
1987 { "bdza-", BBO(16,BODZ
,1,0), BBOATBI_MASK
, PPCCOM
, { BDMA
} },
1988 { "bdza+", BBO(16,BODZ
,1,0), BBOATBI_MASK
, PPCCOM
, { BDPA
} },
1989 { "bdza", BBO(16,BODZ
,1,0), BBOATBI_MASK
, COM
, { BDA
} },
1990 { "bdzla-", BBO(16,BODZ
,1,1), BBOATBI_MASK
, PPCCOM
, { BDMA
} },
1991 { "bdzla+", BBO(16,BODZ
,1,1), BBOATBI_MASK
, PPCCOM
, { BDPA
} },
1992 { "bdzla", BBO(16,BODZ
,1,1), BBOATBI_MASK
, COM
, { BDA
} },
1993 { "blt-", BBOCB(16,BOT
,CBLT
,0,0), BBOATCB_MASK
, PPCCOM
, { CR
, BDM
} },
1994 { "blt+", BBOCB(16,BOT
,CBLT
,0,0), BBOATCB_MASK
, PPCCOM
, { CR
, BDP
} },
1995 { "blt", BBOCB(16,BOT
,CBLT
,0,0), BBOATCB_MASK
, COM
, { CR
, BD
} },
1996 { "bltl-", BBOCB(16,BOT
,CBLT
,0,1), BBOATCB_MASK
, PPCCOM
, { CR
, BDM
} },
1997 { "bltl+", BBOCB(16,BOT
,CBLT
,0,1), BBOATCB_MASK
, PPCCOM
, { CR
, BDP
} },
1998 { "bltl", BBOCB(16,BOT
,CBLT
,0,1), BBOATCB_MASK
, COM
, { CR
, BD
} },
1999 { "blta-", BBOCB(16,BOT
,CBLT
,1,0), BBOATCB_MASK
, PPCCOM
, { CR
, BDMA
} },
2000 { "blta+", BBOCB(16,BOT
,CBLT
,1,0), BBOATCB_MASK
, PPCCOM
, { CR
, BDPA
} },
2001 { "blta", BBOCB(16,BOT
,CBLT
,1,0), BBOATCB_MASK
, COM
, { CR
, BDA
} },
2002 { "bltla-", BBOCB(16,BOT
,CBLT
,1,1), BBOATCB_MASK
, PPCCOM
, { CR
, BDMA
} },
2003 { "bltla+", BBOCB(16,BOT
,CBLT
,1,1), BBOATCB_MASK
, PPCCOM
, { CR
, BDPA
} },
2004 { "bltla", BBOCB(16,BOT
,CBLT
,1,1), BBOATCB_MASK
, COM
, { CR
, BDA
} },
2005 { "bgt-", BBOCB(16,BOT
,CBGT
,0,0), BBOATCB_MASK
, PPCCOM
, { CR
, BDM
} },
2006 { "bgt+", BBOCB(16,BOT
,CBGT
,0,0), BBOATCB_MASK
, PPCCOM
, { CR
, BDP
} },
2007 { "bgt", BBOCB(16,BOT
,CBGT
,0,0), BBOATCB_MASK
, COM
, { CR
, BD
} },
2008 { "bgtl-", BBOCB(16,BOT
,CBGT
,0,1), BBOATCB_MASK
, PPCCOM
, { CR
, BDM
} },
2009 { "bgtl+", BBOCB(16,BOT
,CBGT
,0,1), BBOATCB_MASK
, PPCCOM
, { CR
, BDP
} },
2010 { "bgtl", BBOCB(16,BOT
,CBGT
,0,1), BBOATCB_MASK
, COM
, { CR
, BD
} },
2011 { "bgta-", BBOCB(16,BOT
,CBGT
,1,0), BBOATCB_MASK
, PPCCOM
, { CR
, BDMA
} },
2012 { "bgta+", BBOCB(16,BOT
,CBGT
,1,0), BBOATCB_MASK
, PPCCOM
, { CR
, BDPA
} },
2013 { "bgta", BBOCB(16,BOT
,CBGT
,1,0), BBOATCB_MASK
, COM
, { CR
, BDA
} },
2014 { "bgtla-", BBOCB(16,BOT
,CBGT
,1,1), BBOATCB_MASK
, PPCCOM
, { CR
, BDMA
} },
2015 { "bgtla+", BBOCB(16,BOT
,CBGT
,1,1), BBOATCB_MASK
, PPCCOM
, { CR
, BDPA
} },
2016 { "bgtla", BBOCB(16,BOT
,CBGT
,1,1), BBOATCB_MASK
, COM
, { CR
, BDA
} },
2017 { "beq-", BBOCB(16,BOT
,CBEQ
,0,0), BBOATCB_MASK
, PPCCOM
, { CR
, BDM
} },
2018 { "beq+", BBOCB(16,BOT
,CBEQ
,0,0), BBOATCB_MASK
, PPCCOM
, { CR
, BDP
} },
2019 { "beq", BBOCB(16,BOT
,CBEQ
,0,0), BBOATCB_MASK
, COM
, { CR
, BD
} },
2020 { "beql-", BBOCB(16,BOT
,CBEQ
,0,1), BBOATCB_MASK
, PPCCOM
, { CR
, BDM
} },
2021 { "beql+", BBOCB(16,BOT
,CBEQ
,0,1), BBOATCB_MASK
, PPCCOM
, { CR
, BDP
} },
2022 { "beql", BBOCB(16,BOT
,CBEQ
,0,1), BBOATCB_MASK
, COM
, { CR
, BD
} },
2023 { "beqa-", BBOCB(16,BOT
,CBEQ
,1,0), BBOATCB_MASK
, PPCCOM
, { CR
, BDMA
} },
2024 { "beqa+", BBOCB(16,BOT
,CBEQ
,1,0), BBOATCB_MASK
, PPCCOM
, { CR
, BDPA
} },
2025 { "beqa", BBOCB(16,BOT
,CBEQ
,1,0), BBOATCB_MASK
, COM
, { CR
, BDA
} },
2026 { "beqla-", BBOCB(16,BOT
,CBEQ
,1,1), BBOATCB_MASK
, PPCCOM
, { CR
, BDMA
} },
2027 { "beqla+", BBOCB(16,BOT
,CBEQ
,1,1), BBOATCB_MASK
, PPCCOM
, { CR
, BDPA
} },
2028 { "beqla", BBOCB(16,BOT
,CBEQ
,1,1), BBOATCB_MASK
, COM
, { CR
, BDA
} },
2029 { "bso-", BBOCB(16,BOT
,CBSO
,0,0), BBOATCB_MASK
, PPCCOM
, { CR
, BDM
} },
2030 { "bso+", BBOCB(16,BOT
,CBSO
,0,0), BBOATCB_MASK
, PPCCOM
, { CR
, BDP
} },
2031 { "bso", BBOCB(16,BOT
,CBSO
,0,0), BBOATCB_MASK
, COM
, { CR
, BD
} },
2032 { "bsol-", BBOCB(16,BOT
,CBSO
,0,1), BBOATCB_MASK
, PPCCOM
, { CR
, BDM
} },
2033 { "bsol+", BBOCB(16,BOT
,CBSO
,0,1), BBOATCB_MASK
, PPCCOM
, { CR
, BDP
} },
2034 { "bsol", BBOCB(16,BOT
,CBSO
,0,1), BBOATCB_MASK
, COM
, { CR
, BD
} },
2035 { "bsoa-", BBOCB(16,BOT
,CBSO
,1,0), BBOATCB_MASK
, PPCCOM
, { CR
, BDMA
} },
2036 { "bsoa+", BBOCB(16,BOT
,CBSO
,1,0), BBOATCB_MASK
, PPCCOM
, { CR
, BDPA
} },
2037 { "bsoa", BBOCB(16,BOT
,CBSO
,1,0), BBOATCB_MASK
, COM
, { CR
, BDA
} },
2038 { "bsola-", BBOCB(16,BOT
,CBSO
,1,1), BBOATCB_MASK
, PPCCOM
, { CR
, BDMA
} },
2039 { "bsola+", BBOCB(16,BOT
,CBSO
,1,1), BBOATCB_MASK
, PPCCOM
, { CR
, BDPA
} },
2040 { "bsola", BBOCB(16,BOT
,CBSO
,1,1), BBOATCB_MASK
, COM
, { CR
, BDA
} },
2041 { "bun-", BBOCB(16,BOT
,CBSO
,0,0), BBOATCB_MASK
, PPCCOM
, { CR
, BDM
} },
2042 { "bun+", BBOCB(16,BOT
,CBSO
,0,0), BBOATCB_MASK
, PPCCOM
, { CR
, BDP
} },
2043 { "bun", BBOCB(16,BOT
,CBSO
,0,0), BBOATCB_MASK
, PPCCOM
, { CR
, BD
} },
2044 { "bunl-", BBOCB(16,BOT
,CBSO
,0,1), BBOATCB_MASK
, PPCCOM
, { CR
, BDM
} },
2045 { "bunl+", BBOCB(16,BOT
,CBSO
,0,1), BBOATCB_MASK
, PPCCOM
, { CR
, BDP
} },
2046 { "bunl", BBOCB(16,BOT
,CBSO
,0,1), BBOATCB_MASK
, PPCCOM
, { CR
, BD
} },
2047 { "buna-", BBOCB(16,BOT
,CBSO
,1,0), BBOATCB_MASK
, PPCCOM
, { CR
, BDMA
} },
2048 { "buna+", BBOCB(16,BOT
,CBSO
,1,0), BBOATCB_MASK
, PPCCOM
, { CR
, BDPA
} },
2049 { "buna", BBOCB(16,BOT
,CBSO
,1,0), BBOATCB_MASK
, PPCCOM
, { CR
, BDA
} },
2050 { "bunla-", BBOCB(16,BOT
,CBSO
,1,1), BBOATCB_MASK
, PPCCOM
, { CR
, BDMA
} },
2051 { "bunla+", BBOCB(16,BOT
,CBSO
,1,1), BBOATCB_MASK
, PPCCOM
, { CR
, BDPA
} },
2052 { "bunla", BBOCB(16,BOT
,CBSO
,1,1), BBOATCB_MASK
, PPCCOM
, { CR
, BDA
} },
2053 { "bge-", BBOCB(16,BOF
,CBLT
,0,0), BBOATCB_MASK
, PPCCOM
, { CR
, BDM
} },
2054 { "bge+", BBOCB(16,BOF
,CBLT
,0,0), BBOATCB_MASK
, PPCCOM
, { CR
, BDP
} },
2055 { "bge", BBOCB(16,BOF
,CBLT
,0,0), BBOATCB_MASK
, COM
, { CR
, BD
} },
2056 { "bgel-", BBOCB(16,BOF
,CBLT
,0,1), BBOATCB_MASK
, PPCCOM
, { CR
, BDM
} },
2057 { "bgel+", BBOCB(16,BOF
,CBLT
,0,1), BBOATCB_MASK
, PPCCOM
, { CR
, BDP
} },
2058 { "bgel", BBOCB(16,BOF
,CBLT
,0,1), BBOATCB_MASK
, COM
, { CR
, BD
} },
2059 { "bgea-", BBOCB(16,BOF
,CBLT
,1,0), BBOATCB_MASK
, PPCCOM
, { CR
, BDMA
} },
2060 { "bgea+", BBOCB(16,BOF
,CBLT
,1,0), BBOATCB_MASK
, PPCCOM
, { CR
, BDPA
} },
2061 { "bgea", BBOCB(16,BOF
,CBLT
,1,0), BBOATCB_MASK
, COM
, { CR
, BDA
} },
2062 { "bgela-", BBOCB(16,BOF
,CBLT
,1,1), BBOATCB_MASK
, PPCCOM
, { CR
, BDMA
} },
2063 { "bgela+", BBOCB(16,BOF
,CBLT
,1,1), BBOATCB_MASK
, PPCCOM
, { CR
, BDPA
} },
2064 { "bgela", BBOCB(16,BOF
,CBLT
,1,1), BBOATCB_MASK
, COM
, { CR
, BDA
} },
2065 { "bnl-", BBOCB(16,BOF
,CBLT
,0,0), BBOATCB_MASK
, PPCCOM
, { CR
, BDM
} },
2066 { "bnl+", BBOCB(16,BOF
,CBLT
,0,0), BBOATCB_MASK
, PPCCOM
, { CR
, BDP
} },
2067 { "bnl", BBOCB(16,BOF
,CBLT
,0,0), BBOATCB_MASK
, COM
, { CR
, BD
} },
2068 { "bnll-", BBOCB(16,BOF
,CBLT
,0,1), BBOATCB_MASK
, PPCCOM
, { CR
, BDM
} },
2069 { "bnll+", BBOCB(16,BOF
,CBLT
,0,1), BBOATCB_MASK
, PPCCOM
, { CR
, BDP
} },
2070 { "bnll", BBOCB(16,BOF
,CBLT
,0,1), BBOATCB_MASK
, COM
, { CR
, BD
} },
2071 { "bnla-", BBOCB(16,BOF
,CBLT
,1,0), BBOATCB_MASK
, PPCCOM
, { CR
, BDMA
} },
2072 { "bnla+", BBOCB(16,BOF
,CBLT
,1,0), BBOATCB_MASK
, PPCCOM
, { CR
, BDPA
} },
2073 { "bnla", BBOCB(16,BOF
,CBLT
,1,0), BBOATCB_MASK
, COM
, { CR
, BDA
} },
2074 { "bnlla-", BBOCB(16,BOF
,CBLT
,1,1), BBOATCB_MASK
, PPCCOM
, { CR
, BDMA
} },
2075 { "bnlla+", BBOCB(16,BOF
,CBLT
,1,1), BBOATCB_MASK
, PPCCOM
, { CR
, BDPA
} },
2076 { "bnlla", BBOCB(16,BOF
,CBLT
,1,1), BBOATCB_MASK
, COM
, { CR
, BDA
} },
2077 { "ble-", BBOCB(16,BOF
,CBGT
,0,0), BBOATCB_MASK
, PPCCOM
, { CR
, BDM
} },
2078 { "ble+", BBOCB(16,BOF
,CBGT
,0,0), BBOATCB_MASK
, PPCCOM
, { CR
, BDP
} },
2079 { "ble", BBOCB(16,BOF
,CBGT
,0,0), BBOATCB_MASK
, COM
, { CR
, BD
} },
2080 { "blel-", BBOCB(16,BOF
,CBGT
,0,1), BBOATCB_MASK
, PPCCOM
, { CR
, BDM
} },
2081 { "blel+", BBOCB(16,BOF
,CBGT
,0,1), BBOATCB_MASK
, PPCCOM
, { CR
, BDP
} },
2082 { "blel", BBOCB(16,BOF
,CBGT
,0,1), BBOATCB_MASK
, COM
, { CR
, BD
} },
2083 { "blea-", BBOCB(16,BOF
,CBGT
,1,0), BBOATCB_MASK
, PPCCOM
, { CR
, BDMA
} },
2084 { "blea+", BBOCB(16,BOF
,CBGT
,1,0), BBOATCB_MASK
, PPCCOM
, { CR
, BDPA
} },
2085 { "blea", BBOCB(16,BOF
,CBGT
,1,0), BBOATCB_MASK
, COM
, { CR
, BDA
} },
2086 { "blela-", BBOCB(16,BOF
,CBGT
,1,1), BBOATCB_MASK
, PPCCOM
, { CR
, BDMA
} },
2087 { "blela+", BBOCB(16,BOF
,CBGT
,1,1), BBOATCB_MASK
, PPCCOM
, { CR
, BDPA
} },
2088 { "blela", BBOCB(16,BOF
,CBGT
,1,1), BBOATCB_MASK
, COM
, { CR
, BDA
} },
2089 { "bng-", BBOCB(16,BOF
,CBGT
,0,0), BBOATCB_MASK
, PPCCOM
, { CR
, BDM
} },
2090 { "bng+", BBOCB(16,BOF
,CBGT
,0,0), BBOATCB_MASK
, PPCCOM
, { CR
, BDP
} },
2091 { "bng", BBOCB(16,BOF
,CBGT
,0,0), BBOATCB_MASK
, COM
, { CR
, BD
} },
2092 { "bngl-", BBOCB(16,BOF
,CBGT
,0,1), BBOATCB_MASK
, PPCCOM
, { CR
, BDM
} },
2093 { "bngl+", BBOCB(16,BOF
,CBGT
,0,1), BBOATCB_MASK
, PPCCOM
, { CR
, BDP
} },
2094 { "bngl", BBOCB(16,BOF
,CBGT
,0,1), BBOATCB_MASK
, COM
, { CR
, BD
} },
2095 { "bnga-", BBOCB(16,BOF
,CBGT
,1,0), BBOATCB_MASK
, PPCCOM
, { CR
, BDMA
} },
2096 { "bnga+", BBOCB(16,BOF
,CBGT
,1,0), BBOATCB_MASK
, PPCCOM
, { CR
, BDPA
} },
2097 { "bnga", BBOCB(16,BOF
,CBGT
,1,0), BBOATCB_MASK
, COM
, { CR
, BDA
} },
2098 { "bngla-", BBOCB(16,BOF
,CBGT
,1,1), BBOATCB_MASK
, PPCCOM
, { CR
, BDMA
} },
2099 { "bngla+", BBOCB(16,BOF
,CBGT
,1,1), BBOATCB_MASK
, PPCCOM
, { CR
, BDPA
} },
2100 { "bngla", BBOCB(16,BOF
,CBGT
,1,1), BBOATCB_MASK
, COM
, { CR
, BDA
} },
2101 { "bne-", BBOCB(16,BOF
,CBEQ
,0,0), BBOATCB_MASK
, PPCCOM
, { CR
, BDM
} },
2102 { "bne+", BBOCB(16,BOF
,CBEQ
,0,0), BBOATCB_MASK
, PPCCOM
, { CR
, BDP
} },
2103 { "bne", BBOCB(16,BOF
,CBEQ
,0,0), BBOATCB_MASK
, COM
, { CR
, BD
} },
2104 { "bnel-", BBOCB(16,BOF
,CBEQ
,0,1), BBOATCB_MASK
, PPCCOM
, { CR
, BDM
} },
2105 { "bnel+", BBOCB(16,BOF
,CBEQ
,0,1), BBOATCB_MASK
, PPCCOM
, { CR
, BDP
} },
2106 { "bnel", BBOCB(16,BOF
,CBEQ
,0,1), BBOATCB_MASK
, COM
, { CR
, BD
} },
2107 { "bnea-", BBOCB(16,BOF
,CBEQ
,1,0), BBOATCB_MASK
, PPCCOM
, { CR
, BDMA
} },
2108 { "bnea+", BBOCB(16,BOF
,CBEQ
,1,0), BBOATCB_MASK
, PPCCOM
, { CR
, BDPA
} },
2109 { "bnea", BBOCB(16,BOF
,CBEQ
,1,0), BBOATCB_MASK
, COM
, { CR
, BDA
} },
2110 { "bnela-", BBOCB(16,BOF
,CBEQ
,1,1), BBOATCB_MASK
, PPCCOM
, { CR
, BDMA
} },
2111 { "bnela+", BBOCB(16,BOF
,CBEQ
,1,1), BBOATCB_MASK
, PPCCOM
, { CR
, BDPA
} },
2112 { "bnela", BBOCB(16,BOF
,CBEQ
,1,1), BBOATCB_MASK
, COM
, { CR
, BDA
} },
2113 { "bns-", BBOCB(16,BOF
,CBSO
,0,0), BBOATCB_MASK
, PPCCOM
, { CR
, BDM
} },
2114 { "bns+", BBOCB(16,BOF
,CBSO
,0,0), BBOATCB_MASK
, PPCCOM
, { CR
, BDP
} },
2115 { "bns", BBOCB(16,BOF
,CBSO
,0,0), BBOATCB_MASK
, COM
, { CR
, BD
} },
2116 { "bnsl-", BBOCB(16,BOF
,CBSO
,0,1), BBOATCB_MASK
, PPCCOM
, { CR
, BDM
} },
2117 { "bnsl+", BBOCB(16,BOF
,CBSO
,0,1), BBOATCB_MASK
, PPCCOM
, { CR
, BDP
} },
2118 { "bnsl", BBOCB(16,BOF
,CBSO
,0,1), BBOATCB_MASK
, COM
, { CR
, BD
} },
2119 { "bnsa-", BBOCB(16,BOF
,CBSO
,1,0), BBOATCB_MASK
, PPCCOM
, { CR
, BDMA
} },
2120 { "bnsa+", BBOCB(16,BOF
,CBSO
,1,0), BBOATCB_MASK
, PPCCOM
, { CR
, BDPA
} },
2121 { "bnsa", BBOCB(16,BOF
,CBSO
,1,0), BBOATCB_MASK
, COM
, { CR
, BDA
} },
2122 { "bnsla-", BBOCB(16,BOF
,CBSO
,1,1), BBOATCB_MASK
, PPCCOM
, { CR
, BDMA
} },
2123 { "bnsla+", BBOCB(16,BOF
,CBSO
,1,1), BBOATCB_MASK
, PPCCOM
, { CR
, BDPA
} },
2124 { "bnsla", BBOCB(16,BOF
,CBSO
,1,1), BBOATCB_MASK
, COM
, { CR
, BDA
} },
2125 { "bnu-", BBOCB(16,BOF
,CBSO
,0,0), BBOATCB_MASK
, PPCCOM
, { CR
, BDM
} },
2126 { "bnu+", BBOCB(16,BOF
,CBSO
,0,0), BBOATCB_MASK
, PPCCOM
, { CR
, BDP
} },
2127 { "bnu", BBOCB(16,BOF
,CBSO
,0,0), BBOATCB_MASK
, PPCCOM
, { CR
, BD
} },
2128 { "bnul-", BBOCB(16,BOF
,CBSO
,0,1), BBOATCB_MASK
, PPCCOM
, { CR
, BDM
} },
2129 { "bnul+", BBOCB(16,BOF
,CBSO
,0,1), BBOATCB_MASK
, PPCCOM
, { CR
, BDP
} },
2130 { "bnul", BBOCB(16,BOF
,CBSO
,0,1), BBOATCB_MASK
, PPCCOM
, { CR
, BD
} },
2131 { "bnua-", BBOCB(16,BOF
,CBSO
,1,0), BBOATCB_MASK
, PPCCOM
, { CR
, BDMA
} },
2132 { "bnua+", BBOCB(16,BOF
,CBSO
,1,0), BBOATCB_MASK
, PPCCOM
, { CR
, BDPA
} },
2133 { "bnua", BBOCB(16,BOF
,CBSO
,1,0), BBOATCB_MASK
, PPCCOM
, { CR
, BDA
} },
2134 { "bnula-", BBOCB(16,BOF
,CBSO
,1,1), BBOATCB_MASK
, PPCCOM
, { CR
, BDMA
} },
2135 { "bnula+", BBOCB(16,BOF
,CBSO
,1,1), BBOATCB_MASK
, PPCCOM
, { CR
, BDPA
} },
2136 { "bnula", BBOCB(16,BOF
,CBSO
,1,1), BBOATCB_MASK
, PPCCOM
, { CR
, BDA
} },
2137 { "bdnzt-", BBO(16,BODNZT
,0,0), BBOY_MASK
, NOPOWER4
, { BI
, BDM
} },
2138 { "bdnzt+", BBO(16,BODNZT
,0,0), BBOY_MASK
, NOPOWER4
, { BI
, BDP
} },
2139 { "bdnzt", BBO(16,BODNZT
,0,0), BBOY_MASK
, PPCCOM
, { BI
, BD
} },
2140 { "bdnztl-", BBO(16,BODNZT
,0,1), BBOY_MASK
, NOPOWER4
, { BI
, BDM
} },
2141 { "bdnztl+", BBO(16,BODNZT
,0,1), BBOY_MASK
, NOPOWER4
, { BI
, BDP
} },
2142 { "bdnztl", BBO(16,BODNZT
,0,1), BBOY_MASK
, PPCCOM
, { BI
, BD
} },
2143 { "bdnzta-", BBO(16,BODNZT
,1,0), BBOY_MASK
, NOPOWER4
, { BI
, BDMA
} },
2144 { "bdnzta+", BBO(16,BODNZT
,1,0), BBOY_MASK
, NOPOWER4
, { BI
, BDPA
} },
2145 { "bdnzta", BBO(16,BODNZT
,1,0), BBOY_MASK
, PPCCOM
, { BI
, BDA
} },
2146 { "bdnztla-",BBO(16,BODNZT
,1,1), BBOY_MASK
, NOPOWER4
, { BI
, BDMA
} },
2147 { "bdnztla+",BBO(16,BODNZT
,1,1), BBOY_MASK
, NOPOWER4
, { BI
, BDPA
} },
2148 { "bdnztla", BBO(16,BODNZT
,1,1), BBOY_MASK
, PPCCOM
, { BI
, BDA
} },
2149 { "bdnzf-", BBO(16,BODNZF
,0,0), BBOY_MASK
, NOPOWER4
, { BI
, BDM
} },
2150 { "bdnzf+", BBO(16,BODNZF
,0,0), BBOY_MASK
, NOPOWER4
, { BI
, BDP
} },
2151 { "bdnzf", BBO(16,BODNZF
,0,0), BBOY_MASK
, PPCCOM
, { BI
, BD
} },
2152 { "bdnzfl-", BBO(16,BODNZF
,0,1), BBOY_MASK
, NOPOWER4
, { BI
, BDM
} },
2153 { "bdnzfl+", BBO(16,BODNZF
,0,1), BBOY_MASK
, NOPOWER4
, { BI
, BDP
} },
2154 { "bdnzfl", BBO(16,BODNZF
,0,1), BBOY_MASK
, PPCCOM
, { BI
, BD
} },
2155 { "bdnzfa-", BBO(16,BODNZF
,1,0), BBOY_MASK
, NOPOWER4
, { BI
, BDMA
} },
2156 { "bdnzfa+", BBO(16,BODNZF
,1,0), BBOY_MASK
, NOPOWER4
, { BI
, BDPA
} },
2157 { "bdnzfa", BBO(16,BODNZF
,1,0), BBOY_MASK
, PPCCOM
, { BI
, BDA
} },
2158 { "bdnzfla-",BBO(16,BODNZF
,1,1), BBOY_MASK
, NOPOWER4
, { BI
, BDMA
} },
2159 { "bdnzfla+",BBO(16,BODNZF
,1,1), BBOY_MASK
, NOPOWER4
, { BI
, BDPA
} },
2160 { "bdnzfla", BBO(16,BODNZF
,1,1), BBOY_MASK
, PPCCOM
, { BI
, BDA
} },
2161 { "bt-", BBO(16,BOT
,0,0), BBOAT_MASK
, PPCCOM
, { BI
, BDM
} },
2162 { "bt+", BBO(16,BOT
,0,0), BBOAT_MASK
, PPCCOM
, { BI
, BDP
} },
2163 { "bt", BBO(16,BOT
,0,0), BBOAT_MASK
, PPCCOM
, { BI
, BD
} },
2164 { "bbt", BBO(16,BOT
,0,0), BBOAT_MASK
, PWRCOM
, { BI
, BD
} },
2165 { "btl-", BBO(16,BOT
,0,1), BBOAT_MASK
, PPCCOM
, { BI
, BDM
} },
2166 { "btl+", BBO(16,BOT
,0,1), BBOAT_MASK
, PPCCOM
, { BI
, BDP
} },
2167 { "btl", BBO(16,BOT
,0,1), BBOAT_MASK
, PPCCOM
, { BI
, BD
} },
2168 { "bbtl", BBO(16,BOT
,0,1), BBOAT_MASK
, PWRCOM
, { BI
, BD
} },
2169 { "bta-", BBO(16,BOT
,1,0), BBOAT_MASK
, PPCCOM
, { BI
, BDMA
} },
2170 { "bta+", BBO(16,BOT
,1,0), BBOAT_MASK
, PPCCOM
, { BI
, BDPA
} },
2171 { "bta", BBO(16,BOT
,1,0), BBOAT_MASK
, PPCCOM
, { BI
, BDA
} },
2172 { "bbta", BBO(16,BOT
,1,0), BBOAT_MASK
, PWRCOM
, { BI
, BDA
} },
2173 { "btla-", BBO(16,BOT
,1,1), BBOAT_MASK
, PPCCOM
, { BI
, BDMA
} },
2174 { "btla+", BBO(16,BOT
,1,1), BBOAT_MASK
, PPCCOM
, { BI
, BDPA
} },
2175 { "btla", BBO(16,BOT
,1,1), BBOAT_MASK
, PPCCOM
, { BI
, BDA
} },
2176 { "bbtla", BBO(16,BOT
,1,1), BBOAT_MASK
, PWRCOM
, { BI
, BDA
} },
2177 { "bf-", BBO(16,BOF
,0,0), BBOAT_MASK
, PPCCOM
, { BI
, BDM
} },
2178 { "bf+", BBO(16,BOF
,0,0), BBOAT_MASK
, PPCCOM
, { BI
, BDP
} },
2179 { "bf", BBO(16,BOF
,0,0), BBOAT_MASK
, PPCCOM
, { BI
, BD
} },
2180 { "bbf", BBO(16,BOF
,0,0), BBOAT_MASK
, PWRCOM
, { BI
, BD
} },
2181 { "bfl-", BBO(16,BOF
,0,1), BBOAT_MASK
, PPCCOM
, { BI
, BDM
} },
2182 { "bfl+", BBO(16,BOF
,0,1), BBOAT_MASK
, PPCCOM
, { BI
, BDP
} },
2183 { "bfl", BBO(16,BOF
,0,1), BBOAT_MASK
, PPCCOM
, { BI
, BD
} },
2184 { "bbfl", BBO(16,BOF
,0,1), BBOAT_MASK
, PWRCOM
, { BI
, BD
} },
2185 { "bfa-", BBO(16,BOF
,1,0), BBOAT_MASK
, PPCCOM
, { BI
, BDMA
} },
2186 { "bfa+", BBO(16,BOF
,1,0), BBOAT_MASK
, PPCCOM
, { BI
, BDPA
} },
2187 { "bfa", BBO(16,BOF
,1,0), BBOAT_MASK
, PPCCOM
, { BI
, BDA
} },
2188 { "bbfa", BBO(16,BOF
,1,0), BBOAT_MASK
, PWRCOM
, { BI
, BDA
} },
2189 { "bfla-", BBO(16,BOF
,1,1), BBOAT_MASK
, PPCCOM
, { BI
, BDMA
} },
2190 { "bfla+", BBO(16,BOF
,1,1), BBOAT_MASK
, PPCCOM
, { BI
, BDPA
} },
2191 { "bfla", BBO(16,BOF
,1,1), BBOAT_MASK
, PPCCOM
, { BI
, BDA
} },
2192 { "bbfla", BBO(16,BOF
,1,1), BBOAT_MASK
, PWRCOM
, { BI
, BDA
} },
2193 { "bdzt-", BBO(16,BODZT
,0,0), BBOY_MASK
, NOPOWER4
, { BI
, BDM
} },
2194 { "bdzt+", BBO(16,BODZT
,0,0), BBOY_MASK
, NOPOWER4
, { BI
, BDP
} },
2195 { "bdzt", BBO(16,BODZT
,0,0), BBOY_MASK
, PPCCOM
, { BI
, BD
} },
2196 { "bdztl-", BBO(16,BODZT
,0,1), BBOY_MASK
, NOPOWER4
, { BI
, BDM
} },
2197 { "bdztl+", BBO(16,BODZT
,0,1), BBOY_MASK
, NOPOWER4
, { BI
, BDP
} },
2198 { "bdztl", BBO(16,BODZT
,0,1), BBOY_MASK
, PPCCOM
, { BI
, BD
} },
2199 { "bdzta-", BBO(16,BODZT
,1,0), BBOY_MASK
, NOPOWER4
, { BI
, BDMA
} },
2200 { "bdzta+", BBO(16,BODZT
,1,0), BBOY_MASK
, NOPOWER4
, { BI
, BDPA
} },
2201 { "bdzta", BBO(16,BODZT
,1,0), BBOY_MASK
, PPCCOM
, { BI
, BDA
} },
2202 { "bdztla-", BBO(16,BODZT
,1,1), BBOY_MASK
, NOPOWER4
, { BI
, BDMA
} },
2203 { "bdztla+", BBO(16,BODZT
,1,1), BBOY_MASK
, NOPOWER4
, { BI
, BDPA
} },
2204 { "bdztla", BBO(16,BODZT
,1,1), BBOY_MASK
, PPCCOM
, { BI
, BDA
} },
2205 { "bdzf-", BBO(16,BODZF
,0,0), BBOY_MASK
, NOPOWER4
, { BI
, BDM
} },
2206 { "bdzf+", BBO(16,BODZF
,0,0), BBOY_MASK
, NOPOWER4
, { BI
, BDP
} },
2207 { "bdzf", BBO(16,BODZF
,0,0), BBOY_MASK
, PPCCOM
, { BI
, BD
} },
2208 { "bdzfl-", BBO(16,BODZF
,0,1), BBOY_MASK
, NOPOWER4
, { BI
, BDM
} },
2209 { "bdzfl+", BBO(16,BODZF
,0,1), BBOY_MASK
, NOPOWER4
, { BI
, BDP
} },
2210 { "bdzfl", BBO(16,BODZF
,0,1), BBOY_MASK
, PPCCOM
, { BI
, BD
} },
2211 { "bdzfa-", BBO(16,BODZF
,1,0), BBOY_MASK
, NOPOWER4
, { BI
, BDMA
} },
2212 { "bdzfa+", BBO(16,BODZF
,1,0), BBOY_MASK
, NOPOWER4
, { BI
, BDPA
} },
2213 { "bdzfa", BBO(16,BODZF
,1,0), BBOY_MASK
, PPCCOM
, { BI
, BDA
} },
2214 { "bdzfla-", BBO(16,BODZF
,1,1), BBOY_MASK
, NOPOWER4
, { BI
, BDMA
} },
2215 { "bdzfla+", BBO(16,BODZF
,1,1), BBOY_MASK
, NOPOWER4
, { BI
, BDPA
} },
2216 { "bdzfla", BBO(16,BODZF
,1,1), BBOY_MASK
, PPCCOM
, { BI
, BDA
} },
2217 { "bc-", B(16,0,0), B_MASK
, PPCCOM
, { BOE
, BI
, BDM
} },
2218 { "bc+", B(16,0,0), B_MASK
, PPCCOM
, { BOE
, BI
, BDP
} },
2219 { "bc", B(16,0,0), B_MASK
, COM
, { BO
, BI
, BD
} },
2220 { "bcl-", B(16,0,1), B_MASK
, PPCCOM
, { BOE
, BI
, BDM
} },
2221 { "bcl+", B(16,0,1), B_MASK
, PPCCOM
, { BOE
, BI
, BDP
} },
2222 { "bcl", B(16,0,1), B_MASK
, COM
, { BO
, BI
, BD
} },
2223 { "bca-", B(16,1,0), B_MASK
, PPCCOM
, { BOE
, BI
, BDMA
} },
2224 { "bca+", B(16,1,0), B_MASK
, PPCCOM
, { BOE
, BI
, BDPA
} },
2225 { "bca", B(16,1,0), B_MASK
, COM
, { BO
, BI
, BDA
} },
2226 { "bcla-", B(16,1,1), B_MASK
, PPCCOM
, { BOE
, BI
, BDMA
} },
2227 { "bcla+", B(16,1,1), B_MASK
, PPCCOM
, { BOE
, BI
, BDPA
} },
2228 { "bcla", B(16,1,1), B_MASK
, COM
, { BO
, BI
, BDA
} },
2230 { "sc", SC(17,1,0), 0xffffffff, PPC
, { 0 } },
2231 { "svc", SC(17,0,0), SC_MASK
, POWER
, { LEV
, FL1
, FL2
} },
2232 { "svcl", SC(17,0,1), SC_MASK
, POWER
, { LEV
, FL1
, FL2
} },
2233 { "svca", SC(17,1,0), SC_MASK
, PWRCOM
, { SV
} },
2234 { "svcla", SC(17,1,1), SC_MASK
, POWER
, { SV
} },
2236 { "b", B(18,0,0), B_MASK
, COM
, { LI
} },
2237 { "bl", B(18,0,1), B_MASK
, COM
, { LI
} },
2238 { "ba", B(18,1,0), B_MASK
, COM
, { LIA
} },
2239 { "bla", B(18,1,1), B_MASK
, COM
, { LIA
} },
2241 { "mcrf", XL(19,0), XLBB_MASK
|(3<<21)|(3<<16), COM
, { BF
, BFA
} },
2243 { "blr", XLO(19,BOU
,16,0), XLBOBIBB_MASK
, PPCCOM
, { 0 } },
2244 { "br", XLO(19,BOU
,16,0), XLBOBIBB_MASK
, PWRCOM
, { 0 } },
2245 { "blrl", XLO(19,BOU
,16,1), XLBOBIBB_MASK
, PPCCOM
, { 0 } },
2246 { "brl", XLO(19,BOU
,16,1), XLBOBIBB_MASK
, PWRCOM
, { 0 } },
2247 { "bdnzlr", XLO(19,BODNZ
,16,0), XLBOBIBB_MASK
, PPCCOM
, { 0 } },
2248 { "bdnzlr-", XLO(19,BODNZ
,16,0), XLBOBIBB_MASK
, NOPOWER4
, { 0 } },
2249 { "bdnzlr+", XLO(19,BODNZP
,16,0), XLBOBIBB_MASK
, NOPOWER4
, { 0 } },
2250 { "bdnzlr-", XLO(19,BODNZM4
,16,0), XLBOBIBB_MASK
, POWER4
, { 0 } },
2251 { "bdnzlr+", XLO(19,BODNZP4
,16,0), XLBOBIBB_MASK
, POWER4
, { 0 } },
2252 { "bdnzlrl", XLO(19,BODNZ
,16,1), XLBOBIBB_MASK
, PPCCOM
, { 0 } },
2253 { "bdnzlrl-",XLO(19,BODNZ
,16,1), XLBOBIBB_MASK
, NOPOWER4
, { 0 } },
2254 { "bdnzlrl+",XLO(19,BODNZP
,16,1), XLBOBIBB_MASK
, NOPOWER4
, { 0 } },
2255 { "bdnzlrl-",XLO(19,BODNZM4
,16,1), XLBOBIBB_MASK
, POWER4
, { 0 } },
2256 { "bdnzlrl+",XLO(19,BODNZP4
,16,1), XLBOBIBB_MASK
, POWER4
, { 0 } },
2257 { "bdzlr", XLO(19,BODZ
,16,0), XLBOBIBB_MASK
, PPCCOM
, { 0 } },
2258 { "bdzlr-", XLO(19,BODZ
,16,0), XLBOBIBB_MASK
, NOPOWER4
, { 0 } },
2259 { "bdzlr+", XLO(19,BODZP
,16,0), XLBOBIBB_MASK
, NOPOWER4
, { 0 } },
2260 { "bdzlr-", XLO(19,BODZM4
,16,0), XLBOBIBB_MASK
, POWER4
, { 0 } },
2261 { "bdzlr+", XLO(19,BODZP4
,16,0), XLBOBIBB_MASK
, POWER4
, { 0 } },
2262 { "bdzlrl", XLO(19,BODZ
,16,1), XLBOBIBB_MASK
, PPCCOM
, { 0 } },
2263 { "bdzlrl-", XLO(19,BODZ
,16,1), XLBOBIBB_MASK
, NOPOWER4
, { 0 } },
2264 { "bdzlrl+", XLO(19,BODZP
,16,1), XLBOBIBB_MASK
, NOPOWER4
, { 0 } },
2265 { "bdzlrl-", XLO(19,BODZM4
,16,1), XLBOBIBB_MASK
, POWER4
, { 0 } },
2266 { "bdzlrl+", XLO(19,BODZP4
,16,1), XLBOBIBB_MASK
, POWER4
, { 0 } },
2267 { "bltlr", XLOCB(19,BOT
,CBLT
,16,0), XLBOCBBB_MASK
, PPCCOM
, { CR
} },
2268 { "bltlr-", XLOCB(19,BOT
,CBLT
,16,0), XLBOCBBB_MASK
, NOPOWER4
, { CR
} },
2269 { "bltlr+", XLOCB(19,BOTP
,CBLT
,16,0), XLBOCBBB_MASK
, NOPOWER4
, { CR
} },
2270 { "bltlr-", XLOCB(19,BOTM4
,CBLT
,16,0), XLBOCBBB_MASK
, POWER4
, { CR
} },
2271 { "bltlr+", XLOCB(19,BOTP4
,CBLT
,16,0), XLBOCBBB_MASK
, POWER4
, { CR
} },
2272 { "bltr", XLOCB(19,BOT
,CBLT
,16,0), XLBOCBBB_MASK
, PWRCOM
, { CR
} },
2273 { "bltlrl", XLOCB(19,BOT
,CBLT
,16,1), XLBOCBBB_MASK
, PPCCOM
, { CR
} },
2274 { "bltlrl-", XLOCB(19,BOT
,CBLT
,16,1), XLBOCBBB_MASK
, NOPOWER4
, { CR
} },
2275 { "bltlrl+", XLOCB(19,BOTP
,CBLT
,16,1), XLBOCBBB_MASK
, NOPOWER4
, { CR
} },
2276 { "bltlrl-", XLOCB(19,BOTM4
,CBLT
,16,1), XLBOCBBB_MASK
, POWER4
, { CR
} },
2277 { "bltlrl+", XLOCB(19,BOTP4
,CBLT
,16,1), XLBOCBBB_MASK
, POWER4
, { CR
} },
2278 { "bltrl", XLOCB(19,BOT
,CBLT
,16,1), XLBOCBBB_MASK
, PWRCOM
, { CR
} },
2279 { "bgtlr", XLOCB(19,BOT
,CBGT
,16,0), XLBOCBBB_MASK
, PPCCOM
, { CR
} },
2280 { "bgtlr-", XLOCB(19,BOT
,CBGT
,16,0), XLBOCBBB_MASK
, NOPOWER4
, { CR
} },
2281 { "bgtlr+", XLOCB(19,BOTP
,CBGT
,16,0), XLBOCBBB_MASK
, NOPOWER4
, { CR
} },
2282 { "bgtlr-", XLOCB(19,BOTM4
,CBGT
,16,0), XLBOCBBB_MASK
, POWER4
, { CR
} },
2283 { "bgtlr+", XLOCB(19,BOTP4
,CBGT
,16,0), XLBOCBBB_MASK
, POWER4
, { CR
} },
2284 { "bgtr", XLOCB(19,BOT
,CBGT
,16,0), XLBOCBBB_MASK
, PWRCOM
, { CR
} },
2285 { "bgtlrl", XLOCB(19,BOT
,CBGT
,16,1), XLBOCBBB_MASK
, PPCCOM
, { CR
} },
2286 { "bgtlrl-", XLOCB(19,BOT
,CBGT
,16,1), XLBOCBBB_MASK
, NOPOWER4
, { CR
} },
2287 { "bgtlrl+", XLOCB(19,BOTP
,CBGT
,16,1), XLBOCBBB_MASK
, NOPOWER4
, { CR
} },
2288 { "bgtlrl-", XLOCB(19,BOTM4
,CBGT
,16,1), XLBOCBBB_MASK
, POWER4
, { CR
} },
2289 { "bgtlrl+", XLOCB(19,BOTP4
,CBGT
,16,1), XLBOCBBB_MASK
, POWER4
, { CR
} },
2290 { "bgtrl", XLOCB(19,BOT
,CBGT
,16,1), XLBOCBBB_MASK
, PWRCOM
, { CR
} },
2291 { "beqlr", XLOCB(19,BOT
,CBEQ
,16,0), XLBOCBBB_MASK
, PPCCOM
, { CR
} },
2292 { "beqlr-", XLOCB(19,BOT
,CBEQ
,16,0), XLBOCBBB_MASK
, NOPOWER4
, { CR
} },
2293 { "beqlr+", XLOCB(19,BOTP
,CBEQ
,16,0), XLBOCBBB_MASK
, NOPOWER4
, { CR
} },
2294 { "beqlr-", XLOCB(19,BOTM4
,CBEQ
,16,0), XLBOCBBB_MASK
, POWER4
, { CR
} },
2295 { "beqlr+", XLOCB(19,BOTP4
,CBEQ
,16,0), XLBOCBBB_MASK
, POWER4
, { CR
} },
2296 { "beqr", XLOCB(19,BOT
,CBEQ
,16,0), XLBOCBBB_MASK
, PWRCOM
, { CR
} },
2297 { "beqlrl", XLOCB(19,BOT
,CBEQ
,16,1), XLBOCBBB_MASK
, PPCCOM
, { CR
} },
2298 { "beqlrl-", XLOCB(19,BOT
,CBEQ
,16,1), XLBOCBBB_MASK
, NOPOWER4
, { CR
} },
2299 { "beqlrl+", XLOCB(19,BOTP
,CBEQ
,16,1), XLBOCBBB_MASK
, NOPOWER4
, { CR
} },
2300 { "beqlrl-", XLOCB(19,BOTM4
,CBEQ
,16,1), XLBOCBBB_MASK
, POWER4
, { CR
} },
2301 { "beqlrl+", XLOCB(19,BOTP4
,CBEQ
,16,1), XLBOCBBB_MASK
, POWER4
, { CR
} },
2302 { "beqrl", XLOCB(19,BOT
,CBEQ
,16,1), XLBOCBBB_MASK
, PWRCOM
, { CR
} },
2303 { "bsolr", XLOCB(19,BOT
,CBSO
,16,0), XLBOCBBB_MASK
, PPCCOM
, { CR
} },
2304 { "bsolr-", XLOCB(19,BOT
,CBSO
,16,0), XLBOCBBB_MASK
, NOPOWER4
, { CR
} },
2305 { "bsolr+", XLOCB(19,BOTP
,CBSO
,16,0), XLBOCBBB_MASK
, NOPOWER4
, { CR
} },
2306 { "bsolr-", XLOCB(19,BOTM4
,CBSO
,16,0), XLBOCBBB_MASK
, POWER4
, { CR
} },
2307 { "bsolr+", XLOCB(19,BOTP4
,CBSO
,16,0), XLBOCBBB_MASK
, POWER4
, { CR
} },
2308 { "bsor", XLOCB(19,BOT
,CBSO
,16,0), XLBOCBBB_MASK
, PWRCOM
, { CR
} },
2309 { "bsolrl", XLOCB(19,BOT
,CBSO
,16,1), XLBOCBBB_MASK
, PPCCOM
, { CR
} },
2310 { "bsolrl-", XLOCB(19,BOT
,CBSO
,16,1), XLBOCBBB_MASK
, NOPOWER4
, { CR
} },
2311 { "bsolrl+", XLOCB(19,BOTP
,CBSO
,16,1), XLBOCBBB_MASK
, NOPOWER4
, { CR
} },
2312 { "bsolrl-", XLOCB(19,BOTM4
,CBSO
,16,1), XLBOCBBB_MASK
, POWER4
, { CR
} },
2313 { "bsolrl+", XLOCB(19,BOTP4
,CBSO
,16,1), XLBOCBBB_MASK
, POWER4
, { CR
} },
2314 { "bsorl", XLOCB(19,BOT
,CBSO
,16,1), XLBOCBBB_MASK
, PWRCOM
, { CR
} },
2315 { "bunlr", XLOCB(19,BOT
,CBSO
,16,0), XLBOCBBB_MASK
, PPCCOM
, { CR
} },
2316 { "bunlr-", XLOCB(19,BOT
,CBSO
,16,0), XLBOCBBB_MASK
, NOPOWER4
, { CR
} },
2317 { "bunlr+", XLOCB(19,BOTP
,CBSO
,16,0), XLBOCBBB_MASK
, NOPOWER4
, { CR
} },
2318 { "bunlr-", XLOCB(19,BOTM4
,CBSO
,16,0), XLBOCBBB_MASK
, POWER4
, { CR
} },
2319 { "bunlr+", XLOCB(19,BOTP4
,CBSO
,16,0), XLBOCBBB_MASK
, POWER4
, { CR
} },
2320 { "bunlrl", XLOCB(19,BOT
,CBSO
,16,1), XLBOCBBB_MASK
, PPCCOM
, { CR
} },
2321 { "bunlrl-", XLOCB(19,BOT
,CBSO
,16,1), XLBOCBBB_MASK
, NOPOWER4
, { CR
} },
2322 { "bunlrl+", XLOCB(19,BOTP
,CBSO
,16,1), XLBOCBBB_MASK
, NOPOWER4
, { CR
} },
2323 { "bunlrl-", XLOCB(19,BOTM4
,CBSO
,16,1), XLBOCBBB_MASK
, POWER4
, { CR
} },
2324 { "bunlrl+", XLOCB(19,BOTP4
,CBSO
,16,1), XLBOCBBB_MASK
, POWER4
, { CR
} },
2325 { "bgelr", XLOCB(19,BOF
,CBLT
,16,0), XLBOCBBB_MASK
, PPCCOM
, { CR
} },
2326 { "bgelr-", XLOCB(19,BOF
,CBLT
,16,0), XLBOCBBB_MASK
, NOPOWER4
, { CR
} },
2327 { "bgelr+", XLOCB(19,BOFP
,CBLT
,16,0), XLBOCBBB_MASK
, NOPOWER4
, { CR
} },
2328 { "bgelr-", XLOCB(19,BOFM4
,CBLT
,16,0), XLBOCBBB_MASK
, POWER4
, { CR
} },
2329 { "bgelr+", XLOCB(19,BOFP4
,CBLT
,16,0), XLBOCBBB_MASK
, POWER4
, { CR
} },
2330 { "bger", XLOCB(19,BOF
,CBLT
,16,0), XLBOCBBB_MASK
, PWRCOM
, { CR
} },
2331 { "bgelrl", XLOCB(19,BOF
,CBLT
,16,1), XLBOCBBB_MASK
, PPCCOM
, { CR
} },
2332 { "bgelrl-", XLOCB(19,BOF
,CBLT
,16,1), XLBOCBBB_MASK
, NOPOWER4
, { CR
} },
2333 { "bgelrl+", XLOCB(19,BOFP
,CBLT
,16,1), XLBOCBBB_MASK
, NOPOWER4
, { CR
} },
2334 { "bgelrl-", XLOCB(19,BOFM4
,CBLT
,16,1), XLBOCBBB_MASK
, POWER4
, { CR
} },
2335 { "bgelrl+", XLOCB(19,BOFP4
,CBLT
,16,1), XLBOCBBB_MASK
, POWER4
, { CR
} },
2336 { "bgerl", XLOCB(19,BOF
,CBLT
,16,1), XLBOCBBB_MASK
, PWRCOM
, { CR
} },
2337 { "bnllr", XLOCB(19,BOF
,CBLT
,16,0), XLBOCBBB_MASK
, PPCCOM
, { CR
} },
2338 { "bnllr-", XLOCB(19,BOF
,CBLT
,16,0), XLBOCBBB_MASK
, NOPOWER4
, { CR
} },
2339 { "bnllr+", XLOCB(19,BOFP
,CBLT
,16,0), XLBOCBBB_MASK
, NOPOWER4
, { CR
} },
2340 { "bnllr-", XLOCB(19,BOFM4
,CBLT
,16,0), XLBOCBBB_MASK
, POWER4
, { CR
} },
2341 { "bnllr+", XLOCB(19,BOFP4
,CBLT
,16,0), XLBOCBBB_MASK
, POWER4
, { CR
} },
2342 { "bnlr", XLOCB(19,BOF
,CBLT
,16,0), XLBOCBBB_MASK
, PWRCOM
, { CR
} },
2343 { "bnllrl", XLOCB(19,BOF
,CBLT
,16,1), XLBOCBBB_MASK
, PPCCOM
, { CR
} },
2344 { "bnllrl-", XLOCB(19,BOF
,CBLT
,16,1), XLBOCBBB_MASK
, NOPOWER4
, { CR
} },
2345 { "bnllrl+", XLOCB(19,BOFP
,CBLT
,16,1), XLBOCBBB_MASK
, NOPOWER4
, { CR
} },
2346 { "bnllrl-", XLOCB(19,BOFM4
,CBLT
,16,1), XLBOCBBB_MASK
, POWER4
, { CR
} },
2347 { "bnllrl+", XLOCB(19,BOFP4
,CBLT
,16,1), XLBOCBBB_MASK
, POWER4
, { CR
} },
2348 { "bnlrl", XLOCB(19,BOF
,CBLT
,16,1), XLBOCBBB_MASK
, PWRCOM
, { CR
} },
2349 { "blelr", XLOCB(19,BOF
,CBGT
,16,0), XLBOCBBB_MASK
, PPCCOM
, { CR
} },
2350 { "blelr-", XLOCB(19,BOF
,CBGT
,16,0), XLBOCBBB_MASK
, NOPOWER4
, { CR
} },
2351 { "blelr+", XLOCB(19,BOFP
,CBGT
,16,0), XLBOCBBB_MASK
, NOPOWER4
, { CR
} },
2352 { "blelr-", XLOCB(19,BOFM4
,CBGT
,16,0), XLBOCBBB_MASK
, POWER4
, { CR
} },
2353 { "blelr+", XLOCB(19,BOFP4
,CBGT
,16,0), XLBOCBBB_MASK
, POWER4
, { CR
} },
2354 { "bler", XLOCB(19,BOF
,CBGT
,16,0), XLBOCBBB_MASK
, PWRCOM
, { CR
} },
2355 { "blelrl", XLOCB(19,BOF
,CBGT
,16,1), XLBOCBBB_MASK
, PPCCOM
, { CR
} },
2356 { "blelrl-", XLOCB(19,BOF
,CBGT
,16,1), XLBOCBBB_MASK
, NOPOWER4
, { CR
} },
2357 { "blelrl+", XLOCB(19,BOFP
,CBGT
,16,1), XLBOCBBB_MASK
, NOPOWER4
, { CR
} },
2358 { "blelrl-", XLOCB(19,BOFM4
,CBGT
,16,1), XLBOCBBB_MASK
, POWER4
, { CR
} },
2359 { "blelrl+", XLOCB(19,BOFP4
,CBGT
,16,1), XLBOCBBB_MASK
, POWER4
, { CR
} },
2360 { "blerl", XLOCB(19,BOF
,CBGT
,16,1), XLBOCBBB_MASK
, PWRCOM
, { CR
} },
2361 { "bnglr", XLOCB(19,BOF
,CBGT
,16,0), XLBOCBBB_MASK
, PPCCOM
, { CR
} },
2362 { "bnglr-", XLOCB(19,BOF
,CBGT
,16,0), XLBOCBBB_MASK
, NOPOWER4
, { CR
} },
2363 { "bnglr+", XLOCB(19,BOFP
,CBGT
,16,0), XLBOCBBB_MASK
, NOPOWER4
, { CR
} },
2364 { "bnglr-", XLOCB(19,BOFM4
,CBGT
,16,0), XLBOCBBB_MASK
, POWER4
, { CR
} },
2365 { "bnglr+", XLOCB(19,BOFP4
,CBGT
,16,0), XLBOCBBB_MASK
, POWER4
, { CR
} },
2366 { "bngr", XLOCB(19,BOF
,CBGT
,16,0), XLBOCBBB_MASK
, PWRCOM
, { CR
} },
2367 { "bnglrl", XLOCB(19,BOF
,CBGT
,16,1), XLBOCBBB_MASK
, PPCCOM
, { CR
} },
2368 { "bnglrl-", XLOCB(19,BOF
,CBGT
,16,1), XLBOCBBB_MASK
, NOPOWER4
, { CR
} },
2369 { "bnglrl+", XLOCB(19,BOFP
,CBGT
,16,1), XLBOCBBB_MASK
, NOPOWER4
, { CR
} },
2370 { "bnglrl-", XLOCB(19,BOFM4
,CBGT
,16,1), XLBOCBBB_MASK
, POWER4
, { CR
} },
2371 { "bnglrl+", XLOCB(19,BOFP4
,CBGT
,16,1), XLBOCBBB_MASK
, POWER4
, { CR
} },
2372 { "bngrl", XLOCB(19,BOF
,CBGT
,16,1), XLBOCBBB_MASK
, PWRCOM
, { CR
} },
2373 { "bnelr", XLOCB(19,BOF
,CBEQ
,16,0), XLBOCBBB_MASK
, PPCCOM
, { CR
} },
2374 { "bnelr-", XLOCB(19,BOF
,CBEQ
,16,0), XLBOCBBB_MASK
, NOPOWER4
, { CR
} },
2375 { "bnelr+", XLOCB(19,BOFP
,CBEQ
,16,0), XLBOCBBB_MASK
, NOPOWER4
, { CR
} },
2376 { "bnelr-", XLOCB(19,BOFM4
,CBEQ
,16,0), XLBOCBBB_MASK
, POWER4
, { CR
} },
2377 { "bnelr+", XLOCB(19,BOFP4
,CBEQ
,16,0), XLBOCBBB_MASK
, POWER4
, { CR
} },
2378 { "bner", XLOCB(19,BOF
,CBEQ
,16,0), XLBOCBBB_MASK
, PWRCOM
, { CR
} },
2379 { "bnelrl", XLOCB(19,BOF
,CBEQ
,16,1), XLBOCBBB_MASK
, PPCCOM
, { CR
} },
2380 { "bnelrl-", XLOCB(19,BOF
,CBEQ
,16,1), XLBOCBBB_MASK
, NOPOWER4
, { CR
} },
2381 { "bnelrl+", XLOCB(19,BOFP
,CBEQ
,16,1), XLBOCBBB_MASK
, NOPOWER4
, { CR
} },
2382 { "bnelrl-", XLOCB(19,BOFM4
,CBEQ
,16,1), XLBOCBBB_MASK
, POWER4
, { CR
} },
2383 { "bnelrl+", XLOCB(19,BOFP4
,CBEQ
,16,1), XLBOCBBB_MASK
, POWER4
, { CR
} },
2384 { "bnerl", XLOCB(19,BOF
,CBEQ
,16,1), XLBOCBBB_MASK
, PWRCOM
, { CR
} },
2385 { "bnslr", XLOCB(19,BOF
,CBSO
,16,0), XLBOCBBB_MASK
, PPCCOM
, { CR
} },
2386 { "bnslr-", XLOCB(19,BOF
,CBSO
,16,0), XLBOCBBB_MASK
, NOPOWER4
, { CR
} },
2387 { "bnslr+", XLOCB(19,BOFP
,CBSO
,16,0), XLBOCBBB_MASK
, NOPOWER4
, { CR
} },
2388 { "bnslr-", XLOCB(19,BOFM4
,CBSO
,16,0), XLBOCBBB_MASK
, POWER4
, { CR
} },
2389 { "bnslr+", XLOCB(19,BOFP4
,CBSO
,16,0), XLBOCBBB_MASK
, POWER4
, { CR
} },
2390 { "bnsr", XLOCB(19,BOF
,CBSO
,16,0), XLBOCBBB_MASK
, PWRCOM
, { CR
} },
2391 { "bnslrl", XLOCB(19,BOF
,CBSO
,16,1), XLBOCBBB_MASK
, PPCCOM
, { CR
} },
2392 { "bnslrl-", XLOCB(19,BOF
,CBSO
,16,1), XLBOCBBB_MASK
, NOPOWER4
, { CR
} },
2393 { "bnslrl+", XLOCB(19,BOFP
,CBSO
,16,1), XLBOCBBB_MASK
, NOPOWER4
, { CR
} },
2394 { "bnslrl-", XLOCB(19,BOFM4
,CBSO
,16,1), XLBOCBBB_MASK
, POWER4
, { CR
} },
2395 { "bnslrl+", XLOCB(19,BOFP4
,CBSO
,16,1), XLBOCBBB_MASK
, POWER4
, { CR
} },
2396 { "bnsrl", XLOCB(19,BOF
,CBSO
,16,1), XLBOCBBB_MASK
, PWRCOM
, { CR
} },
2397 { "bnulr", XLOCB(19,BOF
,CBSO
,16,0), XLBOCBBB_MASK
, PPCCOM
, { CR
} },
2398 { "bnulr-", XLOCB(19,BOF
,CBSO
,16,0), XLBOCBBB_MASK
, NOPOWER4
, { CR
} },
2399 { "bnulr+", XLOCB(19,BOFP
,CBSO
,16,0), XLBOCBBB_MASK
, NOPOWER4
, { CR
} },
2400 { "bnulr-", XLOCB(19,BOFM4
,CBSO
,16,0), XLBOCBBB_MASK
, POWER4
, { CR
} },
2401 { "bnulr+", XLOCB(19,BOFP4
,CBSO
,16,0), XLBOCBBB_MASK
, POWER4
, { CR
} },
2402 { "bnulrl", XLOCB(19,BOF
,CBSO
,16,1), XLBOCBBB_MASK
, PPCCOM
, { CR
} },
2403 { "bnulrl-", XLOCB(19,BOF
,CBSO
,16,1), XLBOCBBB_MASK
, NOPOWER4
, { CR
} },
2404 { "bnulrl+", XLOCB(19,BOFP
,CBSO
,16,1), XLBOCBBB_MASK
, NOPOWER4
, { CR
} },
2405 { "bnulrl-", XLOCB(19,BOFM4
,CBSO
,16,1), XLBOCBBB_MASK
, POWER4
, { CR
} },
2406 { "bnulrl+", XLOCB(19,BOFP4
,CBSO
,16,1), XLBOCBBB_MASK
, POWER4
, { CR
} },
2407 { "btlr", XLO(19,BOT
,16,0), XLBOBB_MASK
, PPCCOM
, { BI
} },
2408 { "btlr-", XLO(19,BOT
,16,0), XLBOBB_MASK
, NOPOWER4
, { BI
} },
2409 { "btlr+", XLO(19,BOTP
,16,0), XLBOBB_MASK
, NOPOWER4
, { BI
} },
2410 { "btlr-", XLO(19,BOTM4
,16,0), XLBOBB_MASK
, POWER4
, { BI
} },
2411 { "btlr+", XLO(19,BOTP4
,16,0), XLBOBB_MASK
, POWER4
, { BI
} },
2412 { "bbtr", XLO(19,BOT
,16,0), XLBOBB_MASK
, PWRCOM
, { BI
} },
2413 { "btlrl", XLO(19,BOT
,16,1), XLBOBB_MASK
, PPCCOM
, { BI
} },
2414 { "btlrl-", XLO(19,BOT
,16,1), XLBOBB_MASK
, NOPOWER4
, { BI
} },
2415 { "btlrl+", XLO(19,BOTP
,16,1), XLBOBB_MASK
, NOPOWER4
, { BI
} },
2416 { "btlrl-", XLO(19,BOTM4
,16,1), XLBOBB_MASK
, POWER4
, { BI
} },
2417 { "btlrl+", XLO(19,BOTP4
,16,1), XLBOBB_MASK
, POWER4
, { BI
} },
2418 { "bbtrl", XLO(19,BOT
,16,1), XLBOBB_MASK
, PWRCOM
, { BI
} },
2419 { "bflr", XLO(19,BOF
,16,0), XLBOBB_MASK
, PPCCOM
, { BI
} },
2420 { "bflr-", XLO(19,BOF
,16,0), XLBOBB_MASK
, NOPOWER4
, { BI
} },
2421 { "bflr+", XLO(19,BOFP
,16,0), XLBOBB_MASK
, NOPOWER4
, { BI
} },
2422 { "bflr-", XLO(19,BOFM4
,16,0), XLBOBB_MASK
, POWER4
, { BI
} },
2423 { "bflr+", XLO(19,BOFP4
,16,0), XLBOBB_MASK
, POWER4
, { BI
} },
2424 { "bbfr", XLO(19,BOF
,16,0), XLBOBB_MASK
, PWRCOM
, { BI
} },
2425 { "bflrl", XLO(19,BOF
,16,1), XLBOBB_MASK
, PPCCOM
, { BI
} },
2426 { "bflrl-", XLO(19,BOF
,16,1), XLBOBB_MASK
, NOPOWER4
, { BI
} },
2427 { "bflrl+", XLO(19,BOFP
,16,1), XLBOBB_MASK
, NOPOWER4
, { BI
} },
2428 { "bflrl-", XLO(19,BOFM4
,16,1), XLBOBB_MASK
, POWER4
, { BI
} },
2429 { "bflrl+", XLO(19,BOFP4
,16,1), XLBOBB_MASK
, POWER4
, { BI
} },
2430 { "bbfrl", XLO(19,BOF
,16,1), XLBOBB_MASK
, PWRCOM
, { BI
} },
2431 { "bdnztlr", XLO(19,BODNZT
,16,0), XLBOBB_MASK
, PPCCOM
, { BI
} },
2432 { "bdnztlr-",XLO(19,BODNZT
,16,0), XLBOBB_MASK
, NOPOWER4
, { BI
} },
2433 { "bdnztlr+",XLO(19,BODNZTP
,16,0), XLBOBB_MASK
, NOPOWER4
, { BI
} },
2434 { "bdnztlrl",XLO(19,BODNZT
,16,1), XLBOBB_MASK
, PPCCOM
, { BI
} },
2435 { "bdnztlrl-",XLO(19,BODNZT
,16,1), XLBOBB_MASK
, NOPOWER4
, { BI
} },
2436 { "bdnztlrl+",XLO(19,BODNZTP
,16,1), XLBOBB_MASK
, NOPOWER4
, { BI
} },
2437 { "bdnzflr", XLO(19,BODNZF
,16,0), XLBOBB_MASK
, PPCCOM
, { BI
} },
2438 { "bdnzflr-",XLO(19,BODNZF
,16,0), XLBOBB_MASK
, NOPOWER4
, { BI
} },
2439 { "bdnzflr+",XLO(19,BODNZFP
,16,0), XLBOBB_MASK
, NOPOWER4
, { BI
} },
2440 { "bdnzflrl",XLO(19,BODNZF
,16,1), XLBOBB_MASK
, PPCCOM
, { BI
} },
2441 { "bdnzflrl-",XLO(19,BODNZF
,16,1), XLBOBB_MASK
, NOPOWER4
, { BI
} },
2442 { "bdnzflrl+",XLO(19,BODNZFP
,16,1), XLBOBB_MASK
, NOPOWER4
, { BI
} },
2443 { "bdztlr", XLO(19,BODZT
,16,0), XLBOBB_MASK
, PPCCOM
, { BI
} },
2444 { "bdztlr-", XLO(19,BODZT
,16,0), XLBOBB_MASK
, NOPOWER4
, { BI
} },
2445 { "bdztlr+", XLO(19,BODZTP
,16,0), XLBOBB_MASK
, NOPOWER4
, { BI
} },
2446 { "bdztlrl", XLO(19,BODZT
,16,1), XLBOBB_MASK
, PPCCOM
, { BI
} },
2447 { "bdztlrl-",XLO(19,BODZT
,16,1), XLBOBB_MASK
, NOPOWER4
, { BI
} },
2448 { "bdztlrl+",XLO(19,BODZTP
,16,1), XLBOBB_MASK
, NOPOWER4
, { BI
} },
2449 { "bdzflr", XLO(19,BODZF
,16,0), XLBOBB_MASK
, PPCCOM
, { BI
} },
2450 { "bdzflr-", XLO(19,BODZF
,16,0), XLBOBB_MASK
, NOPOWER4
, { BI
} },
2451 { "bdzflr+", XLO(19,BODZFP
,16,0), XLBOBB_MASK
, NOPOWER4
, { BI
} },
2452 { "bdzflrl", XLO(19,BODZF
,16,1), XLBOBB_MASK
, PPCCOM
, { BI
} },
2453 { "bdzflrl-",XLO(19,BODZF
,16,1), XLBOBB_MASK
, NOPOWER4
, { BI
} },
2454 { "bdzflrl+",XLO(19,BODZFP
,16,1), XLBOBB_MASK
, NOPOWER4
, { BI
} },
2455 { "bclr", XLLK(19,16,0), XLYBB_MASK
, PPCCOM
, { BO
, BI
} },
2456 { "bclrl", XLLK(19,16,1), XLYBB_MASK
, PPCCOM
, { BO
, BI
} },
2457 { "bclr+", XLYLK(19,16,1,0), XLYBB_MASK
, PPCCOM
, { BOE
, BI
} },
2458 { "bclrl+", XLYLK(19,16,1,1), XLYBB_MASK
, PPCCOM
, { BOE
, BI
} },
2459 { "bclr-", XLYLK(19,16,0,0), XLYBB_MASK
, PPCCOM
, { BOE
, BI
} },
2460 { "bclrl-", XLYLK(19,16,0,1), XLYBB_MASK
, PPCCOM
, { BOE
, BI
} },
2461 { "bcr", XLLK(19,16,0), XLBB_MASK
, PWRCOM
, { BO
, BI
} },
2462 { "bcrl", XLLK(19,16,1), XLBB_MASK
, PWRCOM
, { BO
, BI
} },
2463 { "bclre", XLLK(19,17,0), XLBB_MASK
, BOOKE64
, { BO
, BI
} },
2464 { "bclrel", XLLK(19,17,1), XLBB_MASK
, BOOKE64
, { BO
, BI
} },
2466 { "rfid", XL(19,18), 0xffffffff, PPC64
, { 0 } },
2468 { "crnot", XL(19,33), XL_MASK
, PPCCOM
, { BT
, BA
, BBA
} },
2469 { "crnor", XL(19,33), XL_MASK
, COM
, { BT
, BA
, BB
} },
2471 { "rfi", XL(19,50), 0xffffffff, COM
, { 0 } },
2472 { "rfci", XL(19,51), 0xffffffff, PPC403
, { 0 } },
2473 { "rfci", XL(19,51), 0xffffffff, BOOKE
, { 0 } },
2475 { "rfsvc", XL(19,82), 0xffffffff, POWER
, { 0 } },
2477 { "crandc", XL(19,129), XL_MASK
, COM
, { BT
, BA
, BB
} },
2479 { "isync", XL(19,150), 0xffffffff, PPCCOM
, { 0 } },
2480 { "ics", XL(19,150), 0xffffffff, PWRCOM
, { 0 } },
2482 { "crclr", XL(19,193), XL_MASK
, PPCCOM
, { BT
, BAT
, BBA
} },
2483 { "crxor", XL(19,193), XL_MASK
, COM
, { BT
, BA
, BB
} },
2485 { "crnand", XL(19,225), XL_MASK
, COM
, { BT
, BA
, BB
} },
2487 { "crand", XL(19,257), XL_MASK
, COM
, { BT
, BA
, BB
} },
2489 { "crset", XL(19,289), XL_MASK
, PPCCOM
, { BT
, BAT
, BBA
} },
2490 { "creqv", XL(19,289), XL_MASK
, COM
, { BT
, BA
, BB
} },
2492 { "crorc", XL(19,417), XL_MASK
, COM
, { BT
, BA
, BB
} },
2494 { "crmove", XL(19,449), XL_MASK
, PPCCOM
, { BT
, BA
, BBA
} },
2495 { "cror", XL(19,449), XL_MASK
, COM
, { BT
, BA
, BB
} },
2497 { "bctr", XLO(19,BOU
,528,0), XLBOBIBB_MASK
, COM
, { 0 } },
2498 { "bctrl", XLO(19,BOU
,528,1), XLBOBIBB_MASK
, COM
, { 0 } },
2499 { "bltctr", XLOCB(19,BOT
,CBLT
,528,0), XLBOCBBB_MASK
, PPCCOM
, { CR
} },
2500 { "bltctr-", XLOCB(19,BOT
,CBLT
,528,0), XLBOCBBB_MASK
, NOPOWER4
, { CR
} },
2501 { "bltctr+", XLOCB(19,BOTP
,CBLT
,528,0), XLBOCBBB_MASK
, NOPOWER4
, { CR
} },
2502 { "bltctr-", XLOCB(19,BOTM4
,CBLT
,528,0), XLBOCBBB_MASK
, POWER4
, { CR
} },
2503 { "bltctr+", XLOCB(19,BOTP4
,CBLT
,528,0), XLBOCBBB_MASK
, POWER4
, { CR
} },
2504 { "bltctrl", XLOCB(19,BOT
,CBLT
,528,1), XLBOCBBB_MASK
, PPCCOM
, { CR
} },
2505 { "bltctrl-",XLOCB(19,BOT
,CBLT
,528,1), XLBOCBBB_MASK
, NOPOWER4
, { CR
} },
2506 { "bltctrl+",XLOCB(19,BOTP
,CBLT
,528,1), XLBOCBBB_MASK
, NOPOWER4
, { CR
} },
2507 { "bltctrl-",XLOCB(19,BOTM4
,CBLT
,528,1), XLBOCBBB_MASK
, POWER4
, { CR
} },
2508 { "bltctrl+",XLOCB(19,BOTP4
,CBLT
,528,1), XLBOCBBB_MASK
, POWER4
, { CR
} },
2509 { "bgtctr", XLOCB(19,BOT
,CBGT
,528,0), XLBOCBBB_MASK
, PPCCOM
, { CR
} },
2510 { "bgtctr-", XLOCB(19,BOT
,CBGT
,528,0), XLBOCBBB_MASK
, NOPOWER4
, { CR
} },
2511 { "bgtctr+", XLOCB(19,BOTP
,CBGT
,528,0), XLBOCBBB_MASK
, NOPOWER4
, { CR
} },
2512 { "bgtctr-", XLOCB(19,BOTM4
,CBGT
,528,0), XLBOCBBB_MASK
, POWER4
, { CR
} },
2513 { "bgtctr+", XLOCB(19,BOTP4
,CBGT
,528,0), XLBOCBBB_MASK
, POWER4
, { CR
} },
2514 { "bgtctrl", XLOCB(19,BOT
,CBGT
,528,1), XLBOCBBB_MASK
, PPCCOM
, { CR
} },
2515 { "bgtctrl-",XLOCB(19,BOT
,CBGT
,528,1), XLBOCBBB_MASK
, NOPOWER4
, { CR
} },
2516 { "bgtctrl+",XLOCB(19,BOTP
,CBGT
,528,1), XLBOCBBB_MASK
, NOPOWER4
, { CR
} },
2517 { "bgtctrl-",XLOCB(19,BOTM4
,CBGT
,528,1), XLBOCBBB_MASK
, POWER4
, { CR
} },
2518 { "bgtctrl+",XLOCB(19,BOTP4
,CBGT
,528,1), XLBOCBBB_MASK
, POWER4
, { CR
} },
2519 { "beqctr", XLOCB(19,BOT
,CBEQ
,528,0), XLBOCBBB_MASK
, PPCCOM
, { CR
} },
2520 { "beqctr-", XLOCB(19,BOT
,CBEQ
,528,0), XLBOCBBB_MASK
, NOPOWER4
, { CR
} },
2521 { "beqctr+", XLOCB(19,BOTP
,CBEQ
,528,0), XLBOCBBB_MASK
, NOPOWER4
, { CR
} },
2522 { "beqctr-", XLOCB(19,BOTM4
,CBEQ
,528,0), XLBOCBBB_MASK
, POWER4
, { CR
} },
2523 { "beqctr+", XLOCB(19,BOTP4
,CBEQ
,528,0), XLBOCBBB_MASK
, POWER4
, { CR
} },
2524 { "beqctrl", XLOCB(19,BOT
,CBEQ
,528,1), XLBOCBBB_MASK
, PPCCOM
, { CR
} },
2525 { "beqctrl-",XLOCB(19,BOT
,CBEQ
,528,1), XLBOCBBB_MASK
, NOPOWER4
, { CR
} },
2526 { "beqctrl+",XLOCB(19,BOTP
,CBEQ
,528,1), XLBOCBBB_MASK
, NOPOWER4
, { CR
} },
2527 { "beqctrl-",XLOCB(19,BOTM4
,CBEQ
,528,1), XLBOCBBB_MASK
, POWER4
, { CR
} },
2528 { "beqctrl+",XLOCB(19,BOTP4
,CBEQ
,528,1), XLBOCBBB_MASK
, POWER4
, { CR
} },
2529 { "bsoctr", XLOCB(19,BOT
,CBSO
,528,0), XLBOCBBB_MASK
, PPCCOM
, { CR
} },
2530 { "bsoctr-", XLOCB(19,BOT
,CBSO
,528,0), XLBOCBBB_MASK
, NOPOWER4
, { CR
} },
2531 { "bsoctr+", XLOCB(19,BOTP
,CBSO
,528,0), XLBOCBBB_MASK
, NOPOWER4
, { CR
} },
2532 { "bsoctr-", XLOCB(19,BOTM4
,CBSO
,528,0), XLBOCBBB_MASK
, POWER4
, { CR
} },
2533 { "bsoctr+", XLOCB(19,BOTP4
,CBSO
,528,0), XLBOCBBB_MASK
, POWER4
, { CR
} },
2534 { "bsoctrl", XLOCB(19,BOT
,CBSO
,528,1), XLBOCBBB_MASK
, PPCCOM
, { CR
} },
2535 { "bsoctrl-",XLOCB(19,BOT
,CBSO
,528,1), XLBOCBBB_MASK
, NOPOWER4
, { CR
} },
2536 { "bsoctrl+",XLOCB(19,BOTP
,CBSO
,528,1), XLBOCBBB_MASK
, NOPOWER4
, { CR
} },
2537 { "bsoctrl-",XLOCB(19,BOTM4
,CBSO
,528,1), XLBOCBBB_MASK
, POWER4
, { CR
} },
2538 { "bsoctrl+",XLOCB(19,BOTP4
,CBSO
,528,1), XLBOCBBB_MASK
, POWER4
, { CR
} },
2539 { "bunctr", XLOCB(19,BOT
,CBSO
,528,0), XLBOCBBB_MASK
, PPCCOM
, { CR
} },
2540 { "bunctr-", XLOCB(19,BOT
,CBSO
,528,0), XLBOCBBB_MASK
, NOPOWER4
, { CR
} },
2541 { "bunctr+", XLOCB(19,BOTP
,CBSO
,528,0), XLBOCBBB_MASK
, NOPOWER4
, { CR
} },
2542 { "bunctr-", XLOCB(19,BOTM4
,CBSO
,528,0), XLBOCBBB_MASK
, POWER4
, { CR
} },
2543 { "bunctr+", XLOCB(19,BOTP4
,CBSO
,528,0), XLBOCBBB_MASK
, POWER4
, { CR
} },
2544 { "bunctrl", XLOCB(19,BOT
,CBSO
,528,1), XLBOCBBB_MASK
, PPCCOM
, { CR
} },
2545 { "bunctrl-",XLOCB(19,BOT
,CBSO
,528,1), XLBOCBBB_MASK
, NOPOWER4
, { CR
} },
2546 { "bunctrl+",XLOCB(19,BOTP
,CBSO
,528,1), XLBOCBBB_MASK
, NOPOWER4
, { CR
} },
2547 { "bunctrl-",XLOCB(19,BOTM4
,CBSO
,528,1), XLBOCBBB_MASK
, POWER4
, { CR
} },
2548 { "bunctrl+",XLOCB(19,BOTP4
,CBSO
,528,1), XLBOCBBB_MASK
, POWER4
, { CR
} },
2549 { "bgectr", XLOCB(19,BOF
,CBLT
,528,0), XLBOCBBB_MASK
, PPCCOM
, { CR
} },
2550 { "bgectr-", XLOCB(19,BOF
,CBLT
,528,0), XLBOCBBB_MASK
, NOPOWER4
, { CR
} },
2551 { "bgectr+", XLOCB(19,BOFP
,CBLT
,528,0), XLBOCBBB_MASK
, NOPOWER4
, { CR
} },
2552 { "bgectr-", XLOCB(19,BOFM4
,CBLT
,528,0), XLBOCBBB_MASK
, POWER4
, { CR
} },
2553 { "bgectr+", XLOCB(19,BOFP4
,CBLT
,528,0), XLBOCBBB_MASK
, POWER4
, { CR
} },
2554 { "bgectrl", XLOCB(19,BOF
,CBLT
,528,1), XLBOCBBB_MASK
, PPCCOM
, { CR
} },
2555 { "bgectrl-",XLOCB(19,BOF
,CBLT
,528,1), XLBOCBBB_MASK
, NOPOWER4
, { CR
} },
2556 { "bgectrl+",XLOCB(19,BOFP
,CBLT
,528,1), XLBOCBBB_MASK
, NOPOWER4
, { CR
} },
2557 { "bgectrl-",XLOCB(19,BOFM4
,CBLT
,528,1), XLBOCBBB_MASK
, POWER4
, { CR
} },
2558 { "bgectrl+",XLOCB(19,BOFP4
,CBLT
,528,1), XLBOCBBB_MASK
, POWER4
, { CR
} },
2559 { "bnlctr", XLOCB(19,BOF
,CBLT
,528,0), XLBOCBBB_MASK
, PPCCOM
, { CR
} },
2560 { "bnlctr-", XLOCB(19,BOF
,CBLT
,528,0), XLBOCBBB_MASK
, NOPOWER4
, { CR
} },
2561 { "bnlctr+", XLOCB(19,BOFP
,CBLT
,528,0), XLBOCBBB_MASK
, NOPOWER4
, { CR
} },
2562 { "bnlctr-", XLOCB(19,BOFM4
,CBLT
,528,0), XLBOCBBB_MASK
, POWER4
, { CR
} },
2563 { "bnlctr+", XLOCB(19,BOFP4
,CBLT
,528,0), XLBOCBBB_MASK
, POWER4
, { CR
} },
2564 { "bnlctrl", XLOCB(19,BOF
,CBLT
,528,1), XLBOCBBB_MASK
, PPCCOM
, { CR
} },
2565 { "bnlctrl-",XLOCB(19,BOF
,CBLT
,528,1), XLBOCBBB_MASK
, NOPOWER4
, { CR
} },
2566 { "bnlctrl+",XLOCB(19,BOFP
,CBLT
,528,1), XLBOCBBB_MASK
, NOPOWER4
, { CR
} },
2567 { "bnlctrl-",XLOCB(19,BOFM4
,CBLT
,528,1), XLBOCBBB_MASK
, POWER4
, { CR
} },
2568 { "bnlctrl+",XLOCB(19,BOFP4
,CBLT
,528,1), XLBOCBBB_MASK
, POWER4
, { CR
} },
2569 { "blectr", XLOCB(19,BOF
,CBGT
,528,0), XLBOCBBB_MASK
, PPCCOM
, { CR
} },
2570 { "blectr-", XLOCB(19,BOF
,CBGT
,528,0), XLBOCBBB_MASK
, NOPOWER4
, { CR
} },
2571 { "blectr+", XLOCB(19,BOFP
,CBGT
,528,0), XLBOCBBB_MASK
, NOPOWER4
, { CR
} },
2572 { "blectr-", XLOCB(19,BOFM4
,CBGT
,528,0), XLBOCBBB_MASK
, POWER4
, { CR
} },
2573 { "blectr+", XLOCB(19,BOFP4
,CBGT
,528,0), XLBOCBBB_MASK
, POWER4
, { CR
} },
2574 { "blectrl", XLOCB(19,BOF
,CBGT
,528,1), XLBOCBBB_MASK
, PPCCOM
, { CR
} },
2575 { "blectrl-",XLOCB(19,BOF
,CBGT
,528,1), XLBOCBBB_MASK
, NOPOWER4
, { CR
} },
2576 { "blectrl+",XLOCB(19,BOFP
,CBGT
,528,1), XLBOCBBB_MASK
, NOPOWER4
, { CR
} },
2577 { "blectrl-",XLOCB(19,BOFM4
,CBGT
,528,1), XLBOCBBB_MASK
, POWER4
, { CR
} },
2578 { "blectrl+",XLOCB(19,BOFP4
,CBGT
,528,1), XLBOCBBB_MASK
, POWER4
, { CR
} },
2579 { "bngctr", XLOCB(19,BOF
,CBGT
,528,0), XLBOCBBB_MASK
, PPCCOM
, { CR
} },
2580 { "bngctr-", XLOCB(19,BOF
,CBGT
,528,0), XLBOCBBB_MASK
, NOPOWER4
, { CR
} },
2581 { "bngctr+", XLOCB(19,BOFP
,CBGT
,528,0), XLBOCBBB_MASK
, NOPOWER4
, { CR
} },
2582 { "bngctr-", XLOCB(19,BOFM4
,CBGT
,528,0), XLBOCBBB_MASK
, POWER4
, { CR
} },
2583 { "bngctr+", XLOCB(19,BOFP4
,CBGT
,528,0), XLBOCBBB_MASK
, POWER4
, { CR
} },
2584 { "bngctrl", XLOCB(19,BOF
,CBGT
,528,1), XLBOCBBB_MASK
, PPCCOM
, { CR
} },
2585 { "bngctrl-",XLOCB(19,BOF
,CBGT
,528,1), XLBOCBBB_MASK
, NOPOWER4
, { CR
} },
2586 { "bngctrl+",XLOCB(19,BOFP
,CBGT
,528,1), XLBOCBBB_MASK
, NOPOWER4
, { CR
} },
2587 { "bngctrl-",XLOCB(19,BOFM4
,CBGT
,528,1), XLBOCBBB_MASK
, POWER4
, { CR
} },
2588 { "bngctrl+",XLOCB(19,BOFP4
,CBGT
,528,1), XLBOCBBB_MASK
, POWER4
, { CR
} },
2589 { "bnectr", XLOCB(19,BOF
,CBEQ
,528,0), XLBOCBBB_MASK
, PPCCOM
, { CR
} },
2590 { "bnectr-", XLOCB(19,BOF
,CBEQ
,528,0), XLBOCBBB_MASK
, NOPOWER4
, { CR
} },
2591 { "bnectr+", XLOCB(19,BOFP
,CBEQ
,528,0), XLBOCBBB_MASK
, NOPOWER4
, { CR
} },
2592 { "bnectr-", XLOCB(19,BOFM4
,CBEQ
,528,0), XLBOCBBB_MASK
, POWER4
, { CR
} },
2593 { "bnectr+", XLOCB(19,BOFP4
,CBEQ
,528,0), XLBOCBBB_MASK
, POWER4
, { CR
} },
2594 { "bnectrl", XLOCB(19,BOF
,CBEQ
,528,1), XLBOCBBB_MASK
, PPCCOM
, { CR
} },
2595 { "bnectrl-",XLOCB(19,BOF
,CBEQ
,528,1), XLBOCBBB_MASK
, NOPOWER4
, { CR
} },
2596 { "bnectrl+",XLOCB(19,BOFP
,CBEQ
,528,1), XLBOCBBB_MASK
, NOPOWER4
, { CR
} },
2597 { "bnectrl-",XLOCB(19,BOFM4
,CBEQ
,528,1), XLBOCBBB_MASK
, POWER4
, { CR
} },
2598 { "bnectrl+",XLOCB(19,BOFP4
,CBEQ
,528,1), XLBOCBBB_MASK
, POWER4
, { CR
} },
2599 { "bnsctr", XLOCB(19,BOF
,CBSO
,528,0), XLBOCBBB_MASK
, PPCCOM
, { CR
} },
2600 { "bnsctr-", XLOCB(19,BOF
,CBSO
,528,0), XLBOCBBB_MASK
, NOPOWER4
, { CR
} },
2601 { "bnsctr+", XLOCB(19,BOFP
,CBSO
,528,0), XLBOCBBB_MASK
, NOPOWER4
, { CR
} },
2602 { "bnsctr-", XLOCB(19,BOFM4
,CBSO
,528,0), XLBOCBBB_MASK
, POWER4
, { CR
} },
2603 { "bnsctr+", XLOCB(19,BOFP4
,CBSO
,528,0), XLBOCBBB_MASK
, POWER4
, { CR
} },
2604 { "bnsctrl", XLOCB(19,BOF
,CBSO
,528,1), XLBOCBBB_MASK
, PPCCOM
, { CR
} },
2605 { "bnsctrl-",XLOCB(19,BOF
,CBSO
,528,1), XLBOCBBB_MASK
, NOPOWER4
, { CR
} },
2606 { "bnsctrl+",XLOCB(19,BOFP
,CBSO
,528,1), XLBOCBBB_MASK
, NOPOWER4
, { CR
} },
2607 { "bnsctrl-",XLOCB(19,BOFM4
,CBSO
,528,1), XLBOCBBB_MASK
, POWER4
, { CR
} },
2608 { "bnsctrl+",XLOCB(19,BOFP4
,CBSO
,528,1), XLBOCBBB_MASK
, POWER4
, { CR
} },
2609 { "bnuctr", XLOCB(19,BOF
,CBSO
,528,0), XLBOCBBB_MASK
, PPCCOM
, { CR
} },
2610 { "bnuctr-", XLOCB(19,BOF
,CBSO
,528,0), XLBOCBBB_MASK
, NOPOWER4
, { CR
} },
2611 { "bnuctr+", XLOCB(19,BOFP
,CBSO
,528,0), XLBOCBBB_MASK
, NOPOWER4
, { CR
} },
2612 { "bnuctr-", XLOCB(19,BOFM4
,CBSO
,528,0), XLBOCBBB_MASK
, POWER4
, { CR
} },
2613 { "bnuctr+", XLOCB(19,BOFP4
,CBSO
,528,0), XLBOCBBB_MASK
, POWER4
, { CR
} },
2614 { "bnuctrl", XLOCB(19,BOF
,CBSO
,528,1), XLBOCBBB_MASK
, PPCCOM
, { CR
} },
2615 { "bnuctrl-",XLOCB(19,BOF
,CBSO
,528,1), XLBOCBBB_MASK
, NOPOWER4
, { CR
} },
2616 { "bnuctrl+",XLOCB(19,BOFP
,CBSO
,528,1), XLBOCBBB_MASK
, NOPOWER4
, { CR
} },
2617 { "bnuctrl-",XLOCB(19,BOFM4
,CBSO
,528,1), XLBOCBBB_MASK
, POWER4
, { CR
} },
2618 { "bnuctrl+",XLOCB(19,BOFP4
,CBSO
,528,1), XLBOCBBB_MASK
, POWER4
, { CR
} },
2619 { "btctr", XLO(19,BOT
,528,0), XLBOBB_MASK
, PPCCOM
, { BI
} },
2620 { "btctr-", XLO(19,BOT
,528,0), XLBOBB_MASK
, NOPOWER4
, { BI
} },
2621 { "btctr+", XLO(19,BOTP
,528,0), XLBOBB_MASK
, NOPOWER4
, { BI
} },
2622 { "btctr-", XLO(19,BOTM4
,528,0), XLBOBB_MASK
, POWER4
, { BI
} },
2623 { "btctr+", XLO(19,BOTP4
,528,0), XLBOBB_MASK
, POWER4
, { BI
} },
2624 { "btctrl", XLO(19,BOT
,528,1), XLBOBB_MASK
, PPCCOM
, { BI
} },
2625 { "btctrl-", XLO(19,BOT
,528,1), XLBOBB_MASK
, NOPOWER4
, { BI
} },
2626 { "btctrl+", XLO(19,BOTP
,528,1), XLBOBB_MASK
, NOPOWER4
, { BI
} },
2627 { "btctrl-", XLO(19,BOTM4
,528,1), XLBOBB_MASK
, POWER4
, { BI
} },
2628 { "btctrl+", XLO(19,BOTP4
,528,1), XLBOBB_MASK
, POWER4
, { BI
} },
2629 { "bfctr", XLO(19,BOF
,528,0), XLBOBB_MASK
, PPCCOM
, { BI
} },
2630 { "bfctr-", XLO(19,BOF
,528,0), XLBOBB_MASK
, NOPOWER4
, { BI
} },
2631 { "bfctr+", XLO(19,BOFP
,528,0), XLBOBB_MASK
, NOPOWER4
, { BI
} },
2632 { "bfctr-", XLO(19,BOFM4
,528,0), XLBOBB_MASK
, POWER4
, { BI
} },
2633 { "bfctr+", XLO(19,BOFP4
,528,0), XLBOBB_MASK
, POWER4
, { BI
} },
2634 { "bfctrl", XLO(19,BOF
,528,1), XLBOBB_MASK
, PPCCOM
, { BI
} },
2635 { "bfctrl-", XLO(19,BOF
,528,1), XLBOBB_MASK
, NOPOWER4
, { BI
} },
2636 { "bfctrl+", XLO(19,BOFP
,528,1), XLBOBB_MASK
, NOPOWER4
, { BI
} },
2637 { "bfctrl-", XLO(19,BOFM4
,528,1), XLBOBB_MASK
, POWER4
, { BI
} },
2638 { "bfctrl+", XLO(19,BOFP4
,528,1), XLBOBB_MASK
, POWER4
, { BI
} },
2639 { "bcctr", XLLK(19,528,0), XLYBB_MASK
, PPCCOM
, { BO
, BI
} },
2640 { "bcctr-", XLYLK(19,528,0,0), XLYBB_MASK
, PPCCOM
, { BOE
, BI
} },
2641 { "bcctr+", XLYLK(19,528,1,0), XLYBB_MASK
, PPCCOM
, { BOE
, BI
} },
2642 { "bcctrl", XLLK(19,528,1), XLYBB_MASK
, PPCCOM
, { BO
, BI
} },
2643 { "bcctrl-", XLYLK(19,528,0,1), XLYBB_MASK
, PPCCOM
, { BOE
, BI
} },
2644 { "bcctrl+", XLYLK(19,528,1,1), XLYBB_MASK
, PPCCOM
, { BOE
, BI
} },
2645 { "bcc", XLLK(19,528,0), XLBB_MASK
, PWRCOM
, { BO
, BI
} },
2646 { "bccl", XLLK(19,528,1), XLBB_MASK
, PWRCOM
, { BO
, BI
} },
2647 { "bcctre", XLLK(19,529,0), XLYBB_MASK
, BOOKE64
, { BO
, BI
} },
2648 { "bcctrel", XLLK(19,529,1), XLYBB_MASK
, BOOKE64
, { BO
, BI
} },
2650 { "rlwimi", M(20,0), M_MASK
, PPCCOM
, { RA
,RS
,SH
,MBE
,ME
} },
2651 { "rlimi", M(20,0), M_MASK
, PWRCOM
, { RA
,RS
,SH
,MBE
,ME
} },
2653 { "rlwimi.", M(20,1), M_MASK
, PPCCOM
, { RA
,RS
,SH
,MBE
,ME
} },
2654 { "rlimi.", M(20,1), M_MASK
, PWRCOM
, { RA
,RS
,SH
,MBE
,ME
} },
2656 { "rotlwi", MME(21,31,0), MMBME_MASK
, PPCCOM
, { RA
, RS
, SH
} },
2657 { "clrlwi", MME(21,31,0), MSHME_MASK
, PPCCOM
, { RA
, RS
, MB
} },
2658 { "rlwinm", M(21,0), M_MASK
, PPCCOM
, { RA
,RS
,SH
,MBE
,ME
} },
2659 { "rlinm", M(21,0), M_MASK
, PWRCOM
, { RA
,RS
,SH
,MBE
,ME
} },
2660 { "rotlwi.", MME(21,31,1), MMBME_MASK
, PPCCOM
, { RA
,RS
,SH
} },
2661 { "clrlwi.", MME(21,31,1), MSHME_MASK
, PPCCOM
, { RA
, RS
, MB
} },
2662 { "rlwinm.", M(21,1), M_MASK
, PPCCOM
, { RA
,RS
,SH
,MBE
,ME
} },
2663 { "rlinm.", M(21,1), M_MASK
, PWRCOM
, { RA
,RS
,SH
,MBE
,ME
} },
2665 { "rlmi", M(22,0), M_MASK
, M601
, { RA
,RS
,RB
,MBE
,ME
} },
2666 { "rlmi.", M(22,1), M_MASK
, M601
, { RA
,RS
,RB
,MBE
,ME
} },
2668 { "be", B(22,0,0), B_MASK
, BOOKE64
, { LI
} },
2669 { "bel", B(22,0,1), B_MASK
, BOOKE64
, { LI
} },
2670 { "bea", B(22,1,0), B_MASK
, BOOKE64
, { LIA
} },
2671 { "bela", B(22,1,1), B_MASK
, BOOKE64
, { LIA
} },
2673 { "rotlw", MME(23,31,0), MMBME_MASK
, PPCCOM
, { RA
, RS
, RB
} },
2674 { "rlwnm", M(23,0), M_MASK
, PPCCOM
, { RA
,RS
,RB
,MBE
,ME
} },
2675 { "rlnm", M(23,0), M_MASK
, PWRCOM
, { RA
,RS
,RB
,MBE
,ME
} },
2676 { "rotlw.", MME(23,31,1), MMBME_MASK
, PPCCOM
, { RA
, RS
, RB
} },
2677 { "rlwnm.", M(23,1), M_MASK
, PPCCOM
, { RA
,RS
,RB
,MBE
,ME
} },
2678 { "rlnm.", M(23,1), M_MASK
, PWRCOM
, { RA
,RS
,RB
,MBE
,ME
} },
2680 { "nop", OP(24), 0xffffffff, PPCCOM
, { 0 } },
2681 { "ori", OP(24), OP_MASK
, PPCCOM
, { RA
, RS
, UI
} },
2682 { "oril", OP(24), OP_MASK
, PWRCOM
, { RA
, RS
, UI
} },
2684 { "oris", OP(25), OP_MASK
, PPCCOM
, { RA
, RS
, UI
} },
2685 { "oriu", OP(25), OP_MASK
, PWRCOM
, { RA
, RS
, UI
} },
2687 { "xori", OP(26), OP_MASK
, PPCCOM
, { RA
, RS
, UI
} },
2688 { "xoril", OP(26), OP_MASK
, PWRCOM
, { RA
, RS
, UI
} },
2690 { "xoris", OP(27), OP_MASK
, PPCCOM
, { RA
, RS
, UI
} },
2691 { "xoriu", OP(27), OP_MASK
, PWRCOM
, { RA
, RS
, UI
} },
2693 { "andi.", OP(28), OP_MASK
, PPCCOM
, { RA
, RS
, UI
} },
2694 { "andil.", OP(28), OP_MASK
, PWRCOM
, { RA
, RS
, UI
} },
2696 { "andis.", OP(29), OP_MASK
, PPCCOM
, { RA
, RS
, UI
} },
2697 { "andiu.", OP(29), OP_MASK
, PWRCOM
, { RA
, RS
, UI
} },
2699 { "rotldi", MD(30,0,0), MDMB_MASK
, PPC64
, { RA
, RS
, SH6
} },
2700 { "clrldi", MD(30,0,0), MDSH_MASK
, PPC64
, { RA
, RS
, MB6
} },
2701 { "rldicl", MD(30,0,0), MD_MASK
, PPC64
, { RA
, RS
, SH6
, MB6
} },
2702 { "rotldi.", MD(30,0,1), MDMB_MASK
, PPC64
, { RA
, RS
, SH6
} },
2703 { "clrldi.", MD(30,0,1), MDSH_MASK
, PPC64
, { RA
, RS
, MB6
} },
2704 { "rldicl.", MD(30,0,1), MD_MASK
, PPC64
, { RA
, RS
, SH6
, MB6
} },
2706 { "rldicr", MD(30,1,0), MD_MASK
, PPC64
, { RA
, RS
, SH6
, ME6
} },
2707 { "rldicr.", MD(30,1,1), MD_MASK
, PPC64
, { RA
, RS
, SH6
, ME6
} },
2709 { "rldic", MD(30,2,0), MD_MASK
, PPC64
, { RA
, RS
, SH6
, MB6
} },
2710 { "rldic.", MD(30,2,1), MD_MASK
, PPC64
, { RA
, RS
, SH6
, MB6
} },
2712 { "rldimi", MD(30,3,0), MD_MASK
, PPC64
, { RA
, RS
, SH6
, MB6
} },
2713 { "rldimi.", MD(30,3,1), MD_MASK
, PPC64
, { RA
, RS
, SH6
, MB6
} },
2715 { "rotld", MDS(30,8,0), MDSMB_MASK
, PPC64
, { RA
, RS
, RB
} },
2716 { "rldcl", MDS(30,8,0), MDS_MASK
, PPC64
, { RA
, RS
, RB
, MB6
} },
2717 { "rotld.", MDS(30,8,1), MDSMB_MASK
, PPC64
, { RA
, RS
, RB
} },
2718 { "rldcl.", MDS(30,8,1), MDS_MASK
, PPC64
, { RA
, RS
, RB
, MB6
} },
2720 { "rldcr", MDS(30,9,0), MDS_MASK
, PPC64
, { RA
, RS
, RB
, ME6
} },
2721 { "rldcr.", MDS(30,9,1), MDS_MASK
, PPC64
, { RA
, RS
, RB
, ME6
} },
2723 { "cmpw", XCMPL(31,0,0), XCMPL_MASK
, PPCCOM
, { OBF
, RA
, RB
} },
2724 { "cmpd", XCMPL(31,0,1), XCMPL_MASK
, PPC64
, { OBF
, RA
, RB
} },
2725 { "cmp", X(31,0), XCMP_MASK
, PPCONLY
, { BF
, L
, RA
, RB
} },
2726 { "cmp", X(31,0), XCMPL_MASK
, PWRCOM
, { BF
, RA
, RB
} },
2728 { "twlgt", XTO(31,4,TOLGT
), XTO_MASK
, PPCCOM
, { RA
, RB
} },
2729 { "tlgt", XTO(31,4,TOLGT
), XTO_MASK
, PWRCOM
, { RA
, RB
} },
2730 { "twllt", XTO(31,4,TOLLT
), XTO_MASK
, PPCCOM
, { RA
, RB
} },
2731 { "tllt", XTO(31,4,TOLLT
), XTO_MASK
, PWRCOM
, { RA
, RB
} },
2732 { "tweq", XTO(31,4,TOEQ
), XTO_MASK
, PPCCOM
, { RA
, RB
} },
2733 { "teq", XTO(31,4,TOEQ
), XTO_MASK
, PWRCOM
, { RA
, RB
} },
2734 { "twlge", XTO(31,4,TOLGE
), XTO_MASK
, PPCCOM
, { RA
, RB
} },
2735 { "tlge", XTO(31,4,TOLGE
), XTO_MASK
, PWRCOM
, { RA
, RB
} },
2736 { "twlnl", XTO(31,4,TOLNL
), XTO_MASK
, PPCCOM
, { RA
, RB
} },
2737 { "tlnl", XTO(31,4,TOLNL
), XTO_MASK
, PWRCOM
, { RA
, RB
} },
2738 { "twlle", XTO(31,4,TOLLE
), XTO_MASK
, PPCCOM
, { RA
, RB
} },
2739 { "tlle", XTO(31,4,TOLLE
), XTO_MASK
, PWRCOM
, { RA
, RB
} },
2740 { "twlng", XTO(31,4,TOLNG
), XTO_MASK
, PPCCOM
, { RA
, RB
} },
2741 { "tlng", XTO(31,4,TOLNG
), XTO_MASK
, PWRCOM
, { RA
, RB
} },
2742 { "twgt", XTO(31,4,TOGT
), XTO_MASK
, PPCCOM
, { RA
, RB
} },
2743 { "tgt", XTO(31,4,TOGT
), XTO_MASK
, PWRCOM
, { RA
, RB
} },
2744 { "twge", XTO(31,4,TOGE
), XTO_MASK
, PPCCOM
, { RA
, RB
} },
2745 { "tge", XTO(31,4,TOGE
), XTO_MASK
, PWRCOM
, { RA
, RB
} },
2746 { "twnl", XTO(31,4,TONL
), XTO_MASK
, PPCCOM
, { RA
, RB
} },
2747 { "tnl", XTO(31,4,TONL
), XTO_MASK
, PWRCOM
, { RA
, RB
} },
2748 { "twlt", XTO(31,4,TOLT
), XTO_MASK
, PPCCOM
, { RA
, RB
} },
2749 { "tlt", XTO(31,4,TOLT
), XTO_MASK
, PWRCOM
, { RA
, RB
} },
2750 { "twle", XTO(31,4,TOLE
), XTO_MASK
, PPCCOM
, { RA
, RB
} },
2751 { "tle", XTO(31,4,TOLE
), XTO_MASK
, PWRCOM
, { RA
, RB
} },
2752 { "twng", XTO(31,4,TONG
), XTO_MASK
, PPCCOM
, { RA
, RB
} },
2753 { "tng", XTO(31,4,TONG
), XTO_MASK
, PWRCOM
, { RA
, RB
} },
2754 { "twne", XTO(31,4,TONE
), XTO_MASK
, PPCCOM
, { RA
, RB
} },
2755 { "tne", XTO(31,4,TONE
), XTO_MASK
, PWRCOM
, { RA
, RB
} },
2756 { "trap", XTO(31,4,TOU
), 0xffffffff, PPCCOM
, { 0 } },
2757 { "tw", X(31,4), X_MASK
, PPCCOM
, { TO
, RA
, RB
} },
2758 { "t", X(31,4), X_MASK
, PWRCOM
, { TO
, RA
, RB
} },
2760 { "subfc", XO(31,8,0,0), XO_MASK
, PPCCOM
, { RT
, RA
, RB
} },
2761 { "sf", XO(31,8,0,0), XO_MASK
, PWRCOM
, { RT
, RA
, RB
} },
2762 { "subc", XO(31,8,0,0), XO_MASK
, PPC
, { RT
, RB
, RA
} },
2763 { "subfc.", XO(31,8,0,1), XO_MASK
, PPCCOM
, { RT
, RA
, RB
} },
2764 { "sf.", XO(31,8,0,1), XO_MASK
, PWRCOM
, { RT
, RA
, RB
} },
2765 { "subc.", XO(31,8,0,1), XO_MASK
, PPCCOM
, { RT
, RB
, RA
} },
2766 { "subfco", XO(31,8,1,0), XO_MASK
, PPCCOM
, { RT
, RA
, RB
} },
2767 { "sfo", XO(31,8,1,0), XO_MASK
, PWRCOM
, { RT
, RA
, RB
} },
2768 { "subco", XO(31,8,1,0), XO_MASK
, PPC
, { RT
, RB
, RA
} },
2769 { "subfco.", XO(31,8,1,1), XO_MASK
, PPCCOM
, { RT
, RA
, RB
} },
2770 { "sfo.", XO(31,8,1,1), XO_MASK
, PWRCOM
, { RT
, RA
, RB
} },
2771 { "subco.", XO(31,8,1,1), XO_MASK
, PPC
, { RT
, RB
, RA
} },
2773 { "mulhdu", XO(31,9,0,0), XO_MASK
, PPC64
, { RT
, RA
, RB
} },
2774 { "mulhdu.", XO(31,9,0,1), XO_MASK
, PPC64
, { RT
, RA
, RB
} },
2776 { "addc", XO(31,10,0,0), XO_MASK
, PPCCOM
, { RT
, RA
, RB
} },
2777 { "a", XO(31,10,0,0), XO_MASK
, PWRCOM
, { RT
, RA
, RB
} },
2778 { "addc.", XO(31,10,0,1), XO_MASK
, PPCCOM
, { RT
, RA
, RB
} },
2779 { "a.", XO(31,10,0,1), XO_MASK
, PWRCOM
, { RT
, RA
, RB
} },
2780 { "addco", XO(31,10,1,0), XO_MASK
, PPCCOM
, { RT
, RA
, RB
} },
2781 { "ao", XO(31,10,1,0), XO_MASK
, PWRCOM
, { RT
, RA
, RB
} },
2782 { "addco.", XO(31,10,1,1), XO_MASK
, PPCCOM
, { RT
, RA
, RB
} },
2783 { "ao.", XO(31,10,1,1), XO_MASK
, PWRCOM
, { RT
, RA
, RB
} },
2785 { "mulhwu", XO(31,11,0,0), XO_MASK
, PPC
, { RT
, RA
, RB
} },
2786 { "mulhwu.", XO(31,11,0,1), XO_MASK
, PPC
, { RT
, RA
, RB
} },
2788 { "mfcr", X(31,19), XRARB_MASK
, COM
, { RT
} },
2790 { "lwarx", X(31,20), X_MASK
, PPC
, { RT
, RA
, RB
} },
2792 { "ldx", X(31,21), X_MASK
, PPC64
, { RT
, RA
, RB
} },
2794 { "icbt", X(31,22), X_MASK
, BOOKE
, { CT
, RA
, RB
} },
2796 { "lwzx", X(31,23), X_MASK
, PPCCOM
, { RT
, RA
, RB
} },
2797 { "lx", X(31,23), X_MASK
, PWRCOM
, { RT
, RA
, RB
} },
2799 { "slw", XRC(31,24,0), X_MASK
, PPCCOM
, { RA
, RS
, RB
} },
2800 { "sl", XRC(31,24,0), X_MASK
, PWRCOM
, { RA
, RS
, RB
} },
2801 { "slw.", XRC(31,24,1), X_MASK
, PPCCOM
, { RA
, RS
, RB
} },
2802 { "sl.", XRC(31,24,1), X_MASK
, PWRCOM
, { RA
, RS
, RB
} },
2804 { "cntlzw", XRC(31,26,0), XRB_MASK
, PPCCOM
, { RA
, RS
} },
2805 { "cntlz", XRC(31,26,0), XRB_MASK
, PWRCOM
, { RA
, RS
} },
2806 { "cntlzw.", XRC(31,26,1), XRB_MASK
, PPCCOM
, { RA
, RS
} },
2807 { "cntlz.", XRC(31,26,1), XRB_MASK
, PWRCOM
, { RA
, RS
} },
2809 { "sld", XRC(31,27,0), X_MASK
, PPC64
, { RA
, RS
, RB
} },
2810 { "sld.", XRC(31,27,1), X_MASK
, PPC64
, { RA
, RS
, RB
} },
2812 { "and", XRC(31,28,0), X_MASK
, COM
, { RA
, RS
, RB
} },
2813 { "and.", XRC(31,28,1), X_MASK
, COM
, { RA
, RS
, RB
} },
2815 { "maskg", XRC(31,29,0), X_MASK
, M601
, { RA
, RS
, RB
} },
2816 { "maskg.", XRC(31,29,1), X_MASK
, M601
, { RA
, RS
, RB
} },
2818 { "icbte", X(31,30), X_MASK
, BOOKE64
, { CT
, RA
, RB
} },
2820 { "lwzxe", X(31,31), X_MASK
, BOOKE64
, { RT
, RA
, RB
} },
2822 { "cmplw", XCMPL(31,32,0), XCMPL_MASK
, PPCCOM
, { OBF
, RA
, RB
} },
2823 { "cmpld", XCMPL(31,32,1), XCMPL_MASK
, PPC64
, { OBF
, RA
, RB
} },
2824 { "cmpl", X(31,32), XCMP_MASK
, PPCONLY
, { BF
, L
, RA
, RB
} },
2825 { "cmpl", X(31,32), XCMPL_MASK
, PWRCOM
, { BF
, RA
, RB
} },
2827 { "subf", XO(31,40,0,0), XO_MASK
, PPC
, { RT
, RA
, RB
} },
2828 { "sub", XO(31,40,0,0), XO_MASK
, PPC
, { RT
, RB
, RA
} },
2829 { "subf.", XO(31,40,0,1), XO_MASK
, PPC
, { RT
, RA
, RB
} },
2830 { "sub.", XO(31,40,0,1), XO_MASK
, PPC
, { RT
, RB
, RA
} },
2831 { "subfo", XO(31,40,1,0), XO_MASK
, PPC
, { RT
, RA
, RB
} },
2832 { "subo", XO(31,40,1,0), XO_MASK
, PPC
, { RT
, RB
, RA
} },
2833 { "subfo.", XO(31,40,1,1), XO_MASK
, PPC
, { RT
, RA
, RB
} },
2834 { "subo.", XO(31,40,1,1), XO_MASK
, PPC
, { RT
, RB
, RA
} },
2836 { "ldux", X(31,53), X_MASK
, PPC64
, { RT
, RAL
, RB
} },
2838 { "dcbst", X(31,54), XRT_MASK
, PPC
, { RA
, RB
} },
2840 { "lwzux", X(31,55), X_MASK
, PPCCOM
, { RT
, RAL
, RB
} },
2841 { "lux", X(31,55), X_MASK
, PWRCOM
, { RT
, RA
, RB
} },
2843 { "dcbste", X(31,62), XRT_MASK
, BOOKE64
, { RA
, RB
} },
2845 { "lwzuxe", X(31,63), X_MASK
, BOOKE64
, { RT
, RAL
, RB
} },
2847 { "cntlzd", XRC(31,58,0), XRB_MASK
, PPC64
, { RA
, RS
} },
2848 { "cntlzd.", XRC(31,58,1), XRB_MASK
, PPC64
, { RA
, RS
} },
2850 { "andc", XRC(31,60,0), X_MASK
, COM
, { RA
, RS
, RB
} },
2851 { "andc.", XRC(31,60,1), X_MASK
, COM
, { RA
, RS
, RB
} },
2853 { "tdlgt", XTO(31,68,TOLGT
), XTO_MASK
, PPC64
, { RA
, RB
} },
2854 { "tdllt", XTO(31,68,TOLLT
), XTO_MASK
, PPC64
, { RA
, RB
} },
2855 { "tdeq", XTO(31,68,TOEQ
), XTO_MASK
, PPC64
, { RA
, RB
} },
2856 { "tdlge", XTO(31,68,TOLGE
), XTO_MASK
, PPC64
, { RA
, RB
} },
2857 { "tdlnl", XTO(31,68,TOLNL
), XTO_MASK
, PPC64
, { RA
, RB
} },
2858 { "tdlle", XTO(31,68,TOLLE
), XTO_MASK
, PPC64
, { RA
, RB
} },
2859 { "tdlng", XTO(31,68,TOLNG
), XTO_MASK
, PPC64
, { RA
, RB
} },
2860 { "tdgt", XTO(31,68,TOGT
), XTO_MASK
, PPC64
, { RA
, RB
} },
2861 { "tdge", XTO(31,68,TOGE
), XTO_MASK
, PPC64
, { RA
, RB
} },
2862 { "tdnl", XTO(31,68,TONL
), XTO_MASK
, PPC64
, { RA
, RB
} },
2863 { "tdlt", XTO(31,68,TOLT
), XTO_MASK
, PPC64
, { RA
, RB
} },
2864 { "tdle", XTO(31,68,TOLE
), XTO_MASK
, PPC64
, { RA
, RB
} },
2865 { "tdng", XTO(31,68,TONG
), XTO_MASK
, PPC64
, { RA
, RB
} },
2866 { "tdne", XTO(31,68,TONE
), XTO_MASK
, PPC64
, { RA
, RB
} },
2867 { "td", X(31,68), X_MASK
, PPC64
, { TO
, RA
, RB
} },
2869 { "mulhd", XO(31,73,0,0), XO_MASK
, PPC64
, { RT
, RA
, RB
} },
2870 { "mulhd.", XO(31,73,0,1), XO_MASK
, PPC64
, { RT
, RA
, RB
} },
2872 { "mulhw", XO(31,75,0,0), XO_MASK
, PPC
, { RT
, RA
, RB
} },
2873 { "mulhw.", XO(31,75,0,1), XO_MASK
, PPC
, { RT
, RA
, RB
} },
2875 { "mtsrd", X(31,82), XRB_MASK
|(1<<20), PPC64
, { SR
, RS
} },
2877 { "mfmsr", X(31,83), XRARB_MASK
, COM
, { RT
} },
2879 { "ldarx", X(31,84), X_MASK
, PPC64
, { RT
, RA
, RB
} },
2881 { "dcbf", X(31,86), XRT_MASK
, PPC
, { RA
, RB
} },
2883 { "lbzx", X(31,87), X_MASK
, COM
, { RT
, RA
, RB
} },
2885 { "dcbfe", X(31,94), XRT_MASK
, BOOKE64
, { RA
, RB
} },
2887 { "lbzxe", X(31,95), X_MASK
, BOOKE64
, { RT
, RA
, RB
} },
2889 { "neg", XO(31,104,0,0), XORB_MASK
, COM
, { RT
, RA
} },
2890 { "neg.", XO(31,104,0,1), XORB_MASK
, COM
, { RT
, RA
} },
2891 { "nego", XO(31,104,1,0), XORB_MASK
, COM
, { RT
, RA
} },
2892 { "nego.", XO(31,104,1,1), XORB_MASK
, COM
, { RT
, RA
} },
2894 { "mul", XO(31,107,0,0), XO_MASK
, M601
, { RT
, RA
, RB
} },
2895 { "mul.", XO(31,107,0,1), XO_MASK
, M601
, { RT
, RA
, RB
} },
2896 { "mulo", XO(31,107,1,0), XO_MASK
, M601
, { RT
, RA
, RB
} },
2897 { "mulo.", XO(31,107,1,1), XO_MASK
, M601
, { RT
, RA
, RB
} },
2899 { "mtsrdin", X(31,114), XRA_MASK
, PPC64
, { RS
, RB
} },
2901 { "clf", X(31,118), XTO_MASK
, POWER
, { RA
, RB
} },
2903 { "lbzux", X(31,119), X_MASK
, COM
, { RT
, RAL
, RB
} },
2905 { "not", XRC(31,124,0), X_MASK
, COM
, { RA
, RS
, RBS
} },
2906 { "nor", XRC(31,124,0), X_MASK
, COM
, { RA
, RS
, RB
} },
2907 { "not.", XRC(31,124,1), X_MASK
, COM
, { RA
, RS
, RBS
} },
2908 { "nor.", XRC(31,124,1), X_MASK
, COM
, { RA
, RS
, RB
} },
2910 { "lwarxe", X(31,126), X_MASK
, BOOKE64
, { RT
, RA
, RB
} },
2912 { "lbzuxe", X(31,127), X_MASK
, BOOKE64
, { RT
, RAL
, RB
} },
2914 { "wrtee", X(31,131), XRARB_MASK
, PPC403
, { RS
} },
2915 { "wrtee", X(31,131), XRARB_MASK
, BOOKE
, { RS
} },
2917 { "subfe", XO(31,136,0,0), XO_MASK
, PPCCOM
, { RT
, RA
, RB
} },
2918 { "sfe", XO(31,136,0,0), XO_MASK
, PWRCOM
, { RT
, RA
, RB
} },
2919 { "subfe.", XO(31,136,0,1), XO_MASK
, PPCCOM
, { RT
, RA
, RB
} },
2920 { "sfe.", XO(31,136,0,1), XO_MASK
, PWRCOM
, { RT
, RA
, RB
} },
2921 { "subfeo", XO(31,136,1,0), XO_MASK
, PPCCOM
, { RT
, RA
, RB
} },
2922 { "sfeo", XO(31,136,1,0), XO_MASK
, PWRCOM
, { RT
, RA
, RB
} },
2923 { "subfeo.", XO(31,136,1,1), XO_MASK
, PPCCOM
, { RT
, RA
, RB
} },
2924 { "sfeo.", XO(31,136,1,1), XO_MASK
, PWRCOM
, { RT
, RA
, RB
} },
2926 { "adde", XO(31,138,0,0), XO_MASK
, PPCCOM
, { RT
, RA
, RB
} },
2927 { "ae", XO(31,138,0,0), XO_MASK
, PWRCOM
, { RT
, RA
, RB
} },
2928 { "adde.", XO(31,138,0,1), XO_MASK
, PPCCOM
, { RT
, RA
, RB
} },
2929 { "ae.", XO(31,138,0,1), XO_MASK
, PWRCOM
, { RT
, RA
, RB
} },
2930 { "addeo", XO(31,138,1,0), XO_MASK
, PPCCOM
, { RT
, RA
, RB
} },
2931 { "aeo", XO(31,138,1,0), XO_MASK
, PWRCOM
, { RT
, RA
, RB
} },
2932 { "addeo.", XO(31,138,1,1), XO_MASK
, PPCCOM
, { RT
, RA
, RB
} },
2933 { "aeo.", XO(31,138,1,1), XO_MASK
, PWRCOM
, { RT
, RA
, RB
} },
2935 { "mtcr", XFXM(31,144,0xff), XFXFXM_MASK
|FXM_MASK
, COM
, { RS
}},
2936 { "mtcrf", X(31,144), XFXFXM_MASK
, COM
, { FXM
, RS
} },
2938 { "mtmsr", X(31,146), XRARB_MASK
, COM
, { RS
} },
2940 { "stdx", X(31,149), X_MASK
, PPC64
, { RS
, RA
, RB
} },
2942 { "stwcx.", XRC(31,150,1), X_MASK
, PPC
, { RS
, RA
, RB
} },
2944 { "stwx", X(31,151), X_MASK
, PPCCOM
, { RS
, RA
, RB
} },
2945 { "stx", X(31,151), X_MASK
, PWRCOM
, { RS
, RA
, RB
} },
2947 { "stwcxe.", XRC(31,158,1), X_MASK
, BOOKE64
, { RS
, RA
, RB
} },
2949 { "stwxe", X(31,159), X_MASK
, BOOKE64
, { RS
, RA
, RB
} },
2951 { "slq", XRC(31,152,0), X_MASK
, M601
, { RA
, RS
, RB
} },
2952 { "slq.", XRC(31,152,1), X_MASK
, M601
, { RA
, RS
, RB
} },
2954 { "sle", XRC(31,153,0), X_MASK
, M601
, { RA
, RS
, RB
} },
2955 { "sle.", XRC(31,153,1), X_MASK
, M601
, { RA
, RS
, RB
} },
2957 { "wrteei", X(31,163), XE_MASK
, PPC403
, { E
} },
2958 { "wrteei", X(31,163), XE_MASK
, BOOKE
, { E
} },
2960 { "mtmsrd", X(31,178), XRLARB_MASK
, PPC64
, { RS
, MTMSRD_L
} },
2962 { "stdux", X(31,181), X_MASK
, PPC64
, { RS
, RAS
, RB
} },
2964 { "stwux", X(31,183), X_MASK
, PPCCOM
, { RS
, RAS
, RB
} },
2965 { "stux", X(31,183), X_MASK
, PWRCOM
, { RS
, RA
, RB
} },
2967 { "sliq", XRC(31,184,0), X_MASK
, M601
, { RA
, RS
, SH
} },
2968 { "sliq.", XRC(31,184,1), X_MASK
, M601
, { RA
, RS
, SH
} },
2970 { "stwuxe", X(31,191), X_MASK
, BOOKE64
, { RS
, RAS
, RB
} },
2972 { "subfze", XO(31,200,0,0), XORB_MASK
, PPCCOM
, { RT
, RA
} },
2973 { "sfze", XO(31,200,0,0), XORB_MASK
, PWRCOM
, { RT
, RA
} },
2974 { "subfze.", XO(31,200,0,1), XORB_MASK
, PPCCOM
, { RT
, RA
} },
2975 { "sfze.", XO(31,200,0,1), XORB_MASK
, PWRCOM
, { RT
, RA
} },
2976 { "subfzeo", XO(31,200,1,0), XORB_MASK
, PPCCOM
, { RT
, RA
} },
2977 { "sfzeo", XO(31,200,1,0), XORB_MASK
, PWRCOM
, { RT
, RA
} },
2978 { "subfzeo.",XO(31,200,1,1), XORB_MASK
, PPCCOM
, { RT
, RA
} },
2979 { "sfzeo.", XO(31,200,1,1), XORB_MASK
, PWRCOM
, { RT
, RA
} },
2981 { "addze", XO(31,202,0,0), XORB_MASK
, PPCCOM
, { RT
, RA
} },
2982 { "aze", XO(31,202,0,0), XORB_MASK
, PWRCOM
, { RT
, RA
} },
2983 { "addze.", XO(31,202,0,1), XORB_MASK
, PPCCOM
, { RT
, RA
} },
2984 { "aze.", XO(31,202,0,1), XORB_MASK
, PWRCOM
, { RT
, RA
} },
2985 { "addzeo", XO(31,202,1,0), XORB_MASK
, PPCCOM
, { RT
, RA
} },
2986 { "azeo", XO(31,202,1,0), XORB_MASK
, PWRCOM
, { RT
, RA
} },
2987 { "addzeo.", XO(31,202,1,1), XORB_MASK
, PPCCOM
, { RT
, RA
} },
2988 { "azeo.", XO(31,202,1,1), XORB_MASK
, PWRCOM
, { RT
, RA
} },
2990 { "mtsr", X(31,210), XRB_MASK
|(1<<20), COM32
, { SR
, RS
} },
2992 { "stdcx.", XRC(31,214,1), X_MASK
, PPC64
, { RS
, RA
, RB
} },
2994 { "stbx", X(31,215), X_MASK
, COM
, { RS
, RA
, RB
} },
2996 { "sllq", XRC(31,216,0), X_MASK
, M601
, { RA
, RS
, RB
} },
2997 { "sllq.", XRC(31,216,1), X_MASK
, M601
, { RA
, RS
, RB
} },
2999 { "sleq", XRC(31,217,0), X_MASK
, M601
, { RA
, RS
, RB
} },
3000 { "sleq.", XRC(31,217,1), X_MASK
, M601
, { RA
, RS
, RB
} },
3002 { "stbxe", X(31,223), X_MASK
, BOOKE64
, { RS
, RA
, RB
} },
3004 { "subfme", XO(31,232,0,0), XORB_MASK
, PPCCOM
, { RT
, RA
} },
3005 { "sfme", XO(31,232,0,0), XORB_MASK
, PWRCOM
, { RT
, RA
} },
3006 { "subfme.", XO(31,232,0,1), XORB_MASK
, PPCCOM
, { RT
, RA
} },
3007 { "sfme.", XO(31,232,0,1), XORB_MASK
, PWRCOM
, { RT
, RA
} },
3008 { "subfmeo", XO(31,232,1,0), XORB_MASK
, PPCCOM
, { RT
, RA
} },
3009 { "sfmeo", XO(31,232,1,0), XORB_MASK
, PWRCOM
, { RT
, RA
} },
3010 { "subfmeo.",XO(31,232,1,1), XORB_MASK
, PPCCOM
, { RT
, RA
} },
3011 { "sfmeo.", XO(31,232,1,1), XORB_MASK
, PWRCOM
, { RT
, RA
} },
3013 { "mulld", XO(31,233,0,0), XO_MASK
, PPC64
, { RT
, RA
, RB
} },
3014 { "mulld.", XO(31,233,0,1), XO_MASK
, PPC64
, { RT
, RA
, RB
} },
3015 { "mulldo", XO(31,233,1,0), XO_MASK
, PPC64
, { RT
, RA
, RB
} },
3016 { "mulldo.", XO(31,233,1,1), XO_MASK
, PPC64
, { RT
, RA
, RB
} },
3018 { "addme", XO(31,234,0,0), XORB_MASK
, PPCCOM
, { RT
, RA
} },
3019 { "ame", XO(31,234,0,0), XORB_MASK
, PWRCOM
, { RT
, RA
} },
3020 { "addme.", XO(31,234,0,1), XORB_MASK
, PPCCOM
, { RT
, RA
} },
3021 { "ame.", XO(31,234,0,1), XORB_MASK
, PWRCOM
, { RT
, RA
} },
3022 { "addmeo", XO(31,234,1,0), XORB_MASK
, PPCCOM
, { RT
, RA
} },
3023 { "ameo", XO(31,234,1,0), XORB_MASK
, PWRCOM
, { RT
, RA
} },
3024 { "addmeo.", XO(31,234,1,1), XORB_MASK
, PPCCOM
, { RT
, RA
} },
3025 { "ameo.", XO(31,234,1,1), XORB_MASK
, PWRCOM
, { RT
, RA
} },
3027 { "mullw", XO(31,235,0,0), XO_MASK
, PPCCOM
, { RT
, RA
, RB
} },
3028 { "muls", XO(31,235,0,0), XO_MASK
, PWRCOM
, { RT
, RA
, RB
} },
3029 { "mullw.", XO(31,235,0,1), XO_MASK
, PPCCOM
, { RT
, RA
, RB
} },
3030 { "muls.", XO(31,235,0,1), XO_MASK
, PWRCOM
, { RT
, RA
, RB
} },
3031 { "mullwo", XO(31,235,1,0), XO_MASK
, PPCCOM
, { RT
, RA
, RB
} },
3032 { "mulso", XO(31,235,1,0), XO_MASK
, PWRCOM
, { RT
, RA
, RB
} },
3033 { "mullwo.", XO(31,235,1,1), XO_MASK
, PPCCOM
, { RT
, RA
, RB
} },
3034 { "mulso.", XO(31,235,1,1), XO_MASK
, PWRCOM
, { RT
, RA
, RB
} },
3036 { "mtsrin", X(31,242), XRA_MASK
, PPC32
, { RS
, RB
} },
3037 { "mtsri", X(31,242), XRA_MASK
, POWER32
, { RS
, RB
} },
3039 { "dcbtst", X(31,246), XRT_MASK
, PPC
, { CT
, RA
, RB
} },
3041 { "stbux", X(31,247), X_MASK
, COM
, { RS
, RAS
, RB
} },
3043 { "slliq", XRC(31,248,0), X_MASK
, M601
, { RA
, RS
, SH
} },
3044 { "slliq.", XRC(31,248,1), X_MASK
, M601
, { RA
, RS
, SH
} },
3046 { "dcbtste", X(31,253), X_MASK
, BOOKE64
, { CT
, RA
, RB
} },
3048 { "stbuxe", X(31,255), X_MASK
, BOOKE64
, { RS
, RAS
, RB
} },
3050 { "mfdcrx", X(31,259), X_MASK
, BOOKE
, { RS
, RA
} },
3052 { "icbt", X(31,262), XRT_MASK
, PPC403
, { RA
, RB
} },
3054 { "doz", XO(31,264,0,0), XO_MASK
, M601
, { RT
, RA
, RB
} },
3055 { "doz.", XO(31,264,0,1), XO_MASK
, M601
, { RT
, RA
, RB
} },
3056 { "dozo", XO(31,264,1,0), XO_MASK
, M601
, { RT
, RA
, RB
} },
3057 { "dozo.", XO(31,264,1,1), XO_MASK
, M601
, { RT
, RA
, RB
} },
3059 { "add", XO(31,266,0,0), XO_MASK
, PPCCOM
, { RT
, RA
, RB
} },
3060 { "cax", XO(31,266,0,0), XO_MASK
, PWRCOM
, { RT
, RA
, RB
} },
3061 { "add.", XO(31,266,0,1), XO_MASK
, PPCCOM
, { RT
, RA
, RB
} },
3062 { "cax.", XO(31,266,0,1), XO_MASK
, PWRCOM
, { RT
, RA
, RB
} },
3063 { "addo", XO(31,266,1,0), XO_MASK
, PPCCOM
, { RT
, RA
, RB
} },
3064 { "caxo", XO(31,266,1,0), XO_MASK
, PWRCOM
, { RT
, RA
, RB
} },
3065 { "addo.", XO(31,266,1,1), XO_MASK
, PPCCOM
, { RT
, RA
, RB
} },
3066 { "caxo.", XO(31,266,1,1), XO_MASK
, PWRCOM
, { RT
, RA
, RB
} },
3068 { "mfapidi", X(31,275), X_MASK
, BOOKE
, { RT
, RA
} },
3070 { "lscbx", XRC(31,277,0), X_MASK
, M601
, { RT
, RA
, RB
} },
3071 { "lscbx.", XRC(31,277,1), X_MASK
, M601
, { RT
, RA
, RB
} },
3073 { "dcbt", X(31,278), XRT_MASK
, PPC
, { CT
, RA
, RB
} },
3075 { "lhzx", X(31,279), X_MASK
, COM
, { RT
, RA
, RB
} },
3077 { "eqv", XRC(31,284,0), X_MASK
, COM
, { RA
, RS
, RB
} },
3078 { "eqv.", XRC(31,284,1), X_MASK
, COM
, { RA
, RS
, RB
} },
3080 { "dcbte", X(31,286), X_MASK
, BOOKE64
, { CT
, RA
, RB
} },
3082 { "lhzxe", X(31,287), X_MASK
, BOOKE64
, { RT
, RA
, RB
} },
3084 { "tlbie", X(31,306), XRTLRA_MASK
, PPC
, { RB
, L
} },
3085 { "tlbi", X(31,306), XRT_MASK
, POWER
, { RA
, RB
} },
3087 { "eciwx", X(31,310), X_MASK
, PPC
, { RT
, RA
, RB
} },
3089 { "lhzux", X(31,311), X_MASK
, COM
, { RT
, RAL
, RB
} },
3091 { "xor", XRC(31,316,0), X_MASK
, COM
, { RA
, RS
, RB
} },
3092 { "xor.", XRC(31,316,1), X_MASK
, COM
, { RA
, RS
, RB
} },
3094 { "lhzuxe", X(31,319), X_MASK
, BOOKE64
, { RT
, RAL
, RB
} },
3096 { "mfexisr", XSPR(31,323,64), XSPR_MASK
, PPC403
, { RT
} },
3097 { "mfexier", XSPR(31,323,66), XSPR_MASK
, PPC403
, { RT
} },
3098 { "mfbr0", XSPR(31,323,128), XSPR_MASK
, PPC403
, { RT
} },
3099 { "mfbr1", XSPR(31,323,129), XSPR_MASK
, PPC403
, { RT
} },
3100 { "mfbr2", XSPR(31,323,130), XSPR_MASK
, PPC403
, { RT
} },
3101 { "mfbr3", XSPR(31,323,131), XSPR_MASK
, PPC403
, { RT
} },
3102 { "mfbr4", XSPR(31,323,132), XSPR_MASK
, PPC403
, { RT
} },
3103 { "mfbr5", XSPR(31,323,133), XSPR_MASK
, PPC403
, { RT
} },
3104 { "mfbr6", XSPR(31,323,134), XSPR_MASK
, PPC403
, { RT
} },
3105 { "mfbr7", XSPR(31,323,135), XSPR_MASK
, PPC403
, { RT
} },
3106 { "mfbear", XSPR(31,323,144), XSPR_MASK
, PPC403
, { RT
} },
3107 { "mfbesr", XSPR(31,323,145), XSPR_MASK
, PPC403
, { RT
} },
3108 { "mfiocr", XSPR(31,323,160), XSPR_MASK
, PPC403
, { RT
} },
3109 { "mfdmacr0", XSPR(31,323,192), XSPR_MASK
, PPC403
, { RT
} },
3110 { "mfdmact0", XSPR(31,323,193), XSPR_MASK
, PPC403
, { RT
} },
3111 { "mfdmada0", XSPR(31,323,194), XSPR_MASK
, PPC403
, { RT
} },
3112 { "mfdmasa0", XSPR(31,323,195), XSPR_MASK
, PPC403
, { RT
} },
3113 { "mfdmacc0", XSPR(31,323,196), XSPR_MASK
, PPC403
, { RT
} },
3114 { "mfdmacr1", XSPR(31,323,200), XSPR_MASK
, PPC403
, { RT
} },
3115 { "mfdmact1", XSPR(31,323,201), XSPR_MASK
, PPC403
, { RT
} },
3116 { "mfdmada1", XSPR(31,323,202), XSPR_MASK
, PPC403
, { RT
} },
3117 { "mfdmasa1", XSPR(31,323,203), XSPR_MASK
, PPC403
, { RT
} },
3118 { "mfdmacc1", XSPR(31,323,204), XSPR_MASK
, PPC403
, { RT
} },
3119 { "mfdmacr2", XSPR(31,323,208), XSPR_MASK
, PPC403
, { RT
} },
3120 { "mfdmact2", XSPR(31,323,209), XSPR_MASK
, PPC403
, { RT
} },
3121 { "mfdmada2", XSPR(31,323,210), XSPR_MASK
, PPC403
, { RT
} },
3122 { "mfdmasa2", XSPR(31,323,211), XSPR_MASK
, PPC403
, { RT
} },
3123 { "mfdmacc2", XSPR(31,323,212), XSPR_MASK
, PPC403
, { RT
} },
3124 { "mfdmacr3", XSPR(31,323,216), XSPR_MASK
, PPC403
, { RT
} },
3125 { "mfdmact3", XSPR(31,323,217), XSPR_MASK
, PPC403
, { RT
} },
3126 { "mfdmada3", XSPR(31,323,218), XSPR_MASK
, PPC403
, { RT
} },
3127 { "mfdmasa3", XSPR(31,323,219), XSPR_MASK
, PPC403
, { RT
} },
3128 { "mfdmacc3", XSPR(31,323,220), XSPR_MASK
, PPC403
, { RT
} },
3129 { "mfdmasr", XSPR(31,323,224), XSPR_MASK
, PPC403
, { RT
} },
3130 { "mfdcr", X(31,323), X_MASK
, PPC403
, { RT
, SPR
} },
3131 { "mfdcr", X(31,323), X_MASK
, BOOKE
, { RT
, SPR
} },
3133 { "div", XO(31,331,0,0), XO_MASK
, M601
, { RT
, RA
, RB
} },
3134 { "div.", XO(31,331,0,1), XO_MASK
, M601
, { RT
, RA
, RB
} },
3135 { "divo", XO(31,331,1,0), XO_MASK
, M601
, { RT
, RA
, RB
} },
3136 { "divo.", XO(31,331,1,1), XO_MASK
, M601
, { RT
, RA
, RB
} },
3138 { "mfmq", XSPR(31,339,0), XSPR_MASK
, M601
, { RT
} },
3139 { "mfxer", XSPR(31,339,1), XSPR_MASK
, COM
, { RT
} },
3140 { "mfrtcu", XSPR(31,339,4), XSPR_MASK
, COM
, { RT
} },
3141 { "mfrtcl", XSPR(31,339,5), XSPR_MASK
, COM
, { RT
} },
3142 { "mfdec", XSPR(31,339,6), XSPR_MASK
, MFDEC1
, { RT
} },
3143 { "mflr", XSPR(31,339,8), XSPR_MASK
, COM
, { RT
} },
3144 { "mfctr", XSPR(31,339,9), XSPR_MASK
, COM
, { RT
} },
3145 { "mftid", XSPR(31,339,17), XSPR_MASK
, POWER
, { RT
} },
3146 { "mfdsisr", XSPR(31,339,18), XSPR_MASK
, COM
, { RT
} },
3147 { "mfdar", XSPR(31,339,19), XSPR_MASK
, COM
, { RT
} },
3148 { "mfdec", XSPR(31,339,22), XSPR_MASK
, MFDEC2
, { RT
} },
3149 { "mfsdr0", XSPR(31,339,24), XSPR_MASK
, POWER
, { RT
} },
3150 { "mfsdr1", XSPR(31,339,25), XSPR_MASK
, COM
, { RT
} },
3151 { "mfsrr0", XSPR(31,339,26), XSPR_MASK
, COM
, { RT
} },
3152 { "mfsrr1", XSPR(31,339,27), XSPR_MASK
, COM
, { RT
} },
3153 { "mfcmpa", XSPR(31,339,144), XSPR_MASK
, PPC860
, { RT
} },
3154 { "mfcmpb", XSPR(31,339,145), XSPR_MASK
, PPC860
, { RT
} },
3155 { "mfcmpc", XSPR(31,339,146), XSPR_MASK
, PPC860
, { RT
} },
3156 { "mfcmpd", XSPR(31,339,147), XSPR_MASK
, PPC860
, { RT
} },
3157 { "mficr", XSPR(31,339,148), XSPR_MASK
, PPC860
, { RT
} },
3158 { "mfder", XSPR(31,339,149), XSPR_MASK
, PPC860
, { RT
} },
3159 { "mfcounta", XSPR(31,339,150), XSPR_MASK
, PPC860
, { RT
} },
3160 { "mfcountb", XSPR(31,339,151), XSPR_MASK
, PPC860
, { RT
} },
3161 { "mfcmpe", XSPR(31,339,152), XSPR_MASK
, PPC860
, { RT
} },
3162 { "mfcmpf", XSPR(31,339,153), XSPR_MASK
, PPC860
, { RT
} },
3163 { "mfcmpg", XSPR(31,339,154), XSPR_MASK
, PPC860
, { RT
} },
3164 { "mfcmph", XSPR(31,339,155), XSPR_MASK
, PPC860
, { RT
} },
3165 { "mflctrl1", XSPR(31,339,156), XSPR_MASK
, PPC860
, { RT
} },
3166 { "mflctrl2", XSPR(31,339,157), XSPR_MASK
, PPC860
, { RT
} },
3167 { "mfictrl", XSPR(31,339,158), XSPR_MASK
, PPC860
, { RT
} },
3168 { "mfbar", XSPR(31,339,159), XSPR_MASK
, PPC860
, { RT
} },
3169 { "mfvrsave", XSPR(31,339,256), XSPR_MASK
, PPCVEC
, { RT
} },
3170 { "mfsprg4", XSPR(31,339,260), XSPR_MASK
, PPC405
, { RT
} },
3171 { "mfsprg5", XSPR(31,339,261), XSPR_MASK
, PPC405
, { RT
} },
3172 { "mfsprg6", XSPR(31,339,262), XSPR_MASK
, PPC405
, { RT
} },
3173 { "mfsprg7", XSPR(31,339,263), XSPR_MASK
, PPC405
, { RT
} },
3174 { "mfsprg", XSPR(31,339,272), XSPRG_MASK
, PPC
, { RT
, SPRG
} },
3175 { "mfsprg0", XSPR(31,339,272), XSPR_MASK
, PPC
, { RT
} },
3176 { "mfsprg1", XSPR(31,339,273), XSPR_MASK
, PPC
, { RT
} },
3177 { "mfsprg2", XSPR(31,339,274), XSPR_MASK
, PPC
, { RT
} },
3178 { "mfsprg3", XSPR(31,339,275), XSPR_MASK
, PPC
, { RT
} },
3179 { "mfasr", XSPR(31,339,280), XSPR_MASK
, PPC64
, { RT
} },
3180 { "mfear", XSPR(31,339,282), XSPR_MASK
, PPC
, { RT
} },
3181 { "mfpvr", XSPR(31,339,287), XSPR_MASK
, PPC
, { RT
} },
3182 { "mfibatu", XSPR(31,339,528), XSPRBAT_MASK
, PPC
, { RT
, SPRBAT
} },
3183 { "mfibatl", XSPR(31,339,529), XSPRBAT_MASK
, PPC
, { RT
, SPRBAT
} },
3184 { "mfdbatu", XSPR(31,339,536), XSPRBAT_MASK
, PPC
, { RT
, SPRBAT
} },
3185 { "mfdbatl", XSPR(31,339,537), XSPRBAT_MASK
, PPC
, { RT
, SPRBAT
} },
3186 { "mfic_cst", XSPR(31,339,560), XSPR_MASK
, PPC860
, { RT
} },
3187 { "mfic_adr", XSPR(31,339,561), XSPR_MASK
, PPC860
, { RT
} },
3188 { "mfic_dat", XSPR(31,339,562), XSPR_MASK
, PPC860
, { RT
} },
3189 { "mfdc_cst", XSPR(31,339,568), XSPR_MASK
, PPC860
, { RT
} },
3190 { "mfdc_adr", XSPR(31,339,569), XSPR_MASK
, PPC860
, { RT
} },
3191 { "mfdc_dat", XSPR(31,339,570), XSPR_MASK
, PPC860
, { RT
} },
3192 { "mfdpdr", XSPR(31,339,630), XSPR_MASK
, PPC860
, { RT
} },
3193 { "mfdpir", XSPR(31,339,631), XSPR_MASK
, PPC860
, { RT
} },
3194 { "mfimmr", XSPR(31,339,638), XSPR_MASK
, PPC860
, { RT
} },
3195 { "mfmi_ctr", XSPR(31,339,784), XSPR_MASK
, PPC860
, { RT
} },
3196 { "mfmi_ap", XSPR(31,339,786), XSPR_MASK
, PPC860
, { RT
} },
3197 { "mfmi_epn", XSPR(31,339,787), XSPR_MASK
, PPC860
, { RT
} },
3198 { "mfmi_twc", XSPR(31,339,789), XSPR_MASK
, PPC860
, { RT
} },
3199 { "mfmi_rpn", XSPR(31,339,790), XSPR_MASK
, PPC860
, { RT
} },
3200 { "mfmd_ctr", XSPR(31,339,792), XSPR_MASK
, PPC860
, { RT
} },
3201 { "mfm_casid",XSPR(31,339,793), XSPR_MASK
, PPC860
, { RT
} },
3202 { "mfmd_ap", XSPR(31,339,794), XSPR_MASK
, PPC860
, { RT
} },
3203 { "mfmd_epn", XSPR(31,339,795), XSPR_MASK
, PPC860
, { RT
} },
3204 { "mfmd_twb", XSPR(31,339,796), XSPR_MASK
, PPC860
, { RT
} },
3205 { "mfmd_twc", XSPR(31,339,797), XSPR_MASK
, PPC860
, { RT
} },
3206 { "mfmd_rpn", XSPR(31,339,798), XSPR_MASK
, PPC860
, { RT
} },
3207 { "mfm_tw", XSPR(31,339,799), XSPR_MASK
, PPC860
, { RT
} },
3208 { "mfmi_dbcam",XSPR(31,339,816), XSPR_MASK
, PPC860
, { RT
} },
3209 { "mfmi_dbram0",XSPR(31,339,817), XSPR_MASK
, PPC860
, { RT
} },
3210 { "mfmi_dbram1",XSPR(31,339,818), XSPR_MASK
, PPC860
, { RT
} },
3211 { "mfmd_dbcam", XSPR(31,339,824), XSPR_MASK
, PPC860
, { RT
} },
3212 { "mfmd_dbram0",XSPR(31,339,825), XSPR_MASK
, PPC860
, { RT
} },
3213 { "mfmd_dbram1",XSPR(31,339,826), XSPR_MASK
, PPC860
, { RT
} },
3214 { "mfzpr", XSPR(31,339,944), XSPR_MASK
, PPC403
, { RT
} },
3215 { "mfpid", XSPR(31,339,945), XSPR_MASK
, PPC403
, { RT
} },
3216 { "mfccr0", XSPR(31,339,947), XSPR_MASK
, PPC405
, { RT
} },
3217 { "mficdbdr", XSPR(31,339,979), XSPR_MASK
, PPC403
, { RT
} },
3218 { "mfummcr0", XSPR(31,339,936), XSPR_MASK
, PPC750
, { RT
} },
3219 { "mfupmc1", XSPR(31,339,937), XSPR_MASK
, PPC750
, { RT
} },
3220 { "mfupmc2", XSPR(31,339,938), XSPR_MASK
, PPC750
, { RT
} },
3221 { "mfusia", XSPR(31,339,939), XSPR_MASK
, PPC750
, { RT
} },
3222 { "mfummcr1", XSPR(31,339,940), XSPR_MASK
, PPC750
, { RT
} },
3223 { "mfupmc3", XSPR(31,339,941), XSPR_MASK
, PPC750
, { RT
} },
3224 { "mfupmc4", XSPR(31,339,942), XSPR_MASK
, PPC750
, { RT
} },
3225 { "mfiac3", XSPR(31,339,948), XSPR_MASK
, PPC405
, { RT
} },
3226 { "mfiac4", XSPR(31,339,949), XSPR_MASK
, PPC405
, { RT
} },
3227 { "mfdvc1", XSPR(31,339,950), XSPR_MASK
, PPC405
, { RT
} },
3228 { "mfdvc2", XSPR(31,339,951), XSPR_MASK
, PPC405
, { RT
} },
3229 { "mfmmcr0", XSPR(31,339,952), XSPR_MASK
, PPC750
, { RT
} },
3230 { "mfpmc1", XSPR(31,339,953), XSPR_MASK
, PPC750
, { RT
} },
3231 { "mfsgr", XSPR(31,339,953), XSPR_MASK
, PPC403
, { RT
} },
3232 { "mfpmc2", XSPR(31,339,954), XSPR_MASK
, PPC750
, { RT
} },
3233 { "mfdcwr", XSPR(31,339,954), XSPR_MASK
, PPC403
, { RT
} },
3234 { "mfsia", XSPR(31,339,955), XSPR_MASK
, PPC750
, { RT
} },
3235 { "mfsler", XSPR(31,339,955), XSPR_MASK
, PPC405
, { RT
} },
3236 { "mfmmcr1", XSPR(31,339,956), XSPR_MASK
, PPC750
, { RT
} },
3237 { "mfsu0r", XSPR(31,339,956), XSPR_MASK
, PPC405
, { RT
} },
3238 { "mfpmc3", XSPR(31,339,957), XSPR_MASK
, PPC750
, { RT
} },
3239 { "mfdbcr1", XSPR(31,339,957), XSPR_MASK
, PPC405
, { RT
} },
3240 { "mfpmc4", XSPR(31,339,958), XSPR_MASK
, PPC750
, { RT
} },
3241 { "mfesr", XSPR(31,339,980), XSPR_MASK
, PPC403
, { RT
} },
3242 { "mfdear", XSPR(31,339,981), XSPR_MASK
, PPC403
, { RT
} },
3243 { "mfevpr", XSPR(31,339,982), XSPR_MASK
, PPC403
, { RT
} },
3244 { "mfcdbcr", XSPR(31,339,983), XSPR_MASK
, PPC403
, { RT
} },
3245 { "mftsr", XSPR(31,339,984), XSPR_MASK
, PPC403
, { RT
} },
3246 { "mftcr", XSPR(31,339,986), XSPR_MASK
, PPC403
, { RT
} },
3247 { "mfpit", XSPR(31,339,987), XSPR_MASK
, PPC403
, { RT
} },
3248 { "mftbhi", XSPR(31,339,988), XSPR_MASK
, PPC403
, { RT
} },
3249 { "mftblo", XSPR(31,339,989), XSPR_MASK
, PPC403
, { RT
} },
3250 { "mfsrr2", XSPR(31,339,990), XSPR_MASK
, PPC403
, { RT
} },
3251 { "mfsrr3", XSPR(31,339,991), XSPR_MASK
, PPC403
, { RT
} },
3252 { "mfdbsr", XSPR(31,339,1008), XSPR_MASK
, PPC403
, { RT
} },
3253 { "mfdbcr0", XSPR(31,339,1010), XSPR_MASK
, PPC405
, { RT
} },
3254 { "mfiac1", XSPR(31,339,1012), XSPR_MASK
, PPC403
, { RT
} },
3255 { "mfiac2", XSPR(31,339,1013), XSPR_MASK
, PPC403
, { RT
} },
3256 { "mfdac1", XSPR(31,339,1014), XSPR_MASK
, PPC403
, { RT
} },
3257 { "mfdac2", XSPR(31,339,1015), XSPR_MASK
, PPC403
, { RT
} },
3258 { "mfdccr", XSPR(31,339,1018), XSPR_MASK
, PPC403
, { RT
} },
3259 { "mficcr", XSPR(31,339,1019), XSPR_MASK
, PPC403
, { RT
} },
3260 { "mfpbl1", XSPR(31,339,1020), XSPR_MASK
, PPC403
, { RT
} },
3261 { "mfpbu1", XSPR(31,339,1021), XSPR_MASK
, PPC403
, { RT
} },
3262 { "mfpbl2", XSPR(31,339,1022), XSPR_MASK
, PPC403
, { RT
} },
3263 { "mfpbu2", XSPR(31,339,1023), XSPR_MASK
, PPC403
, { RT
} },
3264 { "mfl2cr", XSPR(31,339,1017), XSPR_MASK
, PPC750
, { RT
} },
3265 { "mfictc", XSPR(31,339,1019), XSPR_MASK
, PPC750
, { RT
} },
3266 { "mfthrm1", XSPR(31,339,1020), XSPR_MASK
, PPC750
, { RT
} },
3267 { "mfthrm2", XSPR(31,339,1021), XSPR_MASK
, PPC750
, { RT
} },
3268 { "mfthrm3", XSPR(31,339,1022), XSPR_MASK
, PPC750
, { RT
} },
3269 { "mfspr", X(31,339), X_MASK
, COM
, { RT
, SPR
} },
3271 { "lwax", X(31,341), X_MASK
, PPC64
, { RT
, RA
, RB
} },
3273 { "dst", XDSS(31,342,0), XDSS_MASK
, PPCVEC
, { RA
, RB
, STRM
} },
3274 { "dstt", XDSS(31,342,1), XDSS_MASK
, PPCVEC
, { RA
, RB
, STRM
} },
3276 { "lhax", X(31,343), X_MASK
, COM
, { RT
, RA
, RB
} },
3278 { "lhaxe", X(31,351), X_MASK
, BOOKE64
, { RT
, RA
, RB
} },
3280 { "dstst", XDSS(31,374,0), XDSS_MASK
, PPCVEC
, { RA
, RB
, STRM
} },
3281 { "dststt", XDSS(31,374,1), XDSS_MASK
, PPCVEC
, { RA
, RB
, STRM
} },
3283 { "dccci", X(31,454), XRT_MASK
, PPC403
, { RA
, RB
} },
3285 { "abs", XO(31,360,0,0), XORB_MASK
, M601
, { RT
, RA
} },
3286 { "abs.", XO(31,360,0,1), XORB_MASK
, M601
, { RT
, RA
} },
3287 { "abso", XO(31,360,1,0), XORB_MASK
, M601
, { RT
, RA
} },
3288 { "abso.", XO(31,360,1,1), XORB_MASK
, M601
, { RT
, RA
} },
3290 { "divs", XO(31,363,0,0), XO_MASK
, M601
, { RT
, RA
, RB
} },
3291 { "divs.", XO(31,363,0,1), XO_MASK
, M601
, { RT
, RA
, RB
} },
3292 { "divso", XO(31,363,1,0), XO_MASK
, M601
, { RT
, RA
, RB
} },
3293 { "divso.", XO(31,363,1,1), XO_MASK
, M601
, { RT
, RA
, RB
} },
3295 { "tlbia", X(31,370), 0xffffffff, PPC
, { 0 } },
3297 { "mftbl", XSPR(31,371,268), XSPR_MASK
, PPC
, { RT
} },
3298 { "mftbu", XSPR(31,371,269), XSPR_MASK
, PPC
, { RT
} },
3299 { "mftb", X(31,371), X_MASK
, PPC
, { RT
, TBR
} },
3301 { "lwaux", X(31,373), X_MASK
, PPC64
, { RT
, RAL
, RB
} },
3303 { "lhaux", X(31,375), X_MASK
, COM
, { RT
, RAL
, RB
} },
3305 { "lhauxe", X(31,383), X_MASK
, BOOKE64
, { RT
, RAL
, RB
} },
3307 { "mtdcrx", X(31,387), X_MASK
, BOOKE
, { RA
, RS
} },
3309 { "subfe64", XO(31,392,0,0), XO_MASK
, BOOKE64
, { RT
, RA
, RB
} },
3310 { "subfe64o",XO(31,392,1,0), XO_MASK
, BOOKE64
, { RT
, RA
, RB
} },
3312 { "adde64", XO(31,394,0,0), XO_MASK
, BOOKE64
, { RT
, RA
, RB
} },
3313 { "adde64o", XO(31,394,1,0), XO_MASK
, BOOKE64
, { RT
, RA
, RB
} },
3315 { "slbmte", X(31,402), XRA_MASK
, PPC64
, { RS
, RB
} },
3317 { "sthx", X(31,407), X_MASK
, COM
, { RS
, RA
, RB
} },
3319 { "lfqx", X(31,791), X_MASK
, POWER2
, { FRT
, RA
, RB
} },
3321 { "lfqux", X(31,823), X_MASK
, POWER2
, { FRT
, RA
, RB
} },
3323 { "stfqx", X(31,919), X_MASK
, POWER2
, { FRS
, RA
, RB
} },
3325 { "stfqux", X(31,951), X_MASK
, POWER2
, { FRS
, RA
, RB
} },
3327 { "orc", XRC(31,412,0), X_MASK
, COM
, { RA
, RS
, RB
} },
3328 { "orc.", XRC(31,412,1), X_MASK
, COM
, { RA
, RS
, RB
} },
3330 { "sradi", XS(31,413,0), XS_MASK
, PPC64
, { RA
, RS
, SH6
} },
3331 { "sradi.", XS(31,413,1), XS_MASK
, PPC64
, { RA
, RS
, SH6
} },
3333 { "sthxe", X(31,415), X_MASK
, BOOKE64
, { RS
, RA
, RB
} },
3335 { "slbie", X(31,434), XRTRA_MASK
, PPC64
, { RB
} },
3337 { "ecowx", X(31,438), X_MASK
, PPC
, { RT
, RA
, RB
} },
3339 { "sthux", X(31,439), X_MASK
, COM
, { RS
, RAS
, RB
} },
3341 { "sthuxe", X(31,447), X_MASK
, BOOKE64
, { RS
, RAS
, RB
} },
3343 { "mr", XRC(31,444,0), X_MASK
, COM
, { RA
, RS
, RBS
} },
3344 { "or", XRC(31,444,0), X_MASK
, COM
, { RA
, RS
, RB
} },
3345 { "mr.", XRC(31,444,1), X_MASK
, COM
, { RA
, RS
, RBS
} },
3346 { "or.", XRC(31,444,1), X_MASK
, COM
, { RA
, RS
, RB
} },
3348 { "mtexisr", XSPR(31,451,64), XSPR_MASK
, PPC403
, { RT
} },
3349 { "mtexier", XSPR(31,451,66), XSPR_MASK
, PPC403
, { RT
} },
3350 { "mtbr0", XSPR(31,451,128), XSPR_MASK
, PPC403
, { RT
} },
3351 { "mtbr1", XSPR(31,451,129), XSPR_MASK
, PPC403
, { RT
} },
3352 { "mtbr2", XSPR(31,451,130), XSPR_MASK
, PPC403
, { RT
} },
3353 { "mtbr3", XSPR(31,451,131), XSPR_MASK
, PPC403
, { RT
} },
3354 { "mtbr4", XSPR(31,451,132), XSPR_MASK
, PPC403
, { RT
} },
3355 { "mtbr5", XSPR(31,451,133), XSPR_MASK
, PPC403
, { RT
} },
3356 { "mtbr6", XSPR(31,451,134), XSPR_MASK
, PPC403
, { RT
} },
3357 { "mtbr7", XSPR(31,451,135), XSPR_MASK
, PPC403
, { RT
} },
3358 { "mtbear", XSPR(31,451,144), XSPR_MASK
, PPC403
, { RT
} },
3359 { "mtbesr", XSPR(31,451,145), XSPR_MASK
, PPC403
, { RT
} },
3360 { "mtiocr", XSPR(31,451,160), XSPR_MASK
, PPC403
, { RT
} },
3361 { "mtdmacr0", XSPR(31,451,192), XSPR_MASK
, PPC403
, { RT
} },
3362 { "mtdmact0", XSPR(31,451,193), XSPR_MASK
, PPC403
, { RT
} },
3363 { "mtdmada0", XSPR(31,451,194), XSPR_MASK
, PPC403
, { RT
} },
3364 { "mtdmasa0", XSPR(31,451,195), XSPR_MASK
, PPC403
, { RT
} },
3365 { "mtdmacc0", XSPR(31,451,196), XSPR_MASK
, PPC403
, { RT
} },
3366 { "mtdmacr1", XSPR(31,451,200), XSPR_MASK
, PPC403
, { RT
} },
3367 { "mtdmact1", XSPR(31,451,201), XSPR_MASK
, PPC403
, { RT
} },
3368 { "mtdmada1", XSPR(31,451,202), XSPR_MASK
, PPC403
, { RT
} },
3369 { "mtdmasa1", XSPR(31,451,203), XSPR_MASK
, PPC403
, { RT
} },
3370 { "mtdmacc1", XSPR(31,451,204), XSPR_MASK
, PPC403
, { RT
} },
3371 { "mtdmacr2", XSPR(31,451,208), XSPR_MASK
, PPC403
, { RT
} },
3372 { "mtdmact2", XSPR(31,451,209), XSPR_MASK
, PPC403
, { RT
} },
3373 { "mtdmada2", XSPR(31,451,210), XSPR_MASK
, PPC403
, { RT
} },
3374 { "mtdmasa2", XSPR(31,451,211), XSPR_MASK
, PPC403
, { RT
} },
3375 { "mtdmacc2", XSPR(31,451,212), XSPR_MASK
, PPC403
, { RT
} },
3376 { "mtdmacr3", XSPR(31,451,216), XSPR_MASK
, PPC403
, { RT
} },
3377 { "mtdmact3", XSPR(31,451,217), XSPR_MASK
, PPC403
, { RT
} },
3378 { "mtdmada3", XSPR(31,451,218), XSPR_MASK
, PPC403
, { RT
} },
3379 { "mtdmasa3", XSPR(31,451,219), XSPR_MASK
, PPC403
, { RT
} },
3380 { "mtdmacc3", XSPR(31,451,220), XSPR_MASK
, PPC403
, { RT
} },
3381 { "mtdmasr", XSPR(31,451,224), XSPR_MASK
, PPC403
, { RT
} },
3382 { "mtdcr", X(31,451), X_MASK
, PPC403
, { SPR
, RS
} },
3383 { "mtdcr", X(31,451), X_MASK
, BOOKE
, { SPR
, RS
} },
3385 { "subfze64",XO(31,456,0,0), XORB_MASK
, BOOKE64
, { RT
, RA
} },
3386 { "subfze64o",XO(31,456,1,0), XORB_MASK
, BOOKE64
, { RT
, RA
} },
3388 { "divdu", XO(31,457,0,0), XO_MASK
, PPC64
, { RT
, RA
, RB
} },
3389 { "divdu.", XO(31,457,0,1), XO_MASK
, PPC64
, { RT
, RA
, RB
} },
3390 { "divduo", XO(31,457,1,0), XO_MASK
, PPC64
, { RT
, RA
, RB
} },
3391 { "divduo.", XO(31,457,1,1), XO_MASK
, PPC64
, { RT
, RA
, RB
} },
3393 { "addze64", XO(31,458,0,0), XORB_MASK
, BOOKE64
, { RT
, RA
} },
3394 { "addze64o",XO(31,458,1,0), XORB_MASK
, BOOKE64
, { RT
, RA
} },
3396 { "divwu", XO(31,459,0,0), XO_MASK
, PPC
, { RT
, RA
, RB
} },
3397 { "divwu.", XO(31,459,0,1), XO_MASK
, PPC
, { RT
, RA
, RB
} },
3398 { "divwuo", XO(31,459,1,0), XO_MASK
, PPC
, { RT
, RA
, RB
} },
3399 { "divwuo.", XO(31,459,1,1), XO_MASK
, PPC
, { RT
, RA
, RB
} },
3401 { "mtmq", XSPR(31,467,0), XSPR_MASK
, M601
, { RS
} },
3402 { "mtxer", XSPR(31,467,1), XSPR_MASK
, COM
, { RS
} },
3403 { "mtlr", XSPR(31,467,8), XSPR_MASK
, COM
, { RS
} },
3404 { "mtctr", XSPR(31,467,9), XSPR_MASK
, COM
, { RS
} },
3405 { "mttid", XSPR(31,467,17), XSPR_MASK
, POWER
, { RS
} },
3406 { "mtdsisr", XSPR(31,467,18), XSPR_MASK
, COM
, { RS
} },
3407 { "mtdar", XSPR(31,467,19), XSPR_MASK
, COM
, { RS
} },
3408 { "mtrtcu", XSPR(31,467,20), XSPR_MASK
, COM
, { RS
} },
3409 { "mtrtcl", XSPR(31,467,21), XSPR_MASK
, COM
, { RS
} },
3410 { "mtdec", XSPR(31,467,22), XSPR_MASK
, COM
, { RS
} },
3411 { "mtsdr0", XSPR(31,467,24), XSPR_MASK
, POWER
, { RS
} },
3412 { "mtsdr1", XSPR(31,467,25), XSPR_MASK
, COM
, { RS
} },
3413 { "mtsrr0", XSPR(31,467,26), XSPR_MASK
, COM
, { RS
} },
3414 { "mtsrr1", XSPR(31,467,27), XSPR_MASK
, COM
, { RS
} },
3415 { "mtcmpa", XSPR(31,467,144), XSPR_MASK
, PPC860
, { RT
} },
3416 { "mtcmpb", XSPR(31,467,145), XSPR_MASK
, PPC860
, { RT
} },
3417 { "mtcmpc", XSPR(31,467,146), XSPR_MASK
, PPC860
, { RT
} },
3418 { "mtcmpd", XSPR(31,467,147), XSPR_MASK
, PPC860
, { RT
} },
3419 { "mticr", XSPR(31,467,148), XSPR_MASK
, PPC860
, { RT
} },
3420 { "mtder", XSPR(31,467,149), XSPR_MASK
, PPC860
, { RT
} },
3421 { "mtcounta", XSPR(31,467,150), XSPR_MASK
, PPC860
, { RT
} },
3422 { "mtcountb", XSPR(31,467,151), XSPR_MASK
, PPC860
, { RT
} },
3423 { "mtcmpe", XSPR(31,467,152), XSPR_MASK
, PPC860
, { RT
} },
3424 { "mtcmpf", XSPR(31,467,153), XSPR_MASK
, PPC860
, { RT
} },
3425 { "mtcmpg", XSPR(31,467,154), XSPR_MASK
, PPC860
, { RT
} },
3426 { "mtcmph", XSPR(31,467,155), XSPR_MASK
, PPC860
, { RT
} },
3427 { "mtlctrl1", XSPR(31,467,156), XSPR_MASK
, PPC860
, { RT
} },
3428 { "mtlctrl2", XSPR(31,467,157), XSPR_MASK
, PPC860
, { RT
} },
3429 { "mtictrl", XSPR(31,467,158), XSPR_MASK
, PPC860
, { RT
} },
3430 { "mtbar", XSPR(31,467,159), XSPR_MASK
, PPC860
, { RT
} },
3431 { "mtvrsave",XSPR(31,467,256), XSPR_MASK
, PPCVEC
, { RT
} },
3432 { "mtsprg", XSPR(31,467,272), XSPRG_MASK
, PPC
, { SPRG
, RS
} },
3433 { "mtsprg0", XSPR(31,467,272), XSPR_MASK
, PPC
, { RT
} },
3434 { "mtsprg1", XSPR(31,467,273), XSPR_MASK
, PPC
, { RT
} },
3435 { "mtsprg2", XSPR(31,467,274), XSPR_MASK
, PPC
, { RT
} },
3436 { "mtsprg3", XSPR(31,467,275), XSPR_MASK
, PPC
, { RT
} },
3437 { "mtsprg4", XSPR(31,467,276), XSPR_MASK
, PPC405
, { RT
} },
3438 { "mtsprg5", XSPR(31,467,277), XSPR_MASK
, PPC405
, { RT
} },
3439 { "mtsprg6", XSPR(31,467,278), XSPR_MASK
, PPC405
, { RT
} },
3440 { "mtsprg7", XSPR(31,467,279), XSPR_MASK
, PPC405
, { RT
} },
3441 { "mtasr", XSPR(31,467,280), XSPR_MASK
, PPC64
, { RS
} },
3442 { "mtear", XSPR(31,467,282), XSPR_MASK
, PPC
, { RS
} },
3443 { "mttbl", XSPR(31,467,284), XSPR_MASK
, PPC
, { RS
} },
3444 { "mttbu", XSPR(31,467,285), XSPR_MASK
, PPC
, { RS
} },
3445 { "mtibatu", XSPR(31,467,528), XSPRBAT_MASK
, PPC
, { SPRBAT
, RS
} },
3446 { "mtibatl", XSPR(31,467,529), XSPRBAT_MASK
, PPC
, { SPRBAT
, RS
} },
3447 { "mtdbatu", XSPR(31,467,536), XSPRBAT_MASK
, PPC
, { SPRBAT
, RS
} },
3448 { "mtdbatl", XSPR(31,467,537), XSPRBAT_MASK
, PPC
, { SPRBAT
, RS
} },
3449 { "mtzpr", XSPR(31,467,944), XSPR_MASK
, PPC403
, { RT
} },
3450 { "mtpid", XSPR(31,467,945), XSPR_MASK
, PPC403
, { RT
} },
3451 { "mtccr0", XSPR(31,467,947), XSPR_MASK
, PPC405
, { RT
} },
3452 { "mtiac3", XSPR(31,467,948), XSPR_MASK
, PPC405
, { RT
} },
3453 { "mtiac4", XSPR(31,467,949), XSPR_MASK
, PPC405
, { RT
} },
3454 { "mtdvc1", XSPR(31,467,950), XSPR_MASK
, PPC405
, { RT
} },
3455 { "mtdvc2", XSPR(31,467,951), XSPR_MASK
, PPC405
, { RT
} },
3456 { "mtsgr", XSPR(31,467,953), XSPR_MASK
, PPC403
, { RT
} },
3457 { "mtdcwr", XSPR(31,467,954), XSPR_MASK
, PPC403
, { RT
} },
3458 { "mtsler", XSPR(31,467,955), XSPR_MASK
, PPC405
, { RT
} },
3459 { "mtsu0r", XSPR(31,467,956), XSPR_MASK
, PPC405
, { RT
} },
3460 { "mtdbcr1", XSPR(31,467,957), XSPR_MASK
, PPC405
, { RT
} },
3461 { "mticdbdr",XSPR(31,467,979), XSPR_MASK
, PPC403
, { RT
} },
3462 { "mtesr", XSPR(31,467,980), XSPR_MASK
, PPC403
, { RT
} },
3463 { "mtdear", XSPR(31,467,981), XSPR_MASK
, PPC403
, { RT
} },
3464 { "mtevpr", XSPR(31,467,982), XSPR_MASK
, PPC403
, { RT
} },
3465 { "mtcdbcr", XSPR(31,467,983), XSPR_MASK
, PPC403
, { RT
} },
3466 { "mttsr", XSPR(31,467,984), XSPR_MASK
, PPC403
, { RT
} },
3467 { "mttcr", XSPR(31,467,986), XSPR_MASK
, PPC403
, { RT
} },
3468 { "mtpit", XSPR(31,467,987), XSPR_MASK
, PPC403
, { RT
} },
3469 { "mttbhi", XSPR(31,467,988), XSPR_MASK
, PPC403
, { RT
} },
3470 { "mttblo", XSPR(31,467,989), XSPR_MASK
, PPC403
, { RT
} },
3471 { "mtsrr2", XSPR(31,467,990), XSPR_MASK
, PPC403
, { RT
} },
3472 { "mtsrr3", XSPR(31,467,991), XSPR_MASK
, PPC403
, { RT
} },
3473 { "mtdbsr", XSPR(31,467,1008), XSPR_MASK
, PPC403
, { RT
} },
3474 { "mtdbcr0", XSPR(31,467,1010), XSPR_MASK
, PPC405
, { RT
} },
3475 { "mtiac1", XSPR(31,467,1012), XSPR_MASK
, PPC403
, { RT
} },
3476 { "mtiac2", XSPR(31,467,1013), XSPR_MASK
, PPC403
, { RT
} },
3477 { "mtdac1", XSPR(31,467,1014), XSPR_MASK
, PPC403
, { RT
} },
3478 { "mtdac2", XSPR(31,467,1015), XSPR_MASK
, PPC403
, { RT
} },
3479 { "mtdccr", XSPR(31,467,1018), XSPR_MASK
, PPC403
, { RT
} },
3480 { "mticcr", XSPR(31,467,1019), XSPR_MASK
, PPC403
, { RT
} },
3481 { "mtpbl1", XSPR(31,467,1020), XSPR_MASK
, PPC403
, { RT
} },
3482 { "mtpbu1", XSPR(31,467,1021), XSPR_MASK
, PPC403
, { RT
} },
3483 { "mtpbl2", XSPR(31,467,1022), XSPR_MASK
, PPC403
, { RT
} },
3484 { "mtpbu2", XSPR(31,467,1023), XSPR_MASK
, PPC403
, { RT
} },
3485 { "mtummcr0", XSPR(31,467,936), XSPR_MASK
, PPC750
, { RT
} },
3486 { "mtupmc1", XSPR(31,467,937), XSPR_MASK
, PPC750
, { RT
} },
3487 { "mtupmc2", XSPR(31,467,938), XSPR_MASK
, PPC750
, { RT
} },
3488 { "mtusia", XSPR(31,467,939), XSPR_MASK
, PPC750
, { RT
} },
3489 { "mtummcr1", XSPR(31,467,940), XSPR_MASK
, PPC750
, { RT
} },
3490 { "mtupmc3", XSPR(31,467,941), XSPR_MASK
, PPC750
, { RT
} },
3491 { "mtupmc4", XSPR(31,467,942), XSPR_MASK
, PPC750
, { RT
} },
3492 { "mtmmcr0", XSPR(31,467,952), XSPR_MASK
, PPC750
, { RT
} },
3493 { "mtpmc1", XSPR(31,467,953), XSPR_MASK
, PPC750
, { RT
} },
3494 { "mtpmc2", XSPR(31,467,954), XSPR_MASK
, PPC750
, { RT
} },
3495 { "mtsia", XSPR(31,467,955), XSPR_MASK
, PPC750
, { RT
} },
3496 { "mtmmcr1", XSPR(31,467,956), XSPR_MASK
, PPC750
, { RT
} },
3497 { "mtpmc3", XSPR(31,467,957), XSPR_MASK
, PPC750
, { RT
} },
3498 { "mtpmc4", XSPR(31,467,958), XSPR_MASK
, PPC750
, { RT
} },
3499 { "mtl2cr", XSPR(31,467,1017), XSPR_MASK
, PPC750
, { RT
} },
3500 { "mtictc", XSPR(31,467,1019), XSPR_MASK
, PPC750
, { RT
} },
3501 { "mtthrm1", XSPR(31,467,1020), XSPR_MASK
, PPC750
, { RT
} },
3502 { "mtthrm2", XSPR(31,467,1021), XSPR_MASK
, PPC750
, { RT
} },
3503 { "mtthrm3", XSPR(31,467,1022), XSPR_MASK
, PPC750
, { RT
} },
3504 { "mtspr", X(31,467), X_MASK
, COM
, { SPR
, RS
} },
3506 { "dcbi", X(31,470), XRT_MASK
, PPC
, { RA
, RB
} },
3508 { "nand", XRC(31,476,0), X_MASK
, COM
, { RA
, RS
, RB
} },
3509 { "nand.", XRC(31,476,1), X_MASK
, COM
, { RA
, RS
, RB
} },
3511 { "dcbie", X(31,478), XRT_MASK
, BOOKE64
, { RA
, RB
} },
3513 { "dcread", X(31,486), X_MASK
, PPC403
, { RT
, RA
, RB
}},
3515 { "nabs", XO(31,488,0,0), XORB_MASK
, M601
, { RT
, RA
} },
3516 { "subfme64",XO(31,488,0,0), XORB_MASK
, BOOKE64
, { RT
, RA
} },
3517 { "nabs.", XO(31,488,0,1), XORB_MASK
, M601
, { RT
, RA
} },
3518 { "nabso", XO(31,488,1,0), XORB_MASK
, M601
, { RT
, RA
} },
3519 { "subfme64o",XO(31,488,1,0), XORB_MASK
, BOOKE64
, { RT
, RA
} },
3520 { "nabso.", XO(31,488,1,1), XORB_MASK
, M601
, { RT
, RA
} },
3522 { "divd", XO(31,489,0,0), XO_MASK
, PPC64
, { RT
, RA
, RB
} },
3523 { "divd.", XO(31,489,0,1), XO_MASK
, PPC64
, { RT
, RA
, RB
} },
3524 { "divdo", XO(31,489,1,0), XO_MASK
, PPC64
, { RT
, RA
, RB
} },
3525 { "divdo.", XO(31,489,1,1), XO_MASK
, PPC64
, { RT
, RA
, RB
} },
3527 { "addme64", XO(31,490,0,0), XORB_MASK
, BOOKE64
, { RT
, RA
} },
3528 { "addme64o",XO(31,490,1,0), XORB_MASK
, BOOKE64
, { RT
, RA
} },
3530 { "divw", XO(31,491,0,0), XO_MASK
, PPC
, { RT
, RA
, RB
} },
3531 { "divw.", XO(31,491,0,1), XO_MASK
, PPC
, { RT
, RA
, RB
} },
3532 { "divwo", XO(31,491,1,0), XO_MASK
, PPC
, { RT
, RA
, RB
} },
3533 { "divwo.", XO(31,491,1,1), XO_MASK
, PPC
, { RT
, RA
, RB
} },
3535 { "slbia", X(31,498), 0xffffffff, PPC64
, { 0 } },
3537 { "cli", X(31,502), XRB_MASK
, POWER
, { RT
, RA
} },
3539 { "stdcxe.", XRC(31,511,1), X_MASK
, BOOKE64
, { RS
, RA
, RB
} },
3541 { "mcrxr", X(31,512), XRARB_MASK
|(3<<21), COM
, { BF
} },
3543 { "mcrxr64", X(31,544), XRARB_MASK
|(3<<21), BOOKE
, { BF
} },
3545 { "clcs", X(31,531), XRB_MASK
, M601
, { RT
, RA
} },
3547 { "lswx", X(31,533), X_MASK
, PPCCOM
, { RT
, RA
, RB
} },
3548 { "lsx", X(31,533), X_MASK
, PWRCOM
, { RT
, RA
, RB
} },
3550 { "lwbrx", X(31,534), X_MASK
, PPCCOM
, { RT
, RA
, RB
} },
3551 { "lbrx", X(31,534), X_MASK
, PWRCOM
, { RT
, RA
, RB
} },
3553 { "lfsx", X(31,535), X_MASK
, COM
, { FRT
, RA
, RB
} },
3555 { "srw", XRC(31,536,0), X_MASK
, PPCCOM
, { RA
, RS
, RB
} },
3556 { "sr", XRC(31,536,0), X_MASK
, PWRCOM
, { RA
, RS
, RB
} },
3557 { "srw.", XRC(31,536,1), X_MASK
, PPCCOM
, { RA
, RS
, RB
} },
3558 { "sr.", XRC(31,536,1), X_MASK
, PWRCOM
, { RA
, RS
, RB
} },
3560 { "rrib", XRC(31,537,0), X_MASK
, M601
, { RA
, RS
, RB
} },
3561 { "rrib.", XRC(31,537,1), X_MASK
, M601
, { RA
, RS
, RB
} },
3563 { "srd", XRC(31,539,0), X_MASK
, PPC64
, { RA
, RS
, RB
} },
3564 { "srd.", XRC(31,539,1), X_MASK
, PPC64
, { RA
, RS
, RB
} },
3566 { "maskir", XRC(31,541,0), X_MASK
, M601
, { RA
, RS
, RB
} },
3567 { "maskir.", XRC(31,541,1), X_MASK
, M601
, { RA
, RS
, RB
} },
3569 { "lwbrxe", X(31,542), X_MASK
, BOOKE64
, { RT
, RA
, RB
} },
3571 { "lfsxe", X(31,543), X_MASK
, BOOKE64
, { FRT
, RA
, RB
} },
3573 { "tlbsync", X(31,566), 0xffffffff, PPC
, { 0 } },
3575 { "lfsux", X(31,567), X_MASK
, COM
, { FRT
, RAS
, RB
} },
3577 { "lfsuxe", X(31,575), X_MASK
, BOOKE64
, { FRT
, RAS
, RB
} },
3579 { "mfsr", X(31,595), XRB_MASK
|(1<<20), COM32
, { RT
, SR
} },
3581 { "lswi", X(31,597), X_MASK
, PPCCOM
, { RT
, RA
, NB
} },
3582 { "lsi", X(31,597), X_MASK
, PWRCOM
, { RT
, RA
, NB
} },
3584 { "lwsync", XSYNC(31,598,1), 0xffffffff, PPCONLY
, { 0 } },
3585 { "ptesync", XSYNC(31,598,2), 0xffffffff, PPC64
, { 0 } },
3586 { "sync", X(31,598), XSYNC_MASK
, PPCCOM
, { LS
} },
3587 { "dcs", X(31,598), 0xffffffff, PWRCOM
, { 0 } },
3588 { "msync", X(31,598), 0xf80007fe, BOOKE
, { 0 } },
3590 { "lfdx", X(31,599), X_MASK
, COM
, { FRT
, RA
, RB
} },
3592 { "lfdxe", X(31,607), X_MASK
, BOOKE64
, { FRT
, RA
, RB
} },
3594 { "mfsri", X(31,627), X_MASK
, PWRCOM
, { RT
, RA
, RB
} },
3596 { "dclst", X(31,630), XRB_MASK
, PWRCOM
, { RS
, RA
} },
3598 { "lfdux", X(31,631), X_MASK
, COM
, { FRT
, RAS
, RB
} },
3600 { "lfduxe", X(31,639), X_MASK
, BOOKE64
, { FRT
, RAS
, RB
} },
3602 { "mfsrin", X(31,659), XRA_MASK
, PPC32
, { RT
, RB
} },
3604 { "stswx", X(31,661), X_MASK
, PPCCOM
, { RS
, RA
, RB
} },
3605 { "stsx", X(31,661), X_MASK
, PWRCOM
, { RS
, RA
, RB
} },
3607 { "stwbrx", X(31,662), X_MASK
, PPCCOM
, { RS
, RA
, RB
} },
3608 { "stbrx", X(31,662), X_MASK
, PWRCOM
, { RS
, RA
, RB
} },
3610 { "stfsx", X(31,663), X_MASK
, COM
, { FRS
, RA
, RB
} },
3612 { "srq", XRC(31,664,0), X_MASK
, M601
, { RA
, RS
, RB
} },
3613 { "srq.", XRC(31,664,1), X_MASK
, M601
, { RA
, RS
, RB
} },
3615 { "sre", XRC(31,665,0), X_MASK
, M601
, { RA
, RS
, RB
} },
3616 { "sre.", XRC(31,665,1), X_MASK
, M601
, { RA
, RS
, RB
} },
3618 { "stwbrxe", X(31,670), X_MASK
, BOOKE64
, { RS
, RA
, RB
} },
3620 { "stfsxe", X(31,671), X_MASK
, BOOKE64
, { FRS
, RA
, RB
} },
3622 { "stfsux", X(31,695), X_MASK
, COM
, { FRS
, RAS
, RB
} },
3624 { "sriq", XRC(31,696,0), X_MASK
, M601
, { RA
, RS
, SH
} },
3625 { "sriq.", XRC(31,696,1), X_MASK
, M601
, { RA
, RS
, SH
} },
3627 { "stfsuxe", X(31,703), X_MASK
, BOOKE64
, { FRS
, RAS
, RB
} },
3629 { "stswi", X(31,725), X_MASK
, PPCCOM
, { RS
, RA
, NB
} },
3630 { "stsi", X(31,725), X_MASK
, PWRCOM
, { RS
, RA
, NB
} },
3632 { "stfdx", X(31,727), X_MASK
, COM
, { FRS
, RA
, RB
} },
3634 { "srlq", XRC(31,728,0), X_MASK
, M601
, { RA
, RS
, RB
} },
3635 { "srlq.", XRC(31,728,1), X_MASK
, M601
, { RA
, RS
, RB
} },
3637 { "sreq", XRC(31,729,0), X_MASK
, M601
, { RA
, RS
, RB
} },
3638 { "sreq.", XRC(31,729,1), X_MASK
, M601
, { RA
, RS
, RB
} },
3640 { "stfdxe", X(31,735), X_MASK
, BOOKE64
, { FRS
, RA
, RB
} },
3642 { "dcba", X(31,758), XRT_MASK
, PPC405
, { RA
, RB
} },
3643 { "dcba", X(31,758), XRT_MASK
, BOOKE
, { RA
, RB
} },
3645 { "stfdux", X(31,759), X_MASK
, COM
, { FRS
, RAS
, RB
} },
3647 { "srliq", XRC(31,760,0), X_MASK
, M601
, { RA
, RS
, SH
} },
3648 { "srliq.", XRC(31,760,1), X_MASK
, M601
, { RA
, RS
, SH
} },
3650 { "dcbae", X(31,766), XRT_MASK
, BOOKE64
, { RA
, RB
} },
3652 { "stfduxe", X(31,767), X_MASK
, BOOKE64
, { FRS
, RAS
, RB
} },
3654 { "tlbivax", X(31,786), XRT_MASK
, BOOKE
, { RA
, RB
} },
3655 { "tlbivaxe",X(31,787), XRT_MASK
, BOOKE
, { RA
, RB
} },
3657 { "lhbrx", X(31,790), X_MASK
, COM
, { RT
, RA
, RB
} },
3659 { "sraw", XRC(31,792,0), X_MASK
, PPCCOM
, { RA
, RS
, RB
} },
3660 { "sra", XRC(31,792,0), X_MASK
, PWRCOM
, { RA
, RS
, RB
} },
3661 { "sraw.", XRC(31,792,1), X_MASK
, PPCCOM
, { RA
, RS
, RB
} },
3662 { "sra.", XRC(31,792,1), X_MASK
, PWRCOM
, { RA
, RS
, RB
} },
3664 { "srad", XRC(31,794,0), X_MASK
, PPC64
, { RA
, RS
, RB
} },
3665 { "srad.", XRC(31,794,1), X_MASK
, PPC64
, { RA
, RS
, RB
} },
3667 { "lhbrxe", X(31,798), X_MASK
, BOOKE64
, { RT
, RA
, RB
} },
3669 { "ldxe", X(31,799), X_MASK
, BOOKE64
, { RT
, RA
, RB
} },
3670 { "lduxe", X(31,831), X_MASK
, BOOKE64
, { RT
, RA
, RB
} },
3672 { "rac", X(31,818), X_MASK
, PWRCOM
, { RT
, RA
, RB
} },
3674 { "dss", XDSS(31,822,0), XDSS_MASK
, PPCVEC
, { STRM
} },
3675 { "dssall", XDSS(31,822,1), XDSS_MASK
, PPCVEC
, { STRM
} },
3677 { "srawi", XRC(31,824,0), X_MASK
, PPCCOM
, { RA
, RS
, SH
} },
3678 { "srai", XRC(31,824,0), X_MASK
, PWRCOM
, { RA
, RS
, SH
} },
3679 { "srawi.", XRC(31,824,1), X_MASK
, PPCCOM
, { RA
, RS
, SH
} },
3680 { "srai.", XRC(31,824,1), X_MASK
, PWRCOM
, { RA
, RS
, SH
} },
3682 { "slbmfev", X(31,851), XRA_MASK
, PPC64
, { RT
, RB
} },
3684 { "eieio", X(31,854), 0xffffffff, PPC
, { 0 } },
3685 { "mbar", X(31,854), 0xffffffff, BOOKE
, { MO
} },
3687 { "tlbsx", XRC(31,914,0), X_MASK
, PPC403
, { RT
, RA
, RB
} },
3688 { "tlbsx.", XRC(31,914,1), X_MASK
, PPC403
, { RT
, RA
, RB
} },
3690 { "tlbsx", XRC(31,914,0), X_MASK
, BOOKE
, { RA
, RB
} },
3691 { "tlbsxe", XRC(31,915,0), X_MASK
, BOOKE
, { RA
, RB
} },
3693 { "slbmfee", X(31,915), XRA_MASK
, PPC64
, { RT
, RB
} },
3695 { "sthbrx", X(31,918), X_MASK
, COM
, { RS
, RA
, RB
} },
3697 { "sraq", XRC(31,920,0), X_MASK
, M601
, { RA
, RS
, RB
} },
3698 { "sraq.", XRC(31,920,1), X_MASK
, M601
, { RA
, RS
, RB
} },
3700 { "srea", XRC(31,921,0), X_MASK
, M601
, { RA
, RS
, RB
} },
3701 { "srea.", XRC(31,921,1), X_MASK
, M601
, { RA
, RS
, RB
} },
3703 { "extsh", XRC(31,922,0), XRB_MASK
, PPCCOM
, { RA
, RS
} },
3704 { "exts", XRC(31,922,0), XRB_MASK
, PWRCOM
, { RA
, RS
} },
3705 { "extsh.", XRC(31,922,1), XRB_MASK
, PPCCOM
, { RA
, RS
} },
3706 { "exts.", XRC(31,922,1), XRB_MASK
, PWRCOM
, { RA
, RS
} },
3708 { "sthbrxe", X(31,926), X_MASK
, BOOKE64
, { RS
, RA
, RB
} },
3710 { "stdxe", X(31,927), X_MASK
, BOOKE64
, { RS
, RA
, RB
} },
3712 { "tlbre", X(31,946), X_MASK
, BOOKE
, { RT
, RA
, WS
} },
3714 { "tlbrehi", XTLB(31,946,0), XTLB_MASK
, PPC403
, { RT
, RA
} },
3715 { "tlbrelo", XTLB(31,946,1), XTLB_MASK
, PPC403
, { RT
, RA
} },
3717 { "sraiq", XRC(31,952,0), X_MASK
, M601
, { RA
, RS
, SH
} },
3718 { "sraiq.", XRC(31,952,1), X_MASK
, M601
, { RA
, RS
, SH
} },
3720 { "extsb", XRC(31,954,0), XRB_MASK
, PPC
, { RA
, RS
} },
3721 { "extsb.", XRC(31,954,1), XRB_MASK
, PPC
, { RA
, RS
} },
3723 { "stduxe", X(31,959), X_MASK
, BOOKE64
, { RS
, RAS
, RB
} },
3725 { "iccci", X(31,966), XRT_MASK
, PPC403
, { RA
, RB
} },
3727 { "tlbld", X(31,978), XRTRA_MASK
, PPC
, { RB
} },
3729 { "tlbwehi", XTLB(31,978,0), XTLB_MASK
, PPC403
, { RT
, RA
} },
3730 { "tlbwelo", XTLB(31,978,1), XTLB_MASK
, PPC403
, { RT
, RA
} },
3731 { "tlbwe", X(31,978), X_MASK
, PPC403
, { RS
, RA
, SH
} },
3733 { "tlbwe", X(31,978), X_MASK
, BOOKE
, { RT
, RA
, WS
} },
3735 { "icbi", X(31,982), XRT_MASK
, PPC
, { RA
, RB
} },
3737 { "stfiwx", X(31,983), X_MASK
, PPC
, { FRS
, RA
, RB
} },
3739 { "extsw", XRC(31,986,0), XRB_MASK
, PPC
, { RA
, RS
} },
3740 { "extsw.", XRC(31,986,1), XRB_MASK
, PPC
, { RA
, RS
} },
3742 { "icread", X(31,998), XRT_MASK
, PPC403
, { RA
, RB
} },
3744 { "icbie", X(31,990), XRT_MASK
, BOOKE64
, { RA
, RB
} },
3745 { "stfiwxe", X(31,991), X_MASK
, BOOKE64
, { FRS
, RA
, RB
} },
3747 { "tlbli", X(31,1010), XRTRA_MASK
, PPC
, { RB
} },
3749 { "dcbz", X(31,1014), XRT_MASK
, PPC
, { RA
, RB
} },
3750 { "dclz", X(31,1014), XRT_MASK
, PPC
, { RA
, RB
} },
3752 { "dcbze", X(31,1022), XRT_MASK
, BOOKE64
, { RA
, RB
} },
3754 { "lvebx", X(31, 7), X_MASK
, PPCVEC
, { VD
, RA
, RB
} },
3755 { "lvehx", X(31, 39), X_MASK
, PPCVEC
, { VD
, RA
, RB
} },
3756 { "lvewx", X(31, 71), X_MASK
, PPCVEC
, { VD
, RA
, RB
} },
3757 { "lvsl", X(31, 6), X_MASK
, PPCVEC
, { VD
, RA
, RB
} },
3758 { "lvsr", X(31, 38), X_MASK
, PPCVEC
, { VD
, RA
, RB
} },
3759 { "lvx", X(31, 103), X_MASK
, PPCVEC
, { VD
, RA
, RB
} },
3760 { "lvxl", X(31, 359), X_MASK
, PPCVEC
, { VD
, RA
, RB
} },
3761 { "stvebx", X(31, 135), X_MASK
, PPCVEC
, { VS
, RA
, RB
} },
3762 { "stvehx", X(31, 167), X_MASK
, PPCVEC
, { VS
, RA
, RB
} },
3763 { "stvewx", X(31, 199), X_MASK
, PPCVEC
, { VS
, RA
, RB
} },
3764 { "stvx", X(31, 231), X_MASK
, PPCVEC
, { VS
, RA
, RB
} },
3765 { "stvxl", X(31, 487), X_MASK
, PPCVEC
, { VS
, RA
, RB
} },
3767 { "lwz", OP(32), OP_MASK
, PPCCOM
, { RT
, D
, RA
} },
3768 { "l", OP(32), OP_MASK
, PWRCOM
, { RT
, D
, RA
} },
3770 { "lwzu", OP(33), OP_MASK
, PPCCOM
, { RT
, D
, RAL
} },
3771 { "lu", OP(33), OP_MASK
, PWRCOM
, { RT
, D
, RA
} },
3773 { "lbz", OP(34), OP_MASK
, COM
, { RT
, D
, RA
} },
3775 { "lbzu", OP(35), OP_MASK
, COM
, { RT
, D
, RAL
} },
3777 { "stw", OP(36), OP_MASK
, PPCCOM
, { RS
, D
, RA
} },
3778 { "st", OP(36), OP_MASK
, PWRCOM
, { RS
, D
, RA
} },
3780 { "stwu", OP(37), OP_MASK
, PPCCOM
, { RS
, D
, RAS
} },
3781 { "stu", OP(37), OP_MASK
, PWRCOM
, { RS
, D
, RA
} },
3783 { "stb", OP(38), OP_MASK
, COM
, { RS
, D
, RA
} },
3785 { "stbu", OP(39), OP_MASK
, COM
, { RS
, D
, RAS
} },
3787 { "lhz", OP(40), OP_MASK
, COM
, { RT
, D
, RA
} },
3789 { "lhzu", OP(41), OP_MASK
, COM
, { RT
, D
, RAL
} },
3791 { "lha", OP(42), OP_MASK
, COM
, { RT
, D
, RA
} },
3793 { "lhau", OP(43), OP_MASK
, COM
, { RT
, D
, RAL
} },
3795 { "sth", OP(44), OP_MASK
, COM
, { RS
, D
, RA
} },
3797 { "sthu", OP(45), OP_MASK
, COM
, { RS
, D
, RAS
} },
3799 { "lmw", OP(46), OP_MASK
, PPCCOM
, { RT
, D
, RAM
} },
3800 { "lm", OP(46), OP_MASK
, PWRCOM
, { RT
, D
, RA
} },
3802 { "stmw", OP(47), OP_MASK
, PPCCOM
, { RS
, D
, RA
} },
3803 { "stm", OP(47), OP_MASK
, PWRCOM
, { RS
, D
, RA
} },
3805 { "lfs", OP(48), OP_MASK
, COM
, { FRT
, D
, RA
} },
3807 { "lfsu", OP(49), OP_MASK
, COM
, { FRT
, D
, RAS
} },
3809 { "lfd", OP(50), OP_MASK
, COM
, { FRT
, D
, RA
} },
3811 { "lfdu", OP(51), OP_MASK
, COM
, { FRT
, D
, RAS
} },
3813 { "stfs", OP(52), OP_MASK
, COM
, { FRS
, D
, RA
} },
3815 { "stfsu", OP(53), OP_MASK
, COM
, { FRS
, D
, RAS
} },
3817 { "stfd", OP(54), OP_MASK
, COM
, { FRS
, D
, RA
} },
3819 { "stfdu", OP(55), OP_MASK
, COM
, { FRS
, D
, RAS
} },
3821 { "lfq", OP(56), OP_MASK
, POWER2
, { FRT
, D
, RA
} },
3823 { "lfqu", OP(57), OP_MASK
, POWER2
, { FRT
, D
, RA
} },
3825 { "lbze", DEO(58,0), DE_MASK
, BOOKE64
, { RT
, DE
, RA
} },
3826 { "lbzue", DEO(58,1), DE_MASK
, BOOKE64
, { RT
, DE
, RAL
} },
3827 { "lhze", DEO(58,2), DE_MASK
, BOOKE64
, { RT
, DE
, RA
} },
3828 { "lhzue", DEO(58,3), DE_MASK
, BOOKE64
, { RT
, DE
, RAL
} },
3829 { "lhae", DEO(58,4), DE_MASK
, BOOKE64
, { RT
, DE
, RA
} },
3830 { "lhaue", DEO(58,5), DE_MASK
, BOOKE64
, { RT
, DE
, RAL
} },
3831 { "lwze", DEO(58,6), DE_MASK
, BOOKE64
, { RT
, DE
, RA
} },
3832 { "lwzue", DEO(58,7), DE_MASK
, BOOKE64
, { RT
, DE
, RAL
} },
3833 { "stbe", DEO(58,8), DE_MASK
, BOOKE64
, { RS
, DE
, RA
} },
3834 { "stbue", DEO(58,9), DE_MASK
, BOOKE64
, { RS
, DE
, RAS
} },
3835 { "sthe", DEO(58,10), DE_MASK
, BOOKE64
, { RS
, DE
, RA
} },
3836 { "sthue", DEO(58,11), DE_MASK
, BOOKE64
, { RS
, DE
, RAS
} },
3837 { "stwe", DEO(58,14), DE_MASK
, BOOKE64
, { RS
, DE
, RA
} },
3838 { "stwue", DEO(58,15), DE_MASK
, BOOKE64
, { RS
, DE
, RAS
} },
3840 { "ld", DSO(58,0), DS_MASK
, PPC64
, { RT
, DS
, RA
} },
3842 { "ldu", DSO(58,1), DS_MASK
, PPC64
, { RT
, DS
, RAL
} },
3844 { "lwa", DSO(58,2), DS_MASK
, PPC64
, { RT
, DS
, RA
} },
3846 { "fdivs", A(59,18,0), AFRC_MASK
, PPC
, { FRT
, FRA
, FRB
} },
3847 { "fdivs.", A(59,18,1), AFRC_MASK
, PPC
, { FRT
, FRA
, FRB
} },
3849 { "fsubs", A(59,20,0), AFRC_MASK
, PPC
, { FRT
, FRA
, FRB
} },
3850 { "fsubs.", A(59,20,1), AFRC_MASK
, PPC
, { FRT
, FRA
, FRB
} },
3852 { "fadds", A(59,21,0), AFRC_MASK
, PPC
, { FRT
, FRA
, FRB
} },
3853 { "fadds.", A(59,21,1), AFRC_MASK
, PPC
, { FRT
, FRA
, FRB
} },
3855 { "fsqrts", A(59,22,0), AFRAFRC_MASK
, PPC
, { FRT
, FRB
} },
3856 { "fsqrts.", A(59,22,1), AFRAFRC_MASK
, PPC
, { FRT
, FRB
} },
3858 { "fres", A(59,24,0), AFRAFRC_MASK
, PPC
, { FRT
, FRB
} },
3859 { "fres.", A(59,24,1), AFRAFRC_MASK
, PPC
, { FRT
, FRB
} },
3861 { "fmuls", A(59,25,0), AFRB_MASK
, PPC
, { FRT
, FRA
, FRC
} },
3862 { "fmuls.", A(59,25,1), AFRB_MASK
, PPC
, { FRT
, FRA
, FRC
} },
3864 { "fmsubs", A(59,28,0), A_MASK
, PPC
, { FRT
,FRA
,FRC
,FRB
} },
3865 { "fmsubs.", A(59,28,1), A_MASK
, PPC
, { FRT
,FRA
,FRC
,FRB
} },
3867 { "fmadds", A(59,29,0), A_MASK
, PPC
, { FRT
,FRA
,FRC
,FRB
} },
3868 { "fmadds.", A(59,29,1), A_MASK
, PPC
, { FRT
,FRA
,FRC
,FRB
} },
3870 { "fnmsubs", A(59,30,0), A_MASK
, PPC
, { FRT
,FRA
,FRC
,FRB
} },
3871 { "fnmsubs.",A(59,30,1), A_MASK
, PPC
, { FRT
,FRA
,FRC
,FRB
} },
3873 { "fnmadds", A(59,31,0), A_MASK
, PPC
, { FRT
,FRA
,FRC
,FRB
} },
3874 { "fnmadds.",A(59,31,1), A_MASK
, PPC
, { FRT
,FRA
,FRC
,FRB
} },
3876 { "stfq", OP(60), OP_MASK
, POWER2
, { FRS
, D
, RA
} },
3878 { "stfqu", OP(61), OP_MASK
, POWER2
, { FRS
, D
, RA
} },
3880 { "lde", DEO(62,0), DE_MASK
, BOOKE64
, { RT
, DES
, RA
} },
3881 { "ldue", DEO(62,1), DE_MASK
, BOOKE64
, { RT
, DES
, RA
} },
3882 { "lfse", DEO(62,4), DE_MASK
, BOOKE64
, { FRT
, DES
, RA
} },
3883 { "lfsue", DEO(62,5), DE_MASK
, BOOKE64
, { FRT
, DES
, RAS
} },
3884 { "lfde", DEO(62,6), DE_MASK
, BOOKE64
, { FRT
, DES
, RA
} },
3885 { "lfdue", DEO(62,7), DE_MASK
, BOOKE64
, { FRT
, DES
, RAS
} },
3886 { "stde", DEO(62,8), DE_MASK
, BOOKE64
, { RS
, DES
, RA
} },
3887 { "stdue", DEO(62,9), DE_MASK
, BOOKE64
, { RS
, DES
, RAS
} },
3888 { "stfse", DEO(62,12), DE_MASK
, BOOKE64
, { FRS
, DES
, RA
} },
3889 { "stfsue", DEO(62,13), DE_MASK
, BOOKE64
, { FRS
, DES
, RAS
} },
3890 { "stfde", DEO(62,14), DE_MASK
, BOOKE64
, { FRS
, DES
, RA
} },
3891 { "stfdue", DEO(62,15), DE_MASK
, BOOKE64
, { FRS
, DES
, RAS
} },
3893 { "std", DSO(62,0), DS_MASK
, PPC64
, { RS
, DS
, RA
} },
3895 { "stdu", DSO(62,1), DS_MASK
, PPC64
, { RS
, DS
, RAS
} },
3897 { "fcmpu", X(63,0), X_MASK
|(3<<21), COM
, { BF
, FRA
, FRB
} },
3899 { "frsp", XRC(63,12,0), XRA_MASK
, COM
, { FRT
, FRB
} },
3900 { "frsp.", XRC(63,12,1), XRA_MASK
, COM
, { FRT
, FRB
} },
3902 { "fctiw", XRC(63,14,0), XRA_MASK
, PPCCOM
, { FRT
, FRB
} },
3903 { "fcir", XRC(63,14,0), XRA_MASK
, POWER2
, { FRT
, FRB
} },
3904 { "fctiw.", XRC(63,14,1), XRA_MASK
, PPCCOM
, { FRT
, FRB
} },
3905 { "fcir.", XRC(63,14,1), XRA_MASK
, POWER2
, { FRT
, FRB
} },
3907 { "fctiwz", XRC(63,15,0), XRA_MASK
, PPCCOM
, { FRT
, FRB
} },
3908 { "fcirz", XRC(63,15,0), XRA_MASK
, POWER2
, { FRT
, FRB
} },
3909 { "fctiwz.", XRC(63,15,1), XRA_MASK
, PPCCOM
, { FRT
, FRB
} },
3910 { "fcirz.", XRC(63,15,1), XRA_MASK
, POWER2
, { FRT
, FRB
} },
3912 { "fdiv", A(63,18,0), AFRC_MASK
, PPCCOM
, { FRT
, FRA
, FRB
} },
3913 { "fd", A(63,18,0), AFRC_MASK
, PWRCOM
, { FRT
, FRA
, FRB
} },
3914 { "fdiv.", A(63,18,1), AFRC_MASK
, PPCCOM
, { FRT
, FRA
, FRB
} },
3915 { "fd.", A(63,18,1), AFRC_MASK
, PWRCOM
, { FRT
, FRA
, FRB
} },
3917 { "fsub", A(63,20,0), AFRC_MASK
, PPCCOM
, { FRT
, FRA
, FRB
} },
3918 { "fs", A(63,20,0), AFRC_MASK
, PWRCOM
, { FRT
, FRA
, FRB
} },
3919 { "fsub.", A(63,20,1), AFRC_MASK
, PPCCOM
, { FRT
, FRA
, FRB
} },
3920 { "fs.", A(63,20,1), AFRC_MASK
, PWRCOM
, { FRT
, FRA
, FRB
} },
3922 { "fadd", A(63,21,0), AFRC_MASK
, PPCCOM
, { FRT
, FRA
, FRB
} },
3923 { "fa", A(63,21,0), AFRC_MASK
, PWRCOM
, { FRT
, FRA
, FRB
} },
3924 { "fadd.", A(63,21,1), AFRC_MASK
, PPCCOM
, { FRT
, FRA
, FRB
} },
3925 { "fa.", A(63,21,1), AFRC_MASK
, PWRCOM
, { FRT
, FRA
, FRB
} },
3927 { "fsqrt", A(63,22,0), AFRAFRC_MASK
, PPCPWR2
, { FRT
, FRB
} },
3928 { "fsqrt.", A(63,22,1), AFRAFRC_MASK
, PPCPWR2
, { FRT
, FRB
} },
3930 { "fsel", A(63,23,0), A_MASK
, PPC
, { FRT
,FRA
,FRC
,FRB
} },
3931 { "fsel.", A(63,23,1), A_MASK
, PPC
, { FRT
,FRA
,FRC
,FRB
} },
3933 { "fmul", A(63,25,0), AFRB_MASK
, PPCCOM
, { FRT
, FRA
, FRC
} },
3934 { "fm", A(63,25,0), AFRB_MASK
, PWRCOM
, { FRT
, FRA
, FRC
} },
3935 { "fmul.", A(63,25,1), AFRB_MASK
, PPCCOM
, { FRT
, FRA
, FRC
} },
3936 { "fm.", A(63,25,1), AFRB_MASK
, PWRCOM
, { FRT
, FRA
, FRC
} },
3938 { "frsqrte", A(63,26,0), AFRAFRC_MASK
, PPC
, { FRT
, FRB
} },
3939 { "frsqrte.",A(63,26,1), AFRAFRC_MASK
, PPC
, { FRT
, FRB
} },
3941 { "fmsub", A(63,28,0), A_MASK
, PPCCOM
, { FRT
,FRA
,FRC
,FRB
} },
3942 { "fms", A(63,28,0), A_MASK
, PWRCOM
, { FRT
,FRA
,FRC
,FRB
} },
3943 { "fmsub.", A(63,28,1), A_MASK
, PPCCOM
, { FRT
,FRA
,FRC
,FRB
} },
3944 { "fms.", A(63,28,1), A_MASK
, PWRCOM
, { FRT
,FRA
,FRC
,FRB
} },
3946 { "fmadd", A(63,29,0), A_MASK
, PPCCOM
, { FRT
,FRA
,FRC
,FRB
} },
3947 { "fma", A(63,29,0), A_MASK
, PWRCOM
, { FRT
,FRA
,FRC
,FRB
} },
3948 { "fmadd.", A(63,29,1), A_MASK
, PPCCOM
, { FRT
,FRA
,FRC
,FRB
} },
3949 { "fma.", A(63,29,1), A_MASK
, PWRCOM
, { FRT
,FRA
,FRC
,FRB
} },
3951 { "fnmsub", A(63,30,0), A_MASK
, PPCCOM
, { FRT
,FRA
,FRC
,FRB
} },
3952 { "fnms", A(63,30,0), A_MASK
, PWRCOM
, { FRT
,FRA
,FRC
,FRB
} },
3953 { "fnmsub.", A(63,30,1), A_MASK
, PPCCOM
, { FRT
,FRA
,FRC
,FRB
} },
3954 { "fnms.", A(63,30,1), A_MASK
, PWRCOM
, { FRT
,FRA
,FRC
,FRB
} },
3956 { "fnmadd", A(63,31,0), A_MASK
, PPCCOM
, { FRT
,FRA
,FRC
,FRB
} },
3957 { "fnma", A(63,31,0), A_MASK
, PWRCOM
, { FRT
,FRA
,FRC
,FRB
} },
3958 { "fnmadd.", A(63,31,1), A_MASK
, PPCCOM
, { FRT
,FRA
,FRC
,FRB
} },
3959 { "fnma.", A(63,31,1), A_MASK
, PWRCOM
, { FRT
,FRA
,FRC
,FRB
} },
3961 { "fcmpo", X(63,32), X_MASK
|(3<<21), COM
, { BF
, FRA
, FRB
} },
3963 { "mtfsb1", XRC(63,38,0), XRARB_MASK
, COM
, { BT
} },
3964 { "mtfsb1.", XRC(63,38,1), XRARB_MASK
, COM
, { BT
} },
3966 { "fneg", XRC(63,40,0), XRA_MASK
, COM
, { FRT
, FRB
} },
3967 { "fneg.", XRC(63,40,1), XRA_MASK
, COM
, { FRT
, FRB
} },
3969 { "mcrfs", X(63,64), XRB_MASK
|(3<<21)|(3<<16), COM
, { BF
, BFA
} },
3971 { "mtfsb0", XRC(63,70,0), XRARB_MASK
, COM
, { BT
} },
3972 { "mtfsb0.", XRC(63,70,1), XRARB_MASK
, COM
, { BT
} },
3974 { "fmr", XRC(63,72,0), XRA_MASK
, COM
, { FRT
, FRB
} },
3975 { "fmr.", XRC(63,72,1), XRA_MASK
, COM
, { FRT
, FRB
} },
3977 { "mtfsfi", XRC(63,134,0), XRA_MASK
|(3<<21)|(1<<11), COM
, { BF
, U
} },
3978 { "mtfsfi.", XRC(63,134,1), XRA_MASK
|(3<<21)|(1<<11), COM
, { BF
, U
} },
3980 { "fnabs", XRC(63,136,0), XRA_MASK
, COM
, { FRT
, FRB
} },
3981 { "fnabs.", XRC(63,136,1), XRA_MASK
, COM
, { FRT
, FRB
} },
3983 { "fabs", XRC(63,264,0), XRA_MASK
, COM
, { FRT
, FRB
} },
3984 { "fabs.", XRC(63,264,1), XRA_MASK
, COM
, { FRT
, FRB
} },
3986 { "mffs", XRC(63,583,0), XRARB_MASK
, COM
, { FRT
} },
3987 { "mffs.", XRC(63,583,1), XRARB_MASK
, COM
, { FRT
} },
3989 { "mtfsf", XFL(63,711,0), XFL_MASK
, COM
, { FLM
, FRB
} },
3990 { "mtfsf.", XFL(63,711,1), XFL_MASK
, COM
, { FLM
, FRB
} },
3992 { "fctid", XRC(63,814,0), XRA_MASK
, PPC64
, { FRT
, FRB
} },
3993 { "fctid.", XRC(63,814,1), XRA_MASK
, PPC64
, { FRT
, FRB
} },
3995 { "fctidz", XRC(63,815,0), XRA_MASK
, PPC64
, { FRT
, FRB
} },
3996 { "fctidz.", XRC(63,815,1), XRA_MASK
, PPC64
, { FRT
, FRB
} },
3998 { "fcfid", XRC(63,846,0), XRA_MASK
, PPC64
, { FRT
, FRB
} },
3999 { "fcfid.", XRC(63,846,1), XRA_MASK
, PPC64
, { FRT
, FRB
} },
4003 const int powerpc_num_opcodes
=
4004 sizeof (powerpc_opcodes
) / sizeof (powerpc_opcodes
[0]);
4006 /* The macro table. This is only used by the assembler. */
4008 /* The expressions of the form (-x ! 31) & (x | 31) have the value 0
4009 when x=0; 32-x when x is between 1 and 31; are negative if x is
4010 negative; and are 32 or more otherwise. This is what you want
4011 when, for instance, you are emulating a right shift by a
4012 rotate-left-and-mask, because the underlying instructions support
4013 shifts of size 0 but not shifts of size 32. By comparison, when
4014 extracting x bits from some word you want to use just 32-x, because
4015 the underlying instructions don't support extracting 0 bits but do
4016 support extracting the whole word (32 bits in this case). */
4018 const struct powerpc_macro powerpc_macros
[] = {
4019 { "extldi", 4, PPC64
, "rldicr %0,%1,%3,(%2)-1" },
4020 { "extldi.", 4, PPC64
, "rldicr. %0,%1,%3,(%2)-1" },
4021 { "extrdi", 4, PPC64
, "rldicl %0,%1,(%2)+(%3),64-(%2)" },
4022 { "extrdi.", 4, PPC64
, "rldicl. %0,%1,(%2)+(%3),64-(%2)" },
4023 { "insrdi", 4, PPC64
, "rldimi %0,%1,64-((%2)+(%3)),%3" },
4024 { "insrdi.", 4, PPC64
, "rldimi. %0,%1,64-((%2)+(%3)),%3" },
4025 { "rotrdi", 3, PPC64
, "rldicl %0,%1,(-(%2)!63)&((%2)|63),0" },
4026 { "rotrdi.", 3, PPC64
, "rldicl. %0,%1,(-(%2)!63)&((%2)|63),0" },
4027 { "sldi", 3, PPC64
, "rldicr %0,%1,%2,63-(%2)" },
4028 { "sldi.", 3, PPC64
, "rldicr. %0,%1,%2,63-(%2)" },
4029 { "srdi", 3, PPC64
, "rldicl %0,%1,(-(%2)!63)&((%2)|63),%2" },
4030 { "srdi.", 3, PPC64
, "rldicl. %0,%1,(-(%2)!63)&((%2)|63),%2" },
4031 { "clrrdi", 3, PPC64
, "rldicr %0,%1,0,63-(%2)" },
4032 { "clrrdi.", 3, PPC64
, "rldicr. %0,%1,0,63-(%2)" },
4033 { "clrlsldi",4, PPC64
, "rldic %0,%1,%3,(%2)-(%3)" },
4034 { "clrlsldi.",4, PPC64
, "rldic. %0,%1,%3,(%2)-(%3)" },
4036 { "extlwi", 4, PPCCOM
, "rlwinm %0,%1,%3,0,(%2)-1" },
4037 { "extlwi.", 4, PPCCOM
, "rlwinm. %0,%1,%3,0,(%2)-1" },
4038 { "extrwi", 4, PPCCOM
, "rlwinm %0,%1,(%2)+(%3),32-(%2),31" },
4039 { "extrwi.", 4, PPCCOM
, "rlwinm. %0,%1,(%2)+(%3),32-(%2),31" },
4040 { "inslwi", 4, PPCCOM
, "rlwimi %0,%1,(-(%3)!31)&((%3)|31),%3,(%2)+(%3)-1" },
4041 { "inslwi.", 4, PPCCOM
, "rlwimi. %0,%1,(-(%3)!31)&((%3)|31),%3,(%2)+(%3)-1"},
4042 { "insrwi", 4, PPCCOM
, "rlwimi %0,%1,32-((%2)+(%3)),%3,(%2)+(%3)-1" },
4043 { "insrwi.", 4, PPCCOM
, "rlwimi. %0,%1,32-((%2)+(%3)),%3,(%2)+(%3)-1"},
4044 { "rotrwi", 3, PPCCOM
, "rlwinm %0,%1,(-(%2)!31)&((%2)|31),0,31" },
4045 { "rotrwi.", 3, PPCCOM
, "rlwinm. %0,%1,(-(%2)!31)&((%2)|31),0,31" },
4046 { "slwi", 3, PPCCOM
, "rlwinm %0,%1,%2,0,31-(%2)" },
4047 { "sli", 3, PWRCOM
, "rlinm %0,%1,%2,0,31-(%2)" },
4048 { "slwi.", 3, PPCCOM
, "rlwinm. %0,%1,%2,0,31-(%2)" },
4049 { "sli.", 3, PWRCOM
, "rlinm. %0,%1,%2,0,31-(%2)" },
4050 { "srwi", 3, PPCCOM
, "rlwinm %0,%1,(-(%2)!31)&((%2)|31),%2,31" },
4051 { "sri", 3, PWRCOM
, "rlinm %0,%1,(-(%2)!31)&((%2)|31),%2,31" },
4052 { "srwi.", 3, PPCCOM
, "rlwinm. %0,%1,(-(%2)!31)&((%2)|31),%2,31" },
4053 { "sri.", 3, PWRCOM
, "rlinm. %0,%1,(-(%2)!31)&((%2)|31),%2,31" },
4054 { "clrrwi", 3, PPCCOM
, "rlwinm %0,%1,0,0,31-(%2)" },
4055 { "clrrwi.", 3, PPCCOM
, "rlwinm. %0,%1,0,0,31-(%2)" },
4056 { "clrlslwi",4, PPCCOM
, "rlwinm %0,%1,%3,(%2)-(%3),31-(%3)" },
4057 { "clrlslwi.",4, PPCCOM
, "rlwinm. %0,%1,%3,(%2)-(%3),31-(%3)" },
4061 const int powerpc_num_macros
=
4062 sizeof (powerpc_macros
) / sizeof (powerpc_macros
[0]);