1 /* ppc-opc.c -- PowerPC opcode list
2 Copyright (C) 1994-2018 Free Software Foundation, Inc.
3 Written by Ian Lance Taylor, Cygnus Support
5 This file is part of the GNU opcodes library.
7 This library is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3, or (at your option)
12 It is distributed in the hope that it will be useful, but WITHOUT
13 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
14 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
15 License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this file; see the file COPYING. If not, write to the
19 Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston,
20 MA 02110-1301, USA. */
24 #include "opcode/ppc.h"
27 /* This file holds the PowerPC opcode table. The opcode table
28 includes almost all of the extended instruction mnemonics. This
29 permits the disassembler to use them, and simplifies the assembler
30 logic, at the cost of increasing the table size. The table is
31 strictly constant data, so the compiler should be able to put it in
34 This file also holds the operand table. All knowledge about
35 inserting operands into instructions and vice-versa is kept in this
38 /* The functions used to insert and extract complicated operands. */
40 /* The ARX, ARY, RX and RY operands are alternate encodings of GPRs. */
43 insert_arx (uint64_t insn
,
45 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
46 const char **errmsg ATTRIBUTE_UNUSED
)
48 if (value
>= 8 && value
< 24)
49 return insn
| ((value
- 8) & 0xf);
52 *errmsg
= _("invalid register");
58 extract_arx (uint64_t insn
,
59 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
60 int *invalid ATTRIBUTE_UNUSED
)
62 return (insn
& 0xf) + 8;
66 insert_ary (uint64_t insn
,
68 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
69 const char **errmsg ATTRIBUTE_UNUSED
)
71 if (value
>= 8 && value
< 24)
72 return insn
| (((value
- 8) & 0xf) << 4);
75 *errmsg
= _("invalid register");
81 extract_ary (uint64_t insn
,
82 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
83 int *invalid ATTRIBUTE_UNUSED
)
85 return ((insn
>> 4) & 0xf) + 8;
89 insert_rx (uint64_t insn
,
91 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
94 if (value
>= 0 && value
< 8)
96 else if (value
>= 24 && value
<= 31)
97 return insn
| (value
- 16);
100 *errmsg
= _("invalid register");
106 extract_rx (uint64_t insn
,
107 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
108 int *invalid ATTRIBUTE_UNUSED
)
110 int64_t value
= insn
& 0xf;
111 if (value
>= 0 && value
< 8)
118 insert_ry (uint64_t insn
,
120 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
123 if (value
>= 0 && value
< 8)
124 return insn
| (value
<< 4);
125 else if (value
>= 24 && value
<= 31)
126 return insn
| ((value
- 16) << 4);
129 *errmsg
= _("invalid register");
135 extract_ry (uint64_t insn
,
136 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
137 int *invalid ATTRIBUTE_UNUSED
)
139 int64_t value
= (insn
>> 4) & 0xf;
140 if (value
>= 0 && value
< 8)
146 /* The BA and BB fields in an XL form instruction or the RA and RB fields or
147 VRA and VRB fields in a VX form instruction when they must be the same.
148 This is used for extended mnemonics like crclr. The extraction function
149 enforces that the fields are the same. */
152 insert_bab (uint64_t insn
,
154 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
155 const char **errmsg ATTRIBUTE_UNUSED
)
158 return insn
| (value
<< 16) | (value
<< 11);
162 extract_bab (uint64_t insn
,
163 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
166 int64_t ba
= (insn
>> 16) & 0x1f;
167 int64_t bb
= (insn
>> 11) & 0x1f;
174 /* The BT, BA and BB fields in an XL form instruction when they must all be
175 the same. This is used for extended mnemonics like crclr. The extraction
176 function enforces that the fields are the same. */
179 insert_btab (uint64_t insn
,
185 return (value
<< 21) | insert_bab (insn
, value
, dialect
, errmsg
);
189 extract_btab (uint64_t insn
,
193 int64_t bt
= (insn
>> 21) & 0x1f;
194 int64_t bab
= extract_bab (insn
, dialect
, invalid
);
201 /* The BD field in a B form instruction when the - modifier is used.
202 This modifier means that the branch is not expected to be taken.
203 For chips built to versions of the architecture prior to version 2
204 (ie. not Power4 compatible), we set the y bit of the BO field to 1
205 if the offset is negative. When extracting, we require that the y
206 bit be 1 and that the offset be positive, since if the y bit is 0
207 we just want to print the normal form of the instruction.
208 Power4 compatible targets use two bits, "a", and "t", instead of
209 the "y" bit. "at" == 00 => no hint, "at" == 01 => unpredictable,
210 "at" == 10 => not taken, "at" == 11 => taken. The "t" bit is 00001
211 in BO field, the "a" bit is 00010 for branch on CR(BI) and 01000
212 for branch on CTR. We only handle the taken/not-taken hint here.
213 Note that we don't relax the conditions tested here when
214 disassembling with -Many because insns using extract_bdm and
215 extract_bdp always occur in pairs. One or the other will always
218 #define ISA_V2 (PPC_OPCODE_POWER4 | PPC_OPCODE_E500MC | PPC_OPCODE_TITAN)
221 insert_bdm (uint64_t insn
,
224 const char **errmsg ATTRIBUTE_UNUSED
)
226 if ((dialect
& ISA_V2
) == 0)
228 if ((value
& 0x8000) != 0)
233 if ((insn
& (0x14 << 21)) == (0x04 << 21))
235 else if ((insn
& (0x14 << 21)) == (0x10 << 21))
238 return insn
| (value
& 0xfffc);
242 extract_bdm (uint64_t insn
,
246 if ((dialect
& ISA_V2
) == 0)
248 if (((insn
& (1 << 21)) == 0) != ((insn
& (1 << 15)) == 0))
253 if ((insn
& (0x17 << 21)) != (0x06 << 21)
254 && (insn
& (0x1d << 21)) != (0x18 << 21))
258 return ((insn
& 0xfffc) ^ 0x8000) - 0x8000;
261 /* The BD field in a B form instruction when the + modifier is used.
262 This is like BDM, above, except that the branch is expected to be
266 insert_bdp (uint64_t insn
,
269 const char **errmsg ATTRIBUTE_UNUSED
)
271 if ((dialect
& ISA_V2
) == 0)
273 if ((value
& 0x8000) == 0)
278 if ((insn
& (0x14 << 21)) == (0x04 << 21))
280 else if ((insn
& (0x14 << 21)) == (0x10 << 21))
283 return insn
| (value
& 0xfffc);
287 extract_bdp (uint64_t insn
,
291 if ((dialect
& ISA_V2
) == 0)
293 if (((insn
& (1 << 21)) == 0) == ((insn
& (1 << 15)) == 0))
298 if ((insn
& (0x17 << 21)) != (0x07 << 21)
299 && (insn
& (0x1d << 21)) != (0x19 << 21))
303 return ((insn
& 0xfffc) ^ 0x8000) - 0x8000;
307 valid_bo_pre_v2 (int64_t value
)
309 /* Certain encodings have bits that are required to be zero.
310 These are (z must be zero, y may be anything):
321 if ((value
& 0x14) == 0)
323 else if ((value
& 0x14) == 0x4)
324 return (value
& 0x2) == 0;
325 else if ((value
& 0x14) == 0x10)
326 return (value
& 0x8) == 0;
328 return value
== 0x14;
332 valid_bo_post_v2 (int64_t value
)
334 /* Certain encodings have bits that are required to be zero.
335 These are (z must be zero, a & t may be anything):
346 if ((value
& 0x14) == 0)
347 return (value
& 0x1) == 0;
348 else if ((value
& 0x14) == 0x14)
349 return value
== 0x14;
354 /* Check for legal values of a BO field. */
357 valid_bo (int64_t value
, ppc_cpu_t dialect
, int extract
)
359 int valid_y
= valid_bo_pre_v2 (value
);
360 int valid_at
= valid_bo_post_v2 (value
);
362 /* When disassembling with -Many, accept either encoding on the
363 second pass through opcodes. */
364 if (extract
&& dialect
== ~(ppc_cpu_t
) PPC_OPCODE_ANY
)
365 return valid_y
|| valid_at
;
366 if ((dialect
& ISA_V2
) == 0)
372 /* The BO field in a B form instruction. Warn about attempts to set
373 the field to an illegal value. */
376 insert_bo (uint64_t insn
,
381 if (!valid_bo (value
, dialect
, 0))
382 *errmsg
= _("invalid conditional option");
383 else if (PPC_OP (insn
) == 19 && (insn
& 0x400) && ! (value
& 4))
384 *errmsg
= _("invalid counter access");
385 return insn
| ((value
& 0x1f) << 21);
389 extract_bo (uint64_t insn
,
393 int64_t value
= (insn
>> 21) & 0x1f;
394 if (!valid_bo (value
, dialect
, 1))
399 /* The BO field in a B form instruction when the + or - modifier is
400 used. This is like the BO field, but it must be even. When
401 extracting it, we force it to be even. */
404 insert_boe (uint64_t insn
,
409 if (!valid_bo (value
, dialect
, 0))
410 *errmsg
= _("invalid conditional option");
411 else if (PPC_OP (insn
) == 19 && (insn
& 0x400) && ! (value
& 4))
412 *errmsg
= _("invalid counter access");
413 else if ((value
& 1) != 0)
414 *errmsg
= _("attempt to set y bit when using + or - modifier");
416 return insn
| ((value
& 0x1f) << 21);
420 extract_boe (uint64_t insn
,
424 int64_t value
= (insn
>> 21) & 0x1f;
425 if (!valid_bo (value
, dialect
, 1))
430 /* The DCMX field in a X form instruction when the field is split
431 into separate DC, DM and DX fields. */
434 insert_dcmxs (uint64_t insn
,
436 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
437 const char **errmsg ATTRIBUTE_UNUSED
)
440 | ((value
& 0x1f) << 16)
441 | ((value
& 0x20) >> 3)
446 extract_dcmxs (uint64_t insn
,
447 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
448 int *invalid ATTRIBUTE_UNUSED
)
450 return (insn
& 0x40) | ((insn
<< 3) & 0x20) | ((insn
>> 16) & 0x1f);
453 /* The D field in a DX form instruction when the field is split
454 into separate D0, D1 and D2 fields. */
457 insert_dxd (uint64_t insn
,
459 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
460 const char **errmsg ATTRIBUTE_UNUSED
)
462 return insn
| (value
& 0xffc1) | ((value
& 0x3e) << 15);
466 extract_dxd (uint64_t insn
,
467 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
468 int *invalid ATTRIBUTE_UNUSED
)
470 uint64_t dxd
= (insn
& 0xffc1) | ((insn
>> 15) & 0x3e);
471 return (dxd
^ 0x8000) - 0x8000;
475 insert_dxdn (uint64_t insn
,
477 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
478 const char **errmsg ATTRIBUTE_UNUSED
)
480 return insert_dxd (insn
, -value
, dialect
, errmsg
);
484 extract_dxdn (uint64_t insn
,
485 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
486 int *invalid ATTRIBUTE_UNUSED
)
488 return -extract_dxd (insn
, dialect
, invalid
);
491 /* FXM mask in mfcr and mtcrf instructions. */
494 insert_fxm (uint64_t insn
,
499 /* If we're handling the mfocrf and mtocrf insns ensure that exactly
500 one bit of the mask field is set. */
501 if ((insn
& (1 << 20)) != 0)
503 if (value
== 0 || (value
& -value
) != value
)
505 *errmsg
= _("invalid mask field");
510 /* If only one bit of the FXM field is set, we can use the new form
511 of the instruction, which is faster. Unlike the Power4 branch hint
512 encoding, this is not backward compatible. Do not generate the
513 new form unless -mpower4 has been given, or -many and the two
514 operand form of mfcr was used. */
516 && (value
& -value
) == value
517 && ((dialect
& PPC_OPCODE_POWER4
) != 0
518 || ((dialect
& PPC_OPCODE_ANY
) != 0
519 && (insn
& (0x3ff << 1)) == 19 << 1)))
522 /* Any other value on mfcr is an error. */
523 else if ((insn
& (0x3ff << 1)) == 19 << 1)
525 /* A value of -1 means we used the one operand form of
526 mfcr which is valid. */
528 *errmsg
= _("invalid mfcr mask");
532 return insn
| ((value
& 0xff) << 12);
536 extract_fxm (uint64_t insn
,
537 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
540 int64_t mask
= (insn
>> 12) & 0xff;
542 /* Is this a Power4 insn? */
543 if ((insn
& (1 << 20)) != 0)
545 /* Exactly one bit of MASK should be set. */
546 if (mask
== 0 || (mask
& -mask
) != mask
)
550 /* Check that non-power4 form of mfcr has a zero MASK. */
551 else if ((insn
& (0x3ff << 1)) == 19 << 1)
563 insert_li20 (uint64_t insn
,
565 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
566 const char **errmsg ATTRIBUTE_UNUSED
)
569 | ((value
& 0xf0000) >> 5)
570 | ((value
& 0x0f800) << 5)
575 extract_li20 (uint64_t insn
,
576 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
577 int *invalid ATTRIBUTE_UNUSED
)
579 return ((((insn
<< 5) & 0xf0000)
580 | ((insn
>> 5) & 0xf800)
581 | (insn
& 0x7ff)) ^ 0x80000) - 0x80000;
584 /* The 2-bit L field in a SYNC or WC field in a WAIT instruction.
585 For SYNC, some L values are reserved:
586 * Value 3 is reserved on newer server cpus.
587 * Values 2 and 3 are reserved on all other cpus. */
590 insert_ls (uint64_t insn
,
595 /* For SYNC, some L values are illegal. */
596 if (((insn
>> 1) & 0x3ff) == 598)
598 int64_t max_lvalue
= (dialect
& PPC_OPCODE_POWER4
) ? 2 : 1;
599 if (value
> max_lvalue
)
601 *errmsg
= _("illegal L operand value");
606 return insn
| ((value
& 0x3) << 21);
610 extract_ls (uint64_t insn
,
614 uint64_t lvalue
= (insn
>> 21) & 3;
616 if (((insn
>> 1) & 0x3ff) == 598)
618 uint64_t max_lvalue
= (dialect
& PPC_OPCODE_POWER4
) ? 2 : 1;
619 if (lvalue
> max_lvalue
)
625 /* The 4-bit E field in a sync instruction that accepts 2 operands.
626 If ESYNC is non-zero, then the L field must be either 0 or 1 and
627 the complement of ESYNC-bit2. */
630 insert_esync (uint64_t insn
,
635 uint64_t ls
= (insn
>> 21) & 0x03;
639 if (((dialect
& PPC_OPCODE_E6500
) != 0 && ls
> 1)
640 || ((dialect
& PPC_OPCODE_POWER9
) != 0 && ls
> 2))
641 *errmsg
= _("illegal L operand value");
646 || (((value
>> 1) & 0x1) ^ ls
) == 0)
647 *errmsg
= _("incompatible L operand value");
649 return insn
| ((value
& 0xf) << 16);
653 extract_esync (uint64_t insn
,
657 uint64_t ls
= (insn
>> 21) & 0x3;
658 uint64_t lvalue
= (insn
>> 16) & 0xf;
662 if (((dialect
& PPC_OPCODE_E6500
) != 0 && ls
> 1)
663 || ((dialect
& PPC_OPCODE_POWER9
) != 0 && ls
> 2))
667 || (((lvalue
>> 1) & 0x1) ^ ls
) == 0)
673 /* The MB and ME fields in an M form instruction expressed as a single
674 operand which is itself a bitmask. The extraction function always
675 marks it as invalid, since we never want to recognize an
676 instruction which uses a field of this type. */
679 insert_mbe (uint64_t insn
,
681 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
685 long mb
, me
, mx
, count
, last
;
691 *errmsg
= _("illegal bitmask");
703 /* mb: location of last 0->1 transition */
704 /* me: location of last 1->0 transition */
705 /* count: # transitions */
707 for (mx
= 0, mask
= (uint64_t) 1 << 31; mx
< 32; ++mx
, mask
>>= 1)
709 if ((uval
& mask
) && !last
)
715 else if (!(uval
& mask
) && last
)
725 if (count
!= 2 && (count
!= 0 || ! last
))
726 *errmsg
= _("illegal bitmask");
728 return insn
| (mb
<< 6) | ((me
- 1) << 1);
732 extract_mbe (uint64_t insn
,
733 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
742 mb
= (insn
>> 6) & 0x1f;
743 me
= (insn
>> 1) & 0x1f;
747 for (i
= mb
; i
<= me
; i
++)
748 ret
|= (uint64_t) 1 << (31 - i
);
750 else if (mb
== me
+ 1)
752 else /* (mb > me + 1) */
755 for (i
= me
+ 1; i
< mb
; i
++)
756 ret
&= ~((uint64_t) 1 << (31 - i
));
761 /* The MB or ME field in an MD or MDS form instruction. The high bit
762 is wrapped to the low end. */
765 insert_mb6 (uint64_t insn
,
767 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
768 const char **errmsg ATTRIBUTE_UNUSED
)
770 return insn
| ((value
& 0x1f) << 6) | (value
& 0x20);
774 extract_mb6 (uint64_t insn
,
775 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
776 int *invalid ATTRIBUTE_UNUSED
)
778 return ((insn
>> 6) & 0x1f) | (insn
& 0x20);
781 /* The NB field in an X form instruction. The value 32 is stored as
785 extract_nb (uint64_t insn
,
786 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
787 int *invalid ATTRIBUTE_UNUSED
)
791 ret
= (insn
>> 11) & 0x1f;
797 /* The NB field in an lswi instruction, which has special value
798 restrictions. The value 32 is stored as 0. */
801 insert_nbi (uint64_t insn
,
803 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
804 const char **errmsg ATTRIBUTE_UNUSED
)
806 int64_t rtvalue
= (insn
>> 21) & 0x1f;
807 int64_t ravalue
= (insn
>> 16) & 0x1f;
811 if (rtvalue
+ (value
+ 3) / 4 > (rtvalue
> ravalue
? ravalue
+ 32
813 *errmsg
= _("address register in load range");
814 return insn
| ((value
& 0x1f) << 11);
817 /* The NSI field in a D form instruction. This is the same as the SI
818 field, only negated. The extraction function always marks it as
819 invalid, since we never want to recognize an instruction which uses
820 a field of this type. */
823 insert_nsi (uint64_t insn
,
825 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
826 const char **errmsg ATTRIBUTE_UNUSED
)
828 return insn
| (-value
& 0xffff);
832 extract_nsi (uint64_t insn
,
833 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
837 return -(((insn
& 0xffff) ^ 0x8000) - 0x8000);
840 /* The RA field in a D or X form instruction which is an updating
841 load, which means that the RA field may not be zero and may not
842 equal the RT field. */
845 insert_ral (uint64_t insn
,
847 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
851 || (uint64_t) value
== ((insn
>> 21) & 0x1f))
852 *errmsg
= "invalid register operand when updating";
853 return insn
| ((value
& 0x1f) << 16);
857 extract_ral (uint64_t insn
,
858 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
861 int64_t rtvalue
= (insn
>> 21) & 0x1f;
862 int64_t ravalue
= (insn
>> 16) & 0x1f;
864 if (rtvalue
== ravalue
|| ravalue
== 0)
869 /* The RA field in an lmw instruction, which has special value
873 insert_ram (uint64_t insn
,
875 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
878 if ((uint64_t) value
>= ((insn
>> 21) & 0x1f))
879 *errmsg
= _("index register in load range");
880 return insn
| ((value
& 0x1f) << 16);
884 extract_ram (uint64_t insn
,
885 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
888 uint64_t rtvalue
= (insn
>> 21) & 0x1f;
889 uint64_t ravalue
= (insn
>> 16) & 0x1f;
891 if (ravalue
>= rtvalue
)
896 /* The RA field in the DQ form lq or an lswx instruction, which have special
897 value restrictions. */
900 insert_raq (uint64_t insn
,
902 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
905 int64_t rtvalue
= (insn
>> 21) & 0x1f;
907 if (value
== rtvalue
)
908 *errmsg
= _("source and target register operands must be different");
909 return insn
| ((value
& 0x1f) << 16);
913 extract_raq (uint64_t insn
,
914 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
917 uint64_t rtvalue
= (insn
>> 21) & 0x1f;
918 uint64_t ravalue
= (insn
>> 16) & 0x1f;
920 if (ravalue
== rtvalue
)
925 /* The RA field in a D or X form instruction which is an updating
926 store or an updating floating point load, which means that the RA
927 field may not be zero. */
930 insert_ras (uint64_t insn
,
932 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
936 *errmsg
= _("invalid register operand when updating");
937 return insn
| ((value
& 0x1f) << 16);
941 extract_ras (uint64_t insn
,
942 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
945 uint64_t ravalue
= (insn
>> 16) & 0x1f;
952 /* The RS and RB fields in an X form instruction when they must be the same.
953 This is used for extended mnemonics like mr. The extraction function
954 enforces that the fields are the same. */
957 insert_rsb (uint64_t insn
,
959 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
960 const char **errmsg ATTRIBUTE_UNUSED
)
963 return insn
| (value
<< 21) | (value
<< 11);
967 extract_rsb (uint64_t insn
,
968 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
971 int64_t rs
= (insn
>> 21) & 0x1f;
972 int64_t rb
= (insn
>> 11) & 0x1f;
979 /* The RB field in an lswx instruction, which has special value
983 insert_rbx (uint64_t insn
,
985 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
988 int64_t rtvalue
= (insn
>> 21) & 0x1f;
990 if (value
== rtvalue
)
991 *errmsg
= _("source and target register operands must be different");
992 return insn
| ((value
& 0x1f) << 11);
996 extract_rbx (uint64_t insn
,
997 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1000 uint64_t rtvalue
= (insn
>> 21) & 0x1f;
1001 uint64_t rbvalue
= (insn
>> 11) & 0x1f;
1003 if (rbvalue
== rtvalue
)
1008 /* The SCI8 field is made up of SCL and {U,N}I8 fields. */
1010 insert_sci8 (uint64_t insn
,
1012 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1013 const char **errmsg
)
1015 uint64_t fill_scale
= 0;
1016 uint64_t ui8
= value
;
1018 if ((ui8
& 0xffffff00) == 0)
1020 else if ((ui8
& 0xffffff00) == 0xffffff00)
1022 else if ((ui8
& 0xffff00ff) == 0)
1024 fill_scale
= 1 << 8;
1027 else if ((ui8
& 0xffff00ff) == 0xffff00ff)
1029 fill_scale
= 0x400 | (1 << 8);
1032 else if ((ui8
& 0xff00ffff) == 0)
1034 fill_scale
= 2 << 8;
1037 else if ((ui8
& 0xff00ffff) == 0xff00ffff)
1039 fill_scale
= 0x400 | (2 << 8);
1042 else if ((ui8
& 0x00ffffff) == 0)
1044 fill_scale
= 3 << 8;
1047 else if ((ui8
& 0x00ffffff) == 0x00ffffff)
1049 fill_scale
= 0x400 | (3 << 8);
1054 *errmsg
= _("illegal immediate value");
1058 return insn
| fill_scale
| (ui8
& 0xff);
1062 extract_sci8 (uint64_t insn
,
1063 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1064 int *invalid ATTRIBUTE_UNUSED
)
1066 int64_t fill
= insn
& 0x400;
1067 int64_t scale_factor
= (insn
& 0x300) >> 5;
1068 int64_t value
= (insn
& 0xff) << scale_factor
;
1071 value
|= ~((int64_t) 0xff << scale_factor
);
1076 insert_sci8n (uint64_t insn
,
1079 const char **errmsg
)
1081 return insert_sci8 (insn
, -value
, dialect
, errmsg
);
1085 extract_sci8n (uint64_t insn
,
1089 return -extract_sci8 (insn
, dialect
, invalid
);
1093 insert_sd4h (uint64_t insn
,
1095 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1096 const char **errmsg ATTRIBUTE_UNUSED
)
1098 return insn
| ((value
& 0x1e) << 7);
1102 extract_sd4h (uint64_t insn
,
1103 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1104 int *invalid ATTRIBUTE_UNUSED
)
1106 return ((insn
>> 8) & 0xf) << 1;
1110 insert_sd4w (uint64_t insn
,
1112 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1113 const char **errmsg ATTRIBUTE_UNUSED
)
1115 return insn
| ((value
& 0x3c) << 6);
1119 extract_sd4w (uint64_t insn
,
1120 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1121 int *invalid ATTRIBUTE_UNUSED
)
1123 return ((insn
>> 8) & 0xf) << 2;
1127 insert_oimm (uint64_t insn
,
1129 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1130 const char **errmsg ATTRIBUTE_UNUSED
)
1132 return insn
| (((value
- 1) & 0x1f) << 4);
1136 extract_oimm (uint64_t insn
,
1137 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1138 int *invalid ATTRIBUTE_UNUSED
)
1140 return ((insn
>> 4) & 0x1f) + 1;
1143 /* The SH field in an MD form instruction. This is split. */
1146 insert_sh6 (uint64_t insn
,
1148 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1149 const char **errmsg ATTRIBUTE_UNUSED
)
1151 /* SH6 operand in the rldixor instructions. */
1152 if (PPC_OP (insn
) == 4)
1153 return insn
| ((value
& 0x1f) << 6) | ((value
& 0x20) >> 5);
1155 return insn
| ((value
& 0x1f) << 11) | ((value
& 0x20) >> 4);
1159 extract_sh6 (uint64_t insn
,
1160 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1161 int *invalid ATTRIBUTE_UNUSED
)
1163 /* SH6 operand in the rldixor instructions. */
1164 if (PPC_OP (insn
) == 4)
1165 return ((insn
>> 6) & 0x1f) | ((insn
<< 5) & 0x20);
1167 return ((insn
>> 11) & 0x1f) | ((insn
<< 4) & 0x20);
1170 /* The SPR field in an XFX form instruction. This is flipped--the
1171 lower 5 bits are stored in the upper 5 and vice- versa. */
1174 insert_spr (uint64_t insn
,
1176 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1177 const char **errmsg ATTRIBUTE_UNUSED
)
1179 return insn
| ((value
& 0x1f) << 16) | ((value
& 0x3e0) << 6);
1183 extract_spr (uint64_t insn
,
1184 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1185 int *invalid ATTRIBUTE_UNUSED
)
1187 return ((insn
>> 16) & 0x1f) | ((insn
>> 6) & 0x3e0);
1190 /* Some dialects have 8 SPRG registers instead of the standard 4. */
1191 #define ALLOW8_SPRG (PPC_OPCODE_BOOKE | PPC_OPCODE_405)
1194 insert_sprg (uint64_t insn
,
1197 const char **errmsg
)
1200 || (value
> 3 && (dialect
& ALLOW8_SPRG
) == 0))
1201 *errmsg
= _("invalid sprg number");
1203 /* If this is mfsprg4..7 then use spr 260..263 which can be read in
1204 user mode. Anything else must use spr 272..279. */
1205 if (value
<= 3 || (insn
& 0x100) != 0)
1208 return insn
| ((value
& 0x17) << 16);
1212 extract_sprg (uint64_t insn
,
1216 uint64_t val
= (insn
>> 16) & 0x1f;
1218 /* mfsprg can use 260..263 and 272..279. mtsprg only uses spr 272..279
1219 If not BOOKE, 405 or VLE, then both use only 272..275. */
1220 if ((val
- 0x10 > 3 && (dialect
& ALLOW8_SPRG
) == 0)
1221 || (val
- 0x10 > 7 && (insn
& 0x100) != 0)
1228 /* The TBR field in an XFX instruction. This is just like SPR, but it
1232 insert_tbr (uint64_t insn
,
1234 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1235 const char **errmsg
)
1237 if (value
!= 268 && value
!= 269)
1238 *errmsg
= _("invalid tbr number");
1239 return insn
| ((value
& 0x1f) << 16) | ((value
& 0x3e0) << 6);
1243 extract_tbr (uint64_t insn
,
1244 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1247 int64_t ret
= ((insn
>> 16) & 0x1f) | ((insn
>> 6) & 0x3e0);
1248 if (ret
!= 268 && ret
!= 269)
1253 /* The XT and XS fields in an XX1 or XX3 form instruction. This is split. */
1256 insert_xt6 (uint64_t insn
,
1258 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1259 const char **errmsg ATTRIBUTE_UNUSED
)
1261 return insn
| ((value
& 0x1f) << 21) | ((value
& 0x20) >> 5);
1265 extract_xt6 (uint64_t insn
,
1266 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1267 int *invalid ATTRIBUTE_UNUSED
)
1269 return ((insn
<< 5) & 0x20) | ((insn
>> 21) & 0x1f);
1272 /* The XT and XS fields in an DQ form VSX instruction. This is split. */
1274 insert_xtq6 (uint64_t insn
,
1276 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1277 const char **errmsg ATTRIBUTE_UNUSED
)
1279 return insn
| ((value
& 0x1f) << 21) | ((value
& 0x20) >> 2);
1283 extract_xtq6 (uint64_t insn
,
1284 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1285 int *invalid ATTRIBUTE_UNUSED
)
1287 return ((insn
<< 2) & 0x20) | ((insn
>> 21) & 0x1f);
1290 /* The XA field in an XX3 form instruction. This is split. */
1293 insert_xa6 (uint64_t insn
,
1295 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1296 const char **errmsg ATTRIBUTE_UNUSED
)
1298 return insn
| ((value
& 0x1f) << 16) | ((value
& 0x20) >> 3);
1302 extract_xa6 (uint64_t insn
,
1303 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1304 int *invalid ATTRIBUTE_UNUSED
)
1306 return ((insn
<< 3) & 0x20) | ((insn
>> 16) & 0x1f);
1309 /* The XB field in an XX3 form instruction. This is split. */
1312 insert_xb6 (uint64_t insn
,
1314 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1315 const char **errmsg ATTRIBUTE_UNUSED
)
1317 return insn
| ((value
& 0x1f) << 11) | ((value
& 0x20) >> 4);
1321 extract_xb6 (uint64_t insn
,
1322 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1323 int *invalid ATTRIBUTE_UNUSED
)
1325 return ((insn
<< 4) & 0x20) | ((insn
>> 11) & 0x1f);
1328 /* The XA and XB fields in an XX3 form instruction when they must be the same.
1329 This is used for extended mnemonics like xvmovdp. The extraction function
1330 enforces that the fields are the same. */
1333 insert_xab6 (uint64_t insn
,
1336 const char **errmsg
)
1338 return insert_xa6 (insn
, value
, dialect
, errmsg
)
1339 | insert_xb6 (insn
, value
, dialect
, errmsg
);
1343 extract_xab6 (uint64_t insn
,
1347 int64_t xa6
= extract_xa6 (insn
, dialect
, invalid
);
1348 int64_t xb6
= extract_xb6 (insn
, dialect
, invalid
);
1355 /* The XC field in an XX4 form instruction. This is split. */
1358 insert_xc6 (uint64_t insn
,
1360 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1361 const char **errmsg ATTRIBUTE_UNUSED
)
1363 return insn
| ((value
& 0x1f) << 6) | ((value
& 0x20) >> 2);
1367 extract_xc6 (uint64_t insn
,
1368 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1369 int *invalid ATTRIBUTE_UNUSED
)
1371 return ((insn
<< 2) & 0x20) | ((insn
>> 6) & 0x1f);
1375 insert_dm (uint64_t insn
,
1377 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1378 const char **errmsg
)
1380 if (value
!= 0 && value
!= 1)
1381 *errmsg
= _("invalid constant");
1382 return insn
| (((value
) ? 3 : 0) << 8);
1386 extract_dm (uint64_t insn
,
1387 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1390 int64_t value
= (insn
>> 8) & 3;
1391 if (value
!= 0 && value
!= 3)
1393 return (value
) ? 1 : 0;
1396 /* The VLESIMM field in an I16A form instruction. This is split. */
1399 insert_vlesi (uint64_t insn
,
1401 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1402 const char **errmsg ATTRIBUTE_UNUSED
)
1404 return insn
| ((value
& 0xf800) << 10) | (value
& 0x7ff);
1408 extract_vlesi (uint64_t insn
,
1409 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1410 int *invalid ATTRIBUTE_UNUSED
)
1412 int64_t value
= ((insn
>> 10) & 0xf800) | (insn
& 0x7ff);
1413 value
= (value
^ 0x8000) - 0x8000;
1418 insert_vlensi (uint64_t insn
,
1420 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1421 const char **errmsg ATTRIBUTE_UNUSED
)
1424 return insn
| ((value
& 0xf800) << 10) | (value
& 0x7ff);
1427 extract_vlensi (uint64_t insn
,
1428 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1429 int *invalid ATTRIBUTE_UNUSED
)
1431 int64_t value
= ((insn
>> 10) & 0xf800) | (insn
& 0x7ff);
1432 value
= (value
^ 0x8000) - 0x8000;
1433 /* Don't use for disassembly. */
1438 /* The VLEUIMM field in an I16A form instruction. This is split. */
1441 insert_vleui (uint64_t insn
,
1443 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1444 const char **errmsg ATTRIBUTE_UNUSED
)
1446 return insn
| ((value
& 0xf800) << 10) | (value
& 0x7ff);
1450 extract_vleui (uint64_t insn
,
1451 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1452 int *invalid ATTRIBUTE_UNUSED
)
1454 return ((insn
>> 10) & 0xf800) | (insn
& 0x7ff);
1457 /* The VLEUIMML field in an I16L form instruction. This is split. */
1460 insert_vleil (uint64_t insn
,
1462 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1463 const char **errmsg ATTRIBUTE_UNUSED
)
1465 return insn
| ((value
& 0xf800) << 5) | (value
& 0x7ff);
1469 extract_vleil (uint64_t insn
,
1470 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1471 int *invalid ATTRIBUTE_UNUSED
)
1473 return ((insn
>> 5) & 0xf800) | (insn
& 0x7ff);
1477 insert_evuimm1_ex0 (uint64_t insn
,
1479 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1480 const char **errmsg
)
1482 if (value
> 0 && value
<= 0x1f)
1483 return insn
| ((value
& 0x1f) << 11);
1486 *errmsg
= _("UIMM = 00000 is illegal");
1492 extract_evuimm1_ex0 (uint64_t insn
,
1493 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1496 int64_t value
= ((insn
>> 11) & 0x1f);
1504 insert_evuimm2_ex0 (uint64_t insn
,
1506 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1507 const char **errmsg
)
1509 if (value
> 0 && value
<= 0x3e)
1510 return insn
| ((value
& 0x3e) << 10);
1513 *errmsg
= _("UIMM = 00000 is illegal");
1519 extract_evuimm2_ex0 (uint64_t insn
,
1520 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1523 int64_t value
= ((insn
>> 10) & 0x3e);
1531 insert_evuimm4_ex0 (uint64_t insn
,
1533 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1534 const char **errmsg
)
1536 if (value
> 0 && value
<= 0x7c)
1537 return insn
| ((value
& 0x7c) << 9);
1540 *errmsg
= _("UIMM = 00000 is illegal");
1546 extract_evuimm4_ex0 (uint64_t insn
,
1547 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1550 int64_t value
= ((insn
>> 9) & 0x7c);
1558 insert_evuimm8_ex0 (uint64_t insn
,
1560 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1561 const char **errmsg
)
1563 if (value
> 0 && value
<= 0xf8)
1564 return insn
| ((value
& 0xf8) << 8);
1567 *errmsg
= _("UIMM = 00000 is illegal");
1573 extract_evuimm8_ex0 (uint64_t insn
,
1574 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1577 int64_t value
= ((insn
>> 8) & 0xf8);
1585 insert_evuimm_lt8 (uint64_t insn
,
1587 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1588 const char **errmsg
)
1590 if (value
>= 0 && value
<= 7)
1591 return insn
| ((value
& 0x7) << 11);
1594 *errmsg
= _("UIMM values >7 are illegal");
1600 extract_evuimm_lt8 (uint64_t insn
,
1601 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1604 int64_t value
= ((insn
>> 11) & 0x1f);
1612 insert_evuimm_lt16 (uint64_t insn
,
1614 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1615 const char **errmsg
)
1617 if (value
>= 0 && value
<= 15)
1618 return insn
| ((value
& 0xf) << 11);
1621 *errmsg
= _("UIMM values >15 are illegal");
1627 extract_evuimm_lt16 (uint64_t insn
,
1628 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1631 int64_t value
= ((insn
>> 11) & 0x1f);
1639 insert_rD_rS_even (uint64_t insn
,
1641 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1642 const char **errmsg
)
1644 if ((value
& 0x1) == 0)
1645 return insn
| ((value
& 0x1e) << 21);
1648 *errmsg
= _("GPR odd is illegal");
1654 extract_rD_rS_even (uint64_t insn
,
1655 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1658 int64_t value
= ((insn
>> 21) & 0x1f);
1659 if ((value
& 0x1) != 0)
1666 insert_off_lsp (uint64_t insn
,
1668 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1669 const char **errmsg
)
1671 if (value
> 0 && value
<= 0x3)
1672 return insn
| (value
& 0x3);
1675 *errmsg
= _("invalid offset");
1681 extract_off_lsp (uint64_t insn
,
1682 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1685 int64_t value
= (insn
& 0x3);
1693 insert_off_spe2 (uint64_t insn
,
1695 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1696 const char **errmsg
)
1698 if (value
> 0 && value
<= 0x7)
1699 return insn
| (value
& 0x7);
1702 *errmsg
= _("invalid offset");
1708 extract_off_spe2 (uint64_t insn
,
1709 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1712 int64_t value
= (insn
& 0x7);
1720 insert_Ddd (uint64_t insn
,
1722 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1723 const char **errmsg
)
1725 if (value
>= 0 && value
<= 0x7)
1726 return insn
| ((value
& 0x3) << 11) | ((value
& 0x4) >> 2);
1729 *errmsg
= _("invalid Ddd value");
1735 extract_Ddd (uint64_t insn
,
1736 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1737 int *invalid ATTRIBUTE_UNUSED
)
1739 return ((insn
>> 11) & 0x3) | ((insn
<< 2) & 0x4);
1742 /* The operands table.
1744 The fields are bitm, shift, insert, extract, flags.
1746 We used to put parens around the various additions, like the one
1747 for BA just below. However, that caused trouble with feeble
1748 compilers with a limit on depth of a parenthesized expression, like
1749 (reportedly) the compiler in Microsoft Developer Studio 5. So we
1750 omit the parens, since the macros are never used in a context where
1751 the addition will be ambiguous. */
1753 const struct powerpc_operand powerpc_operands
[] =
1755 /* The zero index is used to indicate the end of the list of
1758 { 0, 0, NULL
, NULL
, 0 },
1760 /* The BA field in an XL form instruction. */
1761 #define BA UNUSED + 1
1762 /* The BI field in a B form or XL form instruction. */
1764 #define BI_MASK (0x1f << 16)
1765 { 0x1f, 16, NULL
, NULL
, PPC_OPERAND_CR_BIT
},
1767 /* The BT, BA and BB fields in a XL form instruction when they must all
1770 { 0x1f, 21, insert_btab
, extract_btab
, PPC_OPERAND_CR_BIT
},
1772 /* The BB field in an XL form instruction. */
1774 #define BB_MASK (0x1f << 11)
1775 { 0x1f, 11, NULL
, NULL
, PPC_OPERAND_CR_BIT
},
1777 /* The BA and BB fields in a XL form instruction when they must be
1780 { 0x1f, 16, insert_bab
, extract_bab
, PPC_OPERAND_CR_BIT
},
1782 /* The VRA and VRB fields in a VX form instruction when they must be the same.
1783 This is used for extended mnemonics like vmr. */
1785 { 0x1f, 16, insert_bab
, extract_bab
, PPC_OPERAND_VR
},
1787 /* The RA and RB fields in a VX form instruction when they must be the same.
1788 This is used for extended mnemonics like evmr. */
1790 { 0x1f, 16, insert_bab
, extract_bab
, PPC_OPERAND_GPR
},
1792 /* The BD field in a B form instruction. The lower two bits are
1795 { 0xfffc, 0, NULL
, NULL
, PPC_OPERAND_RELATIVE
| PPC_OPERAND_SIGNED
},
1797 /* The BD field in a B form instruction when absolute addressing is
1800 { 0xfffc, 0, NULL
, NULL
, PPC_OPERAND_ABSOLUTE
| PPC_OPERAND_SIGNED
},
1802 /* The BD field in a B form instruction when the - modifier is used.
1803 This sets the y bit of the BO field appropriately. */
1805 { 0xfffc, 0, insert_bdm
, extract_bdm
,
1806 PPC_OPERAND_RELATIVE
| PPC_OPERAND_SIGNED
},
1808 /* The BD field in a B form instruction when the - modifier is used
1809 and absolute address is used. */
1810 #define BDMA BDM + 1
1811 { 0xfffc, 0, insert_bdm
, extract_bdm
,
1812 PPC_OPERAND_ABSOLUTE
| PPC_OPERAND_SIGNED
},
1814 /* The BD field in a B form instruction when the + modifier is used.
1815 This sets the y bit of the BO field appropriately. */
1816 #define BDP BDMA + 1
1817 { 0xfffc, 0, insert_bdp
, extract_bdp
,
1818 PPC_OPERAND_RELATIVE
| PPC_OPERAND_SIGNED
},
1820 /* The BD field in a B form instruction when the + modifier is used
1821 and absolute addressing is used. */
1822 #define BDPA BDP + 1
1823 { 0xfffc, 0, insert_bdp
, extract_bdp
,
1824 PPC_OPERAND_ABSOLUTE
| PPC_OPERAND_SIGNED
},
1826 /* The BF field in an X or XL form instruction. */
1828 /* The CRFD field in an X form instruction. */
1830 /* The CRD field in an XL form instruction. */
1832 { 0x7, 23, NULL
, NULL
, PPC_OPERAND_CR_REG
},
1834 /* The BF field in an X or XL form instruction. */
1836 { 0x7, 23, NULL
, NULL
, 0 },
1838 /* An optional BF field. This is used for comparison instructions,
1839 in which an omitted BF field is taken as zero. */
1841 { 0x7, 23, NULL
, NULL
, PPC_OPERAND_CR_REG
| PPC_OPERAND_OPTIONAL
},
1843 /* The BFA field in an X or XL form instruction. */
1845 { 0x7, 18, NULL
, NULL
, PPC_OPERAND_CR_REG
},
1847 /* The BO field in a B form instruction. Certain values are
1850 #define BO_MASK (0x1f << 21)
1851 { 0x1f, 21, insert_bo
, extract_bo
, 0 },
1853 /* The BO field in a B form instruction when the + or - modifier is
1854 used. This is like the BO field, but it must be even. */
1856 { 0x1e, 21, insert_boe
, extract_boe
, 0 },
1858 /* The RM field in an X form instruction. */
1861 { 0x3, 11, NULL
, NULL
, 0 },
1864 { 0x3, 11, NULL
, NULL
, PPC_OPERAND_OPTIONAL
},
1866 /* The BT field in an X or XL form instruction. */
1868 { 0x1f, 21, NULL
, NULL
, PPC_OPERAND_CR_BIT
},
1870 /* The BI16 field in a BD8 form instruction. */
1872 { 0x3, 8, NULL
, NULL
, PPC_OPERAND_CR_BIT
},
1874 /* The BI32 field in a BD15 form instruction. */
1875 #define BI32 BI16 + 1
1876 { 0xf, 16, NULL
, NULL
, PPC_OPERAND_CR_BIT
},
1878 /* The BO32 field in a BD15 form instruction. */
1879 #define BO32 BI32 + 1
1880 { 0x3, 20, NULL
, NULL
, 0 },
1882 /* The B8 field in a BD8 form instruction. */
1884 { 0x1fe, -1, NULL
, NULL
, PPC_OPERAND_RELATIVE
| PPC_OPERAND_SIGNED
},
1886 /* The B15 field in a BD15 form instruction. The lowest bit is
1889 { 0xfffe, 0, NULL
, NULL
, PPC_OPERAND_RELATIVE
| PPC_OPERAND_SIGNED
},
1891 /* The B24 field in a BD24 form instruction. The lowest bit is
1894 { 0x1fffffe, 0, NULL
, NULL
, PPC_OPERAND_RELATIVE
| PPC_OPERAND_SIGNED
},
1896 /* The condition register number portion of the BI field in a B form
1897 or XL form instruction. This is used for the extended
1898 conditional branch mnemonics, which set the lower two bits of the
1899 BI field. This field is optional. */
1901 { 0x7, 18, NULL
, NULL
, PPC_OPERAND_CR_REG
| PPC_OPERAND_OPTIONAL
},
1903 /* The CRB field in an X form instruction. */
1905 /* The MB field in an M form instruction. */
1907 #define MB_MASK (0x1f << 6)
1908 { 0x1f, 6, NULL
, NULL
, 0 },
1910 /* The CRD32 field in an XL form instruction. */
1911 #define CRD32 CRB + 1
1912 { 0x3, 21, NULL
, NULL
, PPC_OPERAND_CR_REG
},
1914 /* The CRFS field in an X form instruction. */
1915 #define CRFS CRD32 + 1
1916 { 0x7, 0, NULL
, NULL
, PPC_OPERAND_CR_REG
},
1918 #define CRS CRFS + 1
1919 { 0x3, 18, NULL
, NULL
, PPC_OPERAND_CR_REG
| PPC_OPERAND_OPTIONAL
},
1921 /* The CT field in an X form instruction. */
1923 /* The MO field in an mbar instruction. */
1925 { 0x1f, 21, NULL
, NULL
, PPC_OPERAND_OPTIONAL
},
1927 /* The D field in a D form instruction. This is a displacement off
1928 a register, and implies that the next operand is a register in
1931 { 0xffff, 0, NULL
, NULL
, PPC_OPERAND_PARENS
| PPC_OPERAND_SIGNED
},
1933 /* The D8 field in a D form instruction. This is a displacement off
1934 a register, and implies that the next operand is a register in
1937 { 0xff, 0, NULL
, NULL
, PPC_OPERAND_PARENS
| PPC_OPERAND_SIGNED
},
1939 /* The DCMX field in an X form instruction. */
1941 { 0x7f, 16, NULL
, NULL
, 0 },
1943 /* The split DCMX field in an X form instruction. */
1944 #define DCMXS DCMX + 1
1945 { 0x7f, PPC_OPSHIFT_INV
, insert_dcmxs
, extract_dcmxs
, 0 },
1947 /* The DQ field in a DQ form instruction. This is like D, but the
1948 lower four bits are forced to zero. */
1949 #define DQ DCMXS + 1
1950 { 0xfff0, 0, NULL
, NULL
,
1951 PPC_OPERAND_PARENS
| PPC_OPERAND_SIGNED
| PPC_OPERAND_DQ
},
1953 /* The DS field in a DS form instruction. This is like D, but the
1954 lower two bits are forced to zero. */
1956 { 0xfffc, 0, NULL
, NULL
,
1957 PPC_OPERAND_PARENS
| PPC_OPERAND_SIGNED
| PPC_OPERAND_DS
},
1959 /* The DUIS or BHRBE fields in a XFX form instruction, 10 bits
1960 unsigned imediate */
1963 { 0x3ff, 11, NULL
, NULL
, 0 },
1965 /* The split D field in a DX form instruction. */
1966 #define DXD DUIS + 1
1967 { 0xffff, PPC_OPSHIFT_INV
, insert_dxd
, extract_dxd
,
1968 PPC_OPERAND_SIGNED
| PPC_OPERAND_SIGNOPT
},
1970 /* The split ND field in a DX form instruction.
1971 This is the same as the DX field, only negated. */
1972 #define NDXD DXD + 1
1973 { 0xffff, PPC_OPSHIFT_INV
, insert_dxdn
, extract_dxdn
,
1974 PPC_OPERAND_NEGATIVE
| PPC_OPERAND_SIGNED
| PPC_OPERAND_SIGNOPT
},
1976 /* The E field in a wrteei instruction. */
1977 /* And the W bit in the pair singles instructions. */
1978 /* And the ST field in a VX form instruction. */
1982 { 0x1, 15, NULL
, NULL
, 0 },
1984 /* The FL1 field in a POWER SC form instruction. */
1986 /* The U field in an X form instruction. */
1988 { 0xf, 12, NULL
, NULL
, 0 },
1990 /* The FL2 field in a POWER SC form instruction. */
1992 { 0x7, 2, NULL
, NULL
, 0 },
1994 /* The FLM field in an XFL form instruction. */
1996 { 0xff, 17, NULL
, NULL
, 0 },
1998 /* The FRA field in an X or A form instruction. */
2000 #define FRA_MASK (0x1f << 16)
2001 { 0x1f, 16, NULL
, NULL
, PPC_OPERAND_FPR
},
2003 /* The FRAp field of DFP instructions. */
2004 #define FRAp FRA + 1
2005 { 0x1e, 16, NULL
, NULL
, PPC_OPERAND_FPR
},
2007 /* The FRB field in an X or A form instruction. */
2008 #define FRB FRAp + 1
2009 #define FRB_MASK (0x1f << 11)
2010 { 0x1f, 11, NULL
, NULL
, PPC_OPERAND_FPR
},
2012 /* The FRBp field of DFP instructions. */
2013 #define FRBp FRB + 1
2014 { 0x1e, 11, NULL
, NULL
, PPC_OPERAND_FPR
},
2016 /* The FRC field in an A form instruction. */
2017 #define FRC FRBp + 1
2018 #define FRC_MASK (0x1f << 6)
2019 { 0x1f, 6, NULL
, NULL
, PPC_OPERAND_FPR
},
2021 /* The FRS field in an X form instruction or the FRT field in a D, X
2022 or A form instruction. */
2025 { 0x1f, 21, NULL
, NULL
, PPC_OPERAND_FPR
},
2027 /* The FRSp field of stfdp or the FRTp field of lfdp and DFP
2029 #define FRSp FRS + 1
2031 { 0x1e, 21, NULL
, NULL
, PPC_OPERAND_FPR
},
2033 /* The FXM field in an XFX instruction. */
2034 #define FXM FRSp + 1
2035 { 0xff, 12, insert_fxm
, extract_fxm
, 0 },
2037 /* Power4 version for mfcr. */
2038 #define FXM4 FXM + 1
2039 { 0xff, 12, insert_fxm
, extract_fxm
,
2040 PPC_OPERAND_OPTIONAL
| PPC_OPERAND_OPTIONAL_VALUE
},
2041 /* If the FXM4 operand is ommitted, use the sentinel value -1. */
2042 { -1, -1, NULL
, NULL
, 0},
2044 /* The IMM20 field in an LI instruction. */
2045 #define IMM20 FXM4 + 2
2046 { 0xfffff, PPC_OPSHIFT_INV
, insert_li20
, extract_li20
, PPC_OPERAND_SIGNED
},
2048 /* The L field in a D or X form instruction. */
2050 { 0x1, 21, NULL
, NULL
, 0 },
2052 /* The optional L field in tlbie and tlbiel instructions. */
2054 /* The R field in a HTM X form instruction. */
2056 { 0x1, 21, NULL
, NULL
, PPC_OPERAND_OPTIONAL
},
2058 /* The optional (for 32-bit) L field in cmp[l][i] instructions. */
2059 #define L32OPT LOPT + 1
2060 { 0x1, 21, NULL
, NULL
, PPC_OPERAND_OPTIONAL
| PPC_OPERAND_OPTIONAL32
},
2062 /* The L field in dcbf instruction. */
2063 #define L2OPT L32OPT + 1
2064 { 0x3, 21, NULL
, NULL
, PPC_OPERAND_OPTIONAL
},
2066 /* The LEV field in a POWER SVC / POWER9 SCV form instruction. */
2067 #define SVC_LEV L2OPT + 1
2068 { 0x7f, 5, NULL
, NULL
, 0 },
2070 /* The LEV field in an SC form instruction. */
2071 #define LEV SVC_LEV + 1
2072 { 0x7f, 5, NULL
, NULL
, PPC_OPERAND_OPTIONAL
},
2074 /* The LI field in an I form instruction. The lower two bits are
2077 { 0x3fffffc, 0, NULL
, NULL
, PPC_OPERAND_RELATIVE
| PPC_OPERAND_SIGNED
},
2079 /* The LI field in an I form instruction when used as an absolute
2082 { 0x3fffffc, 0, NULL
, NULL
, PPC_OPERAND_ABSOLUTE
| PPC_OPERAND_SIGNED
},
2084 /* The LS or WC field in an X (sync or wait) form instruction. */
2087 { 0x3, 21, insert_ls
, extract_ls
, PPC_OPERAND_OPTIONAL
},
2089 /* The ME field in an M form instruction. */
2091 #define ME_MASK (0x1f << 1)
2092 { 0x1f, 1, NULL
, NULL
, 0 },
2094 /* The MB and ME fields in an M form instruction expressed a single
2095 operand which is a bitmask indicating which bits to select. This
2096 is a two operand form using PPC_OPERAND_NEXT. See the
2097 description in opcode/ppc.h for what this means. */
2099 { 0x1f, 6, NULL
, NULL
, PPC_OPERAND_OPTIONAL
| PPC_OPERAND_NEXT
},
2100 { -1, 0, insert_mbe
, extract_mbe
, 0 },
2102 /* The MB or ME field in an MD or MDS form instruction. The high
2103 bit is wrapped to the low end. */
2106 #define MB6_MASK (0x3f << 5)
2107 { 0x3f, 5, insert_mb6
, extract_mb6
, 0 },
2109 /* The NB field in an X form instruction. The value 32 is stored as
2112 { 0x1f, 11, NULL
, extract_nb
, PPC_OPERAND_PLUS1
},
2114 /* The NBI field in an lswi instruction, which has special value
2115 restrictions. The value 32 is stored as 0. */
2117 { 0x1f, 11, insert_nbi
, extract_nb
, PPC_OPERAND_PLUS1
},
2119 /* The NSI field in a D form instruction. This is the same as the
2120 SI field, only negated. */
2122 { 0xffff, 0, insert_nsi
, extract_nsi
,
2123 PPC_OPERAND_NEGATIVE
| PPC_OPERAND_SIGNED
},
2125 /* The NSI field in a D form instruction when we accept a wide range
2126 of positive values. */
2127 #define NSISIGNOPT NSI + 1
2128 { 0xffff, 0, insert_nsi
, extract_nsi
,
2129 PPC_OPERAND_NEGATIVE
| PPC_OPERAND_SIGNED
| PPC_OPERAND_SIGNOPT
},
2131 /* The RA field in an D, DS, DQ, X, XO, M, or MDS form instruction. */
2132 #define RA NSISIGNOPT + 1
2133 #define RA_MASK (0x1f << 16)
2134 { 0x1f, 16, NULL
, NULL
, PPC_OPERAND_GPR
},
2136 /* As above, but 0 in the RA field means zero, not r0. */
2138 { 0x1f, 16, NULL
, NULL
, PPC_OPERAND_GPR_0
},
2140 /* The RA field in the DQ form lq or an lswx instruction, which have
2141 special value restrictions. */
2144 { 0x1f, 16, insert_raq
, extract_raq
, PPC_OPERAND_GPR_0
},
2146 /* The RA field in a D or X form instruction which is an updating
2147 load, which means that the RA field may not be zero and may not
2148 equal the RT field. */
2150 { 0x1f, 16, insert_ral
, extract_ral
, PPC_OPERAND_GPR_0
},
2152 /* The RA field in an lmw instruction, which has special value
2155 { 0x1f, 16, insert_ram
, extract_ram
, PPC_OPERAND_GPR_0
},
2157 /* The RA field in a D or X form instruction which is an updating
2158 store or an updating floating point load, which means that the RA
2159 field may not be zero. */
2161 { 0x1f, 16, insert_ras
, extract_ras
, PPC_OPERAND_GPR_0
},
2163 /* The RA field of the tlbwe, dccci and iccci instructions,
2164 which are optional. */
2165 #define RAOPT RAS + 1
2166 { 0x1f, 16, NULL
, NULL
, PPC_OPERAND_GPR
| PPC_OPERAND_OPTIONAL
},
2168 /* The RB field in an X, XO, M, or MDS form instruction. */
2169 #define RB RAOPT + 1
2170 #define RB_MASK (0x1f << 11)
2171 { 0x1f, 11, NULL
, NULL
, PPC_OPERAND_GPR
},
2173 /* The RS and RB fields in an X form instruction when they must be the same.
2174 This is used for extended mnemonics like mr. */
2176 { 0x1f, 11, insert_rsb
, extract_rsb
, PPC_OPERAND_GPR
},
2178 /* The RB field in an lswx instruction, which has special value
2181 { 0x1f, 11, insert_rbx
, extract_rbx
, PPC_OPERAND_GPR
},
2183 /* The RB field of the dccci and iccci instructions, which are optional. */
2184 #define RBOPT RBX + 1
2185 { 0x1f, 11, NULL
, NULL
, PPC_OPERAND_GPR
| PPC_OPERAND_OPTIONAL
},
2187 /* The RC register field in an maddld, maddhd or maddhdu instruction. */
2188 #define RC RBOPT + 1
2189 { 0x1f, 6, NULL
, NULL
, PPC_OPERAND_GPR
},
2191 /* The RS field in a D, DS, X, XFX, XS, M, MD or MDS form
2192 instruction or the RT field in a D, DS, X, XFX or XO form
2196 #define RT_MASK (0x1f << 21)
2198 { 0x1f, 21, NULL
, NULL
, PPC_OPERAND_GPR
},
2200 #define RD_EVEN RS + 1
2201 #define RS_EVEN RD_EVEN
2202 { 0x1f, 21, insert_rD_rS_even
, extract_rD_rS_even
, PPC_OPERAND_GPR
},
2204 /* The RS and RT fields of the DS form stq and DQ form lq instructions,
2205 which have special value restrictions. */
2206 #define RSQ RS_EVEN + 1
2208 #define Q_MASK (1 << 21)
2209 { 0x1e, 21, NULL
, NULL
, PPC_OPERAND_GPR
},
2211 /* The RS field of the tlbwe instruction, which is optional. */
2214 { 0x1f, 21, NULL
, NULL
, PPC_OPERAND_GPR
| PPC_OPERAND_OPTIONAL
},
2216 /* The RX field of the SE_RR form instruction. */
2218 { 0x1f, PPC_OPSHIFT_INV
, insert_rx
, extract_rx
, PPC_OPERAND_GPR
},
2220 /* The ARX field of the SE_RR form instruction. */
2222 { 0x1f, PPC_OPSHIFT_INV
, insert_arx
, extract_arx
, PPC_OPERAND_GPR
},
2224 /* The RY field of the SE_RR form instruction. */
2227 { 0x1f, PPC_OPSHIFT_INV
, insert_ry
, extract_ry
, PPC_OPERAND_GPR
},
2229 /* The ARY field of the SE_RR form instruction. */
2231 { 0x1f, PPC_OPSHIFT_INV
, insert_ary
, extract_ary
, PPC_OPERAND_GPR
},
2233 /* The SCLSCI8 field in a D form instruction. */
2234 #define SCLSCI8 ARY + 1
2235 { 0xffffffff, PPC_OPSHIFT_INV
, insert_sci8
, extract_sci8
, 0 },
2237 /* The SCLSCI8N field in a D form instruction. This is the same as the
2238 SCLSCI8 field, only negated. */
2239 #define SCLSCI8N SCLSCI8 + 1
2240 { 0xffffffff, PPC_OPSHIFT_INV
, insert_sci8n
, extract_sci8n
,
2241 PPC_OPERAND_NEGATIVE
| PPC_OPERAND_SIGNED
},
2243 /* The SD field of the SD4 form instruction. */
2244 #define SE_SD SCLSCI8N + 1
2245 { 0xf, 8, NULL
, NULL
, PPC_OPERAND_PARENS
},
2247 /* The SD field of the SD4 form instruction, for halfword. */
2248 #define SE_SDH SE_SD + 1
2249 { 0x1e, PPC_OPSHIFT_INV
, insert_sd4h
, extract_sd4h
, PPC_OPERAND_PARENS
},
2251 /* The SD field of the SD4 form instruction, for word. */
2252 #define SE_SDW SE_SDH + 1
2253 { 0x3c, PPC_OPSHIFT_INV
, insert_sd4w
, extract_sd4w
, PPC_OPERAND_PARENS
},
2255 /* The SH field in an X or M form instruction. */
2256 #define SH SE_SDW + 1
2257 #define SH_MASK (0x1f << 11)
2258 /* The other UIMM field in a EVX form instruction. */
2260 /* The FC field in an atomic X form instruction. */
2262 { 0x1f, 11, NULL
, NULL
, 0 },
2264 #define EVUIMM_LT8 SH + 1
2265 { 0x1f, 11, insert_evuimm_lt8
, extract_evuimm_lt8
, 0 },
2267 #define EVUIMM_LT16 EVUIMM_LT8 + 1
2268 { 0x1f, 11, insert_evuimm_lt16
, extract_evuimm_lt16
, 0 },
2270 /* The SI field in a HTM X form instruction. */
2271 #define HTM_SI EVUIMM_LT16 + 1
2272 { 0x1f, 11, NULL
, NULL
, PPC_OPERAND_SIGNED
},
2274 /* The SH field in an MD form instruction. This is split. */
2275 #define SH6 HTM_SI + 1
2276 #define SH6_MASK ((0x1f << 11) | (1 << 1))
2277 { 0x3f, PPC_OPSHIFT_INV
, insert_sh6
, extract_sh6
, 0 },
2279 /* The SH field of some variants of the tlbre and tlbwe
2280 instructions, and the ELEV field of the e_sc instruction. */
2283 { 0x1f, 11, NULL
, NULL
, PPC_OPERAND_OPTIONAL
},
2285 /* The SI field in a D form instruction. */
2287 { 0xffff, 0, NULL
, NULL
, PPC_OPERAND_SIGNED
},
2289 /* The SI field in a D form instruction when we accept a wide range
2290 of positive values. */
2291 #define SISIGNOPT SI + 1
2292 { 0xffff, 0, NULL
, NULL
, PPC_OPERAND_SIGNED
| PPC_OPERAND_SIGNOPT
},
2294 /* The SI8 field in a D form instruction. */
2295 #define SI8 SISIGNOPT + 1
2296 { 0xff, 0, NULL
, NULL
, PPC_OPERAND_SIGNED
},
2298 /* The SPR field in an XFX form instruction. This is flipped--the
2299 lower 5 bits are stored in the upper 5 and vice- versa. */
2303 #define SPR_MASK (0x3ff << 11)
2304 { 0x3ff, 11, insert_spr
, extract_spr
, PPC_OPERAND_SPR
},
2306 /* The BAT index number in an XFX form m[ft]ibat[lu] instruction. */
2307 #define SPRBAT SPR + 1
2308 #define SPRBAT_MASK (0x3 << 17)
2309 { 0x3, 17, NULL
, NULL
, 0 },
2311 /* The SPRG register number in an XFX form m[ft]sprg instruction. */
2312 #define SPRG SPRBAT + 1
2313 { 0x1f, 16, insert_sprg
, extract_sprg
, PPC_OPERAND_SPR
},
2315 /* The SR field in an X form instruction. */
2317 /* The 4-bit UIMM field in a VX form instruction. */
2319 { 0xf, 16, NULL
, NULL
, 0 },
2321 /* The STRM field in an X AltiVec form instruction. */
2323 /* The T field in a tlbilx form instruction. */
2325 /* The L field in wclr instructions. */
2327 { 0x3, 21, NULL
, NULL
, 0 },
2329 /* The ESYNC field in an X (sync) form instruction. */
2330 #define ESYNC STRM + 1
2331 { 0xf, 16, insert_esync
, extract_esync
, PPC_OPERAND_OPTIONAL
},
2333 /* The SV field in a POWER SC form instruction. */
2334 #define SV ESYNC + 1
2335 { 0x3fff, 2, NULL
, NULL
, 0 },
2337 /* The TBR field in an XFX form instruction. This is like the SPR
2338 field, but it is optional. */
2340 { 0x3ff, 11, insert_tbr
, extract_tbr
,
2341 PPC_OPERAND_SPR
| PPC_OPERAND_OPTIONAL
| PPC_OPERAND_OPTIONAL_VALUE
},
2342 /* If the TBR operand is ommitted, use the value 268. */
2343 { -1, 268, NULL
, NULL
, 0},
2345 /* The TO field in a D or X form instruction. */
2348 #define TO_MASK (0x1f << 21)
2349 { 0x1f, 21, NULL
, NULL
, 0 },
2351 /* The UI field in a D form instruction. */
2353 { 0xffff, 0, NULL
, NULL
, 0 },
2355 #define UISIGNOPT UI + 1
2356 { 0xffff, 0, NULL
, NULL
, PPC_OPERAND_SIGNOPT
},
2358 /* The IMM field in an SE_IM5 instruction. */
2359 #define UI5 UISIGNOPT + 1
2360 { 0x1f, 4, NULL
, NULL
, 0 },
2362 /* The OIMM field in an SE_OIM5 instruction. */
2363 #define OIMM5 UI5 + 1
2364 { 0x1f, PPC_OPSHIFT_INV
, insert_oimm
, extract_oimm
, PPC_OPERAND_PLUS1
},
2366 /* The UI7 field in an SE_LI instruction. */
2367 #define UI7 OIMM5 + 1
2368 { 0x7f, 4, NULL
, NULL
, 0 },
2370 /* The VA field in a VA, VX or VXR form instruction. */
2372 { 0x1f, 16, NULL
, NULL
, PPC_OPERAND_VR
},
2374 /* The VB field in a VA, VX or VXR form instruction. */
2376 { 0x1f, 11, NULL
, NULL
, PPC_OPERAND_VR
},
2378 /* The VC field in a VA form instruction. */
2380 { 0x1f, 6, NULL
, NULL
, PPC_OPERAND_VR
},
2382 /* The VD or VS field in a VA, VX, VXR or X form instruction. */
2385 { 0x1f, 21, NULL
, NULL
, PPC_OPERAND_VR
},
2387 /* The SIMM field in a VX form instruction, and TE in Z form. */
2390 { 0x1f, 16, NULL
, NULL
, PPC_OPERAND_SIGNED
},
2392 /* The UIMM field in a VX form instruction. */
2393 #define UIMM SIMM + 1
2395 { 0x1f, 16, NULL
, NULL
, 0 },
2397 /* The 3-bit UIMM field in a VX form instruction. */
2398 #define UIMM3 UIMM + 1
2399 { 0x7, 16, NULL
, NULL
, 0 },
2401 /* The 6-bit UIM field in a X form instruction. */
2402 #define UIM6 UIMM3 + 1
2403 { 0x3f, 16, NULL
, NULL
, 0 },
2405 /* The SIX field in a VX form instruction. */
2406 #define SIX UIM6 + 1
2408 { 0xf, 11, NULL
, NULL
, 0 },
2410 /* The PS field in a VX form instruction. */
2412 { 0x1, 9, NULL
, NULL
, 0 },
2414 /* The SHB field in a VA form instruction. */
2416 { 0xf, 6, NULL
, NULL
, 0 },
2418 /* The other UIMM field in a half word EVX form instruction. */
2419 #define EVUIMM_1 SHB + 1
2420 { 0x1f, 11, NULL
, NULL
, PPC_OPERAND_PARENS
},
2422 #define EVUIMM_1_EX0 EVUIMM_1 + 1
2423 { 0x1f, 11, insert_evuimm1_ex0
, extract_evuimm1_ex0
, PPC_OPERAND_PARENS
},
2425 #define EVUIMM_2 EVUIMM_1_EX0 + 1
2426 { 0x3e, 10, NULL
, NULL
, PPC_OPERAND_PARENS
},
2428 #define EVUIMM_2_EX0 EVUIMM_2 + 1
2429 { 0x3e, 10, insert_evuimm2_ex0
, extract_evuimm2_ex0
, PPC_OPERAND_PARENS
},
2431 /* The other UIMM field in a word EVX form instruction. */
2432 #define EVUIMM_4 EVUIMM_2_EX0 + 1
2433 { 0x7c, 9, NULL
, NULL
, PPC_OPERAND_PARENS
},
2435 #define EVUIMM_4_EX0 EVUIMM_4 + 1
2436 { 0x7c, 9, insert_evuimm4_ex0
, extract_evuimm4_ex0
, PPC_OPERAND_PARENS
},
2438 /* The other UIMM field in a double EVX form instruction. */
2439 #define EVUIMM_8 EVUIMM_4_EX0 + 1
2440 { 0xf8, 8, NULL
, NULL
, PPC_OPERAND_PARENS
},
2442 #define EVUIMM_8_EX0 EVUIMM_8 + 1
2443 { 0xf8, 8, insert_evuimm8_ex0
, extract_evuimm8_ex0
, PPC_OPERAND_PARENS
},
2445 /* The WS or DRM field in an X form instruction. */
2446 #define WS EVUIMM_8_EX0 + 1
2448 /* The NNN field in a VX form instruction for SPE2 */
2450 { 0x7, 11, NULL
, NULL
, 0 },
2452 /* PowerPC paired singles extensions. */
2453 /* W bit in the pair singles instructions for x type instructions. */
2455 /* The BO16 field in a BD8 form instruction. */
2457 { 0x1, 10, 0, 0, 0 },
2459 /* IDX bits for quantization in the pair singles instructions. */
2460 #define PSQ PSWM + 1
2461 { 0x7, 12, 0, 0, PPC_OPERAND_GQR
},
2463 /* IDX bits for quantization in the pair singles x-type instructions. */
2464 #define PSQM PSQ + 1
2465 { 0x7, 7, 0, 0, PPC_OPERAND_GQR
},
2467 /* Smaller D field for quantization in the pair singles instructions. */
2468 #define PSD PSQM + 1
2469 { 0xfff, 0, 0, 0, PPC_OPERAND_PARENS
| PPC_OPERAND_SIGNED
},
2471 /* The L field in an mtmsrd or A form instruction or R or W in an
2476 { 0x1, 16, NULL
, NULL
, PPC_OPERAND_OPTIONAL
},
2478 /* The RMC or CY field in a Z23 form instruction. */
2481 { 0x3, 9, NULL
, NULL
, 0 },
2484 { 0x1, 16, NULL
, NULL
, 0 },
2487 { 0x3, 18, NULL
, NULL
, PPC_OPERAND_OPTIONAL
},
2490 { 0x1, 17, NULL
, NULL
, PPC_OPERAND_OPTIONAL
},
2493 { 0x3, 19, NULL
, NULL
, 0 },
2496 { 0x1, 20, NULL
, NULL
, 0 },
2498 /* The S field in a XL form instruction. */
2500 { 0x1, 11, NULL
, NULL
, PPC_OPERAND_OPTIONAL
| PPC_OPERAND_OPTIONAL_VALUE
},
2501 /* If the SXL operand is ommitted, use the value 1. */
2502 { -1, 1, NULL
, NULL
, 0},
2504 /* SH field starting at bit position 16. */
2505 #define SH16 SXL + 2
2506 /* The DCM and DGM fields in a Z form instruction. */
2509 { 0x3f, 10, NULL
, NULL
, 0 },
2511 /* The EH field in larx instruction. */
2513 { 0x1, 0, NULL
, NULL
, PPC_OPERAND_OPTIONAL
},
2515 /* The L field in an mtfsf or XFL form instruction. */
2516 /* The A field in a HTM X form instruction. */
2517 #define XFL_L EH + 1
2519 { 0x1, 25, NULL
, NULL
, PPC_OPERAND_OPTIONAL
},
2521 /* Xilinx APU related masks and macros */
2522 #define FCRT XFL_L + 1
2523 #define FCRT_MASK (0x1f << 21)
2524 { 0x1f, 21, 0, 0, PPC_OPERAND_FCR
},
2526 /* Xilinx FSL related masks and macros */
2527 #define FSL FCRT + 1
2528 #define FSL_MASK (0x1f << 11)
2529 { 0x1f, 11, 0, 0, PPC_OPERAND_FSL
},
2531 /* Xilinx UDI related masks and macros */
2533 { 0x1f, 21, 0, 0, PPC_OPERAND_UDI
},
2536 { 0x1f, 16, 0, 0, PPC_OPERAND_UDI
},
2539 { 0x1f, 11, 0, 0, PPC_OPERAND_UDI
},
2542 { 0x1f, 6, 0, 0, PPC_OPERAND_UDI
},
2544 /* The VLESIMM field in a D form instruction. */
2545 #define VLESIMM URC + 1
2546 { 0xffff, PPC_OPSHIFT_INV
, insert_vlesi
, extract_vlesi
,
2547 PPC_OPERAND_SIGNED
| PPC_OPERAND_SIGNOPT
},
2549 /* The VLENSIMM field in a D form instruction. */
2550 #define VLENSIMM VLESIMM + 1
2551 { 0xffff, PPC_OPSHIFT_INV
, insert_vlensi
, extract_vlensi
,
2552 PPC_OPERAND_NEGATIVE
| PPC_OPERAND_SIGNED
| PPC_OPERAND_SIGNOPT
},
2554 /* The VLEUIMM field in a D form instruction. */
2555 #define VLEUIMM VLENSIMM + 1
2556 { 0xffff, PPC_OPSHIFT_INV
, insert_vleui
, extract_vleui
, 0 },
2558 /* The VLEUIMML field in a D form instruction. */
2559 #define VLEUIMML VLEUIMM + 1
2560 { 0xffff, PPC_OPSHIFT_INV
, insert_vleil
, extract_vleil
, 0 },
2562 /* The XT and XS fields in an XX1 or XX3 form instruction. This is
2564 #define XS6 VLEUIMML + 1
2566 { 0x3f, PPC_OPSHIFT_INV
, insert_xt6
, extract_xt6
, PPC_OPERAND_VSR
},
2568 /* The XT and XS fields in an DQ form VSX instruction. This is split. */
2569 #define XSQ6 XT6 + 1
2571 { 0x3f, PPC_OPSHIFT_INV
, insert_xtq6
, extract_xtq6
, PPC_OPERAND_VSR
},
2573 /* The XA field in an XX3 form instruction. This is split. */
2574 #define XA6 XTQ6 + 1
2575 { 0x3f, PPC_OPSHIFT_INV
, insert_xa6
, extract_xa6
, PPC_OPERAND_VSR
},
2577 /* The XB field in an XX2 or XX3 form instruction. This is split. */
2579 { 0x3f, PPC_OPSHIFT_INV
, insert_xb6
, extract_xb6
, PPC_OPERAND_VSR
},
2581 /* The XA and XB fields in an XX3 form instruction when they must be the same.
2582 This is used in extended mnemonics like xvmovdp. This is split. */
2583 #define XAB6 XB6 + 1
2584 { 0x3f, PPC_OPSHIFT_INV
, insert_xab6
, extract_xab6
, PPC_OPERAND_VSR
},
2586 /* The XC field in an XX4 form instruction. This is split. */
2587 #define XC6 XAB6 + 1
2588 { 0x3f, PPC_OPSHIFT_INV
, insert_xc6
, extract_xc6
, PPC_OPERAND_VSR
},
2590 /* The DM or SHW field in an XX3 form instruction. */
2593 { 0x3, 8, NULL
, NULL
, 0 },
2595 /* The DM field in an extended mnemonic XX3 form instruction. */
2597 { 0x3, 8, insert_dm
, extract_dm
, 0 },
2599 /* The UIM field in an XX2 form instruction. */
2600 #define UIM DMEX + 1
2601 /* The 2-bit UIMM field in a VX form instruction. */
2603 /* The 2-bit L field in a darn instruction. */
2605 { 0x3, 16, NULL
, NULL
, 0 },
2607 #define ERAT_T UIM + 1
2608 { 0x7, 21, NULL
, NULL
, 0 },
2610 #define IH ERAT_T + 1
2611 { 0x7, 21, NULL
, NULL
, PPC_OPERAND_OPTIONAL
},
2613 /* The 8-bit IMM8 field in a XX1 form instruction. */
2615 { 0xff, 11, NULL
, NULL
, PPC_OPERAND_SIGNOPT
},
2617 #define VX_OFF IMM8 + 1
2618 { 0x3, 0, insert_off_lsp
, extract_off_lsp
, 0 },
2620 #define VX_OFF_SPE2 VX_OFF + 1
2621 { 0x7, 0, insert_off_spe2
, extract_off_spe2
, 0 },
2623 #define BBB VX_OFF_SPE2 + 1
2624 { 0x7, 13, NULL
, NULL
, 0 },
2627 #define VX_MASK_DDD (VX_MASK & ~0x1)
2628 { 0x7, PPC_OPSHIFT_INV
, insert_Ddd
, extract_Ddd
, 0 },
2631 { 0x3, 13, NULL
, NULL
, 0 },
2634 const unsigned int num_powerpc_operands
= (sizeof (powerpc_operands
)
2635 / sizeof (powerpc_operands
[0]));
2637 /* Macros used to form opcodes. */
2639 /* The main opcode. */
2640 #define OP(x) ((((uint64_t)(x)) & 0x3f) << 26)
2641 #define OP_MASK OP (0x3f)
2643 /* The main opcode combined with a trap code in the TO field of a D
2644 form instruction. Used for extended mnemonics for the trap
2646 #define OPTO(x,to) (OP (x) | ((((uint64_t)(to)) & 0x1f) << 21))
2647 #define OPTO_MASK (OP_MASK | TO_MASK)
2649 /* The main opcode combined with a comparison size bit in the L field
2650 of a D form or X form instruction. Used for extended mnemonics for
2651 the comparison instructions. */
2652 #define OPL(x,l) (OP (x) | ((((uint64_t)(l)) & 1) << 21))
2653 #define OPL_MASK OPL (0x3f,1)
2655 /* The main opcode combined with an update code in D form instruction.
2656 Used for extended mnemonics for VLE memory instructions. */
2657 #define OPVUP(x,vup) (OP (x) | ((((uint64_t)(vup)) & 0xff) << 8))
2658 #define OPVUP_MASK OPVUP (0x3f, 0xff)
2660 /* The main opcode combined with an update code and the RT fields
2661 specified in D form instruction. Used for VLE volatile context
2662 save/restore instructions. */
2663 #define OPVUPRT(x,vup,rt) \
2665 | ((((uint64_t)(rt)) & 0x1f) << 21))
2666 #define OPVUPRT_MASK OPVUPRT (0x3f, 0xff, 0x1f)
2668 /* An A form instruction. */
2669 #define A(op, xop, rc) \
2671 | ((((uint64_t)(xop)) & 0x1f) << 1) \
2672 | (((uint64_t)(rc)) & 1))
2673 #define A_MASK A (0x3f, 0x1f, 1)
2675 /* An A_MASK with the FRB field fixed. */
2676 #define AFRB_MASK (A_MASK | FRB_MASK)
2678 /* An A_MASK with the FRC field fixed. */
2679 #define AFRC_MASK (A_MASK | FRC_MASK)
2681 /* An A_MASK with the FRA and FRC fields fixed. */
2682 #define AFRAFRC_MASK (A_MASK | FRA_MASK | FRC_MASK)
2684 /* An AFRAFRC_MASK, but with L bit clear. */
2685 #define AFRALFRC_MASK (AFRAFRC_MASK & ~((uint64_t) 1 << 16))
2687 /* A B form instruction. */
2688 #define B(op, aa, lk) \
2690 | ((((uint64_t)(aa)) & 1) << 1) \
2692 #define B_MASK B (0x3f, 1, 1)
2694 /* A BD8 form instruction. This is a 16-bit instruction. */
2695 #define BD8(op, aa, lk) \
2696 (((((uint64_t)(op)) & 0x3f) << 10) \
2697 | (((aa) & 1) << 9) \
2698 | (((lk) & 1) << 8))
2699 #define BD8_MASK BD8 (0x3f, 1, 1)
2701 /* Another BD8 form instruction. This is a 16-bit instruction. */
2702 #define BD8IO(op) ((((uint64_t)(op)) & 0x1f) << 11)
2703 #define BD8IO_MASK BD8IO (0x1f)
2705 /* A BD8 form instruction for simplified mnemonics. */
2706 #define EBD8IO(op, bo, bi) (BD8IO ((op)) | ((bo) << 10) | ((bi) << 8))
2707 /* A mask that excludes BO32 and BI32. */
2708 #define EBD8IO1_MASK 0xf800
2709 /* A mask that includes BO32 and excludes BI32. */
2710 #define EBD8IO2_MASK 0xfc00
2711 /* A mask that include BO32 AND BI32. */
2712 #define EBD8IO3_MASK 0xff00
2714 /* A BD15 form instruction. */
2715 #define BD15(op, aa, lk) \
2717 | ((((uint64_t)(aa)) & 0xf) << 22) \
2719 #define BD15_MASK BD15 (0x3f, 0xf, 1)
2721 /* A BD15 form instruction for extended conditional branch mnemonics. */
2722 #define EBD15(op, aa, bo, lk) \
2723 (((op) & 0x3f) << 26) \
2724 | (((aa) & 0xf) << 22) \
2725 | (((bo) & 0x3) << 20) \
2727 #define EBD15_MASK 0xfff00001
2729 /* A BD15 form instruction for extended conditional branch mnemonics
2731 #define EBD15BI(op, aa, bo, bi, lk) \
2732 ((((op) & 0x3f) << 26) \
2733 | (((aa) & 0xf) << 22) \
2734 | (((bo) & 0x3) << 20) \
2735 | (((bi) & 0x3) << 16) \
2738 #define EBD15BI_MASK 0xfff30001
2740 /* A BD24 form instruction. */
2741 #define BD24(op, aa, lk) \
2743 | ((((uint64_t)(aa)) & 1) << 25) \
2745 #define BD24_MASK BD24 (0x3f, 1, 1)
2747 /* A B form instruction setting the BO field. */
2748 #define BBO(op, bo, aa, lk) \
2749 (B ((op), (aa), (lk)) \
2750 | ((((uint64_t)(bo)) & 0x1f) << 21))
2751 #define BBO_MASK BBO (0x3f, 0x1f, 1, 1)
2753 /* A BBO_MASK with the y bit of the BO field removed. This permits
2754 matching a conditional branch regardless of the setting of the y
2755 bit. Similarly for the 'at' bits used for power4 branch hints. */
2756 #define Y_MASK (((uint64_t) 1) << 21)
2757 #define AT1_MASK (((uint64_t) 3) << 21)
2758 #define AT2_MASK (((uint64_t) 9) << 21)
2759 #define BBOY_MASK (BBO_MASK &~ Y_MASK)
2760 #define BBOAT_MASK (BBO_MASK &~ AT1_MASK)
2762 /* A B form instruction setting the BO field and the condition bits of
2764 #define BBOCB(op, bo, cb, aa, lk) \
2765 (BBO ((op), (bo), (aa), (lk)) | ((((uint64_t)(cb)) & 0x3) << 16))
2766 #define BBOCB_MASK BBOCB (0x3f, 0x1f, 0x3, 1, 1)
2768 /* A BBOCB_MASK with the y bit of the BO field removed. */
2769 #define BBOYCB_MASK (BBOCB_MASK &~ Y_MASK)
2770 #define BBOATCB_MASK (BBOCB_MASK &~ AT1_MASK)
2771 #define BBOAT2CB_MASK (BBOCB_MASK &~ AT2_MASK)
2773 /* A BBOYCB_MASK in which the BI field is fixed. */
2774 #define BBOYBI_MASK (BBOYCB_MASK | BI_MASK)
2775 #define BBOATBI_MASK (BBOAT2CB_MASK | BI_MASK)
2777 /* A VLE C form instruction. */
2778 #define C_LK(x, lk) (((((uint64_t)(x)) & 0x7fff) << 1) | ((lk) & 1))
2779 #define C_LK_MASK C_LK(0x7fff, 1)
2780 #define C(x) ((((uint64_t)(x)) & 0xffff))
2781 #define C_MASK C(0xffff)
2783 /* An Context form instruction. */
2784 #define CTX(op, xop) (OP (op) | (((uint64_t)(xop)) & 0x7))
2785 #define CTX_MASK CTX(0x3f, 0x7)
2787 /* An User Context form instruction. */
2788 #define UCTX(op, xop) (OP (op) | (((uint64_t)(xop)) & 0x1f))
2789 #define UCTX_MASK UCTX(0x3f, 0x1f)
2791 /* The main opcode mask with the RA field clear. */
2792 #define DRA_MASK (OP_MASK | RA_MASK)
2794 /* A DQ form VSX instruction. */
2795 #define DQX(op, xop) (OP (op) | ((xop) & 0x7))
2796 #define DQX_MASK DQX (0x3f, 7)
2798 /* A DS form instruction. */
2799 #define DSO(op, xop) (OP (op) | ((xop) & 0x3))
2800 #define DS_MASK DSO (0x3f, 3)
2802 /* An DX form instruction. */
2803 #define DX(op, xop) (OP (op) | ((((uint64_t)(xop)) & 0x1f) << 1))
2804 #define DX_MASK DX (0x3f, 0x1f)
2805 /* An DX form instruction with the D bits specified. */
2806 #define NODX_MASK (DX_MASK | 0x1fffc1)
2808 /* An EVSEL form instruction. */
2809 #define EVSEL(op, xop) (OP (op) | (((uint64_t)(xop)) & 0xff) << 3)
2810 #define EVSEL_MASK EVSEL(0x3f, 0xff)
2812 /* An IA16 form instruction. */
2813 #define IA16(op, xop) (OP (op) | (((uint64_t)(xop)) & 0x1f) << 11)
2814 #define IA16_MASK IA16(0x3f, 0x1f)
2816 /* An I16A form instruction. */
2817 #define I16A(op, xop) (OP (op) | (((uint64_t)(xop)) & 0x1f) << 11)
2818 #define I16A_MASK I16A(0x3f, 0x1f)
2820 /* An I16L form instruction. */
2821 #define I16L(op, xop) (OP (op) | (((uint64_t)(xop)) & 0x1f) << 11)
2822 #define I16L_MASK I16L(0x3f, 0x1f)
2824 /* An IM7 form instruction. */
2825 #define IM7(op) ((((uint64_t)(op)) & 0x1f) << 11)
2826 #define IM7_MASK IM7(0x1f)
2828 /* An M form instruction. */
2829 #define M(op, rc) (OP (op) | ((rc) & 1))
2830 #define M_MASK M (0x3f, 1)
2832 /* An LI20 form instruction. */
2833 #define LI20(op, xop) (OP (op) | (((uint64_t)(xop)) & 0x1) << 15)
2834 #define LI20_MASK LI20(0x3f, 0x1)
2836 /* An M form instruction with the ME field specified. */
2837 #define MME(op, me, rc) \
2839 | ((((uint64_t)(me)) & 0x1f) << 1))
2841 /* An M_MASK with the MB and ME fields fixed. */
2842 #define MMBME_MASK (M_MASK | MB_MASK | ME_MASK)
2844 /* An M_MASK with the SH and ME fields fixed. */
2845 #define MSHME_MASK (M_MASK | SH_MASK | ME_MASK)
2847 /* An MD form instruction. */
2848 #define MD(op, xop, rc) \
2850 | ((((uint64_t)(xop)) & 0x7) << 2) \
2852 #define MD_MASK MD (0x3f, 0x7, 1)
2854 /* An MD_MASK with the MB field fixed. */
2855 #define MDMB_MASK (MD_MASK | MB6_MASK)
2857 /* An MD_MASK with the SH field fixed. */
2858 #define MDSH_MASK (MD_MASK | SH6_MASK)
2860 /* An MDS form instruction. */
2861 #define MDS(op, xop, rc) \
2863 | ((((uint64_t)(xop)) & 0xf) << 1) \
2865 #define MDS_MASK MDS (0x3f, 0xf, 1)
2867 /* An MDS_MASK with the MB field fixed. */
2868 #define MDSMB_MASK (MDS_MASK | MB6_MASK)
2870 /* An SC form instruction. */
2871 #define SC(op, sa, lk) \
2873 | ((((uint64_t)(sa)) & 1) << 1) \
2877 | (((uint64_t) 0x3ff) << 16) \
2878 | (((uint64_t) 1) << 1) \
2881 /* An SCI8 form instruction. */
2882 #define SCI8(op, xop) (OP (op) | ((((uint64_t)(xop)) & 0x1f) << 11))
2883 #define SCI8_MASK SCI8(0x3f, 0x1f)
2885 /* An SCI8 form instruction. */
2886 #define SCI8BF(op, fop, xop) \
2888 | ((((uint64_t)(xop)) & 0x1f) << 11) \
2889 | (((fop) & 7) << 23))
2890 #define SCI8BF_MASK SCI8BF(0x3f, 7, 0x1f)
2892 /* An SD4 form instruction. This is a 16-bit instruction. */
2893 #define SD4(op) ((((uint64_t)(op)) & 0xf) << 12)
2894 #define SD4_MASK SD4(0xf)
2896 /* An SE_IM5 form instruction. This is a 16-bit instruction. */
2897 #define SE_IM5(op, xop) \
2898 (((((uint64_t)(op)) & 0x3f) << 10) \
2899 | (((xop) & 0x1) << 9))
2900 #define SE_IM5_MASK SE_IM5(0x3f, 1)
2902 /* An SE_R form instruction. This is a 16-bit instruction. */
2903 #define SE_R(op, xop) \
2904 (((((uint64_t)(op)) & 0x3f) << 10) \
2905 | (((xop) & 0x3f) << 4))
2906 #define SE_R_MASK SE_R(0x3f, 0x3f)
2908 /* An SE_RR form instruction. This is a 16-bit instruction. */
2909 #define SE_RR(op, xop) \
2910 (((((uint64_t)(op)) & 0x3f) << 10) \
2911 | (((xop) & 0x3) << 8))
2912 #define SE_RR_MASK SE_RR(0x3f, 3)
2914 /* A VX form instruction. */
2915 #define VX(op, xop) (OP (op) | (((uint64_t)(xop)) & 0x7ff))
2917 /* The mask for an VX form instruction. */
2918 #define VX_MASK VX(0x3f, 0x7ff)
2920 /* A VX LSP form instruction. */
2921 #define VX_LSP(op, xop) (OP (op) | (((uint64_t)(xop)) & 0xffff))
2923 /* The mask for an VX LSP form instruction. */
2924 #define VX_LSP_MASK VX_LSP(0x3f, 0xffff)
2925 #define VX_LSP_OFF_MASK VX_LSP(0x3f, 0x7fc)
2927 /* Additional format of VX SPE2 form instruction. */
2928 #define VX_RA_CONST(op, xop, bits11_15) \
2930 | (((uint64_t)(bits11_15) & 0x1f) << 16) \
2931 | (((uint64_t)(xop)) & 0x7ff))
2932 #define VX_RA_CONST_MASK VX_RA_CONST(0x3f, 0x7ff, 0x1f)
2934 #define VX_RB_CONST(op, xop, bits16_20) \
2936 | (((uint64_t)(bits16_20) & 0x1f) << 11) \
2937 | (((uint64_t)(xop)) & 0x7ff))
2938 #define VX_RB_CONST_MASK VX_RB_CONST(0x3f, 0x7ff, 0x1f)
2940 #define VX_OFF_SPE2_MASK VX(0x3f, 0x7f8)
2942 #define VX_SPE_CRFD(op, xop, bits9_10) \
2944 | (((uint64_t)(bits9_10) & 0x3) << 21) \
2945 | (((uint64_t)(xop)) & 0x7ff))
2946 #define VX_SPE_CRFD_MASK VX_SPE_CRFD(0x3f, 0x7ff, 0x3)
2948 #define VX_SPE2_CLR(op, xop, bit16) \
2950 | (((uint64_t)(bit16) & 0x1) << 15) \
2951 | (((uint64_t)(xop)) & 0x7ff))
2952 #define VX_SPE2_CLR_MASK VX_SPE2_CLR(0x3f, 0x7ff, 0x1)
2954 #define VX_SPE2_SPLATB(op, xop, bits19_20) \
2956 | (((uint64_t)(bits19_20) & 0x3) << 11) \
2957 | (((uint64_t)(xop)) & 0x7ff))
2958 #define VX_SPE2_SPLATB_MASK VX_SPE2_SPLATB(0x3f, 0x7ff, 0x3)
2960 #define VX_SPE2_OCTET(op, xop, bits16_17) \
2962 | (((uint64_t)(bits16_17) & 0x3) << 14) \
2963 | (((uint64_t)(xop)) & 0x7ff))
2964 #define VX_SPE2_OCTET_MASK VX_SPE2_OCTET(0x3f, 0x7ff, 0x7)
2966 #define VX_SPE2_DDHH(op, xop, bit16) \
2968 | (((uint64_t)(bit16) & 0x1) << 15) \
2969 | (((uint64_t)(xop)) & 0x7ff))
2970 #define VX_SPE2_DDHH_MASK VX_SPE2_DDHH(0x3f, 0x7ff, 0x1)
2972 #define VX_SPE2_HH(op, xop, bit16, bits19_20) \
2974 | (((uint64_t)(bit16) & 0x1) << 15) \
2975 | (((uint64_t)(bits19_20) & 0x3) << 11) \
2976 | (((uint64_t)(xop)) & 0x7ff))
2977 #define VX_SPE2_HH_MASK VX_SPE2_HH(0x3f, 0x7ff, 0x1, 0x3)
2979 #define VX_SPE2_EVMAR(op, xop) \
2981 | ((uint64_t)(0x1) << 11) \
2982 | (((uint64_t)(xop)) & 0x7ff))
2983 #define VX_SPE2_EVMAR_MASK \
2984 (VX_SPE2_EVMAR(0x3f, 0x7ff) \
2985 | ((uint64_t)(0x1) << 11))
2987 /* A VX_MASK with the VA field fixed. */
2988 #define VXVA_MASK (VX_MASK | (0x1f << 16))
2990 /* A VX_MASK with the VB field fixed. */
2991 #define VXVB_MASK (VX_MASK | (0x1f << 11))
2993 /* A VX_MASK with the VA and VB fields fixed. */
2994 #define VXVAVB_MASK (VX_MASK | (0x1f << 16) | (0x1f << 11))
2996 /* A VX_MASK with the VD and VA fields fixed. */
2997 #define VXVDVA_MASK (VX_MASK | (0x1f << 21) | (0x1f << 16))
2999 /* A VX_MASK with a UIMM4 field. */
3000 #define VXUIMM4_MASK (VX_MASK | (0x1 << 20))
3002 /* A VX_MASK with a UIMM3 field. */
3003 #define VXUIMM3_MASK (VX_MASK | (0x3 << 19))
3005 /* A VX_MASK with a UIMM2 field. */
3006 #define VXUIMM2_MASK (VX_MASK | (0x7 << 18))
3008 /* A VX_MASK with a PS field. */
3009 #define VXPS_MASK (VX_MASK & ~(0x1 << 9))
3011 /* A VX_MASK with the VA field fixed with a PS field. */
3012 #define VXVAPS_MASK ((VX_MASK | (0x1f << 16)) & ~(0x1 << 9))
3014 /* A VA form instruction. */
3015 #define VXA(op, xop) (OP (op) | (((uint64_t)(xop)) & 0x03f))
3017 /* The mask for an VA form instruction. */
3018 #define VXA_MASK VXA(0x3f, 0x3f)
3020 /* A VXA_MASK with a SHB field. */
3021 #define VXASHB_MASK (VXA_MASK | (1 << 10))
3023 /* A VXR form instruction. */
3024 #define VXR(op, xop, rc) \
3026 | (((uint64_t)(rc) & 1) << 10) \
3027 | (((uint64_t)(xop)) & 0x3ff))
3029 /* The mask for a VXR form instruction. */
3030 #define VXR_MASK VXR(0x3f, 0x3ff, 1)
3032 /* A VX form instruction with a VA tertiary opcode. */
3033 #define VXVA(op, xop, vaop) (VX(op,xop) | (((vaop) & 0x1f) << 16))
3035 #define VXASH(op, xop) (OP (op) | ((((uint64_t)(xop)) & 0x1f) << 1))
3036 #define VXASH_MASK VXASH (0x3f, 0x1f)
3038 /* An X form instruction. */
3039 #define X(op, xop) (OP (op) | ((((uint64_t)(xop)) & 0x3ff) << 1))
3041 /* A X form instruction for Quad-Precision FP Instructions. */
3042 #define XVA(op, xop, vaop) (X(op,xop) | (((vaop) & 0x1f) << 16))
3044 /* An EX form instruction. */
3045 #define EX(op, xop) (OP (op) | (((uint64_t)(xop)) & 0x7ff))
3047 /* The mask for an EX form instruction. */
3048 #define EX_MASK EX (0x3f, 0x7ff)
3050 /* An XX2 form instruction. */
3051 #define XX2(op, xop) (OP (op) | ((((uint64_t)(xop)) & 0x1ff) << 2))
3053 /* A XX2 form instruction with the VA bits specified. */
3054 #define XX2VA(op, xop, vaop) (XX2(op,xop) | (((vaop) & 0x1f) << 16))
3056 /* An XX3 form instruction. */
3057 #define XX3(op, xop) (OP (op) | ((((uint64_t)(xop)) & 0xff) << 3))
3059 /* An XX3 form instruction with the RC bit specified. */
3060 #define XX3RC(op, xop, rc) \
3062 | (((uint64_t)(rc) & 1) << 10) \
3063 | ((((uint64_t)(xop)) & 0x7f) << 3))
3065 /* An XX4 form instruction. */
3066 #define XX4(op, xop) (OP (op) | ((((uint64_t)(xop)) & 0x3) << 4))
3068 /* A Z form instruction. */
3069 #define Z(op, xop) (OP (op) | ((((uint64_t)(xop)) & 0x1ff) << 1))
3071 /* An X form instruction with the RC bit specified. */
3072 #define XRC(op, xop, rc) (X ((op), (xop)) | ((rc) & 1))
3074 /* A X form instruction for Quad-Precision FP Instructions with RC bit. */
3075 #define XVARC(op, xop, vaop, rc) (XVA ((op), (xop), (vaop)) | ((rc) & 1))
3077 /* An X form instruction with the RA bits specified as two ops. */
3078 #define XMMF(op, xop, mop0, mop1) \
3080 | ((mop0) & 3) << 19 \
3081 | ((mop1) & 7) << 16)
3083 /* A Z form instruction with the RC bit specified. */
3084 #define ZRC(op, xop, rc) (Z ((op), (xop)) | ((rc) & 1))
3086 /* The mask for an X form instruction. */
3087 #define X_MASK XRC (0x3f, 0x3ff, 1)
3089 /* The mask for an X form instruction with the BF bits specified. */
3090 #define XBF_MASK (X_MASK | (3 << 21))
3092 /* An X form wait instruction with everything filled in except the WC
3094 #define XWC_MASK (XRC (0x3f, 0x3ff, 1) | (7 << 23) | RA_MASK | RB_MASK)
3096 /* The mask for an XX1 form instruction. */
3097 #define XX1_MASK X (0x3f, 0x3ff)
3099 /* An XX1_MASK with the RB field fixed. */
3100 #define XX1RB_MASK (XX1_MASK | RB_MASK)
3102 /* The mask for an XX2 form instruction. */
3103 #define XX2_MASK (XX2 (0x3f, 0x1ff) | (0x1f << 16))
3105 /* The mask for an XX2 form instruction with the UIM bits specified. */
3106 #define XX2UIM_MASK (XX2 (0x3f, 0x1ff) | (7 << 18))
3108 /* The mask for an XX2 form instruction with the 4 UIM bits specified. */
3109 #define XX2UIM4_MASK (XX2 (0x3f, 0x1ff) | (1 << 20))
3111 /* The mask for an XX2 form instruction with the BF bits specified. */
3112 #define XX2BF_MASK (XX2_MASK | (3 << 21) | (1))
3114 /* The mask for an XX2 form instruction with the BF and DCMX bits
3116 #define XX2BFD_MASK (XX2 (0x3f, 0x1ff) | 1)
3118 /* The mask for an XX2 form instruction with a split DCMX bits
3120 #define XX2DCMXS_MASK XX2 (0x3f, 0x1ee)
3122 /* The mask for an XX3 form instruction. */
3123 #define XX3_MASK XX3 (0x3f, 0xff)
3125 /* The mask for an XX3 form instruction with the BF bits specified. */
3126 #define XX3BF_MASK (XX3 (0x3f, 0xff) | (3 << 21) | (1))
3128 /* The mask for an XX3 form instruction with the DM or SHW bits
3130 #define XX3DM_MASK (XX3 (0x3f, 0x1f) | (1 << 10))
3131 #define XX3SHW_MASK XX3DM_MASK
3133 /* The mask for an XX4 form instruction. */
3134 #define XX4_MASK XX4 (0x3f, 0x3)
3136 /* An X form wait instruction with everything filled in except the WC
3138 #define XWC_MASK (XRC (0x3f, 0x3ff, 1) | (7 << 23) | RA_MASK | RB_MASK)
3140 /* The mask for an XMMF form instruction. */
3141 #define XMMF_MASK (XMMF (0x3f, 0x3ff, 3, 7) | (1))
3143 /* The mask for a Z form instruction. */
3144 #define Z_MASK ZRC (0x3f, 0x1ff, 1)
3145 #define Z2_MASK ZRC (0x3f, 0xff, 1)
3147 /* An X_MASK with the RA/VA field fixed. */
3148 #define XRA_MASK (X_MASK | RA_MASK)
3149 #define XVA_MASK XRA_MASK
3151 /* An XRA_MASK with the A_L/W field clear. */
3152 #define XWRA_MASK (XRA_MASK & ~((uint64_t) 1 << 16))
3153 #define XRLA_MASK XWRA_MASK
3155 /* An X_MASK with the RB field fixed. */
3156 #define XRB_MASK (X_MASK | RB_MASK)
3158 /* An X_MASK with the RT field fixed. */
3159 #define XRT_MASK (X_MASK | RT_MASK)
3161 /* An XRT_MASK mask with the L bits clear. */
3162 #define XLRT_MASK (XRT_MASK & ~((uint64_t) 0x3 << 21))
3164 /* An X_MASK with the RA and RB fields fixed. */
3165 #define XRARB_MASK (X_MASK | RA_MASK | RB_MASK)
3167 /* An XBF_MASK with the RA and RB fields fixed. */
3168 #define XBFRARB_MASK (XBF_MASK | RA_MASK | RB_MASK)
3170 /* An XRARB_MASK, but with the L bit clear. */
3171 #define XRLARB_MASK (XRARB_MASK & ~((uint64_t) 1 << 16))
3173 /* An XRARB_MASK, but with the L bits in a darn instruction clear. */
3174 #define XLRAND_MASK (XRARB_MASK & ~((uint64_t) 3 << 16))
3176 /* An X_MASK with the RT and RA fields fixed. */
3177 #define XRTRA_MASK (X_MASK | RT_MASK | RA_MASK)
3179 /* An X_MASK with the RT and RB fields fixed. */
3180 #define XRTRB_MASK (X_MASK | RT_MASK | RB_MASK)
3182 /* An XRTRA_MASK, but with L bit clear. */
3183 #define XRTLRA_MASK (XRTRA_MASK & ~((uint64_t) 1 << 21))
3185 /* An X_MASK with the RT, RA and RB fields fixed. */
3186 #define XRTRARB_MASK (X_MASK | RT_MASK | RA_MASK | RB_MASK)
3188 /* An XRTRARB_MASK, but with L bit clear. */
3189 #define XRTLRARB_MASK (XRTRARB_MASK & ~((uint64_t) 1 << 21))
3191 /* An XRTRARB_MASK, but with A bit clear. */
3192 #define XRTARARB_MASK (XRTRARB_MASK & ~((uint64_t) 1 << 25))
3194 /* An XRTRARB_MASK, but with BF bits clear. */
3195 #define XRTBFRARB_MASK (XRTRARB_MASK & ~((uint64_t) 7 << 23))
3197 /* An X form instruction with the L bit specified. */
3198 #define XOPL(op, xop, l) \
3200 | ((((uint64_t)(l)) & 1) << 21))
3202 /* An X form instruction with the L bits specified. */
3203 #define XOPL2(op, xop, l) \
3205 | ((((uint64_t)(l)) & 3) << 21))
3207 /* An X form instruction with the L bit and RC bit specified. */
3208 #define XRCL(op, xop, l, rc) \
3209 (XRC ((op), (xop), (rc)) \
3210 | ((((uint64_t)(l)) & 1) << 21))
3212 /* An X form instruction with RT fields specified */
3213 #define XRT(op, xop, rt) \
3215 | ((((uint64_t)(rt)) & 0x1f) << 21))
3217 /* An X form instruction with RT and RA fields specified */
3218 #define XRTRA(op, xop, rt, ra) \
3220 | ((((uint64_t)(rt)) & 0x1f) << 21) \
3221 | ((((uint64_t)(ra)) & 0x1f) << 16))
3223 /* The mask for an X form comparison instruction. */
3224 #define XCMP_MASK (X_MASK | (((uint64_t)1) << 22))
3226 /* The mask for an X form comparison instruction with the L field
3228 #define XCMPL_MASK (XCMP_MASK | (((uint64_t)1) << 21))
3230 /* An X form trap instruction with the TO field specified. */
3231 #define XTO(op, xop, to) \
3233 | ((((uint64_t)(to)) & 0x1f) << 21))
3234 #define XTO_MASK (X_MASK | TO_MASK)
3236 /* An X form tlb instruction with the SH field specified. */
3237 #define XTLB(op, xop, sh) \
3239 | ((((uint64_t)(sh)) & 0x1f) << 11))
3240 #define XTLB_MASK (X_MASK | SH_MASK)
3242 /* An X form sync instruction. */
3243 #define XSYNC(op, xop, l) \
3245 | ((((uint64_t)(l)) & 3) << 21))
3247 /* An X form sync instruction with everything filled in except the LS
3249 #define XSYNC_MASK (0xff9fffff)
3251 /* An X form sync instruction with everything filled in except the L
3253 #define XSYNCLE_MASK (0xff90ffff)
3255 /* An X_MASK, but with the EH bit clear. */
3256 #define XEH_MASK (X_MASK & ~((uint64_t )1))
3258 /* An X form AltiVec dss instruction. */
3259 #define XDSS(op, xop, a) (X ((op), (xop)) | ((((uint64_t)(a)) & 1) << 25))
3260 #define XDSS_MASK XDSS(0x3f, 0x3ff, 1)
3262 /* An XFL form instruction. */
3263 #define XFL(op, xop, rc) \
3265 | ((((uint64_t)(xop)) & 0x3ff) << 1) \
3266 | (((uint64_t)(rc)) & 1))
3267 #define XFL_MASK XFL (0x3f, 0x3ff, 1)
3269 /* An X form isel instruction. */
3270 #define XISEL(op, xop) (OP (op) | ((((uint64_t)(xop)) & 0x1f) << 1))
3271 #define XISEL_MASK XISEL(0x3f, 0x1f)
3273 /* An XL form instruction with the LK field set to 0. */
3274 #define XL(op, xop) (OP (op) | ((((uint64_t)(xop)) & 0x3ff) << 1))
3276 /* An XL form instruction which uses the LK field. */
3277 #define XLLK(op, xop, lk) (XL ((op), (xop)) | ((lk) & 1))
3279 /* The mask for an XL form instruction. */
3280 #define XL_MASK XLLK (0x3f, 0x3ff, 1)
3282 /* An XL_MASK with the RT, RA and RB fields fixed, but S bit clear. */
3283 #define XLS_MASK ((XL_MASK | RT_MASK | RA_MASK | RB_MASK) & ~(1 << 11))
3285 /* An XL form instruction which explicitly sets the BO field. */
3286 #define XLO(op, bo, xop, lk) \
3287 (XLLK ((op), (xop), (lk)) | ((((uint64_t)(bo)) & 0x1f) << 21))
3288 #define XLO_MASK (XL_MASK | BO_MASK)
3290 /* An XL form instruction which explicitly sets the y bit of the BO
3292 #define XLYLK(op, xop, y, lk) \
3293 (XLLK ((op), (xop), (lk)) \
3294 | ((((uint64_t)(y)) & 1) << 21))
3295 #define XLYLK_MASK (XL_MASK | Y_MASK)
3297 /* An XL form instruction which sets the BO field and the condition
3298 bits of the BI field. */
3299 #define XLOCB(op, bo, cb, xop, lk) \
3300 (XLO ((op), (bo), (xop), (lk)) | ((((uint64_t)(cb)) & 3) << 16))
3301 #define XLOCB_MASK XLOCB (0x3f, 0x1f, 0x3, 0x3ff, 1)
3303 /* An XL_MASK or XLYLK_MASK or XLOCB_MASK with the BB field fixed. */
3304 #define XLBB_MASK (XL_MASK | BB_MASK)
3305 #define XLYBB_MASK (XLYLK_MASK | BB_MASK)
3306 #define XLBOCBBB_MASK (XLOCB_MASK | BB_MASK)
3308 /* A mask for branch instructions using the BH field. */
3309 #define XLBH_MASK (XL_MASK | (0x1c << 11))
3311 /* An XL_MASK with the BO and BB fields fixed. */
3312 #define XLBOBB_MASK (XL_MASK | BO_MASK | BB_MASK)
3314 /* An XL_MASK with the BO, BI and BB fields fixed. */
3315 #define XLBOBIBB_MASK (XL_MASK | BO_MASK | BI_MASK | BB_MASK)
3317 /* An X form mbar instruction with MO field. */
3318 #define XMBAR(op, xop, mo) \
3320 | ((((uint64_t)(mo)) & 1) << 21))
3322 /* An XO form instruction. */
3323 #define XO(op, xop, oe, rc) \
3325 | ((((uint64_t)(xop)) & 0x1ff) << 1) \
3326 | ((((uint64_t)(oe)) & 1) << 10) \
3327 | (((unsigned long)(rc)) & 1))
3328 #define XO_MASK XO (0x3f, 0x1ff, 1, 1)
3330 /* An XO_MASK with the RB field fixed. */
3331 #define XORB_MASK (XO_MASK | RB_MASK)
3333 /* An XOPS form instruction for paired singles. */
3334 #define XOPS(op, xop, rc) \
3336 | ((((uint64_t)(xop)) & 0x3ff) << 1) \
3337 | (((uint64_t)(rc)) & 1))
3338 #define XOPS_MASK XOPS (0x3f, 0x3ff, 1)
3341 /* An XS form instruction. */
3342 #define XS(op, xop, rc) \
3344 | ((((uint64_t)(xop)) & 0x1ff) << 2) \
3345 | (((uint64_t)(rc)) & 1))
3346 #define XS_MASK XS (0x3f, 0x1ff, 1)
3348 /* A mask for the FXM version of an XFX form instruction. */
3349 #define XFXFXM_MASK (X_MASK | (1 << 11) | (1 << 20))
3351 /* An XFX form instruction with the FXM field filled in. */
3352 #define XFXM(op, xop, fxm, p4) \
3354 | ((((uint64_t)(fxm)) & 0xff) << 12) \
3355 | ((uint64_t)(p4) << 20))
3357 /* An XFX form instruction with the SPR field filled in. */
3358 #define XSPR(op, xop, spr) \
3360 | ((((uint64_t)(spr)) & 0x1f) << 16) \
3361 | ((((uint64_t)(spr)) & 0x3e0) << 6))
3362 #define XSPR_MASK (X_MASK | SPR_MASK)
3364 /* An XFX form instruction with the SPR field filled in except for the
3366 #define XSPRBAT_MASK (XSPR_MASK &~ SPRBAT_MASK)
3368 /* An XFX form instruction with the SPR field filled in except for the
3370 #define XSPRG_MASK (XSPR_MASK & ~(0x1f << 16))
3372 /* An X form instruction with everything filled in except the E field. */
3373 #define XE_MASK (0xffff7fff)
3375 /* An X form user context instruction. */
3376 #define XUC(op, xop) (OP (op) | (((uint64_t)(xop)) & 0x1f))
3377 #define XUC_MASK XUC(0x3f, 0x1f)
3379 /* An XW form instruction. */
3380 #define XW(op, xop, rc) \
3382 | ((((uint64_t)(xop)) & 0x3f) << 1) \
3384 /* The mask for a G form instruction. rc not supported at present. */
3385 #define XW_MASK XW (0x3f, 0x3f, 0)
3387 /* An APU form instruction. */
3388 #define APU(op, xop, rc) \
3390 | (((uint64_t)(xop)) & 0x3ff) << 1 \
3393 /* The mask for an APU form instruction. */
3394 #define APU_MASK APU (0x3f, 0x3ff, 1)
3395 #define APU_RT_MASK (APU_MASK | RT_MASK)
3396 #define APU_RA_MASK (APU_MASK | RA_MASK)
3398 /* The BO encodings used in extended conditional branch mnemonics. */
3399 #define BODNZF (0x0)
3400 #define BODNZFP (0x1)
3402 #define BODZFP (0x3)
3403 #define BODNZT (0x8)
3404 #define BODNZTP (0x9)
3406 #define BODZTP (0xb)
3417 #define BODNZ (0x10)
3418 #define BODNZP (0x11)
3420 #define BODZP (0x13)
3421 #define BODNZM4 (0x18)
3422 #define BODNZP4 (0x19)
3423 #define BODZM4 (0x1a)
3424 #define BODZP4 (0x1b)
3428 /* The BO16 encodings used in extended VLE conditional branch mnemonics. */
3432 /* The BO32 encodings used in extended VLE conditional branch mnemonics. */
3435 #define BO32DNZ (0x2)
3436 #define BO32DZ (0x3)
3438 /* The BI condition bit encodings used in extended conditional branch
3445 /* The TO encodings used in extended trap mnemonics. */
3462 /* Smaller names for the flags so each entry in the opcodes table will
3463 fit on a single line. */
3465 #define PPC PPC_OPCODE_PPC
3466 #define PPCCOM PPC_OPCODE_PPC | PPC_OPCODE_COMMON
3467 #define POWER4 PPC_OPCODE_POWER4
3468 #define POWER5 PPC_OPCODE_POWER5
3469 #define POWER6 PPC_OPCODE_POWER6
3470 #define POWER7 PPC_OPCODE_POWER7
3471 #define POWER8 PPC_OPCODE_POWER8
3472 #define POWER9 PPC_OPCODE_POWER9
3473 #define CELL PPC_OPCODE_CELL
3474 #define PPC64 PPC_OPCODE_64 | PPC_OPCODE_64_BRIDGE
3475 #define NON32 (PPC_OPCODE_64 | PPC_OPCODE_POWER4 \
3476 | PPC_OPCODE_EFS | PPC_OPCODE_E500MC | PPC_OPCODE_TITAN)
3477 #define PPC403 PPC_OPCODE_403
3478 #define PPC405 PPC_OPCODE_405
3479 #define PPC440 PPC_OPCODE_440
3480 #define PPC464 PPC440
3481 #define PPC476 PPC_OPCODE_476
3482 #define PPC750 PPC_OPCODE_750
3483 #define PPC7450 PPC_OPCODE_7450
3484 #define PPC860 PPC_OPCODE_860
3485 #define PPCPS PPC_OPCODE_PPCPS
3486 #define PPCVEC PPC_OPCODE_ALTIVEC
3487 #define PPCVEC2 (PPC_OPCODE_POWER8 | PPC_OPCODE_E6500)
3488 #define PPCVEC3 PPC_OPCODE_POWER9
3489 #define PPCVSX PPC_OPCODE_VSX
3490 #define PPCVSX2 PPC_OPCODE_POWER8
3491 #define PPCVSX3 PPC_OPCODE_POWER9
3492 #define POWER PPC_OPCODE_POWER
3493 #define POWER2 PPC_OPCODE_POWER | PPC_OPCODE_POWER2
3494 #define PWR2COM PPC_OPCODE_POWER | PPC_OPCODE_POWER2 | PPC_OPCODE_COMMON
3495 #define PPCPWR2 (PPC_OPCODE_PPC | PPC_OPCODE_POWER | PPC_OPCODE_POWER2 \
3496 | PPC_OPCODE_COMMON)
3497 #define COM PPC_OPCODE_POWER | PPC_OPCODE_PPC | PPC_OPCODE_COMMON
3498 #define M601 PPC_OPCODE_POWER | PPC_OPCODE_601
3499 #define PWRCOM PPC_OPCODE_POWER | PPC_OPCODE_601 | PPC_OPCODE_COMMON
3500 #define MFDEC1 PPC_OPCODE_POWER
3501 #define MFDEC2 (PPC_OPCODE_PPC | PPC_OPCODE_601 | PPC_OPCODE_BOOKE \
3503 #define BOOKE PPC_OPCODE_BOOKE
3504 #define NO371 PPC_OPCODE_BOOKE | PPC_OPCODE_PPCPS | PPC_OPCODE_EFS
3505 #define PPCE300 PPC_OPCODE_E300
3506 #define PPCSPE PPC_OPCODE_SPE
3507 #define PPCSPE2 PPC_OPCODE_SPE2
3508 #define PPCISEL PPC_OPCODE_ISEL
3509 #define PPCEFS PPC_OPCODE_EFS
3510 #define PPCEFS2 PPC_OPCODE_EFS2
3511 #define PPCBRLK PPC_OPCODE_BRLOCK
3512 #define PPCPMR PPC_OPCODE_PMR
3513 #define PPCTMR PPC_OPCODE_TMR
3514 #define PPCCHLK PPC_OPCODE_CACHELCK
3515 #define PPCRFMCI PPC_OPCODE_RFMCI
3516 #define E500MC PPC_OPCODE_E500MC
3517 #define PPCA2 PPC_OPCODE_A2
3518 #define TITAN PPC_OPCODE_TITAN
3519 #define MULHW PPC_OPCODE_405 | PPC_OPCODE_440 | PPC_OPCODE_476 | TITAN
3520 #define E500 PPC_OPCODE_E500
3521 #define E6500 PPC_OPCODE_E6500
3522 #define PPCVLE PPC_OPCODE_VLE
3523 #define PPCHTM PPC_OPCODE_POWER8
3524 #define E200Z4 PPC_OPCODE_E200Z4
3525 #define PPCLSP PPC_OPCODE_LSP
3526 /* The list of embedded processors that use the embedded operand ordering
3527 for the 3 operand dcbt and dcbtst instructions. */
3528 #define DCBT_EO (PPC_OPCODE_E500 | PPC_OPCODE_E500MC | PPC_OPCODE_476 \
3533 /* The opcode table.
3535 The format of the opcode table is:
3537 NAME OPCODE MASK FLAGS ANTI {OPERANDS}
3539 NAME is the name of the instruction.
3540 OPCODE is the instruction opcode.
3541 MASK is the opcode mask; this is used to tell the disassembler
3542 which bits in the actual opcode must match OPCODE.
3543 FLAGS are flags indicating which processors support the instruction.
3544 ANTI indicates which processors don't support the instruction.
3545 OPERANDS is the list of operands.
3547 The disassembler reads the table in order and prints the first
3548 instruction which matches, so this table is sorted to put more
3549 specific instructions before more general instructions.
3551 This table must be sorted by major opcode. Please try to keep it
3552 vaguely sorted within major opcode too, except of course where
3553 constrained otherwise by disassembler operation. */
3555 const struct powerpc_opcode powerpc_opcodes
[] = {
3556 {"attn", X(0,256), X_MASK
, POWER4
|PPCA2
, PPC476
|PPCVLE
, {0}},
3557 {"tdlgti", OPTO(2,TOLGT
), OPTO_MASK
, PPC64
, PPCVLE
, {RA
, SI
}},
3558 {"tdllti", OPTO(2,TOLLT
), OPTO_MASK
, PPC64
, PPCVLE
, {RA
, SI
}},
3559 {"tdeqi", OPTO(2,TOEQ
), OPTO_MASK
, PPC64
, PPCVLE
, {RA
, SI
}},
3560 {"tdlgei", OPTO(2,TOLGE
), OPTO_MASK
, PPC64
, PPCVLE
, {RA
, SI
}},
3561 {"tdlnli", OPTO(2,TOLNL
), OPTO_MASK
, PPC64
, PPCVLE
, {RA
, SI
}},
3562 {"tdllei", OPTO(2,TOLLE
), OPTO_MASK
, PPC64
, PPCVLE
, {RA
, SI
}},
3563 {"tdlngi", OPTO(2,TOLNG
), OPTO_MASK
, PPC64
, PPCVLE
, {RA
, SI
}},
3564 {"tdgti", OPTO(2,TOGT
), OPTO_MASK
, PPC64
, PPCVLE
, {RA
, SI
}},
3565 {"tdgei", OPTO(2,TOGE
), OPTO_MASK
, PPC64
, PPCVLE
, {RA
, SI
}},
3566 {"tdnli", OPTO(2,TONL
), OPTO_MASK
, PPC64
, PPCVLE
, {RA
, SI
}},
3567 {"tdlti", OPTO(2,TOLT
), OPTO_MASK
, PPC64
, PPCVLE
, {RA
, SI
}},
3568 {"tdlei", OPTO(2,TOLE
), OPTO_MASK
, PPC64
, PPCVLE
, {RA
, SI
}},
3569 {"tdngi", OPTO(2,TONG
), OPTO_MASK
, PPC64
, PPCVLE
, {RA
, SI
}},
3570 {"tdnei", OPTO(2,TONE
), OPTO_MASK
, PPC64
, PPCVLE
, {RA
, SI
}},
3571 {"tdui", OPTO(2,TOU
), OPTO_MASK
, PPC64
, PPCVLE
, {RA
, SI
}},
3572 {"tdi", OP(2), OP_MASK
, PPC64
, PPCVLE
, {TO
, RA
, SI
}},
3574 {"twlgti", OPTO(3,TOLGT
), OPTO_MASK
, PPCCOM
, PPCVLE
, {RA
, SI
}},
3575 {"tlgti", OPTO(3,TOLGT
), OPTO_MASK
, PWRCOM
, PPCVLE
, {RA
, SI
}},
3576 {"twllti", OPTO(3,TOLLT
), OPTO_MASK
, PPCCOM
, PPCVLE
, {RA
, SI
}},
3577 {"tllti", OPTO(3,TOLLT
), OPTO_MASK
, PWRCOM
, PPCVLE
, {RA
, SI
}},
3578 {"tweqi", OPTO(3,TOEQ
), OPTO_MASK
, PPCCOM
, PPCVLE
, {RA
, SI
}},
3579 {"teqi", OPTO(3,TOEQ
), OPTO_MASK
, PWRCOM
, PPCVLE
, {RA
, SI
}},
3580 {"twlgei", OPTO(3,TOLGE
), OPTO_MASK
, PPCCOM
, PPCVLE
, {RA
, SI
}},
3581 {"tlgei", OPTO(3,TOLGE
), OPTO_MASK
, PWRCOM
, PPCVLE
, {RA
, SI
}},
3582 {"twlnli", OPTO(3,TOLNL
), OPTO_MASK
, PPCCOM
, PPCVLE
, {RA
, SI
}},
3583 {"tlnli", OPTO(3,TOLNL
), OPTO_MASK
, PWRCOM
, PPCVLE
, {RA
, SI
}},
3584 {"twllei", OPTO(3,TOLLE
), OPTO_MASK
, PPCCOM
, PPCVLE
, {RA
, SI
}},
3585 {"tllei", OPTO(3,TOLLE
), OPTO_MASK
, PWRCOM
, PPCVLE
, {RA
, SI
}},
3586 {"twlngi", OPTO(3,TOLNG
), OPTO_MASK
, PPCCOM
, PPCVLE
, {RA
, SI
}},
3587 {"tlngi", OPTO(3,TOLNG
), OPTO_MASK
, PWRCOM
, PPCVLE
, {RA
, SI
}},
3588 {"twgti", OPTO(3,TOGT
), OPTO_MASK
, PPCCOM
, PPCVLE
, {RA
, SI
}},
3589 {"tgti", OPTO(3,TOGT
), OPTO_MASK
, PWRCOM
, PPCVLE
, {RA
, SI
}},
3590 {"twgei", OPTO(3,TOGE
), OPTO_MASK
, PPCCOM
, PPCVLE
, {RA
, SI
}},
3591 {"tgei", OPTO(3,TOGE
), OPTO_MASK
, PWRCOM
, PPCVLE
, {RA
, SI
}},
3592 {"twnli", OPTO(3,TONL
), OPTO_MASK
, PPCCOM
, PPCVLE
, {RA
, SI
}},
3593 {"tnli", OPTO(3,TONL
), OPTO_MASK
, PWRCOM
, PPCVLE
, {RA
, SI
}},
3594 {"twlti", OPTO(3,TOLT
), OPTO_MASK
, PPCCOM
, PPCVLE
, {RA
, SI
}},
3595 {"tlti", OPTO(3,TOLT
), OPTO_MASK
, PWRCOM
, PPCVLE
, {RA
, SI
}},
3596 {"twlei", OPTO(3,TOLE
), OPTO_MASK
, PPCCOM
, PPCVLE
, {RA
, SI
}},
3597 {"tlei", OPTO(3,TOLE
), OPTO_MASK
, PWRCOM
, PPCVLE
, {RA
, SI
}},
3598 {"twngi", OPTO(3,TONG
), OPTO_MASK
, PPCCOM
, PPCVLE
, {RA
, SI
}},
3599 {"tngi", OPTO(3,TONG
), OPTO_MASK
, PWRCOM
, PPCVLE
, {RA
, SI
}},
3600 {"twnei", OPTO(3,TONE
), OPTO_MASK
, PPCCOM
, PPCVLE
, {RA
, SI
}},
3601 {"tnei", OPTO(3,TONE
), OPTO_MASK
, PWRCOM
, PPCVLE
, {RA
, SI
}},
3602 {"twui", OPTO(3,TOU
), OPTO_MASK
, PPCCOM
, PPCVLE
, {RA
, SI
}},
3603 {"tui", OPTO(3,TOU
), OPTO_MASK
, PWRCOM
, PPCVLE
, {RA
, SI
}},
3604 {"twi", OP(3), OP_MASK
, PPCCOM
, PPCVLE
, {TO
, RA
, SI
}},
3605 {"ti", OP(3), OP_MASK
, PWRCOM
, PPCVLE
, {TO
, RA
, SI
}},
3607 {"ps_cmpu0", X (4, 0), XBF_MASK
, PPCPS
, 0, {BF
, FRA
, FRB
}},
3608 {"vaddubm", VX (4, 0), VX_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
3609 {"vmul10cuq", VX (4, 1), VXVB_MASK
, PPCVEC3
, 0, {VD
, VA
}},
3610 {"vmaxub", VX (4, 2), VX_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
3611 {"vrlb", VX (4, 4), VX_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
3612 {"vcmpequb", VXR(4, 6,0), VXR_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
3613 {"vcmpneb", VXR(4, 7,0), VXR_MASK
, PPCVEC3
, 0, {VD
, VA
, VB
}},
3614 {"vmuloub", VX (4, 8), VX_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
3615 {"vaddfp", VX (4, 10), VX_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
3616 {"psq_lx", XW (4, 6,0), XW_MASK
, PPCPS
, 0, {FRT
,RA
,RB
,PSWM
,PSQM
}},
3617 {"vmrghb", VX (4, 12), VX_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
3618 {"psq_stx", XW (4, 7,0), XW_MASK
, PPCPS
, 0, {FRS
,RA
,RB
,PSWM
,PSQM
}},
3619 {"vpkuhum", VX (4, 14), VX_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
3620 {"mulhhwu", XRC(4, 8,0), X_MASK
, MULHW
, 0, {RT
, RA
, RB
}},
3621 {"mulhhwu.", XRC(4, 8,1), X_MASK
, MULHW
, 0, {RT
, RA
, RB
}},
3622 {"ps_sum0", A (4, 10,0), A_MASK
, PPCPS
, 0, {FRT
, FRA
, FRC
, FRB
}},
3623 {"ps_sum0.", A (4, 10,1), A_MASK
, PPCPS
, 0, {FRT
, FRA
, FRC
, FRB
}},
3624 {"ps_sum1", A (4, 11,0), A_MASK
, PPCPS
, 0, {FRT
, FRA
, FRC
, FRB
}},
3625 {"ps_sum1.", A (4, 11,1), A_MASK
, PPCPS
, 0, {FRT
, FRA
, FRC
, FRB
}},
3626 {"ps_muls0", A (4, 12,0), AFRB_MASK
, PPCPS
, 0, {FRT
, FRA
, FRC
}},
3627 {"machhwu", XO (4, 12,0,0), XO_MASK
, MULHW
, 0, {RT
, RA
, RB
}},
3628 {"ps_muls0.", A (4, 12,1), AFRB_MASK
, PPCPS
, 0, {FRT
, FRA
, FRC
}},
3629 {"machhwu.", XO (4, 12,0,1), XO_MASK
, MULHW
, 0, {RT
, RA
, RB
}},
3630 {"ps_muls1", A (4, 13,0), AFRB_MASK
, PPCPS
, 0, {FRT
, FRA
, FRC
}},
3631 {"ps_muls1.", A (4, 13,1), AFRB_MASK
, PPCPS
, 0, {FRT
, FRA
, FRC
}},
3632 {"ps_madds0", A (4, 14,0), A_MASK
, PPCPS
, 0, {FRT
, FRA
, FRC
, FRB
}},
3633 {"ps_madds0.", A (4, 14,1), A_MASK
, PPCPS
, 0, {FRT
, FRA
, FRC
, FRB
}},
3634 {"ps_madds1", A (4, 15,0), A_MASK
, PPCPS
, 0, {FRT
, FRA
, FRC
, FRB
}},
3635 {"ps_madds1.", A (4, 15,1), A_MASK
, PPCPS
, 0, {FRT
, FRA
, FRC
, FRB
}},
3636 {"vmhaddshs", VXA(4, 32), VXA_MASK
, PPCVEC
, 0, {VD
, VA
, VB
, VC
}},
3637 {"vmhraddshs", VXA(4, 33), VXA_MASK
, PPCVEC
, 0, {VD
, VA
, VB
, VC
}},
3638 {"vmladduhm", VXA(4, 34), VXA_MASK
, PPCVEC
, 0, {VD
, VA
, VB
, VC
}},
3639 {"vmsumudm", VXA(4, 35), VXA_MASK
, PPCVEC3
, 0, {VD
, VA
, VB
, VC
}},
3640 {"ps_div", A (4, 18,0), AFRC_MASK
, PPCPS
, 0, {FRT
, FRA
, FRB
}},
3641 {"vmsumubm", VXA(4, 36), VXA_MASK
, PPCVEC
, 0, {VD
, VA
, VB
, VC
}},
3642 {"ps_div.", A (4, 18,1), AFRC_MASK
, PPCPS
, 0, {FRT
, FRA
, FRB
}},
3643 {"vmsummbm", VXA(4, 37), VXA_MASK
, PPCVEC
, 0, {VD
, VA
, VB
, VC
}},
3644 {"vmsumuhm", VXA(4, 38), VXA_MASK
, PPCVEC
, 0, {VD
, VA
, VB
, VC
}},
3645 {"vmsumuhs", VXA(4, 39), VXA_MASK
, PPCVEC
, 0, {VD
, VA
, VB
, VC
}},
3646 {"ps_sub", A (4, 20,0), AFRC_MASK
, PPCPS
, 0, {FRT
, FRA
, FRB
}},
3647 {"vmsumshm", VXA(4, 40), VXA_MASK
, PPCVEC
, 0, {VD
, VA
, VB
, VC
}},
3648 {"ps_sub.", A (4, 20,1), AFRC_MASK
, PPCPS
, 0, {FRT
, FRA
, FRB
}},
3649 {"vmsumshs", VXA(4, 41), VXA_MASK
, PPCVEC
, 0, {VD
, VA
, VB
, VC
}},
3650 {"ps_add", A (4, 21,0), AFRC_MASK
, PPCPS
, 0, {FRT
, FRA
, FRB
}},
3651 {"vsel", VXA(4, 42), VXA_MASK
, PPCVEC
, 0, {VD
, VA
, VB
, VC
}},
3652 {"ps_add.", A (4, 21,1), AFRC_MASK
, PPCPS
, 0, {FRT
, FRA
, FRB
}},
3653 {"vperm", VXA(4, 43), VXA_MASK
, PPCVEC
, 0, {VD
, VA
, VB
, VC
}},
3654 {"vsldoi", VXA(4, 44), VXASHB_MASK
, PPCVEC
, 0, {VD
, VA
, VB
, SHB
}},
3655 {"vpermxor", VXA(4, 45), VXA_MASK
, PPCVEC2
, 0, {VD
, VA
, VB
, VC
}},
3656 {"ps_sel", A (4, 23,0), A_MASK
, PPCPS
, 0, {FRT
, FRA
, FRC
, FRB
}},
3657 {"vmaddfp", VXA(4, 46), VXA_MASK
, PPCVEC
, 0, {VD
, VA
, VC
, VB
}},
3658 {"ps_sel.", A (4, 23,1), A_MASK
, PPCPS
, 0, {FRT
, FRA
, FRC
, FRB
}},
3659 {"vnmsubfp", VXA(4, 47), VXA_MASK
, PPCVEC
, 0, {VD
, VA
, VC
, VB
}},
3660 {"ps_res", A (4, 24,0), AFRAFRC_MASK
, PPCPS
, 0, {FRT
, FRB
}},
3661 {"maddhd", VXA(4, 48), VXA_MASK
, POWER9
, 0, {RT
, RA
, RB
, RC
}},
3662 {"ps_res.", A (4, 24,1), AFRAFRC_MASK
, PPCPS
, 0, {FRT
, FRB
}},
3663 {"maddhdu", VXA(4, 49), VXA_MASK
, POWER9
, 0, {RT
, RA
, RB
, RC
}},
3664 {"ps_mul", A (4, 25,0), AFRB_MASK
, PPCPS
, 0, {FRT
, FRA
, FRC
}},
3665 {"ps_mul.", A (4, 25,1), AFRB_MASK
, PPCPS
, 0, {FRT
, FRA
, FRC
}},
3666 {"maddld", VXA(4, 51), VXA_MASK
, POWER9
, 0, {RT
, RA
, RB
, RC
}},
3667 {"ps_rsqrte", A (4, 26,0), AFRAFRC_MASK
, PPCPS
, 0, {FRT
, FRB
}},
3668 {"ps_rsqrte.", A (4, 26,1), AFRAFRC_MASK
, PPCPS
, 0, {FRT
, FRB
}},
3669 {"ps_msub", A (4, 28,0), A_MASK
, PPCPS
, 0, {FRT
, FRA
, FRC
, FRB
}},
3670 {"ps_msub.", A (4, 28,1), A_MASK
, PPCPS
, 0, {FRT
, FRA
, FRC
, FRB
}},
3671 {"ps_madd", A (4, 29,0), A_MASK
, PPCPS
, 0, {FRT
, FRA
, FRC
, FRB
}},
3672 {"ps_madd.", A (4, 29,1), A_MASK
, PPCPS
, 0, {FRT
, FRA
, FRC
, FRB
}},
3673 {"vpermr", VXA(4, 59), VXA_MASK
, PPCVEC3
, 0, {VD
, VA
, VB
, VC
}},
3674 {"ps_nmsub", A (4, 30,0), A_MASK
, PPCPS
, 0, {FRT
, FRA
, FRC
, FRB
}},
3675 {"vaddeuqm", VXA(4, 60), VXA_MASK
, PPCVEC2
, 0, {VD
, VA
, VB
, VC
}},
3676 {"ps_nmsub.", A (4, 30,1), A_MASK
, PPCPS
, 0, {FRT
, FRA
, FRC
, FRB
}},
3677 {"vaddecuq", VXA(4, 61), VXA_MASK
, PPCVEC2
, 0, {VD
, VA
, VB
, VC
}},
3678 {"ps_nmadd", A (4, 31,0), A_MASK
, PPCPS
, 0, {FRT
, FRA
, FRC
, FRB
}},
3679 {"vsubeuqm", VXA(4, 62), VXA_MASK
, PPCVEC2
, 0, {VD
, VA
, VB
, VC
}},
3680 {"ps_nmadd.", A (4, 31,1), A_MASK
, PPCPS
, 0, {FRT
, FRA
, FRC
, FRB
}},
3681 {"vsubecuq", VXA(4, 63), VXA_MASK
, PPCVEC2
, 0, {VD
, VA
, VB
, VC
}},
3682 {"ps_cmpo0", X (4, 32), XBF_MASK
, PPCPS
, 0, {BF
, FRA
, FRB
}},
3683 {"vadduhm", VX (4, 64), VX_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
3684 {"vmul10ecuq", VX (4, 65), VX_MASK
, PPCVEC3
, 0, {VD
, VA
, VB
}},
3685 {"vmaxuh", VX (4, 66), VX_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
3686 {"vrlh", VX (4, 68), VX_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
3687 {"vcmpequh", VXR(4, 70,0), VXR_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
3688 {"vcmpneh", VXR(4, 71,0), VXR_MASK
, PPCVEC3
, 0, {VD
, VA
, VB
}},
3689 {"vmulouh", VX (4, 72), VX_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
3690 {"vsubfp", VX (4, 74), VX_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
3691 {"psq_lux", XW (4, 38,0), XW_MASK
, PPCPS
, 0, {FRT
,RA
,RB
,PSWM
,PSQM
}},
3692 {"vmrghh", VX (4, 76), VX_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
3693 {"psq_stux", XW (4, 39,0), XW_MASK
, PPCPS
, 0, {FRS
,RA
,RB
,PSWM
,PSQM
}},
3694 {"vpkuwum", VX (4, 78), VX_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
3695 {"ps_neg", XRC(4, 40,0), XRA_MASK
, PPCPS
, 0, {FRT
, FRB
}},
3696 {"mulhhw", XRC(4, 40,0), X_MASK
, MULHW
, 0, {RT
, RA
, RB
}},
3697 {"ps_neg.", XRC(4, 40,1), XRA_MASK
, PPCPS
, 0, {FRT
, FRB
}},
3698 {"mulhhw.", XRC(4, 40,1), X_MASK
, MULHW
, 0, {RT
, RA
, RB
}},
3699 {"machhw", XO (4, 44,0,0), XO_MASK
, MULHW
, 0, {RT
, RA
, RB
}},
3700 {"machhw.", XO (4, 44,0,1), XO_MASK
, MULHW
, 0, {RT
, RA
, RB
}},
3701 {"nmachhw", XO (4, 46,0,0), XO_MASK
, MULHW
, 0, {RT
, RA
, RB
}},
3702 {"nmachhw.", XO (4, 46,0,1), XO_MASK
, MULHW
, 0, {RT
, RA
, RB
}},
3703 {"ps_cmpu1", X (4, 64), XBF_MASK
, PPCPS
, 0, {BF
, FRA
, FRB
}},
3704 {"vadduwm", VX (4, 128), VX_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
3705 {"vmaxuw", VX (4, 130), VX_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
3706 {"vrlw", VX (4, 132), VX_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
3707 {"vrlwmi", VX (4, 133), VX_MASK
, PPCVEC3
, 0, {VD
, VA
, VB
}},
3708 {"vcmpequw", VXR(4, 134,0), VXR_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
3709 {"vcmpnew", VXR(4, 135,0), VXR_MASK
, PPCVEC3
, 0, {VD
, VA
, VB
}},
3710 {"vmulouw", VX (4, 136), VX_MASK
, PPCVEC2
, 0, {VD
, VA
, VB
}},
3711 {"vmuluwm", VX (4, 137), VX_MASK
, PPCVEC2
, 0, {VD
, VA
, VB
}},
3712 {"vmrghw", VX (4, 140), VX_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
3713 {"vpkuhus", VX (4, 142), VX_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
3714 {"ps_mr", XRC(4, 72,0), XRA_MASK
, PPCPS
, 0, {FRT
, FRB
}},
3715 {"ps_mr.", XRC(4, 72,1), XRA_MASK
, PPCPS
, 0, {FRT
, FRB
}},
3716 {"machhwsu", XO (4, 76,0,0), XO_MASK
, MULHW
, 0, {RT
, RA
, RB
}},
3717 {"machhwsu.", XO (4, 76,0,1), XO_MASK
, MULHW
, 0, {RT
, RA
, RB
}},
3718 {"ps_cmpo1", X (4, 96), XBF_MASK
, PPCPS
, 0, {BF
, FRA
, FRB
}},
3719 {"vaddudm", VX (4, 192), VX_MASK
, PPCVEC2
, 0, {VD
, VA
, VB
}},
3720 {"vmaxud", VX (4, 194), VX_MASK
, PPCVEC2
, 0, {VD
, VA
, VB
}},
3721 {"vrld", VX (4, 196), VX_MASK
, PPCVEC2
, 0, {VD
, VA
, VB
}},
3722 {"vrldmi", VX (4, 197), VX_MASK
, PPCVEC3
, 0, {VD
, VA
, VB
}},
3723 {"vcmpeqfp", VXR(4, 198,0), VXR_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
3724 {"vcmpequd", VXR(4, 199,0), VXR_MASK
, PPCVEC2
, 0, {VD
, VA
, VB
}},
3725 {"vpkuwus", VX (4, 206), VX_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
3726 {"machhws", XO (4, 108,0,0), XO_MASK
, MULHW
, 0, {RT
, RA
, RB
}},
3727 {"machhws.", XO (4, 108,0,1), XO_MASK
, MULHW
, 0, {RT
, RA
, RB
}},
3728 {"nmachhws", XO (4, 110,0,0), XO_MASK
, MULHW
, 0, {RT
, RA
, RB
}},
3729 {"nmachhws.", XO (4, 110,0,1), XO_MASK
, MULHW
, 0, {RT
, RA
, RB
}},
3730 {"vadduqm", VX (4, 256), VX_MASK
, PPCVEC2
, 0, {VD
, VA
, VB
}},
3731 {"vmaxsb", VX (4, 258), VX_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
3732 {"vslb", VX (4, 260), VX_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
3733 {"vcmpnezb", VXR(4, 263,0), VXR_MASK
, PPCVEC3
, 0, {VD
, VA
, VB
}},
3734 {"vmulosb", VX (4, 264), VX_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
3735 {"vrefp", VX (4, 266), VXVA_MASK
, PPCVEC
, 0, {VD
, VB
}},
3736 {"vmrglb", VX (4, 268), VX_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
3737 {"vpkshus", VX (4, 270), VX_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
3738 {"ps_nabs", XRC(4, 136,0), XRA_MASK
, PPCPS
, 0, {FRT
, FRB
}},
3739 {"mulchwu", XRC(4, 136,0), X_MASK
, MULHW
, 0, {RT
, RA
, RB
}},
3740 {"ps_nabs.", XRC(4, 136,1), XRA_MASK
, PPCPS
, 0, {FRT
, FRB
}},
3741 {"mulchwu.", XRC(4, 136,1), X_MASK
, MULHW
, 0, {RT
, RA
, RB
}},
3742 {"macchwu", XO (4, 140,0,0), XO_MASK
, MULHW
, 0, {RT
, RA
, RB
}},
3743 {"macchwu.", XO (4, 140,0,1), XO_MASK
, MULHW
, 0, {RT
, RA
, RB
}},
3744 {"vaddcuq", VX (4, 320), VX_MASK
, PPCVEC2
, 0, {VD
, VA
, VB
}},
3745 {"vmaxsh", VX (4, 322), VX_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
3746 {"vslh", VX (4, 324), VX_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
3747 {"vcmpnezh", VXR(4, 327,0), VXR_MASK
, PPCVEC3
, 0, {VD
, VA
, VB
}},
3748 {"vmulosh", VX (4, 328), VX_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
3749 {"vrsqrtefp", VX (4, 330), VXVA_MASK
, PPCVEC
, 0, {VD
, VB
}},
3750 {"vmrglh", VX (4, 332), VX_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
3751 {"vpkswus", VX (4, 334), VX_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
3752 {"mulchw", XRC(4, 168,0), X_MASK
, MULHW
, 0, {RT
, RA
, RB
}},
3753 {"mulchw.", XRC(4, 168,1), X_MASK
, MULHW
, 0, {RT
, RA
, RB
}},
3754 {"macchw", XO (4, 172,0,0), XO_MASK
, MULHW
, 0, {RT
, RA
, RB
}},
3755 {"macchw.", XO (4, 172,0,1), XO_MASK
, MULHW
, 0, {RT
, RA
, RB
}},
3756 {"nmacchw", XO (4, 174,0,0), XO_MASK
, MULHW
, 0, {RT
, RA
, RB
}},
3757 {"nmacchw.", XO (4, 174,0,1), XO_MASK
, MULHW
, 0, {RT
, RA
, RB
}},
3758 {"vaddcuw", VX (4, 384), VX_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
3759 {"vmaxsw", VX (4, 386), VX_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
3760 {"vslw", VX (4, 388), VX_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
3761 {"vrlwnm", VX (4, 389), VX_MASK
, PPCVEC3
, 0, {VD
, VA
, VB
}},
3762 {"vcmpnezw", VXR(4, 391,0), VXR_MASK
, PPCVEC3
, 0, {VD
, VA
, VB
}},
3763 {"vmulosw", VX (4, 392), VX_MASK
, PPCVEC2
, 0, {VD
, VA
, VB
}},
3764 {"vexptefp", VX (4, 394), VXVA_MASK
, PPCVEC
, 0, {VD
, VB
}},
3765 {"vmrglw", VX (4, 396), VX_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
3766 {"vpkshss", VX (4, 398), VX_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
3767 {"macchwsu", XO (4, 204,0,0), XO_MASK
, MULHW
, 0, {RT
, RA
, RB
}},
3768 {"macchwsu.", XO (4, 204,0,1), XO_MASK
, MULHW
, 0, {RT
, RA
, RB
}},
3769 {"vmaxsd", VX (4, 450), VX_MASK
, PPCVEC2
, 0, {VD
, VA
, VB
}},
3770 {"vsl", VX (4, 452), VX_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
3771 {"vrldnm", VX (4, 453), VX_MASK
, PPCVEC3
, 0, {VD
, VA
, VB
}},
3772 {"vcmpgefp", VXR(4, 454,0), VXR_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
3773 {"vlogefp", VX (4, 458), VXVA_MASK
, PPCVEC
, 0, {VD
, VB
}},
3774 {"vpkswss", VX (4, 462), VX_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
3775 {"macchws", XO (4, 236,0,0), XO_MASK
, MULHW
, 0, {RT
, RA
, RB
}},
3776 {"macchws.", XO (4, 236,0,1), XO_MASK
, MULHW
, 0, {RT
, RA
, RB
}},
3777 {"nmacchws", XO (4, 238,0,0), XO_MASK
, MULHW
, 0, {RT
, RA
, RB
}},
3778 {"nmacchws.", XO (4, 238,0,1), XO_MASK
, MULHW
, 0, {RT
, RA
, RB
}},
3779 {"evaddw", VX (4, 512), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
3780 {"vaddubs", VX (4, 512), VX_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
3781 {"vmul10uq", VX (4, 513), VXVB_MASK
, PPCVEC3
, 0, {VD
, VA
}},
3782 {"evaddiw", VX (4, 514), VX_MASK
, PPCSPE
, 0, {RS
, RB
, UIMM
}},
3783 {"vminub", VX (4, 514), VX_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
3784 {"evsubfw", VX (4, 516), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
3785 {"evsubw", VX (4, 516), VX_MASK
, PPCSPE
, 0, {RS
, RB
, RA
}},
3786 {"vsrb", VX (4, 516), VX_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
3787 {"evsubifw", VX (4, 518), VX_MASK
, PPCSPE
, 0, {RS
, UIMM
, RB
}},
3788 {"evsubiw", VX (4, 518), VX_MASK
, PPCSPE
, 0, {RS
, RB
, UIMM
}},
3789 {"vcmpgtub", VXR(4, 518,0), VXR_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
3790 {"evabs", VX (4, 520), VX_MASK
, PPCSPE
, 0, {RS
, RA
}},
3791 {"vmuleub", VX (4, 520), VX_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
3792 {"evneg", VX (4, 521), VX_MASK
, PPCSPE
, 0, {RS
, RA
}},
3793 {"evextsb", VX (4, 522), VX_MASK
, PPCSPE
, 0, {RS
, RA
}},
3794 {"vrfin", VX (4, 522), VXVA_MASK
, PPCVEC
, 0, {VD
, VB
}},
3795 {"evextsh", VX (4, 523), VX_MASK
, PPCSPE
, 0, {RS
, RA
}},
3796 {"evrndw", VX (4, 524), VX_MASK
, PPCSPE
, 0, {RS
, RA
}},
3797 {"vspltb", VX (4, 524), VXUIMM4_MASK
, PPCVEC
, 0, {VD
, VB
, UIMM4
}},
3798 {"vextractub", VX (4, 525), VXUIMM4_MASK
, PPCVEC3
, 0, {VD
, VB
, UIMM4
}},
3799 {"evcntlzw", VX (4, 525), VX_MASK
, PPCSPE
, 0, {RS
, RA
}},
3800 {"evcntlsw", VX (4, 526), VX_MASK
, PPCSPE
, 0, {RS
, RA
}},
3801 {"vupkhsb", VX (4, 526), VXVA_MASK
, PPCVEC
, 0, {VD
, VB
}},
3802 {"brinc", VX (4, 527), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
3803 {"ps_abs", XRC(4, 264,0), XRA_MASK
, PPCPS
, 0, {FRT
, FRB
}},
3804 {"ps_abs.", XRC(4, 264,1), XRA_MASK
, PPCPS
, 0, {FRT
, FRB
}},
3805 {"evand", VX (4, 529), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
3806 {"evandc", VX (4, 530), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
3807 {"evxor", VX (4, 534), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
3808 {"evmr", VX (4, 535), VX_MASK
, PPCSPE
, 0, {RS
, RAB
}},
3809 {"evor", VX (4, 535), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
3810 {"evnot", VX (4, 536), VX_MASK
, PPCSPE
, 0, {RS
, RAB
}},
3811 {"evnor", VX (4, 536), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
3812 {"get", APU(4, 268,0), APU_RA_MASK
, PPC405
, 0, {RT
, FSL
}},
3813 {"eveqv", VX (4, 537), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
3814 {"evorc", VX (4, 539), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
3815 {"evnand", VX (4, 542), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
3816 {"evsrwu", VX (4, 544), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
3817 {"evsrws", VX (4, 545), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
3818 {"evsrwiu", VX (4, 546), VX_MASK
, PPCSPE
, 0, {RS
, RA
, EVUIMM
}},
3819 {"evsrwis", VX (4, 547), VX_MASK
, PPCSPE
, 0, {RS
, RA
, EVUIMM
}},
3820 {"evslw", VX (4, 548), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
3821 {"evslwi", VX (4, 550), VX_MASK
, PPCSPE
, 0, {RS
, RA
, EVUIMM
}},
3822 {"evrlw", VX (4, 552), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
3823 {"evsplati", VX (4, 553), VX_MASK
, PPCSPE
, 0, {RS
, SIMM
}},
3824 {"evrlwi", VX (4, 554), VX_MASK
, PPCSPE
, 0, {RS
, RA
, EVUIMM
}},
3825 {"evsplatfi", VX (4, 555), VX_MASK
, PPCSPE
, 0, {RS
, SIMM
}},
3826 {"evmergehi", VX (4, 556), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
3827 {"evmergelo", VX (4, 557), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
3828 {"evmergehilo", VX (4, 558), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
3829 {"evmergelohi", VX (4, 559), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
3830 {"evcmpgtu", VX (4, 560), VX_MASK
, PPCSPE
, 0, {CRFD
, RA
, RB
}},
3831 {"evcmpgts", VX (4, 561), VX_MASK
, PPCSPE
, 0, {CRFD
, RA
, RB
}},
3832 {"evcmpltu", VX (4, 562), VX_MASK
, PPCSPE
, 0, {CRFD
, RA
, RB
}},
3833 {"evcmplts", VX (4, 563), VX_MASK
, PPCSPE
, 0, {CRFD
, RA
, RB
}},
3834 {"evcmpeq", VX (4, 564), VX_MASK
, PPCSPE
, 0, {CRFD
, RA
, RB
}},
3835 {"cget", APU(4, 284,0), APU_RA_MASK
, PPC405
, 0, {RT
, FSL
}},
3836 {"vadduhs", VX (4, 576), VX_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
3837 {"vmul10euq", VX (4, 577), VX_MASK
, PPCVEC3
, 0, {VD
, VA
, VB
}},
3838 {"vminuh", VX (4, 578), VX_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
3839 {"vsrh", VX (4, 580), VX_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
3840 {"vcmpgtuh", VXR(4, 582,0), VXR_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
3841 {"vmuleuh", VX (4, 584), VX_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
3842 {"vrfiz", VX (4, 586), VXVA_MASK
, PPCVEC
, 0, {VD
, VB
}},
3843 {"vsplth", VX (4, 588), VXUIMM3_MASK
, PPCVEC
, 0, {VD
, VB
, UIMM3
}},
3844 {"vextractuh", VX (4, 589), VXUIMM4_MASK
, PPCVEC3
, 0, {VD
, VB
, UIMM4
}},
3845 {"vupkhsh", VX (4, 590), VXVA_MASK
, PPCVEC
, 0, {VD
, VB
}},
3846 {"nget", APU(4, 300,0), APU_RA_MASK
, PPC405
, 0, {RT
, FSL
}},
3847 {"evsel", EVSEL(4,79), EVSEL_MASK
, PPCSPE
, 0, {RS
, RA
, RB
, CRFS
}},
3848 {"ncget", APU(4, 316,0), APU_RA_MASK
, PPC405
, 0, {RT
, FSL
}},
3849 {"evfsadd", VX (4, 640), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
3850 {"vadduws", VX (4, 640), VX_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
3851 {"evfssub", VX (4, 641), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
3852 {"evfsmadd", VX (4, 642), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
3853 {"vminuw", VX (4, 642), VX_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
3854 {"evfsmsub", VX (4, 643), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
3855 {"evfsabs", VX (4, 644), VX_MASK
, PPCSPE
, 0, {RS
, RA
}},
3856 {"vsrw", VX (4, 644), VX_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
3857 {"evfsnabs", VX (4, 645), VX_MASK
, PPCSPE
, 0, {RS
, RA
}},
3858 {"evfsneg", VX (4, 646), VX_MASK
, PPCSPE
, 0, {RS
, RA
}},
3859 {"vcmpgtuw", VXR(4, 646,0), VXR_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
3860 {"evfssqrt", VX_RB_CONST(4, 647, 0), VX_RB_CONST_MASK
, PPCEFS2
, 0, {RD
, RA
}},
3861 {"vmuleuw", VX (4, 648), VX_MASK
, PPCVEC2
, 0, {VD
, VA
, VB
}},
3862 {"evfsmul", VX (4, 648), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
3863 {"evfsdiv", VX (4, 649), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
3864 {"evfsnmadd", VX (4, 650), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
3865 {"vrfip", VX (4, 650), VXVA_MASK
, PPCVEC
, 0, {VD
, VB
}},
3866 {"evfsnmsub", VX (4, 651), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
3867 {"evfscmpgt", VX (4, 652), VX_MASK
, PPCSPE
, 0, {CRFD
, RA
, RB
}},
3868 {"vspltw", VX (4, 652), VXUIMM2_MASK
, PPCVEC
, 0, {VD
, VB
, UIMM2
}},
3869 {"vextractuw", VX (4, 653), VXUIMM4_MASK
, PPCVEC3
, 0, {VD
, VB
, UIMM4
}},
3870 {"evfscmplt", VX (4, 653), VX_MASK
, PPCSPE
, 0, {CRFD
, RA
, RB
}},
3871 {"evfscmpeq", VX (4, 654), VX_MASK
, PPCSPE
, 0, {CRFD
, RA
, RB
}},
3872 {"vupklsb", VX (4, 654), VXVA_MASK
, PPCVEC
, 0, {VD
, VB
}},
3873 {"evfscfui", VX (4, 656), VX_MASK
, PPCSPE
, 0, {RS
, RB
}},
3874 {"evfscfh", VX_RA_CONST(4, 657, 4), VX_RA_CONST_MASK
, PPCEFS2
, 0, {RD
, RB
}},
3875 {"evfscfsi", VX (4, 657), VX_MASK
, PPCSPE
, 0, {RS
, RB
}},
3876 {"evfscfuf", VX (4, 658), VX_MASK
, PPCSPE
, 0, {RS
, RB
}},
3877 {"evfscfsf", VX (4, 659), VX_MASK
, PPCSPE
, 0, {RS
, RB
}},
3878 {"evfsctui", VX (4, 660), VX_MASK
, PPCSPE
, 0, {RS
, RB
}},
3879 {"evfscth", VX_RA_CONST(4, 661, 4), VX_RA_CONST_MASK
, PPCEFS2
, 0, {RD
, RB
}},
3880 {"evfsctsi", VX (4, 661), VX_MASK
, PPCSPE
, 0, {RS
, RB
}},
3881 {"evfsctuf", VX (4, 662), VX_MASK
, PPCSPE
, 0, {RS
, RB
}},
3882 {"evfsctsf", VX (4, 663), VX_MASK
, PPCSPE
, 0, {RS
, RB
}},
3883 {"evfsctuiz", VX (4, 664), VX_MASK
, PPCSPE
, 0, {RS
, RB
}},
3884 {"put", APU(4, 332,0), APU_RT_MASK
, PPC405
, 0, {RA
, FSL
}},
3885 {"evfsctsiz", VX (4, 666), VX_MASK
, PPCSPE
, 0, {RS
, RB
}},
3886 {"evfststgt", VX (4, 668), VX_MASK
, PPCSPE
, 0, {CRFD
, RA
, RB
}},
3887 {"evfststlt", VX (4, 669), VX_MASK
, PPCSPE
, 0, {CRFD
, RA
, RB
}},
3888 {"evfststeq", VX (4, 670), VX_MASK
, PPCSPE
, 0, {CRFD
, RA
, RB
}},
3889 {"evfsmax", VX (4, 672), VX_MASK
, PPCEFS2
, 0, {RD
, RA
, RB
}},
3890 {"evfsmin", VX (4, 673), VX_MASK
, PPCEFS2
, 0, {RD
, RA
, RB
}},
3891 {"evfsaddsub", VX (4, 674), VX_MASK
, PPCEFS2
, 0, {RD
, RA
, RB
}},
3892 {"evfssubadd", VX (4, 675), VX_MASK
, PPCEFS2
, 0, {RD
, RA
, RB
}},
3893 {"evfssum", VX (4, 676), VX_MASK
, PPCEFS2
, 0, {RD
, RA
, RB
}},
3894 {"evfsdiff", VX (4, 677), VX_MASK
, PPCEFS2
, 0, {RD
, RA
, RB
}},
3895 {"evfssumdiff", VX (4, 678), VX_MASK
, PPCEFS2
, 0, {RD
, RA
, RB
}},
3896 {"evfsdiffsum", VX (4, 679), VX_MASK
, PPCEFS2
, 0, {RD
, RA
, RB
}},
3897 {"evfsaddx", VX (4, 680), VX_MASK
, PPCEFS2
, 0, {RD
, RA
, RB
}},
3898 {"evfssubx", VX (4, 681), VX_MASK
, PPCEFS2
, 0, {RD
, RA
, RB
}},
3899 {"evfsaddsubx", VX (4, 682), VX_MASK
, PPCEFS2
, 0, {RD
, RA
, RB
}},
3900 {"evfssubaddx", VX (4, 683), VX_MASK
, PPCEFS2
, 0, {RD
, RA
, RB
}},
3901 {"evfsmulx", VX (4, 684), VX_MASK
, PPCEFS2
, 0, {RD
, RA
, RB
}},
3902 {"evfsmule", VX (4, 686), VX_MASK
, PPCEFS2
, 0, {RD
, RA
, RB
}},
3903 {"evfsmulo", VX (4, 687), VX_MASK
, PPCEFS2
, 0, {RD
, RA
, RB
}},
3904 {"efsmax", VX (4, 688), VX_MASK
, PPCEFS2
, 0, {RD
, RA
, RB
}},
3905 {"efsmin", VX (4, 689), VX_MASK
, PPCEFS2
, 0, {RD
, RA
, RB
}},
3906 {"efdmax", VX (4, 696), VX_MASK
, PPCEFS2
, 0, {RD
, RA
, RB
}},
3907 {"cput", APU(4, 348,0), APU_RT_MASK
, PPC405
, 0, {RA
, FSL
}},
3908 {"efdmin", VX (4, 697), VX_MASK
, PPCEFS2
, 0, {RD
, RA
, RB
}},
3909 {"efsadd", VX (4, 704), VX_MASK
, PPCEFS
, 0, {RS
, RA
, RB
}},
3910 {"efssub", VX (4, 705), VX_MASK
, PPCEFS
, 0, {RS
, RA
, RB
}},
3911 {"efsmadd", VX (4, 706), VX_MASK
, PPCEFS2
, 0, {RS
, RA
, RB
}},
3912 {"vminud", VX (4, 706), VX_MASK
, PPCVEC2
, 0, {VD
, VA
, VB
}},
3913 {"efsmsub", VX (4, 707), VX_MASK
, PPCEFS2
, 0, {RS
, RA
, RB
}},
3914 {"efsabs", VX (4, 708), VX_MASK
, PPCEFS
, 0, {RS
, RA
}},
3915 {"vsr", VX (4, 708), VX_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
3916 {"efsnabs", VX (4, 709), VX_MASK
, PPCEFS
, 0, {RS
, RA
}},
3917 {"efsneg", VX (4, 710), VX_MASK
, PPCEFS
, 0, {RS
, RA
}},
3918 {"vcmpgtfp", VXR(4, 710,0), VXR_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
3919 {"efssqrt", VX_RB_CONST(4, 711, 0), VX_RB_CONST_MASK
,PPCEFS2
, 0, {RD
, RA
}},
3920 {"vcmpgtud", VXR(4, 711,0), VXR_MASK
, PPCVEC2
, 0, {VD
, VA
, VB
}},
3921 {"efsmul", VX (4, 712), VX_MASK
, PPCEFS
, 0, {RS
, RA
, RB
}},
3922 {"efsdiv", VX (4, 713), VX_MASK
, PPCEFS
, 0, {RS
, RA
, RB
}},
3923 {"efsnmadd", VX (4, 714), VX_MASK
, PPCEFS2
, 0, {RS
, RA
, RB
}},
3924 {"vrfim", VX (4, 714), VXVA_MASK
, PPCVEC
, 0, {VD
, VB
}},
3925 {"efsnmsub", VX (4, 715), VX_MASK
, PPCEFS2
, 0, {RS
, RA
, RB
}},
3926 {"efscmpgt", VX (4, 716), VX_MASK
, PPCEFS
, 0, {CRFD
, RA
, RB
}},
3927 {"vextractd", VX (4, 717), VXUIMM4_MASK
, PPCVEC3
, 0, {VD
, VB
, UIMM4
}},
3928 {"efscmplt", VX (4, 717), VX_MASK
, PPCEFS
, 0, {CRFD
, RA
, RB
}},
3929 {"efscmpeq", VX (4, 718), VX_MASK
, PPCEFS
, 0, {CRFD
, RA
, RB
}},
3930 {"vupklsh", VX (4, 718), VXVA_MASK
, PPCVEC
, 0, {VD
, VB
}},
3931 {"efscfd", VX (4, 719), VX_MASK
, PPCEFS
, 0, {RS
, RB
}},
3932 {"efscfui", VX (4, 720), VX_MASK
, PPCEFS
, 0, {RS
, RB
}},
3933 {"efscfh", VX_RA_CONST(4, 721, 4), VX_RA_CONST_MASK
, PPCEFS2
, 0, {RD
, RB
}},
3934 {"efscfsi", VX (4, 721), VX_MASK
, PPCEFS
, 0, {RS
, RB
}},
3935 {"efscfuf", VX (4, 722), VX_MASK
, PPCEFS
, 0, {RS
, RB
}},
3936 {"efscfsf", VX (4, 723), VX_MASK
, PPCEFS
, 0, {RS
, RB
}},
3937 {"efsctui", VX (4, 724), VX_MASK
, PPCEFS
, 0, {RS
, RB
}},
3938 {"efscth", VX_RA_CONST(4, 725, 4), VX_RA_CONST_MASK
, PPCEFS2
, 0, {RD
, RB
}},
3939 {"efsctsi", VX (4, 725), VX_MASK
, PPCEFS
, 0, {RS
, RB
}},
3940 {"efsctuf", VX (4, 726), VX_MASK
, PPCEFS
, 0, {RS
, RB
}},
3941 {"efsctsf", VX (4, 727), VX_MASK
, PPCEFS
, 0, {RS
, RB
}},
3942 {"efsctuiz", VX (4, 728), VX_MASK
, PPCEFS
, 0, {RS
, RB
}},
3943 {"nput", APU(4, 364,0), APU_RT_MASK
, PPC405
, 0, {RA
, FSL
}},
3944 {"efsctsiz", VX (4, 730), VX_MASK
, PPCEFS
, 0, {RS
, RB
}},
3945 {"efststgt", VX (4, 732), VX_MASK
, PPCEFS
, 0, {CRFD
, RA
, RB
}},
3946 {"efststlt", VX (4, 733), VX_MASK
, PPCEFS
, 0, {CRFD
, RA
, RB
}},
3947 {"efststeq", VX (4, 734), VX_MASK
, PPCEFS
, 0, {CRFD
, RA
, RB
}},
3948 {"efdadd", VX (4, 736), VX_MASK
, PPCEFS
, 0, {RS
, RA
, RB
}},
3949 {"efdsub", VX (4, 737), VX_MASK
, PPCEFS
, 0, {RS
, RA
, RB
}},
3950 {"efdmadd", VX (4, 738), VX_MASK
, PPCEFS2
, E500
|E500MC
, {RD
, RA
, RB
}},
3951 {"efdcfuid", VX (4, 738), VX_MASK
, E500
|E500MC
,0, {RS
, RB
}},
3952 {"efdmsub", VX (4, 739), VX_MASK
, PPCEFS2
, E500
|E500MC
, {RD
, RA
, RB
}},
3953 {"efdcfsid", VX (4, 739), VX_MASK
, E500
|E500MC
,0, {RS
, RB
}},
3954 {"efdabs", VX (4, 740), VX_MASK
, PPCEFS
, 0, {RS
, RA
}},
3955 {"efdnabs", VX (4, 741), VX_MASK
, PPCEFS
, 0, {RS
, RA
}},
3956 {"efdneg", VX (4, 742), VX_MASK
, PPCEFS
, 0, {RS
, RA
}},
3957 {"efdsqrt", VX_RB_CONST(4, 743, 0), VX_RB_CONST_MASK
, PPCEFS2
, 0, {RD
, RA
}},
3958 {"efdmul", VX (4, 744), VX_MASK
, PPCEFS
, 0, {RS
, RA
, RB
}},
3959 {"efddiv", VX (4, 745), VX_MASK
, PPCEFS
, 0, {RS
, RA
, RB
}},
3960 {"efdnmadd", VX (4, 746), VX_MASK
, PPCEFS2
, E500
|E500MC
, {RD
, RA
, RB
}},
3961 {"efdctuidz", VX (4, 746), VX_MASK
, E500
|E500MC
,0, {RS
, RB
}},
3962 {"efdnmsub", VX (4, 747), VX_MASK
, PPCEFS2
, E500
|E500MC
, {RD
, RA
, RB
}},
3963 {"efdctsidz", VX (4, 747), VX_MASK
, E500
|E500MC
,0, {RS
, RB
}},
3964 {"efdcmpgt", VX (4, 748), VX_MASK
, PPCEFS
, 0, {CRFD
, RA
, RB
}},
3965 {"efdcmplt", VX (4, 749), VX_MASK
, PPCEFS
, 0, {CRFD
, RA
, RB
}},
3966 {"efdcmpeq", VX (4, 750), VX_MASK
, PPCEFS
, 0, {CRFD
, RA
, RB
}},
3967 {"efdcfs", VX (4, 751), VX_MASK
, PPCEFS
, 0, {RS
, RB
}},
3968 {"efdcfui", VX_RA_CONST(4, 752, 0), VX_RA_CONST_MASK
, PPCEFS
, 0, {RS
, RB
}},
3969 {"efdcfuid", VX_RA_CONST(4, 752, 1), VX_RA_CONST_MASK
, PPCEFS
, E500
|E500MC
, {RS
, RB
}},
3970 {"efdcfsi", VX_RA_CONST(4, 753, 0), VX_RA_CONST_MASK
, PPCEFS
, 0, {RS
, RB
}},
3971 {"efdcfsid", VX_RA_CONST(4, 753, 1), VX_RA_CONST_MASK
, PPCEFS
, E500
|E500MC
, {RS
, RB
}},
3972 {"efdcfh", VX_RA_CONST(4, 753, 4), VX_RA_CONST_MASK
, PPCEFS2
, 0, {RD
, RB
}},
3973 {"efdcfuf", VX (4, 754), VX_MASK
, PPCEFS
, 0, {RS
, RB
}},
3974 {"efdcfsf", VX (4, 755), VX_MASK
, PPCEFS
, 0, {RS
, RB
}},
3975 {"efdctui", VX (4, 756), VX_MASK
, PPCEFS
, 0, {RS
, RB
}},
3976 {"efdcth", VX_RA_CONST(4, 757, 4), VX_RA_CONST_MASK
, PPCEFS2
, 0, {RD
, RB
}},
3977 {"efdctsi", VX (4, 757), VX_MASK
, PPCEFS
, 0, {RS
, RB
}},
3978 {"efdctuf", VX (4, 758), VX_MASK
, PPCEFS
, 0, {RS
, RB
}},
3979 {"efdctsf", VX (4, 759), VX_MASK
, PPCEFS
, 0, {RS
, RB
}},
3980 {"efdctuiz", VX_RA_CONST(4, 760, 0), VX_RA_CONST_MASK
, PPCEFS
, 0, {RS
, RB
}},
3981 {"efdctuidz", VX_RA_CONST(4, 760, 1), VX_RA_CONST_MASK
, PPCEFS
, E500
|E500MC
, {RS
, RB
}},
3982 {"ncput", APU(4, 380,0), APU_RT_MASK
, PPC405
, 0, {RA
, FSL
}},
3983 {"efdctsiz", VX_RA_CONST(4, 762, 0), VX_RA_CONST_MASK
, PPCEFS
, 0, {RS
, RB
}},
3984 {"efdctsidz", VX_RA_CONST(4, 762, 1), VX_RA_CONST_MASK
, PPCEFS
, E500
|E500MC
, {RS
, RB
}},
3985 {"efdtstgt", VX (4, 764), VX_MASK
, PPCEFS
, 0, {CRFD
, RA
, RB
}},
3986 {"efdtstlt", VX (4, 765), VX_MASK
, PPCEFS
, 0, {CRFD
, RA
, RB
}},
3987 {"efdtsteq", VX (4, 766), VX_MASK
, PPCEFS
, 0, {CRFD
, RA
, RB
}},
3988 {"evlddx", VX (4, 768), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
3989 {"vaddsbs", VX (4, 768), VX_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
3990 {"evldd", VX (4, 769), VX_MASK
, PPCSPE
, 0, {RS
, EVUIMM_8
, RA
}},
3991 {"evldwx", VX (4, 770), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
3992 {"vminsb", VX (4, 770), VX_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
3993 {"evldw", VX (4, 771), VX_MASK
, PPCSPE
, 0, {RS
, EVUIMM_8
, RA
}},
3994 {"evldhx", VX (4, 772), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
3995 {"vsrab", VX (4, 772), VX_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
3996 {"evldh", VX (4, 773), VX_MASK
, PPCSPE
, 0, {RS
, EVUIMM_8
, RA
}},
3997 {"vcmpgtsb", VXR(4, 774,0), VXR_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
3998 {"evlhhesplatx",VX (4, 776), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
3999 {"vmulesb", VX (4, 776), VX_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
4000 {"evlhhesplat", VX (4, 777), VX_MASK
, PPCSPE
, 0, {RS
, EVUIMM_2
, RA
}},
4001 {"vcfux", VX (4, 778), VX_MASK
, PPCVEC
, 0, {VD
, VB
, UIMM
}},
4002 {"vcuxwfp", VX (4, 778), VX_MASK
, PPCVEC
, 0, {VD
, VB
, UIMM
}},
4003 {"evlhhousplatx",VX(4, 780), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
4004 {"vspltisb", VX (4, 780), VXVB_MASK
, PPCVEC
, 0, {VD
, SIMM
}},
4005 {"vinsertb", VX (4, 781), VXUIMM4_MASK
, PPCVEC3
, 0, {VD
, VB
, UIMM4
}},
4006 {"evlhhousplat",VX (4, 781), VX_MASK
, PPCSPE
, 0, {RS
, EVUIMM_2
, RA
}},
4007 {"evlhhossplatx",VX(4, 782), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
4008 {"vpkpx", VX (4, 782), VX_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
4009 {"evlhhossplat",VX (4, 783), VX_MASK
, PPCSPE
, 0, {RS
, EVUIMM_2
, RA
}},
4010 {"mullhwu", XRC(4, 392,0), X_MASK
, MULHW
, 0, {RT
, RA
, RB
}},
4011 {"evlwhex", VX (4, 784), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
4012 {"mullhwu.", XRC(4, 392,1), X_MASK
, MULHW
, 0, {RT
, RA
, RB
}},
4013 {"evlwhe", VX (4, 785), VX_MASK
, PPCSPE
, 0, {RS
, EVUIMM_4
, RA
}},
4014 {"evlwhoux", VX (4, 788), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
4015 {"evlwhou", VX (4, 789), VX_MASK
, PPCSPE
, 0, {RS
, EVUIMM_4
, RA
}},
4016 {"evlwhosx", VX (4, 790), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
4017 {"evlwhos", VX (4, 791), VX_MASK
, PPCSPE
, 0, {RS
, EVUIMM_4
, RA
}},
4018 {"maclhwu", XO (4, 396,0,0),XO_MASK
, MULHW
, 0, {RT
, RA
, RB
}},
4019 {"evlwwsplatx", VX (4, 792), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
4020 {"maclhwu.", XO (4, 396,0,1),XO_MASK
, MULHW
, 0, {RT
, RA
, RB
}},
4021 {"evlwwsplat", VX (4, 793), VX_MASK
, PPCSPE
, 0, {RS
, EVUIMM_4
, RA
}},
4022 {"evlwhsplatx", VX (4, 796), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
4023 {"evlwhsplat", VX (4, 797), VX_MASK
, PPCSPE
, 0, {RS
, EVUIMM_4
, RA
}},
4024 {"evstddx", VX (4, 800), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
4025 {"evstdd", VX (4, 801), VX_MASK
, PPCSPE
, 0, {RS
, EVUIMM_8
, RA
}},
4026 {"evstdwx", VX (4, 802), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
4027 {"evstdw", VX (4, 803), VX_MASK
, PPCSPE
, 0, {RS
, EVUIMM_8
, RA
}},
4028 {"evstdhx", VX (4, 804), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
4029 {"evstdh", VX (4, 805), VX_MASK
, PPCSPE
, 0, {RS
, EVUIMM_8
, RA
}},
4030 {"evstwhex", VX (4, 816), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
4031 {"evstwhe", VX (4, 817), VX_MASK
, PPCSPE
, 0, {RS
, EVUIMM_4
, RA
}},
4032 {"evstwhox", VX (4, 820), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
4033 {"evstwho", VX (4, 821), VX_MASK
, PPCSPE
, 0, {RS
, EVUIMM_4
, RA
}},
4034 {"evstwwex", VX (4, 824), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
4035 {"evstwwe", VX (4, 825), VX_MASK
, PPCSPE
, 0, {RS
, EVUIMM_4
, RA
}},
4036 {"evstwwox", VX (4, 828), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
4037 {"evstwwo", VX (4, 829), VX_MASK
, PPCSPE
, 0, {RS
, EVUIMM_4
, RA
}},
4038 {"vaddshs", VX (4, 832), VX_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
4039 {"bcdcpsgn.", VX (4, 833), VX_MASK
, PPCVEC3
, 0, {VD
, VA
, VB
}},
4040 {"vminsh", VX (4, 834), VX_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
4041 {"vsrah", VX (4, 836), VX_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
4042 {"vcmpgtsh", VXR(4, 838,0), VXR_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
4043 {"vmulesh", VX (4, 840), VX_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
4044 {"vcfsx", VX (4, 842), VX_MASK
, PPCVEC
, 0, {VD
, VB
, UIMM
}},
4045 {"vcsxwfp", VX (4, 842), VX_MASK
, PPCVEC
, 0, {VD
, VB
, UIMM
}},
4046 {"vspltish", VX (4, 844), VXVB_MASK
, PPCVEC
, 0, {VD
, SIMM
}},
4047 {"vinserth", VX (4, 845), VXUIMM4_MASK
, PPCVEC3
, 0, {VD
, VB
, UIMM4
}},
4048 {"vupkhpx", VX (4, 846), VXVA_MASK
, PPCVEC
, 0, {VD
, VB
}},
4049 {"mullhw", XRC(4, 424,0), X_MASK
, MULHW
, 0, {RT
, RA
, RB
}},
4050 {"mullhw.", XRC(4, 424,1), X_MASK
, MULHW
, 0, {RT
, RA
, RB
}},
4051 {"maclhw", XO (4, 428,0,0),XO_MASK
, MULHW
, 0, {RT
, RA
, RB
}},
4052 {"maclhw.", XO (4, 428,0,1),XO_MASK
, MULHW
, 0, {RT
, RA
, RB
}},
4053 {"nmaclhw", XO (4, 430,0,0),XO_MASK
, MULHW
, 0, {RT
, RA
, RB
}},
4054 {"nmaclhw.", XO (4, 430,0,1),XO_MASK
, MULHW
, 0, {RT
, RA
, RB
}},
4055 {"vaddsws", VX (4, 896), VX_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
4056 {"vminsw", VX (4, 898), VX_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
4057 {"vsraw", VX (4, 900), VX_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
4058 {"vcmpgtsw", VXR(4, 902,0), VXR_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
4059 {"vmulesw", VX (4, 904), VX_MASK
, PPCVEC2
, 0, {VD
, VA
, VB
}},
4060 {"vctuxs", VX (4, 906), VX_MASK
, PPCVEC
, 0, {VD
, VB
, UIMM
}},
4061 {"vcfpuxws", VX (4, 906), VX_MASK
, PPCVEC
, 0, {VD
, VB
, UIMM
}},
4062 {"vspltisw", VX (4, 908), VXVB_MASK
, PPCVEC
, 0, {VD
, SIMM
}},
4063 {"vinsertw", VX (4, 909), VXUIMM4_MASK
, PPCVEC3
, 0, {VD
, VB
, UIMM4
}},
4064 {"maclhwsu", XO (4, 460,0,0), XO_MASK
, MULHW
, 0, {RT
, RA
, RB
}},
4065 {"maclhwsu.", XO (4, 460,0,1), XO_MASK
, MULHW
, 0, {RT
, RA
, RB
}},
4066 {"vminsd", VX (4, 962), VX_MASK
, PPCVEC2
, 0, {VD
, VA
, VB
}},
4067 {"vsrad", VX (4, 964), VX_MASK
, PPCVEC2
, 0, {VD
, VA
, VB
}},
4068 {"vcmpbfp", VXR(4, 966,0), VXR_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
4069 {"vcmpgtsd", VXR(4, 967,0), VXR_MASK
, PPCVEC2
, 0, {VD
, VA
, VB
}},
4070 {"vctsxs", VX (4, 970), VX_MASK
, PPCVEC
, 0, {VD
, VB
, UIMM
}},
4071 {"vcfpsxws", VX (4, 970), VX_MASK
, PPCVEC
, 0, {VD
, VB
, UIMM
}},
4072 {"vinsertd", VX (4, 973), VXUIMM4_MASK
, PPCVEC3
, 0, {VD
, VB
, UIMM4
}},
4073 {"vupklpx", VX (4, 974), VXVA_MASK
, PPCVEC
, 0, {VD
, VB
}},
4074 {"maclhws", XO (4, 492,0,0), XO_MASK
, MULHW
, 0, {RT
, RA
, RB
}},
4075 {"maclhws.", XO (4, 492,0,1), XO_MASK
, MULHW
, 0, {RT
, RA
, RB
}},
4076 {"nmaclhws", XO (4, 494,0,0), XO_MASK
, MULHW
, 0, {RT
, RA
, RB
}},
4077 {"nmaclhws.", XO (4, 494,0,1), XO_MASK
, MULHW
, 0, {RT
, RA
, RB
}},
4078 {"vsububm", VX (4,1024), VX_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
4079 {"bcdadd.", VX (4,1025), VXPS_MASK
, PPCVEC2
, 0, {VD
, VA
, VB
, PS
}},
4080 {"vavgub", VX (4,1026), VX_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
4081 {"vabsdub", VX (4,1027), VX_MASK
, PPCVEC2
, 0, {VD
, VA
, VB
}},
4082 {"evmhessf", VX (4,1027), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
4083 {"vand", VX (4,1028), VX_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
4084 {"vcmpequb.", VXR(4, 6,1), VXR_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
4085 {"vcmpneb.", VXR(4, 7,1), VXR_MASK
, PPCVEC3
, 0, {VD
, VA
, VB
}},
4086 {"udi0fcm.", APU(4, 515,0), APU_MASK
, PPC405
|PPC440
, 0, {URT
, URA
, URB
}},
4087 {"udi0fcm", APU(4, 515,1), APU_MASK
, PPC405
|PPC440
, 0, {URT
, URA
, URB
}},
4088 {"evmhossf", VX (4,1031), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
4089 {"vpmsumb", VX (4,1032), VX_MASK
, PPCVEC2
, 0, {VD
, VA
, VB
}},
4090 {"evmheumi", VX (4,1032), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
4091 {"evmhesmi", VX (4,1033), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
4092 {"vmaxfp", VX (4,1034), VX_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
4093 {"evmhesmf", VX (4,1035), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
4094 {"evmhoumi", VX (4,1036), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
4095 {"vslo", VX (4,1036), VX_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
4096 {"evmhosmi", VX (4,1037), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
4097 {"evmhosmf", VX (4,1039), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
4098 {"machhwuo", XO (4, 12,1,0), XO_MASK
, MULHW
, 0, {RT
, RA
, RB
}},
4099 {"machhwuo.", XO (4, 12,1,1), XO_MASK
, MULHW
, 0, {RT
, RA
, RB
}},
4100 {"ps_merge00", XOPS(4,528,0), XOPS_MASK
, PPCPS
, 0, {FRT
, FRA
, FRB
}},
4101 {"ps_merge00.", XOPS(4,528,1), XOPS_MASK
, PPCPS
, 0, {FRT
, FRA
, FRB
}},
4102 {"evmhessfa", VX (4,1059), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
4103 {"evmhossfa", VX (4,1063), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
4104 {"evmheumia", VX (4,1064), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
4105 {"evmhesmia", VX (4,1065), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
4106 {"evmhesmfa", VX (4,1067), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
4107 {"evmhoumia", VX (4,1068), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
4108 {"evmhosmia", VX (4,1069), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
4109 {"evmhosmfa", VX (4,1071), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
4110 {"vsubuhm", VX (4,1088), VX_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
4111 {"bcdsub.", VX (4,1089), VXPS_MASK
, PPCVEC2
, 0, {VD
, VA
, VB
, PS
}},
4112 {"vavguh", VX (4,1090), VX_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
4113 {"evmwlssf", VX (4,1091), VX_MASK
, PPCSPE
, 0, {RD
, RA
, RB
}},
4114 {"vabsduh", VX (4,1091), VX_MASK
, PPCVEC2
, 0, {VD
, VA
, VB
}},
4115 {"vandc", VX (4,1092), VX_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
4116 {"vcmpequh.", VXR(4, 70,1), VXR_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
4117 {"udi1fcm.", APU(4, 547,0), APU_MASK
, PPC405
|PPC440
, 0, {URT
, URA
, URB
}},
4118 {"udi1fcm", APU(4, 547,1), APU_MASK
, PPC405
|PPC440
, 0, {URT
, URA
, URB
}},
4119 {"vcmpneh.", VXR(4, 71,1), VXR_MASK
, PPCVEC3
, 0, {VD
, VA
, VB
}},
4120 {"evmwhssf", VX (4,1095), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
4121 {"vpmsumh", VX (4,1096), VX_MASK
, PPCVEC2
, 0, {VD
, VA
, VB
}},
4122 {"evmwlumi", VX (4,1096), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
4123 {"vminfp", VX (4,1098), VX_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
4124 {"evmwlsmf", VX (4,1099), VX_MASK
, PPCSPE
, 0, {RD
, RA
, RB
}},
4125 {"evmwhumi", VX (4,1100), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
4126 {"vsro", VX (4,1100), VX_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
4127 {"evmwhsmi", VX (4,1101), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
4128 {"vpkudum", VX (4,1102), VX_MASK
, PPCVEC2
, 0, {VD
, VA
, VB
}},
4129 {"evmwhsmf", VX (4,1103), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
4130 {"evmwssf", VX (4,1107), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
4131 {"machhwo", XO (4, 44,1,0), XO_MASK
, MULHW
, 0, {RT
, RA
, RB
}},
4132 {"evmwumi", VX (4,1112), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
4133 {"machhwo.", XO (4, 44,1,1), XO_MASK
, MULHW
, 0, {RT
, RA
, RB
}},
4134 {"evmwsmi", VX (4,1113), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
4135 {"evmwsmf", VX (4,1115), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
4136 {"nmachhwo", XO (4, 46,1,0), XO_MASK
, MULHW
, 0, {RT
, RA
, RB
}},
4137 {"nmachhwo.", XO (4, 46,1,1), XO_MASK
, MULHW
, 0, {RT
, RA
, RB
}},
4138 {"ps_merge01", XOPS(4,560,0), XOPS_MASK
, PPCPS
, 0, {FRT
, FRA
, FRB
}},
4139 {"ps_merge01.", XOPS(4,560,1), XOPS_MASK
, PPCPS
, 0, {FRT
, FRA
, FRB
}},
4140 {"evmwlssfa", VX (4,1123), VX_MASK
, PPCSPE
, 0, {RD
, RA
, RB
}},
4141 {"evmwhssfa", VX (4,1127), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
4142 {"evmwlumia", VX (4,1128), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
4143 {"evmwlsmfa", VX (4,1131), VX_MASK
, PPCSPE
, 0, {RD
, RA
, RB
}},
4144 {"evmwhumia", VX (4,1132), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
4145 {"evmwhsmia", VX (4,1133), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
4146 {"evmwhsmfa", VX (4,1135), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
4147 {"evmwssfa", VX (4,1139), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
4148 {"evmwumia", VX (4,1144), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
4149 {"evmwsmia", VX (4,1145), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
4150 {"evmwsmfa", VX (4,1147), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
4151 {"vsubuwm", VX (4,1152), VX_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
4152 {"bcdus.", VX (4,1153), VX_MASK
, PPCVEC3
, 0, {VD
, VA
, VB
}},
4153 {"vavguw", VX (4,1154), VX_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
4154 {"vabsduw", VX (4,1155), VX_MASK
, PPCVEC2
, 0, {VD
, VA
, VB
}},
4155 {"vmr", VX (4,1156), VX_MASK
, PPCVEC
, 0, {VD
, VAB
}},
4156 {"vor", VX (4,1156), VX_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
4157 {"vcmpnew.", VXR(4, 135,1), VXR_MASK
, PPCVEC3
, 0, {VD
, VA
, VB
}},
4158 {"vpmsumw", VX (4,1160), VX_MASK
, PPCVEC2
, 0, {VD
, VA
, VB
}},
4159 {"vcmpequw.", VXR(4, 134,1), VXR_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
4160 {"udi2fcm.", APU(4, 579,0), APU_MASK
, PPC405
|PPC440
, 0, {URT
, URA
, URB
}},
4161 {"udi2fcm", APU(4, 579,1), APU_MASK
, PPC405
|PPC440
, 0, {URT
, URA
, URB
}},
4162 {"machhwsuo", XO (4, 76,1,0), XO_MASK
, MULHW
, 0, {RT
, RA
, RB
}},
4163 {"machhwsuo.", XO (4, 76,1,1), XO_MASK
, MULHW
, 0, {RT
, RA
, RB
}},
4164 {"ps_merge10", XOPS(4,592,0), XOPS_MASK
, PPCPS
, 0, {FRT
, FRA
, FRB
}},
4165 {"ps_merge10.", XOPS(4,592,1), XOPS_MASK
, PPCPS
, 0, {FRT
, FRA
, FRB
}},
4166 {"vsubudm", VX (4,1216), VX_MASK
, PPCVEC2
, 0, {VD
, VA
, VB
}},
4167 {"evaddusiaaw", VX (4,1216), VX_MASK
, PPCSPE
, 0, {RS
, RA
}},
4168 {"bcds.", VX (4,1217), VXPS_MASK
, PPCVEC3
, 0, {VD
, VA
, VB
, PS
}},
4169 {"evaddssiaaw", VX (4,1217), VX_MASK
, PPCSPE
, 0, {RS
, RA
}},
4170 {"evsubfusiaaw",VX (4,1218), VX_MASK
, PPCSPE
, 0, {RS
, RA
}},
4171 {"evsubfssiaaw",VX (4,1219), VX_MASK
, PPCSPE
, 0, {RS
, RA
}},
4172 {"evmra", VX (4,1220), VX_MASK
, PPCSPE
, 0, {RS
, RA
}},
4173 {"vxor", VX (4,1220), VX_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
4174 {"evdivws", VX (4,1222), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
4175 {"vcmpeqfp.", VXR(4, 198,1), VXR_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
4176 {"udi3fcm.", APU(4, 611,0), APU_MASK
, PPC405
|PPC440
, 0, {URT
, URA
, URB
}},
4177 {"vcmpequd.", VXR(4, 199,1), VXR_MASK
, PPCVEC2
, 0, {VD
, VA
, VB
}},
4178 {"udi3fcm", APU(4, 611,1), APU_MASK
, PPC405
|PPC440
, 0, {URT
, URA
, URB
}},
4179 {"evdivwu", VX (4,1223), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
4180 {"vpmsumd", VX (4,1224), VX_MASK
, PPCVEC2
, 0, {VD
, VA
, VB
}},
4181 {"evaddumiaaw", VX (4,1224), VX_MASK
, PPCSPE
, 0, {RS
, RA
}},
4182 {"evaddsmiaaw", VX (4,1225), VX_MASK
, PPCSPE
, 0, {RS
, RA
}},
4183 {"evsubfumiaaw",VX (4,1226), VX_MASK
, PPCSPE
, 0, {RS
, RA
}},
4184 {"evsubfsmiaaw",VX (4,1227), VX_MASK
, PPCSPE
, 0, {RS
, RA
}},
4185 {"vpkudus", VX (4,1230), VX_MASK
, PPCVEC2
, 0, {VD
, VA
, VB
}},
4186 {"machhwso", XO (4, 108,1,0), XO_MASK
, MULHW
, 0, {RT
, RA
, RB
}},
4187 {"machhwso.", XO (4, 108,1,1), XO_MASK
, MULHW
, 0, {RT
, RA
, RB
}},
4188 {"nmachhwso", XO (4, 110,1,0), XO_MASK
, MULHW
, 0, {RT
, RA
, RB
}},
4189 {"nmachhwso.", XO (4, 110,1,1), XO_MASK
, MULHW
, 0, {RT
, RA
, RB
}},
4190 {"ps_merge11", XOPS(4,624,0), XOPS_MASK
, PPCPS
, 0, {FRT
, FRA
, FRB
}},
4191 {"ps_merge11.", XOPS(4,624,1), XOPS_MASK
, PPCPS
, 0, {FRT
, FRA
, FRB
}},
4192 {"vsubuqm", VX (4,1280), VX_MASK
, PPCVEC2
, 0, {VD
, VA
, VB
}},
4193 {"evmheusiaaw", VX (4,1280), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
4194 {"bcdtrunc.", VX (4,1281), VXPS_MASK
, PPCVEC3
, 0, {VD
, VA
, VB
, PS
}},
4195 {"evmhessiaaw", VX (4,1281), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
4196 {"vavgsb", VX (4,1282), VX_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
4197 {"evmhessfaaw", VX (4,1283), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
4198 {"evmhousiaaw", VX (4,1284), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
4199 {"vnot", VX (4,1284), VX_MASK
, PPCVEC
, 0, {VD
, VAB
}},
4200 {"vnor", VX (4,1284), VX_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
4201 {"evmhossiaaw", VX (4,1285), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
4202 {"udi4fcm.", APU(4, 643,0), APU_MASK
, PPC405
|PPC440
, 0, {URT
, URA
, URB
}},
4203 {"udi4fcm", APU(4, 643,1), APU_MASK
, PPC405
|PPC440
, 0, {URT
, URA
, URB
}},
4204 {"vcmpnezb.", VXR(4, 263,1), VXR_MASK
, PPCVEC3
, 0, {VD
, VA
, VB
}},
4205 {"evmhossfaaw", VX (4,1287), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
4206 {"evmheumiaaw", VX (4,1288), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
4207 {"vcipher", VX (4,1288), VX_MASK
, PPCVEC2
, 0, {VD
, VA
, VB
}},
4208 {"vcipherlast", VX (4,1289), VX_MASK
, PPCVEC2
, 0, {VD
, VA
, VB
}},
4209 {"evmhesmiaaw", VX (4,1289), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
4210 {"evmhesmfaaw", VX (4,1291), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
4211 {"vgbbd", VX (4,1292), VXVA_MASK
, PPCVEC2
, 0, {VD
, VB
}},
4212 {"evmhoumiaaw", VX (4,1292), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
4213 {"evmhosmiaaw", VX (4,1293), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
4214 {"evmhosmfaaw", VX (4,1295), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
4215 {"macchwuo", XO (4, 140,1,0), XO_MASK
, MULHW
, 0, {RT
, RA
, RB
}},
4216 {"macchwuo.", XO (4, 140,1,1), XO_MASK
, MULHW
, 0, {RT
, RA
, RB
}},
4217 {"evmhegumiaa", VX (4,1320), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
4218 {"evmhegsmiaa", VX (4,1321), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
4219 {"evmhegsmfaa", VX (4,1323), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
4220 {"evmhogumiaa", VX (4,1324), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
4221 {"evmhogsmiaa", VX (4,1325), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
4222 {"evmhogsmfaa", VX (4,1327), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
4223 {"vsubcuq", VX (4,1344), VX_MASK
, PPCVEC2
, 0, {VD
, VA
, VB
}},
4224 {"evmwlusiaaw", VX (4,1344), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
4225 {"bcdutrunc.", VX (4,1345), VX_MASK
, PPCVEC3
, 0, {VD
, VA
, VB
}},
4226 {"evmwlssiaaw", VX (4,1345), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
4227 {"vavgsh", VX (4,1346), VX_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
4228 {"evmwlssfaaw", VX (4,1347), VX_MASK
, PPCSPE
, 0, {RD
, RA
, RB
}},
4229 {"evmwhusiaa", VX (4,1348), VX_MASK
, PPCSPE
, 0, {RD
, RA
, RB
}},
4230 {"vorc", VX (4,1348), VX_MASK
, PPCVEC2
, 0, {VD
, VA
, VB
}},
4231 {"evmwhssmaa", VX (4,1349), VX_MASK
, PPCSPE
, 0, {RD
, RA
, RB
}},
4232 {"udi5fcm.", APU(4, 675,0), APU_MASK
, PPC405
|PPC440
, 0, {URT
, URA
, URB
}},
4233 {"udi5fcm", APU(4, 675,1), APU_MASK
, PPC405
|PPC440
, 0, {URT
, URA
, URB
}},
4234 {"vcmpnezh.", VXR(4, 327,1), VXR_MASK
, PPCVEC3
, 0, {VD
, VA
, VB
}},
4235 {"evmwhssfaa", VX (4,1351), VX_MASK
, PPCSPE
, 0, {RD
, RA
, RB
}},
4236 {"vncipher", VX (4,1352), VX_MASK
, PPCVEC2
, 0, {VD
, VA
, VB
}},
4237 {"evmwlumiaaw", VX (4,1352), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
4238 {"vncipherlast",VX (4,1353), VX_MASK
, PPCVEC2
, 0, {VD
, VA
, VB
}},
4239 {"evmwlsmiaaw", VX (4,1353), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
4240 {"evmwlsmfaaw", VX (4,1355), VX_MASK
, PPCSPE
, 0, {RD
, RA
, RB
}},
4241 {"evmwhumiaa", VX (4,1356), VX_MASK
, PPCSPE
, 0, {RD
, RA
, RB
}},
4242 {"vbpermq", VX (4,1356), VX_MASK
, PPCVEC2
, 0, {VD
, VA
, VB
}},
4243 {"evmwhsmiaa", VX (4,1357), VX_MASK
, PPCSPE
, 0, {RD
, RA
, RB
}},
4244 {"vpksdus", VX (4,1358), VX_MASK
, PPCVEC2
, 0, {VD
, VA
, VB
}},
4245 {"evmwhsmfaa", VX (4,1359), VX_MASK
, PPCSPE
, 0, {RD
, RA
, RB
}},
4246 {"evmwssfaa", VX (4,1363), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
4247 {"macchwo", XO (4, 172,1,0), XO_MASK
, MULHW
, 0, {RT
, RA
, RB
}},
4248 {"evmwumiaa", VX (4,1368), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
4249 {"macchwo.", XO (4, 172,1,1), XO_MASK
, MULHW
, 0, {RT
, RA
, RB
}},
4250 {"evmwsmiaa", VX (4,1369), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
4251 {"evmwsmfaa", VX (4,1371), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
4252 {"nmacchwo", XO (4, 174,1,0), XO_MASK
, MULHW
, 0, {RT
, RA
, RB
}},
4253 {"nmacchwo.", XO (4, 174,1,1), XO_MASK
, MULHW
, 0, {RT
, RA
, RB
}},
4254 {"evmwhgumiaa", VX (4,1380), VX_MASK
, PPCSPE
, 0, {RD
, RA
, RB
}},
4255 {"evmwhgsmiaa", VX (4,1381), VX_MASK
, PPCSPE
, 0, {RD
, RA
, RB
}},
4256 {"evmwhgssfaa", VX (4,1383), VX_MASK
, PPCSPE
, 0, {RD
, RA
, RB
}},
4257 {"evmwhgsmfaa", VX (4,1391), VX_MASK
, PPCSPE
, 0, {RD
, RA
, RB
}},
4258 {"evmheusianw", VX (4,1408), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
4259 {"vsubcuw", VX (4,1408), VX_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
4260 {"evmhessianw", VX (4,1409), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
4261 {"bcdctsq.", VXVA(4,1409,0), VXVA_MASK
, PPCVEC3
, 0, {VD
, VB
}},
4262 {"bcdcfsq.", VXVA(4,1409,2), VXVAPS_MASK
, PPCVEC3
, 0, {VD
, VB
, PS
}},
4263 {"bcdctz.", VXVA(4,1409,4), VXVAPS_MASK
, PPCVEC3
, 0, {VD
, VB
, PS
}},
4264 {"bcdctn.", VXVA(4,1409,5), VXVA_MASK
, PPCVEC3
, 0, {VD
, VB
}},
4265 {"bcdcfz.", VXVA(4,1409,6), VXVAPS_MASK
, PPCVEC3
, 0, {VD
, VB
, PS
}},
4266 {"bcdcfn.", VXVA(4,1409,7), VXVAPS_MASK
, PPCVEC3
, 0, {VD
, VB
, PS
}},
4267 {"bcdsetsgn.", VXVA(4,1409,31), VXVAPS_MASK
, PPCVEC3
, 0, {VD
, VB
, PS
}},
4268 {"vavgsw", VX (4,1410), VX_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
4269 {"evmhessfanw", VX (4,1411), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
4270 {"vnand", VX (4,1412), VX_MASK
, PPCVEC2
, 0, {VD
, VA
, VB
}},
4271 {"evmhousianw", VX (4,1412), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
4272 {"evmhossianw", VX (4,1413), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
4273 {"udi6fcm.", APU(4, 707,0), APU_MASK
, PPC405
|PPC440
, 0, {URT
, URA
, URB
}},
4274 {"udi6fcm", APU(4, 707,1), APU_MASK
, PPC405
|PPC440
, 0, {URT
, URA
, URB
}},
4275 {"vcmpnezw.", VXR(4, 391,1), VXR_MASK
, PPCVEC3
, 0, {VD
, VA
, VB
}},
4276 {"evmhossfanw", VX (4,1415), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
4277 {"evmheumianw", VX (4,1416), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
4278 {"evmhesmianw", VX (4,1417), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
4279 {"evmhesmfanw", VX (4,1419), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
4280 {"evmhoumianw", VX (4,1420), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
4281 {"evmhosmianw", VX (4,1421), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
4282 {"evmhosmfanw", VX (4,1423), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
4283 {"macchwsuo", XO (4, 204,1,0), XO_MASK
, MULHW
, 0, {RT
, RA
, RB
}},
4284 {"macchwsuo.", XO (4, 204,1,1), XO_MASK
, MULHW
, 0, {RT
, RA
, RB
}},
4285 {"evmhegumian", VX (4,1448), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
4286 {"evmhegsmian", VX (4,1449), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
4287 {"evmhegsmfan", VX (4,1451), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
4288 {"evmhogumian", VX (4,1452), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
4289 {"evmhogsmian", VX (4,1453), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
4290 {"evmhogsmfan", VX (4,1455), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
4291 {"evmwlusianw", VX (4,1472), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
4292 {"bcdsr.", VX (4,1473), VXPS_MASK
, PPCVEC3
, 0, {VD
, VA
, VB
, PS
}},
4293 {"evmwlssianw", VX (4,1473), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
4294 {"evmwlssfanw", VX (4,1475), VX_MASK
, PPCSPE
, 0, {RD
, RA
, RB
}},
4295 {"evmwhusian", VX (4,1476), VX_MASK
, PPCSPE
, 0, {RD
, RA
, RB
}},
4296 {"vsld", VX (4,1476), VX_MASK
, PPCVEC2
, 0, {VD
, VA
, VB
}},
4297 {"evmwhssian", VX (4,1477), VX_MASK
, PPCSPE
, 0, {RD
, RA
, RB
}},
4298 {"vcmpgefp.", VXR(4, 454,1), VXR_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
4299 {"udi7fcm.", APU(4, 739,0), APU_MASK
, PPC405
|PPC440
, 0, {URT
, URA
, URB
}},
4300 {"udi7fcm", APU(4, 739,1), APU_MASK
, PPC405
|PPC440
, 0, {URT
, URA
, URB
}},
4301 {"evmwhssfan", VX (4,1479), VX_MASK
, PPCSPE
, 0, {RD
, RA
, RB
}},
4302 {"vsbox", VX (4,1480), VXVB_MASK
, PPCVEC2
, 0, {VD
, VA
}},
4303 {"evmwlumianw", VX (4,1480), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
4304 {"evmwlsmianw", VX (4,1481), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
4305 {"evmwlsmfanw", VX (4,1483), VX_MASK
, PPCSPE
, 0, {RD
, RA
, RB
}},
4306 {"evmwhumian", VX (4,1484), VX_MASK
, PPCSPE
, 0, {RD
, RA
, RB
}},
4307 {"vbpermd", VX (4,1484), VX_MASK
, PPCVEC3
, 0, {VD
, VA
, VB
}},
4308 {"evmwhsmian", VX (4,1485), VX_MASK
, PPCSPE
, 0, {RD
, RA
, RB
}},
4309 {"vpksdss", VX (4,1486), VX_MASK
, PPCVEC2
, 0, {VD
, VA
, VB
}},
4310 {"evmwhsmfan", VX (4,1487), VX_MASK
, PPCSPE
, 0, {RD
, RA
, RB
}},
4311 {"evmwssfan", VX (4,1491), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
4312 {"macchwso", XO (4, 236,1,0), XO_MASK
, MULHW
, 0, {RT
, RA
, RB
}},
4313 {"evmwumian", VX (4,1496), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
4314 {"macchwso.", XO (4, 236,1,1), XO_MASK
, MULHW
, 0, {RT
, RA
, RB
}},
4315 {"evmwsmian", VX (4,1497), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
4316 {"evmwsmfan", VX (4,1499), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
4317 {"evmwhgumian", VX (4,1508), VX_MASK
, PPCSPE
, 0, {RD
, RA
, RB
}},
4318 {"evmwhgsmian", VX (4,1509), VX_MASK
, PPCSPE
, 0, {RD
, RA
, RB
}},
4319 {"evmwhgssfan", VX (4,1511), VX_MASK
, PPCSPE
, 0, {RD
, RA
, RB
}},
4320 {"evmwhgsmfan", VX (4,1519), VX_MASK
, PPCSPE
, 0, {RD
, RA
, RB
}},
4321 {"nmacchwso", XO (4, 238,1,0), XO_MASK
, MULHW
, 0, {RT
, RA
, RB
}},
4322 {"nmacchwso.", XO (4, 238,1,1), XO_MASK
, MULHW
, 0, {RT
, RA
, RB
}},
4323 {"vsububs", VX (4,1536), VX_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
4324 {"vclzlsbb", VXVA(4,1538,0), VXVA_MASK
, PPCVEC3
, 0, {RT
, VB
}},
4325 {"vctzlsbb", VXVA(4,1538,1), VXVA_MASK
, PPCVEC3
, 0, {RT
, VB
}},
4326 {"vnegw", VXVA(4,1538,6), VXVA_MASK
, PPCVEC3
, 0, {VD
, VB
}},
4327 {"vnegd", VXVA(4,1538,7), VXVA_MASK
, PPCVEC3
, 0, {VD
, VB
}},
4328 {"vprtybw", VXVA(4,1538,8), VXVA_MASK
, PPCVEC3
, 0, {VD
, VB
}},
4329 {"vprtybd", VXVA(4,1538,9), VXVA_MASK
, PPCVEC3
, 0, {VD
, VB
}},
4330 {"vprtybq", VXVA(4,1538,10), VXVA_MASK
, PPCVEC3
, 0, {VD
, VB
}},
4331 {"vextsb2w", VXVA(4,1538,16), VXVA_MASK
, PPCVEC3
, 0, {VD
, VB
}},
4332 {"vextsh2w", VXVA(4,1538,17), VXVA_MASK
, PPCVEC3
, 0, {VD
, VB
}},
4333 {"vextsb2d", VXVA(4,1538,24), VXVA_MASK
, PPCVEC3
, 0, {VD
, VB
}},
4334 {"vextsh2d", VXVA(4,1538,25), VXVA_MASK
, PPCVEC3
, 0, {VD
, VB
}},
4335 {"vextsw2d", VXVA(4,1538,26), VXVA_MASK
, PPCVEC3
, 0, {VD
, VB
}},
4336 {"vctzb", VXVA(4,1538,28), VXVA_MASK
, PPCVEC3
, 0, {VD
, VB
}},
4337 {"vctzh", VXVA(4,1538,29), VXVA_MASK
, PPCVEC3
, 0, {VD
, VB
}},
4338 {"vctzw", VXVA(4,1538,30), VXVA_MASK
, PPCVEC3
, 0, {VD
, VB
}},
4339 {"vctzd", VXVA(4,1538,31), VXVA_MASK
, PPCVEC3
, 0, {VD
, VB
}},
4340 {"mfvscr", VX (4,1540), VXVAVB_MASK
, PPCVEC
, 0, {VD
}},
4341 {"vcmpgtub.", VXR(4, 518,1), VXR_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
4342 {"udi8fcm.", APU(4, 771,0), APU_MASK
, PPC440
, 0, {URT
, URA
, URB
}},
4343 {"udi8fcm", APU(4, 771,1), APU_MASK
, PPC440
, 0, {URT
, URA
, URB
}},
4344 {"vsum4ubs", VX (4,1544), VX_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
4345 {"vextublx", VX (4,1549), VX_MASK
, PPCVEC3
, 0, {RT
, RA
, VB
}},
4346 {"vsubuhs", VX (4,1600), VX_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
4347 {"mtvscr", VX (4,1604), VXVDVA_MASK
, PPCVEC
, 0, {VB
}},
4348 {"vcmpgtuh.", VXR(4, 582,1), VXR_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
4349 {"vsum4shs", VX (4,1608), VX_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
4350 {"udi9fcm.", APU(4, 804,0), APU_MASK
, PPC440
, 0, {URT
, URA
, URB
}},
4351 {"udi9fcm", APU(4, 804,1), APU_MASK
, PPC440
, 0, {URT
, URA
, URB
}},
4352 {"vextuhlx", VX (4,1613), VX_MASK
, PPCVEC3
, 0, {RT
, RA
, VB
}},
4353 {"vupkhsw", VX (4,1614), VXVA_MASK
, PPCVEC2
, 0, {VD
, VB
}},
4354 {"vsubuws", VX (4,1664), VX_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
4355 {"vshasigmaw", VX (4,1666), VX_MASK
, PPCVEC2
, 0, {VD
, VA
, ST
, SIX
}},
4356 {"veqv", VX (4,1668), VX_MASK
, PPCVEC2
, 0, {VD
, VA
, VB
}},
4357 {"vcmpgtuw.", VXR(4, 646,1), VXR_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
4358 {"udi10fcm.", APU(4, 835,0), APU_MASK
, PPC440
, 0, {URT
, URA
, URB
}},
4359 {"udi10fcm", APU(4, 835,1), APU_MASK
, PPC440
, 0, {URT
, URA
, URB
}},
4360 {"vsum2sws", VX (4,1672), VX_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
4361 {"vmrgow", VX (4,1676), VX_MASK
, PPCVEC2
, 0, {VD
, VA
, VB
}},
4362 {"vextuwlx", VX (4,1677), VX_MASK
, PPCVEC3
, 0, {RT
, RA
, VB
}},
4363 {"vshasigmad", VX (4,1730), VX_MASK
, PPCVEC2
, 0, {VD
, VA
, ST
, SIX
}},
4364 {"vsrd", VX (4,1732), VX_MASK
, PPCVEC2
, 0, {VD
, VA
, VB
}},
4365 {"vcmpgtfp.", VXR(4, 710,1), VXR_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
4366 {"udi11fcm.", APU(4, 867,0), APU_MASK
, PPC440
, 0, {URT
, URA
, URB
}},
4367 {"vcmpgtud.", VXR(4, 711,1), VXR_MASK
, PPCVEC2
, 0, {VD
, VA
, VB
}},
4368 {"udi11fcm", APU(4, 867,1), APU_MASK
, PPC440
, 0, {URT
, URA
, URB
}},
4369 {"vupklsw", VX (4,1742), VXVA_MASK
, PPCVEC2
, 0, {VD
, VB
}},
4370 {"vsubsbs", VX (4,1792), VX_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
4371 {"vclzb", VX (4,1794), VXVA_MASK
, PPCVEC2
, 0, {VD
, VB
}},
4372 {"vpopcntb", VX (4,1795), VXVA_MASK
, PPCVEC2
, 0, {VD
, VB
}},
4373 {"vsrv", VX (4,1796), VX_MASK
, PPCVEC3
, 0, {VD
, VA
, VB
}},
4374 {"vcmpgtsb.", VXR(4, 774,1), VXR_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
4375 {"udi12fcm.", APU(4, 899,0), APU_MASK
, PPC440
, 0, {URT
, URA
, URB
}},
4376 {"udi12fcm", APU(4, 899,1), APU_MASK
, PPC440
, 0, {URT
, URA
, URB
}},
4377 {"vsum4sbs", VX (4,1800), VX_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
4378 {"vextubrx", VX (4,1805), VX_MASK
, PPCVEC3
, 0, {RT
, RA
, VB
}},
4379 {"maclhwuo", XO (4, 396,1,0), XO_MASK
, MULHW
, 0, {RT
, RA
, RB
}},
4380 {"maclhwuo.", XO (4, 396,1,1), XO_MASK
, MULHW
, 0, {RT
, RA
, RB
}},
4381 {"vsubshs", VX (4,1856), VX_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
4382 {"vclzh", VX (4,1858), VXVA_MASK
, PPCVEC2
, 0, {VD
, VB
}},
4383 {"vpopcnth", VX (4,1859), VXVA_MASK
, PPCVEC2
, 0, {VD
, VB
}},
4384 {"vslv", VX (4,1860), VX_MASK
, PPCVEC3
, 0, {VD
, VA
, VB
}},
4385 {"vcmpgtsh.", VXR(4, 838,1), VXR_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
4386 {"vextuhrx", VX (4,1869), VX_MASK
, PPCVEC3
, 0, {RT
, RA
, VB
}},
4387 {"udi13fcm.", APU(4, 931,0), APU_MASK
, PPC440
, 0, {URT
, URA
, URB
}},
4388 {"udi13fcm", APU(4, 931,1), APU_MASK
, PPC440
, 0, {URT
, URA
, URB
}},
4389 {"maclhwo", XO (4, 428,1,0), XO_MASK
, MULHW
, 0, {RT
, RA
, RB
}},
4390 {"maclhwo.", XO (4, 428,1,1), XO_MASK
, MULHW
, 0, {RT
, RA
, RB
}},
4391 {"nmaclhwo", XO (4, 430,1,0), XO_MASK
, MULHW
, 0, {RT
, RA
, RB
}},
4392 {"nmaclhwo.", XO (4, 430,1,1), XO_MASK
, MULHW
, 0, {RT
, RA
, RB
}},
4393 {"vsubsws", VX (4,1920), VX_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
4394 {"vclzw", VX (4,1922), VXVA_MASK
, PPCVEC2
, 0, {VD
, VB
}},
4395 {"vpopcntw", VX (4,1923), VXVA_MASK
, PPCVEC2
, 0, {VD
, VB
}},
4396 {"vcmpgtsw.", VXR(4, 902,1), VXR_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
4397 {"udi14fcm.", APU(4, 963,0), APU_MASK
, PPC440
, 0, {URT
, URA
, URB
}},
4398 {"udi14fcm", APU(4, 963,1), APU_MASK
, PPC440
, 0, {URT
, URA
, URB
}},
4399 {"vsumsws", VX (4,1928), VX_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
4400 {"vmrgew", VX (4,1932), VX_MASK
, PPCVEC2
, 0, {VD
, VA
, VB
}},
4401 {"vextuwrx", VX (4,1933), VX_MASK
, PPCVEC3
, 0, {RT
, RA
, VB
}},
4402 {"maclhwsuo", XO (4, 460,1,0), XO_MASK
, MULHW
, 0, {RT
, RA
, RB
}},
4403 {"maclhwsuo.", XO (4, 460,1,1), XO_MASK
, MULHW
, 0, {RT
, RA
, RB
}},
4404 {"vclzd", VX (4,1986), VXVA_MASK
, PPCVEC2
, 0, {VD
, VB
}},
4405 {"vpopcntd", VX (4,1987), VXVA_MASK
, PPCVEC2
, 0, {VD
, VB
}},
4406 {"vcmpbfp.", VXR(4, 966,1), VXR_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
4407 {"udi15fcm.", APU(4, 995,0), APU_MASK
, PPC440
, 0, {URT
, URA
, URB
}},
4408 {"vcmpgtsd.", VXR(4, 967,1), VXR_MASK
, PPCVEC2
, 0, {VD
, VA
, VB
}},
4409 {"udi15fcm", APU(4, 995,1), APU_MASK
, PPC440
, 0, {URT
, URA
, URB
}},
4410 {"maclhwso", XO (4, 492,1,0), XO_MASK
, MULHW
, 0, {RT
, RA
, RB
}},
4411 {"maclhwso.", XO (4, 492,1,1), XO_MASK
, MULHW
, 0, {RT
, RA
, RB
}},
4412 {"nmaclhwso", XO (4, 494,1,0), XO_MASK
, MULHW
, 0, {RT
, RA
, RB
}},
4413 {"nmaclhwso.", XO (4, 494,1,1), XO_MASK
, MULHW
, 0, {RT
, RA
, RB
}},
4414 {"dcbz_l", X (4,1014), XRT_MASK
, PPCPS
, 0, {RA
, RB
}},
4416 {"mulli", OP(7), OP_MASK
, PPCCOM
, PPCVLE
, {RT
, RA
, SI
}},
4417 {"muli", OP(7), OP_MASK
, PWRCOM
, PPCVLE
, {RT
, RA
, SI
}},
4419 {"subfic", OP(8), OP_MASK
, PPCCOM
, PPCVLE
, {RT
, RA
, SI
}},
4420 {"sfi", OP(8), OP_MASK
, PWRCOM
, PPCVLE
, {RT
, RA
, SI
}},
4422 {"dozi", OP(9), OP_MASK
, M601
, PPCVLE
, {RT
, RA
, SI
}},
4424 {"cmplwi", OPL(10,0), OPL_MASK
, PPCCOM
, PPCVLE
, {OBF
, RA
, UISIGNOPT
}},
4425 {"cmpldi", OPL(10,1), OPL_MASK
, PPC64
, PPCVLE
, {OBF
, RA
, UISIGNOPT
}},
4426 {"cmpli", OP(10), OP_MASK
, PPC
, PPCVLE
, {BF
, L32OPT
, RA
, UISIGNOPT
}},
4427 {"cmpli", OP(10), OP_MASK
, PWRCOM
, PPC
|PPCVLE
, {BF
, RA
, UISIGNOPT
}},
4429 {"cmpwi", OPL(11,0), OPL_MASK
, PPCCOM
, PPCVLE
, {OBF
, RA
, SI
}},
4430 {"cmpdi", OPL(11,1), OPL_MASK
, PPC64
, PPCVLE
, {OBF
, RA
, SI
}},
4431 {"cmpi", OP(11), OP_MASK
, PPC
, PPCVLE
, {BF
, L32OPT
, RA
, SI
}},
4432 {"cmpi", OP(11), OP_MASK
, PWRCOM
, PPC
|PPCVLE
, {BF
, RA
, SI
}},
4434 {"addic", OP(12), OP_MASK
, PPCCOM
, PPCVLE
, {RT
, RA
, SI
}},
4435 {"ai", OP(12), OP_MASK
, PWRCOM
, PPCVLE
, {RT
, RA
, SI
}},
4436 {"subic", OP(12), OP_MASK
, PPCCOM
, PPCVLE
, {RT
, RA
, NSI
}},
4438 {"addic.", OP(13), OP_MASK
, PPCCOM
, PPCVLE
, {RT
, RA
, SI
}},
4439 {"ai.", OP(13), OP_MASK
, PWRCOM
, PPCVLE
, {RT
, RA
, SI
}},
4440 {"subic.", OP(13), OP_MASK
, PPCCOM
, PPCVLE
, {RT
, RA
, NSI
}},
4442 {"li", OP(14), DRA_MASK
, PPCCOM
, PPCVLE
, {RT
, SI
}},
4443 {"lil", OP(14), DRA_MASK
, PWRCOM
, PPCVLE
, {RT
, SI
}},
4444 {"addi", OP(14), OP_MASK
, PPCCOM
, PPCVLE
, {RT
, RA0
, SI
}},
4445 {"cal", OP(14), OP_MASK
, PWRCOM
, PPCVLE
, {RT
, D
, RA0
}},
4446 {"subi", OP(14), OP_MASK
, PPCCOM
, PPCVLE
, {RT
, RA0
, NSI
}},
4447 {"la", OP(14), OP_MASK
, PPCCOM
, PPCVLE
, {RT
, D
, RA0
}},
4449 {"lis", OP(15), DRA_MASK
, PPCCOM
, PPCVLE
, {RT
, SISIGNOPT
}},
4450 {"liu", OP(15), DRA_MASK
, PWRCOM
, PPCVLE
, {RT
, SISIGNOPT
}},
4451 {"addis", OP(15), OP_MASK
, PPCCOM
, PPCVLE
, {RT
, RA0
, SISIGNOPT
}},
4452 {"cau", OP(15), OP_MASK
, PWRCOM
, PPCVLE
, {RT
, RA0
, SISIGNOPT
}},
4453 {"subis", OP(15), OP_MASK
, PPCCOM
, PPCVLE
, {RT
, RA0
, NSISIGNOPT
}},
4455 {"bdnz-", BBO(16,BODNZ
,0,0), BBOATBI_MASK
, PPCCOM
, PPCVLE
, {BDM
}},
4456 {"bdnz+", BBO(16,BODNZ
,0,0), BBOATBI_MASK
, PPCCOM
, PPCVLE
, {BDP
}},
4457 {"bdnz", BBO(16,BODNZ
,0,0), BBOATBI_MASK
, PPCCOM
, PPCVLE
, {BD
}},
4458 {"bdn", BBO(16,BODNZ
,0,0), BBOATBI_MASK
, PWRCOM
, PPCVLE
, {BD
}},
4459 {"bdnzl-", BBO(16,BODNZ
,0,1), BBOATBI_MASK
, PPCCOM
, PPCVLE
, {BDM
}},
4460 {"bdnzl+", BBO(16,BODNZ
,0,1), BBOATBI_MASK
, PPCCOM
, PPCVLE
, {BDP
}},
4461 {"bdnzl", BBO(16,BODNZ
,0,1), BBOATBI_MASK
, PPCCOM
, PPCVLE
, {BD
}},
4462 {"bdnl", BBO(16,BODNZ
,0,1), BBOATBI_MASK
, PWRCOM
, PPCVLE
, {BD
}},
4463 {"bdnza-", BBO(16,BODNZ
,1,0), BBOATBI_MASK
, PPCCOM
, PPCVLE
, {BDMA
}},
4464 {"bdnza+", BBO(16,BODNZ
,1,0), BBOATBI_MASK
, PPCCOM
, PPCVLE
, {BDPA
}},
4465 {"bdnza", BBO(16,BODNZ
,1,0), BBOATBI_MASK
, PPCCOM
, PPCVLE
, {BDA
}},
4466 {"bdna", BBO(16,BODNZ
,1,0), BBOATBI_MASK
, PWRCOM
, PPCVLE
, {BDA
}},
4467 {"bdnzla-", BBO(16,BODNZ
,1,1), BBOATBI_MASK
, PPCCOM
, PPCVLE
, {BDMA
}},
4468 {"bdnzla+", BBO(16,BODNZ
,1,1), BBOATBI_MASK
, PPCCOM
, PPCVLE
, {BDPA
}},
4469 {"bdnzla", BBO(16,BODNZ
,1,1), BBOATBI_MASK
, PPCCOM
, PPCVLE
, {BDA
}},
4470 {"bdnla", BBO(16,BODNZ
,1,1), BBOATBI_MASK
, PWRCOM
, PPCVLE
, {BDA
}},
4471 {"bdz-", BBO(16,BODZ
,0,0), BBOATBI_MASK
, PPCCOM
, PPCVLE
, {BDM
}},
4472 {"bdz+", BBO(16,BODZ
,0,0), BBOATBI_MASK
, PPCCOM
, PPCVLE
, {BDP
}},
4473 {"bdz", BBO(16,BODZ
,0,0), BBOATBI_MASK
, COM
, PPCVLE
, {BD
}},
4474 {"bdzl-", BBO(16,BODZ
,0,1), BBOATBI_MASK
, PPCCOM
, PPCVLE
, {BDM
}},
4475 {"bdzl+", BBO(16,BODZ
,0,1), BBOATBI_MASK
, PPCCOM
, PPCVLE
, {BDP
}},
4476 {"bdzl", BBO(16,BODZ
,0,1), BBOATBI_MASK
, COM
, PPCVLE
, {BD
}},
4477 {"bdza-", BBO(16,BODZ
,1,0), BBOATBI_MASK
, PPCCOM
, PPCVLE
, {BDMA
}},
4478 {"bdza+", BBO(16,BODZ
,1,0), BBOATBI_MASK
, PPCCOM
, PPCVLE
, {BDPA
}},
4479 {"bdza", BBO(16,BODZ
,1,0), BBOATBI_MASK
, COM
, PPCVLE
, {BDA
}},
4480 {"bdzla-", BBO(16,BODZ
,1,1), BBOATBI_MASK
, PPCCOM
, PPCVLE
, {BDMA
}},
4481 {"bdzla+", BBO(16,BODZ
,1,1), BBOATBI_MASK
, PPCCOM
, PPCVLE
, {BDPA
}},
4482 {"bdzla", BBO(16,BODZ
,1,1), BBOATBI_MASK
, COM
, PPCVLE
, {BDA
}},
4484 {"bge-", BBOCB(16,BOF
,CBLT
,0,0), BBOATCB_MASK
, PPCCOM
, PPCVLE
, {CR
, BDM
}},
4485 {"bge+", BBOCB(16,BOF
,CBLT
,0,0), BBOATCB_MASK
, PPCCOM
, PPCVLE
, {CR
, BDP
}},
4486 {"bge", BBOCB(16,BOF
,CBLT
,0,0), BBOATCB_MASK
, COM
, PPCVLE
, {CR
, BD
}},
4487 {"bnl-", BBOCB(16,BOF
,CBLT
,0,0), BBOATCB_MASK
, PPCCOM
, PPCVLE
, {CR
, BDM
}},
4488 {"bnl+", BBOCB(16,BOF
,CBLT
,0,0), BBOATCB_MASK
, PPCCOM
, PPCVLE
, {CR
, BDP
}},
4489 {"bnl", BBOCB(16,BOF
,CBLT
,0,0), BBOATCB_MASK
, COM
, PPCVLE
, {CR
, BD
}},
4490 {"bgel-", BBOCB(16,BOF
,CBLT
,0,1), BBOATCB_MASK
, PPCCOM
, PPCVLE
, {CR
, BDM
}},
4491 {"bgel+", BBOCB(16,BOF
,CBLT
,0,1), BBOATCB_MASK
, PPCCOM
, PPCVLE
, {CR
, BDP
}},
4492 {"bgel", BBOCB(16,BOF
,CBLT
,0,1), BBOATCB_MASK
, COM
, PPCVLE
, {CR
, BD
}},
4493 {"bnll-", BBOCB(16,BOF
,CBLT
,0,1), BBOATCB_MASK
, PPCCOM
, PPCVLE
, {CR
, BDM
}},
4494 {"bnll+", BBOCB(16,BOF
,CBLT
,0,1), BBOATCB_MASK
, PPCCOM
, PPCVLE
, {CR
, BDP
}},
4495 {"bnll", BBOCB(16,BOF
,CBLT
,0,1), BBOATCB_MASK
, COM
, PPCVLE
, {CR
, BD
}},
4496 {"bgea-", BBOCB(16,BOF
,CBLT
,1,0), BBOATCB_MASK
, PPCCOM
, PPCVLE
, {CR
, BDMA
}},
4497 {"bgea+", BBOCB(16,BOF
,CBLT
,1,0), BBOATCB_MASK
, PPCCOM
, PPCVLE
, {CR
, BDPA
}},
4498 {"bgea", BBOCB(16,BOF
,CBLT
,1,0), BBOATCB_MASK
, COM
, PPCVLE
, {CR
, BDA
}},
4499 {"bnla-", BBOCB(16,BOF
,CBLT
,1,0), BBOATCB_MASK
, PPCCOM
, PPCVLE
, {CR
, BDMA
}},
4500 {"bnla+", BBOCB(16,BOF
,CBLT
,1,0), BBOATCB_MASK
, PPCCOM
, PPCVLE
, {CR
, BDPA
}},
4501 {"bnla", BBOCB(16,BOF
,CBLT
,1,0), BBOATCB_MASK
, COM
, PPCVLE
, {CR
, BDA
}},
4502 {"bgela-", BBOCB(16,BOF
,CBLT
,1,1), BBOATCB_MASK
, PPCCOM
, PPCVLE
, {CR
, BDMA
}},
4503 {"bgela+", BBOCB(16,BOF
,CBLT
,1,1), BBOATCB_MASK
, PPCCOM
, PPCVLE
, {CR
, BDPA
}},
4504 {"bgela", BBOCB(16,BOF
,CBLT
,1,1), BBOATCB_MASK
, COM
, PPCVLE
, {CR
, BDA
}},
4505 {"bnlla-", BBOCB(16,BOF
,CBLT
,1,1), BBOATCB_MASK
, PPCCOM
, PPCVLE
, {CR
, BDMA
}},
4506 {"bnlla+", BBOCB(16,BOF
,CBLT
,1,1), BBOATCB_MASK
, PPCCOM
, PPCVLE
, {CR
, BDPA
}},
4507 {"bnlla", BBOCB(16,BOF
,CBLT
,1,1), BBOATCB_MASK
, COM
, PPCVLE
, {CR
, BDA
}},
4508 {"ble-", BBOCB(16,BOF
,CBGT
,0,0), BBOATCB_MASK
, PPCCOM
, PPCVLE
, {CR
, BDM
}},
4509 {"ble+", BBOCB(16,BOF
,CBGT
,0,0), BBOATCB_MASK
, PPCCOM
, PPCVLE
, {CR
, BDP
}},
4510 {"ble", BBOCB(16,BOF
,CBGT
,0,0), BBOATCB_MASK
, COM
, PPCVLE
, {CR
, BD
}},
4511 {"bng-", BBOCB(16,BOF
,CBGT
,0,0), BBOATCB_MASK
, PPCCOM
, PPCVLE
, {CR
, BDM
}},
4512 {"bng+", BBOCB(16,BOF
,CBGT
,0,0), BBOATCB_MASK
, PPCCOM
, PPCVLE
, {CR
, BDP
}},
4513 {"bng", BBOCB(16,BOF
,CBGT
,0,0), BBOATCB_MASK
, COM
, PPCVLE
, {CR
, BD
}},
4514 {"blel-", BBOCB(16,BOF
,CBGT
,0,1), BBOATCB_MASK
, PPCCOM
, PPCVLE
, {CR
, BDM
}},
4515 {"blel+", BBOCB(16,BOF
,CBGT
,0,1), BBOATCB_MASK
, PPCCOM
, PPCVLE
, {CR
, BDP
}},
4516 {"blel", BBOCB(16,BOF
,CBGT
,0,1), BBOATCB_MASK
, COM
, PPCVLE
, {CR
, BD
}},
4517 {"bngl-", BBOCB(16,BOF
,CBGT
,0,1), BBOATCB_MASK
, PPCCOM
, PPCVLE
, {CR
, BDM
}},
4518 {"bngl+", BBOCB(16,BOF
,CBGT
,0,1), BBOATCB_MASK
, PPCCOM
, PPCVLE
, {CR
, BDP
}},
4519 {"bngl", BBOCB(16,BOF
,CBGT
,0,1), BBOATCB_MASK
, COM
, PPCVLE
, {CR
, BD
}},
4520 {"blea-", BBOCB(16,BOF
,CBGT
,1,0), BBOATCB_MASK
, PPCCOM
, PPCVLE
, {CR
, BDMA
}},
4521 {"blea+", BBOCB(16,BOF
,CBGT
,1,0), BBOATCB_MASK
, PPCCOM
, PPCVLE
, {CR
, BDPA
}},
4522 {"blea", BBOCB(16,BOF
,CBGT
,1,0), BBOATCB_MASK
, COM
, PPCVLE
, {CR
, BDA
}},
4523 {"bnga-", BBOCB(16,BOF
,CBGT
,1,0), BBOATCB_MASK
, PPCCOM
, PPCVLE
, {CR
, BDMA
}},
4524 {"bnga+", BBOCB(16,BOF
,CBGT
,1,0), BBOATCB_MASK
, PPCCOM
, PPCVLE
, {CR
, BDPA
}},
4525 {"bnga", BBOCB(16,BOF
,CBGT
,1,0), BBOATCB_MASK
, COM
, PPCVLE
, {CR
, BDA
}},
4526 {"blela-", BBOCB(16,BOF
,CBGT
,1,1), BBOATCB_MASK
, PPCCOM
, PPCVLE
, {CR
, BDMA
}},
4527 {"blela+", BBOCB(16,BOF
,CBGT
,1,1), BBOATCB_MASK
, PPCCOM
, PPCVLE
, {CR
, BDPA
}},
4528 {"blela", BBOCB(16,BOF
,CBGT
,1,1), BBOATCB_MASK
, COM
, PPCVLE
, {CR
, BDA
}},
4529 {"bngla-", BBOCB(16,BOF
,CBGT
,1,1), BBOATCB_MASK
, PPCCOM
, PPCVLE
, {CR
, BDMA
}},
4530 {"bngla+", BBOCB(16,BOF
,CBGT
,1,1), BBOATCB_MASK
, PPCCOM
, PPCVLE
, {CR
, BDPA
}},
4531 {"bngla", BBOCB(16,BOF
,CBGT
,1,1), BBOATCB_MASK
, COM
, PPCVLE
, {CR
, BDA
}},
4532 {"bne-", BBOCB(16,BOF
,CBEQ
,0,0), BBOATCB_MASK
, PPCCOM
, PPCVLE
, {CR
, BDM
}},
4533 {"bne+", BBOCB(16,BOF
,CBEQ
,0,0), BBOATCB_MASK
, PPCCOM
, PPCVLE
, {CR
, BDP
}},
4534 {"bne", BBOCB(16,BOF
,CBEQ
,0,0), BBOATCB_MASK
, COM
, PPCVLE
, {CR
, BD
}},
4535 {"bnel-", BBOCB(16,BOF
,CBEQ
,0,1), BBOATCB_MASK
, PPCCOM
, PPCVLE
, {CR
, BDM
}},
4536 {"bnel+", BBOCB(16,BOF
,CBEQ
,0,1), BBOATCB_MASK
, PPCCOM
, PPCVLE
, {CR
, BDP
}},
4537 {"bnel", BBOCB(16,BOF
,CBEQ
,0,1), BBOATCB_MASK
, COM
, PPCVLE
, {CR
, BD
}},
4538 {"bnea-", BBOCB(16,BOF
,CBEQ
,1,0), BBOATCB_MASK
, PPCCOM
, PPCVLE
, {CR
, BDMA
}},
4539 {"bnea+", BBOCB(16,BOF
,CBEQ
,1,0), BBOATCB_MASK
, PPCCOM
, PPCVLE
, {CR
, BDPA
}},
4540 {"bnea", BBOCB(16,BOF
,CBEQ
,1,0), BBOATCB_MASK
, COM
, PPCVLE
, {CR
, BDA
}},
4541 {"bnela-", BBOCB(16,BOF
,CBEQ
,1,1), BBOATCB_MASK
, PPCCOM
, PPCVLE
, {CR
, BDMA
}},
4542 {"bnela+", BBOCB(16,BOF
,CBEQ
,1,1), BBOATCB_MASK
, PPCCOM
, PPCVLE
, {CR
, BDPA
}},
4543 {"bnela", BBOCB(16,BOF
,CBEQ
,1,1), BBOATCB_MASK
, COM
, PPCVLE
, {CR
, BDA
}},
4544 {"bns-", BBOCB(16,BOF
,CBSO
,0,0), BBOATCB_MASK
, PPCCOM
, PPCVLE
, {CR
, BDM
}},
4545 {"bns+", BBOCB(16,BOF
,CBSO
,0,0), BBOATCB_MASK
, PPCCOM
, PPCVLE
, {CR
, BDP
}},
4546 {"bns", BBOCB(16,BOF
,CBSO
,0,0), BBOATCB_MASK
, COM
, PPCVLE
, {CR
, BD
}},
4547 {"bnu-", BBOCB(16,BOF
,CBSO
,0,0), BBOATCB_MASK
, PPCCOM
, PPCVLE
, {CR
, BDM
}},
4548 {"bnu+", BBOCB(16,BOF
,CBSO
,0,0), BBOATCB_MASK
, PPCCOM
, PPCVLE
, {CR
, BDP
}},
4549 {"bnu", BBOCB(16,BOF
,CBSO
,0,0), BBOATCB_MASK
, PPCCOM
, PPCVLE
, {CR
, BD
}},
4550 {"bnsl-", BBOCB(16,BOF
,CBSO
,0,1), BBOATCB_MASK
, PPCCOM
, PPCVLE
, {CR
, BDM
}},
4551 {"bnsl+", BBOCB(16,BOF
,CBSO
,0,1), BBOATCB_MASK
, PPCCOM
, PPCVLE
, {CR
, BDP
}},
4552 {"bnsl", BBOCB(16,BOF
,CBSO
,0,1), BBOATCB_MASK
, COM
, PPCVLE
, {CR
, BD
}},
4553 {"bnul-", BBOCB(16,BOF
,CBSO
,0,1), BBOATCB_MASK
, PPCCOM
, PPCVLE
, {CR
, BDM
}},
4554 {"bnul+", BBOCB(16,BOF
,CBSO
,0,1), BBOATCB_MASK
, PPCCOM
, PPCVLE
, {CR
, BDP
}},
4555 {"bnul", BBOCB(16,BOF
,CBSO
,0,1), BBOATCB_MASK
, PPCCOM
, PPCVLE
, {CR
, BD
}},
4556 {"bnsa-", BBOCB(16,BOF
,CBSO
,1,0), BBOATCB_MASK
, PPCCOM
, PPCVLE
, {CR
, BDMA
}},
4557 {"bnsa+", BBOCB(16,BOF
,CBSO
,1,0), BBOATCB_MASK
, PPCCOM
, PPCVLE
, {CR
, BDPA
}},
4558 {"bnsa", BBOCB(16,BOF
,CBSO
,1,0), BBOATCB_MASK
, COM
, PPCVLE
, {CR
, BDA
}},
4559 {"bnua-", BBOCB(16,BOF
,CBSO
,1,0), BBOATCB_MASK
, PPCCOM
, PPCVLE
, {CR
, BDMA
}},
4560 {"bnua+", BBOCB(16,BOF
,CBSO
,1,0), BBOATCB_MASK
, PPCCOM
, PPCVLE
, {CR
, BDPA
}},
4561 {"bnua", BBOCB(16,BOF
,CBSO
,1,0), BBOATCB_MASK
, PPCCOM
, PPCVLE
, {CR
, BDA
}},
4562 {"bnsla-", BBOCB(16,BOF
,CBSO
,1,1), BBOATCB_MASK
, PPCCOM
, PPCVLE
, {CR
, BDMA
}},
4563 {"bnsla+", BBOCB(16,BOF
,CBSO
,1,1), BBOATCB_MASK
, PPCCOM
, PPCVLE
, {CR
, BDPA
}},
4564 {"bnsla", BBOCB(16,BOF
,CBSO
,1,1), BBOATCB_MASK
, COM
, PPCVLE
, {CR
, BDA
}},
4565 {"bnula-", BBOCB(16,BOF
,CBSO
,1,1), BBOATCB_MASK
, PPCCOM
, PPCVLE
, {CR
, BDMA
}},
4566 {"bnula+", BBOCB(16,BOF
,CBSO
,1,1), BBOATCB_MASK
, PPCCOM
, PPCVLE
, {CR
, BDPA
}},
4567 {"bnula", BBOCB(16,BOF
,CBSO
,1,1), BBOATCB_MASK
, PPCCOM
, PPCVLE
, {CR
, BDA
}},
4569 {"blt-", BBOCB(16,BOT
,CBLT
,0,0), BBOATCB_MASK
, PPCCOM
, PPCVLE
, {CR
, BDM
}},
4570 {"blt+", BBOCB(16,BOT
,CBLT
,0,0), BBOATCB_MASK
, PPCCOM
, PPCVLE
, {CR
, BDP
}},
4571 {"blt", BBOCB(16,BOT
,CBLT
,0,0), BBOATCB_MASK
, COM
, PPCVLE
, {CR
, BD
}},
4572 {"bltl-", BBOCB(16,BOT
,CBLT
,0,1), BBOATCB_MASK
, PPCCOM
, PPCVLE
, {CR
, BDM
}},
4573 {"bltl+", BBOCB(16,BOT
,CBLT
,0,1), BBOATCB_MASK
, PPCCOM
, PPCVLE
, {CR
, BDP
}},
4574 {"bltl", BBOCB(16,BOT
,CBLT
,0,1), BBOATCB_MASK
, COM
, PPCVLE
, {CR
, BD
}},
4575 {"blta-", BBOCB(16,BOT
,CBLT
,1,0), BBOATCB_MASK
, PPCCOM
, PPCVLE
, {CR
, BDMA
}},
4576 {"blta+", BBOCB(16,BOT
,CBLT
,1,0), BBOATCB_MASK
, PPCCOM
, PPCVLE
, {CR
, BDPA
}},
4577 {"blta", BBOCB(16,BOT
,CBLT
,1,0), BBOATCB_MASK
, COM
, PPCVLE
, {CR
, BDA
}},
4578 {"bltla-", BBOCB(16,BOT
,CBLT
,1,1), BBOATCB_MASK
, PPCCOM
, PPCVLE
, {CR
, BDMA
}},
4579 {"bltla+", BBOCB(16,BOT
,CBLT
,1,1), BBOATCB_MASK
, PPCCOM
, PPCVLE
, {CR
, BDPA
}},
4580 {"bltla", BBOCB(16,BOT
,CBLT
,1,1), BBOATCB_MASK
, COM
, PPCVLE
, {CR
, BDA
}},
4581 {"bgt-", BBOCB(16,BOT
,CBGT
,0,0), BBOATCB_MASK
, PPCCOM
, PPCVLE
, {CR
, BDM
}},
4582 {"bgt+", BBOCB(16,BOT
,CBGT
,0,0), BBOATCB_MASK
, PPCCOM
, PPCVLE
, {CR
, BDP
}},
4583 {"bgt", BBOCB(16,BOT
,CBGT
,0,0), BBOATCB_MASK
, COM
, PPCVLE
, {CR
, BD
}},
4584 {"bgtl-", BBOCB(16,BOT
,CBGT
,0,1), BBOATCB_MASK
, PPCCOM
, PPCVLE
, {CR
, BDM
}},
4585 {"bgtl+", BBOCB(16,BOT
,CBGT
,0,1), BBOATCB_MASK
, PPCCOM
, PPCVLE
, {CR
, BDP
}},
4586 {"bgtl", BBOCB(16,BOT
,CBGT
,0,1), BBOATCB_MASK
, COM
, PPCVLE
, {CR
, BD
}},
4587 {"bgta-", BBOCB(16,BOT
,CBGT
,1,0), BBOATCB_MASK
, PPCCOM
, PPCVLE
, {CR
, BDMA
}},
4588 {"bgta+", BBOCB(16,BOT
,CBGT
,1,0), BBOATCB_MASK
, PPCCOM
, PPCVLE
, {CR
, BDPA
}},
4589 {"bgta", BBOCB(16,BOT
,CBGT
,1,0), BBOATCB_MASK
, COM
, PPCVLE
, {CR
, BDA
}},
4590 {"bgtla-", BBOCB(16,BOT
,CBGT
,1,1), BBOATCB_MASK
, PPCCOM
, PPCVLE
, {CR
, BDMA
}},
4591 {"bgtla+", BBOCB(16,BOT
,CBGT
,1,1), BBOATCB_MASK
, PPCCOM
, PPCVLE
, {CR
, BDPA
}},
4592 {"bgtla", BBOCB(16,BOT
,CBGT
,1,1), BBOATCB_MASK
, COM
, PPCVLE
, {CR
, BDA
}},
4593 {"beq-", BBOCB(16,BOT
,CBEQ
,0,0), BBOATCB_MASK
, PPCCOM
, PPCVLE
, {CR
, BDM
}},
4594 {"beq+", BBOCB(16,BOT
,CBEQ
,0,0), BBOATCB_MASK
, PPCCOM
, PPCVLE
, {CR
, BDP
}},
4595 {"beq", BBOCB(16,BOT
,CBEQ
,0,0), BBOATCB_MASK
, COM
, PPCVLE
, {CR
, BD
}},
4596 {"beql-", BBOCB(16,BOT
,CBEQ
,0,1), BBOATCB_MASK
, PPCCOM
, PPCVLE
, {CR
, BDM
}},
4597 {"beql+", BBOCB(16,BOT
,CBEQ
,0,1), BBOATCB_MASK
, PPCCOM
, PPCVLE
, {CR
, BDP
}},
4598 {"beql", BBOCB(16,BOT
,CBEQ
,0,1), BBOATCB_MASK
, COM
, PPCVLE
, {CR
, BD
}},
4599 {"beqa-", BBOCB(16,BOT
,CBEQ
,1,0), BBOATCB_MASK
, PPCCOM
, PPCVLE
, {CR
, BDMA
}},
4600 {"beqa+", BBOCB(16,BOT
,CBEQ
,1,0), BBOATCB_MASK
, PPCCOM
, PPCVLE
, {CR
, BDPA
}},
4601 {"beqa", BBOCB(16,BOT
,CBEQ
,1,0), BBOATCB_MASK
, COM
, PPCVLE
, {CR
, BDA
}},
4602 {"beqla-", BBOCB(16,BOT
,CBEQ
,1,1), BBOATCB_MASK
, PPCCOM
, PPCVLE
, {CR
, BDMA
}},
4603 {"beqla+", BBOCB(16,BOT
,CBEQ
,1,1), BBOATCB_MASK
, PPCCOM
, PPCVLE
, {CR
, BDPA
}},
4604 {"beqla", BBOCB(16,BOT
,CBEQ
,1,1), BBOATCB_MASK
, COM
, PPCVLE
, {CR
, BDA
}},
4605 {"bso-", BBOCB(16,BOT
,CBSO
,0,0), BBOATCB_MASK
, PPCCOM
, PPCVLE
, {CR
, BDM
}},
4606 {"bso+", BBOCB(16,BOT
,CBSO
,0,0), BBOATCB_MASK
, PPCCOM
, PPCVLE
, {CR
, BDP
}},
4607 {"bso", BBOCB(16,BOT
,CBSO
,0,0), BBOATCB_MASK
, COM
, PPCVLE
, {CR
, BD
}},
4608 {"bun-", BBOCB(16,BOT
,CBSO
,0,0), BBOATCB_MASK
, PPCCOM
, PPCVLE
, {CR
, BDM
}},
4609 {"bun+", BBOCB(16,BOT
,CBSO
,0,0), BBOATCB_MASK
, PPCCOM
, PPCVLE
, {CR
, BDP
}},
4610 {"bun", BBOCB(16,BOT
,CBSO
,0,0), BBOATCB_MASK
, PPCCOM
, PPCVLE
, {CR
, BD
}},
4611 {"bsol-", BBOCB(16,BOT
,CBSO
,0,1), BBOATCB_MASK
, PPCCOM
, PPCVLE
, {CR
, BDM
}},
4612 {"bsol+", BBOCB(16,BOT
,CBSO
,0,1), BBOATCB_MASK
, PPCCOM
, PPCVLE
, {CR
, BDP
}},
4613 {"bsol", BBOCB(16,BOT
,CBSO
,0,1), BBOATCB_MASK
, COM
, PPCVLE
, {CR
, BD
}},
4614 {"bunl-", BBOCB(16,BOT
,CBSO
,0,1), BBOATCB_MASK
, PPCCOM
, PPCVLE
, {CR
, BDM
}},
4615 {"bunl+", BBOCB(16,BOT
,CBSO
,0,1), BBOATCB_MASK
, PPCCOM
, PPCVLE
, {CR
, BDP
}},
4616 {"bunl", BBOCB(16,BOT
,CBSO
,0,1), BBOATCB_MASK
, PPCCOM
, PPCVLE
, {CR
, BD
}},
4617 {"bsoa-", BBOCB(16,BOT
,CBSO
,1,0), BBOATCB_MASK
, PPCCOM
, PPCVLE
, {CR
, BDMA
}},
4618 {"bsoa+", BBOCB(16,BOT
,CBSO
,1,0), BBOATCB_MASK
, PPCCOM
, PPCVLE
, {CR
, BDPA
}},
4619 {"bsoa", BBOCB(16,BOT
,CBSO
,1,0), BBOATCB_MASK
, COM
, PPCVLE
, {CR
, BDA
}},
4620 {"buna-", BBOCB(16,BOT
,CBSO
,1,0), BBOATCB_MASK
, PPCCOM
, PPCVLE
, {CR
, BDMA
}},
4621 {"buna+", BBOCB(16,BOT
,CBSO
,1,0), BBOATCB_MASK
, PPCCOM
, PPCVLE
, {CR
, BDPA
}},
4622 {"buna", BBOCB(16,BOT
,CBSO
,1,0), BBOATCB_MASK
, PPCCOM
, PPCVLE
, {CR
, BDA
}},
4623 {"bsola-", BBOCB(16,BOT
,CBSO
,1,1), BBOATCB_MASK
, PPCCOM
, PPCVLE
, {CR
, BDMA
}},
4624 {"bsola+", BBOCB(16,BOT
,CBSO
,1,1), BBOATCB_MASK
, PPCCOM
, PPCVLE
, {CR
, BDPA
}},
4625 {"bsola", BBOCB(16,BOT
,CBSO
,1,1), BBOATCB_MASK
, COM
, PPCVLE
, {CR
, BDA
}},
4626 {"bunla-", BBOCB(16,BOT
,CBSO
,1,1), BBOATCB_MASK
, PPCCOM
, PPCVLE
, {CR
, BDMA
}},
4627 {"bunla+", BBOCB(16,BOT
,CBSO
,1,1), BBOATCB_MASK
, PPCCOM
, PPCVLE
, {CR
, BDPA
}},
4628 {"bunla", BBOCB(16,BOT
,CBSO
,1,1), BBOATCB_MASK
, PPCCOM
, PPCVLE
, {CR
, BDA
}},
4630 {"bdnzf-", BBO(16,BODNZF
,0,0), BBOY_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {BI
, BDM
}},
4631 {"bdnzf+", BBO(16,BODNZF
,0,0), BBOY_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {BI
, BDP
}},
4632 {"bdnzf", BBO(16,BODNZF
,0,0), BBOY_MASK
, PPCCOM
, PPCVLE
, {BI
, BD
}},
4633 {"bdnzfl-", BBO(16,BODNZF
,0,1), BBOY_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {BI
, BDM
}},
4634 {"bdnzfl+", BBO(16,BODNZF
,0,1), BBOY_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {BI
, BDP
}},
4635 {"bdnzfl", BBO(16,BODNZF
,0,1), BBOY_MASK
, PPCCOM
, PPCVLE
, {BI
, BD
}},
4636 {"bdnzfa-", BBO(16,BODNZF
,1,0), BBOY_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {BI
, BDMA
}},
4637 {"bdnzfa+", BBO(16,BODNZF
,1,0), BBOY_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {BI
, BDPA
}},
4638 {"bdnzfa", BBO(16,BODNZF
,1,0), BBOY_MASK
, PPCCOM
, PPCVLE
, {BI
, BDA
}},
4639 {"bdnzfla-", BBO(16,BODNZF
,1,1), BBOY_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {BI
, BDMA
}},
4640 {"bdnzfla+", BBO(16,BODNZF
,1,1), BBOY_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {BI
, BDPA
}},
4641 {"bdnzfla", BBO(16,BODNZF
,1,1), BBOY_MASK
, PPCCOM
, PPCVLE
, {BI
, BDA
}},
4642 {"bdzf-", BBO(16,BODZF
,0,0), BBOY_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {BI
, BDM
}},
4643 {"bdzf+", BBO(16,BODZF
,0,0), BBOY_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {BI
, BDP
}},
4644 {"bdzf", BBO(16,BODZF
,0,0), BBOY_MASK
, PPCCOM
, PPCVLE
, {BI
, BD
}},
4645 {"bdzfl-", BBO(16,BODZF
,0,1), BBOY_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {BI
, BDM
}},
4646 {"bdzfl+", BBO(16,BODZF
,0,1), BBOY_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {BI
, BDP
}},
4647 {"bdzfl", BBO(16,BODZF
,0,1), BBOY_MASK
, PPCCOM
, PPCVLE
, {BI
, BD
}},
4648 {"bdzfa-", BBO(16,BODZF
,1,0), BBOY_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {BI
, BDMA
}},
4649 {"bdzfa+", BBO(16,BODZF
,1,0), BBOY_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {BI
, BDPA
}},
4650 {"bdzfa", BBO(16,BODZF
,1,0), BBOY_MASK
, PPCCOM
, PPCVLE
, {BI
, BDA
}},
4651 {"bdzfla-", BBO(16,BODZF
,1,1), BBOY_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {BI
, BDMA
}},
4652 {"bdzfla+", BBO(16,BODZF
,1,1), BBOY_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {BI
, BDPA
}},
4653 {"bdzfla", BBO(16,BODZF
,1,1), BBOY_MASK
, PPCCOM
, PPCVLE
, {BI
, BDA
}},
4655 {"bf-", BBO(16,BOF
,0,0), BBOAT_MASK
, PPCCOM
, PPCVLE
, {BI
, BDM
}},
4656 {"bf+", BBO(16,BOF
,0,0), BBOAT_MASK
, PPCCOM
, PPCVLE
, {BI
, BDP
}},
4657 {"bf", BBO(16,BOF
,0,0), BBOAT_MASK
, PPCCOM
, PPCVLE
, {BI
, BD
}},
4658 {"bbf", BBO(16,BOF
,0,0), BBOAT_MASK
, PWRCOM
, PPCVLE
, {BI
, BD
}},
4659 {"bfl-", BBO(16,BOF
,0,1), BBOAT_MASK
, PPCCOM
, PPCVLE
, {BI
, BDM
}},
4660 {"bfl+", BBO(16,BOF
,0,1), BBOAT_MASK
, PPCCOM
, PPCVLE
, {BI
, BDP
}},
4661 {"bfl", BBO(16,BOF
,0,1), BBOAT_MASK
, PPCCOM
, PPCVLE
, {BI
, BD
}},
4662 {"bbfl", BBO(16,BOF
,0,1), BBOAT_MASK
, PWRCOM
, PPCVLE
, {BI
, BD
}},
4663 {"bfa-", BBO(16,BOF
,1,0), BBOAT_MASK
, PPCCOM
, PPCVLE
, {BI
, BDMA
}},
4664 {"bfa+", BBO(16,BOF
,1,0), BBOAT_MASK
, PPCCOM
, PPCVLE
, {BI
, BDPA
}},
4665 {"bfa", BBO(16,BOF
,1,0), BBOAT_MASK
, PPCCOM
, PPCVLE
, {BI
, BDA
}},
4666 {"bbfa", BBO(16,BOF
,1,0), BBOAT_MASK
, PWRCOM
, PPCVLE
, {BI
, BDA
}},
4667 {"bfla-", BBO(16,BOF
,1,1), BBOAT_MASK
, PPCCOM
, PPCVLE
, {BI
, BDMA
}},
4668 {"bfla+", BBO(16,BOF
,1,1), BBOAT_MASK
, PPCCOM
, PPCVLE
, {BI
, BDPA
}},
4669 {"bfla", BBO(16,BOF
,1,1), BBOAT_MASK
, PPCCOM
, PPCVLE
, {BI
, BDA
}},
4670 {"bbfla", BBO(16,BOF
,1,1), BBOAT_MASK
, PWRCOM
, PPCVLE
, {BI
, BDA
}},
4672 {"bdnzt-", BBO(16,BODNZT
,0,0), BBOY_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {BI
, BDM
}},
4673 {"bdnzt+", BBO(16,BODNZT
,0,0), BBOY_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {BI
, BDP
}},
4674 {"bdnzt", BBO(16,BODNZT
,0,0), BBOY_MASK
, PPCCOM
, PPCVLE
, {BI
, BD
}},
4675 {"bdnztl-", BBO(16,BODNZT
,0,1), BBOY_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {BI
, BDM
}},
4676 {"bdnztl+", BBO(16,BODNZT
,0,1), BBOY_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {BI
, BDP
}},
4677 {"bdnztl", BBO(16,BODNZT
,0,1), BBOY_MASK
, PPCCOM
, PPCVLE
, {BI
, BD
}},
4678 {"bdnzta-", BBO(16,BODNZT
,1,0), BBOY_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {BI
, BDMA
}},
4679 {"bdnzta+", BBO(16,BODNZT
,1,0), BBOY_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {BI
, BDPA
}},
4680 {"bdnzta", BBO(16,BODNZT
,1,0), BBOY_MASK
, PPCCOM
, PPCVLE
, {BI
, BDA
}},
4681 {"bdnztla-", BBO(16,BODNZT
,1,1), BBOY_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {BI
, BDMA
}},
4682 {"bdnztla+", BBO(16,BODNZT
,1,1), BBOY_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {BI
, BDPA
}},
4683 {"bdnztla", BBO(16,BODNZT
,1,1), BBOY_MASK
, PPCCOM
, PPCVLE
, {BI
, BDA
}},
4684 {"bdzt-", BBO(16,BODZT
,0,0), BBOY_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {BI
, BDM
}},
4685 {"bdzt+", BBO(16,BODZT
,0,0), BBOY_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {BI
, BDP
}},
4686 {"bdzt", BBO(16,BODZT
,0,0), BBOY_MASK
, PPCCOM
, PPCVLE
, {BI
, BD
}},
4687 {"bdztl-", BBO(16,BODZT
,0,1), BBOY_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {BI
, BDM
}},
4688 {"bdztl+", BBO(16,BODZT
,0,1), BBOY_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {BI
, BDP
}},
4689 {"bdztl", BBO(16,BODZT
,0,1), BBOY_MASK
, PPCCOM
, PPCVLE
, {BI
, BD
}},
4690 {"bdzta-", BBO(16,BODZT
,1,0), BBOY_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {BI
, BDMA
}},
4691 {"bdzta+", BBO(16,BODZT
,1,0), BBOY_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {BI
, BDPA
}},
4692 {"bdzta", BBO(16,BODZT
,1,0), BBOY_MASK
, PPCCOM
, PPCVLE
, {BI
, BDA
}},
4693 {"bdztla-", BBO(16,BODZT
,1,1), BBOY_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {BI
, BDMA
}},
4694 {"bdztla+", BBO(16,BODZT
,1,1), BBOY_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {BI
, BDPA
}},
4695 {"bdztla", BBO(16,BODZT
,1,1), BBOY_MASK
, PPCCOM
, PPCVLE
, {BI
, BDA
}},
4697 {"bt-", BBO(16,BOT
,0,0), BBOAT_MASK
, PPCCOM
, PPCVLE
, {BI
, BDM
}},
4698 {"bt+", BBO(16,BOT
,0,0), BBOAT_MASK
, PPCCOM
, PPCVLE
, {BI
, BDP
}},
4699 {"bt", BBO(16,BOT
,0,0), BBOAT_MASK
, PPCCOM
, PPCVLE
, {BI
, BD
}},
4700 {"bbt", BBO(16,BOT
,0,0), BBOAT_MASK
, PWRCOM
, PPCVLE
, {BI
, BD
}},
4701 {"btl-", BBO(16,BOT
,0,1), BBOAT_MASK
, PPCCOM
, PPCVLE
, {BI
, BDM
}},
4702 {"btl+", BBO(16,BOT
,0,1), BBOAT_MASK
, PPCCOM
, PPCVLE
, {BI
, BDP
}},
4703 {"btl", BBO(16,BOT
,0,1), BBOAT_MASK
, PPCCOM
, PPCVLE
, {BI
, BD
}},
4704 {"bbtl", BBO(16,BOT
,0,1), BBOAT_MASK
, PWRCOM
, PPCVLE
, {BI
, BD
}},
4705 {"bta-", BBO(16,BOT
,1,0), BBOAT_MASK
, PPCCOM
, PPCVLE
, {BI
, BDMA
}},
4706 {"bta+", BBO(16,BOT
,1,0), BBOAT_MASK
, PPCCOM
, PPCVLE
, {BI
, BDPA
}},
4707 {"bta", BBO(16,BOT
,1,0), BBOAT_MASK
, PPCCOM
, PPCVLE
, {BI
, BDA
}},
4708 {"bbta", BBO(16,BOT
,1,0), BBOAT_MASK
, PWRCOM
, PPCVLE
, {BI
, BDA
}},
4709 {"btla-", BBO(16,BOT
,1,1), BBOAT_MASK
, PPCCOM
, PPCVLE
, {BI
, BDMA
}},
4710 {"btla+", BBO(16,BOT
,1,1), BBOAT_MASK
, PPCCOM
, PPCVLE
, {BI
, BDPA
}},
4711 {"btla", BBO(16,BOT
,1,1), BBOAT_MASK
, PPCCOM
, PPCVLE
, {BI
, BDA
}},
4712 {"bbtla", BBO(16,BOT
,1,1), BBOAT_MASK
, PWRCOM
, PPCVLE
, {BI
, BDA
}},
4714 {"bc-", B(16,0,0), B_MASK
, PPCCOM
, PPCVLE
, {BOE
, BI
, BDM
}},
4715 {"bc+", B(16,0,0), B_MASK
, PPCCOM
, PPCVLE
, {BOE
, BI
, BDP
}},
4716 {"bc", B(16,0,0), B_MASK
, COM
, PPCVLE
, {BO
, BI
, BD
}},
4717 {"bcl-", B(16,0,1), B_MASK
, PPCCOM
, PPCVLE
, {BOE
, BI
, BDM
}},
4718 {"bcl+", B(16,0,1), B_MASK
, PPCCOM
, PPCVLE
, {BOE
, BI
, BDP
}},
4719 {"bcl", B(16,0,1), B_MASK
, COM
, PPCVLE
, {BO
, BI
, BD
}},
4720 {"bca-", B(16,1,0), B_MASK
, PPCCOM
, PPCVLE
, {BOE
, BI
, BDMA
}},
4721 {"bca+", B(16,1,0), B_MASK
, PPCCOM
, PPCVLE
, {BOE
, BI
, BDPA
}},
4722 {"bca", B(16,1,0), B_MASK
, COM
, PPCVLE
, {BO
, BI
, BDA
}},
4723 {"bcla-", B(16,1,1), B_MASK
, PPCCOM
, PPCVLE
, {BOE
, BI
, BDMA
}},
4724 {"bcla+", B(16,1,1), B_MASK
, PPCCOM
, PPCVLE
, {BOE
, BI
, BDPA
}},
4725 {"bcla", B(16,1,1), B_MASK
, COM
, PPCVLE
, {BO
, BI
, BDA
}},
4727 {"svc", SC(17,0,0), SC_MASK
, POWER
, PPCVLE
, {SVC_LEV
, FL1
, FL2
}},
4728 {"scv", SC(17,0,1), SC_MASK
, POWER9
, PPCVLE
, {SVC_LEV
}},
4729 {"svcl", SC(17,0,1), SC_MASK
, POWER
, PPCVLE
, {SVC_LEV
, FL1
, FL2
}},
4730 {"sc", SC(17,1,0), SC_MASK
, PPC
, PPCVLE
, {LEV
}},
4731 {"svca", SC(17,1,0), SC_MASK
, PWRCOM
, PPCVLE
, {SV
}},
4732 {"svcla", SC(17,1,1), SC_MASK
, POWER
, PPCVLE
, {SV
}},
4734 {"b", B(18,0,0), B_MASK
, COM
, PPCVLE
, {LI
}},
4735 {"bl", B(18,0,1), B_MASK
, COM
, PPCVLE
, {LI
}},
4736 {"ba", B(18,1,0), B_MASK
, COM
, PPCVLE
, {LIA
}},
4737 {"bla", B(18,1,1), B_MASK
, COM
, PPCVLE
, {LIA
}},
4739 {"mcrf", XL(19,0), XLBB_MASK
|(3<<21)|(3<<16), COM
, PPCVLE
, {BF
, BFA
}},
4741 {"lnia", DX(19,2), NODX_MASK
, POWER9
, PPCVLE
, {RT
}},
4742 {"addpcis", DX(19,2), DX_MASK
, POWER9
, PPCVLE
, {RT
, DXD
}},
4743 {"subpcis", DX(19,2), DX_MASK
, POWER9
, PPCVLE
, {RT
, NDXD
}},
4745 {"bdnzlr", XLO(19,BODNZ
,16,0), XLBOBIBB_MASK
, PPCCOM
, PPCVLE
, {0}},
4746 {"bdnzlr-", XLO(19,BODNZ
,16,0), XLBOBIBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {0}},
4747 {"bdnzlrl", XLO(19,BODNZ
,16,1), XLBOBIBB_MASK
, PPCCOM
, PPCVLE
, {0}},
4748 {"bdnzlrl-", XLO(19,BODNZ
,16,1), XLBOBIBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {0}},
4749 {"bdnzlr+", XLO(19,BODNZP
,16,0), XLBOBIBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {0}},
4750 {"bdnzlrl+", XLO(19,BODNZP
,16,1), XLBOBIBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {0}},
4751 {"bdzlr", XLO(19,BODZ
,16,0), XLBOBIBB_MASK
, PPCCOM
, PPCVLE
, {0}},
4752 {"bdzlr-", XLO(19,BODZ
,16,0), XLBOBIBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {0}},
4753 {"bdzlrl", XLO(19,BODZ
,16,1), XLBOBIBB_MASK
, PPCCOM
, PPCVLE
, {0}},
4754 {"bdzlrl-", XLO(19,BODZ
,16,1), XLBOBIBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {0}},
4755 {"bdzlr+", XLO(19,BODZP
,16,0), XLBOBIBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {0}},
4756 {"bdzlrl+", XLO(19,BODZP
,16,1), XLBOBIBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {0}},
4757 {"blr", XLO(19,BOU
,16,0), XLBOBIBB_MASK
, PPCCOM
, PPCVLE
, {0}},
4758 {"br", XLO(19,BOU
,16,0), XLBOBIBB_MASK
, PWRCOM
, PPCVLE
, {0}},
4759 {"blrl", XLO(19,BOU
,16,1), XLBOBIBB_MASK
, PPCCOM
, PPCVLE
, {0}},
4760 {"brl", XLO(19,BOU
,16,1), XLBOBIBB_MASK
, PWRCOM
, PPCVLE
, {0}},
4761 {"bdnzlr-", XLO(19,BODNZM4
,16,0), XLBOBIBB_MASK
, ISA_V2
, PPCVLE
, {0}},
4762 {"bdnzlrl-", XLO(19,BODNZM4
,16,1), XLBOBIBB_MASK
, ISA_V2
, PPCVLE
, {0}},
4763 {"bdnzlr+", XLO(19,BODNZP4
,16,0), XLBOBIBB_MASK
, ISA_V2
, PPCVLE
, {0}},
4764 {"bdnzlrl+", XLO(19,BODNZP4
,16,1), XLBOBIBB_MASK
, ISA_V2
, PPCVLE
, {0}},
4765 {"bdzlr-", XLO(19,BODZM4
,16,0), XLBOBIBB_MASK
, ISA_V2
, PPCVLE
, {0}},
4766 {"bdzlrl-", XLO(19,BODZM4
,16,1), XLBOBIBB_MASK
, ISA_V2
, PPCVLE
, {0}},
4767 {"bdzlr+", XLO(19,BODZP4
,16,0), XLBOBIBB_MASK
, ISA_V2
, PPCVLE
, {0}},
4768 {"bdzlrl+", XLO(19,BODZP4
,16,1), XLBOBIBB_MASK
, ISA_V2
, PPCVLE
, {0}},
4770 {"bgelr", XLOCB(19,BOF
,CBLT
,16,0), XLBOCBBB_MASK
, PPCCOM
, PPCVLE
, {CR
}},
4771 {"bgelr-", XLOCB(19,BOF
,CBLT
,16,0), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {CR
}},
4772 {"bger", XLOCB(19,BOF
,CBLT
,16,0), XLBOCBBB_MASK
, PWRCOM
, PPCVLE
, {CR
}},
4773 {"bnllr", XLOCB(19,BOF
,CBLT
,16,0), XLBOCBBB_MASK
, PPCCOM
, PPCVLE
, {CR
}},
4774 {"bnllr-", XLOCB(19,BOF
,CBLT
,16,0), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {CR
}},
4775 {"bnlr", XLOCB(19,BOF
,CBLT
,16,0), XLBOCBBB_MASK
, PWRCOM
, PPCVLE
, {CR
}},
4776 {"bgelrl", XLOCB(19,BOF
,CBLT
,16,1), XLBOCBBB_MASK
, PPCCOM
, PPCVLE
, {CR
}},
4777 {"bgelrl-", XLOCB(19,BOF
,CBLT
,16,1), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {CR
}},
4778 {"bgerl", XLOCB(19,BOF
,CBLT
,16,1), XLBOCBBB_MASK
, PWRCOM
, PPCVLE
, {CR
}},
4779 {"bnllrl", XLOCB(19,BOF
,CBLT
,16,1), XLBOCBBB_MASK
, PPCCOM
, PPCVLE
, {CR
}},
4780 {"bnllrl-", XLOCB(19,BOF
,CBLT
,16,1), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {CR
}},
4781 {"bnlrl", XLOCB(19,BOF
,CBLT
,16,1), XLBOCBBB_MASK
, PWRCOM
, PPCVLE
, {CR
}},
4782 {"blelr", XLOCB(19,BOF
,CBGT
,16,0), XLBOCBBB_MASK
, PPCCOM
, PPCVLE
, {CR
}},
4783 {"blelr-", XLOCB(19,BOF
,CBGT
,16,0), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {CR
}},
4784 {"bler", XLOCB(19,BOF
,CBGT
,16,0), XLBOCBBB_MASK
, PWRCOM
, PPCVLE
, {CR
}},
4785 {"bnglr", XLOCB(19,BOF
,CBGT
,16,0), XLBOCBBB_MASK
, PPCCOM
, PPCVLE
, {CR
}},
4786 {"bnglr-", XLOCB(19,BOF
,CBGT
,16,0), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {CR
}},
4787 {"bngr", XLOCB(19,BOF
,CBGT
,16,0), XLBOCBBB_MASK
, PWRCOM
, PPCVLE
, {CR
}},
4788 {"blelrl", XLOCB(19,BOF
,CBGT
,16,1), XLBOCBBB_MASK
, PPCCOM
, PPCVLE
, {CR
}},
4789 {"blelrl-", XLOCB(19,BOF
,CBGT
,16,1), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {CR
}},
4790 {"blerl", XLOCB(19,BOF
,CBGT
,16,1), XLBOCBBB_MASK
, PWRCOM
, PPCVLE
, {CR
}},
4791 {"bnglrl", XLOCB(19,BOF
,CBGT
,16,1), XLBOCBBB_MASK
, PPCCOM
, PPCVLE
, {CR
}},
4792 {"bnglrl-", XLOCB(19,BOF
,CBGT
,16,1), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {CR
}},
4793 {"bngrl", XLOCB(19,BOF
,CBGT
,16,1), XLBOCBBB_MASK
, PWRCOM
, PPCVLE
, {CR
}},
4794 {"bnelr", XLOCB(19,BOF
,CBEQ
,16,0), XLBOCBBB_MASK
, PPCCOM
, PPCVLE
, {CR
}},
4795 {"bnelr-", XLOCB(19,BOF
,CBEQ
,16,0), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {CR
}},
4796 {"bner", XLOCB(19,BOF
,CBEQ
,16,0), XLBOCBBB_MASK
, PWRCOM
, PPCVLE
, {CR
}},
4797 {"bnelrl", XLOCB(19,BOF
,CBEQ
,16,1), XLBOCBBB_MASK
, PPCCOM
, PPCVLE
, {CR
}},
4798 {"bnelrl-", XLOCB(19,BOF
,CBEQ
,16,1), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {CR
}},
4799 {"bnerl", XLOCB(19,BOF
,CBEQ
,16,1), XLBOCBBB_MASK
, PWRCOM
, PPCVLE
, {CR
}},
4800 {"bnslr", XLOCB(19,BOF
,CBSO
,16,0), XLBOCBBB_MASK
, PPCCOM
, PPCVLE
, {CR
}},
4801 {"bnslr-", XLOCB(19,BOF
,CBSO
,16,0), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {CR
}},
4802 {"bnsr", XLOCB(19,BOF
,CBSO
,16,0), XLBOCBBB_MASK
, PWRCOM
, PPCVLE
, {CR
}},
4803 {"bnulr", XLOCB(19,BOF
,CBSO
,16,0), XLBOCBBB_MASK
, PPCCOM
, PPCVLE
, {CR
}},
4804 {"bnulr-", XLOCB(19,BOF
,CBSO
,16,0), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {CR
}},
4805 {"bnslrl", XLOCB(19,BOF
,CBSO
,16,1), XLBOCBBB_MASK
, PPCCOM
, PPCVLE
, {CR
}},
4806 {"bnslrl-", XLOCB(19,BOF
,CBSO
,16,1), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {CR
}},
4807 {"bnsrl", XLOCB(19,BOF
,CBSO
,16,1), XLBOCBBB_MASK
, PWRCOM
, PPCVLE
, {CR
}},
4808 {"bnulrl", XLOCB(19,BOF
,CBSO
,16,1), XLBOCBBB_MASK
, PPCCOM
, PPCVLE
, {CR
}},
4809 {"bnulrl-", XLOCB(19,BOF
,CBSO
,16,1), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {CR
}},
4810 {"bgelr+", XLOCB(19,BOFP
,CBLT
,16,0), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {CR
}},
4811 {"bnllr+", XLOCB(19,BOFP
,CBLT
,16,0), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {CR
}},
4812 {"bgelrl+", XLOCB(19,BOFP
,CBLT
,16,1), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {CR
}},
4813 {"bnllrl+", XLOCB(19,BOFP
,CBLT
,16,1), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {CR
}},
4814 {"blelr+", XLOCB(19,BOFP
,CBGT
,16,0), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {CR
}},
4815 {"bnglr+", XLOCB(19,BOFP
,CBGT
,16,0), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {CR
}},
4816 {"blelrl+", XLOCB(19,BOFP
,CBGT
,16,1), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {CR
}},
4817 {"bnglrl+", XLOCB(19,BOFP
,CBGT
,16,1), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {CR
}},
4818 {"bnelr+", XLOCB(19,BOFP
,CBEQ
,16,0), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {CR
}},
4819 {"bnelrl+", XLOCB(19,BOFP
,CBEQ
,16,1), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {CR
}},
4820 {"bnslr+", XLOCB(19,BOFP
,CBSO
,16,0), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {CR
}},
4821 {"bnulr+", XLOCB(19,BOFP
,CBSO
,16,0), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {CR
}},
4822 {"bnslrl+", XLOCB(19,BOFP
,CBSO
,16,1), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {CR
}},
4823 {"bnulrl+", XLOCB(19,BOFP
,CBSO
,16,1), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {CR
}},
4824 {"bgelr-", XLOCB(19,BOFM4
,CBLT
,16,0), XLBOCBBB_MASK
, ISA_V2
, PPCVLE
, {CR
}},
4825 {"bnllr-", XLOCB(19,BOFM4
,CBLT
,16,0), XLBOCBBB_MASK
, ISA_V2
, PPCVLE
, {CR
}},
4826 {"bgelrl-", XLOCB(19,BOFM4
,CBLT
,16,1), XLBOCBBB_MASK
, ISA_V2
, PPCVLE
, {CR
}},
4827 {"bnllrl-", XLOCB(19,BOFM4
,CBLT
,16,1), XLBOCBBB_MASK
, ISA_V2
, PPCVLE
, {CR
}},
4828 {"blelr-", XLOCB(19,BOFM4
,CBGT
,16,0), XLBOCBBB_MASK
, ISA_V2
, PPCVLE
, {CR
}},
4829 {"bnglr-", XLOCB(19,BOFM4
,CBGT
,16,0), XLBOCBBB_MASK
, ISA_V2
, PPCVLE
, {CR
}},
4830 {"blelrl-", XLOCB(19,BOFM4
,CBGT
,16,1), XLBOCBBB_MASK
, ISA_V2
, PPCVLE
, {CR
}},
4831 {"bnglrl-", XLOCB(19,BOFM4
,CBGT
,16,1), XLBOCBBB_MASK
, ISA_V2
, PPCVLE
, {CR
}},
4832 {"bnelr-", XLOCB(19,BOFM4
,CBEQ
,16,0), XLBOCBBB_MASK
, ISA_V2
, PPCVLE
, {CR
}},
4833 {"bnelrl-", XLOCB(19,BOFM4
,CBEQ
,16,1), XLBOCBBB_MASK
, ISA_V2
, PPCVLE
, {CR
}},
4834 {"bnslr-", XLOCB(19,BOFM4
,CBSO
,16,0), XLBOCBBB_MASK
, ISA_V2
, PPCVLE
, {CR
}},
4835 {"bnulr-", XLOCB(19,BOFM4
,CBSO
,16,0), XLBOCBBB_MASK
, ISA_V2
, PPCVLE
, {CR
}},
4836 {"bnslrl-", XLOCB(19,BOFM4
,CBSO
,16,1), XLBOCBBB_MASK
, ISA_V2
, PPCVLE
, {CR
}},
4837 {"bnulrl-", XLOCB(19,BOFM4
,CBSO
,16,1), XLBOCBBB_MASK
, ISA_V2
, PPCVLE
, {CR
}},
4838 {"bgelr+", XLOCB(19,BOFP4
,CBLT
,16,0), XLBOCBBB_MASK
, ISA_V2
, PPCVLE
, {CR
}},
4839 {"bnllr+", XLOCB(19,BOFP4
,CBLT
,16,0), XLBOCBBB_MASK
, ISA_V2
, PPCVLE
, {CR
}},
4840 {"bgelrl+", XLOCB(19,BOFP4
,CBLT
,16,1), XLBOCBBB_MASK
, ISA_V2
, PPCVLE
, {CR
}},
4841 {"bnllrl+", XLOCB(19,BOFP4
,CBLT
,16,1), XLBOCBBB_MASK
, ISA_V2
, PPCVLE
, {CR
}},
4842 {"blelr+", XLOCB(19,BOFP4
,CBGT
,16,0), XLBOCBBB_MASK
, ISA_V2
, PPCVLE
, {CR
}},
4843 {"bnglr+", XLOCB(19,BOFP4
,CBGT
,16,0), XLBOCBBB_MASK
, ISA_V2
, PPCVLE
, {CR
}},
4844 {"blelrl+", XLOCB(19,BOFP4
,CBGT
,16,1), XLBOCBBB_MASK
, ISA_V2
, PPCVLE
, {CR
}},
4845 {"bnglrl+", XLOCB(19,BOFP4
,CBGT
,16,1), XLBOCBBB_MASK
, ISA_V2
, PPCVLE
, {CR
}},
4846 {"bnelr+", XLOCB(19,BOFP4
,CBEQ
,16,0), XLBOCBBB_MASK
, ISA_V2
, PPCVLE
, {CR
}},
4847 {"bnelrl+", XLOCB(19,BOFP4
,CBEQ
,16,1), XLBOCBBB_MASK
, ISA_V2
, PPCVLE
, {CR
}},
4848 {"bnslr+", XLOCB(19,BOFP4
,CBSO
,16,0), XLBOCBBB_MASK
, ISA_V2
, PPCVLE
, {CR
}},
4849 {"bnulr+", XLOCB(19,BOFP4
,CBSO
,16,0), XLBOCBBB_MASK
, ISA_V2
, PPCVLE
, {CR
}},
4850 {"bnslrl+", XLOCB(19,BOFP4
,CBSO
,16,1), XLBOCBBB_MASK
, ISA_V2
, PPCVLE
, {CR
}},
4851 {"bnulrl+", XLOCB(19,BOFP4
,CBSO
,16,1), XLBOCBBB_MASK
, ISA_V2
, PPCVLE
, {CR
}},
4852 {"bltlr", XLOCB(19,BOT
,CBLT
,16,0), XLBOCBBB_MASK
, PPCCOM
, PPCVLE
, {CR
}},
4853 {"bltlr-", XLOCB(19,BOT
,CBLT
,16,0), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {CR
}},
4854 {"bltr", XLOCB(19,BOT
,CBLT
,16,0), XLBOCBBB_MASK
, PWRCOM
, PPCVLE
, {CR
}},
4855 {"bltlrl", XLOCB(19,BOT
,CBLT
,16,1), XLBOCBBB_MASK
, PPCCOM
, PPCVLE
, {CR
}},
4856 {"bltlrl-", XLOCB(19,BOT
,CBLT
,16,1), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {CR
}},
4857 {"bltrl", XLOCB(19,BOT
,CBLT
,16,1), XLBOCBBB_MASK
, PWRCOM
, PPCVLE
, {CR
}},
4858 {"bgtlr", XLOCB(19,BOT
,CBGT
,16,0), XLBOCBBB_MASK
, PPCCOM
, PPCVLE
, {CR
}},
4859 {"bgtlr-", XLOCB(19,BOT
,CBGT
,16,0), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {CR
}},
4860 {"bgtr", XLOCB(19,BOT
,CBGT
,16,0), XLBOCBBB_MASK
, PWRCOM
, PPCVLE
, {CR
}},
4861 {"bgtlrl", XLOCB(19,BOT
,CBGT
,16,1), XLBOCBBB_MASK
, PPCCOM
, PPCVLE
, {CR
}},
4862 {"bgtlrl-", XLOCB(19,BOT
,CBGT
,16,1), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {CR
}},
4863 {"bgtrl", XLOCB(19,BOT
,CBGT
,16,1), XLBOCBBB_MASK
, PWRCOM
, PPCVLE
, {CR
}},
4864 {"beqlr", XLOCB(19,BOT
,CBEQ
,16,0), XLBOCBBB_MASK
, PPCCOM
, PPCVLE
, {CR
}},
4865 {"beqlr-", XLOCB(19,BOT
,CBEQ
,16,0), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {CR
}},
4866 {"beqr", XLOCB(19,BOT
,CBEQ
,16,0), XLBOCBBB_MASK
, PWRCOM
, PPCVLE
, {CR
}},
4867 {"beqlrl", XLOCB(19,BOT
,CBEQ
,16,1), XLBOCBBB_MASK
, PPCCOM
, PPCVLE
, {CR
}},
4868 {"beqlrl-", XLOCB(19,BOT
,CBEQ
,16,1), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {CR
}},
4869 {"beqrl", XLOCB(19,BOT
,CBEQ
,16,1), XLBOCBBB_MASK
, PWRCOM
, PPCVLE
, {CR
}},
4870 {"bsolr", XLOCB(19,BOT
,CBSO
,16,0), XLBOCBBB_MASK
, PPCCOM
, PPCVLE
, {CR
}},
4871 {"bsolr-", XLOCB(19,BOT
,CBSO
,16,0), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {CR
}},
4872 {"bsor", XLOCB(19,BOT
,CBSO
,16,0), XLBOCBBB_MASK
, PWRCOM
, PPCVLE
, {CR
}},
4873 {"bunlr", XLOCB(19,BOT
,CBSO
,16,0), XLBOCBBB_MASK
, PPCCOM
, PPCVLE
, {CR
}},
4874 {"bunlr-", XLOCB(19,BOT
,CBSO
,16,0), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {CR
}},
4875 {"bsolrl", XLOCB(19,BOT
,CBSO
,16,1), XLBOCBBB_MASK
, PPCCOM
, PPCVLE
, {CR
}},
4876 {"bsolrl-", XLOCB(19,BOT
,CBSO
,16,1), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {CR
}},
4877 {"bsorl", XLOCB(19,BOT
,CBSO
,16,1), XLBOCBBB_MASK
, PWRCOM
, PPCVLE
, {CR
}},
4878 {"bunlrl", XLOCB(19,BOT
,CBSO
,16,1), XLBOCBBB_MASK
, PPCCOM
, PPCVLE
, {CR
}},
4879 {"bunlrl-", XLOCB(19,BOT
,CBSO
,16,1), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {CR
}},
4880 {"bltlr+", XLOCB(19,BOTP
,CBLT
,16,0), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {CR
}},
4881 {"bltlrl+", XLOCB(19,BOTP
,CBLT
,16,1), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {CR
}},
4882 {"bgtlr+", XLOCB(19,BOTP
,CBGT
,16,0), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {CR
}},
4883 {"bgtlrl+", XLOCB(19,BOTP
,CBGT
,16,1), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {CR
}},
4884 {"beqlr+", XLOCB(19,BOTP
,CBEQ
,16,0), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {CR
}},
4885 {"beqlrl+", XLOCB(19,BOTP
,CBEQ
,16,1), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {CR
}},
4886 {"bsolr+", XLOCB(19,BOTP
,CBSO
,16,0), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {CR
}},
4887 {"bunlr+", XLOCB(19,BOTP
,CBSO
,16,0), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {CR
}},
4888 {"bsolrl+", XLOCB(19,BOTP
,CBSO
,16,1), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {CR
}},
4889 {"bunlrl+", XLOCB(19,BOTP
,CBSO
,16,1), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {CR
}},
4890 {"bltlr-", XLOCB(19,BOTM4
,CBLT
,16,0), XLBOCBBB_MASK
, ISA_V2
, PPCVLE
, {CR
}},
4891 {"bltlrl-", XLOCB(19,BOTM4
,CBLT
,16,1), XLBOCBBB_MASK
, ISA_V2
, PPCVLE
, {CR
}},
4892 {"bgtlr-", XLOCB(19,BOTM4
,CBGT
,16,0), XLBOCBBB_MASK
, ISA_V2
, PPCVLE
, {CR
}},
4893 {"bgtlrl-", XLOCB(19,BOTM4
,CBGT
,16,1), XLBOCBBB_MASK
, ISA_V2
, PPCVLE
, {CR
}},
4894 {"beqlr-", XLOCB(19,BOTM4
,CBEQ
,16,0), XLBOCBBB_MASK
, ISA_V2
, PPCVLE
, {CR
}},
4895 {"beqlrl-", XLOCB(19,BOTM4
,CBEQ
,16,1), XLBOCBBB_MASK
, ISA_V2
, PPCVLE
, {CR
}},
4896 {"bsolr-", XLOCB(19,BOTM4
,CBSO
,16,0), XLBOCBBB_MASK
, ISA_V2
, PPCVLE
, {CR
}},
4897 {"bunlr-", XLOCB(19,BOTM4
,CBSO
,16,0), XLBOCBBB_MASK
, ISA_V2
, PPCVLE
, {CR
}},
4898 {"bsolrl-", XLOCB(19,BOTM4
,CBSO
,16,1), XLBOCBBB_MASK
, ISA_V2
, PPCVLE
, {CR
}},
4899 {"bunlrl-", XLOCB(19,BOTM4
,CBSO
,16,1), XLBOCBBB_MASK
, ISA_V2
, PPCVLE
, {CR
}},
4900 {"bltlr+", XLOCB(19,BOTP4
,CBLT
,16,0), XLBOCBBB_MASK
, ISA_V2
, PPCVLE
, {CR
}},
4901 {"bltlrl+", XLOCB(19,BOTP4
,CBLT
,16,1), XLBOCBBB_MASK
, ISA_V2
, PPCVLE
, {CR
}},
4902 {"bgtlr+", XLOCB(19,BOTP4
,CBGT
,16,0), XLBOCBBB_MASK
, ISA_V2
, PPCVLE
, {CR
}},
4903 {"bgtlrl+", XLOCB(19,BOTP4
,CBGT
,16,1), XLBOCBBB_MASK
, ISA_V2
, PPCVLE
, {CR
}},
4904 {"beqlr+", XLOCB(19,BOTP4
,CBEQ
,16,0), XLBOCBBB_MASK
, ISA_V2
, PPCVLE
, {CR
}},
4905 {"beqlrl+", XLOCB(19,BOTP4
,CBEQ
,16,1), XLBOCBBB_MASK
, ISA_V2
, PPCVLE
, {CR
}},
4906 {"bsolr+", XLOCB(19,BOTP4
,CBSO
,16,0), XLBOCBBB_MASK
, ISA_V2
, PPCVLE
, {CR
}},
4907 {"bunlr+", XLOCB(19,BOTP4
,CBSO
,16,0), XLBOCBBB_MASK
, ISA_V2
, PPCVLE
, {CR
}},
4908 {"bsolrl+", XLOCB(19,BOTP4
,CBSO
,16,1), XLBOCBBB_MASK
, ISA_V2
, PPCVLE
, {CR
}},
4909 {"bunlrl+", XLOCB(19,BOTP4
,CBSO
,16,1), XLBOCBBB_MASK
, ISA_V2
, PPCVLE
, {CR
}},
4911 {"bdnzflr", XLO(19,BODNZF
,16,0), XLBOBB_MASK
, PPCCOM
, PPCVLE
, {BI
}},
4912 {"bdnzflr-", XLO(19,BODNZF
,16,0), XLBOBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {BI
}},
4913 {"bdnzflrl", XLO(19,BODNZF
,16,1), XLBOBB_MASK
, PPCCOM
, PPCVLE
, {BI
}},
4914 {"bdnzflrl-",XLO(19,BODNZF
,16,1), XLBOBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {BI
}},
4915 {"bdnzflr+", XLO(19,BODNZFP
,16,0), XLBOBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {BI
}},
4916 {"bdnzflrl+",XLO(19,BODNZFP
,16,1), XLBOBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {BI
}},
4917 {"bdzflr", XLO(19,BODZF
,16,0), XLBOBB_MASK
, PPCCOM
, PPCVLE
, {BI
}},
4918 {"bdzflr-", XLO(19,BODZF
,16,0), XLBOBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {BI
}},
4919 {"bdzflrl", XLO(19,BODZF
,16,1), XLBOBB_MASK
, PPCCOM
, PPCVLE
, {BI
}},
4920 {"bdzflrl-", XLO(19,BODZF
,16,1), XLBOBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {BI
}},
4921 {"bdzflr+", XLO(19,BODZFP
,16,0), XLBOBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {BI
}},
4922 {"bdzflrl+", XLO(19,BODZFP
,16,1), XLBOBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {BI
}},
4923 {"bflr", XLO(19,BOF
,16,0), XLBOBB_MASK
, PPCCOM
, PPCVLE
, {BI
}},
4924 {"bflr-", XLO(19,BOF
,16,0), XLBOBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {BI
}},
4925 {"bbfr", XLO(19,BOF
,16,0), XLBOBB_MASK
, PWRCOM
, PPCVLE
, {BI
}},
4926 {"bflrl", XLO(19,BOF
,16,1), XLBOBB_MASK
, PPCCOM
, PPCVLE
, {BI
}},
4927 {"bflrl-", XLO(19,BOF
,16,1), XLBOBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {BI
}},
4928 {"bbfrl", XLO(19,BOF
,16,1), XLBOBB_MASK
, PWRCOM
, PPCVLE
, {BI
}},
4929 {"bflr+", XLO(19,BOFP
,16,0), XLBOBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {BI
}},
4930 {"bflrl+", XLO(19,BOFP
,16,1), XLBOBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {BI
}},
4931 {"bflr-", XLO(19,BOFM4
,16,0), XLBOBB_MASK
, ISA_V2
, PPCVLE
, {BI
}},
4932 {"bflrl-", XLO(19,BOFM4
,16,1), XLBOBB_MASK
, ISA_V2
, PPCVLE
, {BI
}},
4933 {"bflr+", XLO(19,BOFP4
,16,0), XLBOBB_MASK
, ISA_V2
, PPCVLE
, {BI
}},
4934 {"bflrl+", XLO(19,BOFP4
,16,1), XLBOBB_MASK
, ISA_V2
, PPCVLE
, {BI
}},
4935 {"bdnztlr", XLO(19,BODNZT
,16,0), XLBOBB_MASK
, PPCCOM
, PPCVLE
, {BI
}},
4936 {"bdnztlr-", XLO(19,BODNZT
,16,0), XLBOBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {BI
}},
4937 {"bdnztlrl", XLO(19,BODNZT
,16,1), XLBOBB_MASK
, PPCCOM
, PPCVLE
, {BI
}},
4938 {"bdnztlrl-", XLO(19,BODNZT
,16,1), XLBOBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {BI
}},
4939 {"bdnztlr+", XLO(19,BODNZTP
,16,0), XLBOBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {BI
}},
4940 {"bdnztlrl+", XLO(19,BODNZTP
,16,1), XLBOBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {BI
}},
4941 {"bdztlr", XLO(19,BODZT
,16,0), XLBOBB_MASK
, PPCCOM
, PPCVLE
, {BI
}},
4942 {"bdztlr-", XLO(19,BODZT
,16,0), XLBOBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {BI
}},
4943 {"bdztlrl", XLO(19,BODZT
,16,1), XLBOBB_MASK
, PPCCOM
, PPCVLE
, {BI
}},
4944 {"bdztlrl-", XLO(19,BODZT
,16,1), XLBOBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {BI
}},
4945 {"bdztlr+", XLO(19,BODZTP
,16,0), XLBOBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {BI
}},
4946 {"bdztlrl+", XLO(19,BODZTP
,16,1), XLBOBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {BI
}},
4947 {"btlr", XLO(19,BOT
,16,0), XLBOBB_MASK
, PPCCOM
, PPCVLE
, {BI
}},
4948 {"btlr-", XLO(19,BOT
,16,0), XLBOBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {BI
}},
4949 {"bbtr", XLO(19,BOT
,16,0), XLBOBB_MASK
, PWRCOM
, PPCVLE
, {BI
}},
4950 {"btlrl", XLO(19,BOT
,16,1), XLBOBB_MASK
, PPCCOM
, PPCVLE
, {BI
}},
4951 {"btlrl-", XLO(19,BOT
,16,1), XLBOBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {BI
}},
4952 {"bbtrl", XLO(19,BOT
,16,1), XLBOBB_MASK
, PWRCOM
, PPCVLE
, {BI
}},
4953 {"btlr+", XLO(19,BOTP
,16,0), XLBOBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {BI
}},
4954 {"btlrl+", XLO(19,BOTP
,16,1), XLBOBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {BI
}},
4955 {"btlr-", XLO(19,BOTM4
,16,0), XLBOBB_MASK
, ISA_V2
, PPCVLE
, {BI
}},
4956 {"btlrl-", XLO(19,BOTM4
,16,1), XLBOBB_MASK
, ISA_V2
, PPCVLE
, {BI
}},
4957 {"btlr+", XLO(19,BOTP4
,16,0), XLBOBB_MASK
, ISA_V2
, PPCVLE
, {BI
}},
4958 {"btlrl+", XLO(19,BOTP4
,16,1), XLBOBB_MASK
, ISA_V2
, PPCVLE
, {BI
}},
4960 {"bclr-", XLYLK(19,16,0,0), XLYBB_MASK
, PPCCOM
, PPCVLE
, {BOE
, BI
}},
4961 {"bclrl-", XLYLK(19,16,0,1), XLYBB_MASK
, PPCCOM
, PPCVLE
, {BOE
, BI
}},
4962 {"bclr+", XLYLK(19,16,1,0), XLYBB_MASK
, PPCCOM
, PPCVLE
, {BOE
, BI
}},
4963 {"bclrl+", XLYLK(19,16,1,1), XLYBB_MASK
, PPCCOM
, PPCVLE
, {BOE
, BI
}},
4964 {"bclr", XLLK(19,16,0), XLBH_MASK
, PPCCOM
, PPCVLE
, {BO
, BI
, BH
}},
4965 {"bcr", XLLK(19,16,0), XLBB_MASK
, PWRCOM
, PPCVLE
, {BO
, BI
}},
4966 {"bclrl", XLLK(19,16,1), XLBH_MASK
, PPCCOM
, PPCVLE
, {BO
, BI
, BH
}},
4967 {"bcrl", XLLK(19,16,1), XLBB_MASK
, PWRCOM
, PPCVLE
, {BO
, BI
}},
4969 {"rfid", XL(19,18), 0xffffffff, PPC64
, PPCVLE
, {0}},
4971 {"crnot", XL(19,33), XL_MASK
, PPCCOM
, PPCVLE
, {BT
, BAB
}},
4972 {"crnor", XL(19,33), XL_MASK
, COM
, PPCVLE
, {BT
, BA
, BB
}},
4973 {"rfmci", X(19,38), 0xffffffff, PPCRFMCI
|PPCA2
|PPC476
, PPCVLE
, {0}},
4975 {"rfdi", XL(19,39), 0xffffffff, E500MC
, PPCVLE
, {0}},
4976 {"rfi", XL(19,50), 0xffffffff, COM
, PPCVLE
, {0}},
4977 {"rfci", XL(19,51), 0xffffffff, PPC403
|BOOKE
|PPCE300
|PPCA2
|PPC476
, PPCVLE
, {0}},
4979 {"rfscv", XL(19,82), 0xffffffff, POWER9
, PPCVLE
, {0}},
4980 {"rfsvc", XL(19,82), 0xffffffff, POWER
, PPCVLE
, {0}},
4982 {"rfgi", XL(19,102), 0xffffffff, E500MC
|PPCA2
, PPCVLE
, {0}},
4984 {"crandc", XL(19,129), XL_MASK
, COM
, PPCVLE
, {BT
, BA
, BB
}},
4986 {"rfebb", XL(19,146), XLS_MASK
, POWER8
, PPCVLE
, {SXL
}},
4988 {"isync", XL(19,150), 0xffffffff, PPCCOM
, PPCVLE
, {0}},
4989 {"ics", XL(19,150), 0xffffffff, PWRCOM
, PPCVLE
, {0}},
4991 {"crclr", XL(19,193), XL_MASK
, PPCCOM
, PPCVLE
, {BTAB
}},
4992 {"crxor", XL(19,193), XL_MASK
, COM
, PPCVLE
, {BT
, BA
, BB
}},
4994 {"dnh", X(19,198), X_MASK
, E500MC
, PPCVLE
, {DUI
, DUIS
}},
4996 {"crnand", XL(19,225), XL_MASK
, COM
, PPCVLE
, {BT
, BA
, BB
}},
4998 {"crand", XL(19,257), XL_MASK
, COM
, PPCVLE
, {BT
, BA
, BB
}},
5000 {"hrfid", XL(19,274), 0xffffffff, POWER5
|CELL
, PPC476
|PPCVLE
, {0}},
5002 {"crset", XL(19,289), XL_MASK
, PPCCOM
, PPCVLE
, {BTAB
}},
5003 {"creqv", XL(19,289), XL_MASK
, COM
, PPCVLE
, {BT
, BA
, BB
}},
5005 {"urfid", XL(19,306), 0xffffffff, POWER9
, PPCVLE
, {0}},
5006 {"stop", XL(19,370), 0xffffffff, POWER9
, PPCVLE
, {0}},
5008 {"doze", XL(19,402), 0xffffffff, POWER6
, POWER9
|PPCVLE
, {0}},
5010 {"crorc", XL(19,417), XL_MASK
, COM
, PPCVLE
, {BT
, BA
, BB
}},
5012 {"nap", XL(19,434), 0xffffffff, POWER6
, POWER9
|PPCVLE
, {0}},
5014 {"crmove", XL(19,449), XL_MASK
, PPCCOM
, PPCVLE
, {BT
, BAB
}},
5015 {"cror", XL(19,449), XL_MASK
, COM
, PPCVLE
, {BT
, BA
, BB
}},
5017 {"sleep", XL(19,466), 0xffffffff, POWER6
, POWER9
|PPCVLE
, {0}},
5018 {"rvwinkle", XL(19,498), 0xffffffff, POWER6
, POWER9
|PPCVLE
, {0}},
5020 {"bctr", XLO(19,BOU
,528,0), XLBOBIBB_MASK
, COM
, PPCVLE
, {0}},
5021 {"bctrl", XLO(19,BOU
,528,1), XLBOBIBB_MASK
, COM
, PPCVLE
, {0}},
5023 {"bgectr", XLOCB(19,BOF
,CBLT
,528,0), XLBOCBBB_MASK
, PPCCOM
, PPCVLE
, {CR
}},
5024 {"bgectr-", XLOCB(19,BOF
,CBLT
,528,0), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {CR
}},
5025 {"bnlctr", XLOCB(19,BOF
,CBLT
,528,0), XLBOCBBB_MASK
, PPCCOM
, PPCVLE
, {CR
}},
5026 {"bnlctr-", XLOCB(19,BOF
,CBLT
,528,0), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {CR
}},
5027 {"bgectrl", XLOCB(19,BOF
,CBLT
,528,1), XLBOCBBB_MASK
, PPCCOM
, PPCVLE
, {CR
}},
5028 {"bgectrl-",XLOCB(19,BOF
,CBLT
,528,1), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {CR
}},
5029 {"bnlctrl", XLOCB(19,BOF
,CBLT
,528,1), XLBOCBBB_MASK
, PPCCOM
, PPCVLE
, {CR
}},
5030 {"bnlctrl-",XLOCB(19,BOF
,CBLT
,528,1), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {CR
}},
5031 {"blectr", XLOCB(19,BOF
,CBGT
,528,0), XLBOCBBB_MASK
, PPCCOM
, PPCVLE
, {CR
}},
5032 {"blectr-", XLOCB(19,BOF
,CBGT
,528,0), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {CR
}},
5033 {"bngctr", XLOCB(19,BOF
,CBGT
,528,0), XLBOCBBB_MASK
, PPCCOM
, PPCVLE
, {CR
}},
5034 {"bngctr-", XLOCB(19,BOF
,CBGT
,528,0), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {CR
}},
5035 {"blectrl", XLOCB(19,BOF
,CBGT
,528,1), XLBOCBBB_MASK
, PPCCOM
, PPCVLE
, {CR
}},
5036 {"blectrl-",XLOCB(19,BOF
,CBGT
,528,1), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {CR
}},
5037 {"bngctrl", XLOCB(19,BOF
,CBGT
,528,1), XLBOCBBB_MASK
, PPCCOM
, PPCVLE
, {CR
}},
5038 {"bngctrl-",XLOCB(19,BOF
,CBGT
,528,1), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {CR
}},
5039 {"bnectr", XLOCB(19,BOF
,CBEQ
,528,0), XLBOCBBB_MASK
, PPCCOM
, PPCVLE
, {CR
}},
5040 {"bnectr-", XLOCB(19,BOF
,CBEQ
,528,0), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {CR
}},
5041 {"bnectrl", XLOCB(19,BOF
,CBEQ
,528,1), XLBOCBBB_MASK
, PPCCOM
, PPCVLE
, {CR
}},
5042 {"bnectrl-",XLOCB(19,BOF
,CBEQ
,528,1), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {CR
}},
5043 {"bnsctr", XLOCB(19,BOF
,CBSO
,528,0), XLBOCBBB_MASK
, PPCCOM
, PPCVLE
, {CR
}},
5044 {"bnsctr-", XLOCB(19,BOF
,CBSO
,528,0), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {CR
}},
5045 {"bnuctr", XLOCB(19,BOF
,CBSO
,528,0), XLBOCBBB_MASK
, PPCCOM
, PPCVLE
, {CR
}},
5046 {"bnuctr-", XLOCB(19,BOF
,CBSO
,528,0), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {CR
}},
5047 {"bnsctrl", XLOCB(19,BOF
,CBSO
,528,1), XLBOCBBB_MASK
, PPCCOM
, PPCVLE
, {CR
}},
5048 {"bnsctrl-",XLOCB(19,BOF
,CBSO
,528,1), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {CR
}},
5049 {"bnuctrl", XLOCB(19,BOF
,CBSO
,528,1), XLBOCBBB_MASK
, PPCCOM
, PPCVLE
, {CR
}},
5050 {"bnuctrl-",XLOCB(19,BOF
,CBSO
,528,1), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {CR
}},
5051 {"bgectr+", XLOCB(19,BOFP
,CBLT
,528,0), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {CR
}},
5052 {"bnlctr+", XLOCB(19,BOFP
,CBLT
,528,0), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {CR
}},
5053 {"bgectrl+",XLOCB(19,BOFP
,CBLT
,528,1), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {CR
}},
5054 {"bnlctrl+",XLOCB(19,BOFP
,CBLT
,528,1), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {CR
}},
5055 {"blectr+", XLOCB(19,BOFP
,CBGT
,528,0), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {CR
}},
5056 {"bngctr+", XLOCB(19,BOFP
,CBGT
,528,0), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {CR
}},
5057 {"blectrl+",XLOCB(19,BOFP
,CBGT
,528,1), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {CR
}},
5058 {"bngctrl+",XLOCB(19,BOFP
,CBGT
,528,1), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {CR
}},
5059 {"bnectr+", XLOCB(19,BOFP
,CBEQ
,528,0), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {CR
}},
5060 {"bnectrl+",XLOCB(19,BOFP
,CBEQ
,528,1), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {CR
}},
5061 {"bnsctr+", XLOCB(19,BOFP
,CBSO
,528,0), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {CR
}},
5062 {"bnuctr+", XLOCB(19,BOFP
,CBSO
,528,0), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {CR
}},
5063 {"bnsctrl+",XLOCB(19,BOFP
,CBSO
,528,1), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {CR
}},
5064 {"bnuctrl+",XLOCB(19,BOFP
,CBSO
,528,1), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {CR
}},
5065 {"bgectr-", XLOCB(19,BOFM4
,CBLT
,528,0), XLBOCBBB_MASK
, ISA_V2
, PPCVLE
, {CR
}},
5066 {"bnlctr-", XLOCB(19,BOFM4
,CBLT
,528,0), XLBOCBBB_MASK
, ISA_V2
, PPCVLE
, {CR
}},
5067 {"bgectrl-",XLOCB(19,BOFM4
,CBLT
,528,1), XLBOCBBB_MASK
, ISA_V2
, PPCVLE
, {CR
}},
5068 {"bnlctrl-",XLOCB(19,BOFM4
,CBLT
,528,1), XLBOCBBB_MASK
, ISA_V2
, PPCVLE
, {CR
}},
5069 {"blectr-", XLOCB(19,BOFM4
,CBGT
,528,0), XLBOCBBB_MASK
, ISA_V2
, PPCVLE
, {CR
}},
5070 {"bngctr-", XLOCB(19,BOFM4
,CBGT
,528,0), XLBOCBBB_MASK
, ISA_V2
, PPCVLE
, {CR
}},
5071 {"blectrl-",XLOCB(19,BOFM4
,CBGT
,528,1), XLBOCBBB_MASK
, ISA_V2
, PPCVLE
, {CR
}},
5072 {"bngctrl-",XLOCB(19,BOFM4
,CBGT
,528,1), XLBOCBBB_MASK
, ISA_V2
, PPCVLE
, {CR
}},
5073 {"bnectr-", XLOCB(19,BOFM4
,CBEQ
,528,0), XLBOCBBB_MASK
, ISA_V2
, PPCVLE
, {CR
}},
5074 {"bnectrl-",XLOCB(19,BOFM4
,CBEQ
,528,1), XLBOCBBB_MASK
, ISA_V2
, PPCVLE
, {CR
}},
5075 {"bnsctr-", XLOCB(19,BOFM4
,CBSO
,528,0), XLBOCBBB_MASK
, ISA_V2
, PPCVLE
, {CR
}},
5076 {"bnuctr-", XLOCB(19,BOFM4
,CBSO
,528,0), XLBOCBBB_MASK
, ISA_V2
, PPCVLE
, {CR
}},
5077 {"bnsctrl-",XLOCB(19,BOFM4
,CBSO
,528,1), XLBOCBBB_MASK
, ISA_V2
, PPCVLE
, {CR
}},
5078 {"bnuctrl-",XLOCB(19,BOFM4
,CBSO
,528,1), XLBOCBBB_MASK
, ISA_V2
, PPCVLE
, {CR
}},
5079 {"bgectr+", XLOCB(19,BOFP4
,CBLT
,528,0), XLBOCBBB_MASK
, ISA_V2
, PPCVLE
, {CR
}},
5080 {"bnlctr+", XLOCB(19,BOFP4
,CBLT
,528,0), XLBOCBBB_MASK
, ISA_V2
, PPCVLE
, {CR
}},
5081 {"bgectrl+",XLOCB(19,BOFP4
,CBLT
,528,1), XLBOCBBB_MASK
, ISA_V2
, PPCVLE
, {CR
}},
5082 {"bnlctrl+",XLOCB(19,BOFP4
,CBLT
,528,1), XLBOCBBB_MASK
, ISA_V2
, PPCVLE
, {CR
}},
5083 {"blectr+", XLOCB(19,BOFP4
,CBGT
,528,0), XLBOCBBB_MASK
, ISA_V2
, PPCVLE
, {CR
}},
5084 {"bngctr+", XLOCB(19,BOFP4
,CBGT
,528,0), XLBOCBBB_MASK
, ISA_V2
, PPCVLE
, {CR
}},
5085 {"blectrl+",XLOCB(19,BOFP4
,CBGT
,528,1), XLBOCBBB_MASK
, ISA_V2
, PPCVLE
, {CR
}},
5086 {"bngctrl+",XLOCB(19,BOFP4
,CBGT
,528,1), XLBOCBBB_MASK
, ISA_V2
, PPCVLE
, {CR
}},
5087 {"bnectr+", XLOCB(19,BOFP4
,CBEQ
,528,0), XLBOCBBB_MASK
, ISA_V2
, PPCVLE
, {CR
}},
5088 {"bnectrl+",XLOCB(19,BOFP4
,CBEQ
,528,1), XLBOCBBB_MASK
, ISA_V2
, PPCVLE
, {CR
}},
5089 {"bnsctr+", XLOCB(19,BOFP4
,CBSO
,528,0), XLBOCBBB_MASK
, ISA_V2
, PPCVLE
, {CR
}},
5090 {"bnuctr+", XLOCB(19,BOFP4
,CBSO
,528,0), XLBOCBBB_MASK
, ISA_V2
, PPCVLE
, {CR
}},
5091 {"bnsctrl+",XLOCB(19,BOFP4
,CBSO
,528,1), XLBOCBBB_MASK
, ISA_V2
, PPCVLE
, {CR
}},
5092 {"bnuctrl+",XLOCB(19,BOFP4
,CBSO
,528,1), XLBOCBBB_MASK
, ISA_V2
, PPCVLE
, {CR
}},
5093 {"bltctr", XLOCB(19,BOT
,CBLT
,528,0), XLBOCBBB_MASK
, PPCCOM
, PPCVLE
, {CR
}},
5094 {"bltctr-", XLOCB(19,BOT
,CBLT
,528,0), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {CR
}},
5095 {"bltctrl", XLOCB(19,BOT
,CBLT
,528,1), XLBOCBBB_MASK
, PPCCOM
, PPCVLE
, {CR
}},
5096 {"bltctrl-",XLOCB(19,BOT
,CBLT
,528,1), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {CR
}},
5097 {"bgtctr", XLOCB(19,BOT
,CBGT
,528,0), XLBOCBBB_MASK
, PPCCOM
, PPCVLE
, {CR
}},
5098 {"bgtctr-", XLOCB(19,BOT
,CBGT
,528,0), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {CR
}},
5099 {"bgtctrl", XLOCB(19,BOT
,CBGT
,528,1), XLBOCBBB_MASK
, PPCCOM
, PPCVLE
, {CR
}},
5100 {"bgtctrl-",XLOCB(19,BOT
,CBGT
,528,1), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {CR
}},
5101 {"beqctr", XLOCB(19,BOT
,CBEQ
,528,0), XLBOCBBB_MASK
, PPCCOM
, PPCVLE
, {CR
}},
5102 {"beqctr-", XLOCB(19,BOT
,CBEQ
,528,0), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {CR
}},
5103 {"beqctrl", XLOCB(19,BOT
,CBEQ
,528,1), XLBOCBBB_MASK
, PPCCOM
, PPCVLE
, {CR
}},
5104 {"beqctrl-",XLOCB(19,BOT
,CBEQ
,528,1), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {CR
}},
5105 {"bsoctr", XLOCB(19,BOT
,CBSO
,528,0), XLBOCBBB_MASK
, PPCCOM
, PPCVLE
, {CR
}},
5106 {"bsoctr-", XLOCB(19,BOT
,CBSO
,528,0), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {CR
}},
5107 {"bunctr", XLOCB(19,BOT
,CBSO
,528,0), XLBOCBBB_MASK
, PPCCOM
, PPCVLE
, {CR
}},
5108 {"bunctr-", XLOCB(19,BOT
,CBSO
,528,0), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {CR
}},
5109 {"bsoctrl", XLOCB(19,BOT
,CBSO
,528,1), XLBOCBBB_MASK
, PPCCOM
, PPCVLE
, {CR
}},
5110 {"bsoctrl-",XLOCB(19,BOT
,CBSO
,528,1), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {CR
}},
5111 {"bunctrl", XLOCB(19,BOT
,CBSO
,528,1), XLBOCBBB_MASK
, PPCCOM
, PPCVLE
, {CR
}},
5112 {"bunctrl-",XLOCB(19,BOT
,CBSO
,528,1), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {CR
}},
5113 {"bltctr+", XLOCB(19,BOTP
,CBLT
,528,0), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {CR
}},
5114 {"bltctrl+",XLOCB(19,BOTP
,CBLT
,528,1), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {CR
}},
5115 {"bgtctr+", XLOCB(19,BOTP
,CBGT
,528,0), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {CR
}},
5116 {"bgtctrl+",XLOCB(19,BOTP
,CBGT
,528,1), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {CR
}},
5117 {"beqctr+", XLOCB(19,BOTP
,CBEQ
,528,0), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {CR
}},
5118 {"beqctrl+",XLOCB(19,BOTP
,CBEQ
,528,1), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {CR
}},
5119 {"bsoctr+", XLOCB(19,BOTP
,CBSO
,528,0), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {CR
}},
5120 {"bunctr+", XLOCB(19,BOTP
,CBSO
,528,0), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {CR
}},
5121 {"bsoctrl+",XLOCB(19,BOTP
,CBSO
,528,1), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {CR
}},
5122 {"bunctrl+",XLOCB(19,BOTP
,CBSO
,528,1), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {CR
}},
5123 {"bltctr-", XLOCB(19,BOTM4
,CBLT
,528,0), XLBOCBBB_MASK
, ISA_V2
, PPCVLE
, {CR
}},
5124 {"bltctrl-",XLOCB(19,BOTM4
,CBLT
,528,1), XLBOCBBB_MASK
, ISA_V2
, PPCVLE
, {CR
}},
5125 {"bgtctr-", XLOCB(19,BOTM4
,CBGT
,528,0), XLBOCBBB_MASK
, ISA_V2
, PPCVLE
, {CR
}},
5126 {"bgtctrl-",XLOCB(19,BOTM4
,CBGT
,528,1), XLBOCBBB_MASK
, ISA_V2
, PPCVLE
, {CR
}},
5127 {"beqctr-", XLOCB(19,BOTM4
,CBEQ
,528,0), XLBOCBBB_MASK
, ISA_V2
, PPCVLE
, {CR
}},
5128 {"beqctrl-",XLOCB(19,BOTM4
,CBEQ
,528,1), XLBOCBBB_MASK
, ISA_V2
, PPCVLE
, {CR
}},
5129 {"bsoctr-", XLOCB(19,BOTM4
,CBSO
,528,0), XLBOCBBB_MASK
, ISA_V2
, PPCVLE
, {CR
}},
5130 {"bunctr-", XLOCB(19,BOTM4
,CBSO
,528,0), XLBOCBBB_MASK
, ISA_V2
, PPCVLE
, {CR
}},
5131 {"bsoctrl-",XLOCB(19,BOTM4
,CBSO
,528,1), XLBOCBBB_MASK
, ISA_V2
, PPCVLE
, {CR
}},
5132 {"bunctrl-",XLOCB(19,BOTM4
,CBSO
,528,1), XLBOCBBB_MASK
, ISA_V2
, PPCVLE
, {CR
}},
5133 {"bltctr+", XLOCB(19,BOTP4
,CBLT
,528,0), XLBOCBBB_MASK
, ISA_V2
, PPCVLE
, {CR
}},
5134 {"bltctrl+",XLOCB(19,BOTP4
,CBLT
,528,1), XLBOCBBB_MASK
, ISA_V2
, PPCVLE
, {CR
}},
5135 {"bgtctr+", XLOCB(19,BOTP4
,CBGT
,528,0), XLBOCBBB_MASK
, ISA_V2
, PPCVLE
, {CR
}},
5136 {"bgtctrl+",XLOCB(19,BOTP4
,CBGT
,528,1), XLBOCBBB_MASK
, ISA_V2
, PPCVLE
, {CR
}},
5137 {"beqctr+", XLOCB(19,BOTP4
,CBEQ
,528,0), XLBOCBBB_MASK
, ISA_V2
, PPCVLE
, {CR
}},
5138 {"beqctrl+",XLOCB(19,BOTP4
,CBEQ
,528,1), XLBOCBBB_MASK
, ISA_V2
, PPCVLE
, {CR
}},
5139 {"bsoctr+", XLOCB(19,BOTP4
,CBSO
,528,0), XLBOCBBB_MASK
, ISA_V2
, PPCVLE
, {CR
}},
5140 {"bunctr+", XLOCB(19,BOTP4
,CBSO
,528,0), XLBOCBBB_MASK
, ISA_V2
, PPCVLE
, {CR
}},
5141 {"bsoctrl+",XLOCB(19,BOTP4
,CBSO
,528,1), XLBOCBBB_MASK
, ISA_V2
, PPCVLE
, {CR
}},
5142 {"bunctrl+",XLOCB(19,BOTP4
,CBSO
,528,1), XLBOCBBB_MASK
, ISA_V2
, PPCVLE
, {CR
}},
5144 {"bfctr", XLO(19,BOF
,528,0), XLBOBB_MASK
, PPCCOM
, PPCVLE
, {BI
}},
5145 {"bfctr-", XLO(19,BOF
,528,0), XLBOBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {BI
}},
5146 {"bfctrl", XLO(19,BOF
,528,1), XLBOBB_MASK
, PPCCOM
, PPCVLE
, {BI
}},
5147 {"bfctrl-", XLO(19,BOF
,528,1), XLBOBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {BI
}},
5148 {"bfctr+", XLO(19,BOFP
,528,0), XLBOBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {BI
}},
5149 {"bfctrl+", XLO(19,BOFP
,528,1), XLBOBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {BI
}},
5150 {"bfctr-", XLO(19,BOFM4
,528,0), XLBOBB_MASK
, ISA_V2
, PPCVLE
, {BI
}},
5151 {"bfctrl-", XLO(19,BOFM4
,528,1), XLBOBB_MASK
, ISA_V2
, PPCVLE
, {BI
}},
5152 {"bfctr+", XLO(19,BOFP4
,528,0), XLBOBB_MASK
, ISA_V2
, PPCVLE
, {BI
}},
5153 {"bfctrl+", XLO(19,BOFP4
,528,1), XLBOBB_MASK
, ISA_V2
, PPCVLE
, {BI
}},
5154 {"btctr", XLO(19,BOT
,528,0), XLBOBB_MASK
, PPCCOM
, PPCVLE
, {BI
}},
5155 {"btctr-", XLO(19,BOT
,528,0), XLBOBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {BI
}},
5156 {"btctrl", XLO(19,BOT
,528,1), XLBOBB_MASK
, PPCCOM
, PPCVLE
, {BI
}},
5157 {"btctrl-", XLO(19,BOT
,528,1), XLBOBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {BI
}},
5158 {"btctr+", XLO(19,BOTP
,528,0), XLBOBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {BI
}},
5159 {"btctrl+", XLO(19,BOTP
,528,1), XLBOBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {BI
}},
5160 {"btctr-", XLO(19,BOTM4
,528,0), XLBOBB_MASK
, ISA_V2
, PPCVLE
, {BI
}},
5161 {"btctrl-", XLO(19,BOTM4
,528,1), XLBOBB_MASK
, ISA_V2
, PPCVLE
, {BI
}},
5162 {"btctr+", XLO(19,BOTP4
,528,0), XLBOBB_MASK
, ISA_V2
, PPCVLE
, {BI
}},
5163 {"btctrl+", XLO(19,BOTP4
,528,1), XLBOBB_MASK
, ISA_V2
, PPCVLE
, {BI
}},
5165 {"bcctr-", XLYLK(19,528,0,0), XLYBB_MASK
, PPCCOM
, PPCVLE
, {BOE
, BI
}},
5166 {"bcctrl-", XLYLK(19,528,0,1), XLYBB_MASK
, PPCCOM
, PPCVLE
, {BOE
, BI
}},
5167 {"bcctr+", XLYLK(19,528,1,0), XLYBB_MASK
, PPCCOM
, PPCVLE
, {BOE
, BI
}},
5168 {"bcctrl+", XLYLK(19,528,1,1), XLYBB_MASK
, PPCCOM
, PPCVLE
, {BOE
, BI
}},
5169 {"bcctr", XLLK(19,528,0), XLBH_MASK
, PPCCOM
, PPCVLE
, {BO
, BI
, BH
}},
5170 {"bcc", XLLK(19,528,0), XLBB_MASK
, PWRCOM
, PPCVLE
, {BO
, BI
}},
5171 {"bcctrl", XLLK(19,528,1), XLBH_MASK
, PPCCOM
, PPCVLE
, {BO
, BI
, BH
}},
5172 {"bccl", XLLK(19,528,1), XLBB_MASK
, PWRCOM
, PPCVLE
, {BO
, BI
}},
5174 {"bctar-", XLYLK(19,560,0,0), XLYBB_MASK
, POWER8
, PPCVLE
, {BOE
, BI
}},
5175 {"bctarl-", XLYLK(19,560,0,1), XLYBB_MASK
, POWER8
, PPCVLE
, {BOE
, BI
}},
5176 {"bctar+", XLYLK(19,560,1,0), XLYBB_MASK
, POWER8
, PPCVLE
, {BOE
, BI
}},
5177 {"bctarl+", XLYLK(19,560,1,1), XLYBB_MASK
, POWER8
, PPCVLE
, {BOE
, BI
}},
5178 {"bctar", XLLK(19,560,0), XLBH_MASK
, POWER8
, PPCVLE
, {BO
, BI
, BH
}},
5179 {"bctarl", XLLK(19,560,1), XLBH_MASK
, POWER8
, PPCVLE
, {BO
, BI
, BH
}},
5181 {"rlwimi", M(20,0), M_MASK
, PPCCOM
, PPCVLE
, {RA
, RS
, SH
, MBE
, ME
}},
5182 {"rlimi", M(20,0), M_MASK
, PWRCOM
, PPCVLE
, {RA
, RS
, SH
, MBE
, ME
}},
5184 {"rlwimi.", M(20,1), M_MASK
, PPCCOM
, PPCVLE
, {RA
, RS
, SH
, MBE
, ME
}},
5185 {"rlimi.", M(20,1), M_MASK
, PWRCOM
, PPCVLE
, {RA
, RS
, SH
, MBE
, ME
}},
5187 {"rotlwi", MME(21,31,0), MMBME_MASK
, PPCCOM
, PPCVLE
, {RA
, RS
, SH
}},
5188 {"clrlwi", MME(21,31,0), MSHME_MASK
, PPCCOM
, PPCVLE
, {RA
, RS
, MB
}},
5189 {"rlwinm", M(21,0), M_MASK
, PPCCOM
, PPCVLE
, {RA
, RS
, SH
, MBE
, ME
}},
5190 {"rlinm", M(21,0), M_MASK
, PWRCOM
, PPCVLE
, {RA
, RS
, SH
, MBE
, ME
}},
5191 {"rotlwi.", MME(21,31,1), MMBME_MASK
, PPCCOM
, PPCVLE
, {RA
, RS
, SH
}},
5192 {"clrlwi.", MME(21,31,1), MSHME_MASK
, PPCCOM
, PPCVLE
, {RA
, RS
, MB
}},
5193 {"rlwinm.", M(21,1), M_MASK
, PPCCOM
, PPCVLE
, {RA
, RS
, SH
, MBE
, ME
}},
5194 {"rlinm.", M(21,1), M_MASK
, PWRCOM
, PPCVLE
, {RA
, RS
, SH
, MBE
, ME
}},
5196 {"rlmi", M(22,0), M_MASK
, M601
, PPCVLE
, {RA
, RS
, RB
, MBE
, ME
}},
5197 {"rlmi.", M(22,1), M_MASK
, M601
, PPCVLE
, {RA
, RS
, RB
, MBE
, ME
}},
5199 {"rotlw", MME(23,31,0), MMBME_MASK
, PPCCOM
, PPCVLE
, {RA
, RS
, RB
}},
5200 {"rlwnm", M(23,0), M_MASK
, PPCCOM
, PPCVLE
, {RA
, RS
, RB
, MBE
, ME
}},
5201 {"rlnm", M(23,0), M_MASK
, PWRCOM
, PPCVLE
, {RA
, RS
, RB
, MBE
, ME
}},
5202 {"rotlw.", MME(23,31,1), MMBME_MASK
, PPCCOM
, PPCVLE
, {RA
, RS
, RB
}},
5203 {"rlwnm.", M(23,1), M_MASK
, PPCCOM
, PPCVLE
, {RA
, RS
, RB
, MBE
, ME
}},
5204 {"rlnm.", M(23,1), M_MASK
, PWRCOM
, PPCVLE
, {RA
, RS
, RB
, MBE
, ME
}},
5206 {"nop", OP(24), 0xffffffff, PPCCOM
, PPCVLE
, {0}},
5207 {"ori", OP(24), OP_MASK
, PPCCOM
, PPCVLE
, {RA
, RS
, UI
}},
5208 {"oril", OP(24), OP_MASK
, PWRCOM
, PPCVLE
, {RA
, RS
, UI
}},
5210 {"oris", OP(25), OP_MASK
, PPCCOM
, PPCVLE
, {RA
, RS
, UI
}},
5211 {"oriu", OP(25), OP_MASK
, PWRCOM
, PPCVLE
, {RA
, RS
, UI
}},
5213 {"xnop", OP(26), 0xffffffff, PPCCOM
, PPCVLE
, {0}},
5214 {"xori", OP(26), OP_MASK
, PPCCOM
, PPCVLE
, {RA
, RS
, UI
}},
5215 {"xoril", OP(26), OP_MASK
, PWRCOM
, PPCVLE
, {RA
, RS
, UI
}},
5217 {"xoris", OP(27), OP_MASK
, PPCCOM
, PPCVLE
, {RA
, RS
, UI
}},
5218 {"xoriu", OP(27), OP_MASK
, PWRCOM
, PPCVLE
, {RA
, RS
, UI
}},
5220 {"andi.", OP(28), OP_MASK
, PPCCOM
, PPCVLE
, {RA
, RS
, UI
}},
5221 {"andil.", OP(28), OP_MASK
, PWRCOM
, PPCVLE
, {RA
, RS
, UI
}},
5223 {"andis.", OP(29), OP_MASK
, PPCCOM
, PPCVLE
, {RA
, RS
, UI
}},
5224 {"andiu.", OP(29), OP_MASK
, PWRCOM
, PPCVLE
, {RA
, RS
, UI
}},
5226 {"rotldi", MD(30,0,0), MDMB_MASK
, PPC64
, PPCVLE
, {RA
, RS
, SH6
}},
5227 {"clrldi", MD(30,0,0), MDSH_MASK
, PPC64
, PPCVLE
, {RA
, RS
, MB6
}},
5228 {"rldicl", MD(30,0,0), MD_MASK
, PPC64
, PPCVLE
, {RA
, RS
, SH6
, MB6
}},
5229 {"rotldi.", MD(30,0,1), MDMB_MASK
, PPC64
, PPCVLE
, {RA
, RS
, SH6
}},
5230 {"clrldi.", MD(30,0,1), MDSH_MASK
, PPC64
, PPCVLE
, {RA
, RS
, MB6
}},
5231 {"rldicl.", MD(30,0,1), MD_MASK
, PPC64
, PPCVLE
, {RA
, RS
, SH6
, MB6
}},
5233 {"rldicr", MD(30,1,0), MD_MASK
, PPC64
, PPCVLE
, {RA
, RS
, SH6
, ME6
}},
5234 {"rldicr.", MD(30,1,1), MD_MASK
, PPC64
, PPCVLE
, {RA
, RS
, SH6
, ME6
}},
5236 {"rldic", MD(30,2,0), MD_MASK
, PPC64
, PPCVLE
, {RA
, RS
, SH6
, MB6
}},
5237 {"rldic.", MD(30,2,1), MD_MASK
, PPC64
, PPCVLE
, {RA
, RS
, SH6
, MB6
}},
5239 {"rldimi", MD(30,3,0), MD_MASK
, PPC64
, PPCVLE
, {RA
, RS
, SH6
, MB6
}},
5240 {"rldimi.", MD(30,3,1), MD_MASK
, PPC64
, PPCVLE
, {RA
, RS
, SH6
, MB6
}},
5242 {"rotld", MDS(30,8,0), MDSMB_MASK
, PPC64
, PPCVLE
, {RA
, RS
, RB
}},
5243 {"rldcl", MDS(30,8,0), MDS_MASK
, PPC64
, PPCVLE
, {RA
, RS
, RB
, MB6
}},
5244 {"rotld.", MDS(30,8,1), MDSMB_MASK
, PPC64
, PPCVLE
, {RA
, RS
, RB
}},
5245 {"rldcl.", MDS(30,8,1), MDS_MASK
, PPC64
, PPCVLE
, {RA
, RS
, RB
, MB6
}},
5247 {"rldcr", MDS(30,9,0), MDS_MASK
, PPC64
, PPCVLE
, {RA
, RS
, RB
, ME6
}},
5248 {"rldcr.", MDS(30,9,1), MDS_MASK
, PPC64
, PPCVLE
, {RA
, RS
, RB
, ME6
}},
5250 {"cmpw", XOPL(31,0,0), XCMPL_MASK
, PPCCOM
, 0, {OBF
, RA
, RB
}},
5251 {"cmpd", XOPL(31,0,1), XCMPL_MASK
, PPC64
, 0, {OBF
, RA
, RB
}},
5252 {"cmp", X(31,0), XCMP_MASK
, PPC
, 0, {BF
, L32OPT
, RA
, RB
}},
5253 {"cmp", X(31,0), XCMPL_MASK
, PWRCOM
, PPC
, {BF
, RA
, RB
}},
5255 {"twlgt", XTO(31,4,TOLGT
), XTO_MASK
, PPCCOM
, 0, {RA
, RB
}},
5256 {"tlgt", XTO(31,4,TOLGT
), XTO_MASK
, PWRCOM
, 0, {RA
, RB
}},
5257 {"twllt", XTO(31,4,TOLLT
), XTO_MASK
, PPCCOM
, 0, {RA
, RB
}},
5258 {"tllt", XTO(31,4,TOLLT
), XTO_MASK
, PWRCOM
, 0, {RA
, RB
}},
5259 {"tweq", XTO(31,4,TOEQ
), XTO_MASK
, PPCCOM
, 0, {RA
, RB
}},
5260 {"teq", XTO(31,4,TOEQ
), XTO_MASK
, PWRCOM
, 0, {RA
, RB
}},
5261 {"twlge", XTO(31,4,TOLGE
), XTO_MASK
, PPCCOM
, 0, {RA
, RB
}},
5262 {"tlge", XTO(31,4,TOLGE
), XTO_MASK
, PWRCOM
, 0, {RA
, RB
}},
5263 {"twlnl", XTO(31,4,TOLNL
), XTO_MASK
, PPCCOM
, 0, {RA
, RB
}},
5264 {"tlnl", XTO(31,4,TOLNL
), XTO_MASK
, PWRCOM
, 0, {RA
, RB
}},
5265 {"twlle", XTO(31,4,TOLLE
), XTO_MASK
, PPCCOM
, 0, {RA
, RB
}},
5266 {"tlle", XTO(31,4,TOLLE
), XTO_MASK
, PWRCOM
, 0, {RA
, RB
}},
5267 {"twlng", XTO(31,4,TOLNG
), XTO_MASK
, PPCCOM
, 0, {RA
, RB
}},
5268 {"tlng", XTO(31,4,TOLNG
), XTO_MASK
, PWRCOM
, 0, {RA
, RB
}},
5269 {"twgt", XTO(31,4,TOGT
), XTO_MASK
, PPCCOM
, 0, {RA
, RB
}},
5270 {"tgt", XTO(31,4,TOGT
), XTO_MASK
, PWRCOM
, 0, {RA
, RB
}},
5271 {"twge", XTO(31,4,TOGE
), XTO_MASK
, PPCCOM
, 0, {RA
, RB
}},
5272 {"tge", XTO(31,4,TOGE
), XTO_MASK
, PWRCOM
, 0, {RA
, RB
}},
5273 {"twnl", XTO(31,4,TONL
), XTO_MASK
, PPCCOM
, 0, {RA
, RB
}},
5274 {"tnl", XTO(31,4,TONL
), XTO_MASK
, PWRCOM
, 0, {RA
, RB
}},
5275 {"twlt", XTO(31,4,TOLT
), XTO_MASK
, PPCCOM
, 0, {RA
, RB
}},
5276 {"tlt", XTO(31,4,TOLT
), XTO_MASK
, PWRCOM
, 0, {RA
, RB
}},
5277 {"twle", XTO(31,4,TOLE
), XTO_MASK
, PPCCOM
, 0, {RA
, RB
}},
5278 {"tle", XTO(31,4,TOLE
), XTO_MASK
, PWRCOM
, 0, {RA
, RB
}},
5279 {"twng", XTO(31,4,TONG
), XTO_MASK
, PPCCOM
, 0, {RA
, RB
}},
5280 {"tng", XTO(31,4,TONG
), XTO_MASK
, PWRCOM
, 0, {RA
, RB
}},
5281 {"twne", XTO(31,4,TONE
), XTO_MASK
, PPCCOM
, 0, {RA
, RB
}},
5282 {"tne", XTO(31,4,TONE
), XTO_MASK
, PWRCOM
, 0, {RA
, RB
}},
5283 {"trap", XTO(31,4,TOU
), 0xffffffff, PPCCOM
, 0, {0}},
5284 {"twu", XTO(31,4,TOU
), XTO_MASK
, PPCCOM
, 0, {RA
, RB
}},
5285 {"tu", XTO(31,4,TOU
), XTO_MASK
, PWRCOM
, 0, {RA
, RB
}},
5286 {"tw", X(31,4), X_MASK
, PPCCOM
, 0, {TO
, RA
, RB
}},
5287 {"t", X(31,4), X_MASK
, PWRCOM
, 0, {TO
, RA
, RB
}},
5289 {"lvsl", X(31,6), X_MASK
, PPCVEC
, 0, {VD
, RA0
, RB
}},
5290 {"lvebx", X(31,7), X_MASK
, PPCVEC
, 0, {VD
, RA0
, RB
}},
5291 {"lbfcmx", APU(31,7,0), APU_MASK
, PPC405
, 0, {FCRT
, RA
, RB
}},
5293 {"subfc", XO(31,8,0,0), XO_MASK
, PPCCOM
, 0, {RT
, RA
, RB
}},
5294 {"sf", XO(31,8,0,0), XO_MASK
, PWRCOM
, 0, {RT
, RA
, RB
}},
5295 {"subc", XO(31,8,0,0), XO_MASK
, PPCCOM
, 0, {RT
, RB
, RA
}},
5296 {"subfc.", XO(31,8,0,1), XO_MASK
, PPCCOM
, 0, {RT
, RA
, RB
}},
5297 {"sf.", XO(31,8,0,1), XO_MASK
, PWRCOM
, 0, {RT
, RA
, RB
}},
5298 {"subc.", XO(31,8,0,1), XO_MASK
, PPCCOM
, 0, {RT
, RB
, RA
}},
5300 {"mulhdu", XO(31,9,0,0), XO_MASK
, PPC64
, 0, {RT
, RA
, RB
}},
5301 {"mulhdu.", XO(31,9,0,1), XO_MASK
, PPC64
, 0, {RT
, RA
, RB
}},
5303 {"addc", XO(31,10,0,0), XO_MASK
, PPCCOM
, 0, {RT
, RA
, RB
}},
5304 {"a", XO(31,10,0,0), XO_MASK
, PWRCOM
, 0, {RT
, RA
, RB
}},
5305 {"addc.", XO(31,10,0,1), XO_MASK
, PPCCOM
, 0, {RT
, RA
, RB
}},
5306 {"a.", XO(31,10,0,1), XO_MASK
, PWRCOM
, 0, {RT
, RA
, RB
}},
5308 {"mulhwu", XO(31,11,0,0), XO_MASK
, PPC
, 0, {RT
, RA
, RB
}},
5309 {"mulhwu.", XO(31,11,0,1), XO_MASK
, PPC
, 0, {RT
, RA
, RB
}},
5311 {"lxsiwzx", X(31,12), XX1_MASK
, PPCVSX2
, 0, {XT6
, RA0
, RB
}},
5313 {"isellt", X(31,15), X_MASK
, PPCISEL
, 0, {RT
, RA0
, RB
}},
5315 {"tlbilxlpid", XTO(31,18,0), XTO_MASK
, E500MC
|PPCA2
, 0, {0}},
5316 {"tlbilxpid", XTO(31,18,1), XTO_MASK
, E500MC
|PPCA2
, 0, {0}},
5317 {"tlbilxva", XTO(31,18,3), XTO_MASK
, E500MC
|PPCA2
, 0, {RA0
, RB
}},
5318 {"tlbilx", X(31,18), X_MASK
, E500MC
|PPCA2
, 0, {T
, RA0
, RB
}},
5320 {"mfcr", XFXM(31,19,0,0), XFXFXM_MASK
, COM
, 0, {RT
, FXM4
}},
5321 {"mfocrf", XFXM(31,19,0,1), XFXFXM_MASK
, COM
, 0, {RT
, FXM
}},
5323 {"lwarx", X(31,20), XEH_MASK
, PPC
, 0, {RT
, RA0
, RB
, EH
}},
5325 {"ldx", X(31,21), X_MASK
, PPC64
, 0, {RT
, RA0
, RB
}},
5327 {"icbt", X(31,22), X_MASK
, BOOKE
|PPCE300
|PPCA2
|PPC476
, 0, {CT
, RA0
, RB
}},
5329 {"lwzx", X(31,23), X_MASK
, PPCCOM
, 0, {RT
, RA0
, RB
}},
5330 {"lx", X(31,23), X_MASK
, PWRCOM
, 0, {RT
, RA
, RB
}},
5332 {"slw", XRC(31,24,0), X_MASK
, PPCCOM
, 0, {RA
, RS
, RB
}},
5333 {"sl", XRC(31,24,0), X_MASK
, PWRCOM
, 0, {RA
, RS
, RB
}},
5334 {"slw.", XRC(31,24,1), X_MASK
, PPCCOM
, 0, {RA
, RS
, RB
}},
5335 {"sl.", XRC(31,24,1), X_MASK
, PWRCOM
, 0, {RA
, RS
, RB
}},
5337 {"cntlzw", XRC(31,26,0), XRB_MASK
, PPCCOM
, 0, {RA
, RS
}},
5338 {"cntlz", XRC(31,26,0), XRB_MASK
, PWRCOM
, 0, {RA
, RS
}},
5339 {"cntlzw.", XRC(31,26,1), XRB_MASK
, PPCCOM
, 0, {RA
, RS
}},
5340 {"cntlz.", XRC(31,26,1), XRB_MASK
, PWRCOM
, 0, {RA
, RS
}},
5342 {"sld", XRC(31,27,0), X_MASK
, PPC64
, 0, {RA
, RS
, RB
}},
5343 {"sld.", XRC(31,27,1), X_MASK
, PPC64
, 0, {RA
, RS
, RB
}},
5345 {"and", XRC(31,28,0), X_MASK
, COM
, 0, {RA
, RS
, RB
}},
5346 {"and.", XRC(31,28,1), X_MASK
, COM
, 0, {RA
, RS
, RB
}},
5348 {"maskg", XRC(31,29,0), X_MASK
, M601
, PPCA2
, {RA
, RS
, RB
}},
5349 {"maskg.", XRC(31,29,1), X_MASK
, M601
, PPCA2
, {RA
, RS
, RB
}},
5351 {"ldepx", X(31,29), X_MASK
, E500MC
|PPCA2
, 0, {RT
, RA0
, RB
}},
5353 {"waitasec", X(31,30), XRTRARB_MASK
, POWER8
, POWER9
, {0}},
5354 {"wait", X(31,30), XWC_MASK
, POWER9
, 0, {WC
}},
5356 {"lwepx", X(31,31), X_MASK
, E500MC
|PPCA2
, 0, {RT
, RA0
, RB
}},
5358 {"cmplw", XOPL(31,32,0), XCMPL_MASK
, PPCCOM
, 0, {OBF
, RA
, RB
}},
5359 {"cmpld", XOPL(31,32,1), XCMPL_MASK
, PPC64
, 0, {OBF
, RA
, RB
}},
5360 {"cmpl", X(31,32), XCMP_MASK
, PPC
, 0, {BF
, L32OPT
, RA
, RB
}},
5361 {"cmpl", X(31,32), XCMPL_MASK
, PWRCOM
, PPC
, {BF
, RA
, RB
}},
5363 {"lvsr", X(31,38), X_MASK
, PPCVEC
, 0, {VD
, RA0
, RB
}},
5364 {"lvehx", X(31,39), X_MASK
, PPCVEC
, 0, {VD
, RA0
, RB
}},
5365 {"lhfcmx", APU(31,39,0), APU_MASK
, PPC405
, 0, {FCRT
, RA
, RB
}},
5367 {"mviwsplt", X(31,46), X_MASK
, E6500
, 0, {VD
, RA
, RB
}},
5369 {"iselgt", X(31,47), X_MASK
, PPCISEL
, 0, {RT
, RA0
, RB
}},
5371 {"lvewx", X(31,71), X_MASK
, PPCVEC
, 0, {VD
, RA0
, RB
}},
5373 {"addg6s", XO(31,74,0,0), XO_MASK
, POWER6
, 0, {RT
, RA
, RB
}},
5375 {"lxsiwax", X(31,76), XX1_MASK
, PPCVSX2
, 0, {XT6
, RA0
, RB
}},
5377 {"iseleq", X(31,79), X_MASK
, PPCISEL
, 0, {RT
, RA0
, RB
}},
5379 {"isel", XISEL(31,15), XISEL_MASK
, PPCISEL
|TITAN
, 0, {RT
, RA0
, RB
, CRB
}},
5381 {"subf", XO(31,40,0,0), XO_MASK
, PPC
, 0, {RT
, RA
, RB
}},
5382 {"sub", XO(31,40,0,0), XO_MASK
, PPC
, 0, {RT
, RB
, RA
}},
5383 {"subf.", XO(31,40,0,1), XO_MASK
, PPC
, 0, {RT
, RA
, RB
}},
5384 {"sub.", XO(31,40,0,1), XO_MASK
, PPC
, 0, {RT
, RB
, RA
}},
5386 {"mfvsrd", X(31,51), XX1RB_MASK
, PPCVSX2
, 0, {RA
, XS6
}},
5387 {"mffprd", X(31,51), XX1RB_MASK
|1, PPCVSX2
, 0, {RA
, FRS
}},
5388 {"mfvrd", X(31,51)|1, XX1RB_MASK
|1, PPCVSX2
, 0, {RA
, VS
}},
5389 {"eratilx", X(31,51), X_MASK
, PPCA2
, 0, {ERAT_T
, RA
, RB
}},
5391 {"lbarx", X(31,52), XEH_MASK
, POWER8
|E6500
, 0, {RT
, RA0
, RB
, EH
}},
5393 {"ldux", X(31,53), X_MASK
, PPC64
, 0, {RT
, RAL
, RB
}},
5395 {"dcbst", X(31,54), XRT_MASK
, PPC
, 0, {RA0
, RB
}},
5397 {"lwzux", X(31,55), X_MASK
, PPCCOM
, 0, {RT
, RAL
, RB
}},
5398 {"lux", X(31,55), X_MASK
, PWRCOM
, 0, {RT
, RA
, RB
}},
5400 {"cntlzd", XRC(31,58,0), XRB_MASK
, PPC64
, 0, {RA
, RS
}},
5401 {"cntlzd.", XRC(31,58,1), XRB_MASK
, PPC64
, 0, {RA
, RS
}},
5403 {"andc", XRC(31,60,0), X_MASK
, COM
, 0, {RA
, RS
, RB
}},
5404 {"andc.", XRC(31,60,1), X_MASK
, COM
, 0, {RA
, RS
, RB
}},
5406 {"waitrsv", X(31,62)|(1<<21), 0xffffffff, E500MC
|PPCA2
, 0, {0}},
5407 {"waitimpl", X(31,62)|(2<<21), 0xffffffff, E500MC
|PPCA2
, 0, {0}},
5408 {"wait", X(31,62), XWC_MASK
, E500MC
|PPCA2
, 0, {WC
}},
5410 {"dcbstep", XRT(31,63,0), XRT_MASK
, E500MC
|PPCA2
, 0, {RA0
, RB
}},
5412 {"tdlgt", XTO(31,68,TOLGT
), XTO_MASK
, PPC64
, 0, {RA
, RB
}},
5413 {"tdllt", XTO(31,68,TOLLT
), XTO_MASK
, PPC64
, 0, {RA
, RB
}},
5414 {"tdeq", XTO(31,68,TOEQ
), XTO_MASK
, PPC64
, 0, {RA
, RB
}},
5415 {"tdlge", XTO(31,68,TOLGE
), XTO_MASK
, PPC64
, 0, {RA
, RB
}},
5416 {"tdlnl", XTO(31,68,TOLNL
), XTO_MASK
, PPC64
, 0, {RA
, RB
}},
5417 {"tdlle", XTO(31,68,TOLLE
), XTO_MASK
, PPC64
, 0, {RA
, RB
}},
5418 {"tdlng", XTO(31,68,TOLNG
), XTO_MASK
, PPC64
, 0, {RA
, RB
}},
5419 {"tdgt", XTO(31,68,TOGT
), XTO_MASK
, PPC64
, 0, {RA
, RB
}},
5420 {"tdge", XTO(31,68,TOGE
), XTO_MASK
, PPC64
, 0, {RA
, RB
}},
5421 {"tdnl", XTO(31,68,TONL
), XTO_MASK
, PPC64
, 0, {RA
, RB
}},
5422 {"tdlt", XTO(31,68,TOLT
), XTO_MASK
, PPC64
, 0, {RA
, RB
}},
5423 {"tdle", XTO(31,68,TOLE
), XTO_MASK
, PPC64
, 0, {RA
, RB
}},
5424 {"tdng", XTO(31,68,TONG
), XTO_MASK
, PPC64
, 0, {RA
, RB
}},
5425 {"tdne", XTO(31,68,TONE
), XTO_MASK
, PPC64
, 0, {RA
, RB
}},
5426 {"tdu", XTO(31,68,TOU
), XTO_MASK
, PPC64
, 0, {RA
, RB
}},
5427 {"td", X(31,68), X_MASK
, PPC64
, 0, {TO
, RA
, RB
}},
5429 {"lwfcmx", APU(31,71,0), APU_MASK
, PPC405
, 0, {FCRT
, RA
, RB
}},
5430 {"mulhd", XO(31,73,0,0), XO_MASK
, PPC64
, 0, {RT
, RA
, RB
}},
5431 {"mulhd.", XO(31,73,0,1), XO_MASK
, PPC64
, 0, {RT
, RA
, RB
}},
5433 {"mulhw", XO(31,75,0,0), XO_MASK
, PPC
, 0, {RT
, RA
, RB
}},
5434 {"mulhw.", XO(31,75,0,1), XO_MASK
, PPC
, 0, {RT
, RA
, RB
}},
5436 {"dlmzb", XRC(31,78,0), X_MASK
, PPC403
|PPC440
|PPC476
|TITAN
, 0, {RA
, RS
, RB
}},
5437 {"dlmzb.", XRC(31,78,1), X_MASK
, PPC403
|PPC440
|PPC476
|TITAN
, 0, {RA
, RS
, RB
}},
5439 {"mtsrd", X(31,82), XRB_MASK
|(1<<20), PPC64
, 0, {SR
, RS
}},
5441 {"mfmsr", X(31,83), XRARB_MASK
, COM
, 0, {RT
}},
5443 {"ldarx", X(31,84), XEH_MASK
, PPC64
, 0, {RT
, RA0
, RB
, EH
}},
5445 {"dcbfl", XOPL(31,86,1), XRT_MASK
, POWER5
, PPC476
, {RA0
, RB
}},
5446 {"dcbf", X(31,86), XLRT_MASK
, PPC
, 0, {RA0
, RB
, L2OPT
}},
5448 {"lbzx", X(31,87), X_MASK
, COM
, 0, {RT
, RA0
, RB
}},
5450 {"lbepx", X(31,95), X_MASK
, E500MC
|PPCA2
, 0, {RT
, RA0
, RB
}},
5452 {"dni", XRC(31,97,1), XRB_MASK
, E6500
, 0, {DUI
, DCTL
}},
5454 {"lvx", X(31,103), X_MASK
, PPCVEC
, 0, {VD
, RA0
, RB
}},
5455 {"lqfcmx", APU(31,103,0), APU_MASK
, PPC405
, 0, {FCRT
, RA
, RB
}},
5457 {"neg", XO(31,104,0,0), XORB_MASK
, COM
, 0, {RT
, RA
}},
5458 {"neg.", XO(31,104,0,1), XORB_MASK
, COM
, 0, {RT
, RA
}},
5460 {"mul", XO(31,107,0,0), XO_MASK
, M601
, 0, {RT
, RA
, RB
}},
5461 {"mul.", XO(31,107,0,1), XO_MASK
, M601
, 0, {RT
, RA
, RB
}},
5463 {"mvidsplt", X(31,110), X_MASK
, E6500
, 0, {VD
, RA
, RB
}},
5465 {"mtsrdin", X(31,114), XRA_MASK
, PPC64
, 0, {RS
, RB
}},
5467 {"mffprwz", X(31,115), XX1RB_MASK
|1, PPCVSX2
, 0, {RA
, FRS
}},
5468 {"mfvrwz", X(31,115)|1, XX1RB_MASK
|1, PPCVSX2
, 0, {RA
, VS
}},
5469 {"mfvsrwz", X(31,115), XX1RB_MASK
, PPCVSX2
, 0, {RA
, XS6
}},
5471 {"lharx", X(31,116), XEH_MASK
, POWER8
|E6500
, 0, {RT
, RA0
, RB
, EH
}},
5473 {"clf", X(31,118), XTO_MASK
, POWER
, 0, {RA
, RB
}},
5475 {"lbzux", X(31,119), X_MASK
, COM
, 0, {RT
, RAL
, RB
}},
5477 {"popcntb", X(31,122), XRB_MASK
, POWER5
, 0, {RA
, RS
}},
5479 {"not", XRC(31,124,0), X_MASK
, COM
, 0, {RA
, RSB
}},
5480 {"nor", XRC(31,124,0), X_MASK
, COM
, 0, {RA
, RS
, RB
}},
5481 {"not.", XRC(31,124,1), X_MASK
, COM
, 0, {RA
, RSB
}},
5482 {"nor.", XRC(31,124,1), X_MASK
, COM
, 0, {RA
, RS
, RB
}},
5484 {"dcbfep", XRT(31,127,0), XRT_MASK
, E500MC
|PPCA2
, 0, {RA0
, RB
}},
5486 {"setb", X(31,128), XRB_MASK
|(3<<16), POWER9
, 0, {RT
, BFA
}},
5488 {"wrtee", X(31,131), XRARB_MASK
, PPC403
|BOOKE
|PPCA2
|PPC476
, 0, {RS
}},
5490 {"dcbtstls", X(31,134), X_MASK
, PPCCHLK
|PPC476
|TITAN
, 0, {CT
, RA0
, RB
}},
5492 {"stvebx", X(31,135), X_MASK
, PPCVEC
, 0, {VS
, RA0
, RB
}},
5493 {"stbfcmx", APU(31,135,0), APU_MASK
, PPC405
, 0, {FCRT
, RA
, RB
}},
5495 {"subfe", XO(31,136,0,0), XO_MASK
, PPCCOM
, 0, {RT
, RA
, RB
}},
5496 {"sfe", XO(31,136,0,0), XO_MASK
, PWRCOM
, 0, {RT
, RA
, RB
}},
5497 {"subfe.", XO(31,136,0,1), XO_MASK
, PPCCOM
, 0, {RT
, RA
, RB
}},
5498 {"sfe.", XO(31,136,0,1), XO_MASK
, PWRCOM
, 0, {RT
, RA
, RB
}},
5500 {"adde", XO(31,138,0,0), XO_MASK
, PPCCOM
, 0, {RT
, RA
, RB
}},
5501 {"ae", XO(31,138,0,0), XO_MASK
, PWRCOM
, 0, {RT
, RA
, RB
}},
5502 {"adde.", XO(31,138,0,1), XO_MASK
, PPCCOM
, 0, {RT
, RA
, RB
}},
5503 {"ae.", XO(31,138,0,1), XO_MASK
, PWRCOM
, 0, {RT
, RA
, RB
}},
5505 {"stxsiwx", X(31,140), XX1_MASK
, PPCVSX2
, 0, {XS6
, RA0
, RB
}},
5507 {"msgsndp", XRTRA(31,142,0,0), XRTRA_MASK
, POWER8
, 0, {RB
}},
5508 {"dcbtstlse", X(31,142), X_MASK
, PPCCHLK
, E500MC
, {CT
, RA0
, RB
}},
5510 {"mtcr", XFXM(31,144,0xff,0), XRARB_MASK
, COM
, 0, {RS
}},
5511 {"mtcrf", XFXM(31,144,0,0), XFXFXM_MASK
, COM
, 0, {FXM
, RS
}},
5512 {"mtocrf", XFXM(31,144,0,1), XFXFXM_MASK
, COM
, 0, {FXM
, RS
}},
5514 {"mtmsr", X(31,146), XRLARB_MASK
, COM
, 0, {RS
, A_L
}},
5516 {"mtsle", X(31,147), XRTLRARB_MASK
, POWER8
, 0, {L
}},
5518 {"eratsx", XRC(31,147,0), X_MASK
, PPCA2
, 0, {RT
, RA0
, RB
}},
5519 {"eratsx.", XRC(31,147,1), X_MASK
, PPCA2
, 0, {RT
, RA0
, RB
}},
5521 {"stdx", X(31,149), X_MASK
, PPC64
, 0, {RS
, RA0
, RB
}},
5523 {"stwcx.", XRC(31,150,1), X_MASK
, PPC
, 0, {RS
, RA0
, RB
}},
5525 {"stwx", X(31,151), X_MASK
, PPCCOM
, 0, {RS
, RA0
, RB
}},
5526 {"stx", X(31,151), X_MASK
, PWRCOM
, 0, {RS
, RA
, RB
}},
5528 {"slq", XRC(31,152,0), X_MASK
, M601
, 0, {RA
, RS
, RB
}},
5529 {"slq.", XRC(31,152,1), X_MASK
, M601
, 0, {RA
, RS
, RB
}},
5531 {"sle", XRC(31,153,0), X_MASK
, M601
, 0, {RA
, RS
, RB
}},
5532 {"sle.", XRC(31,153,1), X_MASK
, M601
, 0, {RA
, RS
, RB
}},
5534 {"prtyw", X(31,154), XRB_MASK
, POWER6
|PPCA2
|PPC476
, 0, {RA
, RS
}},
5536 {"stdepx", X(31,157), X_MASK
, E500MC
|PPCA2
, 0, {RS
, RA0
, RB
}},
5538 {"stwepx", X(31,159), X_MASK
, E500MC
|PPCA2
, 0, {RS
, RA0
, RB
}},
5540 {"wrteei", X(31,163), XE_MASK
, PPC403
|BOOKE
|PPCA2
|PPC476
, 0, {E
}},
5542 {"dcbtls", X(31,166), X_MASK
, PPCCHLK
|PPC476
|TITAN
, 0, {CT
, RA0
, RB
}},
5544 {"stvehx", X(31,167), X_MASK
, PPCVEC
, 0, {VS
, RA0
, RB
}},
5545 {"sthfcmx", APU(31,167,0), APU_MASK
, PPC405
, 0, {FCRT
, RA
, RB
}},
5547 {"addex", ZRC(31,170,0), Z2_MASK
, POWER9
, 0, {RT
, RA
, RB
, CY
}},
5549 {"msgclrp", XRTRA(31,174,0,0), XRTRA_MASK
, POWER8
, 0, {RB
}},
5550 {"dcbtlse", X(31,174), X_MASK
, PPCCHLK
, E500MC
, {CT
, RA0
, RB
}},
5552 {"mtmsrd", X(31,178), XRLARB_MASK
, PPC64
, 0, {RS
, A_L
}},
5554 {"mtvsrd", X(31,179), XX1RB_MASK
, PPCVSX2
, 0, {XT6
, RA
}},
5555 {"mtfprd", X(31,179), XX1RB_MASK
|1, PPCVSX2
, 0, {FRT
, RA
}},
5556 {"mtvrd", X(31,179)|1, XX1RB_MASK
|1, PPCVSX2
, 0, {VD
, RA
}},
5557 {"eratre", X(31,179), X_MASK
, PPCA2
, 0, {RT
, RA
, WS
}},
5559 {"stdux", X(31,181), X_MASK
, PPC64
, 0, {RS
, RAS
, RB
}},
5561 {"stqcx.", XRC(31,182,1), X_MASK
|Q_MASK
, POWER8
, 0, {RSQ
, RA0
, RB
}},
5562 {"wchkall", X(31,182), X_MASK
, PPCA2
, 0, {OBF
}},
5564 {"stwux", X(31,183), X_MASK
, PPCCOM
, 0, {RS
, RAS
, RB
}},
5565 {"stux", X(31,183), X_MASK
, PWRCOM
, 0, {RS
, RA0
, RB
}},
5567 {"sliq", XRC(31,184,0), X_MASK
, M601
, 0, {RA
, RS
, SH
}},
5568 {"sliq.", XRC(31,184,1), X_MASK
, M601
, 0, {RA
, RS
, SH
}},
5570 {"prtyd", X(31,186), XRB_MASK
, POWER6
|PPCA2
, 0, {RA
, RS
}},
5572 {"cmprb", X(31,192), XCMP_MASK
, POWER9
, 0, {BF
, L
, RA
, RB
}},
5574 {"icblq.", XRC(31,198,1), X_MASK
, E6500
, 0, {CT
, RA0
, RB
}},
5576 {"stvewx", X(31,199), X_MASK
, PPCVEC
, 0, {VS
, RA0
, RB
}},
5577 {"stwfcmx", APU(31,199,0), APU_MASK
, PPC405
, 0, {FCRT
, RA
, RB
}},
5579 {"subfze", XO(31,200,0,0), XORB_MASK
, PPCCOM
, 0, {RT
, RA
}},
5580 {"sfze", XO(31,200,0,0), XORB_MASK
, PWRCOM
, 0, {RT
, RA
}},
5581 {"subfze.", XO(31,200,0,1), XORB_MASK
, PPCCOM
, 0, {RT
, RA
}},
5582 {"sfze.", XO(31,200,0,1), XORB_MASK
, PWRCOM
, 0, {RT
, RA
}},
5584 {"addze", XO(31,202,0,0), XORB_MASK
, PPCCOM
, 0, {RT
, RA
}},
5585 {"aze", XO(31,202,0,0), XORB_MASK
, PWRCOM
, 0, {RT
, RA
}},
5586 {"addze.", XO(31,202,0,1), XORB_MASK
, PPCCOM
, 0, {RT
, RA
}},
5587 {"aze.", XO(31,202,0,1), XORB_MASK
, PWRCOM
, 0, {RT
, RA
}},
5589 {"msgsnd", XRTRA(31,206,0,0), XRTRA_MASK
, E500MC
|PPCA2
|POWER8
, 0, {RB
}},
5591 {"mtsr", X(31,210), XRB_MASK
|(1<<20), COM
, NON32
, {SR
, RS
}},
5593 {"mtfprwa", X(31,211), XX1RB_MASK
|1, PPCVSX2
, 0, {FRT
, RA
}},
5594 {"mtvrwa", X(31,211)|1, XX1RB_MASK
|1, PPCVSX2
, 0, {VD
, RA
}},
5595 {"mtvsrwa", X(31,211), XX1RB_MASK
, PPCVSX2
, 0, {XT6
, RA
}},
5596 {"eratwe", X(31,211), X_MASK
, PPCA2
, 0, {RS
, RA
, WS
}},
5598 {"ldawx.", XRC(31,212,1), X_MASK
, PPCA2
, 0, {RT
, RA0
, RB
}},
5600 {"stdcx.", XRC(31,214,1), X_MASK
, PPC64
, 0, {RS
, RA0
, RB
}},
5602 {"stbx", X(31,215), X_MASK
, COM
, 0, {RS
, RA0
, RB
}},
5604 {"sllq", XRC(31,216,0), X_MASK
, M601
, 0, {RA
, RS
, RB
}},
5605 {"sllq.", XRC(31,216,1), X_MASK
, M601
, 0, {RA
, RS
, RB
}},
5607 {"sleq", XRC(31,217,0), X_MASK
, M601
, 0, {RA
, RS
, RB
}},
5608 {"sleq.", XRC(31,217,1), X_MASK
, M601
, 0, {RA
, RS
, RB
}},
5610 {"stbepx", X(31,223), X_MASK
, E500MC
|PPCA2
, 0, {RS
, RA0
, RB
}},
5612 {"cmpeqb", X(31,224), XCMPL_MASK
, POWER9
, 0, {BF
, RA
, RB
}},
5614 {"icblc", X(31,230), X_MASK
, PPCCHLK
|PPC476
|TITAN
, 0, {CT
, RA0
, RB
}},
5616 {"stvx", X(31,231), X_MASK
, PPCVEC
, 0, {VS
, RA0
, RB
}},
5617 {"stqfcmx", APU(31,231,0), APU_MASK
, PPC405
, 0, {FCRT
, RA
, RB
}},
5619 {"subfme", XO(31,232,0,0), XORB_MASK
, PPCCOM
, 0, {RT
, RA
}},
5620 {"sfme", XO(31,232,0,0), XORB_MASK
, PWRCOM
, 0, {RT
, RA
}},
5621 {"subfme.", XO(31,232,0,1), XORB_MASK
, PPCCOM
, 0, {RT
, RA
}},
5622 {"sfme.", XO(31,232,0,1), XORB_MASK
, PWRCOM
, 0, {RT
, RA
}},
5624 {"mulld", XO(31,233,0,0), XO_MASK
, PPC64
, 0, {RT
, RA
, RB
}},
5625 {"mulld.", XO(31,233,0,1), XO_MASK
, PPC64
, 0, {RT
, RA
, RB
}},
5627 {"addme", XO(31,234,0,0), XORB_MASK
, PPCCOM
, 0, {RT
, RA
}},
5628 {"ame", XO(31,234,0,0), XORB_MASK
, PWRCOM
, 0, {RT
, RA
}},
5629 {"addme.", XO(31,234,0,1), XORB_MASK
, PPCCOM
, 0, {RT
, RA
}},
5630 {"ame.", XO(31,234,0,1), XORB_MASK
, PWRCOM
, 0, {RT
, RA
}},
5632 {"mullw", XO(31,235,0,0), XO_MASK
, PPCCOM
, 0, {RT
, RA
, RB
}},
5633 {"muls", XO(31,235,0,0), XO_MASK
, PWRCOM
, 0, {RT
, RA
, RB
}},
5634 {"mullw.", XO(31,235,0,1), XO_MASK
, PPCCOM
, 0, {RT
, RA
, RB
}},
5635 {"muls.", XO(31,235,0,1), XO_MASK
, PWRCOM
, 0, {RT
, RA
, RB
}},
5637 {"icblce", X(31,238), X_MASK
, PPCCHLK
, E500MC
|PPCA2
, {CT
, RA
, RB
}},
5638 {"msgclr", XRTRA(31,238,0,0), XRTRA_MASK
, E500MC
|PPCA2
|POWER8
, 0, {RB
}},
5639 {"mtsrin", X(31,242), XRA_MASK
, PPC
, NON32
, {RS
, RB
}},
5640 {"mtsri", X(31,242), XRA_MASK
, POWER
, NON32
, {RS
, RB
}},
5642 {"mtfprwz", X(31,243), XX1RB_MASK
|1, PPCVSX2
, 0, {FRT
, RA
}},
5643 {"mtvrwz", X(31,243)|1, XX1RB_MASK
|1, PPCVSX2
, 0, {VD
, RA
}},
5644 {"mtvsrwz", X(31,243), XX1RB_MASK
, PPCVSX2
, 0, {XT6
, RA
}},
5646 {"dcbtstt", XRT(31,246,0x10), XRT_MASK
, POWER7
, 0, {RA0
, RB
}},
5647 {"dcbtst", X(31,246), X_MASK
, POWER4
, DCBT_EO
, {RA0
, RB
, CT
}},
5648 {"dcbtst", X(31,246), X_MASK
, DCBT_EO
, 0, {CT
, RA0
, RB
}},
5649 {"dcbtst", X(31,246), X_MASK
, PPC
, POWER4
|DCBT_EO
, {RA0
, RB
}},
5651 {"stbux", X(31,247), X_MASK
, COM
, 0, {RS
, RAS
, RB
}},
5653 {"slliq", XRC(31,248,0), X_MASK
, M601
, 0, {RA
, RS
, SH
}},
5654 {"slliq.", XRC(31,248,1), X_MASK
, M601
, 0, {RA
, RS
, SH
}},
5656 {"bpermd", X(31,252), X_MASK
, POWER7
|PPCA2
, 0, {RA
, RS
, RB
}},
5658 {"dcbtstep", XRT(31,255,0), X_MASK
, E500MC
|PPCA2
, 0, {RT
, RA0
, RB
}},
5660 {"mfdcrx", X(31,259), X_MASK
, BOOKE
|PPCA2
|PPC476
, TITAN
, {RS
, RA
}},
5661 {"mfdcrx.", XRC(31,259,1), X_MASK
, PPCA2
, 0, {RS
, RA
}},
5663 {"lvexbx", X(31,261), X_MASK
, E6500
, 0, {VD
, RA0
, RB
}},
5665 {"icbt", X(31,262), XRT_MASK
, PPC403
, 0, {RA
, RB
}},
5667 {"lvepxl", X(31,263), X_MASK
, E6500
, 0, {VD
, RA0
, RB
}},
5669 {"ldfcmx", APU(31,263,0), APU_MASK
, PPC405
, 0, {FCRT
, RA
, RB
}},
5670 {"doz", XO(31,264,0,0), XO_MASK
, M601
, 0, {RT
, RA
, RB
}},
5671 {"doz.", XO(31,264,0,1), XO_MASK
, M601
, 0, {RT
, RA
, RB
}},
5673 {"modud", X(31,265), X_MASK
, POWER9
, 0, {RT
, RA
, RB
}},
5675 {"add", XO(31,266,0,0), XO_MASK
, PPCCOM
, 0, {RT
, RA
, RB
}},
5676 {"cax", XO(31,266,0,0), XO_MASK
, PWRCOM
, 0, {RT
, RA
, RB
}},
5677 {"add.", XO(31,266,0,1), XO_MASK
, PPCCOM
, 0, {RT
, RA
, RB
}},
5678 {"cax.", XO(31,266,0,1), XO_MASK
, PWRCOM
, 0, {RT
, RA
, RB
}},
5680 {"moduw", X(31,267), X_MASK
, POWER9
, 0, {RT
, RA
, RB
}},
5682 {"lxvx", X(31,268), XX1_MASK
|1<<6, PPCVSX3
, 0, {XT6
, RA0
, RB
}},
5683 {"lxvl", X(31,269), XX1_MASK
, PPCVSX3
, 0, {XT6
, RA0
, RB
}},
5685 {"ehpriv", X(31,270), 0xffffffff, E500MC
|PPCA2
, 0, {0}},
5687 {"tlbiel", X(31,274), X_MASK
|1<<20,POWER9
, 0, {RB
, RSO
, RIC
, PRS
, X_R
}},
5688 {"tlbiel", X(31,274), XRTLRA_MASK
, POWER4
, POWER9
|PPC476
, {RB
, LOPT
}},
5690 {"mfapidi", X(31,275), X_MASK
, BOOKE
, E500
|TITAN
, {RT
, RA
}},
5692 {"lqarx", X(31,276), XEH_MASK
|Q_MASK
, POWER8
, 0, {RTQ
, RAX
, RBX
, EH
}},
5694 {"lscbx", XRC(31,277,0), X_MASK
, M601
, 0, {RT
, RA
, RB
}},
5695 {"lscbx.", XRC(31,277,1), X_MASK
, M601
, 0, {RT
, RA
, RB
}},
5697 {"dcbtt", XRT(31,278,0x10), XRT_MASK
, POWER7
, 0, {RA0
, RB
}},
5698 {"dcbt", X(31,278), X_MASK
, POWER4
, DCBT_EO
, {RA0
, RB
, CT
}},
5699 {"dcbt", X(31,278), X_MASK
, DCBT_EO
, 0, {CT
, RA0
, RB
}},
5700 {"dcbt", X(31,278), X_MASK
, PPC
, POWER4
|DCBT_EO
, {RA0
, RB
}},
5702 {"lhzx", X(31,279), X_MASK
, COM
, 0, {RT
, RA0
, RB
}},
5704 {"cdtbcd", X(31,282), XRB_MASK
, POWER6
, 0, {RA
, RS
}},
5706 {"eqv", XRC(31,284,0), X_MASK
, COM
, 0, {RA
, RS
, RB
}},
5707 {"eqv.", XRC(31,284,1), X_MASK
, COM
, 0, {RA
, RS
, RB
}},
5709 {"lhepx", X(31,287), X_MASK
, E500MC
|PPCA2
, 0, {RT
, RA0
, RB
}},
5711 {"mfdcrux", X(31,291), X_MASK
, PPC464
|PPC476
, 0, {RS
, RA
}},
5713 {"lvexhx", X(31,293), X_MASK
, E6500
, 0, {VD
, RA0
, RB
}},
5714 {"lvepx", X(31,295), X_MASK
, E6500
, 0, {VD
, RA0
, RB
}},
5716 {"lxvll", X(31,301), XX1_MASK
, PPCVSX3
, 0, {XT6
, RA0
, RB
}},
5718 {"mfbhrbe", X(31,302), X_MASK
, POWER8
, 0, {RT
, BHRBE
}},
5720 {"tlbie", X(31,306), X_MASK
|1<<20,POWER9
, TITAN
, {RB
, RS
, RIC
, PRS
, X_R
}},
5721 {"tlbie", X(31,306), XRA_MASK
, POWER7
, POWER9
|TITAN
, {RB
, RS
}},
5722 {"tlbie", X(31,306), XRTLRA_MASK
, PPC
, E500
|POWER7
|TITAN
, {RB
, LOPT
}},
5723 {"tlbi", X(31,306), XRT_MASK
, POWER
, 0, {RA0
, RB
}},
5725 {"mfvsrld", X(31,307), XX1RB_MASK
, PPCVSX3
, 0, {RA
, XS6
}},
5727 {"ldmx", X(31,309), X_MASK
, POWER9
, 0, {RT
, RA0
, RB
}},
5729 {"eciwx", X(31,310), X_MASK
, PPC
, E500
|TITAN
, {RT
, RA0
, RB
}},
5731 {"lhzux", X(31,311), X_MASK
, COM
, 0, {RT
, RAL
, RB
}},
5733 {"cbcdtd", X(31,314), XRB_MASK
, POWER6
, 0, {RA
, RS
}},
5735 {"xor", XRC(31,316,0), X_MASK
, COM
, 0, {RA
, RS
, RB
}},
5736 {"xor.", XRC(31,316,1), X_MASK
, COM
, 0, {RA
, RS
, RB
}},
5738 {"dcbtep", XRT(31,319,0), X_MASK
, E500MC
|PPCA2
, 0, {RT
, RA0
, RB
}},
5740 {"mfexisr", XSPR(31,323, 64), XSPR_MASK
, PPC403
, 0, {RT
}},
5741 {"mfexier", XSPR(31,323, 66), XSPR_MASK
, PPC403
, 0, {RT
}},
5742 {"mfbr0", XSPR(31,323,128), XSPR_MASK
, PPC403
, 0, {RT
}},
5743 {"mfbr1", XSPR(31,323,129), XSPR_MASK
, PPC403
, 0, {RT
}},
5744 {"mfbr2", XSPR(31,323,130), XSPR_MASK
, PPC403
, 0, {RT
}},
5745 {"mfbr3", XSPR(31,323,131), XSPR_MASK
, PPC403
, 0, {RT
}},
5746 {"mfbr4", XSPR(31,323,132), XSPR_MASK
, PPC403
, 0, {RT
}},
5747 {"mfbr5", XSPR(31,323,133), XSPR_MASK
, PPC403
, 0, {RT
}},
5748 {"mfbr6", XSPR(31,323,134), XSPR_MASK
, PPC403
, 0, {RT
}},
5749 {"mfbr7", XSPR(31,323,135), XSPR_MASK
, PPC403
, 0, {RT
}},
5750 {"mfbear", XSPR(31,323,144), XSPR_MASK
, PPC403
, 0, {RT
}},
5751 {"mfbesr", XSPR(31,323,145), XSPR_MASK
, PPC403
, 0, {RT
}},
5752 {"mfiocr", XSPR(31,323,160), XSPR_MASK
, PPC403
, 0, {RT
}},
5753 {"mfdmacr0", XSPR(31,323,192), XSPR_MASK
, PPC403
, 0, {RT
}},
5754 {"mfdmact0", XSPR(31,323,193), XSPR_MASK
, PPC403
, 0, {RT
}},
5755 {"mfdmada0", XSPR(31,323,194), XSPR_MASK
, PPC403
, 0, {RT
}},
5756 {"mfdmasa0", XSPR(31,323,195), XSPR_MASK
, PPC403
, 0, {RT
}},
5757 {"mfdmacc0", XSPR(31,323,196), XSPR_MASK
, PPC403
, 0, {RT
}},
5758 {"mfdmacr1", XSPR(31,323,200), XSPR_MASK
, PPC403
, 0, {RT
}},
5759 {"mfdmact1", XSPR(31,323,201), XSPR_MASK
, PPC403
, 0, {RT
}},
5760 {"mfdmada1", XSPR(31,323,202), XSPR_MASK
, PPC403
, 0, {RT
}},
5761 {"mfdmasa1", XSPR(31,323,203), XSPR_MASK
, PPC403
, 0, {RT
}},
5762 {"mfdmacc1", XSPR(31,323,204), XSPR_MASK
, PPC403
, 0, {RT
}},
5763 {"mfdmacr2", XSPR(31,323,208), XSPR_MASK
, PPC403
, 0, {RT
}},
5764 {"mfdmact2", XSPR(31,323,209), XSPR_MASK
, PPC403
, 0, {RT
}},
5765 {"mfdmada2", XSPR(31,323,210), XSPR_MASK
, PPC403
, 0, {RT
}},
5766 {"mfdmasa2", XSPR(31,323,211), XSPR_MASK
, PPC403
, 0, {RT
}},
5767 {"mfdmacc2", XSPR(31,323,212), XSPR_MASK
, PPC403
, 0, {RT
}},
5768 {"mfdmacr3", XSPR(31,323,216), XSPR_MASK
, PPC403
, 0, {RT
}},
5769 {"mfdmact3", XSPR(31,323,217), XSPR_MASK
, PPC403
, 0, {RT
}},
5770 {"mfdmada3", XSPR(31,323,218), XSPR_MASK
, PPC403
, 0, {RT
}},
5771 {"mfdmasa3", XSPR(31,323,219), XSPR_MASK
, PPC403
, 0, {RT
}},
5772 {"mfdmacc3", XSPR(31,323,220), XSPR_MASK
, PPC403
, 0, {RT
}},
5773 {"mfdmasr", XSPR(31,323,224), XSPR_MASK
, PPC403
, 0, {RT
}},
5774 {"mfdcr", X(31,323), X_MASK
, PPC403
|BOOKE
|PPCA2
|PPC476
, E500
|TITAN
, {RT
, SPR
}},
5775 {"mfdcr.", XRC(31,323,1), X_MASK
, PPCA2
, 0, {RT
, SPR
}},
5777 {"lvexwx", X(31,325), X_MASK
, E6500
, 0, {VD
, RA0
, RB
}},
5779 {"dcread", X(31,326), X_MASK
, PPC476
|TITAN
, 0, {RT
, RA0
, RB
}},
5781 {"div", XO(31,331,0,0), XO_MASK
, M601
, 0, {RT
, RA
, RB
}},
5782 {"div.", XO(31,331,0,1), XO_MASK
, M601
, 0, {RT
, RA
, RB
}},
5784 {"lxvdsx", X(31,332), XX1_MASK
, PPCVSX
, 0, {XT6
, RA0
, RB
}},
5786 {"mfpmr", X(31,334), X_MASK
, PPCPMR
|PPCE300
, 0, {RT
, PMR
}},
5787 {"mftmr", X(31,366), X_MASK
, PPCTMR
, 0, {RT
, TMR
}},
5789 {"slbsync", X(31,338), 0xffffffff, POWER9
, 0, {0}},
5791 {"mfmq", XSPR(31,339, 0), XSPR_MASK
, M601
, 0, {RT
}},
5792 {"mfxer", XSPR(31,339, 1), XSPR_MASK
, COM
, 0, {RT
}},
5793 {"mfrtcu", XSPR(31,339, 4), XSPR_MASK
, COM
, TITAN
, {RT
}},
5794 {"mfrtcl", XSPR(31,339, 5), XSPR_MASK
, COM
, TITAN
, {RT
}},
5795 {"mfdec", XSPR(31,339, 6), XSPR_MASK
, MFDEC1
, 0, {RT
}},
5796 {"mflr", XSPR(31,339, 8), XSPR_MASK
, COM
, 0, {RT
}},
5797 {"mfctr", XSPR(31,339, 9), XSPR_MASK
, COM
, 0, {RT
}},
5798 {"mfdscr", XSPR(31,339, 17), XSPR_MASK
, POWER6
, 0, {RT
}},
5799 {"mftid", XSPR(31,339, 17), XSPR_MASK
, POWER
, 0, {RT
}},
5800 {"mfdsisr", XSPR(31,339, 18), XSPR_MASK
, COM
, TITAN
, {RT
}},
5801 {"mfdar", XSPR(31,339, 19), XSPR_MASK
, COM
, TITAN
, {RT
}},
5802 {"mfdec", XSPR(31,339, 22), XSPR_MASK
, MFDEC2
, MFDEC1
, {RT
}},
5803 {"mfsdr0", XSPR(31,339, 24), XSPR_MASK
, POWER
, 0, {RT
}},
5804 {"mfsdr1", XSPR(31,339, 25), XSPR_MASK
, COM
, TITAN
, {RT
}},
5805 {"mfsrr0", XSPR(31,339, 26), XSPR_MASK
, COM
, 0, {RT
}},
5806 {"mfsrr1", XSPR(31,339, 27), XSPR_MASK
, COM
, 0, {RT
}},
5807 {"mfcfar", XSPR(31,339, 28), XSPR_MASK
, POWER6
, 0, {RT
}},
5808 {"mfpid", XSPR(31,339, 48), XSPR_MASK
, BOOKE
, 0, {RT
}},
5809 {"mfcsrr0", XSPR(31,339, 58), XSPR_MASK
, BOOKE
, 0, {RT
}},
5810 {"mfcsrr1", XSPR(31,339, 59), XSPR_MASK
, BOOKE
, 0, {RT
}},
5811 {"mfdear", XSPR(31,339, 61), XSPR_MASK
, BOOKE
, 0, {RT
}},
5812 {"mfesr", XSPR(31,339, 62), XSPR_MASK
, BOOKE
, 0, {RT
}},
5813 {"mfivpr", XSPR(31,339, 63), XSPR_MASK
, BOOKE
, 0, {RT
}},
5814 {"mfctrl", XSPR(31,339,136), XSPR_MASK
, POWER4
, 0, {RT
}},
5815 {"mfcmpa", XSPR(31,339,144), XSPR_MASK
, PPC860
, 0, {RT
}},
5816 {"mfcmpb", XSPR(31,339,145), XSPR_MASK
, PPC860
, 0, {RT
}},
5817 {"mfcmpc", XSPR(31,339,146), XSPR_MASK
, PPC860
, 0, {RT
}},
5818 {"mfcmpd", XSPR(31,339,147), XSPR_MASK
, PPC860
, 0, {RT
}},
5819 {"mficr", XSPR(31,339,148), XSPR_MASK
, PPC860
, 0, {RT
}},
5820 {"mfder", XSPR(31,339,149), XSPR_MASK
, PPC860
, 0, {RT
}},
5821 {"mfcounta", XSPR(31,339,150), XSPR_MASK
, PPC860
, 0, {RT
}},
5822 {"mfcountb", XSPR(31,339,151), XSPR_MASK
, PPC860
, 0, {RT
}},
5823 {"mfcmpe", XSPR(31,339,152), XSPR_MASK
, PPC860
, 0, {RT
}},
5824 {"mfcmpf", XSPR(31,339,153), XSPR_MASK
, PPC860
, 0, {RT
}},
5825 {"mfcmpg", XSPR(31,339,154), XSPR_MASK
, PPC860
, 0, {RT
}},
5826 {"mfcmph", XSPR(31,339,155), XSPR_MASK
, PPC860
, 0, {RT
}},
5827 {"mflctrl1", XSPR(31,339,156), XSPR_MASK
, PPC860
, 0, {RT
}},
5828 {"mflctrl2", XSPR(31,339,157), XSPR_MASK
, PPC860
, 0, {RT
}},
5829 {"mfictrl", XSPR(31,339,158), XSPR_MASK
, PPC860
, 0, {RT
}},
5830 {"mfbar", XSPR(31,339,159), XSPR_MASK
, PPC860
, 0, {RT
}},
5831 {"mfvrsave", XSPR(31,339,256), XSPR_MASK
, PPCVEC
, 0, {RT
}},
5832 {"mfusprg0", XSPR(31,339,256), XSPR_MASK
, BOOKE
, 0, {RT
}},
5833 {"mfsprg", XSPR(31,339,256), XSPRG_MASK
, PPC
, 0, {RT
, SPRG
}},
5834 {"mfsprg4", XSPR(31,339,260), XSPR_MASK
, PPC405
|BOOKE
, 0, {RT
}},
5835 {"mfsprg5", XSPR(31,339,261), XSPR_MASK
, PPC405
|BOOKE
, 0, {RT
}},
5836 {"mfsprg6", XSPR(31,339,262), XSPR_MASK
, PPC405
|BOOKE
, 0, {RT
}},
5837 {"mfsprg7", XSPR(31,339,263), XSPR_MASK
, PPC405
|BOOKE
, 0, {RT
}},
5838 {"mftbu", XSPR(31,339,269), XSPR_MASK
, POWER4
|BOOKE
, 0, {RT
}},
5839 {"mftb", X(31,339), X_MASK
, POWER4
|BOOKE
, 0, {RT
, TBR
}},
5840 {"mftbl", XSPR(31,339,268), XSPR_MASK
, POWER4
|BOOKE
, 0, {RT
}},
5841 {"mfsprg0", XSPR(31,339,272), XSPR_MASK
, PPC
, 0, {RT
}},
5842 {"mfsprg1", XSPR(31,339,273), XSPR_MASK
, PPC
, 0, {RT
}},
5843 {"mfsprg2", XSPR(31,339,274), XSPR_MASK
, PPC
, 0, {RT
}},
5844 {"mfsprg3", XSPR(31,339,275), XSPR_MASK
, PPC
, 0, {RT
}},
5845 {"mfasr", XSPR(31,339,280), XSPR_MASK
, PPC64
, 0, {RT
}},
5846 {"mfear", XSPR(31,339,282), XSPR_MASK
, PPC
, TITAN
, {RT
}},
5847 {"mfpir", XSPR(31,339,286), XSPR_MASK
, BOOKE
, 0, {RT
}},
5848 {"mfpvr", XSPR(31,339,287), XSPR_MASK
, PPC
, 0, {RT
}},
5849 {"mfdbsr", XSPR(31,339,304), XSPR_MASK
, BOOKE
, 0, {RT
}},
5850 {"mfdbcr0", XSPR(31,339,308), XSPR_MASK
, BOOKE
, 0, {RT
}},
5851 {"mfdbcr1", XSPR(31,339,309), XSPR_MASK
, BOOKE
, 0, {RT
}},
5852 {"mfdbcr2", XSPR(31,339,310), XSPR_MASK
, BOOKE
, 0, {RT
}},
5853 {"mfiac1", XSPR(31,339,312), XSPR_MASK
, BOOKE
, 0, {RT
}},
5854 {"mfiac2", XSPR(31,339,313), XSPR_MASK
, BOOKE
, 0, {RT
}},
5855 {"mfiac3", XSPR(31,339,314), XSPR_MASK
, BOOKE
, 0, {RT
}},
5856 {"mfiac4", XSPR(31,339,315), XSPR_MASK
, BOOKE
, 0, {RT
}},
5857 {"mfdac1", XSPR(31,339,316), XSPR_MASK
, BOOKE
, 0, {RT
}},
5858 {"mfdac2", XSPR(31,339,317), XSPR_MASK
, BOOKE
, 0, {RT
}},
5859 {"mfdvc1", XSPR(31,339,318), XSPR_MASK
, BOOKE
, 0, {RT
}},
5860 {"mfdvc2", XSPR(31,339,319), XSPR_MASK
, BOOKE
, 0, {RT
}},
5861 {"mftsr", XSPR(31,339,336), XSPR_MASK
, BOOKE
, 0, {RT
}},
5862 {"mftcr", XSPR(31,339,340), XSPR_MASK
, BOOKE
, 0, {RT
}},
5863 {"mfivor0", XSPR(31,339,400), XSPR_MASK
, BOOKE
, 0, {RT
}},
5864 {"mfivor1", XSPR(31,339,401), XSPR_MASK
, BOOKE
, 0, {RT
}},
5865 {"mfivor2", XSPR(31,339,402), XSPR_MASK
, BOOKE
, 0, {RT
}},
5866 {"mfivor3", XSPR(31,339,403), XSPR_MASK
, BOOKE
, 0, {RT
}},
5867 {"mfivor4", XSPR(31,339,404), XSPR_MASK
, BOOKE
, 0, {RT
}},
5868 {"mfivor5", XSPR(31,339,405), XSPR_MASK
, BOOKE
, 0, {RT
}},
5869 {"mfivor6", XSPR(31,339,406), XSPR_MASK
, BOOKE
, 0, {RT
}},
5870 {"mfivor7", XSPR(31,339,407), XSPR_MASK
, BOOKE
, 0, {RT
}},
5871 {"mfivor8", XSPR(31,339,408), XSPR_MASK
, BOOKE
, 0, {RT
}},
5872 {"mfivor9", XSPR(31,339,409), XSPR_MASK
, BOOKE
, 0, {RT
}},
5873 {"mfivor10", XSPR(31,339,410), XSPR_MASK
, BOOKE
, 0, {RT
}},
5874 {"mfivor11", XSPR(31,339,411), XSPR_MASK
, BOOKE
, 0, {RT
}},
5875 {"mfivor12", XSPR(31,339,412), XSPR_MASK
, BOOKE
, 0, {RT
}},
5876 {"mfivor13", XSPR(31,339,413), XSPR_MASK
, BOOKE
, 0, {RT
}},
5877 {"mfivor14", XSPR(31,339,414), XSPR_MASK
, BOOKE
, 0, {RT
}},
5878 {"mfivor15", XSPR(31,339,415), XSPR_MASK
, BOOKE
, 0, {RT
}},
5879 {"mfspefscr", XSPR(31,339,512), XSPR_MASK
, PPCSPE
, 0, {RT
}},
5880 {"mfbbear", XSPR(31,339,513), XSPR_MASK
, PPCBRLK
, 0, {RT
}},
5881 {"mfbbtar", XSPR(31,339,514), XSPR_MASK
, PPCBRLK
, 0, {RT
}},
5882 {"mfivor32", XSPR(31,339,528), XSPR_MASK
, PPCSPE
|E6500
, 0, {RT
}},
5883 {"mfivor33", XSPR(31,339,529), XSPR_MASK
, PPCSPE
|E6500
, 0, {RT
}},
5884 {"mfivor34", XSPR(31,339,530), XSPR_MASK
, PPCSPE
, 0, {RT
}},
5885 {"mfivor35", XSPR(31,339,531), XSPR_MASK
, PPCPMR
, 0, {RT
}},
5886 {"mfibatu", XSPR(31,339,528), XSPRBAT_MASK
, PPC
, TITAN
, {RT
, SPRBAT
}},
5887 {"mfibatl", XSPR(31,339,529), XSPRBAT_MASK
, PPC
, TITAN
, {RT
, SPRBAT
}},
5888 {"mfdbatu", XSPR(31,339,536), XSPRBAT_MASK
, PPC
, TITAN
, {RT
, SPRBAT
}},
5889 {"mfdbatl", XSPR(31,339,537), XSPRBAT_MASK
, PPC
, TITAN
, {RT
, SPRBAT
}},
5890 {"mfic_cst", XSPR(31,339,560), XSPR_MASK
, PPC860
, 0, {RT
}},
5891 {"mfic_adr", XSPR(31,339,561), XSPR_MASK
, PPC860
, 0, {RT
}},
5892 {"mfic_dat", XSPR(31,339,562), XSPR_MASK
, PPC860
, 0, {RT
}},
5893 {"mfdc_cst", XSPR(31,339,568), XSPR_MASK
, PPC860
, 0, {RT
}},
5894 {"mfdc_adr", XSPR(31,339,569), XSPR_MASK
, PPC860
, 0, {RT
}},
5895 {"mfdc_dat", XSPR(31,339,570), XSPR_MASK
, PPC860
, 0, {RT
}},
5896 {"mfmcsrr0", XSPR(31,339,570), XSPR_MASK
, PPCRFMCI
, 0, {RT
}},
5897 {"mfmcsrr1", XSPR(31,339,571), XSPR_MASK
, PPCRFMCI
, 0, {RT
}},
5898 {"mfmcsr", XSPR(31,339,572), XSPR_MASK
, PPCRFMCI
, 0, {RT
}},
5899 {"mfmcar", XSPR(31,339,573), XSPR_MASK
, PPCRFMCI
, TITAN
, {RT
}},
5900 {"mfdpdr", XSPR(31,339,630), XSPR_MASK
, PPC860
, 0, {RT
}},
5901 {"mfdpir", XSPR(31,339,631), XSPR_MASK
, PPC860
, 0, {RT
}},
5902 {"mfimmr", XSPR(31,339,638), XSPR_MASK
, PPC860
, 0, {RT
}},
5903 {"mfmi_ctr", XSPR(31,339,784), XSPR_MASK
, PPC860
, 0, {RT
}},
5904 {"mfmi_ap", XSPR(31,339,786), XSPR_MASK
, PPC860
, 0, {RT
}},
5905 {"mfmi_epn", XSPR(31,339,787), XSPR_MASK
, PPC860
, 0, {RT
}},
5906 {"mfmi_twc", XSPR(31,339,789), XSPR_MASK
, PPC860
, 0, {RT
}},
5907 {"mfmi_rpn", XSPR(31,339,790), XSPR_MASK
, PPC860
, 0, {RT
}},
5908 {"mfmd_ctr", XSPR(31,339,792), XSPR_MASK
, PPC860
, 0, {RT
}},
5909 {"mfm_casid", XSPR(31,339,793), XSPR_MASK
, PPC860
, 0, {RT
}},
5910 {"mfmd_ap", XSPR(31,339,794), XSPR_MASK
, PPC860
, 0, {RT
}},
5911 {"mfmd_epn", XSPR(31,339,795), XSPR_MASK
, PPC860
, 0, {RT
}},
5912 {"mfmd_twb", XSPR(31,339,796), XSPR_MASK
, PPC860
, 0, {RT
}},
5913 {"mfmd_twc", XSPR(31,339,797), XSPR_MASK
, PPC860
, 0, {RT
}},
5914 {"mfmd_rpn", XSPR(31,339,798), XSPR_MASK
, PPC860
, 0, {RT
}},
5915 {"mfm_tw", XSPR(31,339,799), XSPR_MASK
, PPC860
, 0, {RT
}},
5916 {"mfmi_dbcam", XSPR(31,339,816), XSPR_MASK
, PPC860
, 0, {RT
}},
5917 {"mfmi_dbram0", XSPR(31,339,817), XSPR_MASK
, PPC860
, 0, {RT
}},
5918 {"mfmi_dbram1", XSPR(31,339,818), XSPR_MASK
, PPC860
, 0, {RT
}},
5919 {"mfmd_dbcam", XSPR(31,339,824), XSPR_MASK
, PPC860
, 0, {RT
}},
5920 {"mfmd_dbram0", XSPR(31,339,825), XSPR_MASK
, PPC860
, 0, {RT
}},
5921 {"mfmd_dbram1", XSPR(31,339,826), XSPR_MASK
, PPC860
, 0, {RT
}},
5922 {"mfivndx", XSPR(31,339,880), XSPR_MASK
, TITAN
, 0, {RT
}},
5923 {"mfdvndx", XSPR(31,339,881), XSPR_MASK
, TITAN
, 0, {RT
}},
5924 {"mfivlim", XSPR(31,339,882), XSPR_MASK
, TITAN
, 0, {RT
}},
5925 {"mfdvlim", XSPR(31,339,883), XSPR_MASK
, TITAN
, 0, {RT
}},
5926 {"mfclcsr", XSPR(31,339,884), XSPR_MASK
, TITAN
, 0, {RT
}},
5927 {"mfccr1", XSPR(31,339,888), XSPR_MASK
, TITAN
, 0, {RT
}},
5928 {"mfppr", XSPR(31,339,896), XSPR_MASK
, POWER7
, 0, {RT
}},
5929 {"mfppr32", XSPR(31,339,898), XSPR_MASK
, POWER7
, 0, {RT
}},
5930 {"mfrstcfg", XSPR(31,339,923), XSPR_MASK
, TITAN
, 0, {RT
}},
5931 {"mfdcdbtrl", XSPR(31,339,924), XSPR_MASK
, TITAN
, 0, {RT
}},
5932 {"mfdcdbtrh", XSPR(31,339,925), XSPR_MASK
, TITAN
, 0, {RT
}},
5933 {"mficdbtr", XSPR(31,339,927), XSPR_MASK
, TITAN
, 0, {RT
}},
5934 {"mfummcr0", XSPR(31,339,936), XSPR_MASK
, PPC750
, 0, {RT
}},
5935 {"mfupmc1", XSPR(31,339,937), XSPR_MASK
, PPC750
, 0, {RT
}},
5936 {"mfupmc2", XSPR(31,339,938), XSPR_MASK
, PPC750
, 0, {RT
}},
5937 {"mfusia", XSPR(31,339,939), XSPR_MASK
, PPC750
, 0, {RT
}},
5938 {"mfummcr1", XSPR(31,339,940), XSPR_MASK
, PPC750
, 0, {RT
}},
5939 {"mfupmc3", XSPR(31,339,941), XSPR_MASK
, PPC750
, 0, {RT
}},
5940 {"mfupmc4", XSPR(31,339,942), XSPR_MASK
, PPC750
, 0, {RT
}},
5941 {"mfzpr", XSPR(31,339,944), XSPR_MASK
, PPC403
, 0, {RT
}},
5942 {"mfpid", XSPR(31,339,945), XSPR_MASK
, PPC403
, 0, {RT
}},
5943 {"mfmmucr", XSPR(31,339,946), XSPR_MASK
, TITAN
, 0, {RT
}},
5944 {"mfccr0", XSPR(31,339,947), XSPR_MASK
, PPC405
|TITAN
, 0, {RT
}},
5945 {"mfiac3", XSPR(31,339,948), XSPR_MASK
, PPC405
, 0, {RT
}},
5946 {"mfiac4", XSPR(31,339,949), XSPR_MASK
, PPC405
, 0, {RT
}},
5947 {"mfdvc1", XSPR(31,339,950), XSPR_MASK
, PPC405
, 0, {RT
}},
5948 {"mfdvc2", XSPR(31,339,951), XSPR_MASK
, PPC405
, 0, {RT
}},
5949 {"mfmmcr0", XSPR(31,339,952), XSPR_MASK
, PPC750
, 0, {RT
}},
5950 {"mfpmc1", XSPR(31,339,953), XSPR_MASK
, PPC750
, 0, {RT
}},
5951 {"mfsgr", XSPR(31,339,953), XSPR_MASK
, PPC403
, 0, {RT
}},
5952 {"mfdcwr", XSPR(31,339,954), XSPR_MASK
, PPC403
, 0, {RT
}},
5953 {"mfpmc2", XSPR(31,339,954), XSPR_MASK
, PPC750
, 0, {RT
}},
5954 {"mfsia", XSPR(31,339,955), XSPR_MASK
, PPC750
, 0, {RT
}},
5955 {"mfsler", XSPR(31,339,955), XSPR_MASK
, PPC405
, 0, {RT
}},
5956 {"mfmmcr1", XSPR(31,339,956), XSPR_MASK
, PPC750
, 0, {RT
}},
5957 {"mfsu0r", XSPR(31,339,956), XSPR_MASK
, PPC405
, 0, {RT
}},
5958 {"mfdbcr1", XSPR(31,339,957), XSPR_MASK
, PPC405
, 0, {RT
}},
5959 {"mfpmc3", XSPR(31,339,957), XSPR_MASK
, PPC750
, 0, {RT
}},
5960 {"mfpmc4", XSPR(31,339,958), XSPR_MASK
, PPC750
, 0, {RT
}},
5961 {"mficdbdr", XSPR(31,339,979), XSPR_MASK
, PPC403
|TITAN
, 0, {RT
}},
5962 {"mfesr", XSPR(31,339,980), XSPR_MASK
, PPC403
, 0, {RT
}},
5963 {"mfdear", XSPR(31,339,981), XSPR_MASK
, PPC403
, 0, {RT
}},
5964 {"mfevpr", XSPR(31,339,982), XSPR_MASK
, PPC403
, 0, {RT
}},
5965 {"mfcdbcr", XSPR(31,339,983), XSPR_MASK
, PPC403
, 0, {RT
}},
5966 {"mftsr", XSPR(31,339,984), XSPR_MASK
, PPC403
, 0, {RT
}},
5967 {"mftcr", XSPR(31,339,986), XSPR_MASK
, PPC403
, 0, {RT
}},
5968 {"mfpit", XSPR(31,339,987), XSPR_MASK
, PPC403
, 0, {RT
}},
5969 {"mftbhi", XSPR(31,339,988), XSPR_MASK
, PPC403
, 0, {RT
}},
5970 {"mftblo", XSPR(31,339,989), XSPR_MASK
, PPC403
, 0, {RT
}},
5971 {"mfsrr2", XSPR(31,339,990), XSPR_MASK
, PPC403
, 0, {RT
}},
5972 {"mfsrr3", XSPR(31,339,991), XSPR_MASK
, PPC403
, 0, {RT
}},
5973 {"mfdbsr", XSPR(31,339,1008), XSPR_MASK
, PPC403
, 0, {RT
}},
5974 {"mfdbcr0", XSPR(31,339,1010), XSPR_MASK
, PPC405
, 0, {RT
}},
5975 {"mfdbdr", XSPR(31,339,1011), XSPR_MASK
, TITAN
, 0, {RS
}},
5976 {"mfiac1", XSPR(31,339,1012), XSPR_MASK
, PPC403
, 0, {RT
}},
5977 {"mfiac2", XSPR(31,339,1013), XSPR_MASK
, PPC403
, 0, {RT
}},
5978 {"mfdac1", XSPR(31,339,1014), XSPR_MASK
, PPC403
, 0, {RT
}},
5979 {"mfdac2", XSPR(31,339,1015), XSPR_MASK
, PPC403
, 0, {RT
}},
5980 {"mfl2cr", XSPR(31,339,1017), XSPR_MASK
, PPC750
, 0, {RT
}},
5981 {"mfdccr", XSPR(31,339,1018), XSPR_MASK
, PPC403
, 0, {RT
}},
5982 {"mficcr", XSPR(31,339,1019), XSPR_MASK
, PPC403
, 0, {RT
}},
5983 {"mfictc", XSPR(31,339,1019), XSPR_MASK
, PPC750
, 0, {RT
}},
5984 {"mfpbl1", XSPR(31,339,1020), XSPR_MASK
, PPC403
, 0, {RT
}},
5985 {"mfthrm1", XSPR(31,339,1020), XSPR_MASK
, PPC750
, 0, {RT
}},
5986 {"mfpbu1", XSPR(31,339,1021), XSPR_MASK
, PPC403
, 0, {RT
}},
5987 {"mfthrm2", XSPR(31,339,1021), XSPR_MASK
, PPC750
, 0, {RT
}},
5988 {"mfpbl2", XSPR(31,339,1022), XSPR_MASK
, PPC403
, 0, {RT
}},
5989 {"mfthrm3", XSPR(31,339,1022), XSPR_MASK
, PPC750
, 0, {RT
}},
5990 {"mfpbu2", XSPR(31,339,1023), XSPR_MASK
, PPC403
, 0, {RT
}},
5991 {"mfspr", X(31,339), X_MASK
, COM
, 0, {RT
, SPR
}},
5993 {"lwax", X(31,341), X_MASK
, PPC64
, 0, {RT
, RA0
, RB
}},
5995 {"dst", XDSS(31,342,0), XDSS_MASK
, PPCVEC
, 0, {RA
, RB
, STRM
}},
5997 {"lhax", X(31,343), X_MASK
, COM
, 0, {RT
, RA0
, RB
}},
5999 {"lvxl", X(31,359), X_MASK
, PPCVEC
, 0, {VD
, RA0
, RB
}},
6001 {"abs", XO(31,360,0,0), XORB_MASK
, M601
, 0, {RT
, RA
}},
6002 {"abs.", XO(31,360,0,1), XORB_MASK
, M601
, 0, {RT
, RA
}},
6004 {"divs", XO(31,363,0,0), XO_MASK
, M601
, 0, {RT
, RA
, RB
}},
6005 {"divs.", XO(31,363,0,1), XO_MASK
, M601
, 0, {RT
, RA
, RB
}},
6007 {"lxvwsx", X(31,364), XX1_MASK
, PPCVSX3
, 0, {XT6
, RA0
, RB
}},
6009 {"tlbia", X(31,370), 0xffffffff, PPC
, E500
|TITAN
, {0}},
6011 {"mftbu", XSPR(31,371,269), XSPR_MASK
, PPC
, NO371
|POWER4
, {RT
}},
6012 {"mftb", X(31,371), X_MASK
, PPC
, NO371
|POWER4
, {RT
, TBR
}},
6013 {"mftbl", XSPR(31,371,268), XSPR_MASK
, PPC
, NO371
|POWER4
, {RT
}},
6015 {"lwaux", X(31,373), X_MASK
, PPC64
, 0, {RT
, RAL
, RB
}},
6017 {"dstst", XDSS(31,374,0), XDSS_MASK
, PPCVEC
, 0, {RA
, RB
, STRM
}},
6019 {"lhaux", X(31,375), X_MASK
, COM
, 0, {RT
, RAL
, RB
}},
6021 {"popcntw", X(31,378), XRB_MASK
, POWER7
|PPCA2
, 0, {RA
, RS
}},
6023 {"mtdcrx", X(31,387), X_MASK
, BOOKE
|PPCA2
|PPC476
, TITAN
, {RA
, RS
}},
6024 {"mtdcrx.", XRC(31,387,1), X_MASK
, PPCA2
, 0, {RA
, RS
}},
6026 {"stvexbx", X(31,389), X_MASK
, E6500
, 0, {VS
, RA0
, RB
}},
6028 {"dcblc", X(31,390), X_MASK
, PPCCHLK
|PPC476
|TITAN
, 0, {CT
, RA0
, RB
}},
6029 {"stdfcmx", APU(31,391,0), APU_MASK
, PPC405
, 0, {FCRT
, RA
, RB
}},
6031 {"divdeu", XO(31,393,0,0), XO_MASK
, POWER7
|PPCA2
, 0, {RT
, RA
, RB
}},
6032 {"divdeu.", XO(31,393,0,1), XO_MASK
, POWER7
|PPCA2
, 0, {RT
, RA
, RB
}},
6033 {"divweu", XO(31,395,0,0), XO_MASK
, POWER7
|PPCA2
, 0, {RT
, RA
, RB
}},
6034 {"divweu.", XO(31,395,0,1), XO_MASK
, POWER7
|PPCA2
, 0, {RT
, RA
, RB
}},
6036 {"stxvx", X(31,396), XX1_MASK
, PPCVSX3
, 0, {XS6
, RA0
, RB
}},
6037 {"stxvl", X(31,397), XX1_MASK
, PPCVSX3
, 0, {XS6
, RA0
, RB
}},
6039 {"dcblce", X(31,398), X_MASK
, PPCCHLK
, E500MC
, {CT
, RA
, RB
}},
6041 {"slbmte", X(31,402), XRA_MASK
, PPC64
, 0, {RS
, RB
}},
6043 {"mtvsrws", X(31,403), XX1RB_MASK
, PPCVSX3
, 0, {XT6
, RA
}},
6045 {"pbt.", XRC(31,404,1), X_MASK
, POWER8
, 0, {RS
, RA0
, RB
}},
6047 {"icswx", XRC(31,406,0), X_MASK
, POWER7
|PPCA2
, 0, {RS
, RA
, RB
}},
6048 {"icswx.", XRC(31,406,1), X_MASK
, POWER7
|PPCA2
, 0, {RS
, RA
, RB
}},
6050 {"sthx", X(31,407), X_MASK
, COM
, 0, {RS
, RA0
, RB
}},
6052 {"orc", XRC(31,412,0), X_MASK
, COM
, 0, {RA
, RS
, RB
}},
6053 {"orc.", XRC(31,412,1), X_MASK
, COM
, 0, {RA
, RS
, RB
}},
6055 {"sthepx", X(31,415), X_MASK
, E500MC
|PPCA2
, 0, {RS
, RA0
, RB
}},
6057 {"mtdcrux", X(31,419), X_MASK
, PPC464
|PPC476
, 0, {RA
, RS
}},
6059 {"stvexhx", X(31,421), X_MASK
, E6500
, 0, {VS
, RA0
, RB
}},
6061 {"dcblq.", XRC(31,422,1), X_MASK
, E6500
, 0, {CT
, RA0
, RB
}},
6063 {"divde", XO(31,425,0,0), XO_MASK
, POWER7
|PPCA2
, 0, {RT
, RA
, RB
}},
6064 {"divde.", XO(31,425,0,1), XO_MASK
, POWER7
|PPCA2
, 0, {RT
, RA
, RB
}},
6065 {"divwe", XO(31,427,0,0), XO_MASK
, POWER7
|PPCA2
, 0, {RT
, RA
, RB
}},
6066 {"divwe.", XO(31,427,0,1), XO_MASK
, POWER7
|PPCA2
, 0, {RT
, RA
, RB
}},
6068 {"stxvll", X(31,429), XX1_MASK
, PPCVSX3
, 0, {XS6
, RA0
, RB
}},
6070 {"clrbhrb", X(31,430), 0xffffffff, POWER8
, 0, {0}},
6072 {"slbie", X(31,434), XRTRA_MASK
, PPC64
, 0, {RB
}},
6074 {"mtvsrdd", X(31,435), XX1_MASK
, PPCVSX3
, 0, {XT6
, RA0
, RB
}},
6076 {"ecowx", X(31,438), X_MASK
, PPC
, E500
|TITAN
, {RT
, RA0
, RB
}},
6078 {"sthux", X(31,439), X_MASK
, COM
, 0, {RS
, RAS
, RB
}},
6080 {"mdors", 0x7f9ce378, 0xffffffff, E500MC
, 0, {0}},
6082 {"miso", 0x7f5ad378, 0xffffffff, E6500
, 0, {0}},
6084 /* The "yield", "mdoio" and "mdoom" instructions are extended mnemonics for
6085 "or rX,rX,rX", with rX being r27, r29 and r30 respectively. */
6086 {"yield", 0x7f7bdb78, 0xffffffff, POWER7
, 0, {0}},
6087 {"mdoio", 0x7fbdeb78, 0xffffffff, POWER7
, 0, {0}},
6088 {"mdoom", 0x7fdef378, 0xffffffff, POWER7
, 0, {0}},
6089 {"mr", XRC(31,444,0), X_MASK
, COM
, 0, {RA
, RSB
}},
6090 {"or", XRC(31,444,0), X_MASK
, COM
, 0, {RA
, RS
, RB
}},
6091 {"mr.", XRC(31,444,1), X_MASK
, COM
, 0, {RA
, RSB
}},
6092 {"or.", XRC(31,444,1), X_MASK
, COM
, 0, {RA
, RS
, RB
}},
6094 {"mtexisr", XSPR(31,451, 64), XSPR_MASK
, PPC403
, 0, {RS
}},
6095 {"mtexier", XSPR(31,451, 66), XSPR_MASK
, PPC403
, 0, {RS
}},
6096 {"mtbr0", XSPR(31,451,128), XSPR_MASK
, PPC403
, 0, {RS
}},
6097 {"mtbr1", XSPR(31,451,129), XSPR_MASK
, PPC403
, 0, {RS
}},
6098 {"mtbr2", XSPR(31,451,130), XSPR_MASK
, PPC403
, 0, {RS
}},
6099 {"mtbr3", XSPR(31,451,131), XSPR_MASK
, PPC403
, 0, {RS
}},
6100 {"mtbr4", XSPR(31,451,132), XSPR_MASK
, PPC403
, 0, {RS
}},
6101 {"mtbr5", XSPR(31,451,133), XSPR_MASK
, PPC403
, 0, {RS
}},
6102 {"mtbr6", XSPR(31,451,134), XSPR_MASK
, PPC403
, 0, {RS
}},
6103 {"mtbr7", XSPR(31,451,135), XSPR_MASK
, PPC403
, 0, {RS
}},
6104 {"mtbear", XSPR(31,451,144), XSPR_MASK
, PPC403
, 0, {RS
}},
6105 {"mtbesr", XSPR(31,451,145), XSPR_MASK
, PPC403
, 0, {RS
}},
6106 {"mtiocr", XSPR(31,451,160), XSPR_MASK
, PPC403
, 0, {RS
}},
6107 {"mtdmacr0", XSPR(31,451,192), XSPR_MASK
, PPC403
, 0, {RS
}},
6108 {"mtdmact0", XSPR(31,451,193), XSPR_MASK
, PPC403
, 0, {RS
}},
6109 {"mtdmada0", XSPR(31,451,194), XSPR_MASK
, PPC403
, 0, {RS
}},
6110 {"mtdmasa0", XSPR(31,451,195), XSPR_MASK
, PPC403
, 0, {RS
}},
6111 {"mtdmacc0", XSPR(31,451,196), XSPR_MASK
, PPC403
, 0, {RS
}},
6112 {"mtdmacr1", XSPR(31,451,200), XSPR_MASK
, PPC403
, 0, {RS
}},
6113 {"mtdmact1", XSPR(31,451,201), XSPR_MASK
, PPC403
, 0, {RS
}},
6114 {"mtdmada1", XSPR(31,451,202), XSPR_MASK
, PPC403
, 0, {RS
}},
6115 {"mtdmasa1", XSPR(31,451,203), XSPR_MASK
, PPC403
, 0, {RS
}},
6116 {"mtdmacc1", XSPR(31,451,204), XSPR_MASK
, PPC403
, 0, {RS
}},
6117 {"mtdmacr2", XSPR(31,451,208), XSPR_MASK
, PPC403
, 0, {RS
}},
6118 {"mtdmact2", XSPR(31,451,209), XSPR_MASK
, PPC403
, 0, {RS
}},
6119 {"mtdmada2", XSPR(31,451,210), XSPR_MASK
, PPC403
, 0, {RS
}},
6120 {"mtdmasa2", XSPR(31,451,211), XSPR_MASK
, PPC403
, 0, {RS
}},
6121 {"mtdmacc2", XSPR(31,451,212), XSPR_MASK
, PPC403
, 0, {RS
}},
6122 {"mtdmacr3", XSPR(31,451,216), XSPR_MASK
, PPC403
, 0, {RS
}},
6123 {"mtdmact3", XSPR(31,451,217), XSPR_MASK
, PPC403
, 0, {RS
}},
6124 {"mtdmada3", XSPR(31,451,218), XSPR_MASK
, PPC403
, 0, {RS
}},
6125 {"mtdmasa3", XSPR(31,451,219), XSPR_MASK
, PPC403
, 0, {RS
}},
6126 {"mtdmacc3", XSPR(31,451,220), XSPR_MASK
, PPC403
, 0, {RS
}},
6127 {"mtdmasr", XSPR(31,451,224), XSPR_MASK
, PPC403
, 0, {RS
}},
6128 {"mtdcr", X(31,451), X_MASK
, PPC403
|BOOKE
|PPCA2
|PPC476
, E500
|TITAN
, {SPR
, RS
}},
6129 {"mtdcr.", XRC(31,451,1), X_MASK
, PPCA2
, 0, {SPR
, RS
}},
6131 {"stvexwx", X(31,453), X_MASK
, E6500
, 0, {VS
, RA0
, RB
}},
6133 {"dccci", X(31,454), XRT_MASK
, PPC403
|PPC440
|PPC476
|TITAN
|PPCA2
, 0, {RAOPT
, RBOPT
}},
6134 {"dci", X(31,454), XRARB_MASK
, PPCA2
|PPC476
, 0, {CT
}},
6136 {"divdu", XO(31,457,0,0), XO_MASK
, PPC64
, 0, {RT
, RA
, RB
}},
6137 {"divdu.", XO(31,457,0,1), XO_MASK
, PPC64
, 0, {RT
, RA
, RB
}},
6139 {"divwu", XO(31,459,0,0), XO_MASK
, PPC
, 0, {RT
, RA
, RB
}},
6140 {"divwu.", XO(31,459,0,1), XO_MASK
, PPC
, 0, {RT
, RA
, RB
}},
6142 {"mtpmr", X(31,462), X_MASK
, PPCPMR
|PPCE300
, 0, {PMR
, RS
}},
6143 {"mttmr", X(31,494), X_MASK
, PPCTMR
, 0, {TMR
, RS
}},
6145 {"slbieg", X(31,466), XRA_MASK
, POWER9
, 0, {RS
, RB
}},
6147 {"mtmq", XSPR(31,467, 0), XSPR_MASK
, M601
, 0, {RS
}},
6148 {"mtxer", XSPR(31,467, 1), XSPR_MASK
, COM
, 0, {RS
}},
6149 {"mtlr", XSPR(31,467, 8), XSPR_MASK
, COM
, 0, {RS
}},
6150 {"mtctr", XSPR(31,467, 9), XSPR_MASK
, COM
, 0, {RS
}},
6151 {"mtdscr", XSPR(31,467, 17), XSPR_MASK
, POWER6
, 0, {RS
}},
6152 {"mttid", XSPR(31,467, 17), XSPR_MASK
, POWER
, 0, {RS
}},
6153 {"mtdsisr", XSPR(31,467, 18), XSPR_MASK
, COM
, TITAN
, {RS
}},
6154 {"mtdar", XSPR(31,467, 19), XSPR_MASK
, COM
, TITAN
, {RS
}},
6155 {"mtrtcu", XSPR(31,467, 20), XSPR_MASK
, COM
, TITAN
, {RS
}},
6156 {"mtrtcl", XSPR(31,467, 21), XSPR_MASK
, COM
, TITAN
, {RS
}},
6157 {"mtdec", XSPR(31,467, 22), XSPR_MASK
, COM
, 0, {RS
}},
6158 {"mtsdr0", XSPR(31,467, 24), XSPR_MASK
, POWER
, 0, {RS
}},
6159 {"mtsdr1", XSPR(31,467, 25), XSPR_MASK
, COM
, TITAN
, {RS
}},
6160 {"mtsrr0", XSPR(31,467, 26), XSPR_MASK
, COM
, 0, {RS
}},
6161 {"mtsrr1", XSPR(31,467, 27), XSPR_MASK
, COM
, 0, {RS
}},
6162 {"mtcfar", XSPR(31,467, 28), XSPR_MASK
, POWER6
, 0, {RS
}},
6163 {"mtpid", XSPR(31,467, 48), XSPR_MASK
, BOOKE
, 0, {RS
}},
6164 {"mtdecar", XSPR(31,467, 54), XSPR_MASK
, BOOKE
, 0, {RS
}},
6165 {"mtcsrr0", XSPR(31,467, 58), XSPR_MASK
, BOOKE
, 0, {RS
}},
6166 {"mtcsrr1", XSPR(31,467, 59), XSPR_MASK
, BOOKE
, 0, {RS
}},
6167 {"mtdear", XSPR(31,467, 61), XSPR_MASK
, BOOKE
, 0, {RS
}},
6168 {"mtesr", XSPR(31,467, 62), XSPR_MASK
, BOOKE
, 0, {RS
}},
6169 {"mtivpr", XSPR(31,467, 63), XSPR_MASK
, BOOKE
, 0, {RS
}},
6170 {"mtcmpa", XSPR(31,467,144), XSPR_MASK
, PPC860
, 0, {RS
}},
6171 {"mtcmpb", XSPR(31,467,145), XSPR_MASK
, PPC860
, 0, {RS
}},
6172 {"mtcmpc", XSPR(31,467,146), XSPR_MASK
, PPC860
, 0, {RS
}},
6173 {"mtcmpd", XSPR(31,467,147), XSPR_MASK
, PPC860
, 0, {RS
}},
6174 {"mticr", XSPR(31,467,148), XSPR_MASK
, PPC860
, 0, {RS
}},
6175 {"mtder", XSPR(31,467,149), XSPR_MASK
, PPC860
, 0, {RS
}},
6176 {"mtcounta", XSPR(31,467,150), XSPR_MASK
, PPC860
, 0, {RS
}},
6177 {"mtcountb", XSPR(31,467,151), XSPR_MASK
, PPC860
, 0, {RS
}},
6178 {"mtctrl", XSPR(31,467,152), XSPR_MASK
, POWER4
, 0, {RS
}},
6179 {"mtcmpe", XSPR(31,467,152), XSPR_MASK
, PPC860
, 0, {RS
}},
6180 {"mtcmpf", XSPR(31,467,153), XSPR_MASK
, PPC860
, 0, {RS
}},
6181 {"mtcmpg", XSPR(31,467,154), XSPR_MASK
, PPC860
, 0, {RS
}},
6182 {"mtcmph", XSPR(31,467,155), XSPR_MASK
, PPC860
, 0, {RS
}},
6183 {"mtlctrl1", XSPR(31,467,156), XSPR_MASK
, PPC860
, 0, {RS
}},
6184 {"mtlctrl2", XSPR(31,467,157), XSPR_MASK
, PPC860
, 0, {RS
}},
6185 {"mtictrl", XSPR(31,467,158), XSPR_MASK
, PPC860
, 0, {RS
}},
6186 {"mtbar", XSPR(31,467,159), XSPR_MASK
, PPC860
, 0, {RS
}},
6187 {"mtvrsave", XSPR(31,467,256), XSPR_MASK
, PPCVEC
, 0, {RS
}},
6188 {"mtusprg0", XSPR(31,467,256), XSPR_MASK
, BOOKE
, 0, {RS
}},
6189 {"mtsprg", XSPR(31,467,256), XSPRG_MASK
, PPC
, 0, {SPRG
, RS
}},
6190 {"mtsprg0", XSPR(31,467,272), XSPR_MASK
, PPC
, 0, {RS
}},
6191 {"mtsprg1", XSPR(31,467,273), XSPR_MASK
, PPC
, 0, {RS
}},
6192 {"mtsprg2", XSPR(31,467,274), XSPR_MASK
, PPC
, 0, {RS
}},
6193 {"mtsprg3", XSPR(31,467,275), XSPR_MASK
, PPC
, 0, {RS
}},
6194 {"mtsprg4", XSPR(31,467,276), XSPR_MASK
, PPC405
|BOOKE
, 0, {RS
}},
6195 {"mtsprg5", XSPR(31,467,277), XSPR_MASK
, PPC405
|BOOKE
, 0, {RS
}},
6196 {"mtsprg6", XSPR(31,467,278), XSPR_MASK
, PPC405
|BOOKE
, 0, {RS
}},
6197 {"mtsprg7", XSPR(31,467,279), XSPR_MASK
, PPC405
|BOOKE
, 0, {RS
}},
6198 {"mtasr", XSPR(31,467,280), XSPR_MASK
, PPC64
, 0, {RS
}},
6199 {"mtear", XSPR(31,467,282), XSPR_MASK
, PPC
, TITAN
, {RS
}},
6200 {"mttbl", XSPR(31,467,284), XSPR_MASK
, PPC
, 0, {RS
}},
6201 {"mttbu", XSPR(31,467,285), XSPR_MASK
, PPC
, 0, {RS
}},
6202 {"mtdbsr", XSPR(31,467,304), XSPR_MASK
, BOOKE
, 0, {RS
}},
6203 {"mtdbcr0", XSPR(31,467,308), XSPR_MASK
, BOOKE
, 0, {RS
}},
6204 {"mtdbcr1", XSPR(31,467,309), XSPR_MASK
, BOOKE
, 0, {RS
}},
6205 {"mtdbcr2", XSPR(31,467,310), XSPR_MASK
, BOOKE
, 0, {RS
}},
6206 {"mtiac1", XSPR(31,467,312), XSPR_MASK
, BOOKE
, 0, {RS
}},
6207 {"mtiac2", XSPR(31,467,313), XSPR_MASK
, BOOKE
, 0, {RS
}},
6208 {"mtiac3", XSPR(31,467,314), XSPR_MASK
, BOOKE
, 0, {RS
}},
6209 {"mtiac4", XSPR(31,467,315), XSPR_MASK
, BOOKE
, 0, {RS
}},
6210 {"mtdac1", XSPR(31,467,316), XSPR_MASK
, BOOKE
, 0, {RS
}},
6211 {"mtdac2", XSPR(31,467,317), XSPR_MASK
, BOOKE
, 0, {RS
}},
6212 {"mtdvc1", XSPR(31,467,318), XSPR_MASK
, BOOKE
, 0, {RS
}},
6213 {"mtdvc2", XSPR(31,467,319), XSPR_MASK
, BOOKE
, 0, {RS
}},
6214 {"mttsr", XSPR(31,467,336), XSPR_MASK
, BOOKE
, 0, {RS
}},
6215 {"mttcr", XSPR(31,467,340), XSPR_MASK
, BOOKE
, 0, {RS
}},
6216 {"mtivor0", XSPR(31,467,400), XSPR_MASK
, BOOKE
, 0, {RS
}},
6217 {"mtivor1", XSPR(31,467,401), XSPR_MASK
, BOOKE
, 0, {RS
}},
6218 {"mtivor2", XSPR(31,467,402), XSPR_MASK
, BOOKE
, 0, {RS
}},
6219 {"mtivor3", XSPR(31,467,403), XSPR_MASK
, BOOKE
, 0, {RS
}},
6220 {"mtivor4", XSPR(31,467,404), XSPR_MASK
, BOOKE
, 0, {RS
}},
6221 {"mtivor5", XSPR(31,467,405), XSPR_MASK
, BOOKE
, 0, {RS
}},
6222 {"mtivor6", XSPR(31,467,406), XSPR_MASK
, BOOKE
, 0, {RS
}},
6223 {"mtivor7", XSPR(31,467,407), XSPR_MASK
, BOOKE
, 0, {RS
}},
6224 {"mtivor8", XSPR(31,467,408), XSPR_MASK
, BOOKE
, 0, {RS
}},
6225 {"mtivor9", XSPR(31,467,409), XSPR_MASK
, BOOKE
, 0, {RS
}},
6226 {"mtivor10", XSPR(31,467,410), XSPR_MASK
, BOOKE
, 0, {RS
}},
6227 {"mtivor11", XSPR(31,467,411), XSPR_MASK
, BOOKE
, 0, {RS
}},
6228 {"mtivor12", XSPR(31,467,412), XSPR_MASK
, BOOKE
, 0, {RS
}},
6229 {"mtivor13", XSPR(31,467,413), XSPR_MASK
, BOOKE
, 0, {RS
}},
6230 {"mtivor14", XSPR(31,467,414), XSPR_MASK
, BOOKE
, 0, {RS
}},
6231 {"mtivor15", XSPR(31,467,415), XSPR_MASK
, BOOKE
, 0, {RS
}},
6232 {"mtspefscr", XSPR(31,467,512), XSPR_MASK
, PPCSPE
, 0, {RS
}},
6233 {"mtbbear", XSPR(31,467,513), XSPR_MASK
, PPCBRLK
, 0, {RS
}},
6234 {"mtbbtar", XSPR(31,467,514), XSPR_MASK
, PPCBRLK
, 0, {RS
}},
6235 {"mtivor32", XSPR(31,467,528), XSPR_MASK
, PPCSPE
|E6500
, 0, {RS
}},
6236 {"mtivor33", XSPR(31,467,529), XSPR_MASK
, PPCSPE
|E6500
, 0, {RS
}},
6237 {"mtivor34", XSPR(31,467,530), XSPR_MASK
, PPCSPE
, 0, {RS
}},
6238 {"mtivor35", XSPR(31,467,531), XSPR_MASK
, PPCPMR
, 0, {RS
}},
6239 {"mtibatu", XSPR(31,467,528), XSPRBAT_MASK
, PPC
, TITAN
, {SPRBAT
, RS
}},
6240 {"mtibatl", XSPR(31,467,529), XSPRBAT_MASK
, PPC
, TITAN
, {SPRBAT
, RS
}},
6241 {"mtdbatu", XSPR(31,467,536), XSPRBAT_MASK
, PPC
, TITAN
, {SPRBAT
, RS
}},
6242 {"mtdbatl", XSPR(31,467,537), XSPRBAT_MASK
, PPC
, TITAN
, {SPRBAT
, RS
}},
6243 {"mtmcsrr0", XSPR(31,467,570), XSPR_MASK
, PPCRFMCI
, 0, {RS
}},
6244 {"mtmcsrr1", XSPR(31,467,571), XSPR_MASK
, PPCRFMCI
, 0, {RS
}},
6245 {"mtmcsr", XSPR(31,467,572), XSPR_MASK
, PPCRFMCI
, 0, {RS
}},
6246 {"mtivndx", XSPR(31,467,880), XSPR_MASK
, TITAN
, 0, {RS
}},
6247 {"mtdvndx", XSPR(31,467,881), XSPR_MASK
, TITAN
, 0, {RS
}},
6248 {"mtivlim", XSPR(31,467,882), XSPR_MASK
, TITAN
, 0, {RS
}},
6249 {"mtdvlim", XSPR(31,467,883), XSPR_MASK
, TITAN
, 0, {RS
}},
6250 {"mtclcsr", XSPR(31,467,884), XSPR_MASK
, TITAN
, 0, {RS
}},
6251 {"mtccr1", XSPR(31,467,888), XSPR_MASK
, TITAN
, 0, {RS
}},
6252 {"mtppr", XSPR(31,467,896), XSPR_MASK
, POWER7
, 0, {RS
}},
6253 {"mtppr32", XSPR(31,467,898), XSPR_MASK
, POWER7
, 0, {RS
}},
6254 {"mtummcr0", XSPR(31,467,936), XSPR_MASK
, PPC750
, 0, {RS
}},
6255 {"mtupmc1", XSPR(31,467,937), XSPR_MASK
, PPC750
, 0, {RS
}},
6256 {"mtupmc2", XSPR(31,467,938), XSPR_MASK
, PPC750
, 0, {RS
}},
6257 {"mtusia", XSPR(31,467,939), XSPR_MASK
, PPC750
, 0, {RS
}},
6258 {"mtummcr1", XSPR(31,467,940), XSPR_MASK
, PPC750
, 0, {RS
}},
6259 {"mtupmc3", XSPR(31,467,941), XSPR_MASK
, PPC750
, 0, {RS
}},
6260 {"mtupmc4", XSPR(31,467,942), XSPR_MASK
, PPC750
, 0, {RS
}},
6261 {"mtzpr", XSPR(31,467,944), XSPR_MASK
, PPC403
, 0, {RS
}},
6262 {"mtpid", XSPR(31,467,945), XSPR_MASK
, PPC403
, 0, {RS
}},
6263 {"mtrmmucr", XSPR(31,467,946), XSPR_MASK
, TITAN
, 0, {RS
}},
6264 {"mtccr0", XSPR(31,467,947), XSPR_MASK
, PPC405
|TITAN
, 0, {RS
}},
6265 {"mtiac3", XSPR(31,467,948), XSPR_MASK
, PPC405
, 0, {RS
}},
6266 {"mtiac4", XSPR(31,467,949), XSPR_MASK
, PPC405
, 0, {RS
}},
6267 {"mtdvc1", XSPR(31,467,950), XSPR_MASK
, PPC405
, 0, {RS
}},
6268 {"mtdvc2", XSPR(31,467,951), XSPR_MASK
, PPC405
, 0, {RS
}},
6269 {"mtmmcr0", XSPR(31,467,952), XSPR_MASK
, PPC750
, 0, {RS
}},
6270 {"mtpmc1", XSPR(31,467,953), XSPR_MASK
, PPC750
, 0, {RS
}},
6271 {"mtsgr", XSPR(31,467,953), XSPR_MASK
, PPC403
, 0, {RS
}},
6272 {"mtdcwr", XSPR(31,467,954), XSPR_MASK
, PPC403
, 0, {RS
}},
6273 {"mtpmc2", XSPR(31,467,954), XSPR_MASK
, PPC750
, 0, {RS
}},
6274 {"mtsia", XSPR(31,467,955), XSPR_MASK
, PPC750
, 0, {RS
}},
6275 {"mtsler", XSPR(31,467,955), XSPR_MASK
, PPC405
, 0, {RS
}},
6276 {"mtmmcr1", XSPR(31,467,956), XSPR_MASK
, PPC750
, 0, {RS
}},
6277 {"mtsu0r", XSPR(31,467,956), XSPR_MASK
, PPC405
, 0, {RS
}},
6278 {"mtdbcr1", XSPR(31,467,957), XSPR_MASK
, PPC405
, 0, {RS
}},
6279 {"mtpmc3", XSPR(31,467,957), XSPR_MASK
, PPC750
, 0, {RS
}},
6280 {"mtpmc4", XSPR(31,467,958), XSPR_MASK
, PPC750
, 0, {RS
}},
6281 {"mticdbdr", XSPR(31,467,979), XSPR_MASK
, PPC403
, 0, {RS
}},
6282 {"mtesr", XSPR(31,467,980), XSPR_MASK
, PPC403
, 0, {RS
}},
6283 {"mtdear", XSPR(31,467,981), XSPR_MASK
, PPC403
, 0, {RS
}},
6284 {"mtevpr", XSPR(31,467,982), XSPR_MASK
, PPC403
, 0, {RS
}},
6285 {"mtcdbcr", XSPR(31,467,983), XSPR_MASK
, PPC403
, 0, {RS
}},
6286 {"mttsr", XSPR(31,467,984), XSPR_MASK
, PPC403
, 0, {RS
}},
6287 {"mttcr", XSPR(31,467,986), XSPR_MASK
, PPC403
, 0, {RS
}},
6288 {"mtpit", XSPR(31,467,987), XSPR_MASK
, PPC403
, 0, {RS
}},
6289 {"mttbhi", XSPR(31,467,988), XSPR_MASK
, PPC403
, 0, {RS
}},
6290 {"mttblo", XSPR(31,467,989), XSPR_MASK
, PPC403
, 0, {RS
}},
6291 {"mtsrr2", XSPR(31,467,990), XSPR_MASK
, PPC403
, 0, {RS
}},
6292 {"mtsrr3", XSPR(31,467,991), XSPR_MASK
, PPC403
, 0, {RS
}},
6293 {"mtdbsr", XSPR(31,467,1008), XSPR_MASK
, PPC403
, 0, {RS
}},
6294 {"mtdbdr", XSPR(31,467,1011), XSPR_MASK
, TITAN
, 0, {RS
}},
6295 {"mtdbcr0", XSPR(31,467,1010), XSPR_MASK
, PPC405
, 0, {RS
}},
6296 {"mtiac1", XSPR(31,467,1012), XSPR_MASK
, PPC403
, 0, {RS
}},
6297 {"mtiac2", XSPR(31,467,1013), XSPR_MASK
, PPC403
, 0, {RS
}},
6298 {"mtdac1", XSPR(31,467,1014), XSPR_MASK
, PPC403
, 0, {RS
}},
6299 {"mtdac2", XSPR(31,467,1015), XSPR_MASK
, PPC403
, 0, {RS
}},
6300 {"mtl2cr", XSPR(31,467,1017), XSPR_MASK
, PPC750
, 0, {RS
}},
6301 {"mtdccr", XSPR(31,467,1018), XSPR_MASK
, PPC403
, 0, {RS
}},
6302 {"mticcr", XSPR(31,467,1019), XSPR_MASK
, PPC403
, 0, {RS
}},
6303 {"mtictc", XSPR(31,467,1019), XSPR_MASK
, PPC750
, 0, {RS
}},
6304 {"mtpbl1", XSPR(31,467,1020), XSPR_MASK
, PPC403
, 0, {RS
}},
6305 {"mtthrm1", XSPR(31,467,1020), XSPR_MASK
, PPC750
, 0, {RS
}},
6306 {"mtpbu1", XSPR(31,467,1021), XSPR_MASK
, PPC403
, 0, {RS
}},
6307 {"mtthrm2", XSPR(31,467,1021), XSPR_MASK
, PPC750
, 0, {RS
}},
6308 {"mtpbl2", XSPR(31,467,1022), XSPR_MASK
, PPC403
, 0, {RS
}},
6309 {"mtthrm3", XSPR(31,467,1022), XSPR_MASK
, PPC750
, 0, {RS
}},
6310 {"mtpbu2", XSPR(31,467,1023), XSPR_MASK
, PPC403
, 0, {RS
}},
6311 {"mtspr", X(31,467), X_MASK
, COM
, 0, {SPR
, RS
}},
6313 {"dcbi", X(31,470), XRT_MASK
, PPC
, 0, {RA0
, RB
}},
6315 {"nand", XRC(31,476,0), X_MASK
, COM
, 0, {RA
, RS
, RB
}},
6316 {"nand.", XRC(31,476,1), X_MASK
, COM
, 0, {RA
, RS
, RB
}},
6318 {"dsn", X(31,483), XRT_MASK
, E500MC
, 0, {RA
, RB
}},
6320 {"dcread", X(31,486), X_MASK
, PPC403
|PPC440
, PPCA2
, {RT
, RA0
, RB
}},
6322 {"icbtls", X(31,486), X_MASK
, PPCCHLK
|PPC476
|TITAN
, 0, {CT
, RA0
, RB
}},
6324 {"stvxl", X(31,487), X_MASK
, PPCVEC
, 0, {VS
, RA0
, RB
}},
6326 {"nabs", XO(31,488,0,0), XORB_MASK
, M601
, 0, {RT
, RA
}},
6327 {"nabs.", XO(31,488,0,1), XORB_MASK
, M601
, 0, {RT
, RA
}},
6329 {"divd", XO(31,489,0,0), XO_MASK
, PPC64
, 0, {RT
, RA
, RB
}},
6330 {"divd.", XO(31,489,0,1), XO_MASK
, PPC64
, 0, {RT
, RA
, RB
}},
6332 {"divw", XO(31,491,0,0), XO_MASK
, PPC
, 0, {RT
, RA
, RB
}},
6333 {"divw.", XO(31,491,0,1), XO_MASK
, PPC
, 0, {RT
, RA
, RB
}},
6335 {"icbtlse", X(31,494), X_MASK
, PPCCHLK
, E500MC
, {CT
, RA
, RB
}},
6337 {"slbia", X(31,498), 0xff1fffff, POWER6
, 0, {IH
}},
6338 {"slbia", X(31,498), 0xffffffff, PPC64
, POWER6
, {0}},
6340 {"cli", X(31,502), XRB_MASK
, POWER
, 0, {RT
, RA
}},
6342 {"popcntd", X(31,506), XRB_MASK
, POWER7
|PPCA2
, 0, {RA
, RS
}},
6344 {"cmpb", X(31,508), X_MASK
, POWER6
|PPCA2
|PPC476
, 0, {RA
, RS
, RB
}},
6346 {"mcrxr", X(31,512), XBFRARB_MASK
, COM
, POWER7
, {BF
}},
6348 {"lbdcbx", X(31,514), X_MASK
, E200Z4
, 0, {RT
, RA
, RB
}},
6349 {"lbdx", X(31,515), X_MASK
, E500MC
|E200Z4
, 0, {RT
, RA
, RB
}},
6351 {"bblels", X(31,518), X_MASK
, PPCBRLK
, 0, {0}},
6353 {"lvlx", X(31,519), X_MASK
, CELL
, 0, {VD
, RA0
, RB
}},
6354 {"lbfcmux", APU(31,519,0), APU_MASK
, PPC405
, 0, {FCRT
, RA
, RB
}},
6356 {"subfco", XO(31,8,1,0), XO_MASK
, PPCCOM
, 0, {RT
, RA
, RB
}},
6357 {"sfo", XO(31,8,1,0), XO_MASK
, PWRCOM
, 0, {RT
, RA
, RB
}},
6358 {"subco", XO(31,8,1,0), XO_MASK
, PPCCOM
, 0, {RT
, RB
, RA
}},
6359 {"subfco.", XO(31,8,1,1), XO_MASK
, PPCCOM
, 0, {RT
, RA
, RB
}},
6360 {"sfo.", XO(31,8,1,1), XO_MASK
, PWRCOM
, 0, {RT
, RA
, RB
}},
6361 {"subco.", XO(31,8,1,1), XO_MASK
, PPCCOM
, 0, {RT
, RB
, RA
}},
6363 {"addco", XO(31,10,1,0), XO_MASK
, PPCCOM
, 0, {RT
, RA
, RB
}},
6364 {"ao", XO(31,10,1,0), XO_MASK
, PWRCOM
, 0, {RT
, RA
, RB
}},
6365 {"addco.", XO(31,10,1,1), XO_MASK
, PPCCOM
, 0, {RT
, RA
, RB
}},
6366 {"ao.", XO(31,10,1,1), XO_MASK
, PWRCOM
, 0, {RT
, RA
, RB
}},
6368 {"lxsspx", X(31,524), XX1_MASK
, PPCVSX2
, 0, {XT6
, RA0
, RB
}},
6370 {"clcs", X(31,531), XRB_MASK
, M601
, 0, {RT
, RA
}},
6372 {"ldbrx", X(31,532), X_MASK
, CELL
|POWER7
|PPCA2
, 0, {RT
, RA0
, RB
}},
6374 {"lswx", X(31,533), X_MASK
, PPCCOM
, E500
|E500MC
, {RT
, RAX
, RBX
}},
6375 {"lsx", X(31,533), X_MASK
, PWRCOM
, 0, {RT
, RA
, RB
}},
6377 {"lwbrx", X(31,534), X_MASK
, PPCCOM
, 0, {RT
, RA0
, RB
}},
6378 {"lbrx", X(31,534), X_MASK
, PWRCOM
, 0, {RT
, RA
, RB
}},
6380 {"lfsx", X(31,535), X_MASK
, COM
, PPCEFS
, {FRT
, RA0
, RB
}},
6382 {"srw", XRC(31,536,0), X_MASK
, PPCCOM
, 0, {RA
, RS
, RB
}},
6383 {"sr", XRC(31,536,0), X_MASK
, PWRCOM
, 0, {RA
, RS
, RB
}},
6384 {"srw.", XRC(31,536,1), X_MASK
, PPCCOM
, 0, {RA
, RS
, RB
}},
6385 {"sr.", XRC(31,536,1), X_MASK
, PWRCOM
, 0, {RA
, RS
, RB
}},
6387 {"rrib", XRC(31,537,0), X_MASK
, M601
, 0, {RA
, RS
, RB
}},
6388 {"rrib.", XRC(31,537,1), X_MASK
, M601
, 0, {RA
, RS
, RB
}},
6390 {"cnttzw", XRC(31,538,0), XRB_MASK
, POWER9
, 0, {RA
, RS
}},
6391 {"cnttzw.", XRC(31,538,1), XRB_MASK
, POWER9
, 0, {RA
, RS
}},
6393 {"srd", XRC(31,539,0), X_MASK
, PPC64
, 0, {RA
, RS
, RB
}},
6394 {"srd.", XRC(31,539,1), X_MASK
, PPC64
, 0, {RA
, RS
, RB
}},
6396 {"maskir", XRC(31,541,0), X_MASK
, M601
, 0, {RA
, RS
, RB
}},
6397 {"maskir.", XRC(31,541,1), X_MASK
, M601
, 0, {RA
, RS
, RB
}},
6399 {"lhdcbx", X(31,546), X_MASK
, E200Z4
, 0, {RT
, RA
, RB
}},
6400 {"lhdx", X(31,547), X_MASK
, E500MC
|E200Z4
, 0, {RT
, RA
, RB
}},
6402 {"lvtrx", X(31,549), X_MASK
, E6500
, 0, {VD
, RA0
, RB
}},
6404 {"bbelr", X(31,550), X_MASK
, PPCBRLK
, 0, {0}},
6406 {"lvrx", X(31,551), X_MASK
, CELL
, 0, {VD
, RA0
, RB
}},
6407 {"lhfcmux", APU(31,551,0), APU_MASK
, PPC405
, 0, {FCRT
, RA
, RB
}},
6409 {"subfo", XO(31,40,1,0), XO_MASK
, PPC
, 0, {RT
, RA
, RB
}},
6410 {"subo", XO(31,40,1,0), XO_MASK
, PPC
, 0, {RT
, RB
, RA
}},
6411 {"subfo.", XO(31,40,1,1), XO_MASK
, PPC
, 0, {RT
, RA
, RB
}},
6412 {"subo.", XO(31,40,1,1), XO_MASK
, PPC
, 0, {RT
, RB
, RA
}},
6414 {"tlbsync", X(31,566), 0xffffffff, PPC
, 0, {0}},
6416 {"lfsux", X(31,567), X_MASK
, COM
, PPCEFS
, {FRT
, RAS
, RB
}},
6418 {"cnttzd", XRC(31,570,0), XRB_MASK
, POWER9
, 0, {RA
, RS
}},
6419 {"cnttzd.", XRC(31,570,1), XRB_MASK
, POWER9
, 0, {RA
, RS
}},
6421 {"mcrxrx", X(31,576), XBFRARB_MASK
, POWER9
, 0, {BF
}},
6423 {"lwdcbx", X(31,578), X_MASK
, E200Z4
, 0, {RT
, RA
, RB
}},
6424 {"lwdx", X(31,579), X_MASK
, E500MC
|E200Z4
, 0, {RT
, RA
, RB
}},
6426 {"lvtlx", X(31,581), X_MASK
, E6500
, 0, {VD
, RA0
, RB
}},
6428 {"lwat", X(31,582), X_MASK
, POWER9
, 0, {RT
, RA0
, FC
}},
6430 {"lwfcmux", APU(31,583,0), APU_MASK
, PPC405
, 0, {FCRT
, RA
, RB
}},
6432 {"lxsdx", X(31,588), XX1_MASK
, PPCVSX
, 0, {XT6
, RA0
, RB
}},
6434 {"mfsr", X(31,595), XRB_MASK
|(1<<20), COM
, NON32
, {RT
, SR
}},
6436 {"lswi", X(31,597), X_MASK
, PPCCOM
, E500
|E500MC
, {RT
, RAX
, NBI
}},
6437 {"lsi", X(31,597), X_MASK
, PWRCOM
, 0, {RT
, RA0
, NB
}},
6439 {"hwsync", XSYNC(31,598,0), 0xffffffff, POWER4
, BOOKE
|PPC476
, {0}},
6440 {"lwsync", XSYNC(31,598,1), 0xffffffff, PPC
, E500
, {0}},
6441 {"ptesync", XSYNC(31,598,2), 0xffffffff, PPC64
, 0, {0}},
6442 {"sync", X(31,598), XSYNCLE_MASK
, E6500
, 0, {LS
, ESYNC
}},
6443 {"sync", X(31,598), XSYNC_MASK
, PPCCOM
, BOOKE
|PPC476
, {LS
}},
6444 {"msync", X(31,598), 0xffffffff, BOOKE
|PPCA2
|PPC476
, 0, {0}},
6445 {"sync", X(31,598), 0xffffffff, BOOKE
|PPC476
, E6500
, {0}},
6446 {"lwsync", X(31,598), 0xffffffff, E500
, 0, {0}},
6447 {"dcs", X(31,598), 0xffffffff, PWRCOM
, 0, {0}},
6449 {"lfdx", X(31,599), X_MASK
, COM
, PPCEFS
, {FRT
, RA0
, RB
}},
6451 {"mffgpr", XRC(31,607,0), XRA_MASK
, POWER6
, POWER7
, {FRT
, RB
}},
6452 {"lfdepx", X(31,607), X_MASK
, E500MC
|PPCA2
, 0, {FRT
, RA0
, RB
}},
6454 {"lddx", X(31,611), X_MASK
, E500MC
, 0, {RT
, RA
, RB
}},
6456 {"lvswx", X(31,613), X_MASK
, E6500
, 0, {VD
, RA0
, RB
}},
6458 {"ldat", X(31,614), X_MASK
, POWER9
, 0, {RT
, RA0
, FC
}},
6460 {"lqfcmux", APU(31,615,0), APU_MASK
, PPC405
, 0, {FCRT
, RA
, RB
}},
6462 {"nego", XO(31,104,1,0), XORB_MASK
, COM
, 0, {RT
, RA
}},
6463 {"nego.", XO(31,104,1,1), XORB_MASK
, COM
, 0, {RT
, RA
}},
6465 {"mulo", XO(31,107,1,0), XO_MASK
, M601
, 0, {RT
, RA
, RB
}},
6466 {"mulo.", XO(31,107,1,1), XO_MASK
, M601
, 0, {RT
, RA
, RB
}},
6468 {"mfsri", X(31,627), X_MASK
, M601
, 0, {RT
, RA
, RB
}},
6470 {"dclst", X(31,630), XRB_MASK
, M601
, 0, {RS
, RA
}},
6472 {"lfdux", X(31,631), X_MASK
, COM
, PPCEFS
, {FRT
, RAS
, RB
}},
6474 {"stbdcbx", X(31,642), X_MASK
, E200Z4
, 0, {RS
, RA
, RB
}},
6475 {"stbdx", X(31,643), X_MASK
, E500MC
|E200Z4
, 0, {RS
, RA
, RB
}},
6477 {"stvlx", X(31,647), X_MASK
, CELL
, 0, {VS
, RA0
, RB
}},
6478 {"stbfcmux", APU(31,647,0), APU_MASK
, PPC405
, 0, {FCRT
, RA
, RB
}},
6480 {"stxsspx", X(31,652), XX1_MASK
, PPCVSX2
, 0, {XS6
, RA0
, RB
}},
6482 {"tbegin.", XRC(31,654,1), XRTLRARB_MASK
, PPCHTM
, 0, {HTM_R
}},
6484 {"subfeo", XO(31,136,1,0), XO_MASK
, PPCCOM
, 0, {RT
, RA
, RB
}},
6485 {"sfeo", XO(31,136,1,0), XO_MASK
, PWRCOM
, 0, {RT
, RA
, RB
}},
6486 {"subfeo.", XO(31,136,1,1), XO_MASK
, PPCCOM
, 0, {RT
, RA
, RB
}},
6487 {"sfeo.", XO(31,136,1,1), XO_MASK
, PWRCOM
, 0, {RT
, RA
, RB
}},
6489 {"addeo", XO(31,138,1,0), XO_MASK
, PPCCOM
, 0, {RT
, RA
, RB
}},
6490 {"aeo", XO(31,138,1,0), XO_MASK
, PWRCOM
, 0, {RT
, RA
, RB
}},
6491 {"addeo.", XO(31,138,1,1), XO_MASK
, PPCCOM
, 0, {RT
, RA
, RB
}},
6492 {"aeo.", XO(31,138,1,1), XO_MASK
, PWRCOM
, 0, {RT
, RA
, RB
}},
6494 {"mfsrin", X(31,659), XRA_MASK
, PPC
, NON32
, {RT
, RB
}},
6496 {"stdbrx", X(31,660), X_MASK
, CELL
|POWER7
|PPCA2
, 0, {RS
, RA0
, RB
}},
6498 {"stswx", X(31,661), X_MASK
, PPCCOM
, E500
|E500MC
, {RS
, RA0
, RB
}},
6499 {"stsx", X(31,661), X_MASK
, PWRCOM
, 0, {RS
, RA0
, RB
}},
6501 {"stwbrx", X(31,662), X_MASK
, PPCCOM
, 0, {RS
, RA0
, RB
}},
6502 {"stbrx", X(31,662), X_MASK
, PWRCOM
, 0, {RS
, RA0
, RB
}},
6504 {"stfsx", X(31,663), X_MASK
, COM
, PPCEFS
, {FRS
, RA0
, RB
}},
6506 {"srq", XRC(31,664,0), X_MASK
, M601
, 0, {RA
, RS
, RB
}},
6507 {"srq.", XRC(31,664,1), X_MASK
, M601
, 0, {RA
, RS
, RB
}},
6509 {"sre", XRC(31,665,0), X_MASK
, M601
, 0, {RA
, RS
, RB
}},
6510 {"sre.", XRC(31,665,1), X_MASK
, M601
, 0, {RA
, RS
, RB
}},
6512 {"sthdcbx", X(31,674), X_MASK
, E200Z4
, 0, {RS
, RA
, RB
}},
6513 {"sthdx", X(31,675), X_MASK
, E500MC
|E200Z4
, 0, {RS
, RA
, RB
}},
6515 {"stvfrx", X(31,677), X_MASK
, E6500
, 0, {VS
, RA0
, RB
}},
6517 {"stvrx", X(31,679), X_MASK
, CELL
, 0, {VS
, RA0
, RB
}},
6518 {"sthfcmux", APU(31,679,0), APU_MASK
, PPC405
, 0, {FCRT
, RA
, RB
}},
6520 {"tendall.", XRC(31,686,1)|(1<<25), XRTRARB_MASK
, PPCHTM
, 0, {0}},
6521 {"tend.", XRC(31,686,1), XRTARARB_MASK
, PPCHTM
, 0, {HTM_A
}},
6523 {"stbcx.", XRC(31,694,1), X_MASK
, POWER8
|E6500
, 0, {RS
, RA0
, RB
}},
6525 {"stfsux", X(31,695), X_MASK
, COM
, PPCEFS
, {FRS
, RAS
, RB
}},
6527 {"sriq", XRC(31,696,0), X_MASK
, M601
, 0, {RA
, RS
, SH
}},
6528 {"sriq.", XRC(31,696,1), X_MASK
, M601
, 0, {RA
, RS
, SH
}},
6530 {"stwdcbx", X(31,706), X_MASK
, E200Z4
, 0, {RS
, RA
, RB
}},
6531 {"stwdx", X(31,707), X_MASK
, E500MC
|E200Z4
, 0, {RS
, RA
, RB
}},
6533 {"stvflx", X(31,709), X_MASK
, E6500
, 0, {VS
, RA0
, RB
}},
6535 {"stwat", X(31,710), X_MASK
, POWER9
, 0, {RS
, RA0
, FC
}},
6537 {"stwfcmux", APU(31,711,0), APU_MASK
, PPC405
, 0, {FCRT
, RA
, RB
}},
6539 {"stxsdx", X(31,716), XX1_MASK
, PPCVSX
, 0, {XS6
, RA0
, RB
}},
6541 {"tcheck", X(31,718), XRTBFRARB_MASK
, PPCHTM
, 0, {BF
}},
6543 {"subfzeo", XO(31,200,1,0), XORB_MASK
, PPCCOM
, 0, {RT
, RA
}},
6544 {"sfzeo", XO(31,200,1,0), XORB_MASK
, PWRCOM
, 0, {RT
, RA
}},
6545 {"subfzeo.", XO(31,200,1,1), XORB_MASK
, PPCCOM
, 0, {RT
, RA
}},
6546 {"sfzeo.", XO(31,200,1,1), XORB_MASK
, PWRCOM
, 0, {RT
, RA
}},
6548 {"addzeo", XO(31,202,1,0), XORB_MASK
, PPCCOM
, 0, {RT
, RA
}},
6549 {"azeo", XO(31,202,1,0), XORB_MASK
, PWRCOM
, 0, {RT
, RA
}},
6550 {"addzeo.", XO(31,202,1,1), XORB_MASK
, PPCCOM
, 0, {RT
, RA
}},
6551 {"azeo.", XO(31,202,1,1), XORB_MASK
, PWRCOM
, 0, {RT
, RA
}},
6553 {"stswi", X(31,725), X_MASK
, PPCCOM
, E500
|E500MC
, {RS
, RA0
, NB
}},
6554 {"stsi", X(31,725), X_MASK
, PWRCOM
, 0, {RS
, RA0
, NB
}},
6556 {"sthcx.", XRC(31,726,1), X_MASK
, POWER8
|E6500
, 0, {RS
, RA0
, RB
}},
6558 {"stfdx", X(31,727), X_MASK
, COM
, PPCEFS
, {FRS
, RA0
, RB
}},
6560 {"srlq", XRC(31,728,0), X_MASK
, M601
, 0, {RA
, RS
, RB
}},
6561 {"srlq.", XRC(31,728,1), X_MASK
, M601
, 0, {RA
, RS
, RB
}},
6563 {"sreq", XRC(31,729,0), X_MASK
, M601
, 0, {RA
, RS
, RB
}},
6564 {"sreq.", XRC(31,729,1), X_MASK
, M601
, 0, {RA
, RS
, RB
}},
6566 {"mftgpr", XRC(31,735,0), XRA_MASK
, POWER6
, POWER7
, {RT
, FRB
}},
6567 {"stfdepx", X(31,735), X_MASK
, E500MC
|PPCA2
, 0, {FRS
, RA0
, RB
}},
6569 {"stddx", X(31,739), X_MASK
, E500MC
, 0, {RS
, RA
, RB
}},
6571 {"stvswx", X(31,741), X_MASK
, E6500
, 0, {VS
, RA0
, RB
}},
6573 {"stdat", X(31,742), X_MASK
, POWER9
, 0, {RS
, RA0
, FC
}},
6575 {"stqfcmux", APU(31,743,0), APU_MASK
, PPC405
, 0, {FCRT
, RA
, RB
}},
6577 {"subfmeo", XO(31,232,1,0), XORB_MASK
, PPCCOM
, 0, {RT
, RA
}},
6578 {"sfmeo", XO(31,232,1,0), XORB_MASK
, PWRCOM
, 0, {RT
, RA
}},
6579 {"subfmeo.", XO(31,232,1,1), XORB_MASK
, PPCCOM
, 0, {RT
, RA
}},
6580 {"sfmeo.", XO(31,232,1,1), XORB_MASK
, PWRCOM
, 0, {RT
, RA
}},
6582 {"mulldo", XO(31,233,1,0), XO_MASK
, PPC64
, 0, {RT
, RA
, RB
}},
6583 {"mulldo.", XO(31,233,1,1), XO_MASK
, PPC64
, 0, {RT
, RA
, RB
}},
6585 {"addmeo", XO(31,234,1,0), XORB_MASK
, PPCCOM
, 0, {RT
, RA
}},
6586 {"ameo", XO(31,234,1,0), XORB_MASK
, PWRCOM
, 0, {RT
, RA
}},
6587 {"addmeo.", XO(31,234,1,1), XORB_MASK
, PPCCOM
, 0, {RT
, RA
}},
6588 {"ameo.", XO(31,234,1,1), XORB_MASK
, PWRCOM
, 0, {RT
, RA
}},
6590 {"mullwo", XO(31,235,1,0), XO_MASK
, PPCCOM
, 0, {RT
, RA
, RB
}},
6591 {"mulso", XO(31,235,1,0), XO_MASK
, PWRCOM
, 0, {RT
, RA
, RB
}},
6592 {"mullwo.", XO(31,235,1,1), XO_MASK
, PPCCOM
, 0, {RT
, RA
, RB
}},
6593 {"mulso.", XO(31,235,1,1), XO_MASK
, PWRCOM
, 0, {RT
, RA
, RB
}},
6595 {"tsuspend.", XRCL(31,750,0,1), XRTRARB_MASK
,PPCHTM
, 0, {0}},
6596 {"tresume.", XRCL(31,750,1,1), XRTRARB_MASK
,PPCHTM
, 0, {0}},
6597 {"tsr.", XRC(31,750,1), XRTLRARB_MASK
,PPCHTM
, 0, {L
}},
6599 {"darn", X(31,755), XLRAND_MASK
, POWER9
, 0, {RT
, LRAND
}},
6601 {"dcba", X(31,758), XRT_MASK
, PPC405
|PPC7450
|BOOKE
|PPCA2
|PPC476
, 0, {RA0
, RB
}},
6602 {"dcbal", XOPL(31,758,1), XRT_MASK
, E500MC
, 0, {RA0
, RB
}},
6604 {"stfdux", X(31,759), X_MASK
, COM
, PPCEFS
, {FRS
, RAS
, RB
}},
6606 {"srliq", XRC(31,760,0), X_MASK
, M601
, 0, {RA
, RS
, SH
}},
6607 {"srliq.", XRC(31,760,1), X_MASK
, M601
, 0, {RA
, RS
, SH
}},
6609 {"lvsm", X(31,773), X_MASK
, E6500
, 0, {VD
, RA0
, RB
}},
6611 {"copy", XOPL(31,774,1), XRT_MASK
, POWER9
, 0, {RA0
, RB
}},
6613 {"stvepxl", X(31,775), X_MASK
, E6500
, 0, {VS
, RA0
, RB
}},
6614 {"lvlxl", X(31,775), X_MASK
, CELL
, 0, {VD
, RA0
, RB
}},
6615 {"ldfcmux", APU(31,775,0), APU_MASK
, PPC405
, 0, {FCRT
, RA
, RB
}},
6617 {"dozo", XO(31,264,1,0), XO_MASK
, M601
, 0, {RT
, RA
, RB
}},
6618 {"dozo.", XO(31,264,1,1), XO_MASK
, M601
, 0, {RT
, RA
, RB
}},
6620 {"addo", XO(31,266,1,0), XO_MASK
, PPCCOM
, 0, {RT
, RA
, RB
}},
6621 {"caxo", XO(31,266,1,0), XO_MASK
, PWRCOM
, 0, {RT
, RA
, RB
}},
6622 {"addo.", XO(31,266,1,1), XO_MASK
, PPCCOM
, 0, {RT
, RA
, RB
}},
6623 {"caxo.", XO(31,266,1,1), XO_MASK
, PWRCOM
, 0, {RT
, RA
, RB
}},
6625 {"modsd", X(31,777), X_MASK
, POWER9
, 0, {RT
, RA
, RB
}},
6626 {"modsw", X(31,779), X_MASK
, POWER9
, 0, {RT
, RA
, RB
}},
6628 {"lxvw4x", X(31,780), XX1_MASK
, PPCVSX
, 0, {XT6
, RA0
, RB
}},
6629 {"lxsibzx", X(31,781), XX1_MASK
, PPCVSX3
, 0, {XT6
, RA0
, RB
}},
6631 {"tabortwc.", XRC(31,782,1), X_MASK
, PPCHTM
, 0, {TO
, RA
, RB
}},
6633 {"tlbivax", X(31,786), XRT_MASK
, BOOKE
|PPCA2
|PPC476
, 0, {RA0
, RB
}},
6635 {"lwzcix", X(31,789), X_MASK
, POWER6
, 0, {RT
, RA0
, RB
}},
6637 {"lhbrx", X(31,790), X_MASK
, COM
, 0, {RT
, RA0
, RB
}},
6639 {"lfdpx", X(31,791), X_MASK
|Q_MASK
, POWER6
, POWER7
, {FRTp
, RA0
, RB
}},
6640 {"lfqx", X(31,791), X_MASK
, POWER2
, 0, {FRT
, RA
, RB
}},
6642 {"sraw", XRC(31,792,0), X_MASK
, PPCCOM
, 0, {RA
, RS
, RB
}},
6643 {"sra", XRC(31,792,0), X_MASK
, PWRCOM
, 0, {RA
, RS
, RB
}},
6644 {"sraw.", XRC(31,792,1), X_MASK
, PPCCOM
, 0, {RA
, RS
, RB
}},
6645 {"sra.", XRC(31,792,1), X_MASK
, PWRCOM
, 0, {RA
, RS
, RB
}},
6647 {"srad", XRC(31,794,0), X_MASK
, PPC64
, 0, {RA
, RS
, RB
}},
6648 {"srad.", XRC(31,794,1), X_MASK
, PPC64
, 0, {RA
, RS
, RB
}},
6650 {"evlddepx", VX (31, 1598), VX_MASK
, PPCSPE
, 0, {RT
, RA
, RB
}},
6651 {"lfddx", X(31,803), X_MASK
, E500MC
, 0, {FRT
, RA
, RB
}},
6653 {"lvtrxl", X(31,805), X_MASK
, E6500
, 0, {VD
, RA0
, RB
}},
6654 {"stvepx", X(31,807), X_MASK
, E6500
, 0, {VS
, RA0
, RB
}},
6655 {"lvrxl", X(31,807), X_MASK
, CELL
, 0, {VD
, RA0
, RB
}},
6657 {"lxvh8x", X(31,812), XX1_MASK
, PPCVSX3
, 0, {XT6
, RA0
, RB
}},
6658 {"lxsihzx", X(31,813), XX1_MASK
, PPCVSX3
, 0, {XT6
, RA0
, RB
}},
6660 {"tabortdc.", XRC(31,814,1), X_MASK
, PPCHTM
, 0, {TO
, RA
, RB
}},
6662 {"rac", X(31,818), X_MASK
, M601
, 0, {RT
, RA
, RB
}},
6664 {"erativax", X(31,819), X_MASK
, PPCA2
, 0, {RS
, RA0
, RB
}},
6666 {"lhzcix", X(31,821), X_MASK
, POWER6
, 0, {RT
, RA0
, RB
}},
6668 {"dss", XDSS(31,822,0), XDSS_MASK
, PPCVEC
, 0, {STRM
}},
6670 {"lfqux", X(31,823), X_MASK
, POWER2
, 0, {FRT
, RA
, RB
}},
6672 {"srawi", XRC(31,824,0), X_MASK
, PPCCOM
, 0, {RA
, RS
, SH
}},
6673 {"srai", XRC(31,824,0), X_MASK
, PWRCOM
, 0, {RA
, RS
, SH
}},
6674 {"srawi.", XRC(31,824,1), X_MASK
, PPCCOM
, 0, {RA
, RS
, SH
}},
6675 {"srai.", XRC(31,824,1), X_MASK
, PWRCOM
, 0, {RA
, RS
, SH
}},
6677 {"sradi", XS(31,413,0), XS_MASK
, PPC64
, 0, {RA
, RS
, SH6
}},
6678 {"sradi.", XS(31,413,1), XS_MASK
, PPC64
, 0, {RA
, RS
, SH6
}},
6680 {"lvtlxl", X(31,837), X_MASK
, E6500
, 0, {VD
, RA0
, RB
}},
6682 {"cpabort", X(31,838), XRTRARB_MASK
,POWER9
, 0, {0}},
6684 {"divo", XO(31,331,1,0), XO_MASK
, M601
, 0, {RT
, RA
, RB
}},
6685 {"divo.", XO(31,331,1,1), XO_MASK
, M601
, 0, {RT
, RA
, RB
}},
6687 {"lxvd2x", X(31,844), XX1_MASK
, PPCVSX
, 0, {XT6
, RA0
, RB
}},
6688 {"lxvx", X(31,844), XX1_MASK
, POWER8
, POWER9
|PPCVSX3
, {XT6
, RA0
, RB
}},
6690 {"tabortwci.", XRC(31,846,1), X_MASK
, PPCHTM
, 0, {TO
, RA
, HTM_SI
}},
6692 {"tlbsrx.", XRC(31,850,1), XRT_MASK
, PPCA2
, 0, {RA0
, RB
}},
6694 {"slbiag", X(31,850), XRARB_MASK
, POWER9
, 0, {RS
}},
6695 {"slbmfev", X(31,851), XRLA_MASK
, POWER9
, 0, {RT
, RB
, A_L
}},
6696 {"slbmfev", X(31,851), XRA_MASK
, PPC64
, POWER9
, {RT
, RB
}},
6698 {"lbzcix", X(31,853), X_MASK
, POWER6
, 0, {RT
, RA0
, RB
}},
6700 {"eieio", X(31,854), 0xffffffff, PPC
, BOOKE
|PPCA2
|PPC476
, {0}},
6701 {"mbar", X(31,854), X_MASK
, BOOKE
|PPCA2
|PPC476
, 0, {MO
}},
6702 {"eieio", XMBAR(31,854,1),0xffffffff, E500
, 0, {0}},
6703 {"eieio", X(31,854), 0xffffffff, PPCA2
|PPC476
, 0, {0}},
6705 {"lfiwax", X(31,855), X_MASK
, POWER6
|PPCA2
|PPC476
, 0, {FRT
, RA0
, RB
}},
6707 {"lvswxl", X(31,869), X_MASK
, E6500
, 0, {VD
, RA0
, RB
}},
6709 {"abso", XO(31,360,1,0), XORB_MASK
, M601
, 0, {RT
, RA
}},
6710 {"abso.", XO(31,360,1,1), XORB_MASK
, M601
, 0, {RT
, RA
}},
6712 {"divso", XO(31,363,1,0), XO_MASK
, M601
, 0, {RT
, RA
, RB
}},
6713 {"divso.", XO(31,363,1,1), XO_MASK
, M601
, 0, {RT
, RA
, RB
}},
6715 {"lxvb16x", X(31,876), XX1_MASK
, PPCVSX3
, 0, {XT6
, RA0
, RB
}},
6717 {"tabortdci.", XRC(31,878,1), X_MASK
, PPCHTM
, 0, {TO
, RA
, HTM_SI
}},
6719 {"rmieg", X(31,882), XRTRA_MASK
, POWER9
, 0, {RB
}},
6721 {"ldcix", X(31,885), X_MASK
, POWER6
, 0, {RT
, RA0
, RB
}},
6723 {"msgsync", X(31,886), 0xffffffff, POWER9
, 0, {0}},
6725 {"lfiwzx", X(31,887), X_MASK
, POWER7
|PPCA2
, 0, {FRT
, RA0
, RB
}},
6727 {"extswsli", XS(31,445,0), XS_MASK
, POWER9
, 0, {RA
, RS
, SH6
}},
6728 {"extswsli.", XS(31,445,1), XS_MASK
, POWER9
, 0, {RA
, RS
, SH6
}},
6730 {"paste.", XRCL(31,902,1,1),XRT_MASK
, POWER9
, 0, {RA0
, RB
}},
6732 {"stvlxl", X(31,903), X_MASK
, CELL
, 0, {VS
, RA0
, RB
}},
6733 {"stdfcmux", APU(31,903,0), APU_MASK
, PPC405
, 0, {FCRT
, RA
, RB
}},
6735 {"divdeuo", XO(31,393,1,0), XO_MASK
, POWER7
|PPCA2
, 0, {RT
, RA
, RB
}},
6736 {"divdeuo.", XO(31,393,1,1), XO_MASK
, POWER7
|PPCA2
, 0, {RT
, RA
, RB
}},
6737 {"divweuo", XO(31,395,1,0), XO_MASK
, POWER7
|PPCA2
, 0, {RT
, RA
, RB
}},
6738 {"divweuo.", XO(31,395,1,1), XO_MASK
, POWER7
|PPCA2
, 0, {RT
, RA
, RB
}},
6740 {"stxvw4x", X(31,908), XX1_MASK
, PPCVSX
, 0, {XS6
, RA0
, RB
}},
6741 {"stxsibx", X(31,909), XX1_MASK
, PPCVSX3
, 0, {XS6
, RA0
, RB
}},
6743 {"tabort.", XRC(31,910,1), XRTRB_MASK
, PPCHTM
, 0, {RA
}},
6745 {"tlbsx", XRC(31,914,0), X_MASK
, PPC403
|BOOKE
|PPCA2
|PPC476
, 0, {RTO
, RA0
, RB
}},
6746 {"tlbsx.", XRC(31,914,1), X_MASK
, PPC403
|BOOKE
|PPCA2
|PPC476
, 0, {RTO
, RA0
, RB
}},
6748 {"slbmfee", X(31,915), XRLA_MASK
, POWER9
, 0, {RT
, RB
, A_L
}},
6749 {"slbmfee", X(31,915), XRA_MASK
, PPC64
, POWER9
, {RT
, RB
}},
6751 {"stwcix", X(31,917), X_MASK
, POWER6
, 0, {RS
, RA0
, RB
}},
6753 {"sthbrx", X(31,918), X_MASK
, COM
, 0, {RS
, RA0
, RB
}},
6755 {"stfdpx", X(31,919), X_MASK
|Q_MASK
, POWER6
, POWER7
, {FRSp
, RA0
, RB
}},
6756 {"stfqx", X(31,919), X_MASK
, POWER2
, 0, {FRS
, RA0
, RB
}},
6758 {"sraq", XRC(31,920,0), X_MASK
, M601
, 0, {RA
, RS
, RB
}},
6759 {"sraq.", XRC(31,920,1), X_MASK
, M601
, 0, {RA
, RS
, RB
}},
6761 {"srea", XRC(31,921,0), X_MASK
, M601
, 0, {RA
, RS
, RB
}},
6762 {"srea.", XRC(31,921,1), X_MASK
, M601
, 0, {RA
, RS
, RB
}},
6764 {"extsh", XRC(31,922,0), XRB_MASK
, PPCCOM
, 0, {RA
, RS
}},
6765 {"exts", XRC(31,922,0), XRB_MASK
, PWRCOM
, 0, {RA
, RS
}},
6766 {"extsh.", XRC(31,922,1), XRB_MASK
, PPCCOM
, 0, {RA
, RS
}},
6767 {"exts.", XRC(31,922,1), XRB_MASK
, PWRCOM
, 0, {RA
, RS
}},
6769 {"evstddepx", VX (31, 1854), VX_MASK
, PPCSPE
, 0, {RT
, RA
, RB
}},
6770 {"stfddx", X(31,931), X_MASK
, E500MC
, 0, {FRS
, RA
, RB
}},
6772 {"stvfrxl", X(31,933), X_MASK
, E6500
, 0, {VS
, RA0
, RB
}},
6774 {"wclrone", XOPL2(31,934,2),XRT_MASK
, PPCA2
, 0, {RA0
, RB
}},
6775 {"wclrall", X(31,934), XRARB_MASK
, PPCA2
, 0, {L2
}},
6776 {"wclr", X(31,934), X_MASK
, PPCA2
, 0, {L2
, RA0
, RB
}},
6778 {"stvrxl", X(31,935), X_MASK
, CELL
, 0, {VS
, RA0
, RB
}},
6780 {"divdeo", XO(31,425,1,0), XO_MASK
, POWER7
|PPCA2
, 0, {RT
, RA
, RB
}},
6781 {"divdeo.", XO(31,425,1,1), XO_MASK
, POWER7
|PPCA2
, 0, {RT
, RA
, RB
}},
6782 {"divweo", XO(31,427,1,0), XO_MASK
, POWER7
|PPCA2
, 0, {RT
, RA
, RB
}},
6783 {"divweo.", XO(31,427,1,1), XO_MASK
, POWER7
|PPCA2
, 0, {RT
, RA
, RB
}},
6785 {"stxvh8x", X(31,940), XX1_MASK
, PPCVSX3
, 0, {XS6
, RA0
, RB
}},
6786 {"stxsihx", X(31,941), XX1_MASK
, PPCVSX3
, 0, {XS6
, RA0
, RB
}},
6788 {"treclaim.", XRC(31,942,1), XRTRB_MASK
, PPCHTM
, 0, {RA
}},
6790 {"tlbrehi", XTLB(31,946,0), XTLB_MASK
, PPC403
, PPCA2
, {RT
, RA
}},
6791 {"tlbrelo", XTLB(31,946,1), XTLB_MASK
, PPC403
, PPCA2
, {RT
, RA
}},
6792 {"tlbre", X(31,946), X_MASK
, PPC403
|BOOKE
|PPCA2
|PPC476
, 0, {RSO
, RAOPT
, SHO
}},
6794 {"sthcix", X(31,949), X_MASK
, POWER6
, 0, {RS
, RA0
, RB
}},
6796 {"icswepx", XRC(31,950,0), X_MASK
, PPCA2
, 0, {RS
, RA
, RB
}},
6797 {"icswepx.", XRC(31,950,1), X_MASK
, PPCA2
, 0, {RS
, RA
, RB
}},
6799 {"stfqux", X(31,951), X_MASK
, POWER2
, 0, {FRS
, RA
, RB
}},
6801 {"sraiq", XRC(31,952,0), X_MASK
, M601
, 0, {RA
, RS
, SH
}},
6802 {"sraiq.", XRC(31,952,1), X_MASK
, M601
, 0, {RA
, RS
, SH
}},
6804 {"extsb", XRC(31,954,0), XRB_MASK
, PPC
, 0, {RA
, RS
}},
6805 {"extsb.", XRC(31,954,1), XRB_MASK
, PPC
, 0, {RA
, RS
}},
6807 {"stvflxl", X(31,965), X_MASK
, E6500
, 0, {VS
, RA0
, RB
}},
6809 {"iccci", X(31,966), XRT_MASK
, PPC403
|PPC440
|PPC476
|TITAN
|PPCA2
, 0, {RAOPT
, RBOPT
}},
6810 {"ici", X(31,966), XRARB_MASK
, PPCA2
|PPC476
, 0, {CT
}},
6812 {"divduo", XO(31,457,1,0), XO_MASK
, PPC64
, 0, {RT
, RA
, RB
}},
6813 {"divduo.", XO(31,457,1,1), XO_MASK
, PPC64
, 0, {RT
, RA
, RB
}},
6815 {"divwuo", XO(31,459,1,0), XO_MASK
, PPC
, 0, {RT
, RA
, RB
}},
6816 {"divwuo.", XO(31,459,1,1), XO_MASK
, PPC
, 0, {RT
, RA
, RB
}},
6818 {"stxvd2x", X(31,972), XX1_MASK
, PPCVSX
, 0, {XS6
, RA0
, RB
}},
6819 {"stxvx", X(31,972), XX1_MASK
, POWER8
, POWER9
|PPCVSX3
, {XS6
, RA0
, RB
}},
6821 {"tlbld", X(31,978), XRTRA_MASK
, PPC
, PPC403
|BOOKE
|PPCA2
|PPC476
, {RB
}},
6822 {"tlbwehi", XTLB(31,978,0), XTLB_MASK
, PPC403
, 0, {RT
, RA
}},
6823 {"tlbwelo", XTLB(31,978,1), XTLB_MASK
, PPC403
, 0, {RT
, RA
}},
6824 {"tlbwe", X(31,978), X_MASK
, PPC403
|BOOKE
|PPCA2
|PPC476
, 0, {RSO
, RAOPT
, SHO
}},
6826 {"slbfee.", XRC(31,979,1), XRA_MASK
, POWER6
, 0, {RT
, RB
}},
6828 {"stbcix", X(31,981), X_MASK
, POWER6
, 0, {RS
, RA0
, RB
}},
6830 {"icbi", X(31,982), XRT_MASK
, PPC
, 0, {RA0
, RB
}},
6832 {"stfiwx", X(31,983), X_MASK
, PPC
, PPCEFS
, {FRS
, RA0
, RB
}},
6834 {"extsw", XRC(31,986,0), XRB_MASK
, PPC64
, 0, {RA
, RS
}},
6835 {"extsw.", XRC(31,986,1), XRB_MASK
, PPC64
, 0, {RA
, RS
}},
6837 {"icbiep", XRT(31,991,0), XRT_MASK
, E500MC
|PPCA2
, 0, {RA0
, RB
}},
6839 {"stvswxl", X(31,997), X_MASK
, E6500
, 0, {VS
, RA0
, RB
}},
6841 {"icread", X(31,998), XRT_MASK
, PPC403
|PPC440
|PPC476
|TITAN
, 0, {RA0
, RB
}},
6843 {"nabso", XO(31,488,1,0), XORB_MASK
, M601
, 0, {RT
, RA
}},
6844 {"nabso.", XO(31,488,1,1), XORB_MASK
, M601
, 0, {RT
, RA
}},
6846 {"divdo", XO(31,489,1,0), XO_MASK
, PPC64
, 0, {RT
, RA
, RB
}},
6847 {"divdo.", XO(31,489,1,1), XO_MASK
, PPC64
, 0, {RT
, RA
, RB
}},
6849 {"divwo", XO(31,491,1,0), XO_MASK
, PPC
, 0, {RT
, RA
, RB
}},
6850 {"divwo.", XO(31,491,1,1), XO_MASK
, PPC
, 0, {RT
, RA
, RB
}},
6852 {"stxvb16x", X(31,1004), XX1_MASK
, PPCVSX3
, 0, {XS6
, RA0
, RB
}},
6854 {"trechkpt.", XRC(31,1006,1), XRTRARB_MASK
,PPCHTM
, 0, {0}},
6856 {"tlbli", X(31,1010), XRTRA_MASK
, PPC
, TITAN
, {RB
}},
6858 {"stdcix", X(31,1013), X_MASK
, POWER6
, 0, {RS
, RA0
, RB
}},
6860 {"dcbz", X(31,1014), XRT_MASK
, PPC
, 0, {RA0
, RB
}},
6861 {"dclz", X(31,1014), XRT_MASK
, PPC
, 0, {RA0
, RB
}},
6863 {"dcbzep", XRT(31,1023,0), XRT_MASK
, E500MC
|PPCA2
, 0, {RA0
, RB
}},
6865 {"dcbzl", XOPL(31,1014,1), XRT_MASK
, POWER4
|E500MC
, PPC476
, {RA0
, RB
}},
6867 {"cctpl", 0x7c210b78, 0xffffffff, CELL
, 0, {0}},
6868 {"cctpm", 0x7c421378, 0xffffffff, CELL
, 0, {0}},
6869 {"cctph", 0x7c631b78, 0xffffffff, CELL
, 0, {0}},
6871 {"dstt", XDSS(31,342,1), XDSS_MASK
, PPCVEC
, 0, {RA
, RB
, STRM
}},
6872 {"dststt", XDSS(31,374,1), XDSS_MASK
, PPCVEC
, 0, {RA
, RB
, STRM
}},
6873 {"dssall", XDSS(31,822,1), XDSS_MASK
, PPCVEC
, 0, {0}},
6875 {"db8cyc", 0x7f9ce378, 0xffffffff, CELL
, 0, {0}},
6876 {"db10cyc", 0x7fbdeb78, 0xffffffff, CELL
, 0, {0}},
6877 {"db12cyc", 0x7fdef378, 0xffffffff, CELL
, 0, {0}},
6878 {"db16cyc", 0x7ffffb78, 0xffffffff, CELL
, 0, {0}},
6880 {"lwz", OP(32), OP_MASK
, PPCCOM
, PPCVLE
, {RT
, D
, RA0
}},
6881 {"l", OP(32), OP_MASK
, PWRCOM
, PPCVLE
, {RT
, D
, RA0
}},
6883 {"lwzu", OP(33), OP_MASK
, PPCCOM
, PPCVLE
, {RT
, D
, RAL
}},
6884 {"lu", OP(33), OP_MASK
, PWRCOM
, PPCVLE
, {RT
, D
, RA0
}},
6886 {"lbz", OP(34), OP_MASK
, COM
, PPCVLE
, {RT
, D
, RA0
}},
6888 {"lbzu", OP(35), OP_MASK
, COM
, PPCVLE
, {RT
, D
, RAL
}},
6890 {"stw", OP(36), OP_MASK
, PPCCOM
, PPCVLE
, {RS
, D
, RA0
}},
6891 {"st", OP(36), OP_MASK
, PWRCOM
, PPCVLE
, {RS
, D
, RA0
}},
6893 {"stwu", OP(37), OP_MASK
, PPCCOM
, PPCVLE
, {RS
, D
, RAS
}},
6894 {"stu", OP(37), OP_MASK
, PWRCOM
, PPCVLE
, {RS
, D
, RA0
}},
6896 {"stb", OP(38), OP_MASK
, COM
, PPCVLE
, {RS
, D
, RA0
}},
6898 {"stbu", OP(39), OP_MASK
, COM
, PPCVLE
, {RS
, D
, RAS
}},
6900 {"lhz", OP(40), OP_MASK
, COM
, PPCVLE
, {RT
, D
, RA0
}},
6902 {"lhzu", OP(41), OP_MASK
, COM
, PPCVLE
, {RT
, D
, RAL
}},
6904 {"lha", OP(42), OP_MASK
, COM
, PPCVLE
, {RT
, D
, RA0
}},
6906 {"lhau", OP(43), OP_MASK
, COM
, PPCVLE
, {RT
, D
, RAL
}},
6908 {"sth", OP(44), OP_MASK
, COM
, PPCVLE
, {RS
, D
, RA0
}},
6910 {"sthu", OP(45), OP_MASK
, COM
, PPCVLE
, {RS
, D
, RAS
}},
6912 {"lmw", OP(46), OP_MASK
, PPCCOM
, PPCVLE
, {RT
, D
, RAM
}},
6913 {"lm", OP(46), OP_MASK
, PWRCOM
, PPCVLE
, {RT
, D
, RA0
}},
6915 {"stmw", OP(47), OP_MASK
, PPCCOM
, PPCVLE
, {RS
, D
, RA0
}},
6916 {"stm", OP(47), OP_MASK
, PWRCOM
, PPCVLE
, {RS
, D
, RA0
}},
6918 {"lfs", OP(48), OP_MASK
, COM
, PPCEFS
|PPCVLE
, {FRT
, D
, RA0
}},
6920 {"lfsu", OP(49), OP_MASK
, COM
, PPCEFS
|PPCVLE
, {FRT
, D
, RAS
}},
6922 {"lfd", OP(50), OP_MASK
, COM
, PPCEFS
|PPCVLE
, {FRT
, D
, RA0
}},
6924 {"lfdu", OP(51), OP_MASK
, COM
, PPCEFS
|PPCVLE
, {FRT
, D
, RAS
}},
6926 {"stfs", OP(52), OP_MASK
, COM
, PPCEFS
|PPCVLE
, {FRS
, D
, RA0
}},
6928 {"stfsu", OP(53), OP_MASK
, COM
, PPCEFS
|PPCVLE
, {FRS
, D
, RAS
}},
6930 {"stfd", OP(54), OP_MASK
, COM
, PPCEFS
|PPCVLE
, {FRS
, D
, RA0
}},
6932 {"stfdu", OP(55), OP_MASK
, COM
, PPCEFS
|PPCVLE
, {FRS
, D
, RAS
}},
6934 {"lq", OP(56), OP_MASK
|Q_MASK
, POWER4
, PPC476
|PPCVLE
, {RTQ
, DQ
, RAQ
}},
6935 {"psq_l", OP(56), OP_MASK
, PPCPS
, PPCVLE
, {FRT
,PSD
,RA
,PSW
,PSQ
}},
6936 {"lfq", OP(56), OP_MASK
, POWER2
, PPCVLE
, {FRT
, D
, RA0
}},
6938 {"lxsd", DSO(57,2), DS_MASK
, PPCVSX3
, PPCVLE
, {VD
, DS
, RA0
}},
6939 {"lxssp", DSO(57,3), DS_MASK
, PPCVSX3
, PPCVLE
, {VD
, DS
, RA0
}},
6940 {"lfdp", OP(57), OP_MASK
|Q_MASK
, POWER6
, POWER7
|PPCVLE
, {FRTp
, DS
, RA0
}},
6941 {"psq_lu", OP(57), OP_MASK
, PPCPS
, PPCVLE
, {FRT
,PSD
,RA
,PSW
,PSQ
}},
6942 {"lfqu", OP(57), OP_MASK
, POWER2
, PPCVLE
, {FRT
, D
, RA0
}},
6944 {"ld", DSO(58,0), DS_MASK
, PPC64
, PPCVLE
, {RT
, DS
, RA0
}},
6945 {"ldu", DSO(58,1), DS_MASK
, PPC64
, PPCVLE
, {RT
, DS
, RAL
}},
6946 {"lwa", DSO(58,2), DS_MASK
, PPC64
, PPCVLE
, {RT
, DS
, RA0
}},
6948 {"dadd", XRC(59,2,0), X_MASK
, POWER6
, PPCVLE
, {FRT
, FRA
, FRB
}},
6949 {"dadd.", XRC(59,2,1), X_MASK
, POWER6
, PPCVLE
, {FRT
, FRA
, FRB
}},
6951 {"dqua", ZRC(59,3,0), Z2_MASK
, POWER6
, PPCVLE
, {FRT
,FRA
,FRB
,RMC
}},
6952 {"dqua.", ZRC(59,3,1), Z2_MASK
, POWER6
, PPCVLE
, {FRT
,FRA
,FRB
,RMC
}},
6954 {"fdivs", A(59,18,0), AFRC_MASK
, PPC
, PPCEFS
|PPCVLE
, {FRT
, FRA
, FRB
}},
6955 {"fdivs.", A(59,18,1), AFRC_MASK
, PPC
, PPCEFS
|PPCVLE
, {FRT
, FRA
, FRB
}},
6957 {"fsubs", A(59,20,0), AFRC_MASK
, PPC
, PPCEFS
|PPCVLE
, {FRT
, FRA
, FRB
}},
6958 {"fsubs.", A(59,20,1), AFRC_MASK
, PPC
, PPCEFS
|PPCVLE
, {FRT
, FRA
, FRB
}},
6960 {"fadds", A(59,21,0), AFRC_MASK
, PPC
, PPCEFS
|PPCVLE
, {FRT
, FRA
, FRB
}},
6961 {"fadds.", A(59,21,1), AFRC_MASK
, PPC
, PPCEFS
|PPCVLE
, {FRT
, FRA
, FRB
}},
6963 {"fsqrts", A(59,22,0), AFRAFRC_MASK
, PPC
, TITAN
|PPCVLE
, {FRT
, FRB
}},
6964 {"fsqrts.", A(59,22,1), AFRAFRC_MASK
, PPC
, TITAN
|PPCVLE
, {FRT
, FRB
}},
6966 {"fres", A(59,24,0), AFRAFRC_MASK
, POWER7
, PPCVLE
, {FRT
, FRB
}},
6967 {"fres", A(59,24,0), AFRALFRC_MASK
, PPC
, POWER7
|PPCVLE
, {FRT
, FRB
, A_L
}},
6968 {"fres.", A(59,24,1), AFRAFRC_MASK
, POWER7
, PPCVLE
, {FRT
, FRB
}},
6969 {"fres.", A(59,24,1), AFRALFRC_MASK
, PPC
, POWER7
|PPCVLE
, {FRT
, FRB
, A_L
}},
6971 {"fmuls", A(59,25,0), AFRB_MASK
, PPC
, PPCEFS
|PPCVLE
, {FRT
, FRA
, FRC
}},
6972 {"fmuls.", A(59,25,1), AFRB_MASK
, PPC
, PPCEFS
|PPCVLE
, {FRT
, FRA
, FRC
}},
6974 {"frsqrtes", A(59,26,0), AFRAFRC_MASK
, POWER7
, PPCVLE
, {FRT
, FRB
}},
6975 {"frsqrtes", A(59,26,0), AFRALFRC_MASK
, POWER5
, POWER7
|PPCVLE
, {FRT
, FRB
, A_L
}},
6976 {"frsqrtes.", A(59,26,1), AFRAFRC_MASK
, POWER7
, PPCVLE
, {FRT
, FRB
}},
6977 {"frsqrtes.", A(59,26,1), AFRALFRC_MASK
, POWER5
, POWER7
|PPCVLE
, {FRT
, FRB
, A_L
}},
6979 {"fmsubs", A(59,28,0), A_MASK
, PPC
, PPCEFS
|PPCVLE
, {FRT
, FRA
, FRC
, FRB
}},
6980 {"fmsubs.", A(59,28,1), A_MASK
, PPC
, PPCEFS
|PPCVLE
, {FRT
, FRA
, FRC
, FRB
}},
6982 {"fmadds", A(59,29,0), A_MASK
, PPC
, PPCEFS
|PPCVLE
, {FRT
, FRA
, FRC
, FRB
}},
6983 {"fmadds.", A(59,29,1), A_MASK
, PPC
, PPCEFS
|PPCVLE
, {FRT
, FRA
, FRC
, FRB
}},
6985 {"fnmsubs", A(59,30,0), A_MASK
, PPC
, PPCEFS
|PPCVLE
, {FRT
, FRA
, FRC
, FRB
}},
6986 {"fnmsubs.", A(59,30,1), A_MASK
, PPC
, PPCEFS
|PPCVLE
, {FRT
, FRA
, FRC
, FRB
}},
6988 {"fnmadds", A(59,31,0), A_MASK
, PPC
, PPCEFS
|PPCVLE
, {FRT
, FRA
, FRC
, FRB
}},
6989 {"fnmadds.", A(59,31,1), A_MASK
, PPC
, PPCEFS
|PPCVLE
, {FRT
, FRA
, FRC
, FRB
}},
6991 {"dmul", XRC(59,34,0), X_MASK
, POWER6
, PPCVLE
, {FRT
, FRA
, FRB
}},
6992 {"dmul.", XRC(59,34,1), X_MASK
, POWER6
, PPCVLE
, {FRT
, FRA
, FRB
}},
6994 {"drrnd", ZRC(59,35,0), Z2_MASK
, POWER6
, PPCVLE
, {FRT
, FRA
, FRB
, RMC
}},
6995 {"drrnd.", ZRC(59,35,1), Z2_MASK
, POWER6
, PPCVLE
, {FRT
, FRA
, FRB
, RMC
}},
6997 {"dscli", ZRC(59,66,0), Z_MASK
, POWER6
, PPCVLE
, {FRT
, FRA
, SH16
}},
6998 {"dscli.", ZRC(59,66,1), Z_MASK
, POWER6
, PPCVLE
, {FRT
, FRA
, SH16
}},
7000 {"dquai", ZRC(59,67,0), Z2_MASK
, POWER6
, PPCVLE
, {TE
, FRT
,FRB
,RMC
}},
7001 {"dquai.", ZRC(59,67,1), Z2_MASK
, POWER6
, PPCVLE
, {TE
, FRT
,FRB
,RMC
}},
7003 {"dscri", ZRC(59,98,0), Z_MASK
, POWER6
, PPCVLE
, {FRT
, FRA
, SH16
}},
7004 {"dscri.", ZRC(59,98,1), Z_MASK
, POWER6
, PPCVLE
, {FRT
, FRA
, SH16
}},
7006 {"drintx", ZRC(59,99,0), Z2_MASK
, POWER6
, PPCVLE
, {R
, FRT
, FRB
, RMC
}},
7007 {"drintx.", ZRC(59,99,1), Z2_MASK
, POWER6
, PPCVLE
, {R
, FRT
, FRB
, RMC
}},
7009 {"dcmpo", X(59,130), X_MASK
, POWER6
, PPCVLE
, {BF
, FRA
, FRB
}},
7011 {"dtstex", X(59,162), X_MASK
, POWER6
, PPCVLE
, {BF
, FRA
, FRB
}},
7012 {"dtstdc", Z(59,194), Z_MASK
, POWER6
, PPCVLE
, {BF
, FRA
, DCM
}},
7013 {"dtstdg", Z(59,226), Z_MASK
, POWER6
, PPCVLE
, {BF
, FRA
, DGM
}},
7015 {"drintn", ZRC(59,227,0), Z2_MASK
, POWER6
, PPCVLE
, {R
, FRT
, FRB
, RMC
}},
7016 {"drintn.", ZRC(59,227,1), Z2_MASK
, POWER6
, PPCVLE
, {R
, FRT
, FRB
, RMC
}},
7018 {"dctdp", XRC(59,258,0), X_MASK
, POWER6
, PPCVLE
, {FRT
, FRB
}},
7019 {"dctdp.", XRC(59,258,1), X_MASK
, POWER6
, PPCVLE
, {FRT
, FRB
}},
7021 {"dctfix", XRC(59,290,0), X_MASK
, POWER6
, PPCVLE
, {FRT
, FRB
}},
7022 {"dctfix.", XRC(59,290,1), X_MASK
, POWER6
, PPCVLE
, {FRT
, FRB
}},
7024 {"ddedpd", XRC(59,322,0), X_MASK
, POWER6
, PPCVLE
, {SP
, FRT
, FRB
}},
7025 {"ddedpd.", XRC(59,322,1), X_MASK
, POWER6
, PPCVLE
, {SP
, FRT
, FRB
}},
7027 {"dxex", XRC(59,354,0), X_MASK
, POWER6
, PPCVLE
, {FRT
, FRB
}},
7028 {"dxex.", XRC(59,354,1), X_MASK
, POWER6
, PPCVLE
, {FRT
, FRB
}},
7030 {"dsub", XRC(59,514,0), X_MASK
, POWER6
, PPCVLE
, {FRT
, FRA
, FRB
}},
7031 {"dsub.", XRC(59,514,1), X_MASK
, POWER6
, PPCVLE
, {FRT
, FRA
, FRB
}},
7033 {"ddiv", XRC(59,546,0), X_MASK
, POWER6
, PPCVLE
, {FRT
, FRA
, FRB
}},
7034 {"ddiv.", XRC(59,546,1), X_MASK
, POWER6
, PPCVLE
, {FRT
, FRA
, FRB
}},
7036 {"dcmpu", X(59,642), X_MASK
, POWER6
, PPCVLE
, {BF
, FRA
, FRB
}},
7038 {"dtstsf", X(59,674), X_MASK
, POWER6
, PPCVLE
, {BF
, FRA
, FRB
}},
7039 {"dtstsfi", X(59,675), X_MASK
|1<<22,POWER9
, PPCVLE
, {BF
, UIM6
, FRB
}},
7041 {"drsp", XRC(59,770,0), X_MASK
, POWER6
, PPCVLE
, {FRT
, FRB
}},
7042 {"drsp.", XRC(59,770,1), X_MASK
, POWER6
, PPCVLE
, {FRT
, FRB
}},
7044 {"dcffix", XRC(59,802,0), X_MASK
|FRA_MASK
, POWER7
, PPCVLE
, {FRT
, FRB
}},
7045 {"dcffix.", XRC(59,802,1), X_MASK
|FRA_MASK
, POWER7
, PPCVLE
, {FRT
, FRB
}},
7047 {"denbcd", XRC(59,834,0), X_MASK
, POWER6
, PPCVLE
, {S
, FRT
, FRB
}},
7048 {"denbcd.", XRC(59,834,1), X_MASK
, POWER6
, PPCVLE
, {S
, FRT
, FRB
}},
7050 {"fcfids", XRC(59,846,0), XRA_MASK
, POWER7
|PPCA2
, PPCVLE
, {FRT
, FRB
}},
7051 {"fcfids.", XRC(59,846,1), XRA_MASK
, POWER7
|PPCA2
, PPCVLE
, {FRT
, FRB
}},
7053 {"diex", XRC(59,866,0), X_MASK
, POWER6
, PPCVLE
, {FRT
, FRA
, FRB
}},
7054 {"diex.", XRC(59,866,1), X_MASK
, POWER6
, PPCVLE
, {FRT
, FRA
, FRB
}},
7056 {"fcfidus", XRC(59,974,0), XRA_MASK
, POWER7
|PPCA2
, PPCVLE
, {FRT
, FRB
}},
7057 {"fcfidus.", XRC(59,974,1), XRA_MASK
, POWER7
|PPCA2
, PPCVLE
, {FRT
, FRB
}},
7059 {"xsaddsp", XX3(60,0), XX3_MASK
, PPCVSX2
, PPCVLE
, {XT6
, XA6
, XB6
}},
7060 {"xsmaddasp", XX3(60,1), XX3_MASK
, PPCVSX2
, PPCVLE
, {XT6
, XA6
, XB6
}},
7061 {"xxsldwi", XX3(60,2), XX3SHW_MASK
, PPCVSX
, PPCVLE
, {XT6
, XA6
, XB6
, SHW
}},
7062 {"xscmpeqdp", XX3(60,3), XX3_MASK
, PPCVSX3
, PPCVLE
, {XT6
, XA6
, XB6
}},
7063 {"xsrsqrtesp", XX2(60,10), XX2_MASK
, PPCVSX2
, PPCVLE
, {XT6
, XB6
}},
7064 {"xssqrtsp", XX2(60,11), XX2_MASK
, PPCVSX2
, PPCVLE
, {XT6
, XB6
}},
7065 {"xxsel", XX4(60,3), XX4_MASK
, PPCVSX
, PPCVLE
, {XT6
, XA6
, XB6
, XC6
}},
7066 {"xssubsp", XX3(60,8), XX3_MASK
, PPCVSX2
, PPCVLE
, {XT6
, XA6
, XB6
}},
7067 {"xsmaddmsp", XX3(60,9), XX3_MASK
, PPCVSX2
, PPCVLE
, {XT6
, XA6
, XB6
}},
7068 {"xxspltd", XX3(60,10), XX3DM_MASK
, PPCVSX
, PPCVLE
, {XT6
, XAB6
, DMEX
}},
7069 {"xxmrghd", XX3(60,10), XX3_MASK
, PPCVSX
, PPCVLE
, {XT6
, XA6
, XB6
}},
7070 {"xxswapd", XX3(60,10)|(2<<8), XX3_MASK
, PPCVSX
, PPCVLE
, {XT6
, XAB6
}},
7071 {"xxmrgld", XX3(60,10)|(3<<8), XX3_MASK
, PPCVSX
, PPCVLE
, {XT6
, XA6
, XB6
}},
7072 {"xxpermdi", XX3(60,10), XX3DM_MASK
, PPCVSX
, PPCVLE
, {XT6
, XA6
, XB6
, DM
}},
7073 {"xscmpgtdp", XX3(60,11), XX3_MASK
, PPCVSX3
, PPCVLE
, {XT6
, XA6
, XB6
}},
7074 {"xsresp", XX2(60,26), XX2_MASK
, PPCVSX2
, PPCVLE
, {XT6
, XB6
}},
7075 {"xsmulsp", XX3(60,16), XX3_MASK
, PPCVSX2
, PPCVLE
, {XT6
, XA6
, XB6
}},
7076 {"xsmsubasp", XX3(60,17), XX3_MASK
, PPCVSX2
, PPCVLE
, {XT6
, XA6
, XB6
}},
7077 {"xxmrghw", XX3(60,18), XX3_MASK
, PPCVSX
, PPCVLE
, {XT6
, XA6
, XB6
}},
7078 {"xscmpgedp", XX3(60,19), XX3_MASK
, PPCVSX3
, PPCVLE
, {XT6
, XA6
, XB6
}},
7079 {"xsdivsp", XX3(60,24), XX3_MASK
, PPCVSX2
, PPCVLE
, {XT6
, XA6
, XB6
}},
7080 {"xsmsubmsp", XX3(60,25), XX3_MASK
, PPCVSX2
, PPCVLE
, {XT6
, XA6
, XB6
}},
7081 {"xxperm", XX3(60,26), XX3_MASK
, PPCVSX3
, PPCVLE
, {XT6
, XA6
, XB6
}},
7082 {"xsadddp", XX3(60,32), XX3_MASK
, PPCVSX
, PPCVLE
, {XT6
, XA6
, XB6
}},
7083 {"xsmaddadp", XX3(60,33), XX3_MASK
, PPCVSX
, PPCVLE
, {XT6
, XA6
, XB6
}},
7084 {"xscmpudp", XX3(60,35), XX3BF_MASK
, PPCVSX
, PPCVLE
, {BF
, XA6
, XB6
}},
7085 {"xscvdpuxws", XX2(60,72), XX2_MASK
, PPCVSX
, PPCVLE
, {XT6
, XB6
}},
7086 {"xsrdpi", XX2(60,73), XX2_MASK
, PPCVSX
, PPCVLE
, {XT6
, XB6
}},
7087 {"xsrsqrtedp", XX2(60,74), XX2_MASK
, PPCVSX
, PPCVLE
, {XT6
, XB6
}},
7088 {"xssqrtdp", XX2(60,75), XX2_MASK
, PPCVSX
, PPCVLE
, {XT6
, XB6
}},
7089 {"xssubdp", XX3(60,40), XX3_MASK
, PPCVSX
, PPCVLE
, {XT6
, XA6
, XB6
}},
7090 {"xsmaddmdp", XX3(60,41), XX3_MASK
, PPCVSX
, PPCVLE
, {XT6
, XA6
, XB6
}},
7091 {"xscmpodp", XX3(60,43), XX3BF_MASK
, PPCVSX
, PPCVLE
, {BF
, XA6
, XB6
}},
7092 {"xscvdpsxws", XX2(60,88), XX2_MASK
, PPCVSX
, PPCVLE
, {XT6
, XB6
}},
7093 {"xsrdpiz", XX2(60,89), XX2_MASK
, PPCVSX
, PPCVLE
, {XT6
, XB6
}},
7094 {"xsredp", XX2(60,90), XX2_MASK
, PPCVSX
, PPCVLE
, {XT6
, XB6
}},
7095 {"xsmuldp", XX3(60,48), XX3_MASK
, PPCVSX
, PPCVLE
, {XT6
, XA6
, XB6
}},
7096 {"xsmsubadp", XX3(60,49), XX3_MASK
, PPCVSX
, PPCVLE
, {XT6
, XA6
, XB6
}},
7097 {"xxmrglw", XX3(60,50), XX3_MASK
, PPCVSX
, PPCVLE
, {XT6
, XA6
, XB6
}},
7098 {"xsrdpip", XX2(60,105), XX2_MASK
, PPCVSX
, PPCVLE
, {XT6
, XB6
}},
7099 {"xstsqrtdp", XX2(60,106), XX2BF_MASK
, PPCVSX
, PPCVLE
, {BF
, XB6
}},
7100 {"xsrdpic", XX2(60,107), XX2_MASK
, PPCVSX
, PPCVLE
, {XT6
, XB6
}},
7101 {"xsdivdp", XX3(60,56), XX3_MASK
, PPCVSX
, PPCVLE
, {XT6
, XA6
, XB6
}},
7102 {"xsmsubmdp", XX3(60,57), XX3_MASK
, PPCVSX
, PPCVLE
, {XT6
, XA6
, XB6
}},
7103 {"xxpermr", XX3(60,58), XX3_MASK
, PPCVSX3
, PPCVLE
, {XT6
, XA6
, XB6
}},
7104 {"xscmpexpdp", XX3(60,59), XX3BF_MASK
, PPCVSX3
, PPCVLE
, {BF
, XA6
, XB6
}},
7105 {"xsrdpim", XX2(60,121), XX2_MASK
, PPCVSX
, PPCVLE
, {XT6
, XB6
}},
7106 {"xstdivdp", XX3(60,61), XX3BF_MASK
, PPCVSX
, PPCVLE
, {BF
, XA6
, XB6
}},
7107 {"xvaddsp", XX3(60,64), XX3_MASK
, PPCVSX
, PPCVLE
, {XT6
, XA6
, XB6
}},
7108 {"xvmaddasp", XX3(60,65), XX3_MASK
, PPCVSX
, PPCVLE
, {XT6
, XA6
, XB6
}},
7109 {"xvcmpeqsp", XX3RC(60,67,0), XX3_MASK
, PPCVSX
, PPCVLE
, {XT6
, XA6
, XB6
}},
7110 {"xvcmpeqsp.", XX3RC(60,67,1), XX3_MASK
, PPCVSX
, PPCVLE
, {XT6
, XA6
, XB6
}},
7111 {"xvcvspuxws", XX2(60,136), XX2_MASK
, PPCVSX
, PPCVLE
, {XT6
, XB6
}},
7112 {"xvrspi", XX2(60,137), XX2_MASK
, PPCVSX
, PPCVLE
, {XT6
, XB6
}},
7113 {"xvrsqrtesp", XX2(60,138), XX2_MASK
, PPCVSX
, PPCVLE
, {XT6
, XB6
}},
7114 {"xvsqrtsp", XX2(60,139), XX2_MASK
, PPCVSX
, PPCVLE
, {XT6
, XB6
}},
7115 {"xvsubsp", XX3(60,72), XX3_MASK
, PPCVSX
, PPCVLE
, {XT6
, XA6
, XB6
}},
7116 {"xvmaddmsp", XX3(60,73), XX3_MASK
, PPCVSX
, PPCVLE
, {XT6
, XA6
, XB6
}},
7117 {"xvcmpgtsp", XX3RC(60,75,0), XX3_MASK
, PPCVSX
, PPCVLE
, {XT6
, XA6
, XB6
}},
7118 {"xvcmpgtsp.", XX3RC(60,75,1), XX3_MASK
, PPCVSX
, PPCVLE
, {XT6
, XA6
, XB6
}},
7119 {"xvcvspsxws", XX2(60,152), XX2_MASK
, PPCVSX
, PPCVLE
, {XT6
, XB6
}},
7120 {"xvrspiz", XX2(60,153), XX2_MASK
, PPCVSX
, PPCVLE
, {XT6
, XB6
}},
7121 {"xvresp", XX2(60,154), XX2_MASK
, PPCVSX
, PPCVLE
, {XT6
, XB6
}},
7122 {"xvmulsp", XX3(60,80), XX3_MASK
, PPCVSX
, PPCVLE
, {XT6
, XA6
, XB6
}},
7123 {"xvmsubasp", XX3(60,81), XX3_MASK
, PPCVSX
, PPCVLE
, {XT6
, XA6
, XB6
}},
7124 {"xxspltw", XX2(60,164), XX2UIM_MASK
, PPCVSX
, PPCVLE
, {XT6
, XB6
, UIM
}},
7125 {"xxextractuw", XX2(60,165), XX2UIM4_MASK
, PPCVSX3
, PPCVLE
, {XT6
, XB6
, UIMM4
}},
7126 {"xvcmpgesp", XX3RC(60,83,0), XX3_MASK
, PPCVSX
, PPCVLE
, {XT6
, XA6
, XB6
}},
7127 {"xvcmpgesp.", XX3RC(60,83,1), XX3_MASK
, PPCVSX
, PPCVLE
, {XT6
, XA6
, XB6
}},
7128 {"xvcvuxwsp", XX2(60,168), XX2_MASK
, PPCVSX
, PPCVLE
, {XT6
, XB6
}},
7129 {"xvrspip", XX2(60,169), XX2_MASK
, PPCVSX
, PPCVLE
, {XT6
, XB6
}},
7130 {"xvtsqrtsp", XX2(60,170), XX2BF_MASK
, PPCVSX
, PPCVLE
, {BF
, XB6
}},
7131 {"xvrspic", XX2(60,171), XX2_MASK
, PPCVSX
, PPCVLE
, {XT6
, XB6
}},
7132 {"xvdivsp", XX3(60,88), XX3_MASK
, PPCVSX
, PPCVLE
, {XT6
, XA6
, XB6
}},
7133 {"xvmsubmsp", XX3(60,89), XX3_MASK
, PPCVSX
, PPCVLE
, {XT6
, XA6
, XB6
}},
7134 {"xxspltib", X(60,360), XX1_MASK
|3<<19, PPCVSX3
, PPCVLE
, {XT6
, IMM8
}},
7135 {"xxinsertw", XX2(60,181), XX2UIM4_MASK
, PPCVSX3
, PPCVLE
, {XT6
, XB6
, UIMM4
}},
7136 {"xvcvsxwsp", XX2(60,184), XX2_MASK
, PPCVSX
, PPCVLE
, {XT6
, XB6
}},
7137 {"xvrspim", XX2(60,185), XX2_MASK
, PPCVSX
, PPCVLE
, {XT6
, XB6
}},
7138 {"xvtdivsp", XX3(60,93), XX3BF_MASK
, PPCVSX
, PPCVLE
, {BF
, XA6
, XB6
}},
7139 {"xvadddp", XX3(60,96), XX3_MASK
, PPCVSX
, PPCVLE
, {XT6
, XA6
, XB6
}},
7140 {"xvmaddadp", XX3(60,97), XX3_MASK
, PPCVSX
, PPCVLE
, {XT6
, XA6
, XB6
}},
7141 {"xvcmpeqdp", XX3RC(60,99,0), XX3_MASK
, PPCVSX
, PPCVLE
, {XT6
, XA6
, XB6
}},
7142 {"xvcmpeqdp.", XX3RC(60,99,1), XX3_MASK
, PPCVSX
, PPCVLE
, {XT6
, XA6
, XB6
}},
7143 {"xvcvdpuxws", XX2(60,200), XX2_MASK
, PPCVSX
, PPCVLE
, {XT6
, XB6
}},
7144 {"xvrdpi", XX2(60,201), XX2_MASK
, PPCVSX
, PPCVLE
, {XT6
, XB6
}},
7145 {"xvrsqrtedp", XX2(60,202), XX2_MASK
, PPCVSX
, PPCVLE
, {XT6
, XB6
}},
7146 {"xvsqrtdp", XX2(60,203), XX2_MASK
, PPCVSX
, PPCVLE
, {XT6
, XB6
}},
7147 {"xvsubdp", XX3(60,104), XX3_MASK
, PPCVSX
, PPCVLE
, {XT6
, XA6
, XB6
}},
7148 {"xvmaddmdp", XX3(60,105), XX3_MASK
, PPCVSX
, PPCVLE
, {XT6
, XA6
, XB6
}},
7149 {"xvcmpgtdp", XX3RC(60,107,0), XX3_MASK
, PPCVSX
, PPCVLE
, {XT6
, XA6
, XB6
}},
7150 {"xvcmpgtdp.", XX3RC(60,107,1), XX3_MASK
, PPCVSX
, PPCVLE
, {XT6
, XA6
, XB6
}},
7151 {"xvcvdpsxws", XX2(60,216), XX2_MASK
, PPCVSX
, PPCVLE
, {XT6
, XB6
}},
7152 {"xvrdpiz", XX2(60,217), XX2_MASK
, PPCVSX
, PPCVLE
, {XT6
, XB6
}},
7153 {"xvredp", XX2(60,218), XX2_MASK
, PPCVSX
, PPCVLE
, {XT6
, XB6
}},
7154 {"xvmuldp", XX3(60,112), XX3_MASK
, PPCVSX
, PPCVLE
, {XT6
, XA6
, XB6
}},
7155 {"xvmsubadp", XX3(60,113), XX3_MASK
, PPCVSX
, PPCVLE
, {XT6
, XA6
, XB6
}},
7156 {"xvcmpgedp", XX3RC(60,115,0), XX3_MASK
, PPCVSX
, PPCVLE
, {XT6
, XA6
, XB6
}},
7157 {"xvcmpgedp.", XX3RC(60,115,1), XX3_MASK
, PPCVSX
, PPCVLE
, {XT6
, XA6
, XB6
}},
7158 {"xvcvuxwdp", XX2(60,232), XX2_MASK
, PPCVSX
, PPCVLE
, {XT6
, XB6
}},
7159 {"xvrdpip", XX2(60,233), XX2_MASK
, PPCVSX
, PPCVLE
, {XT6
, XB6
}},
7160 {"xvtsqrtdp", XX2(60,234), XX2BF_MASK
, PPCVSX
, PPCVLE
, {BF
, XB6
}},
7161 {"xvrdpic", XX2(60,235), XX2_MASK
, PPCVSX
, PPCVLE
, {XT6
, XB6
}},
7162 {"xvdivdp", XX3(60,120), XX3_MASK
, PPCVSX
, PPCVLE
, {XT6
, XA6
, XB6
}},
7163 {"xvmsubmdp", XX3(60,121), XX3_MASK
, PPCVSX
, PPCVLE
, {XT6
, XA6
, XB6
}},
7164 {"xvcvsxwdp", XX2(60,248), XX2_MASK
, PPCVSX
, PPCVLE
, {XT6
, XB6
}},
7165 {"xvrdpim", XX2(60,249), XX2_MASK
, PPCVSX
, PPCVLE
, {XT6
, XB6
}},
7166 {"xvtdivdp", XX3(60,125), XX3BF_MASK
, PPCVSX
, PPCVLE
, {BF
, XA6
, XB6
}},
7167 {"xsmaxcdp", XX3(60,128), XX3_MASK
, PPCVSX3
, PPCVLE
, {XT6
, XA6
, XB6
}},
7168 {"xsnmaddasp", XX3(60,129), XX3_MASK
, PPCVSX2
, PPCVLE
, {XT6
, XA6
, XB6
}},
7169 {"xxland", XX3(60,130), XX3_MASK
, PPCVSX
, PPCVLE
, {XT6
, XA6
, XB6
}},
7170 {"xscvdpsp", XX2(60,265), XX2_MASK
, PPCVSX
, PPCVLE
, {XT6
, XB6
}},
7171 {"xscvdpspn", XX2(60,267), XX2_MASK
, PPCVSX2
, PPCVLE
, {XT6
, XB6
}},
7172 {"xsmincdp", XX3(60,136), XX3_MASK
, PPCVSX3
, PPCVLE
, {XT6
, XA6
, XB6
}},
7173 {"xsnmaddmsp", XX3(60,137), XX3_MASK
, PPCVSX2
, PPCVLE
, {XT6
, XA6
, XB6
}},
7174 {"xxlandc", XX3(60,138), XX3_MASK
, PPCVSX
, PPCVLE
, {XT6
, XA6
, XB6
}},
7175 {"xsrsp", XX2(60,281), XX2_MASK
, PPCVSX2
, PPCVLE
, {XT6
, XB6
}},
7176 {"xsmaxjdp", XX3(60,144), XX3_MASK
, PPCVSX3
, PPCVLE
, {XT6
, XA6
, XB6
}},
7177 {"xsnmsubasp", XX3(60,145), XX3_MASK
, PPCVSX2
, PPCVLE
, {XT6
, XA6
, XB6
}},
7178 {"xxlor", XX3(60,146), XX3_MASK
, PPCVSX
, PPCVLE
, {XT6
, XA6
, XB6
}},
7179 {"xscvuxdsp", XX2(60,296), XX2_MASK
, PPCVSX2
, PPCVLE
, {XT6
, XB6
}},
7180 {"xststdcsp", XX2(60,298), XX2BFD_MASK
, PPCVSX3
, PPCVLE
, {BF
, XB6
, DCMX
}},
7181 {"xsminjdp", XX3(60,152), XX3_MASK
, PPCVSX3
, PPCVLE
, {XT6
, XA6
, XB6
}},
7182 {"xsnmsubmsp", XX3(60,153), XX3_MASK
, PPCVSX2
, PPCVLE
, {XT6
, XA6
, XB6
}},
7183 {"xxlxor", XX3(60,154), XX3_MASK
, PPCVSX
, PPCVLE
, {XT6
, XA6
, XB6
}},
7184 {"xscvsxdsp", XX2(60,312), XX2_MASK
, PPCVSX2
, PPCVLE
, {XT6
, XB6
}},
7185 {"xsmaxdp", XX3(60,160), XX3_MASK
, PPCVSX
, PPCVLE
, {XT6
, XA6
, XB6
}},
7186 {"xsnmaddadp", XX3(60,161), XX3_MASK
, PPCVSX
, PPCVLE
, {XT6
, XA6
, XB6
}},
7187 {"xxlnor", XX3(60,162), XX3_MASK
, PPCVSX
, PPCVLE
, {XT6
, XA6
, XB6
}},
7188 {"xscvdpuxds", XX2(60,328), XX2_MASK
, PPCVSX
, PPCVLE
, {XT6
, XB6
}},
7189 {"xscvspdp", XX2(60,329), XX2_MASK
, PPCVSX
, PPCVLE
, {XT6
, XB6
}},
7190 {"xscvspdpn", XX2(60,331), XX2_MASK
, PPCVSX2
, PPCVLE
, {XT6
, XB6
}},
7191 {"xsmindp", XX3(60,168), XX3_MASK
, PPCVSX
, PPCVLE
, {XT6
, XA6
, XB6
}},
7192 {"xsnmaddmdp", XX3(60,169), XX3_MASK
, PPCVSX
, PPCVLE
, {XT6
, XA6
, XB6
}},
7193 {"xxlorc", XX3(60,170), XX3_MASK
, PPCVSX2
, PPCVLE
, {XT6
, XA6
, XB6
}},
7194 {"xscvdpsxds", XX2(60,344), XX2_MASK
, PPCVSX
, PPCVLE
, {XT6
, XB6
}},
7195 {"xsabsdp", XX2(60,345), XX2_MASK
, PPCVSX
, PPCVLE
, {XT6
, XB6
}},
7196 {"xsxexpdp", XX2VA(60,347,0),XX2_MASK
|1, PPCVSX3
, PPCVLE
, {RT
, XB6
}},
7197 {"xsxsigdp", XX2VA(60,347,1),XX2_MASK
|1, PPCVSX3
, PPCVLE
, {RT
, XB6
}},
7198 {"xscvhpdp", XX2VA(60,347,16),XX2_MASK
, PPCVSX3
, PPCVLE
, {XT6
, XB6
}},
7199 {"xscvdphp", XX2VA(60,347,17),XX2_MASK
, PPCVSX3
, PPCVLE
, {XT6
, XB6
}},
7200 {"xscpsgndp", XX3(60,176), XX3_MASK
, PPCVSX
, PPCVLE
, {XT6
, XA6
, XB6
}},
7201 {"xsnmsubadp", XX3(60,177), XX3_MASK
, PPCVSX
, PPCVLE
, {XT6
, XA6
, XB6
}},
7202 {"xxlnand", XX3(60,178), XX3_MASK
, PPCVSX2
, PPCVLE
, {XT6
, XA6
, XB6
}},
7203 {"xscvuxddp", XX2(60,360), XX2_MASK
, PPCVSX
, PPCVLE
, {XT6
, XB6
}},
7204 {"xsnabsdp", XX2(60,361), XX2_MASK
, PPCVSX
, PPCVLE
, {XT6
, XB6
}},
7205 {"xststdcdp", XX2(60,362), XX2BFD_MASK
, PPCVSX3
, PPCVLE
, {BF
, XB6
, DCMX
}},
7206 {"xsnmsubmdp", XX3(60,185), XX3_MASK
, PPCVSX
, PPCVLE
, {XT6
, XA6
, XB6
}},
7207 {"xxleqv", XX3(60,186), XX3_MASK
, PPCVSX2
, PPCVLE
, {XT6
, XA6
, XB6
}},
7208 {"xscvsxddp", XX2(60,376), XX2_MASK
, PPCVSX
, PPCVLE
, {XT6
, XB6
}},
7209 {"xsnegdp", XX2(60,377), XX2_MASK
, PPCVSX
, PPCVLE
, {XT6
, XB6
}},
7210 {"xvmaxsp", XX3(60,192), XX3_MASK
, PPCVSX
, PPCVLE
, {XT6
, XA6
, XB6
}},
7211 {"xvnmaddasp", XX3(60,193), XX3_MASK
, PPCVSX
, PPCVLE
, {XT6
, XA6
, XB6
}},
7212 {"xvcvspuxds", XX2(60,392), XX2_MASK
, PPCVSX
, PPCVLE
, {XT6
, XB6
}},
7213 {"xvcvdpsp", XX2(60,393), XX2_MASK
, PPCVSX
, PPCVLE
, {XT6
, XB6
}},
7214 {"xvminsp", XX3(60,200), XX3_MASK
, PPCVSX
, PPCVLE
, {XT6
, XA6
, XB6
}},
7215 {"xvnmaddmsp", XX3(60,201), XX3_MASK
, PPCVSX
, PPCVLE
, {XT6
, XA6
, XB6
}},
7216 {"xvcvspsxds", XX2(60,408), XX2_MASK
, PPCVSX
, PPCVLE
, {XT6
, XB6
}},
7217 {"xvabssp", XX2(60,409), XX2_MASK
, PPCVSX
, PPCVLE
, {XT6
, XB6
}},
7218 {"xvmovsp", XX3(60,208), XX3_MASK
, PPCVSX
, PPCVLE
, {XT6
, XAB6
}},
7219 {"xvcpsgnsp", XX3(60,208), XX3_MASK
, PPCVSX
, PPCVLE
, {XT6
, XA6
, XB6
}},
7220 {"xvnmsubasp", XX3(60,209), XX3_MASK
, PPCVSX
, PPCVLE
, {XT6
, XA6
, XB6
}},
7221 {"xvcvuxdsp", XX2(60,424), XX2_MASK
, PPCVSX
, PPCVLE
, {XT6
, XB6
}},
7222 {"xvnabssp", XX2(60,425), XX2_MASK
, PPCVSX
, PPCVLE
, {XT6
, XB6
}},
7223 {"xvtstdcsp", XX2(60,426), XX2DCMXS_MASK
, PPCVSX3
, PPCVLE
, {XT6
, XB6
, DCMXS
}},
7224 {"xviexpsp", XX3(60,216), XX3_MASK
, PPCVSX3
, PPCVLE
, {XT6
, XA6
, XB6
}},
7225 {"xvnmsubmsp", XX3(60,217), XX3_MASK
, PPCVSX
, PPCVLE
, {XT6
, XA6
, XB6
}},
7226 {"xvcvsxdsp", XX2(60,440), XX2_MASK
, PPCVSX
, PPCVLE
, {XT6
, XB6
}},
7227 {"xvnegsp", XX2(60,441), XX2_MASK
, PPCVSX
, PPCVLE
, {XT6
, XB6
}},
7228 {"xvmaxdp", XX3(60,224), XX3_MASK
, PPCVSX
, PPCVLE
, {XT6
, XA6
, XB6
}},
7229 {"xvnmaddadp", XX3(60,225), XX3_MASK
, PPCVSX
, PPCVLE
, {XT6
, XA6
, XB6
}},
7230 {"xvcvdpuxds", XX2(60,456), XX2_MASK
, PPCVSX
, PPCVLE
, {XT6
, XB6
}},
7231 {"xvcvspdp", XX2(60,457), XX2_MASK
, PPCVSX
, PPCVLE
, {XT6
, XB6
}},
7232 {"xsiexpdp", X(60,918), XX1_MASK
, PPCVSX3
, PPCVLE
, {XT6
, RA
, RB
}},
7233 {"xvmindp", XX3(60,232), XX3_MASK
, PPCVSX
, PPCVLE
, {XT6
, XA6
, XB6
}},
7234 {"xvnmaddmdp", XX3(60,233), XX3_MASK
, PPCVSX
, PPCVLE
, {XT6
, XA6
, XB6
}},
7235 {"xvcvdpsxds", XX2(60,472), XX2_MASK
, PPCVSX
, PPCVLE
, {XT6
, XB6
}},
7236 {"xvabsdp", XX2(60,473), XX2_MASK
, PPCVSX
, PPCVLE
, {XT6
, XB6
}},
7237 {"xvxexpdp", XX2VA(60,475,0),XX2_MASK
, PPCVSX3
, PPCVLE
, {XT6
, XB6
}},
7238 {"xvxsigdp", XX2VA(60,475,1),XX2_MASK
, PPCVSX3
, PPCVLE
, {XT6
, XB6
}},
7239 {"xxbrh", XX2VA(60,475,7),XX2_MASK
, PPCVSX3
, PPCVLE
, {XT6
, XB6
}},
7240 {"xvxexpsp", XX2VA(60,475,8),XX2_MASK
, PPCVSX3
, PPCVLE
, {XT6
, XB6
}},
7241 {"xvxsigsp", XX2VA(60,475,9),XX2_MASK
, PPCVSX3
, PPCVLE
, {XT6
, XB6
}},
7242 {"xxbrw", XX2VA(60,475,15),XX2_MASK
, PPCVSX3
, PPCVLE
, {XT6
, XB6
}},
7243 {"xxbrd", XX2VA(60,475,23),XX2_MASK
, PPCVSX3
, PPCVLE
, {XT6
, XB6
}},
7244 {"xvcvhpsp", XX2VA(60,475,24),XX2_MASK
, PPCVSX3
, PPCVLE
, {XT6
, XB6
}},
7245 {"xvcvsphp", XX2VA(60,475,25),XX2_MASK
, PPCVSX3
, PPCVLE
, {XT6
, XB6
}},
7246 {"xxbrq", XX2VA(60,475,31),XX2_MASK
, PPCVSX3
, PPCVLE
, {XT6
, XB6
}},
7247 {"xvmovdp", XX3(60,240), XX3_MASK
, PPCVSX
, PPCVLE
, {XT6
, XAB6
}},
7248 {"xvcpsgndp", XX3(60,240), XX3_MASK
, PPCVSX
, PPCVLE
, {XT6
, XA6
, XB6
}},
7249 {"xvnmsubadp", XX3(60,241), XX3_MASK
, PPCVSX
, PPCVLE
, {XT6
, XA6
, XB6
}},
7250 {"xvcvuxddp", XX2(60,488), XX2_MASK
, PPCVSX
, PPCVLE
, {XT6
, XB6
}},
7251 {"xvnabsdp", XX2(60,489), XX2_MASK
, PPCVSX
, PPCVLE
, {XT6
, XB6
}},
7252 {"xvtstdcdp", XX2(60,490), XX2DCMXS_MASK
, PPCVSX3
, PPCVLE
, {XT6
, XB6
, DCMXS
}},
7253 {"xviexpdp", XX3(60,248), XX3_MASK
, PPCVSX3
, PPCVLE
, {XT6
, XA6
, XB6
}},
7254 {"xvnmsubmdp", XX3(60,249), XX3_MASK
, PPCVSX
, PPCVLE
, {XT6
, XA6
, XB6
}},
7255 {"xvcvsxddp", XX2(60,504), XX2_MASK
, PPCVSX
, PPCVLE
, {XT6
, XB6
}},
7256 {"xvnegdp", XX2(60,505), XX2_MASK
, PPCVSX
, PPCVLE
, {XT6
, XB6
}},
7258 {"psq_st", OP(60), OP_MASK
, PPCPS
, PPCVLE
, {FRS
,PSD
,RA
,PSW
,PSQ
}},
7259 {"stfq", OP(60), OP_MASK
, POWER2
, PPCVLE
, {FRS
, D
, RA
}},
7261 {"lxv", DQX(61,1), DQX_MASK
, PPCVSX3
, PPCVLE
, {XTQ6
, DQ
, RA0
}},
7262 {"stxv", DQX(61,5), DQX_MASK
, PPCVSX3
, PPCVLE
, {XSQ6
, DQ
, RA0
}},
7263 {"stxsd", DSO(61,2), DS_MASK
, PPCVSX3
, PPCVLE
, {VS
, DS
, RA0
}},
7264 {"stxssp", DSO(61,3), DS_MASK
, PPCVSX3
, PPCVLE
, {VS
, DS
, RA0
}},
7265 {"stfdp", OP(61), OP_MASK
|Q_MASK
, POWER6
, POWER7
|PPCVLE
, {FRSp
, DS
, RA0
}},
7266 {"psq_stu", OP(61), OP_MASK
, PPCPS
, PPCVLE
, {FRS
,PSD
,RA
,PSW
,PSQ
}},
7267 {"stfqu", OP(61), OP_MASK
, POWER2
, PPCVLE
, {FRS
, D
, RA
}},
7269 {"std", DSO(62,0), DS_MASK
, PPC64
, PPCVLE
, {RS
, DS
, RA0
}},
7270 {"stdu", DSO(62,1), DS_MASK
, PPC64
, PPCVLE
, {RS
, DS
, RAS
}},
7271 {"stq", DSO(62,2), DS_MASK
|Q_MASK
, POWER4
, PPC476
|PPCVLE
, {RSQ
, DS
, RA0
}},
7273 {"fcmpu", X(63,0), XBF_MASK
, COM
, PPCEFS
|PPCVLE
, {BF
, FRA
, FRB
}},
7275 {"daddq", XRC(63,2,0), X_MASK
|Q_MASK
, POWER6
, PPCVLE
, {FRTp
, FRAp
, FRBp
}},
7276 {"daddq.", XRC(63,2,1), X_MASK
|Q_MASK
, POWER6
, PPCVLE
, {FRTp
, FRAp
, FRBp
}},
7278 {"dquaq", ZRC(63,3,0), Z2_MASK
|Q_MASK
, POWER6
, PPCVLE
, {FRTp
, FRAp
, FRBp
, RMC
}},
7279 {"dquaq.", ZRC(63,3,1), Z2_MASK
|Q_MASK
, POWER6
, PPCVLE
, {FRTp
, FRAp
, FRBp
, RMC
}},
7281 {"xsaddqp", XRC(63,4,0), X_MASK
, PPCVSX3
, PPCVLE
, {VD
, VA
, VB
}},
7282 {"xsaddqpo", XRC(63,4,1), X_MASK
, PPCVSX3
, PPCVLE
, {VD
, VA
, VB
}},
7284 {"xsrqpi", ZRC(63,5,0), Z2_MASK
, PPCVSX3
, PPCVLE
, {R
, VD
, VB
, RMC
}},
7285 {"xsrqpix", ZRC(63,5,1), Z2_MASK
, PPCVSX3
, PPCVLE
, {R
, VD
, VB
, RMC
}},
7287 {"fcpsgn", XRC(63,8,0), X_MASK
, POWER6
|PPCA2
|PPC476
, PPCVLE
, {FRT
, FRA
, FRB
}},
7288 {"fcpsgn.", XRC(63,8,1), X_MASK
, POWER6
|PPCA2
|PPC476
, PPCVLE
, {FRT
, FRA
, FRB
}},
7290 {"frsp", XRC(63,12,0), XRA_MASK
, COM
, PPCEFS
|PPCVLE
, {FRT
, FRB
}},
7291 {"frsp.", XRC(63,12,1), XRA_MASK
, COM
, PPCEFS
|PPCVLE
, {FRT
, FRB
}},
7293 {"fctiw", XRC(63,14,0), XRA_MASK
, PPCCOM
, PPCEFS
|PPCVLE
, {FRT
, FRB
}},
7294 {"fcir", XRC(63,14,0), XRA_MASK
, PWR2COM
, PPCVLE
, {FRT
, FRB
}},
7295 {"fctiw.", XRC(63,14,1), XRA_MASK
, PPCCOM
, PPCEFS
|PPCVLE
, {FRT
, FRB
}},
7296 {"fcir.", XRC(63,14,1), XRA_MASK
, PWR2COM
, PPCVLE
, {FRT
, FRB
}},
7298 {"fctiwz", XRC(63,15,0), XRA_MASK
, PPCCOM
, PPCEFS
|PPCVLE
, {FRT
, FRB
}},
7299 {"fcirz", XRC(63,15,0), XRA_MASK
, PWR2COM
, PPCVLE
, {FRT
, FRB
}},
7300 {"fctiwz.", XRC(63,15,1), XRA_MASK
, PPCCOM
, PPCEFS
|PPCVLE
, {FRT
, FRB
}},
7301 {"fcirz.", XRC(63,15,1), XRA_MASK
, PWR2COM
, PPCVLE
, {FRT
, FRB
}},
7303 {"fdiv", A(63,18,0), AFRC_MASK
, PPCCOM
, PPCEFS
|PPCVLE
, {FRT
, FRA
, FRB
}},
7304 {"fd", A(63,18,0), AFRC_MASK
, PWRCOM
, PPCVLE
, {FRT
, FRA
, FRB
}},
7305 {"fdiv.", A(63,18,1), AFRC_MASK
, PPCCOM
, PPCEFS
|PPCVLE
, {FRT
, FRA
, FRB
}},
7306 {"fd.", A(63,18,1), AFRC_MASK
, PWRCOM
, PPCVLE
, {FRT
, FRA
, FRB
}},
7308 {"fsub", A(63,20,0), AFRC_MASK
, PPCCOM
, PPCEFS
|PPCVLE
, {FRT
, FRA
, FRB
}},
7309 {"fs", A(63,20,0), AFRC_MASK
, PWRCOM
, PPCVLE
, {FRT
, FRA
, FRB
}},
7310 {"fsub.", A(63,20,1), AFRC_MASK
, PPCCOM
, PPCEFS
|PPCVLE
, {FRT
, FRA
, FRB
}},
7311 {"fs.", A(63,20,1), AFRC_MASK
, PWRCOM
, PPCVLE
, {FRT
, FRA
, FRB
}},
7313 {"fadd", A(63,21,0), AFRC_MASK
, PPCCOM
, PPCEFS
|PPCVLE
, {FRT
, FRA
, FRB
}},
7314 {"fa", A(63,21,0), AFRC_MASK
, PWRCOM
, PPCVLE
, {FRT
, FRA
, FRB
}},
7315 {"fadd.", A(63,21,1), AFRC_MASK
, PPCCOM
, PPCEFS
|PPCVLE
, {FRT
, FRA
, FRB
}},
7316 {"fa.", A(63,21,1), AFRC_MASK
, PWRCOM
, PPCVLE
, {FRT
, FRA
, FRB
}},
7318 {"fsqrt", A(63,22,0), AFRAFRC_MASK
, PPCPWR2
, TITAN
|PPCVLE
, {FRT
, FRB
}},
7319 {"fsqrt.", A(63,22,1), AFRAFRC_MASK
, PPCPWR2
, TITAN
|PPCVLE
, {FRT
, FRB
}},
7321 {"fsel", A(63,23,0), A_MASK
, PPC
, PPCEFS
|PPCVLE
, {FRT
, FRA
, FRC
, FRB
}},
7322 {"fsel.", A(63,23,1), A_MASK
, PPC
, PPCEFS
|PPCVLE
, {FRT
, FRA
, FRC
, FRB
}},
7324 {"fre", A(63,24,0), AFRAFRC_MASK
, POWER7
, PPCVLE
, {FRT
, FRB
}},
7325 {"fre", A(63,24,0), AFRALFRC_MASK
, POWER5
, POWER7
|PPCVLE
, {FRT
, FRB
, A_L
}},
7326 {"fre.", A(63,24,1), AFRAFRC_MASK
, POWER7
, PPCVLE
, {FRT
, FRB
}},
7327 {"fre.", A(63,24,1), AFRALFRC_MASK
, POWER5
, POWER7
|PPCVLE
, {FRT
, FRB
, A_L
}},
7329 {"fmul", A(63,25,0), AFRB_MASK
, PPCCOM
, PPCEFS
|PPCVLE
, {FRT
, FRA
, FRC
}},
7330 {"fm", A(63,25,0), AFRB_MASK
, PWRCOM
, PPCVLE
|PPCVLE
, {FRT
, FRA
, FRC
}},
7331 {"fmul.", A(63,25,1), AFRB_MASK
, PPCCOM
, PPCEFS
|PPCVLE
, {FRT
, FRA
, FRC
}},
7332 {"fm.", A(63,25,1), AFRB_MASK
, PWRCOM
, PPCVLE
|PPCVLE
, {FRT
, FRA
, FRC
}},
7334 {"frsqrte", A(63,26,0), AFRAFRC_MASK
, POWER7
, PPCVLE
, {FRT
, FRB
}},
7335 {"frsqrte", A(63,26,0), AFRALFRC_MASK
, PPC
, POWER7
|PPCVLE
, {FRT
, FRB
, A_L
}},
7336 {"frsqrte.", A(63,26,1), AFRAFRC_MASK
, POWER7
, PPCVLE
, {FRT
, FRB
}},
7337 {"frsqrte.", A(63,26,1), AFRALFRC_MASK
, PPC
, POWER7
|PPCVLE
, {FRT
, FRB
, A_L
}},
7339 {"fmsub", A(63,28,0), A_MASK
, PPCCOM
, PPCEFS
|PPCVLE
, {FRT
, FRA
, FRC
, FRB
}},
7340 {"fms", A(63,28,0), A_MASK
, PWRCOM
, PPCVLE
, {FRT
, FRA
, FRC
, FRB
}},
7341 {"fmsub.", A(63,28,1), A_MASK
, PPCCOM
, PPCEFS
|PPCVLE
, {FRT
, FRA
, FRC
, FRB
}},
7342 {"fms.", A(63,28,1), A_MASK
, PWRCOM
, PPCVLE
, {FRT
, FRA
, FRC
, FRB
}},
7344 {"fmadd", A(63,29,0), A_MASK
, PPCCOM
, PPCEFS
|PPCVLE
, {FRT
, FRA
, FRC
, FRB
}},
7345 {"fma", A(63,29,0), A_MASK
, PWRCOM
, PPCVLE
, {FRT
, FRA
, FRC
, FRB
}},
7346 {"fmadd.", A(63,29,1), A_MASK
, PPCCOM
, PPCEFS
|PPCVLE
, {FRT
, FRA
, FRC
, FRB
}},
7347 {"fma.", A(63,29,1), A_MASK
, PWRCOM
, PPCVLE
, {FRT
, FRA
, FRC
, FRB
}},
7349 {"fnmsub", A(63,30,0), A_MASK
, PPCCOM
, PPCEFS
|PPCVLE
, {FRT
, FRA
, FRC
, FRB
}},
7350 {"fnms", A(63,30,0), A_MASK
, PWRCOM
, PPCVLE
, {FRT
, FRA
, FRC
, FRB
}},
7351 {"fnmsub.", A(63,30,1), A_MASK
, PPCCOM
, PPCEFS
|PPCVLE
, {FRT
, FRA
, FRC
, FRB
}},
7352 {"fnms.", A(63,30,1), A_MASK
, PWRCOM
, PPCVLE
, {FRT
, FRA
, FRC
, FRB
}},
7354 {"fnmadd", A(63,31,0), A_MASK
, PPCCOM
, PPCEFS
|PPCVLE
, {FRT
, FRA
, FRC
, FRB
}},
7355 {"fnma", A(63,31,0), A_MASK
, PWRCOM
, PPCVLE
, {FRT
, FRA
, FRC
, FRB
}},
7356 {"fnmadd.", A(63,31,1), A_MASK
, PPCCOM
, PPCEFS
|PPCVLE
, {FRT
, FRA
, FRC
, FRB
}},
7357 {"fnma.", A(63,31,1), A_MASK
, PWRCOM
, PPCVLE
, {FRT
, FRA
, FRC
, FRB
}},
7359 {"fcmpo", X(63,32), XBF_MASK
, COM
, PPCEFS
|PPCVLE
, {BF
, FRA
, FRB
}},
7361 {"dmulq", XRC(63,34,0), X_MASK
|Q_MASK
, POWER6
, PPCVLE
, {FRTp
, FRAp
, FRBp
}},
7362 {"dmulq.", XRC(63,34,1), X_MASK
|Q_MASK
, POWER6
, PPCVLE
, {FRTp
, FRAp
, FRBp
}},
7364 {"drrndq", ZRC(63,35,0), Z2_MASK
|Q_MASK
, POWER6
, PPCVLE
, {FRTp
, FRA
, FRBp
, RMC
}},
7365 {"drrndq.", ZRC(63,35,1), Z2_MASK
|Q_MASK
, POWER6
, PPCVLE
, {FRTp
, FRA
, FRBp
, RMC
}},
7367 {"xsmulqp", XRC(63,36,0), X_MASK
, PPCVSX3
, PPCVLE
, {VD
, VA
, VB
}},
7368 {"xsmulqpo", XRC(63,36,1), X_MASK
, PPCVSX3
, PPCVLE
, {VD
, VA
, VB
}},
7370 {"xsrqpxp", Z(63,37), Z2_MASK
, PPCVSX3
, PPCVLE
, {R
, VD
, VB
, RMC
}},
7372 {"mtfsb1", XRC(63,38,0), XRARB_MASK
, COM
, PPCVLE
, {BT
}},
7373 {"mtfsb1.", XRC(63,38,1), XRARB_MASK
, COM
, PPCVLE
, {BT
}},
7375 {"fneg", XRC(63,40,0), XRA_MASK
, COM
, PPCEFS
|PPCVLE
, {FRT
, FRB
}},
7376 {"fneg.", XRC(63,40,1), XRA_MASK
, COM
, PPCEFS
|PPCVLE
, {FRT
, FRB
}},
7378 {"mcrfs", X(63,64), XRB_MASK
|(3<<21)|(3<<16), COM
, PPCVLE
, {BF
, BFA
}},
7380 {"dscliq", ZRC(63,66,0), Z_MASK
|Q_MASK
, POWER6
, PPCVLE
, {FRTp
, FRAp
, SH16
}},
7381 {"dscliq.", ZRC(63,66,1), Z_MASK
|Q_MASK
, POWER6
, PPCVLE
, {FRTp
, FRAp
, SH16
}},
7383 {"dquaiq", ZRC(63,67,0), Z2_MASK
|Q_MASK
, POWER6
, PPCVLE
, {TE
, FRTp
, FRBp
, RMC
}},
7384 {"dquaiq.", ZRC(63,67,1), Z2_MASK
|Q_MASK
, POWER6
, PPCVLE
, {TE
, FRTp
, FRBp
, RMC
}},
7386 {"mtfsb0", XRC(63,70,0), XRARB_MASK
, COM
, PPCVLE
, {BT
}},
7387 {"mtfsb0.", XRC(63,70,1), XRARB_MASK
, COM
, PPCVLE
, {BT
}},
7389 {"fmr", XRC(63,72,0), XRA_MASK
, COM
, PPCEFS
|PPCVLE
, {FRT
, FRB
}},
7390 {"fmr.", XRC(63,72,1), XRA_MASK
, COM
, PPCEFS
|PPCVLE
, {FRT
, FRB
}},
7392 {"dscriq", ZRC(63,98,0), Z_MASK
|Q_MASK
, POWER6
, PPCVLE
, {FRTp
, FRAp
, SH16
}},
7393 {"dscriq.", ZRC(63,98,1), Z_MASK
|Q_MASK
, POWER6
, PPCVLE
, {FRTp
, FRAp
, SH16
}},
7395 {"drintxq", ZRC(63,99,0), Z2_MASK
|Q_MASK
, POWER6
, PPCVLE
, {R
, FRTp
, FRBp
, RMC
}},
7396 {"drintxq.", ZRC(63,99,1), Z2_MASK
|Q_MASK
, POWER6
, PPCVLE
, {R
, FRTp
, FRBp
, RMC
}},
7398 {"xscpsgnqp", X(63,100), X_MASK
, PPCVSX3
, PPCVLE
, {VD
, VA
, VB
}},
7400 {"ftdiv", X(63,128), XBF_MASK
, POWER7
, PPCVLE
, {BF
, FRA
, FRB
}},
7402 {"dcmpoq", X(63,130), X_MASK
, POWER6
, PPCVLE
, {BF
, FRAp
, FRBp
}},
7404 {"xscmpoqp", X(63,132), XBF_MASK
, PPCVSX3
, PPCVLE
, {BF
, VA
, VB
}},
7406 {"mtfsfi", XRC(63,134,0), XWRA_MASK
|(3<<21)|(1<<11), POWER6
|PPCA2
|PPC476
, PPCVLE
, {BFF
, U
, W
}},
7407 {"mtfsfi", XRC(63,134,0), XRA_MASK
|(3<<21)|(1<<11), COM
, POWER6
|PPCA2
|PPC476
|PPCVLE
, {BFF
, U
}},
7408 {"mtfsfi.", XRC(63,134,1), XWRA_MASK
|(3<<21)|(1<<11), POWER6
|PPCA2
|PPC476
, PPCVLE
, {BFF
, U
, W
}},
7409 {"mtfsfi.", XRC(63,134,1), XRA_MASK
|(3<<21)|(1<<11), COM
, POWER6
|PPCA2
|PPC476
|PPCVLE
, {BFF
, U
}},
7411 {"fnabs", XRC(63,136,0), XRA_MASK
, COM
, PPCEFS
|PPCVLE
, {FRT
, FRB
}},
7412 {"fnabs.", XRC(63,136,1), XRA_MASK
, COM
, PPCEFS
|PPCVLE
, {FRT
, FRB
}},
7414 {"fctiwu", XRC(63,142,0), XRA_MASK
, POWER7
, PPCVLE
, {FRT
, FRB
}},
7415 {"fctiwu.", XRC(63,142,1), XRA_MASK
, POWER7
, PPCVLE
, {FRT
, FRB
}},
7416 {"fctiwuz", XRC(63,143,0), XRA_MASK
, POWER7
, PPCVLE
, {FRT
, FRB
}},
7417 {"fctiwuz.", XRC(63,143,1), XRA_MASK
, POWER7
, PPCVLE
, {FRT
, FRB
}},
7419 {"ftsqrt", X(63,160), XBF_MASK
|FRA_MASK
, POWER7
, PPCVLE
, {BF
, FRB
}},
7421 {"dtstexq", X(63,162), X_MASK
, POWER6
, PPCVLE
, {BF
, FRAp
, FRBp
}},
7423 {"xscmpexpqp", X(63,164), XBF_MASK
, PPCVSX3
, PPCVLE
, {BF
, VA
, VB
}},
7425 {"dtstdcq", Z(63,194), Z_MASK
, POWER6
, PPCVLE
, {BF
, FRAp
, DCM
}},
7426 {"dtstdgq", Z(63,226), Z_MASK
, POWER6
, PPCVLE
, {BF
, FRAp
, DGM
}},
7428 {"drintnq", ZRC(63,227,0), Z2_MASK
|Q_MASK
, POWER6
, PPCVLE
, {R
, FRTp
, FRBp
, RMC
}},
7429 {"drintnq.", ZRC(63,227,1), Z2_MASK
|Q_MASK
, POWER6
, PPCVLE
, {R
, FRTp
, FRBp
, RMC
}},
7431 {"dctqpq", XRC(63,258,0), X_MASK
|Q_MASK
, POWER6
, PPCVLE
, {FRTp
, FRB
}},
7432 {"dctqpq.", XRC(63,258,1), X_MASK
|Q_MASK
, POWER6
, PPCVLE
, {FRTp
, FRB
}},
7434 {"fabs", XRC(63,264,0), XRA_MASK
, COM
, PPCEFS
|PPCVLE
, {FRT
, FRB
}},
7435 {"fabs.", XRC(63,264,1), XRA_MASK
, COM
, PPCEFS
|PPCVLE
, {FRT
, FRB
}},
7437 {"dctfixq", XRC(63,290,0), X_MASK
, POWER6
, PPCVLE
, {FRT
, FRBp
}},
7438 {"dctfixq.", XRC(63,290,1), X_MASK
, POWER6
, PPCVLE
, {FRT
, FRBp
}},
7440 {"ddedpdq", XRC(63,322,0), X_MASK
|Q_MASK
, POWER6
, PPCVLE
, {SP
, FRTp
, FRBp
}},
7441 {"ddedpdq.", XRC(63,322,1), X_MASK
|Q_MASK
, POWER6
, PPCVLE
, {SP
, FRTp
, FRBp
}},
7443 {"dxexq", XRC(63,354,0), X_MASK
, POWER6
, PPCVLE
, {FRT
, FRBp
}},
7444 {"dxexq.", XRC(63,354,1), X_MASK
, POWER6
, PPCVLE
, {FRT
, FRBp
}},
7446 {"xsmaddqp", XRC(63,388,0), X_MASK
, PPCVSX3
, PPCVLE
, {VD
, VA
, VB
}},
7447 {"xsmaddqpo", XRC(63,388,1), X_MASK
, PPCVSX3
, PPCVLE
, {VD
, VA
, VB
}},
7449 {"frin", XRC(63,392,0), XRA_MASK
, POWER5
, PPCVLE
, {FRT
, FRB
}},
7450 {"frin.", XRC(63,392,1), XRA_MASK
, POWER5
, PPCVLE
, {FRT
, FRB
}},
7452 {"xsmsubqp", XRC(63,420,0), X_MASK
, PPCVSX3
, PPCVLE
, {VD
, VA
, VB
}},
7453 {"xsmsubqpo", XRC(63,420,1), X_MASK
, PPCVSX3
, PPCVLE
, {VD
, VA
, VB
}},
7455 {"friz", XRC(63,424,0), XRA_MASK
, POWER5
, PPCVLE
, {FRT
, FRB
}},
7456 {"friz.", XRC(63,424,1), XRA_MASK
, POWER5
, PPCVLE
, {FRT
, FRB
}},
7458 {"xsnmaddqp", XRC(63,452,0), X_MASK
, PPCVSX3
, PPCVLE
, {VD
, VA
, VB
}},
7459 {"xsnmaddqpo", XRC(63,452,1), X_MASK
, PPCVSX3
, PPCVLE
, {VD
, VA
, VB
}},
7461 {"frip", XRC(63,456,0), XRA_MASK
, POWER5
, PPCVLE
, {FRT
, FRB
}},
7462 {"frip.", XRC(63,456,1), XRA_MASK
, POWER5
, PPCVLE
, {FRT
, FRB
}},
7464 {"xsnmsubqp", XRC(63,484,0), X_MASK
, PPCVSX3
, PPCVLE
, {VD
, VA
, VB
}},
7465 {"xsnmsubqpo", XRC(63,484,1), X_MASK
, PPCVSX3
, PPCVLE
, {VD
, VA
, VB
}},
7467 {"frim", XRC(63,488,0), XRA_MASK
, POWER5
, PPCVLE
, {FRT
, FRB
}},
7468 {"frim.", XRC(63,488,1), XRA_MASK
, POWER5
, PPCVLE
, {FRT
, FRB
}},
7470 {"dsubq", XRC(63,514,0), X_MASK
|Q_MASK
, POWER6
, PPCVLE
, {FRTp
, FRAp
, FRBp
}},
7471 {"dsubq.", XRC(63,514,1), X_MASK
|Q_MASK
, POWER6
, PPCVLE
, {FRTp
, FRAp
, FRBp
}},
7473 {"xssubqp", XRC(63,516,0), X_MASK
, PPCVSX3
, PPCVLE
, {VD
, VA
, VB
}},
7474 {"xssubqpo", XRC(63,516,1), X_MASK
, PPCVSX3
, PPCVLE
, {VD
, VA
, VB
}},
7476 {"ddivq", XRC(63,546,0), X_MASK
|Q_MASK
, POWER6
, PPCVLE
, {FRTp
, FRAp
, FRBp
}},
7477 {"ddivq.", XRC(63,546,1), X_MASK
|Q_MASK
, POWER6
, PPCVLE
, {FRTp
, FRAp
, FRBp
}},
7479 {"xsdivqp", XRC(63,548,0), X_MASK
, PPCVSX3
, PPCVLE
, {VD
, VA
, VB
}},
7480 {"xsdivqpo", XRC(63,548,1), X_MASK
, PPCVSX3
, PPCVLE
, {VD
, VA
, VB
}},
7482 {"mffs", XRC(63,583,0), XRARB_MASK
, COM
, PPCEFS
|PPCVLE
, {FRT
}},
7483 {"mffs.", XRC(63,583,1), XRARB_MASK
, COM
, PPCEFS
|PPCVLE
, {FRT
}},
7485 {"mffsce", XMMF(63,583,0,1), XMMF_MASK
|RB_MASK
, POWER9
, PPCVLE
, {FRT
}},
7486 {"mffscdrn", XMMF(63,583,2,4), XMMF_MASK
, POWER9
, PPCVLE
, {FRT
, FRB
}},
7487 {"mffscdrni", XMMF(63,583,2,5), XMMF_MASK
|(3<<14), POWER9
, PPCVLE
, {FRT
, DRM
}},
7488 {"mffscrn", XMMF(63,583,2,6), XMMF_MASK
, POWER9
, PPCVLE
, {FRT
, FRB
}},
7489 {"mffscrni", XMMF(63,583,2,7), XMMF_MASK
|(7<<13), POWER9
, PPCVLE
, {FRT
, RM
}},
7490 {"mffsl", XMMF(63,583,3,0), XMMF_MASK
|RB_MASK
, POWER9
, PPCVLE
, {FRT
}},
7492 {"dcmpuq", X(63,642), X_MASK
, POWER6
, PPCVLE
, {BF
, FRAp
, FRBp
}},
7494 {"xscmpuqp", X(63,644), XBF_MASK
, PPCVSX3
, PPCVLE
, {BF
, VA
, VB
}},
7496 {"dtstsfq", X(63,674), X_MASK
, POWER6
, PPCVLE
, {BF
, FRA
, FRBp
}},
7497 {"dtstsfiq", X(63,675), X_MASK
|1<<22,POWER9
, PPCVLE
, {BF
, UIM6
, FRBp
}},
7499 {"xststdcqp", X(63,708), X_MASK
, PPCVSX3
, PPCVLE
, {BF
, VB
, DCMX
}},
7501 {"mtfsf", XFL(63,711,0), XFL_MASK
, POWER6
|PPCA2
|PPC476
, PPCVLE
, {FLM
, FRB
, XFL_L
, W
}},
7502 {"mtfsf", XFL(63,711,0), XFL_MASK
, COM
, POWER6
|PPCA2
|PPC476
|PPCEFS
|PPCVLE
, {FLM
, FRB
}},
7503 {"mtfsf.", XFL(63,711,1), XFL_MASK
, POWER6
|PPCA2
|PPC476
, PPCVLE
, {FLM
, FRB
, XFL_L
, W
}},
7504 {"mtfsf.", XFL(63,711,1), XFL_MASK
, COM
, POWER6
|PPCA2
|PPC476
|PPCEFS
|PPCVLE
, {FLM
, FRB
}},
7506 {"drdpq", XRC(63,770,0), X_MASK
|Q_MASK
, POWER6
, PPCVLE
, {FRTp
, FRBp
}},
7507 {"drdpq.", XRC(63,770,1), X_MASK
|Q_MASK
, POWER6
, PPCVLE
, {FRTp
, FRBp
}},
7509 {"dcffixq", XRC(63,802,0), X_MASK
|Q_MASK
, POWER6
, PPCVLE
, {FRTp
, FRB
}},
7510 {"dcffixq.", XRC(63,802,1), X_MASK
|Q_MASK
, POWER6
, PPCVLE
, {FRTp
, FRB
}},
7512 {"xsabsqp", XVA(63,804,0), XVA_MASK
, PPCVSX3
, PPCVLE
, {VD
, VB
}},
7513 {"xsxexpqp", XVA(63,804,2), XVA_MASK
, PPCVSX3
, PPCVLE
, {VD
, VB
}},
7514 {"xsnabsqp", XVA(63,804,8), XVA_MASK
, PPCVSX3
, PPCVLE
, {VD
, VB
}},
7515 {"xsnegqp", XVA(63,804,16), XVA_MASK
, PPCVSX3
, PPCVLE
, {VD
, VB
}},
7516 {"xsxsigqp", XVA(63,804,18), XVA_MASK
, PPCVSX3
, PPCVLE
, {VD
, VB
}},
7517 {"xssqrtqp", XVARC(63,804,27,0), XVA_MASK
, PPCVSX3
, PPCVLE
, {VD
, VB
}},
7518 {"xssqrtqpo", XVARC(63,804,27,1), XVA_MASK
, PPCVSX3
, PPCVLE
, {VD
, VB
}},
7520 {"fctid", XRC(63,814,0), XRA_MASK
, PPC64
, PPCVLE
, {FRT
, FRB
}},
7521 {"fctid", XRC(63,814,0), XRA_MASK
, PPC476
, PPCVLE
, {FRT
, FRB
}},
7522 {"fctid.", XRC(63,814,1), XRA_MASK
, PPC64
, PPCVLE
, {FRT
, FRB
}},
7523 {"fctid.", XRC(63,814,1), XRA_MASK
, PPC476
, PPCVLE
, {FRT
, FRB
}},
7525 {"fctidz", XRC(63,815,0), XRA_MASK
, PPC64
, PPCVLE
, {FRT
, FRB
}},
7526 {"fctidz", XRC(63,815,0), XRA_MASK
, PPC476
, PPCVLE
, {FRT
, FRB
}},
7527 {"fctidz.", XRC(63,815,1), XRA_MASK
, PPC64
, PPCVLE
, {FRT
, FRB
}},
7528 {"fctidz.", XRC(63,815,1), XRA_MASK
, PPC476
, PPCVLE
, {FRT
, FRB
}},
7530 {"denbcdq", XRC(63,834,0), X_MASK
|Q_MASK
, POWER6
, PPCVLE
, {S
, FRTp
, FRBp
}},
7531 {"denbcdq.", XRC(63,834,1), X_MASK
|Q_MASK
, POWER6
, PPCVLE
, {S
, FRTp
, FRBp
}},
7533 {"xscvqpuwz", XVA(63,836,1), XVA_MASK
, PPCVSX3
, PPCVLE
, {VD
, VB
}},
7534 {"xscvudqp", XVA(63,836,2), XVA_MASK
, PPCVSX3
, PPCVLE
, {VD
, VB
}},
7535 {"xscvqpswz", XVA(63,836,9), XVA_MASK
, PPCVSX3
, PPCVLE
, {VD
, VB
}},
7536 {"xscvsdqp", XVA(63,836,10), XVA_MASK
, PPCVSX3
, PPCVLE
, {VD
, VB
}},
7537 {"xscvqpudz", XVA(63,836,17), XVA_MASK
, PPCVSX3
, PPCVLE
, {VD
, VB
}},
7538 {"xscvqpdp", XVARC(63,836,20,0), XVA_MASK
, PPCVSX3
, PPCVLE
, {VD
, VB
}},
7539 {"xscvqpdpo", XVARC(63,836,20,1), XVA_MASK
, PPCVSX3
, PPCVLE
, {VD
, VB
}},
7540 {"xscvdpqp", XVA(63,836,22), XVA_MASK
, PPCVSX3
, PPCVLE
, {VD
, VB
}},
7541 {"xscvqpsdz", XVA(63,836,25), XVA_MASK
, PPCVSX3
, PPCVLE
, {VD
, VB
}},
7543 {"fmrgow", X(63,838), X_MASK
, PPCVSX2
, PPCVLE
, {FRT
, FRA
, FRB
}},
7545 {"fcfid", XRC(63,846,0), XRA_MASK
, PPC64
, PPCVLE
, {FRT
, FRB
}},
7546 {"fcfid", XRC(63,846,0), XRA_MASK
, PPC476
, PPCVLE
, {FRT
, FRB
}},
7547 {"fcfid.", XRC(63,846,1), XRA_MASK
, PPC64
, PPCVLE
, {FRT
, FRB
}},
7548 {"fcfid.", XRC(63,846,1), XRA_MASK
, PPC476
, PPCVLE
, {FRT
, FRB
}},
7550 {"diexq", XRC(63,866,0), X_MASK
|Q_MASK
, POWER6
, PPCVLE
, {FRTp
, FRA
, FRBp
}},
7551 {"diexq.", XRC(63,866,1), X_MASK
|Q_MASK
, POWER6
, PPCVLE
, {FRTp
, FRA
, FRBp
}},
7553 {"xsiexpqp", X(63,868), X_MASK
, PPCVSX3
, PPCVLE
, {VD
, VA
, VB
}},
7555 {"fctidu", XRC(63,942,0), XRA_MASK
, POWER7
|PPCA2
, PPCVLE
, {FRT
, FRB
}},
7556 {"fctidu.", XRC(63,942,1), XRA_MASK
, POWER7
|PPCA2
, PPCVLE
, {FRT
, FRB
}},
7558 {"fctiduz", XRC(63,943,0), XRA_MASK
, POWER7
|PPCA2
, PPCVLE
, {FRT
, FRB
}},
7559 {"fctiduz.", XRC(63,943,1), XRA_MASK
, POWER7
|PPCA2
, PPCVLE
, {FRT
, FRB
}},
7561 {"fmrgew", X(63,966), X_MASK
, PPCVSX2
, PPCVLE
, {FRT
, FRA
, FRB
}},
7563 {"fcfidu", XRC(63,974,0), XRA_MASK
, POWER7
|PPCA2
, PPCVLE
, {FRT
, FRB
}},
7564 {"fcfidu.", XRC(63,974,1), XRA_MASK
, POWER7
|PPCA2
, PPCVLE
, {FRT
, FRB
}},
7567 const unsigned int powerpc_num_opcodes
=
7568 sizeof (powerpc_opcodes
) / sizeof (powerpc_opcodes
[0]);
7570 /* The VLE opcode table.
7572 The format of this opcode table is the same as the main opcode table. */
7574 const struct powerpc_opcode vle_opcodes
[] = {
7575 {"se_illegal", C(0), C_MASK
, PPCVLE
, 0, {}},
7576 {"se_isync", C(1), C_MASK
, PPCVLE
, 0, {}},
7577 {"se_sc", C(2), C_MASK
, PPCVLE
, 0, {}},
7578 {"se_blr", C_LK(2,0), C_LK_MASK
, PPCVLE
, 0, {}},
7579 {"se_blrl", C_LK(2,1), C_LK_MASK
, PPCVLE
, 0, {}},
7580 {"se_bctr", C_LK(3,0), C_LK_MASK
, PPCVLE
, 0, {}},
7581 {"se_bctrl", C_LK(3,1), C_LK_MASK
, PPCVLE
, 0, {}},
7582 {"se_rfi", C(8), C_MASK
, PPCVLE
, 0, {}},
7583 {"se_rfci", C(9), C_MASK
, PPCVLE
, 0, {}},
7584 {"se_rfdi", C(10), C_MASK
, PPCVLE
, 0, {}},
7585 {"se_rfmci", C(11), C_MASK
, PPCRFMCI
|PPCVLE
, 0, {}},
7586 {"se_rfgi", C(12), C_MASK
, PPCVLE
, 0, {}},
7587 {"se_not", SE_R(0,2), SE_R_MASK
, PPCVLE
, 0, {RX
}},
7588 {"se_neg", SE_R(0,3), SE_R_MASK
, PPCVLE
, 0, {RX
}},
7589 {"se_mflr", SE_R(0,8), SE_R_MASK
, PPCVLE
, 0, {RX
}},
7590 {"se_mtlr", SE_R(0,9), SE_R_MASK
, PPCVLE
, 0, {RX
}},
7591 {"se_mfctr", SE_R(0,10), SE_R_MASK
, PPCVLE
, 0, {RX
}},
7592 {"se_mtctr", SE_R(0,11), SE_R_MASK
, PPCVLE
, 0, {RX
}},
7593 {"se_extzb", SE_R(0,12), SE_R_MASK
, PPCVLE
, 0, {RX
}},
7594 {"se_extsb", SE_R(0,13), SE_R_MASK
, PPCVLE
, 0, {RX
}},
7595 {"se_extzh", SE_R(0,14), SE_R_MASK
, PPCVLE
, 0, {RX
}},
7596 {"se_extsh", SE_R(0,15), SE_R_MASK
, PPCVLE
, 0, {RX
}},
7597 {"se_mr", SE_RR(0,1), SE_RR_MASK
, PPCVLE
, 0, {RX
, RY
}},
7598 {"se_mtar", SE_RR(0,2), SE_RR_MASK
, PPCVLE
, 0, {ARX
, RY
}},
7599 {"se_mfar", SE_RR(0,3), SE_RR_MASK
, PPCVLE
, 0, {RX
, ARY
}},
7600 {"se_add", SE_RR(1,0), SE_RR_MASK
, PPCVLE
, 0, {RX
, RY
}},
7601 {"se_mullw", SE_RR(1,1), SE_RR_MASK
, PPCVLE
, 0, {RX
, RY
}},
7602 {"se_sub", SE_RR(1,2), SE_RR_MASK
, PPCVLE
, 0, {RX
, RY
}},
7603 {"se_subf", SE_RR(1,3), SE_RR_MASK
, PPCVLE
, 0, {RX
, RY
}},
7604 {"se_cmp", SE_RR(3,0), SE_RR_MASK
, PPCVLE
, 0, {RX
, RY
}},
7605 {"se_cmpl", SE_RR(3,1), SE_RR_MASK
, PPCVLE
, 0, {RX
, RY
}},
7606 {"se_cmph", SE_RR(3,2), SE_RR_MASK
, PPCVLE
, 0, {RX
, RY
}},
7607 {"se_cmphl", SE_RR(3,3), SE_RR_MASK
, PPCVLE
, 0, {RX
, RY
}},
7609 /* by major opcode */
7610 {"zvaddih", VX(4, 0x200), VX_MASK
, PPCLSP
, 0, {RD
, RA
, EVUIMM
}},
7611 {"zvsubifh", VX(4, 0x201), VX_MASK
, PPCLSP
, 0, {RD
, RA
, EVUIMM
}},
7612 {"zvaddh", VX(4, 0x204), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
7613 {"zvsubfh", VX(4, 0x205), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
7614 {"zvaddsubfh", VX(4, 0x206), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
7615 {"zvsubfaddh", VX(4, 0x207), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
7616 {"zvaddhx", VX(4, 0x20C), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
7617 {"zvsubfhx", VX(4, 0x20D), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
7618 {"zvaddsubfhx", VX(4, 0x20E), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
7619 {"zvsubfaddhx", VX(4, 0x20F), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
7620 {"zaddwus", VX(4, 0x210), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
7621 {"zsubfwus", VX(4, 0x211), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
7622 {"zaddwss", VX(4, 0x212), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
7623 {"zsubfwss", VX(4, 0x213), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
7624 {"zvaddhus", VX(4, 0x214), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
7625 {"zvsubfhus", VX(4, 0x215), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
7626 {"zvaddhss", VX(4, 0x216), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
7627 {"zvsubfhss", VX(4, 0x217), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
7628 {"zvaddsubfhss", VX(4, 0x21A), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
7629 {"zvsubfaddhss", VX(4, 0x21B), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
7630 {"zvaddhxss", VX(4, 0x21C), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
7631 {"zvsubfhxss", VX(4, 0x21D), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
7632 {"zvaddsubfhxss", VX(4, 0x21E), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
7633 {"zvsubfaddhxss", VX(4, 0x21F), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
7634 {"zaddheuw", VX(4, 0x220), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
7635 {"zsubfheuw", VX(4, 0x221), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
7636 {"zaddhesw", VX(4, 0x222), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
7637 {"zsubfhesw", VX(4, 0x223), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
7638 {"zaddhouw", VX(4, 0x224), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
7639 {"zsubfhouw", VX(4, 0x225), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
7640 {"zaddhosw", VX(4, 0x226), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
7641 {"zsubfhosw", VX(4, 0x227), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
7642 {"zvmergehih", VX(4, 0x22C), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
7643 {"zvmergeloh", VX(4, 0x22D), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
7644 {"zvmergehiloh", VX(4, 0x22E), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
7645 {"zvmergelohih", VX(4, 0x22F), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
7646 {"zvcmpgthu", VX(4, 0x230), VX_MASK
, PPCLSP
, 0, {CRFD
, RA
, RB
}},
7647 {"zvcmpgths", VX(4, 0x230), VX_MASK
, PPCLSP
, 0, {CRFD
, RA
, RB
}},
7648 {"zvcmplthu", VX(4, 0x231), VX_MASK
, PPCLSP
, 0, {CRFD
, RA
, RB
}},
7649 {"zvcmplths", VX(4, 0x231), VX_MASK
, PPCLSP
, 0, {CRFD
, RA
, RB
}},
7650 {"zvcmpeqh", VX(4, 0x232), VX_MASK
, PPCLSP
, 0, {CRFD
, RA
, RB
}},
7651 {"zpkswgshfrs", VX(4, 0x238), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
7652 {"zpkswgswfrs", VX(4, 0x239), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
7653 {"zvpkshgwshfrs", VX(4, 0x23A), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
7654 {"zvpkswshfrs", VX(4, 0x23B), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
7655 {"zvpkswuhs", VX(4, 0x23C), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
7656 {"zvpkswshs", VX(4, 0x23D), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
7657 {"zvpkuwuhs", VX(4, 0x23E), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
7658 {"zvsplatih", VX_LSP(4, 0x23F), VX_LSP_MASK
, PPCLSP
, 0, {RD
, SIMM
}},
7659 {"zvsplatfih", VX_LSP(4, 0xA3F), VX_LSP_MASK
, PPCLSP
, 0, {RD
, SIMM
}},
7660 {"zcntlsw", VX_LSP(4, 0x2A3F), VX_LSP_MASK
, PPCLSP
, 0, {RD
, RA
}},
7661 {"zvcntlzh", VX_LSP(4, 0x323F), VX_LSP_MASK
, PPCLSP
, 0, {RD
, RA
}},
7662 {"zvcntlsh", VX_LSP(4, 0x3A3F), VX_LSP_MASK
, PPCLSP
, 0, {RD
, RA
}},
7663 {"znegws", VX_LSP(4, 0x4A3F), VX_LSP_MASK
, PPCLSP
, 0, {RD
, RA
}},
7664 {"zvnegh", VX_LSP(4, 0x523F), VX_LSP_MASK
, PPCLSP
, 0, {RD
, RA
}},
7665 {"zvneghs", VX_LSP(4, 0x5A3F), VX_LSP_MASK
, PPCLSP
, 0, {RD
, RA
}},
7666 {"zvnegho", VX_LSP(4, 0x623F), VX_LSP_MASK
, PPCLSP
, 0, {RD
, RA
}},
7667 {"zvneghos", VX_LSP(4, 0x6A3F), VX_LSP_MASK
, PPCLSP
, 0, {RD
, RA
}},
7668 {"zrndwh", VX_LSP(4, 0x823F), VX_LSP_MASK
, PPCLSP
, 0, {RD
, RA
}},
7669 {"zrndwhss", VX_LSP(4, 0x8A3F), VX_LSP_MASK
, PPCLSP
, 0, {RD
, RA
}},
7670 {"zvabsh", VX_LSP(4, 0xA23F), VX_LSP_MASK
, PPCLSP
, 0, {RD
, RA
}},
7671 {"zvabshs", VX_LSP(4, 0xAA3F), VX_LSP_MASK
, PPCLSP
, 0, {RD
, RA
}},
7672 {"zabsw", VX_LSP(4, 0xB23F), VX_LSP_MASK
, PPCLSP
, 0, {RD
, RA
}},
7673 {"zabsws", VX_LSP(4, 0xBA3F), VX_LSP_MASK
, PPCLSP
, 0, {RD
, RA
}},
7674 {"zsatswuw", VX_LSP(4, 0xC23F), VX_LSP_MASK
, PPCLSP
, 0, {RD
, RA
}},
7675 {"zsatuwsw", VX_LSP(4, 0xCA3F), VX_LSP_MASK
, PPCLSP
, 0, {RD
, RA
}},
7676 {"zsatswuh", VX_LSP(4, 0xD23F), VX_LSP_MASK
, PPCLSP
, 0, {RD
, RA
}},
7677 {"zsatswsh", VX_LSP(4, 0xDA3F), VX_LSP_MASK
, PPCLSP
, 0, {RD
, RA
}},
7678 {"zvsatshuh", VX_LSP(4, 0xE23F), VX_LSP_MASK
, PPCLSP
, 0, {RD
, RA
}},
7679 {"zvsatuhsh", VX_LSP(4, 0xEA3F), VX_LSP_MASK
, PPCLSP
, 0, {RD
, RA
}},
7680 {"zsatuwuh", VX_LSP(4, 0xF23F), VX_LSP_MASK
, PPCLSP
, 0, {RD
, RA
}},
7681 {"zsatuwsh", VX_LSP(4, 0xFA3F), VX_LSP_MASK
, PPCLSP
, 0, {RD
, RA
}},
7682 {"zsatsduw", VX(4, 0x260), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
7683 {"zsatsdsw", VX(4, 0x261), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
7684 {"zsatuduw", VX(4, 0x262), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
7685 {"zvselh", VX(4, 0x264), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
7686 {"zxtrw", VX(4, 0x264), VX_LSP_OFF_MASK
, PPCLSP
, 0, {RD
, RA
, RB
, VX_OFF
}},
7687 {"zbrminc", VX(4, 0x268), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
7688 {"zcircinc", VX(4, 0x269), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
7689 {"zdivwsf", VX(4, 0x26B), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
7690 {"zvsrhu", VX(4, 0x270), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
7691 {"zvsrhs", VX(4, 0x271), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
7692 {"zvsrhiu", VX(4, 0x272), VX_MASK
, PPCLSP
, 0, {RD
, RA
, EVUIMM_LT16
}},
7693 {"zvsrhis", VX(4, 0x273), VX_MASK
, PPCLSP
, 0, {RD
, RA
, EVUIMM_LT16
}},
7694 {"zvslh", VX(4, 0x274), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
7695 {"zvrlh", VX(4, 0x275), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
7696 {"zvslhi", VX(4, 0x276), VX_MASK
, PPCLSP
, 0, {RD
, RA
, EVUIMM_LT16
}},
7697 {"zvrlhi", VX(4, 0x277), VX_MASK
, PPCLSP
, 0, {RD
, RA
, EVUIMM_LT16
}},
7698 {"zvslhus", VX(4, 0x278), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
7699 {"zvslhss", VX(4, 0x279), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
7700 {"zvslhius", VX(4, 0x27A), VX_MASK
, PPCLSP
, 0, {RD
, RA
, EVUIMM_LT16
}},
7701 {"zvslhiss", VX(4, 0x27B), VX_MASK
, PPCLSP
, 0, {RD
, RA
, EVUIMM_LT16
}},
7702 {"zslwus", VX(4, 0x27C), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
7703 {"zslwss", VX(4, 0x27D), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
7704 {"zslwius", VX(4, 0x27E), VX_MASK
, PPCLSP
, 0, {RD
, RA
, EVUIMM
}},
7705 {"zslwiss", VX(4, 0x27F), VX_MASK
, PPCLSP
, 0, {RD
, RA
, EVUIMM
}},
7706 {"zaddwgui", VX(4, 0x460), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7707 {"zsubfwgui", VX(4, 0x461), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7708 {"zaddd", VX(4, 0x462), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7709 {"zsubfd", VX(4, 0x463), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7710 {"zvaddsubfw", VX(4, 0x464), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7711 {"zvsubfaddw", VX(4, 0x465), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7712 {"zvaddw", VX(4, 0x466), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7713 {"zvsubfw", VX(4, 0x467), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7714 {"zaddwgsi", VX(4, 0x468), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7715 {"zsubfwgsi", VX(4, 0x469), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7716 {"zadddss", VX(4, 0x46A), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7717 {"zsubfdss", VX(4, 0x46B), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7718 {"zvaddsubfwss", VX(4, 0x46C), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7719 {"zvsubfaddwss", VX(4, 0x46D), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7720 {"zvaddwss", VX(4, 0x46E), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
7721 {"zvsubfwss", VX(4, 0x46F), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7722 {"zaddwgsf", VX(4, 0x470), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7723 {"zsubfwgsf", VX(4, 0x471), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7724 {"zadddus", VX(4, 0x472), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7725 {"zsubfdus", VX(4, 0x473), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7726 {"zvaddwus", VX(4, 0x476), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7727 {"zvsubfwus", VX(4, 0x477), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7728 {"zvunpkhgwsf", VX_LSP(4, 0x478), VX_LSP_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
}},
7729 {"zvunpkhsf", VX_LSP(4, 0xC78), VX_LSP_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
}},
7730 {"zvunpkhui", VX_LSP(4, 0x1478), VX_LSP_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
}},
7731 {"zvunpkhsi", VX_LSP(4, 0x1C78), VX_LSP_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
}},
7732 {"zunpkwgsf", VX_LSP(4, 0x2478), VX_LSP_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
}},
7733 {"zvdotphgwasmf", VX(4, 0x488), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
7734 {"zvdotphgwasmfr", VX(4, 0x489), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
7735 {"zvdotphgwasmfaa", VX(4, 0x48A), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
7736 {"zvdotphgwasmfraa", VX(4, 0x48B), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
7737 {"zvdotphgwasmfan", VX(4, 0x48C), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
7738 {"zvdotphgwasmfran", VX(4, 0x48D), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
7739 {"zvmhulgwsmf", VX(4, 0x490), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7740 {"zvmhulgwsmfr", VX(4, 0x491), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7741 {"zvmhulgwsmfaa", VX(4, 0x492), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7742 {"zvmhulgwsmfraa", VX(4, 0x493), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7743 {"zvmhulgwsmfan", VX(4, 0x494), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7744 {"zvmhulgwsmfran", VX(4, 0x495), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7745 {"zvmhulgwsmfanp", VX(4, 0x496), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7746 {"zvmhulgwsmfranp", VX(4, 0x497), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7747 {"zmhegwsmf", VX(4, 0x498), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
7748 {"zmhegwsmfr", VX(4, 0x499), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
7749 {"zmhegwsmfaa", VX(4, 0x49A), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
7750 {"zmhegwsmfraa", VX(4, 0x49B), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
7751 {"zmhegwsmfan", VX(4, 0x49C), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
7752 {"zmhegwsmfran", VX(4, 0x49D), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
7753 {"zvdotphxgwasmf", VX(4, 0x4A8), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
7754 {"zvdotphxgwasmfr", VX(4, 0x4A9), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
7755 {"zvdotphxgwasmfaa", VX(4, 0x4AA), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
7756 {"zvdotphxgwasmfraa", VX(4, 0x4AB), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
7757 {"zvdotphxgwasmfan", VX(4, 0x4AC), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
7758 {"zvdotphxgwasmfran", VX(4, 0x4AD), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
7759 {"zvmhllgwsmf", VX(4, 0x4B0), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7760 {"zvmhllgwsmfr", VX(4, 0x4B1), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7761 {"zvmhllgwsmfaa", VX(4, 0x4B2), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7762 {"zvmhllgwsmfraa", VX(4, 0x4B3), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7763 {"zvmhllgwsmfan", VX(4, 0x4B4), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7764 {"zvmhllgwsmfran", VX(4, 0x4B5), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7765 {"zvmhllgwsmfanp", VX(4, 0x4B6), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7766 {"zvmhllgwsmfranp", VX(4, 0x4B7), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7767 {"zmheogwsmf", VX(4, 0x4B8), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
7768 {"zmheogwsmfr", VX(4, 0x4B9), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
7769 {"zmheogwsmfaa", VX(4, 0x4BA), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
7770 {"zmheogwsmfraa", VX(4, 0x4BB), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
7771 {"zmheogwsmfan", VX(4, 0x4BC), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
7772 {"zmheogwsmfran", VX(4, 0x4BD), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
7773 {"zvdotphgwssmf", VX(4, 0x4C8), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
7774 {"zvdotphgwssmfr", VX(4, 0x4C9), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
7775 {"zvdotphgwssmfaa", VX(4, 0x4CA), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
7776 {"zvdotphgwssmfraa", VX(4, 0x4CB), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
7777 {"zvdotphgwssmfan", VX(4, 0x4CC), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
7778 {"zvdotphgwssmfran", VX(4, 0x4CD), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
7779 {"zvmhuugwsmf", VX(4, 0x4D0), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7780 {"zvmhuugwsmfr", VX(4, 0x4D1), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7781 {"zvmhuugwsmfaa", VX(4, 0x4D2), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7782 {"zvmhuugwsmfraa", VX(4, 0x4D3), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7783 {"zvmhuugwsmfan", VX(4, 0x4D4), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7784 {"zvmhuugwsmfran", VX(4, 0x4D5), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7785 {"zvmhuugwsmfanp", VX(4, 0x4D6), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7786 {"zvmhuugwsmfranp", VX(4, 0x4D7), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7787 {"zmhogwsmf", VX(4, 0x4D8), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
7788 {"zmhogwsmfr", VX(4, 0x4D9), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
7789 {"zmhogwsmfaa", VX(4, 0x4DA), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
7790 {"zmhogwsmfraa", VX(4, 0x4DB), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
7791 {"zmhogwsmfan", VX(4, 0x4DC), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
7792 {"zmhogwsmfran", VX(4, 0x4DD), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
7793 {"zvmhxlgwsmf", VX(4, 0x4F0), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7794 {"zvmhxlgwsmfr", VX(4, 0x4F1), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7795 {"zvmhxlgwsmfaa", VX(4, 0x4F2), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7796 {"zvmhxlgwsmfraa", VX(4, 0x4F3), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7797 {"zvmhxlgwsmfan", VX(4, 0x4F4), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7798 {"zvmhxlgwsmfran", VX(4, 0x4F5), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7799 {"zvmhxlgwsmfanp", VX(4, 0x4F6), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7800 {"zvmhxlgwsmfranp", VX(4, 0x4F7), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7801 {"zmhegui", VX(4, 0x500), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7802 {"zvdotphgaui", VX(4, 0x501), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7803 {"zmheguiaa", VX(4, 0x502), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7804 {"zvdotphgauiaa", VX(4, 0x503), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7805 {"zmheguian", VX(4, 0x504), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7806 {"zvdotphgauian", VX(4, 0x505), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7807 {"zmhegsi", VX(4, 0x508), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7808 {"zvdotphgasi", VX(4, 0x509), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7809 {"zmhegsiaa", VX(4, 0x50A), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7810 {"zvdotphgasiaa", VX(4, 0x50B), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7811 {"zmhegsian", VX(4, 0x50C), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7812 {"zvdotphgasian", VX(4, 0x50D), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7813 {"zmhegsui", VX(4, 0x510), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7814 {"zvdotphgasui", VX(4, 0x511), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7815 {"zmhegsuiaa", VX(4, 0x512), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7816 {"zvdotphgasuiaa", VX(4, 0x513), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7817 {"zmhegsuian", VX(4, 0x514), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7818 {"zvdotphgasuian", VX(4, 0x515), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7819 {"zmhegsmf", VX(4, 0x518), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7820 {"zvdotphgasmf", VX(4, 0x519), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7821 {"zmhegsmfaa", VX(4, 0x51A), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7822 {"zvdotphgasmfaa", VX(4, 0x51B), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7823 {"zmhegsmfan", VX(4, 0x51C), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7824 {"zvdotphgasmfan", VX(4, 0x51D), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7825 {"zmheogui", VX(4, 0x520), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7826 {"zvdotphxgaui", VX(4, 0x521), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7827 {"zmheoguiaa", VX(4, 0x522), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7828 {"zvdotphxgauiaa", VX(4, 0x523), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7829 {"zmheoguian", VX(4, 0x524), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7830 {"zvdotphxgauian", VX(4, 0x525), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7831 {"zmheogsi", VX(4, 0x528), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7832 {"zvdotphxgasi", VX(4, 0x529), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7833 {"zmheogsiaa", VX(4, 0x52A), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7834 {"zvdotphxgasiaa", VX(4, 0x52B), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7835 {"zmheogsian", VX(4, 0x52C), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7836 {"zvdotphxgasian", VX(4, 0x52D), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7837 {"zmheogsui", VX(4, 0x530), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7838 {"zvdotphxgasui", VX(4, 0x531), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7839 {"zmheogsuiaa", VX(4, 0x532), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7840 {"zvdotphxgasuiaa", VX(4, 0x533), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7841 {"zmheogsuian", VX(4, 0x534), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7842 {"zvdotphxgasuian", VX(4, 0x535), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7843 {"zmheogsmf", VX(4, 0x538), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7844 {"zvdotphxgasmf", VX(4, 0x539), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7845 {"zmheogsmfaa", VX(4, 0x53A), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7846 {"zvdotphxgasmfaa", VX(4, 0x53B), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7847 {"zmheogsmfan", VX(4, 0x53C), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7848 {"zvdotphxgasmfan", VX(4, 0x53D), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7849 {"zmhogui", VX(4, 0x540), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7850 {"zvdotphgsui", VX(4, 0x541), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7851 {"zmhoguiaa", VX(4, 0x542), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7852 {"zvdotphgsuiaa", VX(4, 0x543), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7853 {"zmhoguian", VX(4, 0x544), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7854 {"zvdotphgsuian", VX(4, 0x545), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7855 {"zmhogsi", VX(4, 0x548), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7856 {"zvdotphgssi", VX(4, 0x549), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7857 {"zmhogsiaa", VX(4, 0x54A), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7858 {"zvdotphgssiaa", VX(4, 0x54B), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7859 {"zmhogsian", VX(4, 0x54C), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7860 {"zvdotphgssian", VX(4, 0x54D), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7861 {"zmhogsui", VX(4, 0x550), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7862 {"zvdotphgssui", VX(4, 0x551), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7863 {"zmhogsuiaa", VX(4, 0x552), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7864 {"zvdotphgssuiaa", VX(4, 0x553), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7865 {"zmhogsuian", VX(4, 0x554), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7866 {"zvdotphgssuian", VX(4, 0x555), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7867 {"zmhogsmf", VX(4, 0x558), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7868 {"zvdotphgssmf", VX(4, 0x559), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7869 {"zmhogsmfaa", VX(4, 0x55A), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7870 {"zvdotphgssmfaa", VX(4, 0x55B), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7871 {"zmhogsmfan", VX(4, 0x55C), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7872 {"zvdotphgssmfan", VX(4, 0x55D), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7873 {"zmwgui", VX(4, 0x560), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7874 {"zmwguiaa", VX(4, 0x562), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7875 {"zmwguiaas", VX(4, 0x563), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7876 {"zmwguian", VX(4, 0x564), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7877 {"zmwguians", VX(4, 0x565), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7878 {"zmwgsi", VX(4, 0x568), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7879 {"zmwgsiaa", VX(4, 0x56A), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7880 {"zmwgsiaas", VX(4, 0x56B), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7881 {"zmwgsian", VX(4, 0x56C), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7882 {"zmwgsians", VX(4, 0x56D), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7883 {"zmwgsui", VX(4, 0x570), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7884 {"zmwgsuiaa", VX(4, 0x572), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7885 {"zmwgsuiaas", VX(4, 0x573), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7886 {"zmwgsuian", VX(4, 0x574), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7887 {"zmwgsuians", VX(4, 0x575), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7888 {"zmwgsmf", VX(4, 0x578), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7889 {"zmwgsmfr", VX(4, 0x579), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7890 {"zmwgsmfaa", VX(4, 0x57A), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7891 {"zmwgsmfraa", VX(4, 0x57B), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7892 {"zmwgsmfan", VX(4, 0x57C), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7893 {"zmwgsmfran", VX(4, 0x57D), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7894 {"zvmhului", VX(4, 0x580), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7895 {"zvmhuluiaa", VX(4, 0x582), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7896 {"zvmhuluiaas", VX(4, 0x583), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7897 {"zvmhuluian", VX(4, 0x584), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7898 {"zvmhuluians", VX(4, 0x585), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7899 {"zvmhuluianp", VX(4, 0x586), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7900 {"zvmhuluianps", VX(4, 0x587), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7901 {"zvmhulsi", VX(4, 0x588), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7902 {"zvmhulsiaa", VX(4, 0x58A), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7903 {"zvmhulsiaas", VX(4, 0x58B), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7904 {"zvmhulsian", VX(4, 0x58C), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7905 {"zvmhulsians", VX(4, 0x58D), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7906 {"zvmhulsianp", VX(4, 0x58E), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7907 {"zvmhulsianps", VX(4, 0x58F), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7908 {"zvmhulsui", VX(4, 0x590), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7909 {"zvmhulsuiaa", VX(4, 0x592), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7910 {"zvmhulsuiaas", VX(4, 0x593), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7911 {"zvmhulsuian", VX(4, 0x594), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7912 {"zvmhulsuians", VX(4, 0x595), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7913 {"zvmhulsuianp", VX(4, 0x596), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7914 {"zvmhulsuianps", VX(4, 0x597), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7915 {"zvmhulsf", VX(4, 0x598), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7916 {"zvmhulsfr", VX(4, 0x599), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7917 {"zvmhulsfaas", VX(4, 0x59A), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7918 {"zvmhulsfraas", VX(4, 0x59B), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7919 {"zvmhulsfans", VX(4, 0x59C), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7920 {"zvmhulsfrans", VX(4, 0x59D), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7921 {"zvmhulsfanps", VX(4, 0x59E), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7922 {"zvmhulsfranps", VX(4, 0x59F), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7923 {"zvmhllui", VX(4, 0x5A0), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7924 {"zvmhlluiaa", VX(4, 0x5A2), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7925 {"zvmhlluiaas", VX(4, 0x5A3), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7926 {"zvmhlluian", VX(4, 0x5A4), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7927 {"zvmhlluians", VX(4, 0x5A5), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7928 {"zvmhlluianp", VX(4, 0x5A6), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7929 {"zvmhlluianps", VX(4, 0x5A7), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7930 {"zvmhllsi", VX(4, 0x5A8), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7931 {"zvmhllsiaa", VX(4, 0x5AA), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7932 {"zvmhllsiaas", VX(4, 0x5AB), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7933 {"zvmhllsian", VX(4, 0x5AC), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7934 {"zvmhllsians", VX(4, 0x5AD), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7935 {"zvmhllsianp", VX(4, 0x5AE), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7936 {"zvmhllsianps", VX(4, 0x5AF), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7937 {"zvmhllsui", VX(4, 0x5B0), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7938 {"zvmhllsuiaa", VX(4, 0x5B2), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7939 {"zvmhllsuiaas", VX(4, 0x5B3), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7940 {"zvmhllsuian", VX(4, 0x5B4), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7941 {"zvmhllsuians", VX(4, 0x5B5), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7942 {"zvmhllsuianp", VX(4, 0x5B6), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7943 {"zvmhllsuianps", VX(4, 0x5B7), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7944 {"zvmhllsf", VX(4, 0x5B8), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7945 {"zvmhllsfr", VX(4, 0x5B9), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7946 {"zvmhllsfaas", VX(4, 0x5BA), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7947 {"zvmhllsfraas", VX(4, 0x5BB), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7948 {"zvmhllsfans", VX(4, 0x5BC), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7949 {"zvmhllsfrans", VX(4, 0x5BD), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7950 {"zvmhllsfanps", VX(4, 0x5BE), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7951 {"zvmhllsfranps", VX(4, 0x5BF), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7952 {"zvmhuuui", VX(4, 0x5C0), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7953 {"zvmhuuuiaa", VX(4, 0x5C2), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7954 {"zvmhuuuiaas", VX(4, 0x5C3), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7955 {"zvmhuuuian", VX(4, 0x5C4), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7956 {"zvmhuuuians", VX(4, 0x5C5), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7957 {"zvmhuuuianp", VX(4, 0x5C6), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7958 {"zvmhuuuianps", VX(4, 0x5C7), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7959 {"zvmhuusi", VX(4, 0x5C8), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7960 {"zvmhuusiaa", VX(4, 0x5CA), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7961 {"zvmhuusiaas", VX(4, 0x5CB), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7962 {"zvmhuusian", VX(4, 0x5CC), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7963 {"zvmhuusians", VX(4, 0x5CD), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7964 {"zvmhuusianp", VX(4, 0x5CE), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7965 {"zvmhuusianps", VX(4, 0x5CF), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7966 {"zvmhuusui", VX(4, 0x5D0), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7967 {"zvmhuusuiaa", VX(4, 0x5D2), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7968 {"zvmhuusuiaas", VX(4, 0x5D3), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7969 {"zvmhuusuian", VX(4, 0x5D4), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7970 {"zvmhuusuians", VX(4, 0x5D5), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7971 {"zvmhuusuianp", VX(4, 0x5D6), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7972 {"zvmhuusuianps", VX(4, 0x5D7), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7973 {"zvmhuusf", VX(4, 0x5D8), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7974 {"zvmhuusfr", VX(4, 0x5D9), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7975 {"zvmhuusfaas", VX(4, 0x5DA), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7976 {"zvmhuusfraas", VX(4, 0x5DB), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7977 {"zvmhuusfans", VX(4, 0x5DC), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7978 {"zvmhuusfrans", VX(4, 0x5DD), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7979 {"zvmhuusfanps", VX(4, 0x5DE), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7980 {"zvmhuusfranps", VX(4, 0x5DF), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7981 {"zvmhxlui", VX(4, 0x5E0), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7982 {"zvmhxluiaa", VX(4, 0x5E2), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7983 {"zvmhxluiaas", VX(4, 0x5E3), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7984 {"zvmhxluian", VX(4, 0x5E4), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7985 {"zvmhxluians", VX(4, 0x5E5), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7986 {"zvmhxluianp", VX(4, 0x5E6), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7987 {"zvmhxluianps", VX(4, 0x5E7), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7988 {"zvmhxlsi", VX(4, 0x5E8), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7989 {"zvmhxlsiaa", VX(4, 0x5EA), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7990 {"zvmhxlsiaas", VX(4, 0x5EB), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7991 {"zvmhxlsian", VX(4, 0x5EC), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7992 {"zvmhxlsians", VX(4, 0x5ED), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7993 {"zvmhxlsianp", VX(4, 0x5EE), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7994 {"zvmhxlsianps", VX(4, 0x5EF), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7995 {"zvmhxlsui", VX(4, 0x5F0), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7996 {"zvmhxlsuiaa", VX(4, 0x5F2), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7997 {"zvmhxlsuiaas", VX(4, 0x5F3), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7998 {"zvmhxlsuian", VX(4, 0x5F4), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7999 {"zvmhxlsuians", VX(4, 0x5F5), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
8000 {"zvmhxlsuianp", VX(4, 0x5F6), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
8001 {"zvmhxlsuianps", VX(4, 0x5F7), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
8002 {"zvmhxlsf", VX(4, 0x5F8), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
8003 {"zvmhxlsfr", VX(4, 0x5F9), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
8004 {"zvmhxlsfaas", VX(4, 0x5FA), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
8005 {"zvmhxlsfraas", VX(4, 0x5FB), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
8006 {"zvmhxlsfans", VX(4, 0x5FC), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
8007 {"zvmhxlsfrans", VX(4, 0x5FD), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
8008 {"zvmhxlsfanps", VX(4, 0x5FE), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
8009 {"zvmhxlsfranps", VX(4, 0x5FF), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
8010 {"zmheui", VX(4, 0x600), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8011 {"zmheuiaa", VX(4, 0x602), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8012 {"zmheuiaas", VX(4, 0x603), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8013 {"zmheuian", VX(4, 0x604), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8014 {"zmheuians", VX(4, 0x605), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8015 {"zmhesi", VX(4, 0x608), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8016 {"zmhesiaa", VX(4, 0x60A), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8017 {"zmhesiaas", VX(4, 0x60B), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8018 {"zmhesian", VX(4, 0x60C), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8019 {"zmhesians", VX(4, 0x60D), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8020 {"zmhesui", VX(4, 0x610), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8021 {"zmhesuiaa", VX(4, 0x612), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8022 {"zmhesuiaas", VX(4, 0x613), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8023 {"zmhesuian", VX(4, 0x614), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8024 {"zmhesuians", VX(4, 0x615), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8025 {"zmhesf", VX(4, 0x618), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8026 {"zmhesfr", VX(4, 0x619), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8027 {"zmhesfaas", VX(4, 0x61A), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8028 {"zmhesfraas", VX(4, 0x61B), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8029 {"zmhesfans", VX(4, 0x61C), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8030 {"zmhesfrans", VX(4, 0x61D), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8031 {"zmheoui", VX(4, 0x620), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8032 {"zmheouiaa", VX(4, 0x622), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8033 {"zmheouiaas", VX(4, 0x623), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8034 {"zmheouian", VX(4, 0x624), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8035 {"zmheouians", VX(4, 0x625), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8036 {"zmheosi", VX(4, 0x628), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8037 {"zmheosiaa", VX(4, 0x62A), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8038 {"zmheosiaas", VX(4, 0x62B), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8039 {"zmheosian", VX(4, 0x62C), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8040 {"zmheosians", VX(4, 0x62D), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8041 {"zmheosui", VX(4, 0x630), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8042 {"zmheosuiaa", VX(4, 0x632), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8043 {"zmheosuiaas", VX(4, 0x633), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8044 {"zmheosuian", VX(4, 0x634), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8045 {"zmheosuians", VX(4, 0x635), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8046 {"zmheosf", VX(4, 0x638), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8047 {"zmheosfr", VX(4, 0x639), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8048 {"zmheosfaas", VX(4, 0x63A), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8049 {"zmheosfraas", VX(4, 0x63B), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8050 {"zmheosfans", VX(4, 0x63C), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8051 {"zmheosfrans", VX(4, 0x63D), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8052 {"zmhoui", VX(4, 0x640), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8053 {"zmhouiaa", VX(4, 0x642), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8054 {"zmhouiaas", VX(4, 0x643), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8055 {"zmhouian", VX(4, 0x644), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8056 {"zmhouians", VX(4, 0x645), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8057 {"zmhosi", VX(4, 0x648), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8058 {"zmhosiaa", VX(4, 0x64A), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8059 {"zmhosiaas", VX(4, 0x64B), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8060 {"zmhosian", VX(4, 0x64C), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8061 {"zmhosians", VX(4, 0x64D), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8062 {"zmhosui", VX(4, 0x650), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8063 {"zmhosuiaa", VX(4, 0x652), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8064 {"zmhosuiaas", VX(4, 0x653), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8065 {"zmhosuian", VX(4, 0x654), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8066 {"zmhosuians", VX(4, 0x655), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8067 {"zmhosf", VX(4, 0x658), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8068 {"zmhosfr", VX(4, 0x659), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8069 {"zmhosfaas", VX(4, 0x65A), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8070 {"zmhosfraas", VX(4, 0x65B), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8071 {"zmhosfans", VX(4, 0x65C), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8072 {"zmhosfrans", VX(4, 0x65D), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8073 {"zvmhuih", VX(4, 0x660), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8074 {"zvmhuihs", VX(4, 0x661), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8075 {"zvmhuiaah", VX(4, 0x662), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8076 {"zvmhuiaahs", VX(4, 0x663), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8077 {"zvmhuianh", VX(4, 0x664), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8078 {"zvmhuianhs", VX(4, 0x665), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8079 {"zvmhsihs", VX(4, 0x669), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8080 {"zvmhsiaahs", VX(4, 0x66B), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8081 {"zvmhsianhs", VX(4, 0x66D), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8082 {"zvmhsuihs", VX(4, 0x671), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8083 {"zvmhsuiaahs", VX(4, 0x673), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8084 {"zvmhsuianhs", VX(4, 0x675), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8085 {"zvmhsfh", VX(4, 0x678), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8086 {"zvmhsfrh", VX(4, 0x679), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8087 {"zvmhsfaahs", VX(4, 0x67A), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8088 {"zvmhsfraahs", VX(4, 0x67B), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8089 {"zvmhsfanhs", VX(4, 0x67C), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8090 {"zvmhsfranhs", VX(4, 0x67D), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8091 {"zvdotphaui", VX(4, 0x680), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8092 {"zvdotphauis", VX(4, 0x681), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8093 {"zvdotphauiaa", VX(4, 0x682), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8094 {"zvdotphauiaas", VX(4, 0x683), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8095 {"zvdotphauian", VX(4, 0x684), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8096 {"zvdotphauians", VX(4, 0x685), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8097 {"zvdotphasi", VX(4, 0x688), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8098 {"zvdotphasis", VX(4, 0x689), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8099 {"zvdotphasiaa", VX(4, 0x68A), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8100 {"zvdotphasiaas", VX(4, 0x68B), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8101 {"zvdotphasian", VX(4, 0x68C), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8102 {"zvdotphasians", VX(4, 0x68D), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8103 {"zvdotphasui", VX(4, 0x690), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8104 {"zvdotphasuis", VX(4, 0x691), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8105 {"zvdotphasuiaa", VX(4, 0x692), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8106 {"zvdotphasuiaas", VX(4, 0x693), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8107 {"zvdotphasuian", VX(4, 0x694), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8108 {"zvdotphasuians", VX(4, 0x695), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8109 {"zvdotphasfs", VX(4, 0x698), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8110 {"zvdotphasfrs", VX(4, 0x699), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8111 {"zvdotphasfaas", VX(4, 0x69A), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8112 {"zvdotphasfraas", VX(4, 0x69B), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8113 {"zvdotphasfans", VX(4, 0x69C), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8114 {"zvdotphasfrans", VX(4, 0x69D), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8115 {"zvdotphxaui", VX(4, 0x6A0), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8116 {"zvdotphxauis", VX(4, 0x6A1), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8117 {"zvdotphxauiaa", VX(4, 0x6A2), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8118 {"zvdotphxauiaas", VX(4, 0x6A3), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8119 {"zvdotphxauian", VX(4, 0x6A4), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8120 {"zvdotphxauians", VX(4, 0x6A5), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8121 {"zvdotphxasi", VX(4, 0x6A8), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8122 {"zvdotphxasis", VX(4, 0x6A9), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8123 {"zvdotphxasiaa", VX(4, 0x6AA), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8124 {"zvdotphxasiaas", VX(4, 0x6AB), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8125 {"zvdotphxasian", VX(4, 0x6AC), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8126 {"zvdotphxasians", VX(4, 0x6AD), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8127 {"zvdotphxasui", VX(4, 0x6B0), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8128 {"zvdotphxasuis", VX(4, 0x6B1), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8129 {"zvdotphxasuiaa", VX(4, 0x6B2), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8130 {"zvdotphxasuiaas", VX(4, 0x6B3), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8131 {"zvdotphxasuian", VX(4, 0x6B4), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8132 {"zvdotphxasuians", VX(4, 0x6B5), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8133 {"zvdotphxasfs", VX(4, 0x6B8), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8134 {"zvdotphxasfrs", VX(4, 0x6B9), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8135 {"zvdotphxasfaas", VX(4, 0x6BA), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8136 {"zvdotphxasfraas", VX(4, 0x6BB), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8137 {"zvdotphxasfans", VX(4, 0x6BC), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8138 {"zvdotphxasfrans", VX(4, 0x6BD), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8139 {"zvdotphsui", VX(4, 0x6C0), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8140 {"zvdotphsuis", VX(4, 0x6C1), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8141 {"zvdotphsuiaa", VX(4, 0x6C2), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8142 {"zvdotphsuiaas", VX(4, 0x6C3), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8143 {"zvdotphsuian", VX(4, 0x6C4), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8144 {"zvdotphsuians", VX(4, 0x6C5), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8145 {"zvdotphssi", VX(4, 0x6C8), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8146 {"zvdotphssis", VX(4, 0x6C9), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8147 {"zvdotphssiaa", VX(4, 0x6CA), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8148 {"zvdotphssiaas", VX(4, 0x6CB), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8149 {"zvdotphssian", VX(4, 0x6CC), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8150 {"zvdotphssians", VX(4, 0x6CD), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8151 {"zvdotphssui", VX(4, 0x6D0), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8152 {"zvdotphssuis", VX(4, 0x6D1), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8153 {"zvdotphssuiaa", VX(4, 0x6D2), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8154 {"zvdotphssuiaas", VX(4, 0x6D3), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8155 {"zvdotphssuian", VX(4, 0x6D4), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8156 {"zvdotphssuians", VX(4, 0x6D5), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8157 {"zvdotphssfs", VX(4, 0x6D8), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8158 {"zvdotphssfrs", VX(4, 0x6D9), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8159 {"zvdotphssfaas", VX(4, 0x6DA), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8160 {"zvdotphssfraas", VX(4, 0x6DB), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8161 {"zvdotphssfans", VX(4, 0x6DC), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8162 {"zvdotphssfrans", VX(4, 0x6DD), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8163 {"zmwluis", VX(4, 0x6E1), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8164 {"zmwluiaa", VX(4, 0x6E2), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8165 {"zmwluiaas", VX(4, 0x6E3), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8166 {"zmwluian", VX(4, 0x6E4), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8167 {"zmwluians", VX(4, 0x6E5), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8168 {"zmwlsis", VX(4, 0x6E9), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8169 {"zmwlsiaas", VX(4, 0x6EB), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8170 {"zmwlsians", VX(4, 0x6ED), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8171 {"zmwlsuis", VX(4, 0x6F1), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8172 {"zmwlsuiaas", VX(4, 0x6F3), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8173 {"zmwlsuians", VX(4, 0x6F5), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8174 {"zmwsf", VX(4, 0x6F8), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8175 {"zmwsfr", VX(4, 0x6F9), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8176 {"zmwsfaas", VX(4, 0x6FA), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8177 {"zmwsfraas", VX(4, 0x6FB), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8178 {"zmwsfans", VX(4, 0x6FC), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8179 {"zmwsfrans", VX(4, 0x6FD), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8180 {"zlddx", VX(4, 0x300), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
8181 {"zldd", VX(4, 0x301), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, EVUIMM_8
, RA
}},
8182 {"zldwx", VX(4, 0x302), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
8183 {"zldw", VX(4, 0x303), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, EVUIMM_8
, RA
}},
8184 {"zldhx", VX(4, 0x304), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
8185 {"zldh", VX(4, 0x305), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, EVUIMM_8
, RA
}},
8186 {"zlwgsfdx", VX(4, 0x308), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
8187 {"zlwgsfd", VX(4, 0x309), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, EVUIMM_4
, RA
}},
8188 {"zlwwosdx", VX(4, 0x30A), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
8189 {"zlwwosd", VX(4, 0x30B), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, EVUIMM_4
, RA
}},
8190 {"zlwhsplatwdx", VX(4, 0x30C), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
8191 {"zlwhsplatwd", VX(4, 0x30D), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, EVUIMM_4
, RA
}},
8192 {"zlwhsplatdx", VX(4, 0x30E), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
8193 {"zlwhsplatd", VX(4, 0x30F), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, EVUIMM_4
, RA
}},
8194 {"zlwhgwsfdx", VX(4, 0x310), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
8195 {"zlwhgwsfd", VX(4, 0x311), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, EVUIMM_4
, RA
}},
8196 {"zlwhedx", VX(4, 0x312), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
8197 {"zlwhed", VX(4, 0x313), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, EVUIMM_4
, RA
}},
8198 {"zlwhosdx", VX(4, 0x314), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
8199 {"zlwhosd", VX(4, 0x315), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, EVUIMM_4
, RA
}},
8200 {"zlwhoudx", VX(4, 0x316), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
8201 {"zlwhoud", VX(4, 0x317), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, EVUIMM_4
, RA
}},
8202 {"zlwhx", VX(4, 0x318), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8203 {"zlwh", VX(4, 0x319), VX_MASK
, PPCLSP
, 0, {RD
, EVUIMM_4
, RA
}},
8204 {"zlwwx", VX(4, 0x31A), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8205 {"zlww", VX(4, 0x31B), VX_MASK
, PPCLSP
, 0, {RD
, EVUIMM_4
, RA
}},
8206 {"zlhgwsfx", VX(4, 0x31C), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8207 {"zlhgwsf", VX(4, 0x31D), VX_MASK
, PPCLSP
, 0, {RD
, EVUIMM_2
, RA
}},
8208 {"zlhhsplatx", VX(4, 0x31E), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8209 {"zlhhsplat", VX(4, 0x31F), VX_MASK
, PPCLSP
, 0, {RD
, EVUIMM_2
, RA
}},
8210 {"zstddx", VX(4, 0x320), VX_MASK
, PPCLSP
, 0, {RS_EVEN
, RA
, RB
}},
8211 {"zstdd", VX(4, 0x321), VX_MASK
, PPCLSP
, 0, {RS_EVEN
, EVUIMM_8
, RA
}},
8212 {"zstdwx", VX(4, 0x322), VX_MASK
, PPCLSP
, 0, {RS_EVEN
, RA
, RB
}},
8213 {"zstdw", VX(4, 0x323), VX_MASK
, PPCLSP
, 0, {RS_EVEN
, EVUIMM_8
, RA
}},
8214 {"zstdhx", VX(4, 0x324), VX_MASK
, PPCLSP
, 0, {RS_EVEN
, RA
, RB
}},
8215 {"zstdh", VX(4, 0x325), VX_MASK
, PPCLSP
, 0, {RS_EVEN
, EVUIMM_8
, RA
}},
8216 {"zstwhedx", VX(4, 0x328), VX_MASK
, PPCLSP
, 0, {RS_EVEN
, RA
, RB
}},
8217 {"zstwhed", VX(4, 0x329), VX_MASK
, PPCLSP
, 0, {RS_EVEN
, EVUIMM_4
, RA
}},
8218 {"zstwhodx", VX(4, 0x32A), VX_MASK
, PPCLSP
, 0, {RS_EVEN
, RA
, RB
}},
8219 {"zstwhod", VX(4, 0x32B), VX_MASK
, PPCLSP
, 0, {RS_EVEN
, EVUIMM_4
, RA
}},
8220 {"zlhhex", VX(4, 0x330), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8221 {"zlhhe", VX(4, 0x331), VX_MASK
, PPCLSP
, 0, {RD
, EVUIMM_2
, RA
}},
8222 {"zlhhosx", VX(4, 0x332), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8223 {"zlhhos", VX(4, 0x333), VX_MASK
, PPCLSP
, 0, {RD
, EVUIMM_2
, RA
}},
8224 {"zlhhoux", VX(4, 0x334), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8225 {"zlhhou", VX(4, 0x335), VX_MASK
, PPCLSP
, 0, {RD
, EVUIMM_2
, RA
}},
8226 {"zsthex", VX(4, 0x338), VX_MASK
, PPCLSP
, 0, {RS
, RA
, RB
}},
8227 {"zsthe", VX(4, 0x339), VX_MASK
, PPCLSP
, 0, {RS
, EVUIMM_2
, RA
}},
8228 {"zsthox", VX(4, 0x33A), VX_MASK
, PPCLSP
, 0, {RS
, RA
, RB
}},
8229 {"zstho", VX(4, 0x33B), VX_MASK
, PPCLSP
, 0, {RS
, EVUIMM_2
, RA
}},
8230 {"zstwhx", VX(4, 0x33C), VX_MASK
, PPCLSP
, 0, {RS
, RA
, RB
}},
8231 {"zstwh", VX(4, 0x33D), VX_MASK
, PPCLSP
, 0, {RS
, EVUIMM_4
, RA
}},
8232 {"zstwwx", VX(4, 0x33E), VX_MASK
, PPCLSP
, 0, {RS
, RA
, RB
}},
8233 {"zstww", VX(4, 0x33F), VX_MASK
, PPCLSP
, 0, {RS
, EVUIMM_4
, RA
}},
8234 {"zlddmx", VX(4, 0x340), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
8235 {"zlddu", VX(4, 0x341), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, EVUIMM_8_EX0
, RA
}},
8236 {"zldwmx", VX(4, 0x342), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
8237 {"zldwu", VX(4, 0x343), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, EVUIMM_8_EX0
, RA
}},
8238 {"zldhmx", VX(4, 0x344), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
8239 {"zldhu", VX(4, 0x345), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, EVUIMM_8_EX0
, RA
}},
8240 {"zlwgsfdmx", VX(4, 0x348), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
8241 {"zlwgsfdu", VX(4, 0x349), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, EVUIMM_4_EX0
, RA
}},
8242 {"zlwwosdmx", VX(4, 0x34A), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
8243 {"zlwwosdu", VX(4, 0x34B), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, EVUIMM_4_EX0
, RA
}},
8244 {"zlwhsplatwdmx", VX(4, 0x34C), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
8245 {"zlwhsplatwdu", VX(4, 0x34D), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, EVUIMM_4_EX0
, RA
}},
8246 {"zlwhsplatdmx", VX(4, 0x34E), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
8247 {"zlwhsplatdu", VX(4, 0x34F), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, EVUIMM_4_EX0
, RA
}},
8248 {"zlwhgwsfdmx", VX(4, 0x350), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
8249 {"zlwhgwsfdu", VX(4, 0x351), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, EVUIMM_4_EX0
, RA
}},
8250 {"zlwhedmx", VX(4, 0x352), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
8251 {"zlwhedu", VX(4, 0x353), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, EVUIMM_4_EX0
, RA
}},
8252 {"zlwhosdmx", VX(4, 0x354), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
8253 {"zlwhosdu", VX(4, 0x355), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, EVUIMM_4_EX0
, RA
}},
8254 {"zlwhoudmx", VX(4, 0x356), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
8255 {"zlwhoudu", VX(4, 0x357), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, EVUIMM_4_EX0
, RA
}},
8256 {"zlwhmx", VX(4, 0x358), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8257 {"zlwhu", VX(4, 0x359), VX_MASK
, PPCLSP
, 0, {RD
, EVUIMM_4_EX0
, RA
}},
8258 {"zlwwmx", VX(4, 0x35A), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8259 {"zlwwu", VX(4, 0x35B), VX_MASK
, PPCLSP
, 0, {RD
, EVUIMM_4_EX0
, RA
}},
8260 {"zlhgwsfmx", VX(4, 0x35C), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8261 {"zlhgwsfu", VX(4, 0x35D), VX_MASK
, PPCLSP
, 0, {RD
, EVUIMM_2_EX0
, RA
}},
8262 {"zlhhsplatmx", VX(4, 0x35E), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8263 {"zlhhsplatu", VX(4, 0x35F), VX_MASK
, PPCLSP
, 0, {RD
, EVUIMM_2_EX0
, RA
}},
8264 {"zstddmx", VX(4, 0x360), VX_MASK
, PPCLSP
, 0, {RS_EVEN
, RA
, RB
}},
8265 {"zstddu", VX(4, 0x361), VX_MASK
, PPCLSP
, 0, {RS
, EVUIMM_8_EX0
, RA
}},
8266 {"zstdwmx", VX(4, 0x362), VX_MASK
, PPCLSP
, 0, {RS_EVEN
, RA
, RB
}},
8267 {"zstdwu", VX(4, 0x363), VX_MASK
, PPCLSP
, 0, {RS_EVEN
, EVUIMM_8_EX0
, RA
}},
8268 {"zstdhmx", VX(4, 0x364), VX_MASK
, PPCLSP
, 0, {RS_EVEN
, RA
, RB
}},
8269 {"zstdhu", VX(4, 0x365), VX_MASK
, PPCLSP
, 0, {RS_EVEN
, EVUIMM_8_EX0
, RA
}},
8270 {"zstwhedmx", VX(4, 0x368), VX_MASK
, PPCLSP
, 0, {RS_EVEN
, RA
, RB
}},
8271 {"zstwhedu", VX(4, 0x369), VX_MASK
, PPCLSP
, 0, {RS_EVEN
, EVUIMM_4_EX0
, RA
}},
8272 {"zstwhodmx", VX(4, 0x36A), VX_MASK
, PPCLSP
, 0, {RS_EVEN
, RA
, RB
}},
8273 {"zstwhodu", VX(4, 0x36B), VX_MASK
, PPCLSP
, 0, {RS_EVEN
, EVUIMM_4_EX0
, RA
}},
8274 {"zlhhemx", VX(4, 0x370), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8275 {"zlhheu", VX(4, 0x371), VX_MASK
, PPCLSP
, 0, {RD
, EVUIMM_2_EX0
, RA
}},
8276 {"zlhhosmx", VX(4, 0x372), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8277 {"zlhhosu", VX(4, 0x373), VX_MASK
, PPCLSP
, 0, {RD
, EVUIMM_2_EX0
, RA
}},
8278 {"zlhhoumx", VX(4, 0x374), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8279 {"zlhhouu", VX(4, 0x375), VX_MASK
, PPCLSP
, 0, {RD
, EVUIMM_2_EX0
, RA
}},
8280 {"zsthemx", VX(4, 0x378), VX_MASK
, PPCLSP
, 0, {RS
, RA
, RB
}},
8281 {"zstheu", VX(4, 0x379), VX_MASK
, PPCLSP
, 0, {RS
, EVUIMM_2_EX0
, RA
}},
8282 {"zsthomx", VX(4, 0x37A), VX_MASK
, PPCLSP
, 0, {RS
, RA
, RB
}},
8283 {"zsthou", VX(4, 0x37B), VX_MASK
, PPCLSP
, 0, {RS
, EVUIMM_2_EX0
, RA
}},
8284 {"zstwhmx", VX(4, 0x37C), VX_MASK
, PPCLSP
, 0, {RS
, RA
, RB
}},
8285 {"zstwhu", VX(4, 0x37D), VX_MASK
, PPCLSP
, 0, {RS
, EVUIMM_4_EX0
, RA
}},
8286 {"zstwwmx", VX(4, 0x37E), VX_MASK
, PPCLSP
, 0, {RS
, RA
, RB
}},
8287 {"zstwwu", VX(4, 0x37F), VX_MASK
, PPCLSP
, 0, {RS
, EVUIMM_4_EX0
, RA
}},
8289 {"e_cmpi", SCI8BF(6,0,21), SCI8BF_MASK
, PPCVLE
, 0, {CRD32
, RA
, SCLSCI8
}},
8290 {"e_cmpwi", SCI8BF(6,0,21), SCI8BF_MASK
, PPCVLE
, 0, {CRD32
, RA
, SCLSCI8
}},
8291 {"e_cmpli", SCI8BF(6,1,21), SCI8BF_MASK
, PPCVLE
, 0, {CRD32
, RA
, SCLSCI8
}},
8292 {"e_cmplwi", SCI8BF(6,1,21), SCI8BF_MASK
, PPCVLE
, 0, {CRD32
, RA
, SCLSCI8
}},
8293 {"e_addi", SCI8(6,16), SCI8_MASK
, PPCVLE
, 0, {RT
, RA
, SCLSCI8
}},
8294 {"e_subi", SCI8(6,16), SCI8_MASK
, PPCVLE
, 0, {RT
, RA
, SCLSCI8N
}},
8295 {"e_addi.", SCI8(6,17), SCI8_MASK
, PPCVLE
, 0, {RT
, RA
, SCLSCI8
}},
8296 {"e_addic", SCI8(6,18), SCI8_MASK
, PPCVLE
, 0, {RT
, RA
, SCLSCI8
}},
8297 {"e_subic", SCI8(6,18), SCI8_MASK
, PPCVLE
, 0, {RT
, RA
, SCLSCI8N
}},
8298 {"e_addic.", SCI8(6,19), SCI8_MASK
, PPCVLE
, 0, {RT
, RA
, SCLSCI8
}},
8299 {"e_subic.", SCI8(6,19), SCI8_MASK
, PPCVLE
, 0, {RT
, RA
, SCLSCI8N
}},
8300 {"e_mulli", SCI8(6,20), SCI8_MASK
, PPCVLE
, 0, {RT
, RA
, SCLSCI8
}},
8301 {"e_subfic", SCI8(6,22), SCI8_MASK
, PPCVLE
, 0, {RT
, RA
, SCLSCI8
}},
8302 {"e_subfic.", SCI8(6,23), SCI8_MASK
, PPCVLE
, 0, {RT
, RA
, SCLSCI8
}},
8303 {"e_andi", SCI8(6,24), SCI8_MASK
, PPCVLE
, 0, {RA
, RS
, SCLSCI8
}},
8304 {"e_andi.", SCI8(6,25), SCI8_MASK
, PPCVLE
, 0, {RA
, RS
, SCLSCI8
}},
8305 {"e_nop", SCI8(6,26), 0xffffffff, PPCVLE
, 0, {0}},
8306 {"e_ori", SCI8(6,26), SCI8_MASK
, PPCVLE
, 0, {RA
, RS
, SCLSCI8
}},
8307 {"e_ori.", SCI8(6,27), SCI8_MASK
, PPCVLE
, 0, {RA
, RS
, SCLSCI8
}},
8308 {"e_xori", SCI8(6,28), SCI8_MASK
, PPCVLE
, 0, {RA
, RS
, SCLSCI8
}},
8309 {"e_xori.", SCI8(6,29), SCI8_MASK
, PPCVLE
, 0, {RA
, RS
, SCLSCI8
}},
8310 {"e_lbzu", OPVUP(6,0), OPVUP_MASK
, PPCVLE
, 0, {RT
, D8
, RA0
}},
8311 {"e_lhau", OPVUP(6,3), OPVUP_MASK
, PPCVLE
, 0, {RT
, D8
, RA0
}},
8312 {"e_lhzu", OPVUP(6,1), OPVUP_MASK
, PPCVLE
, 0, {RT
, D8
, RA0
}},
8313 {"e_lmw", OPVUP(6,8), OPVUP_MASK
, PPCVLE
, 0, {RT
, D8
, RA0
}},
8314 {"e_lwzu", OPVUP(6,2), OPVUP_MASK
, PPCVLE
, 0, {RT
, D8
, RA0
}},
8315 {"e_stbu", OPVUP(6,4), OPVUP_MASK
, PPCVLE
, 0, {RT
, D8
, RA0
}},
8316 {"e_sthu", OPVUP(6,5), OPVUP_MASK
, PPCVLE
, 0, {RT
, D8
, RA0
}},
8317 {"e_stwu", OPVUP(6,6), OPVUP_MASK
, PPCVLE
, 0, {RT
, D8
, RA0
}},
8318 {"e_stmw", OPVUP(6,9), OPVUP_MASK
, PPCVLE
, 0, {RT
, D8
, RA0
}},
8319 {"e_lmvgprw", OPVUPRT(6,16,0),OPVUPRT_MASK
, PPCVLE
, 0, {D8
, RA0
}},
8320 {"e_ldmvgprw", OPVUPRT(6,16,0),OPVUPRT_MASK
, PPCVLE
, 0, {D8
, RA0
}},
8321 {"e_stmvgprw", OPVUPRT(6,17,0),OPVUPRT_MASK
, PPCVLE
, 0, {D8
, RA0
}},
8322 {"e_lmvsprw", OPVUPRT(6,16,1),OPVUPRT_MASK
, PPCVLE
, 0, {D8
, RA0
}},
8323 {"e_ldmvsprw", OPVUPRT(6,16,1),OPVUPRT_MASK
, PPCVLE
, 0, {D8
, RA0
}},
8324 {"e_stmvsprw", OPVUPRT(6,17,1),OPVUPRT_MASK
, PPCVLE
, 0, {D8
, RA0
}},
8325 {"e_lmvsrrw", OPVUPRT(6,16,4),OPVUPRT_MASK
, PPCVLE
, 0, {D8
, RA0
}},
8326 {"e_ldmvsrrw", OPVUPRT(6,16,4),OPVUPRT_MASK
, PPCVLE
, 0, {D8
, RA0
}},
8327 {"e_stmvsrrw", OPVUPRT(6,17,4),OPVUPRT_MASK
, PPCVLE
, 0, {D8
, RA0
}},
8328 {"e_lmvcsrrw", OPVUPRT(6,16,5),OPVUPRT_MASK
, PPCVLE
, 0, {D8
, RA0
}},
8329 {"e_ldmvcsrrw", OPVUPRT(6,16,5),OPVUPRT_MASK
, PPCVLE
, 0, {D8
, RA0
}},
8330 {"e_stmvcsrrw", OPVUPRT(6,17,5),OPVUPRT_MASK
, PPCVLE
, 0, {D8
, RA0
}},
8331 {"e_lmvdsrrw", OPVUPRT(6,16,6),OPVUPRT_MASK
, PPCVLE
, 0, {D8
, RA0
}},
8332 {"e_ldmvdsrrw", OPVUPRT(6,16,6),OPVUPRT_MASK
, PPCVLE
, 0, {D8
, RA0
}},
8333 {"e_stmvdsrrw", OPVUPRT(6,17,6),OPVUPRT_MASK
, PPCVLE
, 0, {D8
, RA0
}},
8334 {"e_lmvmcsrrw", OPVUPRT(6,16,7),OPVUPRT_MASK
, PPCVLE
, 0, {D8
, RA0
}},
8335 {"e_stmvmcsrrw", OPVUPRT(6,17,7),OPVUPRT_MASK
, PPCVLE
, 0, {D8
, RA0
}},
8336 {"e_add16i", OP(7), OP_MASK
, PPCVLE
, 0, {RT
, RA
, SI
}},
8337 {"e_la", OP(7), OP_MASK
, PPCVLE
, 0, {RT
, D
, RA0
}},
8338 {"e_sub16i", OP(7), OP_MASK
, PPCVLE
, 0, {RT
, RA
, NSI
}},
8340 {"se_addi", SE_IM5(8,0), SE_IM5_MASK
, PPCVLE
, 0, {RX
, OIMM5
}},
8341 {"se_cmpli", SE_IM5(8,1), SE_IM5_MASK
, PPCVLE
, 0, {RX
, OIMM5
}},
8342 {"se_subi", SE_IM5(9,0), SE_IM5_MASK
, PPCVLE
, 0, {RX
, OIMM5
}},
8343 {"se_subi.", SE_IM5(9,1), SE_IM5_MASK
, PPCVLE
, 0, {RX
, OIMM5
}},
8344 {"se_cmpi", SE_IM5(10,1), SE_IM5_MASK
, PPCVLE
, 0, {RX
, UI5
}},
8345 {"se_bmaski", SE_IM5(11,0), SE_IM5_MASK
, PPCVLE
, 0, {RX
, UI5
}},
8346 {"se_andi", SE_IM5(11,1), SE_IM5_MASK
, PPCVLE
, 0, {RX
, UI5
}},
8348 {"e_lbz", OP(12), OP_MASK
, PPCVLE
, 0, {RT
, D
, RA0
}},
8349 {"e_stb", OP(13), OP_MASK
, PPCVLE
, 0, {RT
, D
, RA0
}},
8350 {"e_lha", OP(14), OP_MASK
, PPCVLE
, 0, {RT
, D
, RA0
}},
8352 {"se_srw", SE_RR(16,0), SE_RR_MASK
, PPCVLE
, 0, {RX
, RY
}},
8353 {"se_sraw", SE_RR(16,1), SE_RR_MASK
, PPCVLE
, 0, {RX
, RY
}},
8354 {"se_slw", SE_RR(16,2), SE_RR_MASK
, PPCVLE
, 0, {RX
, RY
}},
8355 {"se_nop", SE_RR(17,0), 0xffff, PPCVLE
, 0, {0}},
8356 {"se_or", SE_RR(17,0), SE_RR_MASK
, PPCVLE
, 0, {RX
, RY
}},
8357 {"se_andc", SE_RR(17,1), SE_RR_MASK
, PPCVLE
, 0, {RX
, RY
}},
8358 {"se_and", SE_RR(17,2), SE_RR_MASK
, PPCVLE
, 0, {RX
, RY
}},
8359 {"se_and.", SE_RR(17,3), SE_RR_MASK
, PPCVLE
, 0, {RX
, RY
}},
8360 {"se_li", IM7(9), IM7_MASK
, PPCVLE
, 0, {RX
, UI7
}},
8362 {"e_lwz", OP(20), OP_MASK
, PPCVLE
, 0, {RT
, D
, RA0
}},
8363 {"e_stw", OP(21), OP_MASK
, PPCVLE
, 0, {RT
, D
, RA0
}},
8364 {"e_lhz", OP(22), OP_MASK
, PPCVLE
, 0, {RT
, D
, RA0
}},
8365 {"e_sth", OP(23), OP_MASK
, PPCVLE
, 0, {RT
, D
, RA0
}},
8367 {"se_bclri", SE_IM5(24,0), SE_IM5_MASK
, PPCVLE
, 0, {RX
, UI5
}},
8368 {"se_bgeni", SE_IM5(24,1), SE_IM5_MASK
, PPCVLE
, 0, {RX
, UI5
}},
8369 {"se_bseti", SE_IM5(25,0), SE_IM5_MASK
, PPCVLE
, 0, {RX
, UI5
}},
8370 {"se_btsti", SE_IM5(25,1), SE_IM5_MASK
, PPCVLE
, 0, {RX
, UI5
}},
8371 {"se_srwi", SE_IM5(26,0), SE_IM5_MASK
, PPCVLE
, 0, {RX
, UI5
}},
8372 {"se_srawi", SE_IM5(26,1), SE_IM5_MASK
, PPCVLE
, 0, {RX
, UI5
}},
8373 {"se_slwi", SE_IM5(27,0), SE_IM5_MASK
, PPCVLE
, 0, {RX
, UI5
}},
8375 {"e_lis", I16L(28,28), I16L_MASK
, PPCVLE
, 0, {RD
, VLEUIMML
}},
8376 {"e_and2is.", I16L(28,29), I16L_MASK
, PPCVLE
, 0, {RD
, VLEUIMML
}},
8377 {"e_or2is", I16L(28,26), I16L_MASK
, PPCVLE
, 0, {RD
, VLEUIMML
}},
8378 {"e_and2i.", I16L(28,25), I16L_MASK
, PPCVLE
, 0, {RD
, VLEUIMML
}},
8379 {"e_or2i", I16L(28,24), I16L_MASK
, PPCVLE
, 0, {RD
, VLEUIMML
}},
8380 {"e_cmphl16i", IA16(28,23), IA16_MASK
, PPCVLE
, 0, {RA
, VLEUIMM
}},
8381 {"e_cmph16i", IA16(28,22), IA16_MASK
, PPCVLE
, 0, {RA
, VLESIMM
}},
8382 {"e_cmpl16i", I16A(28,21), I16A_MASK
, PPCVLE
, 0, {RA
, VLEUIMM
}},
8383 {"e_mull2i", I16A(28,20), I16A_MASK
, PPCVLE
, 0, {RA
, VLESIMM
}},
8384 {"e_cmp16i", IA16(28,19), IA16_MASK
, PPCVLE
, 0, {RA
, VLESIMM
}},
8385 {"e_sub2is", I16A(28,18), I16A_MASK
, PPCVLE
, 0, {RA
, VLENSIMM
}},
8386 {"e_add2is", I16A(28,18), I16A_MASK
, PPCVLE
, 0, {RA
, VLESIMM
}},
8387 {"e_sub2i.", I16A(28,17), I16A_MASK
, PPCVLE
, 0, {RA
, VLENSIMM
}},
8388 {"e_add2i.", I16A(28,17), I16A_MASK
, PPCVLE
, 0, {RA
, VLESIMM
}},
8389 {"e_li", LI20(28,0), LI20_MASK
, PPCVLE
, 0, {RT
, IMM20
}},
8390 {"e_rlwimi", M(29,0), M_MASK
, PPCVLE
, 0, {RA
, RS
, SH
, MB
, ME
}},
8391 {"e_rlwinm", M(29,1), M_MASK
, PPCVLE
, 0, {RA
, RT
, SH
, MBE
, ME
}},
8392 {"e_b", BD24(30,0,0), BD24_MASK
, PPCVLE
, 0, {B24
}},
8393 {"e_bl", BD24(30,0,1), BD24_MASK
, PPCVLE
, 0, {B24
}},
8394 {"e_bdnz", EBD15(30,8,BO32DNZ
,0), EBD15_MASK
, PPCVLE
, 0, {B15
}},
8395 {"e_bdnzl", EBD15(30,8,BO32DNZ
,1), EBD15_MASK
, PPCVLE
, 0, {B15
}},
8396 {"e_bdz", EBD15(30,8,BO32DZ
,0), EBD15_MASK
, PPCVLE
, 0, {B15
}},
8397 {"e_bdzl", EBD15(30,8,BO32DZ
,1), EBD15_MASK
, PPCVLE
, 0, {B15
}},
8398 {"e_bge", EBD15BI(30,8,BO32F
,CBLT
,0), EBD15BI_MASK
, PPCVLE
, 0, {CRS
,B15
}},
8399 {"e_bgel", EBD15BI(30,8,BO32F
,CBLT
,1), EBD15BI_MASK
, PPCVLE
, 0, {CRS
,B15
}},
8400 {"e_bnl", EBD15BI(30,8,BO32F
,CBLT
,0), EBD15BI_MASK
, PPCVLE
, 0, {CRS
,B15
}},
8401 {"e_bnll", EBD15BI(30,8,BO32F
,CBLT
,1), EBD15BI_MASK
, PPCVLE
, 0, {CRS
,B15
}},
8402 {"e_blt", EBD15BI(30,8,BO32T
,CBLT
,0), EBD15BI_MASK
, PPCVLE
, 0, {CRS
,B15
}},
8403 {"e_bltl", EBD15BI(30,8,BO32T
,CBLT
,1), EBD15BI_MASK
, PPCVLE
, 0, {CRS
,B15
}},
8404 {"e_bgt", EBD15BI(30,8,BO32T
,CBGT
,0), EBD15BI_MASK
, PPCVLE
, 0, {CRS
,B15
}},
8405 {"e_bgtl", EBD15BI(30,8,BO32T
,CBGT
,1), EBD15BI_MASK
, PPCVLE
, 0, {CRS
,B15
}},
8406 {"e_ble", EBD15BI(30,8,BO32F
,CBGT
,0), EBD15BI_MASK
, PPCVLE
, 0, {CRS
,B15
}},
8407 {"e_blel", EBD15BI(30,8,BO32F
,CBGT
,1), EBD15BI_MASK
, PPCVLE
, 0, {CRS
,B15
}},
8408 {"e_bng", EBD15BI(30,8,BO32F
,CBGT
,0), EBD15BI_MASK
, PPCVLE
, 0, {CRS
,B15
}},
8409 {"e_bngl", EBD15BI(30,8,BO32F
,CBGT
,1), EBD15BI_MASK
, PPCVLE
, 0, {CRS
,B15
}},
8410 {"e_bne", EBD15BI(30,8,BO32F
,CBEQ
,0), EBD15BI_MASK
, PPCVLE
, 0, {CRS
,B15
}},
8411 {"e_bnel", EBD15BI(30,8,BO32F
,CBEQ
,1), EBD15BI_MASK
, PPCVLE
, 0, {CRS
,B15
}},
8412 {"e_beq", EBD15BI(30,8,BO32T
,CBEQ
,0), EBD15BI_MASK
, PPCVLE
, 0, {CRS
,B15
}},
8413 {"e_beql", EBD15BI(30,8,BO32T
,CBEQ
,1), EBD15BI_MASK
, PPCVLE
, 0, {CRS
,B15
}},
8414 {"e_bso", EBD15BI(30,8,BO32T
,CBSO
,0), EBD15BI_MASK
, PPCVLE
, 0, {CRS
,B15
}},
8415 {"e_bsol", EBD15BI(30,8,BO32T
,CBSO
,1), EBD15BI_MASK
, PPCVLE
, 0, {CRS
,B15
}},
8416 {"e_bun", EBD15BI(30,8,BO32T
,CBSO
,0), EBD15BI_MASK
, PPCVLE
, 0, {CRS
,B15
}},
8417 {"e_bunl", EBD15BI(30,8,BO32T
,CBSO
,1), EBD15BI_MASK
, PPCVLE
, 0, {CRS
,B15
}},
8418 {"e_bns", EBD15BI(30,8,BO32F
,CBSO
,0), EBD15BI_MASK
, PPCVLE
, 0, {CRS
,B15
}},
8419 {"e_bnsl", EBD15BI(30,8,BO32F
,CBSO
,1), EBD15BI_MASK
, PPCVLE
, 0, {CRS
,B15
}},
8420 {"e_bnu", EBD15BI(30,8,BO32F
,CBSO
,0), EBD15BI_MASK
, PPCVLE
, 0, {CRS
,B15
}},
8421 {"e_bnul", EBD15BI(30,8,BO32F
,CBSO
,1), EBD15BI_MASK
, PPCVLE
, 0, {CRS
,B15
}},
8422 {"e_bc", BD15(30,8,0), BD15_MASK
, PPCVLE
, 0, {BO32
, BI32
, B15
}},
8423 {"e_bcl", BD15(30,8,1), BD15_MASK
, PPCVLE
, 0, {BO32
, BI32
, B15
}},
8425 {"e_bf", EBD15(30,8,BO32F
,0), EBD15_MASK
, PPCVLE
, 0, {BI32
,B15
}},
8426 {"e_bfl", EBD15(30,8,BO32F
,1), EBD15_MASK
, PPCVLE
, 0, {BI32
,B15
}},
8427 {"e_bt", EBD15(30,8,BO32T
,0), EBD15_MASK
, PPCVLE
, 0, {BI32
,B15
}},
8428 {"e_btl", EBD15(30,8,BO32T
,1), EBD15_MASK
, PPCVLE
, 0, {BI32
,B15
}},
8430 {"e_cmph", X(31,14), X_MASK
, PPCVLE
, 0, {CRD
, RA
, RB
}},
8431 {"e_sc", X(31,36), XRTRA_MASK
, PPCVLE
, 0, {ELEV
}},
8432 {"e_cmphl", X(31,46), X_MASK
, PPCVLE
, 0, {CRD
, RA
, RB
}},
8433 {"e_crandc", XL(31,129), XL_MASK
, PPCVLE
, 0, {BT
, BA
, BB
}},
8434 {"e_crnand", XL(31,225), XL_MASK
, PPCVLE
, 0, {BT
, BA
, BB
}},
8435 {"e_crnot", XL(31,33), XL_MASK
, PPCVLE
, 0, {BT
, BAB
}},
8436 {"e_crnor", XL(31,33), XL_MASK
, PPCVLE
, 0, {BT
, BA
, BB
}},
8437 {"e_crclr", XL(31,193), XL_MASK
, PPCVLE
, 0, {BTAB
}},
8438 {"e_crxor", XL(31,193), XL_MASK
, PPCVLE
, 0, {BT
, BA
, BB
}},
8439 {"e_mcrf", XL(31,16), XL_MASK
, PPCVLE
, 0, {CRD
, CR
}},
8440 {"e_slwi", EX(31,112), EX_MASK
, PPCVLE
, 0, {RA
, RS
, SH
}},
8441 {"e_slwi.", EX(31,113), EX_MASK
, PPCVLE
, 0, {RA
, RS
, SH
}},
8443 {"e_crand", XL(31,257), XL_MASK
, PPCVLE
, 0, {BT
, BA
, BB
}},
8445 {"e_rlw", EX(31,560), EX_MASK
, PPCVLE
, 0, {RA
, RS
, RB
}},
8446 {"e_rlw.", EX(31,561), EX_MASK
, PPCVLE
, 0, {RA
, RS
, RB
}},
8448 {"e_crset", XL(31,289), XL_MASK
, PPCVLE
, 0, {BTAB
}},
8449 {"e_creqv", XL(31,289), XL_MASK
, PPCVLE
, 0, {BT
, BA
, BB
}},
8451 {"e_rlwi", EX(31,624), EX_MASK
, PPCVLE
, 0, {RA
, RS
, SH
}},
8452 {"e_rlwi.", EX(31,625), EX_MASK
, PPCVLE
, 0, {RA
, RS
, SH
}},
8454 {"e_crorc", XL(31,417), XL_MASK
, PPCVLE
, 0, {BT
, BA
, BB
}},
8456 {"e_crmove", XL(31,449), XL_MASK
, PPCVLE
, 0, {BT
, BAB
}},
8457 {"e_cror", XL(31,449), XL_MASK
, PPCVLE
, 0, {BT
, BA
, BB
}},
8459 {"mtmas1", XSPR(31,467,625), XSPR_MASK
, PPCVLE
, 0, {RS
}},
8461 {"e_srwi", EX(31,1136), EX_MASK
, PPCVLE
, 0, {RA
, RS
, SH
}},
8462 {"e_srwi.", EX(31,1137), EX_MASK
, PPCVLE
, 0, {RA
, RS
, SH
}},
8464 {"se_lbz", SD4(8), SD4_MASK
, PPCVLE
, 0, {RZ
, SE_SD
, RX
}},
8466 {"se_stb", SD4(9), SD4_MASK
, PPCVLE
, 0, {RZ
, SE_SD
, RX
}},
8468 {"se_lhz", SD4(10), SD4_MASK
, PPCVLE
, 0, {RZ
, SE_SDH
, RX
}},
8470 {"se_sth", SD4(11), SD4_MASK
, PPCVLE
, 0, {RZ
, SE_SDH
, RX
}},
8472 {"se_lwz", SD4(12), SD4_MASK
, PPCVLE
, 0, {RZ
, SE_SDW
, RX
}},
8474 {"se_stw", SD4(13), SD4_MASK
, PPCVLE
, 0, {RZ
, SE_SDW
, RX
}},
8476 {"se_bge", EBD8IO(28,0,0), EBD8IO3_MASK
, PPCVLE
, 0, {B8
}},
8477 {"se_bnl", EBD8IO(28,0,0), EBD8IO3_MASK
, PPCVLE
, 0, {B8
}},
8478 {"se_ble", EBD8IO(28,0,1), EBD8IO3_MASK
, PPCVLE
, 0, {B8
}},
8479 {"se_bng", EBD8IO(28,0,1), EBD8IO3_MASK
, PPCVLE
, 0, {B8
}},
8480 {"se_bne", EBD8IO(28,0,2), EBD8IO3_MASK
, PPCVLE
, 0, {B8
}},
8481 {"se_bns", EBD8IO(28,0,3), EBD8IO3_MASK
, PPCVLE
, 0, {B8
}},
8482 {"se_bnu", EBD8IO(28,0,3), EBD8IO3_MASK
, PPCVLE
, 0, {B8
}},
8483 {"se_bf", EBD8IO(28,0,0), EBD8IO2_MASK
, PPCVLE
, 0, {BI16
, B8
}},
8484 {"se_blt", EBD8IO(28,1,0), EBD8IO3_MASK
, PPCVLE
, 0, {B8
}},
8485 {"se_bgt", EBD8IO(28,1,1), EBD8IO3_MASK
, PPCVLE
, 0, {B8
}},
8486 {"se_beq", EBD8IO(28,1,2), EBD8IO3_MASK
, PPCVLE
, 0, {B8
}},
8487 {"se_bso", EBD8IO(28,1,3), EBD8IO3_MASK
, PPCVLE
, 0, {B8
}},
8488 {"se_bun", EBD8IO(28,1,3), EBD8IO3_MASK
, PPCVLE
, 0, {B8
}},
8489 {"se_bt", EBD8IO(28,1,0), EBD8IO2_MASK
, PPCVLE
, 0, {BI16
, B8
}},
8490 {"se_bc", BD8IO(28), BD8IO_MASK
, PPCVLE
, 0, {BO16
, BI16
, B8
}},
8491 {"se_b", BD8(58,0,0), BD8_MASK
, PPCVLE
, 0, {B8
}},
8492 {"se_bl", BD8(58,0,1), BD8_MASK
, PPCVLE
, 0, {B8
}},
8495 const unsigned int vle_num_opcodes
=
8496 sizeof (vle_opcodes
) / sizeof (vle_opcodes
[0]);
8498 /* The macro table. This is only used by the assembler. */
8500 /* The expressions of the form (-x ! 31) & (x | 31) have the value 0
8501 when x=0; 32-x when x is between 1 and 31; are negative if x is
8502 negative; and are 32 or more otherwise. This is what you want
8503 when, for instance, you are emulating a right shift by a
8504 rotate-left-and-mask, because the underlying instructions support
8505 shifts of size 0 but not shifts of size 32. By comparison, when
8506 extracting x bits from some word you want to use just 32-x, because
8507 the underlying instructions don't support extracting 0 bits but do
8508 support extracting the whole word (32 bits in this case). */
8510 const struct powerpc_macro powerpc_macros
[] = {
8511 {"extldi", 4, PPC64
, "rldicr %0,%1,%3,(%2)-1"},
8512 {"extldi.", 4, PPC64
, "rldicr. %0,%1,%3,(%2)-1"},
8513 {"extrdi", 4, PPC64
, "rldicl %0,%1,((%2)+(%3))&((%2)+(%3)<>64),64-(%2)"},
8514 {"extrdi.", 4, PPC64
, "rldicl. %0,%1,((%2)+(%3))&((%2)+(%3)<>64),64-(%2)"},
8515 {"insrdi", 4, PPC64
, "rldimi %0,%1,64-((%2)+(%3)),%3"},
8516 {"insrdi.", 4, PPC64
, "rldimi. %0,%1,64-((%2)+(%3)),%3"},
8517 {"rotrdi", 3, PPC64
, "rldicl %0,%1,(-(%2)!63)&((%2)|63),0"},
8518 {"rotrdi.", 3, PPC64
, "rldicl. %0,%1,(-(%2)!63)&((%2)|63),0"},
8519 {"sldi", 3, PPC64
, "rldicr %0,%1,%2,63-(%2)"},
8520 {"sldi.", 3, PPC64
, "rldicr. %0,%1,%2,63-(%2)"},
8521 {"srdi", 3, PPC64
, "rldicl %0,%1,(-(%2)!63)&((%2)|63),%2"},
8522 {"srdi.", 3, PPC64
, "rldicl. %0,%1,(-(%2)!63)&((%2)|63),%2"},
8523 {"clrrdi", 3, PPC64
, "rldicr %0,%1,0,63-(%2)"},
8524 {"clrrdi.", 3, PPC64
, "rldicr. %0,%1,0,63-(%2)"},
8525 {"clrlsldi", 4, PPC64
, "rldic %0,%1,%3,(%2)-(%3)"},
8526 {"clrlsldi.",4, PPC64
, "rldic. %0,%1,%3,(%2)-(%3)"},
8528 {"extlwi", 4, PPCCOM
, "rlwinm %0,%1,%3,0,(%2)-1"},
8529 {"extlwi.", 4, PPCCOM
, "rlwinm. %0,%1,%3,0,(%2)-1"},
8530 {"extrwi", 4, PPCCOM
, "rlwinm %0,%1,((%2)+(%3))&((%2)+(%3)<>32),32-(%2),31"},
8531 {"extrwi.", 4, PPCCOM
, "rlwinm. %0,%1,((%2)+(%3))&((%2)+(%3)<>32),32-(%2),31"},
8532 {"inslwi", 4, PPCCOM
, "rlwimi %0,%1,(-(%3)!31)&((%3)|31),%3,(%2)+(%3)-1"},
8533 {"inslwi.", 4, PPCCOM
, "rlwimi. %0,%1,(-(%3)!31)&((%3)|31),%3,(%2)+(%3)-1"},
8534 {"insrwi", 4, PPCCOM
, "rlwimi %0,%1,32-((%2)+(%3)),%3,(%2)+(%3)-1"},
8535 {"insrwi.", 4, PPCCOM
, "rlwimi. %0,%1,32-((%2)+(%3)),%3,(%2)+(%3)-1"},
8536 {"rotrwi", 3, PPCCOM
, "rlwinm %0,%1,(-(%2)!31)&((%2)|31),0,31"},
8537 {"rotrwi.", 3, PPCCOM
, "rlwinm. %0,%1,(-(%2)!31)&((%2)|31),0,31"},
8538 {"slwi", 3, PPCCOM
, "rlwinm %0,%1,%2,0,31-(%2)"},
8539 {"sli", 3, PWRCOM
, "rlinm %0,%1,%2,0,31-(%2)"},
8540 {"slwi.", 3, PPCCOM
, "rlwinm. %0,%1,%2,0,31-(%2)"},
8541 {"sli.", 3, PWRCOM
, "rlinm. %0,%1,%2,0,31-(%2)"},
8542 {"srwi", 3, PPCCOM
, "rlwinm %0,%1,(-(%2)!31)&((%2)|31),%2,31"},
8543 {"sri", 3, PWRCOM
, "rlinm %0,%1,(-(%2)!31)&((%2)|31),%2,31"},
8544 {"srwi.", 3, PPCCOM
, "rlwinm. %0,%1,(-(%2)!31)&((%2)|31),%2,31"},
8545 {"sri.", 3, PWRCOM
, "rlinm. %0,%1,(-(%2)!31)&((%2)|31),%2,31"},
8546 {"clrrwi", 3, PPCCOM
, "rlwinm %0,%1,0,0,31-(%2)"},
8547 {"clrrwi.", 3, PPCCOM
, "rlwinm. %0,%1,0,0,31-(%2)"},
8548 {"clrlslwi", 4, PPCCOM
, "rlwinm %0,%1,%3,(%2)-(%3),31-(%3)"},
8549 {"clrlslwi.",4, PPCCOM
, "rlwinm. %0,%1,%3,(%2)-(%3),31-(%3)"},
8551 {"e_extlwi", 4, PPCVLE
, "e_rlwinm %0,%1,%3,0,(%2)-1"},
8552 {"e_extrwi", 4, PPCVLE
, "e_rlwinm %0,%1,((%2)+(%3))&((%2)+(%3)<>32),32-(%2),31"},
8553 {"e_inslwi", 4, PPCVLE
, "e_rlwimi %0,%1,(-(%3)!31)&((%3)|31),%3,(%2)+(%3)-1"},
8554 {"e_insrwi", 4, PPCVLE
, "e_rlwimi %0,%1,32-((%2)+(%3)),%3,(%2)+(%3)-1"},
8555 {"e_rotlwi", 3, PPCVLE
, "e_rlwinm %0,%1,%2,0,31"},
8556 {"e_rotrwi", 3, PPCVLE
, "e_rlwinm %0,%1,(-(%2)!31)&((%2)|31),0,31"},
8557 {"e_slwi", 3, PPCVLE
, "e_rlwinm %0,%1,%2,0,31-(%2)"},
8558 {"e_srwi", 3, PPCVLE
, "e_rlwinm %0,%1,(-(%2)!31)&((%2)|31),%2,31"},
8559 {"e_clrlwi", 3, PPCVLE
, "e_rlwinm %0,%1,0,%2,31"},
8560 {"e_clrrwi", 3, PPCVLE
, "e_rlwinm %0,%1,0,0,31-(%2)"},
8561 {"e_clrlslwi",4, PPCVLE
, "e_rlwinm %0,%1,%3,(%2)-(%3),31-(%3)"},
8563 /* old SPE instructions have new names with the same opcodes */
8564 {"evsadd", 3, PPCSPE
|PPCVLE
, "efsadd %0,%1,%2"},
8565 {"evssub", 3, PPCSPE
|PPCVLE
, "efssub %0,%1,%2"},
8566 {"evsabs", 2, PPCSPE
|PPCVLE
, "efsabs %0,%1"},
8567 {"evsnabs", 2, PPCSPE
|PPCVLE
, "efsnabs %0,%1"},
8568 {"evsneg", 2, PPCSPE
|PPCVLE
, "efsneg %0,%1"},
8569 {"evsmul", 3, PPCSPE
|PPCVLE
, "efsmul %0,%1,%2"},
8570 {"evsdiv", 3, PPCSPE
|PPCVLE
, "efsdiv %0,%1,%2"},
8571 {"evscmpgt", 3, PPCSPE
|PPCVLE
, "efscmpgt %0,%1,%2"},
8572 {"evsgmplt", 3, PPCSPE
|PPCVLE
, "efscmplt %0,%1,%2"},
8573 {"evsgmpeq", 3, PPCSPE
|PPCVLE
, "efscmpeq %0,%1,%2"},
8574 {"evscfui", 2, PPCSPE
|PPCVLE
, "efscfui %0,%1"},
8575 {"evscfsi", 2, PPCSPE
|PPCVLE
, "efscfsi %0,%1"},
8576 {"evscfuf", 2, PPCSPE
|PPCVLE
, "efscfuf %0,%1"},
8577 {"evscfsf", 2, PPCSPE
|PPCVLE
, "efscfsf %0,%1"},
8578 {"evsctui", 2, PPCSPE
|PPCVLE
, "efsctui %0,%1"},
8579 {"evsctsi", 2, PPCSPE
|PPCVLE
, "efsctsi %0,%1"},
8580 {"evsctuf", 2, PPCSPE
|PPCVLE
, "efsctuf %0,%1"},
8581 {"evsctsf", 2, PPCSPE
|PPCVLE
, "efsctsf %0,%1"},
8582 {"evsctuiz", 2, PPCSPE
|PPCVLE
, "efsctuiz %0,%1"},
8583 {"evsctsiz", 2, PPCSPE
|PPCVLE
, "efsctsiz %0,%1"},
8584 {"evststgt", 3, PPCSPE
|PPCVLE
, "efststgt %0,%1,%2"},
8585 {"evststlt", 3, PPCSPE
|PPCVLE
, "efststlt %0,%1,%2"},
8586 {"evststeq", 3, PPCSPE
|PPCVLE
, "efststeq %0,%1,%2"},
8588 /* SPE2 instructions which just are mapped to SPE2 */
8589 {"evdotphsssi", 3, PPCSPE2
, "evdotphssmi %0,%1,%2"},
8590 {"evdotphsssia", 3, PPCSPE2
, "evdotphssmia %0,%1,%2"},
8591 {"evdotpwsssi", 3, PPCSPE2
, "evdotpwssmi %0,%1,%2"},
8592 {"evdotpwsssia", 3, PPCSPE2
, "evdotpwssmia %0,%1,%2"}
8595 const int powerpc_num_macros
=
8596 sizeof (powerpc_macros
) / sizeof (powerpc_macros
[0]);
8598 /* SPE v2 instruction set from SPE2PIM Rev. 2 08/2011 */
8599 const struct powerpc_opcode spe2_opcodes
[] = {
8600 {"evdotpwcssi", VX (4, 128), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
8601 {"evdotpwcsmi", VX (4, 129), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
8602 {"evdotpwcssfr", VX (4, 130), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
8603 {"evdotpwcssf", VX (4, 131), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
8604 {"evdotpwgasmf", VX (4, 136), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
8605 {"evdotpwxgasmf", VX (4, 137), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
8606 {"evdotpwgasmfr", VX (4, 138), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
8607 {"evdotpwxgasmfr", VX (4, 139), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
8608 {"evdotpwgssmf", VX (4, 140), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
8609 {"evdotpwxgssmf", VX (4, 141), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
8610 {"evdotpwgssmfr", VX (4, 142), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
8611 {"evdotpwxgssmfr", VX (4, 143), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
8612 {"evdotpwcssiaaw3", VX (4, 144), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
8613 {"evdotpwcsmiaaw3", VX (4, 145), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
8614 {"evdotpwcssfraaw3", VX (4, 146), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
8615 {"evdotpwcssfaaw3", VX (4, 147), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
8616 {"evdotpwgasmfaa3", VX (4, 152), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
8617 {"evdotpwxgasmfaa3", VX (4, 153), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
8618 {"evdotpwgasmfraa3", VX (4, 154), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
8619 {"evdotpwxgasmfraa3", VX (4, 155), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
8620 {"evdotpwgssmfaa3", VX (4, 156), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
8621 {"evdotpwxgssmfaa3", VX (4, 157), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
8622 {"evdotpwgssmfraa3", VX (4, 158), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
8623 {"evdotpwxgssmfraa3", VX (4, 159), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
8624 {"evdotpwcssia", VX (4, 160), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
8625 {"evdotpwcsmia", VX (4, 161), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
8626 {"evdotpwcssfra", VX (4, 162), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
8627 {"evdotpwcssfa", VX (4, 163), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
8628 {"evdotpwgasmfa", VX (4, 168), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
8629 {"evdotpwxgasmfa", VX (4, 169), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
8630 {"evdotpwgasmfra", VX (4, 170), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
8631 {"evdotpwxgasmfra", VX (4, 171), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
8632 {"evdotpwgssmfa", VX (4, 172), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
8633 {"evdotpwxgssmfa", VX (4, 173), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
8634 {"evdotpwgssmfra", VX (4, 174), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
8635 {"evdotpwxgssmfra", VX (4, 175), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
8636 {"evdotpwcssiaaw", VX (4, 176), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
8637 {"evdotpwcsmiaaw", VX (4, 177), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
8638 {"evdotpwcssfraaw", VX (4, 178), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
8639 {"evdotpwcssfaaw", VX (4, 179), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
8640 {"evdotpwgasmfaa", VX (4, 184), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
8641 {"evdotpwxgasmfaa", VX (4, 185), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
8642 {"evdotpwgasmfraa", VX (4, 186), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
8643 {"evdotpwxgasmfraa", VX (4, 187), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
8644 {"evdotpwgssmfaa", VX (4, 188), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
8645 {"evdotpwxgssmfaa", VX (4, 189), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
8646 {"evdotpwgssmfraa", VX (4, 190), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
8647 {"evdotpwxgssmfraa", VX (4, 191), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
8648 {"evdotphihcssi", VX (4, 256), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
8649 {"evdotplohcssi", VX (4, 257), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
8650 {"evdotphihcssf", VX (4, 258), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
8651 {"evdotplohcssf", VX (4, 259), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
8652 {"evdotphihcsmi", VX (4, 264), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
8653 {"evdotplohcsmi", VX (4, 265), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
8654 {"evdotphihcssfr", VX (4, 266), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
8655 {"evdotplohcssfr", VX (4, 267), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
8656 {"evdotphihcssiaaw3", VX (4, 272), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
8657 {"evdotplohcssiaaw3", VX (4, 273), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
8658 {"evdotphihcssfaaw3", VX (4, 274), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
8659 {"evdotplohcssfaaw3", VX (4, 275), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
8660 {"evdotphihcsmiaaw3", VX (4, 280), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
8661 {"evdotplohcsmiaaw3", VX (4, 281), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
8662 {"evdotphihcssfraaw3", VX (4, 282), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
8663 {"evdotplohcssfraaw3", VX (4, 283), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
8664 {"evdotphihcssia", VX (4, 288), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
8665 {"evdotplohcssia", VX (4, 289), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
8666 {"evdotphihcssfa", VX (4, 290), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
8667 {"evdotplohcssfa", VX (4, 291), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
8668 {"evdotphihcsmia", VX (4, 296), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
8669 {"evdotplohcsmia", VX (4, 297), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
8670 {"evdotphihcssfra", VX (4, 298), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
8671 {"evdotplohcssfra", VX (4, 299), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
8672 {"evdotphihcssiaaw", VX (4, 304), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
8673 {"evdotplohcssiaaw", VX (4, 305), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
8674 {"evdotphihcssfaaw", VX (4, 306), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
8675 {"evdotplohcssfaaw", VX (4, 307), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
8676 {"evdotphihcsmiaaw", VX (4, 312), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
8677 {"evdotplohcsmiaaw", VX (4, 313), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
8678 {"evdotphihcssfraaw", VX (4, 314), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
8679 {"evdotplohcssfraaw", VX (4, 315), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
8680 {"evdotphausi", VX (4, 320), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
8681 {"evdotphassi", VX (4, 321), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
8682 {"evdotphasusi", VX (4, 322), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
8683 {"evdotphassf", VX (4, 323), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
8684 {"evdotphsssf", VX (4, 327), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
8685 {"evdotphaumi", VX (4, 328), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
8686 {"evdotphasmi", VX (4, 329), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
8687 {"evdotphasumi", VX (4, 330), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
8688 {"evdotphassfr", VX (4, 331), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
8689 {"evdotphssmi", VX (4, 333), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
8690 {"evdotphsssfr", VX (4, 335), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
8691 {"evdotphausiaaw3", VX (4, 336), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
8692 {"evdotphassiaaw3", VX (4, 337), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
8693 {"evdotphasusiaaw3", VX (4, 338), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
8694 {"evdotphassfaaw3", VX (4, 339), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
8695 {"evdotphsssiaaw3", VX (4, 341), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
8696 {"evdotphsssfaaw3", VX (4, 343), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
8697 {"evdotphaumiaaw3", VX (4, 344), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
8698 {"evdotphasmiaaw3", VX (4, 345), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
8699 {"evdotphasumiaaw3", VX (4, 346), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
8700 {"evdotphassfraaw3", VX (4, 347), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
8701 {"evdotphssmiaaw3", VX (4, 349), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
8702 {"evdotphsssfraaw3", VX (4, 351), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
8703 {"evdotphausia", VX (4, 352), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
8704 {"evdotphassia", VX (4, 353), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
8705 {"evdotphasusia", VX (4, 354), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
8706 {"evdotphassfa", VX (4, 355), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
8707 {"evdotphsssfa", VX (4, 359), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
8708 {"evdotphaumia", VX (4, 360), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
8709 {"evdotphasmia", VX (4, 361), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
8710 {"evdotphasumia", VX (4, 362), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
8711 {"evdotphassfra", VX (4, 363), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
8712 {"evdotphssmia", VX (4, 365), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
8713 {"evdotphsssfra", VX (4, 367), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
8714 {"evdotphausiaaw", VX (4, 368), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
8715 {"evdotphassiaaw", VX (4, 369), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
8716 {"evdotphasusiaaw", VX (4, 370), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
8717 {"evdotphassfaaw", VX (4, 371), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
8718 {"evdotphsssiaaw", VX (4, 373), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
8719 {"evdotphsssfaaw", VX (4, 375), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
8720 {"evdotphaumiaaw", VX (4, 376), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
8721 {"evdotphasmiaaw", VX (4, 377), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
8722 {"evdotphasumiaaw", VX (4, 378), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
8723 {"evdotphassfraaw", VX (4, 379), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
8724 {"evdotphssmiaaw", VX (4, 381), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
8725 {"evdotphsssfraaw", VX (4, 383), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
8726 {"evdotp4hgaumi", VX (4, 384), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
8727 {"evdotp4hgasmi", VX (4, 385), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
8728 {"evdotp4hgasumi", VX (4, 386), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
8729 {"evdotp4hgasmf", VX (4, 387), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
8730 {"evdotp4hgssmi", VX (4, 388), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
8731 {"evdotp4hgssmf", VX (4, 389), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
8732 {"evdotp4hxgasmi", VX (4, 390), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
8733 {"evdotp4hxgasmf", VX (4, 391), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
8734 {"evdotpbaumi", VX (4, 392), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
8735 {"evdotpbasmi", VX (4, 393), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
8736 {"evdotpbasumi", VX (4, 394), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
8737 {"evdotp4hxgssmi", VX (4, 398), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
8738 {"evdotp4hxgssmf", VX (4, 399), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
8739 {"evdotp4hgaumiaa3", VX (4, 400), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
8740 {"evdotp4hgasmiaa3", VX (4, 401), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
8741 {"evdotp4hgasumiaa3", VX (4, 402), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
8742 {"evdotp4hgasmfaa3", VX (4, 403), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
8743 {"evdotp4hgssmiaa3", VX (4, 404), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
8744 {"evdotp4hgssmfaa3", VX (4, 405), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
8745 {"evdotp4hxgasmiaa3", VX (4, 406), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
8746 {"evdotp4hxgasmfaa3", VX (4, 407), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
8747 {"evdotpbaumiaaw3", VX (4, 408), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
8748 {"evdotpbasmiaaw3", VX (4, 409), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
8749 {"evdotpbasumiaaw3", VX (4, 410), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
8750 {"evdotp4hxgssmiaa3", VX (4, 414), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
8751 {"evdotp4hxgssmfaa3", VX (4, 415), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
8752 {"evdotp4hgaumia", VX (4, 416), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
8753 {"evdotp4hgasmia", VX (4, 417), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
8754 {"evdotp4hgasumia", VX (4, 418), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
8755 {"evdotp4hgasmfa", VX (4, 419), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
8756 {"evdotp4hgssmia", VX (4, 420), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
8757 {"evdotp4hgssmfa", VX (4, 421), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
8758 {"evdotp4hxgasmia", VX (4, 422), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
8759 {"evdotp4hxgasmfa", VX (4, 423), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
8760 {"evdotpbaumia", VX (4, 424), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
8761 {"evdotpbasmia", VX (4, 425), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
8762 {"evdotpbasumia", VX (4, 426), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
8763 {"evdotp4hxgssmia", VX (4, 430), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
8764 {"evdotp4hxgssmfa", VX (4, 431), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
8765 {"evdotp4hgaumiaa", VX (4, 432), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
8766 {"evdotp4hgasmiaa", VX (4, 433), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
8767 {"evdotp4hgasumiaa", VX (4, 434), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
8768 {"evdotp4hgasmfaa", VX (4, 435), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
8769 {"evdotp4hgssmiaa", VX (4, 436), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
8770 {"evdotp4hgssmfaa", VX (4, 437), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
8771 {"evdotp4hxgasmiaa", VX (4, 438), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
8772 {"evdotp4hxgasmfaa", VX (4, 439), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
8773 {"evdotpbaumiaaw", VX (4, 440), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
8774 {"evdotpbasmiaaw", VX (4, 441), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
8775 {"evdotpbasumiaaw", VX (4, 442), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
8776 {"evdotp4hxgssmiaa", VX (4, 446), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
8777 {"evdotp4hxgssmfaa", VX (4, 447), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
8778 {"evdotpwausi", VX (4, 448), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
8779 {"evdotpwassi", VX (4, 449), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
8780 {"evdotpwasusi", VX (4, 450), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
8781 {"evdotpwaumi", VX (4, 456), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
8782 {"evdotpwasmi", VX (4, 457), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
8783 {"evdotpwasumi", VX (4, 458), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
8784 {"evdotpwssmi", VX (4, 461), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
8785 {"evdotpwausiaa3", VX (4, 464), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
8786 {"evdotpwassiaa3", VX (4, 465), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
8787 {"evdotpwasusiaa3", VX (4, 466), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
8788 {"evdotpwsssiaa3", VX (4, 469), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
8789 {"evdotpwaumiaa3", VX (4, 472), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
8790 {"evdotpwasmiaa3", VX (4, 473), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
8791 {"evdotpwasumiaa3", VX (4, 474), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
8792 {"evdotpwssmiaa3", VX (4, 477), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
8793 {"evdotpwausia", VX (4, 480), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
8794 {"evdotpwassia", VX (4, 481), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
8795 {"evdotpwasusia", VX (4, 482), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
8796 {"evdotpwaumia", VX (4, 488), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
8797 {"evdotpwasmia", VX (4, 489), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
8798 {"evdotpwasumia", VX (4, 490), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
8799 {"evdotpwssmia", VX (4, 493), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
8800 {"evdotpwausiaa", VX (4, 496), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
8801 {"evdotpwassiaa", VX (4, 497), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
8802 {"evdotpwasusiaa", VX (4, 498), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
8803 {"evdotpwsssiaa", VX (4, 501), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
8804 {"evdotpwaumiaa", VX (4, 504), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
8805 {"evdotpwasmiaa", VX (4, 505), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
8806 {"evdotpwasumiaa", VX (4, 506), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
8807 {"evdotpwssmiaa", VX (4, 509), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
8808 {"evaddib", VX (4, 515), VX_MASK
, PPCSPE2
, 0, {RD
, RB
, UIMM
}},
8809 {"evaddih", VX (4, 513), VX_MASK
, PPCSPE2
, 0, {RD
, RB
, UIMM
}},
8810 {"evsubifh", VX (4, 517), VX_MASK
, PPCSPE2
, 0, {RD
, UIMM
, RB
}},
8811 {"evsubifb", VX (4, 519), VX_MASK
, PPCSPE2
, 0, {RD
, UIMM
, RB
}},
8812 {"evabsb", VX_RB_CONST(4, 520, 2), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, RA
}},
8813 {"evabsh", VX_RB_CONST(4, 520, 4), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, RA
}},
8814 {"evabsd", VX_RB_CONST(4, 520, 6), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, RA
}},
8815 {"evabss", VX_RB_CONST(4, 520, 8), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, RA
}},
8816 {"evabsbs", VX_RB_CONST(4, 520, 10), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, RA
}},
8817 {"evabshs", VX_RB_CONST(4, 520, 12), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, RA
}},
8818 {"evabsds", VX_RB_CONST(4, 520, 14), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, RA
}},
8819 {"evnegwo", VX_RB_CONST(4, 521, 1), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, RA
}},
8820 {"evnegb", VX_RB_CONST(4, 521, 2), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, RA
}},
8821 {"evnegbo", VX_RB_CONST(4, 521, 3), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, RA
}},
8822 {"evnegh", VX_RB_CONST(4, 521, 4), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, RA
}},
8823 {"evnegho", VX_RB_CONST(4, 521, 5), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, RA
}},
8824 {"evnegd", VX_RB_CONST(4, 521, 6), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, RA
}},
8825 {"evnegs", VX_RB_CONST(4, 521, 8), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, RA
}},
8826 {"evnegwos", VX_RB_CONST(4, 521, 9), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, RA
}},
8827 {"evnegbs", VX_RB_CONST(4, 521, 10), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, RA
}},
8828 {"evnegbos", VX_RB_CONST(4, 521, 11), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, RA
}},
8829 {"evneghs", VX_RB_CONST(4, 521, 12), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, RA
}},
8830 {"evneghos", VX_RB_CONST(4, 521, 13), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, RA
}},
8831 {"evnegds", VX_RB_CONST(4, 521, 14), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, RA
}},
8832 {"evextzb", VX_RB_CONST(4, 522, 1), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, RA
}},
8833 {"evextsbh", VX_RB_CONST(4, 522, 4), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, RA
}},
8834 {"evextsw", VX_RB_CONST(4, 523, 6), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, RA
}},
8835 {"evrndwh", VX_RB_CONST(4, 524, 0), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, RA
}},
8836 {"evrndhb", VX_RB_CONST(4, 524, 4), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, RA
}},
8837 {"evrnddw", VX_RB_CONST(4, 524, 6), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, RA
}},
8838 {"evrndwhus", VX_RB_CONST(4, 524, 8), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, RA
}},
8839 {"evrndwhss", VX_RB_CONST(4, 524, 9), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, RA
}},
8840 {"evrndhbus", VX_RB_CONST(4, 524, 12), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, RA
}},
8841 {"evrndhbss", VX_RB_CONST(4, 524, 13), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, RA
}},
8842 {"evrnddwus", VX_RB_CONST(4, 524, 14), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, RA
}},
8843 {"evrnddwss", VX_RB_CONST(4, 524, 15), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, RA
}},
8844 {"evrndwnh", VX_RB_CONST(4, 524, 16), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, RA
}},
8845 {"evrndhnb", VX_RB_CONST(4, 524, 20), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, RA
}},
8846 {"evrnddnw", VX_RB_CONST(4, 524, 22), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, RA
}},
8847 {"evrndwnhus", VX_RB_CONST(4, 524, 24), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, RA
}},
8848 {"evrndwnhss", VX_RB_CONST(4, 524, 25), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, RA
}},
8849 {"evrndhnbus", VX_RB_CONST(4, 524, 28), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, RA
}},
8850 {"evrndhnbss", VX_RB_CONST(4, 524, 29), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, RA
}},
8851 {"evrnddnwus", VX_RB_CONST(4, 524, 30), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, RA
}},
8852 {"evrnddnwss", VX_RB_CONST(4, 524, 31), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, RA
}},
8853 {"evcntlzh", VX_RB_CONST(4, 525, 4), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, RA
}},
8854 {"evcntlsh", VX_RB_CONST(4, 526, 4), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, RA
}},
8855 {"evpopcntb", VX_RB_CONST(4, 526, 26), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, RA
}},
8856 {"circinc", VX (4, 528), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
8857 {"evunpkhibui", VX_RB_CONST(4, 540, 0), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, RA
}},
8858 {"evunpkhibsi", VX_RB_CONST(4, 540, 1), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, RA
}},
8859 {"evunpkhihui", VX_RB_CONST(4, 540, 2), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, RA
}},
8860 {"evunpkhihsi", VX_RB_CONST(4, 540, 3), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, RA
}},
8861 {"evunpklobui", VX_RB_CONST(4, 540, 4), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, RA
}},
8862 {"evunpklobsi", VX_RB_CONST(4, 540, 5), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, RA
}},
8863 {"evunpklohui", VX_RB_CONST(4, 540, 6), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, RA
}},
8864 {"evunpklohsi", VX_RB_CONST(4, 540, 7), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, RA
}},
8865 {"evunpklohf", VX_RB_CONST(4, 540, 8), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, RA
}},
8866 {"evunpkhihf", VX_RB_CONST(4, 540, 9), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, RA
}},
8867 {"evunpklowgsf", VX_RB_CONST(4, 540, 12), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, RA
}},
8868 {"evunpkhiwgsf", VX_RB_CONST(4, 540, 13), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, RA
}},
8869 {"evsatsduw", VX_RB_CONST(4, 540, 16), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, RA
}},
8870 {"evsatsdsw", VX_RB_CONST(4, 540, 17), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, RA
}},
8871 {"evsatshub", VX_RB_CONST(4, 540, 18), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, RA
}},
8872 {"evsatshsb", VX_RB_CONST(4, 540, 19), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, RA
}},
8873 {"evsatuwuh", VX_RB_CONST(4, 540, 20), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, RA
}},
8874 {"evsatswsh", VX_RB_CONST(4, 540, 21), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, RA
}},
8875 {"evsatswuh", VX_RB_CONST(4, 540, 22), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, RA
}},
8876 {"evsatuhub", VX_RB_CONST(4, 540, 23), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, RA
}},
8877 {"evsatuduw", VX_RB_CONST(4, 540, 24), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, RA
}},
8878 {"evsatuwsw", VX_RB_CONST(4, 540, 25), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, RA
}},
8879 {"evsatshuh", VX_RB_CONST(4, 540, 26), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, RA
}},
8880 {"evsatuhsh", VX_RB_CONST(4, 540, 27), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, RA
}},
8881 {"evsatswuw", VX_RB_CONST(4, 540, 28), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, RA
}},
8882 {"evsatswgsdf", VX_RB_CONST(4, 540, 29), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, RA
}},
8883 {"evsatsbub", VX_RB_CONST(4, 540, 30), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, RA
}},
8884 {"evsatubsb", VX_RB_CONST(4, 540, 31), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, RA
}},
8885 {"evmaxhpuw", VX_RB_CONST(4, 541, 0), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, RA
}},
8886 {"evmaxhpsw", VX_RB_CONST(4, 541, 1), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, RA
}},
8887 {"evmaxbpuh", VX_RB_CONST(4, 541, 4), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, RA
}},
8888 {"evmaxbpsh", VX_RB_CONST(4, 541, 5), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, RA
}},
8889 {"evmaxwpud", VX_RB_CONST(4, 541, 6), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, RA
}},
8890 {"evmaxwpsd", VX_RB_CONST(4, 541, 7), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, RA
}},
8891 {"evminhpuw", VX_RB_CONST(4, 541, 8), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, RA
}},
8892 {"evminhpsw", VX_RB_CONST(4, 541, 9), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, RA
}},
8893 {"evminbpuh", VX_RB_CONST(4, 541, 12), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, RA
}},
8894 {"evminbpsh", VX_RB_CONST(4, 541, 13), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, RA
}},
8895 {"evminwpud", VX_RB_CONST(4, 541, 14), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, RA
}},
8896 {"evminwpsd", VX_RB_CONST(4, 541, 15), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, RA
}},
8897 {"evmaxmagws", VX (4, 543), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
8898 {"evsl", VX (4, 549), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
8899 {"evsli", VX (4, 551), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, EVUIMM
}},
8900 {"evsplatie", VX_RB_CONST (4, 553, 1), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, SIMM
}},
8901 {"evsplatib", VX_RB_CONST (4, 553, 2), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, SIMM
}},
8902 {"evsplatibe", VX_RB_CONST (4, 553, 3), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, SIMM
}},
8903 {"evsplatih", VX_RB_CONST (4, 553, 4), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, SIMM
}},
8904 {"evsplatihe", VX_RB_CONST (4, 553, 5), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, SIMM
}},
8905 {"evsplatid", VX_RB_CONST (4, 553, 6), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, SIMM
}},
8906 {"evsplatia", VX_RB_CONST (4, 553, 16), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, SIMM
}},
8907 {"evsplatiea", VX_RB_CONST (4, 553, 17), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, SIMM
}},
8908 {"evsplatiba", VX_RB_CONST (4, 553, 18), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, SIMM
}},
8909 {"evsplatibea", VX_RB_CONST (4, 553, 19), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, SIMM
}},
8910 {"evsplatiha", VX_RB_CONST (4, 553, 20), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, SIMM
}},
8911 {"evsplatihea", VX_RB_CONST (4, 553, 21), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, SIMM
}},
8912 {"evsplatida", VX_RB_CONST (4, 553, 22), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, SIMM
}},
8913 {"evsplatfio", VX_RB_CONST (4, 555, 1), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, SIMM
}},
8914 {"evsplatfib", VX_RB_CONST (4, 555, 2), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, SIMM
}},
8915 {"evsplatfibo", VX_RB_CONST (4, 555, 3), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, SIMM
}},
8916 {"evsplatfih", VX_RB_CONST (4, 555, 4), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, SIMM
}},
8917 {"evsplatfiho", VX_RB_CONST (4, 555, 5), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, SIMM
}},
8918 {"evsplatfid", VX_RB_CONST (4, 555, 6), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, SIMM
}},
8919 {"evsplatfia", VX_RB_CONST (4, 555, 16), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, SIMM
}},
8920 {"evsplatfioa", VX_RB_CONST (4, 555, 17), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, SIMM
}},
8921 {"evsplatfiba", VX_RB_CONST (4, 555, 18), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, SIMM
}},
8922 {"evsplatfiboa", VX_RB_CONST (4, 555, 19), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, SIMM
}},
8923 {"evsplatfiha", VX_RB_CONST (4, 555, 20), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, SIMM
}},
8924 {"evsplatfihoa", VX_RB_CONST (4, 555, 21), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, SIMM
}},
8925 {"evsplatfida", VX_RB_CONST (4, 555, 22), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, SIMM
}},
8926 {"evcmpgtdu", VX_SPE_CRFD (4, 560, 1), VX_SPE_CRFD_MASK
, PPCSPE2
, 0, {CRFD
, RA
, RB
}},
8927 {"evcmpgtds", VX_SPE_CRFD (4, 561, 1), VX_SPE_CRFD_MASK
, PPCSPE2
, 0, {CRFD
, RA
, RB
}},
8928 {"evcmpltdu", VX_SPE_CRFD (4, 562, 1), VX_SPE_CRFD_MASK
, PPCSPE2
, 0, {CRFD
, RA
, RB
}},
8929 {"evcmpltds", VX_SPE_CRFD (4, 563, 1), VX_SPE_CRFD_MASK
, PPCSPE2
, 0, {CRFD
, RA
, RB
}},
8930 {"evcmpeqd", VX_SPE_CRFD (4, 564, 1), VX_SPE_CRFD_MASK
, PPCSPE2
, 0, {CRFD
, RA
, RB
}},
8931 {"evswapbhilo", VX (4, 568), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
8932 {"evswapblohi", VX (4, 569), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
8933 {"evswaphhilo", VX (4, 570), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
8934 {"evswaphlohi", VX (4, 571), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
8935 {"evswaphe", VX (4, 572), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
8936 {"evswaphhi", VX (4, 573), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
8937 {"evswaphlo", VX (4, 574), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
8938 {"evswapho", VX (4, 575), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
8939 {"evinsb", VX (4, 584), VX_MASK_DDD
, PPCSPE2
, 0, {RD
, RA
, DDD
, BBB
}},
8940 {"evxtrb", VX (4, 586), VX_MASK_DDD
, PPCSPE2
, 0, {RD
, RA
, DDD
, BBB
}},
8941 {"evsplath", VX_SPE2_HH (4, 588, 0, 0), VX_SPE2_HH_MASK
, PPCSPE2
, 0, {RD
, RA
, HH
}},
8942 {"evsplatb", VX_SPE2_SPLATB (4, 588, 2), VX_SPE2_SPLATB_MASK
, PPCSPE2
, 0, {RD
, RA
, BBB
}},
8943 {"evinsh", VX_SPE2_DDHH (4, 589, 0), VX_SPE2_DDHH_MASK
, PPCSPE2
, 0, {RD
, RA
, DD
, HH
}},
8944 {"evclrbe", VX_SPE2_CLR (4, 590, 0), VX_SPE2_CLR_MASK
, PPCSPE2
, 0, {RD
, RA
, MMMM
}},
8945 {"evclrbo", VX_SPE2_CLR (4, 590, 1), VX_SPE2_CLR_MASK
, PPCSPE2
, 0, {RD
, RA
, MMMM
}},
8946 {"evclrh", VX_SPE2_CLR (4, 591, 1), VX_SPE2_CLR_MASK
, PPCSPE2
, 0, {RD
, RA
, MMMM
}},
8947 {"evxtrh", VX_SPE2_DDHH (4, 591, 0), VX_SPE2_DDHH_MASK
, PPCSPE2
, 0, {RD
, RA
, DD
, HH
}},
8948 {"evselbitm0", VX (4, 592), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
8949 {"evselbitm1", VX (4, 593), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
8950 {"evselbit", VX (4, 594), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
8951 {"evperm", VX (4, 596), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
8952 {"evperm2", VX (4, 597), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
8953 {"evperm3", VX (4, 598), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
8954 {"evxtrd", VX (4, 600), VX_OFF_SPE2_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
, VX_OFF_SPE2
}},
8955 {"evsrbu", VX (4, 608), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
8956 {"evsrbs", VX (4, 609), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
8957 {"evsrbiu", VX (4, 610), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, EVUIMM_LT8
}},
8958 {"evsrbis", VX (4, 611), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, EVUIMM_LT8
}},
8959 {"evslb", VX (4, 612), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
8960 {"evrlb", VX (4, 613), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
8961 {"evslbi", VX (4, 614), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, EVUIMM_LT8
}},
8962 {"evrlbi", VX (4, 615), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, EVUIMM_LT8
}},
8963 {"evsrhu", VX (4, 616), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
8964 {"evsrhs", VX (4, 617), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
8965 {"evsrhiu", VX (4, 618), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, EVUIMM_LT16
}},
8966 {"evsrhis", VX (4, 619), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, EVUIMM_LT16
}},
8967 {"evslh", VX (4, 620), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
8968 {"evrlh", VX (4, 621), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
8969 {"evslhi", VX (4, 622), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, EVUIMM_LT16
}},
8970 {"evrlhi", VX (4, 623), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, EVUIMM_LT16
}},
8971 {"evsru", VX (4, 624), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
8972 {"evsrs", VX (4, 625), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
8973 {"evsriu", VX (4, 626), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, EVUIMM
}},
8974 {"evsris", VX (4, 627), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, EVUIMM
}},
8975 {"evlvsl", VX (4, 628), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
8976 {"evlvsr", VX (4, 629), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
8977 {"evsroiu", VX_SPE2_OCTET (4, 631, 0), VX_SPE2_OCTET_MASK
, PPCSPE2
, 0, {RD
, RA
, NNN
}},
8978 {"evsrois", VX_SPE2_OCTET (4, 631, 1), VX_SPE2_OCTET_MASK
, PPCSPE2
, 0, {RD
, RA
, NNN
}},
8979 {"evsloi", VX_SPE2_OCTET (4, 631, 2), VX_SPE2_OCTET_MASK
, PPCSPE2
, 0, {RD
, RA
, NNN
}},
8980 {"evldbx", VX (4, 774), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
8981 {"evldb", VX (4, 775), VX_MASK
, PPCSPE2
, 0, {RD
, EVUIMM_8
, RA
}},
8982 {"evlhhsplathx", VX (4, 778), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
8983 {"evlhhsplath", VX (4, 779), VX_MASK
, PPCSPE2
, 0, {RD
, EVUIMM_2
, RA
}},
8984 {"evlwbsplatwx", VX (4, 786), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
8985 {"evlwbsplatw", VX (4, 787), VX_MASK
, PPCSPE2
, 0, {RD
, EVUIMM_4
, RA
}},
8986 {"evlwhsplatwx", VX (4, 794), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
8987 {"evlwhsplatw", VX (4, 795), VX_MASK
, PPCSPE2
, 0, {RD
, EVUIMM_4
, RA
}},
8988 {"evlbbsplatbx", VX (4, 798), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
8989 {"evlbbsplatb", VX (4, 799), VX_MASK
, PPCSPE2
, 0, {RD
, EVUIMM_1
, RA
}},
8990 {"evstdbx", VX (4, 806), VX_MASK
, PPCSPE2
, 0, {RS
, RA
, RB
}},
8991 {"evstdb", VX (4, 807), VX_MASK
, PPCSPE2
, 0, {RS
, EVUIMM_8
, RA
}},
8992 {"evlwbex", VX (4, 810), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
8993 {"evlwbe", VX (4, 811), VX_MASK
, PPCSPE2
, 0, {RD
, EVUIMM_4
, RA
}},
8994 {"evlwboux", VX (4, 812), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
8995 {"evlwbou", VX (4, 813), VX_MASK
, PPCSPE2
, 0, {RD
, EVUIMM_4
, RA
}},
8996 {"evlwbosx", VX (4, 814), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
8997 {"evlwbos", VX (4, 815), VX_MASK
, PPCSPE2
, 0, {RD
, EVUIMM_4
, RA
}},
8998 {"evstwbex", VX (4, 818), VX_MASK
, PPCSPE2
, 0, {RS
, RA
, RB
}},
8999 {"evstwbe", VX (4, 819), VX_MASK
, PPCSPE2
, 0, {RS
, EVUIMM_4
, RA
}},
9000 {"evstwbox", VX (4, 822), VX_MASK
, PPCSPE2
, 0, {RS
, RA
, RB
}},
9001 {"evstwbo", VX (4, 823), VX_MASK
, PPCSPE2
, 0, {RS
, EVUIMM_4
, RA
}},
9002 {"evstwbx", VX (4, 826), VX_MASK
, PPCSPE2
, 0, {RS
, RA
, RB
}},
9003 {"evstwb", VX (4, 827), VX_MASK
, PPCSPE2
, 0, {RS
, EVUIMM_4
, RA
}},
9004 {"evsthbx", VX (4, 830), VX_MASK
, PPCSPE2
, 0, {RS
, RA
, RB
}},
9005 {"evsthb", VX (4, 831), VX_MASK
, PPCSPE2
, 0, {RS
, EVUIMM_2
, RA
}},
9006 {"evlddmx", VX (4, 832), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9007 {"evlddu", VX (4, 833), VX_MASK
, PPCSPE2
, 0, {RD
, EVUIMM_8_EX0
, RA
}},
9008 {"evldwmx", VX (4, 834), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9009 {"evldwu", VX (4, 835), VX_MASK
, PPCSPE2
, 0, {RD
, EVUIMM_8_EX0
, RA
}},
9010 {"evldhmx", VX (4, 836), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9011 {"evldhu", VX (4, 837), VX_MASK
, PPCSPE2
, 0, {RD
, EVUIMM_8_EX0
, RA
}},
9012 {"evldbmx", VX (4, 838), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9013 {"evldbu", VX (4, 839), VX_MASK
, PPCSPE2
, 0, {RD
, EVUIMM_8_EX0
, RA
}},
9014 {"evlhhesplatmx", VX (4, 840), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9015 {"evlhhesplatu", VX (4, 841), VX_MASK
, PPCSPE2
, 0, {RD
, EVUIMM_2_EX0
, RA
}},
9016 {"evlhhsplathmx", VX (4, 842), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9017 {"evlhhsplathu", VX (4, 843), VX_MASK
, PPCSPE2
, 0, {RD
, EVUIMM_2_EX0
, RA
}},
9018 {"evlhhousplatmx", VX (4, 844), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9019 {"evlhhousplatu", VX (4, 845), VX_MASK
, PPCSPE2
, 0, {RD
, EVUIMM_2_EX0
, RA
}},
9020 {"evlhhossplatmx", VX (4, 846), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9021 {"evlhhossplatu", VX (4, 847), VX_MASK
, PPCSPE2
, 0, {RD
, EVUIMM_2_EX0
, RA
}},
9022 {"evlwhemx", VX (4, 848), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9023 {"evlwheu", VX (4, 849), VX_MASK
, PPCSPE2
, 0, {RD
, EVUIMM_4_EX0
, RA
}},
9024 {"evlwbsplatwmx", VX (4, 850), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9025 {"evlwbsplatwu", VX (4, 851), VX_MASK
, PPCSPE2
, 0, {RD
, EVUIMM_4_EX0
, RA
}},
9026 {"evlwhoumx", VX (4, 852), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9027 {"evlwhouu", VX (4, 853), VX_MASK
, PPCSPE2
, 0, {RD
, EVUIMM_4_EX0
, RA
}},
9028 {"evlwhosmx", VX (4, 854), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9029 {"evlwhosu", VX (4, 855), VX_MASK
, PPCSPE2
, 0, {RD
, EVUIMM_4_EX0
, RA
}},
9030 {"evlwwsplatmx", VX (4, 856), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9031 {"evlwwsplatu", VX (4, 857), VX_MASK
, PPCSPE2
, 0, {RD
, EVUIMM_4_EX0
, RA
}},
9032 {"evlwhsplatwmx", VX (4, 858), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9033 {"evlwhsplatwu", VX (4, 859), VX_MASK
, PPCSPE2
, 0, {RD
, EVUIMM_4_EX0
, RA
}},
9034 {"evlwhsplatmx", VX (4, 860), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9035 {"evlwhsplatu", VX (4, 861), VX_MASK
, PPCSPE2
, 0, {RD
, EVUIMM_4_EX0
, RA
}},
9036 {"evlbbsplatbmx", VX (4, 862), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9037 {"evlbbsplatbu", VX (4, 863), VX_MASK
, PPCSPE2
, 0, {RD
, EVUIMM_1_EX0
, RA
}},
9038 {"evstddmx", VX (4, 864), VX_MASK
, PPCSPE2
, 0, {RS
, RA
, RB
}},
9039 {"evstddu", VX (4, 865), VX_MASK
, PPCSPE2
, 0, {RS
, EVUIMM_8_EX0
, RA
}},
9040 {"evstdwmx", VX (4, 866), VX_MASK
, PPCSPE2
, 0, {RS
, RA
, RB
}},
9041 {"evstdwu", VX (4, 867), VX_MASK
, PPCSPE2
, 0, {RS
, EVUIMM_8_EX0
, RA
}},
9042 {"evstdhmx", VX (4, 868), VX_MASK
, PPCSPE2
, 0, {RS
, RA
, RB
}},
9043 {"evstdhu", VX (4, 869), VX_MASK
, PPCSPE2
, 0, {RS
, EVUIMM_8_EX0
, RA
}},
9044 {"evstdbmx", VX (4, 870), VX_MASK
, PPCSPE2
, 0, {RS
, RA
, RB
}},
9045 {"evstdbu", VX (4, 871), VX_MASK
, PPCSPE2
, 0, {RS
, EVUIMM_8_EX0
, RA
}},
9046 {"evlwbemx", VX (4, 874), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9047 {"evlwbeu", VX (4, 875), VX_MASK
, PPCSPE2
, 0, {RD
, EVUIMM_4_EX0
, RA
}},
9048 {"evlwboumx", VX (4, 876), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9049 {"evlwbouu", VX (4, 877), VX_MASK
, PPCSPE2
, 0, {RD
, EVUIMM_4_EX0
, RA
}},
9050 {"evlwbosmx", VX (4, 878), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9051 {"evlwbosu", VX (4, 879), VX_MASK
, PPCSPE2
, 0, {RD
, EVUIMM_4_EX0
, RA
}},
9052 {"evstwhemx", VX (4, 880), VX_MASK
, PPCSPE2
, 0, {RS
, RA
, RB
}},
9053 {"evstwheu", VX (4, 881), VX_MASK
, PPCSPE2
, 0, {RS
, EVUIMM_4_EX0
, RA
}},
9054 {"evstwbemx", VX (4, 882), VX_MASK
, PPCSPE2
, 0, {RS
, RA
, RB
}},
9055 {"evstwbeu", VX (4, 883), VX_MASK
, PPCSPE2
, 0, {RS
, EVUIMM_4_EX0
, RA
}},
9056 {"evstwhomx", VX (4, 884), VX_MASK
, PPCSPE2
, 0, {RS
, RA
, RB
}},
9057 {"evstwhou", VX (4, 885), VX_MASK
, PPCSPE2
, 0, {RS
, EVUIMM_4_EX0
, RA
}},
9058 {"evstwbomx", VX (4, 886), VX_MASK
, PPCSPE2
, 0, {RS
, RA
, RB
}},
9059 {"evstwbou", VX (4, 887), VX_MASK
, PPCSPE2
, 0, {RS
, EVUIMM_4_EX0
, RA
}},
9060 {"evstwwemx", VX (4, 888), VX_MASK
, PPCSPE2
, 0, {RS
, RA
, RB
}},
9061 {"evstwweu", VX (4, 889), VX_MASK
, PPCSPE2
, 0, {RS
, EVUIMM_4_EX0
, RA
}},
9062 {"evstwbmx", VX (4, 890), VX_MASK
, PPCSPE2
, 0, {RS
, RA
, RB
}},
9063 {"evstwbu", VX (4, 891), VX_MASK
, PPCSPE2
, 0, {RS
, EVUIMM_4_EX0
, RA
}},
9064 {"evstwwomx", VX (4, 892), VX_MASK
, PPCSPE2
, 0, {RS
, RA
, RB
}},
9065 {"evstwwou", VX (4, 893), VX_MASK
, PPCSPE2
, 0, {RS
, EVUIMM_4_EX0
, RA
}},
9066 {"evsthbmx", VX (4, 894), VX_MASK
, PPCSPE2
, 0, {RS
, RA
, RB
}},
9067 {"evsthbu", VX (4, 895), VX_MASK
, PPCSPE2
, 0, {RS
, EVUIMM_2_EX0
, RA
}},
9068 {"evmhusi", VX (4, 1024), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9069 {"evmhssi", VX (4, 1025), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9070 {"evmhsusi", VX (4, 1026), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9071 {"evmhssf", VX (4, 1028), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9072 {"evmhumi", VX (4, 1029), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9073 {"evmhssfr", VX (4, 1030), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9074 {"evmhesumi", VX (4, 1034), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9075 {"evmhosumi", VX (4, 1038), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9076 {"evmbeumi", VX (4, 1048), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9077 {"evmbesmi", VX (4, 1049), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9078 {"evmbesumi", VX (4, 1050), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9079 {"evmboumi", VX (4, 1052), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9080 {"evmbosmi", VX (4, 1053), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9081 {"evmbosumi", VX (4, 1054), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9082 {"evmhesumia", VX (4, 1066), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9083 {"evmhosumia", VX (4, 1070), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9084 {"evmbeumia", VX (4, 1080), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9085 {"evmbesmia", VX (4, 1081), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9086 {"evmbesumia", VX (4, 1082), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9087 {"evmboumia", VX (4, 1084), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9088 {"evmbosmia", VX (4, 1085), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9089 {"evmbosumia", VX (4, 1086), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9090 {"evmwusiw", VX (4, 1088), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9091 {"evmwssiw", VX (4, 1089), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9092 {"evmwhssfr", VX (4, 1094), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9093 {"evmwehgsmfr", VX (4, 1110), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9094 {"evmwehgsmf", VX (4, 1111), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9095 {"evmwohgsmfr", VX (4, 1118), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9096 {"evmwohgsmf", VX (4, 1119), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9097 {"evmwhssfra", VX (4, 1126), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9098 {"evmwehgsmfra", VX (4, 1142), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9099 {"evmwehgsmfa", VX (4, 1143), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9100 {"evmwohgsmfra", VX (4, 1150), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9101 {"evmwohgsmfa", VX (4, 1151), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9102 {"evaddusiaa", VX_RB_CONST(4, 1152, 0), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, RA
}},
9103 {"evaddssiaa", VX_RB_CONST(4, 1153, 0), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, RA
}},
9104 {"evsubfusiaa", VX_RB_CONST(4, 1154, 0), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, RA
}},
9105 {"evsubfssiaa", VX_RB_CONST(4, 1155, 0), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, RA
}},
9106 {"evaddsmiaa", VX_RB_CONST(4, 1156, 0), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, RA
}},
9107 {"evsubfsmiaa", VX_RB_CONST(4, 1158, 0), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, RA
}},
9108 {"evaddh", VX (4, 1160), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9109 {"evaddhss", VX (4, 1161), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9110 {"evsubfh", VX (4, 1162), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9111 {"evsubfhss", VX (4, 1163), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9112 {"evaddhx", VX (4, 1164), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9113 {"evaddhxss", VX (4, 1165), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9114 {"evsubfhx", VX (4, 1166), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9115 {"evsubfhxss", VX (4, 1167), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9116 {"evaddd", VX (4, 1168), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9117 {"evadddss", VX (4, 1169), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9118 {"evsubfd", VX (4, 1170), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9119 {"evsubfdss", VX (4, 1171), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9120 {"evaddb", VX (4, 1172), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9121 {"evaddbss", VX (4, 1173), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9122 {"evsubfb", VX (4, 1174), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9123 {"evsubfbss", VX (4, 1175), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9124 {"evaddsubfh", VX (4, 1176), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9125 {"evaddsubfhss", VX (4, 1177), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9126 {"evsubfaddh", VX (4, 1178), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9127 {"evsubfaddhss", VX (4, 1179), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9128 {"evaddsubfhx", VX (4, 1180), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9129 {"evaddsubfhxss", VX (4, 1181), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9130 {"evsubfaddhx", VX (4, 1182), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9131 {"evsubfaddhxss", VX (4, 1183), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9132 {"evadddus", VX (4, 1184), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9133 {"evaddbus", VX (4, 1185), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9134 {"evsubfdus", VX (4, 1186), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9135 {"evsubfbus", VX (4, 1187), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9136 {"evaddwus", VX (4, 1188), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9137 {"evaddwxus", VX (4, 1189), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9138 {"evsubfwus", VX (4, 1190), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9139 {"evsubfwxus", VX (4, 1191), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9140 {"evadd2subf2h", VX (4, 1192), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9141 {"evadd2subf2hss", VX (4, 1193), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9142 {"evsubf2add2h", VX (4, 1194), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9143 {"evsubf2add2hss", VX (4, 1195), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9144 {"evaddhus", VX (4, 1196), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9145 {"evaddhxus", VX (4, 1197), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9146 {"evsubfhus", VX (4, 1198), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9147 {"evsubfhxus", VX (4, 1199), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9148 {"evaddwss", VX (4, 1201), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9149 {"evsubfwss", VX (4, 1203), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9150 {"evaddwx", VX (4, 1204), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9151 {"evaddwxss", VX (4, 1205), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9152 {"evsubfwx", VX (4, 1206), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9153 {"evsubfwxss", VX (4, 1207), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9154 {"evaddsubfw", VX (4, 1208), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9155 {"evaddsubfwss", VX (4, 1209), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9156 {"evsubfaddw", VX (4, 1210), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9157 {"evsubfaddwss", VX (4, 1211), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9158 {"evaddsubfwx", VX (4, 1212), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9159 {"evaddsubfwxss", VX (4, 1213), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9160 {"evsubfaddwx", VX (4, 1214), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9161 {"evsubfaddwxss", VX (4, 1215), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9162 {"evmar", VX_SPE2_EVMAR (4, 1220), VX_SPE2_EVMAR_MASK
, PPCSPE2
, 0, {RD
}},
9163 {"evsumwu", VX_RB_CONST(4, 1221, 0), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, RA
}},
9164 {"evsumws", VX_RB_CONST(4, 1221, 1), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, RA
}},
9165 {"evsum4bu", VX_RB_CONST(4, 1221, 2), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, RA
}},
9166 {"evsum4bs", VX_RB_CONST(4, 1221, 3), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, RA
}},
9167 {"evsum2hu", VX_RB_CONST(4, 1221, 4), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, RA
}},
9168 {"evsum2hs", VX_RB_CONST(4, 1221, 5), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, RA
}},
9169 {"evdiff2his", VX_RB_CONST(4, 1221, 6), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, RA
}},
9170 {"evsum2his", VX_RB_CONST(4, 1221, 7), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, RA
}},
9171 {"evsumwua", VX_RB_CONST(4, 1221, 16), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, RA
}},
9172 {"evsumwsa", VX_RB_CONST(4, 1221, 17), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, RA
}},
9173 {"evsum4bua", VX_RB_CONST(4, 1221, 18), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, RA
}},
9174 {"evsum4bsa", VX_RB_CONST(4, 1221, 19), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, RA
}},
9175 {"evsum2hua", VX_RB_CONST(4, 1221, 20), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, RA
}},
9176 {"evsum2hsa", VX_RB_CONST(4, 1221, 21), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, RA
}},
9177 {"evdiff2hisa", VX_RB_CONST(4, 1221, 22), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, RA
}},
9178 {"evsum2hisa", VX_RB_CONST(4, 1221, 23), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, RA
}},
9179 {"evsumwuaa", VX_RB_CONST(4, 1221, 24), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, RA
}},
9180 {"evsumwsaa", VX_RB_CONST(4, 1221, 25), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, RA
}},
9181 {"evsum4buaaw", VX_RB_CONST(4, 1221, 26), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, RA
}},
9182 {"evsum4bsaaw", VX_RB_CONST(4, 1221, 27), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, RA
}},
9183 {"evsum2huaaw", VX_RB_CONST(4, 1221, 28), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, RA
}},
9184 {"evsum2hsaaw", VX_RB_CONST(4, 1221, 29), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, RA
}},
9185 {"evdiff2hisaaw", VX_RB_CONST(4, 1221, 30), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, RA
}},
9186 {"evsum2hisaaw", VX_RB_CONST(4, 1221, 31), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, RA
}},
9187 {"evdivwsf", VX (4, 1228), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9188 {"evdivwuf", VX (4, 1229), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9189 {"evdivs", VX (4, 1230), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9190 {"evdivu", VX (4, 1231), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9191 {"evaddwegsi", VX (4, 1232), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9192 {"evaddwegsf", VX (4, 1233), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9193 {"evsubfwegsi", VX (4, 1234), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9194 {"evsubfwegsf", VX (4, 1235), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9195 {"evaddwogsi", VX (4, 1236), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9196 {"evaddwogsf", VX (4, 1237), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9197 {"evsubfwogsi", VX (4, 1238), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9198 {"evsubfwogsf", VX (4, 1239), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9199 {"evaddhhiuw", VX (4, 1240), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9200 {"evaddhhisw", VX (4, 1241), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9201 {"evsubfhhiuw", VX (4, 1242), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9202 {"evsubfhhisw", VX (4, 1243), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9203 {"evaddhlouw", VX (4, 1244), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9204 {"evaddhlosw", VX (4, 1245), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9205 {"evsubfhlouw", VX (4, 1246), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9206 {"evsubfhlosw", VX (4, 1247), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9207 {"evmhesusiaaw", VX (4, 1282), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9208 {"evmhosusiaaw", VX (4, 1286), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9209 {"evmhesumiaaw", VX (4, 1290), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9210 {"evmhosumiaaw", VX (4, 1294), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9211 {"evmbeusiaah", VX (4, 1296), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9212 {"evmbessiaah", VX (4, 1297), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9213 {"evmbesusiaah", VX (4, 1298), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9214 {"evmbousiaah", VX (4, 1300), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9215 {"evmbossiaah", VX (4, 1301), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9216 {"evmbosusiaah", VX (4, 1302), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9217 {"evmbeumiaah", VX (4, 1304), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9218 {"evmbesmiaah", VX (4, 1305), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9219 {"evmbesumiaah", VX (4, 1306), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9220 {"evmboumiaah", VX (4, 1308), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9221 {"evmbosmiaah", VX (4, 1309), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9222 {"evmbosumiaah", VX (4, 1310), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9223 {"evmwlusiaaw3", VX (4, 1346), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9224 {"evmwlssiaaw3", VX (4, 1347), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9225 {"evmwhssfraaw3", VX (4, 1348), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9226 {"evmwhssfaaw3", VX (4, 1349), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9227 {"evmwhssfraaw", VX (4, 1350), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9228 {"evmwhssfaaw", VX (4, 1351), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9229 {"evmwlumiaaw3", VX (4, 1354), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9230 {"evmwlsmiaaw3", VX (4, 1355), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9231 {"evmwusiaa", VX (4, 1360), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9232 {"evmwssiaa", VX (4, 1361), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9233 {"evmwehgsmfraa", VX (4, 1366), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9234 {"evmwehgsmfaa", VX (4, 1367), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9235 {"evmwohgsmfraa", VX (4, 1374), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9236 {"evmwohgsmfaa", VX (4, 1375), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9237 {"evmhesusianw", VX (4, 1410), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9238 {"evmhosusianw", VX (4, 1414), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9239 {"evmhesumianw", VX (4, 1418), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9240 {"evmhosumianw", VX (4, 1422), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9241 {"evmbeusianh", VX (4, 1424), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9242 {"evmbessianh", VX (4, 1425), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9243 {"evmbesusianh", VX (4, 1426), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9244 {"evmbousianh", VX (4, 1428), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9245 {"evmbossianh", VX (4, 1429), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9246 {"evmbosusianh", VX (4, 1430), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9247 {"evmbeumianh", VX (4, 1432), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9248 {"evmbesmianh", VX (4, 1433), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9249 {"evmbesumianh", VX (4, 1434), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9250 {"evmboumianh", VX (4, 1436), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9251 {"evmbosmianh", VX (4, 1437), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9252 {"evmbosumianh", VX (4, 1438), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9253 {"evmwlusianw3", VX (4, 1474), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9254 {"evmwlssianw3", VX (4, 1475), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9255 {"evmwhssfranw3", VX (4, 1476), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9256 {"evmwhssfanw3", VX (4, 1477), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9257 {"evmwhssfranw", VX (4, 1478), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9258 {"evmwhssfanw", VX (4, 1479), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9259 {"evmwlumianw3", VX (4, 1482), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9260 {"evmwlsmianw3", VX (4, 1483), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9261 {"evmwusian", VX (4, 1488), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9262 {"evmwssian", VX (4, 1489), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9263 {"evmwehgsmfran", VX (4, 1494), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9264 {"evmwehgsmfan", VX (4, 1495), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9265 {"evmwohgsmfran", VX (4, 1502), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9266 {"evmwohgsmfan", VX (4, 1503), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9267 {"evseteqb", VX (4, 1536), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9268 {"evseteqb.", VX (4, 1537), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9269 {"evseteqh", VX (4, 1538), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9270 {"evseteqh.", VX (4, 1539), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9271 {"evseteqw", VX (4, 1540), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9272 {"evseteqw.", VX (4, 1541), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9273 {"evsetgthu", VX (4, 1544), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9274 {"evsetgthu.", VX (4, 1545), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9275 {"evsetgths", VX (4, 1546), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9276 {"evsetgths.", VX (4, 1547), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9277 {"evsetgtwu", VX (4, 1548), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9278 {"evsetgtwu.", VX (4, 1549), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9279 {"evsetgtws", VX (4, 1550), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9280 {"evsetgtws.", VX (4, 1551), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9281 {"evsetgtbu", VX (4, 1552), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9282 {"evsetgtbu.", VX (4, 1553), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9283 {"evsetgtbs", VX (4, 1554), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9284 {"evsetgtbs.", VX (4, 1555), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9285 {"evsetltbu", VX (4, 1556), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9286 {"evsetltbu.", VX (4, 1557), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9287 {"evsetltbs", VX (4, 1558), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9288 {"evsetltbs.", VX (4, 1559), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9289 {"evsetlthu", VX (4, 1560), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9290 {"evsetlthu.", VX (4, 1561), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9291 {"evsetlths", VX (4, 1562), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9292 {"evsetlths.", VX (4, 1563), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9293 {"evsetltwu", VX (4, 1564), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9294 {"evsetltwu.", VX (4, 1565), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9295 {"evsetltws", VX (4, 1566), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9296 {"evsetltws.", VX (4, 1567), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9297 {"evsaduw", VX (4, 1568), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9298 {"evsadsw", VX (4, 1569), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9299 {"evsad4ub", VX (4, 1570), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9300 {"evsad4sb", VX (4, 1571), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9301 {"evsad2uh", VX (4, 1572), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9302 {"evsad2sh", VX (4, 1573), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9303 {"evsaduwa", VX (4, 1576), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9304 {"evsadswa", VX (4, 1577), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9305 {"evsad4uba", VX (4, 1578), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9306 {"evsad4sba", VX (4, 1579), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9307 {"evsad2uha", VX (4, 1580), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9308 {"evsad2sha", VX (4, 1581), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9309 {"evabsdifuw", VX (4, 1584), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9310 {"evabsdifsw", VX (4, 1585), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9311 {"evabsdifub", VX (4, 1586), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9312 {"evabsdifsb", VX (4, 1587), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9313 {"evabsdifuh", VX (4, 1588), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9314 {"evabsdifsh", VX (4, 1589), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9315 {"evsaduwaa", VX (4, 1592), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9316 {"evsadswaa", VX (4, 1593), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9317 {"evsad4ubaaw", VX (4, 1594), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9318 {"evsad4sbaaw", VX (4, 1595), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9319 {"evsad2uhaaw", VX (4, 1596), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9320 {"evsad2shaaw", VX (4, 1597), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9321 {"evpkshubs", VX (4, 1600), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9322 {"evpkshsbs", VX (4, 1601), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9323 {"evpkswuhs", VX (4, 1602), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9324 {"evpkswshs", VX (4, 1603), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9325 {"evpkuhubs", VX (4, 1604), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9326 {"evpkuwuhs", VX (4, 1605), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9327 {"evpkswshilvs", VX (4, 1606), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9328 {"evpkswgshefrs", VX (4, 1607), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9329 {"evpkswshfrs", VX (4, 1608), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9330 {"evpkswshilvfrs", VX (4, 1609), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9331 {"evpksdswfrs", VX (4, 1610), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9332 {"evpksdshefrs", VX (4, 1611), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9333 {"evpkuduws", VX (4, 1612), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9334 {"evpksdsws", VX (4, 1613), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9335 {"evpkswgswfrs", VX (4, 1614), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9336 {"evilveh", VX (4, 1616), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9337 {"evilveoh", VX (4, 1617), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9338 {"evilvhih", VX (4, 1618), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9339 {"evilvhiloh", VX (4, 1619), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9340 {"evilvloh", VX (4, 1620), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9341 {"evilvlohih", VX (4, 1621), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9342 {"evilvoeh", VX (4, 1622), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9343 {"evilvoh", VX (4, 1623), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9344 {"evdlveb", VX (4, 1624), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9345 {"evdlveh", VX (4, 1625), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9346 {"evdlveob", VX (4, 1626), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9347 {"evdlveoh", VX (4, 1627), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9348 {"evdlvob", VX (4, 1628), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9349 {"evdlvoh", VX (4, 1629), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9350 {"evdlvoeb", VX (4, 1630), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9351 {"evdlvoeh", VX (4, 1631), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9352 {"evmaxbu", VX (4, 1632), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9353 {"evmaxbs", VX (4, 1633), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9354 {"evmaxhu", VX (4, 1634), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9355 {"evmaxhs", VX (4, 1635), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9356 {"evmaxwu", VX (4, 1636), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9357 {"evmaxws", VX (4, 1637), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9358 {"evmaxdu", VX (4, 1638), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9359 {"evmaxds", VX (4, 1639), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9360 {"evminbu", VX (4, 1640), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9361 {"evminbs", VX (4, 1641), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9362 {"evminhu", VX (4, 1642), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9363 {"evminhs", VX (4, 1643), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9364 {"evminwu", VX (4, 1644), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9365 {"evminws", VX (4, 1645), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9366 {"evmindu", VX (4, 1646), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9367 {"evminds", VX (4, 1647), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9368 {"evavgwu", VX (4, 1648), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9369 {"evavgws", VX (4, 1649), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9370 {"evavgbu", VX (4, 1650), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9371 {"evavgbs", VX (4, 1651), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9372 {"evavghu", VX (4, 1652), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9373 {"evavghs", VX (4, 1653), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9374 {"evavgdu", VX (4, 1654), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9375 {"evavgds", VX (4, 1655), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9376 {"evavgwur", VX (4, 1656), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9377 {"evavgwsr", VX (4, 1657), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9378 {"evavgbur", VX (4, 1658), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9379 {"evavgbsr", VX (4, 1659), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9380 {"evavghur", VX (4, 1660), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9381 {"evavghsr", VX (4, 1661), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9382 {"evavgdur", VX (4, 1662), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9383 {"evavgdsr", VX (4, 1663), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9386 const unsigned int spe2_num_opcodes
=
9387 sizeof (spe2_opcodes
) / sizeof (spe2_opcodes
[0]);