1 /* ppc-opc.c -- PowerPC opcode list
2 Copyright (C) 1994-2020 Free Software Foundation, Inc.
3 Written by Ian Lance Taylor, Cygnus Support
5 This file is part of the GNU opcodes library.
7 This library is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3, or (at your option)
12 It is distributed in the hope that it will be useful, but WITHOUT
13 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
14 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
15 License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this file; see the file COPYING. If not, write to the
19 Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston,
20 MA 02110-1301, USA. */
24 #include "opcode/ppc.h"
27 /* This file holds the PowerPC opcode table. The opcode table
28 includes almost all of the extended instruction mnemonics. This
29 permits the disassembler to use them, and simplifies the assembler
30 logic, at the cost of increasing the table size. The table is
31 strictly constant data, so the compiler should be able to put it in
34 This file also holds the operand table. All knowledge about
35 inserting operands into instructions and vice-versa is kept in this
38 /* The functions used to insert and extract complicated operands. */
40 /* The ARX, ARY, RX and RY operands are alternate encodings of GPRs. */
43 insert_arx (uint64_t insn
,
45 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
46 const char **errmsg ATTRIBUTE_UNUSED
)
49 if (value
< 0 || value
>= 16)
51 *errmsg
= _("invalid register");
58 extract_arx (uint64_t insn
,
59 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
60 int *invalid ATTRIBUTE_UNUSED
)
62 return (insn
& 0xf) + 8;
66 insert_ary (uint64_t insn
,
68 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
69 const char **errmsg ATTRIBUTE_UNUSED
)
72 if (value
< 0 || value
>= 16)
74 *errmsg
= _("invalid register");
77 return insn
| (value
<< 4);
81 extract_ary (uint64_t insn
,
82 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
83 int *invalid ATTRIBUTE_UNUSED
)
85 return ((insn
>> 4) & 0xf) + 8;
89 insert_rx (uint64_t insn
,
91 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
94 if (value
>= 0 && value
< 8)
96 else if (value
>= 24 && value
<= 31)
100 *errmsg
= _("invalid register");
107 extract_rx (uint64_t insn
,
108 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
109 int *invalid ATTRIBUTE_UNUSED
)
111 int64_t value
= insn
& 0xf;
112 if (value
>= 0 && value
< 8)
119 insert_ry (uint64_t insn
,
121 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
124 if (value
>= 0 && value
< 8)
126 else if (value
>= 24 && value
<= 31)
130 *errmsg
= _("invalid register");
133 return insn
| (value
<< 4);
137 extract_ry (uint64_t insn
,
138 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
139 int *invalid ATTRIBUTE_UNUSED
)
141 int64_t value
= (insn
>> 4) & 0xf;
142 if (value
>= 0 && value
< 8)
148 /* The BA and BB fields in an XL form instruction or the RA and RB fields or
149 VRA and VRB fields in a VX form instruction when they must be the same.
150 This is used for extended mnemonics like crclr. The extraction function
151 enforces that the fields are the same. */
154 insert_bab (uint64_t insn
,
156 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
157 const char **errmsg ATTRIBUTE_UNUSED
)
160 return insn
| (value
<< 16) | (value
<< 11);
164 extract_bab (uint64_t insn
,
165 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
168 int64_t ba
= (insn
>> 16) & 0x1f;
169 int64_t bb
= (insn
>> 11) & 0x1f;
176 /* The BT, BA and BB fields in an XL form instruction when they must all be
177 the same. This is used for extended mnemonics like crclr. The extraction
178 function enforces that the fields are the same. */
181 insert_btab (uint64_t insn
,
187 return (value
<< 21) | insert_bab (insn
, value
, dialect
, errmsg
);
191 extract_btab (uint64_t insn
,
195 int64_t bt
= (insn
>> 21) & 0x1f;
196 int64_t bab
= extract_bab (insn
, dialect
, invalid
);
203 /* The BD field in a B form instruction when the - modifier is used.
204 This modifier means that the branch is not expected to be taken.
205 For chips built to versions of the architecture prior to version 2
206 (ie. not Power4 compatible), we set the y bit of the BO field to 1
207 if the offset is negative. When extracting, we require that the y
208 bit be 1 and that the offset be positive, since if the y bit is 0
209 we just want to print the normal form of the instruction.
210 Power4 compatible targets use two bits, "a", and "t", instead of
211 the "y" bit. "at" == 00 => no hint, "at" == 01 => unpredictable,
212 "at" == 10 => not taken, "at" == 11 => taken. The "t" bit is 00001
213 in BO field, the "a" bit is 00010 for branch on CR(BI) and 01000
214 for branch on CTR. We only handle the taken/not-taken hint here.
215 Note that we don't relax the conditions tested here when
216 disassembling with -Many because insns using extract_bdm and
217 extract_bdp always occur in pairs. One or the other will always
220 #define ISA_V2 (PPC_OPCODE_POWER4 | PPC_OPCODE_E500MC | PPC_OPCODE_TITAN)
223 insert_bdm (uint64_t insn
,
226 const char **errmsg ATTRIBUTE_UNUSED
)
228 if ((dialect
& ISA_V2
) == 0)
230 if ((value
& 0x8000) != 0)
235 if ((insn
& (0x14 << 21)) == (0x04 << 21))
237 else if ((insn
& (0x14 << 21)) == (0x10 << 21))
240 return insn
| (value
& 0xfffc);
244 extract_bdm (uint64_t insn
,
248 if ((dialect
& ISA_V2
) == 0)
250 if (((insn
& (1 << 21)) == 0) != ((insn
& (1 << 15)) == 0))
255 if ((insn
& (0x17 << 21)) != (0x06 << 21)
256 && (insn
& (0x1d << 21)) != (0x18 << 21))
260 return ((insn
& 0xfffc) ^ 0x8000) - 0x8000;
263 /* The BD field in a B form instruction when the + modifier is used.
264 This is like BDM, above, except that the branch is expected to be
268 insert_bdp (uint64_t insn
,
271 const char **errmsg ATTRIBUTE_UNUSED
)
273 if ((dialect
& ISA_V2
) == 0)
275 if ((value
& 0x8000) == 0)
280 if ((insn
& (0x14 << 21)) == (0x04 << 21))
282 else if ((insn
& (0x14 << 21)) == (0x10 << 21))
285 return insn
| (value
& 0xfffc);
289 extract_bdp (uint64_t insn
,
293 if ((dialect
& ISA_V2
) == 0)
295 if (((insn
& (1 << 21)) == 0) == ((insn
& (1 << 15)) == 0))
300 if ((insn
& (0x17 << 21)) != (0x07 << 21)
301 && (insn
& (0x1d << 21)) != (0x19 << 21))
305 return ((insn
& 0xfffc) ^ 0x8000) - 0x8000;
309 valid_bo_pre_v2 (int64_t value
)
311 /* Certain encodings have bits that are required to be zero.
312 These are (z must be zero, y may be anything):
323 if ((value
& 0x14) == 0)
324 /* BO: 0000y, 0001y, 0100y, 0101y. */
326 else if ((value
& 0x14) == 0x4)
327 /* BO: 001zy, 011zy. */
328 return (value
& 0x2) == 0;
329 else if ((value
& 0x14) == 0x10)
330 /* BO: 1z00y, 1z01y. */
331 return (value
& 0x8) == 0;
334 return value
== 0x14;
338 valid_bo_post_v2 (int64_t value
)
340 /* Certain encodings have bits that are required to be zero.
341 These are (z must be zero, a & t may be anything):
352 if ((value
& 0x14) == 0)
353 /* BO: 0000z, 0001z, 0100z, 0101z. */
354 return (value
& 0x1) == 0;
355 else if ((value
& 0x14) == 0x14)
357 return value
== 0x14;
358 else if ((value
& 0x14) == 0x4)
359 /* BO: 001at, 011at, with "at" == 0b01 being reserved. */
360 return (value
& 0x3) != 1;
361 else if ((value
& 0x14) == 0x10)
362 /* BO: 1a00t, 1a01t, with "at" == 0b01 being reserved. */
363 return (value
& 0x9) != 1;
368 /* Check for legal values of a BO field. */
371 valid_bo (int64_t value
, ppc_cpu_t dialect
, int extract
)
373 int valid_y
= valid_bo_pre_v2 (value
);
374 int valid_at
= valid_bo_post_v2 (value
);
376 /* When disassembling with -Many, accept either encoding on the
377 second pass through opcodes. */
378 if (extract
&& dialect
== ~(ppc_cpu_t
) PPC_OPCODE_ANY
)
379 return valid_y
|| valid_at
;
380 if ((dialect
& ISA_V2
) == 0)
386 /* The BO field in a B form instruction. Warn about attempts to set
387 the field to an illegal value. */
390 insert_bo (uint64_t insn
,
395 if (!valid_bo (value
, dialect
, 0))
396 *errmsg
= _("invalid conditional option");
397 else if (PPC_OP (insn
) == 19
398 && (((insn
>> 1) & 0x3ff) == 528) && ! (value
& 4))
399 *errmsg
= _("invalid counter access");
400 return insn
| ((value
& 0x1f) << 21);
404 extract_bo (uint64_t insn
,
408 int64_t value
= (insn
>> 21) & 0x1f;
409 if (!valid_bo (value
, dialect
, 1))
414 /* For the given BO value, return a bit mask detailing which bits
415 define the branch hints. */
418 get_bo_hint_mask (int64_t bo
, ppc_cpu_t dialect
)
420 if ((dialect
& ISA_V2
) == 0)
422 if ((bo
& 0x14) != 0x14)
423 /* BO: 0000y, 0001y, 001zy, 0100y, 0101y, 011zy, 1z00y, 1z01y . */
431 if ((bo
& 0x14) == 0x4)
432 /* BO: 001at, 011at. */
434 else if ((bo
& 0x14) == 0x10)
435 /* BO: 1a00t, 1a01t. */
438 /* BO: 0000z, 0001z, 0100z, 0101z, 1z1zz. */
443 /* The BO field in a B form instruction when the + or - modifier is used. */
446 insert_boe (uint64_t insn
,
452 int64_t implied_hint
;
453 int64_t hint_mask
= get_bo_hint_mask (value
, dialect
);
456 implied_hint
= hint_mask
;
458 implied_hint
= hint_mask
& ~1;
460 /* The branch hint bit(s) in the BO field must either be zero or exactly
461 match the branch hint bits implied by the '+' or '-' modifier. */
462 if (implied_hint
== 0)
463 *errmsg
= _("BO value implies no branch hint, when using + or - modifier");
464 else if ((value
& hint_mask
) != 0
465 && (value
& hint_mask
) != implied_hint
)
467 if ((dialect
& ISA_V2
) == 0)
468 *errmsg
= _("attempt to set y bit when using + or - modifier");
470 *errmsg
= _("attempt to set 'at' bits when using + or - modifier");
473 value
|= implied_hint
;
475 return insert_bo (insn
, value
, dialect
, errmsg
);
479 extract_boe (uint64_t insn
,
484 int64_t value
= (insn
>> 21) & 0x1f;
485 int64_t implied_hint
;
486 int64_t hint_mask
= get_bo_hint_mask (value
, dialect
);
489 implied_hint
= hint_mask
;
491 implied_hint
= hint_mask
& ~1;
493 if (!valid_bo (value
, dialect
, 1)
495 || (value
& hint_mask
) != implied_hint
)
500 /* The BO field in a B form instruction when the - modifier is used. */
503 insert_bom (uint64_t insn
,
508 return insert_boe (insn
, value
, dialect
, errmsg
, 0);
512 extract_bom (uint64_t insn
,
516 return extract_boe (insn
, dialect
, invalid
, 0);
519 /* The BO field in a B form instruction when the + modifier is used. */
522 insert_bop (uint64_t insn
,
527 return insert_boe (insn
, value
, dialect
, errmsg
, 1);
531 extract_bop (uint64_t insn
,
535 return extract_boe (insn
, dialect
, invalid
, 1);
538 /* The DCMX field in a X form instruction when the field is split
539 into separate DC, DM and DX fields. */
542 insert_dcmxs (uint64_t insn
,
544 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
545 const char **errmsg ATTRIBUTE_UNUSED
)
548 | ((value
& 0x1f) << 16)
549 | ((value
& 0x20) >> 3)
554 extract_dcmxs (uint64_t insn
,
555 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
556 int *invalid ATTRIBUTE_UNUSED
)
558 return (insn
& 0x40) | ((insn
<< 3) & 0x20) | ((insn
>> 16) & 0x1f);
561 /* The D field in a DX form instruction when the field is split
562 into separate D0, D1 and D2 fields. */
565 insert_dxd (uint64_t insn
,
567 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
568 const char **errmsg ATTRIBUTE_UNUSED
)
570 return insn
| (value
& 0xffc1) | ((value
& 0x3e) << 15);
574 extract_dxd (uint64_t insn
,
575 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
576 int *invalid ATTRIBUTE_UNUSED
)
578 uint64_t dxd
= (insn
& 0xffc1) | ((insn
>> 15) & 0x3e);
579 return (dxd
^ 0x8000) - 0x8000;
583 insert_dxdn (uint64_t insn
,
585 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
586 const char **errmsg ATTRIBUTE_UNUSED
)
588 return insert_dxd (insn
, -value
, dialect
, errmsg
);
592 extract_dxdn (uint64_t insn
,
593 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
596 return -extract_dxd (insn
, dialect
, invalid
);
599 /* The D field in a 64-bit D form prefix instruction when the field is split
600 into separate D0 and D1 fields. */
603 insert_d34 (uint64_t insn
,
605 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
606 const char **errmsg ATTRIBUTE_UNUSED
)
608 return insn
| ((value
& 0x3ffff0000ULL
) << 16) | (value
& 0xffff);
612 extract_d34 (uint64_t insn
,
613 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
614 int *invalid ATTRIBUTE_UNUSED
)
616 int64_t mask
= 1ULL << 33;
617 int64_t value
= ((insn
>> 16) & 0x3ffff0000ULL
) | (insn
& 0xffff);
618 value
= (value
^ mask
) - mask
;
622 /* The NSI34 field in an 8-byte D form prefix instruction. This is the same
623 as the SI34 field, only negated. The extraction function always marks it
624 as invalid, since we never want to recognize an instruction which uses
625 a field of this type. */
628 insert_nsi34 (uint64_t insn
,
633 return insert_d34 (insn
, -value
, dialect
, errmsg
);
637 extract_nsi34 (uint64_t insn
,
641 int64_t value
= extract_d34 (insn
, dialect
, invalid
);
646 /* The split IMM32 field in a vector splat insn. */
649 insert_imm32 (uint64_t insn
,
651 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
652 const char **errmsg ATTRIBUTE_UNUSED
)
654 return insn
| ((value
& 0xffff0000) << 16) | (value
& 0xffff);
658 extract_imm32 (uint64_t insn
,
659 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
660 int *invalid ATTRIBUTE_UNUSED
)
662 return (insn
& 0xffff) | ((insn
>> 16) & 0xffff0000);
665 /* The R field in an 8-byte prefix instruction when there are restrictions
666 between R's value and the RA value (ie, they cannot both be non zero). */
669 insert_pcrel (uint64_t insn
,
671 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
675 int64_t ra
= (insn
>> 16) & 0x1f;
676 if (ra
!= 0 && value
!= 0)
677 *errmsg
= _("invalid R operand");
679 return insn
| (value
<< 52);
683 extract_pcrel (uint64_t insn
,
684 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
687 /* If called with *invalid < 0 to return the value for missing
688 operands, *invalid will be the negative count of missing operands
689 including this one. Return a default value of 1 if the PRA0/PRAQ
690 operand was also omitted (ie. *invalid is -2). Return a default
691 value of 0 if the PRA0/PRAQ operand was not omitted
692 (ie. *invalid is -1). */
694 return ~ *invalid
& 1;
696 int64_t ra
= (insn
>> 16) & 0x1f;
697 int64_t pcrel
= (insn
>> 52) & 0x1;
698 if (ra
!= 0 && pcrel
!= 0)
704 /* Variant of extract_pcrel that sets invalid for R bit set. The idea
705 is to disassemble "paddi rt,0,offset,1" as "pla rt,offset". */
708 extract_pcrel0 (uint64_t insn
,
712 int64_t pcrel
= extract_pcrel (insn
, dialect
, invalid
);
718 /* FXM mask in mfcr and mtcrf instructions. */
721 insert_fxm (uint64_t insn
,
726 /* If we're handling the mfocrf and mtocrf insns ensure that exactly
727 one bit of the mask field is set. */
728 if ((insn
& (1 << 20)) != 0)
730 if (value
== 0 || (value
& -value
) != value
)
732 *errmsg
= _("invalid mask field");
737 /* If only one bit of the FXM field is set, we can use the new form
738 of the instruction, which is faster. Unlike the Power4 branch hint
739 encoding, this is not backward compatible. Do not generate the
740 new form unless -mpower4 has been given, or -many and the two
741 operand form of mfcr was used. */
743 && (value
& -value
) == value
744 && ((dialect
& PPC_OPCODE_POWER4
) != 0
745 || ((dialect
& PPC_OPCODE_ANY
) != 0
746 && (insn
& (0x3ff << 1)) == 19 << 1)))
749 /* Any other value on mfcr is an error. */
750 else if ((insn
& (0x3ff << 1)) == 19 << 1)
752 /* A value of -1 means we used the one operand form of
753 mfcr which is valid. */
755 *errmsg
= _("invalid mfcr mask");
759 return insn
| ((value
& 0xff) << 12);
763 extract_fxm (uint64_t insn
,
764 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
767 /* Return a value of -1 for a missing optional operand, which is
768 used as a flag by insert_fxm. */
772 int64_t mask
= (insn
>> 12) & 0xff;
773 /* Is this a Power4 insn? */
774 if ((insn
& (1 << 20)) != 0)
776 /* Exactly one bit of MASK should be set. */
777 if (mask
== 0 || (mask
& -mask
) != mask
)
781 /* Check that non-power4 form of mfcr has a zero MASK. */
782 else if ((insn
& (0x3ff << 1)) == 19 << 1)
793 /* L field in the paste. instruction. */
796 insert_l1opt (uint64_t insn
,
798 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
799 const char **errmsg ATTRIBUTE_UNUSED
)
801 return insn
| ((value
& 1) << 21);
805 extract_l1opt (uint64_t insn
,
806 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
809 /* Return a value of 1 for a missing optional operand. */
813 return (insn
>> 21) & 1;
817 insert_li20 (uint64_t insn
,
819 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
820 const char **errmsg ATTRIBUTE_UNUSED
)
823 | ((value
& 0xf0000) >> 5)
824 | ((value
& 0x0f800) << 5)
829 extract_li20 (uint64_t insn
,
830 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
831 int *invalid ATTRIBUTE_UNUSED
)
833 return ((((insn
<< 5) & 0xf0000)
834 | ((insn
>> 5) & 0xf800)
835 | (insn
& 0x7ff)) ^ 0x80000) - 0x80000;
838 /* The 2-bit L field in a SYNC or WC field in a WAIT instruction.
839 For SYNC, some L values are reserved:
840 * Value 3 is reserved on newer server cpus.
841 * Values 2 and 3 are reserved on all other cpus. */
844 insert_ls (uint64_t insn
,
849 /* For SYNC, some L values are illegal. */
850 if (((insn
>> 1) & 0x3ff) == 598)
852 int64_t max_lvalue
= (dialect
& PPC_OPCODE_POWER4
) ? 2 : 1;
853 if (value
> max_lvalue
)
854 *errmsg
= _("illegal L operand value");
857 return insn
| ((value
& 0x3) << 21);
861 extract_ls (uint64_t insn
,
865 /* Missing optional operands have a value of zero. */
869 uint64_t lvalue
= (insn
>> 21) & 3;
870 if (((insn
>> 1) & 0x3ff) == 598)
872 uint64_t max_lvalue
= (dialect
& PPC_OPCODE_POWER4
) ? 2 : 1;
873 if (lvalue
> max_lvalue
)
879 /* The 4-bit E field in a sync instruction that accepts 2 operands.
880 If ESYNC is non-zero, then the L field must be either 0 or 1 and
881 the complement of ESYNC-bit2. */
884 insert_esync (uint64_t insn
,
886 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
889 uint64_t ls
= (insn
>> 21) & 0x03;
892 && ((~value
>> 1) & 0x1) != ls
)
893 *errmsg
= _("incompatible L operand value");
895 return insn
| ((value
& 0xf) << 16);
899 extract_esync (uint64_t insn
,
900 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
903 /* Missing optional operands have a value of zero. */
907 uint64_t ls
= (insn
>> 21) & 0x3;
908 uint64_t value
= (insn
>> 16) & 0xf;
910 && ((~value
>> 1) & 0x1) != ls
)
915 /* The MB and ME fields in an M form instruction expressed as a single
916 operand which is itself a bitmask. The extraction function always
917 marks it as invalid, since we never want to recognize an
918 instruction which uses a field of this type. */
921 insert_mbe (uint64_t insn
,
923 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
927 long mb
, me
, mx
, count
, last
;
933 *errmsg
= _("illegal bitmask");
945 /* mb: location of last 0->1 transition */
946 /* me: location of last 1->0 transition */
947 /* count: # transitions */
949 for (mx
= 0, mask
= (uint64_t) 1 << 31; mx
< 32; ++mx
, mask
>>= 1)
951 if ((uval
& mask
) && !last
)
957 else if (!(uval
& mask
) && last
)
967 if (count
!= 2 && (count
!= 0 || ! last
))
968 *errmsg
= _("illegal bitmask");
970 return insn
| (mb
<< 6) | ((me
- 1) << 1);
974 extract_mbe (uint64_t insn
,
975 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
984 mb
= (insn
>> 6) & 0x1f;
985 me
= (insn
>> 1) & 0x1f;
989 for (i
= mb
; i
<= me
; i
++)
990 ret
|= (uint64_t) 1 << (31 - i
);
992 else if (mb
== me
+ 1)
994 else /* (mb > me + 1) */
997 for (i
= me
+ 1; i
< mb
; i
++)
998 ret
&= ~((uint64_t) 1 << (31 - i
));
1003 /* The MB or ME field in an MD or MDS form instruction. The high bit
1004 is wrapped to the low end. */
1007 insert_mb6 (uint64_t insn
,
1009 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1010 const char **errmsg ATTRIBUTE_UNUSED
)
1012 return insn
| ((value
& 0x1f) << 6) | (value
& 0x20);
1016 extract_mb6 (uint64_t insn
,
1017 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1018 int *invalid ATTRIBUTE_UNUSED
)
1020 return ((insn
>> 6) & 0x1f) | (insn
& 0x20);
1023 /* The NB field in an X form instruction. The value 32 is stored as
1027 extract_nb (uint64_t insn
,
1028 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1029 int *invalid ATTRIBUTE_UNUSED
)
1033 ret
= (insn
>> 11) & 0x1f;
1039 /* The NB field in an lswi instruction, which has special value
1040 restrictions. The value 32 is stored as 0. */
1043 insert_nbi (uint64_t insn
,
1045 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1046 const char **errmsg ATTRIBUTE_UNUSED
)
1048 int64_t rtvalue
= (insn
>> 21) & 0x1f;
1049 int64_t ravalue
= (insn
>> 16) & 0x1f;
1053 if (rtvalue
+ (value
+ 3) / 4 > (rtvalue
> ravalue
? ravalue
+ 32
1055 *errmsg
= _("address register in load range");
1056 return insn
| ((value
& 0x1f) << 11);
1059 /* The NSI field in a D form instruction. This is the same as the SI
1060 field, only negated. The extraction function always marks it as
1061 invalid, since we never want to recognize an instruction which uses
1062 a field of this type. */
1065 insert_nsi (uint64_t insn
,
1067 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1068 const char **errmsg ATTRIBUTE_UNUSED
)
1070 return insn
| (-value
& 0xffff);
1074 extract_nsi (uint64_t insn
,
1075 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1079 return -(((insn
& 0xffff) ^ 0x8000) - 0x8000);
1082 /* The RA field in a D or X form instruction which is an updating
1083 load, which means that the RA field may not be zero and may not
1084 equal the RT field. */
1087 insert_ral (uint64_t insn
,
1089 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1090 const char **errmsg
)
1093 || (uint64_t) value
== ((insn
>> 21) & 0x1f))
1094 *errmsg
= "invalid register operand when updating";
1095 return insn
| ((value
& 0x1f) << 16);
1099 extract_ral (uint64_t insn
,
1100 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1103 int64_t rtvalue
= (insn
>> 21) & 0x1f;
1104 int64_t ravalue
= (insn
>> 16) & 0x1f;
1106 if (rtvalue
== ravalue
|| ravalue
== 0)
1111 /* The RA field in an lmw instruction, which has special value
1115 insert_ram (uint64_t insn
,
1117 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1118 const char **errmsg
)
1120 if ((uint64_t) value
>= ((insn
>> 21) & 0x1f))
1121 *errmsg
= _("index register in load range");
1122 return insn
| ((value
& 0x1f) << 16);
1126 extract_ram (uint64_t insn
,
1127 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1130 uint64_t rtvalue
= (insn
>> 21) & 0x1f;
1131 uint64_t ravalue
= (insn
>> 16) & 0x1f;
1133 if (ravalue
>= rtvalue
)
1138 /* The RA field in the DQ form lq or an lswx instruction, which have special
1139 value restrictions. */
1142 insert_raq (uint64_t insn
,
1144 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1145 const char **errmsg
)
1147 int64_t rtvalue
= (insn
>> 21) & 0x1f;
1149 if (value
== rtvalue
)
1150 *errmsg
= _("source and target register operands must be different");
1151 return insn
| ((value
& 0x1f) << 16);
1155 extract_raq (uint64_t insn
,
1156 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1159 /* Missing optional operands have a value of zero. */
1163 uint64_t rtvalue
= (insn
>> 21) & 0x1f;
1164 uint64_t ravalue
= (insn
>> 16) & 0x1f;
1165 if (ravalue
== rtvalue
)
1170 /* The RA field in a D or X form instruction which is an updating
1171 store or an updating floating point load, which means that the RA
1172 field may not be zero. */
1175 insert_ras (uint64_t insn
,
1177 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1178 const char **errmsg
)
1181 *errmsg
= _("invalid register operand when updating");
1182 return insn
| ((value
& 0x1f) << 16);
1186 extract_ras (uint64_t insn
,
1187 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1190 uint64_t ravalue
= (insn
>> 16) & 0x1f;
1197 /* The RS and RB fields in an X form instruction when they must be the same.
1198 This is used for extended mnemonics like mr. The extraction function
1199 enforces that the fields are the same. */
1202 insert_rsb (uint64_t insn
,
1204 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1205 const char **errmsg ATTRIBUTE_UNUSED
)
1208 return insn
| (value
<< 21) | (value
<< 11);
1212 extract_rsb (uint64_t insn
,
1213 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1216 int64_t rs
= (insn
>> 21) & 0x1f;
1217 int64_t rb
= (insn
>> 11) & 0x1f;
1224 /* The RB field in an lswx instruction, which has special value
1228 insert_rbx (uint64_t insn
,
1230 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1231 const char **errmsg
)
1233 int64_t rtvalue
= (insn
>> 21) & 0x1f;
1235 if (value
== rtvalue
)
1236 *errmsg
= _("source and target register operands must be different");
1237 return insn
| ((value
& 0x1f) << 11);
1241 extract_rbx (uint64_t insn
,
1242 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1245 uint64_t rtvalue
= (insn
>> 21) & 0x1f;
1246 uint64_t rbvalue
= (insn
>> 11) & 0x1f;
1248 if (rbvalue
== rtvalue
)
1253 /* The SCI8 field is made up of SCL and {U,N}I8 fields. */
1255 insert_sci8 (uint64_t insn
,
1257 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1258 const char **errmsg
)
1260 uint64_t fill_scale
= 0;
1261 uint64_t ui8
= value
;
1263 if ((ui8
& 0xffffff00) == 0)
1265 else if ((ui8
& 0xffffff00) == 0xffffff00)
1267 else if ((ui8
& 0xffff00ff) == 0)
1269 fill_scale
= 1 << 8;
1272 else if ((ui8
& 0xffff00ff) == 0xffff00ff)
1274 fill_scale
= 0x400 | (1 << 8);
1277 else if ((ui8
& 0xff00ffff) == 0)
1279 fill_scale
= 2 << 8;
1282 else if ((ui8
& 0xff00ffff) == 0xff00ffff)
1284 fill_scale
= 0x400 | (2 << 8);
1287 else if ((ui8
& 0x00ffffff) == 0)
1289 fill_scale
= 3 << 8;
1292 else if ((ui8
& 0x00ffffff) == 0x00ffffff)
1294 fill_scale
= 0x400 | (3 << 8);
1299 *errmsg
= _("illegal immediate value");
1303 return insn
| fill_scale
| (ui8
& 0xff);
1307 extract_sci8 (uint64_t insn
,
1308 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1309 int *invalid ATTRIBUTE_UNUSED
)
1311 int64_t fill
= insn
& 0x400;
1312 int64_t scale_factor
= (insn
& 0x300) >> 5;
1313 int64_t value
= (insn
& 0xff) << scale_factor
;
1316 value
|= ~((int64_t) 0xff << scale_factor
);
1321 insert_sci8n (uint64_t insn
,
1324 const char **errmsg
)
1326 return insert_sci8 (insn
, -value
, dialect
, errmsg
);
1330 extract_sci8n (uint64_t insn
,
1334 return -extract_sci8 (insn
, dialect
, invalid
);
1338 insert_oimm (uint64_t insn
,
1340 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1341 const char **errmsg ATTRIBUTE_UNUSED
)
1343 return insn
| (((value
- 1) & 0x1f) << 4);
1347 extract_oimm (uint64_t insn
,
1348 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1349 int *invalid ATTRIBUTE_UNUSED
)
1351 return ((insn
>> 4) & 0x1f) + 1;
1354 /* The SH field in an MD form instruction. This is split. */
1357 insert_sh6 (uint64_t insn
,
1359 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1360 const char **errmsg ATTRIBUTE_UNUSED
)
1362 return insn
| ((value
& 0x1f) << 11) | ((value
& 0x20) >> 4);
1366 extract_sh6 (uint64_t insn
,
1367 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1368 int *invalid ATTRIBUTE_UNUSED
)
1370 return ((insn
>> 11) & 0x1f) | ((insn
<< 4) & 0x20);
1373 /* The SPR field in an XFX form instruction. This is flipped--the
1374 lower 5 bits are stored in the upper 5 and vice- versa. */
1377 insert_spr (uint64_t insn
,
1379 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1380 const char **errmsg ATTRIBUTE_UNUSED
)
1382 return insn
| ((value
& 0x1f) << 16) | ((value
& 0x3e0) << 6);
1386 extract_spr (uint64_t insn
,
1387 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1388 int *invalid ATTRIBUTE_UNUSED
)
1390 return ((insn
>> 16) & 0x1f) | ((insn
>> 6) & 0x3e0);
1393 /* Some dialects have 8 [DI]BAT registers instead of the standard 4. */
1394 #define ALLOW8_BAT (PPC_OPCODE_750)
1397 insert_sprbat (uint64_t insn
,
1400 const char **errmsg
)
1402 if ((uint64_t) value
> 7
1403 || ((uint64_t) value
> 3 && (dialect
& ALLOW8_BAT
) == 0))
1404 *errmsg
= _("invalid bat number");
1406 /* If this is [di]bat4..7 then use spr 560..575, otherwise 528..543. */
1407 if ((uint64_t) value
> 3)
1408 value
= ((value
& 3) << 6) | 1;
1412 return insn
| (value
<< 11);
1416 extract_sprbat (uint64_t insn
,
1420 uint64_t val
= (insn
>> 17) & 0x3;
1422 val
= val
+ ((insn
>> 9) & 0x4);
1423 if (val
> 3 && (dialect
& ALLOW8_BAT
) == 0)
1428 /* Some dialects have 8 SPRG registers instead of the standard 4. */
1429 #define ALLOW8_SPRG (PPC_OPCODE_BOOKE | PPC_OPCODE_405)
1432 insert_sprg (uint64_t insn
,
1435 const char **errmsg
)
1437 if ((uint64_t) value
> 7
1438 || ((uint64_t) value
> 3 && (dialect
& ALLOW8_SPRG
) == 0))
1439 *errmsg
= _("invalid sprg number");
1441 /* If this is mfsprg4..7 then use spr 260..263 which can be read in
1442 user mode. Anything else must use spr 272..279. */
1443 if ((uint64_t) value
<= 3 || (insn
& 0x100) != 0)
1446 return insn
| ((value
& 0x17) << 16);
1450 extract_sprg (uint64_t insn
,
1454 uint64_t val
= (insn
>> 16) & 0x1f;
1456 /* mfsprg can use 260..263 and 272..279. mtsprg only uses spr 272..279
1457 If not BOOKE, 405 or VLE, then both use only 272..275. */
1458 if ((val
- 0x10 > 3 && (dialect
& ALLOW8_SPRG
) == 0)
1459 || (val
- 0x10 > 7 && (insn
& 0x100) != 0)
1466 /* The TBR field in an XFX instruction. This is just like SPR, but it
1470 insert_tbr (uint64_t insn
,
1472 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1473 const char **errmsg
)
1475 if (value
!= 268 && value
!= 269)
1476 *errmsg
= _("invalid tbr number");
1477 return insn
| ((value
& 0x1f) << 16) | ((value
& 0x3e0) << 6);
1481 extract_tbr (uint64_t insn
,
1482 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1485 /* Missing optional operands have a value of 268. */
1489 int64_t ret
= ((insn
>> 16) & 0x1f) | ((insn
>> 6) & 0x3e0);
1490 if (ret
!= 268 && ret
!= 269)
1495 /* The XT and XS fields in an XX1 or XX3 form instruction. This is split. */
1498 insert_xt6 (uint64_t insn
,
1500 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1501 const char **errmsg ATTRIBUTE_UNUSED
)
1503 return insn
| ((value
& 0x1f) << 21) | ((value
& 0x20) >> 5);
1507 extract_xt6 (uint64_t insn
,
1508 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1509 int *invalid ATTRIBUTE_UNUSED
)
1511 return ((insn
<< 5) & 0x20) | ((insn
>> 21) & 0x1f);
1514 /* The XT and XS fields in an DQ form VSX instruction. This is split. */
1516 insert_xtq6 (uint64_t insn
,
1518 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1519 const char **errmsg ATTRIBUTE_UNUSED
)
1521 return insn
| ((value
& 0x1f) << 21) | ((value
& 0x20) >> 2);
1525 extract_xtq6 (uint64_t insn
,
1526 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1527 int *invalid ATTRIBUTE_UNUSED
)
1529 return ((insn
<< 2) & 0x20) | ((insn
>> 21) & 0x1f);
1532 /* The XA field in an XX3 form instruction. This is split. */
1535 insert_xa6 (uint64_t insn
,
1537 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1538 const char **errmsg ATTRIBUTE_UNUSED
)
1540 return insn
| ((value
& 0x1f) << 16) | ((value
& 0x20) >> 3);
1544 extract_xa6 (uint64_t insn
,
1545 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1546 int *invalid ATTRIBUTE_UNUSED
)
1548 return ((insn
<< 3) & 0x20) | ((insn
>> 16) & 0x1f);
1551 /* The XA field in an MMA XX3 form instruction. This is split
1552 and must not overlap with the ACC operand. */
1555 insert_xa6a (uint64_t insn
,
1558 const char **errmsg
)
1560 int64_t acc
= (insn
>> 23) & 0x7;
1561 if ((value
>> 2) == acc
)
1562 *errmsg
= _("VSR overlaps ACC operand");
1563 return insert_xa6 (insn
, value
, dialect
, errmsg
);
1567 extract_xa6a (uint64_t insn
,
1571 int64_t acc
= (insn
>> 23) & 0x7;
1572 int64_t value
= extract_xa6 (insn
, dialect
, invalid
);
1573 if ((value
>> 2) == acc
)
1578 /* The XB field in an XX3 form instruction. This is split. */
1581 insert_xb6 (uint64_t insn
,
1583 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1584 const char **errmsg ATTRIBUTE_UNUSED
)
1586 return insn
| ((value
& 0x1f) << 11) | ((value
& 0x20) >> 4);
1590 extract_xb6 (uint64_t insn
,
1591 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1592 int *invalid ATTRIBUTE_UNUSED
)
1594 return ((insn
<< 4) & 0x20) | ((insn
>> 11) & 0x1f);
1597 /* The XB field in an MMA XX3 form instruction. This is split
1598 and must not overlap with the ACC operand. */
1601 insert_xb6a (uint64_t insn
,
1604 const char **errmsg
)
1606 int64_t acc
= (insn
>> 23) & 0x7;
1607 if ((value
>> 2) == acc
)
1608 *errmsg
= _("VSR overlaps ACC operand");
1609 return insert_xb6 (insn
, value
, dialect
, errmsg
);
1613 extract_xb6a (uint64_t insn
,
1617 int64_t acc
= (insn
>> 23) & 0x7;
1618 int64_t value
= extract_xb6 (insn
, dialect
, invalid
);
1619 if ((value
>> 2) == acc
)
1624 /* The XA and XB fields in an XX3 form instruction when they must be the same.
1625 This is used for extended mnemonics like xvmovdp. The extraction function
1626 enforces that the fields are the same. */
1629 insert_xab6 (uint64_t insn
,
1632 const char **errmsg
)
1634 return insert_xa6 (insn
, value
, dialect
, errmsg
)
1635 | insert_xb6 (insn
, value
, dialect
, errmsg
);
1639 extract_xab6 (uint64_t insn
,
1643 int64_t xa6
= extract_xa6 (insn
, dialect
, invalid
);
1644 int64_t xb6
= extract_xb6 (insn
, dialect
, invalid
);
1651 /* The XC field in an XX4 form instruction. This is split. */
1654 insert_xc6 (uint64_t insn
,
1656 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1657 const char **errmsg ATTRIBUTE_UNUSED
)
1659 return insn
| ((value
& 0x1f) << 6) | ((value
& 0x20) >> 2);
1663 extract_xc6 (uint64_t insn
,
1664 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1665 int *invalid ATTRIBUTE_UNUSED
)
1667 return ((insn
<< 2) & 0x20) | ((insn
>> 6) & 0x1f);
1670 /* The split XTp field in a vector paired insn. */
1673 insert_xtp (uint64_t insn
,
1675 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1676 const char **errmsg ATTRIBUTE_UNUSED
)
1678 return insn
| ((value
& 0x1e) << 21) | ((value
& 0x20) << (21 - 5));
1682 extract_xtp (uint64_t insn
,
1683 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1684 int *invalid ATTRIBUTE_UNUSED
)
1686 return ((insn
>> (21 - 5)) & 0x20) | ((insn
>> 21) & 0x1e);
1689 /* The split XT field in a vector splat insn. */
1692 insert_xts (uint64_t insn
,
1694 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1695 const char **errmsg ATTRIBUTE_UNUSED
)
1697 return insn
| ((value
& 0x1f) << 21) | ((value
& 0x20) << (16 - 5));
1701 extract_xts (uint64_t insn
,
1702 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1703 int *invalid ATTRIBUTE_UNUSED
)
1705 return ((insn
>> (16 - 5)) & 0x20) | ((insn
>> 21) & 0x1f);
1709 insert_dm (uint64_t insn
,
1711 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1712 const char **errmsg
)
1714 if (value
!= 0 && value
!= 1)
1715 *errmsg
= _("invalid constant");
1716 return insn
| (((value
) ? 3 : 0) << 8);
1720 extract_dm (uint64_t insn
,
1721 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1724 int64_t value
= (insn
>> 8) & 3;
1725 if (value
!= 0 && value
!= 3)
1727 return (value
) ? 1 : 0;
1730 /* The VLESIMM field in an I16A form instruction. This is split. */
1733 insert_vlesi (uint64_t insn
,
1735 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1736 const char **errmsg ATTRIBUTE_UNUSED
)
1738 return insn
| ((value
& 0xf800) << 10) | (value
& 0x7ff);
1742 extract_vlesi (uint64_t insn
,
1743 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1744 int *invalid ATTRIBUTE_UNUSED
)
1746 int64_t value
= ((insn
>> 10) & 0xf800) | (insn
& 0x7ff);
1747 value
= (value
^ 0x8000) - 0x8000;
1752 insert_vlensi (uint64_t insn
,
1754 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1755 const char **errmsg ATTRIBUTE_UNUSED
)
1758 return insn
| ((value
& 0xf800) << 10) | (value
& 0x7ff);
1761 extract_vlensi (uint64_t insn
,
1762 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1765 int64_t value
= ((insn
>> 10) & 0xf800) | (insn
& 0x7ff);
1766 value
= (value
^ 0x8000) - 0x8000;
1767 /* Don't use for disassembly. */
1772 /* The VLEUIMM field in an I16A form instruction. This is split. */
1775 insert_vleui (uint64_t insn
,
1777 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1778 const char **errmsg ATTRIBUTE_UNUSED
)
1780 return insn
| ((value
& 0xf800) << 10) | (value
& 0x7ff);
1784 extract_vleui (uint64_t insn
,
1785 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1786 int *invalid ATTRIBUTE_UNUSED
)
1788 return ((insn
>> 10) & 0xf800) | (insn
& 0x7ff);
1791 /* The VLEUIMML field in an I16L form instruction. This is split. */
1794 insert_vleil (uint64_t insn
,
1796 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1797 const char **errmsg ATTRIBUTE_UNUSED
)
1799 return insn
| ((value
& 0xf800) << 5) | (value
& 0x7ff);
1803 extract_vleil (uint64_t insn
,
1804 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1805 int *invalid ATTRIBUTE_UNUSED
)
1807 return ((insn
>> 5) & 0xf800) | (insn
& 0x7ff);
1811 insert_evuimm1_ex0 (uint64_t insn
,
1813 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1814 const char **errmsg
)
1816 if (value
<= 0 || value
> 0x1f)
1817 *errmsg
= _("UIMM = 00000 is illegal");
1818 return insn
| ((value
& 0x1f) << 11);
1822 extract_evuimm1_ex0 (uint64_t insn
,
1823 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1826 int64_t value
= ((insn
>> 11) & 0x1f);
1834 insert_evuimm2_ex0 (uint64_t insn
,
1836 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1837 const char **errmsg
)
1839 if (value
<= 0 || value
> 0x3e)
1840 *errmsg
= _("UIMM = 00000 is illegal");
1841 return insn
| ((value
& 0x3e) << 10);
1845 extract_evuimm2_ex0 (uint64_t insn
,
1846 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1849 int64_t value
= ((insn
>> 10) & 0x3e);
1857 insert_evuimm4_ex0 (uint64_t insn
,
1859 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1860 const char **errmsg
)
1862 if (value
<= 0 || value
> 0x7c)
1863 *errmsg
= _("UIMM = 00000 is illegal");
1864 return insn
| ((value
& 0x7c) << 9);
1868 extract_evuimm4_ex0 (uint64_t insn
,
1869 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1872 int64_t value
= ((insn
>> 9) & 0x7c);
1880 insert_evuimm8_ex0 (uint64_t insn
,
1882 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1883 const char **errmsg
)
1885 if (value
<= 0 || value
> 0xf8)
1886 *errmsg
= _("UIMM = 00000 is illegal");
1887 return insn
| ((value
& 0xf8) << 8);
1891 extract_evuimm8_ex0 (uint64_t insn
,
1892 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1895 int64_t value
= ((insn
>> 8) & 0xf8);
1903 insert_evuimm_lt8 (uint64_t insn
,
1905 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1906 const char **errmsg
)
1908 if (value
< 0 || value
> 7)
1909 *errmsg
= _("UIMM values >7 are illegal");
1910 return insn
| ((value
& 0x7) << 11);
1914 extract_evuimm_lt8 (uint64_t insn
,
1915 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1918 int64_t value
= ((insn
>> 11) & 0x1f);
1926 insert_evuimm_lt16 (uint64_t insn
,
1928 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1929 const char **errmsg
)
1931 if (value
< 0 || value
> 15)
1932 *errmsg
= _("UIMM values >15 are illegal");
1933 return insn
| ((value
& 0xf) << 11);
1937 extract_evuimm_lt16 (uint64_t insn
,
1938 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1941 int64_t value
= ((insn
>> 11) & 0x1f);
1949 insert_rD_rS_even (uint64_t insn
,
1951 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1952 const char **errmsg
)
1954 if ((value
& 0x1) != 0)
1955 *errmsg
= _("GPR odd is illegal");
1956 return insn
| ((value
& 0x1e) << 21);
1960 extract_rD_rS_even (uint64_t insn
,
1961 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1964 int64_t value
= ((insn
>> 21) & 0x1f);
1965 if ((value
& 0x1) != 0)
1972 insert_off_lsp (uint64_t insn
,
1974 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1975 const char **errmsg
)
1977 if (value
<= 0 || value
> 0x3)
1978 *errmsg
= _("invalid offset");
1979 return insn
| (value
& 0x3);
1983 extract_off_lsp (uint64_t insn
,
1984 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1987 int64_t value
= (insn
& 0x3);
1995 insert_off_spe2 (uint64_t insn
,
1997 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1998 const char **errmsg
)
2000 if (value
<= 0 || value
> 0x7)
2001 *errmsg
= _("invalid offset");
2002 return insn
| (value
& 0x7);
2006 extract_off_spe2 (uint64_t insn
,
2007 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
2010 int64_t value
= (insn
& 0x7);
2018 insert_Ddd (uint64_t insn
,
2020 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
2021 const char **errmsg
)
2023 if (value
< 0 || value
> 0x7)
2024 *errmsg
= _("invalid Ddd value");
2025 return insn
| ((value
& 0x3) << 11) | ((value
& 0x4) >> 2);
2029 extract_Ddd (uint64_t insn
,
2030 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
2031 int *invalid ATTRIBUTE_UNUSED
)
2033 return ((insn
>> 11) & 0x3) | ((insn
<< 2) & 0x4);
2037 insert_sxl (uint64_t insn
,
2039 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
2040 const char **errmsg ATTRIBUTE_UNUSED
)
2042 return insn
| ((value
& 0x1) << 11);
2046 extract_sxl (uint64_t insn
,
2047 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
2050 /* Missing optional operands have a value of one. */
2053 return (insn
>> 11) & 0x1;
2056 /* The operands table.
2058 The fields are bitm, shift, insert, extract, flags.
2060 We used to put parens around the various additions, like the one
2061 for BA just below. However, that caused trouble with feeble
2062 compilers with a limit on depth of a parenthesized expression, like
2063 (reportedly) the compiler in Microsoft Developer Studio 5. So we
2064 omit the parens, since the macros are never used in a context where
2065 the addition will be ambiguous. */
2067 const struct powerpc_operand powerpc_operands
[] =
2069 /* The zero index is used to indicate the end of the list of
2072 { 0, 0, NULL
, NULL
, 0 },
2074 /* The BA field in an XL form instruction. */
2075 #define BA UNUSED + 1
2076 /* The BI field in a B form or XL form instruction. */
2078 #define BI_MASK (0x1f << 16)
2079 { 0x1f, 16, NULL
, NULL
, PPC_OPERAND_CR_BIT
},
2081 /* The BT, BA and BB fields in a XL form instruction when they must all
2084 { 0x1f, 21, insert_btab
, extract_btab
, PPC_OPERAND_CR_BIT
},
2086 /* The BB field in an XL form instruction. */
2088 #define BB_MASK (0x1f << 11)
2089 { 0x1f, 11, NULL
, NULL
, PPC_OPERAND_CR_BIT
},
2091 /* The BA and BB fields in a XL form instruction when they must be
2094 { 0x1f, 16, insert_bab
, extract_bab
, PPC_OPERAND_CR_BIT
},
2096 /* The VRA and VRB fields in a VX form instruction when they must be the same.
2097 This is used for extended mnemonics like vmr. */
2099 { 0x1f, 16, insert_bab
, extract_bab
, PPC_OPERAND_VR
},
2101 /* The RA and RB fields in a VX form instruction when they must be the same.
2102 This is used for extended mnemonics like evmr. */
2104 { 0x1f, 16, insert_bab
, extract_bab
, PPC_OPERAND_GPR
},
2106 /* The BD field in a B form instruction. The lower two bits are
2109 { 0xfffc, 0, NULL
, NULL
, PPC_OPERAND_RELATIVE
| PPC_OPERAND_SIGNED
},
2111 /* The BD field in a B form instruction when absolute addressing is
2114 { 0xfffc, 0, NULL
, NULL
, PPC_OPERAND_ABSOLUTE
| PPC_OPERAND_SIGNED
},
2116 /* The BD field in a B form instruction when the - modifier is used.
2117 This sets the y bit of the BO field appropriately. */
2119 { 0xfffc, 0, insert_bdm
, extract_bdm
,
2120 PPC_OPERAND_RELATIVE
| PPC_OPERAND_SIGNED
},
2122 /* The BD field in a B form instruction when the - modifier is used
2123 and absolute address is used. */
2124 #define BDMA BDM + 1
2125 { 0xfffc, 0, insert_bdm
, extract_bdm
,
2126 PPC_OPERAND_ABSOLUTE
| PPC_OPERAND_SIGNED
},
2128 /* The BD field in a B form instruction when the + modifier is used.
2129 This sets the y bit of the BO field appropriately. */
2130 #define BDP BDMA + 1
2131 { 0xfffc, 0, insert_bdp
, extract_bdp
,
2132 PPC_OPERAND_RELATIVE
| PPC_OPERAND_SIGNED
},
2134 /* The BD field in a B form instruction when the + modifier is used
2135 and absolute addressing is used. */
2136 #define BDPA BDP + 1
2137 { 0xfffc, 0, insert_bdp
, extract_bdp
,
2138 PPC_OPERAND_ABSOLUTE
| PPC_OPERAND_SIGNED
},
2140 /* The BF field in an X or XL form instruction. */
2142 /* The CRFD field in an X form instruction. */
2144 /* The CRD field in an XL form instruction. */
2146 { 0x7, 23, NULL
, NULL
, PPC_OPERAND_CR_REG
},
2148 /* The BF field in an X or XL form instruction. */
2150 { 0x7, 23, NULL
, NULL
, 0 },
2152 /* The ACC field in a VSX ACC 8LS:D-form instruction. */
2154 { 0x7, 23, NULL
, NULL
, PPC_OPERAND_ACC
},
2156 /* An optional BF field. This is used for comparison instructions,
2157 in which an omitted BF field is taken as zero. */
2159 { 0x7, 23, NULL
, NULL
, PPC_OPERAND_CR_REG
| PPC_OPERAND_OPTIONAL
},
2161 /* The BFA field in an X or XL form instruction. */
2163 { 0x7, 18, NULL
, NULL
, PPC_OPERAND_CR_REG
},
2165 /* The BO field in a B form instruction. Certain values are
2168 #define BO_MASK (0x1f << 21)
2169 { 0x1f, 21, insert_bo
, extract_bo
, 0 },
2171 /* The BO field in a B form instruction when the - modifier is used. */
2173 { 0x1f, 21, insert_bom
, extract_bom
, 0 },
2175 /* The BO field in a B form instruction when the + modifier is used. */
2177 { 0x1f, 21, insert_bop
, extract_bop
, 0 },
2179 /* The RM field in an X form instruction. */
2182 { 0x3, 11, NULL
, NULL
, 0 },
2185 { 0x3, 11, NULL
, NULL
, PPC_OPERAND_OPTIONAL
},
2187 /* The BT field in an X or XL form instruction. */
2189 { 0x1f, 21, NULL
, NULL
, PPC_OPERAND_CR_BIT
},
2191 /* The BT field in a mtfsb0 or mtfsb1 instruction. */
2193 { 0x1f, 21, NULL
, NULL
, PPC_OPERAND_CR_BIT
| PPC_OPERAND_CR_REG
},
2195 /* The BI16 field in a BD8 form instruction. */
2196 #define BI16 BTF + 1
2197 { 0x3, 8, NULL
, NULL
, PPC_OPERAND_CR_BIT
},
2199 /* The BI32 field in a BD15 form instruction. */
2200 #define BI32 BI16 + 1
2201 { 0xf, 16, NULL
, NULL
, PPC_OPERAND_CR_BIT
},
2203 /* The BO32 field in a BD15 form instruction. */
2204 #define BO32 BI32 + 1
2205 { 0x3, 20, NULL
, NULL
, 0 },
2207 /* The B8 field in a BD8 form instruction. */
2209 { 0x1fe, -1, NULL
, NULL
, PPC_OPERAND_RELATIVE
| PPC_OPERAND_SIGNED
},
2211 /* The B15 field in a BD15 form instruction. The lowest bit is
2214 { 0xfffe, 0, NULL
, NULL
, PPC_OPERAND_RELATIVE
| PPC_OPERAND_SIGNED
},
2216 /* The B24 field in a BD24 form instruction. The lowest bit is
2219 { 0x1fffffe, 0, NULL
, NULL
, PPC_OPERAND_RELATIVE
| PPC_OPERAND_SIGNED
},
2221 /* The condition register number portion of the BI field in a B form
2222 or XL form instruction. This is used for the extended
2223 conditional branch mnemonics, which set the lower two bits of the
2224 BI field. This field is optional. */
2226 { 0x7, 18, NULL
, NULL
, PPC_OPERAND_CR_REG
| PPC_OPERAND_OPTIONAL
},
2228 /* The CRB field in an X form instruction. */
2230 /* The MB field in an M form instruction. */
2232 #define MB_MASK (0x1f << 6)
2233 { 0x1f, 6, NULL
, NULL
, 0 },
2235 /* The CRD32 field in an XL form instruction. */
2236 #define CRD32 CRB + 1
2237 { 0x3, 21, NULL
, NULL
, PPC_OPERAND_CR_REG
},
2239 /* The CRFS field in an X form instruction. */
2240 #define CRFS CRD32 + 1
2241 { 0x7, 0, NULL
, NULL
, PPC_OPERAND_CR_REG
},
2243 #define CRS CRFS + 1
2244 { 0x3, 18, NULL
, NULL
, PPC_OPERAND_CR_REG
| PPC_OPERAND_OPTIONAL
},
2246 /* The CT field in an X form instruction. */
2248 /* The MO field in an mbar instruction. */
2250 { 0x1f, 21, NULL
, NULL
, PPC_OPERAND_OPTIONAL
},
2252 /* The D field in a D form instruction. This is a displacement off
2253 a register, and implies that the next operand is a register in
2256 { 0xffff, 0, NULL
, NULL
, PPC_OPERAND_PARENS
| PPC_OPERAND_SIGNED
},
2258 /* The D8 field in a D form instruction. This is a displacement off
2259 a register, and implies that the next operand is a register in
2262 { 0xff, 0, NULL
, NULL
, PPC_OPERAND_PARENS
| PPC_OPERAND_SIGNED
},
2264 /* The DCMX field in an X form instruction. */
2266 { 0x7f, 16, NULL
, NULL
, 0 },
2268 /* The split DCMX field in an X form instruction. */
2269 #define DCMXS DCMX + 1
2270 { 0x7f, PPC_OPSHIFT_INV
, insert_dcmxs
, extract_dcmxs
, 0 },
2272 /* The DQ field in a DQ form instruction. This is like D, but the
2273 lower four bits are forced to zero. */
2274 #define DQ DCMXS + 1
2275 { 0xfff0, 0, NULL
, NULL
,
2276 PPC_OPERAND_PARENS
| PPC_OPERAND_SIGNED
| PPC_OPERAND_DQ
},
2278 /* The DS field in a DS form instruction. This is like D, but the
2279 lower two bits are forced to zero. */
2281 { 0xfffc, 0, NULL
, NULL
,
2282 PPC_OPERAND_PARENS
| PPC_OPERAND_SIGNED
| PPC_OPERAND_DS
},
2284 /* The D field in an 8-byte D form prefix instruction. This is a displacement
2285 off a register, and implies that the next operand is a register in
2288 { UINT64_C(0x3ffffffff), PPC_OPSHIFT_INV
, insert_d34
, extract_d34
,
2289 PPC_OPERAND_PARENS
| PPC_OPERAND_SIGNED
},
2291 /* The SI field in an 8-byte D form prefix instruction. */
2292 #define SI34 D34 + 1
2293 { UINT64_C(0x3ffffffff), PPC_OPSHIFT_INV
, insert_d34
, extract_d34
, PPC_OPERAND_SIGNED
},
2295 /* The NSI field in an 8-byte D form prefix instruction. This is the
2296 same as the SI34 field, only negated. */
2297 #define NSI34 SI34 + 1
2298 { UINT64_C(0x3ffffffff), PPC_OPSHIFT_INV
, insert_nsi34
, extract_nsi34
,
2299 PPC_OPERAND_NEGATIVE
| PPC_OPERAND_SIGNED
},
2301 /* The IMM32 field in a vector splat immediate prefix instruction. */
2302 #define IMM32 NSI34 + 1
2303 { 0xffffffff, PPC_OPSHIFT_INV
, insert_imm32
, extract_imm32
, 0},
2305 /* The UIM field in a vector permute extended prefix instruction. */
2306 #define UIM3 IMM32 + 1
2307 { 0x7, 32, NULL
, NULL
, 0},
2309 /* The IX field in xxsplti32dx. */
2311 { 0x1, 17, NULL
, NULL
, 0 },
2313 /* The PMSK field in GER rank 8 prefix instructions. */
2314 #define PMSK8 IX + 1
2315 { 0xff, 40, NULL
, NULL
, 0 },
2317 /* The PMSK field in GER rank 4 prefix instructions. */
2318 #define PMSK4 PMSK8 + 1
2319 { 0xf, 44, NULL
, NULL
, 0 },
2321 /* The PMSK field in GER rank 2 prefix instructions. */
2322 #define PMSK2 PMSK4 + 1
2323 { 0x3, 46, NULL
, NULL
, 0 },
2325 /* The XMSK field in GER prefix instructions. */
2326 #define XMSK PMSK2 + 1
2327 { 0xf, 36, NULL
, NULL
, 0 },
2329 /* The YMSK field in GER prefix instructions. */
2330 #define YMSK XMSK + 1
2331 { 0xf, 32, NULL
, NULL
, 0 },
2333 /* The YMSK field in 64-bit GER prefix instructions. */
2334 #define YMSK2 YMSK + 1
2335 { 0x3, 34, NULL
, NULL
, 0 },
2337 /* The DUIS or BHRBE fields in a XFX form instruction, 10 bits
2338 unsigned imediate */
2339 #define DUIS YMSK2 + 1
2341 { 0x3ff, 11, NULL
, NULL
, 0 },
2343 /* The split D field in a DX form instruction. */
2344 #define DXD DUIS + 1
2345 { 0xffff, PPC_OPSHIFT_INV
, insert_dxd
, extract_dxd
,
2346 PPC_OPERAND_SIGNED
| PPC_OPERAND_SIGNOPT
},
2348 /* The split ND field in a DX form instruction.
2349 This is the same as the DX field, only negated. */
2350 #define NDXD DXD + 1
2351 { 0xffff, PPC_OPSHIFT_INV
, insert_dxdn
, extract_dxdn
,
2352 PPC_OPERAND_NEGATIVE
| PPC_OPERAND_SIGNED
| PPC_OPERAND_SIGNOPT
},
2354 /* The E field in a wrteei instruction. */
2355 /* And the W bit in the pair singles instructions. */
2356 /* And the ST field in a VX form instruction. */
2360 { 0x1, 15, NULL
, NULL
, 0 },
2362 /* The FL1 field in a POWER SC form instruction. */
2364 /* The U field in an X form instruction. */
2366 { 0xf, 12, NULL
, NULL
, 0 },
2368 /* The FL2 field in a POWER SC form instruction. */
2370 { 0x7, 2, NULL
, NULL
, 0 },
2372 /* The FLM field in an XFL form instruction. */
2374 { 0xff, 17, NULL
, NULL
, 0 },
2376 /* The FRA field in an X or A form instruction. */
2378 #define FRA_MASK (0x1f << 16)
2379 { 0x1f, 16, NULL
, NULL
, PPC_OPERAND_FPR
},
2381 /* The FRAp field of DFP instructions. */
2382 #define FRAp FRA + 1
2383 { 0x1e, 16, NULL
, NULL
, PPC_OPERAND_FPR
},
2385 /* The FRB field in an X or A form instruction. */
2386 #define FRB FRAp + 1
2387 #define FRB_MASK (0x1f << 11)
2388 { 0x1f, 11, NULL
, NULL
, PPC_OPERAND_FPR
},
2390 /* The FRBp field of DFP instructions. */
2391 #define FRBp FRB + 1
2392 { 0x1e, 11, NULL
, NULL
, PPC_OPERAND_FPR
},
2394 /* The FRC field in an A form instruction. */
2395 #define FRC FRBp + 1
2396 #define FRC_MASK (0x1f << 6)
2397 { 0x1f, 6, NULL
, NULL
, PPC_OPERAND_FPR
},
2399 /* The FRS field in an X form instruction or the FRT field in a D, X
2400 or A form instruction. */
2403 { 0x1f, 21, NULL
, NULL
, PPC_OPERAND_FPR
},
2405 /* The FRSp field of stfdp or the FRTp field of lfdp and DFP
2407 #define FRSp FRS + 1
2409 { 0x1e, 21, NULL
, NULL
, PPC_OPERAND_FPR
},
2411 /* The FXM field in an XFX instruction. */
2412 #define FXM FRSp + 1
2413 { 0xff, 12, insert_fxm
, extract_fxm
, 0 },
2415 /* Power4 version for mfcr. */
2416 #define FXM4 FXM + 1
2417 { 0xff, 12, insert_fxm
, extract_fxm
, PPC_OPERAND_OPTIONAL
},
2419 /* The IMM20 field in an LI instruction. */
2420 #define IMM20 FXM4 + 1
2421 { 0xfffff, PPC_OPSHIFT_INV
, insert_li20
, extract_li20
, PPC_OPERAND_SIGNED
},
2423 /* The L field in a D or X form instruction. */
2425 { 0x1, 21, NULL
, NULL
, 0 },
2427 /* The optional L field in tlbie and tlbiel instructions. */
2429 /* The R field in a HTM X form instruction. */
2431 { 0x1, 21, NULL
, NULL
, PPC_OPERAND_OPTIONAL
},
2433 /* The optional L field in the paste. instruction. This is similar to LOPT
2434 above, but with a default value of 1. */
2435 #define L1OPT LOPT + 1
2436 { 0x1, 21, insert_l1opt
, extract_l1opt
, PPC_OPERAND_OPTIONAL
},
2438 /* The optional (for 32-bit) L field in cmp[l][i] instructions. */
2439 #define L32OPT L1OPT + 1
2440 { 0x1, 21, NULL
, NULL
, PPC_OPERAND_OPTIONAL
| PPC_OPERAND_OPTIONAL32
},
2442 /* The L field in dcbf instruction. */
2443 #define L2OPT L32OPT + 1
2444 { 0x3, 21, NULL
, NULL
, PPC_OPERAND_OPTIONAL
},
2446 /* The LEV field in a POWER SVC / POWER9 SCV form instruction. */
2447 #define SVC_LEV L2OPT + 1
2448 { 0x7f, 5, NULL
, NULL
, 0 },
2450 /* The LEV field in an SC form instruction. */
2451 #define LEV SVC_LEV + 1
2452 { 0x7f, 5, NULL
, NULL
, PPC_OPERAND_OPTIONAL
},
2454 /* The LI field in an I form instruction. The lower two bits are
2457 { 0x3fffffc, 0, NULL
, NULL
, PPC_OPERAND_RELATIVE
| PPC_OPERAND_SIGNED
},
2459 /* The LI field in an I form instruction when used as an absolute
2462 { 0x3fffffc, 0, NULL
, NULL
, PPC_OPERAND_ABSOLUTE
| PPC_OPERAND_SIGNED
},
2464 /* The LS or WC field in an X (sync or wait) form instruction. */
2467 { 0x3, 21, insert_ls
, extract_ls
, PPC_OPERAND_OPTIONAL
},
2469 /* The ME field in an M form instruction. */
2471 #define ME_MASK (0x1f << 1)
2472 { 0x1f, 1, NULL
, NULL
, 0 },
2474 /* The MB and ME fields in an M form instruction expressed a single
2475 operand which is a bitmask indicating which bits to select. This
2476 is a two operand form using PPC_OPERAND_NEXT. See the
2477 description in opcode/ppc.h for what this means. */
2479 { 0x1f, 6, NULL
, NULL
, PPC_OPERAND_OPTIONAL
| PPC_OPERAND_NEXT
},
2480 { -1, 0, insert_mbe
, extract_mbe
, 0 },
2482 /* The MB or ME field in an MD or MDS form instruction. The high
2483 bit is wrapped to the low end. */
2486 #define MB6_MASK (0x3f << 5)
2487 { 0x3f, 5, insert_mb6
, extract_mb6
, 0 },
2489 /* The NB field in an X form instruction. The value 32 is stored as
2492 { 0x1f, 11, NULL
, extract_nb
, PPC_OPERAND_PLUS1
},
2494 /* The NBI field in an lswi instruction, which has special value
2495 restrictions. The value 32 is stored as 0. */
2497 { 0x1f, 11, insert_nbi
, extract_nb
, PPC_OPERAND_PLUS1
},
2499 /* The NSI field in a D form instruction. This is the same as the
2500 SI field, only negated. */
2502 { 0xffff, 0, insert_nsi
, extract_nsi
,
2503 PPC_OPERAND_NEGATIVE
| PPC_OPERAND_SIGNED
},
2505 /* The NSI field in a D form instruction when we accept a wide range
2506 of positive values. */
2507 #define NSISIGNOPT NSI + 1
2508 { 0xffff, 0, insert_nsi
, extract_nsi
,
2509 PPC_OPERAND_NEGATIVE
| PPC_OPERAND_SIGNED
| PPC_OPERAND_SIGNOPT
},
2511 /* The RA field in an D, DS, DQ, X, XO, M, or MDS form instruction. */
2512 #define RA NSISIGNOPT + 1
2513 #define RA_MASK (0x1f << 16)
2514 { 0x1f, 16, NULL
, NULL
, PPC_OPERAND_GPR
},
2516 /* As above, but 0 in the RA field means zero, not r0. */
2518 { 0x1f, 16, NULL
, NULL
, PPC_OPERAND_GPR_0
},
2520 /* Similar to above, but optional. */
2521 #define PRA0 RA0 + 1
2522 { 0x1f, 16, NULL
, NULL
, PPC_OPERAND_GPR_0
| PPC_OPERAND_OPTIONAL
},
2524 /* The RA field in the DQ form lq or an lswx instruction, which have
2525 special value restrictions. */
2526 #define RAQ PRA0 + 1
2528 { 0x1f, 16, insert_raq
, extract_raq
, PPC_OPERAND_GPR_0
},
2530 /* Similar to above, but optional. */
2531 #define PRAQ RAQ + 1
2532 { 0x1f, 16, insert_raq
, extract_raq
,
2533 PPC_OPERAND_GPR_0
| PPC_OPERAND_OPTIONAL
},
2535 /* The R field in an 8-byte D, DS, DQ or X form prefix instruction. */
2536 #define PCREL PRAQ + 1
2537 #define PCREL_MASK (1ULL << 52)
2538 { 0x1, 52, insert_pcrel
, extract_pcrel
, PPC_OPERAND_OPTIONAL
},
2540 #define PCREL0 PCREL + 1
2541 { 0x1, 52, insert_pcrel
, extract_pcrel0
, PPC_OPERAND_OPTIONAL
},
2543 /* The RA field in a D or X form instruction which is an updating
2544 load, which means that the RA field may not be zero and may not
2545 equal the RT field. */
2546 #define RAL PCREL0 + 1
2547 { 0x1f, 16, insert_ral
, extract_ral
, PPC_OPERAND_GPR_0
},
2549 /* The RA field in an lmw instruction, which has special value
2552 { 0x1f, 16, insert_ram
, extract_ram
, PPC_OPERAND_GPR_0
},
2554 /* The RA field in a D or X form instruction which is an updating
2555 store or an updating floating point load, which means that the RA
2556 field may not be zero. */
2558 { 0x1f, 16, insert_ras
, extract_ras
, PPC_OPERAND_GPR_0
},
2560 /* The RA field of the tlbwe, dccci and iccci instructions,
2561 which are optional. */
2562 #define RAOPT RAS + 1
2563 { 0x1f, 16, NULL
, NULL
, PPC_OPERAND_GPR
| PPC_OPERAND_OPTIONAL
},
2565 /* The RB field in an X, XO, M, or MDS form instruction. */
2566 #define RB RAOPT + 1
2567 #define RB_MASK (0x1f << 11)
2568 { 0x1f, 11, NULL
, NULL
, PPC_OPERAND_GPR
},
2570 /* The RS and RB fields in an X form instruction when they must be the same.
2571 This is used for extended mnemonics like mr. */
2573 { 0x1f, 11, insert_rsb
, extract_rsb
, PPC_OPERAND_GPR
},
2575 /* The RB field in an lswx instruction, which has special value
2578 { 0x1f, 11, insert_rbx
, extract_rbx
, PPC_OPERAND_GPR
},
2580 /* The RB field of the dccci and iccci instructions, which are optional. */
2581 #define RBOPT RBX + 1
2582 { 0x1f, 11, NULL
, NULL
, PPC_OPERAND_GPR
| PPC_OPERAND_OPTIONAL
},
2584 /* The RC register field in an maddld, maddhd or maddhdu instruction. */
2585 #define RC RBOPT + 1
2586 { 0x1f, 6, NULL
, NULL
, PPC_OPERAND_GPR
},
2588 /* The RS field in a D, DS, X, XFX, XS, M, MD or MDS form
2589 instruction or the RT field in a D, DS, X, XFX or XO form
2593 #define RT_MASK (0x1f << 21)
2595 { 0x1f, 21, NULL
, NULL
, PPC_OPERAND_GPR
},
2597 #define RD_EVEN RS + 1
2598 #define RS_EVEN RD_EVEN
2599 { 0x1f, 21, insert_rD_rS_even
, extract_rD_rS_even
, PPC_OPERAND_GPR
},
2601 /* The RS and RT fields of the DS form stq and DQ form lq instructions,
2602 which have special value restrictions. */
2603 #define RSQ RS_EVEN + 1
2605 #define Q_MASK (1 << 21)
2606 { 0x1e, 21, NULL
, NULL
, PPC_OPERAND_GPR
},
2608 /* The RS field of the tlbwe instruction, which is optional. */
2611 { 0x1f, 21, NULL
, NULL
, PPC_OPERAND_GPR
| PPC_OPERAND_OPTIONAL
},
2613 /* The RX field of the SE_RR form instruction. */
2615 { 0x1f, PPC_OPSHIFT_INV
, insert_rx
, extract_rx
, PPC_OPERAND_GPR
},
2617 /* The ARX field of the SE_RR form instruction. */
2619 { 0x1f, PPC_OPSHIFT_INV
, insert_arx
, extract_arx
, PPC_OPERAND_GPR
},
2621 /* The RY field of the SE_RR form instruction. */
2624 { 0x1f, PPC_OPSHIFT_INV
, insert_ry
, extract_ry
, PPC_OPERAND_GPR
},
2626 /* The ARY field of the SE_RR form instruction. */
2628 { 0x1f, PPC_OPSHIFT_INV
, insert_ary
, extract_ary
, PPC_OPERAND_GPR
},
2630 /* The SCLSCI8 field in a D form instruction. */
2631 #define SCLSCI8 ARY + 1
2632 { 0xffffffff, PPC_OPSHIFT_INV
, insert_sci8
, extract_sci8
, 0 },
2634 /* The SCLSCI8N field in a D form instruction. This is the same as the
2635 SCLSCI8 field, only negated. */
2636 #define SCLSCI8N SCLSCI8 + 1
2637 { 0xffffffff, PPC_OPSHIFT_INV
, insert_sci8n
, extract_sci8n
,
2638 PPC_OPERAND_NEGATIVE
| PPC_OPERAND_SIGNED
},
2640 /* The SD field of the SD4 form instruction. */
2641 #define SE_SD SCLSCI8N + 1
2642 { 0xf, 8, NULL
, NULL
, PPC_OPERAND_PARENS
},
2644 /* The SD field of the SD4 form instruction, for halfword. */
2645 #define SE_SDH SE_SD + 1
2646 { 0x1e, 7, NULL
, NULL
, PPC_OPERAND_PARENS
},
2648 /* The SD field of the SD4 form instruction, for word. */
2649 #define SE_SDW SE_SDH + 1
2650 { 0x3c, 6, NULL
, NULL
, PPC_OPERAND_PARENS
},
2652 /* The SH field in an X or M form instruction. */
2653 #define SH SE_SDW + 1
2654 #define SH_MASK (0x1f << 11)
2655 /* The other UIMM field in a EVX form instruction. */
2657 /* The FC field in an atomic X form instruction. */
2660 { 0x1f, 11, NULL
, NULL
, 0 },
2662 #define EVUIMM_LT8 SH + 1
2663 { 0x1f, 11, insert_evuimm_lt8
, extract_evuimm_lt8
, 0 },
2665 #define EVUIMM_LT16 EVUIMM_LT8 + 1
2666 { 0x1f, 11, insert_evuimm_lt16
, extract_evuimm_lt16
, 0 },
2668 /* The SI field in a HTM X form instruction. */
2669 #define HTM_SI EVUIMM_LT16 + 1
2670 { 0x1f, 11, NULL
, NULL
, PPC_OPERAND_SIGNED
},
2672 /* The SH field in an MD form instruction. This is split. */
2673 #define SH6 HTM_SI + 1
2674 #define SH6_MASK ((0x1f << 11) | (1 << 1))
2675 { 0x3f, PPC_OPSHIFT_INV
, insert_sh6
, extract_sh6
, 0 },
2677 /* The SH field of some variants of the tlbre and tlbwe
2678 instructions, and the ELEV field of the e_sc instruction. */
2681 { 0x1f, 11, NULL
, NULL
, PPC_OPERAND_OPTIONAL
},
2683 /* The SI field in a D form instruction. */
2685 { 0xffff, 0, NULL
, NULL
, PPC_OPERAND_SIGNED
},
2687 /* The SI field in a D form instruction when we accept a wide range
2688 of positive values. */
2689 #define SISIGNOPT SI + 1
2690 { 0xffff, 0, NULL
, NULL
, PPC_OPERAND_SIGNED
| PPC_OPERAND_SIGNOPT
},
2692 /* The SI8 field in a D form instruction. */
2693 #define SI8 SISIGNOPT + 1
2694 { 0xff, 0, NULL
, NULL
, PPC_OPERAND_SIGNED
},
2696 /* The SPR field in an XFX form instruction. This is flipped--the
2697 lower 5 bits are stored in the upper 5 and vice- versa. */
2701 #define SPR_MASK (0x3ff << 11)
2702 { 0x3ff, 11, insert_spr
, extract_spr
, PPC_OPERAND_SPR
},
2704 /* The BAT index number in an XFX form m[ft]ibat[lu] instruction. */
2705 #define SPRBAT SPR + 1
2706 #define SPRBAT_MASK (0xc1 << 11)
2707 { 0x7, PPC_OPSHIFT_INV
, insert_sprbat
, extract_sprbat
, PPC_OPERAND_SPR
},
2709 /* The GQR index number in an XFX form m[ft]gqr instruction. */
2710 #define SPRGQR SPRBAT + 1
2711 #define SPRGQR_MASK (0x7 << 16)
2712 { 0x7, 16, NULL
, NULL
, PPC_OPERAND_GQR
},
2714 /* The SPRG register number in an XFX form m[ft]sprg instruction. */
2715 #define SPRG SPRGQR + 1
2716 { 0x1f, 16, insert_sprg
, extract_sprg
, PPC_OPERAND_SPR
},
2718 /* The SR field in an X form instruction. */
2720 /* The 4-bit UIMM field in a VX form instruction. */
2722 { 0xf, 16, NULL
, NULL
, 0 },
2724 /* The STRM field in an X AltiVec form instruction. */
2726 /* The T field in a tlbilx form instruction. */
2728 /* The L field in wclr instructions. */
2730 { 0x3, 21, NULL
, NULL
, 0 },
2732 /* The ESYNC field in an X (sync) form instruction. */
2733 #define ESYNC STRM + 1
2734 { 0xf, 16, insert_esync
, extract_esync
, PPC_OPERAND_OPTIONAL
},
2736 /* The SV field in a POWER SC form instruction. */
2737 #define SV ESYNC + 1
2738 { 0x3fff, 2, NULL
, NULL
, 0 },
2740 /* The TBR field in an XFX form instruction. This is like the SPR
2741 field, but it is optional. */
2743 { 0x3ff, 11, insert_tbr
, extract_tbr
,
2744 PPC_OPERAND_SPR
| PPC_OPERAND_OPTIONAL
},
2746 /* The TO field in a D or X form instruction. */
2749 #define TO_MASK (0x1f << 21)
2750 { 0x1f, 21, NULL
, NULL
, 0 },
2752 /* The UI field in a D form instruction. */
2754 { 0xffff, 0, NULL
, NULL
, 0 },
2756 #define UISIGNOPT UI + 1
2757 { 0xffff, 0, NULL
, NULL
, PPC_OPERAND_SIGNOPT
},
2759 /* The IMM field in an SE_IM5 instruction. */
2760 #define UI5 UISIGNOPT + 1
2761 { 0x1f, 4, NULL
, NULL
, 0 },
2763 /* The OIMM field in an SE_OIM5 instruction. */
2764 #define OIMM5 UI5 + 1
2765 { 0x1f, 4, insert_oimm
, extract_oimm
, PPC_OPERAND_PLUS1
},
2767 /* The UI7 field in an SE_LI instruction. */
2768 #define UI7 OIMM5 + 1
2769 { 0x7f, 4, NULL
, NULL
, 0 },
2771 /* The VA field in a VA, VX or VXR form instruction. */
2773 { 0x1f, 16, NULL
, NULL
, PPC_OPERAND_VR
},
2775 /* The VB field in a VA, VX or VXR form instruction. */
2777 { 0x1f, 11, NULL
, NULL
, PPC_OPERAND_VR
},
2779 /* The VC field in a VA form instruction. */
2781 { 0x1f, 6, NULL
, NULL
, PPC_OPERAND_VR
},
2783 /* The VD or VS field in a VA, VX, VXR or X form instruction. */
2786 { 0x1f, 21, NULL
, NULL
, PPC_OPERAND_VR
},
2788 /* The SIMM field in a VX form instruction, and TE in Z form. */
2791 { 0x1f, 16, NULL
, NULL
, PPC_OPERAND_SIGNED
},
2793 /* The UIMM field in a VX form instruction. */
2794 #define UIMM SIMM + 1
2796 { 0x1f, 16, NULL
, NULL
, 0 },
2798 /* The 3-bit UIMM field in a VX form instruction. */
2799 #define UIMM3 UIMM + 1
2800 { 0x7, 16, NULL
, NULL
, 0 },
2802 /* The 6-bit UIM field in a X form instruction. */
2803 #define UIM6 UIMM3 + 1
2804 { 0x3f, 16, NULL
, NULL
, 0 },
2806 /* The SIX field in a VX form instruction. */
2807 #define SIX UIM6 + 1
2809 { 0xf, 11, NULL
, NULL
, 0 },
2811 /* The PS field in a VX form instruction. */
2813 { 0x1, 9, NULL
, NULL
, 0 },
2815 /* The SH field in a vector shift double by bit immediate instruction. */
2817 { 0x7, 6, NULL
, NULL
, 0 },
2819 /* The SHB field in a VA form instruction. */
2821 { 0xf, 6, NULL
, NULL
, 0 },
2823 /* The other UIMM field in a half word EVX form instruction. */
2824 #define EVUIMM_1 SHB + 1
2825 { 0x1f, 11, NULL
, NULL
, PPC_OPERAND_PARENS
},
2827 #define EVUIMM_1_EX0 EVUIMM_1 + 1
2828 { 0x1f, 11, insert_evuimm1_ex0
, extract_evuimm1_ex0
, PPC_OPERAND_PARENS
},
2830 #define EVUIMM_2 EVUIMM_1_EX0 + 1
2831 { 0x3e, 10, NULL
, NULL
, PPC_OPERAND_PARENS
},
2833 #define EVUIMM_2_EX0 EVUIMM_2 + 1
2834 { 0x3e, 10, insert_evuimm2_ex0
, extract_evuimm2_ex0
, PPC_OPERAND_PARENS
},
2836 /* The other UIMM field in a word EVX form instruction. */
2837 #define EVUIMM_4 EVUIMM_2_EX0 + 1
2838 { 0x7c, 9, NULL
, NULL
, PPC_OPERAND_PARENS
},
2840 #define EVUIMM_4_EX0 EVUIMM_4 + 1
2841 { 0x7c, 9, insert_evuimm4_ex0
, extract_evuimm4_ex0
, PPC_OPERAND_PARENS
},
2843 /* The other UIMM field in a double EVX form instruction. */
2844 #define EVUIMM_8 EVUIMM_4_EX0 + 1
2845 { 0xf8, 8, NULL
, NULL
, PPC_OPERAND_PARENS
},
2847 #define EVUIMM_8_EX0 EVUIMM_8 + 1
2848 { 0xf8, 8, insert_evuimm8_ex0
, extract_evuimm8_ex0
, PPC_OPERAND_PARENS
},
2850 /* The WS or DRM field in an X form instruction. */
2851 #define WS EVUIMM_8_EX0 + 1
2853 /* The NNN field in a VX form instruction for SPE2 */
2855 { 0x7, 11, NULL
, NULL
, 0 },
2857 /* PowerPC paired singles extensions. */
2858 /* W bit in the pair singles instructions for x type instructions. */
2860 /* The BO16 field in a BD8 form instruction. */
2862 { 0x1, 10, 0, 0, 0 },
2864 /* IDX bits for quantization in the pair singles instructions. */
2865 #define PSQ PSWM + 1
2866 { 0x7, 12, 0, 0, PPC_OPERAND_GQR
},
2868 /* IDX bits for quantization in the pair singles x-type instructions. */
2869 #define PSQM PSQ + 1
2870 { 0x7, 7, 0, 0, PPC_OPERAND_GQR
},
2872 /* Smaller D field for quantization in the pair singles instructions. */
2873 #define PSD PSQM + 1
2874 { 0xfff, 0, 0, 0, PPC_OPERAND_PARENS
| PPC_OPERAND_SIGNED
},
2876 /* The L field in an mtmsrd or A form instruction or R or W in an
2881 { 0x1, 16, NULL
, NULL
, PPC_OPERAND_OPTIONAL
},
2883 /* The RMC or CY field in a Z23 form instruction. */
2886 { 0x3, 9, NULL
, NULL
, 0 },
2890 { 0x1, 16, NULL
, NULL
, 0 },
2893 { 0x3, 18, NULL
, NULL
, PPC_OPERAND_OPTIONAL
},
2896 { 0x1, 17, NULL
, NULL
, PPC_OPERAND_OPTIONAL
},
2899 { 0x3, 19, NULL
, NULL
, 0 },
2902 { 0x1, 20, NULL
, NULL
, 0 },
2904 /* The S field in a XL form instruction. */
2906 { 0x1, 11, insert_sxl
, extract_sxl
, PPC_OPERAND_OPTIONAL
},
2908 /* SH field starting at bit position 16. */
2909 #define SH16 SXL + 1
2910 /* The DCM and DGM fields in a Z form instruction. */
2913 { 0x3f, 10, NULL
, NULL
, 0 },
2915 /* The EH field in larx instruction. */
2917 { 0x1, 0, NULL
, NULL
, PPC_OPERAND_OPTIONAL
},
2919 /* The L field in an mtfsf or XFL form instruction. */
2920 /* The A field in a HTM X form instruction. */
2921 #define XFL_L EH + 1
2923 { 0x1, 25, NULL
, NULL
, PPC_OPERAND_OPTIONAL
},
2925 /* Xilinx APU related masks and macros */
2926 #define FCRT XFL_L + 1
2927 #define FCRT_MASK (0x1f << 21)
2928 { 0x1f, 21, 0, 0, PPC_OPERAND_FCR
},
2930 /* Xilinx FSL related masks and macros */
2931 #define FSL FCRT + 1
2932 #define FSL_MASK (0x1f << 11)
2933 { 0x1f, 11, 0, 0, PPC_OPERAND_FSL
},
2935 /* Xilinx UDI related masks and macros */
2937 { 0x1f, 21, 0, 0, PPC_OPERAND_UDI
},
2940 { 0x1f, 16, 0, 0, PPC_OPERAND_UDI
},
2943 { 0x1f, 11, 0, 0, PPC_OPERAND_UDI
},
2946 { 0x1f, 6, 0, 0, PPC_OPERAND_UDI
},
2948 /* The VLESIMM field in a D form instruction. */
2949 #define VLESIMM URC + 1
2950 { 0xffff, PPC_OPSHIFT_INV
, insert_vlesi
, extract_vlesi
,
2951 PPC_OPERAND_SIGNED
| PPC_OPERAND_SIGNOPT
},
2953 /* The VLENSIMM field in a D form instruction. */
2954 #define VLENSIMM VLESIMM + 1
2955 { 0xffff, PPC_OPSHIFT_INV
, insert_vlensi
, extract_vlensi
,
2956 PPC_OPERAND_NEGATIVE
| PPC_OPERAND_SIGNED
| PPC_OPERAND_SIGNOPT
},
2958 /* The VLEUIMM field in a D form instruction. */
2959 #define VLEUIMM VLENSIMM + 1
2960 { 0xffff, PPC_OPSHIFT_INV
, insert_vleui
, extract_vleui
, 0 },
2962 /* The VLEUIMML field in a D form instruction. */
2963 #define VLEUIMML VLEUIMM + 1
2964 { 0xffff, PPC_OPSHIFT_INV
, insert_vleil
, extract_vleil
, 0 },
2966 /* The XT and XS fields in an XX1 or XX3 form instruction. This is
2968 #define XS6 VLEUIMML + 1
2970 { 0x3f, PPC_OPSHIFT_INV
, insert_xt6
, extract_xt6
, PPC_OPERAND_VSR
},
2972 /* The XT and XS fields in an DQ form VSX instruction. This is split. */
2973 #define XSQ6 XT6 + 1
2975 { 0x3f, PPC_OPSHIFT_INV
, insert_xtq6
, extract_xtq6
, PPC_OPERAND_VSR
},
2977 /* The split XTp field in a vector paired instruction. */
2978 #define XTP XSQ6 + 1
2979 { 0x3e, PPC_OPSHIFT_INV
, insert_xtp
, extract_xtp
, PPC_OPERAND_VSR
},
2982 { 0x3f, PPC_OPSHIFT_INV
, insert_xts
, extract_xts
, PPC_OPERAND_VSR
},
2984 /* The XT field in a plxv instruction. Runs into the OP field. */
2985 #define XTOP XTS + 1
2986 { 0x3f, 21, NULL
, NULL
, PPC_OPERAND_VSR
},
2988 /* The XA field in an XX3 form instruction. This is split. */
2989 #define XA6 XTOP + 1
2990 { 0x3f, PPC_OPSHIFT_INV
, insert_xa6
, extract_xa6
, PPC_OPERAND_VSR
},
2992 /* The XA field in an MMA XX3 form instruction. This is split and
2993 must not overlap with the ACC operand. */
2994 #define XA6a XA6 + 1
2995 { 0x3f, PPC_OPSHIFT_INV
, insert_xa6a
, extract_xa6a
, PPC_OPERAND_VSR
},
2997 /* The XAp field in an MMA XX3 form instruction. This is split.
2998 This is like XA6a, but must be even. */
2999 #define XA6ap XA6a + 1
3000 { 0x3e, PPC_OPSHIFT_INV
, insert_xa6a
, extract_xa6a
, PPC_OPERAND_VSR
},
3002 /* The XB field in an XX2 or XX3 form instruction. This is split. */
3003 #define XB6 XA6ap + 1
3004 { 0x3f, PPC_OPSHIFT_INV
, insert_xb6
, extract_xb6
, PPC_OPERAND_VSR
},
3006 /* The XB field in an XX3 form instruction. This is split and
3007 must not overlap with the ACC operand. */
3008 #define XB6a XB6 + 1
3009 { 0x3f, PPC_OPSHIFT_INV
, insert_xb6a
, extract_xb6a
, PPC_OPERAND_VSR
},
3011 /* The XA and XB fields in an XX3 form instruction when they must be the same.
3012 This is used in extended mnemonics like xvmovdp. This is split. */
3013 #define XAB6 XB6a + 1
3014 { 0x3f, PPC_OPSHIFT_INV
, insert_xab6
, extract_xab6
, PPC_OPERAND_VSR
},
3016 /* The XC field in an XX4 form instruction. This is split. */
3017 #define XC6 XAB6 + 1
3018 { 0x3f, PPC_OPSHIFT_INV
, insert_xc6
, extract_xc6
, PPC_OPERAND_VSR
},
3020 /* The DM or SHW field in an XX3 form instruction. */
3023 { 0x3, 8, NULL
, NULL
, 0 },
3025 /* The DM field in an extended mnemonic XX3 form instruction. */
3027 { 0x3, 8, insert_dm
, extract_dm
, 0 },
3029 /* The UIM field in an XX2 form instruction. */
3030 #define UIM DMEX + 1
3031 /* The 2-bit UIMM field in a VX form instruction. */
3033 /* The 2-bit L field in a darn instruction. */
3035 { 0x3, 16, NULL
, NULL
, 0 },
3037 #define ERAT_T UIM + 1
3038 { 0x7, 21, NULL
, NULL
, 0 },
3040 #define IH ERAT_T + 1
3041 { 0x7, 21, NULL
, NULL
, PPC_OPERAND_OPTIONAL
},
3043 /* The 8-bit IMM8 field in a XX1 form instruction. */
3045 { 0xff, 11, NULL
, NULL
, PPC_OPERAND_SIGNOPT
},
3047 #define VX_OFF IMM8 + 1
3048 { 0x3, 0, insert_off_lsp
, extract_off_lsp
, 0 },
3050 #define VX_OFF_SPE2 VX_OFF + 1
3051 { 0x7, 0, insert_off_spe2
, extract_off_spe2
, 0 },
3053 #define BBB VX_OFF_SPE2 + 1
3054 { 0x7, 13, NULL
, NULL
, 0 },
3057 #define VX_MASK_DDD (VX_MASK & ~0x1)
3058 { 0x7, PPC_OPSHIFT_INV
, insert_Ddd
, extract_Ddd
, 0 },
3061 { 0x3, 13, NULL
, NULL
, 0 },
3064 const unsigned int num_powerpc_operands
= (sizeof (powerpc_operands
)
3065 / sizeof (powerpc_operands
[0]));
3067 /* Macros used to form opcodes. */
3069 /* The main opcode. */
3070 #define OP(x) ((((uint64_t)(x)) & 0x3f) << 26)
3071 #define OP_MASK OP (0x3f)
3073 /* The prefix opcode. */
3074 #define PREFIX_OP (1ULL << 58)
3076 /* The 2-bit prefix form. */
3077 #define PREFIX_FORM(x) ((x & 3ULL) << 56)
3079 #define SUFFIX_MASK ((1ULL << 32) - 1)
3080 #define PREFIX_MASK (SUFFIX_MASK << 32)
3082 /* Prefix insn, eight byte load/store form 8LS. */
3083 #define P8LS (PREFIX_OP | PREFIX_FORM (0))
3085 /* Prefix insn, eight byte register to register form 8RR. */
3086 #define P8RR (PREFIX_OP | PREFIX_FORM (1))
3088 /* Prefix insn, modified load/store form MLS. */
3089 #define PMLS (PREFIX_OP | PREFIX_FORM (2))
3091 /* Prefix insn, modified register to register form MRR. */
3092 #define PMRR (PREFIX_OP | PREFIX_FORM (3))
3094 /* Prefix insn, modified masked immediate register to register form MMIRR. */
3095 #define PMMIRR (PREFIX_OP | PREFIX_FORM (3) | (9ULL << 52))
3097 /* An 8-byte D form prefix instruction. */
3098 #define P_D_MASK (((-1ULL << 50) & ~PCREL_MASK) | OP_MASK)
3100 /* The same as P_D_MASK, but with the RA and PCREL fields specified. */
3101 #define P_DRAPCREL_MASK (P_D_MASK | PCREL_MASK | RA_MASK)
3103 /* Mask for prefix X form instructions. */
3104 #define P_X_MASK (PREFIX_MASK | X_MASK)
3105 #define P_XX1_MASK (PREFIX_MASK | XX1_MASK)
3107 /* Mask for prefix vector permute insns. */
3108 #define P_XX4_MASK (PREFIX_MASK | XX4_MASK)
3109 #define P_UXX4_MASK (P_XX4_MASK & ~(7ULL << 32))
3111 /* MMIRR:XX3-form 8-byte outer product instructions. */
3112 #define P_GER_MASK ((-1ULL << 40) | XX3_MASK | (3 << 21) | 1)
3113 #define P_GER2_MASK (P_GER_MASK & ~(3ULL << 46))
3114 #define P_GER4_MASK (P_GER_MASK & ~(15ULL << 44))
3115 #define P_GER8_MASK (P_GER_MASK & ~(255ULL << 40))
3116 #define P_GER64_MASK (P_GER_MASK | (3ULL << 32))
3118 /* Vector splat immediate op. */
3119 #define VSOP(op, xop) (OP (op) | (xop << 17))
3120 #define P_VS_MASK ((-1ULL << 48) | VSOP (0x3f, 0xf))
3121 #define P_VSI_MASK ((-1ULL << 48) | VSOP (0x3f, 0xe))
3123 /* The main opcode combined with a trap code in the TO field of a D
3124 form instruction. Used for extended mnemonics for the trap
3126 #define OPTO(x,to) (OP (x) | ((((uint64_t)(to)) & 0x1f) << 21))
3127 #define OPTO_MASK (OP_MASK | TO_MASK)
3129 /* The main opcode combined with a comparison size bit in the L field
3130 of a D form or X form instruction. Used for extended mnemonics for
3131 the comparison instructions. */
3132 #define OPL(x,l) (OP (x) | ((((uint64_t)(l)) & 1) << 21))
3133 #define OPL_MASK OPL (0x3f,1)
3135 /* The main opcode combined with an update code in D form instruction.
3136 Used for extended mnemonics for VLE memory instructions. */
3137 #define OPVUP(x,vup) (OP (x) | ((((uint64_t)(vup)) & 0xff) << 8))
3138 #define OPVUP_MASK OPVUP (0x3f, 0xff)
3140 /* The main opcode combined with an update code and the RT fields
3141 specified in D form instruction. Used for VLE volatile context
3142 save/restore instructions. */
3143 #define OPVUPRT(x,vup,rt) \
3145 | ((((uint64_t)(rt)) & 0x1f) << 21))
3146 #define OPVUPRT_MASK OPVUPRT (0x3f, 0xff, 0x1f)
3148 /* An A form instruction. */
3149 #define A(op, xop, rc) \
3151 | ((((uint64_t)(xop)) & 0x1f) << 1) \
3152 | (((uint64_t)(rc)) & 1))
3153 #define A_MASK A (0x3f, 0x1f, 1)
3155 /* An A_MASK with the FRB field fixed. */
3156 #define AFRB_MASK (A_MASK | FRB_MASK)
3158 /* An A_MASK with the FRC field fixed. */
3159 #define AFRC_MASK (A_MASK | FRC_MASK)
3161 /* An A_MASK with the FRA and FRC fields fixed. */
3162 #define AFRAFRC_MASK (A_MASK | FRA_MASK | FRC_MASK)
3164 /* An AFRAFRC_MASK, but with L bit clear. */
3165 #define AFRALFRC_MASK (AFRAFRC_MASK & ~((uint64_t) 1 << 16))
3167 /* A B form instruction. */
3168 #define B(op, aa, lk) \
3170 | ((((uint64_t)(aa)) & 1) << 1) \
3172 #define B_MASK B (0x3f, 1, 1)
3174 /* A BD8 form instruction. This is a 16-bit instruction. */
3175 #define BD8(op, aa, lk) \
3176 (((((uint64_t)(op)) & 0x3f) << 10) \
3177 | (((aa) & 1) << 9) \
3178 | (((lk) & 1) << 8))
3179 #define BD8_MASK BD8 (0x3f, 1, 1)
3181 /* Another BD8 form instruction. This is a 16-bit instruction. */
3182 #define BD8IO(op) ((((uint64_t)(op)) & 0x1f) << 11)
3183 #define BD8IO_MASK BD8IO (0x1f)
3185 /* A BD8 form instruction for simplified mnemonics. */
3186 #define EBD8IO(op, bo, bi) (BD8IO ((op)) | ((bo) << 10) | ((bi) << 8))
3187 /* A mask that excludes BO32 and BI32. */
3188 #define EBD8IO1_MASK 0xf800
3189 /* A mask that includes BO32 and excludes BI32. */
3190 #define EBD8IO2_MASK 0xfc00
3191 /* A mask that include BO32 AND BI32. */
3192 #define EBD8IO3_MASK 0xff00
3194 /* A BD15 form instruction. */
3195 #define BD15(op, aa, lk) \
3197 | ((((uint64_t)(aa)) & 0xf) << 22) \
3199 #define BD15_MASK BD15 (0x3f, 0xf, 1)
3201 /* A BD15 form instruction for extended conditional branch mnemonics. */
3202 #define EBD15(op, aa, bo, lk) \
3203 (((op) & 0x3fu) << 26) \
3204 | (((aa) & 0xf) << 22) \
3205 | (((bo) & 0x3) << 20) \
3207 #define EBD15_MASK 0xfff00001
3209 /* A BD15 form instruction for extended conditional branch mnemonics
3211 #define EBD15BI(op, aa, bo, bi, lk) \
3212 ((((op) & 0x3fu) << 26) \
3213 | (((aa) & 0xf) << 22) \
3214 | (((bo) & 0x3) << 20) \
3215 | (((bi) & 0x3) << 16) \
3218 #define EBD15BI_MASK 0xfff30001
3220 /* A BD24 form instruction. */
3221 #define BD24(op, aa, lk) \
3223 | ((((uint64_t)(aa)) & 1) << 25) \
3225 #define BD24_MASK BD24 (0x3f, 1, 1)
3227 /* A B form instruction setting the BO field. */
3228 #define BBO(op, bo, aa, lk) \
3229 (B ((op), (aa), (lk)) \
3230 | ((((uint64_t)(bo)) & 0x1f) << 21))
3231 #define BBO_MASK BBO (0x3f, 0x1f, 1, 1)
3233 /* A BBO_MASK with the y bit of the BO field removed. This permits
3234 matching a conditional branch regardless of the setting of the y
3235 bit. Similarly for the 'at' bits used for power4 branch hints. */
3236 #define Y_MASK (((uint64_t) 1) << 21)
3237 #define AT1_MASK (((uint64_t) 3) << 21)
3238 #define AT2_MASK (((uint64_t) 9) << 21)
3239 #define BBOY_MASK (BBO_MASK &~ Y_MASK)
3240 #define BBOAT_MASK (BBO_MASK &~ AT1_MASK)
3242 /* A B form instruction setting the BO field and the condition bits of
3244 #define BBOCB(op, bo, cb, aa, lk) \
3245 (BBO ((op), (bo), (aa), (lk)) | ((((uint64_t)(cb)) & 0x3) << 16))
3246 #define BBOCB_MASK BBOCB (0x3f, 0x1f, 0x3, 1, 1)
3248 /* A BBOCB_MASK with the y bit of the BO field removed. */
3249 #define BBOYCB_MASK (BBOCB_MASK &~ Y_MASK)
3250 #define BBOATCB_MASK (BBOCB_MASK &~ AT1_MASK)
3251 #define BBOAT2CB_MASK (BBOCB_MASK &~ AT2_MASK)
3253 /* A BBOYCB_MASK in which the BI field is fixed. */
3254 #define BBOYBI_MASK (BBOYCB_MASK | BI_MASK)
3255 #define BBOATBI_MASK (BBOAT2CB_MASK | BI_MASK)
3257 /* A VLE C form instruction. */
3258 #define C_LK(x, lk) (((((uint64_t)(x)) & 0x7fff) << 1) | ((lk) & 1))
3259 #define C_LK_MASK C_LK(0x7fff, 1)
3260 #define C(x) ((((uint64_t)(x)) & 0xffff))
3261 #define C_MASK C(0xffff)
3263 /* An Context form instruction. */
3264 #define CTX(op, xop) (OP (op) | (((uint64_t)(xop)) & 0x7))
3265 #define CTX_MASK CTX(0x3f, 0x7)
3267 /* An User Context form instruction. */
3268 #define UCTX(op, xop) (OP (op) | (((uint64_t)(xop)) & 0x1f))
3269 #define UCTX_MASK UCTX(0x3f, 0x1f)
3271 /* The main opcode mask with the RA field clear. */
3272 #define DRA_MASK (OP_MASK | RA_MASK)
3274 /* A DQ form VSX instruction. */
3275 #define DQX(op, xop) (OP (op) | ((xop) & 0x7))
3276 #define DQX_MASK DQX (0x3f, 7)
3278 /* A DQ form VSX vector paired instruction. */
3279 #define DQXP(op, xop) (OP (op) | ((xop) & 0xf))
3280 #define DQXP_MASK DQXP (0x3f, 0xf)
3282 /* A DS form instruction. */
3283 #define DSO(op, xop) (OP (op) | ((xop) & 0x3))
3284 #define DS_MASK DSO (0x3f, 3)
3286 /* An DX form instruction. */
3287 #define DX(op, xop) (OP (op) | ((((uint64_t)(xop)) & 0x1f) << 1))
3288 #define DX_MASK DX (0x3f, 0x1f)
3289 /* An DX form instruction with the D bits specified. */
3290 #define NODX_MASK (DX_MASK | 0x1fffc1)
3292 /* An EVSEL form instruction. */
3293 #define EVSEL(op, xop) (OP (op) | (((uint64_t)(xop)) & 0xff) << 3)
3294 #define EVSEL_MASK EVSEL(0x3f, 0xff)
3296 /* An IA16 form instruction. */
3297 #define IA16(op, xop) (OP (op) | (((uint64_t)(xop)) & 0x1f) << 11)
3298 #define IA16_MASK IA16(0x3f, 0x1f)
3300 /* An I16A form instruction. */
3301 #define I16A(op, xop) (OP (op) | (((uint64_t)(xop)) & 0x1f) << 11)
3302 #define I16A_MASK I16A(0x3f, 0x1f)
3304 /* An I16L form instruction. */
3305 #define I16L(op, xop) (OP (op) | (((uint64_t)(xop)) & 0x1f) << 11)
3306 #define I16L_MASK I16L(0x3f, 0x1f)
3308 /* An IM7 form instruction. */
3309 #define IM7(op) ((((uint64_t)(op)) & 0x1f) << 11)
3310 #define IM7_MASK IM7(0x1f)
3312 /* An M form instruction. */
3313 #define M(op, rc) (OP (op) | ((rc) & 1))
3314 #define M_MASK M (0x3f, 1)
3316 /* An LI20 form instruction. */
3317 #define LI20(op, xop) (OP (op) | (((uint64_t)(xop)) & 0x1) << 15)
3318 #define LI20_MASK LI20(0x3f, 0x1)
3320 /* An M form instruction with the ME field specified. */
3321 #define MME(op, me, rc) \
3323 | ((((uint64_t)(me)) & 0x1f) << 1))
3325 /* An M_MASK with the MB and ME fields fixed. */
3326 #define MMBME_MASK (M_MASK | MB_MASK | ME_MASK)
3328 /* An M_MASK with the SH and ME fields fixed. */
3329 #define MSHME_MASK (M_MASK | SH_MASK | ME_MASK)
3331 /* An MD form instruction. */
3332 #define MD(op, xop, rc) \
3334 | ((((uint64_t)(xop)) & 0x7) << 2) \
3336 #define MD_MASK MD (0x3f, 0x7, 1)
3338 /* An MD_MASK with the MB field fixed. */
3339 #define MDMB_MASK (MD_MASK | MB6_MASK)
3341 /* An MD_MASK with the SH field fixed. */
3342 #define MDSH_MASK (MD_MASK | SH6_MASK)
3344 /* An MDS form instruction. */
3345 #define MDS(op, xop, rc) \
3347 | ((((uint64_t)(xop)) & 0xf) << 1) \
3349 #define MDS_MASK MDS (0x3f, 0xf, 1)
3351 /* An MDS_MASK with the MB field fixed. */
3352 #define MDSMB_MASK (MDS_MASK | MB6_MASK)
3354 /* An SC form instruction. */
3355 #define SC(op, sa, lk) \
3357 | ((((uint64_t)(sa)) & 1) << 1) \
3361 | (((uint64_t) 0x3ff) << 16) \
3362 | (((uint64_t) 1) << 1) \
3365 /* An SCI8 form instruction. */
3366 #define SCI8(op, xop) (OP (op) | ((((uint64_t)(xop)) & 0x1f) << 11))
3367 #define SCI8_MASK SCI8(0x3f, 0x1f)
3369 /* An SCI8 form instruction. */
3370 #define SCI8BF(op, fop, xop) \
3372 | ((((uint64_t)(xop)) & 0x1f) << 11) \
3373 | (((fop) & 7) << 23))
3374 #define SCI8BF_MASK SCI8BF(0x3f, 7, 0x1f)
3376 /* An SD4 form instruction. This is a 16-bit instruction. */
3377 #define SD4(op) ((((uint64_t)(op)) & 0xf) << 12)
3378 #define SD4_MASK SD4(0xf)
3380 /* An SE_IM5 form instruction. This is a 16-bit instruction. */
3381 #define SE_IM5(op, xop) \
3382 (((((uint64_t)(op)) & 0x3f) << 10) \
3383 | (((xop) & 0x1) << 9))
3384 #define SE_IM5_MASK SE_IM5(0x3f, 1)
3386 /* An SE_R form instruction. This is a 16-bit instruction. */
3387 #define SE_R(op, xop) \
3388 (((((uint64_t)(op)) & 0x3f) << 10) \
3389 | (((xop) & 0x3f) << 4))
3390 #define SE_R_MASK SE_R(0x3f, 0x3f)
3392 /* An SE_RR form instruction. This is a 16-bit instruction. */
3393 #define SE_RR(op, xop) \
3394 (((((uint64_t)(op)) & 0x3f) << 10) \
3395 | (((xop) & 0x3) << 8))
3396 #define SE_RR_MASK SE_RR(0x3f, 3)
3398 /* A VX form instruction. */
3399 #define VX(op, xop) (OP (op) | (((uint64_t)(xop)) & 0x7ff))
3401 /* The mask for an VX form instruction. */
3402 #define VX_MASK VX(0x3f, 0x7ff)
3404 /* A VX LSP form instruction. */
3405 #define VX_LSP(op, xop) (OP (op) | (((uint64_t)(xop)) & 0xffff))
3407 /* The mask for an VX LSP form instruction. */
3408 #define VX_LSP_MASK VX_LSP(0x3f, 0xffff)
3409 #define VX_LSP_OFF_MASK VX_LSP(0x3f, 0x7fc)
3411 /* Additional format of VX SPE2 form instruction. */
3412 #define VX_RA_CONST(op, xop, bits11_15) \
3414 | (((uint64_t)(bits11_15) & 0x1f) << 16) \
3415 | (((uint64_t)(xop)) & 0x7ff))
3416 #define VX_RA_CONST_MASK VX_RA_CONST(0x3f, 0x7ff, 0x1f)
3418 #define VX_RB_CONST(op, xop, bits16_20) \
3420 | (((uint64_t)(bits16_20) & 0x1f) << 11) \
3421 | (((uint64_t)(xop)) & 0x7ff))
3422 #define VX_RB_CONST_MASK VX_RB_CONST(0x3f, 0x7ff, 0x1f)
3424 #define VX_OFF_SPE2_MASK VX(0x3f, 0x7f8)
3426 #define VX_SPE_CRFD(op, xop, bits9_10) \
3428 | (((uint64_t)(bits9_10) & 0x3) << 21) \
3429 | (((uint64_t)(xop)) & 0x7ff))
3430 #define VX_SPE_CRFD_MASK VX_SPE_CRFD(0x3f, 0x7ff, 0x3)
3432 #define VX_SPE2_CLR(op, xop, bit16) \
3434 | (((uint64_t)(bit16) & 0x1) << 15) \
3435 | (((uint64_t)(xop)) & 0x7ff))
3436 #define VX_SPE2_CLR_MASK VX_SPE2_CLR(0x3f, 0x7ff, 0x1)
3438 #define VX_SPE2_SPLATB(op, xop, bits19_20) \
3440 | (((uint64_t)(bits19_20) & 0x3) << 11) \
3441 | (((uint64_t)(xop)) & 0x7ff))
3442 #define VX_SPE2_SPLATB_MASK VX_SPE2_SPLATB(0x3f, 0x7ff, 0x3)
3444 #define VX_SPE2_OCTET(op, xop, bits16_17) \
3446 | (((uint64_t)(bits16_17) & 0x3) << 14) \
3447 | (((uint64_t)(xop)) & 0x7ff))
3448 #define VX_SPE2_OCTET_MASK VX_SPE2_OCTET(0x3f, 0x7ff, 0x7)
3450 #define VX_SPE2_DDHH(op, xop, bit16) \
3452 | (((uint64_t)(bit16) & 0x1) << 15) \
3453 | (((uint64_t)(xop)) & 0x7ff))
3454 #define VX_SPE2_DDHH_MASK VX_SPE2_DDHH(0x3f, 0x7ff, 0x1)
3456 #define VX_SPE2_HH(op, xop, bit16, bits19_20) \
3458 | (((uint64_t)(bit16) & 0x1) << 15) \
3459 | (((uint64_t)(bits19_20) & 0x3) << 11) \
3460 | (((uint64_t)(xop)) & 0x7ff))
3461 #define VX_SPE2_HH_MASK VX_SPE2_HH(0x3f, 0x7ff, 0x1, 0x3)
3463 #define VX_SPE2_EVMAR(op, xop) \
3465 | ((uint64_t)(0x1) << 11) \
3466 | (((uint64_t)(xop)) & 0x7ff))
3467 #define VX_SPE2_EVMAR_MASK \
3468 (VX_SPE2_EVMAR(0x3f, 0x7ff) \
3469 | ((uint64_t)(0x1) << 11))
3471 /* A VX_MASK with the VA field fixed. */
3472 #define VXVA_MASK (VX_MASK | (0x1f << 16))
3474 /* A VX_MASK with the VB field fixed. */
3475 #define VXVB_MASK (VX_MASK | (0x1f << 11))
3477 /* A VX_MASK with the VA and VB fields fixed. */
3478 #define VXVAVB_MASK (VX_MASK | (0x1f << 16) | (0x1f << 11))
3480 /* A VX_MASK with the VD and VA fields fixed. */
3481 #define VXVDVA_MASK (VX_MASK | (0x1f << 21) | (0x1f << 16))
3483 /* A VX_MASK with a UIMM4 field. */
3484 #define VXUIMM4_MASK (VX_MASK | (0x1 << 20))
3486 /* A VX_MASK with a UIMM3 field. */
3487 #define VXUIMM3_MASK (VX_MASK | (0x3 << 19))
3489 /* A VX_MASK with a UIMM2 field. */
3490 #define VXUIMM2_MASK (VX_MASK | (0x7 << 18))
3492 /* A VX_MASK with a PS field. */
3493 #define VXPS_MASK (VX_MASK & ~(0x1 << 9))
3495 /* A VX_MASK with the VA field fixed with a PS field. */
3496 #define VXVAPS_MASK (VXVA_MASK & ~(0x1 << 9))
3498 /* A VX_MASK with the VA field fixed with a MP field. */
3499 #define VXVAM_MASK (VXVA_MASK & ~(0x1 << 16))
3501 /* A VX_MASK for instructions using a BF field. */
3502 #define VXBF_MASK (VX_MASK | (3 << 21))
3504 /* A VX_MASK for instructions with an RC field. */
3505 #define VXRC_MASK (VX_MASK & ~(0x1f << 6))
3507 /* A VX_MASK for instructions with a SH field. */
3508 #define VXSH_MASK (VX_MASK & ~(0x7 << 6))
3510 /* A VA form instruction. */
3511 #define VXA(op, xop) (OP (op) | (((uint64_t)(xop)) & 0x03f))
3513 /* The mask for an VA form instruction. */
3514 #define VXA_MASK VXA(0x3f, 0x3f)
3516 /* A VXA_MASK with a SHB field. */
3517 #define VXASHB_MASK (VXA_MASK | (1 << 10))
3519 /* A VXR form instruction. */
3520 #define VXR(op, xop, rc) \
3522 | (((uint64_t)(rc) & 1) << 10) \
3523 | (((uint64_t)(xop)) & 0x3ff))
3525 /* The mask for a VXR form instruction. */
3526 #define VXR_MASK VXR(0x3f, 0x3ff, 1)
3528 /* A VX form instruction with a VA tertiary opcode. */
3529 #define VXVA(op, xop, vaop) (VX(op,xop) | (((vaop) & 0x1f) << 16))
3531 #define VXASH(op, xop) (OP (op) | ((((uint64_t)(xop)) & 0x1f) << 1))
3532 #define VXASH_MASK VXASH (0x3f, 0x1f)
3534 /* An X form instruction. */
3535 #define X(op, xop) (OP (op) | ((((uint64_t)(xop)) & 0x3ff) << 1))
3537 /* A X form instruction for Quad-Precision FP Instructions. */
3538 #define XVA(op, xop, vaop) (X(op,xop) | (((vaop) & 0x1f) << 16))
3540 /* An EX form instruction. */
3541 #define EX(op, xop) (OP (op) | (((uint64_t)(xop)) & 0x7ff))
3543 /* The mask for an EX form instruction. */
3544 #define EX_MASK EX (0x3f, 0x7ff)
3546 /* An XX2 form instruction. */
3547 #define XX2(op, xop) (OP (op) | ((((uint64_t)(xop)) & 0x1ff) << 2))
3549 /* A XX2 form instruction with the VA bits specified. */
3550 #define XX2VA(op, xop, vaop) (XX2(op,xop) | (((vaop) & 0x1f) << 16))
3552 /* An XX3 form instruction. */
3553 #define XX3(op, xop) (OP (op) | ((((uint64_t)(xop)) & 0xff) << 3))
3555 /* An XX3 form instruction with the RC bit specified. */
3556 #define XX3RC(op, xop, rc) \
3558 | (((uint64_t)(rc) & 1) << 10) \
3559 | ((((uint64_t)(xop)) & 0x7f) << 3))
3561 /* An XX4 form instruction. */
3562 #define XX4(op, xop) (OP (op) | ((((uint64_t)(xop)) & 0x3) << 4))
3564 /* A Z form instruction. */
3565 #define Z(op, xop) (OP (op) | ((((uint64_t)(xop)) & 0x1ff) << 1))
3567 /* An X form instruction with the RC bit specified. */
3568 #define XRC(op, xop, rc) (X ((op), (xop)) | ((rc) & 1))
3570 /* A X form instruction for Quad-Precision FP Instructions with RC bit. */
3571 #define XVARC(op, xop, vaop, rc) (XVA ((op), (xop), (vaop)) | ((rc) & 1))
3573 /* An X form instruction with the RA bits specified as two ops. */
3574 #define XMMF(op, xop, mop0, mop1) \
3576 | ((mop0) & 3) << 19 \
3577 | ((mop1) & 7) << 16)
3579 /* A Z form instruction with the RC bit specified. */
3580 #define ZRC(op, xop, rc) (Z ((op), (xop)) | ((rc) & 1))
3582 /* The mask for an X form instruction. */
3583 #define X_MASK XRC (0x3f, 0x3ff, 1)
3585 /* The mask for an X form instruction with the BF bits specified. */
3586 #define XBF_MASK (X_MASK | (3 << 21))
3588 /* An X form wait instruction with everything filled in except the WC
3590 #define XWC_MASK (XRC (0x3f, 0x3ff, 1) | (7 << 23) | RA_MASK | RB_MASK)
3592 /* The mask for an XX1 form instruction. */
3593 #define XX1_MASK X (0x3f, 0x3ff)
3595 /* An XX1_MASK with the RB field fixed. */
3596 #define XX1RB_MASK (XX1_MASK | RB_MASK)
3598 /* The mask for an XX2 form instruction. */
3599 #define XX2_MASK (XX2 (0x3f, 0x1ff) | (0x1f << 16))
3601 /* The mask for an XX2 form instruction with the UIM bits specified. */
3602 #define XX2UIM_MASK (XX2 (0x3f, 0x1ff) | (7 << 18))
3604 /* The mask for an XX2 form instruction with the 4 UIM bits specified. */
3605 #define XX2UIM4_MASK (XX2 (0x3f, 0x1ff) | (1 << 20))
3607 /* The mask for an XX2 form instruction with the BF bits specified. */
3608 #define XX2BF_MASK (XX2_MASK | (3 << 21) | (1))
3610 /* The mask for an XX2 form instruction with the BF and DCMX bits
3612 #define XX2BFD_MASK (XX2 (0x3f, 0x1ff) | 1)
3614 /* The mask for an XX2 form instruction with a split DCMX bits
3616 #define XX2DCMXS_MASK XX2 (0x3f, 0x1ee)
3618 /* The mask for an XX3 form instruction. */
3619 #define XX3_MASK XX3 (0x3f, 0xff)
3621 /* The mask for an XX3 form instruction with the BF bits specified. */
3622 #define XX3BF_MASK (XX3 (0x3f, 0xff) | (3 << 21) | (1))
3624 /* The mask for an XX3 form instruction with the DM or SHW bits
3626 #define XX3DM_MASK (XX3 (0x3f, 0x1f) | (1 << 10))
3627 #define XX3SHW_MASK XX3DM_MASK
3629 /* The mask for an XX4 form instruction. */
3630 #define XX4_MASK XX4 (0x3f, 0x3)
3632 /* An X form wait instruction with everything filled in except the WC
3634 #define XWC_MASK (XRC (0x3f, 0x3ff, 1) | (7 << 23) | RA_MASK | RB_MASK)
3636 /* The mask for an XMMF form instruction. */
3637 #define XMMF_MASK (XMMF (0x3f, 0x3ff, 3, 7) | (1))
3639 /* The mask for a Z form instruction. */
3640 #define Z_MASK ZRC (0x3f, 0x1ff, 1)
3641 #define Z2_MASK ZRC (0x3f, 0xff, 1)
3643 /* An X_MASK with the RA/VA field fixed. */
3644 #define XRA_MASK (X_MASK | RA_MASK)
3645 #define XVA_MASK XRA_MASK
3647 /* An XRA_MASK with the A_L/W field clear. */
3648 #define XWRA_MASK (XRA_MASK & ~((uint64_t) 1 << 16))
3649 #define XRLA_MASK XWRA_MASK
3651 /* An X_MASK with the RB field fixed. */
3652 #define XRB_MASK (X_MASK | RB_MASK)
3654 /* An X_MASK with the RT field fixed. */
3655 #define XRT_MASK (X_MASK | RT_MASK)
3657 /* An XRT_MASK mask with the L bits clear. */
3658 #define XLRT_MASK (XRT_MASK & ~((uint64_t) 0x3 << 21))
3660 /* An X_MASK with the RA and RB fields fixed. */
3661 #define XRARB_MASK (X_MASK | RA_MASK | RB_MASK)
3663 /* An XBF_MASK with the RA and RB fields fixed. */
3664 #define XBFRARB_MASK (XBF_MASK | RA_MASK | RB_MASK)
3666 /* An XRARB_MASK, but with the L bit clear. */
3667 #define XRLARB_MASK (XRARB_MASK & ~((uint64_t) 1 << 16))
3669 /* An XRARB_MASK, but with the L bits in a darn instruction clear. */
3670 #define XLRAND_MASK (XRARB_MASK & ~((uint64_t) 3 << 16))
3672 /* An X_MASK with the RT and RA fields fixed. */
3673 #define XRTRA_MASK (X_MASK | RT_MASK | RA_MASK)
3675 /* An X_MASK with the RT and RB fields fixed. */
3676 #define XRTRB_MASK (X_MASK | RT_MASK | RB_MASK)
3678 /* An XRTRA_MASK, but with L bit clear. */
3679 #define XRTLRA_MASK (XRTRA_MASK & ~((uint64_t) 1 << 21))
3681 /* An X_MASK with the RT, RA and RB fields fixed. */
3682 #define XRTRARB_MASK (X_MASK | RT_MASK | RA_MASK | RB_MASK)
3684 /* An XRTRARB_MASK, but with L bit clear. */
3685 #define XRTLRARB_MASK (XRTRARB_MASK & ~((uint64_t) 1 << 21))
3687 /* An XRTRARB_MASK, but with A bit clear. */
3688 #define XRTARARB_MASK (XRTRARB_MASK & ~((uint64_t) 1 << 25))
3690 /* An XRTRARB_MASK, but with BF bits clear. */
3691 #define XRTBFRARB_MASK (XRTRARB_MASK & ~((uint64_t) 7 << 23))
3693 /* An X form instruction with the L bit specified. */
3694 #define XOPL(op, xop, l) \
3696 | ((((uint64_t)(l)) & 1) << 21))
3698 /* An X form instruction with the L bits specified. */
3699 #define XOPL2(op, xop, l) \
3701 | ((((uint64_t)(l)) & 3) << 21))
3703 /* An X form instruction with the L bit and RC bit specified. */
3704 #define XRCL(op, xop, l, rc) \
3705 (XRC ((op), (xop), (rc)) \
3706 | ((((uint64_t)(l)) & 1) << 21))
3708 /* An X form instruction with RT fields specified */
3709 #define XRT(op, xop, rt) \
3711 | ((((uint64_t)(rt)) & 0x1f) << 21))
3713 /* An X form instruction with RT and RA fields specified */
3714 #define XRTRA(op, xop, rt, ra) \
3716 | ((((uint64_t)(rt)) & 0x1f) << 21) \
3717 | ((((uint64_t)(ra)) & 0x1f) << 16))
3719 /* The mask for an X form comparison instruction. */
3720 #define XCMP_MASK (X_MASK | (((uint64_t)1) << 22))
3722 /* The mask for an X form comparison instruction with the L field
3724 #define XCMPL_MASK (XCMP_MASK | (((uint64_t)1) << 21))
3726 /* An X form trap instruction with the TO field specified. */
3727 #define XTO(op, xop, to) \
3729 | ((((uint64_t)(to)) & 0x1f) << 21))
3730 #define XTO_MASK (X_MASK | TO_MASK)
3732 /* An X form tlb instruction with the SH field specified. */
3733 #define XTLB(op, xop, sh) \
3735 | ((((uint64_t)(sh)) & 0x1f) << 11))
3736 #define XTLB_MASK (X_MASK | SH_MASK)
3738 /* An X form sync instruction. */
3739 #define XSYNC(op, xop, l) \
3741 | ((((uint64_t)(l)) & 3) << 21))
3743 /* An X form sync instruction with everything filled in except the LS
3745 #define XSYNC_MASK (0xff9fffff)
3747 /* An X form sync instruction with everything filled in except the L
3749 #define XSYNCLE_MASK (0xff90ffff)
3751 /* An X_MASK, but with the EH bit clear. */
3752 #define XEH_MASK (X_MASK & ~((uint64_t )1))
3754 /* An X form AltiVec dss instruction. */
3755 #define XDSS(op, xop, a) (X ((op), (xop)) | ((((uint64_t)(a)) & 1) << 25))
3756 #define XDSS_MASK XDSS(0x3f, 0x3ff, 1)
3758 /* An XFL form instruction. */
3759 #define XFL(op, xop, rc) \
3761 | ((((uint64_t)(xop)) & 0x3ff) << 1) \
3762 | (((uint64_t)(rc)) & 1))
3763 #define XFL_MASK XFL (0x3f, 0x3ff, 1)
3765 /* An X form isel instruction. */
3766 #define XISEL(op, xop) (OP (op) | ((((uint64_t)(xop)) & 0x1f) << 1))
3767 #define XISEL_MASK XISEL(0x3f, 0x1f)
3769 /* An XL form instruction with the LK field set to 0. */
3770 #define XL(op, xop) (OP (op) | ((((uint64_t)(xop)) & 0x3ff) << 1))
3772 /* An XL form instruction which uses the LK field. */
3773 #define XLLK(op, xop, lk) (XL ((op), (xop)) | ((lk) & 1))
3775 /* The mask for an XL form instruction. */
3776 #define XL_MASK XLLK (0x3f, 0x3ff, 1)
3778 /* An XL_MASK with the RT, RA and RB fields fixed, but S bit clear. */
3779 #define XLS_MASK ((XL_MASK | RT_MASK | RA_MASK | RB_MASK) & ~(1 << 11))
3781 /* An XL form instruction which explicitly sets the BO field. */
3782 #define XLO(op, bo, xop, lk) \
3783 (XLLK ((op), (xop), (lk)) | ((((uint64_t)(bo)) & 0x1f) << 21))
3784 #define XLO_MASK (XL_MASK | BO_MASK)
3786 /* An XL form instruction which sets the BO field and the condition
3787 bits of the BI field. */
3788 #define XLOCB(op, bo, cb, xop, lk) \
3789 (XLO ((op), (bo), (xop), (lk)) | ((((uint64_t)(cb)) & 3) << 16))
3790 #define XLOCB_MASK XLOCB (0x3f, 0x1f, 0x3, 0x3ff, 1)
3792 /* An XL_MASK or XLOCB_MASK with the BB field fixed. */
3793 #define XLBB_MASK (XL_MASK | BB_MASK)
3794 #define XLBOCBBB_MASK (XLOCB_MASK | BB_MASK)
3796 /* A mask for branch instructions using the BH field. */
3797 #define XLBH_MASK (XL_MASK | (BB_MASK & ~(3 << 11)))
3799 /* An XL_MASK with the BO and BB fields fixed. */
3800 #define XLBOBB_MASK (XL_MASK | BO_MASK | BB_MASK)
3802 /* An XL_MASK with the BO, BI and BB fields fixed. */
3803 #define XLBOBIBB_MASK (XL_MASK | BO_MASK | BI_MASK | BB_MASK)
3805 /* An X form mbar instruction with MO field. */
3806 #define XMBAR(op, xop, mo) \
3808 | ((((uint64_t)(mo)) & 1) << 21))
3810 /* An XO form instruction. */
3811 #define XO(op, xop, oe, rc) \
3813 | ((((uint64_t)(xop)) & 0x1ff) << 1) \
3814 | ((((uint64_t)(oe)) & 1) << 10) \
3815 | (((unsigned long)(rc)) & 1))
3816 #define XO_MASK XO (0x3f, 0x1ff, 1, 1)
3818 /* An XO_MASK with the RB field fixed. */
3819 #define XORB_MASK (XO_MASK | RB_MASK)
3821 /* An XOPS form instruction for paired singles. */
3822 #define XOPS(op, xop, rc) \
3824 | ((((uint64_t)(xop)) & 0x3ff) << 1) \
3825 | (((uint64_t)(rc)) & 1))
3826 #define XOPS_MASK XOPS (0x3f, 0x3ff, 1)
3829 /* An XS form instruction. */
3830 #define XS(op, xop, rc) \
3832 | ((((uint64_t)(xop)) & 0x1ff) << 2) \
3833 | (((uint64_t)(rc)) & 1))
3834 #define XS_MASK XS (0x3f, 0x1ff, 1)
3836 /* A mask for the FXM version of an XFX form instruction. */
3837 #define XFXFXM_MASK (X_MASK | (1 << 11) | (1 << 20))
3839 /* An XFX form instruction with the FXM field filled in. */
3840 #define XFXM(op, xop, fxm, p4) \
3842 | ((((uint64_t)(fxm)) & 0xff) << 12) \
3843 | ((uint64_t)(p4) << 20))
3845 /* An XFX form instruction with the SPR field filled in. */
3846 #define XSPR(op, xop, spr) \
3848 | ((((uint64_t)(spr)) & 0x1f) << 16) \
3849 | ((((uint64_t)(spr)) & 0x3e0) << 6))
3850 #define XSPR_MASK (X_MASK | SPR_MASK)
3852 /* An XFX form instruction with the SPR field filled in except for the
3854 #define XSPRBAT_MASK (XSPR_MASK &~ SPRBAT_MASK)
3856 /* An XFX form instruction with the SPR field filled in except for the
3858 #define XSPRGQR_MASK (XSPR_MASK &~ SPRGQR_MASK)
3860 /* An XFX form instruction with the SPR field filled in except for the
3862 #define XSPRG_MASK (XSPR_MASK & ~(0x1f << 16))
3864 /* An X form instruction with everything filled in except the E field. */
3865 #define XE_MASK (0xffff7fff)
3867 /* An X form user context instruction. */
3868 #define XUC(op, xop) (OP (op) | (((uint64_t)(xop)) & 0x1f))
3869 #define XUC_MASK XUC(0x3f, 0x1f)
3871 /* An XW form instruction. */
3872 #define XW(op, xop, rc) \
3874 | ((((uint64_t)(xop)) & 0x3f) << 1) \
3876 /* The mask for a G form instruction. rc not supported at present. */
3877 #define XW_MASK XW (0x3f, 0x3f, 0)
3879 /* An APU form instruction. */
3880 #define APU(op, xop, rc) \
3882 | (((uint64_t)(xop)) & 0x3ff) << 1 \
3885 /* The mask for an APU form instruction. */
3886 #define APU_MASK APU (0x3f, 0x3ff, 1)
3887 #define APU_RT_MASK (APU_MASK | RT_MASK)
3888 #define APU_RA_MASK (APU_MASK | RA_MASK)
3890 /* The BO encodings used in extended conditional branch mnemonics. */
3891 #define BODNZF (0x0)
3892 #define BODNZFP (0x1)
3894 #define BODZFP (0x3)
3895 #define BODNZT (0x8)
3896 #define BODNZTP (0x9)
3898 #define BODZTP (0xb)
3909 #define BODNZ (0x10)
3910 #define BODNZP (0x11)
3912 #define BODZP (0x13)
3913 #define BODNZM4 (0x18)
3914 #define BODNZP4 (0x19)
3915 #define BODZM4 (0x1a)
3916 #define BODZP4 (0x1b)
3920 /* The BO16 encodings used in extended VLE conditional branch mnemonics. */
3924 /* The BO32 encodings used in extended VLE conditional branch mnemonics. */
3927 #define BO32DNZ (0x2)
3928 #define BO32DZ (0x3)
3930 /* The BI condition bit encodings used in extended conditional branch
3937 /* The TO encodings used in extended trap mnemonics. */
3954 /* Smaller names for the flags so each entry in the opcodes table will
3955 fit on a single line. */
3957 #define PPC PPC_OPCODE_PPC
3958 #define PPCCOM PPC_OPCODE_PPC | PPC_OPCODE_COMMON
3959 #define POWER4 PPC_OPCODE_POWER4
3960 #define POWER5 PPC_OPCODE_POWER5
3961 #define POWER6 PPC_OPCODE_POWER6
3962 #define POWER7 PPC_OPCODE_POWER7
3963 #define POWER8 PPC_OPCODE_POWER8
3964 #define POWER9 PPC_OPCODE_POWER9
3965 #define POWER10 PPC_OPCODE_POWER10
3966 #define CELL PPC_OPCODE_CELL
3967 #define PPC64 PPC_OPCODE_64 | PPC_OPCODE_64_BRIDGE
3968 #define NON32 (PPC_OPCODE_64 | PPC_OPCODE_POWER4 \
3969 | PPC_OPCODE_EFS | PPC_OPCODE_E500MC | PPC_OPCODE_TITAN)
3970 #define PPC403 PPC_OPCODE_403
3971 #define PPC405 PPC_OPCODE_405
3972 #define PPC440 PPC_OPCODE_440
3973 #define PPC464 PPC440
3974 #define PPC476 PPC_OPCODE_476
3975 #define PPC750 PPC_OPCODE_750
3976 #define GEKKO PPC_OPCODE_750
3977 #define BROADWAY PPC_OPCODE_750
3978 #define PPC7450 PPC_OPCODE_7450
3979 #define PPC860 PPC_OPCODE_860
3980 #define PPCPS PPC_OPCODE_PPCPS
3981 #define PPCVEC PPC_OPCODE_ALTIVEC
3982 #define PPCVEC2 (PPC_OPCODE_POWER8 | PPC_OPCODE_E6500)
3983 #define PPCVEC3 PPC_OPCODE_POWER9
3984 #define PPCVSX PPC_OPCODE_VSX
3985 #define PPCVSX2 PPC_OPCODE_POWER8
3986 #define PPCVSX3 PPC_OPCODE_POWER9
3987 #define PPCVSX4 PPC_OPCODE_POWER10
3988 #define POWER PPC_OPCODE_POWER
3989 #define POWER2 PPC_OPCODE_POWER | PPC_OPCODE_POWER2
3990 #define PWR2COM PPC_OPCODE_POWER | PPC_OPCODE_POWER2 | PPC_OPCODE_COMMON
3991 #define PPCPWR2 (PPC_OPCODE_PPC | PPC_OPCODE_POWER | PPC_OPCODE_POWER2 \
3992 | PPC_OPCODE_COMMON)
3993 #define COM PPC_OPCODE_POWER | PPC_OPCODE_PPC | PPC_OPCODE_COMMON
3994 #define M601 PPC_OPCODE_POWER | PPC_OPCODE_601
3995 #define PWRCOM PPC_OPCODE_POWER | PPC_OPCODE_601 | PPC_OPCODE_COMMON
3996 #define MFDEC1 PPC_OPCODE_POWER
3997 #define MFDEC2 (PPC_OPCODE_PPC | PPC_OPCODE_601 | PPC_OPCODE_BOOKE \
3999 #define BOOKE PPC_OPCODE_BOOKE
4000 #define NO371 PPC_OPCODE_BOOKE | PPC_OPCODE_PPCPS | PPC_OPCODE_EFS
4001 #define PPCE300 PPC_OPCODE_E300
4002 #define PPCSPE PPC_OPCODE_SPE
4003 #define PPCSPE2 PPC_OPCODE_SPE2
4004 #define PPCISEL PPC_OPCODE_ISEL
4005 #define PPCEFS PPC_OPCODE_EFS
4006 #define PPCEFS2 PPC_OPCODE_EFS2
4007 #define PPCBRLK PPC_OPCODE_BRLOCK
4008 #define PPCPMR PPC_OPCODE_PMR
4009 #define PPCTMR PPC_OPCODE_TMR
4010 #define PPCCHLK PPC_OPCODE_CACHELCK
4011 #define PPCRFMCI PPC_OPCODE_RFMCI
4012 #define E500MC PPC_OPCODE_E500MC
4013 #define PPCA2 PPC_OPCODE_A2
4014 #define TITAN PPC_OPCODE_TITAN
4015 #define MULHW PPC_OPCODE_405 | PPC_OPCODE_440 | PPC_OPCODE_476 | TITAN
4016 #define E500 PPC_OPCODE_E500
4017 #define E6500 PPC_OPCODE_E6500
4018 #define PPCVLE PPC_OPCODE_VLE
4019 #define PPCHTM PPC_OPCODE_POWER8
4020 #define E200Z4 PPC_OPCODE_E200Z4
4021 #define PPCLSP PPC_OPCODE_LSP
4022 /* The list of embedded processors that use the embedded operand ordering
4023 for the 3 operand dcbt and dcbtst instructions. */
4024 #define DCBT_EO (PPC_OPCODE_E500 | PPC_OPCODE_E500MC | PPC_OPCODE_476 \
4029 /* The opcode table.
4031 The format of the opcode table is:
4033 NAME OPCODE MASK FLAGS ANTI {OPERANDS}
4035 NAME is the name of the instruction.
4036 OPCODE is the instruction opcode.
4037 MASK is the opcode mask; this is used to tell the disassembler
4038 which bits in the actual opcode must match OPCODE.
4039 FLAGS are flags indicating which processors support the instruction.
4040 ANTI indicates which processors don't support the instruction.
4041 OPERANDS is the list of operands.
4043 The disassembler reads the table in order and prints the first
4044 instruction which matches, so this table is sorted to put more
4045 specific instructions before more general instructions.
4047 This table must be sorted by major opcode. Please try to keep it
4048 vaguely sorted within major opcode too, except of course where
4049 constrained otherwise by disassembler operation. */
4051 const struct powerpc_opcode powerpc_opcodes
[] = {
4052 {"attn", X(0,256), X_MASK
, POWER4
|PPCA2
, PPC476
|PPCVLE
, {0}},
4053 {"tdlgti", OPTO(2,TOLGT
), OPTO_MASK
, PPC64
, PPCVLE
, {RA
, SI
}},
4054 {"tdllti", OPTO(2,TOLLT
), OPTO_MASK
, PPC64
, PPCVLE
, {RA
, SI
}},
4055 {"tdeqi", OPTO(2,TOEQ
), OPTO_MASK
, PPC64
, PPCVLE
, {RA
, SI
}},
4056 {"tdlgei", OPTO(2,TOLGE
), OPTO_MASK
, PPC64
, PPCVLE
, {RA
, SI
}},
4057 {"tdlnli", OPTO(2,TOLNL
), OPTO_MASK
, PPC64
, PPCVLE
, {RA
, SI
}},
4058 {"tdllei", OPTO(2,TOLLE
), OPTO_MASK
, PPC64
, PPCVLE
, {RA
, SI
}},
4059 {"tdlngi", OPTO(2,TOLNG
), OPTO_MASK
, PPC64
, PPCVLE
, {RA
, SI
}},
4060 {"tdgti", OPTO(2,TOGT
), OPTO_MASK
, PPC64
, PPCVLE
, {RA
, SI
}},
4061 {"tdgei", OPTO(2,TOGE
), OPTO_MASK
, PPC64
, PPCVLE
, {RA
, SI
}},
4062 {"tdnli", OPTO(2,TONL
), OPTO_MASK
, PPC64
, PPCVLE
, {RA
, SI
}},
4063 {"tdlti", OPTO(2,TOLT
), OPTO_MASK
, PPC64
, PPCVLE
, {RA
, SI
}},
4064 {"tdlei", OPTO(2,TOLE
), OPTO_MASK
, PPC64
, PPCVLE
, {RA
, SI
}},
4065 {"tdngi", OPTO(2,TONG
), OPTO_MASK
, PPC64
, PPCVLE
, {RA
, SI
}},
4066 {"tdnei", OPTO(2,TONE
), OPTO_MASK
, PPC64
, PPCVLE
, {RA
, SI
}},
4067 {"tdui", OPTO(2,TOU
), OPTO_MASK
, PPC64
, PPCVLE
, {RA
, SI
}},
4068 {"tdi", OP(2), OP_MASK
, PPC64
, PPCVLE
, {TO
, RA
, SI
}},
4070 {"twlgti", OPTO(3,TOLGT
), OPTO_MASK
, PPCCOM
, PPCVLE
, {RA
, SI
}},
4071 {"tlgti", OPTO(3,TOLGT
), OPTO_MASK
, PWRCOM
, PPCVLE
, {RA
, SI
}},
4072 {"twllti", OPTO(3,TOLLT
), OPTO_MASK
, PPCCOM
, PPCVLE
, {RA
, SI
}},
4073 {"tllti", OPTO(3,TOLLT
), OPTO_MASK
, PWRCOM
, PPCVLE
, {RA
, SI
}},
4074 {"tweqi", OPTO(3,TOEQ
), OPTO_MASK
, PPCCOM
, PPCVLE
, {RA
, SI
}},
4075 {"teqi", OPTO(3,TOEQ
), OPTO_MASK
, PWRCOM
, PPCVLE
, {RA
, SI
}},
4076 {"twlgei", OPTO(3,TOLGE
), OPTO_MASK
, PPCCOM
, PPCVLE
, {RA
, SI
}},
4077 {"tlgei", OPTO(3,TOLGE
), OPTO_MASK
, PWRCOM
, PPCVLE
, {RA
, SI
}},
4078 {"twlnli", OPTO(3,TOLNL
), OPTO_MASK
, PPCCOM
, PPCVLE
, {RA
, SI
}},
4079 {"tlnli", OPTO(3,TOLNL
), OPTO_MASK
, PWRCOM
, PPCVLE
, {RA
, SI
}},
4080 {"twllei", OPTO(3,TOLLE
), OPTO_MASK
, PPCCOM
, PPCVLE
, {RA
, SI
}},
4081 {"tllei", OPTO(3,TOLLE
), OPTO_MASK
, PWRCOM
, PPCVLE
, {RA
, SI
}},
4082 {"twlngi", OPTO(3,TOLNG
), OPTO_MASK
, PPCCOM
, PPCVLE
, {RA
, SI
}},
4083 {"tlngi", OPTO(3,TOLNG
), OPTO_MASK
, PWRCOM
, PPCVLE
, {RA
, SI
}},
4084 {"twgti", OPTO(3,TOGT
), OPTO_MASK
, PPCCOM
, PPCVLE
, {RA
, SI
}},
4085 {"tgti", OPTO(3,TOGT
), OPTO_MASK
, PWRCOM
, PPCVLE
, {RA
, SI
}},
4086 {"twgei", OPTO(3,TOGE
), OPTO_MASK
, PPCCOM
, PPCVLE
, {RA
, SI
}},
4087 {"tgei", OPTO(3,TOGE
), OPTO_MASK
, PWRCOM
, PPCVLE
, {RA
, SI
}},
4088 {"twnli", OPTO(3,TONL
), OPTO_MASK
, PPCCOM
, PPCVLE
, {RA
, SI
}},
4089 {"tnli", OPTO(3,TONL
), OPTO_MASK
, PWRCOM
, PPCVLE
, {RA
, SI
}},
4090 {"twlti", OPTO(3,TOLT
), OPTO_MASK
, PPCCOM
, PPCVLE
, {RA
, SI
}},
4091 {"tlti", OPTO(3,TOLT
), OPTO_MASK
, PWRCOM
, PPCVLE
, {RA
, SI
}},
4092 {"twlei", OPTO(3,TOLE
), OPTO_MASK
, PPCCOM
, PPCVLE
, {RA
, SI
}},
4093 {"tlei", OPTO(3,TOLE
), OPTO_MASK
, PWRCOM
, PPCVLE
, {RA
, SI
}},
4094 {"twngi", OPTO(3,TONG
), OPTO_MASK
, PPCCOM
, PPCVLE
, {RA
, SI
}},
4095 {"tngi", OPTO(3,TONG
), OPTO_MASK
, PWRCOM
, PPCVLE
, {RA
, SI
}},
4096 {"twnei", OPTO(3,TONE
), OPTO_MASK
, PPCCOM
, PPCVLE
, {RA
, SI
}},
4097 {"tnei", OPTO(3,TONE
), OPTO_MASK
, PWRCOM
, PPCVLE
, {RA
, SI
}},
4098 {"twui", OPTO(3,TOU
), OPTO_MASK
, PPCCOM
, PPCVLE
, {RA
, SI
}},
4099 {"tui", OPTO(3,TOU
), OPTO_MASK
, PWRCOM
, PPCVLE
, {RA
, SI
}},
4100 {"twi", OP(3), OP_MASK
, PPCCOM
, PPCVLE
, {TO
, RA
, SI
}},
4101 {"ti", OP(3), OP_MASK
, PWRCOM
, PPCVLE
, {TO
, RA
, SI
}},
4103 {"ps_cmpu0", X (4, 0), XBF_MASK
, PPCPS
, 0, {BF
, FRA
, FRB
}},
4104 {"vaddubm", VX (4, 0), VX_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
4105 {"vmul10cuq", VX (4, 1), VXVB_MASK
, PPCVEC3
, 0, {VD
, VA
}},
4106 {"vmaxub", VX (4, 2), VX_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
4107 {"vrlb", VX (4, 4), VX_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
4108 {"vrlq", VX (4, 5), VX_MASK
, POWER10
, 0, {VD
, VA
, VB
}},
4109 {"vcmpequb", VXR(4, 6,0), VXR_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
4110 {"vcmpneb", VXR(4, 7,0), VXR_MASK
, PPCVEC3
, 0, {VD
, VA
, VB
}},
4111 {"vmuloub", VX (4, 8), VX_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
4112 {"vaddfp", VX (4, 10), VX_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
4113 {"vdivuq", VX (4, 11), VX_MASK
, POWER10
, 0, {VD
, VA
, VB
}},
4114 {"psq_lx", XW (4, 6,0), XW_MASK
, PPCPS
, 0, {FRT
,RA
,RB
,PSWM
,PSQM
}},
4115 {"vmrghb", VX (4, 12), VX_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
4116 {"psq_stx", XW (4, 7,0), XW_MASK
, PPCPS
, 0, {FRS
,RA
,RB
,PSWM
,PSQM
}},
4117 {"vpkuhum", VX (4, 14), VX_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
4118 {"vinsbvlx", VX (4, 15), VX_MASK
, POWER10
, 0, {VD
, RA
, VB
}},
4119 {"mulhhwu", XRC(4, 8,0), X_MASK
, MULHW
, 0, {RT
, RA
, RB
}},
4120 {"mulhhwu.", XRC(4, 8,1), X_MASK
, MULHW
, 0, {RT
, RA
, RB
}},
4121 {"mtvsrbmi", DX (4,10), DX_MASK
, POWER10
, 0, {VD
, DXD
}},
4122 {"ps_sum0", A (4, 10,0), A_MASK
, PPCPS
, 0, {FRT
, FRA
, FRC
, FRB
}},
4123 {"ps_sum0.", A (4, 10,1), A_MASK
, PPCPS
, 0, {FRT
, FRA
, FRC
, FRB
}},
4124 {"vsldbi", VX (4, 22), VXSH_MASK
, POWER10
, 0, {VD
, VA
, VB
, SH3
}},
4125 {"ps_sum1", A (4, 11,0), A_MASK
, PPCPS
, 0, {FRT
, FRA
, FRC
, FRB
}},
4126 {"ps_sum1.", A (4, 11,1), A_MASK
, PPCPS
, 0, {FRT
, FRA
, FRC
, FRB
}},
4127 {"vextdubvlx", VX (4, 24), VXRC_MASK
, POWER10
, 0, {VD
, VA
, VB
, RC
}},
4128 {"ps_muls0", A (4, 12,0), AFRB_MASK
, PPCPS
, 0, {FRT
, FRA
, FRC
}},
4129 {"machhwu", XO (4, 12,0,0), XO_MASK
, MULHW
, 0, {RT
, RA
, RB
}},
4130 {"vextdubvrx", VX (4, 25), VXRC_MASK
, POWER10
, 0, {VD
, VA
, VB
, RC
}},
4131 {"ps_muls0.", A (4, 12,1), AFRB_MASK
, PPCPS
, 0, {FRT
, FRA
, FRC
}},
4132 {"machhwu.", XO (4, 12,0,1), XO_MASK
, MULHW
, 0, {RT
, RA
, RB
}},
4133 {"vextduhvlx", VX (4, 26), VXRC_MASK
, POWER10
, 0, {VD
, VA
, VB
, RC
}},
4134 {"ps_muls1", A (4, 13,0), AFRB_MASK
, PPCPS
, 0, {FRT
, FRA
, FRC
}},
4135 {"vextduhvrx", VX (4, 27), VXRC_MASK
, POWER10
, 0, {VD
, VA
, VB
, RC
}},
4136 {"ps_muls1.", A (4, 13,1), AFRB_MASK
, PPCPS
, 0, {FRT
, FRA
, FRC
}},
4137 {"vextduwvlx", VX (4, 28), VXRC_MASK
, POWER10
, 0, {VD
, VA
, VB
, RC
}},
4138 {"ps_madds0", A (4, 14,0), A_MASK
, PPCPS
, 0, {FRT
, FRA
, FRC
, FRB
}},
4139 {"vextduwvrx", VX (4, 29), VXRC_MASK
, POWER10
, 0, {VD
, VA
, VB
, RC
}},
4140 {"ps_madds0.", A (4, 14,1), A_MASK
, PPCPS
, 0, {FRT
, FRA
, FRC
, FRB
}},
4141 {"vextddvlx", VX (4, 30), VXRC_MASK
, POWER10
, 0, {VD
, VA
, VB
, RC
}},
4142 {"ps_madds1", A (4, 15,0), A_MASK
, PPCPS
, 0, {FRT
, FRA
, FRC
, FRB
}},
4143 {"vextddvrx", VX (4, 31), VXRC_MASK
, POWER10
, 0, {VD
, VA
, VB
, RC
}},
4144 {"ps_madds1.", A (4, 15,1), A_MASK
, PPCPS
, 0, {FRT
, FRA
, FRC
, FRB
}},
4145 {"vmhaddshs", VXA(4, 32), VXA_MASK
, PPCVEC
, 0, {VD
, VA
, VB
, VC
}},
4146 {"vmhraddshs", VXA(4, 33), VXA_MASK
, PPCVEC
, 0, {VD
, VA
, VB
, VC
}},
4147 {"vmladduhm", VXA(4, 34), VXA_MASK
, PPCVEC
, 0, {VD
, VA
, VB
, VC
}},
4148 {"vmsumudm", VXA(4, 35), VXA_MASK
, PPCVEC3
, 0, {VD
, VA
, VB
, VC
}},
4149 {"ps_div", A (4, 18,0), AFRC_MASK
, PPCPS
, 0, {FRT
, FRA
, FRB
}},
4150 {"vmsumcud", VXA(4, 23), VXA_MASK
, POWER10
, 0, {VD
, VA
, VB
, VC
}},
4151 {"vmsumubm", VXA(4, 36), VXA_MASK
, PPCVEC
, 0, {VD
, VA
, VB
, VC
}},
4152 {"ps_div.", A (4, 18,1), AFRC_MASK
, PPCPS
, 0, {FRT
, FRA
, FRB
}},
4153 {"vmsummbm", VXA(4, 37), VXA_MASK
, PPCVEC
, 0, {VD
, VA
, VB
, VC
}},
4154 {"vmsumuhm", VXA(4, 38), VXA_MASK
, PPCVEC
, 0, {VD
, VA
, VB
, VC
}},
4155 {"vmsumuhs", VXA(4, 39), VXA_MASK
, PPCVEC
, 0, {VD
, VA
, VB
, VC
}},
4156 {"ps_sub", A (4, 20,0), AFRC_MASK
, PPCPS
, 0, {FRT
, FRA
, FRB
}},
4157 {"vmsumshm", VXA(4, 40), VXA_MASK
, PPCVEC
, 0, {VD
, VA
, VB
, VC
}},
4158 {"ps_sub.", A (4, 20,1), AFRC_MASK
, PPCPS
, 0, {FRT
, FRA
, FRB
}},
4159 {"vmsumshs", VXA(4, 41), VXA_MASK
, PPCVEC
, 0, {VD
, VA
, VB
, VC
}},
4160 {"ps_add", A (4, 21,0), AFRC_MASK
, PPCPS
, 0, {FRT
, FRA
, FRB
}},
4161 {"vsel", VXA(4, 42), VXA_MASK
, PPCVEC
, 0, {VD
, VA
, VB
, VC
}},
4162 {"ps_add.", A (4, 21,1), AFRC_MASK
, PPCPS
, 0, {FRT
, FRA
, FRB
}},
4163 {"vperm", VXA(4, 43), VXA_MASK
, PPCVEC
, 0, {VD
, VA
, VB
, VC
}},
4164 {"vsldoi", VXA(4, 44), VXASHB_MASK
, PPCVEC
, 0, {VD
, VA
, VB
, SHB
}},
4165 {"vpermxor", VXA(4, 45), VXA_MASK
, PPCVEC2
, 0, {VD
, VA
, VB
, VC
}},
4166 {"ps_sel", A (4, 23,0), A_MASK
, PPCPS
, 0, {FRT
, FRA
, FRC
, FRB
}},
4167 {"vmaddfp", VXA(4, 46), VXA_MASK
, PPCVEC
, 0, {VD
, VA
, VC
, VB
}},
4168 {"ps_sel.", A (4, 23,1), A_MASK
, PPCPS
, 0, {FRT
, FRA
, FRC
, FRB
}},
4169 {"vnmsubfp", VXA(4, 47), VXA_MASK
, PPCVEC
, 0, {VD
, VA
, VC
, VB
}},
4170 {"ps_res", A (4, 24,0), AFRAFRC_MASK
, PPCPS
, 0, {FRT
, FRB
}},
4171 {"maddhd", VXA(4, 48), VXA_MASK
, POWER9
, 0, {RT
, RA
, RB
, RC
}},
4172 {"ps_res.", A (4, 24,1), AFRAFRC_MASK
, PPCPS
, 0, {FRT
, FRB
}},
4173 {"maddhdu", VXA(4, 49), VXA_MASK
, POWER9
, 0, {RT
, RA
, RB
, RC
}},
4174 {"ps_mul", A (4, 25,0), AFRB_MASK
, PPCPS
, 0, {FRT
, FRA
, FRC
}},
4175 {"ps_mul.", A (4, 25,1), AFRB_MASK
, PPCPS
, 0, {FRT
, FRA
, FRC
}},
4176 {"maddld", VXA(4, 51), VXA_MASK
, POWER9
, 0, {RT
, RA
, RB
, RC
}},
4177 {"ps_rsqrte", A (4, 26,0), AFRAFRC_MASK
, PPCPS
, 0, {FRT
, FRB
}},
4178 {"ps_rsqrte.", A (4, 26,1), AFRAFRC_MASK
, PPCPS
, 0, {FRT
, FRB
}},
4179 {"ps_msub", A (4, 28,0), A_MASK
, PPCPS
, 0, {FRT
, FRA
, FRC
, FRB
}},
4180 {"ps_msub.", A (4, 28,1), A_MASK
, PPCPS
, 0, {FRT
, FRA
, FRC
, FRB
}},
4181 {"ps_madd", A (4, 29,0), A_MASK
, PPCPS
, 0, {FRT
, FRA
, FRC
, FRB
}},
4182 {"ps_madd.", A (4, 29,1), A_MASK
, PPCPS
, 0, {FRT
, FRA
, FRC
, FRB
}},
4183 {"vpermr", VXA(4, 59), VXA_MASK
, PPCVEC3
, 0, {VD
, VA
, VB
, VC
}},
4184 {"ps_nmsub", A (4, 30,0), A_MASK
, PPCPS
, 0, {FRT
, FRA
, FRC
, FRB
}},
4185 {"vaddeuqm", VXA(4, 60), VXA_MASK
, PPCVEC2
, 0, {VD
, VA
, VB
, VC
}},
4186 {"ps_nmsub.", A (4, 30,1), A_MASK
, PPCPS
, 0, {FRT
, FRA
, FRC
, FRB
}},
4187 {"vaddecuq", VXA(4, 61), VXA_MASK
, PPCVEC2
, 0, {VD
, VA
, VB
, VC
}},
4188 {"ps_nmadd", A (4, 31,0), A_MASK
, PPCPS
, 0, {FRT
, FRA
, FRC
, FRB
}},
4189 {"vsubeuqm", VXA(4, 62), VXA_MASK
, PPCVEC2
, 0, {VD
, VA
, VB
, VC
}},
4190 {"ps_nmadd.", A (4, 31,1), A_MASK
, PPCPS
, 0, {FRT
, FRA
, FRC
, FRB
}},
4191 {"vsubecuq", VXA(4, 63), VXA_MASK
, PPCVEC2
, 0, {VD
, VA
, VB
, VC
}},
4192 {"ps_cmpo0", X (4, 32), XBF_MASK
, PPCPS
, 0, {BF
, FRA
, FRB
}},
4193 {"vadduhm", VX (4, 64), VX_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
4194 {"vmul10ecuq", VX (4, 65), VX_MASK
, PPCVEC3
, 0, {VD
, VA
, VB
}},
4195 {"vmaxuh", VX (4, 66), VX_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
4196 {"vrlh", VX (4, 68), VX_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
4197 {"vrlqmi", VX (4, 69), VX_MASK
, POWER10
, 0, {VD
, VA
, VB
}},
4198 {"vcmpequh", VXR(4, 70,0), VXR_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
4199 {"vcmpneh", VXR(4, 71,0), VXR_MASK
, PPCVEC3
, 0, {VD
, VA
, VB
}},
4200 {"vmulouh", VX (4, 72), VX_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
4201 {"vsubfp", VX (4, 74), VX_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
4202 {"psq_lux", XW (4, 38,0), XW_MASK
, PPCPS
, 0, {FRT
,RA
,RB
,PSWM
,PSQM
}},
4203 {"vmrghh", VX (4, 76), VX_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
4204 {"psq_stux", XW (4, 39,0), XW_MASK
, PPCPS
, 0, {FRS
,RA
,RB
,PSWM
,PSQM
}},
4205 {"vpkuwum", VX (4, 78), VX_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
4206 {"vinshvlx", VX (4, 79), VX_MASK
, POWER10
, 0, {VD
, RA
, VB
}},
4207 {"ps_neg", XRC(4, 40,0), XRA_MASK
, PPCPS
, 0, {FRT
, FRB
}},
4208 {"mulhhw", XRC(4, 40,0), X_MASK
, MULHW
, 0, {RT
, RA
, RB
}},
4209 {"ps_neg.", XRC(4, 40,1), XRA_MASK
, PPCPS
, 0, {FRT
, FRB
}},
4210 {"mulhhw.", XRC(4, 40,1), X_MASK
, MULHW
, 0, {RT
, RA
, RB
}},
4211 {"machhw", XO (4, 44,0,0), XO_MASK
, MULHW
, 0, {RT
, RA
, RB
}},
4212 {"machhw.", XO (4, 44,0,1), XO_MASK
, MULHW
, 0, {RT
, RA
, RB
}},
4213 {"nmachhw", XO (4, 46,0,0), XO_MASK
, MULHW
, 0, {RT
, RA
, RB
}},
4214 {"nmachhw.", XO (4, 46,0,1), XO_MASK
, MULHW
, 0, {RT
, RA
, RB
}},
4215 {"ps_cmpu1", X (4, 64), XBF_MASK
, PPCPS
, 0, {BF
, FRA
, FRB
}},
4216 {"vadduwm", VX (4, 128), VX_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
4217 {"vmaxuw", VX (4, 130), VX_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
4218 {"vrlw", VX (4, 132), VX_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
4219 {"vrlwmi", VX (4, 133), VX_MASK
, PPCVEC3
, 0, {VD
, VA
, VB
}},
4220 {"vcmpequw", VXR(4, 134,0), VXR_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
4221 {"vcmpnew", VXR(4, 135,0), VXR_MASK
, PPCVEC3
, 0, {VD
, VA
, VB
}},
4222 {"vmulouw", VX (4, 136), VX_MASK
, PPCVEC2
, 0, {VD
, VA
, VB
}},
4223 {"vmuluwm", VX (4, 137), VX_MASK
, PPCVEC2
, 0, {VD
, VA
, VB
}},
4224 {"vdivuw", VX (4, 139), VX_MASK
, POWER10
, 0, {VD
, VA
, VB
}},
4225 {"vmrghw", VX (4, 140), VX_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
4226 {"vpkuhus", VX (4, 142), VX_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
4227 {"vinswvlx", VX (4, 143), VX_MASK
, POWER10
, 0, {VD
, RA
, VB
}},
4228 {"ps_mr", XRC(4, 72,0), XRA_MASK
, PPCPS
, 0, {FRT
, FRB
}},
4229 {"ps_mr.", XRC(4, 72,1), XRA_MASK
, PPCPS
, 0, {FRT
, FRB
}},
4230 {"machhwsu", XO (4, 76,0,0), XO_MASK
, MULHW
, 0, {RT
, RA
, RB
}},
4231 {"machhwsu.", XO (4, 76,0,1), XO_MASK
, MULHW
, 0, {RT
, RA
, RB
}},
4232 {"ps_cmpo1", X (4, 96), XBF_MASK
, PPCPS
, 0, {BF
, FRA
, FRB
}},
4233 {"vaddudm", VX (4, 192), VX_MASK
, PPCVEC2
, 0, {VD
, VA
, VB
}},
4234 {"vmaxud", VX (4, 194), VX_MASK
, PPCVEC2
, 0, {VD
, VA
, VB
}},
4235 {"vrld", VX (4, 196), VX_MASK
, PPCVEC2
, 0, {VD
, VA
, VB
}},
4236 {"vrldmi", VX (4, 197), VX_MASK
, PPCVEC3
, 0, {VD
, VA
, VB
}},
4237 {"vcmpeqfp", VXR(4, 198,0), VXR_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
4238 {"vcmpequd", VXR(4, 199,0), VXR_MASK
, PPCVEC2
, 0, {VD
, VA
, VB
}},
4239 {"vmuloud", VX (4, 200), VX_MASK
, POWER10
, 0, {VD
, VA
, VB
}},
4240 {"vdivud", VX (4, 203), VX_MASK
, POWER10
, 0, {VD
, VA
, VB
}},
4241 {"vpkuwus", VX (4, 206), VX_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
4242 {"vinsw", VX (4, 207), VXUIMM4_MASK
, POWER10
, 0, {VD
, RB
, UIMM4
}},
4243 {"machhws", XO (4, 108,0,0), XO_MASK
, MULHW
, 0, {RT
, RA
, RB
}},
4244 {"machhws.", XO (4, 108,0,1), XO_MASK
, MULHW
, 0, {RT
, RA
, RB
}},
4245 {"nmachhws", XO (4, 110,0,0), XO_MASK
, MULHW
, 0, {RT
, RA
, RB
}},
4246 {"nmachhws.", XO (4, 110,0,1), XO_MASK
, MULHW
, 0, {RT
, RA
, RB
}},
4247 {"vadduqm", VX (4, 256), VX_MASK
, PPCVEC2
, 0, {VD
, VA
, VB
}},
4248 {"vcmpuq", VX (4, 257), VXBF_MASK
, POWER10
, 0, {OBF
, VA
, VB
}},
4249 {"vmaxsb", VX (4, 258), VX_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
4250 {"vslb", VX (4, 260), VX_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
4251 {"vslq", VX (4, 261), VX_MASK
, POWER10
, 0, {VD
, VA
, VB
}},
4252 {"vcmpnezb", VXR(4, 263,0), VXR_MASK
, PPCVEC3
, 0, {VD
, VA
, VB
}},
4253 {"vmulosb", VX (4, 264), VX_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
4254 {"vrefp", VX (4, 266), VXVA_MASK
, PPCVEC
, 0, {VD
, VB
}},
4255 {"vdivsq", VX (4, 267), VX_MASK
, POWER10
, 0, {VD
, VA
, VB
}},
4256 {"vmrglb", VX (4, 268), VX_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
4257 {"vpkshus", VX (4, 270), VX_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
4258 {"vinsbvrx", VX (4, 271), VX_MASK
, POWER10
, 0, {VD
, RA
, VB
}},
4259 {"ps_nabs", XRC(4, 136,0), XRA_MASK
, PPCPS
, 0, {FRT
, FRB
}},
4260 {"mulchwu", XRC(4, 136,0), X_MASK
, MULHW
, 0, {RT
, RA
, RB
}},
4261 {"ps_nabs.", XRC(4, 136,1), XRA_MASK
, PPCPS
, 0, {FRT
, FRB
}},
4262 {"mulchwu.", XRC(4, 136,1), X_MASK
, MULHW
, 0, {RT
, RA
, RB
}},
4263 {"macchwu", XO (4, 140,0,0), XO_MASK
, MULHW
, 0, {RT
, RA
, RB
}},
4264 {"macchwu.", XO (4, 140,0,1), XO_MASK
, MULHW
, 0, {RT
, RA
, RB
}},
4265 {"vaddcuq", VX (4, 320), VX_MASK
, PPCVEC2
, 0, {VD
, VA
, VB
}},
4266 {"vcmpsq", VX (4, 321), VXBF_MASK
, POWER10
, 0, {OBF
, VA
, VB
}},
4267 {"vmaxsh", VX (4, 322), VX_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
4268 {"vslh", VX (4, 324), VX_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
4269 {"vrlqnm", VX (4, 325), VX_MASK
, POWER10
, 0, {VD
, VA
, VB
}},
4270 {"vcmpnezh", VXR(4, 327,0), VXR_MASK
, PPCVEC3
, 0, {VD
, VA
, VB
}},
4271 {"vmulosh", VX (4, 328), VX_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
4272 {"vrsqrtefp", VX (4, 330), VXVA_MASK
, PPCVEC
, 0, {VD
, VB
}},
4273 {"vmrglh", VX (4, 332), VX_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
4274 {"vpkswus", VX (4, 334), VX_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
4275 {"vinshvrx", VX (4, 335), VX_MASK
, POWER10
, 0, {VD
, RA
, VB
}},
4276 {"mulchw", XRC(4, 168,0), X_MASK
, MULHW
, 0, {RT
, RA
, RB
}},
4277 {"mulchw.", XRC(4, 168,1), X_MASK
, MULHW
, 0, {RT
, RA
, RB
}},
4278 {"macchw", XO (4, 172,0,0), XO_MASK
, MULHW
, 0, {RT
, RA
, RB
}},
4279 {"macchw.", XO (4, 172,0,1), XO_MASK
, MULHW
, 0, {RT
, RA
, RB
}},
4280 {"nmacchw", XO (4, 174,0,0), XO_MASK
, MULHW
, 0, {RT
, RA
, RB
}},
4281 {"nmacchw.", XO (4, 174,0,1), XO_MASK
, MULHW
, 0, {RT
, RA
, RB
}},
4282 {"vaddcuw", VX (4, 384), VX_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
4283 {"vmaxsw", VX (4, 386), VX_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
4284 {"vslw", VX (4, 388), VX_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
4285 {"vrlwnm", VX (4, 389), VX_MASK
, PPCVEC3
, 0, {VD
, VA
, VB
}},
4286 {"vcmpnezw", VXR(4, 391,0), VXR_MASK
, PPCVEC3
, 0, {VD
, VA
, VB
}},
4287 {"vmulosw", VX (4, 392), VX_MASK
, PPCVEC2
, 0, {VD
, VA
, VB
}},
4288 {"vexptefp", VX (4, 394), VXVA_MASK
, PPCVEC
, 0, {VD
, VB
}},
4289 {"vdivsw", VX (4, 395), VX_MASK
, POWER10
, 0, {VD
, VA
, VB
}},
4290 {"vmrglw", VX (4, 396), VX_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
4291 {"vpkshss", VX (4, 398), VX_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
4292 {"vinswvrx", VX (4, 399), VX_MASK
, POWER10
, 0, {VD
, RA
, VB
}},
4293 {"macchwsu", XO (4, 204,0,0), XO_MASK
, MULHW
, 0, {RT
, RA
, RB
}},
4294 {"macchwsu.", XO (4, 204,0,1), XO_MASK
, MULHW
, 0, {RT
, RA
, RB
}},
4295 {"vmaxsd", VX (4, 450), VX_MASK
, PPCVEC2
, 0, {VD
, VA
, VB
}},
4296 {"vsl", VX (4, 452), VX_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
4297 {"vrldnm", VX (4, 453), VX_MASK
, PPCVEC3
, 0, {VD
, VA
, VB
}},
4298 {"vcmpgefp", VXR(4, 454,0), VXR_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
4299 {"vcmpequq", VXR(4, 455,0), VXR_MASK
, POWER10
, 0, {VD
, VA
, VB
}},
4300 {"vmulosd", VX (4, 456), VX_MASK
, POWER10
, 0, {VD
, VA
, VB
}},
4301 {"vmulld", VX (4, 457), VX_MASK
, POWER10
, 0, {VD
, VA
, VB
}},
4302 {"vlogefp", VX (4, 458), VXVA_MASK
, PPCVEC
, 0, {VD
, VB
}},
4303 {"vdivsd", VX (4, 459), VX_MASK
, POWER10
, 0, {VD
, VA
, VB
}},
4304 {"vpkswss", VX (4, 462), VX_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
4305 {"vinsd", VX (4, 463), VXUIMM4_MASK
, POWER10
, 0, {VD
, RB
, UIMM4
}},
4306 {"macchws", XO (4, 236,0,0), XO_MASK
, MULHW
, 0, {RT
, RA
, RB
}},
4307 {"macchws.", XO (4, 236,0,1), XO_MASK
, MULHW
, 0, {RT
, RA
, RB
}},
4308 {"nmacchws", XO (4, 238,0,0), XO_MASK
, MULHW
, 0, {RT
, RA
, RB
}},
4309 {"nmacchws.", XO (4, 238,0,1), XO_MASK
, MULHW
, 0, {RT
, RA
, RB
}},
4310 {"evaddw", VX (4, 512), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
4311 {"vaddubs", VX (4, 512), VX_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
4312 {"vmul10uq", VX (4, 513), VXVB_MASK
, PPCVEC3
, 0, {VD
, VA
}},
4313 {"evaddiw", VX (4, 514), VX_MASK
, PPCSPE
, 0, {RS
, RB
, UIMM
}},
4314 {"vminub", VX (4, 514), VX_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
4315 {"evsubfw", VX (4, 516), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
4316 {"evsubw", VX (4, 516), VX_MASK
, PPCSPE
, 0, {RS
, RB
, RA
}},
4317 {"vsrb", VX (4, 516), VX_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
4318 {"vsrq", VX (4, 517), VX_MASK
, POWER10
, 0, {VD
, VA
, VB
}},
4319 {"evsubifw", VX (4, 518), VX_MASK
, PPCSPE
, 0, {RS
, UIMM
, RB
}},
4320 {"evsubiw", VX (4, 518), VX_MASK
, PPCSPE
, 0, {RS
, RB
, UIMM
}},
4321 {"vcmpgtub", VXR(4, 518,0), VXR_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
4322 {"evabs", VX (4, 520), VX_MASK
, PPCSPE
, 0, {RS
, RA
}},
4323 {"vmuleub", VX (4, 520), VX_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
4324 {"evneg", VX (4, 521), VX_MASK
, PPCSPE
, 0, {RS
, RA
}},
4325 {"evextsb", VX (4, 522), VX_MASK
, PPCSPE
, 0, {RS
, RA
}},
4326 {"vrfin", VX (4, 522), VXVA_MASK
, PPCVEC
, 0, {VD
, VB
}},
4327 {"vdiveuq", VX (4, 523), VX_MASK
, POWER10
, 0, {VD
, VA
, VB
}},
4328 {"evextsh", VX (4, 523), VX_MASK
, PPCSPE
, 0, {RS
, RA
}},
4329 {"evrndw", VX (4, 524), VX_MASK
, PPCSPE
, 0, {RS
, RA
}},
4330 {"vspltb", VX (4, 524), VXUIMM4_MASK
, PPCVEC
, 0, {VD
, VB
, UIMM4
}},
4331 {"vextractub", VX (4, 525), VXUIMM4_MASK
, PPCVEC3
, 0, {VD
, VB
, UIMM4
}},
4332 {"evcntlzw", VX (4, 525), VX_MASK
, PPCSPE
, 0, {RS
, RA
}},
4333 {"evcntlsw", VX (4, 526), VX_MASK
, PPCSPE
, 0, {RS
, RA
}},
4334 {"vupkhsb", VX (4, 526), VXVA_MASK
, PPCVEC
, 0, {VD
, VB
}},
4335 {"vinsblx", VX (4, 527), VX_MASK
, POWER10
, 0, {VD
, RA
, RB
}},
4336 {"brinc", VX (4, 527), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
4337 {"ps_abs", XRC(4, 264,0), XRA_MASK
, PPCPS
, 0, {FRT
, FRB
}},
4338 {"ps_abs.", XRC(4, 264,1), XRA_MASK
, PPCPS
, 0, {FRT
, FRB
}},
4339 {"evand", VX (4, 529), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
4340 {"evandc", VX (4, 530), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
4341 {"vsrdbi", VX (4, 534), VXSH_MASK
, POWER10
, 0, {VD
, VA
, VB
, SH3
}},
4342 {"evxor", VX (4, 534), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
4343 {"evmr", VX (4, 535), VX_MASK
, PPCSPE
, 0, {RS
, RAB
}},
4344 {"evor", VX (4, 535), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
4345 {"evnot", VX (4, 536), VX_MASK
, PPCSPE
, 0, {RS
, RAB
}},
4346 {"evnor", VX (4, 536), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
4347 {"get", APU(4, 268,0), APU_RA_MASK
, PPC405
, 0, {RT
, FSL
}},
4348 {"eveqv", VX (4, 537), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
4349 {"evorc", VX (4, 539), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
4350 {"evnand", VX (4, 542), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
4351 {"evsrwu", VX (4, 544), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
4352 {"evsrws", VX (4, 545), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
4353 {"evsrwiu", VX (4, 546), VX_MASK
, PPCSPE
, 0, {RS
, RA
, EVUIMM
}},
4354 {"evsrwis", VX (4, 547), VX_MASK
, PPCSPE
, 0, {RS
, RA
, EVUIMM
}},
4355 {"evslw", VX (4, 548), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
4356 {"evslwi", VX (4, 550), VX_MASK
, PPCSPE
, 0, {RS
, RA
, EVUIMM
}},
4357 {"evrlw", VX (4, 552), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
4358 {"evsplati", VX (4, 553), VX_MASK
, PPCSPE
, 0, {RS
, SIMM
}},
4359 {"evrlwi", VX (4, 554), VX_MASK
, PPCSPE
, 0, {RS
, RA
, EVUIMM
}},
4360 {"evsplatfi", VX (4, 555), VX_MASK
, PPCSPE
, 0, {RS
, SIMM
}},
4361 {"evmergehi", VX (4, 556), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
4362 {"evmergelo", VX (4, 557), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
4363 {"evmergehilo", VX (4, 558), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
4364 {"evmergelohi", VX (4, 559), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
4365 {"evcmpgtu", VX (4, 560), VX_MASK
, PPCSPE
, 0, {CRFD
, RA
, RB
}},
4366 {"evcmpgts", VX (4, 561), VX_MASK
, PPCSPE
, 0, {CRFD
, RA
, RB
}},
4367 {"evcmpltu", VX (4, 562), VX_MASK
, PPCSPE
, 0, {CRFD
, RA
, RB
}},
4368 {"evcmplts", VX (4, 563), VX_MASK
, PPCSPE
, 0, {CRFD
, RA
, RB
}},
4369 {"evcmpeq", VX (4, 564), VX_MASK
, PPCSPE
, 0, {CRFD
, RA
, RB
}},
4370 {"cget", APU(4, 284,0), APU_RA_MASK
, PPC405
, 0, {RT
, FSL
}},
4371 {"vadduhs", VX (4, 576), VX_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
4372 {"vmul10euq", VX (4, 577), VX_MASK
, PPCVEC3
, 0, {VD
, VA
, VB
}},
4373 {"vminuh", VX (4, 578), VX_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
4374 {"vsrh", VX (4, 580), VX_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
4375 {"vcmpgtuh", VXR(4, 582,0), VXR_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
4376 {"vmuleuh", VX (4, 584), VX_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
4377 {"vrfiz", VX (4, 586), VXVA_MASK
, PPCVEC
, 0, {VD
, VB
}},
4378 {"vsplth", VX (4, 588), VXUIMM3_MASK
, PPCVEC
, 0, {VD
, VB
, UIMM3
}},
4379 {"vextractuh", VX (4, 589), VXUIMM4_MASK
, PPCVEC3
, 0, {VD
, VB
, UIMM4
}},
4380 {"vupkhsh", VX (4, 590), VXVA_MASK
, PPCVEC
, 0, {VD
, VB
}},
4381 {"vinshlx", VX (4, 591), VX_MASK
, POWER10
, 0, {VD
, RA
, RB
}},
4382 {"nget", APU(4, 300,0), APU_RA_MASK
, PPC405
, 0, {RT
, FSL
}},
4383 {"evsel", EVSEL(4,79), EVSEL_MASK
, PPCSPE
, 0, {RS
, RA
, RB
, CRFS
}},
4384 {"ncget", APU(4, 316,0), APU_RA_MASK
, PPC405
, 0, {RT
, FSL
}},
4385 {"evfsadd", VX (4, 640), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
4386 {"vadduws", VX (4, 640), VX_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
4387 {"evfssub", VX (4, 641), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
4388 {"evfsmadd", VX (4, 642), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
4389 {"vminuw", VX (4, 642), VX_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
4390 {"evfsmsub", VX (4, 643), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
4391 {"evfsabs", VX (4, 644), VX_MASK
, PPCSPE
, 0, {RS
, RA
}},
4392 {"vsrw", VX (4, 644), VX_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
4393 {"evfsnabs", VX (4, 645), VX_MASK
, PPCSPE
, 0, {RS
, RA
}},
4394 {"evfsneg", VX (4, 646), VX_MASK
, PPCSPE
, 0, {RS
, RA
}},
4395 {"vcmpgtuw", VXR(4, 646,0), VXR_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
4396 {"vcmpgtuq", VXR(4, 647,0), VXR_MASK
, POWER10
, 0, {VD
, VA
, VB
}},
4397 {"evfssqrt", VX_RB_CONST(4, 647, 0), VX_RB_CONST_MASK
, PPCEFS2
, 0, {RD
, RA
}},
4398 {"vmuleuw", VX (4, 648), VX_MASK
, PPCVEC2
, 0, {VD
, VA
, VB
}},
4399 {"evfsmul", VX (4, 648), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
4400 {"vmulhuw", VX (4, 649), VX_MASK
, POWER10
, 0, {VD
, VA
, VB
}},
4401 {"evfsdiv", VX (4, 649), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
4402 {"evfsnmadd", VX (4, 650), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
4403 {"vrfip", VX (4, 650), VXVA_MASK
, PPCVEC
, 0, {VD
, VB
}},
4404 {"vdiveuw", VX (4, 651), VX_MASK
, POWER10
, 0, {VD
, VA
, VB
}},
4405 {"evfsnmsub", VX (4, 651), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
4406 {"evfscmpgt", VX (4, 652), VX_MASK
, PPCSPE
, 0, {CRFD
, RA
, RB
}},
4407 {"vspltw", VX (4, 652), VXUIMM2_MASK
, PPCVEC
, 0, {VD
, VB
, UIMM2
}},
4408 {"vextractuw", VX (4, 653), VXUIMM4_MASK
, PPCVEC3
, 0, {VD
, VB
, UIMM4
}},
4409 {"evfscmplt", VX (4, 653), VX_MASK
, PPCSPE
, 0, {CRFD
, RA
, RB
}},
4410 {"evfscmpeq", VX (4, 654), VX_MASK
, PPCSPE
, 0, {CRFD
, RA
, RB
}},
4411 {"vupklsb", VX (4, 654), VXVA_MASK
, PPCVEC
, 0, {VD
, VB
}},
4412 {"vinswlx", VX (4, 655), VX_MASK
, POWER10
, 0, {VD
, RA
, RB
}},
4413 {"evfscfui", VX (4, 656), VX_MASK
, PPCSPE
, 0, {RS
, RB
}},
4414 {"evfscfh", VX_RA_CONST(4, 657, 4), VX_RA_CONST_MASK
, PPCEFS2
, 0, {RD
, RB
}},
4415 {"evfscfsi", VX (4, 657), VX_MASK
, PPCSPE
, 0, {RS
, RB
}},
4416 {"evfscfuf", VX (4, 658), VX_MASK
, PPCSPE
, 0, {RS
, RB
}},
4417 {"evfscfsf", VX (4, 659), VX_MASK
, PPCSPE
, 0, {RS
, RB
}},
4418 {"evfsctui", VX (4, 660), VX_MASK
, PPCSPE
, 0, {RS
, RB
}},
4419 {"evfscth", VX_RA_CONST(4, 661, 4), VX_RA_CONST_MASK
, PPCEFS2
, 0, {RD
, RB
}},
4420 {"evfsctsi", VX (4, 661), VX_MASK
, PPCSPE
, 0, {RS
, RB
}},
4421 {"evfsctuf", VX (4, 662), VX_MASK
, PPCSPE
, 0, {RS
, RB
}},
4422 {"evfsctsf", VX (4, 663), VX_MASK
, PPCSPE
, 0, {RS
, RB
}},
4423 {"evfsctuiz", VX (4, 664), VX_MASK
, PPCSPE
, 0, {RS
, RB
}},
4424 {"put", APU(4, 332,0), APU_RT_MASK
, PPC405
, 0, {RA
, FSL
}},
4425 {"evfsctsiz", VX (4, 666), VX_MASK
, PPCSPE
, 0, {RS
, RB
}},
4426 {"evfststgt", VX (4, 668), VX_MASK
, PPCSPE
, 0, {CRFD
, RA
, RB
}},
4427 {"evfststlt", VX (4, 669), VX_MASK
, PPCSPE
, 0, {CRFD
, RA
, RB
}},
4428 {"evfststeq", VX (4, 670), VX_MASK
, PPCSPE
, 0, {CRFD
, RA
, RB
}},
4429 {"evfsmax", VX (4, 672), VX_MASK
, PPCEFS2
, 0, {RD
, RA
, RB
}},
4430 {"evfsmin", VX (4, 673), VX_MASK
, PPCEFS2
, 0, {RD
, RA
, RB
}},
4431 {"evfsaddsub", VX (4, 674), VX_MASK
, PPCEFS2
, 0, {RD
, RA
, RB
}},
4432 {"evfssubadd", VX (4, 675), VX_MASK
, PPCEFS2
, 0, {RD
, RA
, RB
}},
4433 {"evfssum", VX (4, 676), VX_MASK
, PPCEFS2
, 0, {RD
, RA
, RB
}},
4434 {"evfsdiff", VX (4, 677), VX_MASK
, PPCEFS2
, 0, {RD
, RA
, RB
}},
4435 {"evfssumdiff", VX (4, 678), VX_MASK
, PPCEFS2
, 0, {RD
, RA
, RB
}},
4436 {"evfsdiffsum", VX (4, 679), VX_MASK
, PPCEFS2
, 0, {RD
, RA
, RB
}},
4437 {"evfsaddx", VX (4, 680), VX_MASK
, PPCEFS2
, 0, {RD
, RA
, RB
}},
4438 {"evfssubx", VX (4, 681), VX_MASK
, PPCEFS2
, 0, {RD
, RA
, RB
}},
4439 {"evfsaddsubx", VX (4, 682), VX_MASK
, PPCEFS2
, 0, {RD
, RA
, RB
}},
4440 {"evfssubaddx", VX (4, 683), VX_MASK
, PPCEFS2
, 0, {RD
, RA
, RB
}},
4441 {"evfsmulx", VX (4, 684), VX_MASK
, PPCEFS2
, 0, {RD
, RA
, RB
}},
4442 {"evfsmule", VX (4, 686), VX_MASK
, PPCEFS2
, 0, {RD
, RA
, RB
}},
4443 {"evfsmulo", VX (4, 687), VX_MASK
, PPCEFS2
, 0, {RD
, RA
, RB
}},
4444 {"efsmax", VX (4, 688), VX_MASK
, PPCEFS2
, 0, {RD
, RA
, RB
}},
4445 {"efsmin", VX (4, 689), VX_MASK
, PPCEFS2
, 0, {RD
, RA
, RB
}},
4446 {"efdmax", VX (4, 696), VX_MASK
, PPCEFS2
, 0, {RD
, RA
, RB
}},
4447 {"cput", APU(4, 348,0), APU_RT_MASK
, PPC405
, 0, {RA
, FSL
}},
4448 {"efdmin", VX (4, 697), VX_MASK
, PPCEFS2
, 0, {RD
, RA
, RB
}},
4449 {"efsadd", VX (4, 704), VX_MASK
, PPCEFS
, 0, {RS
, RA
, RB
}},
4450 {"efssub", VX (4, 705), VX_MASK
, PPCEFS
, 0, {RS
, RA
, RB
}},
4451 {"efsmadd", VX (4, 706), VX_MASK
, PPCEFS2
, 0, {RS
, RA
, RB
}},
4452 {"vminud", VX (4, 706), VX_MASK
, PPCVEC2
, 0, {VD
, VA
, VB
}},
4453 {"efsmsub", VX (4, 707), VX_MASK
, PPCEFS2
, 0, {RS
, RA
, RB
}},
4454 {"efsabs", VX (4, 708), VX_MASK
, PPCEFS
, 0, {RS
, RA
}},
4455 {"vsr", VX (4, 708), VX_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
4456 {"efsnabs", VX (4, 709), VX_MASK
, PPCEFS
, 0, {RS
, RA
}},
4457 {"efsneg", VX (4, 710), VX_MASK
, PPCEFS
, 0, {RS
, RA
}},
4458 {"vcmpgtfp", VXR(4, 710,0), VXR_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
4459 {"efssqrt", VX_RB_CONST(4, 711, 0), VX_RB_CONST_MASK
,PPCEFS2
, 0, {RD
, RA
}},
4460 {"vcmpgtud", VXR(4, 711,0), VXR_MASK
, PPCVEC2
, 0, {VD
, VA
, VB
}},
4461 {"vmuleud", VX (4, 712), VX_MASK
, POWER10
, 0, {VD
, VA
, VB
}},
4462 {"efsmul", VX (4, 712), VX_MASK
, PPCEFS
, 0, {RS
, RA
, RB
}},
4463 {"vmulhud", VX (4, 713), VX_MASK
, POWER10
, 0, {VD
, VA
, VB
}},
4464 {"efsdiv", VX (4, 713), VX_MASK
, PPCEFS
, 0, {RS
, RA
, RB
}},
4465 {"efsnmadd", VX (4, 714), VX_MASK
, PPCEFS2
, 0, {RS
, RA
, RB
}},
4466 {"vrfim", VX (4, 714), VXVA_MASK
, PPCVEC
, 0, {VD
, VB
}},
4467 {"vdiveud", VX (4, 715), VX_MASK
, POWER10
, 0, {VD
, VA
, VB
}},
4468 {"efsnmsub", VX (4, 715), VX_MASK
, PPCEFS2
, 0, {RS
, RA
, RB
}},
4469 {"efscmpgt", VX (4, 716), VX_MASK
, PPCEFS
, 0, {CRFD
, RA
, RB
}},
4470 {"vextractd", VX (4, 717), VXUIMM4_MASK
, PPCVEC3
, 0, {VD
, VB
, UIMM4
}},
4471 {"efscmplt", VX (4, 717), VX_MASK
, PPCEFS
, 0, {CRFD
, RA
, RB
}},
4472 {"efscmpeq", VX (4, 718), VX_MASK
, PPCEFS
, 0, {CRFD
, RA
, RB
}},
4473 {"vupklsh", VX (4, 718), VXVA_MASK
, PPCVEC
, 0, {VD
, VB
}},
4474 {"vinsdlx", VX (4, 719), VX_MASK
, POWER10
, 0, {VD
, RA
, RB
}},
4475 {"efscfd", VX (4, 719), VX_MASK
, PPCEFS
, 0, {RS
, RB
}},
4476 {"efscfui", VX (4, 720), VX_MASK
, PPCEFS
, 0, {RS
, RB
}},
4477 {"efscfh", VX_RA_CONST(4, 721, 4), VX_RA_CONST_MASK
, PPCEFS2
, 0, {RD
, RB
}},
4478 {"efscfsi", VX (4, 721), VX_MASK
, PPCEFS
, 0, {RS
, RB
}},
4479 {"efscfuf", VX (4, 722), VX_MASK
, PPCEFS
, 0, {RS
, RB
}},
4480 {"efscfsf", VX (4, 723), VX_MASK
, PPCEFS
, 0, {RS
, RB
}},
4481 {"efsctui", VX (4, 724), VX_MASK
, PPCEFS
, 0, {RS
, RB
}},
4482 {"efscth", VX_RA_CONST(4, 725, 4), VX_RA_CONST_MASK
, PPCEFS2
, 0, {RD
, RB
}},
4483 {"efsctsi", VX (4, 725), VX_MASK
, PPCEFS
, 0, {RS
, RB
}},
4484 {"efsctuf", VX (4, 726), VX_MASK
, PPCEFS
, 0, {RS
, RB
}},
4485 {"efsctsf", VX (4, 727), VX_MASK
, PPCEFS
, 0, {RS
, RB
}},
4486 {"efsctuiz", VX (4, 728), VX_MASK
, PPCEFS
, 0, {RS
, RB
}},
4487 {"nput", APU(4, 364,0), APU_RT_MASK
, PPC405
, 0, {RA
, FSL
}},
4488 {"efsctsiz", VX (4, 730), VX_MASK
, PPCEFS
, 0, {RS
, RB
}},
4489 {"efststgt", VX (4, 732), VX_MASK
, PPCEFS
, 0, {CRFD
, RA
, RB
}},
4490 {"efststlt", VX (4, 733), VX_MASK
, PPCEFS
, 0, {CRFD
, RA
, RB
}},
4491 {"efststeq", VX (4, 734), VX_MASK
, PPCEFS
, 0, {CRFD
, RA
, RB
}},
4492 {"efdadd", VX (4, 736), VX_MASK
, PPCEFS
, 0, {RS
, RA
, RB
}},
4493 {"efdsub", VX (4, 737), VX_MASK
, PPCEFS
, 0, {RS
, RA
, RB
}},
4494 {"efdmadd", VX (4, 738), VX_MASK
, PPCEFS2
, E500
|E500MC
, {RD
, RA
, RB
}},
4495 {"efdcfuid", VX (4, 738), VX_MASK
, E500
|E500MC
,0, {RS
, RB
}},
4496 {"efdmsub", VX (4, 739), VX_MASK
, PPCEFS2
, E500
|E500MC
, {RD
, RA
, RB
}},
4497 {"efdcfsid", VX (4, 739), VX_MASK
, E500
|E500MC
,0, {RS
, RB
}},
4498 {"efdabs", VX (4, 740), VX_MASK
, PPCEFS
, 0, {RS
, RA
}},
4499 {"efdnabs", VX (4, 741), VX_MASK
, PPCEFS
, 0, {RS
, RA
}},
4500 {"efdneg", VX (4, 742), VX_MASK
, PPCEFS
, 0, {RS
, RA
}},
4501 {"efdsqrt", VX_RB_CONST(4, 743, 0), VX_RB_CONST_MASK
, PPCEFS2
, 0, {RD
, RA
}},
4502 {"efdmul", VX (4, 744), VX_MASK
, PPCEFS
, 0, {RS
, RA
, RB
}},
4503 {"efddiv", VX (4, 745), VX_MASK
, PPCEFS
, 0, {RS
, RA
, RB
}},
4504 {"efdnmadd", VX (4, 746), VX_MASK
, PPCEFS2
, E500
|E500MC
, {RD
, RA
, RB
}},
4505 {"efdctuidz", VX (4, 746), VX_MASK
, E500
|E500MC
,0, {RS
, RB
}},
4506 {"efdnmsub", VX (4, 747), VX_MASK
, PPCEFS2
, E500
|E500MC
, {RD
, RA
, RB
}},
4507 {"efdctsidz", VX (4, 747), VX_MASK
, E500
|E500MC
,0, {RS
, RB
}},
4508 {"efdcmpgt", VX (4, 748), VX_MASK
, PPCEFS
, 0, {CRFD
, RA
, RB
}},
4509 {"efdcmplt", VX (4, 749), VX_MASK
, PPCEFS
, 0, {CRFD
, RA
, RB
}},
4510 {"efdcmpeq", VX (4, 750), VX_MASK
, PPCEFS
, 0, {CRFD
, RA
, RB
}},
4511 {"efdcfs", VX (4, 751), VX_MASK
, PPCEFS
, 0, {RS
, RB
}},
4512 {"efdcfui", VX_RA_CONST(4, 752, 0), VX_RA_CONST_MASK
, PPCEFS
, 0, {RS
, RB
}},
4513 {"efdcfuid", VX_RA_CONST(4, 752, 1), VX_RA_CONST_MASK
, PPCEFS
, E500
|E500MC
, {RS
, RB
}},
4514 {"efdcfsi", VX_RA_CONST(4, 753, 0), VX_RA_CONST_MASK
, PPCEFS
, 0, {RS
, RB
}},
4515 {"efdcfsid", VX_RA_CONST(4, 753, 1), VX_RA_CONST_MASK
, PPCEFS
, E500
|E500MC
, {RS
, RB
}},
4516 {"efdcfh", VX_RA_CONST(4, 753, 4), VX_RA_CONST_MASK
, PPCEFS2
, 0, {RD
, RB
}},
4517 {"efdcfuf", VX (4, 754), VX_MASK
, PPCEFS
, 0, {RS
, RB
}},
4518 {"efdcfsf", VX (4, 755), VX_MASK
, PPCEFS
, 0, {RS
, RB
}},
4519 {"efdctui", VX (4, 756), VX_MASK
, PPCEFS
, 0, {RS
, RB
}},
4520 {"efdcth", VX_RA_CONST(4, 757, 4), VX_RA_CONST_MASK
, PPCEFS2
, 0, {RD
, RB
}},
4521 {"efdctsi", VX (4, 757), VX_MASK
, PPCEFS
, 0, {RS
, RB
}},
4522 {"efdctuf", VX (4, 758), VX_MASK
, PPCEFS
, 0, {RS
, RB
}},
4523 {"efdctsf", VX (4, 759), VX_MASK
, PPCEFS
, 0, {RS
, RB
}},
4524 {"efdctuiz", VX_RA_CONST(4, 760, 0), VX_RA_CONST_MASK
, PPCEFS
, 0, {RS
, RB
}},
4525 {"efdctuidz", VX_RA_CONST(4, 760, 1), VX_RA_CONST_MASK
, PPCEFS
, E500
|E500MC
, {RS
, RB
}},
4526 {"ncput", APU(4, 380,0), APU_RT_MASK
, PPC405
, 0, {RA
, FSL
}},
4527 {"efdctsiz", VX_RA_CONST(4, 762, 0), VX_RA_CONST_MASK
, PPCEFS
, 0, {RS
, RB
}},
4528 {"efdctsidz", VX_RA_CONST(4, 762, 1), VX_RA_CONST_MASK
, PPCEFS
, E500
|E500MC
, {RS
, RB
}},
4529 {"efdtstgt", VX (4, 764), VX_MASK
, PPCEFS
, 0, {CRFD
, RA
, RB
}},
4530 {"efdtstlt", VX (4, 765), VX_MASK
, PPCEFS
, 0, {CRFD
, RA
, RB
}},
4531 {"efdtsteq", VX (4, 766), VX_MASK
, PPCEFS
, 0, {CRFD
, RA
, RB
}},
4532 {"evlddx", VX (4, 768), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
4533 {"vaddsbs", VX (4, 768), VX_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
4534 {"evldd", VX (4, 769), VX_MASK
, PPCSPE
, 0, {RS
, EVUIMM_8
, RA
}},
4535 {"evldwx", VX (4, 770), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
4536 {"vminsb", VX (4, 770), VX_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
4537 {"evldw", VX (4, 771), VX_MASK
, PPCSPE
, 0, {RS
, EVUIMM_8
, RA
}},
4538 {"evldhx", VX (4, 772), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
4539 {"vsrab", VX (4, 772), VX_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
4540 {"vsraq", VX (4, 773), VX_MASK
, POWER10
, 0, {VD
, VA
, VB
}},
4541 {"evldh", VX (4, 773), VX_MASK
, PPCSPE
, 0, {RS
, EVUIMM_8
, RA
}},
4542 {"vcmpgtsb", VXR(4, 774,0), VXR_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
4543 {"evlhhesplatx",VX (4, 776), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
4544 {"vmulesb", VX (4, 776), VX_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
4545 {"evlhhesplat", VX (4, 777), VX_MASK
, PPCSPE
, 0, {RS
, EVUIMM_2
, RA
}},
4546 {"vcfux", VX (4, 778), VX_MASK
, PPCVEC
, 0, {VD
, VB
, UIMM
}},
4547 {"vcuxwfp", VX (4, 778), VX_MASK
, PPCVEC
, 0, {VD
, VB
, UIMM
}},
4548 {"vdivesq", VX (4, 779), VX_MASK
, POWER10
, 0, {VD
, VA
, VB
}},
4549 {"evlhhousplatx",VX(4, 780), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
4550 {"vspltisb", VX (4, 780), VXVB_MASK
, PPCVEC
, 0, {VD
, SIMM
}},
4551 {"vinsertb", VX (4, 781), VXUIMM4_MASK
, PPCVEC3
, 0, {VD
, VB
, UIMM4
}},
4552 {"evlhhousplat",VX (4, 781), VX_MASK
, PPCSPE
, 0, {RS
, EVUIMM_2
, RA
}},
4553 {"evlhhossplatx",VX(4, 782), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
4554 {"vpkpx", VX (4, 782), VX_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
4555 {"vinsbrx", VX (4, 783), VX_MASK
, POWER10
, 0, {VD
, RA
, RB
}},
4556 {"evlhhossplat",VX (4, 783), VX_MASK
, PPCSPE
, 0, {RS
, EVUIMM_2
, RA
}},
4557 {"mullhwu", XRC(4, 392,0), X_MASK
, MULHW
, 0, {RT
, RA
, RB
}},
4558 {"evlwhex", VX (4, 784), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
4559 {"mullhwu.", XRC(4, 392,1), X_MASK
, MULHW
, 0, {RT
, RA
, RB
}},
4560 {"evlwhe", VX (4, 785), VX_MASK
, PPCSPE
, 0, {RS
, EVUIMM_4
, RA
}},
4561 {"evlwhoux", VX (4, 788), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
4562 {"evlwhou", VX (4, 789), VX_MASK
, PPCSPE
, 0, {RS
, EVUIMM_4
, RA
}},
4563 {"evlwhosx", VX (4, 790), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
4564 {"evlwhos", VX (4, 791), VX_MASK
, PPCSPE
, 0, {RS
, EVUIMM_4
, RA
}},
4565 {"maclhwu", XO (4, 396,0,0),XO_MASK
, MULHW
, 0, {RT
, RA
, RB
}},
4566 {"evlwwsplatx", VX (4, 792), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
4567 {"maclhwu.", XO (4, 396,0,1),XO_MASK
, MULHW
, 0, {RT
, RA
, RB
}},
4568 {"evlwwsplat", VX (4, 793), VX_MASK
, PPCSPE
, 0, {RS
, EVUIMM_4
, RA
}},
4569 {"evlwhsplatx", VX (4, 796), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
4570 {"evlwhsplat", VX (4, 797), VX_MASK
, PPCSPE
, 0, {RS
, EVUIMM_4
, RA
}},
4571 {"evstddx", VX (4, 800), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
4572 {"evstdd", VX (4, 801), VX_MASK
, PPCSPE
, 0, {RS
, EVUIMM_8
, RA
}},
4573 {"evstdwx", VX (4, 802), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
4574 {"evstdw", VX (4, 803), VX_MASK
, PPCSPE
, 0, {RS
, EVUIMM_8
, RA
}},
4575 {"evstdhx", VX (4, 804), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
4576 {"evstdh", VX (4, 805), VX_MASK
, PPCSPE
, 0, {RS
, EVUIMM_8
, RA
}},
4577 {"evstwhex", VX (4, 816), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
4578 {"evstwhe", VX (4, 817), VX_MASK
, PPCSPE
, 0, {RS
, EVUIMM_4
, RA
}},
4579 {"evstwhox", VX (4, 820), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
4580 {"evstwho", VX (4, 821), VX_MASK
, PPCSPE
, 0, {RS
, EVUIMM_4
, RA
}},
4581 {"evstwwex", VX (4, 824), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
4582 {"evstwwe", VX (4, 825), VX_MASK
, PPCSPE
, 0, {RS
, EVUIMM_4
, RA
}},
4583 {"evstwwox", VX (4, 828), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
4584 {"evstwwo", VX (4, 829), VX_MASK
, PPCSPE
, 0, {RS
, EVUIMM_4
, RA
}},
4585 {"vaddshs", VX (4, 832), VX_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
4586 {"bcdcpsgn.", VX (4, 833), VX_MASK
, PPCVEC3
, 0, {VD
, VA
, VB
}},
4587 {"vminsh", VX (4, 834), VX_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
4588 {"vsrah", VX (4, 836), VX_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
4589 {"vcmpgtsh", VXR(4, 838,0), VXR_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
4590 {"vmulesh", VX (4, 840), VX_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
4591 {"vcfsx", VX (4, 842), VX_MASK
, PPCVEC
, 0, {VD
, VB
, UIMM
}},
4592 {"vcsxwfp", VX (4, 842), VX_MASK
, PPCVEC
, 0, {VD
, VB
, UIMM
}},
4593 {"vspltish", VX (4, 844), VXVB_MASK
, PPCVEC
, 0, {VD
, SIMM
}},
4594 {"vinserth", VX (4, 845), VXUIMM4_MASK
, PPCVEC3
, 0, {VD
, VB
, UIMM4
}},
4595 {"vupkhpx", VX (4, 846), VXVA_MASK
, PPCVEC
, 0, {VD
, VB
}},
4596 {"vinshrx", VX (4, 847), VX_MASK
, POWER10
, 0, {VD
, RA
, RB
}},
4597 {"mullhw", XRC(4, 424,0), X_MASK
, MULHW
, 0, {RT
, RA
, RB
}},
4598 {"mullhw.", XRC(4, 424,1), X_MASK
, MULHW
, 0, {RT
, RA
, RB
}},
4599 {"maclhw", XO (4, 428,0,0),XO_MASK
, MULHW
, 0, {RT
, RA
, RB
}},
4600 {"maclhw.", XO (4, 428,0,1),XO_MASK
, MULHW
, 0, {RT
, RA
, RB
}},
4601 {"nmaclhw", XO (4, 430,0,0),XO_MASK
, MULHW
, 0, {RT
, RA
, RB
}},
4602 {"nmaclhw.", XO (4, 430,0,1),XO_MASK
, MULHW
, 0, {RT
, RA
, RB
}},
4603 {"vaddsws", VX (4, 896), VX_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
4604 {"vminsw", VX (4, 898), VX_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
4605 {"vsraw", VX (4, 900), VX_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
4606 {"vcmpgtsw", VXR(4, 902,0), VXR_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
4607 {"vcmpgtsq", VXR(4, 903,0), VXR_MASK
, POWER10
, 0, {VD
, VA
, VB
}},
4608 {"vmulesw", VX (4, 904), VX_MASK
, PPCVEC2
, 0, {VD
, VA
, VB
}},
4609 {"vmulhsw", VX (4, 905), VX_MASK
, POWER10
, 0, {VD
, VA
, VB
}},
4610 {"vctuxs", VX (4, 906), VX_MASK
, PPCVEC
, 0, {VD
, VB
, UIMM
}},
4611 {"vcfpuxws", VX (4, 906), VX_MASK
, PPCVEC
, 0, {VD
, VB
, UIMM
}},
4612 {"vdivesw", VX (4, 907), VX_MASK
, POWER10
, 0, {VD
, VA
, VB
}},
4613 {"vspltisw", VX (4, 908), VXVB_MASK
, PPCVEC
, 0, {VD
, SIMM
}},
4614 {"vinsertw", VX (4, 909), VXUIMM4_MASK
, PPCVEC3
, 0, {VD
, VB
, UIMM4
}},
4615 {"vinswrx", VX (4, 911), VX_MASK
, POWER10
, 0, {VD
, RA
, RB
}},
4616 {"maclhwsu", XO (4, 460,0,0), XO_MASK
, MULHW
, 0, {RT
, RA
, RB
}},
4617 {"maclhwsu.", XO (4, 460,0,1), XO_MASK
, MULHW
, 0, {RT
, RA
, RB
}},
4618 {"vminsd", VX (4, 962), VX_MASK
, PPCVEC2
, 0, {VD
, VA
, VB
}},
4619 {"vsrad", VX (4, 964), VX_MASK
, PPCVEC2
, 0, {VD
, VA
, VB
}},
4620 {"vcmpbfp", VXR(4, 966,0), VXR_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
4621 {"vcmpgtsd", VXR(4, 967,0), VXR_MASK
, PPCVEC2
, 0, {VD
, VA
, VB
}},
4622 {"vmulesd", VX (4, 968), VX_MASK
, POWER10
, 0, {VD
, VA
, VB
}},
4623 {"vmulhsd", VX (4, 969), VX_MASK
, POWER10
, 0, {VD
, VA
, VB
}},
4624 {"vctsxs", VX (4, 970), VX_MASK
, PPCVEC
, 0, {VD
, VB
, UIMM
}},
4625 {"vcfpsxws", VX (4, 970), VX_MASK
, PPCVEC
, 0, {VD
, VB
, UIMM
}},
4626 {"vdivesd", VX (4, 971), VX_MASK
, POWER10
, 0, {VD
, VA
, VB
}},
4627 {"vinsertd", VX (4, 973), VXUIMM4_MASK
, PPCVEC3
, 0, {VD
, VB
, UIMM4
}},
4628 {"vupklpx", VX (4, 974), VXVA_MASK
, PPCVEC
, 0, {VD
, VB
}},
4629 {"vinsdrx", VX (4, 975), VX_MASK
, POWER10
, 0, {VD
, RA
, RB
}},
4630 {"maclhws", XO (4, 492,0,0), XO_MASK
, MULHW
, 0, {RT
, RA
, RB
}},
4631 {"maclhws.", XO (4, 492,0,1), XO_MASK
, MULHW
, 0, {RT
, RA
, RB
}},
4632 {"nmaclhws", XO (4, 494,0,0), XO_MASK
, MULHW
, 0, {RT
, RA
, RB
}},
4633 {"nmaclhws.", XO (4, 494,0,1), XO_MASK
, MULHW
, 0, {RT
, RA
, RB
}},
4634 {"vsububm", VX (4,1024), VX_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
4635 {"bcdadd.", VX (4,1025), VXPS_MASK
, PPCVEC2
, 0, {VD
, VA
, VB
, PS
}},
4636 {"vavgub", VX (4,1026), VX_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
4637 {"vabsdub", VX (4,1027), VX_MASK
, PPCVEC2
, 0, {VD
, VA
, VB
}},
4638 {"evmhessf", VX (4,1027), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
4639 {"vand", VX (4,1028), VX_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
4640 {"vcmpequb.", VXR(4, 6,1), VXR_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
4641 {"vcmpneb.", VXR(4, 7,1), VXR_MASK
, PPCVEC3
, 0, {VD
, VA
, VB
}},
4642 {"udi0fcm.", APU(4, 515,0), APU_MASK
, PPC405
|PPC440
, 0, {URT
, URA
, URB
}},
4643 {"udi0fcm", APU(4, 515,1), APU_MASK
, PPC405
|PPC440
, 0, {URT
, URA
, URB
}},
4644 {"evmhossf", VX (4,1031), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
4645 {"vpmsumb", VX (4,1032), VX_MASK
, PPCVEC2
, 0, {VD
, VA
, VB
}},
4646 {"evmheumi", VX (4,1032), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
4647 {"evmhesmi", VX (4,1033), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
4648 {"vmaxfp", VX (4,1034), VX_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
4649 {"evmhesmf", VX (4,1035), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
4650 {"evmhoumi", VX (4,1036), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
4651 {"vslo", VX (4,1036), VX_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
4652 {"evmhosmi", VX (4,1037), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
4653 {"evmhosmf", VX (4,1039), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
4654 {"machhwuo", XO (4, 12,1,0), XO_MASK
, MULHW
, 0, {RT
, RA
, RB
}},
4655 {"machhwuo.", XO (4, 12,1,1), XO_MASK
, MULHW
, 0, {RT
, RA
, RB
}},
4656 {"ps_merge00", XOPS(4,528,0), XOPS_MASK
, PPCPS
, 0, {FRT
, FRA
, FRB
}},
4657 {"ps_merge00.", XOPS(4,528,1), XOPS_MASK
, PPCPS
, 0, {FRT
, FRA
, FRB
}},
4658 {"evmhessfa", VX (4,1059), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
4659 {"evmhossfa", VX (4,1063), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
4660 {"evmheumia", VX (4,1064), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
4661 {"evmhesmia", VX (4,1065), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
4662 {"evmhesmfa", VX (4,1067), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
4663 {"evmhoumia", VX (4,1068), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
4664 {"evmhosmia", VX (4,1069), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
4665 {"evmhosmfa", VX (4,1071), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
4666 {"vsubuhm", VX (4,1088), VX_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
4667 {"bcdsub.", VX (4,1089), VXPS_MASK
, PPCVEC2
, 0, {VD
, VA
, VB
, PS
}},
4668 {"vavguh", VX (4,1090), VX_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
4669 {"evmwlssf", VX (4,1091), VX_MASK
, PPCSPE
, 0, {RD
, RA
, RB
}},
4670 {"vabsduh", VX (4,1091), VX_MASK
, PPCVEC2
, 0, {VD
, VA
, VB
}},
4671 {"vandc", VX (4,1092), VX_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
4672 {"vcmpequh.", VXR(4, 70,1), VXR_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
4673 {"udi1fcm.", APU(4, 547,0), APU_MASK
, PPC405
|PPC440
, 0, {URT
, URA
, URB
}},
4674 {"udi1fcm", APU(4, 547,1), APU_MASK
, PPC405
|PPC440
, 0, {URT
, URA
, URB
}},
4675 {"vcmpneh.", VXR(4, 71,1), VXR_MASK
, PPCVEC3
, 0, {VD
, VA
, VB
}},
4676 {"evmwhssf", VX (4,1095), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
4677 {"vpmsumh", VX (4,1096), VX_MASK
, PPCVEC2
, 0, {VD
, VA
, VB
}},
4678 {"evmwlumi", VX (4,1096), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
4679 {"vminfp", VX (4,1098), VX_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
4680 {"evmwlsmf", VX (4,1099), VX_MASK
, PPCSPE
, 0, {RD
, RA
, RB
}},
4681 {"evmwhumi", VX (4,1100), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
4682 {"vsro", VX (4,1100), VX_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
4683 {"evmwhsmi", VX (4,1101), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
4684 {"vpkudum", VX (4,1102), VX_MASK
, PPCVEC2
, 0, {VD
, VA
, VB
}},
4685 {"evmwhsmf", VX (4,1103), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
4686 {"evmwssf", VX (4,1107), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
4687 {"machhwo", XO (4, 44,1,0), XO_MASK
, MULHW
, 0, {RT
, RA
, RB
}},
4688 {"evmwumi", VX (4,1112), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
4689 {"machhwo.", XO (4, 44,1,1), XO_MASK
, MULHW
, 0, {RT
, RA
, RB
}},
4690 {"evmwsmi", VX (4,1113), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
4691 {"evmwsmf", VX (4,1115), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
4692 {"nmachhwo", XO (4, 46,1,0), XO_MASK
, MULHW
, 0, {RT
, RA
, RB
}},
4693 {"nmachhwo.", XO (4, 46,1,1), XO_MASK
, MULHW
, 0, {RT
, RA
, RB
}},
4694 {"ps_merge01", XOPS(4,560,0), XOPS_MASK
, PPCPS
, 0, {FRT
, FRA
, FRB
}},
4695 {"ps_merge01.", XOPS(4,560,1), XOPS_MASK
, PPCPS
, 0, {FRT
, FRA
, FRB
}},
4696 {"evmwlssfa", VX (4,1123), VX_MASK
, PPCSPE
, 0, {RD
, RA
, RB
}},
4697 {"evmwhssfa", VX (4,1127), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
4698 {"evmwlumia", VX (4,1128), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
4699 {"evmwlsmfa", VX (4,1131), VX_MASK
, PPCSPE
, 0, {RD
, RA
, RB
}},
4700 {"evmwhumia", VX (4,1132), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
4701 {"evmwhsmia", VX (4,1133), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
4702 {"evmwhsmfa", VX (4,1135), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
4703 {"evmwssfa", VX (4,1139), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
4704 {"evmwumia", VX (4,1144), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
4705 {"evmwsmia", VX (4,1145), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
4706 {"evmwsmfa", VX (4,1147), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
4707 {"vsubuwm", VX (4,1152), VX_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
4708 {"bcdus.", VX (4,1153), VX_MASK
, PPCVEC3
, 0, {VD
, VA
, VB
}},
4709 {"vavguw", VX (4,1154), VX_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
4710 {"vabsduw", VX (4,1155), VX_MASK
, PPCVEC2
, 0, {VD
, VA
, VB
}},
4711 {"vmr", VX (4,1156), VX_MASK
, PPCVEC
, 0, {VD
, VAB
}},
4712 {"vor", VX (4,1156), VX_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
4713 {"vcmpnew.", VXR(4, 135,1), VXR_MASK
, PPCVEC3
, 0, {VD
, VA
, VB
}},
4714 {"vpmsumw", VX (4,1160), VX_MASK
, PPCVEC2
, 0, {VD
, VA
, VB
}},
4715 {"vcmpequw.", VXR(4, 134,1), VXR_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
4716 {"udi2fcm.", APU(4, 579,0), APU_MASK
, PPC405
|PPC440
, 0, {URT
, URA
, URB
}},
4717 {"udi2fcm", APU(4, 579,1), APU_MASK
, PPC405
|PPC440
, 0, {URT
, URA
, URB
}},
4718 {"machhwsuo", XO (4, 76,1,0), XO_MASK
, MULHW
, 0, {RT
, RA
, RB
}},
4719 {"machhwsuo.", XO (4, 76,1,1), XO_MASK
, MULHW
, 0, {RT
, RA
, RB
}},
4720 {"ps_merge10", XOPS(4,592,0), XOPS_MASK
, PPCPS
, 0, {FRT
, FRA
, FRB
}},
4721 {"ps_merge10.", XOPS(4,592,1), XOPS_MASK
, PPCPS
, 0, {FRT
, FRA
, FRB
}},
4722 {"vsubudm", VX (4,1216), VX_MASK
, PPCVEC2
, 0, {VD
, VA
, VB
}},
4723 {"evaddusiaaw", VX (4,1216), VX_MASK
, PPCSPE
, 0, {RS
, RA
}},
4724 {"bcds.", VX (4,1217), VXPS_MASK
, PPCVEC3
, 0, {VD
, VA
, VB
, PS
}},
4725 {"evaddssiaaw", VX (4,1217), VX_MASK
, PPCSPE
, 0, {RS
, RA
}},
4726 {"evsubfusiaaw",VX (4,1218), VX_MASK
, PPCSPE
, 0, {RS
, RA
}},
4727 {"evsubfssiaaw",VX (4,1219), VX_MASK
, PPCSPE
, 0, {RS
, RA
}},
4728 {"evmra", VX (4,1220), VX_MASK
, PPCSPE
, 0, {RS
, RA
}},
4729 {"vxor", VX (4,1220), VX_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
4730 {"evdivws", VX (4,1222), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
4731 {"vcmpeqfp.", VXR(4, 198,1), VXR_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
4732 {"udi3fcm.", APU(4, 611,0), APU_MASK
, PPC405
|PPC440
, 0, {URT
, URA
, URB
}},
4733 {"vcmpequd.", VXR(4, 199,1), VXR_MASK
, PPCVEC2
, 0, {VD
, VA
, VB
}},
4734 {"udi3fcm", APU(4, 611,1), APU_MASK
, PPC405
|PPC440
, 0, {URT
, URA
, URB
}},
4735 {"evdivwu", VX (4,1223), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
4736 {"vpmsumd", VX (4,1224), VX_MASK
, PPCVEC2
, 0, {VD
, VA
, VB
}},
4737 {"evaddumiaaw", VX (4,1224), VX_MASK
, PPCSPE
, 0, {RS
, RA
}},
4738 {"evaddsmiaaw", VX (4,1225), VX_MASK
, PPCSPE
, 0, {RS
, RA
}},
4739 {"evsubfumiaaw",VX (4,1226), VX_MASK
, PPCSPE
, 0, {RS
, RA
}},
4740 {"evsubfsmiaaw",VX (4,1227), VX_MASK
, PPCSPE
, 0, {RS
, RA
}},
4741 {"vpkudus", VX (4,1230), VX_MASK
, PPCVEC2
, 0, {VD
, VA
, VB
}},
4742 {"machhwso", XO (4, 108,1,0), XO_MASK
, MULHW
, 0, {RT
, RA
, RB
}},
4743 {"machhwso.", XO (4, 108,1,1), XO_MASK
, MULHW
, 0, {RT
, RA
, RB
}},
4744 {"nmachhwso", XO (4, 110,1,0), XO_MASK
, MULHW
, 0, {RT
, RA
, RB
}},
4745 {"nmachhwso.", XO (4, 110,1,1), XO_MASK
, MULHW
, 0, {RT
, RA
, RB
}},
4746 {"ps_merge11", XOPS(4,624,0), XOPS_MASK
, PPCPS
, 0, {FRT
, FRA
, FRB
}},
4747 {"ps_merge11.", XOPS(4,624,1), XOPS_MASK
, PPCPS
, 0, {FRT
, FRA
, FRB
}},
4748 {"vsubuqm", VX (4,1280), VX_MASK
, PPCVEC2
, 0, {VD
, VA
, VB
}},
4749 {"evmheusiaaw", VX (4,1280), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
4750 {"bcdtrunc.", VX (4,1281), VXPS_MASK
, PPCVEC3
, 0, {VD
, VA
, VB
, PS
}},
4751 {"evmhessiaaw", VX (4,1281), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
4752 {"vavgsb", VX (4,1282), VX_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
4753 {"evmhessfaaw", VX (4,1283), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
4754 {"evmhousiaaw", VX (4,1284), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
4755 {"vnot", VX (4,1284), VX_MASK
, PPCVEC
, 0, {VD
, VAB
}},
4756 {"vnor", VX (4,1284), VX_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
4757 {"evmhossiaaw", VX (4,1285), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
4758 {"udi4fcm.", APU(4, 643,0), APU_MASK
, PPC405
|PPC440
, 0, {URT
, URA
, URB
}},
4759 {"udi4fcm", APU(4, 643,1), APU_MASK
, PPC405
|PPC440
, 0, {URT
, URA
, URB
}},
4760 {"vcmpnezb.", VXR(4, 263,1), VXR_MASK
, PPCVEC3
, 0, {VD
, VA
, VB
}},
4761 {"evmhossfaaw", VX (4,1287), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
4762 {"evmheumiaaw", VX (4,1288), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
4763 {"vcipher", VX (4,1288), VX_MASK
, PPCVEC2
, 0, {VD
, VA
, VB
}},
4764 {"vcipherlast", VX (4,1289), VX_MASK
, PPCVEC2
, 0, {VD
, VA
, VB
}},
4765 {"evmhesmiaaw", VX (4,1289), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
4766 {"evmhesmfaaw", VX (4,1291), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
4767 {"vgbbd", VX (4,1292), VXVA_MASK
, PPCVEC2
, 0, {VD
, VB
}},
4768 {"evmhoumiaaw", VX (4,1292), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
4769 {"evmhosmiaaw", VX (4,1293), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
4770 {"evmhosmfaaw", VX (4,1295), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
4771 {"macchwuo", XO (4, 140,1,0), XO_MASK
, MULHW
, 0, {RT
, RA
, RB
}},
4772 {"macchwuo.", XO (4, 140,1,1), XO_MASK
, MULHW
, 0, {RT
, RA
, RB
}},
4773 {"evmhegumiaa", VX (4,1320), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
4774 {"evmhegsmiaa", VX (4,1321), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
4775 {"evmhegsmfaa", VX (4,1323), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
4776 {"evmhogumiaa", VX (4,1324), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
4777 {"evmhogsmiaa", VX (4,1325), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
4778 {"evmhogsmfaa", VX (4,1327), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
4779 {"vsubcuq", VX (4,1344), VX_MASK
, PPCVEC2
, 0, {VD
, VA
, VB
}},
4780 {"evmwlusiaaw", VX (4,1344), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
4781 {"bcdutrunc.", VX (4,1345), VX_MASK
, PPCVEC3
, 0, {VD
, VA
, VB
}},
4782 {"evmwlssiaaw", VX (4,1345), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
4783 {"vavgsh", VX (4,1346), VX_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
4784 {"evmwlssfaaw", VX (4,1347), VX_MASK
, PPCSPE
, 0, {RD
, RA
, RB
}},
4785 {"evmwhusiaa", VX (4,1348), VX_MASK
, PPCSPE
, 0, {RD
, RA
, RB
}},
4786 {"vorc", VX (4,1348), VX_MASK
, PPCVEC2
, 0, {VD
, VA
, VB
}},
4787 {"evmwhssmaa", VX (4,1349), VX_MASK
, PPCSPE
, 0, {RD
, RA
, RB
}},
4788 {"udi5fcm.", APU(4, 675,0), APU_MASK
, PPC405
|PPC440
, 0, {URT
, URA
, URB
}},
4789 {"udi5fcm", APU(4, 675,1), APU_MASK
, PPC405
|PPC440
, 0, {URT
, URA
, URB
}},
4790 {"vcmpnezh.", VXR(4, 327,1), VXR_MASK
, PPCVEC3
, 0, {VD
, VA
, VB
}},
4791 {"evmwhssfaa", VX (4,1351), VX_MASK
, PPCSPE
, 0, {RD
, RA
, RB
}},
4792 {"vncipher", VX (4,1352), VX_MASK
, PPCVEC2
, 0, {VD
, VA
, VB
}},
4793 {"evmwlumiaaw", VX (4,1352), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
4794 {"vncipherlast",VX (4,1353), VX_MASK
, PPCVEC2
, 0, {VD
, VA
, VB
}},
4795 {"evmwlsmiaaw", VX (4,1353), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
4796 {"evmwlsmfaaw", VX (4,1355), VX_MASK
, PPCSPE
, 0, {RD
, RA
, RB
}},
4797 {"evmwhumiaa", VX (4,1356), VX_MASK
, PPCSPE
, 0, {RD
, RA
, RB
}},
4798 {"vbpermq", VX (4,1356), VX_MASK
, PPCVEC2
, 0, {VD
, VA
, VB
}},
4799 {"evmwhsmiaa", VX (4,1357), VX_MASK
, PPCSPE
, 0, {RD
, RA
, RB
}},
4800 {"vpksdus", VX (4,1358), VX_MASK
, PPCVEC2
, 0, {VD
, VA
, VB
}},
4801 {"evmwhsmfaa", VX (4,1359), VX_MASK
, PPCSPE
, 0, {RD
, RA
, RB
}},
4802 {"evmwssfaa", VX (4,1363), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
4803 {"macchwo", XO (4, 172,1,0), XO_MASK
, MULHW
, 0, {RT
, RA
, RB
}},
4804 {"evmwumiaa", VX (4,1368), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
4805 {"macchwo.", XO (4, 172,1,1), XO_MASK
, MULHW
, 0, {RT
, RA
, RB
}},
4806 {"evmwsmiaa", VX (4,1369), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
4807 {"evmwsmfaa", VX (4,1371), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
4808 {"nmacchwo", XO (4, 174,1,0), XO_MASK
, MULHW
, 0, {RT
, RA
, RB
}},
4809 {"nmacchwo.", XO (4, 174,1,1), XO_MASK
, MULHW
, 0, {RT
, RA
, RB
}},
4810 {"evmwhgumiaa", VX (4,1380), VX_MASK
, PPCSPE
, 0, {RD
, RA
, RB
}},
4811 {"evmwhgsmiaa", VX (4,1381), VX_MASK
, PPCSPE
, 0, {RD
, RA
, RB
}},
4812 {"evmwhgssfaa", VX (4,1383), VX_MASK
, PPCSPE
, 0, {RD
, RA
, RB
}},
4813 {"evmwhgsmfaa", VX (4,1391), VX_MASK
, PPCSPE
, 0, {RD
, RA
, RB
}},
4814 {"evmheusianw", VX (4,1408), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
4815 {"vsubcuw", VX (4,1408), VX_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
4816 {"evmhessianw", VX (4,1409), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
4817 {"bcdctsq.", VXVA(4,1409,0), VXVA_MASK
, PPCVEC3
, 0, {VD
, VB
}},
4818 {"bcdcfsq.", VXVA(4,1409,2), VXVAPS_MASK
, PPCVEC3
, 0, {VD
, VB
, PS
}},
4819 {"bcdctz.", VXVA(4,1409,4), VXVAPS_MASK
, PPCVEC3
, 0, {VD
, VB
, PS
}},
4820 {"bcdctn.", VXVA(4,1409,5), VXVA_MASK
, PPCVEC3
, 0, {VD
, VB
}},
4821 {"bcdcfz.", VXVA(4,1409,6), VXVAPS_MASK
, PPCVEC3
, 0, {VD
, VB
, PS
}},
4822 {"bcdcfn.", VXVA(4,1409,7), VXVAPS_MASK
, PPCVEC3
, 0, {VD
, VB
, PS
}},
4823 {"bcdsetsgn.", VXVA(4,1409,31), VXVAPS_MASK
, PPCVEC3
, 0, {VD
, VB
, PS
}},
4824 {"vavgsw", VX (4,1410), VX_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
4825 {"evmhessfanw", VX (4,1411), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
4826 {"vnand", VX (4,1412), VX_MASK
, PPCVEC2
, 0, {VD
, VA
, VB
}},
4827 {"evmhousianw", VX (4,1412), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
4828 {"evmhossianw", VX (4,1413), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
4829 {"udi6fcm.", APU(4, 707,0), APU_MASK
, PPC405
|PPC440
, 0, {URT
, URA
, URB
}},
4830 {"udi6fcm", APU(4, 707,1), APU_MASK
, PPC405
|PPC440
, 0, {URT
, URA
, URB
}},
4831 {"vcmpnezw.", VXR(4, 391,1), VXR_MASK
, PPCVEC3
, 0, {VD
, VA
, VB
}},
4832 {"evmhossfanw", VX (4,1415), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
4833 {"evmheumianw", VX (4,1416), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
4834 {"evmhesmianw", VX (4,1417), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
4835 {"evmhesmfanw", VX (4,1419), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
4836 {"evmhoumianw", VX (4,1420), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
4837 {"evmhosmianw", VX (4,1421), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
4838 {"evmhosmfanw", VX (4,1423), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
4839 {"macchwsuo", XO (4, 204,1,0), XO_MASK
, MULHW
, 0, {RT
, RA
, RB
}},
4840 {"macchwsuo.", XO (4, 204,1,1), XO_MASK
, MULHW
, 0, {RT
, RA
, RB
}},
4841 {"evmhegumian", VX (4,1448), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
4842 {"evmhegsmian", VX (4,1449), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
4843 {"evmhegsmfan", VX (4,1451), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
4844 {"evmhogumian", VX (4,1452), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
4845 {"evmhogsmian", VX (4,1453), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
4846 {"evmhogsmfan", VX (4,1455), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
4847 {"evmwlusianw", VX (4,1472), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
4848 {"bcdsr.", VX (4,1473), VXPS_MASK
, PPCVEC3
, 0, {VD
, VA
, VB
, PS
}},
4849 {"evmwlssianw", VX (4,1473), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
4850 {"evmwlssfanw", VX (4,1475), VX_MASK
, PPCSPE
, 0, {RD
, RA
, RB
}},
4851 {"evmwhusian", VX (4,1476), VX_MASK
, PPCSPE
, 0, {RD
, RA
, RB
}},
4852 {"vsld", VX (4,1476), VX_MASK
, PPCVEC2
, 0, {VD
, VA
, VB
}},
4853 {"evmwhssian", VX (4,1477), VX_MASK
, PPCSPE
, 0, {RD
, RA
, RB
}},
4854 {"vcmpgefp.", VXR(4, 454,1), VXR_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
4855 {"udi7fcm.", APU(4, 739,0), APU_MASK
, PPC405
|PPC440
, 0, {URT
, URA
, URB
}},
4856 {"udi7fcm", APU(4, 739,1), APU_MASK
, PPC405
|PPC440
, 0, {URT
, URA
, URB
}},
4857 {"vcmpequq.", VXR(4, 455,1), VXR_MASK
, POWER10
, 0, {VD
, VA
, VB
}},
4858 {"evmwhssfan", VX (4,1479), VX_MASK
, PPCSPE
, 0, {RD
, RA
, RB
}},
4859 {"vsbox", VX (4,1480), VXVB_MASK
, PPCVEC2
, 0, {VD
, VA
}},
4860 {"evmwlumianw", VX (4,1480), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
4861 {"evmwlsmianw", VX (4,1481), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
4862 {"evmwlsmfanw", VX (4,1483), VX_MASK
, PPCSPE
, 0, {RD
, RA
, RB
}},
4863 {"evmwhumian", VX (4,1484), VX_MASK
, PPCSPE
, 0, {RD
, RA
, RB
}},
4864 {"vbpermd", VX (4,1484), VX_MASK
, PPCVEC3
, 0, {VD
, VA
, VB
}},
4865 {"evmwhsmian", VX (4,1485), VX_MASK
, PPCSPE
, 0, {RD
, RA
, RB
}},
4866 {"vpksdss", VX (4,1486), VX_MASK
, PPCVEC2
, 0, {VD
, VA
, VB
}},
4867 {"evmwhsmfan", VX (4,1487), VX_MASK
, PPCSPE
, 0, {RD
, RA
, RB
}},
4868 {"evmwssfan", VX (4,1491), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
4869 {"macchwso", XO (4, 236,1,0), XO_MASK
, MULHW
, 0, {RT
, RA
, RB
}},
4870 {"evmwumian", VX (4,1496), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
4871 {"macchwso.", XO (4, 236,1,1), XO_MASK
, MULHW
, 0, {RT
, RA
, RB
}},
4872 {"evmwsmian", VX (4,1497), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
4873 {"evmwsmfan", VX (4,1499), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
4874 {"evmwhgumian", VX (4,1508), VX_MASK
, PPCSPE
, 0, {RD
, RA
, RB
}},
4875 {"evmwhgsmian", VX (4,1509), VX_MASK
, PPCSPE
, 0, {RD
, RA
, RB
}},
4876 {"evmwhgssfan", VX (4,1511), VX_MASK
, PPCSPE
, 0, {RD
, RA
, RB
}},
4877 {"evmwhgsmfan", VX (4,1519), VX_MASK
, PPCSPE
, 0, {RD
, RA
, RB
}},
4878 {"nmacchwso", XO (4, 238,1,0), XO_MASK
, MULHW
, 0, {RT
, RA
, RB
}},
4879 {"nmacchwso.", XO (4, 238,1,1), XO_MASK
, MULHW
, 0, {RT
, RA
, RB
}},
4880 {"vsububs", VX (4,1536), VX_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
4881 {"vclzlsbb", VXVA(4,1538,0), VXVA_MASK
, PPCVEC3
, 0, {RT
, VB
}},
4882 {"vctzlsbb", VXVA(4,1538,1), VXVA_MASK
, PPCVEC3
, 0, {RT
, VB
}},
4883 {"vnegw", VXVA(4,1538,6), VXVA_MASK
, PPCVEC3
, 0, {VD
, VB
}},
4884 {"vnegd", VXVA(4,1538,7), VXVA_MASK
, PPCVEC3
, 0, {VD
, VB
}},
4885 {"vprtybw", VXVA(4,1538,8), VXVA_MASK
, PPCVEC3
, 0, {VD
, VB
}},
4886 {"vprtybd", VXVA(4,1538,9), VXVA_MASK
, PPCVEC3
, 0, {VD
, VB
}},
4887 {"vprtybq", VXVA(4,1538,10), VXVA_MASK
, PPCVEC3
, 0, {VD
, VB
}},
4888 {"vextsb2w", VXVA(4,1538,16), VXVA_MASK
, PPCVEC3
, 0, {VD
, VB
}},
4889 {"vextsh2w", VXVA(4,1538,17), VXVA_MASK
, PPCVEC3
, 0, {VD
, VB
}},
4890 {"vextsb2d", VXVA(4,1538,24), VXVA_MASK
, PPCVEC3
, 0, {VD
, VB
}},
4891 {"vextsh2d", VXVA(4,1538,25), VXVA_MASK
, PPCVEC3
, 0, {VD
, VB
}},
4892 {"vextsw2d", VXVA(4,1538,26), VXVA_MASK
, PPCVEC3
, 0, {VD
, VB
}},
4893 {"vextsd2q", VXVA(4,1538,27), VXVA_MASK
, POWER10
, 0, {VD
, VB
}},
4894 {"vctzb", VXVA(4,1538,28), VXVA_MASK
, PPCVEC3
, 0, {VD
, VB
}},
4895 {"vctzh", VXVA(4,1538,29), VXVA_MASK
, PPCVEC3
, 0, {VD
, VB
}},
4896 {"vctzw", VXVA(4,1538,30), VXVA_MASK
, PPCVEC3
, 0, {VD
, VB
}},
4897 {"vctzd", VXVA(4,1538,31), VXVA_MASK
, PPCVEC3
, 0, {VD
, VB
}},
4898 {"mfvscr", VX (4,1540), VXVAVB_MASK
, PPCVEC
, 0, {VD
}},
4899 {"vcmpgtub.", VXR(4, 518,1), VXR_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
4900 {"udi8fcm.", APU(4, 771,0), APU_MASK
, PPC440
, 0, {URT
, URA
, URB
}},
4901 {"udi8fcm", APU(4, 771,1), APU_MASK
, PPC440
, 0, {URT
, URA
, URB
}},
4902 {"vsum4ubs", VX (4,1544), VX_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
4903 {"vmoduq", VX (4,1547), VX_MASK
, POWER10
, 0, {VD
, VA
, VB
}},
4904 {"vextublx", VX (4,1549), VX_MASK
, PPCVEC3
, 0, {RT
, RA
, VB
}},
4905 {"vsubuhs", VX (4,1600), VX_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
4907 {"vexpandbm", VXVA(4,1602,0), VXVA_MASK
, POWER10
, 0, {VD
, VB
}},
4908 {"vexpandhm", VXVA(4,1602,1), VXVA_MASK
, POWER10
, 0, {VD
, VB
}},
4909 {"vexpandwm", VXVA(4,1602,2), VXVA_MASK
, POWER10
, 0, {VD
, VB
}},
4910 {"vexpanddm", VXVA(4,1602,3), VXVA_MASK
, POWER10
, 0, {VD
, VB
}},
4911 {"vexpandqm", VXVA(4,1602,4), VXVA_MASK
, POWER10
, 0, {VD
, VB
}},
4912 {"vextractbm", VXVA(4,1602,8), VXVA_MASK
, POWER10
, 0, {RT
, VB
}},
4913 {"vextracthm", VXVA(4,1602,9), VXVA_MASK
, POWER10
, 0, {RT
, VB
}},
4914 {"vextractwm", VXVA(4,1602,10), VXVA_MASK
, POWER10
, 0, {RT
, VB
}},
4915 {"vextractdm", VXVA(4,1602,11), VXVA_MASK
, POWER10
, 0, {RT
, VB
}},
4916 {"vextractqm", VXVA(4,1602,12), VXVA_MASK
, POWER10
, 0, {RT
, VB
}},
4917 {"mtvsrbm", VXVA(4,1602,16), VXVA_MASK
, POWER10
, 0, {VD
, RB
}},
4918 {"mtvsrhm", VXVA(4,1602,17), VXVA_MASK
, POWER10
, 0, {VD
, RB
}},
4919 {"mtvsrwm", VXVA(4,1602,18), VXVA_MASK
, POWER10
, 0, {VD
, RB
}},
4920 {"mtvsrdm", VXVA(4,1602,19), VXVA_MASK
, POWER10
, 0, {VD
, RB
}},
4921 {"mtvsrqm", VXVA(4,1602,20), VXVA_MASK
, POWER10
, 0, {VD
, RB
}},
4922 {"vcntmbb", VXVA(4,1602,24), VXVAM_MASK
, POWER10
, 0, {RT
, VB
, MP
}},
4923 {"vcntmbh", VXVA(4,1602,26), VXVAM_MASK
, POWER10
, 0, {RT
, VB
, MP
}},
4924 {"vcntmbw", VXVA(4,1602,28), VXVAM_MASK
, POWER10
, 0, {RT
, VB
, MP
}},
4925 {"vcntmbd", VXVA(4,1602,30), VXVAM_MASK
, POWER10
, 0, {RT
, VB
, MP
}},
4927 {"mtvscr", VX (4,1604), VXVDVA_MASK
, PPCVEC
, 0, {VB
}},
4928 {"vcmpgtuh.", VXR(4, 582,1), VXR_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
4929 {"vsum4shs", VX (4,1608), VX_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
4930 {"udi9fcm.", APU(4, 804,0), APU_MASK
, PPC440
, 0, {URT
, URA
, URB
}},
4931 {"udi9fcm", APU(4, 804,1), APU_MASK
, PPC440
, 0, {URT
, URA
, URB
}},
4932 {"vextuhlx", VX (4,1613), VX_MASK
, PPCVEC3
, 0, {RT
, RA
, VB
}},
4933 {"vupkhsw", VX (4,1614), VXVA_MASK
, PPCVEC2
, 0, {VD
, VB
}},
4934 {"vsubuws", VX (4,1664), VX_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
4935 {"vshasigmaw", VX (4,1666), VX_MASK
, PPCVEC2
, 0, {VD
, VA
, ST
, SIX
}},
4936 {"veqv", VX (4,1668), VX_MASK
, PPCVEC2
, 0, {VD
, VA
, VB
}},
4937 {"vcmpgtuw.", VXR(4, 646,1), VXR_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
4938 {"udi10fcm.", APU(4, 835,0), APU_MASK
, PPC440
, 0, {URT
, URA
, URB
}},
4939 {"vcmpgtuq.", VXR(4, 647,1), VXR_MASK
, POWER10
, 0, {VD
, VA
, VB
}},
4940 {"udi10fcm", APU(4, 835,1), APU_MASK
, PPC440
, 0, {URT
, URA
, URB
}},
4941 {"vsum2sws", VX (4,1672), VX_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
4942 {"vmoduw", VX (4,1675), VX_MASK
, POWER10
, 0, {VD
, VA
, VB
}},
4943 {"vmrgow", VX (4,1676), VX_MASK
, PPCVEC2
, 0, {VD
, VA
, VB
}},
4944 {"vextuwlx", VX (4,1677), VX_MASK
, PPCVEC3
, 0, {RT
, RA
, VB
}},
4945 {"vshasigmad", VX (4,1730), VX_MASK
, PPCVEC2
, 0, {VD
, VA
, ST
, SIX
}},
4946 {"vsrd", VX (4,1732), VX_MASK
, PPCVEC2
, 0, {VD
, VA
, VB
}},
4947 {"vcmpgtfp.", VXR(4, 710,1), VXR_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
4948 {"udi11fcm.", APU(4, 867,0), APU_MASK
, PPC440
, 0, {URT
, URA
, URB
}},
4949 {"vcmpgtud.", VXR(4, 711,1), VXR_MASK
, PPCVEC2
, 0, {VD
, VA
, VB
}},
4950 {"udi11fcm", APU(4, 867,1), APU_MASK
, PPC440
, 0, {URT
, URA
, URB
}},
4951 {"vmodud", VX (4,1739), VX_MASK
, POWER10
, 0, {VD
, VA
, VB
}},
4952 {"vupklsw", VX (4,1742), VXVA_MASK
, PPCVEC2
, 0, {VD
, VB
}},
4953 {"vsubsbs", VX (4,1792), VX_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
4954 {"vclzb", VX (4,1794), VXVA_MASK
, PPCVEC2
, 0, {VD
, VB
}},
4955 {"vpopcntb", VX (4,1795), VXVA_MASK
, PPCVEC2
, 0, {VD
, VB
}},
4956 {"vsrv", VX (4,1796), VX_MASK
, PPCVEC3
, 0, {VD
, VA
, VB
}},
4957 {"vcmpgtsb.", VXR(4, 774,1), VXR_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
4958 {"udi12fcm.", APU(4, 899,0), APU_MASK
, PPC440
, 0, {URT
, URA
, URB
}},
4959 {"udi12fcm", APU(4, 899,1), APU_MASK
, PPC440
, 0, {URT
, URA
, URB
}},
4960 {"vsum4sbs", VX (4,1800), VX_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
4961 {"vmodsq", VX (4,1803), VX_MASK
, POWER10
, 0, {VD
, VA
, VB
}},
4962 {"vextubrx", VX (4,1805), VX_MASK
, PPCVEC3
, 0, {RT
, RA
, VB
}},
4963 {"maclhwuo", XO (4, 396,1,0), XO_MASK
, MULHW
, 0, {RT
, RA
, RB
}},
4964 {"maclhwuo.", XO (4, 396,1,1), XO_MASK
, MULHW
, 0, {RT
, RA
, RB
}},
4965 {"vsubshs", VX (4,1856), VX_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
4966 {"vclzh", VX (4,1858), VXVA_MASK
, PPCVEC2
, 0, {VD
, VB
}},
4967 {"vpopcnth", VX (4,1859), VXVA_MASK
, PPCVEC2
, 0, {VD
, VB
}},
4968 {"vslv", VX (4,1860), VX_MASK
, PPCVEC3
, 0, {VD
, VA
, VB
}},
4969 {"vcmpgtsh.", VXR(4, 838,1), VXR_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
4970 {"vextuhrx", VX (4,1869), VX_MASK
, PPCVEC3
, 0, {RT
, RA
, VB
}},
4971 {"udi13fcm.", APU(4, 931,0), APU_MASK
, PPC440
, 0, {URT
, URA
, URB
}},
4972 {"udi13fcm", APU(4, 931,1), APU_MASK
, PPC440
, 0, {URT
, URA
, URB
}},
4973 {"maclhwo", XO (4, 428,1,0), XO_MASK
, MULHW
, 0, {RT
, RA
, RB
}},
4974 {"maclhwo.", XO (4, 428,1,1), XO_MASK
, MULHW
, 0, {RT
, RA
, RB
}},
4975 {"nmaclhwo", XO (4, 430,1,0), XO_MASK
, MULHW
, 0, {RT
, RA
, RB
}},
4976 {"nmaclhwo.", XO (4, 430,1,1), XO_MASK
, MULHW
, 0, {RT
, RA
, RB
}},
4977 {"vsubsws", VX (4,1920), VX_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
4978 {"vclzw", VX (4,1922), VXVA_MASK
, PPCVEC2
, 0, {VD
, VB
}},
4979 {"vpopcntw", VX (4,1923), VXVA_MASK
, PPCVEC2
, 0, {VD
, VB
}},
4980 {"vcmpgtsw.", VXR(4, 902,1), VXR_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
4981 {"udi14fcm.", APU(4, 963,0), APU_MASK
, PPC440
, 0, {URT
, URA
, URB
}},
4982 {"vcmpgtsq.", VXR(4, 903,1), VXR_MASK
, POWER10
, 0, {VD
, VA
, VB
}},
4983 {"udi14fcm", APU(4, 963,1), APU_MASK
, PPC440
, 0, {URT
, URA
, URB
}},
4984 {"vsumsws", VX (4,1928), VX_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
4985 {"vmodsw", VX (4,1931), VX_MASK
, POWER10
, 0, {VD
, VA
, VB
}},
4986 {"vmrgew", VX (4,1932), VX_MASK
, PPCVEC2
, 0, {VD
, VA
, VB
}},
4987 {"vextuwrx", VX (4,1933), VX_MASK
, PPCVEC3
, 0, {RT
, RA
, VB
}},
4988 {"maclhwsuo", XO (4, 460,1,0), XO_MASK
, MULHW
, 0, {RT
, RA
, RB
}},
4989 {"maclhwsuo.", XO (4, 460,1,1), XO_MASK
, MULHW
, 0, {RT
, RA
, RB
}},
4990 {"vclzd", VX (4,1986), VXVA_MASK
, PPCVEC2
, 0, {VD
, VB
}},
4991 {"vpopcntd", VX (4,1987), VXVA_MASK
, PPCVEC2
, 0, {VD
, VB
}},
4992 {"vcmpbfp.", VXR(4, 966,1), VXR_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
4993 {"udi15fcm.", APU(4, 995,0), APU_MASK
, PPC440
, 0, {URT
, URA
, URB
}},
4994 {"vcmpgtsd.", VXR(4, 967,1), VXR_MASK
, PPCVEC2
, 0, {VD
, VA
, VB
}},
4995 {"udi15fcm", APU(4, 995,1), APU_MASK
, PPC440
, 0, {URT
, URA
, URB
}},
4996 {"vmodsd", VX (4,1995), VX_MASK
, POWER10
, 0, {VD
, VA
, VB
}},
4997 {"maclhwso", XO (4, 492,1,0), XO_MASK
, MULHW
, 0, {RT
, RA
, RB
}},
4998 {"maclhwso.", XO (4, 492,1,1), XO_MASK
, MULHW
, 0, {RT
, RA
, RB
}},
4999 {"nmaclhwso", XO (4, 494,1,0), XO_MASK
, MULHW
, 0, {RT
, RA
, RB
}},
5000 {"nmaclhwso.", XO (4, 494,1,1), XO_MASK
, MULHW
, 0, {RT
, RA
, RB
}},
5001 {"dcbz_l", X (4,1014), XRT_MASK
, PPCPS
, 0, {RA
, RB
}},
5003 {"lxvp", DQXP(6,0), DQXP_MASK
, POWER10
, PPCVLE
, {XTP
, DQ
, RA0
}},
5004 {"stxvp", DQXP(6,1), DQXP_MASK
, POWER10
, PPCVLE
, {XTP
, DQ
, RA0
}},
5006 {"mulli", OP(7), OP_MASK
, PPCCOM
, PPCVLE
, {RT
, RA
, SI
}},
5007 {"muli", OP(7), OP_MASK
, PWRCOM
, PPCVLE
, {RT
, RA
, SI
}},
5009 {"subfic", OP(8), OP_MASK
, PPCCOM
, PPCVLE
, {RT
, RA
, SI
}},
5010 {"sfi", OP(8), OP_MASK
, PWRCOM
, PPCVLE
, {RT
, RA
, SI
}},
5012 {"dozi", OP(9), OP_MASK
, M601
, PPCVLE
, {RT
, RA
, SI
}},
5014 {"cmplwi", OPL(10,0), OPL_MASK
, PPCCOM
, PPCVLE
, {OBF
, RA
, UISIGNOPT
}},
5015 {"cmpldi", OPL(10,1), OPL_MASK
, PPC64
, PPCVLE
, {OBF
, RA
, UISIGNOPT
}},
5016 {"cmpli", OP(10), OP_MASK
, PPC
, PPCVLE
, {BF
, L32OPT
, RA
, UISIGNOPT
}},
5017 {"cmpli", OP(10), OP_MASK
, PWRCOM
, PPC
|PPCVLE
, {BF
, RA
, UISIGNOPT
}},
5019 {"cmpwi", OPL(11,0), OPL_MASK
, PPCCOM
, PPCVLE
, {OBF
, RA
, SI
}},
5020 {"cmpdi", OPL(11,1), OPL_MASK
, PPC64
, PPCVLE
, {OBF
, RA
, SI
}},
5021 {"cmpi", OP(11), OP_MASK
, PPC
, PPCVLE
, {BF
, L32OPT
, RA
, SI
}},
5022 {"cmpi", OP(11), OP_MASK
, PWRCOM
, PPC
|PPCVLE
, {BF
, RA
, SI
}},
5024 {"addic", OP(12), OP_MASK
, PPCCOM
, PPCVLE
, {RT
, RA
, SI
}},
5025 {"ai", OP(12), OP_MASK
, PWRCOM
, PPCVLE
, {RT
, RA
, SI
}},
5026 {"subic", OP(12), OP_MASK
, PPCCOM
, PPCVLE
, {RT
, RA
, NSI
}},
5028 {"addic.", OP(13), OP_MASK
, PPCCOM
, PPCVLE
, {RT
, RA
, SI
}},
5029 {"ai.", OP(13), OP_MASK
, PWRCOM
, PPCVLE
, {RT
, RA
, SI
}},
5030 {"subic.", OP(13), OP_MASK
, PPCCOM
, PPCVLE
, {RT
, RA
, NSI
}},
5032 {"li", OP(14), DRA_MASK
, PPCCOM
, PPCVLE
, {RT
, SI
}},
5033 {"lil", OP(14), DRA_MASK
, PWRCOM
, PPCVLE
, {RT
, SI
}},
5034 {"addi", OP(14), OP_MASK
, PPCCOM
, PPCVLE
, {RT
, RA0
, SI
}},
5035 {"cal", OP(14), OP_MASK
, PWRCOM
, PPCVLE
, {RT
, D
, RA0
}},
5036 {"subi", OP(14), OP_MASK
, PPCCOM
, PPCVLE
, {RT
, RA0
, NSI
}},
5037 {"la", OP(14), OP_MASK
, PPCCOM
, PPCVLE
, {RT
, D
, RA0
}},
5039 {"lis", OP(15), DRA_MASK
, PPCCOM
, PPCVLE
, {RT
, SISIGNOPT
}},
5040 {"liu", OP(15), DRA_MASK
, PWRCOM
, PPCVLE
, {RT
, SISIGNOPT
}},
5041 {"addis", OP(15), OP_MASK
, PPCCOM
, PPCVLE
, {RT
, RA0
, SISIGNOPT
}},
5042 {"cau", OP(15), OP_MASK
, PWRCOM
, PPCVLE
, {RT
, RA0
, SISIGNOPT
}},
5043 {"subis", OP(15), OP_MASK
, PPCCOM
, PPCVLE
, {RT
, RA0
, NSISIGNOPT
}},
5045 {"bdnz-", BBO(16,BODNZ
,0,0), BBOATBI_MASK
, PPCCOM
, PPCVLE
, {BDM
}},
5046 {"bdnz+", BBO(16,BODNZ
,0,0), BBOATBI_MASK
, PPCCOM
, PPCVLE
, {BDP
}},
5047 {"bdnz", BBO(16,BODNZ
,0,0), BBOATBI_MASK
, PPCCOM
, PPCVLE
, {BD
}},
5048 {"bdn", BBO(16,BODNZ
,0,0), BBOATBI_MASK
, PWRCOM
, PPCVLE
, {BD
}},
5049 {"bdnzl-", BBO(16,BODNZ
,0,1), BBOATBI_MASK
, PPCCOM
, PPCVLE
, {BDM
}},
5050 {"bdnzl+", BBO(16,BODNZ
,0,1), BBOATBI_MASK
, PPCCOM
, PPCVLE
, {BDP
}},
5051 {"bdnzl", BBO(16,BODNZ
,0,1), BBOATBI_MASK
, PPCCOM
, PPCVLE
, {BD
}},
5052 {"bdnl", BBO(16,BODNZ
,0,1), BBOATBI_MASK
, PWRCOM
, PPCVLE
, {BD
}},
5053 {"bdnza-", BBO(16,BODNZ
,1,0), BBOATBI_MASK
, PPCCOM
, PPCVLE
, {BDMA
}},
5054 {"bdnza+", BBO(16,BODNZ
,1,0), BBOATBI_MASK
, PPCCOM
, PPCVLE
, {BDPA
}},
5055 {"bdnza", BBO(16,BODNZ
,1,0), BBOATBI_MASK
, PPCCOM
, PPCVLE
, {BDA
}},
5056 {"bdna", BBO(16,BODNZ
,1,0), BBOATBI_MASK
, PWRCOM
, PPCVLE
, {BDA
}},
5057 {"bdnzla-", BBO(16,BODNZ
,1,1), BBOATBI_MASK
, PPCCOM
, PPCVLE
, {BDMA
}},
5058 {"bdnzla+", BBO(16,BODNZ
,1,1), BBOATBI_MASK
, PPCCOM
, PPCVLE
, {BDPA
}},
5059 {"bdnzla", BBO(16,BODNZ
,1,1), BBOATBI_MASK
, PPCCOM
, PPCVLE
, {BDA
}},
5060 {"bdnla", BBO(16,BODNZ
,1,1), BBOATBI_MASK
, PWRCOM
, PPCVLE
, {BDA
}},
5061 {"bdz-", BBO(16,BODZ
,0,0), BBOATBI_MASK
, PPCCOM
, PPCVLE
, {BDM
}},
5062 {"bdz+", BBO(16,BODZ
,0,0), BBOATBI_MASK
, PPCCOM
, PPCVLE
, {BDP
}},
5063 {"bdz", BBO(16,BODZ
,0,0), BBOATBI_MASK
, COM
, PPCVLE
, {BD
}},
5064 {"bdzl-", BBO(16,BODZ
,0,1), BBOATBI_MASK
, PPCCOM
, PPCVLE
, {BDM
}},
5065 {"bdzl+", BBO(16,BODZ
,0,1), BBOATBI_MASK
, PPCCOM
, PPCVLE
, {BDP
}},
5066 {"bdzl", BBO(16,BODZ
,0,1), BBOATBI_MASK
, COM
, PPCVLE
, {BD
}},
5067 {"bdza-", BBO(16,BODZ
,1,0), BBOATBI_MASK
, PPCCOM
, PPCVLE
, {BDMA
}},
5068 {"bdza+", BBO(16,BODZ
,1,0), BBOATBI_MASK
, PPCCOM
, PPCVLE
, {BDPA
}},
5069 {"bdza", BBO(16,BODZ
,1,0), BBOATBI_MASK
, COM
, PPCVLE
, {BDA
}},
5070 {"bdzla-", BBO(16,BODZ
,1,1), BBOATBI_MASK
, PPCCOM
, PPCVLE
, {BDMA
}},
5071 {"bdzla+", BBO(16,BODZ
,1,1), BBOATBI_MASK
, PPCCOM
, PPCVLE
, {BDPA
}},
5072 {"bdzla", BBO(16,BODZ
,1,1), BBOATBI_MASK
, COM
, PPCVLE
, {BDA
}},
5074 {"bge-", BBOCB(16,BOF
,CBLT
,0,0), BBOATCB_MASK
, PPCCOM
, PPCVLE
, {CR
, BDM
}},
5075 {"bge+", BBOCB(16,BOF
,CBLT
,0,0), BBOATCB_MASK
, PPCCOM
, PPCVLE
, {CR
, BDP
}},
5076 {"bge", BBOCB(16,BOF
,CBLT
,0,0), BBOATCB_MASK
, COM
, PPCVLE
, {CR
, BD
}},
5077 {"bnl-", BBOCB(16,BOF
,CBLT
,0,0), BBOATCB_MASK
, PPCCOM
, PPCVLE
, {CR
, BDM
}},
5078 {"bnl+", BBOCB(16,BOF
,CBLT
,0,0), BBOATCB_MASK
, PPCCOM
, PPCVLE
, {CR
, BDP
}},
5079 {"bnl", BBOCB(16,BOF
,CBLT
,0,0), BBOATCB_MASK
, COM
, PPCVLE
, {CR
, BD
}},
5080 {"bgel-", BBOCB(16,BOF
,CBLT
,0,1), BBOATCB_MASK
, PPCCOM
, PPCVLE
, {CR
, BDM
}},
5081 {"bgel+", BBOCB(16,BOF
,CBLT
,0,1), BBOATCB_MASK
, PPCCOM
, PPCVLE
, {CR
, BDP
}},
5082 {"bgel", BBOCB(16,BOF
,CBLT
,0,1), BBOATCB_MASK
, COM
, PPCVLE
, {CR
, BD
}},
5083 {"bnll-", BBOCB(16,BOF
,CBLT
,0,1), BBOATCB_MASK
, PPCCOM
, PPCVLE
, {CR
, BDM
}},
5084 {"bnll+", BBOCB(16,BOF
,CBLT
,0,1), BBOATCB_MASK
, PPCCOM
, PPCVLE
, {CR
, BDP
}},
5085 {"bnll", BBOCB(16,BOF
,CBLT
,0,1), BBOATCB_MASK
, COM
, PPCVLE
, {CR
, BD
}},
5086 {"bgea-", BBOCB(16,BOF
,CBLT
,1,0), BBOATCB_MASK
, PPCCOM
, PPCVLE
, {CR
, BDMA
}},
5087 {"bgea+", BBOCB(16,BOF
,CBLT
,1,0), BBOATCB_MASK
, PPCCOM
, PPCVLE
, {CR
, BDPA
}},
5088 {"bgea", BBOCB(16,BOF
,CBLT
,1,0), BBOATCB_MASK
, COM
, PPCVLE
, {CR
, BDA
}},
5089 {"bnla-", BBOCB(16,BOF
,CBLT
,1,0), BBOATCB_MASK
, PPCCOM
, PPCVLE
, {CR
, BDMA
}},
5090 {"bnla+", BBOCB(16,BOF
,CBLT
,1,0), BBOATCB_MASK
, PPCCOM
, PPCVLE
, {CR
, BDPA
}},
5091 {"bnla", BBOCB(16,BOF
,CBLT
,1,0), BBOATCB_MASK
, COM
, PPCVLE
, {CR
, BDA
}},
5092 {"bgela-", BBOCB(16,BOF
,CBLT
,1,1), BBOATCB_MASK
, PPCCOM
, PPCVLE
, {CR
, BDMA
}},
5093 {"bgela+", BBOCB(16,BOF
,CBLT
,1,1), BBOATCB_MASK
, PPCCOM
, PPCVLE
, {CR
, BDPA
}},
5094 {"bgela", BBOCB(16,BOF
,CBLT
,1,1), BBOATCB_MASK
, COM
, PPCVLE
, {CR
, BDA
}},
5095 {"bnlla-", BBOCB(16,BOF
,CBLT
,1,1), BBOATCB_MASK
, PPCCOM
, PPCVLE
, {CR
, BDMA
}},
5096 {"bnlla+", BBOCB(16,BOF
,CBLT
,1,1), BBOATCB_MASK
, PPCCOM
, PPCVLE
, {CR
, BDPA
}},
5097 {"bnlla", BBOCB(16,BOF
,CBLT
,1,1), BBOATCB_MASK
, COM
, PPCVLE
, {CR
, BDA
}},
5098 {"ble-", BBOCB(16,BOF
,CBGT
,0,0), BBOATCB_MASK
, PPCCOM
, PPCVLE
, {CR
, BDM
}},
5099 {"ble+", BBOCB(16,BOF
,CBGT
,0,0), BBOATCB_MASK
, PPCCOM
, PPCVLE
, {CR
, BDP
}},
5100 {"ble", BBOCB(16,BOF
,CBGT
,0,0), BBOATCB_MASK
, COM
, PPCVLE
, {CR
, BD
}},
5101 {"bng-", BBOCB(16,BOF
,CBGT
,0,0), BBOATCB_MASK
, PPCCOM
, PPCVLE
, {CR
, BDM
}},
5102 {"bng+", BBOCB(16,BOF
,CBGT
,0,0), BBOATCB_MASK
, PPCCOM
, PPCVLE
, {CR
, BDP
}},
5103 {"bng", BBOCB(16,BOF
,CBGT
,0,0), BBOATCB_MASK
, COM
, PPCVLE
, {CR
, BD
}},
5104 {"blel-", BBOCB(16,BOF
,CBGT
,0,1), BBOATCB_MASK
, PPCCOM
, PPCVLE
, {CR
, BDM
}},
5105 {"blel+", BBOCB(16,BOF
,CBGT
,0,1), BBOATCB_MASK
, PPCCOM
, PPCVLE
, {CR
, BDP
}},
5106 {"blel", BBOCB(16,BOF
,CBGT
,0,1), BBOATCB_MASK
, COM
, PPCVLE
, {CR
, BD
}},
5107 {"bngl-", BBOCB(16,BOF
,CBGT
,0,1), BBOATCB_MASK
, PPCCOM
, PPCVLE
, {CR
, BDM
}},
5108 {"bngl+", BBOCB(16,BOF
,CBGT
,0,1), BBOATCB_MASK
, PPCCOM
, PPCVLE
, {CR
, BDP
}},
5109 {"bngl", BBOCB(16,BOF
,CBGT
,0,1), BBOATCB_MASK
, COM
, PPCVLE
, {CR
, BD
}},
5110 {"blea-", BBOCB(16,BOF
,CBGT
,1,0), BBOATCB_MASK
, PPCCOM
, PPCVLE
, {CR
, BDMA
}},
5111 {"blea+", BBOCB(16,BOF
,CBGT
,1,0), BBOATCB_MASK
, PPCCOM
, PPCVLE
, {CR
, BDPA
}},
5112 {"blea", BBOCB(16,BOF
,CBGT
,1,0), BBOATCB_MASK
, COM
, PPCVLE
, {CR
, BDA
}},
5113 {"bnga-", BBOCB(16,BOF
,CBGT
,1,0), BBOATCB_MASK
, PPCCOM
, PPCVLE
, {CR
, BDMA
}},
5114 {"bnga+", BBOCB(16,BOF
,CBGT
,1,0), BBOATCB_MASK
, PPCCOM
, PPCVLE
, {CR
, BDPA
}},
5115 {"bnga", BBOCB(16,BOF
,CBGT
,1,0), BBOATCB_MASK
, COM
, PPCVLE
, {CR
, BDA
}},
5116 {"blela-", BBOCB(16,BOF
,CBGT
,1,1), BBOATCB_MASK
, PPCCOM
, PPCVLE
, {CR
, BDMA
}},
5117 {"blela+", BBOCB(16,BOF
,CBGT
,1,1), BBOATCB_MASK
, PPCCOM
, PPCVLE
, {CR
, BDPA
}},
5118 {"blela", BBOCB(16,BOF
,CBGT
,1,1), BBOATCB_MASK
, COM
, PPCVLE
, {CR
, BDA
}},
5119 {"bngla-", BBOCB(16,BOF
,CBGT
,1,1), BBOATCB_MASK
, PPCCOM
, PPCVLE
, {CR
, BDMA
}},
5120 {"bngla+", BBOCB(16,BOF
,CBGT
,1,1), BBOATCB_MASK
, PPCCOM
, PPCVLE
, {CR
, BDPA
}},
5121 {"bngla", BBOCB(16,BOF
,CBGT
,1,1), BBOATCB_MASK
, COM
, PPCVLE
, {CR
, BDA
}},
5122 {"bne-", BBOCB(16,BOF
,CBEQ
,0,0), BBOATCB_MASK
, PPCCOM
, PPCVLE
, {CR
, BDM
}},
5123 {"bne+", BBOCB(16,BOF
,CBEQ
,0,0), BBOATCB_MASK
, PPCCOM
, PPCVLE
, {CR
, BDP
}},
5124 {"bne", BBOCB(16,BOF
,CBEQ
,0,0), BBOATCB_MASK
, COM
, PPCVLE
, {CR
, BD
}},
5125 {"bnel-", BBOCB(16,BOF
,CBEQ
,0,1), BBOATCB_MASK
, PPCCOM
, PPCVLE
, {CR
, BDM
}},
5126 {"bnel+", BBOCB(16,BOF
,CBEQ
,0,1), BBOATCB_MASK
, PPCCOM
, PPCVLE
, {CR
, BDP
}},
5127 {"bnel", BBOCB(16,BOF
,CBEQ
,0,1), BBOATCB_MASK
, COM
, PPCVLE
, {CR
, BD
}},
5128 {"bnea-", BBOCB(16,BOF
,CBEQ
,1,0), BBOATCB_MASK
, PPCCOM
, PPCVLE
, {CR
, BDMA
}},
5129 {"bnea+", BBOCB(16,BOF
,CBEQ
,1,0), BBOATCB_MASK
, PPCCOM
, PPCVLE
, {CR
, BDPA
}},
5130 {"bnea", BBOCB(16,BOF
,CBEQ
,1,0), BBOATCB_MASK
, COM
, PPCVLE
, {CR
, BDA
}},
5131 {"bnela-", BBOCB(16,BOF
,CBEQ
,1,1), BBOATCB_MASK
, PPCCOM
, PPCVLE
, {CR
, BDMA
}},
5132 {"bnela+", BBOCB(16,BOF
,CBEQ
,1,1), BBOATCB_MASK
, PPCCOM
, PPCVLE
, {CR
, BDPA
}},
5133 {"bnela", BBOCB(16,BOF
,CBEQ
,1,1), BBOATCB_MASK
, COM
, PPCVLE
, {CR
, BDA
}},
5134 {"bns-", BBOCB(16,BOF
,CBSO
,0,0), BBOATCB_MASK
, PPCCOM
, PPCVLE
, {CR
, BDM
}},
5135 {"bns+", BBOCB(16,BOF
,CBSO
,0,0), BBOATCB_MASK
, PPCCOM
, PPCVLE
, {CR
, BDP
}},
5136 {"bns", BBOCB(16,BOF
,CBSO
,0,0), BBOATCB_MASK
, COM
, PPCVLE
, {CR
, BD
}},
5137 {"bnu-", BBOCB(16,BOF
,CBSO
,0,0), BBOATCB_MASK
, PPCCOM
, PPCVLE
, {CR
, BDM
}},
5138 {"bnu+", BBOCB(16,BOF
,CBSO
,0,0), BBOATCB_MASK
, PPCCOM
, PPCVLE
, {CR
, BDP
}},
5139 {"bnu", BBOCB(16,BOF
,CBSO
,0,0), BBOATCB_MASK
, PPCCOM
, PPCVLE
, {CR
, BD
}},
5140 {"bnsl-", BBOCB(16,BOF
,CBSO
,0,1), BBOATCB_MASK
, PPCCOM
, PPCVLE
, {CR
, BDM
}},
5141 {"bnsl+", BBOCB(16,BOF
,CBSO
,0,1), BBOATCB_MASK
, PPCCOM
, PPCVLE
, {CR
, BDP
}},
5142 {"bnsl", BBOCB(16,BOF
,CBSO
,0,1), BBOATCB_MASK
, COM
, PPCVLE
, {CR
, BD
}},
5143 {"bnul-", BBOCB(16,BOF
,CBSO
,0,1), BBOATCB_MASK
, PPCCOM
, PPCVLE
, {CR
, BDM
}},
5144 {"bnul+", BBOCB(16,BOF
,CBSO
,0,1), BBOATCB_MASK
, PPCCOM
, PPCVLE
, {CR
, BDP
}},
5145 {"bnul", BBOCB(16,BOF
,CBSO
,0,1), BBOATCB_MASK
, PPCCOM
, PPCVLE
, {CR
, BD
}},
5146 {"bnsa-", BBOCB(16,BOF
,CBSO
,1,0), BBOATCB_MASK
, PPCCOM
, PPCVLE
, {CR
, BDMA
}},
5147 {"bnsa+", BBOCB(16,BOF
,CBSO
,1,0), BBOATCB_MASK
, PPCCOM
, PPCVLE
, {CR
, BDPA
}},
5148 {"bnsa", BBOCB(16,BOF
,CBSO
,1,0), BBOATCB_MASK
, COM
, PPCVLE
, {CR
, BDA
}},
5149 {"bnua-", BBOCB(16,BOF
,CBSO
,1,0), BBOATCB_MASK
, PPCCOM
, PPCVLE
, {CR
, BDMA
}},
5150 {"bnua+", BBOCB(16,BOF
,CBSO
,1,0), BBOATCB_MASK
, PPCCOM
, PPCVLE
, {CR
, BDPA
}},
5151 {"bnua", BBOCB(16,BOF
,CBSO
,1,0), BBOATCB_MASK
, PPCCOM
, PPCVLE
, {CR
, BDA
}},
5152 {"bnsla-", BBOCB(16,BOF
,CBSO
,1,1), BBOATCB_MASK
, PPCCOM
, PPCVLE
, {CR
, BDMA
}},
5153 {"bnsla+", BBOCB(16,BOF
,CBSO
,1,1), BBOATCB_MASK
, PPCCOM
, PPCVLE
, {CR
, BDPA
}},
5154 {"bnsla", BBOCB(16,BOF
,CBSO
,1,1), BBOATCB_MASK
, COM
, PPCVLE
, {CR
, BDA
}},
5155 {"bnula-", BBOCB(16,BOF
,CBSO
,1,1), BBOATCB_MASK
, PPCCOM
, PPCVLE
, {CR
, BDMA
}},
5156 {"bnula+", BBOCB(16,BOF
,CBSO
,1,1), BBOATCB_MASK
, PPCCOM
, PPCVLE
, {CR
, BDPA
}},
5157 {"bnula", BBOCB(16,BOF
,CBSO
,1,1), BBOATCB_MASK
, PPCCOM
, PPCVLE
, {CR
, BDA
}},
5159 {"blt-", BBOCB(16,BOT
,CBLT
,0,0), BBOATCB_MASK
, PPCCOM
, PPCVLE
, {CR
, BDM
}},
5160 {"blt+", BBOCB(16,BOT
,CBLT
,0,0), BBOATCB_MASK
, PPCCOM
, PPCVLE
, {CR
, BDP
}},
5161 {"blt", BBOCB(16,BOT
,CBLT
,0,0), BBOATCB_MASK
, COM
, PPCVLE
, {CR
, BD
}},
5162 {"bltl-", BBOCB(16,BOT
,CBLT
,0,1), BBOATCB_MASK
, PPCCOM
, PPCVLE
, {CR
, BDM
}},
5163 {"bltl+", BBOCB(16,BOT
,CBLT
,0,1), BBOATCB_MASK
, PPCCOM
, PPCVLE
, {CR
, BDP
}},
5164 {"bltl", BBOCB(16,BOT
,CBLT
,0,1), BBOATCB_MASK
, COM
, PPCVLE
, {CR
, BD
}},
5165 {"blta-", BBOCB(16,BOT
,CBLT
,1,0), BBOATCB_MASK
, PPCCOM
, PPCVLE
, {CR
, BDMA
}},
5166 {"blta+", BBOCB(16,BOT
,CBLT
,1,0), BBOATCB_MASK
, PPCCOM
, PPCVLE
, {CR
, BDPA
}},
5167 {"blta", BBOCB(16,BOT
,CBLT
,1,0), BBOATCB_MASK
, COM
, PPCVLE
, {CR
, BDA
}},
5168 {"bltla-", BBOCB(16,BOT
,CBLT
,1,1), BBOATCB_MASK
, PPCCOM
, PPCVLE
, {CR
, BDMA
}},
5169 {"bltla+", BBOCB(16,BOT
,CBLT
,1,1), BBOATCB_MASK
, PPCCOM
, PPCVLE
, {CR
, BDPA
}},
5170 {"bltla", BBOCB(16,BOT
,CBLT
,1,1), BBOATCB_MASK
, COM
, PPCVLE
, {CR
, BDA
}},
5171 {"bgt-", BBOCB(16,BOT
,CBGT
,0,0), BBOATCB_MASK
, PPCCOM
, PPCVLE
, {CR
, BDM
}},
5172 {"bgt+", BBOCB(16,BOT
,CBGT
,0,0), BBOATCB_MASK
, PPCCOM
, PPCVLE
, {CR
, BDP
}},
5173 {"bgt", BBOCB(16,BOT
,CBGT
,0,0), BBOATCB_MASK
, COM
, PPCVLE
, {CR
, BD
}},
5174 {"bgtl-", BBOCB(16,BOT
,CBGT
,0,1), BBOATCB_MASK
, PPCCOM
, PPCVLE
, {CR
, BDM
}},
5175 {"bgtl+", BBOCB(16,BOT
,CBGT
,0,1), BBOATCB_MASK
, PPCCOM
, PPCVLE
, {CR
, BDP
}},
5176 {"bgtl", BBOCB(16,BOT
,CBGT
,0,1), BBOATCB_MASK
, COM
, PPCVLE
, {CR
, BD
}},
5177 {"bgta-", BBOCB(16,BOT
,CBGT
,1,0), BBOATCB_MASK
, PPCCOM
, PPCVLE
, {CR
, BDMA
}},
5178 {"bgta+", BBOCB(16,BOT
,CBGT
,1,0), BBOATCB_MASK
, PPCCOM
, PPCVLE
, {CR
, BDPA
}},
5179 {"bgta", BBOCB(16,BOT
,CBGT
,1,0), BBOATCB_MASK
, COM
, PPCVLE
, {CR
, BDA
}},
5180 {"bgtla-", BBOCB(16,BOT
,CBGT
,1,1), BBOATCB_MASK
, PPCCOM
, PPCVLE
, {CR
, BDMA
}},
5181 {"bgtla+", BBOCB(16,BOT
,CBGT
,1,1), BBOATCB_MASK
, PPCCOM
, PPCVLE
, {CR
, BDPA
}},
5182 {"bgtla", BBOCB(16,BOT
,CBGT
,1,1), BBOATCB_MASK
, COM
, PPCVLE
, {CR
, BDA
}},
5183 {"beq-", BBOCB(16,BOT
,CBEQ
,0,0), BBOATCB_MASK
, PPCCOM
, PPCVLE
, {CR
, BDM
}},
5184 {"beq+", BBOCB(16,BOT
,CBEQ
,0,0), BBOATCB_MASK
, PPCCOM
, PPCVLE
, {CR
, BDP
}},
5185 {"beq", BBOCB(16,BOT
,CBEQ
,0,0), BBOATCB_MASK
, COM
, PPCVLE
, {CR
, BD
}},
5186 {"beql-", BBOCB(16,BOT
,CBEQ
,0,1), BBOATCB_MASK
, PPCCOM
, PPCVLE
, {CR
, BDM
}},
5187 {"beql+", BBOCB(16,BOT
,CBEQ
,0,1), BBOATCB_MASK
, PPCCOM
, PPCVLE
, {CR
, BDP
}},
5188 {"beql", BBOCB(16,BOT
,CBEQ
,0,1), BBOATCB_MASK
, COM
, PPCVLE
, {CR
, BD
}},
5189 {"beqa-", BBOCB(16,BOT
,CBEQ
,1,0), BBOATCB_MASK
, PPCCOM
, PPCVLE
, {CR
, BDMA
}},
5190 {"beqa+", BBOCB(16,BOT
,CBEQ
,1,0), BBOATCB_MASK
, PPCCOM
, PPCVLE
, {CR
, BDPA
}},
5191 {"beqa", BBOCB(16,BOT
,CBEQ
,1,0), BBOATCB_MASK
, COM
, PPCVLE
, {CR
, BDA
}},
5192 {"beqla-", BBOCB(16,BOT
,CBEQ
,1,1), BBOATCB_MASK
, PPCCOM
, PPCVLE
, {CR
, BDMA
}},
5193 {"beqla+", BBOCB(16,BOT
,CBEQ
,1,1), BBOATCB_MASK
, PPCCOM
, PPCVLE
, {CR
, BDPA
}},
5194 {"beqla", BBOCB(16,BOT
,CBEQ
,1,1), BBOATCB_MASK
, COM
, PPCVLE
, {CR
, BDA
}},
5195 {"bso-", BBOCB(16,BOT
,CBSO
,0,0), BBOATCB_MASK
, PPCCOM
, PPCVLE
, {CR
, BDM
}},
5196 {"bso+", BBOCB(16,BOT
,CBSO
,0,0), BBOATCB_MASK
, PPCCOM
, PPCVLE
, {CR
, BDP
}},
5197 {"bso", BBOCB(16,BOT
,CBSO
,0,0), BBOATCB_MASK
, COM
, PPCVLE
, {CR
, BD
}},
5198 {"bun-", BBOCB(16,BOT
,CBSO
,0,0), BBOATCB_MASK
, PPCCOM
, PPCVLE
, {CR
, BDM
}},
5199 {"bun+", BBOCB(16,BOT
,CBSO
,0,0), BBOATCB_MASK
, PPCCOM
, PPCVLE
, {CR
, BDP
}},
5200 {"bun", BBOCB(16,BOT
,CBSO
,0,0), BBOATCB_MASK
, PPCCOM
, PPCVLE
, {CR
, BD
}},
5201 {"bsol-", BBOCB(16,BOT
,CBSO
,0,1), BBOATCB_MASK
, PPCCOM
, PPCVLE
, {CR
, BDM
}},
5202 {"bsol+", BBOCB(16,BOT
,CBSO
,0,1), BBOATCB_MASK
, PPCCOM
, PPCVLE
, {CR
, BDP
}},
5203 {"bsol", BBOCB(16,BOT
,CBSO
,0,1), BBOATCB_MASK
, COM
, PPCVLE
, {CR
, BD
}},
5204 {"bunl-", BBOCB(16,BOT
,CBSO
,0,1), BBOATCB_MASK
, PPCCOM
, PPCVLE
, {CR
, BDM
}},
5205 {"bunl+", BBOCB(16,BOT
,CBSO
,0,1), BBOATCB_MASK
, PPCCOM
, PPCVLE
, {CR
, BDP
}},
5206 {"bunl", BBOCB(16,BOT
,CBSO
,0,1), BBOATCB_MASK
, PPCCOM
, PPCVLE
, {CR
, BD
}},
5207 {"bsoa-", BBOCB(16,BOT
,CBSO
,1,0), BBOATCB_MASK
, PPCCOM
, PPCVLE
, {CR
, BDMA
}},
5208 {"bsoa+", BBOCB(16,BOT
,CBSO
,1,0), BBOATCB_MASK
, PPCCOM
, PPCVLE
, {CR
, BDPA
}},
5209 {"bsoa", BBOCB(16,BOT
,CBSO
,1,0), BBOATCB_MASK
, COM
, PPCVLE
, {CR
, BDA
}},
5210 {"buna-", BBOCB(16,BOT
,CBSO
,1,0), BBOATCB_MASK
, PPCCOM
, PPCVLE
, {CR
, BDMA
}},
5211 {"buna+", BBOCB(16,BOT
,CBSO
,1,0), BBOATCB_MASK
, PPCCOM
, PPCVLE
, {CR
, BDPA
}},
5212 {"buna", BBOCB(16,BOT
,CBSO
,1,0), BBOATCB_MASK
, PPCCOM
, PPCVLE
, {CR
, BDA
}},
5213 {"bsola-", BBOCB(16,BOT
,CBSO
,1,1), BBOATCB_MASK
, PPCCOM
, PPCVLE
, {CR
, BDMA
}},
5214 {"bsola+", BBOCB(16,BOT
,CBSO
,1,1), BBOATCB_MASK
, PPCCOM
, PPCVLE
, {CR
, BDPA
}},
5215 {"bsola", BBOCB(16,BOT
,CBSO
,1,1), BBOATCB_MASK
, COM
, PPCVLE
, {CR
, BDA
}},
5216 {"bunla-", BBOCB(16,BOT
,CBSO
,1,1), BBOATCB_MASK
, PPCCOM
, PPCVLE
, {CR
, BDMA
}},
5217 {"bunla+", BBOCB(16,BOT
,CBSO
,1,1), BBOATCB_MASK
, PPCCOM
, PPCVLE
, {CR
, BDPA
}},
5218 {"bunla", BBOCB(16,BOT
,CBSO
,1,1), BBOATCB_MASK
, PPCCOM
, PPCVLE
, {CR
, BDA
}},
5220 {"bdnzf-", BBO(16,BODNZF
,0,0), BBOY_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {BI
, BDM
}},
5221 {"bdnzf+", BBO(16,BODNZF
,0,0), BBOY_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {BI
, BDP
}},
5222 {"bdnzf", BBO(16,BODNZF
,0,0), BBOY_MASK
, PPCCOM
, PPCVLE
, {BI
, BD
}},
5223 {"bdnzfl-", BBO(16,BODNZF
,0,1), BBOY_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {BI
, BDM
}},
5224 {"bdnzfl+", BBO(16,BODNZF
,0,1), BBOY_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {BI
, BDP
}},
5225 {"bdnzfl", BBO(16,BODNZF
,0,1), BBOY_MASK
, PPCCOM
, PPCVLE
, {BI
, BD
}},
5226 {"bdnzfa-", BBO(16,BODNZF
,1,0), BBOY_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {BI
, BDMA
}},
5227 {"bdnzfa+", BBO(16,BODNZF
,1,0), BBOY_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {BI
, BDPA
}},
5228 {"bdnzfa", BBO(16,BODNZF
,1,0), BBOY_MASK
, PPCCOM
, PPCVLE
, {BI
, BDA
}},
5229 {"bdnzfla-", BBO(16,BODNZF
,1,1), BBOY_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {BI
, BDMA
}},
5230 {"bdnzfla+", BBO(16,BODNZF
,1,1), BBOY_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {BI
, BDPA
}},
5231 {"bdnzfla", BBO(16,BODNZF
,1,1), BBOY_MASK
, PPCCOM
, PPCVLE
, {BI
, BDA
}},
5232 {"bdzf-", BBO(16,BODZF
,0,0), BBOY_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {BI
, BDM
}},
5233 {"bdzf+", BBO(16,BODZF
,0,0), BBOY_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {BI
, BDP
}},
5234 {"bdzf", BBO(16,BODZF
,0,0), BBOY_MASK
, PPCCOM
, PPCVLE
, {BI
, BD
}},
5235 {"bdzfl-", BBO(16,BODZF
,0,1), BBOY_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {BI
, BDM
}},
5236 {"bdzfl+", BBO(16,BODZF
,0,1), BBOY_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {BI
, BDP
}},
5237 {"bdzfl", BBO(16,BODZF
,0,1), BBOY_MASK
, PPCCOM
, PPCVLE
, {BI
, BD
}},
5238 {"bdzfa-", BBO(16,BODZF
,1,0), BBOY_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {BI
, BDMA
}},
5239 {"bdzfa+", BBO(16,BODZF
,1,0), BBOY_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {BI
, BDPA
}},
5240 {"bdzfa", BBO(16,BODZF
,1,0), BBOY_MASK
, PPCCOM
, PPCVLE
, {BI
, BDA
}},
5241 {"bdzfla-", BBO(16,BODZF
,1,1), BBOY_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {BI
, BDMA
}},
5242 {"bdzfla+", BBO(16,BODZF
,1,1), BBOY_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {BI
, BDPA
}},
5243 {"bdzfla", BBO(16,BODZF
,1,1), BBOY_MASK
, PPCCOM
, PPCVLE
, {BI
, BDA
}},
5245 {"bf-", BBO(16,BOF
,0,0), BBOAT_MASK
, PPCCOM
, PPCVLE
, {BI
, BDM
}},
5246 {"bf+", BBO(16,BOF
,0,0), BBOAT_MASK
, PPCCOM
, PPCVLE
, {BI
, BDP
}},
5247 {"bf", BBO(16,BOF
,0,0), BBOAT_MASK
, PPCCOM
, PPCVLE
, {BI
, BD
}},
5248 {"bbf", BBO(16,BOF
,0,0), BBOAT_MASK
, PWRCOM
, PPCVLE
, {BI
, BD
}},
5249 {"bfl-", BBO(16,BOF
,0,1), BBOAT_MASK
, PPCCOM
, PPCVLE
, {BI
, BDM
}},
5250 {"bfl+", BBO(16,BOF
,0,1), BBOAT_MASK
, PPCCOM
, PPCVLE
, {BI
, BDP
}},
5251 {"bfl", BBO(16,BOF
,0,1), BBOAT_MASK
, PPCCOM
, PPCVLE
, {BI
, BD
}},
5252 {"bbfl", BBO(16,BOF
,0,1), BBOAT_MASK
, PWRCOM
, PPCVLE
, {BI
, BD
}},
5253 {"bfa-", BBO(16,BOF
,1,0), BBOAT_MASK
, PPCCOM
, PPCVLE
, {BI
, BDMA
}},
5254 {"bfa+", BBO(16,BOF
,1,0), BBOAT_MASK
, PPCCOM
, PPCVLE
, {BI
, BDPA
}},
5255 {"bfa", BBO(16,BOF
,1,0), BBOAT_MASK
, PPCCOM
, PPCVLE
, {BI
, BDA
}},
5256 {"bbfa", BBO(16,BOF
,1,0), BBOAT_MASK
, PWRCOM
, PPCVLE
, {BI
, BDA
}},
5257 {"bfla-", BBO(16,BOF
,1,1), BBOAT_MASK
, PPCCOM
, PPCVLE
, {BI
, BDMA
}},
5258 {"bfla+", BBO(16,BOF
,1,1), BBOAT_MASK
, PPCCOM
, PPCVLE
, {BI
, BDPA
}},
5259 {"bfla", BBO(16,BOF
,1,1), BBOAT_MASK
, PPCCOM
, PPCVLE
, {BI
, BDA
}},
5260 {"bbfla", BBO(16,BOF
,1,1), BBOAT_MASK
, PWRCOM
, PPCVLE
, {BI
, BDA
}},
5262 {"bdnzt-", BBO(16,BODNZT
,0,0), BBOY_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {BI
, BDM
}},
5263 {"bdnzt+", BBO(16,BODNZT
,0,0), BBOY_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {BI
, BDP
}},
5264 {"bdnzt", BBO(16,BODNZT
,0,0), BBOY_MASK
, PPCCOM
, PPCVLE
, {BI
, BD
}},
5265 {"bdnztl-", BBO(16,BODNZT
,0,1), BBOY_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {BI
, BDM
}},
5266 {"bdnztl+", BBO(16,BODNZT
,0,1), BBOY_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {BI
, BDP
}},
5267 {"bdnztl", BBO(16,BODNZT
,0,1), BBOY_MASK
, PPCCOM
, PPCVLE
, {BI
, BD
}},
5268 {"bdnzta-", BBO(16,BODNZT
,1,0), BBOY_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {BI
, BDMA
}},
5269 {"bdnzta+", BBO(16,BODNZT
,1,0), BBOY_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {BI
, BDPA
}},
5270 {"bdnzta", BBO(16,BODNZT
,1,0), BBOY_MASK
, PPCCOM
, PPCVLE
, {BI
, BDA
}},
5271 {"bdnztla-", BBO(16,BODNZT
,1,1), BBOY_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {BI
, BDMA
}},
5272 {"bdnztla+", BBO(16,BODNZT
,1,1), BBOY_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {BI
, BDPA
}},
5273 {"bdnztla", BBO(16,BODNZT
,1,1), BBOY_MASK
, PPCCOM
, PPCVLE
, {BI
, BDA
}},
5274 {"bdzt-", BBO(16,BODZT
,0,0), BBOY_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {BI
, BDM
}},
5275 {"bdzt+", BBO(16,BODZT
,0,0), BBOY_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {BI
, BDP
}},
5276 {"bdzt", BBO(16,BODZT
,0,0), BBOY_MASK
, PPCCOM
, PPCVLE
, {BI
, BD
}},
5277 {"bdztl-", BBO(16,BODZT
,0,1), BBOY_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {BI
, BDM
}},
5278 {"bdztl+", BBO(16,BODZT
,0,1), BBOY_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {BI
, BDP
}},
5279 {"bdztl", BBO(16,BODZT
,0,1), BBOY_MASK
, PPCCOM
, PPCVLE
, {BI
, BD
}},
5280 {"bdzta-", BBO(16,BODZT
,1,0), BBOY_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {BI
, BDMA
}},
5281 {"bdzta+", BBO(16,BODZT
,1,0), BBOY_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {BI
, BDPA
}},
5282 {"bdzta", BBO(16,BODZT
,1,0), BBOY_MASK
, PPCCOM
, PPCVLE
, {BI
, BDA
}},
5283 {"bdztla-", BBO(16,BODZT
,1,1), BBOY_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {BI
, BDMA
}},
5284 {"bdztla+", BBO(16,BODZT
,1,1), BBOY_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {BI
, BDPA
}},
5285 {"bdztla", BBO(16,BODZT
,1,1), BBOY_MASK
, PPCCOM
, PPCVLE
, {BI
, BDA
}},
5287 {"bt-", BBO(16,BOT
,0,0), BBOAT_MASK
, PPCCOM
, PPCVLE
, {BI
, BDM
}},
5288 {"bt+", BBO(16,BOT
,0,0), BBOAT_MASK
, PPCCOM
, PPCVLE
, {BI
, BDP
}},
5289 {"bt", BBO(16,BOT
,0,0), BBOAT_MASK
, PPCCOM
, PPCVLE
, {BI
, BD
}},
5290 {"bbt", BBO(16,BOT
,0,0), BBOAT_MASK
, PWRCOM
, PPCVLE
, {BI
, BD
}},
5291 {"btl-", BBO(16,BOT
,0,1), BBOAT_MASK
, PPCCOM
, PPCVLE
, {BI
, BDM
}},
5292 {"btl+", BBO(16,BOT
,0,1), BBOAT_MASK
, PPCCOM
, PPCVLE
, {BI
, BDP
}},
5293 {"btl", BBO(16,BOT
,0,1), BBOAT_MASK
, PPCCOM
, PPCVLE
, {BI
, BD
}},
5294 {"bbtl", BBO(16,BOT
,0,1), BBOAT_MASK
, PWRCOM
, PPCVLE
, {BI
, BD
}},
5295 {"bta-", BBO(16,BOT
,1,0), BBOAT_MASK
, PPCCOM
, PPCVLE
, {BI
, BDMA
}},
5296 {"bta+", BBO(16,BOT
,1,0), BBOAT_MASK
, PPCCOM
, PPCVLE
, {BI
, BDPA
}},
5297 {"bta", BBO(16,BOT
,1,0), BBOAT_MASK
, PPCCOM
, PPCVLE
, {BI
, BDA
}},
5298 {"bbta", BBO(16,BOT
,1,0), BBOAT_MASK
, PWRCOM
, PPCVLE
, {BI
, BDA
}},
5299 {"btla-", BBO(16,BOT
,1,1), BBOAT_MASK
, PPCCOM
, PPCVLE
, {BI
, BDMA
}},
5300 {"btla+", BBO(16,BOT
,1,1), BBOAT_MASK
, PPCCOM
, PPCVLE
, {BI
, BDPA
}},
5301 {"btla", BBO(16,BOT
,1,1), BBOAT_MASK
, PPCCOM
, PPCVLE
, {BI
, BDA
}},
5302 {"bbtla", BBO(16,BOT
,1,1), BBOAT_MASK
, PWRCOM
, PPCVLE
, {BI
, BDA
}},
5304 {"bc-", B(16,0,0), B_MASK
, PPCCOM
, PPCVLE
, {BOM
, BI
, BDM
}},
5305 {"bc+", B(16,0,0), B_MASK
, PPCCOM
, PPCVLE
, {BOP
, BI
, BDP
}},
5306 {"bc", B(16,0,0), B_MASK
, COM
, PPCVLE
, {BO
, BI
, BD
}},
5307 {"bcl-", B(16,0,1), B_MASK
, PPCCOM
, PPCVLE
, {BOM
, BI
, BDM
}},
5308 {"bcl+", B(16,0,1), B_MASK
, PPCCOM
, PPCVLE
, {BOP
, BI
, BDP
}},
5309 {"bcl", B(16,0,1), B_MASK
, COM
, PPCVLE
, {BO
, BI
, BD
}},
5310 {"bca-", B(16,1,0), B_MASK
, PPCCOM
, PPCVLE
, {BOM
, BI
, BDMA
}},
5311 {"bca+", B(16,1,0), B_MASK
, PPCCOM
, PPCVLE
, {BOP
, BI
, BDPA
}},
5312 {"bca", B(16,1,0), B_MASK
, COM
, PPCVLE
, {BO
, BI
, BDA
}},
5313 {"bcla-", B(16,1,1), B_MASK
, PPCCOM
, PPCVLE
, {BOM
, BI
, BDMA
}},
5314 {"bcla+", B(16,1,1), B_MASK
, PPCCOM
, PPCVLE
, {BOP
, BI
, BDPA
}},
5315 {"bcla", B(16,1,1), B_MASK
, COM
, PPCVLE
, {BO
, BI
, BDA
}},
5317 {"svc", SC(17,0,0), SC_MASK
, POWER
, PPCVLE
, {SVC_LEV
, FL1
, FL2
}},
5318 {"scv", SC(17,0,1), SC_MASK
, POWER9
, PPCVLE
, {SVC_LEV
}},
5319 {"svcl", SC(17,0,1), SC_MASK
, POWER
, PPCVLE
, {SVC_LEV
, FL1
, FL2
}},
5320 {"sc", SC(17,1,0), SC_MASK
, PPC
, PPCVLE
, {LEV
}},
5321 {"svca", SC(17,1,0), SC_MASK
, PWRCOM
, PPCVLE
, {SV
}},
5322 {"svcla", SC(17,1,1), SC_MASK
, POWER
, PPCVLE
, {SV
}},
5324 {"b", B(18,0,0), B_MASK
, COM
, PPCVLE
, {LI
}},
5325 {"bl", B(18,0,1), B_MASK
, COM
, PPCVLE
, {LI
}},
5326 {"ba", B(18,1,0), B_MASK
, COM
, PPCVLE
, {LIA
}},
5327 {"bla", B(18,1,1), B_MASK
, COM
, PPCVLE
, {LIA
}},
5329 {"mcrf", XL(19,0), XLBB_MASK
|(3<<21)|(3<<16), COM
, PPCVLE
, {BF
, BFA
}},
5331 {"lnia", DX(19,2), NODX_MASK
, POWER9
, PPCVLE
, {RT
}},
5332 {"addpcis", DX(19,2), DX_MASK
, POWER9
, PPCVLE
, {RT
, DXD
}},
5333 {"subpcis", DX(19,2), DX_MASK
, POWER9
, PPCVLE
, {RT
, NDXD
}},
5335 {"bdnzlr-", XLO(19,BODNZ
,16,0), XLBOBIBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {0}},
5336 {"bdnzlr+", XLO(19,BODNZP
,16,0), XLBOBIBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {0}},
5337 {"bdnzlr", XLO(19,BODNZ
,16,0), XLBOBIBB_MASK
, PPCCOM
, PPCVLE
, {0}},
5338 {"bdnzlrl-", XLO(19,BODNZ
,16,1), XLBOBIBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {0}},
5339 {"bdnzlrl+", XLO(19,BODNZP
,16,1), XLBOBIBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {0}},
5340 {"bdnzlrl", XLO(19,BODNZ
,16,1), XLBOBIBB_MASK
, PPCCOM
, PPCVLE
, {0}},
5341 {"bdzlr-", XLO(19,BODZ
,16,0), XLBOBIBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {0}},
5342 {"bdzlr+", XLO(19,BODZP
,16,0), XLBOBIBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {0}},
5343 {"bdzlr", XLO(19,BODZ
,16,0), XLBOBIBB_MASK
, PPCCOM
, PPCVLE
, {0}},
5344 {"bdzlrl-", XLO(19,BODZ
,16,1), XLBOBIBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {0}},
5345 {"bdzlrl+", XLO(19,BODZP
,16,1), XLBOBIBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {0}},
5346 {"bdzlrl", XLO(19,BODZ
,16,1), XLBOBIBB_MASK
, PPCCOM
, PPCVLE
, {0}},
5347 {"blr", XLO(19,BOU
,16,0), XLBOBIBB_MASK
, PPCCOM
, PPCVLE
, {0}},
5348 {"br", XLO(19,BOU
,16,0), XLBOBIBB_MASK
, PWRCOM
, PPCVLE
, {0}},
5349 {"blrl", XLO(19,BOU
,16,1), XLBOBIBB_MASK
, PPCCOM
, PPCVLE
, {0}},
5350 {"brl", XLO(19,BOU
,16,1), XLBOBIBB_MASK
, PWRCOM
, PPCVLE
, {0}},
5351 {"bdnzlr-", XLO(19,BODNZM4
,16,0), XLBOBIBB_MASK
, ISA_V2
, PPCVLE
, {0}},
5352 {"bdnzlrl-", XLO(19,BODNZM4
,16,1), XLBOBIBB_MASK
, ISA_V2
, PPCVLE
, {0}},
5353 {"bdnzlr+", XLO(19,BODNZP4
,16,0), XLBOBIBB_MASK
, ISA_V2
, PPCVLE
, {0}},
5354 {"bdnzlrl+", XLO(19,BODNZP4
,16,1), XLBOBIBB_MASK
, ISA_V2
, PPCVLE
, {0}},
5355 {"bdzlr-", XLO(19,BODZM4
,16,0), XLBOBIBB_MASK
, ISA_V2
, PPCVLE
, {0}},
5356 {"bdzlrl-", XLO(19,BODZM4
,16,1), XLBOBIBB_MASK
, ISA_V2
, PPCVLE
, {0}},
5357 {"bdzlr+", XLO(19,BODZP4
,16,0), XLBOBIBB_MASK
, ISA_V2
, PPCVLE
, {0}},
5358 {"bdzlrl+", XLO(19,BODZP4
,16,1), XLBOBIBB_MASK
, ISA_V2
, PPCVLE
, {0}},
5360 {"bgelr-", XLOCB(19,BOF
,CBLT
,16,0), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {CR
}},
5361 {"bgelr+", XLOCB(19,BOFP
,CBLT
,16,0), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {CR
}},
5362 {"bgelr", XLOCB(19,BOF
,CBLT
,16,0), XLBOCBBB_MASK
, PPCCOM
, PPCVLE
, {CR
}},
5363 {"bger", XLOCB(19,BOF
,CBLT
,16,0), XLBOCBBB_MASK
, PWRCOM
, PPCVLE
, {CR
}},
5364 {"bnllr-", XLOCB(19,BOF
,CBLT
,16,0), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {CR
}},
5365 {"bnllr+", XLOCB(19,BOFP
,CBLT
,16,0), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {CR
}},
5366 {"bnllr", XLOCB(19,BOF
,CBLT
,16,0), XLBOCBBB_MASK
, PPCCOM
, PPCVLE
, {CR
}},
5367 {"bnlr", XLOCB(19,BOF
,CBLT
,16,0), XLBOCBBB_MASK
, PWRCOM
, PPCVLE
, {CR
}},
5368 {"bgelrl-", XLOCB(19,BOF
,CBLT
,16,1), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {CR
}},
5369 {"bgelrl+", XLOCB(19,BOFP
,CBLT
,16,1), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {CR
}},
5370 {"bgelrl", XLOCB(19,BOF
,CBLT
,16,1), XLBOCBBB_MASK
, PPCCOM
, PPCVLE
, {CR
}},
5371 {"bgerl", XLOCB(19,BOF
,CBLT
,16,1), XLBOCBBB_MASK
, PWRCOM
, PPCVLE
, {CR
}},
5372 {"bnllrl-", XLOCB(19,BOF
,CBLT
,16,1), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {CR
}},
5373 {"bnllrl+", XLOCB(19,BOFP
,CBLT
,16,1), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {CR
}},
5374 {"bnllrl", XLOCB(19,BOF
,CBLT
,16,1), XLBOCBBB_MASK
, PPCCOM
, PPCVLE
, {CR
}},
5375 {"bnlrl", XLOCB(19,BOF
,CBLT
,16,1), XLBOCBBB_MASK
, PWRCOM
, PPCVLE
, {CR
}},
5376 {"blelr-", XLOCB(19,BOF
,CBGT
,16,0), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {CR
}},
5377 {"blelr+", XLOCB(19,BOFP
,CBGT
,16,0), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {CR
}},
5378 {"blelr", XLOCB(19,BOF
,CBGT
,16,0), XLBOCBBB_MASK
, PPCCOM
, PPCVLE
, {CR
}},
5379 {"bler", XLOCB(19,BOF
,CBGT
,16,0), XLBOCBBB_MASK
, PWRCOM
, PPCVLE
, {CR
}},
5380 {"bnglr-", XLOCB(19,BOF
,CBGT
,16,0), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {CR
}},
5381 {"bnglr+", XLOCB(19,BOFP
,CBGT
,16,0), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {CR
}},
5382 {"bnglr", XLOCB(19,BOF
,CBGT
,16,0), XLBOCBBB_MASK
, PPCCOM
, PPCVLE
, {CR
}},
5383 {"bngr", XLOCB(19,BOF
,CBGT
,16,0), XLBOCBBB_MASK
, PWRCOM
, PPCVLE
, {CR
}},
5384 {"blelrl-", XLOCB(19,BOF
,CBGT
,16,1), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {CR
}},
5385 {"blelrl+", XLOCB(19,BOFP
,CBGT
,16,1), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {CR
}},
5386 {"blelrl", XLOCB(19,BOF
,CBGT
,16,1), XLBOCBBB_MASK
, PPCCOM
, PPCVLE
, {CR
}},
5387 {"blerl", XLOCB(19,BOF
,CBGT
,16,1), XLBOCBBB_MASK
, PWRCOM
, PPCVLE
, {CR
}},
5388 {"bnglrl-", XLOCB(19,BOF
,CBGT
,16,1), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {CR
}},
5389 {"bnglrl+", XLOCB(19,BOFP
,CBGT
,16,1), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {CR
}},
5390 {"bnglrl", XLOCB(19,BOF
,CBGT
,16,1), XLBOCBBB_MASK
, PPCCOM
, PPCVLE
, {CR
}},
5391 {"bngrl", XLOCB(19,BOF
,CBGT
,16,1), XLBOCBBB_MASK
, PWRCOM
, PPCVLE
, {CR
}},
5392 {"bnelr-", XLOCB(19,BOF
,CBEQ
,16,0), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {CR
}},
5393 {"bnelr+", XLOCB(19,BOFP
,CBEQ
,16,0), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {CR
}},
5394 {"bnelr", XLOCB(19,BOF
,CBEQ
,16,0), XLBOCBBB_MASK
, PPCCOM
, PPCVLE
, {CR
}},
5395 {"bner", XLOCB(19,BOF
,CBEQ
,16,0), XLBOCBBB_MASK
, PWRCOM
, PPCVLE
, {CR
}},
5396 {"bnelrl-", XLOCB(19,BOF
,CBEQ
,16,1), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {CR
}},
5397 {"bnelrl+", XLOCB(19,BOFP
,CBEQ
,16,1), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {CR
}},
5398 {"bnelrl", XLOCB(19,BOF
,CBEQ
,16,1), XLBOCBBB_MASK
, PPCCOM
, PPCVLE
, {CR
}},
5399 {"bnerl", XLOCB(19,BOF
,CBEQ
,16,1), XLBOCBBB_MASK
, PWRCOM
, PPCVLE
, {CR
}},
5400 {"bnslr-", XLOCB(19,BOF
,CBSO
,16,0), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {CR
}},
5401 {"bnslr+", XLOCB(19,BOFP
,CBSO
,16,0), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {CR
}},
5402 {"bnslr", XLOCB(19,BOF
,CBSO
,16,0), XLBOCBBB_MASK
, PPCCOM
, PPCVLE
, {CR
}},
5403 {"bnsr", XLOCB(19,BOF
,CBSO
,16,0), XLBOCBBB_MASK
, PWRCOM
, PPCVLE
, {CR
}},
5404 {"bnulr-", XLOCB(19,BOF
,CBSO
,16,0), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {CR
}},
5405 {"bnulr+", XLOCB(19,BOFP
,CBSO
,16,0), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {CR
}},
5406 {"bnulr", XLOCB(19,BOF
,CBSO
,16,0), XLBOCBBB_MASK
, PPCCOM
, PPCVLE
, {CR
}},
5407 {"bnslrl-", XLOCB(19,BOF
,CBSO
,16,1), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {CR
}},
5408 {"bnslrl+", XLOCB(19,BOFP
,CBSO
,16,1), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {CR
}},
5409 {"bnslrl", XLOCB(19,BOF
,CBSO
,16,1), XLBOCBBB_MASK
, PPCCOM
, PPCVLE
, {CR
}},
5410 {"bnsrl", XLOCB(19,BOF
,CBSO
,16,1), XLBOCBBB_MASK
, PWRCOM
, PPCVLE
, {CR
}},
5411 {"bnulrl-", XLOCB(19,BOF
,CBSO
,16,1), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {CR
}},
5412 {"bnulrl+", XLOCB(19,BOFP
,CBSO
,16,1), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {CR
}},
5413 {"bnulrl", XLOCB(19,BOF
,CBSO
,16,1), XLBOCBBB_MASK
, PPCCOM
, PPCVLE
, {CR
}},
5414 {"bgelr-", XLOCB(19,BOFM4
,CBLT
,16,0), XLBOCBBB_MASK
, ISA_V2
, PPCVLE
, {CR
}},
5415 {"bnllr-", XLOCB(19,BOFM4
,CBLT
,16,0), XLBOCBBB_MASK
, ISA_V2
, PPCVLE
, {CR
}},
5416 {"bgelrl-", XLOCB(19,BOFM4
,CBLT
,16,1), XLBOCBBB_MASK
, ISA_V2
, PPCVLE
, {CR
}},
5417 {"bnllrl-", XLOCB(19,BOFM4
,CBLT
,16,1), XLBOCBBB_MASK
, ISA_V2
, PPCVLE
, {CR
}},
5418 {"blelr-", XLOCB(19,BOFM4
,CBGT
,16,0), XLBOCBBB_MASK
, ISA_V2
, PPCVLE
, {CR
}},
5419 {"bnglr-", XLOCB(19,BOFM4
,CBGT
,16,0), XLBOCBBB_MASK
, ISA_V2
, PPCVLE
, {CR
}},
5420 {"blelrl-", XLOCB(19,BOFM4
,CBGT
,16,1), XLBOCBBB_MASK
, ISA_V2
, PPCVLE
, {CR
}},
5421 {"bnglrl-", XLOCB(19,BOFM4
,CBGT
,16,1), XLBOCBBB_MASK
, ISA_V2
, PPCVLE
, {CR
}},
5422 {"bnelr-", XLOCB(19,BOFM4
,CBEQ
,16,0), XLBOCBBB_MASK
, ISA_V2
, PPCVLE
, {CR
}},
5423 {"bnelrl-", XLOCB(19,BOFM4
,CBEQ
,16,1), XLBOCBBB_MASK
, ISA_V2
, PPCVLE
, {CR
}},
5424 {"bnslr-", XLOCB(19,BOFM4
,CBSO
,16,0), XLBOCBBB_MASK
, ISA_V2
, PPCVLE
, {CR
}},
5425 {"bnulr-", XLOCB(19,BOFM4
,CBSO
,16,0), XLBOCBBB_MASK
, ISA_V2
, PPCVLE
, {CR
}},
5426 {"bnslrl-", XLOCB(19,BOFM4
,CBSO
,16,1), XLBOCBBB_MASK
, ISA_V2
, PPCVLE
, {CR
}},
5427 {"bnulrl-", XLOCB(19,BOFM4
,CBSO
,16,1), XLBOCBBB_MASK
, ISA_V2
, PPCVLE
, {CR
}},
5428 {"bgelr+", XLOCB(19,BOFP4
,CBLT
,16,0), XLBOCBBB_MASK
, ISA_V2
, PPCVLE
, {CR
}},
5429 {"bnllr+", XLOCB(19,BOFP4
,CBLT
,16,0), XLBOCBBB_MASK
, ISA_V2
, PPCVLE
, {CR
}},
5430 {"bgelrl+", XLOCB(19,BOFP4
,CBLT
,16,1), XLBOCBBB_MASK
, ISA_V2
, PPCVLE
, {CR
}},
5431 {"bnllrl+", XLOCB(19,BOFP4
,CBLT
,16,1), XLBOCBBB_MASK
, ISA_V2
, PPCVLE
, {CR
}},
5432 {"blelr+", XLOCB(19,BOFP4
,CBGT
,16,0), XLBOCBBB_MASK
, ISA_V2
, PPCVLE
, {CR
}},
5433 {"bnglr+", XLOCB(19,BOFP4
,CBGT
,16,0), XLBOCBBB_MASK
, ISA_V2
, PPCVLE
, {CR
}},
5434 {"blelrl+", XLOCB(19,BOFP4
,CBGT
,16,1), XLBOCBBB_MASK
, ISA_V2
, PPCVLE
, {CR
}},
5435 {"bnglrl+", XLOCB(19,BOFP4
,CBGT
,16,1), XLBOCBBB_MASK
, ISA_V2
, PPCVLE
, {CR
}},
5436 {"bnelr+", XLOCB(19,BOFP4
,CBEQ
,16,0), XLBOCBBB_MASK
, ISA_V2
, PPCVLE
, {CR
}},
5437 {"bnelrl+", XLOCB(19,BOFP4
,CBEQ
,16,1), XLBOCBBB_MASK
, ISA_V2
, PPCVLE
, {CR
}},
5438 {"bnslr+", XLOCB(19,BOFP4
,CBSO
,16,0), XLBOCBBB_MASK
, ISA_V2
, PPCVLE
, {CR
}},
5439 {"bnulr+", XLOCB(19,BOFP4
,CBSO
,16,0), XLBOCBBB_MASK
, ISA_V2
, PPCVLE
, {CR
}},
5440 {"bnslrl+", XLOCB(19,BOFP4
,CBSO
,16,1), XLBOCBBB_MASK
, ISA_V2
, PPCVLE
, {CR
}},
5441 {"bnulrl+", XLOCB(19,BOFP4
,CBSO
,16,1), XLBOCBBB_MASK
, ISA_V2
, PPCVLE
, {CR
}},
5442 {"bltlr-", XLOCB(19,BOT
,CBLT
,16,0), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {CR
}},
5443 {"bltlr+", XLOCB(19,BOTP
,CBLT
,16,0), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {CR
}},
5444 {"bltlr", XLOCB(19,BOT
,CBLT
,16,0), XLBOCBBB_MASK
, PPCCOM
, PPCVLE
, {CR
}},
5445 {"bltr", XLOCB(19,BOT
,CBLT
,16,0), XLBOCBBB_MASK
, PWRCOM
, PPCVLE
, {CR
}},
5446 {"bltlrl-", XLOCB(19,BOT
,CBLT
,16,1), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {CR
}},
5447 {"bltlrl+", XLOCB(19,BOTP
,CBLT
,16,1), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {CR
}},
5448 {"bltlrl", XLOCB(19,BOT
,CBLT
,16,1), XLBOCBBB_MASK
, PPCCOM
, PPCVLE
, {CR
}},
5449 {"bltrl", XLOCB(19,BOT
,CBLT
,16,1), XLBOCBBB_MASK
, PWRCOM
, PPCVLE
, {CR
}},
5450 {"bgtlr-", XLOCB(19,BOT
,CBGT
,16,0), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {CR
}},
5451 {"bgtlr+", XLOCB(19,BOTP
,CBGT
,16,0), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {CR
}},
5452 {"bgtlr", XLOCB(19,BOT
,CBGT
,16,0), XLBOCBBB_MASK
, PPCCOM
, PPCVLE
, {CR
}},
5453 {"bgtr", XLOCB(19,BOT
,CBGT
,16,0), XLBOCBBB_MASK
, PWRCOM
, PPCVLE
, {CR
}},
5454 {"bgtlrl-", XLOCB(19,BOT
,CBGT
,16,1), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {CR
}},
5455 {"bgtlrl+", XLOCB(19,BOTP
,CBGT
,16,1), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {CR
}},
5456 {"bgtlrl", XLOCB(19,BOT
,CBGT
,16,1), XLBOCBBB_MASK
, PPCCOM
, PPCVLE
, {CR
}},
5457 {"bgtrl", XLOCB(19,BOT
,CBGT
,16,1), XLBOCBBB_MASK
, PWRCOM
, PPCVLE
, {CR
}},
5458 {"beqlr-", XLOCB(19,BOT
,CBEQ
,16,0), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {CR
}},
5459 {"beqlr+", XLOCB(19,BOTP
,CBEQ
,16,0), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {CR
}},
5460 {"beqlr", XLOCB(19,BOT
,CBEQ
,16,0), XLBOCBBB_MASK
, PPCCOM
, PPCVLE
, {CR
}},
5461 {"beqr", XLOCB(19,BOT
,CBEQ
,16,0), XLBOCBBB_MASK
, PWRCOM
, PPCVLE
, {CR
}},
5462 {"beqlrl-", XLOCB(19,BOT
,CBEQ
,16,1), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {CR
}},
5463 {"beqlrl+", XLOCB(19,BOTP
,CBEQ
,16,1), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {CR
}},
5464 {"beqlrl", XLOCB(19,BOT
,CBEQ
,16,1), XLBOCBBB_MASK
, PPCCOM
, PPCVLE
, {CR
}},
5465 {"beqrl", XLOCB(19,BOT
,CBEQ
,16,1), XLBOCBBB_MASK
, PWRCOM
, PPCVLE
, {CR
}},
5466 {"bsolr-", XLOCB(19,BOT
,CBSO
,16,0), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {CR
}},
5467 {"bsolr+", XLOCB(19,BOTP
,CBSO
,16,0), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {CR
}},
5468 {"bsolr", XLOCB(19,BOT
,CBSO
,16,0), XLBOCBBB_MASK
, PPCCOM
, PPCVLE
, {CR
}},
5469 {"bsor", XLOCB(19,BOT
,CBSO
,16,0), XLBOCBBB_MASK
, PWRCOM
, PPCVLE
, {CR
}},
5470 {"bunlr-", XLOCB(19,BOT
,CBSO
,16,0), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {CR
}},
5471 {"bunlr+", XLOCB(19,BOTP
,CBSO
,16,0), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {CR
}},
5472 {"bunlr", XLOCB(19,BOT
,CBSO
,16,0), XLBOCBBB_MASK
, PPCCOM
, PPCVLE
, {CR
}},
5473 {"bsolrl-", XLOCB(19,BOT
,CBSO
,16,1), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {CR
}},
5474 {"bsolrl+", XLOCB(19,BOTP
,CBSO
,16,1), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {CR
}},
5475 {"bsolrl", XLOCB(19,BOT
,CBSO
,16,1), XLBOCBBB_MASK
, PPCCOM
, PPCVLE
, {CR
}},
5476 {"bsorl", XLOCB(19,BOT
,CBSO
,16,1), XLBOCBBB_MASK
, PWRCOM
, PPCVLE
, {CR
}},
5477 {"bunlrl-", XLOCB(19,BOT
,CBSO
,16,1), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {CR
}},
5478 {"bunlrl+", XLOCB(19,BOTP
,CBSO
,16,1), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {CR
}},
5479 {"bunlrl", XLOCB(19,BOT
,CBSO
,16,1), XLBOCBBB_MASK
, PPCCOM
, PPCVLE
, {CR
}},
5480 {"bltlr-", XLOCB(19,BOTM4
,CBLT
,16,0), XLBOCBBB_MASK
, ISA_V2
, PPCVLE
, {CR
}},
5481 {"bltlrl-", XLOCB(19,BOTM4
,CBLT
,16,1), XLBOCBBB_MASK
, ISA_V2
, PPCVLE
, {CR
}},
5482 {"bgtlr-", XLOCB(19,BOTM4
,CBGT
,16,0), XLBOCBBB_MASK
, ISA_V2
, PPCVLE
, {CR
}},
5483 {"bgtlrl-", XLOCB(19,BOTM4
,CBGT
,16,1), XLBOCBBB_MASK
, ISA_V2
, PPCVLE
, {CR
}},
5484 {"beqlr-", XLOCB(19,BOTM4
,CBEQ
,16,0), XLBOCBBB_MASK
, ISA_V2
, PPCVLE
, {CR
}},
5485 {"beqlrl-", XLOCB(19,BOTM4
,CBEQ
,16,1), XLBOCBBB_MASK
, ISA_V2
, PPCVLE
, {CR
}},
5486 {"bsolr-", XLOCB(19,BOTM4
,CBSO
,16,0), XLBOCBBB_MASK
, ISA_V2
, PPCVLE
, {CR
}},
5487 {"bunlr-", XLOCB(19,BOTM4
,CBSO
,16,0), XLBOCBBB_MASK
, ISA_V2
, PPCVLE
, {CR
}},
5488 {"bsolrl-", XLOCB(19,BOTM4
,CBSO
,16,1), XLBOCBBB_MASK
, ISA_V2
, PPCVLE
, {CR
}},
5489 {"bunlrl-", XLOCB(19,BOTM4
,CBSO
,16,1), XLBOCBBB_MASK
, ISA_V2
, PPCVLE
, {CR
}},
5490 {"bltlr+", XLOCB(19,BOTP4
,CBLT
,16,0), XLBOCBBB_MASK
, ISA_V2
, PPCVLE
, {CR
}},
5491 {"bltlrl+", XLOCB(19,BOTP4
,CBLT
,16,1), XLBOCBBB_MASK
, ISA_V2
, PPCVLE
, {CR
}},
5492 {"bgtlr+", XLOCB(19,BOTP4
,CBGT
,16,0), XLBOCBBB_MASK
, ISA_V2
, PPCVLE
, {CR
}},
5493 {"bgtlrl+", XLOCB(19,BOTP4
,CBGT
,16,1), XLBOCBBB_MASK
, ISA_V2
, PPCVLE
, {CR
}},
5494 {"beqlr+", XLOCB(19,BOTP4
,CBEQ
,16,0), XLBOCBBB_MASK
, ISA_V2
, PPCVLE
, {CR
}},
5495 {"beqlrl+", XLOCB(19,BOTP4
,CBEQ
,16,1), XLBOCBBB_MASK
, ISA_V2
, PPCVLE
, {CR
}},
5496 {"bsolr+", XLOCB(19,BOTP4
,CBSO
,16,0), XLBOCBBB_MASK
, ISA_V2
, PPCVLE
, {CR
}},
5497 {"bunlr+", XLOCB(19,BOTP4
,CBSO
,16,0), XLBOCBBB_MASK
, ISA_V2
, PPCVLE
, {CR
}},
5498 {"bsolrl+", XLOCB(19,BOTP4
,CBSO
,16,1), XLBOCBBB_MASK
, ISA_V2
, PPCVLE
, {CR
}},
5499 {"bunlrl+", XLOCB(19,BOTP4
,CBSO
,16,1), XLBOCBBB_MASK
, ISA_V2
, PPCVLE
, {CR
}},
5501 {"bdnzflr-", XLO(19,BODNZF
,16,0), XLBOBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {BI
}},
5502 {"bdnzflr+", XLO(19,BODNZFP
,16,0), XLBOBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {BI
}},
5503 {"bdnzflr", XLO(19,BODNZF
,16,0), XLBOBB_MASK
, PPCCOM
, PPCVLE
, {BI
}},
5504 {"bdnzflrl-",XLO(19,BODNZF
,16,1), XLBOBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {BI
}},
5505 {"bdnzflrl+",XLO(19,BODNZFP
,16,1), XLBOBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {BI
}},
5506 {"bdnzflrl", XLO(19,BODNZF
,16,1), XLBOBB_MASK
, PPCCOM
, PPCVLE
, {BI
}},
5507 {"bdzflr-", XLO(19,BODZF
,16,0), XLBOBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {BI
}},
5508 {"bdzflr+", XLO(19,BODZFP
,16,0), XLBOBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {BI
}},
5509 {"bdzflr", XLO(19,BODZF
,16,0), XLBOBB_MASK
, PPCCOM
, PPCVLE
, {BI
}},
5510 {"bdzflrl-", XLO(19,BODZF
,16,1), XLBOBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {BI
}},
5511 {"bdzflrl+", XLO(19,BODZFP
,16,1), XLBOBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {BI
}},
5512 {"bdzflrl", XLO(19,BODZF
,16,1), XLBOBB_MASK
, PPCCOM
, PPCVLE
, {BI
}},
5513 {"bflr-", XLO(19,BOF
,16,0), XLBOBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {BI
}},
5514 {"bflr+", XLO(19,BOFP
,16,0), XLBOBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {BI
}},
5515 {"bflr", XLO(19,BOF
,16,0), XLBOBB_MASK
, PPCCOM
, PPCVLE
, {BI
}},
5516 {"bbfr", XLO(19,BOF
,16,0), XLBOBB_MASK
, PWRCOM
, PPCVLE
, {BI
}},
5517 {"bflrl-", XLO(19,BOF
,16,1), XLBOBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {BI
}},
5518 {"bflrl+", XLO(19,BOFP
,16,1), XLBOBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {BI
}},
5519 {"bflrl", XLO(19,BOF
,16,1), XLBOBB_MASK
, PPCCOM
, PPCVLE
, {BI
}},
5520 {"bbfrl", XLO(19,BOF
,16,1), XLBOBB_MASK
, PWRCOM
, PPCVLE
, {BI
}},
5521 {"bflr-", XLO(19,BOFM4
,16,0), XLBOBB_MASK
, ISA_V2
, PPCVLE
, {BI
}},
5522 {"bflrl-", XLO(19,BOFM4
,16,1), XLBOBB_MASK
, ISA_V2
, PPCVLE
, {BI
}},
5523 {"bflr+", XLO(19,BOFP4
,16,0), XLBOBB_MASK
, ISA_V2
, PPCVLE
, {BI
}},
5524 {"bflrl+", XLO(19,BOFP4
,16,1), XLBOBB_MASK
, ISA_V2
, PPCVLE
, {BI
}},
5525 {"bdnztlr-", XLO(19,BODNZT
,16,0), XLBOBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {BI
}},
5526 {"bdnztlr+", XLO(19,BODNZTP
,16,0), XLBOBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {BI
}},
5527 {"bdnztlr", XLO(19,BODNZT
,16,0), XLBOBB_MASK
, PPCCOM
, PPCVLE
, {BI
}},
5528 {"bdnztlrl-", XLO(19,BODNZT
,16,1), XLBOBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {BI
}},
5529 {"bdnztlrl+", XLO(19,BODNZTP
,16,1), XLBOBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {BI
}},
5530 {"bdnztlrl", XLO(19,BODNZT
,16,1), XLBOBB_MASK
, PPCCOM
, PPCVLE
, {BI
}},
5531 {"bdztlr-", XLO(19,BODZT
,16,0), XLBOBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {BI
}},
5532 {"bdztlr+", XLO(19,BODZTP
,16,0), XLBOBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {BI
}},
5533 {"bdztlr", XLO(19,BODZT
,16,0), XLBOBB_MASK
, PPCCOM
, PPCVLE
, {BI
}},
5534 {"bdztlrl-", XLO(19,BODZT
,16,1), XLBOBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {BI
}},
5535 {"bdztlrl+", XLO(19,BODZTP
,16,1), XLBOBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {BI
}},
5536 {"bdztlrl", XLO(19,BODZT
,16,1), XLBOBB_MASK
, PPCCOM
, PPCVLE
, {BI
}},
5537 {"btlr-", XLO(19,BOT
,16,0), XLBOBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {BI
}},
5538 {"btlr+", XLO(19,BOTP
,16,0), XLBOBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {BI
}},
5539 {"btlr", XLO(19,BOT
,16,0), XLBOBB_MASK
, PPCCOM
, PPCVLE
, {BI
}},
5540 {"bbtr", XLO(19,BOT
,16,0), XLBOBB_MASK
, PWRCOM
, PPCVLE
, {BI
}},
5541 {"btlrl-", XLO(19,BOT
,16,1), XLBOBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {BI
}},
5542 {"btlrl+", XLO(19,BOTP
,16,1), XLBOBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {BI
}},
5543 {"btlrl", XLO(19,BOT
,16,1), XLBOBB_MASK
, PPCCOM
, PPCVLE
, {BI
}},
5544 {"bbtrl", XLO(19,BOT
,16,1), XLBOBB_MASK
, PWRCOM
, PPCVLE
, {BI
}},
5545 {"btlr-", XLO(19,BOTM4
,16,0), XLBOBB_MASK
, ISA_V2
, PPCVLE
, {BI
}},
5546 {"btlrl-", XLO(19,BOTM4
,16,1), XLBOBB_MASK
, ISA_V2
, PPCVLE
, {BI
}},
5547 {"btlr+", XLO(19,BOTP4
,16,0), XLBOBB_MASK
, ISA_V2
, PPCVLE
, {BI
}},
5548 {"btlrl+", XLO(19,BOTP4
,16,1), XLBOBB_MASK
, ISA_V2
, PPCVLE
, {BI
}},
5550 {"bclr-", XLLK(19,16,0), XLBH_MASK
, PPCCOM
, PPCVLE
, {BOM
, BI
, BH
}},
5551 {"bclr+", XLLK(19,16,0), XLBH_MASK
, PPCCOM
, PPCVLE
, {BOP
, BI
, BH
}},
5552 {"bclr", XLLK(19,16,0), XLBH_MASK
, PPCCOM
, PPCVLE
, {BO
, BI
, BH
}},
5553 {"bcr", XLLK(19,16,0), XLBH_MASK
, PWRCOM
, PPCVLE
, {BO
, BI
, BH
}},
5554 {"bclrl-", XLLK(19,16,1), XLBH_MASK
, PPCCOM
, PPCVLE
, {BOM
, BI
, BH
}},
5555 {"bclrl+", XLLK(19,16,1), XLBH_MASK
, PPCCOM
, PPCVLE
, {BOP
, BI
, BH
}},
5556 {"bclrl", XLLK(19,16,1), XLBH_MASK
, PPCCOM
, PPCVLE
, {BO
, BI
, BH
}},
5557 {"bcrl", XLLK(19,16,1), XLBH_MASK
, PWRCOM
, PPCVLE
, {BO
, BI
, BH
}},
5559 {"rfid", XL(19,18), 0xffffffff, PPC64
, PPCVLE
, {0}},
5561 {"crnot", XL(19,33), XL_MASK
, PPCCOM
, PPCVLE
, {BT
, BAB
}},
5562 {"crnor", XL(19,33), XL_MASK
, COM
, PPCVLE
, {BT
, BA
, BB
}},
5563 {"rfmci", X(19,38), 0xffffffff, PPCRFMCI
|PPCA2
|PPC476
, PPCVLE
, {0}},
5565 {"rfdi", XL(19,39), 0xffffffff, E500MC
, PPCVLE
, {0}},
5566 {"rfi", XL(19,50), 0xffffffff, COM
, PPCVLE
, {0}},
5567 {"rfci", XL(19,51), 0xffffffff, PPC403
|BOOKE
|PPCE300
|PPCA2
|PPC476
, PPCVLE
, {0}},
5569 {"rfscv", XL(19,82), 0xffffffff, POWER9
, PPCVLE
, {0}},
5570 {"rfsvc", XL(19,82), 0xffffffff, POWER
, PPCVLE
, {0}},
5572 {"rfgi", XL(19,102), 0xffffffff, E500MC
|PPCA2
, PPCVLE
, {0}},
5574 {"crandc", XL(19,129), XL_MASK
, COM
, PPCVLE
, {BT
, BA
, BB
}},
5576 {"rfebb", XL(19,146), XLS_MASK
, POWER8
, PPCVLE
, {SXL
}},
5578 {"isync", XL(19,150), 0xffffffff, PPCCOM
, PPCVLE
, {0}},
5579 {"ics", XL(19,150), 0xffffffff, PWRCOM
, PPCVLE
, {0}},
5581 {"crclr", XL(19,193), XL_MASK
, PPCCOM
, PPCVLE
, {BTAB
}},
5582 {"crxor", XL(19,193), XL_MASK
, COM
, PPCVLE
, {BT
, BA
, BB
}},
5584 {"dnh", X(19,198), X_MASK
, E500MC
, PPCVLE
, {DUI
, DUIS
}},
5586 {"crnand", XL(19,225), XL_MASK
, COM
, PPCVLE
, {BT
, BA
, BB
}},
5588 {"crand", XL(19,257), XL_MASK
, COM
, PPCVLE
, {BT
, BA
, BB
}},
5590 {"hrfid", XL(19,274), 0xffffffff, POWER5
|CELL
, PPC476
|PPCVLE
, {0}},
5592 {"crset", XL(19,289), XL_MASK
, PPCCOM
, PPCVLE
, {BTAB
}},
5593 {"creqv", XL(19,289), XL_MASK
, COM
, PPCVLE
, {BT
, BA
, BB
}},
5595 {"urfid", XL(19,306), 0xffffffff, POWER9
, PPCVLE
, {0}},
5596 {"stop", XL(19,370), 0xffffffff, POWER9
, PPCVLE
, {0}},
5598 {"doze", XL(19,402), 0xffffffff, POWER6
, POWER9
|PPCVLE
, {0}},
5600 {"crorc", XL(19,417), XL_MASK
, COM
, PPCVLE
, {BT
, BA
, BB
}},
5602 {"nap", XL(19,434), 0xffffffff, POWER6
, POWER9
|PPCVLE
, {0}},
5604 {"crmove", XL(19,449), XL_MASK
, PPCCOM
, PPCVLE
, {BT
, BAB
}},
5605 {"cror", XL(19,449), XL_MASK
, COM
, PPCVLE
, {BT
, BA
, BB
}},
5607 {"sleep", XL(19,466), 0xffffffff, POWER6
, POWER9
|PPCVLE
, {0}},
5608 {"rvwinkle", XL(19,498), 0xffffffff, POWER6
, POWER9
|PPCVLE
, {0}},
5610 {"bctr", XLO(19,BOU
,528,0), XLBOBIBB_MASK
, COM
, PPCVLE
, {0}},
5611 {"bctrl", XLO(19,BOU
,528,1), XLBOBIBB_MASK
, COM
, PPCVLE
, {0}},
5613 {"bgectr-", XLOCB(19,BOF
,CBLT
,528,0), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {CR
}},
5614 {"bgectr+", XLOCB(19,BOFP
,CBLT
,528,0), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {CR
}},
5615 {"bgectr", XLOCB(19,BOF
,CBLT
,528,0), XLBOCBBB_MASK
, PPCCOM
, PPCVLE
, {CR
}},
5616 {"bnlctr-", XLOCB(19,BOF
,CBLT
,528,0), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {CR
}},
5617 {"bnlctr+", XLOCB(19,BOFP
,CBLT
,528,0), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {CR
}},
5618 {"bnlctr", XLOCB(19,BOF
,CBLT
,528,0), XLBOCBBB_MASK
, PPCCOM
, PPCVLE
, {CR
}},
5619 {"bgectrl-",XLOCB(19,BOF
,CBLT
,528,1), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {CR
}},
5620 {"bgectrl+",XLOCB(19,BOFP
,CBLT
,528,1), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {CR
}},
5621 {"bgectrl", XLOCB(19,BOF
,CBLT
,528,1), XLBOCBBB_MASK
, PPCCOM
, PPCVLE
, {CR
}},
5622 {"bnlctrl-",XLOCB(19,BOF
,CBLT
,528,1), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {CR
}},
5623 {"bnlctrl+",XLOCB(19,BOFP
,CBLT
,528,1), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {CR
}},
5624 {"bnlctrl", XLOCB(19,BOF
,CBLT
,528,1), XLBOCBBB_MASK
, PPCCOM
, PPCVLE
, {CR
}},
5625 {"blectr-", XLOCB(19,BOF
,CBGT
,528,0), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {CR
}},
5626 {"blectr+", XLOCB(19,BOFP
,CBGT
,528,0), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {CR
}},
5627 {"blectr", XLOCB(19,BOF
,CBGT
,528,0), XLBOCBBB_MASK
, PPCCOM
, PPCVLE
, {CR
}},
5628 {"bngctr-", XLOCB(19,BOF
,CBGT
,528,0), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {CR
}},
5629 {"bngctr+", XLOCB(19,BOFP
,CBGT
,528,0), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {CR
}},
5630 {"bngctr", XLOCB(19,BOF
,CBGT
,528,0), XLBOCBBB_MASK
, PPCCOM
, PPCVLE
, {CR
}},
5631 {"blectrl-",XLOCB(19,BOF
,CBGT
,528,1), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {CR
}},
5632 {"blectrl+",XLOCB(19,BOFP
,CBGT
,528,1), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {CR
}},
5633 {"blectrl", XLOCB(19,BOF
,CBGT
,528,1), XLBOCBBB_MASK
, PPCCOM
, PPCVLE
, {CR
}},
5634 {"bngctrl-",XLOCB(19,BOF
,CBGT
,528,1), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {CR
}},
5635 {"bngctrl+",XLOCB(19,BOFP
,CBGT
,528,1), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {CR
}},
5636 {"bngctrl", XLOCB(19,BOF
,CBGT
,528,1), XLBOCBBB_MASK
, PPCCOM
, PPCVLE
, {CR
}},
5637 {"bnectr-", XLOCB(19,BOF
,CBEQ
,528,0), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {CR
}},
5638 {"bnectr+", XLOCB(19,BOFP
,CBEQ
,528,0), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {CR
}},
5639 {"bnectr", XLOCB(19,BOF
,CBEQ
,528,0), XLBOCBBB_MASK
, PPCCOM
, PPCVLE
, {CR
}},
5640 {"bnectrl-",XLOCB(19,BOF
,CBEQ
,528,1), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {CR
}},
5641 {"bnectrl+",XLOCB(19,BOFP
,CBEQ
,528,1), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {CR
}},
5642 {"bnectrl", XLOCB(19,BOF
,CBEQ
,528,1), XLBOCBBB_MASK
, PPCCOM
, PPCVLE
, {CR
}},
5643 {"bnsctr-", XLOCB(19,BOF
,CBSO
,528,0), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {CR
}},
5644 {"bnsctr+", XLOCB(19,BOFP
,CBSO
,528,0), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {CR
}},
5645 {"bnsctr", XLOCB(19,BOF
,CBSO
,528,0), XLBOCBBB_MASK
, PPCCOM
, PPCVLE
, {CR
}},
5646 {"bnuctr-", XLOCB(19,BOF
,CBSO
,528,0), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {CR
}},
5647 {"bnuctr+", XLOCB(19,BOFP
,CBSO
,528,0), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {CR
}},
5648 {"bnuctr", XLOCB(19,BOF
,CBSO
,528,0), XLBOCBBB_MASK
, PPCCOM
, PPCVLE
, {CR
}},
5649 {"bnsctrl-",XLOCB(19,BOF
,CBSO
,528,1), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {CR
}},
5650 {"bnsctrl+",XLOCB(19,BOFP
,CBSO
,528,1), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {CR
}},
5651 {"bnsctrl", XLOCB(19,BOF
,CBSO
,528,1), XLBOCBBB_MASK
, PPCCOM
, PPCVLE
, {CR
}},
5652 {"bnuctrl-",XLOCB(19,BOF
,CBSO
,528,1), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {CR
}},
5653 {"bnuctrl+",XLOCB(19,BOFP
,CBSO
,528,1), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {CR
}},
5654 {"bnuctrl", XLOCB(19,BOF
,CBSO
,528,1), XLBOCBBB_MASK
, PPCCOM
, PPCVLE
, {CR
}},
5655 {"bgectr-", XLOCB(19,BOFM4
,CBLT
,528,0), XLBOCBBB_MASK
, ISA_V2
, PPCVLE
, {CR
}},
5656 {"bnlctr-", XLOCB(19,BOFM4
,CBLT
,528,0), XLBOCBBB_MASK
, ISA_V2
, PPCVLE
, {CR
}},
5657 {"bgectrl-",XLOCB(19,BOFM4
,CBLT
,528,1), XLBOCBBB_MASK
, ISA_V2
, PPCVLE
, {CR
}},
5658 {"bnlctrl-",XLOCB(19,BOFM4
,CBLT
,528,1), XLBOCBBB_MASK
, ISA_V2
, PPCVLE
, {CR
}},
5659 {"blectr-", XLOCB(19,BOFM4
,CBGT
,528,0), XLBOCBBB_MASK
, ISA_V2
, PPCVLE
, {CR
}},
5660 {"bngctr-", XLOCB(19,BOFM4
,CBGT
,528,0), XLBOCBBB_MASK
, ISA_V2
, PPCVLE
, {CR
}},
5661 {"blectrl-",XLOCB(19,BOFM4
,CBGT
,528,1), XLBOCBBB_MASK
, ISA_V2
, PPCVLE
, {CR
}},
5662 {"bngctrl-",XLOCB(19,BOFM4
,CBGT
,528,1), XLBOCBBB_MASK
, ISA_V2
, PPCVLE
, {CR
}},
5663 {"bnectr-", XLOCB(19,BOFM4
,CBEQ
,528,0), XLBOCBBB_MASK
, ISA_V2
, PPCVLE
, {CR
}},
5664 {"bnectrl-",XLOCB(19,BOFM4
,CBEQ
,528,1), XLBOCBBB_MASK
, ISA_V2
, PPCVLE
, {CR
}},
5665 {"bnsctr-", XLOCB(19,BOFM4
,CBSO
,528,0), XLBOCBBB_MASK
, ISA_V2
, PPCVLE
, {CR
}},
5666 {"bnuctr-", XLOCB(19,BOFM4
,CBSO
,528,0), XLBOCBBB_MASK
, ISA_V2
, PPCVLE
, {CR
}},
5667 {"bnsctrl-",XLOCB(19,BOFM4
,CBSO
,528,1), XLBOCBBB_MASK
, ISA_V2
, PPCVLE
, {CR
}},
5668 {"bnuctrl-",XLOCB(19,BOFM4
,CBSO
,528,1), XLBOCBBB_MASK
, ISA_V2
, PPCVLE
, {CR
}},
5669 {"bgectr+", XLOCB(19,BOFP4
,CBLT
,528,0), XLBOCBBB_MASK
, ISA_V2
, PPCVLE
, {CR
}},
5670 {"bnlctr+", XLOCB(19,BOFP4
,CBLT
,528,0), XLBOCBBB_MASK
, ISA_V2
, PPCVLE
, {CR
}},
5671 {"bgectrl+",XLOCB(19,BOFP4
,CBLT
,528,1), XLBOCBBB_MASK
, ISA_V2
, PPCVLE
, {CR
}},
5672 {"bnlctrl+",XLOCB(19,BOFP4
,CBLT
,528,1), XLBOCBBB_MASK
, ISA_V2
, PPCVLE
, {CR
}},
5673 {"blectr+", XLOCB(19,BOFP4
,CBGT
,528,0), XLBOCBBB_MASK
, ISA_V2
, PPCVLE
, {CR
}},
5674 {"bngctr+", XLOCB(19,BOFP4
,CBGT
,528,0), XLBOCBBB_MASK
, ISA_V2
, PPCVLE
, {CR
}},
5675 {"blectrl+",XLOCB(19,BOFP4
,CBGT
,528,1), XLBOCBBB_MASK
, ISA_V2
, PPCVLE
, {CR
}},
5676 {"bngctrl+",XLOCB(19,BOFP4
,CBGT
,528,1), XLBOCBBB_MASK
, ISA_V2
, PPCVLE
, {CR
}},
5677 {"bnectr+", XLOCB(19,BOFP4
,CBEQ
,528,0), XLBOCBBB_MASK
, ISA_V2
, PPCVLE
, {CR
}},
5678 {"bnectrl+",XLOCB(19,BOFP4
,CBEQ
,528,1), XLBOCBBB_MASK
, ISA_V2
, PPCVLE
, {CR
}},
5679 {"bnsctr+", XLOCB(19,BOFP4
,CBSO
,528,0), XLBOCBBB_MASK
, ISA_V2
, PPCVLE
, {CR
}},
5680 {"bnuctr+", XLOCB(19,BOFP4
,CBSO
,528,0), XLBOCBBB_MASK
, ISA_V2
, PPCVLE
, {CR
}},
5681 {"bnsctrl+",XLOCB(19,BOFP4
,CBSO
,528,1), XLBOCBBB_MASK
, ISA_V2
, PPCVLE
, {CR
}},
5682 {"bnuctrl+",XLOCB(19,BOFP4
,CBSO
,528,1), XLBOCBBB_MASK
, ISA_V2
, PPCVLE
, {CR
}},
5683 {"bltctr-", XLOCB(19,BOT
,CBLT
,528,0), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {CR
}},
5684 {"bltctr+", XLOCB(19,BOTP
,CBLT
,528,0), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {CR
}},
5685 {"bltctr", XLOCB(19,BOT
,CBLT
,528,0), XLBOCBBB_MASK
, PPCCOM
, PPCVLE
, {CR
}},
5686 {"bltctrl-",XLOCB(19,BOT
,CBLT
,528,1), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {CR
}},
5687 {"bltctrl+",XLOCB(19,BOTP
,CBLT
,528,1), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {CR
}},
5688 {"bltctrl", XLOCB(19,BOT
,CBLT
,528,1), XLBOCBBB_MASK
, PPCCOM
, PPCVLE
, {CR
}},
5689 {"bgtctr-", XLOCB(19,BOT
,CBGT
,528,0), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {CR
}},
5690 {"bgtctr+", XLOCB(19,BOTP
,CBGT
,528,0), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {CR
}},
5691 {"bgtctr", XLOCB(19,BOT
,CBGT
,528,0), XLBOCBBB_MASK
, PPCCOM
, PPCVLE
, {CR
}},
5692 {"bgtctrl-",XLOCB(19,BOT
,CBGT
,528,1), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {CR
}},
5693 {"bgtctrl+",XLOCB(19,BOTP
,CBGT
,528,1), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {CR
}},
5694 {"bgtctrl", XLOCB(19,BOT
,CBGT
,528,1), XLBOCBBB_MASK
, PPCCOM
, PPCVLE
, {CR
}},
5695 {"beqctr-", XLOCB(19,BOT
,CBEQ
,528,0), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {CR
}},
5696 {"beqctr+", XLOCB(19,BOTP
,CBEQ
,528,0), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {CR
}},
5697 {"beqctr", XLOCB(19,BOT
,CBEQ
,528,0), XLBOCBBB_MASK
, PPCCOM
, PPCVLE
, {CR
}},
5698 {"beqctrl-",XLOCB(19,BOT
,CBEQ
,528,1), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {CR
}},
5699 {"beqctrl+",XLOCB(19,BOTP
,CBEQ
,528,1), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {CR
}},
5700 {"beqctrl", XLOCB(19,BOT
,CBEQ
,528,1), XLBOCBBB_MASK
, PPCCOM
, PPCVLE
, {CR
}},
5701 {"bsoctr-", XLOCB(19,BOT
,CBSO
,528,0), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {CR
}},
5702 {"bsoctr+", XLOCB(19,BOTP
,CBSO
,528,0), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {CR
}},
5703 {"bsoctr", XLOCB(19,BOT
,CBSO
,528,0), XLBOCBBB_MASK
, PPCCOM
, PPCVLE
, {CR
}},
5704 {"bunctr-", XLOCB(19,BOT
,CBSO
,528,0), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {CR
}},
5705 {"bunctr+", XLOCB(19,BOTP
,CBSO
,528,0), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {CR
}},
5706 {"bunctr", XLOCB(19,BOT
,CBSO
,528,0), XLBOCBBB_MASK
, PPCCOM
, PPCVLE
, {CR
}},
5707 {"bsoctrl-",XLOCB(19,BOT
,CBSO
,528,1), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {CR
}},
5708 {"bsoctrl+",XLOCB(19,BOTP
,CBSO
,528,1), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {CR
}},
5709 {"bsoctrl", XLOCB(19,BOT
,CBSO
,528,1), XLBOCBBB_MASK
, PPCCOM
, PPCVLE
, {CR
}},
5710 {"bunctrl-",XLOCB(19,BOT
,CBSO
,528,1), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {CR
}},
5711 {"bunctrl+",XLOCB(19,BOTP
,CBSO
,528,1), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {CR
}},
5712 {"bunctrl", XLOCB(19,BOT
,CBSO
,528,1), XLBOCBBB_MASK
, PPCCOM
, PPCVLE
, {CR
}},
5713 {"bltctr-", XLOCB(19,BOTM4
,CBLT
,528,0), XLBOCBBB_MASK
, ISA_V2
, PPCVLE
, {CR
}},
5714 {"bltctrl-",XLOCB(19,BOTM4
,CBLT
,528,1), XLBOCBBB_MASK
, ISA_V2
, PPCVLE
, {CR
}},
5715 {"bgtctr-", XLOCB(19,BOTM4
,CBGT
,528,0), XLBOCBBB_MASK
, ISA_V2
, PPCVLE
, {CR
}},
5716 {"bgtctrl-",XLOCB(19,BOTM4
,CBGT
,528,1), XLBOCBBB_MASK
, ISA_V2
, PPCVLE
, {CR
}},
5717 {"beqctr-", XLOCB(19,BOTM4
,CBEQ
,528,0), XLBOCBBB_MASK
, ISA_V2
, PPCVLE
, {CR
}},
5718 {"beqctrl-",XLOCB(19,BOTM4
,CBEQ
,528,1), XLBOCBBB_MASK
, ISA_V2
, PPCVLE
, {CR
}},
5719 {"bsoctr-", XLOCB(19,BOTM4
,CBSO
,528,0), XLBOCBBB_MASK
, ISA_V2
, PPCVLE
, {CR
}},
5720 {"bunctr-", XLOCB(19,BOTM4
,CBSO
,528,0), XLBOCBBB_MASK
, ISA_V2
, PPCVLE
, {CR
}},
5721 {"bsoctrl-",XLOCB(19,BOTM4
,CBSO
,528,1), XLBOCBBB_MASK
, ISA_V2
, PPCVLE
, {CR
}},
5722 {"bunctrl-",XLOCB(19,BOTM4
,CBSO
,528,1), XLBOCBBB_MASK
, ISA_V2
, PPCVLE
, {CR
}},
5723 {"bltctr+", XLOCB(19,BOTP4
,CBLT
,528,0), XLBOCBBB_MASK
, ISA_V2
, PPCVLE
, {CR
}},
5724 {"bltctrl+",XLOCB(19,BOTP4
,CBLT
,528,1), XLBOCBBB_MASK
, ISA_V2
, PPCVLE
, {CR
}},
5725 {"bgtctr+", XLOCB(19,BOTP4
,CBGT
,528,0), XLBOCBBB_MASK
, ISA_V2
, PPCVLE
, {CR
}},
5726 {"bgtctrl+",XLOCB(19,BOTP4
,CBGT
,528,1), XLBOCBBB_MASK
, ISA_V2
, PPCVLE
, {CR
}},
5727 {"beqctr+", XLOCB(19,BOTP4
,CBEQ
,528,0), XLBOCBBB_MASK
, ISA_V2
, PPCVLE
, {CR
}},
5728 {"beqctrl+",XLOCB(19,BOTP4
,CBEQ
,528,1), XLBOCBBB_MASK
, ISA_V2
, PPCVLE
, {CR
}},
5729 {"bsoctr+", XLOCB(19,BOTP4
,CBSO
,528,0), XLBOCBBB_MASK
, ISA_V2
, PPCVLE
, {CR
}},
5730 {"bunctr+", XLOCB(19,BOTP4
,CBSO
,528,0), XLBOCBBB_MASK
, ISA_V2
, PPCVLE
, {CR
}},
5731 {"bsoctrl+",XLOCB(19,BOTP4
,CBSO
,528,1), XLBOCBBB_MASK
, ISA_V2
, PPCVLE
, {CR
}},
5732 {"bunctrl+",XLOCB(19,BOTP4
,CBSO
,528,1), XLBOCBBB_MASK
, ISA_V2
, PPCVLE
, {CR
}},
5734 {"bfctr-", XLO(19,BOF
,528,0), XLBOBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {BI
}},
5735 {"bfctr+", XLO(19,BOFP
,528,0), XLBOBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {BI
}},
5736 {"bfctr", XLO(19,BOF
,528,0), XLBOBB_MASK
, PPCCOM
, PPCVLE
, {BI
}},
5737 {"bfctrl-", XLO(19,BOF
,528,1), XLBOBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {BI
}},
5738 {"bfctrl+", XLO(19,BOFP
,528,1), XLBOBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {BI
}},
5739 {"bfctrl", XLO(19,BOF
,528,1), XLBOBB_MASK
, PPCCOM
, PPCVLE
, {BI
}},
5740 {"bfctr-", XLO(19,BOFM4
,528,0), XLBOBB_MASK
, ISA_V2
, PPCVLE
, {BI
}},
5741 {"bfctrl-", XLO(19,BOFM4
,528,1), XLBOBB_MASK
, ISA_V2
, PPCVLE
, {BI
}},
5742 {"bfctr+", XLO(19,BOFP4
,528,0), XLBOBB_MASK
, ISA_V2
, PPCVLE
, {BI
}},
5743 {"bfctrl+", XLO(19,BOFP4
,528,1), XLBOBB_MASK
, ISA_V2
, PPCVLE
, {BI
}},
5744 {"btctr-", XLO(19,BOT
,528,0), XLBOBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {BI
}},
5745 {"btctr+", XLO(19,BOTP
,528,0), XLBOBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {BI
}},
5746 {"btctr", XLO(19,BOT
,528,0), XLBOBB_MASK
, PPCCOM
, PPCVLE
, {BI
}},
5747 {"btctrl-", XLO(19,BOT
,528,1), XLBOBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {BI
}},
5748 {"btctrl+", XLO(19,BOTP
,528,1), XLBOBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {BI
}},
5749 {"btctrl", XLO(19,BOT
,528,1), XLBOBB_MASK
, PPCCOM
, PPCVLE
, {BI
}},
5750 {"btctr-", XLO(19,BOTM4
,528,0), XLBOBB_MASK
, ISA_V2
, PPCVLE
, {BI
}},
5751 {"btctrl-", XLO(19,BOTM4
,528,1), XLBOBB_MASK
, ISA_V2
, PPCVLE
, {BI
}},
5752 {"btctr+", XLO(19,BOTP4
,528,0), XLBOBB_MASK
, ISA_V2
, PPCVLE
, {BI
}},
5753 {"btctrl+", XLO(19,BOTP4
,528,1), XLBOBB_MASK
, ISA_V2
, PPCVLE
, {BI
}},
5755 {"bcctr-", XLLK(19,528,0), XLBH_MASK
, PPCCOM
, PPCVLE
, {BOM
, BI
, BH
}},
5756 {"bcctr+", XLLK(19,528,0), XLBH_MASK
, PPCCOM
, PPCVLE
, {BOP
, BI
, BH
}},
5757 {"bcctr", XLLK(19,528,0), XLBH_MASK
, PPCCOM
, PPCVLE
, {BO
, BI
, BH
}},
5758 {"bcc", XLLK(19,528,0), XLBH_MASK
, PWRCOM
, PPCVLE
, {BO
, BI
, BH
}},
5759 {"bcctrl-", XLLK(19,528,1), XLBH_MASK
, PPCCOM
, PPCVLE
, {BOM
, BI
, BH
}},
5760 {"bcctrl+", XLLK(19,528,1), XLBH_MASK
, PPCCOM
, PPCVLE
, {BOP
, BI
, BH
}},
5761 {"bcctrl", XLLK(19,528,1), XLBH_MASK
, PPCCOM
, PPCVLE
, {BO
, BI
, BH
}},
5762 {"bccl", XLLK(19,528,1), XLBH_MASK
, PWRCOM
, PPCVLE
, {BO
, BI
, BH
}},
5764 {"bdnztar", XLO(19,BODNZ
,560,0), XLBOBIBB_MASK
, POWER8
, PPCVLE
, {0}},
5765 {"bdnztarl", XLO(19,BODNZ
,560,1), XLBOBIBB_MASK
, POWER8
, PPCVLE
, {0}},
5766 {"bdztar", XLO(19,BODZ
,560,0), XLBOBIBB_MASK
, POWER8
, PPCVLE
, {0}},
5767 {"bdztarl", XLO(19,BODZ
,560,1), XLBOBIBB_MASK
, POWER8
, PPCVLE
, {0}},
5768 {"btar", XLO(19,BOU
,560,0), XLBOBIBB_MASK
, POWER8
, PPCVLE
, {0}},
5769 {"btarl", XLO(19,BOU
,560,1), XLBOBIBB_MASK
, POWER8
, PPCVLE
, {0}},
5770 {"bdnztar-", XLO(19,BODNZM4
,560,0), XLBOBIBB_MASK
, POWER8
, PPCVLE
, {0}},
5771 {"bdnztarl-", XLO(19,BODNZM4
,560,1), XLBOBIBB_MASK
, POWER8
, PPCVLE
, {0}},
5772 {"bdnztar+", XLO(19,BODNZP4
,560,0), XLBOBIBB_MASK
, POWER8
, PPCVLE
, {0}},
5773 {"bdnztarl+", XLO(19,BODNZP4
,560,1), XLBOBIBB_MASK
, POWER8
, PPCVLE
, {0}},
5774 {"bdztar-", XLO(19,BODZM4
,560,0), XLBOBIBB_MASK
, POWER8
, PPCVLE
, {0}},
5775 {"bdztarl-", XLO(19,BODZM4
,560,1), XLBOBIBB_MASK
, POWER8
, PPCVLE
, {0}},
5776 {"bdztar+", XLO(19,BODZP4
,560,0), XLBOBIBB_MASK
, POWER8
, PPCVLE
, {0}},
5777 {"bdztarl+", XLO(19,BODZP4
,560,1), XLBOBIBB_MASK
, POWER8
, PPCVLE
, {0}},
5779 {"bgetar", XLOCB(19,BOF
,CBLT
,560,0), XLBOCBBB_MASK
, POWER8
, PPCVLE
, {CR
}},
5780 {"bnltar", XLOCB(19,BOF
,CBLT
,560,0), XLBOCBBB_MASK
, POWER8
, PPCVLE
, {CR
}},
5781 {"bgetarl", XLOCB(19,BOF
,CBLT
,560,1), XLBOCBBB_MASK
, POWER8
, PPCVLE
, {CR
}},
5782 {"bnltarl", XLOCB(19,BOF
,CBLT
,560,1), XLBOCBBB_MASK
, POWER8
, PPCVLE
, {CR
}},
5783 {"bletar", XLOCB(19,BOF
,CBGT
,560,0), XLBOCBBB_MASK
, POWER8
, PPCVLE
, {CR
}},
5784 {"bngtar", XLOCB(19,BOF
,CBGT
,560,0), XLBOCBBB_MASK
, POWER8
, PPCVLE
, {CR
}},
5785 {"bletarl", XLOCB(19,BOF
,CBGT
,560,1), XLBOCBBB_MASK
, POWER8
, PPCVLE
, {CR
}},
5786 {"bngtarl", XLOCB(19,BOF
,CBGT
,560,1), XLBOCBBB_MASK
, POWER8
, PPCVLE
, {CR
}},
5787 {"bnetar", XLOCB(19,BOF
,CBEQ
,560,0), XLBOCBBB_MASK
, POWER8
, PPCVLE
, {CR
}},
5788 {"bnetarl", XLOCB(19,BOF
,CBEQ
,560,1), XLBOCBBB_MASK
, POWER8
, PPCVLE
, {CR
}},
5789 {"bnstar", XLOCB(19,BOF
,CBSO
,560,0), XLBOCBBB_MASK
, POWER8
, PPCVLE
, {CR
}},
5790 {"bnutar", XLOCB(19,BOF
,CBSO
,560,0), XLBOCBBB_MASK
, POWER8
, PPCVLE
, {CR
}},
5791 {"bnstarl", XLOCB(19,BOF
,CBSO
,560,1), XLBOCBBB_MASK
, POWER8
, PPCVLE
, {CR
}},
5792 {"bnutarl", XLOCB(19,BOF
,CBSO
,560,1), XLBOCBBB_MASK
, POWER8
, PPCVLE
, {CR
}},
5793 {"bgetar-", XLOCB(19,BOFM4
,CBLT
,560,0), XLBOCBBB_MASK
, POWER8
, PPCVLE
, {CR
}},
5794 {"bnltar-", XLOCB(19,BOFM4
,CBLT
,560,0), XLBOCBBB_MASK
, POWER8
, PPCVLE
, {CR
}},
5795 {"bgetarl-",XLOCB(19,BOFM4
,CBLT
,560,1), XLBOCBBB_MASK
, POWER8
, PPCVLE
, {CR
}},
5796 {"bnltarl-",XLOCB(19,BOFM4
,CBLT
,560,1), XLBOCBBB_MASK
, POWER8
, PPCVLE
, {CR
}},
5797 {"bletar-", XLOCB(19,BOFM4
,CBGT
,560,0), XLBOCBBB_MASK
, POWER8
, PPCVLE
, {CR
}},
5798 {"bngtar-", XLOCB(19,BOFM4
,CBGT
,560,0), XLBOCBBB_MASK
, POWER8
, PPCVLE
, {CR
}},
5799 {"bletarl-",XLOCB(19,BOFM4
,CBGT
,560,1), XLBOCBBB_MASK
, POWER8
, PPCVLE
, {CR
}},
5800 {"bngtarl-",XLOCB(19,BOFM4
,CBGT
,560,1), XLBOCBBB_MASK
, POWER8
, PPCVLE
, {CR
}},
5801 {"bnetar-", XLOCB(19,BOFM4
,CBEQ
,560,0), XLBOCBBB_MASK
, POWER8
, PPCVLE
, {CR
}},
5802 {"bnetarl-",XLOCB(19,BOFM4
,CBEQ
,560,1), XLBOCBBB_MASK
, POWER8
, PPCVLE
, {CR
}},
5803 {"bnstar-", XLOCB(19,BOFM4
,CBSO
,560,0), XLBOCBBB_MASK
, POWER8
, PPCVLE
, {CR
}},
5804 {"bnutar-", XLOCB(19,BOFM4
,CBSO
,560,0), XLBOCBBB_MASK
, POWER8
, PPCVLE
, {CR
}},
5805 {"bnstarl-",XLOCB(19,BOFM4
,CBSO
,560,1), XLBOCBBB_MASK
, POWER8
, PPCVLE
, {CR
}},
5806 {"bnutarl-",XLOCB(19,BOFM4
,CBSO
,560,1), XLBOCBBB_MASK
, POWER8
, PPCVLE
, {CR
}},
5807 {"bgetar+", XLOCB(19,BOFP4
,CBLT
,560,0), XLBOCBBB_MASK
, POWER8
, PPCVLE
, {CR
}},
5808 {"bnltar+", XLOCB(19,BOFP4
,CBLT
,560,0), XLBOCBBB_MASK
, POWER8
, PPCVLE
, {CR
}},
5809 {"bgetarl+",XLOCB(19,BOFP4
,CBLT
,560,1), XLBOCBBB_MASK
, POWER8
, PPCVLE
, {CR
}},
5810 {"bnltarl+",XLOCB(19,BOFP4
,CBLT
,560,1), XLBOCBBB_MASK
, POWER8
, PPCVLE
, {CR
}},
5811 {"bletar+", XLOCB(19,BOFP4
,CBGT
,560,0), XLBOCBBB_MASK
, POWER8
, PPCVLE
, {CR
}},
5812 {"bngtar+", XLOCB(19,BOFP4
,CBGT
,560,0), XLBOCBBB_MASK
, POWER8
, PPCVLE
, {CR
}},
5813 {"bletarl+",XLOCB(19,BOFP4
,CBGT
,560,1), XLBOCBBB_MASK
, POWER8
, PPCVLE
, {CR
}},
5814 {"bngtarl+",XLOCB(19,BOFP4
,CBGT
,560,1), XLBOCBBB_MASK
, POWER8
, PPCVLE
, {CR
}},
5815 {"bnetar+", XLOCB(19,BOFP4
,CBEQ
,560,0), XLBOCBBB_MASK
, POWER8
, PPCVLE
, {CR
}},
5816 {"bnetarl+",XLOCB(19,BOFP4
,CBEQ
,560,1), XLBOCBBB_MASK
, POWER8
, PPCVLE
, {CR
}},
5817 {"bnstar+", XLOCB(19,BOFP4
,CBSO
,560,0), XLBOCBBB_MASK
, POWER8
, PPCVLE
, {CR
}},
5818 {"bnutar+", XLOCB(19,BOFP4
,CBSO
,560,0), XLBOCBBB_MASK
, POWER8
, PPCVLE
, {CR
}},
5819 {"bnstarl+",XLOCB(19,BOFP4
,CBSO
,560,1), XLBOCBBB_MASK
, POWER8
, PPCVLE
, {CR
}},
5820 {"bnutarl+",XLOCB(19,BOFP4
,CBSO
,560,1), XLBOCBBB_MASK
, POWER8
, PPCVLE
, {CR
}},
5821 {"blttar", XLOCB(19,BOT
,CBLT
,560,0), XLBOCBBB_MASK
, POWER8
, PPCVLE
, {CR
}},
5822 {"blttarl", XLOCB(19,BOT
,CBLT
,560,1), XLBOCBBB_MASK
, POWER8
, PPCVLE
, {CR
}},
5823 {"bgttar", XLOCB(19,BOT
,CBGT
,560,0), XLBOCBBB_MASK
, POWER8
, PPCVLE
, {CR
}},
5824 {"bgttarl", XLOCB(19,BOT
,CBGT
,560,1), XLBOCBBB_MASK
, POWER8
, PPCVLE
, {CR
}},
5825 {"beqtar", XLOCB(19,BOT
,CBEQ
,560,0), XLBOCBBB_MASK
, POWER8
, PPCVLE
, {CR
}},
5826 {"beqtarl", XLOCB(19,BOT
,CBEQ
,560,1), XLBOCBBB_MASK
, POWER8
, PPCVLE
, {CR
}},
5827 {"bsotar", XLOCB(19,BOT
,CBSO
,560,0), XLBOCBBB_MASK
, POWER8
, PPCVLE
, {CR
}},
5828 {"buntar", XLOCB(19,BOT
,CBSO
,560,0), XLBOCBBB_MASK
, POWER8
, PPCVLE
, {CR
}},
5829 {"bsotarl", XLOCB(19,BOT
,CBSO
,560,1), XLBOCBBB_MASK
, POWER8
, PPCVLE
, {CR
}},
5830 {"buntarl", XLOCB(19,BOT
,CBSO
,560,1), XLBOCBBB_MASK
, POWER8
, PPCVLE
, {CR
}},
5831 {"blttar-", XLOCB(19,BOTM4
,CBLT
,560,0), XLBOCBBB_MASK
, POWER8
, PPCVLE
, {CR
}},
5832 {"blttarl-",XLOCB(19,BOTM4
,CBLT
,560,1), XLBOCBBB_MASK
, POWER8
, PPCVLE
, {CR
}},
5833 {"bgttar-", XLOCB(19,BOTM4
,CBGT
,560,0), XLBOCBBB_MASK
, POWER8
, PPCVLE
, {CR
}},
5834 {"bgttarl-",XLOCB(19,BOTM4
,CBGT
,560,1), XLBOCBBB_MASK
, POWER8
, PPCVLE
, {CR
}},
5835 {"beqtar-", XLOCB(19,BOTM4
,CBEQ
,560,0), XLBOCBBB_MASK
, POWER8
, PPCVLE
, {CR
}},
5836 {"beqtarl-",XLOCB(19,BOTM4
,CBEQ
,560,1), XLBOCBBB_MASK
, POWER8
, PPCVLE
, {CR
}},
5837 {"bsotar-", XLOCB(19,BOTM4
,CBSO
,560,0), XLBOCBBB_MASK
, POWER8
, PPCVLE
, {CR
}},
5838 {"buntar-", XLOCB(19,BOTM4
,CBSO
,560,0), XLBOCBBB_MASK
, POWER8
, PPCVLE
, {CR
}},
5839 {"bsotarl-",XLOCB(19,BOTM4
,CBSO
,560,1), XLBOCBBB_MASK
, POWER8
, PPCVLE
, {CR
}},
5840 {"buntarl-",XLOCB(19,BOTM4
,CBSO
,560,1), XLBOCBBB_MASK
, POWER8
, PPCVLE
, {CR
}},
5841 {"blttar+", XLOCB(19,BOTP4
,CBLT
,560,0), XLBOCBBB_MASK
, POWER8
, PPCVLE
, {CR
}},
5842 {"blttarl+",XLOCB(19,BOTP4
,CBLT
,560,1), XLBOCBBB_MASK
, POWER8
, PPCVLE
, {CR
}},
5843 {"bgttar+", XLOCB(19,BOTP4
,CBGT
,560,0), XLBOCBBB_MASK
, POWER8
, PPCVLE
, {CR
}},
5844 {"bgttarl+",XLOCB(19,BOTP4
,CBGT
,560,1), XLBOCBBB_MASK
, POWER8
, PPCVLE
, {CR
}},
5845 {"beqtar+", XLOCB(19,BOTP4
,CBEQ
,560,0), XLBOCBBB_MASK
, POWER8
, PPCVLE
, {CR
}},
5846 {"beqtarl+",XLOCB(19,BOTP4
,CBEQ
,560,1), XLBOCBBB_MASK
, POWER8
, PPCVLE
, {CR
}},
5847 {"bsotar+", XLOCB(19,BOTP4
,CBSO
,560,0), XLBOCBBB_MASK
, POWER8
, PPCVLE
, {CR
}},
5848 {"buntar+", XLOCB(19,BOTP4
,CBSO
,560,0), XLBOCBBB_MASK
, POWER8
, PPCVLE
, {CR
}},
5849 {"bsotarl+",XLOCB(19,BOTP4
,CBSO
,560,1), XLBOCBBB_MASK
, POWER8
, PPCVLE
, {CR
}},
5850 {"buntarl+",XLOCB(19,BOTP4
,CBSO
,560,1), XLBOCBBB_MASK
, POWER8
, PPCVLE
, {CR
}},
5852 {"bdnzftar", XLO(19,BODNZF
,560,0), XLBOBB_MASK
, POWER8
, PPCVLE
, {BI
}},
5853 {"bdnzftarl", XLO(19,BODNZF
,560,1), XLBOBB_MASK
, POWER8
, PPCVLE
, {BI
}},
5854 {"bdzftar", XLO(19,BODZF
,560,0), XLBOBB_MASK
, POWER8
, PPCVLE
, {BI
}},
5855 {"bdzftarl", XLO(19,BODZF
,560,1), XLBOBB_MASK
, POWER8
, PPCVLE
, {BI
}},
5857 {"bftar", XLO(19,BOF
,560,0), XLBOBB_MASK
, POWER8
, PPCVLE
, {BI
}},
5858 {"bftarl", XLO(19,BOF
,560,1), XLBOBB_MASK
, POWER8
, PPCVLE
, {BI
}},
5859 {"bftar-", XLO(19,BOFM4
,560,0), XLBOBB_MASK
, POWER8
, PPCVLE
, {BI
}},
5860 {"bftarl-", XLO(19,BOFM4
,560,1), XLBOBB_MASK
, POWER8
, PPCVLE
, {BI
}},
5861 {"bftar+", XLO(19,BOFP4
,560,0), XLBOBB_MASK
, POWER8
, PPCVLE
, {BI
}},
5862 {"bftarl+", XLO(19,BOFP4
,560,1), XLBOBB_MASK
, POWER8
, PPCVLE
, {BI
}},
5864 {"bdnzttar", XLO(19,BODNZT
,560,0), XLBOBB_MASK
, POWER8
, PPCVLE
, {BI
}},
5865 {"bdnzttarl", XLO(19,BODNZT
,560,1), XLBOBB_MASK
, POWER8
, PPCVLE
, {BI
}},
5866 {"bdzttar", XLO(19,BODZT
,560,0), XLBOBB_MASK
, POWER8
, PPCVLE
, {BI
}},
5867 {"bdzttarl", XLO(19,BODZT
,560,1), XLBOBB_MASK
, POWER8
, PPCVLE
, {BI
}},
5869 {"bttar", XLO(19,BOT
,560,0), XLBOBB_MASK
, POWER8
, PPCVLE
, {BI
}},
5870 {"bttarl", XLO(19,BOT
,560,1), XLBOBB_MASK
, POWER8
, PPCVLE
, {BI
}},
5871 {"bttar-", XLO(19,BOTM4
,560,0), XLBOBB_MASK
, POWER8
, PPCVLE
, {BI
}},
5872 {"bttarl-", XLO(19,BOTM4
,560,1), XLBOBB_MASK
, POWER8
, PPCVLE
, {BI
}},
5873 {"bttar+", XLO(19,BOTP4
,560,0), XLBOBB_MASK
, POWER8
, PPCVLE
, {BI
}},
5874 {"bttarl+", XLO(19,BOTP4
,560,1), XLBOBB_MASK
, POWER8
, PPCVLE
, {BI
}},
5876 {"bctar-", XLLK(19,560,0), XLBH_MASK
, POWER8
, PPCVLE
, {BOM
, BI
, BH
}},
5877 {"bctar+", XLLK(19,560,0), XLBH_MASK
, POWER8
, PPCVLE
, {BOP
, BI
, BH
}},
5878 {"bctar", XLLK(19,560,0), XLBH_MASK
, POWER8
, PPCVLE
, {BO
, BI
, BH
}},
5879 {"bctarl-", XLLK(19,560,1), XLBH_MASK
, POWER8
, PPCVLE
, {BOM
, BI
, BH
}},
5880 {"bctarl+", XLLK(19,560,1), XLBH_MASK
, POWER8
, PPCVLE
, {BOP
, BI
, BH
}},
5881 {"bctarl", XLLK(19,560,1), XLBH_MASK
, POWER8
, PPCVLE
, {BO
, BI
, BH
}},
5883 {"rlwimi", M(20,0), M_MASK
, PPCCOM
, PPCVLE
, {RA
, RS
, SH
, MBE
, ME
}},
5884 {"rlimi", M(20,0), M_MASK
, PWRCOM
, PPCVLE
, {RA
, RS
, SH
, MBE
, ME
}},
5886 {"rlwimi.", M(20,1), M_MASK
, PPCCOM
, PPCVLE
, {RA
, RS
, SH
, MBE
, ME
}},
5887 {"rlimi.", M(20,1), M_MASK
, PWRCOM
, PPCVLE
, {RA
, RS
, SH
, MBE
, ME
}},
5889 {"rotlwi", MME(21,31,0), MMBME_MASK
, PPCCOM
, PPCVLE
, {RA
, RS
, SH
}},
5890 {"clrlwi", MME(21,31,0), MSHME_MASK
, PPCCOM
, PPCVLE
, {RA
, RS
, MB
}},
5891 {"rlwinm", M(21,0), M_MASK
, PPCCOM
, PPCVLE
, {RA
, RS
, SH
, MBE
, ME
}},
5892 {"rlinm", M(21,0), M_MASK
, PWRCOM
, PPCVLE
, {RA
, RS
, SH
, MBE
, ME
}},
5893 {"rotlwi.", MME(21,31,1), MMBME_MASK
, PPCCOM
, PPCVLE
, {RA
, RS
, SH
}},
5894 {"clrlwi.", MME(21,31,1), MSHME_MASK
, PPCCOM
, PPCVLE
, {RA
, RS
, MB
}},
5895 {"rlwinm.", M(21,1), M_MASK
, PPCCOM
, PPCVLE
, {RA
, RS
, SH
, MBE
, ME
}},
5896 {"rlinm.", M(21,1), M_MASK
, PWRCOM
, PPCVLE
, {RA
, RS
, SH
, MBE
, ME
}},
5898 {"rlmi", M(22,0), M_MASK
, M601
, PPCVLE
, {RA
, RS
, RB
, MBE
, ME
}},
5899 {"rlmi.", M(22,1), M_MASK
, M601
, PPCVLE
, {RA
, RS
, RB
, MBE
, ME
}},
5901 {"rotlw", MME(23,31,0), MMBME_MASK
, PPCCOM
, PPCVLE
, {RA
, RS
, RB
}},
5902 {"rlwnm", M(23,0), M_MASK
, PPCCOM
, PPCVLE
, {RA
, RS
, RB
, MBE
, ME
}},
5903 {"rlnm", M(23,0), M_MASK
, PWRCOM
, PPCVLE
, {RA
, RS
, RB
, MBE
, ME
}},
5904 {"rotlw.", MME(23,31,1), MMBME_MASK
, PPCCOM
, PPCVLE
, {RA
, RS
, RB
}},
5905 {"rlwnm.", M(23,1), M_MASK
, PPCCOM
, PPCVLE
, {RA
, RS
, RB
, MBE
, ME
}},
5906 {"rlnm.", M(23,1), M_MASK
, PWRCOM
, PPCVLE
, {RA
, RS
, RB
, MBE
, ME
}},
5908 {"nop", OP(24), 0xffffffff, PPCCOM
, PPCVLE
, {0}},
5909 {"ori", OP(24), OP_MASK
, PPCCOM
, PPCVLE
, {RA
, RS
, UI
}},
5910 {"oril", OP(24), OP_MASK
, PWRCOM
, PPCVLE
, {RA
, RS
, UI
}},
5912 {"oris", OP(25), OP_MASK
, PPCCOM
, PPCVLE
, {RA
, RS
, UI
}},
5913 {"oriu", OP(25), OP_MASK
, PWRCOM
, PPCVLE
, {RA
, RS
, UI
}},
5915 {"xnop", OP(26), 0xffffffff, PPCCOM
, PPCVLE
, {0}},
5916 {"xori", OP(26), OP_MASK
, PPCCOM
, PPCVLE
, {RA
, RS
, UI
}},
5917 {"xoril", OP(26), OP_MASK
, PWRCOM
, PPCVLE
, {RA
, RS
, UI
}},
5919 {"xoris", OP(27), OP_MASK
, PPCCOM
, PPCVLE
, {RA
, RS
, UI
}},
5920 {"xoriu", OP(27), OP_MASK
, PWRCOM
, PPCVLE
, {RA
, RS
, UI
}},
5922 {"andi.", OP(28), OP_MASK
, PPCCOM
, PPCVLE
, {RA
, RS
, UI
}},
5923 {"andil.", OP(28), OP_MASK
, PWRCOM
, PPCVLE
, {RA
, RS
, UI
}},
5925 {"andis.", OP(29), OP_MASK
, PPCCOM
, PPCVLE
, {RA
, RS
, UI
}},
5926 {"andiu.", OP(29), OP_MASK
, PWRCOM
, PPCVLE
, {RA
, RS
, UI
}},
5928 {"rotldi", MD(30,0,0), MDMB_MASK
, PPC64
, PPCVLE
, {RA
, RS
, SH6
}},
5929 {"clrldi", MD(30,0,0), MDSH_MASK
, PPC64
, PPCVLE
, {RA
, RS
, MB6
}},
5930 {"rldicl", MD(30,0,0), MD_MASK
, PPC64
, PPCVLE
, {RA
, RS
, SH6
, MB6
}},
5931 {"rotldi.", MD(30,0,1), MDMB_MASK
, PPC64
, PPCVLE
, {RA
, RS
, SH6
}},
5932 {"clrldi.", MD(30,0,1), MDSH_MASK
, PPC64
, PPCVLE
, {RA
, RS
, MB6
}},
5933 {"rldicl.", MD(30,0,1), MD_MASK
, PPC64
, PPCVLE
, {RA
, RS
, SH6
, MB6
}},
5935 {"rldicr", MD(30,1,0), MD_MASK
, PPC64
, PPCVLE
, {RA
, RS
, SH6
, ME6
}},
5936 {"rldicr.", MD(30,1,1), MD_MASK
, PPC64
, PPCVLE
, {RA
, RS
, SH6
, ME6
}},
5938 {"rldic", MD(30,2,0), MD_MASK
, PPC64
, PPCVLE
, {RA
, RS
, SH6
, MB6
}},
5939 {"rldic.", MD(30,2,1), MD_MASK
, PPC64
, PPCVLE
, {RA
, RS
, SH6
, MB6
}},
5941 {"rldimi", MD(30,3,0), MD_MASK
, PPC64
, PPCVLE
, {RA
, RS
, SH6
, MB6
}},
5942 {"rldimi.", MD(30,3,1), MD_MASK
, PPC64
, PPCVLE
, {RA
, RS
, SH6
, MB6
}},
5944 {"rotld", MDS(30,8,0), MDSMB_MASK
, PPC64
, PPCVLE
, {RA
, RS
, RB
}},
5945 {"rldcl", MDS(30,8,0), MDS_MASK
, PPC64
, PPCVLE
, {RA
, RS
, RB
, MB6
}},
5946 {"rotld.", MDS(30,8,1), MDSMB_MASK
, PPC64
, PPCVLE
, {RA
, RS
, RB
}},
5947 {"rldcl.", MDS(30,8,1), MDS_MASK
, PPC64
, PPCVLE
, {RA
, RS
, RB
, MB6
}},
5949 {"rldcr", MDS(30,9,0), MDS_MASK
, PPC64
, PPCVLE
, {RA
, RS
, RB
, ME6
}},
5950 {"rldcr.", MDS(30,9,1), MDS_MASK
, PPC64
, PPCVLE
, {RA
, RS
, RB
, ME6
}},
5952 {"cmpw", XOPL(31,0,0), XCMPL_MASK
, PPCCOM
, 0, {OBF
, RA
, RB
}},
5953 {"cmpd", XOPL(31,0,1), XCMPL_MASK
, PPC64
, 0, {OBF
, RA
, RB
}},
5954 {"cmp", X(31,0), XCMP_MASK
, PPC
, 0, {BF
, L32OPT
, RA
, RB
}},
5955 {"cmp", X(31,0), XCMPL_MASK
, PWRCOM
, PPC
, {BF
, RA
, RB
}},
5957 {"twlgt", XTO(31,4,TOLGT
), XTO_MASK
, PPCCOM
, 0, {RA
, RB
}},
5958 {"tlgt", XTO(31,4,TOLGT
), XTO_MASK
, PWRCOM
, 0, {RA
, RB
}},
5959 {"twllt", XTO(31,4,TOLLT
), XTO_MASK
, PPCCOM
, 0, {RA
, RB
}},
5960 {"tllt", XTO(31,4,TOLLT
), XTO_MASK
, PWRCOM
, 0, {RA
, RB
}},
5961 {"tweq", XTO(31,4,TOEQ
), XTO_MASK
, PPCCOM
, 0, {RA
, RB
}},
5962 {"teq", XTO(31,4,TOEQ
), XTO_MASK
, PWRCOM
, 0, {RA
, RB
}},
5963 {"twlge", XTO(31,4,TOLGE
), XTO_MASK
, PPCCOM
, 0, {RA
, RB
}},
5964 {"tlge", XTO(31,4,TOLGE
), XTO_MASK
, PWRCOM
, 0, {RA
, RB
}},
5965 {"twlnl", XTO(31,4,TOLNL
), XTO_MASK
, PPCCOM
, 0, {RA
, RB
}},
5966 {"tlnl", XTO(31,4,TOLNL
), XTO_MASK
, PWRCOM
, 0, {RA
, RB
}},
5967 {"twlle", XTO(31,4,TOLLE
), XTO_MASK
, PPCCOM
, 0, {RA
, RB
}},
5968 {"tlle", XTO(31,4,TOLLE
), XTO_MASK
, PWRCOM
, 0, {RA
, RB
}},
5969 {"twlng", XTO(31,4,TOLNG
), XTO_MASK
, PPCCOM
, 0, {RA
, RB
}},
5970 {"tlng", XTO(31,4,TOLNG
), XTO_MASK
, PWRCOM
, 0, {RA
, RB
}},
5971 {"twgt", XTO(31,4,TOGT
), XTO_MASK
, PPCCOM
, 0, {RA
, RB
}},
5972 {"tgt", XTO(31,4,TOGT
), XTO_MASK
, PWRCOM
, 0, {RA
, RB
}},
5973 {"twge", XTO(31,4,TOGE
), XTO_MASK
, PPCCOM
, 0, {RA
, RB
}},
5974 {"tge", XTO(31,4,TOGE
), XTO_MASK
, PWRCOM
, 0, {RA
, RB
}},
5975 {"twnl", XTO(31,4,TONL
), XTO_MASK
, PPCCOM
, 0, {RA
, RB
}},
5976 {"tnl", XTO(31,4,TONL
), XTO_MASK
, PWRCOM
, 0, {RA
, RB
}},
5977 {"twlt", XTO(31,4,TOLT
), XTO_MASK
, PPCCOM
, 0, {RA
, RB
}},
5978 {"tlt", XTO(31,4,TOLT
), XTO_MASK
, PWRCOM
, 0, {RA
, RB
}},
5979 {"twle", XTO(31,4,TOLE
), XTO_MASK
, PPCCOM
, 0, {RA
, RB
}},
5980 {"tle", XTO(31,4,TOLE
), XTO_MASK
, PWRCOM
, 0, {RA
, RB
}},
5981 {"twng", XTO(31,4,TONG
), XTO_MASK
, PPCCOM
, 0, {RA
, RB
}},
5982 {"tng", XTO(31,4,TONG
), XTO_MASK
, PWRCOM
, 0, {RA
, RB
}},
5983 {"twne", XTO(31,4,TONE
), XTO_MASK
, PPCCOM
, 0, {RA
, RB
}},
5984 {"tne", XTO(31,4,TONE
), XTO_MASK
, PWRCOM
, 0, {RA
, RB
}},
5985 {"trap", XTO(31,4,TOU
), 0xffffffff, PPCCOM
, 0, {0}},
5986 {"twu", XTO(31,4,TOU
), XTO_MASK
, PPCCOM
, 0, {RA
, RB
}},
5987 {"tu", XTO(31,4,TOU
), XTO_MASK
, PWRCOM
, 0, {RA
, RB
}},
5988 {"tw", X(31,4), X_MASK
, PPCCOM
, 0, {TO
, RA
, RB
}},
5989 {"t", X(31,4), X_MASK
, PWRCOM
, 0, {TO
, RA
, RB
}},
5991 {"lvsl", X(31,6), X_MASK
, PPCVEC
, 0, {VD
, RA0
, RB
}},
5992 {"lvebx", X(31,7), X_MASK
, PPCVEC
, 0, {VD
, RA0
, RB
}},
5993 {"lbfcmx", APU(31,7,0), APU_MASK
, PPC405
, 0, {FCRT
, RA
, RB
}},
5995 {"subfc", XO(31,8,0,0), XO_MASK
, PPCCOM
, 0, {RT
, RA
, RB
}},
5996 {"sf", XO(31,8,0,0), XO_MASK
, PWRCOM
, 0, {RT
, RA
, RB
}},
5997 {"subc", XO(31,8,0,0), XO_MASK
, PPCCOM
, 0, {RT
, RB
, RA
}},
5998 {"subfc.", XO(31,8,0,1), XO_MASK
, PPCCOM
, 0, {RT
, RA
, RB
}},
5999 {"sf.", XO(31,8,0,1), XO_MASK
, PWRCOM
, 0, {RT
, RA
, RB
}},
6000 {"subc.", XO(31,8,0,1), XO_MASK
, PPCCOM
, 0, {RT
, RB
, RA
}},
6002 {"mulhdu", XO(31,9,0,0), XO_MASK
, PPC64
, 0, {RT
, RA
, RB
}},
6003 {"mulhdu.", XO(31,9,0,1), XO_MASK
, PPC64
, 0, {RT
, RA
, RB
}},
6005 {"addc", XO(31,10,0,0), XO_MASK
, PPCCOM
, 0, {RT
, RA
, RB
}},
6006 {"a", XO(31,10,0,0), XO_MASK
, PWRCOM
, 0, {RT
, RA
, RB
}},
6007 {"addc.", XO(31,10,0,1), XO_MASK
, PPCCOM
, 0, {RT
, RA
, RB
}},
6008 {"a.", XO(31,10,0,1), XO_MASK
, PWRCOM
, 0, {RT
, RA
, RB
}},
6010 {"mulhwu", XO(31,11,0,0), XO_MASK
, PPC
, 0, {RT
, RA
, RB
}},
6011 {"mulhwu.", XO(31,11,0,1), XO_MASK
, PPC
, 0, {RT
, RA
, RB
}},
6013 {"lxsiwzx", X(31,12), XX1_MASK
, PPCVSX2
, 0, {XT6
, RA0
, RB
}},
6015 {"isellt", X(31,15), X_MASK
, PPCISEL
, 0, {RT
, RA0
, RB
}},
6017 {"tlbilxlpid", XTO(31,18,0), XTO_MASK
, E500MC
|PPCA2
, 0, {0}},
6018 {"tlbilxpid", XTO(31,18,1), XTO_MASK
, E500MC
|PPCA2
, 0, {0}},
6019 {"tlbilxva", XTO(31,18,3), XTO_MASK
, E500MC
|PPCA2
, 0, {RA0
, RB
}},
6020 {"tlbilx", X(31,18), X_MASK
, E500MC
|PPCA2
, 0, {T
, RA0
, RB
}},
6022 {"mfcr", XFXM(31,19,0,0), XFXFXM_MASK
, COM
, 0, {RT
, FXM4
}},
6023 {"mfocrf", XFXM(31,19,0,1), XFXFXM_MASK
, COM
, 0, {RT
, FXM
}},
6025 {"lwarx", X(31,20), XEH_MASK
, PPC
, 0, {RT
, RA0
, RB
, EH
}},
6027 {"ldx", X(31,21), X_MASK
, PPC64
, 0, {RT
, RA0
, RB
}},
6029 {"icbt", X(31,22), X_MASK
, BOOKE
|PPCE300
|PPCA2
|PPC476
, 0, {CT
, RA0
, RB
}},
6031 {"lwzx", X(31,23), X_MASK
, PPCCOM
, 0, {RT
, RA0
, RB
}},
6032 {"lx", X(31,23), X_MASK
, PWRCOM
, 0, {RT
, RA
, RB
}},
6034 {"slw", XRC(31,24,0), X_MASK
, PPCCOM
, 0, {RA
, RS
, RB
}},
6035 {"sl", XRC(31,24,0), X_MASK
, PWRCOM
, 0, {RA
, RS
, RB
}},
6036 {"slw.", XRC(31,24,1), X_MASK
, PPCCOM
, 0, {RA
, RS
, RB
}},
6037 {"sl.", XRC(31,24,1), X_MASK
, PWRCOM
, 0, {RA
, RS
, RB
}},
6039 {"cntlzw", XRC(31,26,0), XRB_MASK
, PPCCOM
, 0, {RA
, RS
}},
6040 {"cntlz", XRC(31,26,0), XRB_MASK
, PWRCOM
, 0, {RA
, RS
}},
6041 {"cntlzw.", XRC(31,26,1), XRB_MASK
, PPCCOM
, 0, {RA
, RS
}},
6042 {"cntlz.", XRC(31,26,1), XRB_MASK
, PWRCOM
, 0, {RA
, RS
}},
6044 {"sld", XRC(31,27,0), X_MASK
, PPC64
, 0, {RA
, RS
, RB
}},
6045 {"sld.", XRC(31,27,1), X_MASK
, PPC64
, 0, {RA
, RS
, RB
}},
6047 {"and", XRC(31,28,0), X_MASK
, COM
, 0, {RA
, RS
, RB
}},
6048 {"and.", XRC(31,28,1), X_MASK
, COM
, 0, {RA
, RS
, RB
}},
6050 {"maskg", XRC(31,29,0), X_MASK
, M601
, PPCA2
, {RA
, RS
, RB
}},
6051 {"maskg.", XRC(31,29,1), X_MASK
, M601
, PPCA2
, {RA
, RS
, RB
}},
6053 {"ldepx", X(31,29), X_MASK
, E500MC
|PPCA2
, 0, {RT
, RA0
, RB
}},
6055 {"waitasec", X(31,30), XRTRARB_MASK
, POWER8
, POWER9
, {0}},
6056 {"wait", X(31,30), XWC_MASK
, POWER9
, 0, {WC
}},
6058 {"lwepx", X(31,31), X_MASK
, E500MC
|PPCA2
, 0, {RT
, RA0
, RB
}},
6060 {"cmplw", XOPL(31,32,0), XCMPL_MASK
, PPCCOM
, 0, {OBF
, RA
, RB
}},
6061 {"cmpld", XOPL(31,32,1), XCMPL_MASK
, PPC64
, 0, {OBF
, RA
, RB
}},
6062 {"cmpl", X(31,32), XCMP_MASK
, PPC
, 0, {BF
, L32OPT
, RA
, RB
}},
6063 {"cmpl", X(31,32), XCMPL_MASK
, PWRCOM
, PPC
, {BF
, RA
, RB
}},
6065 {"lvsr", X(31,38), X_MASK
, PPCVEC
, 0, {VD
, RA0
, RB
}},
6066 {"lvehx", X(31,39), X_MASK
, PPCVEC
, 0, {VD
, RA0
, RB
}},
6067 {"lhfcmx", APU(31,39,0), APU_MASK
, PPC405
, 0, {FCRT
, RA
, RB
}},
6069 {"mviwsplt", X(31,46), X_MASK
, E6500
, 0, {VD
, RA
, RB
}},
6071 {"iselgt", X(31,47), X_MASK
, PPCISEL
, 0, {RT
, RA0
, RB
}},
6073 {"lvewx", X(31,71), X_MASK
, PPCVEC
, 0, {VD
, RA0
, RB
}},
6075 {"addg6s", XO(31,74,0,0), XO_MASK
, POWER6
, 0, {RT
, RA
, RB
}},
6077 {"lxsiwax", X(31,76), XX1_MASK
, PPCVSX2
, 0, {XT6
, RA0
, RB
}},
6079 {"iseleq", X(31,79), X_MASK
, PPCISEL
, 0, {RT
, RA0
, RB
}},
6081 {"isel", XISEL(31,15), XISEL_MASK
, PPCISEL
|TITAN
, 0, {RT
, RA0
, RB
, CRB
}},
6083 {"subf", XO(31,40,0,0), XO_MASK
, PPC
, 0, {RT
, RA
, RB
}},
6084 {"sub", XO(31,40,0,0), XO_MASK
, PPC
, 0, {RT
, RB
, RA
}},
6085 {"subf.", XO(31,40,0,1), XO_MASK
, PPC
, 0, {RT
, RA
, RB
}},
6086 {"sub.", XO(31,40,0,1), XO_MASK
, PPC
, 0, {RT
, RB
, RA
}},
6088 {"mfvsrd", X(31,51), XX1RB_MASK
, PPCVSX2
, 0, {RA
, XS6
}},
6089 {"mffprd", X(31,51), XX1RB_MASK
|1, PPCVSX2
, 0, {RA
, FRS
}},
6090 {"mfvrd", X(31,51)|1, XX1RB_MASK
|1, PPCVSX2
, 0, {RA
, VS
}},
6091 {"eratilx", X(31,51), X_MASK
, PPCA2
, 0, {ERAT_T
, RA
, RB
}},
6093 {"lbarx", X(31,52), XEH_MASK
, POWER8
|E6500
, 0, {RT
, RA0
, RB
, EH
}},
6095 {"ldux", X(31,53), X_MASK
, PPC64
, 0, {RT
, RAL
, RB
}},
6097 {"dcbst", X(31,54), XRT_MASK
, PPC
, 0, {RA0
, RB
}},
6099 {"lwzux", X(31,55), X_MASK
, PPCCOM
, 0, {RT
, RAL
, RB
}},
6100 {"lux", X(31,55), X_MASK
, PWRCOM
, 0, {RT
, RA
, RB
}},
6102 {"cntlzd", XRC(31,58,0), XRB_MASK
, PPC64
, 0, {RA
, RS
}},
6103 {"cntlzd.", XRC(31,58,1), XRB_MASK
, PPC64
, 0, {RA
, RS
}},
6105 {"andc", XRC(31,60,0), X_MASK
, COM
, 0, {RA
, RS
, RB
}},
6106 {"andc.", XRC(31,60,1), X_MASK
, COM
, 0, {RA
, RS
, RB
}},
6108 {"waitrsv", X(31,62)|(1<<21), 0xffffffff, E500MC
|PPCA2
, 0, {0}},
6109 {"waitimpl", X(31,62)|(2<<21), 0xffffffff, E500MC
|PPCA2
, 0, {0}},
6110 {"wait", X(31,62), XWC_MASK
, E500MC
|PPCA2
, 0, {WC
}},
6112 {"dcbstep", XRT(31,63,0), XRT_MASK
, E500MC
|PPCA2
, 0, {RA0
, RB
}},
6114 {"tdlgt", XTO(31,68,TOLGT
), XTO_MASK
, PPC64
, 0, {RA
, RB
}},
6115 {"tdllt", XTO(31,68,TOLLT
), XTO_MASK
, PPC64
, 0, {RA
, RB
}},
6116 {"tdeq", XTO(31,68,TOEQ
), XTO_MASK
, PPC64
, 0, {RA
, RB
}},
6117 {"tdlge", XTO(31,68,TOLGE
), XTO_MASK
, PPC64
, 0, {RA
, RB
}},
6118 {"tdlnl", XTO(31,68,TOLNL
), XTO_MASK
, PPC64
, 0, {RA
, RB
}},
6119 {"tdlle", XTO(31,68,TOLLE
), XTO_MASK
, PPC64
, 0, {RA
, RB
}},
6120 {"tdlng", XTO(31,68,TOLNG
), XTO_MASK
, PPC64
, 0, {RA
, RB
}},
6121 {"tdgt", XTO(31,68,TOGT
), XTO_MASK
, PPC64
, 0, {RA
, RB
}},
6122 {"tdge", XTO(31,68,TOGE
), XTO_MASK
, PPC64
, 0, {RA
, RB
}},
6123 {"tdnl", XTO(31,68,TONL
), XTO_MASK
, PPC64
, 0, {RA
, RB
}},
6124 {"tdlt", XTO(31,68,TOLT
), XTO_MASK
, PPC64
, 0, {RA
, RB
}},
6125 {"tdle", XTO(31,68,TOLE
), XTO_MASK
, PPC64
, 0, {RA
, RB
}},
6126 {"tdng", XTO(31,68,TONG
), XTO_MASK
, PPC64
, 0, {RA
, RB
}},
6127 {"tdne", XTO(31,68,TONE
), XTO_MASK
, PPC64
, 0, {RA
, RB
}},
6128 {"tdu", XTO(31,68,TOU
), XTO_MASK
, PPC64
, 0, {RA
, RB
}},
6129 {"td", X(31,68), X_MASK
, PPC64
, 0, {TO
, RA
, RB
}},
6131 {"lwfcmx", APU(31,71,0), APU_MASK
, PPC405
, 0, {FCRT
, RA
, RB
}},
6132 {"mulhd", XO(31,73,0,0), XO_MASK
, PPC64
, 0, {RT
, RA
, RB
}},
6133 {"mulhd.", XO(31,73,0,1), XO_MASK
, PPC64
, 0, {RT
, RA
, RB
}},
6135 {"mulhw", XO(31,75,0,0), XO_MASK
, PPC
, 0, {RT
, RA
, RB
}},
6136 {"mulhw.", XO(31,75,0,1), XO_MASK
, PPC
, 0, {RT
, RA
, RB
}},
6138 {"dlmzb", XRC(31,78,0), X_MASK
, PPC403
|PPC440
|PPC476
|TITAN
, 0, {RA
, RS
, RB
}},
6139 {"dlmzb.", XRC(31,78,1), X_MASK
, PPC403
|PPC440
|PPC476
|TITAN
, 0, {RA
, RS
, RB
}},
6141 {"mtsrd", X(31,82), XRB_MASK
|(1<<20), PPC64
, 0, {SR
, RS
}},
6143 {"mfmsr", X(31,83), XRARB_MASK
, COM
, 0, {RT
}},
6145 {"ldarx", X(31,84), XEH_MASK
, PPC64
, 0, {RT
, RA0
, RB
, EH
}},
6147 {"dcbfl", XOPL(31,86,1), XRT_MASK
, POWER5
, PPC476
, {RA0
, RB
}},
6148 {"dcbf", X(31,86), XLRT_MASK
, PPC
, 0, {RA0
, RB
, L2OPT
}},
6150 {"lbzx", X(31,87), X_MASK
, COM
, 0, {RT
, RA0
, RB
}},
6152 {"lbepx", X(31,95), X_MASK
, E500MC
|PPCA2
, 0, {RT
, RA0
, RB
}},
6154 {"dni", XRC(31,97,1), XRB_MASK
, E6500
, 0, {DUI
, DCTL
}},
6156 {"lvx", X(31,103), X_MASK
, PPCVEC
, 0, {VD
, RA0
, RB
}},
6157 {"lqfcmx", APU(31,103,0), APU_MASK
, PPC405
, 0, {FCRT
, RA
, RB
}},
6159 {"neg", XO(31,104,0,0), XORB_MASK
, COM
, 0, {RT
, RA
}},
6160 {"neg.", XO(31,104,0,1), XORB_MASK
, COM
, 0, {RT
, RA
}},
6162 {"mul", XO(31,107,0,0), XO_MASK
, M601
, 0, {RT
, RA
, RB
}},
6163 {"mul.", XO(31,107,0,1), XO_MASK
, M601
, 0, {RT
, RA
, RB
}},
6165 {"mvidsplt", X(31,110), X_MASK
, E6500
, 0, {VD
, RA
, RB
}},
6167 {"mtsrdin", X(31,114), XRA_MASK
, PPC64
, 0, {RS
, RB
}},
6169 {"mffprwz", X(31,115), XX1RB_MASK
|1, PPCVSX2
, 0, {RA
, FRS
}},
6170 {"mfvrwz", X(31,115)|1, XX1RB_MASK
|1, PPCVSX2
, 0, {RA
, VS
}},
6171 {"mfvsrwz", X(31,115), XX1RB_MASK
, PPCVSX2
, 0, {RA
, XS6
}},
6173 {"lharx", X(31,116), XEH_MASK
, POWER8
|E6500
, 0, {RT
, RA0
, RB
, EH
}},
6175 {"clf", X(31,118), XTO_MASK
, POWER
, 0, {RA
, RB
}},
6177 {"lbzux", X(31,119), X_MASK
, COM
, 0, {RT
, RAL
, RB
}},
6179 {"popcntb", X(31,122), XRB_MASK
, POWER5
, 0, {RA
, RS
}},
6181 {"not", XRC(31,124,0), X_MASK
, COM
, 0, {RA
, RSB
}},
6182 {"nor", XRC(31,124,0), X_MASK
, COM
, 0, {RA
, RS
, RB
}},
6183 {"not.", XRC(31,124,1), X_MASK
, COM
, 0, {RA
, RSB
}},
6184 {"nor.", XRC(31,124,1), X_MASK
, COM
, 0, {RA
, RS
, RB
}},
6186 {"dcbfep", XRT(31,127,0), XRT_MASK
, E500MC
|PPCA2
, 0, {RA0
, RB
}},
6188 {"setb", X(31,128), XRB_MASK
|(3<<16), POWER9
, 0, {RT
, BFA
}},
6190 {"wrtee", X(31,131), XRARB_MASK
, PPC403
|BOOKE
|PPCA2
|PPC476
, 0, {RS
}},
6192 {"dcbtstls", X(31,134), X_MASK
, PPCCHLK
|PPC476
|TITAN
, 0, {CT
, RA0
, RB
}},
6194 {"stvebx", X(31,135), X_MASK
, PPCVEC
, 0, {VS
, RA0
, RB
}},
6195 {"stbfcmx", APU(31,135,0), APU_MASK
, PPC405
, 0, {FCRT
, RA
, RB
}},
6197 {"subfe", XO(31,136,0,0), XO_MASK
, PPCCOM
, 0, {RT
, RA
, RB
}},
6198 {"sfe", XO(31,136,0,0), XO_MASK
, PWRCOM
, 0, {RT
, RA
, RB
}},
6199 {"subfe.", XO(31,136,0,1), XO_MASK
, PPCCOM
, 0, {RT
, RA
, RB
}},
6200 {"sfe.", XO(31,136,0,1), XO_MASK
, PWRCOM
, 0, {RT
, RA
, RB
}},
6202 {"adde", XO(31,138,0,0), XO_MASK
, PPCCOM
, 0, {RT
, RA
, RB
}},
6203 {"ae", XO(31,138,0,0), XO_MASK
, PWRCOM
, 0, {RT
, RA
, RB
}},
6204 {"adde.", XO(31,138,0,1), XO_MASK
, PPCCOM
, 0, {RT
, RA
, RB
}},
6205 {"ae.", XO(31,138,0,1), XO_MASK
, PWRCOM
, 0, {RT
, RA
, RB
}},
6207 {"stxsiwx", X(31,140), XX1_MASK
, PPCVSX2
, 0, {XS6
, RA0
, RB
}},
6209 {"msgsndp", XRTRA(31,142,0,0), XRTRA_MASK
, POWER8
, 0, {RB
}},
6210 {"dcbtstlse", X(31,142), X_MASK
, PPCCHLK
, E500MC
, {CT
, RA0
, RB
}},
6212 {"mtcr", XFXM(31,144,0xff,0), XRARB_MASK
, COM
, 0, {RS
}},
6213 {"mtcrf", XFXM(31,144,0,0), XFXFXM_MASK
, COM
, 0, {FXM
, RS
}},
6214 {"mtocrf", XFXM(31,144,0,1), XFXFXM_MASK
, COM
, 0, {FXM
, RS
}},
6216 {"mtmsr", X(31,146), XRLARB_MASK
, COM
, 0, {RS
, A_L
}},
6218 {"mtsle", X(31,147), XRTLRARB_MASK
, POWER8
, 0, {L
}},
6220 {"eratsx", XRC(31,147,0), X_MASK
, PPCA2
, 0, {RT
, RA0
, RB
}},
6221 {"eratsx.", XRC(31,147,1), X_MASK
, PPCA2
, 0, {RT
, RA0
, RB
}},
6223 {"stdx", X(31,149), X_MASK
, PPC64
, 0, {RS
, RA0
, RB
}},
6225 {"stwcx.", XRC(31,150,1), X_MASK
, PPC
, 0, {RS
, RA0
, RB
}},
6227 {"stwx", X(31,151), X_MASK
, PPCCOM
, 0, {RS
, RA0
, RB
}},
6228 {"stx", X(31,151), X_MASK
, PWRCOM
, 0, {RS
, RA
, RB
}},
6230 {"slq", XRC(31,152,0), X_MASK
, M601
, 0, {RA
, RS
, RB
}},
6231 {"slq.", XRC(31,152,1), X_MASK
, M601
, 0, {RA
, RS
, RB
}},
6233 {"sle", XRC(31,153,0), X_MASK
, M601
, 0, {RA
, RS
, RB
}},
6234 {"sle.", XRC(31,153,1), X_MASK
, M601
, 0, {RA
, RS
, RB
}},
6236 {"prtyw", X(31,154), XRB_MASK
, POWER6
|PPCA2
|PPC476
, 0, {RA
, RS
}},
6238 {"brw", X(31,155), XRB_MASK
, POWER10
, 0, {RA
, RS
}},
6240 {"stdepx", X(31,157), X_MASK
, E500MC
|PPCA2
, 0, {RS
, RA0
, RB
}},
6242 {"stwepx", X(31,159), X_MASK
, E500MC
|PPCA2
, 0, {RS
, RA0
, RB
}},
6244 {"wrteei", X(31,163), XE_MASK
, PPC403
|BOOKE
|PPCA2
|PPC476
, 0, {E
}},
6246 {"dcbtls", X(31,166), X_MASK
, PPCCHLK
|PPC476
|TITAN
, 0, {CT
, RA0
, RB
}},
6248 {"stvehx", X(31,167), X_MASK
, PPCVEC
, 0, {VS
, RA0
, RB
}},
6249 {"sthfcmx", APU(31,167,0), APU_MASK
, PPC405
, 0, {FCRT
, RA
, RB
}},
6251 {"addex", ZRC(31,170,0), Z2_MASK
, POWER9
, 0, {RT
, RA
, RB
, CY
}},
6253 {"msgclrp", XRTRA(31,174,0,0), XRTRA_MASK
, POWER8
, 0, {RB
}},
6254 {"dcbtlse", X(31,174), X_MASK
, PPCCHLK
, E500MC
, {CT
, RA0
, RB
}},
6256 {"xxmfacc", XVA(31,177,0), XRARB_MASK
|3<<21, POWER10
, 0, {ACC
}},
6257 {"xxmtacc", XVA(31,177,1), XRARB_MASK
|3<<21, POWER10
, 0, {ACC
}},
6258 {"xxsetaccz", XVA(31,177,3), XRARB_MASK
|3<<21, POWER10
, 0, {ACC
}},
6260 {"mtmsrd", X(31,178), XRLARB_MASK
, PPC64
, 0, {RS
, A_L
}},
6262 {"mtvsrd", X(31,179), XX1RB_MASK
, PPCVSX2
, 0, {XT6
, RA
}},
6263 {"mtfprd", X(31,179), XX1RB_MASK
|1, PPCVSX2
, 0, {FRT
, RA
}},
6264 {"mtvrd", X(31,179)|1, XX1RB_MASK
|1, PPCVSX2
, 0, {VD
, RA
}},
6265 {"eratre", X(31,179), X_MASK
, PPCA2
, 0, {RT
, RA
, WS
}},
6267 {"stdux", X(31,181), X_MASK
, PPC64
, 0, {RS
, RAS
, RB
}},
6269 {"stqcx.", XRC(31,182,1), X_MASK
|Q_MASK
, POWER8
, 0, {RSQ
, RA0
, RB
}},
6270 {"wchkall", X(31,182), X_MASK
, PPCA2
, 0, {OBF
}},
6272 {"stwux", X(31,183), X_MASK
, PPCCOM
, 0, {RS
, RAS
, RB
}},
6273 {"stux", X(31,183), X_MASK
, PWRCOM
, 0, {RS
, RA0
, RB
}},
6275 {"sliq", XRC(31,184,0), X_MASK
, M601
, 0, {RA
, RS
, SH
}},
6276 {"sliq.", XRC(31,184,1), X_MASK
, M601
, 0, {RA
, RS
, SH
}},
6278 {"prtyd", X(31,186), XRB_MASK
, POWER6
|PPCA2
, 0, {RA
, RS
}},
6280 {"brd", X(31,187), XRB_MASK
, POWER10
, 0, {RA
, RS
}},
6282 {"cmprb", X(31,192), XCMP_MASK
, POWER9
, 0, {BF
, L
, RA
, RB
}},
6284 {"icblq.", XRC(31,198,1), X_MASK
, E6500
, 0, {CT
, RA0
, RB
}},
6286 {"stvewx", X(31,199), X_MASK
, PPCVEC
, 0, {VS
, RA0
, RB
}},
6287 {"stwfcmx", APU(31,199,0), APU_MASK
, PPC405
, 0, {FCRT
, RA
, RB
}},
6289 {"subfze", XO(31,200,0,0), XORB_MASK
, PPCCOM
, 0, {RT
, RA
}},
6290 {"sfze", XO(31,200,0,0), XORB_MASK
, PWRCOM
, 0, {RT
, RA
}},
6291 {"subfze.", XO(31,200,0,1), XORB_MASK
, PPCCOM
, 0, {RT
, RA
}},
6292 {"sfze.", XO(31,200,0,1), XORB_MASK
, PWRCOM
, 0, {RT
, RA
}},
6294 {"addze", XO(31,202,0,0), XORB_MASK
, PPCCOM
, 0, {RT
, RA
}},
6295 {"aze", XO(31,202,0,0), XORB_MASK
, PWRCOM
, 0, {RT
, RA
}},
6296 {"addze.", XO(31,202,0,1), XORB_MASK
, PPCCOM
, 0, {RT
, RA
}},
6297 {"aze.", XO(31,202,0,1), XORB_MASK
, PWRCOM
, 0, {RT
, RA
}},
6299 {"msgsnd", XRTRA(31,206,0,0), XRTRA_MASK
, E500MC
|PPCA2
|POWER8
, 0, {RB
}},
6301 {"mtsr", X(31,210), XRB_MASK
|(1<<20), COM
, NON32
, {SR
, RS
}},
6303 {"mtfprwa", X(31,211), XX1RB_MASK
|1, PPCVSX2
, 0, {FRT
, RA
}},
6304 {"mtvrwa", X(31,211)|1, XX1RB_MASK
|1, PPCVSX2
, 0, {VD
, RA
}},
6305 {"mtvsrwa", X(31,211), XX1RB_MASK
, PPCVSX2
, 0, {XT6
, RA
}},
6306 {"eratwe", X(31,211), X_MASK
, PPCA2
, 0, {RS
, RA
, WS
}},
6308 {"ldawx.", XRC(31,212,1), X_MASK
, PPCA2
, 0, {RT
, RA0
, RB
}},
6310 {"stdcx.", XRC(31,214,1), X_MASK
, PPC64
, 0, {RS
, RA0
, RB
}},
6312 {"stbx", X(31,215), X_MASK
, COM
, 0, {RS
, RA0
, RB
}},
6314 {"sllq", XRC(31,216,0), X_MASK
, M601
, 0, {RA
, RS
, RB
}},
6315 {"sllq.", XRC(31,216,1), X_MASK
, M601
, 0, {RA
, RS
, RB
}},
6317 {"sleq", XRC(31,217,0), X_MASK
, M601
, 0, {RA
, RS
, RB
}},
6318 {"sleq.", XRC(31,217,1), X_MASK
, M601
, 0, {RA
, RS
, RB
}},
6320 {"brh", X(31,219), XRB_MASK
, POWER10
, 0, {RA
, RS
}},
6322 {"stbepx", X(31,223), X_MASK
, E500MC
|PPCA2
, 0, {RS
, RA0
, RB
}},
6324 {"cmpeqb", X(31,224), XCMPL_MASK
, POWER9
, 0, {BF
, RA
, RB
}},
6326 {"icblc", X(31,230), X_MASK
, PPCCHLK
|PPC476
|TITAN
, 0, {CT
, RA0
, RB
}},
6328 {"stvx", X(31,231), X_MASK
, PPCVEC
, 0, {VS
, RA0
, RB
}},
6329 {"stqfcmx", APU(31,231,0), APU_MASK
, PPC405
, 0, {FCRT
, RA
, RB
}},
6331 {"subfme", XO(31,232,0,0), XORB_MASK
, PPCCOM
, 0, {RT
, RA
}},
6332 {"sfme", XO(31,232,0,0), XORB_MASK
, PWRCOM
, 0, {RT
, RA
}},
6333 {"subfme.", XO(31,232,0,1), XORB_MASK
, PPCCOM
, 0, {RT
, RA
}},
6334 {"sfme.", XO(31,232,0,1), XORB_MASK
, PWRCOM
, 0, {RT
, RA
}},
6336 {"mulld", XO(31,233,0,0), XO_MASK
, PPC64
, 0, {RT
, RA
, RB
}},
6337 {"mulld.", XO(31,233,0,1), XO_MASK
, PPC64
, 0, {RT
, RA
, RB
}},
6339 {"addme", XO(31,234,0,0), XORB_MASK
, PPCCOM
, 0, {RT
, RA
}},
6340 {"ame", XO(31,234,0,0), XORB_MASK
, PWRCOM
, 0, {RT
, RA
}},
6341 {"addme.", XO(31,234,0,1), XORB_MASK
, PPCCOM
, 0, {RT
, RA
}},
6342 {"ame.", XO(31,234,0,1), XORB_MASK
, PWRCOM
, 0, {RT
, RA
}},
6344 {"mullw", XO(31,235,0,0), XO_MASK
, PPCCOM
, 0, {RT
, RA
, RB
}},
6345 {"muls", XO(31,235,0,0), XO_MASK
, PWRCOM
, 0, {RT
, RA
, RB
}},
6346 {"mullw.", XO(31,235,0,1), XO_MASK
, PPCCOM
, 0, {RT
, RA
, RB
}},
6347 {"muls.", XO(31,235,0,1), XO_MASK
, PWRCOM
, 0, {RT
, RA
, RB
}},
6349 {"icblce", X(31,238), X_MASK
, PPCCHLK
, E500MC
|PPCA2
, {CT
, RA
, RB
}},
6350 {"msgclr", XRTRA(31,238,0,0), XRTRA_MASK
, E500MC
|PPCA2
|POWER8
, 0, {RB
}},
6351 {"mtsrin", X(31,242), XRA_MASK
, PPC
, NON32
, {RS
, RB
}},
6352 {"mtsri", X(31,242), XRA_MASK
, POWER
, NON32
, {RS
, RB
}},
6354 {"mtfprwz", X(31,243), XX1RB_MASK
|1, PPCVSX2
, 0, {FRT
, RA
}},
6355 {"mtvrwz", X(31,243)|1, XX1RB_MASK
|1, PPCVSX2
, 0, {VD
, RA
}},
6356 {"mtvsrwz", X(31,243), XX1RB_MASK
, PPCVSX2
, 0, {XT6
, RA
}},
6358 {"dcbtstt", XRT(31,246,0x10), XRT_MASK
, POWER7
, 0, {RA0
, RB
}},
6359 {"dcbtst", X(31,246), X_MASK
, POWER4
, DCBT_EO
, {RA0
, RB
, CT
}},
6360 {"dcbtst", X(31,246), X_MASK
, DCBT_EO
, 0, {CT
, RA0
, RB
}},
6361 {"dcbtst", X(31,246), X_MASK
, PPC
, POWER4
|DCBT_EO
, {RA0
, RB
}},
6363 {"stbux", X(31,247), X_MASK
, COM
, 0, {RS
, RAS
, RB
}},
6365 {"slliq", XRC(31,248,0), X_MASK
, M601
, 0, {RA
, RS
, SH
}},
6366 {"slliq.", XRC(31,248,1), X_MASK
, M601
, 0, {RA
, RS
, SH
}},
6368 {"bpermd", X(31,252), X_MASK
, POWER7
|PPCA2
, 0, {RA
, RS
, RB
}},
6370 {"dcbtstep", XRT(31,255,0), X_MASK
, E500MC
|PPCA2
, 0, {RT
, RA0
, RB
}},
6372 {"mfdcrx", X(31,259), X_MASK
, BOOKE
|PPCA2
|PPC476
, TITAN
, {RS
, RA
}},
6373 {"mfdcrx.", XRC(31,259,1), X_MASK
, PPCA2
, 0, {RS
, RA
}},
6375 {"lvexbx", X(31,261), X_MASK
, E6500
, 0, {VD
, RA0
, RB
}},
6377 {"icbt", X(31,262), XRT_MASK
, PPC403
, 0, {RA
, RB
}},
6379 {"lvepxl", X(31,263), X_MASK
, E6500
, 0, {VD
, RA0
, RB
}},
6381 {"ldfcmx", APU(31,263,0), APU_MASK
, PPC405
, 0, {FCRT
, RA
, RB
}},
6382 {"doz", XO(31,264,0,0), XO_MASK
, M601
, 0, {RT
, RA
, RB
}},
6383 {"doz.", XO(31,264,0,1), XO_MASK
, M601
, 0, {RT
, RA
, RB
}},
6385 {"modud", X(31,265), X_MASK
, POWER9
, 0, {RT
, RA
, RB
}},
6387 {"add", XO(31,266,0,0), XO_MASK
, PPCCOM
, 0, {RT
, RA
, RB
}},
6388 {"cax", XO(31,266,0,0), XO_MASK
, PWRCOM
, 0, {RT
, RA
, RB
}},
6389 {"add.", XO(31,266,0,1), XO_MASK
, PPCCOM
, 0, {RT
, RA
, RB
}},
6390 {"cax.", XO(31,266,0,1), XO_MASK
, PWRCOM
, 0, {RT
, RA
, RB
}},
6392 {"moduw", X(31,267), X_MASK
, POWER9
, 0, {RT
, RA
, RB
}},
6394 {"lxvx", X(31,268), XX1_MASK
|1<<6, PPCVSX3
, 0, {XT6
, RA0
, RB
}},
6395 {"lxvl", X(31,269), XX1_MASK
, PPCVSX3
, 0, {XT6
, RA0
, RB
}},
6397 {"ehpriv", X(31,270), 0xffffffff, E500MC
|PPCA2
, 0, {0}},
6399 {"tlbiel", X(31,274), X_MASK
|1<<20,POWER9
, 0, {RB
, RSO
, RIC
, PRS
, X_R
}},
6400 {"tlbiel", X(31,274), XRTLRA_MASK
, POWER4
, POWER9
|PPC476
, {RB
, LOPT
}},
6402 {"mfapidi", X(31,275), X_MASK
, BOOKE
, E500
|TITAN
, {RT
, RA
}},
6404 {"lqarx", X(31,276), XEH_MASK
|Q_MASK
, POWER8
, 0, {RTQ
, RAX
, RBX
, EH
}},
6406 {"lscbx", XRC(31,277,0), X_MASK
, M601
, 0, {RT
, RA
, RB
}},
6407 {"lscbx.", XRC(31,277,1), X_MASK
, M601
, 0, {RT
, RA
, RB
}},
6409 {"dcbtt", XRT(31,278,0x10), XRT_MASK
, POWER7
, 0, {RA0
, RB
}},
6410 {"dcbt", X(31,278), X_MASK
, POWER4
, DCBT_EO
, {RA0
, RB
, CT
}},
6411 {"dcbt", X(31,278), X_MASK
, DCBT_EO
, 0, {CT
, RA0
, RB
}},
6412 {"dcbt", X(31,278), X_MASK
, PPC
, POWER4
|DCBT_EO
, {RA0
, RB
}},
6414 {"lhzx", X(31,279), X_MASK
, COM
, 0, {RT
, RA0
, RB
}},
6416 {"cdtbcd", X(31,282), XRB_MASK
, POWER6
, 0, {RA
, RS
}},
6418 {"eqv", XRC(31,284,0), X_MASK
, COM
, 0, {RA
, RS
, RB
}},
6419 {"eqv.", XRC(31,284,1), X_MASK
, COM
, 0, {RA
, RS
, RB
}},
6421 {"lhepx", X(31,287), X_MASK
, E500MC
|PPCA2
, 0, {RT
, RA0
, RB
}},
6423 {"mfdcrux", X(31,291), X_MASK
, PPC464
|PPC476
, 0, {RS
, RA
}},
6425 {"lvexhx", X(31,293), X_MASK
, E6500
, 0, {VD
, RA0
, RB
}},
6426 {"lvepx", X(31,295), X_MASK
, E6500
, 0, {VD
, RA0
, RB
}},
6428 {"lxvll", X(31,301), XX1_MASK
, PPCVSX3
, 0, {XT6
, RA0
, RB
}},
6430 {"mfbhrbe", X(31,302), X_MASK
, POWER8
, 0, {RT
, BHRBE
}},
6432 {"tlbie", X(31,306), X_MASK
|1<<20,POWER9
, TITAN
, {RB
, RS
, RIC
, PRS
, X_R
}},
6433 {"tlbie", X(31,306), XRA_MASK
, POWER7
, POWER9
|TITAN
, {RB
, RS
}},
6434 {"tlbie", X(31,306), XRTLRA_MASK
, PPC
, E500
|POWER7
|TITAN
, {RB
, LOPT
}},
6435 {"tlbi", X(31,306), XRT_MASK
, POWER
, 0, {RA0
, RB
}},
6437 {"mfvsrld", X(31,307), XX1RB_MASK
, PPCVSX3
, 0, {RA
, XS6
}},
6439 {"eciwx", X(31,310), X_MASK
, PPC
, E500
|TITAN
, {RT
, RA0
, RB
}},
6441 {"lhzux", X(31,311), X_MASK
, COM
, 0, {RT
, RAL
, RB
}},
6443 {"cbcdtd", X(31,314), XRB_MASK
, POWER6
, 0, {RA
, RS
}},
6445 {"xor", XRC(31,316,0), X_MASK
, COM
, 0, {RA
, RS
, RB
}},
6446 {"xor.", XRC(31,316,1), X_MASK
, COM
, 0, {RA
, RS
, RB
}},
6448 {"dcbtep", XRT(31,319,0), X_MASK
, E500MC
|PPCA2
, 0, {RT
, RA0
, RB
}},
6450 {"mfexisr", XSPR(31,323, 64), XSPR_MASK
, PPC403
, 0, {RT
}},
6451 {"mfexier", XSPR(31,323, 66), XSPR_MASK
, PPC403
, 0, {RT
}},
6452 {"mfbr0", XSPR(31,323,128), XSPR_MASK
, PPC403
, 0, {RT
}},
6453 {"mfbr1", XSPR(31,323,129), XSPR_MASK
, PPC403
, 0, {RT
}},
6454 {"mfbr2", XSPR(31,323,130), XSPR_MASK
, PPC403
, 0, {RT
}},
6455 {"mfbr3", XSPR(31,323,131), XSPR_MASK
, PPC403
, 0, {RT
}},
6456 {"mfbr4", XSPR(31,323,132), XSPR_MASK
, PPC403
, 0, {RT
}},
6457 {"mfbr5", XSPR(31,323,133), XSPR_MASK
, PPC403
, 0, {RT
}},
6458 {"mfbr6", XSPR(31,323,134), XSPR_MASK
, PPC403
, 0, {RT
}},
6459 {"mfbr7", XSPR(31,323,135), XSPR_MASK
, PPC403
, 0, {RT
}},
6460 {"mfbear", XSPR(31,323,144), XSPR_MASK
, PPC403
, 0, {RT
}},
6461 {"mfbesr", XSPR(31,323,145), XSPR_MASK
, PPC403
, 0, {RT
}},
6462 {"mfiocr", XSPR(31,323,160), XSPR_MASK
, PPC403
, 0, {RT
}},
6463 {"mfdmacr0", XSPR(31,323,192), XSPR_MASK
, PPC403
, 0, {RT
}},
6464 {"mfdmact0", XSPR(31,323,193), XSPR_MASK
, PPC403
, 0, {RT
}},
6465 {"mfdmada0", XSPR(31,323,194), XSPR_MASK
, PPC403
, 0, {RT
}},
6466 {"mfdmasa0", XSPR(31,323,195), XSPR_MASK
, PPC403
, 0, {RT
}},
6467 {"mfdmacc0", XSPR(31,323,196), XSPR_MASK
, PPC403
, 0, {RT
}},
6468 {"mfdmacr1", XSPR(31,323,200), XSPR_MASK
, PPC403
, 0, {RT
}},
6469 {"mfdmact1", XSPR(31,323,201), XSPR_MASK
, PPC403
, 0, {RT
}},
6470 {"mfdmada1", XSPR(31,323,202), XSPR_MASK
, PPC403
, 0, {RT
}},
6471 {"mfdmasa1", XSPR(31,323,203), XSPR_MASK
, PPC403
, 0, {RT
}},
6472 {"mfdmacc1", XSPR(31,323,204), XSPR_MASK
, PPC403
, 0, {RT
}},
6473 {"mfdmacr2", XSPR(31,323,208), XSPR_MASK
, PPC403
, 0, {RT
}},
6474 {"mfdmact2", XSPR(31,323,209), XSPR_MASK
, PPC403
, 0, {RT
}},
6475 {"mfdmada2", XSPR(31,323,210), XSPR_MASK
, PPC403
, 0, {RT
}},
6476 {"mfdmasa2", XSPR(31,323,211), XSPR_MASK
, PPC403
, 0, {RT
}},
6477 {"mfdmacc2", XSPR(31,323,212), XSPR_MASK
, PPC403
, 0, {RT
}},
6478 {"mfdmacr3", XSPR(31,323,216), XSPR_MASK
, PPC403
, 0, {RT
}},
6479 {"mfdmact3", XSPR(31,323,217), XSPR_MASK
, PPC403
, 0, {RT
}},
6480 {"mfdmada3", XSPR(31,323,218), XSPR_MASK
, PPC403
, 0, {RT
}},
6481 {"mfdmasa3", XSPR(31,323,219), XSPR_MASK
, PPC403
, 0, {RT
}},
6482 {"mfdmacc3", XSPR(31,323,220), XSPR_MASK
, PPC403
, 0, {RT
}},
6483 {"mfdmasr", XSPR(31,323,224), XSPR_MASK
, PPC403
, 0, {RT
}},
6484 {"mfdcr", X(31,323), X_MASK
, PPC403
|BOOKE
|PPCA2
|PPC476
, E500
|TITAN
, {RT
, SPR
}},
6485 {"mfdcr.", XRC(31,323,1), X_MASK
, PPCA2
, 0, {RT
, SPR
}},
6487 {"lvexwx", X(31,325), X_MASK
, E6500
, 0, {VD
, RA0
, RB
}},
6489 {"dcread", X(31,326), X_MASK
, PPC476
|TITAN
, 0, {RT
, RA0
, RB
}},
6491 {"div", XO(31,331,0,0), XO_MASK
, M601
, 0, {RT
, RA
, RB
}},
6492 {"div.", XO(31,331,0,1), XO_MASK
, M601
, 0, {RT
, RA
, RB
}},
6494 {"lxvdsx", X(31,332), XX1_MASK
, PPCVSX
, 0, {XT6
, RA0
, RB
}},
6496 {"lxvpx", X(31,333), XX1_MASK
, POWER10
, 0, {XTP
, RA0
, RB
}},
6498 {"mfpmr", X(31,334), X_MASK
, PPCPMR
|PPCE300
, 0, {RT
, PMR
}},
6499 {"mftmr", X(31,366), X_MASK
, PPCTMR
, 0, {RT
, TMR
}},
6501 {"slbsync", X(31,338), 0xffffffff, POWER9
, 0, {0}},
6503 {"mfmq", XSPR(31,339, 0), XSPR_MASK
, M601
, 0, {RT
}},
6504 {"mfxer", XSPR(31,339, 1), XSPR_MASK
, COM
, 0, {RT
}},
6505 {"mfrtcu", XSPR(31,339, 4), XSPR_MASK
, COM
, TITAN
, {RT
}},
6506 {"mfrtcl", XSPR(31,339, 5), XSPR_MASK
, COM
, TITAN
, {RT
}},
6507 {"mfdec", XSPR(31,339, 6), XSPR_MASK
, MFDEC1
, 0, {RT
}},
6508 {"mflr", XSPR(31,339, 8), XSPR_MASK
, COM
, 0, {RT
}},
6509 {"mfctr", XSPR(31,339, 9), XSPR_MASK
, COM
, 0, {RT
}},
6510 {"mfdscr", XSPR(31,339, 17), XSPR_MASK
, POWER6
, 0, {RT
}},
6511 {"mftid", XSPR(31,339, 17), XSPR_MASK
, POWER
, 0, {RT
}},
6512 {"mfdsisr", XSPR(31,339, 18), XSPR_MASK
, COM
, TITAN
, {RT
}},
6513 {"mfdar", XSPR(31,339, 19), XSPR_MASK
, COM
, TITAN
, {RT
}},
6514 {"mfdec", XSPR(31,339, 22), XSPR_MASK
, MFDEC2
, MFDEC1
, {RT
}},
6515 {"mfsdr0", XSPR(31,339, 24), XSPR_MASK
, POWER
, 0, {RT
}},
6516 {"mfsdr1", XSPR(31,339, 25), XSPR_MASK
, COM
, TITAN
, {RT
}},
6517 {"mfsrr0", XSPR(31,339, 26), XSPR_MASK
, COM
, 0, {RT
}},
6518 {"mfsrr1", XSPR(31,339, 27), XSPR_MASK
, COM
, 0, {RT
}},
6519 {"mfcfar", XSPR(31,339, 28), XSPR_MASK
, POWER6
, 0, {RT
}},
6520 {"mfpid", XSPR(31,339, 48), XSPR_MASK
, BOOKE
, 0, {RT
}},
6521 {"mfcsrr0", XSPR(31,339, 58), XSPR_MASK
, BOOKE
, 0, {RT
}},
6522 {"mfcsrr1", XSPR(31,339, 59), XSPR_MASK
, BOOKE
, 0, {RT
}},
6523 {"mfdear", XSPR(31,339, 61), XSPR_MASK
, BOOKE
, 0, {RT
}},
6524 {"mfesr", XSPR(31,339, 62), XSPR_MASK
, BOOKE
, 0, {RT
}},
6525 {"mfivpr", XSPR(31,339, 63), XSPR_MASK
, BOOKE
, 0, {RT
}},
6526 {"mfctrl", XSPR(31,339,136), XSPR_MASK
, POWER4
, 0, {RT
}},
6527 {"mfcmpa", XSPR(31,339,144), XSPR_MASK
, PPC860
, 0, {RT
}},
6528 {"mfcmpb", XSPR(31,339,145), XSPR_MASK
, PPC860
, 0, {RT
}},
6529 {"mfcmpc", XSPR(31,339,146), XSPR_MASK
, PPC860
, 0, {RT
}},
6530 {"mfcmpd", XSPR(31,339,147), XSPR_MASK
, PPC860
, 0, {RT
}},
6531 {"mficr", XSPR(31,339,148), XSPR_MASK
, PPC860
, 0, {RT
}},
6532 {"mfder", XSPR(31,339,149), XSPR_MASK
, PPC860
, 0, {RT
}},
6533 {"mfcounta", XSPR(31,339,150), XSPR_MASK
, PPC860
, 0, {RT
}},
6534 {"mfcountb", XSPR(31,339,151), XSPR_MASK
, PPC860
, 0, {RT
}},
6535 {"mfcmpe", XSPR(31,339,152), XSPR_MASK
, PPC860
, 0, {RT
}},
6536 {"mfcmpf", XSPR(31,339,153), XSPR_MASK
, PPC860
, 0, {RT
}},
6537 {"mfcmpg", XSPR(31,339,154), XSPR_MASK
, PPC860
, 0, {RT
}},
6538 {"mfcmph", XSPR(31,339,155), XSPR_MASK
, PPC860
, 0, {RT
}},
6539 {"mflctrl1", XSPR(31,339,156), XSPR_MASK
, PPC860
, 0, {RT
}},
6540 {"mflctrl2", XSPR(31,339,157), XSPR_MASK
, PPC860
, 0, {RT
}},
6541 {"mfictrl", XSPR(31,339,158), XSPR_MASK
, PPC860
, 0, {RT
}},
6542 {"mfbar", XSPR(31,339,159), XSPR_MASK
, PPC860
, 0, {RT
}},
6543 {"mfvrsave", XSPR(31,339,256), XSPR_MASK
, PPCVEC
, 0, {RT
}},
6544 {"mfusprg0", XSPR(31,339,256), XSPR_MASK
, BOOKE
, 0, {RT
}},
6545 {"mfsprg", XSPR(31,339,256), XSPRG_MASK
, PPC
, 0, {RT
, SPRG
}},
6546 {"mfsprg4", XSPR(31,339,260), XSPR_MASK
, PPC405
|BOOKE
, 0, {RT
}},
6547 {"mfsprg5", XSPR(31,339,261), XSPR_MASK
, PPC405
|BOOKE
, 0, {RT
}},
6548 {"mfsprg6", XSPR(31,339,262), XSPR_MASK
, PPC405
|BOOKE
, 0, {RT
}},
6549 {"mfsprg7", XSPR(31,339,263), XSPR_MASK
, PPC405
|BOOKE
, 0, {RT
}},
6550 {"mftbu", XSPR(31,339,269), XSPR_MASK
, POWER4
|BOOKE
, 0, {RT
}},
6551 {"mftb", X(31,339), X_MASK
, POWER4
|BOOKE
, 0, {RT
, TBR
}},
6552 {"mftbl", XSPR(31,339,268), XSPR_MASK
, POWER4
|BOOKE
, 0, {RT
}},
6553 {"mfsprg0", XSPR(31,339,272), XSPR_MASK
, PPC
, 0, {RT
}},
6554 {"mfsprg1", XSPR(31,339,273), XSPR_MASK
, PPC
, 0, {RT
}},
6555 {"mfsprg2", XSPR(31,339,274), XSPR_MASK
, PPC
, 0, {RT
}},
6556 {"mfsprg3", XSPR(31,339,275), XSPR_MASK
, PPC
, 0, {RT
}},
6557 {"mfasr", XSPR(31,339,280), XSPR_MASK
, PPC64
, 0, {RT
}},
6558 {"mfear", XSPR(31,339,282), XSPR_MASK
, PPC
, TITAN
, {RT
}},
6559 {"mfpir", XSPR(31,339,286), XSPR_MASK
, BOOKE
, 0, {RT
}},
6560 {"mfpvr", XSPR(31,339,287), XSPR_MASK
, PPC
, 0, {RT
}},
6561 {"mfdbsr", XSPR(31,339,304), XSPR_MASK
, BOOKE
, 0, {RT
}},
6562 {"mfdbcr0", XSPR(31,339,308), XSPR_MASK
, BOOKE
, 0, {RT
}},
6563 {"mfdbcr1", XSPR(31,339,309), XSPR_MASK
, BOOKE
, 0, {RT
}},
6564 {"mfdbcr2", XSPR(31,339,310), XSPR_MASK
, BOOKE
, 0, {RT
}},
6565 {"mfiac1", XSPR(31,339,312), XSPR_MASK
, BOOKE
, 0, {RT
}},
6566 {"mfiac2", XSPR(31,339,313), XSPR_MASK
, BOOKE
, 0, {RT
}},
6567 {"mfiac3", XSPR(31,339,314), XSPR_MASK
, BOOKE
, 0, {RT
}},
6568 {"mfiac4", XSPR(31,339,315), XSPR_MASK
, BOOKE
, 0, {RT
}},
6569 {"mfdac1", XSPR(31,339,316), XSPR_MASK
, BOOKE
, 0, {RT
}},
6570 {"mfdac2", XSPR(31,339,317), XSPR_MASK
, BOOKE
, 0, {RT
}},
6571 {"mfdvc1", XSPR(31,339,318), XSPR_MASK
, BOOKE
, 0, {RT
}},
6572 {"mfdvc2", XSPR(31,339,319), XSPR_MASK
, BOOKE
, 0, {RT
}},
6573 {"mftsr", XSPR(31,339,336), XSPR_MASK
, BOOKE
, 0, {RT
}},
6574 {"mftcr", XSPR(31,339,340), XSPR_MASK
, BOOKE
, 0, {RT
}},
6575 {"mfivor0", XSPR(31,339,400), XSPR_MASK
, BOOKE
, 0, {RT
}},
6576 {"mfivor1", XSPR(31,339,401), XSPR_MASK
, BOOKE
, 0, {RT
}},
6577 {"mfivor2", XSPR(31,339,402), XSPR_MASK
, BOOKE
, 0, {RT
}},
6578 {"mfivor3", XSPR(31,339,403), XSPR_MASK
, BOOKE
, 0, {RT
}},
6579 {"mfivor4", XSPR(31,339,404), XSPR_MASK
, BOOKE
, 0, {RT
}},
6580 {"mfivor5", XSPR(31,339,405), XSPR_MASK
, BOOKE
, 0, {RT
}},
6581 {"mfivor6", XSPR(31,339,406), XSPR_MASK
, BOOKE
, 0, {RT
}},
6582 {"mfivor7", XSPR(31,339,407), XSPR_MASK
, BOOKE
, 0, {RT
}},
6583 {"mfivor8", XSPR(31,339,408), XSPR_MASK
, BOOKE
, 0, {RT
}},
6584 {"mfivor9", XSPR(31,339,409), XSPR_MASK
, BOOKE
, 0, {RT
}},
6585 {"mfivor10", XSPR(31,339,410), XSPR_MASK
, BOOKE
, 0, {RT
}},
6586 {"mfivor11", XSPR(31,339,411), XSPR_MASK
, BOOKE
, 0, {RT
}},
6587 {"mfivor12", XSPR(31,339,412), XSPR_MASK
, BOOKE
, 0, {RT
}},
6588 {"mfivor13", XSPR(31,339,413), XSPR_MASK
, BOOKE
, 0, {RT
}},
6589 {"mfivor14", XSPR(31,339,414), XSPR_MASK
, BOOKE
, 0, {RT
}},
6590 {"mfivor15", XSPR(31,339,415), XSPR_MASK
, BOOKE
, 0, {RT
}},
6591 {"mfspefscr", XSPR(31,339,512), XSPR_MASK
, PPCSPE
, 0, {RT
}},
6592 {"mfbbear", XSPR(31,339,513), XSPR_MASK
, PPCBRLK
, 0, {RT
}},
6593 {"mfbbtar", XSPR(31,339,514), XSPR_MASK
, PPCBRLK
, 0, {RT
}},
6594 {"mfivor32", XSPR(31,339,528), XSPR_MASK
, PPCSPE
|E6500
, 0, {RT
}},
6595 {"mfivor33", XSPR(31,339,529), XSPR_MASK
, PPCSPE
|E6500
, 0, {RT
}},
6596 {"mfivor34", XSPR(31,339,530), XSPR_MASK
, PPCSPE
, 0, {RT
}},
6597 {"mfivor35", XSPR(31,339,531), XSPR_MASK
, PPCPMR
, 0, {RT
}},
6598 {"mfibatu", XSPR(31,339,528), XSPRBAT_MASK
, PPC
, TITAN
, {RT
, SPRBAT
}},
6599 {"mfibatl", XSPR(31,339,529), XSPRBAT_MASK
, PPC
, TITAN
, {RT
, SPRBAT
}},
6600 {"mfdbatu", XSPR(31,339,536), XSPRBAT_MASK
, PPC
, TITAN
, {RT
, SPRBAT
}},
6601 {"mfdbatl", XSPR(31,339,537), XSPRBAT_MASK
, PPC
, TITAN
, {RT
, SPRBAT
}},
6602 {"mfic_cst", XSPR(31,339,560), XSPR_MASK
, PPC860
, 0, {RT
}},
6603 {"mfic_adr", XSPR(31,339,561), XSPR_MASK
, PPC860
, 0, {RT
}},
6604 {"mfic_dat", XSPR(31,339,562), XSPR_MASK
, PPC860
, 0, {RT
}},
6605 {"mfdc_cst", XSPR(31,339,568), XSPR_MASK
, PPC860
, 0, {RT
}},
6606 {"mfdc_adr", XSPR(31,339,569), XSPR_MASK
, PPC860
, 0, {RT
}},
6607 {"mfdc_dat", XSPR(31,339,570), XSPR_MASK
, PPC860
, 0, {RT
}},
6608 {"mfmcsrr0", XSPR(31,339,570), XSPR_MASK
, PPCRFMCI
, 0, {RT
}},
6609 {"mfmcsrr1", XSPR(31,339,571), XSPR_MASK
, PPCRFMCI
, 0, {RT
}},
6610 {"mfmcsr", XSPR(31,339,572), XSPR_MASK
, PPCRFMCI
, 0, {RT
}},
6611 {"mfmcar", XSPR(31,339,573), XSPR_MASK
, PPCRFMCI
, TITAN
, {RT
}},
6612 {"mfdpdr", XSPR(31,339,630), XSPR_MASK
, PPC860
, 0, {RT
}},
6613 {"mfdpir", XSPR(31,339,631), XSPR_MASK
, PPC860
, 0, {RT
}},
6614 {"mfimmr", XSPR(31,339,638), XSPR_MASK
, PPC860
, 0, {RT
}},
6615 {"mfupmc1", XSPR(31,339,771), XSPR_MASK
, POWER9
, 0, {RT
}},
6616 {"mfpmc1", XSPR(31,339,771), XSPR_MASK
, POWER9
, 0, {RT
}},
6617 {"mfupmc2", XSPR(31,339,772), XSPR_MASK
, POWER9
, 0, {RT
}},
6618 {"mfpmc2", XSPR(31,339,772), XSPR_MASK
, POWER9
, 0, {RT
}},
6619 {"mfupmc3", XSPR(31,339,773), XSPR_MASK
, POWER9
, 0, {RT
}},
6620 {"mfpmc3", XSPR(31,339,773), XSPR_MASK
, POWER9
, 0, {RT
}},
6621 {"mfupmc4", XSPR(31,339,774), XSPR_MASK
, POWER9
, 0, {RT
}},
6622 {"mfpmc4", XSPR(31,339,774), XSPR_MASK
, POWER9
, 0, {RT
}},
6623 {"mfupmc5", XSPR(31,339,775), XSPR_MASK
, POWER9
, 0, {RT
}},
6624 {"mfpmc5", XSPR(31,339,775), XSPR_MASK
, POWER9
, 0, {RT
}},
6625 {"mfupmc6", XSPR(31,339,776), XSPR_MASK
, POWER9
, 0, {RT
}},
6626 {"mfpmc6", XSPR(31,339,776), XSPR_MASK
, POWER9
, 0, {RT
}},
6627 {"mfmi_ctr", XSPR(31,339,784), XSPR_MASK
, PPC860
, 0, {RT
}},
6628 {"mfmi_ap", XSPR(31,339,786), XSPR_MASK
, PPC860
, 0, {RT
}},
6629 {"mfmi_epn", XSPR(31,339,787), XSPR_MASK
, PPC860
, 0, {RT
}},
6630 {"mfmi_twc", XSPR(31,339,789), XSPR_MASK
, PPC860
, 0, {RT
}},
6631 {"mfmi_rpn", XSPR(31,339,790), XSPR_MASK
, PPC860
, 0, {RT
}},
6632 {"mfmd_ctr", XSPR(31,339,792), XSPR_MASK
, PPC860
, 0, {RT
}},
6633 {"mfm_casid", XSPR(31,339,793), XSPR_MASK
, PPC860
, 0, {RT
}},
6634 {"mfmd_ap", XSPR(31,339,794), XSPR_MASK
, PPC860
, 0, {RT
}},
6635 {"mfmd_epn", XSPR(31,339,795), XSPR_MASK
, PPC860
, 0, {RT
}},
6636 {"mfmd_twb", XSPR(31,339,796), XSPR_MASK
, PPC860
, 0, {RT
}},
6637 {"mfmd_twc", XSPR(31,339,797), XSPR_MASK
, PPC860
, 0, {RT
}},
6638 {"mfmd_rpn", XSPR(31,339,798), XSPR_MASK
, PPC860
, 0, {RT
}},
6639 {"mfm_tw", XSPR(31,339,799), XSPR_MASK
, PPC860
, 0, {RT
}},
6640 {"mfmi_dbcam", XSPR(31,339,816), XSPR_MASK
, PPC860
, 0, {RT
}},
6641 {"mfmi_dbram0", XSPR(31,339,817), XSPR_MASK
, PPC860
, 0, {RT
}},
6642 {"mfmi_dbram1", XSPR(31,339,818), XSPR_MASK
, PPC860
, 0, {RT
}},
6643 {"mfmd_dbcam", XSPR(31,339,824), XSPR_MASK
, PPC860
, 0, {RT
}},
6644 {"mfmd_dbram0", XSPR(31,339,825), XSPR_MASK
, PPC860
, 0, {RT
}},
6645 {"mfmd_dbram1", XSPR(31,339,826), XSPR_MASK
, PPC860
, 0, {RT
}},
6646 {"mfivndx", XSPR(31,339,880), XSPR_MASK
, TITAN
, 0, {RT
}},
6647 {"mfdvndx", XSPR(31,339,881), XSPR_MASK
, TITAN
, 0, {RT
}},
6648 {"mfivlim", XSPR(31,339,882), XSPR_MASK
, TITAN
, 0, {RT
}},
6649 {"mfdvlim", XSPR(31,339,883), XSPR_MASK
, TITAN
, 0, {RT
}},
6650 {"mfclcsr", XSPR(31,339,884), XSPR_MASK
, TITAN
, 0, {RT
}},
6651 {"mfccr1", XSPR(31,339,888), XSPR_MASK
, TITAN
, 0, {RT
}},
6652 {"mfppr", XSPR(31,339,896), XSPR_MASK
, POWER7
, 0, {RT
}},
6653 {"mfppr32", XSPR(31,339,898), XSPR_MASK
, POWER7
, 0, {RT
}},
6654 {"mfgqr", XSPR(31,339,912), XSPRGQR_MASK
, PPCPS
, 0, {RT
, SPRGQR
}},
6655 {"mfhid2", XSPR(31,339,920), XSPR_MASK
, GEKKO
, 0, {RT
}},
6656 {"mfwpar", XSPR(31,339,921), XSPR_MASK
, GEKKO
, 0, {RT
}},
6657 {"mfdmau", XSPR(31,339,922), XSPR_MASK
, GEKKO
, 0, {RT
}},
6658 {"mfdmal", XSPR(31,339,923), XSPR_MASK
, GEKKO
, 0, {RT
}},
6659 {"mfrstcfg", XSPR(31,339,923), XSPR_MASK
, TITAN
, 0, {RT
}},
6660 {"mfdcdbtrl", XSPR(31,339,924), XSPR_MASK
, TITAN
, 0, {RT
}},
6661 {"mfdcdbtrh", XSPR(31,339,925), XSPR_MASK
, TITAN
, 0, {RT
}},
6662 {"mficdbtr", XSPR(31,339,927), XSPR_MASK
, TITAN
, 0, {RT
}},
6663 {"mfummcr0", XSPR(31,339,936), XSPR_MASK
, PPC750
, 0, {RT
}},
6664 {"mfupmc1", XSPR(31,339,937), XSPR_MASK
, PPC750
, 0, {RT
}},
6665 {"mfupmc2", XSPR(31,339,938), XSPR_MASK
, PPC750
, 0, {RT
}},
6666 {"mfusia", XSPR(31,339,939), XSPR_MASK
, PPC750
, 0, {RT
}},
6667 {"mfummcr1", XSPR(31,339,940), XSPR_MASK
, PPC750
, 0, {RT
}},
6668 {"mfupmc3", XSPR(31,339,941), XSPR_MASK
, PPC750
, 0, {RT
}},
6669 {"mfupmc4", XSPR(31,339,942), XSPR_MASK
, PPC750
, 0, {RT
}},
6670 {"mfzpr", XSPR(31,339,944), XSPR_MASK
, PPC403
, 0, {RT
}},
6671 {"mfpid", XSPR(31,339,945), XSPR_MASK
, PPC403
, 0, {RT
}},
6672 {"mfmmucr", XSPR(31,339,946), XSPR_MASK
, TITAN
, 0, {RT
}},
6673 {"mfccr0", XSPR(31,339,947), XSPR_MASK
, PPC405
|TITAN
, 0, {RT
}},
6674 {"mfiac3", XSPR(31,339,948), XSPR_MASK
, PPC405
, 0, {RT
}},
6675 {"mfiac4", XSPR(31,339,949), XSPR_MASK
, PPC405
, 0, {RT
}},
6676 {"mfdvc1", XSPR(31,339,950), XSPR_MASK
, PPC405
, 0, {RT
}},
6677 {"mfdvc2", XSPR(31,339,951), XSPR_MASK
, PPC405
, 0, {RT
}},
6678 {"mfmmcr0", XSPR(31,339,952), XSPR_MASK
, PPC750
, 0, {RT
}},
6679 {"mfpmc1", XSPR(31,339,953), XSPR_MASK
, PPC750
, 0, {RT
}},
6680 {"mfsgr", XSPR(31,339,953), XSPR_MASK
, PPC403
, 0, {RT
}},
6681 {"mfdcwr", XSPR(31,339,954), XSPR_MASK
, PPC403
, 0, {RT
}},
6682 {"mfpmc2", XSPR(31,339,954), XSPR_MASK
, PPC750
, 0, {RT
}},
6683 {"mfsia", XSPR(31,339,955), XSPR_MASK
, PPC750
, 0, {RT
}},
6684 {"mfsler", XSPR(31,339,955), XSPR_MASK
, PPC405
, 0, {RT
}},
6685 {"mfmmcr1", XSPR(31,339,956), XSPR_MASK
, PPC750
, 0, {RT
}},
6686 {"mfsu0r", XSPR(31,339,956), XSPR_MASK
, PPC405
, 0, {RT
}},
6687 {"mfdbcr1", XSPR(31,339,957), XSPR_MASK
, PPC405
, 0, {RT
}},
6688 {"mfpmc3", XSPR(31,339,957), XSPR_MASK
, PPC750
, 0, {RT
}},
6689 {"mfpmc4", XSPR(31,339,958), XSPR_MASK
, PPC750
, 0, {RT
}},
6690 {"mficdbdr", XSPR(31,339,979), XSPR_MASK
, PPC403
|TITAN
, 0, {RT
}},
6691 {"mfesr", XSPR(31,339,980), XSPR_MASK
, PPC403
, 0, {RT
}},
6692 {"mfdear", XSPR(31,339,981), XSPR_MASK
, PPC403
, 0, {RT
}},
6693 {"mfevpr", XSPR(31,339,982), XSPR_MASK
, PPC403
, 0, {RT
}},
6694 {"mfcdbcr", XSPR(31,339,983), XSPR_MASK
, PPC403
, 0, {RT
}},
6695 {"mftsr", XSPR(31,339,984), XSPR_MASK
, PPC403
, 0, {RT
}},
6696 {"mftcr", XSPR(31,339,986), XSPR_MASK
, PPC403
, 0, {RT
}},
6697 {"mfpit", XSPR(31,339,987), XSPR_MASK
, PPC403
, 0, {RT
}},
6698 {"mftbhi", XSPR(31,339,988), XSPR_MASK
, PPC403
, 0, {RT
}},
6699 {"mftblo", XSPR(31,339,989), XSPR_MASK
, PPC403
, 0, {RT
}},
6700 {"mfsrr2", XSPR(31,339,990), XSPR_MASK
, PPC403
, 0, {RT
}},
6701 {"mfsrr3", XSPR(31,339,991), XSPR_MASK
, PPC403
, 0, {RT
}},
6702 {"mfdbsr", XSPR(31,339,1008), XSPR_MASK
, PPC403
, 0, {RT
}},
6703 {"mfhid0", XSPR(31,339,1008), XSPR_MASK
, GEKKO
, 0, {RT
}},
6704 {"mfhid1", XSPR(31,339,1009), XSPR_MASK
, GEKKO
, 0, {RT
}},
6705 {"mfdbcr0", XSPR(31,339,1010), XSPR_MASK
, PPC405
, 0, {RT
}},
6706 {"mfiabr", XSPR(31,339,1010), XSPR_MASK
, GEKKO
, 0, {RT
}},
6707 {"mfhid4", XSPR(31,339,1011), XSPR_MASK
, BROADWAY
, 0, {RT
}},
6708 {"mfdbdr", XSPR(31,339,1011), XSPR_MASK
, TITAN
, 0, {RS
}},
6709 {"mfiac1", XSPR(31,339,1012), XSPR_MASK
, PPC403
, 0, {RT
}},
6710 {"mfiac2", XSPR(31,339,1013), XSPR_MASK
, PPC403
, 0, {RT
}},
6711 {"mfdabr", XSPR(31,339,1013), XSPR_MASK
, PPC750
, 0, {RT
}},
6712 {"mfdac1", XSPR(31,339,1014), XSPR_MASK
, PPC403
, 0, {RT
}},
6713 {"mfdac2", XSPR(31,339,1015), XSPR_MASK
, PPC403
, 0, {RT
}},
6714 {"mfl2cr", XSPR(31,339,1017), XSPR_MASK
, PPC750
, 0, {RT
}},
6715 {"mfdccr", XSPR(31,339,1018), XSPR_MASK
, PPC403
, 0, {RT
}},
6716 {"mficcr", XSPR(31,339,1019), XSPR_MASK
, PPC403
, 0, {RT
}},
6717 {"mfictc", XSPR(31,339,1019), XSPR_MASK
, PPC750
, 0, {RT
}},
6718 {"mfpbl1", XSPR(31,339,1020), XSPR_MASK
, PPC403
, 0, {RT
}},
6719 {"mfthrm1", XSPR(31,339,1020), XSPR_MASK
, PPC750
, 0, {RT
}},
6720 {"mfpbu1", XSPR(31,339,1021), XSPR_MASK
, PPC403
, 0, {RT
}},
6721 {"mfthrm2", XSPR(31,339,1021), XSPR_MASK
, PPC750
, 0, {RT
}},
6722 {"mfpbl2", XSPR(31,339,1022), XSPR_MASK
, PPC403
, 0, {RT
}},
6723 {"mfthrm3", XSPR(31,339,1022), XSPR_MASK
, PPC750
, 0, {RT
}},
6724 {"mfpbu2", XSPR(31,339,1023), XSPR_MASK
, PPC403
, 0, {RT
}},
6725 {"mfspr", X(31,339), X_MASK
, COM
, 0, {RT
, SPR
}},
6727 {"lwax", X(31,341), X_MASK
, PPC64
, 0, {RT
, RA0
, RB
}},
6729 {"dst", XDSS(31,342,0), XDSS_MASK
, PPCVEC
, 0, {RA
, RB
, STRM
}},
6731 {"lhax", X(31,343), X_MASK
, COM
, 0, {RT
, RA0
, RB
}},
6733 {"lvxl", X(31,359), X_MASK
, PPCVEC
, 0, {VD
, RA0
, RB
}},
6735 {"abs", XO(31,360,0,0), XORB_MASK
, M601
, 0, {RT
, RA
}},
6736 {"abs.", XO(31,360,0,1), XORB_MASK
, M601
, 0, {RT
, RA
}},
6738 {"divs", XO(31,363,0,0), XO_MASK
, M601
, 0, {RT
, RA
, RB
}},
6739 {"divs.", XO(31,363,0,1), XO_MASK
, M601
, 0, {RT
, RA
, RB
}},
6741 {"lxvwsx", X(31,364), XX1_MASK
, PPCVSX3
, 0, {XT6
, RA0
, RB
}},
6743 {"tlbia", X(31,370), 0xffffffff, PPC
, E500
|TITAN
, {0}},
6745 {"mftbu", XSPR(31,371,269), XSPR_MASK
, PPC
, NO371
|POWER4
, {RT
}},
6746 {"mftb", X(31,371), X_MASK
, PPC
, NO371
|POWER4
, {RT
, TBR
}},
6747 {"mftbl", XSPR(31,371,268), XSPR_MASK
, PPC
, NO371
|POWER4
, {RT
}},
6749 {"lwaux", X(31,373), X_MASK
, PPC64
, 0, {RT
, RAL
, RB
}},
6751 {"dstst", XDSS(31,374,0), XDSS_MASK
, PPCVEC
, 0, {RA
, RB
, STRM
}},
6753 {"lhaux", X(31,375), X_MASK
, COM
, 0, {RT
, RAL
, RB
}},
6755 {"popcntw", X(31,378), XRB_MASK
, POWER7
|PPCA2
, 0, {RA
, RS
}},
6757 {"mtdcrx", X(31,387), X_MASK
, BOOKE
|PPCA2
|PPC476
, TITAN
, {RA
, RS
}},
6758 {"mtdcrx.", XRC(31,387,1), X_MASK
, PPCA2
, 0, {RA
, RS
}},
6760 {"stvexbx", X(31,389), X_MASK
, E6500
, 0, {VS
, RA0
, RB
}},
6762 {"dcblc", X(31,390), X_MASK
, PPCCHLK
|PPC476
|TITAN
, 0, {CT
, RA0
, RB
}},
6763 {"stdfcmx", APU(31,391,0), APU_MASK
, PPC405
, 0, {FCRT
, RA
, RB
}},
6765 {"divdeu", XO(31,393,0,0), XO_MASK
, POWER7
|PPCA2
, 0, {RT
, RA
, RB
}},
6766 {"divdeu.", XO(31,393,0,1), XO_MASK
, POWER7
|PPCA2
, 0, {RT
, RA
, RB
}},
6767 {"divweu", XO(31,395,0,0), XO_MASK
, POWER7
|PPCA2
, 0, {RT
, RA
, RB
}},
6768 {"divweu.", XO(31,395,0,1), XO_MASK
, POWER7
|PPCA2
, 0, {RT
, RA
, RB
}},
6770 {"stxvx", X(31,396), XX1_MASK
, PPCVSX3
, 0, {XS6
, RA0
, RB
}},
6771 {"stxvl", X(31,397), XX1_MASK
, PPCVSX3
, 0, {XS6
, RA0
, RB
}},
6773 {"dcblce", X(31,398), X_MASK
, PPCCHLK
, E500MC
, {CT
, RA
, RB
}},
6775 {"slbmte", X(31,402), XRA_MASK
, PPC64
, 0, {RS
, RB
}},
6777 {"mtvsrws", X(31,403), XX1RB_MASK
, PPCVSX3
, 0, {XT6
, RA
}},
6779 {"pbt.", XRC(31,404,1), X_MASK
, POWER8
, 0, {RS
, RA0
, RB
}},
6781 {"icswx", XRC(31,406,0), X_MASK
, POWER7
|PPCA2
, 0, {RS
, RA
, RB
}},
6782 {"icswx.", XRC(31,406,1), X_MASK
, POWER7
|PPCA2
, 0, {RS
, RA
, RB
}},
6784 {"sthx", X(31,407), X_MASK
, COM
, 0, {RS
, RA0
, RB
}},
6786 {"orc", XRC(31,412,0), X_MASK
, COM
, 0, {RA
, RS
, RB
}},
6787 {"orc.", XRC(31,412,1), X_MASK
, COM
, 0, {RA
, RS
, RB
}},
6789 {"sthepx", X(31,415), X_MASK
, E500MC
|PPCA2
, 0, {RS
, RA0
, RB
}},
6791 {"mtdcrux", X(31,419), X_MASK
, PPC464
|PPC476
, 0, {RA
, RS
}},
6793 {"stvexhx", X(31,421), X_MASK
, E6500
, 0, {VS
, RA0
, RB
}},
6795 {"dcblq.", XRC(31,422,1), X_MASK
, E6500
, 0, {CT
, RA0
, RB
}},
6797 {"divde", XO(31,425,0,0), XO_MASK
, POWER7
|PPCA2
, 0, {RT
, RA
, RB
}},
6798 {"divde.", XO(31,425,0,1), XO_MASK
, POWER7
|PPCA2
, 0, {RT
, RA
, RB
}},
6799 {"divwe", XO(31,427,0,0), XO_MASK
, POWER7
|PPCA2
, 0, {RT
, RA
, RB
}},
6800 {"divwe.", XO(31,427,0,1), XO_MASK
, POWER7
|PPCA2
, 0, {RT
, RA
, RB
}},
6802 {"stxvll", X(31,429), XX1_MASK
, PPCVSX3
, 0, {XS6
, RA0
, RB
}},
6804 {"clrbhrb", X(31,430), 0xffffffff, POWER8
, 0, {0}},
6806 {"slbie", X(31,434), XRTRA_MASK
, PPC64
, 0, {RB
}},
6808 {"mtvsrdd", X(31,435), XX1_MASK
, PPCVSX3
, 0, {XT6
, RA0
, RB
}},
6810 {"ecowx", X(31,438), X_MASK
, PPC
, E500
|TITAN
, {RT
, RA0
, RB
}},
6812 {"sthux", X(31,439), X_MASK
, COM
, 0, {RS
, RAS
, RB
}},
6814 {"mdors", 0x7f9ce378, 0xffffffff, E500MC
, 0, {0}},
6816 {"miso", 0x7f5ad378, 0xffffffff, E6500
, 0, {0}},
6818 /* The "yield", "mdoio" and "mdoom" instructions are extended mnemonics for
6819 "or rX,rX,rX", with rX being r27, r29 and r30 respectively. */
6820 {"yield", 0x7f7bdb78, 0xffffffff, POWER7
, 0, {0}},
6821 {"mdoio", 0x7fbdeb78, 0xffffffff, POWER7
, 0, {0}},
6822 {"mdoom", 0x7fdef378, 0xffffffff, POWER7
, 0, {0}},
6823 {"mr", XRC(31,444,0), X_MASK
, COM
, 0, {RA
, RSB
}},
6824 {"or", XRC(31,444,0), X_MASK
, COM
, 0, {RA
, RS
, RB
}},
6825 {"mr.", XRC(31,444,1), X_MASK
, COM
, 0, {RA
, RSB
}},
6826 {"or.", XRC(31,444,1), X_MASK
, COM
, 0, {RA
, RS
, RB
}},
6828 {"mtexisr", XSPR(31,451, 64), XSPR_MASK
, PPC403
, 0, {RS
}},
6829 {"mtexier", XSPR(31,451, 66), XSPR_MASK
, PPC403
, 0, {RS
}},
6830 {"mtbr0", XSPR(31,451,128), XSPR_MASK
, PPC403
, 0, {RS
}},
6831 {"mtbr1", XSPR(31,451,129), XSPR_MASK
, PPC403
, 0, {RS
}},
6832 {"mtbr2", XSPR(31,451,130), XSPR_MASK
, PPC403
, 0, {RS
}},
6833 {"mtbr3", XSPR(31,451,131), XSPR_MASK
, PPC403
, 0, {RS
}},
6834 {"mtbr4", XSPR(31,451,132), XSPR_MASK
, PPC403
, 0, {RS
}},
6835 {"mtbr5", XSPR(31,451,133), XSPR_MASK
, PPC403
, 0, {RS
}},
6836 {"mtbr6", XSPR(31,451,134), XSPR_MASK
, PPC403
, 0, {RS
}},
6837 {"mtbr7", XSPR(31,451,135), XSPR_MASK
, PPC403
, 0, {RS
}},
6838 {"mtbear", XSPR(31,451,144), XSPR_MASK
, PPC403
, 0, {RS
}},
6839 {"mtbesr", XSPR(31,451,145), XSPR_MASK
, PPC403
, 0, {RS
}},
6840 {"mtiocr", XSPR(31,451,160), XSPR_MASK
, PPC403
, 0, {RS
}},
6841 {"mtdmacr0", XSPR(31,451,192), XSPR_MASK
, PPC403
, 0, {RS
}},
6842 {"mtdmact0", XSPR(31,451,193), XSPR_MASK
, PPC403
, 0, {RS
}},
6843 {"mtdmada0", XSPR(31,451,194), XSPR_MASK
, PPC403
, 0, {RS
}},
6844 {"mtdmasa0", XSPR(31,451,195), XSPR_MASK
, PPC403
, 0, {RS
}},
6845 {"mtdmacc0", XSPR(31,451,196), XSPR_MASK
, PPC403
, 0, {RS
}},
6846 {"mtdmacr1", XSPR(31,451,200), XSPR_MASK
, PPC403
, 0, {RS
}},
6847 {"mtdmact1", XSPR(31,451,201), XSPR_MASK
, PPC403
, 0, {RS
}},
6848 {"mtdmada1", XSPR(31,451,202), XSPR_MASK
, PPC403
, 0, {RS
}},
6849 {"mtdmasa1", XSPR(31,451,203), XSPR_MASK
, PPC403
, 0, {RS
}},
6850 {"mtdmacc1", XSPR(31,451,204), XSPR_MASK
, PPC403
, 0, {RS
}},
6851 {"mtdmacr2", XSPR(31,451,208), XSPR_MASK
, PPC403
, 0, {RS
}},
6852 {"mtdmact2", XSPR(31,451,209), XSPR_MASK
, PPC403
, 0, {RS
}},
6853 {"mtdmada2", XSPR(31,451,210), XSPR_MASK
, PPC403
, 0, {RS
}},
6854 {"mtdmasa2", XSPR(31,451,211), XSPR_MASK
, PPC403
, 0, {RS
}},
6855 {"mtdmacc2", XSPR(31,451,212), XSPR_MASK
, PPC403
, 0, {RS
}},
6856 {"mtdmacr3", XSPR(31,451,216), XSPR_MASK
, PPC403
, 0, {RS
}},
6857 {"mtdmact3", XSPR(31,451,217), XSPR_MASK
, PPC403
, 0, {RS
}},
6858 {"mtdmada3", XSPR(31,451,218), XSPR_MASK
, PPC403
, 0, {RS
}},
6859 {"mtdmasa3", XSPR(31,451,219), XSPR_MASK
, PPC403
, 0, {RS
}},
6860 {"mtdmacc3", XSPR(31,451,220), XSPR_MASK
, PPC403
, 0, {RS
}},
6861 {"mtdmasr", XSPR(31,451,224), XSPR_MASK
, PPC403
, 0, {RS
}},
6862 {"mtdcr", X(31,451), X_MASK
, PPC403
|BOOKE
|PPCA2
|PPC476
, E500
|TITAN
, {SPR
, RS
}},
6863 {"mtdcr.", XRC(31,451,1), X_MASK
, PPCA2
, 0, {SPR
, RS
}},
6865 {"stvexwx", X(31,453), X_MASK
, E6500
, 0, {VS
, RA0
, RB
}},
6867 {"dccci", X(31,454), XRT_MASK
, PPC403
|PPC440
|PPC476
|TITAN
|PPCA2
, 0, {RAOPT
, RBOPT
}},
6868 {"dci", X(31,454), XRARB_MASK
, PPCA2
|PPC476
, 0, {CT
}},
6870 {"divdu", XO(31,457,0,0), XO_MASK
, PPC64
, 0, {RT
, RA
, RB
}},
6871 {"divdu.", XO(31,457,0,1), XO_MASK
, PPC64
, 0, {RT
, RA
, RB
}},
6873 {"divwu", XO(31,459,0,0), XO_MASK
, PPC
, 0, {RT
, RA
, RB
}},
6874 {"divwu.", XO(31,459,0,1), XO_MASK
, PPC
, 0, {RT
, RA
, RB
}},
6876 {"stxvpx", X(31,461), XX1_MASK
, POWER10
, 0, {XTP
, RA0
, RB
}},
6878 {"mtpmr", X(31,462), X_MASK
, PPCPMR
|PPCE300
, 0, {PMR
, RS
}},
6879 {"mttmr", X(31,494), X_MASK
, PPCTMR
, 0, {TMR
, RS
}},
6881 {"slbieg", X(31,466), XRA_MASK
, POWER9
, 0, {RS
, RB
}},
6883 {"mtmq", XSPR(31,467, 0), XSPR_MASK
, M601
, 0, {RS
}},
6884 {"mtxer", XSPR(31,467, 1), XSPR_MASK
, COM
, 0, {RS
}},
6885 {"mtlr", XSPR(31,467, 8), XSPR_MASK
, COM
, 0, {RS
}},
6886 {"mtctr", XSPR(31,467, 9), XSPR_MASK
, COM
, 0, {RS
}},
6887 {"mtdscr", XSPR(31,467, 17), XSPR_MASK
, POWER6
, 0, {RS
}},
6888 {"mttid", XSPR(31,467, 17), XSPR_MASK
, POWER
, 0, {RS
}},
6889 {"mtdsisr", XSPR(31,467, 18), XSPR_MASK
, COM
, TITAN
, {RS
}},
6890 {"mtdar", XSPR(31,467, 19), XSPR_MASK
, COM
, TITAN
, {RS
}},
6891 {"mtrtcu", XSPR(31,467, 20), XSPR_MASK
, COM
, TITAN
, {RS
}},
6892 {"mtrtcl", XSPR(31,467, 21), XSPR_MASK
, COM
, TITAN
, {RS
}},
6893 {"mtdec", XSPR(31,467, 22), XSPR_MASK
, COM
, 0, {RS
}},
6894 {"mtsdr0", XSPR(31,467, 24), XSPR_MASK
, POWER
, 0, {RS
}},
6895 {"mtsdr1", XSPR(31,467, 25), XSPR_MASK
, COM
, TITAN
, {RS
}},
6896 {"mtsrr0", XSPR(31,467, 26), XSPR_MASK
, COM
, 0, {RS
}},
6897 {"mtsrr1", XSPR(31,467, 27), XSPR_MASK
, COM
, 0, {RS
}},
6898 {"mtcfar", XSPR(31,467, 28), XSPR_MASK
, POWER6
, 0, {RS
}},
6899 {"mtpid", XSPR(31,467, 48), XSPR_MASK
, BOOKE
, 0, {RS
}},
6900 {"mtdecar", XSPR(31,467, 54), XSPR_MASK
, BOOKE
, 0, {RS
}},
6901 {"mtcsrr0", XSPR(31,467, 58), XSPR_MASK
, BOOKE
, 0, {RS
}},
6902 {"mtcsrr1", XSPR(31,467, 59), XSPR_MASK
, BOOKE
, 0, {RS
}},
6903 {"mtdear", XSPR(31,467, 61), XSPR_MASK
, BOOKE
, 0, {RS
}},
6904 {"mtesr", XSPR(31,467, 62), XSPR_MASK
, BOOKE
, 0, {RS
}},
6905 {"mtivpr", XSPR(31,467, 63), XSPR_MASK
, BOOKE
, 0, {RS
}},
6906 {"mtcmpa", XSPR(31,467,144), XSPR_MASK
, PPC860
, 0, {RS
}},
6907 {"mtcmpb", XSPR(31,467,145), XSPR_MASK
, PPC860
, 0, {RS
}},
6908 {"mtcmpc", XSPR(31,467,146), XSPR_MASK
, PPC860
, 0, {RS
}},
6909 {"mtcmpd", XSPR(31,467,147), XSPR_MASK
, PPC860
, 0, {RS
}},
6910 {"mticr", XSPR(31,467,148), XSPR_MASK
, PPC860
, 0, {RS
}},
6911 {"mtder", XSPR(31,467,149), XSPR_MASK
, PPC860
, 0, {RS
}},
6912 {"mtcounta", XSPR(31,467,150), XSPR_MASK
, PPC860
, 0, {RS
}},
6913 {"mtcountb", XSPR(31,467,151), XSPR_MASK
, PPC860
, 0, {RS
}},
6914 {"mtctrl", XSPR(31,467,152), XSPR_MASK
, POWER4
, 0, {RS
}},
6915 {"mtcmpe", XSPR(31,467,152), XSPR_MASK
, PPC860
, 0, {RS
}},
6916 {"mtcmpf", XSPR(31,467,153), XSPR_MASK
, PPC860
, 0, {RS
}},
6917 {"mtcmpg", XSPR(31,467,154), XSPR_MASK
, PPC860
, 0, {RS
}},
6918 {"mtcmph", XSPR(31,467,155), XSPR_MASK
, PPC860
, 0, {RS
}},
6919 {"mtlctrl1", XSPR(31,467,156), XSPR_MASK
, PPC860
, 0, {RS
}},
6920 {"mtlctrl2", XSPR(31,467,157), XSPR_MASK
, PPC860
, 0, {RS
}},
6921 {"mtictrl", XSPR(31,467,158), XSPR_MASK
, PPC860
, 0, {RS
}},
6922 {"mtbar", XSPR(31,467,159), XSPR_MASK
, PPC860
, 0, {RS
}},
6923 {"mtvrsave", XSPR(31,467,256), XSPR_MASK
, PPCVEC
, 0, {RS
}},
6924 {"mtusprg0", XSPR(31,467,256), XSPR_MASK
, BOOKE
, 0, {RS
}},
6925 {"mtsprg", XSPR(31,467,256), XSPRG_MASK
, PPC
, 0, {SPRG
, RS
}},
6926 {"mtsprg0", XSPR(31,467,272), XSPR_MASK
, PPC
, 0, {RS
}},
6927 {"mtsprg1", XSPR(31,467,273), XSPR_MASK
, PPC
, 0, {RS
}},
6928 {"mtsprg2", XSPR(31,467,274), XSPR_MASK
, PPC
, 0, {RS
}},
6929 {"mtsprg3", XSPR(31,467,275), XSPR_MASK
, PPC
, 0, {RS
}},
6930 {"mtsprg4", XSPR(31,467,276), XSPR_MASK
, PPC405
|BOOKE
, 0, {RS
}},
6931 {"mtsprg5", XSPR(31,467,277), XSPR_MASK
, PPC405
|BOOKE
, 0, {RS
}},
6932 {"mtsprg6", XSPR(31,467,278), XSPR_MASK
, PPC405
|BOOKE
, 0, {RS
}},
6933 {"mtsprg7", XSPR(31,467,279), XSPR_MASK
, PPC405
|BOOKE
, 0, {RS
}},
6934 {"mtasr", XSPR(31,467,280), XSPR_MASK
, PPC64
, 0, {RS
}},
6935 {"mtear", XSPR(31,467,282), XSPR_MASK
, PPC
, TITAN
, {RS
}},
6936 {"mttbl", XSPR(31,467,284), XSPR_MASK
, PPC
, 0, {RS
}},
6937 {"mttbu", XSPR(31,467,285), XSPR_MASK
, PPC
, 0, {RS
}},
6938 {"mtdbsr", XSPR(31,467,304), XSPR_MASK
, BOOKE
, 0, {RS
}},
6939 {"mtdbcr0", XSPR(31,467,308), XSPR_MASK
, BOOKE
, 0, {RS
}},
6940 {"mtdbcr1", XSPR(31,467,309), XSPR_MASK
, BOOKE
, 0, {RS
}},
6941 {"mtdbcr2", XSPR(31,467,310), XSPR_MASK
, BOOKE
, 0, {RS
}},
6942 {"mtiac1", XSPR(31,467,312), XSPR_MASK
, BOOKE
, 0, {RS
}},
6943 {"mtiac2", XSPR(31,467,313), XSPR_MASK
, BOOKE
, 0, {RS
}},
6944 {"mtiac3", XSPR(31,467,314), XSPR_MASK
, BOOKE
, 0, {RS
}},
6945 {"mtiac4", XSPR(31,467,315), XSPR_MASK
, BOOKE
, 0, {RS
}},
6946 {"mtdac1", XSPR(31,467,316), XSPR_MASK
, BOOKE
, 0, {RS
}},
6947 {"mtdac2", XSPR(31,467,317), XSPR_MASK
, BOOKE
, 0, {RS
}},
6948 {"mtdvc1", XSPR(31,467,318), XSPR_MASK
, BOOKE
, 0, {RS
}},
6949 {"mtdvc2", XSPR(31,467,319), XSPR_MASK
, BOOKE
, 0, {RS
}},
6950 {"mttsr", XSPR(31,467,336), XSPR_MASK
, BOOKE
, 0, {RS
}},
6951 {"mttcr", XSPR(31,467,340), XSPR_MASK
, BOOKE
, 0, {RS
}},
6952 {"mtivor0", XSPR(31,467,400), XSPR_MASK
, BOOKE
, 0, {RS
}},
6953 {"mtivor1", XSPR(31,467,401), XSPR_MASK
, BOOKE
, 0, {RS
}},
6954 {"mtivor2", XSPR(31,467,402), XSPR_MASK
, BOOKE
, 0, {RS
}},
6955 {"mtivor3", XSPR(31,467,403), XSPR_MASK
, BOOKE
, 0, {RS
}},
6956 {"mtivor4", XSPR(31,467,404), XSPR_MASK
, BOOKE
, 0, {RS
}},
6957 {"mtivor5", XSPR(31,467,405), XSPR_MASK
, BOOKE
, 0, {RS
}},
6958 {"mtivor6", XSPR(31,467,406), XSPR_MASK
, BOOKE
, 0, {RS
}},
6959 {"mtivor7", XSPR(31,467,407), XSPR_MASK
, BOOKE
, 0, {RS
}},
6960 {"mtivor8", XSPR(31,467,408), XSPR_MASK
, BOOKE
, 0, {RS
}},
6961 {"mtivor9", XSPR(31,467,409), XSPR_MASK
, BOOKE
, 0, {RS
}},
6962 {"mtivor10", XSPR(31,467,410), XSPR_MASK
, BOOKE
, 0, {RS
}},
6963 {"mtivor11", XSPR(31,467,411), XSPR_MASK
, BOOKE
, 0, {RS
}},
6964 {"mtivor12", XSPR(31,467,412), XSPR_MASK
, BOOKE
, 0, {RS
}},
6965 {"mtivor13", XSPR(31,467,413), XSPR_MASK
, BOOKE
, 0, {RS
}},
6966 {"mtivor14", XSPR(31,467,414), XSPR_MASK
, BOOKE
, 0, {RS
}},
6967 {"mtivor15", XSPR(31,467,415), XSPR_MASK
, BOOKE
, 0, {RS
}},
6968 {"mtspefscr", XSPR(31,467,512), XSPR_MASK
, PPCSPE
, 0, {RS
}},
6969 {"mtbbear", XSPR(31,467,513), XSPR_MASK
, PPCBRLK
, 0, {RS
}},
6970 {"mtbbtar", XSPR(31,467,514), XSPR_MASK
, PPCBRLK
, 0, {RS
}},
6971 {"mtivor32", XSPR(31,467,528), XSPR_MASK
, PPCSPE
|E6500
, 0, {RS
}},
6972 {"mtivor33", XSPR(31,467,529), XSPR_MASK
, PPCSPE
|E6500
, 0, {RS
}},
6973 {"mtivor34", XSPR(31,467,530), XSPR_MASK
, PPCSPE
, 0, {RS
}},
6974 {"mtivor35", XSPR(31,467,531), XSPR_MASK
, PPCPMR
, 0, {RS
}},
6975 {"mtibatu", XSPR(31,467,528), XSPRBAT_MASK
, PPC
, TITAN
, {SPRBAT
, RS
}},
6976 {"mtibatl", XSPR(31,467,529), XSPRBAT_MASK
, PPC
, TITAN
, {SPRBAT
, RS
}},
6977 {"mtdbatu", XSPR(31,467,536), XSPRBAT_MASK
, PPC
, TITAN
, {SPRBAT
, RS
}},
6978 {"mtdbatl", XSPR(31,467,537), XSPRBAT_MASK
, PPC
, TITAN
, {SPRBAT
, RS
}},
6979 {"mtmcsrr0", XSPR(31,467,570), XSPR_MASK
, PPCRFMCI
, 0, {RS
}},
6980 {"mtmcsrr1", XSPR(31,467,571), XSPR_MASK
, PPCRFMCI
, 0, {RS
}},
6981 {"mtmcsr", XSPR(31,467,572), XSPR_MASK
, PPCRFMCI
, 0, {RS
}},
6982 {"mtupmc1", XSPR(31,467,771), XSPR_MASK
, POWER9
, 0, {RS
}},
6983 {"mtupmc2", XSPR(31,467,772), XSPR_MASK
, POWER9
, 0, {RS
}},
6984 {"mtupmc3", XSPR(31,467,773), XSPR_MASK
, POWER9
, 0, {RS
}},
6985 {"mtupmc4", XSPR(31,467,774), XSPR_MASK
, POWER9
, 0, {RS
}},
6986 {"mtupmc5", XSPR(31,467,775), XSPR_MASK
, POWER9
, 0, {RS
}},
6987 {"mtupmc6", XSPR(31,467,776), XSPR_MASK
, POWER9
, 0, {RS
}},
6988 {"mtivndx", XSPR(31,467,880), XSPR_MASK
, TITAN
, 0, {RS
}},
6989 {"mtdvndx", XSPR(31,467,881), XSPR_MASK
, TITAN
, 0, {RS
}},
6990 {"mtivlim", XSPR(31,467,882), XSPR_MASK
, TITAN
, 0, {RS
}},
6991 {"mtdvlim", XSPR(31,467,883), XSPR_MASK
, TITAN
, 0, {RS
}},
6992 {"mtclcsr", XSPR(31,467,884), XSPR_MASK
, TITAN
, 0, {RS
}},
6993 {"mtccr1", XSPR(31,467,888), XSPR_MASK
, TITAN
, 0, {RS
}},
6994 {"mtppr", XSPR(31,467,896), XSPR_MASK
, POWER7
, 0, {RS
}},
6995 {"mtppr32", XSPR(31,467,898), XSPR_MASK
, POWER7
, 0, {RS
}},
6996 {"mtgqr", XSPR(31,467,912), XSPRGQR_MASK
, PPCPS
, 0, {SPRGQR
, RS
}},
6997 {"mthid2", XSPR(31,467,920), XSPR_MASK
, GEKKO
, 0, {RS
}},
6998 {"mtwpar", XSPR(31,467,921), XSPR_MASK
, GEKKO
, 0, {RS
}},
6999 {"mtdmau", XSPR(31,467,922), XSPR_MASK
, GEKKO
, 0, {RS
}},
7000 {"mtdmal", XSPR(31,467,923), XSPR_MASK
, GEKKO
, 0, {RS
}},
7001 {"mtummcr0", XSPR(31,467,936), XSPR_MASK
, PPC750
, 0, {RS
}},
7002 {"mtupmc1", XSPR(31,467,937), XSPR_MASK
, PPC750
, 0, {RS
}},
7003 {"mtupmc2", XSPR(31,467,938), XSPR_MASK
, PPC750
, 0, {RS
}},
7004 {"mtusia", XSPR(31,467,939), XSPR_MASK
, PPC750
, 0, {RS
}},
7005 {"mtummcr1", XSPR(31,467,940), XSPR_MASK
, PPC750
, 0, {RS
}},
7006 {"mtupmc3", XSPR(31,467,941), XSPR_MASK
, PPC750
, 0, {RS
}},
7007 {"mtupmc4", XSPR(31,467,942), XSPR_MASK
, PPC750
, 0, {RS
}},
7008 {"mtzpr", XSPR(31,467,944), XSPR_MASK
, PPC403
, 0, {RS
}},
7009 {"mtpid", XSPR(31,467,945), XSPR_MASK
, PPC403
, 0, {RS
}},
7010 {"mtrmmucr", XSPR(31,467,946), XSPR_MASK
, TITAN
, 0, {RS
}},
7011 {"mtccr0", XSPR(31,467,947), XSPR_MASK
, PPC405
|TITAN
, 0, {RS
}},
7012 {"mtiac3", XSPR(31,467,948), XSPR_MASK
, PPC405
, 0, {RS
}},
7013 {"mtiac4", XSPR(31,467,949), XSPR_MASK
, PPC405
, 0, {RS
}},
7014 {"mtdvc1", XSPR(31,467,950), XSPR_MASK
, PPC405
, 0, {RS
}},
7015 {"mtdvc2", XSPR(31,467,951), XSPR_MASK
, PPC405
, 0, {RS
}},
7016 {"mtmmcr0", XSPR(31,467,952), XSPR_MASK
, PPC750
, 0, {RS
}},
7017 {"mtpmc1", XSPR(31,467,953), XSPR_MASK
, PPC750
, 0, {RS
}},
7018 {"mtsgr", XSPR(31,467,953), XSPR_MASK
, PPC403
, 0, {RS
}},
7019 {"mtdcwr", XSPR(31,467,954), XSPR_MASK
, PPC403
, 0, {RS
}},
7020 {"mtpmc2", XSPR(31,467,954), XSPR_MASK
, PPC750
, 0, {RS
}},
7021 {"mtsia", XSPR(31,467,955), XSPR_MASK
, PPC750
, 0, {RS
}},
7022 {"mtsler", XSPR(31,467,955), XSPR_MASK
, PPC405
, 0, {RS
}},
7023 {"mtmmcr1", XSPR(31,467,956), XSPR_MASK
, PPC750
, 0, {RS
}},
7024 {"mtsu0r", XSPR(31,467,956), XSPR_MASK
, PPC405
, 0, {RS
}},
7025 {"mtdbcr1", XSPR(31,467,957), XSPR_MASK
, PPC405
, 0, {RS
}},
7026 {"mtpmc3", XSPR(31,467,957), XSPR_MASK
, PPC750
, 0, {RS
}},
7027 {"mtpmc4", XSPR(31,467,958), XSPR_MASK
, PPC750
, 0, {RS
}},
7028 {"mticdbdr", XSPR(31,467,979), XSPR_MASK
, PPC403
, 0, {RS
}},
7029 {"mtesr", XSPR(31,467,980), XSPR_MASK
, PPC403
, 0, {RS
}},
7030 {"mtdear", XSPR(31,467,981), XSPR_MASK
, PPC403
, 0, {RS
}},
7031 {"mtevpr", XSPR(31,467,982), XSPR_MASK
, PPC403
, 0, {RS
}},
7032 {"mtcdbcr", XSPR(31,467,983), XSPR_MASK
, PPC403
, 0, {RS
}},
7033 {"mttsr", XSPR(31,467,984), XSPR_MASK
, PPC403
, 0, {RS
}},
7034 {"mttcr", XSPR(31,467,986), XSPR_MASK
, PPC403
, 0, {RS
}},
7035 {"mtpit", XSPR(31,467,987), XSPR_MASK
, PPC403
, 0, {RS
}},
7036 {"mttbhi", XSPR(31,467,988), XSPR_MASK
, PPC403
, 0, {RS
}},
7037 {"mttblo", XSPR(31,467,989), XSPR_MASK
, PPC403
, 0, {RS
}},
7038 {"mtsrr2", XSPR(31,467,990), XSPR_MASK
, PPC403
, 0, {RS
}},
7039 {"mtsrr3", XSPR(31,467,991), XSPR_MASK
, PPC403
, 0, {RS
}},
7040 {"mtdbsr", XSPR(31,467,1008), XSPR_MASK
, PPC403
, 0, {RS
}},
7041 {"mthid0", XSPR(31,467,1008), XSPR_MASK
, GEKKO
, 0, {RS
}},
7042 {"mthid1", XSPR(31,467,1009), XSPR_MASK
, GEKKO
, 0, {RS
}},
7043 {"mtdbcr0", XSPR(31,467,1010), XSPR_MASK
, PPC405
, 0, {RS
}},
7044 {"mtiabr", XSPR(31,467,1010), XSPR_MASK
, GEKKO
, 0, {RS
}},
7045 {"mthid4", XSPR(31,467,1011), XSPR_MASK
, BROADWAY
, 0, {RS
}},
7046 {"mtdbdr", XSPR(31,467,1011), XSPR_MASK
, TITAN
, 0, {RS
}},
7047 {"mtiac1", XSPR(31,467,1012), XSPR_MASK
, PPC403
, 0, {RS
}},
7048 {"mtiac2", XSPR(31,467,1013), XSPR_MASK
, PPC403
, 0, {RS
}},
7049 {"mtdabr", XSPR(31,467,1013), XSPR_MASK
, PPC750
, 0, {RS
}},
7050 {"mtdac1", XSPR(31,467,1014), XSPR_MASK
, PPC403
, 0, {RS
}},
7051 {"mtdac2", XSPR(31,467,1015), XSPR_MASK
, PPC403
, 0, {RS
}},
7052 {"mtl2cr", XSPR(31,467,1017), XSPR_MASK
, PPC750
, 0, {RS
}},
7053 {"mtdccr", XSPR(31,467,1018), XSPR_MASK
, PPC403
, 0, {RS
}},
7054 {"mticcr", XSPR(31,467,1019), XSPR_MASK
, PPC403
, 0, {RS
}},
7055 {"mtictc", XSPR(31,467,1019), XSPR_MASK
, PPC750
, 0, {RS
}},
7056 {"mtpbl1", XSPR(31,467,1020), XSPR_MASK
, PPC403
, 0, {RS
}},
7057 {"mtthrm1", XSPR(31,467,1020), XSPR_MASK
, PPC750
, 0, {RS
}},
7058 {"mtpbu1", XSPR(31,467,1021), XSPR_MASK
, PPC403
, 0, {RS
}},
7059 {"mtthrm2", XSPR(31,467,1021), XSPR_MASK
, PPC750
, 0, {RS
}},
7060 {"mtpbl2", XSPR(31,467,1022), XSPR_MASK
, PPC403
, 0, {RS
}},
7061 {"mtthrm3", XSPR(31,467,1022), XSPR_MASK
, PPC750
, 0, {RS
}},
7062 {"mtpbu2", XSPR(31,467,1023), XSPR_MASK
, PPC403
, 0, {RS
}},
7063 {"mtspr", X(31,467), X_MASK
, COM
, 0, {SPR
, RS
}},
7065 {"dcbi", X(31,470), XRT_MASK
, PPC
, 0, {RA0
, RB
}},
7067 {"nand", XRC(31,476,0), X_MASK
, COM
, 0, {RA
, RS
, RB
}},
7068 {"nand.", XRC(31,476,1), X_MASK
, COM
, 0, {RA
, RS
, RB
}},
7070 {"dsn", X(31,483), XRT_MASK
, E500MC
, 0, {RA
, RB
}},
7072 {"dcread", X(31,486), X_MASK
, PPC403
|PPC440
, PPCA2
, {RT
, RA0
, RB
}},
7074 {"icbtls", X(31,486), X_MASK
, PPCCHLK
|PPC476
|TITAN
, 0, {CT
, RA0
, RB
}},
7076 {"stvxl", X(31,487), X_MASK
, PPCVEC
, 0, {VS
, RA0
, RB
}},
7078 {"nabs", XO(31,488,0,0), XORB_MASK
, M601
, 0, {RT
, RA
}},
7079 {"nabs.", XO(31,488,0,1), XORB_MASK
, M601
, 0, {RT
, RA
}},
7081 {"divd", XO(31,489,0,0), XO_MASK
, PPC64
, 0, {RT
, RA
, RB
}},
7082 {"divd.", XO(31,489,0,1), XO_MASK
, PPC64
, 0, {RT
, RA
, RB
}},
7084 {"divw", XO(31,491,0,0), XO_MASK
, PPC
, 0, {RT
, RA
, RB
}},
7085 {"divw.", XO(31,491,0,1), XO_MASK
, PPC
, 0, {RT
, RA
, RB
}},
7087 {"icbtlse", X(31,494), X_MASK
, PPCCHLK
, E500MC
, {CT
, RA
, RB
}},
7089 {"slbia", X(31,498), 0xff1fffff, POWER6
, 0, {IH
}},
7090 {"slbia", X(31,498), 0xffffffff, PPC64
, POWER6
, {0}},
7092 {"cli", X(31,502), XRB_MASK
, POWER
, 0, {RT
, RA
}},
7094 {"popcntd", X(31,506), XRB_MASK
, POWER7
|PPCA2
, 0, {RA
, RS
}},
7096 {"cmpb", X(31,508), X_MASK
, POWER6
|PPCA2
|PPC476
, 0, {RA
, RS
, RB
}},
7098 {"mcrxr", X(31,512), XBFRARB_MASK
, COM
, POWER7
, {BF
}},
7100 {"lbdcbx", X(31,514), X_MASK
, E200Z4
, 0, {RT
, RA
, RB
}},
7101 {"lbdx", X(31,515), X_MASK
, E500MC
|E200Z4
, 0, {RT
, RA
, RB
}},
7103 {"bblels", X(31,518), X_MASK
, PPCBRLK
, 0, {0}},
7105 {"lvlx", X(31,519), X_MASK
, CELL
, 0, {VD
, RA0
, RB
}},
7106 {"lbfcmux", APU(31,519,0), APU_MASK
, PPC405
, 0, {FCRT
, RA
, RB
}},
7108 {"subfco", XO(31,8,1,0), XO_MASK
, PPCCOM
, 0, {RT
, RA
, RB
}},
7109 {"sfo", XO(31,8,1,0), XO_MASK
, PWRCOM
, 0, {RT
, RA
, RB
}},
7110 {"subco", XO(31,8,1,0), XO_MASK
, PPCCOM
, 0, {RT
, RB
, RA
}},
7111 {"subfco.", XO(31,8,1,1), XO_MASK
, PPCCOM
, 0, {RT
, RA
, RB
}},
7112 {"sfo.", XO(31,8,1,1), XO_MASK
, PWRCOM
, 0, {RT
, RA
, RB
}},
7113 {"subco.", XO(31,8,1,1), XO_MASK
, PPCCOM
, 0, {RT
, RB
, RA
}},
7115 {"addco", XO(31,10,1,0), XO_MASK
, PPCCOM
, 0, {RT
, RA
, RB
}},
7116 {"ao", XO(31,10,1,0), XO_MASK
, PWRCOM
, 0, {RT
, RA
, RB
}},
7117 {"addco.", XO(31,10,1,1), XO_MASK
, PPCCOM
, 0, {RT
, RA
, RB
}},
7118 {"ao.", XO(31,10,1,1), XO_MASK
, PWRCOM
, 0, {RT
, RA
, RB
}},
7120 {"lxsspx", X(31,524), XX1_MASK
, PPCVSX2
, 0, {XT6
, RA0
, RB
}},
7122 {"clcs", X(31,531), XRB_MASK
, M601
, 0, {RT
, RA
}},
7124 {"ldbrx", X(31,532), X_MASK
, CELL
|POWER7
|PPCA2
, 0, {RT
, RA0
, RB
}},
7126 {"lswx", X(31,533), X_MASK
, PPCCOM
, E500
|E500MC
, {RT
, RAX
, RBX
}},
7127 {"lsx", X(31,533), X_MASK
, PWRCOM
, 0, {RT
, RA
, RB
}},
7129 {"lwbrx", X(31,534), X_MASK
, PPCCOM
, 0, {RT
, RA0
, RB
}},
7130 {"lbrx", X(31,534), X_MASK
, PWRCOM
, 0, {RT
, RA
, RB
}},
7132 {"lfsx", X(31,535), X_MASK
, COM
, PPCEFS
, {FRT
, RA0
, RB
}},
7134 {"srw", XRC(31,536,0), X_MASK
, PPCCOM
, 0, {RA
, RS
, RB
}},
7135 {"sr", XRC(31,536,0), X_MASK
, PWRCOM
, 0, {RA
, RS
, RB
}},
7136 {"srw.", XRC(31,536,1), X_MASK
, PPCCOM
, 0, {RA
, RS
, RB
}},
7137 {"sr.", XRC(31,536,1), X_MASK
, PWRCOM
, 0, {RA
, RS
, RB
}},
7139 {"rrib", XRC(31,537,0), X_MASK
, M601
, 0, {RA
, RS
, RB
}},
7140 {"rrib.", XRC(31,537,1), X_MASK
, M601
, 0, {RA
, RS
, RB
}},
7142 {"cnttzw", XRC(31,538,0), XRB_MASK
, POWER9
, 0, {RA
, RS
}},
7143 {"cnttzw.", XRC(31,538,1), XRB_MASK
, POWER9
, 0, {RA
, RS
}},
7145 {"srd", XRC(31,539,0), X_MASK
, PPC64
, 0, {RA
, RS
, RB
}},
7146 {"srd.", XRC(31,539,1), X_MASK
, PPC64
, 0, {RA
, RS
, RB
}},
7148 {"maskir", XRC(31,541,0), X_MASK
, M601
, 0, {RA
, RS
, RB
}},
7149 {"maskir.", XRC(31,541,1), X_MASK
, M601
, 0, {RA
, RS
, RB
}},
7151 {"lhdcbx", X(31,546), X_MASK
, E200Z4
, 0, {RT
, RA
, RB
}},
7152 {"lhdx", X(31,547), X_MASK
, E500MC
|E200Z4
, 0, {RT
, RA
, RB
}},
7154 {"lvtrx", X(31,549), X_MASK
, E6500
, 0, {VD
, RA0
, RB
}},
7156 {"bbelr", X(31,550), X_MASK
, PPCBRLK
, 0, {0}},
7158 {"lvrx", X(31,551), X_MASK
, CELL
, 0, {VD
, RA0
, RB
}},
7159 {"lhfcmux", APU(31,551,0), APU_MASK
, PPC405
, 0, {FCRT
, RA
, RB
}},
7161 {"subfo", XO(31,40,1,0), XO_MASK
, PPC
, 0, {RT
, RA
, RB
}},
7162 {"subo", XO(31,40,1,0), XO_MASK
, PPC
, 0, {RT
, RB
, RA
}},
7163 {"subfo.", XO(31,40,1,1), XO_MASK
, PPC
, 0, {RT
, RA
, RB
}},
7164 {"subo.", XO(31,40,1,1), XO_MASK
, PPC
, 0, {RT
, RB
, RA
}},
7166 {"tlbsync", X(31,566), 0xffffffff, PPC
, 0, {0}},
7168 {"lfsux", X(31,567), X_MASK
, COM
, PPCEFS
, {FRT
, RAS
, RB
}},
7170 {"cnttzd", XRC(31,570,0), XRB_MASK
, POWER9
, 0, {RA
, RS
}},
7171 {"cnttzd.", XRC(31,570,1), XRB_MASK
, POWER9
, 0, {RA
, RS
}},
7173 {"mcrxrx", X(31,576), XBFRARB_MASK
, POWER9
, 0, {BF
}},
7175 {"lwdcbx", X(31,578), X_MASK
, E200Z4
, 0, {RT
, RA
, RB
}},
7176 {"lwdx", X(31,579), X_MASK
, E500MC
|E200Z4
, 0, {RT
, RA
, RB
}},
7178 {"lvtlx", X(31,581), X_MASK
, E6500
, 0, {VD
, RA0
, RB
}},
7180 {"lwat", X(31,582), X_MASK
, POWER9
, 0, {RT
, RA0
, FC
}},
7182 {"lwfcmux", APU(31,583,0), APU_MASK
, PPC405
, 0, {FCRT
, RA
, RB
}},
7184 {"lxsdx", X(31,588), XX1_MASK
, PPCVSX
, 0, {XT6
, RA0
, RB
}},
7186 {"mfsr", X(31,595), XRB_MASK
|(1<<20), COM
, NON32
, {RT
, SR
}},
7188 {"lswi", X(31,597), X_MASK
, PPCCOM
, E500
|E500MC
, {RT
, RAX
, NBI
}},
7189 {"lsi", X(31,597), X_MASK
, PWRCOM
, 0, {RT
, RA0
, NB
}},
7191 {"hwsync", XSYNC(31,598,0), 0xffffffff, POWER4
, BOOKE
|PPC476
, {0}},
7192 {"lwsync", XSYNC(31,598,1), 0xffffffff, PPC
, E500
, {0}},
7193 {"ptesync", XSYNC(31,598,2), 0xffffffff, PPC64
, 0, {0}},
7194 {"sync", X(31,598), XSYNCLE_MASK
, E6500
, 0, {LS
, ESYNC
}},
7195 {"sync", X(31,598), XSYNC_MASK
, PPCCOM
, BOOKE
|PPC476
, {LS
}},
7196 {"msync", X(31,598), 0xffffffff, BOOKE
|PPCA2
|PPC476
, 0, {0}},
7197 {"sync", X(31,598), 0xffffffff, BOOKE
|PPC476
, E6500
, {0}},
7198 {"lwsync", X(31,598), 0xffffffff, E500
, 0, {0}},
7199 {"dcs", X(31,598), 0xffffffff, PWRCOM
, 0, {0}},
7201 {"lfdx", X(31,599), X_MASK
, COM
, PPCEFS
, {FRT
, RA0
, RB
}},
7203 {"mffgpr", XRC(31,607,0), XRA_MASK
, POWER6
, POWER7
, {FRT
, RB
}},
7204 {"lfdepx", X(31,607), X_MASK
, E500MC
|PPCA2
, 0, {FRT
, RA0
, RB
}},
7206 {"lddx", X(31,611), X_MASK
, E500MC
, 0, {RT
, RA
, RB
}},
7208 {"lvswx", X(31,613), X_MASK
, E6500
, 0, {VD
, RA0
, RB
}},
7210 {"ldat", X(31,614), X_MASK
, POWER9
, 0, {RT
, RA0
, FC
}},
7212 {"lqfcmux", APU(31,615,0), APU_MASK
, PPC405
, 0, {FCRT
, RA
, RB
}},
7214 {"nego", XO(31,104,1,0), XORB_MASK
, COM
, 0, {RT
, RA
}},
7215 {"nego.", XO(31,104,1,1), XORB_MASK
, COM
, 0, {RT
, RA
}},
7217 {"mulo", XO(31,107,1,0), XO_MASK
, M601
, 0, {RT
, RA
, RB
}},
7218 {"mulo.", XO(31,107,1,1), XO_MASK
, M601
, 0, {RT
, RA
, RB
}},
7220 {"mfsri", X(31,627), X_MASK
, M601
, 0, {RT
, RA
, RB
}},
7222 {"dclst", X(31,630), XRB_MASK
, M601
, 0, {RS
, RA
}},
7224 {"lfdux", X(31,631), X_MASK
, COM
, PPCEFS
, {FRT
, RAS
, RB
}},
7226 {"stbdcbx", X(31,642), X_MASK
, E200Z4
, 0, {RS
, RA
, RB
}},
7227 {"stbdx", X(31,643), X_MASK
, E500MC
|E200Z4
, 0, {RS
, RA
, RB
}},
7229 {"stvlx", X(31,647), X_MASK
, CELL
, 0, {VS
, RA0
, RB
}},
7230 {"stbfcmux", APU(31,647,0), APU_MASK
, PPC405
, 0, {FCRT
, RA
, RB
}},
7232 {"stxsspx", X(31,652), XX1_MASK
, PPCVSX2
, 0, {XS6
, RA0
, RB
}},
7234 {"tbegin.", XRC(31,654,1), XRTLRARB_MASK
, PPCHTM
, 0, {HTM_R
}},
7236 {"subfeo", XO(31,136,1,0), XO_MASK
, PPCCOM
, 0, {RT
, RA
, RB
}},
7237 {"sfeo", XO(31,136,1,0), XO_MASK
, PWRCOM
, 0, {RT
, RA
, RB
}},
7238 {"subfeo.", XO(31,136,1,1), XO_MASK
, PPCCOM
, 0, {RT
, RA
, RB
}},
7239 {"sfeo.", XO(31,136,1,1), XO_MASK
, PWRCOM
, 0, {RT
, RA
, RB
}},
7241 {"addeo", XO(31,138,1,0), XO_MASK
, PPCCOM
, 0, {RT
, RA
, RB
}},
7242 {"aeo", XO(31,138,1,0), XO_MASK
, PWRCOM
, 0, {RT
, RA
, RB
}},
7243 {"addeo.", XO(31,138,1,1), XO_MASK
, PPCCOM
, 0, {RT
, RA
, RB
}},
7244 {"aeo.", XO(31,138,1,1), XO_MASK
, PWRCOM
, 0, {RT
, RA
, RB
}},
7246 {"mfsrin", X(31,659), XRA_MASK
, PPC
, NON32
, {RT
, RB
}},
7248 {"stdbrx", X(31,660), X_MASK
, CELL
|POWER7
|PPCA2
, 0, {RS
, RA0
, RB
}},
7250 {"stswx", X(31,661), X_MASK
, PPCCOM
, E500
|E500MC
, {RS
, RA0
, RB
}},
7251 {"stsx", X(31,661), X_MASK
, PWRCOM
, 0, {RS
, RA0
, RB
}},
7253 {"stwbrx", X(31,662), X_MASK
, PPCCOM
, 0, {RS
, RA0
, RB
}},
7254 {"stbrx", X(31,662), X_MASK
, PWRCOM
, 0, {RS
, RA0
, RB
}},
7256 {"stfsx", X(31,663), X_MASK
, COM
, PPCEFS
, {FRS
, RA0
, RB
}},
7258 {"srq", XRC(31,664,0), X_MASK
, M601
, 0, {RA
, RS
, RB
}},
7259 {"srq.", XRC(31,664,1), X_MASK
, M601
, 0, {RA
, RS
, RB
}},
7261 {"sre", XRC(31,665,0), X_MASK
, M601
, 0, {RA
, RS
, RB
}},
7262 {"sre.", XRC(31,665,1), X_MASK
, M601
, 0, {RA
, RS
, RB
}},
7264 {"sthdcbx", X(31,674), X_MASK
, E200Z4
, 0, {RS
, RA
, RB
}},
7265 {"sthdx", X(31,675), X_MASK
, E500MC
|E200Z4
, 0, {RS
, RA
, RB
}},
7267 {"stvfrx", X(31,677), X_MASK
, E6500
, 0, {VS
, RA0
, RB
}},
7269 {"stvrx", X(31,679), X_MASK
, CELL
, 0, {VS
, RA0
, RB
}},
7270 {"sthfcmux", APU(31,679,0), APU_MASK
, PPC405
, 0, {FCRT
, RA
, RB
}},
7272 {"tendall.", XRC(31,686,1)|(1<<25), XRTRARB_MASK
, PPCHTM
, 0, {0}},
7273 {"tend.", XRC(31,686,1), XRTARARB_MASK
, PPCHTM
, 0, {HTM_A
}},
7275 {"stbcx.", XRC(31,694,1), X_MASK
, POWER8
|E6500
, 0, {RS
, RA0
, RB
}},
7277 {"stfsux", X(31,695), X_MASK
, COM
, PPCEFS
, {FRS
, RAS
, RB
}},
7279 {"sriq", XRC(31,696,0), X_MASK
, M601
, 0, {RA
, RS
, SH
}},
7280 {"sriq.", XRC(31,696,1), X_MASK
, M601
, 0, {RA
, RS
, SH
}},
7282 {"stwdcbx", X(31,706), X_MASK
, E200Z4
, 0, {RS
, RA
, RB
}},
7283 {"stwdx", X(31,707), X_MASK
, E500MC
|E200Z4
, 0, {RS
, RA
, RB
}},
7285 {"stvflx", X(31,709), X_MASK
, E6500
, 0, {VS
, RA0
, RB
}},
7287 {"stwat", X(31,710), X_MASK
, POWER9
, 0, {RS
, RA0
, FC
}},
7289 {"stwfcmux", APU(31,711,0), APU_MASK
, PPC405
, 0, {FCRT
, RA
, RB
}},
7291 {"stxsdx", X(31,716), XX1_MASK
, PPCVSX
, 0, {XS6
, RA0
, RB
}},
7293 {"tcheck", X(31,718), XRTBFRARB_MASK
, PPCHTM
, 0, {BF
}},
7295 {"subfzeo", XO(31,200,1,0), XORB_MASK
, PPCCOM
, 0, {RT
, RA
}},
7296 {"sfzeo", XO(31,200,1,0), XORB_MASK
, PWRCOM
, 0, {RT
, RA
}},
7297 {"subfzeo.", XO(31,200,1,1), XORB_MASK
, PPCCOM
, 0, {RT
, RA
}},
7298 {"sfzeo.", XO(31,200,1,1), XORB_MASK
, PWRCOM
, 0, {RT
, RA
}},
7300 {"addzeo", XO(31,202,1,0), XORB_MASK
, PPCCOM
, 0, {RT
, RA
}},
7301 {"azeo", XO(31,202,1,0), XORB_MASK
, PWRCOM
, 0, {RT
, RA
}},
7302 {"addzeo.", XO(31,202,1,1), XORB_MASK
, PPCCOM
, 0, {RT
, RA
}},
7303 {"azeo.", XO(31,202,1,1), XORB_MASK
, PWRCOM
, 0, {RT
, RA
}},
7305 {"stswi", X(31,725), X_MASK
, PPCCOM
, E500
|E500MC
, {RS
, RA0
, NB
}},
7306 {"stsi", X(31,725), X_MASK
, PWRCOM
, 0, {RS
, RA0
, NB
}},
7308 {"sthcx.", XRC(31,726,1), X_MASK
, POWER8
|E6500
, 0, {RS
, RA0
, RB
}},
7310 {"stfdx", X(31,727), X_MASK
, COM
, PPCEFS
, {FRS
, RA0
, RB
}},
7312 {"srlq", XRC(31,728,0), X_MASK
, M601
, 0, {RA
, RS
, RB
}},
7313 {"srlq.", XRC(31,728,1), X_MASK
, M601
, 0, {RA
, RS
, RB
}},
7315 {"sreq", XRC(31,729,0), X_MASK
, M601
, 0, {RA
, RS
, RB
}},
7316 {"sreq.", XRC(31,729,1), X_MASK
, M601
, 0, {RA
, RS
, RB
}},
7318 {"mftgpr", XRC(31,735,0), XRA_MASK
, POWER6
, POWER7
, {RT
, FRB
}},
7319 {"stfdepx", X(31,735), X_MASK
, E500MC
|PPCA2
, 0, {FRS
, RA0
, RB
}},
7321 {"stddx", X(31,739), X_MASK
, E500MC
, 0, {RS
, RA
, RB
}},
7323 {"stvswx", X(31,741), X_MASK
, E6500
, 0, {VS
, RA0
, RB
}},
7325 {"stdat", X(31,742), X_MASK
, POWER9
, 0, {RS
, RA0
, FC
}},
7327 {"stqfcmux", APU(31,743,0), APU_MASK
, PPC405
, 0, {FCRT
, RA
, RB
}},
7329 {"subfmeo", XO(31,232,1,0), XORB_MASK
, PPCCOM
, 0, {RT
, RA
}},
7330 {"sfmeo", XO(31,232,1,0), XORB_MASK
, PWRCOM
, 0, {RT
, RA
}},
7331 {"subfmeo.", XO(31,232,1,1), XORB_MASK
, PPCCOM
, 0, {RT
, RA
}},
7332 {"sfmeo.", XO(31,232,1,1), XORB_MASK
, PWRCOM
, 0, {RT
, RA
}},
7334 {"mulldo", XO(31,233,1,0), XO_MASK
, PPC64
, 0, {RT
, RA
, RB
}},
7335 {"mulldo.", XO(31,233,1,1), XO_MASK
, PPC64
, 0, {RT
, RA
, RB
}},
7337 {"addmeo", XO(31,234,1,0), XORB_MASK
, PPCCOM
, 0, {RT
, RA
}},
7338 {"ameo", XO(31,234,1,0), XORB_MASK
, PWRCOM
, 0, {RT
, RA
}},
7339 {"addmeo.", XO(31,234,1,1), XORB_MASK
, PPCCOM
, 0, {RT
, RA
}},
7340 {"ameo.", XO(31,234,1,1), XORB_MASK
, PWRCOM
, 0, {RT
, RA
}},
7342 {"mullwo", XO(31,235,1,0), XO_MASK
, PPCCOM
, 0, {RT
, RA
, RB
}},
7343 {"mulso", XO(31,235,1,0), XO_MASK
, PWRCOM
, 0, {RT
, RA
, RB
}},
7344 {"mullwo.", XO(31,235,1,1), XO_MASK
, PPCCOM
, 0, {RT
, RA
, RB
}},
7345 {"mulso.", XO(31,235,1,1), XO_MASK
, PWRCOM
, 0, {RT
, RA
, RB
}},
7347 {"tsuspend.", XRCL(31,750,0,1), XRTRARB_MASK
,PPCHTM
, 0, {0}},
7348 {"tresume.", XRCL(31,750,1,1), XRTRARB_MASK
,PPCHTM
, 0, {0}},
7349 {"tsr.", XRC(31,750,1), XRTLRARB_MASK
,PPCHTM
, 0, {L
}},
7351 {"darn", X(31,755), XLRAND_MASK
, POWER9
, 0, {RT
, LRAND
}},
7353 {"dcba", X(31,758), XRT_MASK
, PPC405
|PPC7450
|BOOKE
|PPCA2
|PPC476
, 0, {RA0
, RB
}},
7354 {"dcbal", XOPL(31,758,1), XRT_MASK
, E500MC
, 0, {RA0
, RB
}},
7356 {"stfdux", X(31,759), X_MASK
, COM
, PPCEFS
, {FRS
, RAS
, RB
}},
7358 {"srliq", XRC(31,760,0), X_MASK
, M601
, 0, {RA
, RS
, SH
}},
7359 {"srliq.", XRC(31,760,1), X_MASK
, M601
, 0, {RA
, RS
, SH
}},
7361 {"lvsm", X(31,773), X_MASK
, E6500
, 0, {VD
, RA0
, RB
}},
7363 {"copy", XOPL(31,774,1), XRT_MASK
, POWER9
, 0, {RA0
, RB
}},
7365 {"stvepxl", X(31,775), X_MASK
, E6500
, 0, {VS
, RA0
, RB
}},
7366 {"lvlxl", X(31,775), X_MASK
, CELL
, 0, {VD
, RA0
, RB
}},
7367 {"ldfcmux", APU(31,775,0), APU_MASK
, PPC405
, 0, {FCRT
, RA
, RB
}},
7369 {"dozo", XO(31,264,1,0), XO_MASK
, M601
, 0, {RT
, RA
, RB
}},
7370 {"dozo.", XO(31,264,1,1), XO_MASK
, M601
, 0, {RT
, RA
, RB
}},
7372 {"addo", XO(31,266,1,0), XO_MASK
, PPCCOM
, 0, {RT
, RA
, RB
}},
7373 {"caxo", XO(31,266,1,0), XO_MASK
, PWRCOM
, 0, {RT
, RA
, RB
}},
7374 {"addo.", XO(31,266,1,1), XO_MASK
, PPCCOM
, 0, {RT
, RA
, RB
}},
7375 {"caxo.", XO(31,266,1,1), XO_MASK
, PWRCOM
, 0, {RT
, RA
, RB
}},
7377 {"modsd", X(31,777), X_MASK
, POWER9
, 0, {RT
, RA
, RB
}},
7378 {"modsw", X(31,779), X_MASK
, POWER9
, 0, {RT
, RA
, RB
}},
7380 {"lxvw4x", X(31,780), XX1_MASK
, PPCVSX
, 0, {XT6
, RA0
, RB
}},
7381 {"lxsibzx", X(31,781), XX1_MASK
, PPCVSX3
, 0, {XT6
, RA0
, RB
}},
7383 {"tabortwc.", XRC(31,782,1), X_MASK
, PPCHTM
, 0, {TO
, RA
, RB
}},
7385 {"tlbivax", X(31,786), XRT_MASK
, BOOKE
|PPCA2
|PPC476
, 0, {RA0
, RB
}},
7387 {"lwzcix", X(31,789), X_MASK
, POWER6
, 0, {RT
, RA0
, RB
}},
7389 {"lhbrx", X(31,790), X_MASK
, COM
, 0, {RT
, RA0
, RB
}},
7391 {"lfdpx", X(31,791), X_MASK
|Q_MASK
, POWER6
, POWER7
, {FRTp
, RA0
, RB
}},
7392 {"lfqx", X(31,791), X_MASK
, POWER2
, 0, {FRT
, RA
, RB
}},
7394 {"sraw", XRC(31,792,0), X_MASK
, PPCCOM
, 0, {RA
, RS
, RB
}},
7395 {"sra", XRC(31,792,0), X_MASK
, PWRCOM
, 0, {RA
, RS
, RB
}},
7396 {"sraw.", XRC(31,792,1), X_MASK
, PPCCOM
, 0, {RA
, RS
, RB
}},
7397 {"sra.", XRC(31,792,1), X_MASK
, PWRCOM
, 0, {RA
, RS
, RB
}},
7399 {"srad", XRC(31,794,0), X_MASK
, PPC64
, 0, {RA
, RS
, RB
}},
7400 {"srad.", XRC(31,794,1), X_MASK
, PPC64
, 0, {RA
, RS
, RB
}},
7402 {"evlddepx", VX (31, 1598), VX_MASK
, PPCSPE
, 0, {RT
, RA
, RB
}},
7403 {"lfddx", X(31,803), X_MASK
, E500MC
, 0, {FRT
, RA
, RB
}},
7405 {"lvtrxl", X(31,805), X_MASK
, E6500
, 0, {VD
, RA0
, RB
}},
7406 {"stvepx", X(31,807), X_MASK
, E6500
, 0, {VS
, RA0
, RB
}},
7407 {"lvrxl", X(31,807), X_MASK
, CELL
, 0, {VD
, RA0
, RB
}},
7409 {"lxvh8x", X(31,812), XX1_MASK
, PPCVSX3
, 0, {XT6
, RA0
, RB
}},
7410 {"lxsihzx", X(31,813), XX1_MASK
, PPCVSX3
, 0, {XT6
, RA0
, RB
}},
7412 {"tabortdc.", XRC(31,814,1), X_MASK
, PPCHTM
, 0, {TO
, RA
, RB
}},
7414 {"rac", X(31,818), X_MASK
, M601
, 0, {RT
, RA
, RB
}},
7416 {"erativax", X(31,819), X_MASK
, PPCA2
, 0, {RS
, RA0
, RB
}},
7418 {"lhzcix", X(31,821), X_MASK
, POWER6
, 0, {RT
, RA0
, RB
}},
7420 {"dss", XDSS(31,822,0), XDSS_MASK
, PPCVEC
, 0, {STRM
}},
7422 {"lfqux", X(31,823), X_MASK
, POWER2
, 0, {FRT
, RA
, RB
}},
7424 {"srawi", XRC(31,824,0), X_MASK
, PPCCOM
, 0, {RA
, RS
, SH
}},
7425 {"srai", XRC(31,824,0), X_MASK
, PWRCOM
, 0, {RA
, RS
, SH
}},
7426 {"srawi.", XRC(31,824,1), X_MASK
, PPCCOM
, 0, {RA
, RS
, SH
}},
7427 {"srai.", XRC(31,824,1), X_MASK
, PWRCOM
, 0, {RA
, RS
, SH
}},
7429 {"sradi", XS(31,413,0), XS_MASK
, PPC64
, 0, {RA
, RS
, SH6
}},
7430 {"sradi.", XS(31,413,1), XS_MASK
, PPC64
, 0, {RA
, RS
, SH6
}},
7432 {"lvtlxl", X(31,837), X_MASK
, E6500
, 0, {VD
, RA0
, RB
}},
7434 {"cpabort", X(31,838), XRTRARB_MASK
,POWER9
, 0, {0}},
7436 {"divo", XO(31,331,1,0), XO_MASK
, M601
, 0, {RT
, RA
, RB
}},
7437 {"divo.", XO(31,331,1,1), XO_MASK
, M601
, 0, {RT
, RA
, RB
}},
7439 {"lxvd2x", X(31,844), XX1_MASK
, PPCVSX
, 0, {XT6
, RA0
, RB
}},
7440 {"lxvx", X(31,844), XX1_MASK
, POWER8
, POWER9
|PPCVSX3
, {XT6
, RA0
, RB
}},
7442 {"tabortwci.", XRC(31,846,1), X_MASK
, PPCHTM
, 0, {TO
, RA
, HTM_SI
}},
7444 {"tlbsrx.", XRC(31,850,1), XRT_MASK
, PPCA2
, 0, {RA0
, RB
}},
7446 {"slbiag", X(31,850), XRLARB_MASK
, POWER10
, 0, {RS
, A_L
}},
7447 {"slbiag", X(31,850), XRARB_MASK
, POWER9
, POWER10
, {RS
}},
7449 {"slbmfev", X(31,851), XRLA_MASK
, POWER9
, 0, {RT
, RB
, A_L
}},
7450 {"slbmfev", X(31,851), XRA_MASK
, PPC64
, POWER9
, {RT
, RB
}},
7452 {"lbzcix", X(31,853), X_MASK
, POWER6
, 0, {RT
, RA0
, RB
}},
7454 {"eieio", X(31,854), 0xffffffff, PPC
, BOOKE
|PPCA2
|PPC476
, {0}},
7455 {"mbar", X(31,854), X_MASK
, BOOKE
|PPCA2
|PPC476
, 0, {MO
}},
7456 {"eieio", XMBAR(31,854,1),0xffffffff, E500
, 0, {0}},
7457 {"eieio", X(31,854), 0xffffffff, PPCA2
|PPC476
, 0, {0}},
7459 {"lfiwax", X(31,855), X_MASK
, POWER6
|PPCA2
|PPC476
, 0, {FRT
, RA0
, RB
}},
7461 {"lvswxl", X(31,869), X_MASK
, E6500
, 0, {VD
, RA0
, RB
}},
7463 {"abso", XO(31,360,1,0), XORB_MASK
, M601
, 0, {RT
, RA
}},
7464 {"abso.", XO(31,360,1,1), XORB_MASK
, M601
, 0, {RT
, RA
}},
7466 {"divso", XO(31,363,1,0), XO_MASK
, M601
, 0, {RT
, RA
, RB
}},
7467 {"divso.", XO(31,363,1,1), XO_MASK
, M601
, 0, {RT
, RA
, RB
}},
7469 {"lxvb16x", X(31,876), XX1_MASK
, PPCVSX3
, 0, {XT6
, RA0
, RB
}},
7471 {"tabortdci.", XRC(31,878,1), X_MASK
, PPCHTM
, 0, {TO
, RA
, HTM_SI
}},
7473 {"rmieg", X(31,882), XRTRA_MASK
, POWER9
, 0, {RB
}},
7475 {"ldcix", X(31,885), X_MASK
, POWER6
, 0, {RT
, RA0
, RB
}},
7477 {"msgsync", X(31,886), 0xffffffff, POWER9
, 0, {0}},
7479 {"lfiwzx", X(31,887), X_MASK
, POWER7
|PPCA2
, 0, {FRT
, RA0
, RB
}},
7481 {"extswsli", XS(31,445,0), XS_MASK
, POWER9
, 0, {RA
, RS
, SH6
}},
7482 {"extswsli.", XS(31,445,1), XS_MASK
, POWER9
, 0, {RA
, RS
, SH6
}},
7484 {"paste.", XRC(31,902,1), XLRT_MASK
, POWER10
, 0, {RA0
, RB
, L1OPT
}},
7485 {"paste.", XRCL(31,902,1,1),XRT_MASK
, POWER9
, POWER10
, {RA0
, RB
}},
7487 {"stvlxl", X(31,903), X_MASK
, CELL
, 0, {VS
, RA0
, RB
}},
7488 {"stdfcmux", APU(31,903,0), APU_MASK
, PPC405
, 0, {FCRT
, RA
, RB
}},
7490 {"divdeuo", XO(31,393,1,0), XO_MASK
, POWER7
|PPCA2
, 0, {RT
, RA
, RB
}},
7491 {"divdeuo.", XO(31,393,1,1), XO_MASK
, POWER7
|PPCA2
, 0, {RT
, RA
, RB
}},
7492 {"divweuo", XO(31,395,1,0), XO_MASK
, POWER7
|PPCA2
, 0, {RT
, RA
, RB
}},
7493 {"divweuo.", XO(31,395,1,1), XO_MASK
, POWER7
|PPCA2
, 0, {RT
, RA
, RB
}},
7495 {"stxvw4x", X(31,908), XX1_MASK
, PPCVSX
, 0, {XS6
, RA0
, RB
}},
7496 {"stxsibx", X(31,909), XX1_MASK
, PPCVSX3
, 0, {XS6
, RA0
, RB
}},
7498 {"tabort.", XRC(31,910,1), XRTRB_MASK
, PPCHTM
, 0, {RA
}},
7500 {"tlbsx", XRC(31,914,0), X_MASK
, PPC403
|BOOKE
|PPCA2
|PPC476
, 0, {RTO
, RA0
, RB
}},
7501 {"tlbsx.", XRC(31,914,1), X_MASK
, PPC403
|BOOKE
|PPCA2
|PPC476
, 0, {RTO
, RA0
, RB
}},
7503 {"slbmfee", X(31,915), XRLA_MASK
, POWER9
, 0, {RT
, RB
, A_L
}},
7504 {"slbmfee", X(31,915), XRA_MASK
, PPC64
, POWER9
, {RT
, RB
}},
7506 {"stwcix", X(31,917), X_MASK
, POWER6
, 0, {RS
, RA0
, RB
}},
7508 {"sthbrx", X(31,918), X_MASK
, COM
, 0, {RS
, RA0
, RB
}},
7510 {"stfdpx", X(31,919), X_MASK
|Q_MASK
, POWER6
, POWER7
, {FRSp
, RA0
, RB
}},
7511 {"stfqx", X(31,919), X_MASK
, POWER2
, 0, {FRS
, RA0
, RB
}},
7513 {"sraq", XRC(31,920,0), X_MASK
, M601
, 0, {RA
, RS
, RB
}},
7514 {"sraq.", XRC(31,920,1), X_MASK
, M601
, 0, {RA
, RS
, RB
}},
7516 {"srea", XRC(31,921,0), X_MASK
, M601
, 0, {RA
, RS
, RB
}},
7517 {"srea.", XRC(31,921,1), X_MASK
, M601
, 0, {RA
, RS
, RB
}},
7519 {"extsh", XRC(31,922,0), XRB_MASK
, PPCCOM
, 0, {RA
, RS
}},
7520 {"exts", XRC(31,922,0), XRB_MASK
, PWRCOM
, 0, {RA
, RS
}},
7521 {"extsh.", XRC(31,922,1), XRB_MASK
, PPCCOM
, 0, {RA
, RS
}},
7522 {"exts.", XRC(31,922,1), XRB_MASK
, PWRCOM
, 0, {RA
, RS
}},
7524 {"evstddepx", VX (31, 1854), VX_MASK
, PPCSPE
, 0, {RT
, RA
, RB
}},
7525 {"stfddx", X(31,931), X_MASK
, E500MC
, 0, {FRS
, RA
, RB
}},
7527 {"stvfrxl", X(31,933), X_MASK
, E6500
, 0, {VS
, RA0
, RB
}},
7529 {"wclrone", XOPL2(31,934,2),XRT_MASK
, PPCA2
, 0, {RA0
, RB
}},
7530 {"wclrall", X(31,934), XRARB_MASK
, PPCA2
, 0, {L2
}},
7531 {"wclr", X(31,934), X_MASK
, PPCA2
, 0, {L2
, RA0
, RB
}},
7533 {"stvrxl", X(31,935), X_MASK
, CELL
, 0, {VS
, RA0
, RB
}},
7535 {"divdeo", XO(31,425,1,0), XO_MASK
, POWER7
|PPCA2
, 0, {RT
, RA
, RB
}},
7536 {"divdeo.", XO(31,425,1,1), XO_MASK
, POWER7
|PPCA2
, 0, {RT
, RA
, RB
}},
7537 {"divweo", XO(31,427,1,0), XO_MASK
, POWER7
|PPCA2
, 0, {RT
, RA
, RB
}},
7538 {"divweo.", XO(31,427,1,1), XO_MASK
, POWER7
|PPCA2
, 0, {RT
, RA
, RB
}},
7540 {"stxvh8x", X(31,940), XX1_MASK
, PPCVSX3
, 0, {XS6
, RA0
, RB
}},
7541 {"stxsihx", X(31,941), XX1_MASK
, PPCVSX3
, 0, {XS6
, RA0
, RB
}},
7543 {"treclaim.", XRC(31,942,1), XRTRB_MASK
, PPCHTM
, 0, {RA
}},
7545 {"tlbrehi", XTLB(31,946,0), XTLB_MASK
, PPC403
, PPCA2
, {RT
, RA
}},
7546 {"tlbrelo", XTLB(31,946,1), XTLB_MASK
, PPC403
, PPCA2
, {RT
, RA
}},
7547 {"tlbre", X(31,946), X_MASK
, PPC403
|BOOKE
|PPCA2
|PPC476
, 0, {RSO
, RAOPT
, SHO
}},
7549 {"sthcix", X(31,949), X_MASK
, POWER6
, 0, {RS
, RA0
, RB
}},
7551 {"icswepx", XRC(31,950,0), X_MASK
, PPCA2
, 0, {RS
, RA
, RB
}},
7552 {"icswepx.", XRC(31,950,1), X_MASK
, PPCA2
, 0, {RS
, RA
, RB
}},
7554 {"stfqux", X(31,951), X_MASK
, POWER2
, 0, {FRS
, RA
, RB
}},
7556 {"sraiq", XRC(31,952,0), X_MASK
, M601
, 0, {RA
, RS
, SH
}},
7557 {"sraiq.", XRC(31,952,1), X_MASK
, M601
, 0, {RA
, RS
, SH
}},
7559 {"extsb", XRC(31,954,0), XRB_MASK
, PPC
, 0, {RA
, RS
}},
7560 {"extsb.", XRC(31,954,1), XRB_MASK
, PPC
, 0, {RA
, RS
}},
7562 {"stvflxl", X(31,965), X_MASK
, E6500
, 0, {VS
, RA0
, RB
}},
7564 {"iccci", X(31,966), XRT_MASK
, PPC403
|PPC440
|PPC476
|TITAN
|PPCA2
, 0, {RAOPT
, RBOPT
}},
7565 {"ici", X(31,966), XRARB_MASK
, PPCA2
|PPC476
, 0, {CT
}},
7567 {"divduo", XO(31,457,1,0), XO_MASK
, PPC64
, 0, {RT
, RA
, RB
}},
7568 {"divduo.", XO(31,457,1,1), XO_MASK
, PPC64
, 0, {RT
, RA
, RB
}},
7570 {"divwuo", XO(31,459,1,0), XO_MASK
, PPC
, 0, {RT
, RA
, RB
}},
7571 {"divwuo.", XO(31,459,1,1), XO_MASK
, PPC
, 0, {RT
, RA
, RB
}},
7573 {"stxvd2x", X(31,972), XX1_MASK
, PPCVSX
, 0, {XS6
, RA0
, RB
}},
7574 {"stxvx", X(31,972), XX1_MASK
, POWER8
, POWER9
|PPCVSX3
, {XS6
, RA0
, RB
}},
7576 {"tlbld", X(31,978), XRTRA_MASK
, PPC
, PPC403
|BOOKE
|PPCA2
|PPC476
, {RB
}},
7577 {"tlbwehi", XTLB(31,978,0), XTLB_MASK
, PPC403
, 0, {RT
, RA
}},
7578 {"tlbwelo", XTLB(31,978,1), XTLB_MASK
, PPC403
, 0, {RT
, RA
}},
7579 {"tlbwe", X(31,978), X_MASK
, PPC403
|BOOKE
|PPCA2
|PPC476
, 0, {RSO
, RAOPT
, SHO
}},
7581 {"slbfee.", XRC(31,979,1), XRA_MASK
, POWER6
, 0, {RT
, RB
}},
7583 {"stbcix", X(31,981), X_MASK
, POWER6
, 0, {RS
, RA0
, RB
}},
7585 {"icbi", X(31,982), XRT_MASK
, PPC
, 0, {RA0
, RB
}},
7587 {"stfiwx", X(31,983), X_MASK
, PPC
, PPCEFS
, {FRS
, RA0
, RB
}},
7589 {"extsw", XRC(31,986,0), XRB_MASK
, PPC64
, 0, {RA
, RS
}},
7590 {"extsw.", XRC(31,986,1), XRB_MASK
, PPC64
, 0, {RA
, RS
}},
7592 {"icbiep", XRT(31,991,0), XRT_MASK
, E500MC
|PPCA2
, 0, {RA0
, RB
}},
7594 {"stvswxl", X(31,997), X_MASK
, E6500
, 0, {VS
, RA0
, RB
}},
7596 {"icread", X(31,998), XRT_MASK
, PPC403
|PPC440
|PPC476
|TITAN
, 0, {RA0
, RB
}},
7598 {"nabso", XO(31,488,1,0), XORB_MASK
, M601
, 0, {RT
, RA
}},
7599 {"nabso.", XO(31,488,1,1), XORB_MASK
, M601
, 0, {RT
, RA
}},
7601 {"divdo", XO(31,489,1,0), XO_MASK
, PPC64
, 0, {RT
, RA
, RB
}},
7602 {"divdo.", XO(31,489,1,1), XO_MASK
, PPC64
, 0, {RT
, RA
, RB
}},
7604 {"divwo", XO(31,491,1,0), XO_MASK
, PPC
, 0, {RT
, RA
, RB
}},
7605 {"divwo.", XO(31,491,1,1), XO_MASK
, PPC
, 0, {RT
, RA
, RB
}},
7607 {"stxvb16x", X(31,1004), XX1_MASK
, PPCVSX3
, 0, {XS6
, RA0
, RB
}},
7609 {"trechkpt.", XRC(31,1006,1), XRTRARB_MASK
,PPCHTM
, 0, {0}},
7611 {"tlbli", X(31,1010), XRTRA_MASK
, PPC
, TITAN
, {RB
}},
7613 {"stdcix", X(31,1013), X_MASK
, POWER6
, 0, {RS
, RA0
, RB
}},
7615 {"dcbz", X(31,1014), XRT_MASK
, PPC
, 0, {RA0
, RB
}},
7616 {"dclz", X(31,1014), XRT_MASK
, PPC
, 0, {RA0
, RB
}},
7618 {"dcbzep", XRT(31,1023,0), XRT_MASK
, E500MC
|PPCA2
, 0, {RA0
, RB
}},
7620 {"dcbzl", XOPL(31,1014,1), XRT_MASK
, POWER4
|E500MC
, PPC476
, {RA0
, RB
}},
7622 {"cctpl", 0x7c210b78, 0xffffffff, CELL
, 0, {0}},
7623 {"cctpm", 0x7c421378, 0xffffffff, CELL
, 0, {0}},
7624 {"cctph", 0x7c631b78, 0xffffffff, CELL
, 0, {0}},
7626 {"dstt", XDSS(31,342,1), XDSS_MASK
, PPCVEC
, 0, {RA
, RB
, STRM
}},
7627 {"dststt", XDSS(31,374,1), XDSS_MASK
, PPCVEC
, 0, {RA
, RB
, STRM
}},
7628 {"dssall", XDSS(31,822,1), XDSS_MASK
, PPCVEC
, 0, {0}},
7630 {"db8cyc", 0x7f9ce378, 0xffffffff, CELL
, 0, {0}},
7631 {"db10cyc", 0x7fbdeb78, 0xffffffff, CELL
, 0, {0}},
7632 {"db12cyc", 0x7fdef378, 0xffffffff, CELL
, 0, {0}},
7633 {"db16cyc", 0x7ffffb78, 0xffffffff, CELL
, 0, {0}},
7635 {"lwz", OP(32), OP_MASK
, PPCCOM
, PPCVLE
, {RT
, D
, RA0
}},
7636 {"l", OP(32), OP_MASK
, PWRCOM
, PPCVLE
, {RT
, D
, RA0
}},
7638 {"lwzu", OP(33), OP_MASK
, PPCCOM
, PPCVLE
, {RT
, D
, RAL
}},
7639 {"lu", OP(33), OP_MASK
, PWRCOM
, PPCVLE
, {RT
, D
, RA0
}},
7641 {"lbz", OP(34), OP_MASK
, COM
, PPCVLE
, {RT
, D
, RA0
}},
7643 {"lbzu", OP(35), OP_MASK
, COM
, PPCVLE
, {RT
, D
, RAL
}},
7645 {"stw", OP(36), OP_MASK
, PPCCOM
, PPCVLE
, {RS
, D
, RA0
}},
7646 {"st", OP(36), OP_MASK
, PWRCOM
, PPCVLE
, {RS
, D
, RA0
}},
7648 {"stwu", OP(37), OP_MASK
, PPCCOM
, PPCVLE
, {RS
, D
, RAS
}},
7649 {"stu", OP(37), OP_MASK
, PWRCOM
, PPCVLE
, {RS
, D
, RA0
}},
7651 {"stb", OP(38), OP_MASK
, COM
, PPCVLE
, {RS
, D
, RA0
}},
7653 {"stbu", OP(39), OP_MASK
, COM
, PPCVLE
, {RS
, D
, RAS
}},
7655 {"lhz", OP(40), OP_MASK
, COM
, PPCVLE
, {RT
, D
, RA0
}},
7657 {"lhzu", OP(41), OP_MASK
, COM
, PPCVLE
, {RT
, D
, RAL
}},
7659 {"lha", OP(42), OP_MASK
, COM
, PPCVLE
, {RT
, D
, RA0
}},
7661 {"lhau", OP(43), OP_MASK
, COM
, PPCVLE
, {RT
, D
, RAL
}},
7663 {"sth", OP(44), OP_MASK
, COM
, PPCVLE
, {RS
, D
, RA0
}},
7665 {"sthu", OP(45), OP_MASK
, COM
, PPCVLE
, {RS
, D
, RAS
}},
7667 {"lmw", OP(46), OP_MASK
, PPCCOM
, PPCVLE
, {RT
, D
, RAM
}},
7668 {"lm", OP(46), OP_MASK
, PWRCOM
, PPCVLE
, {RT
, D
, RA0
}},
7670 {"stmw", OP(47), OP_MASK
, PPCCOM
, PPCVLE
, {RS
, D
, RA0
}},
7671 {"stm", OP(47), OP_MASK
, PWRCOM
, PPCVLE
, {RS
, D
, RA0
}},
7673 {"lfs", OP(48), OP_MASK
, COM
, PPCEFS
|PPCVLE
, {FRT
, D
, RA0
}},
7675 {"lfsu", OP(49), OP_MASK
, COM
, PPCEFS
|PPCVLE
, {FRT
, D
, RAS
}},
7677 {"lfd", OP(50), OP_MASK
, COM
, PPCEFS
|PPCVLE
, {FRT
, D
, RA0
}},
7679 {"lfdu", OP(51), OP_MASK
, COM
, PPCEFS
|PPCVLE
, {FRT
, D
, RAS
}},
7681 {"stfs", OP(52), OP_MASK
, COM
, PPCEFS
|PPCVLE
, {FRS
, D
, RA0
}},
7683 {"stfsu", OP(53), OP_MASK
, COM
, PPCEFS
|PPCVLE
, {FRS
, D
, RAS
}},
7685 {"stfd", OP(54), OP_MASK
, COM
, PPCEFS
|PPCVLE
, {FRS
, D
, RA0
}},
7687 {"stfdu", OP(55), OP_MASK
, COM
, PPCEFS
|PPCVLE
, {FRS
, D
, RAS
}},
7689 {"lq", OP(56), OP_MASK
|Q_MASK
, POWER4
, PPC476
|PPCVLE
, {RTQ
, DQ
, RAQ
}},
7690 {"psq_l", OP(56), OP_MASK
, PPCPS
, PPCVLE
, {FRT
,PSD
,RA
,PSW
,PSQ
}},
7691 {"lfq", OP(56), OP_MASK
, POWER2
, PPCVLE
, {FRT
, D
, RA0
}},
7693 {"lxsd", DSO(57,2), DS_MASK
, PPCVSX3
, PPCVLE
, {VD
, DS
, RA0
}},
7694 {"lxssp", DSO(57,3), DS_MASK
, PPCVSX3
, PPCVLE
, {VD
, DS
, RA0
}},
7695 {"lfdp", OP(57), OP_MASK
|Q_MASK
, POWER6
, POWER7
|PPCVLE
, {FRTp
, DS
, RA0
}},
7696 {"psq_lu", OP(57), OP_MASK
, PPCPS
, PPCVLE
, {FRT
,PSD
,RA
,PSW
,PSQ
}},
7697 {"lfqu", OP(57), OP_MASK
, POWER2
, PPCVLE
, {FRT
, D
, RA0
}},
7699 {"ld", DSO(58,0), DS_MASK
, PPC64
, PPCVLE
, {RT
, DS
, RA0
}},
7700 {"ldu", DSO(58,1), DS_MASK
, PPC64
, PPCVLE
, {RT
, DS
, RAL
}},
7701 {"lwa", DSO(58,2), DS_MASK
, PPC64
, PPCVLE
, {RT
, DS
, RA0
}},
7703 {"dadd", XRC(59,2,0), X_MASK
, POWER6
, PPCVLE
, {FRT
, FRA
, FRB
}},
7704 {"dadd.", XRC(59,2,1), X_MASK
, POWER6
, PPCVLE
, {FRT
, FRA
, FRB
}},
7706 {"dqua", ZRC(59,3,0), Z2_MASK
, POWER6
, PPCVLE
, {FRT
,FRA
,FRB
,RMC
}},
7707 {"dqua.", ZRC(59,3,1), Z2_MASK
, POWER6
, PPCVLE
, {FRT
,FRA
,FRB
,RMC
}},
7709 {"xvi8ger4pp", XX3(59,2), XX3_MASK
|3<<21, POWER10
, PPCVLE
, {ACC
, XA6a
, XB6a
}},
7710 {"xvi8ger4", XX3(59,3), XX3_MASK
|3<<21, POWER10
, PPCVLE
, {ACC
, XA6a
, XB6a
}},
7712 {"fdivs", A(59,18,0), AFRC_MASK
, PPC
, PPCEFS
|PPCVLE
, {FRT
, FRA
, FRB
}},
7713 {"fdivs.", A(59,18,1), AFRC_MASK
, PPC
, PPCEFS
|PPCVLE
, {FRT
, FRA
, FRB
}},
7715 {"fsubs", A(59,20,0), AFRC_MASK
, PPC
, PPCEFS
|PPCVLE
, {FRT
, FRA
, FRB
}},
7716 {"fsubs.", A(59,20,1), AFRC_MASK
, PPC
, PPCEFS
|PPCVLE
, {FRT
, FRA
, FRB
}},
7718 {"fadds", A(59,21,0), AFRC_MASK
, PPC
, PPCEFS
|PPCVLE
, {FRT
, FRA
, FRB
}},
7719 {"fadds.", A(59,21,1), AFRC_MASK
, PPC
, PPCEFS
|PPCVLE
, {FRT
, FRA
, FRB
}},
7721 {"fsqrts", A(59,22,0), AFRAFRC_MASK
, PPC
, TITAN
|PPCVLE
, {FRT
, FRB
}},
7722 {"fsqrts.", A(59,22,1), AFRAFRC_MASK
, PPC
, TITAN
|PPCVLE
, {FRT
, FRB
}},
7724 {"fres", A(59,24,0), AFRAFRC_MASK
, POWER7
, PPCVLE
, {FRT
, FRB
}},
7725 {"fres", A(59,24,0), AFRALFRC_MASK
, PPC
, POWER7
|PPCVLE
, {FRT
, FRB
, A_L
}},
7726 {"fres.", A(59,24,1), AFRAFRC_MASK
, POWER7
, PPCVLE
, {FRT
, FRB
}},
7727 {"fres.", A(59,24,1), AFRALFRC_MASK
, PPC
, POWER7
|PPCVLE
, {FRT
, FRB
, A_L
}},
7729 {"fmuls", A(59,25,0), AFRB_MASK
, PPC
, PPCEFS
|PPCVLE
, {FRT
, FRA
, FRC
}},
7730 {"fmuls.", A(59,25,1), AFRB_MASK
, PPC
, PPCEFS
|PPCVLE
, {FRT
, FRA
, FRC
}},
7732 {"frsqrtes", A(59,26,0), AFRAFRC_MASK
, POWER7
, PPCVLE
, {FRT
, FRB
}},
7733 {"frsqrtes", A(59,26,0), AFRALFRC_MASK
, POWER5
, POWER7
|PPCVLE
, {FRT
, FRB
, A_L
}},
7734 {"frsqrtes.", A(59,26,1), AFRAFRC_MASK
, POWER7
, PPCVLE
, {FRT
, FRB
}},
7735 {"frsqrtes.", A(59,26,1), AFRALFRC_MASK
, POWER5
, POWER7
|PPCVLE
, {FRT
, FRB
, A_L
}},
7737 {"fmsubs", A(59,28,0), A_MASK
, PPC
, PPCEFS
|PPCVLE
, {FRT
, FRA
, FRC
, FRB
}},
7738 {"fmsubs.", A(59,28,1), A_MASK
, PPC
, PPCEFS
|PPCVLE
, {FRT
, FRA
, FRC
, FRB
}},
7740 {"fmadds", A(59,29,0), A_MASK
, PPC
, PPCEFS
|PPCVLE
, {FRT
, FRA
, FRC
, FRB
}},
7741 {"fmadds.", A(59,29,1), A_MASK
, PPC
, PPCEFS
|PPCVLE
, {FRT
, FRA
, FRC
, FRB
}},
7743 {"fnmsubs", A(59,30,0), A_MASK
, PPC
, PPCEFS
|PPCVLE
, {FRT
, FRA
, FRC
, FRB
}},
7744 {"fnmsubs.", A(59,30,1), A_MASK
, PPC
, PPCEFS
|PPCVLE
, {FRT
, FRA
, FRC
, FRB
}},
7746 {"fnmadds", A(59,31,0), A_MASK
, PPC
, PPCEFS
|PPCVLE
, {FRT
, FRA
, FRC
, FRB
}},
7747 {"fnmadds.", A(59,31,1), A_MASK
, PPC
, PPCEFS
|PPCVLE
, {FRT
, FRA
, FRC
, FRB
}},
7749 {"dmul", XRC(59,34,0), X_MASK
, POWER6
, PPCVLE
, {FRT
, FRA
, FRB
}},
7750 {"dmul.", XRC(59,34,1), X_MASK
, POWER6
, PPCVLE
, {FRT
, FRA
, FRB
}},
7752 {"drrnd", ZRC(59,35,0), Z2_MASK
, POWER6
, PPCVLE
, {FRT
, FRA
, FRB
, RMC
}},
7753 {"drrnd.", ZRC(59,35,1), Z2_MASK
, POWER6
, PPCVLE
, {FRT
, FRA
, FRB
, RMC
}},
7755 {"dscli", ZRC(59,66,0), Z_MASK
, POWER6
, PPCVLE
, {FRT
, FRA
, SH16
}},
7756 {"dscli.", ZRC(59,66,1), Z_MASK
, POWER6
, PPCVLE
, {FRT
, FRA
, SH16
}},
7758 {"dquai", ZRC(59,67,0), Z2_MASK
, POWER6
, PPCVLE
, {TE
, FRT
,FRB
,RMC
}},
7759 {"dquai.", ZRC(59,67,1), Z2_MASK
, POWER6
, PPCVLE
, {TE
, FRT
,FRB
,RMC
}},
7761 {"xvf16ger2pp", XX3(59,18), XX3_MASK
|3<<21, POWER10
, PPCVLE
, {ACC
, XA6a
, XB6a
}},
7762 {"xvf16ger2", XX3(59,19), XX3_MASK
|3<<21, POWER10
, PPCVLE
, {ACC
, XA6a
, XB6a
}},
7764 {"dscri", ZRC(59,98,0), Z_MASK
, POWER6
, PPCVLE
, {FRT
, FRA
, SH16
}},
7765 {"dscri.", ZRC(59,98,1), Z_MASK
, POWER6
, PPCVLE
, {FRT
, FRA
, SH16
}},
7767 {"drintx", ZRC(59,99,0), Z2_MASK
, POWER6
, PPCVLE
, {R
, FRT
, FRB
, RMC
}},
7768 {"drintx.", ZRC(59,99,1), Z2_MASK
, POWER6
, PPCVLE
, {R
, FRT
, FRB
, RMC
}},
7770 {"xvf32gerpp", XX3(59,26), XX3_MASK
|3<<21, POWER10
, PPCVLE
, {ACC
, XA6a
, XB6a
}},
7771 {"xvf32ger", XX3(59,27), XX3_MASK
|3<<21, POWER10
, PPCVLE
, {ACC
, XA6a
, XB6a
}},
7773 {"dcmpo", X(59,130), X_MASK
, POWER6
, PPCVLE
, {BF
, FRA
, FRB
}},
7775 {"xvi4ger8pp", XX3(59,34), XX3_MASK
|3<<21, POWER10
, PPCVLE
, {ACC
, XA6a
, XB6a
}},
7776 {"xvi4ger8", XX3(59,35), XX3_MASK
|3<<21, POWER10
, PPCVLE
, {ACC
, XA6a
, XB6a
}},
7778 {"dtstex", X(59,162), X_MASK
, POWER6
, PPCVLE
, {BF
, FRA
, FRB
}},
7780 {"xvi16ger2spp", XX3(59,42), XX3_MASK
|3<<21, POWER10
, PPCVLE
, {ACC
, XA6a
, XB6a
}},
7781 {"xvi16ger2s", XX3(59,43), XX3_MASK
|3<<21, POWER10
, PPCVLE
, {ACC
, XA6a
, XB6a
}},
7783 {"dtstdc", Z(59,194), Z_MASK
, POWER6
, PPCVLE
, {BF
, FRA
, DCM
}},
7785 {"xvbf16ger2pp",XX3(59,50), XX3_MASK
|3<<21, POWER10
, PPCVLE
, {ACC
, XA6a
, XB6a
}},
7786 {"xvbf16ger2", XX3(59,51), XX3_MASK
|3<<21, POWER10
, PPCVLE
, {ACC
, XA6a
, XB6a
}},
7788 {"dtstdg", Z(59,226), Z_MASK
, POWER6
, PPCVLE
, {BF
, FRA
, DGM
}},
7790 {"drintn", ZRC(59,227,0), Z2_MASK
, POWER6
, PPCVLE
, {R
, FRT
, FRB
, RMC
}},
7791 {"drintn.", ZRC(59,227,1), Z2_MASK
, POWER6
, PPCVLE
, {R
, FRT
, FRB
, RMC
}},
7793 {"xvf64gerpp", XX3(59,58), XX3_MASK
|3<<21, POWER10
, PPCVLE
, {ACC
, XA6ap
, XB6a
}},
7794 {"xvf64ger", XX3(59,59), XX3_MASK
|3<<21, POWER10
, PPCVLE
, {ACC
, XA6ap
, XB6a
}},
7796 {"dctdp", XRC(59,258,0), X_MASK
, POWER6
, PPCVLE
, {FRT
, FRB
}},
7797 {"dctdp.", XRC(59,258,1), X_MASK
, POWER6
, PPCVLE
, {FRT
, FRB
}},
7799 {"dctfix", XRC(59,290,0), X_MASK
, POWER6
, PPCVLE
, {FRT
, FRB
}},
7800 {"dctfix.", XRC(59,290,1), X_MASK
, POWER6
, PPCVLE
, {FRT
, FRB
}},
7802 {"ddedpd", XRC(59,322,0), X_MASK
, POWER6
, PPCVLE
, {SP
, FRT
, FRB
}},
7803 {"ddedpd.", XRC(59,322,1), X_MASK
, POWER6
, PPCVLE
, {SP
, FRT
, FRB
}},
7805 {"xvi16ger2", XX3(59,75), XX3_MASK
|3<<21, POWER10
, PPCVLE
, {ACC
, XA6a
, XB6a
}},
7807 {"xvf16ger2np", XX3(59,82), XX3_MASK
|3<<21, POWER10
, PPCVLE
, {ACC
, XA6a
, XB6a
}},
7809 {"dxex", XRC(59,354,0), X_MASK
, POWER6
, PPCVLE
, {FRT
, FRB
}},
7810 {"dxex.", XRC(59,354,1), X_MASK
, POWER6
, PPCVLE
, {FRT
, FRB
}},
7812 {"xvf32gernp", XX3(59,90), XX3_MASK
|3<<21, POWER10
, PPCVLE
, {ACC
, XA6a
, XB6a
}},
7814 {"xvi8ger4spp", XX3(59,99), XX3_MASK
|3<<21, POWER10
, PPCVLE
, {ACC
, XA6a
, XB6a
}},
7816 {"xvi16ger2pp", XX3(59,107), XX3_MASK
|3<<21, POWER10
, PPCVLE
, {ACC
, XA6a
, XB6a
}},
7818 {"xvbf16ger2np",XX3(59,114), XX3_MASK
|3<<21, POWER10
, PPCVLE
, {ACC
, XA6a
, XB6a
}},
7820 {"xvf64gernp", XX3(59,122), XX3_MASK
|3<<21, POWER10
, PPCVLE
, {ACC
, XA6ap
, XB6a
}},
7822 {"dsub", XRC(59,514,0), X_MASK
, POWER6
, PPCVLE
, {FRT
, FRA
, FRB
}},
7823 {"dsub.", XRC(59,514,1), X_MASK
, POWER6
, PPCVLE
, {FRT
, FRA
, FRB
}},
7825 {"ddiv", XRC(59,546,0), X_MASK
, POWER6
, PPCVLE
, {FRT
, FRA
, FRB
}},
7826 {"ddiv.", XRC(59,546,1), X_MASK
, POWER6
, PPCVLE
, {FRT
, FRA
, FRB
}},
7828 {"xvf16ger2pn", XX3(59,146), XX3_MASK
|3<<21, POWER10
, PPCVLE
, {ACC
, XA6a
, XB6a
}},
7830 {"xvf32gerpn", XX3(59,154), XX3_MASK
|3<<21, POWER10
, PPCVLE
, {ACC
, XA6a
, XB6a
}},
7832 {"dcmpu", X(59,642), X_MASK
, POWER6
, PPCVLE
, {BF
, FRA
, FRB
}},
7834 {"dtstsf", X(59,674), X_MASK
, POWER6
, PPCVLE
, {BF
, FRA
, FRB
}},
7835 {"dtstsfi", X(59,675), X_MASK
|1<<22,POWER9
, PPCVLE
, {BF
, UIM6
, FRB
}},
7837 {"xvbf16ger2pn",XX3(59,178), XX3_MASK
|3<<21, POWER10
, PPCVLE
, {ACC
, XA6a
, XB6a
}},
7839 {"xvf64gerpn", XX3(59,186), XX3_MASK
|3<<21, POWER10
, PPCVLE
, {ACC
, XA6ap
, XB6a
}},
7841 {"drsp", XRC(59,770,0), X_MASK
, POWER6
, PPCVLE
, {FRT
, FRB
}},
7842 {"drsp.", XRC(59,770,1), X_MASK
, POWER6
, PPCVLE
, {FRT
, FRB
}},
7844 {"dcffix", XRC(59,802,0), X_MASK
|FRA_MASK
, POWER7
, PPCVLE
, {FRT
, FRB
}},
7845 {"dcffix.", XRC(59,802,1), X_MASK
|FRA_MASK
, POWER7
, PPCVLE
, {FRT
, FRB
}},
7847 {"denbcd", XRC(59,834,0), X_MASK
, POWER6
, PPCVLE
, {S
, FRT
, FRB
}},
7848 {"denbcd.", XRC(59,834,1), X_MASK
, POWER6
, PPCVLE
, {S
, FRT
, FRB
}},
7850 {"xvf16ger2nn", XX3(59,210), XX3_MASK
|3<<21, POWER10
, PPCVLE
, {ACC
, XA6a
, XB6a
}},
7852 {"fcfids", XRC(59,846,0), XRA_MASK
, POWER7
|PPCA2
, PPCVLE
, {FRT
, FRB
}},
7853 {"fcfids.", XRC(59,846,1), XRA_MASK
, POWER7
|PPCA2
, PPCVLE
, {FRT
, FRB
}},
7855 {"diex", XRC(59,866,0), X_MASK
, POWER6
, PPCVLE
, {FRT
, FRA
, FRB
}},
7856 {"diex.", XRC(59,866,1), X_MASK
, POWER6
, PPCVLE
, {FRT
, FRA
, FRB
}},
7858 {"xvf32gernn", XX3(59,218), XX3_MASK
|3<<21, POWER10
, PPCVLE
, {ACC
, XA6a
, XB6a
}},
7860 {"xvbf16ger2nn",XX3(59,242), XX3_MASK
|3<<21, POWER10
, PPCVLE
, {ACC
, XA6a
, XB6a
}},
7862 {"fcfidus", XRC(59,974,0), XRA_MASK
, POWER7
|PPCA2
, PPCVLE
, {FRT
, FRB
}},
7863 {"fcfidus.", XRC(59,974,1), XRA_MASK
, POWER7
|PPCA2
, PPCVLE
, {FRT
, FRB
}},
7865 {"xvf64gernn", XX3(59,250), XX3_MASK
|3<<21, POWER10
, PPCVLE
, {ACC
, XA6ap
, XB6a
}},
7867 {"xsaddsp", XX3(60,0), XX3_MASK
, PPCVSX2
, PPCVLE
, {XT6
, XA6
, XB6
}},
7868 {"xsmaddasp", XX3(60,1), XX3_MASK
, PPCVSX2
, PPCVLE
, {XT6
, XA6
, XB6
}},
7869 {"xxsldwi", XX3(60,2), XX3SHW_MASK
, PPCVSX
, PPCVLE
, {XT6
, XA6
, XB6
, SHW
}},
7870 {"xscmpeqdp", XX3(60,3), XX3_MASK
, PPCVSX3
, PPCVLE
, {XT6
, XA6
, XB6
}},
7871 {"xsrsqrtesp", XX2(60,10), XX2_MASK
, PPCVSX2
, PPCVLE
, {XT6
, XB6
}},
7872 {"xssqrtsp", XX2(60,11), XX2_MASK
, PPCVSX2
, PPCVLE
, {XT6
, XB6
}},
7873 {"xxsel", XX4(60,3), XX4_MASK
, PPCVSX
, PPCVLE
, {XT6
, XA6
, XB6
, XC6
}},
7874 {"xssubsp", XX3(60,8), XX3_MASK
, PPCVSX2
, PPCVLE
, {XT6
, XA6
, XB6
}},
7875 {"xsmaddmsp", XX3(60,9), XX3_MASK
, PPCVSX2
, PPCVLE
, {XT6
, XA6
, XB6
}},
7876 {"xxspltd", XX3(60,10), XX3DM_MASK
, PPCVSX
, PPCVLE
, {XT6
, XAB6
, DMEX
}},
7877 {"xxmrghd", XX3(60,10), XX3_MASK
, PPCVSX
, PPCVLE
, {XT6
, XA6
, XB6
}},
7878 {"xxswapd", XX3(60,10)|(2<<8), XX3_MASK
, PPCVSX
, PPCVLE
, {XT6
, XAB6
}},
7879 {"xxmrgld", XX3(60,10)|(3<<8), XX3_MASK
, PPCVSX
, PPCVLE
, {XT6
, XA6
, XB6
}},
7880 {"xxpermdi", XX3(60,10), XX3DM_MASK
, PPCVSX
, PPCVLE
, {XT6
, XA6
, XB6
, DM
}},
7881 {"xscmpgtdp", XX3(60,11), XX3_MASK
, PPCVSX3
, PPCVLE
, {XT6
, XA6
, XB6
}},
7882 {"xsresp", XX2(60,26), XX2_MASK
, PPCVSX2
, PPCVLE
, {XT6
, XB6
}},
7883 {"xsmulsp", XX3(60,16), XX3_MASK
, PPCVSX2
, PPCVLE
, {XT6
, XA6
, XB6
}},
7884 {"xsmsubasp", XX3(60,17), XX3_MASK
, PPCVSX2
, PPCVLE
, {XT6
, XA6
, XB6
}},
7885 {"xxmrghw", XX3(60,18), XX3_MASK
, PPCVSX
, PPCVLE
, {XT6
, XA6
, XB6
}},
7886 {"xscmpgedp", XX3(60,19), XX3_MASK
, PPCVSX3
, PPCVLE
, {XT6
, XA6
, XB6
}},
7887 {"xsdivsp", XX3(60,24), XX3_MASK
, PPCVSX2
, PPCVLE
, {XT6
, XA6
, XB6
}},
7888 {"xsmsubmsp", XX3(60,25), XX3_MASK
, PPCVSX2
, PPCVLE
, {XT6
, XA6
, XB6
}},
7889 {"xxperm", XX3(60,26), XX3_MASK
, PPCVSX3
, PPCVLE
, {XT6
, XA6
, XB6
}},
7890 {"xsadddp", XX3(60,32), XX3_MASK
, PPCVSX
, PPCVLE
, {XT6
, XA6
, XB6
}},
7891 {"xsmaddadp", XX3(60,33), XX3_MASK
, PPCVSX
, PPCVLE
, {XT6
, XA6
, XB6
}},
7892 {"xscmpudp", XX3(60,35), XX3BF_MASK
, PPCVSX
, PPCVLE
, {BF
, XA6
, XB6
}},
7893 {"xscvdpuxws", XX2(60,72), XX2_MASK
, PPCVSX
, PPCVLE
, {XT6
, XB6
}},
7894 {"xsrdpi", XX2(60,73), XX2_MASK
, PPCVSX
, PPCVLE
, {XT6
, XB6
}},
7895 {"xsrsqrtedp", XX2(60,74), XX2_MASK
, PPCVSX
, PPCVLE
, {XT6
, XB6
}},
7896 {"xssqrtdp", XX2(60,75), XX2_MASK
, PPCVSX
, PPCVLE
, {XT6
, XB6
}},
7897 {"xssubdp", XX3(60,40), XX3_MASK
, PPCVSX
, PPCVLE
, {XT6
, XA6
, XB6
}},
7898 {"xsmaddmdp", XX3(60,41), XX3_MASK
, PPCVSX
, PPCVLE
, {XT6
, XA6
, XB6
}},
7899 {"xscmpodp", XX3(60,43), XX3BF_MASK
, PPCVSX
, PPCVLE
, {BF
, XA6
, XB6
}},
7900 {"xscvdpsxws", XX2(60,88), XX2_MASK
, PPCVSX
, PPCVLE
, {XT6
, XB6
}},
7901 {"xsrdpiz", XX2(60,89), XX2_MASK
, PPCVSX
, PPCVLE
, {XT6
, XB6
}},
7902 {"xsredp", XX2(60,90), XX2_MASK
, PPCVSX
, PPCVLE
, {XT6
, XB6
}},
7903 {"xsmuldp", XX3(60,48), XX3_MASK
, PPCVSX
, PPCVLE
, {XT6
, XA6
, XB6
}},
7904 {"xsmsubadp", XX3(60,49), XX3_MASK
, PPCVSX
, PPCVLE
, {XT6
, XA6
, XB6
}},
7905 {"xxmrglw", XX3(60,50), XX3_MASK
, PPCVSX
, PPCVLE
, {XT6
, XA6
, XB6
}},
7906 {"xsrdpip", XX2(60,105), XX2_MASK
, PPCVSX
, PPCVLE
, {XT6
, XB6
}},
7907 {"xstsqrtdp", XX2(60,106), XX2BF_MASK
, PPCVSX
, PPCVLE
, {BF
, XB6
}},
7908 {"xsrdpic", XX2(60,107), XX2_MASK
, PPCVSX
, PPCVLE
, {XT6
, XB6
}},
7909 {"xsdivdp", XX3(60,56), XX3_MASK
, PPCVSX
, PPCVLE
, {XT6
, XA6
, XB6
}},
7910 {"xsmsubmdp", XX3(60,57), XX3_MASK
, PPCVSX
, PPCVLE
, {XT6
, XA6
, XB6
}},
7911 {"xxpermr", XX3(60,58), XX3_MASK
, PPCVSX3
, PPCVLE
, {XT6
, XA6
, XB6
}},
7912 {"xscmpexpdp", XX3(60,59), XX3BF_MASK
, PPCVSX3
, PPCVLE
, {BF
, XA6
, XB6
}},
7913 {"xsrdpim", XX2(60,121), XX2_MASK
, PPCVSX
, PPCVLE
, {XT6
, XB6
}},
7914 {"xstdivdp", XX3(60,61), XX3BF_MASK
, PPCVSX
, PPCVLE
, {BF
, XA6
, XB6
}},
7915 {"xvaddsp", XX3(60,64), XX3_MASK
, PPCVSX
, PPCVLE
, {XT6
, XA6
, XB6
}},
7916 {"xvmaddasp", XX3(60,65), XX3_MASK
, PPCVSX
, PPCVLE
, {XT6
, XA6
, XB6
}},
7917 {"xvcmpeqsp", XX3RC(60,67,0), XX3_MASK
, PPCVSX
, PPCVLE
, {XT6
, XA6
, XB6
}},
7918 {"xvcmpeqsp.", XX3RC(60,67,1), XX3_MASK
, PPCVSX
, PPCVLE
, {XT6
, XA6
, XB6
}},
7919 {"xvcvspuxws", XX2(60,136), XX2_MASK
, PPCVSX
, PPCVLE
, {XT6
, XB6
}},
7920 {"xvrspi", XX2(60,137), XX2_MASK
, PPCVSX
, PPCVLE
, {XT6
, XB6
}},
7921 {"xvrsqrtesp", XX2(60,138), XX2_MASK
, PPCVSX
, PPCVLE
, {XT6
, XB6
}},
7922 {"xvsqrtsp", XX2(60,139), XX2_MASK
, PPCVSX
, PPCVLE
, {XT6
, XB6
}},
7923 {"xvsubsp", XX3(60,72), XX3_MASK
, PPCVSX
, PPCVLE
, {XT6
, XA6
, XB6
}},
7924 {"xvmaddmsp", XX3(60,73), XX3_MASK
, PPCVSX
, PPCVLE
, {XT6
, XA6
, XB6
}},
7925 {"xvcmpgtsp", XX3RC(60,75,0), XX3_MASK
, PPCVSX
, PPCVLE
, {XT6
, XA6
, XB6
}},
7926 {"xvcmpgtsp.", XX3RC(60,75,1), XX3_MASK
, PPCVSX
, PPCVLE
, {XT6
, XA6
, XB6
}},
7927 {"xvcvspsxws", XX2(60,152), XX2_MASK
, PPCVSX
, PPCVLE
, {XT6
, XB6
}},
7928 {"xvrspiz", XX2(60,153), XX2_MASK
, PPCVSX
, PPCVLE
, {XT6
, XB6
}},
7929 {"xvresp", XX2(60,154), XX2_MASK
, PPCVSX
, PPCVLE
, {XT6
, XB6
}},
7930 {"xvmulsp", XX3(60,80), XX3_MASK
, PPCVSX
, PPCVLE
, {XT6
, XA6
, XB6
}},
7931 {"xvmsubasp", XX3(60,81), XX3_MASK
, PPCVSX
, PPCVLE
, {XT6
, XA6
, XB6
}},
7932 {"xxspltw", XX2(60,164), XX2UIM_MASK
, PPCVSX
, PPCVLE
, {XT6
, XB6
, UIM
}},
7933 {"xxextractuw", XX2(60,165), XX2UIM4_MASK
, PPCVSX3
, PPCVLE
, {XT6
, XB6
, UIMM4
}},
7934 {"xvcmpgesp", XX3RC(60,83,0), XX3_MASK
, PPCVSX
, PPCVLE
, {XT6
, XA6
, XB6
}},
7935 {"xvcmpgesp.", XX3RC(60,83,1), XX3_MASK
, PPCVSX
, PPCVLE
, {XT6
, XA6
, XB6
}},
7936 {"xvcvuxwsp", XX2(60,168), XX2_MASK
, PPCVSX
, PPCVLE
, {XT6
, XB6
}},
7937 {"xvrspip", XX2(60,169), XX2_MASK
, PPCVSX
, PPCVLE
, {XT6
, XB6
}},
7938 {"xvtsqrtsp", XX2(60,170), XX2BF_MASK
, PPCVSX
, PPCVLE
, {BF
, XB6
}},
7939 {"xvrspic", XX2(60,171), XX2_MASK
, PPCVSX
, PPCVLE
, {XT6
, XB6
}},
7940 {"xvdivsp", XX3(60,88), XX3_MASK
, PPCVSX
, PPCVLE
, {XT6
, XA6
, XB6
}},
7941 {"xvmsubmsp", XX3(60,89), XX3_MASK
, PPCVSX
, PPCVLE
, {XT6
, XA6
, XB6
}},
7942 {"xxspltib", X(60,360), XX1_MASK
|3<<19, PPCVSX3
, PPCVLE
, {XT6
, IMM8
}},
7943 {"lxvkq", XVA(60,360,31), XVA_MASK
&~1, POWER10
, PPCVLE
, {XT6
, UIM5
}},
7944 {"xxinsertw", XX2(60,181), XX2UIM4_MASK
, PPCVSX3
, PPCVLE
, {XT6
, XB6
, UIMM4
}},
7945 {"xvcvsxwsp", XX2(60,184), XX2_MASK
, PPCVSX
, PPCVLE
, {XT6
, XB6
}},
7946 {"xvrspim", XX2(60,185), XX2_MASK
, PPCVSX
, PPCVLE
, {XT6
, XB6
}},
7947 {"xvtdivsp", XX3(60,93), XX3BF_MASK
, PPCVSX
, PPCVLE
, {BF
, XA6
, XB6
}},
7948 {"xvadddp", XX3(60,96), XX3_MASK
, PPCVSX
, PPCVLE
, {XT6
, XA6
, XB6
}},
7949 {"xvmaddadp", XX3(60,97), XX3_MASK
, PPCVSX
, PPCVLE
, {XT6
, XA6
, XB6
}},
7950 {"xvcmpeqdp", XX3RC(60,99,0), XX3_MASK
, PPCVSX
, PPCVLE
, {XT6
, XA6
, XB6
}},
7951 {"xvcmpeqdp.", XX3RC(60,99,1), XX3_MASK
, PPCVSX
, PPCVLE
, {XT6
, XA6
, XB6
}},
7952 {"xvcvdpuxws", XX2(60,200), XX2_MASK
, PPCVSX
, PPCVLE
, {XT6
, XB6
}},
7953 {"xvrdpi", XX2(60,201), XX2_MASK
, PPCVSX
, PPCVLE
, {XT6
, XB6
}},
7954 {"xvrsqrtedp", XX2(60,202), XX2_MASK
, PPCVSX
, PPCVLE
, {XT6
, XB6
}},
7955 {"xvsqrtdp", XX2(60,203), XX2_MASK
, PPCVSX
, PPCVLE
, {XT6
, XB6
}},
7956 {"xvsubdp", XX3(60,104), XX3_MASK
, PPCVSX
, PPCVLE
, {XT6
, XA6
, XB6
}},
7957 {"xvmaddmdp", XX3(60,105), XX3_MASK
, PPCVSX
, PPCVLE
, {XT6
, XA6
, XB6
}},
7958 {"xvcmpgtdp", XX3RC(60,107,0), XX3_MASK
, PPCVSX
, PPCVLE
, {XT6
, XA6
, XB6
}},
7959 {"xvcmpgtdp.", XX3RC(60,107,1), XX3_MASK
, PPCVSX
, PPCVLE
, {XT6
, XA6
, XB6
}},
7960 {"xvcvdpsxws", XX2(60,216), XX2_MASK
, PPCVSX
, PPCVLE
, {XT6
, XB6
}},
7961 {"xvrdpiz", XX2(60,217), XX2_MASK
, PPCVSX
, PPCVLE
, {XT6
, XB6
}},
7962 {"xvredp", XX2(60,218), XX2_MASK
, PPCVSX
, PPCVLE
, {XT6
, XB6
}},
7963 {"xvmuldp", XX3(60,112), XX3_MASK
, PPCVSX
, PPCVLE
, {XT6
, XA6
, XB6
}},
7964 {"xvmsubadp", XX3(60,113), XX3_MASK
, PPCVSX
, PPCVLE
, {XT6
, XA6
, XB6
}},
7965 {"xvcmpgedp", XX3RC(60,115,0), XX3_MASK
, PPCVSX
, PPCVLE
, {XT6
, XA6
, XB6
}},
7966 {"xvcmpgedp.", XX3RC(60,115,1), XX3_MASK
, PPCVSX
, PPCVLE
, {XT6
, XA6
, XB6
}},
7967 {"xvcvuxwdp", XX2(60,232), XX2_MASK
, PPCVSX
, PPCVLE
, {XT6
, XB6
}},
7968 {"xvrdpip", XX2(60,233), XX2_MASK
, PPCVSX
, PPCVLE
, {XT6
, XB6
}},
7969 {"xvtsqrtdp", XX2(60,234), XX2BF_MASK
, PPCVSX
, PPCVLE
, {BF
, XB6
}},
7970 {"xvrdpic", XX2(60,235), XX2_MASK
, PPCVSX
, PPCVLE
, {XT6
, XB6
}},
7971 {"xvdivdp", XX3(60,120), XX3_MASK
, PPCVSX
, PPCVLE
, {XT6
, XA6
, XB6
}},
7972 {"xvmsubmdp", XX3(60,121), XX3_MASK
, PPCVSX
, PPCVLE
, {XT6
, XA6
, XB6
}},
7973 {"xvcvsxwdp", XX2(60,248), XX2_MASK
, PPCVSX
, PPCVLE
, {XT6
, XB6
}},
7974 {"xvrdpim", XX2(60,249), XX2_MASK
, PPCVSX
, PPCVLE
, {XT6
, XB6
}},
7975 {"xvtdivdp", XX3(60,125), XX3BF_MASK
, PPCVSX
, PPCVLE
, {BF
, XA6
, XB6
}},
7976 {"xsmaxcdp", XX3(60,128), XX3_MASK
, PPCVSX3
, PPCVLE
, {XT6
, XA6
, XB6
}},
7977 {"xsnmaddasp", XX3(60,129), XX3_MASK
, PPCVSX2
, PPCVLE
, {XT6
, XA6
, XB6
}},
7978 {"xxland", XX3(60,130), XX3_MASK
, PPCVSX
, PPCVLE
, {XT6
, XA6
, XB6
}},
7979 {"xscvdpsp", XX2(60,265), XX2_MASK
, PPCVSX
, PPCVLE
, {XT6
, XB6
}},
7980 {"xscvdpspn", XX2(60,267), XX2_MASK
, PPCVSX2
, PPCVLE
, {XT6
, XB6
}},
7981 {"xsmincdp", XX3(60,136), XX3_MASK
, PPCVSX3
, PPCVLE
, {XT6
, XA6
, XB6
}},
7982 {"xsnmaddmsp", XX3(60,137), XX3_MASK
, PPCVSX2
, PPCVLE
, {XT6
, XA6
, XB6
}},
7983 {"xxlandc", XX3(60,138), XX3_MASK
, PPCVSX
, PPCVLE
, {XT6
, XA6
, XB6
}},
7984 {"xsrsp", XX2(60,281), XX2_MASK
, PPCVSX2
, PPCVLE
, {XT6
, XB6
}},
7985 {"xsmaxjdp", XX3(60,144), XX3_MASK
, PPCVSX3
, PPCVLE
, {XT6
, XA6
, XB6
}},
7986 {"xsnmsubasp", XX3(60,145), XX3_MASK
, PPCVSX2
, PPCVLE
, {XT6
, XA6
, XB6
}},
7987 {"xxlor", XX3(60,146), XX3_MASK
, PPCVSX
, PPCVLE
, {XT6
, XA6
, XB6
}},
7988 {"xscvuxdsp", XX2(60,296), XX2_MASK
, PPCVSX2
, PPCVLE
, {XT6
, XB6
}},
7989 {"xststdcsp", XX2(60,298), XX2BFD_MASK
, PPCVSX3
, PPCVLE
, {BF
, XB6
, DCMX
}},
7990 {"xsminjdp", XX3(60,152), XX3_MASK
, PPCVSX3
, PPCVLE
, {XT6
, XA6
, XB6
}},
7991 {"xsnmsubmsp", XX3(60,153), XX3_MASK
, PPCVSX2
, PPCVLE
, {XT6
, XA6
, XB6
}},
7992 {"xxlxor", XX3(60,154), XX3_MASK
, PPCVSX
, PPCVLE
, {XT6
, XA6
, XB6
}},
7993 {"xscvsxdsp", XX2(60,312), XX2_MASK
, PPCVSX2
, PPCVLE
, {XT6
, XB6
}},
7994 {"xsmaxdp", XX3(60,160), XX3_MASK
, PPCVSX
, PPCVLE
, {XT6
, XA6
, XB6
}},
7995 {"xsnmaddadp", XX3(60,161), XX3_MASK
, PPCVSX
, PPCVLE
, {XT6
, XA6
, XB6
}},
7996 {"xxlnor", XX3(60,162), XX3_MASK
, PPCVSX
, PPCVLE
, {XT6
, XA6
, XB6
}},
7997 {"xscvdpuxds", XX2(60,328), XX2_MASK
, PPCVSX
, PPCVLE
, {XT6
, XB6
}},
7998 {"xscvspdp", XX2(60,329), XX2_MASK
, PPCVSX
, PPCVLE
, {XT6
, XB6
}},
7999 {"xscvspdpn", XX2(60,331), XX2_MASK
, PPCVSX2
, PPCVLE
, {XT6
, XB6
}},
8000 {"xsmindp", XX3(60,168), XX3_MASK
, PPCVSX
, PPCVLE
, {XT6
, XA6
, XB6
}},
8001 {"xsnmaddmdp", XX3(60,169), XX3_MASK
, PPCVSX
, PPCVLE
, {XT6
, XA6
, XB6
}},
8002 {"xxlorc", XX3(60,170), XX3_MASK
, PPCVSX2
, PPCVLE
, {XT6
, XA6
, XB6
}},
8003 {"xscvdpsxds", XX2(60,344), XX2_MASK
, PPCVSX
, PPCVLE
, {XT6
, XB6
}},
8004 {"xsabsdp", XX2(60,345), XX2_MASK
, PPCVSX
, PPCVLE
, {XT6
, XB6
}},
8005 {"xsxexpdp", XX2VA(60,347,0),XX2_MASK
|1, PPCVSX3
, PPCVLE
, {RT
, XB6
}},
8006 {"xsxsigdp", XX2VA(60,347,1),XX2_MASK
|1, PPCVSX3
, PPCVLE
, {RT
, XB6
}},
8007 {"xscvhpdp", XX2VA(60,347,16),XX2_MASK
, PPCVSX3
, PPCVLE
, {XT6
, XB6
}},
8008 {"xscvdphp", XX2VA(60,347,17),XX2_MASK
, PPCVSX3
, PPCVLE
, {XT6
, XB6
}},
8009 {"xscpsgndp", XX3(60,176), XX3_MASK
, PPCVSX
, PPCVLE
, {XT6
, XA6
, XB6
}},
8010 {"xsnmsubadp", XX3(60,177), XX3_MASK
, PPCVSX
, PPCVLE
, {XT6
, XA6
, XB6
}},
8011 {"xxlnand", XX3(60,178), XX3_MASK
, PPCVSX2
, PPCVLE
, {XT6
, XA6
, XB6
}},
8012 {"xscvuxddp", XX2(60,360), XX2_MASK
, PPCVSX
, PPCVLE
, {XT6
, XB6
}},
8013 {"xsnabsdp", XX2(60,361), XX2_MASK
, PPCVSX
, PPCVLE
, {XT6
, XB6
}},
8014 {"xststdcdp", XX2(60,362), XX2BFD_MASK
, PPCVSX3
, PPCVLE
, {BF
, XB6
, DCMX
}},
8015 {"xsnmsubmdp", XX3(60,185), XX3_MASK
, PPCVSX
, PPCVLE
, {XT6
, XA6
, XB6
}},
8016 {"xxleqv", XX3(60,186), XX3_MASK
, PPCVSX2
, PPCVLE
, {XT6
, XA6
, XB6
}},
8017 {"xscvsxddp", XX2(60,376), XX2_MASK
, PPCVSX
, PPCVLE
, {XT6
, XB6
}},
8018 {"xsnegdp", XX2(60,377), XX2_MASK
, PPCVSX
, PPCVLE
, {XT6
, XB6
}},
8019 {"xvmaxsp", XX3(60,192), XX3_MASK
, PPCVSX
, PPCVLE
, {XT6
, XA6
, XB6
}},
8020 {"xvnmaddasp", XX3(60,193), XX3_MASK
, PPCVSX
, PPCVLE
, {XT6
, XA6
, XB6
}},
8021 {"xvcvspuxds", XX2(60,392), XX2_MASK
, PPCVSX
, PPCVLE
, {XT6
, XB6
}},
8022 {"xvcvdpsp", XX2(60,393), XX2_MASK
, PPCVSX
, PPCVLE
, {XT6
, XB6
}},
8023 {"xvminsp", XX3(60,200), XX3_MASK
, PPCVSX
, PPCVLE
, {XT6
, XA6
, XB6
}},
8024 {"xvnmaddmsp", XX3(60,201), XX3_MASK
, PPCVSX
, PPCVLE
, {XT6
, XA6
, XB6
}},
8025 {"xvcvspsxds", XX2(60,408), XX2_MASK
, PPCVSX
, PPCVLE
, {XT6
, XB6
}},
8026 {"xvabssp", XX2(60,409), XX2_MASK
, PPCVSX
, PPCVLE
, {XT6
, XB6
}},
8027 {"xvmovsp", XX3(60,208), XX3_MASK
, PPCVSX
, PPCVLE
, {XT6
, XAB6
}},
8028 {"xvcpsgnsp", XX3(60,208), XX3_MASK
, PPCVSX
, PPCVLE
, {XT6
, XA6
, XB6
}},
8029 {"xvnmsubasp", XX3(60,209), XX3_MASK
, PPCVSX
, PPCVLE
, {XT6
, XA6
, XB6
}},
8030 {"xvcvuxdsp", XX2(60,424), XX2_MASK
, PPCVSX
, PPCVLE
, {XT6
, XB6
}},
8031 {"xvnabssp", XX2(60,425), XX2_MASK
, PPCVSX
, PPCVLE
, {XT6
, XB6
}},
8032 {"xvtstdcsp", XX2(60,426), XX2DCMXS_MASK
, PPCVSX3
, PPCVLE
, {XT6
, XB6
, DCMXS
}},
8033 {"xviexpsp", XX3(60,216), XX3_MASK
, PPCVSX3
, PPCVLE
, {XT6
, XA6
, XB6
}},
8034 {"xvnmsubmsp", XX3(60,217), XX3_MASK
, PPCVSX
, PPCVLE
, {XT6
, XA6
, XB6
}},
8035 {"xvcvsxdsp", XX2(60,440), XX2_MASK
, PPCVSX
, PPCVLE
, {XT6
, XB6
}},
8036 {"xvnegsp", XX2(60,441), XX2_MASK
, PPCVSX
, PPCVLE
, {XT6
, XB6
}},
8037 {"xvmaxdp", XX3(60,224), XX3_MASK
, PPCVSX
, PPCVLE
, {XT6
, XA6
, XB6
}},
8038 {"xvnmaddadp", XX3(60,225), XX3_MASK
, PPCVSX
, PPCVLE
, {XT6
, XA6
, XB6
}},
8039 {"xvcvdpuxds", XX2(60,456), XX2_MASK
, PPCVSX
, PPCVLE
, {XT6
, XB6
}},
8040 {"xvcvspdp", XX2(60,457), XX2_MASK
, PPCVSX
, PPCVLE
, {XT6
, XB6
}},
8041 {"xsiexpdp", X(60,918), XX1_MASK
, PPCVSX3
, PPCVLE
, {XT6
, RA
, RB
}},
8042 {"xvmindp", XX3(60,232), XX3_MASK
, PPCVSX
, PPCVLE
, {XT6
, XA6
, XB6
}},
8043 {"xvnmaddmdp", XX3(60,233), XX3_MASK
, PPCVSX
, PPCVLE
, {XT6
, XA6
, XB6
}},
8044 {"xvcvdpsxds", XX2(60,472), XX2_MASK
, PPCVSX
, PPCVLE
, {XT6
, XB6
}},
8045 {"xvabsdp", XX2(60,473), XX2_MASK
, PPCVSX
, PPCVLE
, {XT6
, XB6
}},
8046 {"xvxexpdp", XX2VA(60,475,0),XX2_MASK
, PPCVSX3
, PPCVLE
, {XT6
, XB6
}},
8047 {"xvxsigdp", XX2VA(60,475,1),XX2_MASK
, PPCVSX3
, PPCVLE
, {XT6
, XB6
}},
8048 {"xxbrh", XX2VA(60,475,7),XX2_MASK
, PPCVSX3
, PPCVLE
, {XT6
, XB6
}},
8049 {"xvxexpsp", XX2VA(60,475,8),XX2_MASK
, PPCVSX3
, PPCVLE
, {XT6
, XB6
}},
8050 {"xvxsigsp", XX2VA(60,475,9),XX2_MASK
, PPCVSX3
, PPCVLE
, {XT6
, XB6
}},
8051 {"xxbrw", XX2VA(60,475,15),XX2_MASK
, PPCVSX3
, PPCVLE
, {XT6
, XB6
}},
8052 {"xvcvbf16sp", XX2VA(60,475,16),XX2_MASK
, PPCVSX4
, PPCVLE
, {XT6
, XB6
}},
8053 {"xvcvspbf16", XX2VA(60,475,17),XX2_MASK
, PPCVSX4
, PPCVLE
, {XT6
, XB6
}},
8054 {"xxbrd", XX2VA(60,475,23),XX2_MASK
, PPCVSX3
, PPCVLE
, {XT6
, XB6
}},
8055 {"xvcvhpsp", XX2VA(60,475,24),XX2_MASK
, PPCVSX3
, PPCVLE
, {XT6
, XB6
}},
8056 {"xvcvsphp", XX2VA(60,475,25),XX2_MASK
, PPCVSX3
, PPCVLE
, {XT6
, XB6
}},
8057 {"xxbrq", XX2VA(60,475,31),XX2_MASK
, PPCVSX3
, PPCVLE
, {XT6
, XB6
}},
8058 {"xvmovdp", XX3(60,240), XX3_MASK
, PPCVSX
, PPCVLE
, {XT6
, XAB6
}},
8059 {"xvcpsgndp", XX3(60,240), XX3_MASK
, PPCVSX
, PPCVLE
, {XT6
, XA6
, XB6
}},
8060 {"xvnmsubadp", XX3(60,241), XX3_MASK
, PPCVSX
, PPCVLE
, {XT6
, XA6
, XB6
}},
8061 {"xvcvuxddp", XX2(60,488), XX2_MASK
, PPCVSX
, PPCVLE
, {XT6
, XB6
}},
8062 {"xvnabsdp", XX2(60,489), XX2_MASK
, PPCVSX
, PPCVLE
, {XT6
, XB6
}},
8063 {"xvtstdcdp", XX2(60,490), XX2DCMXS_MASK
, PPCVSX3
, PPCVLE
, {XT6
, XB6
, DCMXS
}},
8064 {"xviexpdp", XX3(60,248), XX3_MASK
, PPCVSX3
, PPCVLE
, {XT6
, XA6
, XB6
}},
8065 {"xvnmsubmdp", XX3(60,249), XX3_MASK
, PPCVSX
, PPCVLE
, {XT6
, XA6
, XB6
}},
8066 {"xvcvsxddp", XX2(60,504), XX2_MASK
, PPCVSX
, PPCVLE
, {XT6
, XB6
}},
8067 {"xvnegdp", XX2(60,505), XX2_MASK
, PPCVSX
, PPCVLE
, {XT6
, XB6
}},
8069 {"psq_st", OP(60), OP_MASK
, PPCPS
, PPCVLE
, {FRS
,PSD
,RA
,PSW
,PSQ
}},
8070 {"stfq", OP(60), OP_MASK
, POWER2
, PPCVLE
, {FRS
, D
, RA
}},
8072 {"lxv", DQX(61,1), DQX_MASK
, PPCVSX3
, PPCVLE
, {XTQ6
, DQ
, RA0
}},
8073 {"stxv", DQX(61,5), DQX_MASK
, PPCVSX3
, PPCVLE
, {XSQ6
, DQ
, RA0
}},
8074 {"stxsd", DSO(61,2), DS_MASK
, PPCVSX3
, PPCVLE
, {VS
, DS
, RA0
}},
8075 {"stxssp", DSO(61,3), DS_MASK
, PPCVSX3
, PPCVLE
, {VS
, DS
, RA0
}},
8076 {"stfdp", OP(61), OP_MASK
|Q_MASK
, POWER6
, POWER7
|PPCVLE
, {FRSp
, DS
, RA0
}},
8077 {"psq_stu", OP(61), OP_MASK
, PPCPS
, PPCVLE
, {FRS
,PSD
,RA
,PSW
,PSQ
}},
8078 {"stfqu", OP(61), OP_MASK
, POWER2
, PPCVLE
, {FRS
, D
, RA
}},
8080 {"std", DSO(62,0), DS_MASK
, PPC64
, PPCVLE
, {RS
, DS
, RA0
}},
8081 {"stdu", DSO(62,1), DS_MASK
, PPC64
, PPCVLE
, {RS
, DS
, RAS
}},
8082 {"stq", DSO(62,2), DS_MASK
|Q_MASK
, POWER4
, PPC476
|PPCVLE
, {RSQ
, DS
, RA0
}},
8084 {"fcmpu", X(63,0), XBF_MASK
, COM
, PPCEFS
|PPCVLE
, {BF
, FRA
, FRB
}},
8086 {"daddq", XRC(63,2,0), X_MASK
|Q_MASK
, POWER6
, PPCVLE
, {FRTp
, FRAp
, FRBp
}},
8087 {"daddq.", XRC(63,2,1), X_MASK
|Q_MASK
, POWER6
, PPCVLE
, {FRTp
, FRAp
, FRBp
}},
8089 {"dquaq", ZRC(63,3,0), Z2_MASK
|Q_MASK
, POWER6
, PPCVLE
, {FRTp
, FRAp
, FRBp
, RMC
}},
8090 {"dquaq.", ZRC(63,3,1), Z2_MASK
|Q_MASK
, POWER6
, PPCVLE
, {FRTp
, FRAp
, FRBp
, RMC
}},
8092 {"xsaddqp", XRC(63,4,0), X_MASK
, PPCVSX3
, PPCVLE
, {VD
, VA
, VB
}},
8093 {"xsaddqpo", XRC(63,4,1), X_MASK
, PPCVSX3
, PPCVLE
, {VD
, VA
, VB
}},
8095 {"xsrqpi", ZRC(63,5,0), Z2_MASK
, PPCVSX3
, PPCVLE
, {R
, VD
, VB
, RMC
}},
8096 {"xsrqpix", ZRC(63,5,1), Z2_MASK
, PPCVSX3
, PPCVLE
, {R
, VD
, VB
, RMC
}},
8098 {"fcpsgn", XRC(63,8,0), X_MASK
, POWER6
|PPCA2
|PPC476
, PPCVLE
, {FRT
, FRA
, FRB
}},
8099 {"fcpsgn.", XRC(63,8,1), X_MASK
, POWER6
|PPCA2
|PPC476
, PPCVLE
, {FRT
, FRA
, FRB
}},
8101 {"frsp", XRC(63,12,0), XRA_MASK
, COM
, PPCEFS
|PPCVLE
, {FRT
, FRB
}},
8102 {"frsp.", XRC(63,12,1), XRA_MASK
, COM
, PPCEFS
|PPCVLE
, {FRT
, FRB
}},
8104 {"fctiw", XRC(63,14,0), XRA_MASK
, PPCCOM
, PPCEFS
|PPCVLE
, {FRT
, FRB
}},
8105 {"fcir", XRC(63,14,0), XRA_MASK
, PWR2COM
, PPCVLE
, {FRT
, FRB
}},
8106 {"fctiw.", XRC(63,14,1), XRA_MASK
, PPCCOM
, PPCEFS
|PPCVLE
, {FRT
, FRB
}},
8107 {"fcir.", XRC(63,14,1), XRA_MASK
, PWR2COM
, PPCVLE
, {FRT
, FRB
}},
8109 {"fctiwz", XRC(63,15,0), XRA_MASK
, PPCCOM
, PPCEFS
|PPCVLE
, {FRT
, FRB
}},
8110 {"fcirz", XRC(63,15,0), XRA_MASK
, PWR2COM
, PPCVLE
, {FRT
, FRB
}},
8111 {"fctiwz.", XRC(63,15,1), XRA_MASK
, PPCCOM
, PPCEFS
|PPCVLE
, {FRT
, FRB
}},
8112 {"fcirz.", XRC(63,15,1), XRA_MASK
, PWR2COM
, PPCVLE
, {FRT
, FRB
}},
8114 {"fdiv", A(63,18,0), AFRC_MASK
, PPCCOM
, PPCEFS
|PPCVLE
, {FRT
, FRA
, FRB
}},
8115 {"fd", A(63,18,0), AFRC_MASK
, PWRCOM
, PPCVLE
, {FRT
, FRA
, FRB
}},
8116 {"fdiv.", A(63,18,1), AFRC_MASK
, PPCCOM
, PPCEFS
|PPCVLE
, {FRT
, FRA
, FRB
}},
8117 {"fd.", A(63,18,1), AFRC_MASK
, PWRCOM
, PPCVLE
, {FRT
, FRA
, FRB
}},
8119 {"fsub", A(63,20,0), AFRC_MASK
, PPCCOM
, PPCEFS
|PPCVLE
, {FRT
, FRA
, FRB
}},
8120 {"fs", A(63,20,0), AFRC_MASK
, PWRCOM
, PPCVLE
, {FRT
, FRA
, FRB
}},
8121 {"fsub.", A(63,20,1), AFRC_MASK
, PPCCOM
, PPCEFS
|PPCVLE
, {FRT
, FRA
, FRB
}},
8122 {"fs.", A(63,20,1), AFRC_MASK
, PWRCOM
, PPCVLE
, {FRT
, FRA
, FRB
}},
8124 {"fadd", A(63,21,0), AFRC_MASK
, PPCCOM
, PPCEFS
|PPCVLE
, {FRT
, FRA
, FRB
}},
8125 {"fa", A(63,21,0), AFRC_MASK
, PWRCOM
, PPCVLE
, {FRT
, FRA
, FRB
}},
8126 {"fadd.", A(63,21,1), AFRC_MASK
, PPCCOM
, PPCEFS
|PPCVLE
, {FRT
, FRA
, FRB
}},
8127 {"fa.", A(63,21,1), AFRC_MASK
, PWRCOM
, PPCVLE
, {FRT
, FRA
, FRB
}},
8129 {"fsqrt", A(63,22,0), AFRAFRC_MASK
, PPCPWR2
, TITAN
|PPCVLE
, {FRT
, FRB
}},
8130 {"fsqrt.", A(63,22,1), AFRAFRC_MASK
, PPCPWR2
, TITAN
|PPCVLE
, {FRT
, FRB
}},
8132 {"fsel", A(63,23,0), A_MASK
, PPC
, PPCEFS
|PPCVLE
, {FRT
, FRA
, FRC
, FRB
}},
8133 {"fsel.", A(63,23,1), A_MASK
, PPC
, PPCEFS
|PPCVLE
, {FRT
, FRA
, FRC
, FRB
}},
8135 {"fre", A(63,24,0), AFRAFRC_MASK
, POWER7
, PPCVLE
, {FRT
, FRB
}},
8136 {"fre", A(63,24,0), AFRALFRC_MASK
, POWER5
, POWER7
|PPCVLE
, {FRT
, FRB
, A_L
}},
8137 {"fre.", A(63,24,1), AFRAFRC_MASK
, POWER7
, PPCVLE
, {FRT
, FRB
}},
8138 {"fre.", A(63,24,1), AFRALFRC_MASK
, POWER5
, POWER7
|PPCVLE
, {FRT
, FRB
, A_L
}},
8140 {"fmul", A(63,25,0), AFRB_MASK
, PPCCOM
, PPCEFS
|PPCVLE
, {FRT
, FRA
, FRC
}},
8141 {"fm", A(63,25,0), AFRB_MASK
, PWRCOM
, PPCVLE
|PPCVLE
, {FRT
, FRA
, FRC
}},
8142 {"fmul.", A(63,25,1), AFRB_MASK
, PPCCOM
, PPCEFS
|PPCVLE
, {FRT
, FRA
, FRC
}},
8143 {"fm.", A(63,25,1), AFRB_MASK
, PWRCOM
, PPCVLE
|PPCVLE
, {FRT
, FRA
, FRC
}},
8145 {"frsqrte", A(63,26,0), AFRAFRC_MASK
, POWER7
, PPCVLE
, {FRT
, FRB
}},
8146 {"frsqrte", A(63,26,0), AFRALFRC_MASK
, PPC
, POWER7
|PPCVLE
, {FRT
, FRB
, A_L
}},
8147 {"frsqrte.", A(63,26,1), AFRAFRC_MASK
, POWER7
, PPCVLE
, {FRT
, FRB
}},
8148 {"frsqrte.", A(63,26,1), AFRALFRC_MASK
, PPC
, POWER7
|PPCVLE
, {FRT
, FRB
, A_L
}},
8150 {"fmsub", A(63,28,0), A_MASK
, PPCCOM
, PPCEFS
|PPCVLE
, {FRT
, FRA
, FRC
, FRB
}},
8151 {"fms", A(63,28,0), A_MASK
, PWRCOM
, PPCVLE
, {FRT
, FRA
, FRC
, FRB
}},
8152 {"fmsub.", A(63,28,1), A_MASK
, PPCCOM
, PPCEFS
|PPCVLE
, {FRT
, FRA
, FRC
, FRB
}},
8153 {"fms.", A(63,28,1), A_MASK
, PWRCOM
, PPCVLE
, {FRT
, FRA
, FRC
, FRB
}},
8155 {"fmadd", A(63,29,0), A_MASK
, PPCCOM
, PPCEFS
|PPCVLE
, {FRT
, FRA
, FRC
, FRB
}},
8156 {"fma", A(63,29,0), A_MASK
, PWRCOM
, PPCVLE
, {FRT
, FRA
, FRC
, FRB
}},
8157 {"fmadd.", A(63,29,1), A_MASK
, PPCCOM
, PPCEFS
|PPCVLE
, {FRT
, FRA
, FRC
, FRB
}},
8158 {"fma.", A(63,29,1), A_MASK
, PWRCOM
, PPCVLE
, {FRT
, FRA
, FRC
, FRB
}},
8160 {"fnmsub", A(63,30,0), A_MASK
, PPCCOM
, PPCEFS
|PPCVLE
, {FRT
, FRA
, FRC
, FRB
}},
8161 {"fnms", A(63,30,0), A_MASK
, PWRCOM
, PPCVLE
, {FRT
, FRA
, FRC
, FRB
}},
8162 {"fnmsub.", A(63,30,1), A_MASK
, PPCCOM
, PPCEFS
|PPCVLE
, {FRT
, FRA
, FRC
, FRB
}},
8163 {"fnms.", A(63,30,1), A_MASK
, PWRCOM
, PPCVLE
, {FRT
, FRA
, FRC
, FRB
}},
8165 {"fnmadd", A(63,31,0), A_MASK
, PPCCOM
, PPCEFS
|PPCVLE
, {FRT
, FRA
, FRC
, FRB
}},
8166 {"fnma", A(63,31,0), A_MASK
, PWRCOM
, PPCVLE
, {FRT
, FRA
, FRC
, FRB
}},
8167 {"fnmadd.", A(63,31,1), A_MASK
, PPCCOM
, PPCEFS
|PPCVLE
, {FRT
, FRA
, FRC
, FRB
}},
8168 {"fnma.", A(63,31,1), A_MASK
, PWRCOM
, PPCVLE
, {FRT
, FRA
, FRC
, FRB
}},
8170 {"fcmpo", X(63,32), XBF_MASK
, COM
, PPCEFS
|PPCVLE
, {BF
, FRA
, FRB
}},
8172 {"dmulq", XRC(63,34,0), X_MASK
|Q_MASK
, POWER6
, PPCVLE
, {FRTp
, FRAp
, FRBp
}},
8173 {"dmulq.", XRC(63,34,1), X_MASK
|Q_MASK
, POWER6
, PPCVLE
, {FRTp
, FRAp
, FRBp
}},
8175 {"drrndq", ZRC(63,35,0), Z2_MASK
|Q_MASK
, POWER6
, PPCVLE
, {FRTp
, FRA
, FRBp
, RMC
}},
8176 {"drrndq.", ZRC(63,35,1), Z2_MASK
|Q_MASK
, POWER6
, PPCVLE
, {FRTp
, FRA
, FRBp
, RMC
}},
8178 {"xsmulqp", XRC(63,36,0), X_MASK
, PPCVSX3
, PPCVLE
, {VD
, VA
, VB
}},
8179 {"xsmulqpo", XRC(63,36,1), X_MASK
, PPCVSX3
, PPCVLE
, {VD
, VA
, VB
}},
8181 {"xsrqpxp", Z(63,37), Z2_MASK
, PPCVSX3
, PPCVLE
, {R
, VD
, VB
, RMC
}},
8183 {"mtfsb1", XRC(63,38,0), XRARB_MASK
, COM
, PPCVLE
, {BTF
}},
8184 {"mtfsb1.", XRC(63,38,1), XRARB_MASK
, COM
, PPCVLE
, {BTF
}},
8186 {"fneg", XRC(63,40,0), XRA_MASK
, COM
, PPCEFS
|PPCVLE
, {FRT
, FRB
}},
8187 {"fneg.", XRC(63,40,1), XRA_MASK
, COM
, PPCEFS
|PPCVLE
, {FRT
, FRB
}},
8189 {"mcrfs", X(63,64), XRB_MASK
|(3<<21)|(3<<16), COM
, PPCVLE
, {BF
, BFA
}},
8191 {"dscliq", ZRC(63,66,0), Z_MASK
|Q_MASK
, POWER6
, PPCVLE
, {FRTp
, FRAp
, SH16
}},
8192 {"dscliq.", ZRC(63,66,1), Z_MASK
|Q_MASK
, POWER6
, PPCVLE
, {FRTp
, FRAp
, SH16
}},
8194 {"dquaiq", ZRC(63,67,0), Z2_MASK
|Q_MASK
, POWER6
, PPCVLE
, {TE
, FRTp
, FRBp
, RMC
}},
8195 {"dquaiq.", ZRC(63,67,1), Z2_MASK
|Q_MASK
, POWER6
, PPCVLE
, {TE
, FRTp
, FRBp
, RMC
}},
8197 {"mtfsb0", XRC(63,70,0), XRARB_MASK
, COM
, PPCVLE
, {BTF
}},
8198 {"mtfsb0.", XRC(63,70,1), XRARB_MASK
, COM
, PPCVLE
, {BTF
}},
8200 {"fmr", XRC(63,72,0), XRA_MASK
, COM
, PPCEFS
|PPCVLE
, {FRT
, FRB
}},
8201 {"fmr.", XRC(63,72,1), XRA_MASK
, COM
, PPCEFS
|PPCVLE
, {FRT
, FRB
}},
8203 {"dscriq", ZRC(63,98,0), Z_MASK
|Q_MASK
, POWER6
, PPCVLE
, {FRTp
, FRAp
, SH16
}},
8204 {"dscriq.", ZRC(63,98,1), Z_MASK
|Q_MASK
, POWER6
, PPCVLE
, {FRTp
, FRAp
, SH16
}},
8206 {"drintxq", ZRC(63,99,0), Z2_MASK
|Q_MASK
, POWER6
, PPCVLE
, {R
, FRTp
, FRBp
, RMC
}},
8207 {"drintxq.", ZRC(63,99,1), Z2_MASK
|Q_MASK
, POWER6
, PPCVLE
, {R
, FRTp
, FRBp
, RMC
}},
8209 {"xscpsgnqp", X(63,100), X_MASK
, PPCVSX3
, PPCVLE
, {VD
, VA
, VB
}},
8211 {"ftdiv", X(63,128), XBF_MASK
, POWER7
, PPCVLE
, {BF
, FRA
, FRB
}},
8213 {"dcmpoq", X(63,130), X_MASK
, POWER6
, PPCVLE
, {BF
, FRAp
, FRBp
}},
8215 {"xscmpoqp", X(63,132), XBF_MASK
, PPCVSX3
, PPCVLE
, {BF
, VA
, VB
}},
8217 {"mtfsfi", XRC(63,134,0), XWRA_MASK
|(3<<21)|(1<<11), POWER6
|PPCA2
|PPC476
, PPCVLE
, {BFF
, U
, W
}},
8218 {"mtfsfi", XRC(63,134,0), XRA_MASK
|(3<<21)|(1<<11), COM
, POWER6
|PPCA2
|PPC476
|PPCVLE
, {BFF
, U
}},
8219 {"mtfsfi.", XRC(63,134,1), XWRA_MASK
|(3<<21)|(1<<11), POWER6
|PPCA2
|PPC476
, PPCVLE
, {BFF
, U
, W
}},
8220 {"mtfsfi.", XRC(63,134,1), XRA_MASK
|(3<<21)|(1<<11), COM
, POWER6
|PPCA2
|PPC476
|PPCVLE
, {BFF
, U
}},
8222 {"fnabs", XRC(63,136,0), XRA_MASK
, COM
, PPCEFS
|PPCVLE
, {FRT
, FRB
}},
8223 {"fnabs.", XRC(63,136,1), XRA_MASK
, COM
, PPCEFS
|PPCVLE
, {FRT
, FRB
}},
8225 {"fctiwu", XRC(63,142,0), XRA_MASK
, POWER7
, PPCVLE
, {FRT
, FRB
}},
8226 {"fctiwu.", XRC(63,142,1), XRA_MASK
, POWER7
, PPCVLE
, {FRT
, FRB
}},
8227 {"fctiwuz", XRC(63,143,0), XRA_MASK
, POWER7
, PPCVLE
, {FRT
, FRB
}},
8228 {"fctiwuz.", XRC(63,143,1), XRA_MASK
, POWER7
, PPCVLE
, {FRT
, FRB
}},
8230 {"ftsqrt", X(63,160), XBF_MASK
|FRA_MASK
, POWER7
, PPCVLE
, {BF
, FRB
}},
8232 {"dtstexq", X(63,162), X_MASK
, POWER6
, PPCVLE
, {BF
, FRAp
, FRBp
}},
8234 {"xscmpexpqp", X(63,164), XBF_MASK
, PPCVSX3
, PPCVLE
, {BF
, VA
, VB
}},
8236 {"dtstdcq", Z(63,194), Z_MASK
, POWER6
, PPCVLE
, {BF
, FRAp
, DCM
}},
8237 {"dtstdgq", Z(63,226), Z_MASK
, POWER6
, PPCVLE
, {BF
, FRAp
, DGM
}},
8239 {"drintnq", ZRC(63,227,0), Z2_MASK
|Q_MASK
, POWER6
, PPCVLE
, {R
, FRTp
, FRBp
, RMC
}},
8240 {"drintnq.", ZRC(63,227,1), Z2_MASK
|Q_MASK
, POWER6
, PPCVLE
, {R
, FRTp
, FRBp
, RMC
}},
8242 {"dctqpq", XRC(63,258,0), X_MASK
|Q_MASK
, POWER6
, PPCVLE
, {FRTp
, FRB
}},
8243 {"dctqpq.", XRC(63,258,1), X_MASK
|Q_MASK
, POWER6
, PPCVLE
, {FRTp
, FRB
}},
8245 {"fabs", XRC(63,264,0), XRA_MASK
, COM
, PPCEFS
|PPCVLE
, {FRT
, FRB
}},
8246 {"fabs.", XRC(63,264,1), XRA_MASK
, COM
, PPCEFS
|PPCVLE
, {FRT
, FRB
}},
8248 {"dctfixq", XRC(63,290,0), X_MASK
, POWER6
, PPCVLE
, {FRT
, FRBp
}},
8249 {"dctfixq.", XRC(63,290,1), X_MASK
, POWER6
, PPCVLE
, {FRT
, FRBp
}},
8251 {"ddedpdq", XRC(63,322,0), X_MASK
|Q_MASK
, POWER6
, PPCVLE
, {SP
, FRTp
, FRBp
}},
8252 {"ddedpdq.", XRC(63,322,1), X_MASK
|Q_MASK
, POWER6
, PPCVLE
, {SP
, FRTp
, FRBp
}},
8254 {"dxexq", XRC(63,354,0), X_MASK
, POWER6
, PPCVLE
, {FRT
, FRBp
}},
8255 {"dxexq.", XRC(63,354,1), X_MASK
, POWER6
, PPCVLE
, {FRT
, FRBp
}},
8257 {"xsmaddqp", XRC(63,388,0), X_MASK
, PPCVSX3
, PPCVLE
, {VD
, VA
, VB
}},
8258 {"xsmaddqpo", XRC(63,388,1), X_MASK
, PPCVSX3
, PPCVLE
, {VD
, VA
, VB
}},
8260 {"frin", XRC(63,392,0), XRA_MASK
, POWER5
, PPCVLE
, {FRT
, FRB
}},
8261 {"frin.", XRC(63,392,1), XRA_MASK
, POWER5
, PPCVLE
, {FRT
, FRB
}},
8263 {"xsmsubqp", XRC(63,420,0), X_MASK
, PPCVSX3
, PPCVLE
, {VD
, VA
, VB
}},
8264 {"xsmsubqpo", XRC(63,420,1), X_MASK
, PPCVSX3
, PPCVLE
, {VD
, VA
, VB
}},
8266 {"friz", XRC(63,424,0), XRA_MASK
, POWER5
, PPCVLE
, {FRT
, FRB
}},
8267 {"friz.", XRC(63,424,1), XRA_MASK
, POWER5
, PPCVLE
, {FRT
, FRB
}},
8269 {"xsnmaddqp", XRC(63,452,0), X_MASK
, PPCVSX3
, PPCVLE
, {VD
, VA
, VB
}},
8270 {"xsnmaddqpo", XRC(63,452,1), X_MASK
, PPCVSX3
, PPCVLE
, {VD
, VA
, VB
}},
8272 {"frip", XRC(63,456,0), XRA_MASK
, POWER5
, PPCVLE
, {FRT
, FRB
}},
8273 {"frip.", XRC(63,456,1), XRA_MASK
, POWER5
, PPCVLE
, {FRT
, FRB
}},
8275 {"xsnmsubqp", XRC(63,484,0), X_MASK
, PPCVSX3
, PPCVLE
, {VD
, VA
, VB
}},
8276 {"xsnmsubqpo", XRC(63,484,1), X_MASK
, PPCVSX3
, PPCVLE
, {VD
, VA
, VB
}},
8278 {"frim", XRC(63,488,0), XRA_MASK
, POWER5
, PPCVLE
, {FRT
, FRB
}},
8279 {"frim.", XRC(63,488,1), XRA_MASK
, POWER5
, PPCVLE
, {FRT
, FRB
}},
8281 {"dsubq", XRC(63,514,0), X_MASK
|Q_MASK
, POWER6
, PPCVLE
, {FRTp
, FRAp
, FRBp
}},
8282 {"dsubq.", XRC(63,514,1), X_MASK
|Q_MASK
, POWER6
, PPCVLE
, {FRTp
, FRAp
, FRBp
}},
8284 {"xssubqp", XRC(63,516,0), X_MASK
, PPCVSX3
, PPCVLE
, {VD
, VA
, VB
}},
8285 {"xssubqpo", XRC(63,516,1), X_MASK
, PPCVSX3
, PPCVLE
, {VD
, VA
, VB
}},
8287 {"ddivq", XRC(63,546,0), X_MASK
|Q_MASK
, POWER6
, PPCVLE
, {FRTp
, FRAp
, FRBp
}},
8288 {"ddivq.", XRC(63,546,1), X_MASK
|Q_MASK
, POWER6
, PPCVLE
, {FRTp
, FRAp
, FRBp
}},
8290 {"xsdivqp", XRC(63,548,0), X_MASK
, PPCVSX3
, PPCVLE
, {VD
, VA
, VB
}},
8291 {"xsdivqpo", XRC(63,548,1), X_MASK
, PPCVSX3
, PPCVLE
, {VD
, VA
, VB
}},
8293 {"mffs", XRC(63,583,0), XRARB_MASK
, COM
, PPCEFS
|PPCVLE
, {FRT
}},
8294 {"mffs.", XRC(63,583,1), XRARB_MASK
, COM
, PPCEFS
|PPCVLE
, {FRT
}},
8296 {"mffsce", XMMF(63,583,0,1), XMMF_MASK
|RB_MASK
, POWER9
, PPCVLE
, {FRT
}},
8297 {"mffscdrn", XMMF(63,583,2,4), XMMF_MASK
, POWER9
, PPCVLE
, {FRT
, FRB
}},
8298 {"mffscdrni", XMMF(63,583,2,5), XMMF_MASK
|(3<<14), POWER9
, PPCVLE
, {FRT
, DRM
}},
8299 {"mffscrn", XMMF(63,583,2,6), XMMF_MASK
, POWER9
, PPCVLE
, {FRT
, FRB
}},
8300 {"mffscrni", XMMF(63,583,2,7), XMMF_MASK
|(7<<13), POWER9
, PPCVLE
, {FRT
, RM
}},
8301 {"mffsl", XMMF(63,583,3,0), XMMF_MASK
|RB_MASK
, POWER9
, PPCVLE
, {FRT
}},
8303 {"dcmpuq", X(63,642), X_MASK
, POWER6
, PPCVLE
, {BF
, FRAp
, FRBp
}},
8305 {"xscmpuqp", X(63,644), XBF_MASK
, PPCVSX3
, PPCVLE
, {BF
, VA
, VB
}},
8307 {"dtstsfq", X(63,674), X_MASK
, POWER6
, PPCVLE
, {BF
, FRA
, FRBp
}},
8308 {"dtstsfiq", X(63,675), X_MASK
|1<<22,POWER9
, PPCVLE
, {BF
, UIM6
, FRBp
}},
8310 {"xststdcqp", X(63,708), X_MASK
, PPCVSX3
, PPCVLE
, {BF
, VB
, DCMX
}},
8312 {"mtfsf", XFL(63,711,0), XFL_MASK
, POWER6
|PPCA2
|PPC476
, PPCVLE
, {FLM
, FRB
, XFL_L
, W
}},
8313 {"mtfsf", XFL(63,711,0), XFL_MASK
, COM
, POWER6
|PPCA2
|PPC476
|PPCEFS
|PPCVLE
, {FLM
, FRB
}},
8314 {"mtfsf.", XFL(63,711,1), XFL_MASK
, POWER6
|PPCA2
|PPC476
, PPCVLE
, {FLM
, FRB
, XFL_L
, W
}},
8315 {"mtfsf.", XFL(63,711,1), XFL_MASK
, COM
, POWER6
|PPCA2
|PPC476
|PPCEFS
|PPCVLE
, {FLM
, FRB
}},
8317 {"drdpq", XRC(63,770,0), X_MASK
|Q_MASK
, POWER6
, PPCVLE
, {FRTp
, FRBp
}},
8318 {"drdpq.", XRC(63,770,1), X_MASK
|Q_MASK
, POWER6
, PPCVLE
, {FRTp
, FRBp
}},
8320 {"dcffixq", XRC(63,802,0), X_MASK
|Q_MASK
, POWER6
, PPCVLE
, {FRTp
, FRB
}},
8321 {"dcffixq.", XRC(63,802,1), X_MASK
|Q_MASK
, POWER6
, PPCVLE
, {FRTp
, FRB
}},
8323 {"xsabsqp", XVA(63,804,0), XVA_MASK
, PPCVSX3
, PPCVLE
, {VD
, VB
}},
8324 {"xsxexpqp", XVA(63,804,2), XVA_MASK
, PPCVSX3
, PPCVLE
, {VD
, VB
}},
8325 {"xsnabsqp", XVA(63,804,8), XVA_MASK
, PPCVSX3
, PPCVLE
, {VD
, VB
}},
8326 {"xsnegqp", XVA(63,804,16), XVA_MASK
, PPCVSX3
, PPCVLE
, {VD
, VB
}},
8327 {"xsxsigqp", XVA(63,804,18), XVA_MASK
, PPCVSX3
, PPCVLE
, {VD
, VB
}},
8328 {"xssqrtqp", XVARC(63,804,27,0), XVA_MASK
, PPCVSX3
, PPCVLE
, {VD
, VB
}},
8329 {"xssqrtqpo", XVARC(63,804,27,1), XVA_MASK
, PPCVSX3
, PPCVLE
, {VD
, VB
}},
8331 {"fctid", XRC(63,814,0), XRA_MASK
, PPC64
, PPCVLE
, {FRT
, FRB
}},
8332 {"fctid", XRC(63,814,0), XRA_MASK
, PPC476
, PPCVLE
, {FRT
, FRB
}},
8333 {"fctid.", XRC(63,814,1), XRA_MASK
, PPC64
, PPCVLE
, {FRT
, FRB
}},
8334 {"fctid.", XRC(63,814,1), XRA_MASK
, PPC476
, PPCVLE
, {FRT
, FRB
}},
8336 {"fctidz", XRC(63,815,0), XRA_MASK
, PPC64
, PPCVLE
, {FRT
, FRB
}},
8337 {"fctidz", XRC(63,815,0), XRA_MASK
, PPC476
, PPCVLE
, {FRT
, FRB
}},
8338 {"fctidz.", XRC(63,815,1), XRA_MASK
, PPC64
, PPCVLE
, {FRT
, FRB
}},
8339 {"fctidz.", XRC(63,815,1), XRA_MASK
, PPC476
, PPCVLE
, {FRT
, FRB
}},
8341 {"denbcdq", XRC(63,834,0), X_MASK
|Q_MASK
, POWER6
, PPCVLE
, {S
, FRTp
, FRBp
}},
8342 {"denbcdq.", XRC(63,834,1), X_MASK
|Q_MASK
, POWER6
, PPCVLE
, {S
, FRTp
, FRBp
}},
8344 {"xscvqpuqz", XVA(63,836,0), XVA_MASK
, POWER10
, PPCVLE
, {VD
, VB
}},
8345 {"xscvqpuwz", XVA(63,836,1), XVA_MASK
, PPCVSX3
, PPCVLE
, {VD
, VB
}},
8346 {"xscvudqp", XVA(63,836,2), XVA_MASK
, PPCVSX3
, PPCVLE
, {VD
, VB
}},
8347 {"xscvuqqp", XVA(63,836,3), XVA_MASK
, POWER10
, PPCVLE
, {VD
, VB
}},
8348 {"xscvqpsqz", XVA(63,836,8), XVA_MASK
, POWER10
, PPCVLE
, {VD
, VB
}},
8349 {"xscvqpswz", XVA(63,836,9), XVA_MASK
, PPCVSX3
, PPCVLE
, {VD
, VB
}},
8350 {"xscvsdqp", XVA(63,836,10), XVA_MASK
, PPCVSX3
, PPCVLE
, {VD
, VB
}},
8351 {"xscvsqqp", XVA(63,836,11), XVA_MASK
, POWER10
, PPCVLE
, {VD
, VB
}},
8352 {"xscvqpudz", XVA(63,836,17), XVA_MASK
, PPCVSX3
, PPCVLE
, {VD
, VB
}},
8353 {"xscvqpdp", XVARC(63,836,20,0), XVA_MASK
, PPCVSX3
, PPCVLE
, {VD
, VB
}},
8354 {"xscvqpdpo", XVARC(63,836,20,1), XVA_MASK
, PPCVSX3
, PPCVLE
, {VD
, VB
}},
8355 {"xscvdpqp", XVA(63,836,22), XVA_MASK
, PPCVSX3
, PPCVLE
, {VD
, VB
}},
8356 {"xscvqpsdz", XVA(63,836,25), XVA_MASK
, PPCVSX3
, PPCVLE
, {VD
, VB
}},
8358 {"fmrgow", X(63,838), X_MASK
, PPCVSX2
, PPCVLE
, {FRT
, FRA
, FRB
}},
8360 {"fcfid", XRC(63,846,0), XRA_MASK
, PPC64
, PPCVLE
, {FRT
, FRB
}},
8361 {"fcfid", XRC(63,846,0), XRA_MASK
, PPC476
, PPCVLE
, {FRT
, FRB
}},
8362 {"fcfid.", XRC(63,846,1), XRA_MASK
, PPC64
, PPCVLE
, {FRT
, FRB
}},
8363 {"fcfid.", XRC(63,846,1), XRA_MASK
, PPC476
, PPCVLE
, {FRT
, FRB
}},
8365 {"diexq", XRC(63,866,0), X_MASK
|Q_MASK
, POWER6
, PPCVLE
, {FRTp
, FRA
, FRBp
}},
8366 {"diexq.", XRC(63,866,1), X_MASK
|Q_MASK
, POWER6
, PPCVLE
, {FRTp
, FRA
, FRBp
}},
8368 {"xsiexpqp", X(63,868), X_MASK
, PPCVSX3
, PPCVLE
, {VD
, VA
, VB
}},
8370 {"fctidu", XRC(63,942,0), XRA_MASK
, POWER7
|PPCA2
, PPCVLE
, {FRT
, FRB
}},
8371 {"fctidu.", XRC(63,942,1), XRA_MASK
, POWER7
|PPCA2
, PPCVLE
, {FRT
, FRB
}},
8373 {"fctiduz", XRC(63,943,0), XRA_MASK
, POWER7
|PPCA2
, PPCVLE
, {FRT
, FRB
}},
8374 {"fctiduz.", XRC(63,943,1), XRA_MASK
, POWER7
|PPCA2
, PPCVLE
, {FRT
, FRB
}},
8376 {"fmrgew", X(63,966), X_MASK
, PPCVSX2
, PPCVLE
, {FRT
, FRA
, FRB
}},
8378 {"fcfidu", XRC(63,974,0), XRA_MASK
, POWER7
|PPCA2
, PPCVLE
, {FRT
, FRB
}},
8379 {"fcfidu.", XRC(63,974,1), XRA_MASK
, POWER7
|PPCA2
, PPCVLE
, {FRT
, FRB
}},
8381 {"dcffixqq", XVA(63,994,0), XVA_MASK
, POWER10
, PPCVLE
, {FRTp
, VB
}},
8382 {"dctfixqq", XVA(63,994,1), XVA_MASK
, POWER10
, PPCVLE
, {VD
, FRBp
}},
8385 const unsigned int powerpc_num_opcodes
=
8386 sizeof (powerpc_opcodes
) / sizeof (powerpc_opcodes
[0]);
8388 /* The opcode table for 8-byte prefix instructions.
8390 The format of this opcode table is the same as the main opcode table. */
8392 const struct powerpc_opcode prefix_opcodes
[] = {
8393 {"pnop", PMRR
, PREFIX_MASK
, POWER10
, 0, {0}},
8394 {"pli", PMLS
|OP(14), P_DRAPCREL_MASK
, POWER10
, 0, {RT
, SI34
}},
8395 {"paddi", PMLS
|OP(14), P_D_MASK
, POWER10
, 0, {RT
, RA0
, SI34
, PCREL0
}},
8396 {"psubi", PMLS
|OP(14), P_D_MASK
, POWER10
, 0, {RT
, RA0
, NSI34
, PCREL0
}},
8397 {"pla", PMLS
|OP(14), P_D_MASK
, POWER10
, 0, {RT
, D34
, PRA0
, PCREL
}},
8398 {"xxsplti32dx", P8RR
|VSOP(32,0), P_VSI_MASK
, POWER10
, 0, {XTS
, IX
, IMM32
}},
8399 {"xxspltidp", P8RR
|VSOP(32,2), P_VS_MASK
, POWER10
, 0, {XTS
, IMM32
}},
8400 {"xxspltiw", P8RR
|VSOP(32,3), P_VS_MASK
, POWER10
, 0, {XTS
, IMM32
}},
8401 {"plwz", PMLS
|OP(32), P_D_MASK
, POWER10
, 0, {RT
, D34
, PRA0
, PCREL
}},
8402 {"xxblendvb", P8RR
|XX4(33,0), P_XX4_MASK
, POWER10
, 0, {XT6
, XA6
, XB6
, XC6
}},
8403 {"xxblendvh", P8RR
|XX4(33,1), P_XX4_MASK
, POWER10
, 0, {XT6
, XA6
, XB6
, XC6
}},
8404 {"xxblendvw", P8RR
|XX4(33,2), P_XX4_MASK
, POWER10
, 0, {XT6
, XA6
, XB6
, XC6
}},
8405 {"xxblendvd", P8RR
|XX4(33,3), P_XX4_MASK
, POWER10
, 0, {XT6
, XA6
, XB6
, XC6
}},
8406 {"xxpermx", P8RR
|XX4(34,0), P_UXX4_MASK
, POWER10
, 0, {XT6
, XA6
, XB6
, XC6
, UIM3
}},
8407 {"plbz", PMLS
|OP(34), P_D_MASK
, POWER10
, 0, {RT
, D34
, PRA0
, PCREL
}},
8408 {"pstw", PMLS
|OP(36), P_D_MASK
, POWER10
, 0, {RS
, D34
, PRA0
, PCREL
}},
8409 {"pstb", PMLS
|OP(38), P_D_MASK
, POWER10
, 0, {RS
, D34
, PRA0
, PCREL
}},
8410 {"plhz", PMLS
|OP(40), P_D_MASK
, POWER10
, 0, {RT
, D34
, PRA0
, PCREL
}},
8411 {"plwa", P8LS
|OP(41), P_D_MASK
, POWER10
, 0, {RT
, D34
, PRA0
, PCREL
}},
8412 {"plxsd", P8LS
|OP(42), P_D_MASK
, POWER10
, 0, {VD
, D34
, PRA0
, PCREL
}},
8413 {"plha", PMLS
|OP(42), P_D_MASK
, POWER10
, 0, {RT
, D34
, PRA0
, PCREL
}},
8414 {"plxssp", P8LS
|OP(43), P_D_MASK
, POWER10
, 0, {VD
, D34
, PRA0
, PCREL
}},
8415 {"psth", PMLS
|OP(44), P_D_MASK
, POWER10
, 0, {RS
, D34
, PRA0
, PCREL
}},
8416 {"pstxsd", P8LS
|OP(46), P_D_MASK
, POWER10
, 0, {VS
, D34
, PRA0
, PCREL
}},
8417 {"pstxssp", P8LS
|OP(47), P_D_MASK
, POWER10
, 0, {VS
, D34
, PRA0
, PCREL
}},
8418 {"plfs", PMLS
|OP(48), P_D_MASK
, POWER10
, 0, {FRT
, D34
, PRA0
, PCREL
}},
8419 {"plxv", P8LS
|OP(50), P_D_MASK
&~OP(1), POWER10
, 0, {XTOP
, D34
, PRA0
, PCREL
}},
8420 {"plfd", PMLS
|OP(50), P_D_MASK
, POWER10
, 0, {FRT
, D34
, PRA0
, PCREL
}},
8421 {"pstfs", PMLS
|OP(52), P_D_MASK
, POWER10
, 0, {FRS
, D34
, PRA0
, PCREL
}},
8422 {"pstxv", P8LS
|OP(54), P_D_MASK
&~OP(1), POWER10
, 0, {XTOP
, D34
, PRA0
, PCREL
}},
8423 {"pstfd", PMLS
|OP(54), P_D_MASK
, POWER10
, 0, {FRS
, D34
, PRA0
, PCREL
}},
8424 {"plq", P8LS
|OP(56), P_D_MASK
, POWER10
, 0, {RTQ
, D34
, PRAQ
, PCREL
}},
8425 {"pld", P8LS
|OP(57), P_D_MASK
, POWER10
, 0, {RT
, D34
, PRA0
, PCREL
}},
8426 {"plxvp", P8LS
|OP(58), P_D_MASK
, POWER10
, 0, {XTP
, D34
, PRA0
, PCREL
}},
8427 {"pmxvi8ger4pp", PMMIRR
|XX3(59,2), P_GER4_MASK
, POWER10
, 0, {ACC
, XA6a
, XB6a
, XMSK
, YMSK
, PMSK4
}},
8428 {"pmxvi8ger4", PMMIRR
|XX3(59,3), P_GER4_MASK
, POWER10
, 0, {ACC
, XA6a
, XB6a
, XMSK
, YMSK
, PMSK4
}},
8429 {"pmxvf16ger2pp", PMMIRR
|XX3(59,18), P_GER2_MASK
, POWER10
, 0, {ACC
, XA6a
, XB6a
, XMSK
, YMSK
, PMSK2
}},
8430 {"pmxvf16ger2", PMMIRR
|XX3(59,19), P_GER2_MASK
, POWER10
, 0, {ACC
, XA6a
, XB6a
, XMSK
, YMSK
, PMSK2
}},
8431 {"pmxvf32gerpp", PMMIRR
|XX3(59,26), P_GER_MASK
, POWER10
, 0, {ACC
, XA6a
, XB6a
, XMSK
, YMSK
}},
8432 {"pmxvf32ger", PMMIRR
|XX3(59,27), P_GER_MASK
, POWER10
, 0, {ACC
, XA6a
, XB6a
, XMSK
, YMSK
}},
8433 {"pmxvi4ger8pp", PMMIRR
|XX3(59,34), P_GER8_MASK
, POWER10
, 0, {ACC
, XA6a
, XB6a
, XMSK
, YMSK
, PMSK8
}},
8434 {"pmxvi4ger8", PMMIRR
|XX3(59,35), P_GER8_MASK
, POWER10
, 0, {ACC
, XA6a
, XB6a
, XMSK
, YMSK
, PMSK8
}},
8435 {"pmxvi16ger2spp",PMMIRR
|XX3(59,42), P_GER2_MASK
, POWER10
, 0, {ACC
, XA6a
, XB6a
, XMSK
, YMSK
, PMSK2
}},
8436 {"pmxvi16ger2s", PMMIRR
|XX3(59,43), P_GER2_MASK
, POWER10
, 0, {ACC
, XA6a
, XB6a
, XMSK
, YMSK
, PMSK2
}},
8437 {"pmxvbf16ger2pp",PMMIRR
|XX3(59,50), P_GER2_MASK
, POWER10
, 0, {ACC
, XA6a
, XB6a
, XMSK
, YMSK
, PMSK2
}},
8438 {"pmxvbf16ger2", PMMIRR
|XX3(59,51), P_GER2_MASK
, POWER10
, 0, {ACC
, XA6a
, XB6a
, XMSK
, YMSK
, PMSK2
}},
8439 {"pmxvf64gerpp", PMMIRR
|XX3(59,58), P_GER64_MASK
, POWER10
, 0, {ACC
, XA6ap
, XB6a
, XMSK
, YMSK2
}},
8440 {"pmxvf64ger", PMMIRR
|XX3(59,59), P_GER64_MASK
, POWER10
, 0, {ACC
, XA6ap
, XB6a
, XMSK
, YMSK2
}},
8441 {"pmxvi16ger2", PMMIRR
|XX3(59,75), P_GER2_MASK
, POWER10
, 0, {ACC
, XA6a
, XB6a
, XMSK
, YMSK
, PMSK2
}},
8442 {"pmxvf16ger2np", PMMIRR
|XX3(59,82), P_GER2_MASK
, POWER10
, 0, {ACC
, XA6a
, XB6a
, XMSK
, YMSK
, PMSK2
}},
8443 {"pmxvf32gernp", PMMIRR
|XX3(59,90), P_GER_MASK
, POWER10
, 0, {ACC
, XA6a
, XB6a
, XMSK
, YMSK
}},
8444 {"pmxvi8ger4spp", PMMIRR
|XX3(59,99), P_GER4_MASK
, POWER10
, 0, {ACC
, XA6a
, XB6a
, XMSK
, YMSK
, PMSK4
}},
8445 {"pmxvi16ger2pp", PMMIRR
|XX3(59,107), P_GER2_MASK
, POWER10
, 0, {ACC
, XA6a
, XB6a
, XMSK
, YMSK
, PMSK2
}},
8446 {"pmxvbf16ger2np",PMMIRR
|XX3(59,114), P_GER2_MASK
, POWER10
, 0, {ACC
, XA6a
, XB6a
, XMSK
, YMSK
, PMSK2
}},
8447 {"pmxvf64gernp", PMMIRR
|XX3(59,122), P_GER64_MASK
, POWER10
, 0, {ACC
, XA6ap
, XB6a
, XMSK
, YMSK2
}},
8448 {"pmxvf16ger2pn", PMMIRR
|XX3(59,146), P_GER2_MASK
, POWER10
, 0, {ACC
, XA6a
, XB6a
, XMSK
, YMSK
, PMSK2
}},
8449 {"pmxvf32gerpn", PMMIRR
|XX3(59,154), P_GER_MASK
, POWER10
, 0, {ACC
, XA6a
, XB6a
, XMSK
, YMSK
}},
8450 {"pmxvbf16ger2pn",PMMIRR
|XX3(59,178), P_GER2_MASK
, POWER10
, 0, {ACC
, XA6a
, XB6a
, XMSK
, YMSK
, PMSK2
}},
8451 {"pmxvf64gerpn", PMMIRR
|XX3(59,186), P_GER64_MASK
, POWER10
, 0, {ACC
, XA6ap
, XB6a
, XMSK
, YMSK2
}},
8452 {"pmxvf16ger2nn", PMMIRR
|XX3(59,210), P_GER2_MASK
, POWER10
, 0, {ACC
, XA6a
, XB6a
, XMSK
, YMSK
, PMSK2
}},
8453 {"pmxvf32gernn", PMMIRR
|XX3(59,218), P_GER_MASK
, POWER10
, 0, {ACC
, XA6a
, XB6a
, XMSK
, YMSK
}},
8454 {"pmxvbf16ger2nn",PMMIRR
|XX3(59,242), P_GER2_MASK
, POWER10
, 0, {ACC
, XA6a
, XB6a
, XMSK
, YMSK
, PMSK2
}},
8455 {"pmxvf64gernn", PMMIRR
|XX3(59,250), P_GER64_MASK
, POWER10
, 0, {ACC
, XA6ap
, XB6a
, XMSK
, YMSK2
}},
8456 {"pstq", P8LS
|OP(60), P_D_MASK
, POWER10
, 0, {RSQ
, D34
, PRA0
, PCREL
}},
8457 {"pstd", P8LS
|OP(61), P_D_MASK
, POWER10
, 0, {RS
, D34
, PRA0
, PCREL
}},
8458 {"pstxvp", P8LS
|OP(62), P_D_MASK
, POWER10
, 0, {XTP
, D34
, PRA0
, PCREL
}},
8461 const unsigned int prefix_num_opcodes
=
8462 sizeof (prefix_opcodes
) / sizeof (prefix_opcodes
[0]);
8464 /* The VLE opcode table.
8466 The format of this opcode table is the same as the main opcode table. */
8468 const struct powerpc_opcode vle_opcodes
[] = {
8469 {"se_illegal", C(0), C_MASK
, PPCVLE
, 0, {}},
8470 {"se_isync", C(1), C_MASK
, PPCVLE
, 0, {}},
8471 {"se_sc", C(2), C_MASK
, PPCVLE
, 0, {}},
8472 {"se_blr", C_LK(2,0), C_LK_MASK
, PPCVLE
, 0, {}},
8473 {"se_blrl", C_LK(2,1), C_LK_MASK
, PPCVLE
, 0, {}},
8474 {"se_bctr", C_LK(3,0), C_LK_MASK
, PPCVLE
, 0, {}},
8475 {"se_bctrl", C_LK(3,1), C_LK_MASK
, PPCVLE
, 0, {}},
8476 {"se_rfi", C(8), C_MASK
, PPCVLE
, 0, {}},
8477 {"se_rfci", C(9), C_MASK
, PPCVLE
, 0, {}},
8478 {"se_rfdi", C(10), C_MASK
, PPCVLE
, 0, {}},
8479 {"se_rfmci", C(11), C_MASK
, PPCRFMCI
|PPCVLE
, 0, {}},
8480 {"se_rfgi", C(12), C_MASK
, PPCVLE
, 0, {}},
8481 {"se_not", SE_R(0,2), SE_R_MASK
, PPCVLE
, 0, {RX
}},
8482 {"se_neg", SE_R(0,3), SE_R_MASK
, PPCVLE
, 0, {RX
}},
8483 {"se_mflr", SE_R(0,8), SE_R_MASK
, PPCVLE
, 0, {RX
}},
8484 {"se_mtlr", SE_R(0,9), SE_R_MASK
, PPCVLE
, 0, {RX
}},
8485 {"se_mfctr", SE_R(0,10), SE_R_MASK
, PPCVLE
, 0, {RX
}},
8486 {"se_mtctr", SE_R(0,11), SE_R_MASK
, PPCVLE
, 0, {RX
}},
8487 {"se_extzb", SE_R(0,12), SE_R_MASK
, PPCVLE
, 0, {RX
}},
8488 {"se_extsb", SE_R(0,13), SE_R_MASK
, PPCVLE
, 0, {RX
}},
8489 {"se_extzh", SE_R(0,14), SE_R_MASK
, PPCVLE
, 0, {RX
}},
8490 {"se_extsh", SE_R(0,15), SE_R_MASK
, PPCVLE
, 0, {RX
}},
8491 {"se_mr", SE_RR(0,1), SE_RR_MASK
, PPCVLE
, 0, {RX
, RY
}},
8492 {"se_mtar", SE_RR(0,2), SE_RR_MASK
, PPCVLE
, 0, {ARX
, RY
}},
8493 {"se_mfar", SE_RR(0,3), SE_RR_MASK
, PPCVLE
, 0, {RX
, ARY
}},
8494 {"se_add", SE_RR(1,0), SE_RR_MASK
, PPCVLE
, 0, {RX
, RY
}},
8495 {"se_mullw", SE_RR(1,1), SE_RR_MASK
, PPCVLE
, 0, {RX
, RY
}},
8496 {"se_sub", SE_RR(1,2), SE_RR_MASK
, PPCVLE
, 0, {RX
, RY
}},
8497 {"se_subf", SE_RR(1,3), SE_RR_MASK
, PPCVLE
, 0, {RX
, RY
}},
8498 {"se_cmp", SE_RR(3,0), SE_RR_MASK
, PPCVLE
, 0, {RX
, RY
}},
8499 {"se_cmpl", SE_RR(3,1), SE_RR_MASK
, PPCVLE
, 0, {RX
, RY
}},
8500 {"se_cmph", SE_RR(3,2), SE_RR_MASK
, PPCVLE
, 0, {RX
, RY
}},
8501 {"se_cmphl", SE_RR(3,3), SE_RR_MASK
, PPCVLE
, 0, {RX
, RY
}},
8503 /* by major opcode */
8504 {"zvaddih", VX(4, 0x200), VX_MASK
, PPCLSP
, 0, {RD
, RA
, EVUIMM
}},
8505 {"zvsubifh", VX(4, 0x201), VX_MASK
, PPCLSP
, 0, {RD
, RA
, EVUIMM
}},
8506 {"zvaddh", VX(4, 0x204), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8507 {"zvsubfh", VX(4, 0x205), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8508 {"zvaddsubfh", VX(4, 0x206), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8509 {"zvsubfaddh", VX(4, 0x207), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8510 {"zvaddhx", VX(4, 0x20C), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8511 {"zvsubfhx", VX(4, 0x20D), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8512 {"zvaddsubfhx", VX(4, 0x20E), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8513 {"zvsubfaddhx", VX(4, 0x20F), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8514 {"zaddwus", VX(4, 0x210), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8515 {"zsubfwus", VX(4, 0x211), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8516 {"zaddwss", VX(4, 0x212), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8517 {"zsubfwss", VX(4, 0x213), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8518 {"zvaddhus", VX(4, 0x214), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8519 {"zvsubfhus", VX(4, 0x215), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8520 {"zvaddhss", VX(4, 0x216), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8521 {"zvsubfhss", VX(4, 0x217), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8522 {"zvaddsubfhss", VX(4, 0x21A), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8523 {"zvsubfaddhss", VX(4, 0x21B), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8524 {"zvaddhxss", VX(4, 0x21C), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8525 {"zvsubfhxss", VX(4, 0x21D), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8526 {"zvaddsubfhxss", VX(4, 0x21E), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8527 {"zvsubfaddhxss", VX(4, 0x21F), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8528 {"zaddheuw", VX(4, 0x220), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8529 {"zsubfheuw", VX(4, 0x221), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8530 {"zaddhesw", VX(4, 0x222), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8531 {"zsubfhesw", VX(4, 0x223), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8532 {"zaddhouw", VX(4, 0x224), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8533 {"zsubfhouw", VX(4, 0x225), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8534 {"zaddhosw", VX(4, 0x226), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8535 {"zsubfhosw", VX(4, 0x227), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8536 {"zvmergehih", VX(4, 0x22C), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8537 {"zvmergeloh", VX(4, 0x22D), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8538 {"zvmergehiloh", VX(4, 0x22E), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8539 {"zvmergelohih", VX(4, 0x22F), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8540 {"zvcmpgthu", VX(4, 0x230), VX_MASK
, PPCLSP
, 0, {CRFD
, RA
, RB
}},
8541 {"zvcmpgths", VX(4, 0x230), VX_MASK
, PPCLSP
, 0, {CRFD
, RA
, RB
}},
8542 {"zvcmplthu", VX(4, 0x231), VX_MASK
, PPCLSP
, 0, {CRFD
, RA
, RB
}},
8543 {"zvcmplths", VX(4, 0x231), VX_MASK
, PPCLSP
, 0, {CRFD
, RA
, RB
}},
8544 {"zvcmpeqh", VX(4, 0x232), VX_MASK
, PPCLSP
, 0, {CRFD
, RA
, RB
}},
8545 {"zpkswgshfrs", VX(4, 0x238), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8546 {"zpkswgswfrs", VX(4, 0x239), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8547 {"zvpkshgwshfrs", VX(4, 0x23A), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8548 {"zvpkswshfrs", VX(4, 0x23B), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8549 {"zvpkswuhs", VX(4, 0x23C), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8550 {"zvpkswshs", VX(4, 0x23D), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8551 {"zvpkuwuhs", VX(4, 0x23E), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8552 {"zvsplatih", VX_LSP(4, 0x23F), VX_LSP_MASK
, PPCLSP
, 0, {RD
, SIMM
}},
8553 {"zvsplatfih", VX_LSP(4, 0xA3F), VX_LSP_MASK
, PPCLSP
, 0, {RD
, SIMM
}},
8554 {"zcntlsw", VX_LSP(4, 0x2A3F), VX_LSP_MASK
, PPCLSP
, 0, {RD
, RA
}},
8555 {"zvcntlzh", VX_LSP(4, 0x323F), VX_LSP_MASK
, PPCLSP
, 0, {RD
, RA
}},
8556 {"zvcntlsh", VX_LSP(4, 0x3A3F), VX_LSP_MASK
, PPCLSP
, 0, {RD
, RA
}},
8557 {"znegws", VX_LSP(4, 0x4A3F), VX_LSP_MASK
, PPCLSP
, 0, {RD
, RA
}},
8558 {"zvnegh", VX_LSP(4, 0x523F), VX_LSP_MASK
, PPCLSP
, 0, {RD
, RA
}},
8559 {"zvneghs", VX_LSP(4, 0x5A3F), VX_LSP_MASK
, PPCLSP
, 0, {RD
, RA
}},
8560 {"zvnegho", VX_LSP(4, 0x623F), VX_LSP_MASK
, PPCLSP
, 0, {RD
, RA
}},
8561 {"zvneghos", VX_LSP(4, 0x6A3F), VX_LSP_MASK
, PPCLSP
, 0, {RD
, RA
}},
8562 {"zrndwh", VX_LSP(4, 0x823F), VX_LSP_MASK
, PPCLSP
, 0, {RD
, RA
}},
8563 {"zrndwhss", VX_LSP(4, 0x8A3F), VX_LSP_MASK
, PPCLSP
, 0, {RD
, RA
}},
8564 {"zvabsh", VX_LSP(4, 0xA23F), VX_LSP_MASK
, PPCLSP
, 0, {RD
, RA
}},
8565 {"zvabshs", VX_LSP(4, 0xAA3F), VX_LSP_MASK
, PPCLSP
, 0, {RD
, RA
}},
8566 {"zabsw", VX_LSP(4, 0xB23F), VX_LSP_MASK
, PPCLSP
, 0, {RD
, RA
}},
8567 {"zabsws", VX_LSP(4, 0xBA3F), VX_LSP_MASK
, PPCLSP
, 0, {RD
, RA
}},
8568 {"zsatswuw", VX_LSP(4, 0xC23F), VX_LSP_MASK
, PPCLSP
, 0, {RD
, RA
}},
8569 {"zsatuwsw", VX_LSP(4, 0xCA3F), VX_LSP_MASK
, PPCLSP
, 0, {RD
, RA
}},
8570 {"zsatswuh", VX_LSP(4, 0xD23F), VX_LSP_MASK
, PPCLSP
, 0, {RD
, RA
}},
8571 {"zsatswsh", VX_LSP(4, 0xDA3F), VX_LSP_MASK
, PPCLSP
, 0, {RD
, RA
}},
8572 {"zvsatshuh", VX_LSP(4, 0xE23F), VX_LSP_MASK
, PPCLSP
, 0, {RD
, RA
}},
8573 {"zvsatuhsh", VX_LSP(4, 0xEA3F), VX_LSP_MASK
, PPCLSP
, 0, {RD
, RA
}},
8574 {"zsatuwuh", VX_LSP(4, 0xF23F), VX_LSP_MASK
, PPCLSP
, 0, {RD
, RA
}},
8575 {"zsatuwsh", VX_LSP(4, 0xFA3F), VX_LSP_MASK
, PPCLSP
, 0, {RD
, RA
}},
8576 {"zsatsduw", VX(4, 0x260), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8577 {"zsatsdsw", VX(4, 0x261), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8578 {"zsatuduw", VX(4, 0x262), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8579 {"zvselh", VX(4, 0x264), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8580 {"zxtrw", VX(4, 0x264), VX_LSP_OFF_MASK
, PPCLSP
, 0, {RD
, RA
, RB
, VX_OFF
}},
8581 {"zbrminc", VX(4, 0x268), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8582 {"zcircinc", VX(4, 0x269), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8583 {"zdivwsf", VX(4, 0x26B), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8584 {"zvsrhu", VX(4, 0x270), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8585 {"zvsrhs", VX(4, 0x271), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8586 {"zvsrhiu", VX(4, 0x272), VX_MASK
, PPCLSP
, 0, {RD
, RA
, EVUIMM_LT16
}},
8587 {"zvsrhis", VX(4, 0x273), VX_MASK
, PPCLSP
, 0, {RD
, RA
, EVUIMM_LT16
}},
8588 {"zvslh", VX(4, 0x274), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8589 {"zvrlh", VX(4, 0x275), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8590 {"zvslhi", VX(4, 0x276), VX_MASK
, PPCLSP
, 0, {RD
, RA
, EVUIMM_LT16
}},
8591 {"zvrlhi", VX(4, 0x277), VX_MASK
, PPCLSP
, 0, {RD
, RA
, EVUIMM_LT16
}},
8592 {"zvslhus", VX(4, 0x278), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8593 {"zvslhss", VX(4, 0x279), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8594 {"zvslhius", VX(4, 0x27A), VX_MASK
, PPCLSP
, 0, {RD
, RA
, EVUIMM_LT16
}},
8595 {"zvslhiss", VX(4, 0x27B), VX_MASK
, PPCLSP
, 0, {RD
, RA
, EVUIMM_LT16
}},
8596 {"zslwus", VX(4, 0x27C), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8597 {"zslwss", VX(4, 0x27D), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8598 {"zslwius", VX(4, 0x27E), VX_MASK
, PPCLSP
, 0, {RD
, RA
, EVUIMM
}},
8599 {"zslwiss", VX(4, 0x27F), VX_MASK
, PPCLSP
, 0, {RD
, RA
, EVUIMM
}},
8600 {"zaddwgui", VX(4, 0x460), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
8601 {"zsubfwgui", VX(4, 0x461), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
8602 {"zaddd", VX(4, 0x462), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
8603 {"zsubfd", VX(4, 0x463), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
8604 {"zvaddsubfw", VX(4, 0x464), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
8605 {"zvsubfaddw", VX(4, 0x465), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
8606 {"zvaddw", VX(4, 0x466), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
8607 {"zvsubfw", VX(4, 0x467), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
8608 {"zaddwgsi", VX(4, 0x468), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
8609 {"zsubfwgsi", VX(4, 0x469), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
8610 {"zadddss", VX(4, 0x46A), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
8611 {"zsubfdss", VX(4, 0x46B), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
8612 {"zvaddsubfwss", VX(4, 0x46C), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
8613 {"zvsubfaddwss", VX(4, 0x46D), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
8614 {"zvaddwss", VX(4, 0x46E), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8615 {"zvsubfwss", VX(4, 0x46F), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
8616 {"zaddwgsf", VX(4, 0x470), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
8617 {"zsubfwgsf", VX(4, 0x471), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
8618 {"zadddus", VX(4, 0x472), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
8619 {"zsubfdus", VX(4, 0x473), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
8620 {"zvaddwus", VX(4, 0x476), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
8621 {"zvsubfwus", VX(4, 0x477), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
8622 {"zvunpkhgwsf", VX_LSP(4, 0x478), VX_LSP_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
}},
8623 {"zvunpkhsf", VX_LSP(4, 0xC78), VX_LSP_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
}},
8624 {"zvunpkhui", VX_LSP(4, 0x1478), VX_LSP_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
}},
8625 {"zvunpkhsi", VX_LSP(4, 0x1C78), VX_LSP_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
}},
8626 {"zunpkwgsf", VX_LSP(4, 0x2478), VX_LSP_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
}},
8627 {"zvdotphgwasmf", VX(4, 0x488), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8628 {"zvdotphgwasmfr", VX(4, 0x489), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8629 {"zvdotphgwasmfaa", VX(4, 0x48A), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8630 {"zvdotphgwasmfraa", VX(4, 0x48B), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8631 {"zvdotphgwasmfan", VX(4, 0x48C), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8632 {"zvdotphgwasmfran", VX(4, 0x48D), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8633 {"zvmhulgwsmf", VX(4, 0x490), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
8634 {"zvmhulgwsmfr", VX(4, 0x491), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
8635 {"zvmhulgwsmfaa", VX(4, 0x492), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
8636 {"zvmhulgwsmfraa", VX(4, 0x493), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
8637 {"zvmhulgwsmfan", VX(4, 0x494), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
8638 {"zvmhulgwsmfran", VX(4, 0x495), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
8639 {"zvmhulgwsmfanp", VX(4, 0x496), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
8640 {"zvmhulgwsmfranp", VX(4, 0x497), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
8641 {"zmhegwsmf", VX(4, 0x498), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8642 {"zmhegwsmfr", VX(4, 0x499), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8643 {"zmhegwsmfaa", VX(4, 0x49A), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8644 {"zmhegwsmfraa", VX(4, 0x49B), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8645 {"zmhegwsmfan", VX(4, 0x49C), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8646 {"zmhegwsmfran", VX(4, 0x49D), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8647 {"zvdotphxgwasmf", VX(4, 0x4A8), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8648 {"zvdotphxgwasmfr", VX(4, 0x4A9), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8649 {"zvdotphxgwasmfaa", VX(4, 0x4AA), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8650 {"zvdotphxgwasmfraa", VX(4, 0x4AB), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8651 {"zvdotphxgwasmfan", VX(4, 0x4AC), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8652 {"zvdotphxgwasmfran", VX(4, 0x4AD), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8653 {"zvmhllgwsmf", VX(4, 0x4B0), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
8654 {"zvmhllgwsmfr", VX(4, 0x4B1), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
8655 {"zvmhllgwsmfaa", VX(4, 0x4B2), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
8656 {"zvmhllgwsmfraa", VX(4, 0x4B3), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
8657 {"zvmhllgwsmfan", VX(4, 0x4B4), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
8658 {"zvmhllgwsmfran", VX(4, 0x4B5), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
8659 {"zvmhllgwsmfanp", VX(4, 0x4B6), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
8660 {"zvmhllgwsmfranp", VX(4, 0x4B7), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
8661 {"zmheogwsmf", VX(4, 0x4B8), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8662 {"zmheogwsmfr", VX(4, 0x4B9), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8663 {"zmheogwsmfaa", VX(4, 0x4BA), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8664 {"zmheogwsmfraa", VX(4, 0x4BB), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8665 {"zmheogwsmfan", VX(4, 0x4BC), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8666 {"zmheogwsmfran", VX(4, 0x4BD), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8667 {"zvdotphgwssmf", VX(4, 0x4C8), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8668 {"zvdotphgwssmfr", VX(4, 0x4C9), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8669 {"zvdotphgwssmfaa", VX(4, 0x4CA), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8670 {"zvdotphgwssmfraa", VX(4, 0x4CB), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8671 {"zvdotphgwssmfan", VX(4, 0x4CC), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8672 {"zvdotphgwssmfran", VX(4, 0x4CD), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8673 {"zvmhuugwsmf", VX(4, 0x4D0), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
8674 {"zvmhuugwsmfr", VX(4, 0x4D1), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
8675 {"zvmhuugwsmfaa", VX(4, 0x4D2), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
8676 {"zvmhuugwsmfraa", VX(4, 0x4D3), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
8677 {"zvmhuugwsmfan", VX(4, 0x4D4), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
8678 {"zvmhuugwsmfran", VX(4, 0x4D5), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
8679 {"zvmhuugwsmfanp", VX(4, 0x4D6), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
8680 {"zvmhuugwsmfranp", VX(4, 0x4D7), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
8681 {"zmhogwsmf", VX(4, 0x4D8), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8682 {"zmhogwsmfr", VX(4, 0x4D9), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8683 {"zmhogwsmfaa", VX(4, 0x4DA), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8684 {"zmhogwsmfraa", VX(4, 0x4DB), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8685 {"zmhogwsmfan", VX(4, 0x4DC), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8686 {"zmhogwsmfran", VX(4, 0x4DD), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8687 {"zvmhxlgwsmf", VX(4, 0x4F0), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
8688 {"zvmhxlgwsmfr", VX(4, 0x4F1), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
8689 {"zvmhxlgwsmfaa", VX(4, 0x4F2), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
8690 {"zvmhxlgwsmfraa", VX(4, 0x4F3), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
8691 {"zvmhxlgwsmfan", VX(4, 0x4F4), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
8692 {"zvmhxlgwsmfran", VX(4, 0x4F5), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
8693 {"zvmhxlgwsmfanp", VX(4, 0x4F6), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
8694 {"zvmhxlgwsmfranp", VX(4, 0x4F7), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
8695 {"zmhegui", VX(4, 0x500), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
8696 {"zvdotphgaui", VX(4, 0x501), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
8697 {"zmheguiaa", VX(4, 0x502), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
8698 {"zvdotphgauiaa", VX(4, 0x503), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
8699 {"zmheguian", VX(4, 0x504), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
8700 {"zvdotphgauian", VX(4, 0x505), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
8701 {"zmhegsi", VX(4, 0x508), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
8702 {"zvdotphgasi", VX(4, 0x509), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
8703 {"zmhegsiaa", VX(4, 0x50A), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
8704 {"zvdotphgasiaa", VX(4, 0x50B), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
8705 {"zmhegsian", VX(4, 0x50C), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
8706 {"zvdotphgasian", VX(4, 0x50D), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
8707 {"zmhegsui", VX(4, 0x510), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
8708 {"zvdotphgasui", VX(4, 0x511), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
8709 {"zmhegsuiaa", VX(4, 0x512), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
8710 {"zvdotphgasuiaa", VX(4, 0x513), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
8711 {"zmhegsuian", VX(4, 0x514), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
8712 {"zvdotphgasuian", VX(4, 0x515), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
8713 {"zmhegsmf", VX(4, 0x518), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
8714 {"zvdotphgasmf", VX(4, 0x519), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
8715 {"zmhegsmfaa", VX(4, 0x51A), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
8716 {"zvdotphgasmfaa", VX(4, 0x51B), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
8717 {"zmhegsmfan", VX(4, 0x51C), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
8718 {"zvdotphgasmfan", VX(4, 0x51D), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
8719 {"zmheogui", VX(4, 0x520), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
8720 {"zvdotphxgaui", VX(4, 0x521), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
8721 {"zmheoguiaa", VX(4, 0x522), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
8722 {"zvdotphxgauiaa", VX(4, 0x523), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
8723 {"zmheoguian", VX(4, 0x524), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
8724 {"zvdotphxgauian", VX(4, 0x525), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
8725 {"zmheogsi", VX(4, 0x528), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
8726 {"zvdotphxgasi", VX(4, 0x529), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
8727 {"zmheogsiaa", VX(4, 0x52A), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
8728 {"zvdotphxgasiaa", VX(4, 0x52B), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
8729 {"zmheogsian", VX(4, 0x52C), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
8730 {"zvdotphxgasian", VX(4, 0x52D), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
8731 {"zmheogsui", VX(4, 0x530), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
8732 {"zvdotphxgasui", VX(4, 0x531), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
8733 {"zmheogsuiaa", VX(4, 0x532), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
8734 {"zvdotphxgasuiaa", VX(4, 0x533), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
8735 {"zmheogsuian", VX(4, 0x534), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
8736 {"zvdotphxgasuian", VX(4, 0x535), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
8737 {"zmheogsmf", VX(4, 0x538), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
8738 {"zvdotphxgasmf", VX(4, 0x539), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
8739 {"zmheogsmfaa", VX(4, 0x53A), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
8740 {"zvdotphxgasmfaa", VX(4, 0x53B), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
8741 {"zmheogsmfan", VX(4, 0x53C), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
8742 {"zvdotphxgasmfan", VX(4, 0x53D), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
8743 {"zmhogui", VX(4, 0x540), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
8744 {"zvdotphgsui", VX(4, 0x541), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
8745 {"zmhoguiaa", VX(4, 0x542), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
8746 {"zvdotphgsuiaa", VX(4, 0x543), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
8747 {"zmhoguian", VX(4, 0x544), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
8748 {"zvdotphgsuian", VX(4, 0x545), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
8749 {"zmhogsi", VX(4, 0x548), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
8750 {"zvdotphgssi", VX(4, 0x549), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
8751 {"zmhogsiaa", VX(4, 0x54A), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
8752 {"zvdotphgssiaa", VX(4, 0x54B), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
8753 {"zmhogsian", VX(4, 0x54C), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
8754 {"zvdotphgssian", VX(4, 0x54D), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
8755 {"zmhogsui", VX(4, 0x550), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
8756 {"zvdotphgssui", VX(4, 0x551), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
8757 {"zmhogsuiaa", VX(4, 0x552), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
8758 {"zvdotphgssuiaa", VX(4, 0x553), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
8759 {"zmhogsuian", VX(4, 0x554), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
8760 {"zvdotphgssuian", VX(4, 0x555), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
8761 {"zmhogsmf", VX(4, 0x558), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
8762 {"zvdotphgssmf", VX(4, 0x559), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
8763 {"zmhogsmfaa", VX(4, 0x55A), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
8764 {"zvdotphgssmfaa", VX(4, 0x55B), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
8765 {"zmhogsmfan", VX(4, 0x55C), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
8766 {"zvdotphgssmfan", VX(4, 0x55D), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
8767 {"zmwgui", VX(4, 0x560), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
8768 {"zmwguiaa", VX(4, 0x562), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
8769 {"zmwguiaas", VX(4, 0x563), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
8770 {"zmwguian", VX(4, 0x564), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
8771 {"zmwguians", VX(4, 0x565), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
8772 {"zmwgsi", VX(4, 0x568), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
8773 {"zmwgsiaa", VX(4, 0x56A), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
8774 {"zmwgsiaas", VX(4, 0x56B), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
8775 {"zmwgsian", VX(4, 0x56C), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
8776 {"zmwgsians", VX(4, 0x56D), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
8777 {"zmwgsui", VX(4, 0x570), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
8778 {"zmwgsuiaa", VX(4, 0x572), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
8779 {"zmwgsuiaas", VX(4, 0x573), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
8780 {"zmwgsuian", VX(4, 0x574), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
8781 {"zmwgsuians", VX(4, 0x575), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
8782 {"zmwgsmf", VX(4, 0x578), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
8783 {"zmwgsmfr", VX(4, 0x579), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
8784 {"zmwgsmfaa", VX(4, 0x57A), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
8785 {"zmwgsmfraa", VX(4, 0x57B), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
8786 {"zmwgsmfan", VX(4, 0x57C), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
8787 {"zmwgsmfran", VX(4, 0x57D), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
8788 {"zvmhului", VX(4, 0x580), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
8789 {"zvmhuluiaa", VX(4, 0x582), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
8790 {"zvmhuluiaas", VX(4, 0x583), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
8791 {"zvmhuluian", VX(4, 0x584), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
8792 {"zvmhuluians", VX(4, 0x585), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
8793 {"zvmhuluianp", VX(4, 0x586), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
8794 {"zvmhuluianps", VX(4, 0x587), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
8795 {"zvmhulsi", VX(4, 0x588), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
8796 {"zvmhulsiaa", VX(4, 0x58A), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
8797 {"zvmhulsiaas", VX(4, 0x58B), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
8798 {"zvmhulsian", VX(4, 0x58C), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
8799 {"zvmhulsians", VX(4, 0x58D), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
8800 {"zvmhulsianp", VX(4, 0x58E), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
8801 {"zvmhulsianps", VX(4, 0x58F), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
8802 {"zvmhulsui", VX(4, 0x590), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
8803 {"zvmhulsuiaa", VX(4, 0x592), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
8804 {"zvmhulsuiaas", VX(4, 0x593), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
8805 {"zvmhulsuian", VX(4, 0x594), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
8806 {"zvmhulsuians", VX(4, 0x595), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
8807 {"zvmhulsuianp", VX(4, 0x596), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
8808 {"zvmhulsuianps", VX(4, 0x597), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
8809 {"zvmhulsf", VX(4, 0x598), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
8810 {"zvmhulsfr", VX(4, 0x599), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
8811 {"zvmhulsfaas", VX(4, 0x59A), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
8812 {"zvmhulsfraas", VX(4, 0x59B), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
8813 {"zvmhulsfans", VX(4, 0x59C), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
8814 {"zvmhulsfrans", VX(4, 0x59D), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
8815 {"zvmhulsfanps", VX(4, 0x59E), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
8816 {"zvmhulsfranps", VX(4, 0x59F), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
8817 {"zvmhllui", VX(4, 0x5A0), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
8818 {"zvmhlluiaa", VX(4, 0x5A2), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
8819 {"zvmhlluiaas", VX(4, 0x5A3), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
8820 {"zvmhlluian", VX(4, 0x5A4), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
8821 {"zvmhlluians", VX(4, 0x5A5), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
8822 {"zvmhlluianp", VX(4, 0x5A6), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
8823 {"zvmhlluianps", VX(4, 0x5A7), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
8824 {"zvmhllsi", VX(4, 0x5A8), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
8825 {"zvmhllsiaa", VX(4, 0x5AA), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
8826 {"zvmhllsiaas", VX(4, 0x5AB), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
8827 {"zvmhllsian", VX(4, 0x5AC), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
8828 {"zvmhllsians", VX(4, 0x5AD), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
8829 {"zvmhllsianp", VX(4, 0x5AE), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
8830 {"zvmhllsianps", VX(4, 0x5AF), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
8831 {"zvmhllsui", VX(4, 0x5B0), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
8832 {"zvmhllsuiaa", VX(4, 0x5B2), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
8833 {"zvmhllsuiaas", VX(4, 0x5B3), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
8834 {"zvmhllsuian", VX(4, 0x5B4), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
8835 {"zvmhllsuians", VX(4, 0x5B5), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
8836 {"zvmhllsuianp", VX(4, 0x5B6), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
8837 {"zvmhllsuianps", VX(4, 0x5B7), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
8838 {"zvmhllsf", VX(4, 0x5B8), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
8839 {"zvmhllsfr", VX(4, 0x5B9), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
8840 {"zvmhllsfaas", VX(4, 0x5BA), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
8841 {"zvmhllsfraas", VX(4, 0x5BB), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
8842 {"zvmhllsfans", VX(4, 0x5BC), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
8843 {"zvmhllsfrans", VX(4, 0x5BD), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
8844 {"zvmhllsfanps", VX(4, 0x5BE), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
8845 {"zvmhllsfranps", VX(4, 0x5BF), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
8846 {"zvmhuuui", VX(4, 0x5C0), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
8847 {"zvmhuuuiaa", VX(4, 0x5C2), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
8848 {"zvmhuuuiaas", VX(4, 0x5C3), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
8849 {"zvmhuuuian", VX(4, 0x5C4), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
8850 {"zvmhuuuians", VX(4, 0x5C5), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
8851 {"zvmhuuuianp", VX(4, 0x5C6), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
8852 {"zvmhuuuianps", VX(4, 0x5C7), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
8853 {"zvmhuusi", VX(4, 0x5C8), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
8854 {"zvmhuusiaa", VX(4, 0x5CA), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
8855 {"zvmhuusiaas", VX(4, 0x5CB), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
8856 {"zvmhuusian", VX(4, 0x5CC), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
8857 {"zvmhuusians", VX(4, 0x5CD), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
8858 {"zvmhuusianp", VX(4, 0x5CE), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
8859 {"zvmhuusianps", VX(4, 0x5CF), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
8860 {"zvmhuusui", VX(4, 0x5D0), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
8861 {"zvmhuusuiaa", VX(4, 0x5D2), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
8862 {"zvmhuusuiaas", VX(4, 0x5D3), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
8863 {"zvmhuusuian", VX(4, 0x5D4), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
8864 {"zvmhuusuians", VX(4, 0x5D5), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
8865 {"zvmhuusuianp", VX(4, 0x5D6), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
8866 {"zvmhuusuianps", VX(4, 0x5D7), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
8867 {"zvmhuusf", VX(4, 0x5D8), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
8868 {"zvmhuusfr", VX(4, 0x5D9), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
8869 {"zvmhuusfaas", VX(4, 0x5DA), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
8870 {"zvmhuusfraas", VX(4, 0x5DB), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
8871 {"zvmhuusfans", VX(4, 0x5DC), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
8872 {"zvmhuusfrans", VX(4, 0x5DD), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
8873 {"zvmhuusfanps", VX(4, 0x5DE), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
8874 {"zvmhuusfranps", VX(4, 0x5DF), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
8875 {"zvmhxlui", VX(4, 0x5E0), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
8876 {"zvmhxluiaa", VX(4, 0x5E2), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
8877 {"zvmhxluiaas", VX(4, 0x5E3), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
8878 {"zvmhxluian", VX(4, 0x5E4), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
8879 {"zvmhxluians", VX(4, 0x5E5), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
8880 {"zvmhxluianp", VX(4, 0x5E6), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
8881 {"zvmhxluianps", VX(4, 0x5E7), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
8882 {"zvmhxlsi", VX(4, 0x5E8), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
8883 {"zvmhxlsiaa", VX(4, 0x5EA), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
8884 {"zvmhxlsiaas", VX(4, 0x5EB), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
8885 {"zvmhxlsian", VX(4, 0x5EC), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
8886 {"zvmhxlsians", VX(4, 0x5ED), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
8887 {"zvmhxlsianp", VX(4, 0x5EE), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
8888 {"zvmhxlsianps", VX(4, 0x5EF), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
8889 {"zvmhxlsui", VX(4, 0x5F0), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
8890 {"zvmhxlsuiaa", VX(4, 0x5F2), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
8891 {"zvmhxlsuiaas", VX(4, 0x5F3), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
8892 {"zvmhxlsuian", VX(4, 0x5F4), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
8893 {"zvmhxlsuians", VX(4, 0x5F5), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
8894 {"zvmhxlsuianp", VX(4, 0x5F6), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
8895 {"zvmhxlsuianps", VX(4, 0x5F7), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
8896 {"zvmhxlsf", VX(4, 0x5F8), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
8897 {"zvmhxlsfr", VX(4, 0x5F9), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
8898 {"zvmhxlsfaas", VX(4, 0x5FA), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
8899 {"zvmhxlsfraas", VX(4, 0x5FB), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
8900 {"zvmhxlsfans", VX(4, 0x5FC), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
8901 {"zvmhxlsfrans", VX(4, 0x5FD), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
8902 {"zvmhxlsfanps", VX(4, 0x5FE), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
8903 {"zvmhxlsfranps", VX(4, 0x5FF), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
8904 {"zmheui", VX(4, 0x600), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8905 {"zmheuiaa", VX(4, 0x602), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8906 {"zmheuiaas", VX(4, 0x603), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8907 {"zmheuian", VX(4, 0x604), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8908 {"zmheuians", VX(4, 0x605), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8909 {"zmhesi", VX(4, 0x608), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8910 {"zmhesiaa", VX(4, 0x60A), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8911 {"zmhesiaas", VX(4, 0x60B), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8912 {"zmhesian", VX(4, 0x60C), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8913 {"zmhesians", VX(4, 0x60D), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8914 {"zmhesui", VX(4, 0x610), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8915 {"zmhesuiaa", VX(4, 0x612), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8916 {"zmhesuiaas", VX(4, 0x613), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8917 {"zmhesuian", VX(4, 0x614), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8918 {"zmhesuians", VX(4, 0x615), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8919 {"zmhesf", VX(4, 0x618), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8920 {"zmhesfr", VX(4, 0x619), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8921 {"zmhesfaas", VX(4, 0x61A), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8922 {"zmhesfraas", VX(4, 0x61B), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8923 {"zmhesfans", VX(4, 0x61C), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8924 {"zmhesfrans", VX(4, 0x61D), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8925 {"zmheoui", VX(4, 0x620), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8926 {"zmheouiaa", VX(4, 0x622), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8927 {"zmheouiaas", VX(4, 0x623), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8928 {"zmheouian", VX(4, 0x624), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8929 {"zmheouians", VX(4, 0x625), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8930 {"zmheosi", VX(4, 0x628), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8931 {"zmheosiaa", VX(4, 0x62A), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8932 {"zmheosiaas", VX(4, 0x62B), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8933 {"zmheosian", VX(4, 0x62C), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8934 {"zmheosians", VX(4, 0x62D), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8935 {"zmheosui", VX(4, 0x630), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8936 {"zmheosuiaa", VX(4, 0x632), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8937 {"zmheosuiaas", VX(4, 0x633), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8938 {"zmheosuian", VX(4, 0x634), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8939 {"zmheosuians", VX(4, 0x635), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8940 {"zmheosf", VX(4, 0x638), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8941 {"zmheosfr", VX(4, 0x639), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8942 {"zmheosfaas", VX(4, 0x63A), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8943 {"zmheosfraas", VX(4, 0x63B), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8944 {"zmheosfans", VX(4, 0x63C), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8945 {"zmheosfrans", VX(4, 0x63D), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8946 {"zmhoui", VX(4, 0x640), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8947 {"zmhouiaa", VX(4, 0x642), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8948 {"zmhouiaas", VX(4, 0x643), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8949 {"zmhouian", VX(4, 0x644), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8950 {"zmhouians", VX(4, 0x645), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8951 {"zmhosi", VX(4, 0x648), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8952 {"zmhosiaa", VX(4, 0x64A), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8953 {"zmhosiaas", VX(4, 0x64B), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8954 {"zmhosian", VX(4, 0x64C), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8955 {"zmhosians", VX(4, 0x64D), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8956 {"zmhosui", VX(4, 0x650), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8957 {"zmhosuiaa", VX(4, 0x652), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8958 {"zmhosuiaas", VX(4, 0x653), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8959 {"zmhosuian", VX(4, 0x654), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8960 {"zmhosuians", VX(4, 0x655), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8961 {"zmhosf", VX(4, 0x658), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8962 {"zmhosfr", VX(4, 0x659), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8963 {"zmhosfaas", VX(4, 0x65A), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8964 {"zmhosfraas", VX(4, 0x65B), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8965 {"zmhosfans", VX(4, 0x65C), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8966 {"zmhosfrans", VX(4, 0x65D), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8967 {"zvmhuih", VX(4, 0x660), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8968 {"zvmhuihs", VX(4, 0x661), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8969 {"zvmhuiaah", VX(4, 0x662), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8970 {"zvmhuiaahs", VX(4, 0x663), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8971 {"zvmhuianh", VX(4, 0x664), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8972 {"zvmhuianhs", VX(4, 0x665), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8973 {"zvmhsihs", VX(4, 0x669), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8974 {"zvmhsiaahs", VX(4, 0x66B), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8975 {"zvmhsianhs", VX(4, 0x66D), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8976 {"zvmhsuihs", VX(4, 0x671), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8977 {"zvmhsuiaahs", VX(4, 0x673), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8978 {"zvmhsuianhs", VX(4, 0x675), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8979 {"zvmhsfh", VX(4, 0x678), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8980 {"zvmhsfrh", VX(4, 0x679), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8981 {"zvmhsfaahs", VX(4, 0x67A), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8982 {"zvmhsfraahs", VX(4, 0x67B), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8983 {"zvmhsfanhs", VX(4, 0x67C), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8984 {"zvmhsfranhs", VX(4, 0x67D), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8985 {"zvdotphaui", VX(4, 0x680), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8986 {"zvdotphauis", VX(4, 0x681), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8987 {"zvdotphauiaa", VX(4, 0x682), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8988 {"zvdotphauiaas", VX(4, 0x683), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8989 {"zvdotphauian", VX(4, 0x684), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8990 {"zvdotphauians", VX(4, 0x685), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8991 {"zvdotphasi", VX(4, 0x688), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8992 {"zvdotphasis", VX(4, 0x689), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8993 {"zvdotphasiaa", VX(4, 0x68A), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8994 {"zvdotphasiaas", VX(4, 0x68B), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8995 {"zvdotphasian", VX(4, 0x68C), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8996 {"zvdotphasians", VX(4, 0x68D), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8997 {"zvdotphasui", VX(4, 0x690), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8998 {"zvdotphasuis", VX(4, 0x691), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8999 {"zvdotphasuiaa", VX(4, 0x692), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
9000 {"zvdotphasuiaas", VX(4, 0x693), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
9001 {"zvdotphasuian", VX(4, 0x694), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
9002 {"zvdotphasuians", VX(4, 0x695), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
9003 {"zvdotphasfs", VX(4, 0x698), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
9004 {"zvdotphasfrs", VX(4, 0x699), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
9005 {"zvdotphasfaas", VX(4, 0x69A), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
9006 {"zvdotphasfraas", VX(4, 0x69B), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
9007 {"zvdotphasfans", VX(4, 0x69C), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
9008 {"zvdotphasfrans", VX(4, 0x69D), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
9009 {"zvdotphxaui", VX(4, 0x6A0), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
9010 {"zvdotphxauis", VX(4, 0x6A1), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
9011 {"zvdotphxauiaa", VX(4, 0x6A2), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
9012 {"zvdotphxauiaas", VX(4, 0x6A3), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
9013 {"zvdotphxauian", VX(4, 0x6A4), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
9014 {"zvdotphxauians", VX(4, 0x6A5), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
9015 {"zvdotphxasi", VX(4, 0x6A8), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
9016 {"zvdotphxasis", VX(4, 0x6A9), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
9017 {"zvdotphxasiaa", VX(4, 0x6AA), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
9018 {"zvdotphxasiaas", VX(4, 0x6AB), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
9019 {"zvdotphxasian", VX(4, 0x6AC), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
9020 {"zvdotphxasians", VX(4, 0x6AD), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
9021 {"zvdotphxasui", VX(4, 0x6B0), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
9022 {"zvdotphxasuis", VX(4, 0x6B1), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
9023 {"zvdotphxasuiaa", VX(4, 0x6B2), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
9024 {"zvdotphxasuiaas", VX(4, 0x6B3), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
9025 {"zvdotphxasuian", VX(4, 0x6B4), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
9026 {"zvdotphxasuians", VX(4, 0x6B5), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
9027 {"zvdotphxasfs", VX(4, 0x6B8), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
9028 {"zvdotphxasfrs", VX(4, 0x6B9), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
9029 {"zvdotphxasfaas", VX(4, 0x6BA), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
9030 {"zvdotphxasfraas", VX(4, 0x6BB), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
9031 {"zvdotphxasfans", VX(4, 0x6BC), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
9032 {"zvdotphxasfrans", VX(4, 0x6BD), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
9033 {"zvdotphsui", VX(4, 0x6C0), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
9034 {"zvdotphsuis", VX(4, 0x6C1), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
9035 {"zvdotphsuiaa", VX(4, 0x6C2), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
9036 {"zvdotphsuiaas", VX(4, 0x6C3), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
9037 {"zvdotphsuian", VX(4, 0x6C4), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
9038 {"zvdotphsuians", VX(4, 0x6C5), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
9039 {"zvdotphssi", VX(4, 0x6C8), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
9040 {"zvdotphssis", VX(4, 0x6C9), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
9041 {"zvdotphssiaa", VX(4, 0x6CA), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
9042 {"zvdotphssiaas", VX(4, 0x6CB), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
9043 {"zvdotphssian", VX(4, 0x6CC), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
9044 {"zvdotphssians", VX(4, 0x6CD), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
9045 {"zvdotphssui", VX(4, 0x6D0), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
9046 {"zvdotphssuis", VX(4, 0x6D1), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
9047 {"zvdotphssuiaa", VX(4, 0x6D2), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
9048 {"zvdotphssuiaas", VX(4, 0x6D3), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
9049 {"zvdotphssuian", VX(4, 0x6D4), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
9050 {"zvdotphssuians", VX(4, 0x6D5), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
9051 {"zvdotphssfs", VX(4, 0x6D8), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
9052 {"zvdotphssfrs", VX(4, 0x6D9), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
9053 {"zvdotphssfaas", VX(4, 0x6DA), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
9054 {"zvdotphssfraas", VX(4, 0x6DB), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
9055 {"zvdotphssfans", VX(4, 0x6DC), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
9056 {"zvdotphssfrans", VX(4, 0x6DD), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
9057 {"zmwluis", VX(4, 0x6E1), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
9058 {"zmwluiaa", VX(4, 0x6E2), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
9059 {"zmwluiaas", VX(4, 0x6E3), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
9060 {"zmwluian", VX(4, 0x6E4), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
9061 {"zmwluians", VX(4, 0x6E5), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
9062 {"zmwlsis", VX(4, 0x6E9), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
9063 {"zmwlsiaas", VX(4, 0x6EB), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
9064 {"zmwlsians", VX(4, 0x6ED), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
9065 {"zmwlsuis", VX(4, 0x6F1), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
9066 {"zmwlsuiaas", VX(4, 0x6F3), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
9067 {"zmwlsuians", VX(4, 0x6F5), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
9068 {"zmwsf", VX(4, 0x6F8), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
9069 {"zmwsfr", VX(4, 0x6F9), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
9070 {"zmwsfaas", VX(4, 0x6FA), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
9071 {"zmwsfraas", VX(4, 0x6FB), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
9072 {"zmwsfans", VX(4, 0x6FC), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
9073 {"zmwsfrans", VX(4, 0x6FD), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
9074 {"zlddx", VX(4, 0x300), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
9075 {"zldd", VX(4, 0x301), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, EVUIMM_8
, RA
}},
9076 {"zldwx", VX(4, 0x302), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
9077 {"zldw", VX(4, 0x303), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, EVUIMM_8
, RA
}},
9078 {"zldhx", VX(4, 0x304), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
9079 {"zldh", VX(4, 0x305), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, EVUIMM_8
, RA
}},
9080 {"zlwgsfdx", VX(4, 0x308), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
9081 {"zlwgsfd", VX(4, 0x309), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, EVUIMM_4
, RA
}},
9082 {"zlwwosdx", VX(4, 0x30A), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
9083 {"zlwwosd", VX(4, 0x30B), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, EVUIMM_4
, RA
}},
9084 {"zlwhsplatwdx", VX(4, 0x30C), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
9085 {"zlwhsplatwd", VX(4, 0x30D), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, EVUIMM_4
, RA
}},
9086 {"zlwhsplatdx", VX(4, 0x30E), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
9087 {"zlwhsplatd", VX(4, 0x30F), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, EVUIMM_4
, RA
}},
9088 {"zlwhgwsfdx", VX(4, 0x310), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
9089 {"zlwhgwsfd", VX(4, 0x311), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, EVUIMM_4
, RA
}},
9090 {"zlwhedx", VX(4, 0x312), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
9091 {"zlwhed", VX(4, 0x313), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, EVUIMM_4
, RA
}},
9092 {"zlwhosdx", VX(4, 0x314), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
9093 {"zlwhosd", VX(4, 0x315), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, EVUIMM_4
, RA
}},
9094 {"zlwhoudx", VX(4, 0x316), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
9095 {"zlwhoud", VX(4, 0x317), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, EVUIMM_4
, RA
}},
9096 {"zlwhx", VX(4, 0x318), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
9097 {"zlwh", VX(4, 0x319), VX_MASK
, PPCLSP
, 0, {RD
, EVUIMM_4
, RA
}},
9098 {"zlwwx", VX(4, 0x31A), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
9099 {"zlww", VX(4, 0x31B), VX_MASK
, PPCLSP
, 0, {RD
, EVUIMM_4
, RA
}},
9100 {"zlhgwsfx", VX(4, 0x31C), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
9101 {"zlhgwsf", VX(4, 0x31D), VX_MASK
, PPCLSP
, 0, {RD
, EVUIMM_2
, RA
}},
9102 {"zlhhsplatx", VX(4, 0x31E), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
9103 {"zlhhsplat", VX(4, 0x31F), VX_MASK
, PPCLSP
, 0, {RD
, EVUIMM_2
, RA
}},
9104 {"zstddx", VX(4, 0x320), VX_MASK
, PPCLSP
, 0, {RS_EVEN
, RA
, RB
}},
9105 {"zstdd", VX(4, 0x321), VX_MASK
, PPCLSP
, 0, {RS_EVEN
, EVUIMM_8
, RA
}},
9106 {"zstdwx", VX(4, 0x322), VX_MASK
, PPCLSP
, 0, {RS_EVEN
, RA
, RB
}},
9107 {"zstdw", VX(4, 0x323), VX_MASK
, PPCLSP
, 0, {RS_EVEN
, EVUIMM_8
, RA
}},
9108 {"zstdhx", VX(4, 0x324), VX_MASK
, PPCLSP
, 0, {RS_EVEN
, RA
, RB
}},
9109 {"zstdh", VX(4, 0x325), VX_MASK
, PPCLSP
, 0, {RS_EVEN
, EVUIMM_8
, RA
}},
9110 {"zstwhedx", VX(4, 0x328), VX_MASK
, PPCLSP
, 0, {RS_EVEN
, RA
, RB
}},
9111 {"zstwhed", VX(4, 0x329), VX_MASK
, PPCLSP
, 0, {RS_EVEN
, EVUIMM_4
, RA
}},
9112 {"zstwhodx", VX(4, 0x32A), VX_MASK
, PPCLSP
, 0, {RS_EVEN
, RA
, RB
}},
9113 {"zstwhod", VX(4, 0x32B), VX_MASK
, PPCLSP
, 0, {RS_EVEN
, EVUIMM_4
, RA
}},
9114 {"zlhhex", VX(4, 0x330), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
9115 {"zlhhe", VX(4, 0x331), VX_MASK
, PPCLSP
, 0, {RD
, EVUIMM_2
, RA
}},
9116 {"zlhhosx", VX(4, 0x332), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
9117 {"zlhhos", VX(4, 0x333), VX_MASK
, PPCLSP
, 0, {RD
, EVUIMM_2
, RA
}},
9118 {"zlhhoux", VX(4, 0x334), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
9119 {"zlhhou", VX(4, 0x335), VX_MASK
, PPCLSP
, 0, {RD
, EVUIMM_2
, RA
}},
9120 {"zsthex", VX(4, 0x338), VX_MASK
, PPCLSP
, 0, {RS
, RA
, RB
}},
9121 {"zsthe", VX(4, 0x339), VX_MASK
, PPCLSP
, 0, {RS
, EVUIMM_2
, RA
}},
9122 {"zsthox", VX(4, 0x33A), VX_MASK
, PPCLSP
, 0, {RS
, RA
, RB
}},
9123 {"zstho", VX(4, 0x33B), VX_MASK
, PPCLSP
, 0, {RS
, EVUIMM_2
, RA
}},
9124 {"zstwhx", VX(4, 0x33C), VX_MASK
, PPCLSP
, 0, {RS
, RA
, RB
}},
9125 {"zstwh", VX(4, 0x33D), VX_MASK
, PPCLSP
, 0, {RS
, EVUIMM_4
, RA
}},
9126 {"zstwwx", VX(4, 0x33E), VX_MASK
, PPCLSP
, 0, {RS
, RA
, RB
}},
9127 {"zstww", VX(4, 0x33F), VX_MASK
, PPCLSP
, 0, {RS
, EVUIMM_4
, RA
}},
9128 {"zlddmx", VX(4, 0x340), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
9129 {"zlddu", VX(4, 0x341), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, EVUIMM_8_EX0
, RA
}},
9130 {"zldwmx", VX(4, 0x342), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
9131 {"zldwu", VX(4, 0x343), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, EVUIMM_8_EX0
, RA
}},
9132 {"zldhmx", VX(4, 0x344), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
9133 {"zldhu", VX(4, 0x345), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, EVUIMM_8_EX0
, RA
}},
9134 {"zlwgsfdmx", VX(4, 0x348), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
9135 {"zlwgsfdu", VX(4, 0x349), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, EVUIMM_4_EX0
, RA
}},
9136 {"zlwwosdmx", VX(4, 0x34A), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
9137 {"zlwwosdu", VX(4, 0x34B), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, EVUIMM_4_EX0
, RA
}},
9138 {"zlwhsplatwdmx", VX(4, 0x34C), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
9139 {"zlwhsplatwdu", VX(4, 0x34D), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, EVUIMM_4_EX0
, RA
}},
9140 {"zlwhsplatdmx", VX(4, 0x34E), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
9141 {"zlwhsplatdu", VX(4, 0x34F), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, EVUIMM_4_EX0
, RA
}},
9142 {"zlwhgwsfdmx", VX(4, 0x350), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
9143 {"zlwhgwsfdu", VX(4, 0x351), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, EVUIMM_4_EX0
, RA
}},
9144 {"zlwhedmx", VX(4, 0x352), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
9145 {"zlwhedu", VX(4, 0x353), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, EVUIMM_4_EX0
, RA
}},
9146 {"zlwhosdmx", VX(4, 0x354), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
9147 {"zlwhosdu", VX(4, 0x355), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, EVUIMM_4_EX0
, RA
}},
9148 {"zlwhoudmx", VX(4, 0x356), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
9149 {"zlwhoudu", VX(4, 0x357), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, EVUIMM_4_EX0
, RA
}},
9150 {"zlwhmx", VX(4, 0x358), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
9151 {"zlwhu", VX(4, 0x359), VX_MASK
, PPCLSP
, 0, {RD
, EVUIMM_4_EX0
, RA
}},
9152 {"zlwwmx", VX(4, 0x35A), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
9153 {"zlwwu", VX(4, 0x35B), VX_MASK
, PPCLSP
, 0, {RD
, EVUIMM_4_EX0
, RA
}},
9154 {"zlhgwsfmx", VX(4, 0x35C), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
9155 {"zlhgwsfu", VX(4, 0x35D), VX_MASK
, PPCLSP
, 0, {RD
, EVUIMM_2_EX0
, RA
}},
9156 {"zlhhsplatmx", VX(4, 0x35E), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
9157 {"zlhhsplatu", VX(4, 0x35F), VX_MASK
, PPCLSP
, 0, {RD
, EVUIMM_2_EX0
, RA
}},
9158 {"zstddmx", VX(4, 0x360), VX_MASK
, PPCLSP
, 0, {RS_EVEN
, RA
, RB
}},
9159 {"zstddu", VX(4, 0x361), VX_MASK
, PPCLSP
, 0, {RS
, EVUIMM_8_EX0
, RA
}},
9160 {"zstdwmx", VX(4, 0x362), VX_MASK
, PPCLSP
, 0, {RS_EVEN
, RA
, RB
}},
9161 {"zstdwu", VX(4, 0x363), VX_MASK
, PPCLSP
, 0, {RS_EVEN
, EVUIMM_8_EX0
, RA
}},
9162 {"zstdhmx", VX(4, 0x364), VX_MASK
, PPCLSP
, 0, {RS_EVEN
, RA
, RB
}},
9163 {"zstdhu", VX(4, 0x365), VX_MASK
, PPCLSP
, 0, {RS_EVEN
, EVUIMM_8_EX0
, RA
}},
9164 {"zstwhedmx", VX(4, 0x368), VX_MASK
, PPCLSP
, 0, {RS_EVEN
, RA
, RB
}},
9165 {"zstwhedu", VX(4, 0x369), VX_MASK
, PPCLSP
, 0, {RS_EVEN
, EVUIMM_4_EX0
, RA
}},
9166 {"zstwhodmx", VX(4, 0x36A), VX_MASK
, PPCLSP
, 0, {RS_EVEN
, RA
, RB
}},
9167 {"zstwhodu", VX(4, 0x36B), VX_MASK
, PPCLSP
, 0, {RS_EVEN
, EVUIMM_4_EX0
, RA
}},
9168 {"zlhhemx", VX(4, 0x370), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
9169 {"zlhheu", VX(4, 0x371), VX_MASK
, PPCLSP
, 0, {RD
, EVUIMM_2_EX0
, RA
}},
9170 {"zlhhosmx", VX(4, 0x372), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
9171 {"zlhhosu", VX(4, 0x373), VX_MASK
, PPCLSP
, 0, {RD
, EVUIMM_2_EX0
, RA
}},
9172 {"zlhhoumx", VX(4, 0x374), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
9173 {"zlhhouu", VX(4, 0x375), VX_MASK
, PPCLSP
, 0, {RD
, EVUIMM_2_EX0
, RA
}},
9174 {"zsthemx", VX(4, 0x378), VX_MASK
, PPCLSP
, 0, {RS
, RA
, RB
}},
9175 {"zstheu", VX(4, 0x379), VX_MASK
, PPCLSP
, 0, {RS
, EVUIMM_2_EX0
, RA
}},
9176 {"zsthomx", VX(4, 0x37A), VX_MASK
, PPCLSP
, 0, {RS
, RA
, RB
}},
9177 {"zsthou", VX(4, 0x37B), VX_MASK
, PPCLSP
, 0, {RS
, EVUIMM_2_EX0
, RA
}},
9178 {"zstwhmx", VX(4, 0x37C), VX_MASK
, PPCLSP
, 0, {RS
, RA
, RB
}},
9179 {"zstwhu", VX(4, 0x37D), VX_MASK
, PPCLSP
, 0, {RS
, EVUIMM_4_EX0
, RA
}},
9180 {"zstwwmx", VX(4, 0x37E), VX_MASK
, PPCLSP
, 0, {RS
, RA
, RB
}},
9181 {"zstwwu", VX(4, 0x37F), VX_MASK
, PPCLSP
, 0, {RS
, EVUIMM_4_EX0
, RA
}},
9183 {"e_cmpi", SCI8BF(6,0,21), SCI8BF_MASK
, PPCVLE
, 0, {CRD32
, RA
, SCLSCI8
}},
9184 {"e_cmpwi", SCI8BF(6,0,21), SCI8BF_MASK
, PPCVLE
, 0, {CRD32
, RA
, SCLSCI8
}},
9185 {"e_cmpli", SCI8BF(6,1,21), SCI8BF_MASK
, PPCVLE
, 0, {CRD32
, RA
, SCLSCI8
}},
9186 {"e_cmplwi", SCI8BF(6,1,21), SCI8BF_MASK
, PPCVLE
, 0, {CRD32
, RA
, SCLSCI8
}},
9187 {"e_addi", SCI8(6,16), SCI8_MASK
, PPCVLE
, 0, {RT
, RA
, SCLSCI8
}},
9188 {"e_subi", SCI8(6,16), SCI8_MASK
, PPCVLE
, 0, {RT
, RA
, SCLSCI8N
}},
9189 {"e_addi.", SCI8(6,17), SCI8_MASK
, PPCVLE
, 0, {RT
, RA
, SCLSCI8
}},
9190 {"e_addic", SCI8(6,18), SCI8_MASK
, PPCVLE
, 0, {RT
, RA
, SCLSCI8
}},
9191 {"e_subic", SCI8(6,18), SCI8_MASK
, PPCVLE
, 0, {RT
, RA
, SCLSCI8N
}},
9192 {"e_addic.", SCI8(6,19), SCI8_MASK
, PPCVLE
, 0, {RT
, RA
, SCLSCI8
}},
9193 {"e_subic.", SCI8(6,19), SCI8_MASK
, PPCVLE
, 0, {RT
, RA
, SCLSCI8N
}},
9194 {"e_mulli", SCI8(6,20), SCI8_MASK
, PPCVLE
, 0, {RT
, RA
, SCLSCI8
}},
9195 {"e_subfic", SCI8(6,22), SCI8_MASK
, PPCVLE
, 0, {RT
, RA
, SCLSCI8
}},
9196 {"e_subfic.", SCI8(6,23), SCI8_MASK
, PPCVLE
, 0, {RT
, RA
, SCLSCI8
}},
9197 {"e_andi", SCI8(6,24), SCI8_MASK
, PPCVLE
, 0, {RA
, RS
, SCLSCI8
}},
9198 {"e_andi.", SCI8(6,25), SCI8_MASK
, PPCVLE
, 0, {RA
, RS
, SCLSCI8
}},
9199 {"e_nop", SCI8(6,26), 0xffffffff, PPCVLE
, 0, {0}},
9200 {"e_ori", SCI8(6,26), SCI8_MASK
, PPCVLE
, 0, {RA
, RS
, SCLSCI8
}},
9201 {"e_ori.", SCI8(6,27), SCI8_MASK
, PPCVLE
, 0, {RA
, RS
, SCLSCI8
}},
9202 {"e_xori", SCI8(6,28), SCI8_MASK
, PPCVLE
, 0, {RA
, RS
, SCLSCI8
}},
9203 {"e_xori.", SCI8(6,29), SCI8_MASK
, PPCVLE
, 0, {RA
, RS
, SCLSCI8
}},
9204 {"e_lbzu", OPVUP(6,0), OPVUP_MASK
, PPCVLE
, 0, {RT
, D8
, RA0
}},
9205 {"e_lhau", OPVUP(6,3), OPVUP_MASK
, PPCVLE
, 0, {RT
, D8
, RA0
}},
9206 {"e_lhzu", OPVUP(6,1), OPVUP_MASK
, PPCVLE
, 0, {RT
, D8
, RA0
}},
9207 {"e_lmw", OPVUP(6,8), OPVUP_MASK
, PPCVLE
, 0, {RT
, D8
, RA0
}},
9208 {"e_lwzu", OPVUP(6,2), OPVUP_MASK
, PPCVLE
, 0, {RT
, D8
, RA0
}},
9209 {"e_stbu", OPVUP(6,4), OPVUP_MASK
, PPCVLE
, 0, {RT
, D8
, RA0
}},
9210 {"e_sthu", OPVUP(6,5), OPVUP_MASK
, PPCVLE
, 0, {RT
, D8
, RA0
}},
9211 {"e_stwu", OPVUP(6,6), OPVUP_MASK
, PPCVLE
, 0, {RT
, D8
, RA0
}},
9212 {"e_stmw", OPVUP(6,9), OPVUP_MASK
, PPCVLE
, 0, {RT
, D8
, RA0
}},
9213 {"e_lmvgprw", OPVUPRT(6,16,0),OPVUPRT_MASK
, PPCVLE
, 0, {D8
, RA0
}},
9214 {"e_ldmvgprw", OPVUPRT(6,16,0),OPVUPRT_MASK
, PPCVLE
, 0, {D8
, RA0
}},
9215 {"e_stmvgprw", OPVUPRT(6,17,0),OPVUPRT_MASK
, PPCVLE
, 0, {D8
, RA0
}},
9216 {"e_lmvsprw", OPVUPRT(6,16,1),OPVUPRT_MASK
, PPCVLE
, 0, {D8
, RA0
}},
9217 {"e_ldmvsprw", OPVUPRT(6,16,1),OPVUPRT_MASK
, PPCVLE
, 0, {D8
, RA0
}},
9218 {"e_stmvsprw", OPVUPRT(6,17,1),OPVUPRT_MASK
, PPCVLE
, 0, {D8
, RA0
}},
9219 {"e_lmvsrrw", OPVUPRT(6,16,4),OPVUPRT_MASK
, PPCVLE
, 0, {D8
, RA0
}},
9220 {"e_ldmvsrrw", OPVUPRT(6,16,4),OPVUPRT_MASK
, PPCVLE
, 0, {D8
, RA0
}},
9221 {"e_stmvsrrw", OPVUPRT(6,17,4),OPVUPRT_MASK
, PPCVLE
, 0, {D8
, RA0
}},
9222 {"e_lmvcsrrw", OPVUPRT(6,16,5),OPVUPRT_MASK
, PPCVLE
, 0, {D8
, RA0
}},
9223 {"e_ldmvcsrrw", OPVUPRT(6,16,5),OPVUPRT_MASK
, PPCVLE
, 0, {D8
, RA0
}},
9224 {"e_stmvcsrrw", OPVUPRT(6,17,5),OPVUPRT_MASK
, PPCVLE
, 0, {D8
, RA0
}},
9225 {"e_lmvdsrrw", OPVUPRT(6,16,6),OPVUPRT_MASK
, PPCVLE
, 0, {D8
, RA0
}},
9226 {"e_ldmvdsrrw", OPVUPRT(6,16,6),OPVUPRT_MASK
, PPCVLE
, 0, {D8
, RA0
}},
9227 {"e_stmvdsrrw", OPVUPRT(6,17,6),OPVUPRT_MASK
, PPCVLE
, 0, {D8
, RA0
}},
9228 {"e_lmvmcsrrw", OPVUPRT(6,16,7),OPVUPRT_MASK
, PPCVLE
, 0, {D8
, RA0
}},
9229 {"e_stmvmcsrrw", OPVUPRT(6,17,7),OPVUPRT_MASK
, PPCVLE
, 0, {D8
, RA0
}},
9230 {"e_add16i", OP(7), OP_MASK
, PPCVLE
, 0, {RT
, RA
, SI
}},
9231 {"e_la", OP(7), OP_MASK
, PPCVLE
, 0, {RT
, D
, RA0
}},
9232 {"e_sub16i", OP(7), OP_MASK
, PPCVLE
, 0, {RT
, RA
, NSI
}},
9234 {"se_addi", SE_IM5(8,0), SE_IM5_MASK
, PPCVLE
, 0, {RX
, OIMM5
}},
9235 {"se_cmpli", SE_IM5(8,1), SE_IM5_MASK
, PPCVLE
, 0, {RX
, OIMM5
}},
9236 {"se_subi", SE_IM5(9,0), SE_IM5_MASK
, PPCVLE
, 0, {RX
, OIMM5
}},
9237 {"se_subi.", SE_IM5(9,1), SE_IM5_MASK
, PPCVLE
, 0, {RX
, OIMM5
}},
9238 {"se_cmpi", SE_IM5(10,1), SE_IM5_MASK
, PPCVLE
, 0, {RX
, UI5
}},
9239 {"se_bmaski", SE_IM5(11,0), SE_IM5_MASK
, PPCVLE
, 0, {RX
, UI5
}},
9240 {"se_andi", SE_IM5(11,1), SE_IM5_MASK
, PPCVLE
, 0, {RX
, UI5
}},
9242 {"e_lbz", OP(12), OP_MASK
, PPCVLE
, 0, {RT
, D
, RA0
}},
9243 {"e_stb", OP(13), OP_MASK
, PPCVLE
, 0, {RT
, D
, RA0
}},
9244 {"e_lha", OP(14), OP_MASK
, PPCVLE
, 0, {RT
, D
, RA0
}},
9246 {"se_srw", SE_RR(16,0), SE_RR_MASK
, PPCVLE
, 0, {RX
, RY
}},
9247 {"se_sraw", SE_RR(16,1), SE_RR_MASK
, PPCVLE
, 0, {RX
, RY
}},
9248 {"se_slw", SE_RR(16,2), SE_RR_MASK
, PPCVLE
, 0, {RX
, RY
}},
9249 {"se_nop", SE_RR(17,0), 0xffff, PPCVLE
, 0, {0}},
9250 {"se_or", SE_RR(17,0), SE_RR_MASK
, PPCVLE
, 0, {RX
, RY
}},
9251 {"se_andc", SE_RR(17,1), SE_RR_MASK
, PPCVLE
, 0, {RX
, RY
}},
9252 {"se_and", SE_RR(17,2), SE_RR_MASK
, PPCVLE
, 0, {RX
, RY
}},
9253 {"se_and.", SE_RR(17,3), SE_RR_MASK
, PPCVLE
, 0, {RX
, RY
}},
9254 {"se_li", IM7(9), IM7_MASK
, PPCVLE
, 0, {RX
, UI7
}},
9256 {"e_lwz", OP(20), OP_MASK
, PPCVLE
, 0, {RT
, D
, RA0
}},
9257 {"e_stw", OP(21), OP_MASK
, PPCVLE
, 0, {RT
, D
, RA0
}},
9258 {"e_lhz", OP(22), OP_MASK
, PPCVLE
, 0, {RT
, D
, RA0
}},
9259 {"e_sth", OP(23), OP_MASK
, PPCVLE
, 0, {RT
, D
, RA0
}},
9261 {"se_bclri", SE_IM5(24,0), SE_IM5_MASK
, PPCVLE
, 0, {RX
, UI5
}},
9262 {"se_bgeni", SE_IM5(24,1), SE_IM5_MASK
, PPCVLE
, 0, {RX
, UI5
}},
9263 {"se_bseti", SE_IM5(25,0), SE_IM5_MASK
, PPCVLE
, 0, {RX
, UI5
}},
9264 {"se_btsti", SE_IM5(25,1), SE_IM5_MASK
, PPCVLE
, 0, {RX
, UI5
}},
9265 {"se_srwi", SE_IM5(26,0), SE_IM5_MASK
, PPCVLE
, 0, {RX
, UI5
}},
9266 {"se_srawi", SE_IM5(26,1), SE_IM5_MASK
, PPCVLE
, 0, {RX
, UI5
}},
9267 {"se_slwi", SE_IM5(27,0), SE_IM5_MASK
, PPCVLE
, 0, {RX
, UI5
}},
9269 {"e_lis", I16L(28,28), I16L_MASK
, PPCVLE
, 0, {RD
, VLEUIMML
}},
9270 {"e_and2is.", I16L(28,29), I16L_MASK
, PPCVLE
, 0, {RD
, VLEUIMML
}},
9271 {"e_or2is", I16L(28,26), I16L_MASK
, PPCVLE
, 0, {RD
, VLEUIMML
}},
9272 {"e_and2i.", I16L(28,25), I16L_MASK
, PPCVLE
, 0, {RD
, VLEUIMML
}},
9273 {"e_or2i", I16L(28,24), I16L_MASK
, PPCVLE
, 0, {RD
, VLEUIMML
}},
9274 {"e_cmphl16i", IA16(28,23), IA16_MASK
, PPCVLE
, 0, {RA
, VLEUIMM
}},
9275 {"e_cmph16i", IA16(28,22), IA16_MASK
, PPCVLE
, 0, {RA
, VLESIMM
}},
9276 {"e_cmpl16i", I16A(28,21), I16A_MASK
, PPCVLE
, 0, {RA
, VLEUIMM
}},
9277 {"e_mull2i", I16A(28,20), I16A_MASK
, PPCVLE
, 0, {RA
, VLESIMM
}},
9278 {"e_cmp16i", IA16(28,19), IA16_MASK
, PPCVLE
, 0, {RA
, VLESIMM
}},
9279 {"e_sub2is", I16A(28,18), I16A_MASK
, PPCVLE
, 0, {RA
, VLENSIMM
}},
9280 {"e_add2is", I16A(28,18), I16A_MASK
, PPCVLE
, 0, {RA
, VLESIMM
}},
9281 {"e_sub2i.", I16A(28,17), I16A_MASK
, PPCVLE
, 0, {RA
, VLENSIMM
}},
9282 {"e_add2i.", I16A(28,17), I16A_MASK
, PPCVLE
, 0, {RA
, VLESIMM
}},
9283 {"e_li", LI20(28,0), LI20_MASK
, PPCVLE
, 0, {RT
, IMM20
}},
9284 {"e_rlwimi", M(29,0), M_MASK
, PPCVLE
, 0, {RA
, RS
, SH
, MB
, ME
}},
9285 {"e_rlwinm", M(29,1), M_MASK
, PPCVLE
, 0, {RA
, RT
, SH
, MBE
, ME
}},
9286 {"e_b", BD24(30,0,0), BD24_MASK
, PPCVLE
, 0, {B24
}},
9287 {"e_bl", BD24(30,0,1), BD24_MASK
, PPCVLE
, 0, {B24
}},
9288 {"e_bdnz", EBD15(30,8,BO32DNZ
,0), EBD15_MASK
, PPCVLE
, 0, {B15
}},
9289 {"e_bdnzl", EBD15(30,8,BO32DNZ
,1), EBD15_MASK
, PPCVLE
, 0, {B15
}},
9290 {"e_bdz", EBD15(30,8,BO32DZ
,0), EBD15_MASK
, PPCVLE
, 0, {B15
}},
9291 {"e_bdzl", EBD15(30,8,BO32DZ
,1), EBD15_MASK
, PPCVLE
, 0, {B15
}},
9292 {"e_bge", EBD15BI(30,8,BO32F
,CBLT
,0), EBD15BI_MASK
, PPCVLE
, 0, {CRS
,B15
}},
9293 {"e_bgel", EBD15BI(30,8,BO32F
,CBLT
,1), EBD15BI_MASK
, PPCVLE
, 0, {CRS
,B15
}},
9294 {"e_bnl", EBD15BI(30,8,BO32F
,CBLT
,0), EBD15BI_MASK
, PPCVLE
, 0, {CRS
,B15
}},
9295 {"e_bnll", EBD15BI(30,8,BO32F
,CBLT
,1), EBD15BI_MASK
, PPCVLE
, 0, {CRS
,B15
}},
9296 {"e_blt", EBD15BI(30,8,BO32T
,CBLT
,0), EBD15BI_MASK
, PPCVLE
, 0, {CRS
,B15
}},
9297 {"e_bltl", EBD15BI(30,8,BO32T
,CBLT
,1), EBD15BI_MASK
, PPCVLE
, 0, {CRS
,B15
}},
9298 {"e_bgt", EBD15BI(30,8,BO32T
,CBGT
,0), EBD15BI_MASK
, PPCVLE
, 0, {CRS
,B15
}},
9299 {"e_bgtl", EBD15BI(30,8,BO32T
,CBGT
,1), EBD15BI_MASK
, PPCVLE
, 0, {CRS
,B15
}},
9300 {"e_ble", EBD15BI(30,8,BO32F
,CBGT
,0), EBD15BI_MASK
, PPCVLE
, 0, {CRS
,B15
}},
9301 {"e_blel", EBD15BI(30,8,BO32F
,CBGT
,1), EBD15BI_MASK
, PPCVLE
, 0, {CRS
,B15
}},
9302 {"e_bng", EBD15BI(30,8,BO32F
,CBGT
,0), EBD15BI_MASK
, PPCVLE
, 0, {CRS
,B15
}},
9303 {"e_bngl", EBD15BI(30,8,BO32F
,CBGT
,1), EBD15BI_MASK
, PPCVLE
, 0, {CRS
,B15
}},
9304 {"e_bne", EBD15BI(30,8,BO32F
,CBEQ
,0), EBD15BI_MASK
, PPCVLE
, 0, {CRS
,B15
}},
9305 {"e_bnel", EBD15BI(30,8,BO32F
,CBEQ
,1), EBD15BI_MASK
, PPCVLE
, 0, {CRS
,B15
}},
9306 {"e_beq", EBD15BI(30,8,BO32T
,CBEQ
,0), EBD15BI_MASK
, PPCVLE
, 0, {CRS
,B15
}},
9307 {"e_beql", EBD15BI(30,8,BO32T
,CBEQ
,1), EBD15BI_MASK
, PPCVLE
, 0, {CRS
,B15
}},
9308 {"e_bso", EBD15BI(30,8,BO32T
,CBSO
,0), EBD15BI_MASK
, PPCVLE
, 0, {CRS
,B15
}},
9309 {"e_bsol", EBD15BI(30,8,BO32T
,CBSO
,1), EBD15BI_MASK
, PPCVLE
, 0, {CRS
,B15
}},
9310 {"e_bun", EBD15BI(30,8,BO32T
,CBSO
,0), EBD15BI_MASK
, PPCVLE
, 0, {CRS
,B15
}},
9311 {"e_bunl", EBD15BI(30,8,BO32T
,CBSO
,1), EBD15BI_MASK
, PPCVLE
, 0, {CRS
,B15
}},
9312 {"e_bns", EBD15BI(30,8,BO32F
,CBSO
,0), EBD15BI_MASK
, PPCVLE
, 0, {CRS
,B15
}},
9313 {"e_bnsl", EBD15BI(30,8,BO32F
,CBSO
,1), EBD15BI_MASK
, PPCVLE
, 0, {CRS
,B15
}},
9314 {"e_bnu", EBD15BI(30,8,BO32F
,CBSO
,0), EBD15BI_MASK
, PPCVLE
, 0, {CRS
,B15
}},
9315 {"e_bnul", EBD15BI(30,8,BO32F
,CBSO
,1), EBD15BI_MASK
, PPCVLE
, 0, {CRS
,B15
}},
9316 {"e_bc", BD15(30,8,0), BD15_MASK
, PPCVLE
, 0, {BO32
, BI32
, B15
}},
9317 {"e_bcl", BD15(30,8,1), BD15_MASK
, PPCVLE
, 0, {BO32
, BI32
, B15
}},
9319 {"e_bf", EBD15(30,8,BO32F
,0), EBD15_MASK
, PPCVLE
, 0, {BI32
,B15
}},
9320 {"e_bfl", EBD15(30,8,BO32F
,1), EBD15_MASK
, PPCVLE
, 0, {BI32
,B15
}},
9321 {"e_bt", EBD15(30,8,BO32T
,0), EBD15_MASK
, PPCVLE
, 0, {BI32
,B15
}},
9322 {"e_btl", EBD15(30,8,BO32T
,1), EBD15_MASK
, PPCVLE
, 0, {BI32
,B15
}},
9324 {"e_cmph", X(31,14), X_MASK
, PPCVLE
, 0, {CRD
, RA
, RB
}},
9325 {"e_sc", X(31,36), XRTRA_MASK
, PPCVLE
, 0, {ELEV
}},
9326 {"e_cmphl", X(31,46), X_MASK
, PPCVLE
, 0, {CRD
, RA
, RB
}},
9327 {"e_crandc", XL(31,129), XL_MASK
, PPCVLE
, 0, {BT
, BA
, BB
}},
9328 {"e_crnand", XL(31,225), XL_MASK
, PPCVLE
, 0, {BT
, BA
, BB
}},
9329 {"e_crnot", XL(31,33), XL_MASK
, PPCVLE
, 0, {BT
, BAB
}},
9330 {"e_crnor", XL(31,33), XL_MASK
, PPCVLE
, 0, {BT
, BA
, BB
}},
9331 {"e_crclr", XL(31,193), XL_MASK
, PPCVLE
, 0, {BTAB
}},
9332 {"e_crxor", XL(31,193), XL_MASK
, PPCVLE
, 0, {BT
, BA
, BB
}},
9333 {"e_mcrf", XL(31,16), XL_MASK
, PPCVLE
, 0, {CRD
, CR
}},
9334 {"e_slwi", EX(31,112), EX_MASK
, PPCVLE
, 0, {RA
, RS
, SH
}},
9335 {"e_slwi.", EX(31,113), EX_MASK
, PPCVLE
, 0, {RA
, RS
, SH
}},
9337 {"e_crand", XL(31,257), XL_MASK
, PPCVLE
, 0, {BT
, BA
, BB
}},
9339 {"e_rlw", EX(31,560), EX_MASK
, PPCVLE
, 0, {RA
, RS
, RB
}},
9340 {"e_rlw.", EX(31,561), EX_MASK
, PPCVLE
, 0, {RA
, RS
, RB
}},
9342 {"e_crset", XL(31,289), XL_MASK
, PPCVLE
, 0, {BTAB
}},
9343 {"e_creqv", XL(31,289), XL_MASK
, PPCVLE
, 0, {BT
, BA
, BB
}},
9345 {"e_rlwi", EX(31,624), EX_MASK
, PPCVLE
, 0, {RA
, RS
, SH
}},
9346 {"e_rlwi.", EX(31,625), EX_MASK
, PPCVLE
, 0, {RA
, RS
, SH
}},
9348 {"e_crorc", XL(31,417), XL_MASK
, PPCVLE
, 0, {BT
, BA
, BB
}},
9350 {"e_crmove", XL(31,449), XL_MASK
, PPCVLE
, 0, {BT
, BAB
}},
9351 {"e_cror", XL(31,449), XL_MASK
, PPCVLE
, 0, {BT
, BA
, BB
}},
9353 {"mtmas1", XSPR(31,467,625), XSPR_MASK
, PPCVLE
, 0, {RS
}},
9355 {"e_srwi", EX(31,1136), EX_MASK
, PPCVLE
, 0, {RA
, RS
, SH
}},
9356 {"e_srwi.", EX(31,1137), EX_MASK
, PPCVLE
, 0, {RA
, RS
, SH
}},
9358 {"se_lbz", SD4(8), SD4_MASK
, PPCVLE
, 0, {RZ
, SE_SD
, RX
}},
9360 {"se_stb", SD4(9), SD4_MASK
, PPCVLE
, 0, {RZ
, SE_SD
, RX
}},
9362 {"se_lhz", SD4(10), SD4_MASK
, PPCVLE
, 0, {RZ
, SE_SDH
, RX
}},
9364 {"se_sth", SD4(11), SD4_MASK
, PPCVLE
, 0, {RZ
, SE_SDH
, RX
}},
9366 {"se_lwz", SD4(12), SD4_MASK
, PPCVLE
, 0, {RZ
, SE_SDW
, RX
}},
9368 {"se_stw", SD4(13), SD4_MASK
, PPCVLE
, 0, {RZ
, SE_SDW
, RX
}},
9370 {"se_bge", EBD8IO(28,0,0), EBD8IO3_MASK
, PPCVLE
, 0, {B8
}},
9371 {"se_bnl", EBD8IO(28,0,0), EBD8IO3_MASK
, PPCVLE
, 0, {B8
}},
9372 {"se_ble", EBD8IO(28,0,1), EBD8IO3_MASK
, PPCVLE
, 0, {B8
}},
9373 {"se_bng", EBD8IO(28,0,1), EBD8IO3_MASK
, PPCVLE
, 0, {B8
}},
9374 {"se_bne", EBD8IO(28,0,2), EBD8IO3_MASK
, PPCVLE
, 0, {B8
}},
9375 {"se_bns", EBD8IO(28,0,3), EBD8IO3_MASK
, PPCVLE
, 0, {B8
}},
9376 {"se_bnu", EBD8IO(28,0,3), EBD8IO3_MASK
, PPCVLE
, 0, {B8
}},
9377 {"se_bf", EBD8IO(28,0,0), EBD8IO2_MASK
, PPCVLE
, 0, {BI16
, B8
}},
9378 {"se_blt", EBD8IO(28,1,0), EBD8IO3_MASK
, PPCVLE
, 0, {B8
}},
9379 {"se_bgt", EBD8IO(28,1,1), EBD8IO3_MASK
, PPCVLE
, 0, {B8
}},
9380 {"se_beq", EBD8IO(28,1,2), EBD8IO3_MASK
, PPCVLE
, 0, {B8
}},
9381 {"se_bso", EBD8IO(28,1,3), EBD8IO3_MASK
, PPCVLE
, 0, {B8
}},
9382 {"se_bun", EBD8IO(28,1,3), EBD8IO3_MASK
, PPCVLE
, 0, {B8
}},
9383 {"se_bt", EBD8IO(28,1,0), EBD8IO2_MASK
, PPCVLE
, 0, {BI16
, B8
}},
9384 {"se_bc", BD8IO(28), BD8IO_MASK
, PPCVLE
, 0, {BO16
, BI16
, B8
}},
9385 {"se_b", BD8(58,0,0), BD8_MASK
, PPCVLE
, 0, {B8
}},
9386 {"se_bl", BD8(58,0,1), BD8_MASK
, PPCVLE
, 0, {B8
}},
9389 const unsigned int vle_num_opcodes
=
9390 sizeof (vle_opcodes
) / sizeof (vle_opcodes
[0]);
9392 /* The macro table. This is only used by the assembler. */
9394 /* The expressions of the form (-x ! 31) & (x | 31) have the value 0
9395 when x=0; 32-x when x is between 1 and 31; are negative if x is
9396 negative; and are 32 or more otherwise. This is what you want
9397 when, for instance, you are emulating a right shift by a
9398 rotate-left-and-mask, because the underlying instructions support
9399 shifts of size 0 but not shifts of size 32. By comparison, when
9400 extracting x bits from some word you want to use just 32-x, because
9401 the underlying instructions don't support extracting 0 bits but do
9402 support extracting the whole word (32 bits in this case). */
9404 const struct powerpc_macro powerpc_macros
[] = {
9405 {"extldi", 4, PPC64
, "rldicr %0,%1,%3,(%2)-1"},
9406 {"extldi.", 4, PPC64
, "rldicr. %0,%1,%3,(%2)-1"},
9407 {"extrdi", 4, PPC64
, "rldicl %0,%1,((%2)+(%3))&((%2)+(%3)<>64),64-(%2)"},
9408 {"extrdi.", 4, PPC64
, "rldicl. %0,%1,((%2)+(%3))&((%2)+(%3)<>64),64-(%2)"},
9409 {"insrdi", 4, PPC64
, "rldimi %0,%1,64-((%2)+(%3)),%3"},
9410 {"insrdi.", 4, PPC64
, "rldimi. %0,%1,64-((%2)+(%3)),%3"},
9411 {"rotrdi", 3, PPC64
, "rldicl %0,%1,(-(%2)!63)&((%2)|63),0"},
9412 {"rotrdi.", 3, PPC64
, "rldicl. %0,%1,(-(%2)!63)&((%2)|63),0"},
9413 {"sldi", 3, PPC64
, "rldicr %0,%1,%2,63-(%2)"},
9414 {"sldi.", 3, PPC64
, "rldicr. %0,%1,%2,63-(%2)"},
9415 {"srdi", 3, PPC64
, "rldicl %0,%1,(-(%2)!63)&((%2)|63),%2"},
9416 {"srdi.", 3, PPC64
, "rldicl. %0,%1,(-(%2)!63)&((%2)|63),%2"},
9417 {"clrrdi", 3, PPC64
, "rldicr %0,%1,0,63-(%2)"},
9418 {"clrrdi.", 3, PPC64
, "rldicr. %0,%1,0,63-(%2)"},
9419 {"clrlsldi", 4, PPC64
, "rldic %0,%1,%3,(%2)-(%3)"},
9420 {"clrlsldi.",4, PPC64
, "rldic. %0,%1,%3,(%2)-(%3)"},
9422 {"extlwi", 4, PPCCOM
, "rlwinm %0,%1,%3,0,(%2)-1"},
9423 {"extlwi.", 4, PPCCOM
, "rlwinm. %0,%1,%3,0,(%2)-1"},
9424 {"extrwi", 4, PPCCOM
, "rlwinm %0,%1,((%2)+(%3))&((%2)+(%3)<>32),32-(%2),31"},
9425 {"extrwi.", 4, PPCCOM
, "rlwinm. %0,%1,((%2)+(%3))&((%2)+(%3)<>32),32-(%2),31"},
9426 {"inslwi", 4, PPCCOM
, "rlwimi %0,%1,(-(%3)!31)&((%3)|31),%3,(%2)+(%3)-1"},
9427 {"inslwi.", 4, PPCCOM
, "rlwimi. %0,%1,(-(%3)!31)&((%3)|31),%3,(%2)+(%3)-1"},
9428 {"insrwi", 4, PPCCOM
, "rlwimi %0,%1,32-((%2)+(%3)),%3,(%2)+(%3)-1"},
9429 {"insrwi.", 4, PPCCOM
, "rlwimi. %0,%1,32-((%2)+(%3)),%3,(%2)+(%3)-1"},
9430 {"rotrwi", 3, PPCCOM
, "rlwinm %0,%1,(-(%2)!31)&((%2)|31),0,31"},
9431 {"rotrwi.", 3, PPCCOM
, "rlwinm. %0,%1,(-(%2)!31)&((%2)|31),0,31"},
9432 {"slwi", 3, PPCCOM
, "rlwinm %0,%1,%2,0,31-(%2)"},
9433 {"sli", 3, PWRCOM
, "rlinm %0,%1,%2,0,31-(%2)"},
9434 {"slwi.", 3, PPCCOM
, "rlwinm. %0,%1,%2,0,31-(%2)"},
9435 {"sli.", 3, PWRCOM
, "rlinm. %0,%1,%2,0,31-(%2)"},
9436 {"srwi", 3, PPCCOM
, "rlwinm %0,%1,(-(%2)!31)&((%2)|31),%2,31"},
9437 {"sri", 3, PWRCOM
, "rlinm %0,%1,(-(%2)!31)&((%2)|31),%2,31"},
9438 {"srwi.", 3, PPCCOM
, "rlwinm. %0,%1,(-(%2)!31)&((%2)|31),%2,31"},
9439 {"sri.", 3, PWRCOM
, "rlinm. %0,%1,(-(%2)!31)&((%2)|31),%2,31"},
9440 {"clrrwi", 3, PPCCOM
, "rlwinm %0,%1,0,0,31-(%2)"},
9441 {"clrrwi.", 3, PPCCOM
, "rlwinm. %0,%1,0,0,31-(%2)"},
9442 {"clrlslwi", 4, PPCCOM
, "rlwinm %0,%1,%3,(%2)-(%3),31-(%3)"},
9443 {"clrlslwi.",4, PPCCOM
, "rlwinm. %0,%1,%3,(%2)-(%3),31-(%3)"},
9445 {"e_extlwi", 4, PPCVLE
, "e_rlwinm %0,%1,%3,0,(%2)-1"},
9446 {"e_extrwi", 4, PPCVLE
, "e_rlwinm %0,%1,((%2)+(%3))&((%2)+(%3)<>32),32-(%2),31"},
9447 {"e_inslwi", 4, PPCVLE
, "e_rlwimi %0,%1,(-(%3)!31)&((%3)|31),%3,(%2)+(%3)-1"},
9448 {"e_insrwi", 4, PPCVLE
, "e_rlwimi %0,%1,32-((%2)+(%3)),%3,(%2)+(%3)-1"},
9449 {"e_rotlwi", 3, PPCVLE
, "e_rlwinm %0,%1,%2,0,31"},
9450 {"e_rotrwi", 3, PPCVLE
, "e_rlwinm %0,%1,(-(%2)!31)&((%2)|31),0,31"},
9451 {"e_slwi", 3, PPCVLE
, "e_rlwinm %0,%1,%2,0,31-(%2)"},
9452 {"e_srwi", 3, PPCVLE
, "e_rlwinm %0,%1,(-(%2)!31)&((%2)|31),%2,31"},
9453 {"e_clrlwi", 3, PPCVLE
, "e_rlwinm %0,%1,0,%2,31"},
9454 {"e_clrrwi", 3, PPCVLE
, "e_rlwinm %0,%1,0,0,31-(%2)"},
9455 {"e_clrlslwi",4, PPCVLE
, "e_rlwinm %0,%1,%3,(%2)-(%3),31-(%3)"},
9457 /* old SPE instructions have new names with the same opcodes */
9458 {"evsadd", 3, PPCSPE
|PPCVLE
, "efsadd %0,%1,%2"},
9459 {"evssub", 3, PPCSPE
|PPCVLE
, "efssub %0,%1,%2"},
9460 {"evsabs", 2, PPCSPE
|PPCVLE
, "efsabs %0,%1"},
9461 {"evsnabs", 2, PPCSPE
|PPCVLE
, "efsnabs %0,%1"},
9462 {"evsneg", 2, PPCSPE
|PPCVLE
, "efsneg %0,%1"},
9463 {"evsmul", 3, PPCSPE
|PPCVLE
, "efsmul %0,%1,%2"},
9464 {"evsdiv", 3, PPCSPE
|PPCVLE
, "efsdiv %0,%1,%2"},
9465 {"evscmpgt", 3, PPCSPE
|PPCVLE
, "efscmpgt %0,%1,%2"},
9466 {"evsgmplt", 3, PPCSPE
|PPCVLE
, "efscmplt %0,%1,%2"},
9467 {"evsgmpeq", 3, PPCSPE
|PPCVLE
, "efscmpeq %0,%1,%2"},
9468 {"evscfui", 2, PPCSPE
|PPCVLE
, "efscfui %0,%1"},
9469 {"evscfsi", 2, PPCSPE
|PPCVLE
, "efscfsi %0,%1"},
9470 {"evscfuf", 2, PPCSPE
|PPCVLE
, "efscfuf %0,%1"},
9471 {"evscfsf", 2, PPCSPE
|PPCVLE
, "efscfsf %0,%1"},
9472 {"evsctui", 2, PPCSPE
|PPCVLE
, "efsctui %0,%1"},
9473 {"evsctsi", 2, PPCSPE
|PPCVLE
, "efsctsi %0,%1"},
9474 {"evsctuf", 2, PPCSPE
|PPCVLE
, "efsctuf %0,%1"},
9475 {"evsctsf", 2, PPCSPE
|PPCVLE
, "efsctsf %0,%1"},
9476 {"evsctuiz", 2, PPCSPE
|PPCVLE
, "efsctuiz %0,%1"},
9477 {"evsctsiz", 2, PPCSPE
|PPCVLE
, "efsctsiz %0,%1"},
9478 {"evststgt", 3, PPCSPE
|PPCVLE
, "efststgt %0,%1,%2"},
9479 {"evststlt", 3, PPCSPE
|PPCVLE
, "efststlt %0,%1,%2"},
9480 {"evststeq", 3, PPCSPE
|PPCVLE
, "efststeq %0,%1,%2"},
9482 /* SPE2 instructions which just are mapped to SPE2 */
9483 {"evdotphsssi", 3, PPCSPE2
, "evdotphssmi %0,%1,%2"},
9484 {"evdotphsssia", 3, PPCSPE2
, "evdotphssmia %0,%1,%2"},
9485 {"evdotpwsssi", 3, PPCSPE2
, "evdotpwssmi %0,%1,%2"},
9486 {"evdotpwsssia", 3, PPCSPE2
, "evdotpwssmia %0,%1,%2"}
9489 const int powerpc_num_macros
=
9490 sizeof (powerpc_macros
) / sizeof (powerpc_macros
[0]);
9492 /* SPE v2 instruction set from SPE2PIM Rev. 2 08/2011 */
9493 const struct powerpc_opcode spe2_opcodes
[] = {
9494 {"evdotpwcssi", VX (4, 128), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9495 {"evdotpwcsmi", VX (4, 129), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9496 {"evdotpwcssfr", VX (4, 130), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9497 {"evdotpwcssf", VX (4, 131), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9498 {"evdotpwgasmf", VX (4, 136), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9499 {"evdotpwxgasmf", VX (4, 137), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9500 {"evdotpwgasmfr", VX (4, 138), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9501 {"evdotpwxgasmfr", VX (4, 139), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9502 {"evdotpwgssmf", VX (4, 140), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9503 {"evdotpwxgssmf", VX (4, 141), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9504 {"evdotpwgssmfr", VX (4, 142), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9505 {"evdotpwxgssmfr", VX (4, 143), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9506 {"evdotpwcssiaaw3", VX (4, 144), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9507 {"evdotpwcsmiaaw3", VX (4, 145), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9508 {"evdotpwcssfraaw3", VX (4, 146), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9509 {"evdotpwcssfaaw3", VX (4, 147), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9510 {"evdotpwgasmfaa3", VX (4, 152), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9511 {"evdotpwxgasmfaa3", VX (4, 153), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9512 {"evdotpwgasmfraa3", VX (4, 154), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9513 {"evdotpwxgasmfraa3", VX (4, 155), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9514 {"evdotpwgssmfaa3", VX (4, 156), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9515 {"evdotpwxgssmfaa3", VX (4, 157), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9516 {"evdotpwgssmfraa3", VX (4, 158), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9517 {"evdotpwxgssmfraa3", VX (4, 159), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9518 {"evdotpwcssia", VX (4, 160), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9519 {"evdotpwcsmia", VX (4, 161), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9520 {"evdotpwcssfra", VX (4, 162), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9521 {"evdotpwcssfa", VX (4, 163), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9522 {"evdotpwgasmfa", VX (4, 168), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9523 {"evdotpwxgasmfa", VX (4, 169), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9524 {"evdotpwgasmfra", VX (4, 170), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9525 {"evdotpwxgasmfra", VX (4, 171), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9526 {"evdotpwgssmfa", VX (4, 172), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9527 {"evdotpwxgssmfa", VX (4, 173), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9528 {"evdotpwgssmfra", VX (4, 174), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9529 {"evdotpwxgssmfra", VX (4, 175), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9530 {"evdotpwcssiaaw", VX (4, 176), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9531 {"evdotpwcsmiaaw", VX (4, 177), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9532 {"evdotpwcssfraaw", VX (4, 178), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9533 {"evdotpwcssfaaw", VX (4, 179), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9534 {"evdotpwgasmfaa", VX (4, 184), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9535 {"evdotpwxgasmfaa", VX (4, 185), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9536 {"evdotpwgasmfraa", VX (4, 186), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9537 {"evdotpwxgasmfraa", VX (4, 187), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9538 {"evdotpwgssmfaa", VX (4, 188), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9539 {"evdotpwxgssmfaa", VX (4, 189), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9540 {"evdotpwgssmfraa", VX (4, 190), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9541 {"evdotpwxgssmfraa", VX (4, 191), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9542 {"evdotphihcssi", VX (4, 256), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9543 {"evdotplohcssi", VX (4, 257), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9544 {"evdotphihcssf", VX (4, 258), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9545 {"evdotplohcssf", VX (4, 259), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9546 {"evdotphihcsmi", VX (4, 264), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9547 {"evdotplohcsmi", VX (4, 265), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9548 {"evdotphihcssfr", VX (4, 266), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9549 {"evdotplohcssfr", VX (4, 267), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9550 {"evdotphihcssiaaw3", VX (4, 272), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9551 {"evdotplohcssiaaw3", VX (4, 273), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9552 {"evdotphihcssfaaw3", VX (4, 274), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9553 {"evdotplohcssfaaw3", VX (4, 275), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9554 {"evdotphihcsmiaaw3", VX (4, 280), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9555 {"evdotplohcsmiaaw3", VX (4, 281), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9556 {"evdotphihcssfraaw3", VX (4, 282), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9557 {"evdotplohcssfraaw3", VX (4, 283), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9558 {"evdotphihcssia", VX (4, 288), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9559 {"evdotplohcssia", VX (4, 289), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9560 {"evdotphihcssfa", VX (4, 290), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9561 {"evdotplohcssfa", VX (4, 291), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9562 {"evdotphihcsmia", VX (4, 296), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9563 {"evdotplohcsmia", VX (4, 297), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9564 {"evdotphihcssfra", VX (4, 298), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9565 {"evdotplohcssfra", VX (4, 299), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9566 {"evdotphihcssiaaw", VX (4, 304), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9567 {"evdotplohcssiaaw", VX (4, 305), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9568 {"evdotphihcssfaaw", VX (4, 306), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9569 {"evdotplohcssfaaw", VX (4, 307), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9570 {"evdotphihcsmiaaw", VX (4, 312), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9571 {"evdotplohcsmiaaw", VX (4, 313), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9572 {"evdotphihcssfraaw", VX (4, 314), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9573 {"evdotplohcssfraaw", VX (4, 315), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9574 {"evdotphausi", VX (4, 320), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9575 {"evdotphassi", VX (4, 321), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9576 {"evdotphasusi", VX (4, 322), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9577 {"evdotphassf", VX (4, 323), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9578 {"evdotphsssf", VX (4, 327), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9579 {"evdotphaumi", VX (4, 328), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9580 {"evdotphasmi", VX (4, 329), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9581 {"evdotphasumi", VX (4, 330), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9582 {"evdotphassfr", VX (4, 331), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9583 {"evdotphssmi", VX (4, 333), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9584 {"evdotphsssfr", VX (4, 335), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9585 {"evdotphausiaaw3", VX (4, 336), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9586 {"evdotphassiaaw3", VX (4, 337), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9587 {"evdotphasusiaaw3", VX (4, 338), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9588 {"evdotphassfaaw3", VX (4, 339), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9589 {"evdotphsssiaaw3", VX (4, 341), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9590 {"evdotphsssfaaw3", VX (4, 343), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9591 {"evdotphaumiaaw3", VX (4, 344), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9592 {"evdotphasmiaaw3", VX (4, 345), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9593 {"evdotphasumiaaw3", VX (4, 346), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9594 {"evdotphassfraaw3", VX (4, 347), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9595 {"evdotphssmiaaw3", VX (4, 349), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9596 {"evdotphsssfraaw3", VX (4, 351), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9597 {"evdotphausia", VX (4, 352), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9598 {"evdotphassia", VX (4, 353), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9599 {"evdotphasusia", VX (4, 354), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9600 {"evdotphassfa", VX (4, 355), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9601 {"evdotphsssfa", VX (4, 359), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9602 {"evdotphaumia", VX (4, 360), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9603 {"evdotphasmia", VX (4, 361), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9604 {"evdotphasumia", VX (4, 362), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9605 {"evdotphassfra", VX (4, 363), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9606 {"evdotphssmia", VX (4, 365), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9607 {"evdotphsssfra", VX (4, 367), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9608 {"evdotphausiaaw", VX (4, 368), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9609 {"evdotphassiaaw", VX (4, 369), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9610 {"evdotphasusiaaw", VX (4, 370), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9611 {"evdotphassfaaw", VX (4, 371), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9612 {"evdotphsssiaaw", VX (4, 373), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9613 {"evdotphsssfaaw", VX (4, 375), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9614 {"evdotphaumiaaw", VX (4, 376), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9615 {"evdotphasmiaaw", VX (4, 377), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9616 {"evdotphasumiaaw", VX (4, 378), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9617 {"evdotphassfraaw", VX (4, 379), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9618 {"evdotphssmiaaw", VX (4, 381), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9619 {"evdotphsssfraaw", VX (4, 383), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9620 {"evdotp4hgaumi", VX (4, 384), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9621 {"evdotp4hgasmi", VX (4, 385), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9622 {"evdotp4hgasumi", VX (4, 386), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9623 {"evdotp4hgasmf", VX (4, 387), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9624 {"evdotp4hgssmi", VX (4, 388), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9625 {"evdotp4hgssmf", VX (4, 389), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9626 {"evdotp4hxgasmi", VX (4, 390), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9627 {"evdotp4hxgasmf", VX (4, 391), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9628 {"evdotpbaumi", VX (4, 392), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9629 {"evdotpbasmi", VX (4, 393), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9630 {"evdotpbasumi", VX (4, 394), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9631 {"evdotp4hxgssmi", VX (4, 398), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9632 {"evdotp4hxgssmf", VX (4, 399), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9633 {"evdotp4hgaumiaa3", VX (4, 400), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9634 {"evdotp4hgasmiaa3", VX (4, 401), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9635 {"evdotp4hgasumiaa3", VX (4, 402), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9636 {"evdotp4hgasmfaa3", VX (4, 403), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9637 {"evdotp4hgssmiaa3", VX (4, 404), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9638 {"evdotp4hgssmfaa3", VX (4, 405), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9639 {"evdotp4hxgasmiaa3", VX (4, 406), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9640 {"evdotp4hxgasmfaa3", VX (4, 407), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9641 {"evdotpbaumiaaw3", VX (4, 408), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9642 {"evdotpbasmiaaw3", VX (4, 409), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9643 {"evdotpbasumiaaw3", VX (4, 410), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9644 {"evdotp4hxgssmiaa3", VX (4, 414), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9645 {"evdotp4hxgssmfaa3", VX (4, 415), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9646 {"evdotp4hgaumia", VX (4, 416), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9647 {"evdotp4hgasmia", VX (4, 417), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9648 {"evdotp4hgasumia", VX (4, 418), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9649 {"evdotp4hgasmfa", VX (4, 419), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9650 {"evdotp4hgssmia", VX (4, 420), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9651 {"evdotp4hgssmfa", VX (4, 421), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9652 {"evdotp4hxgasmia", VX (4, 422), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9653 {"evdotp4hxgasmfa", VX (4, 423), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9654 {"evdotpbaumia", VX (4, 424), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9655 {"evdotpbasmia", VX (4, 425), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9656 {"evdotpbasumia", VX (4, 426), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9657 {"evdotp4hxgssmia", VX (4, 430), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9658 {"evdotp4hxgssmfa", VX (4, 431), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9659 {"evdotp4hgaumiaa", VX (4, 432), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9660 {"evdotp4hgasmiaa", VX (4, 433), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9661 {"evdotp4hgasumiaa", VX (4, 434), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9662 {"evdotp4hgasmfaa", VX (4, 435), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9663 {"evdotp4hgssmiaa", VX (4, 436), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9664 {"evdotp4hgssmfaa", VX (4, 437), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9665 {"evdotp4hxgasmiaa", VX (4, 438), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9666 {"evdotp4hxgasmfaa", VX (4, 439), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9667 {"evdotpbaumiaaw", VX (4, 440), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9668 {"evdotpbasmiaaw", VX (4, 441), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9669 {"evdotpbasumiaaw", VX (4, 442), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9670 {"evdotp4hxgssmiaa", VX (4, 446), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9671 {"evdotp4hxgssmfaa", VX (4, 447), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9672 {"evdotpwausi", VX (4, 448), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9673 {"evdotpwassi", VX (4, 449), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9674 {"evdotpwasusi", VX (4, 450), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9675 {"evdotpwaumi", VX (4, 456), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9676 {"evdotpwasmi", VX (4, 457), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9677 {"evdotpwasumi", VX (4, 458), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9678 {"evdotpwssmi", VX (4, 461), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9679 {"evdotpwausiaa3", VX (4, 464), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9680 {"evdotpwassiaa3", VX (4, 465), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9681 {"evdotpwasusiaa3", VX (4, 466), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9682 {"evdotpwsssiaa3", VX (4, 469), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9683 {"evdotpwaumiaa3", VX (4, 472), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9684 {"evdotpwasmiaa3", VX (4, 473), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9685 {"evdotpwasumiaa3", VX (4, 474), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9686 {"evdotpwssmiaa3", VX (4, 477), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9687 {"evdotpwausia", VX (4, 480), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9688 {"evdotpwassia", VX (4, 481), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9689 {"evdotpwasusia", VX (4, 482), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9690 {"evdotpwaumia", VX (4, 488), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9691 {"evdotpwasmia", VX (4, 489), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9692 {"evdotpwasumia", VX (4, 490), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9693 {"evdotpwssmia", VX (4, 493), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9694 {"evdotpwausiaa", VX (4, 496), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9695 {"evdotpwassiaa", VX (4, 497), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9696 {"evdotpwasusiaa", VX (4, 498), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9697 {"evdotpwsssiaa", VX (4, 501), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9698 {"evdotpwaumiaa", VX (4, 504), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9699 {"evdotpwasmiaa", VX (4, 505), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9700 {"evdotpwasumiaa", VX (4, 506), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9701 {"evdotpwssmiaa", VX (4, 509), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9702 {"evaddib", VX (4, 515), VX_MASK
, PPCSPE2
, 0, {RD
, RB
, UIMM
}},
9703 {"evaddih", VX (4, 513), VX_MASK
, PPCSPE2
, 0, {RD
, RB
, UIMM
}},
9704 {"evsubifh", VX (4, 517), VX_MASK
, PPCSPE2
, 0, {RD
, UIMM
, RB
}},
9705 {"evsubifb", VX (4, 519), VX_MASK
, PPCSPE2
, 0, {RD
, UIMM
, RB
}},
9706 {"evabsb", VX_RB_CONST(4, 520, 2), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, RA
}},
9707 {"evabsh", VX_RB_CONST(4, 520, 4), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, RA
}},
9708 {"evabsd", VX_RB_CONST(4, 520, 6), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, RA
}},
9709 {"evabss", VX_RB_CONST(4, 520, 8), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, RA
}},
9710 {"evabsbs", VX_RB_CONST(4, 520, 10), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, RA
}},
9711 {"evabshs", VX_RB_CONST(4, 520, 12), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, RA
}},
9712 {"evabsds", VX_RB_CONST(4, 520, 14), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, RA
}},
9713 {"evnegwo", VX_RB_CONST(4, 521, 1), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, RA
}},
9714 {"evnegb", VX_RB_CONST(4, 521, 2), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, RA
}},
9715 {"evnegbo", VX_RB_CONST(4, 521, 3), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, RA
}},
9716 {"evnegh", VX_RB_CONST(4, 521, 4), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, RA
}},
9717 {"evnegho", VX_RB_CONST(4, 521, 5), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, RA
}},
9718 {"evnegd", VX_RB_CONST(4, 521, 6), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, RA
}},
9719 {"evnegs", VX_RB_CONST(4, 521, 8), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, RA
}},
9720 {"evnegwos", VX_RB_CONST(4, 521, 9), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, RA
}},
9721 {"evnegbs", VX_RB_CONST(4, 521, 10), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, RA
}},
9722 {"evnegbos", VX_RB_CONST(4, 521, 11), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, RA
}},
9723 {"evneghs", VX_RB_CONST(4, 521, 12), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, RA
}},
9724 {"evneghos", VX_RB_CONST(4, 521, 13), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, RA
}},
9725 {"evnegds", VX_RB_CONST(4, 521, 14), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, RA
}},
9726 {"evextzb", VX_RB_CONST(4, 522, 1), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, RA
}},
9727 {"evextsbh", VX_RB_CONST(4, 522, 4), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, RA
}},
9728 {"evextsw", VX_RB_CONST(4, 523, 6), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, RA
}},
9729 {"evrndwh", VX_RB_CONST(4, 524, 0), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, RA
}},
9730 {"evrndhb", VX_RB_CONST(4, 524, 4), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, RA
}},
9731 {"evrnddw", VX_RB_CONST(4, 524, 6), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, RA
}},
9732 {"evrndwhus", VX_RB_CONST(4, 524, 8), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, RA
}},
9733 {"evrndwhss", VX_RB_CONST(4, 524, 9), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, RA
}},
9734 {"evrndhbus", VX_RB_CONST(4, 524, 12), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, RA
}},
9735 {"evrndhbss", VX_RB_CONST(4, 524, 13), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, RA
}},
9736 {"evrnddwus", VX_RB_CONST(4, 524, 14), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, RA
}},
9737 {"evrnddwss", VX_RB_CONST(4, 524, 15), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, RA
}},
9738 {"evrndwnh", VX_RB_CONST(4, 524, 16), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, RA
}},
9739 {"evrndhnb", VX_RB_CONST(4, 524, 20), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, RA
}},
9740 {"evrnddnw", VX_RB_CONST(4, 524, 22), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, RA
}},
9741 {"evrndwnhus", VX_RB_CONST(4, 524, 24), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, RA
}},
9742 {"evrndwnhss", VX_RB_CONST(4, 524, 25), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, RA
}},
9743 {"evrndhnbus", VX_RB_CONST(4, 524, 28), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, RA
}},
9744 {"evrndhnbss", VX_RB_CONST(4, 524, 29), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, RA
}},
9745 {"evrnddnwus", VX_RB_CONST(4, 524, 30), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, RA
}},
9746 {"evrnddnwss", VX_RB_CONST(4, 524, 31), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, RA
}},
9747 {"evcntlzh", VX_RB_CONST(4, 525, 4), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, RA
}},
9748 {"evcntlsh", VX_RB_CONST(4, 526, 4), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, RA
}},
9749 {"evpopcntb", VX_RB_CONST(4, 526, 26), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, RA
}},
9750 {"circinc", VX (4, 528), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9751 {"evunpkhibui", VX_RB_CONST(4, 540, 0), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, RA
}},
9752 {"evunpkhibsi", VX_RB_CONST(4, 540, 1), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, RA
}},
9753 {"evunpkhihui", VX_RB_CONST(4, 540, 2), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, RA
}},
9754 {"evunpkhihsi", VX_RB_CONST(4, 540, 3), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, RA
}},
9755 {"evunpklobui", VX_RB_CONST(4, 540, 4), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, RA
}},
9756 {"evunpklobsi", VX_RB_CONST(4, 540, 5), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, RA
}},
9757 {"evunpklohui", VX_RB_CONST(4, 540, 6), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, RA
}},
9758 {"evunpklohsi", VX_RB_CONST(4, 540, 7), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, RA
}},
9759 {"evunpklohf", VX_RB_CONST(4, 540, 8), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, RA
}},
9760 {"evunpkhihf", VX_RB_CONST(4, 540, 9), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, RA
}},
9761 {"evunpklowgsf", VX_RB_CONST(4, 540, 12), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, RA
}},
9762 {"evunpkhiwgsf", VX_RB_CONST(4, 540, 13), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, RA
}},
9763 {"evsatsduw", VX_RB_CONST(4, 540, 16), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, RA
}},
9764 {"evsatsdsw", VX_RB_CONST(4, 540, 17), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, RA
}},
9765 {"evsatshub", VX_RB_CONST(4, 540, 18), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, RA
}},
9766 {"evsatshsb", VX_RB_CONST(4, 540, 19), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, RA
}},
9767 {"evsatuwuh", VX_RB_CONST(4, 540, 20), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, RA
}},
9768 {"evsatswsh", VX_RB_CONST(4, 540, 21), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, RA
}},
9769 {"evsatswuh", VX_RB_CONST(4, 540, 22), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, RA
}},
9770 {"evsatuhub", VX_RB_CONST(4, 540, 23), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, RA
}},
9771 {"evsatuduw", VX_RB_CONST(4, 540, 24), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, RA
}},
9772 {"evsatuwsw", VX_RB_CONST(4, 540, 25), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, RA
}},
9773 {"evsatshuh", VX_RB_CONST(4, 540, 26), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, RA
}},
9774 {"evsatuhsh", VX_RB_CONST(4, 540, 27), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, RA
}},
9775 {"evsatswuw", VX_RB_CONST(4, 540, 28), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, RA
}},
9776 {"evsatswgsdf", VX_RB_CONST(4, 540, 29), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, RA
}},
9777 {"evsatsbub", VX_RB_CONST(4, 540, 30), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, RA
}},
9778 {"evsatubsb", VX_RB_CONST(4, 540, 31), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, RA
}},
9779 {"evmaxhpuw", VX_RB_CONST(4, 541, 0), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, RA
}},
9780 {"evmaxhpsw", VX_RB_CONST(4, 541, 1), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, RA
}},
9781 {"evmaxbpuh", VX_RB_CONST(4, 541, 4), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, RA
}},
9782 {"evmaxbpsh", VX_RB_CONST(4, 541, 5), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, RA
}},
9783 {"evmaxwpud", VX_RB_CONST(4, 541, 6), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, RA
}},
9784 {"evmaxwpsd", VX_RB_CONST(4, 541, 7), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, RA
}},
9785 {"evminhpuw", VX_RB_CONST(4, 541, 8), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, RA
}},
9786 {"evminhpsw", VX_RB_CONST(4, 541, 9), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, RA
}},
9787 {"evminbpuh", VX_RB_CONST(4, 541, 12), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, RA
}},
9788 {"evminbpsh", VX_RB_CONST(4, 541, 13), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, RA
}},
9789 {"evminwpud", VX_RB_CONST(4, 541, 14), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, RA
}},
9790 {"evminwpsd", VX_RB_CONST(4, 541, 15), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, RA
}},
9791 {"evmaxmagws", VX (4, 543), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9792 {"evsl", VX (4, 549), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9793 {"evsli", VX (4, 551), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, EVUIMM
}},
9794 {"evsplatie", VX_RB_CONST (4, 553, 1), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, SIMM
}},
9795 {"evsplatib", VX_RB_CONST (4, 553, 2), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, SIMM
}},
9796 {"evsplatibe", VX_RB_CONST (4, 553, 3), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, SIMM
}},
9797 {"evsplatih", VX_RB_CONST (4, 553, 4), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, SIMM
}},
9798 {"evsplatihe", VX_RB_CONST (4, 553, 5), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, SIMM
}},
9799 {"evsplatid", VX_RB_CONST (4, 553, 6), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, SIMM
}},
9800 {"evsplatia", VX_RB_CONST (4, 553, 16), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, SIMM
}},
9801 {"evsplatiea", VX_RB_CONST (4, 553, 17), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, SIMM
}},
9802 {"evsplatiba", VX_RB_CONST (4, 553, 18), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, SIMM
}},
9803 {"evsplatibea", VX_RB_CONST (4, 553, 19), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, SIMM
}},
9804 {"evsplatiha", VX_RB_CONST (4, 553, 20), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, SIMM
}},
9805 {"evsplatihea", VX_RB_CONST (4, 553, 21), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, SIMM
}},
9806 {"evsplatida", VX_RB_CONST (4, 553, 22), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, SIMM
}},
9807 {"evsplatfio", VX_RB_CONST (4, 555, 1), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, SIMM
}},
9808 {"evsplatfib", VX_RB_CONST (4, 555, 2), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, SIMM
}},
9809 {"evsplatfibo", VX_RB_CONST (4, 555, 3), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, SIMM
}},
9810 {"evsplatfih", VX_RB_CONST (4, 555, 4), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, SIMM
}},
9811 {"evsplatfiho", VX_RB_CONST (4, 555, 5), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, SIMM
}},
9812 {"evsplatfid", VX_RB_CONST (4, 555, 6), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, SIMM
}},
9813 {"evsplatfia", VX_RB_CONST (4, 555, 16), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, SIMM
}},
9814 {"evsplatfioa", VX_RB_CONST (4, 555, 17), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, SIMM
}},
9815 {"evsplatfiba", VX_RB_CONST (4, 555, 18), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, SIMM
}},
9816 {"evsplatfiboa", VX_RB_CONST (4, 555, 19), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, SIMM
}},
9817 {"evsplatfiha", VX_RB_CONST (4, 555, 20), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, SIMM
}},
9818 {"evsplatfihoa", VX_RB_CONST (4, 555, 21), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, SIMM
}},
9819 {"evsplatfida", VX_RB_CONST (4, 555, 22), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, SIMM
}},
9820 {"evcmpgtdu", VX_SPE_CRFD (4, 560, 1), VX_SPE_CRFD_MASK
, PPCSPE2
, 0, {CRFD
, RA
, RB
}},
9821 {"evcmpgtds", VX_SPE_CRFD (4, 561, 1), VX_SPE_CRFD_MASK
, PPCSPE2
, 0, {CRFD
, RA
, RB
}},
9822 {"evcmpltdu", VX_SPE_CRFD (4, 562, 1), VX_SPE_CRFD_MASK
, PPCSPE2
, 0, {CRFD
, RA
, RB
}},
9823 {"evcmpltds", VX_SPE_CRFD (4, 563, 1), VX_SPE_CRFD_MASK
, PPCSPE2
, 0, {CRFD
, RA
, RB
}},
9824 {"evcmpeqd", VX_SPE_CRFD (4, 564, 1), VX_SPE_CRFD_MASK
, PPCSPE2
, 0, {CRFD
, RA
, RB
}},
9825 {"evswapbhilo", VX (4, 568), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9826 {"evswapblohi", VX (4, 569), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9827 {"evswaphhilo", VX (4, 570), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9828 {"evswaphlohi", VX (4, 571), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9829 {"evswaphe", VX (4, 572), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9830 {"evswaphhi", VX (4, 573), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9831 {"evswaphlo", VX (4, 574), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9832 {"evswapho", VX (4, 575), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9833 {"evinsb", VX (4, 584), VX_MASK_DDD
, PPCSPE2
, 0, {RD
, RA
, DDD
, BBB
}},
9834 {"evxtrb", VX (4, 586), VX_MASK_DDD
, PPCSPE2
, 0, {RD
, RA
, DDD
, BBB
}},
9835 {"evsplath", VX_SPE2_HH (4, 588, 0, 0), VX_SPE2_HH_MASK
, PPCSPE2
, 0, {RD
, RA
, HH
}},
9836 {"evsplatb", VX_SPE2_SPLATB (4, 588, 2), VX_SPE2_SPLATB_MASK
, PPCSPE2
, 0, {RD
, RA
, BBB
}},
9837 {"evinsh", VX_SPE2_DDHH (4, 589, 0), VX_SPE2_DDHH_MASK
, PPCSPE2
, 0, {RD
, RA
, DD
, HH
}},
9838 {"evclrbe", VX_SPE2_CLR (4, 590, 0), VX_SPE2_CLR_MASK
, PPCSPE2
, 0, {RD
, RA
, MMMM
}},
9839 {"evclrbo", VX_SPE2_CLR (4, 590, 1), VX_SPE2_CLR_MASK
, PPCSPE2
, 0, {RD
, RA
, MMMM
}},
9840 {"evclrh", VX_SPE2_CLR (4, 591, 1), VX_SPE2_CLR_MASK
, PPCSPE2
, 0, {RD
, RA
, MMMM
}},
9841 {"evxtrh", VX_SPE2_DDHH (4, 591, 0), VX_SPE2_DDHH_MASK
, PPCSPE2
, 0, {RD
, RA
, DD
, HH
}},
9842 {"evselbitm0", VX (4, 592), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9843 {"evselbitm1", VX (4, 593), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9844 {"evselbit", VX (4, 594), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9845 {"evperm", VX (4, 596), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9846 {"evperm2", VX (4, 597), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9847 {"evperm3", VX (4, 598), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9848 {"evxtrd", VX (4, 600), VX_OFF_SPE2_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
, VX_OFF_SPE2
}},
9849 {"evsrbu", VX (4, 608), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9850 {"evsrbs", VX (4, 609), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9851 {"evsrbiu", VX (4, 610), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, EVUIMM_LT8
}},
9852 {"evsrbis", VX (4, 611), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, EVUIMM_LT8
}},
9853 {"evslb", VX (4, 612), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9854 {"evrlb", VX (4, 613), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9855 {"evslbi", VX (4, 614), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, EVUIMM_LT8
}},
9856 {"evrlbi", VX (4, 615), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, EVUIMM_LT8
}},
9857 {"evsrhu", VX (4, 616), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9858 {"evsrhs", VX (4, 617), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9859 {"evsrhiu", VX (4, 618), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, EVUIMM_LT16
}},
9860 {"evsrhis", VX (4, 619), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, EVUIMM_LT16
}},
9861 {"evslh", VX (4, 620), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9862 {"evrlh", VX (4, 621), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9863 {"evslhi", VX (4, 622), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, EVUIMM_LT16
}},
9864 {"evrlhi", VX (4, 623), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, EVUIMM_LT16
}},
9865 {"evsru", VX (4, 624), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9866 {"evsrs", VX (4, 625), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9867 {"evsriu", VX (4, 626), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, EVUIMM
}},
9868 {"evsris", VX (4, 627), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, EVUIMM
}},
9869 {"evlvsl", VX (4, 628), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9870 {"evlvsr", VX (4, 629), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9871 {"evsroiu", VX_SPE2_OCTET (4, 631, 0), VX_SPE2_OCTET_MASK
, PPCSPE2
, 0, {RD
, RA
, NNN
}},
9872 {"evsrois", VX_SPE2_OCTET (4, 631, 1), VX_SPE2_OCTET_MASK
, PPCSPE2
, 0, {RD
, RA
, NNN
}},
9873 {"evsloi", VX_SPE2_OCTET (4, 631, 2), VX_SPE2_OCTET_MASK
, PPCSPE2
, 0, {RD
, RA
, NNN
}},
9874 {"evldbx", VX (4, 774), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9875 {"evldb", VX (4, 775), VX_MASK
, PPCSPE2
, 0, {RD
, EVUIMM_8
, RA
}},
9876 {"evlhhsplathx", VX (4, 778), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9877 {"evlhhsplath", VX (4, 779), VX_MASK
, PPCSPE2
, 0, {RD
, EVUIMM_2
, RA
}},
9878 {"evlwbsplatwx", VX (4, 786), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9879 {"evlwbsplatw", VX (4, 787), VX_MASK
, PPCSPE2
, 0, {RD
, EVUIMM_4
, RA
}},
9880 {"evlwhsplatwx", VX (4, 794), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9881 {"evlwhsplatw", VX (4, 795), VX_MASK
, PPCSPE2
, 0, {RD
, EVUIMM_4
, RA
}},
9882 {"evlbbsplatbx", VX (4, 798), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9883 {"evlbbsplatb", VX (4, 799), VX_MASK
, PPCSPE2
, 0, {RD
, EVUIMM_1
, RA
}},
9884 {"evstdbx", VX (4, 806), VX_MASK
, PPCSPE2
, 0, {RS
, RA
, RB
}},
9885 {"evstdb", VX (4, 807), VX_MASK
, PPCSPE2
, 0, {RS
, EVUIMM_8
, RA
}},
9886 {"evlwbex", VX (4, 810), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9887 {"evlwbe", VX (4, 811), VX_MASK
, PPCSPE2
, 0, {RD
, EVUIMM_4
, RA
}},
9888 {"evlwboux", VX (4, 812), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9889 {"evlwbou", VX (4, 813), VX_MASK
, PPCSPE2
, 0, {RD
, EVUIMM_4
, RA
}},
9890 {"evlwbosx", VX (4, 814), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9891 {"evlwbos", VX (4, 815), VX_MASK
, PPCSPE2
, 0, {RD
, EVUIMM_4
, RA
}},
9892 {"evstwbex", VX (4, 818), VX_MASK
, PPCSPE2
, 0, {RS
, RA
, RB
}},
9893 {"evstwbe", VX (4, 819), VX_MASK
, PPCSPE2
, 0, {RS
, EVUIMM_4
, RA
}},
9894 {"evstwbox", VX (4, 822), VX_MASK
, PPCSPE2
, 0, {RS
, RA
, RB
}},
9895 {"evstwbo", VX (4, 823), VX_MASK
, PPCSPE2
, 0, {RS
, EVUIMM_4
, RA
}},
9896 {"evstwbx", VX (4, 826), VX_MASK
, PPCSPE2
, 0, {RS
, RA
, RB
}},
9897 {"evstwb", VX (4, 827), VX_MASK
, PPCSPE2
, 0, {RS
, EVUIMM_4
, RA
}},
9898 {"evsthbx", VX (4, 830), VX_MASK
, PPCSPE2
, 0, {RS
, RA
, RB
}},
9899 {"evsthb", VX (4, 831), VX_MASK
, PPCSPE2
, 0, {RS
, EVUIMM_2
, RA
}},
9900 {"evlddmx", VX (4, 832), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9901 {"evlddu", VX (4, 833), VX_MASK
, PPCSPE2
, 0, {RD
, EVUIMM_8_EX0
, RA
}},
9902 {"evldwmx", VX (4, 834), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9903 {"evldwu", VX (4, 835), VX_MASK
, PPCSPE2
, 0, {RD
, EVUIMM_8_EX0
, RA
}},
9904 {"evldhmx", VX (4, 836), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9905 {"evldhu", VX (4, 837), VX_MASK
, PPCSPE2
, 0, {RD
, EVUIMM_8_EX0
, RA
}},
9906 {"evldbmx", VX (4, 838), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9907 {"evldbu", VX (4, 839), VX_MASK
, PPCSPE2
, 0, {RD
, EVUIMM_8_EX0
, RA
}},
9908 {"evlhhesplatmx", VX (4, 840), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9909 {"evlhhesplatu", VX (4, 841), VX_MASK
, PPCSPE2
, 0, {RD
, EVUIMM_2_EX0
, RA
}},
9910 {"evlhhsplathmx", VX (4, 842), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9911 {"evlhhsplathu", VX (4, 843), VX_MASK
, PPCSPE2
, 0, {RD
, EVUIMM_2_EX0
, RA
}},
9912 {"evlhhousplatmx", VX (4, 844), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9913 {"evlhhousplatu", VX (4, 845), VX_MASK
, PPCSPE2
, 0, {RD
, EVUIMM_2_EX0
, RA
}},
9914 {"evlhhossplatmx", VX (4, 846), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9915 {"evlhhossplatu", VX (4, 847), VX_MASK
, PPCSPE2
, 0, {RD
, EVUIMM_2_EX0
, RA
}},
9916 {"evlwhemx", VX (4, 848), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9917 {"evlwheu", VX (4, 849), VX_MASK
, PPCSPE2
, 0, {RD
, EVUIMM_4_EX0
, RA
}},
9918 {"evlwbsplatwmx", VX (4, 850), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9919 {"evlwbsplatwu", VX (4, 851), VX_MASK
, PPCSPE2
, 0, {RD
, EVUIMM_4_EX0
, RA
}},
9920 {"evlwhoumx", VX (4, 852), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9921 {"evlwhouu", VX (4, 853), VX_MASK
, PPCSPE2
, 0, {RD
, EVUIMM_4_EX0
, RA
}},
9922 {"evlwhosmx", VX (4, 854), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9923 {"evlwhosu", VX (4, 855), VX_MASK
, PPCSPE2
, 0, {RD
, EVUIMM_4_EX0
, RA
}},
9924 {"evlwwsplatmx", VX (4, 856), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9925 {"evlwwsplatu", VX (4, 857), VX_MASK
, PPCSPE2
, 0, {RD
, EVUIMM_4_EX0
, RA
}},
9926 {"evlwhsplatwmx", VX (4, 858), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9927 {"evlwhsplatwu", VX (4, 859), VX_MASK
, PPCSPE2
, 0, {RD
, EVUIMM_4_EX0
, RA
}},
9928 {"evlwhsplatmx", VX (4, 860), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9929 {"evlwhsplatu", VX (4, 861), VX_MASK
, PPCSPE2
, 0, {RD
, EVUIMM_4_EX0
, RA
}},
9930 {"evlbbsplatbmx", VX (4, 862), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9931 {"evlbbsplatbu", VX (4, 863), VX_MASK
, PPCSPE2
, 0, {RD
, EVUIMM_1_EX0
, RA
}},
9932 {"evstddmx", VX (4, 864), VX_MASK
, PPCSPE2
, 0, {RS
, RA
, RB
}},
9933 {"evstddu", VX (4, 865), VX_MASK
, PPCSPE2
, 0, {RS
, EVUIMM_8_EX0
, RA
}},
9934 {"evstdwmx", VX (4, 866), VX_MASK
, PPCSPE2
, 0, {RS
, RA
, RB
}},
9935 {"evstdwu", VX (4, 867), VX_MASK
, PPCSPE2
, 0, {RS
, EVUIMM_8_EX0
, RA
}},
9936 {"evstdhmx", VX (4, 868), VX_MASK
, PPCSPE2
, 0, {RS
, RA
, RB
}},
9937 {"evstdhu", VX (4, 869), VX_MASK
, PPCSPE2
, 0, {RS
, EVUIMM_8_EX0
, RA
}},
9938 {"evstdbmx", VX (4, 870), VX_MASK
, PPCSPE2
, 0, {RS
, RA
, RB
}},
9939 {"evstdbu", VX (4, 871), VX_MASK
, PPCSPE2
, 0, {RS
, EVUIMM_8_EX0
, RA
}},
9940 {"evlwbemx", VX (4, 874), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9941 {"evlwbeu", VX (4, 875), VX_MASK
, PPCSPE2
, 0, {RD
, EVUIMM_4_EX0
, RA
}},
9942 {"evlwboumx", VX (4, 876), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9943 {"evlwbouu", VX (4, 877), VX_MASK
, PPCSPE2
, 0, {RD
, EVUIMM_4_EX0
, RA
}},
9944 {"evlwbosmx", VX (4, 878), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9945 {"evlwbosu", VX (4, 879), VX_MASK
, PPCSPE2
, 0, {RD
, EVUIMM_4_EX0
, RA
}},
9946 {"evstwhemx", VX (4, 880), VX_MASK
, PPCSPE2
, 0, {RS
, RA
, RB
}},
9947 {"evstwheu", VX (4, 881), VX_MASK
, PPCSPE2
, 0, {RS
, EVUIMM_4_EX0
, RA
}},
9948 {"evstwbemx", VX (4, 882), VX_MASK
, PPCSPE2
, 0, {RS
, RA
, RB
}},
9949 {"evstwbeu", VX (4, 883), VX_MASK
, PPCSPE2
, 0, {RS
, EVUIMM_4_EX0
, RA
}},
9950 {"evstwhomx", VX (4, 884), VX_MASK
, PPCSPE2
, 0, {RS
, RA
, RB
}},
9951 {"evstwhou", VX (4, 885), VX_MASK
, PPCSPE2
, 0, {RS
, EVUIMM_4_EX0
, RA
}},
9952 {"evstwbomx", VX (4, 886), VX_MASK
, PPCSPE2
, 0, {RS
, RA
, RB
}},
9953 {"evstwbou", VX (4, 887), VX_MASK
, PPCSPE2
, 0, {RS
, EVUIMM_4_EX0
, RA
}},
9954 {"evstwwemx", VX (4, 888), VX_MASK
, PPCSPE2
, 0, {RS
, RA
, RB
}},
9955 {"evstwweu", VX (4, 889), VX_MASK
, PPCSPE2
, 0, {RS
, EVUIMM_4_EX0
, RA
}},
9956 {"evstwbmx", VX (4, 890), VX_MASK
, PPCSPE2
, 0, {RS
, RA
, RB
}},
9957 {"evstwbu", VX (4, 891), VX_MASK
, PPCSPE2
, 0, {RS
, EVUIMM_4_EX0
, RA
}},
9958 {"evstwwomx", VX (4, 892), VX_MASK
, PPCSPE2
, 0, {RS
, RA
, RB
}},
9959 {"evstwwou", VX (4, 893), VX_MASK
, PPCSPE2
, 0, {RS
, EVUIMM_4_EX0
, RA
}},
9960 {"evsthbmx", VX (4, 894), VX_MASK
, PPCSPE2
, 0, {RS
, RA
, RB
}},
9961 {"evsthbu", VX (4, 895), VX_MASK
, PPCSPE2
, 0, {RS
, EVUIMM_2_EX0
, RA
}},
9962 {"evmhusi", VX (4, 1024), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9963 {"evmhssi", VX (4, 1025), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9964 {"evmhsusi", VX (4, 1026), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9965 {"evmhssf", VX (4, 1028), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9966 {"evmhumi", VX (4, 1029), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9967 {"evmhssfr", VX (4, 1030), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9968 {"evmhesumi", VX (4, 1034), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9969 {"evmhosumi", VX (4, 1038), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9970 {"evmbeumi", VX (4, 1048), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9971 {"evmbesmi", VX (4, 1049), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9972 {"evmbesumi", VX (4, 1050), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9973 {"evmboumi", VX (4, 1052), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9974 {"evmbosmi", VX (4, 1053), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9975 {"evmbosumi", VX (4, 1054), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9976 {"evmhesumia", VX (4, 1066), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9977 {"evmhosumia", VX (4, 1070), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9978 {"evmbeumia", VX (4, 1080), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9979 {"evmbesmia", VX (4, 1081), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9980 {"evmbesumia", VX (4, 1082), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9981 {"evmboumia", VX (4, 1084), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9982 {"evmbosmia", VX (4, 1085), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9983 {"evmbosumia", VX (4, 1086), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9984 {"evmwusiw", VX (4, 1088), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9985 {"evmwssiw", VX (4, 1089), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9986 {"evmwhssfr", VX (4, 1094), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9987 {"evmwehgsmfr", VX (4, 1110), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9988 {"evmwehgsmf", VX (4, 1111), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9989 {"evmwohgsmfr", VX (4, 1118), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9990 {"evmwohgsmf", VX (4, 1119), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9991 {"evmwhssfra", VX (4, 1126), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9992 {"evmwehgsmfra", VX (4, 1142), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9993 {"evmwehgsmfa", VX (4, 1143), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9994 {"evmwohgsmfra", VX (4, 1150), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9995 {"evmwohgsmfa", VX (4, 1151), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9996 {"evaddusiaa", VX_RB_CONST(4, 1152, 0), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, RA
}},
9997 {"evaddssiaa", VX_RB_CONST(4, 1153, 0), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, RA
}},
9998 {"evsubfusiaa", VX_RB_CONST(4, 1154, 0), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, RA
}},
9999 {"evsubfssiaa", VX_RB_CONST(4, 1155, 0), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, RA
}},
10000 {"evaddsmiaa", VX_RB_CONST(4, 1156, 0), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, RA
}},
10001 {"evsubfsmiaa", VX_RB_CONST(4, 1158, 0), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, RA
}},
10002 {"evaddh", VX (4, 1160), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10003 {"evaddhss", VX (4, 1161), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10004 {"evsubfh", VX (4, 1162), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10005 {"evsubfhss", VX (4, 1163), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10006 {"evaddhx", VX (4, 1164), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10007 {"evaddhxss", VX (4, 1165), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10008 {"evsubfhx", VX (4, 1166), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10009 {"evsubfhxss", VX (4, 1167), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10010 {"evaddd", VX (4, 1168), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10011 {"evadddss", VX (4, 1169), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10012 {"evsubfd", VX (4, 1170), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10013 {"evsubfdss", VX (4, 1171), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10014 {"evaddb", VX (4, 1172), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10015 {"evaddbss", VX (4, 1173), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10016 {"evsubfb", VX (4, 1174), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10017 {"evsubfbss", VX (4, 1175), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10018 {"evaddsubfh", VX (4, 1176), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10019 {"evaddsubfhss", VX (4, 1177), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10020 {"evsubfaddh", VX (4, 1178), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10021 {"evsubfaddhss", VX (4, 1179), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10022 {"evaddsubfhx", VX (4, 1180), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10023 {"evaddsubfhxss", VX (4, 1181), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10024 {"evsubfaddhx", VX (4, 1182), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10025 {"evsubfaddhxss", VX (4, 1183), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10026 {"evadddus", VX (4, 1184), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10027 {"evaddbus", VX (4, 1185), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10028 {"evsubfdus", VX (4, 1186), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10029 {"evsubfbus", VX (4, 1187), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10030 {"evaddwus", VX (4, 1188), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10031 {"evaddwxus", VX (4, 1189), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10032 {"evsubfwus", VX (4, 1190), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10033 {"evsubfwxus", VX (4, 1191), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10034 {"evadd2subf2h", VX (4, 1192), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10035 {"evadd2subf2hss", VX (4, 1193), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10036 {"evsubf2add2h", VX (4, 1194), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10037 {"evsubf2add2hss", VX (4, 1195), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10038 {"evaddhus", VX (4, 1196), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10039 {"evaddhxus", VX (4, 1197), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10040 {"evsubfhus", VX (4, 1198), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10041 {"evsubfhxus", VX (4, 1199), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10042 {"evaddwss", VX (4, 1201), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10043 {"evsubfwss", VX (4, 1203), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10044 {"evaddwx", VX (4, 1204), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10045 {"evaddwxss", VX (4, 1205), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10046 {"evsubfwx", VX (4, 1206), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10047 {"evsubfwxss", VX (4, 1207), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10048 {"evaddsubfw", VX (4, 1208), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10049 {"evaddsubfwss", VX (4, 1209), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10050 {"evsubfaddw", VX (4, 1210), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10051 {"evsubfaddwss", VX (4, 1211), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10052 {"evaddsubfwx", VX (4, 1212), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10053 {"evaddsubfwxss", VX (4, 1213), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10054 {"evsubfaddwx", VX (4, 1214), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10055 {"evsubfaddwxss", VX (4, 1215), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10056 {"evmar", VX_SPE2_EVMAR (4, 1220), VX_SPE2_EVMAR_MASK
, PPCSPE2
, 0, {RD
}},
10057 {"evsumwu", VX_RB_CONST(4, 1221, 0), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, RA
}},
10058 {"evsumws", VX_RB_CONST(4, 1221, 1), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, RA
}},
10059 {"evsum4bu", VX_RB_CONST(4, 1221, 2), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, RA
}},
10060 {"evsum4bs", VX_RB_CONST(4, 1221, 3), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, RA
}},
10061 {"evsum2hu", VX_RB_CONST(4, 1221, 4), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, RA
}},
10062 {"evsum2hs", VX_RB_CONST(4, 1221, 5), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, RA
}},
10063 {"evdiff2his", VX_RB_CONST(4, 1221, 6), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, RA
}},
10064 {"evsum2his", VX_RB_CONST(4, 1221, 7), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, RA
}},
10065 {"evsumwua", VX_RB_CONST(4, 1221, 16), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, RA
}},
10066 {"evsumwsa", VX_RB_CONST(4, 1221, 17), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, RA
}},
10067 {"evsum4bua", VX_RB_CONST(4, 1221, 18), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, RA
}},
10068 {"evsum4bsa", VX_RB_CONST(4, 1221, 19), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, RA
}},
10069 {"evsum2hua", VX_RB_CONST(4, 1221, 20), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, RA
}},
10070 {"evsum2hsa", VX_RB_CONST(4, 1221, 21), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, RA
}},
10071 {"evdiff2hisa", VX_RB_CONST(4, 1221, 22), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, RA
}},
10072 {"evsum2hisa", VX_RB_CONST(4, 1221, 23), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, RA
}},
10073 {"evsumwuaa", VX_RB_CONST(4, 1221, 24), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, RA
}},
10074 {"evsumwsaa", VX_RB_CONST(4, 1221, 25), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, RA
}},
10075 {"evsum4buaaw", VX_RB_CONST(4, 1221, 26), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, RA
}},
10076 {"evsum4bsaaw", VX_RB_CONST(4, 1221, 27), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, RA
}},
10077 {"evsum2huaaw", VX_RB_CONST(4, 1221, 28), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, RA
}},
10078 {"evsum2hsaaw", VX_RB_CONST(4, 1221, 29), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, RA
}},
10079 {"evdiff2hisaaw", VX_RB_CONST(4, 1221, 30), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, RA
}},
10080 {"evsum2hisaaw", VX_RB_CONST(4, 1221, 31), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, RA
}},
10081 {"evdivwsf", VX (4, 1228), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10082 {"evdivwuf", VX (4, 1229), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10083 {"evdivs", VX (4, 1230), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10084 {"evdivu", VX (4, 1231), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10085 {"evaddwegsi", VX (4, 1232), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10086 {"evaddwegsf", VX (4, 1233), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10087 {"evsubfwegsi", VX (4, 1234), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10088 {"evsubfwegsf", VX (4, 1235), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10089 {"evaddwogsi", VX (4, 1236), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10090 {"evaddwogsf", VX (4, 1237), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10091 {"evsubfwogsi", VX (4, 1238), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10092 {"evsubfwogsf", VX (4, 1239), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10093 {"evaddhhiuw", VX (4, 1240), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10094 {"evaddhhisw", VX (4, 1241), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10095 {"evsubfhhiuw", VX (4, 1242), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10096 {"evsubfhhisw", VX (4, 1243), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10097 {"evaddhlouw", VX (4, 1244), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10098 {"evaddhlosw", VX (4, 1245), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10099 {"evsubfhlouw", VX (4, 1246), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10100 {"evsubfhlosw", VX (4, 1247), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10101 {"evmhesusiaaw", VX (4, 1282), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10102 {"evmhosusiaaw", VX (4, 1286), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10103 {"evmhesumiaaw", VX (4, 1290), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10104 {"evmhosumiaaw", VX (4, 1294), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10105 {"evmbeusiaah", VX (4, 1296), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10106 {"evmbessiaah", VX (4, 1297), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10107 {"evmbesusiaah", VX (4, 1298), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10108 {"evmbousiaah", VX (4, 1300), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10109 {"evmbossiaah", VX (4, 1301), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10110 {"evmbosusiaah", VX (4, 1302), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10111 {"evmbeumiaah", VX (4, 1304), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10112 {"evmbesmiaah", VX (4, 1305), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10113 {"evmbesumiaah", VX (4, 1306), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10114 {"evmboumiaah", VX (4, 1308), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10115 {"evmbosmiaah", VX (4, 1309), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10116 {"evmbosumiaah", VX (4, 1310), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10117 {"evmwlusiaaw3", VX (4, 1346), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10118 {"evmwlssiaaw3", VX (4, 1347), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10119 {"evmwhssfraaw3", VX (4, 1348), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10120 {"evmwhssfaaw3", VX (4, 1349), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10121 {"evmwhssfraaw", VX (4, 1350), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10122 {"evmwhssfaaw", VX (4, 1351), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10123 {"evmwlumiaaw3", VX (4, 1354), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10124 {"evmwlsmiaaw3", VX (4, 1355), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10125 {"evmwusiaa", VX (4, 1360), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10126 {"evmwssiaa", VX (4, 1361), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10127 {"evmwehgsmfraa", VX (4, 1366), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10128 {"evmwehgsmfaa", VX (4, 1367), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10129 {"evmwohgsmfraa", VX (4, 1374), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10130 {"evmwohgsmfaa", VX (4, 1375), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10131 {"evmhesusianw", VX (4, 1410), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10132 {"evmhosusianw", VX (4, 1414), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10133 {"evmhesumianw", VX (4, 1418), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10134 {"evmhosumianw", VX (4, 1422), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10135 {"evmbeusianh", VX (4, 1424), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10136 {"evmbessianh", VX (4, 1425), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10137 {"evmbesusianh", VX (4, 1426), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10138 {"evmbousianh", VX (4, 1428), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10139 {"evmbossianh", VX (4, 1429), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10140 {"evmbosusianh", VX (4, 1430), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10141 {"evmbeumianh", VX (4, 1432), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10142 {"evmbesmianh", VX (4, 1433), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10143 {"evmbesumianh", VX (4, 1434), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10144 {"evmboumianh", VX (4, 1436), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10145 {"evmbosmianh", VX (4, 1437), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10146 {"evmbosumianh", VX (4, 1438), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10147 {"evmwlusianw3", VX (4, 1474), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10148 {"evmwlssianw3", VX (4, 1475), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10149 {"evmwhssfranw3", VX (4, 1476), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10150 {"evmwhssfanw3", VX (4, 1477), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10151 {"evmwhssfranw", VX (4, 1478), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10152 {"evmwhssfanw", VX (4, 1479), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10153 {"evmwlumianw3", VX (4, 1482), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10154 {"evmwlsmianw3", VX (4, 1483), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10155 {"evmwusian", VX (4, 1488), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10156 {"evmwssian", VX (4, 1489), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10157 {"evmwehgsmfran", VX (4, 1494), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10158 {"evmwehgsmfan", VX (4, 1495), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10159 {"evmwohgsmfran", VX (4, 1502), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10160 {"evmwohgsmfan", VX (4, 1503), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10161 {"evseteqb", VX (4, 1536), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10162 {"evseteqb.", VX (4, 1537), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10163 {"evseteqh", VX (4, 1538), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10164 {"evseteqh.", VX (4, 1539), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10165 {"evseteqw", VX (4, 1540), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10166 {"evseteqw.", VX (4, 1541), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10167 {"evsetgthu", VX (4, 1544), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10168 {"evsetgthu.", VX (4, 1545), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10169 {"evsetgths", VX (4, 1546), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10170 {"evsetgths.", VX (4, 1547), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10171 {"evsetgtwu", VX (4, 1548), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10172 {"evsetgtwu.", VX (4, 1549), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10173 {"evsetgtws", VX (4, 1550), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10174 {"evsetgtws.", VX (4, 1551), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10175 {"evsetgtbu", VX (4, 1552), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10176 {"evsetgtbu.", VX (4, 1553), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10177 {"evsetgtbs", VX (4, 1554), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10178 {"evsetgtbs.", VX (4, 1555), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10179 {"evsetltbu", VX (4, 1556), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10180 {"evsetltbu.", VX (4, 1557), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10181 {"evsetltbs", VX (4, 1558), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10182 {"evsetltbs.", VX (4, 1559), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10183 {"evsetlthu", VX (4, 1560), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10184 {"evsetlthu.", VX (4, 1561), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10185 {"evsetlths", VX (4, 1562), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10186 {"evsetlths.", VX (4, 1563), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10187 {"evsetltwu", VX (4, 1564), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10188 {"evsetltwu.", VX (4, 1565), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10189 {"evsetltws", VX (4, 1566), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10190 {"evsetltws.", VX (4, 1567), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10191 {"evsaduw", VX (4, 1568), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10192 {"evsadsw", VX (4, 1569), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10193 {"evsad4ub", VX (4, 1570), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10194 {"evsad4sb", VX (4, 1571), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10195 {"evsad2uh", VX (4, 1572), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10196 {"evsad2sh", VX (4, 1573), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10197 {"evsaduwa", VX (4, 1576), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10198 {"evsadswa", VX (4, 1577), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10199 {"evsad4uba", VX (4, 1578), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10200 {"evsad4sba", VX (4, 1579), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10201 {"evsad2uha", VX (4, 1580), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10202 {"evsad2sha", VX (4, 1581), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10203 {"evabsdifuw", VX (4, 1584), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10204 {"evabsdifsw", VX (4, 1585), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10205 {"evabsdifub", VX (4, 1586), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10206 {"evabsdifsb", VX (4, 1587), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10207 {"evabsdifuh", VX (4, 1588), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10208 {"evabsdifsh", VX (4, 1589), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10209 {"evsaduwaa", VX (4, 1592), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10210 {"evsadswaa", VX (4, 1593), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10211 {"evsad4ubaaw", VX (4, 1594), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10212 {"evsad4sbaaw", VX (4, 1595), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10213 {"evsad2uhaaw", VX (4, 1596), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10214 {"evsad2shaaw", VX (4, 1597), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10215 {"evpkshubs", VX (4, 1600), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10216 {"evpkshsbs", VX (4, 1601), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10217 {"evpkswuhs", VX (4, 1602), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10218 {"evpkswshs", VX (4, 1603), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10219 {"evpkuhubs", VX (4, 1604), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10220 {"evpkuwuhs", VX (4, 1605), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10221 {"evpkswshilvs", VX (4, 1606), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10222 {"evpkswgshefrs", VX (4, 1607), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10223 {"evpkswshfrs", VX (4, 1608), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10224 {"evpkswshilvfrs", VX (4, 1609), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10225 {"evpksdswfrs", VX (4, 1610), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10226 {"evpksdshefrs", VX (4, 1611), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10227 {"evpkuduws", VX (4, 1612), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10228 {"evpksdsws", VX (4, 1613), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10229 {"evpkswgswfrs", VX (4, 1614), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10230 {"evilveh", VX (4, 1616), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10231 {"evilveoh", VX (4, 1617), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10232 {"evilvhih", VX (4, 1618), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10233 {"evilvhiloh", VX (4, 1619), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10234 {"evilvloh", VX (4, 1620), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10235 {"evilvlohih", VX (4, 1621), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10236 {"evilvoeh", VX (4, 1622), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10237 {"evilvoh", VX (4, 1623), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10238 {"evdlveb", VX (4, 1624), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10239 {"evdlveh", VX (4, 1625), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10240 {"evdlveob", VX (4, 1626), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10241 {"evdlveoh", VX (4, 1627), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10242 {"evdlvob", VX (4, 1628), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10243 {"evdlvoh", VX (4, 1629), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10244 {"evdlvoeb", VX (4, 1630), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10245 {"evdlvoeh", VX (4, 1631), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10246 {"evmaxbu", VX (4, 1632), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10247 {"evmaxbs", VX (4, 1633), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10248 {"evmaxhu", VX (4, 1634), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10249 {"evmaxhs", VX (4, 1635), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10250 {"evmaxwu", VX (4, 1636), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10251 {"evmaxws", VX (4, 1637), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10252 {"evmaxdu", VX (4, 1638), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10253 {"evmaxds", VX (4, 1639), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10254 {"evminbu", VX (4, 1640), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10255 {"evminbs", VX (4, 1641), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10256 {"evminhu", VX (4, 1642), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10257 {"evminhs", VX (4, 1643), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10258 {"evminwu", VX (4, 1644), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10259 {"evminws", VX (4, 1645), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10260 {"evmindu", VX (4, 1646), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10261 {"evminds", VX (4, 1647), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10262 {"evavgwu", VX (4, 1648), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10263 {"evavgws", VX (4, 1649), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10264 {"evavgbu", VX (4, 1650), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10265 {"evavgbs", VX (4, 1651), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10266 {"evavghu", VX (4, 1652), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10267 {"evavghs", VX (4, 1653), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10268 {"evavgdu", VX (4, 1654), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10269 {"evavgds", VX (4, 1655), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10270 {"evavgwur", VX (4, 1656), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10271 {"evavgwsr", VX (4, 1657), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10272 {"evavgbur", VX (4, 1658), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10273 {"evavgbsr", VX (4, 1659), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10274 {"evavghur", VX (4, 1660), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10275 {"evavghsr", VX (4, 1661), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10276 {"evavgdur", VX (4, 1662), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10277 {"evavgdsr", VX (4, 1663), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10280 const unsigned int spe2_num_opcodes
=
10281 sizeof (spe2_opcodes
) / sizeof (spe2_opcodes
[0]);