1 /* ppc-opc.c -- PowerPC opcode list
2 Copyright (C) 1994-2015 Free Software Foundation, Inc.
3 Written by Ian Lance Taylor, Cygnus Support
5 This file is part of the GNU opcodes library.
7 This library is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3, or (at your option)
12 It is distributed in the hope that it will be useful, but WITHOUT
13 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
14 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
15 License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this file; see the file COPYING. If not, write to the
19 Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston,
20 MA 02110-1301, USA. */
24 #include "opcode/ppc.h"
27 /* This file holds the PowerPC opcode table. The opcode table
28 includes almost all of the extended instruction mnemonics. This
29 permits the disassembler to use them, and simplifies the assembler
30 logic, at the cost of increasing the table size. The table is
31 strictly constant data, so the compiler should be able to put it in
34 This file also holds the operand table. All knowledge about
35 inserting operands into instructions and vice-versa is kept in this
38 /* Local insertion and extraction functions. */
40 static unsigned long insert_arx (unsigned long, long, ppc_cpu_t
, const char **);
41 static long extract_arx (unsigned long, ppc_cpu_t
, int *);
42 static unsigned long insert_ary (unsigned long, long, ppc_cpu_t
, const char **);
43 static long extract_ary (unsigned long, ppc_cpu_t
, int *);
44 static unsigned long insert_bat (unsigned long, long, ppc_cpu_t
, const char **);
45 static long extract_bat (unsigned long, ppc_cpu_t
, int *);
46 static unsigned long insert_bba (unsigned long, long, ppc_cpu_t
, const char **);
47 static long extract_bba (unsigned long, ppc_cpu_t
, int *);
48 static unsigned long insert_bdm (unsigned long, long, ppc_cpu_t
, const char **);
49 static long extract_bdm (unsigned long, ppc_cpu_t
, int *);
50 static unsigned long insert_bdp (unsigned long, long, ppc_cpu_t
, const char **);
51 static long extract_bdp (unsigned long, ppc_cpu_t
, int *);
52 static unsigned long insert_bo (unsigned long, long, ppc_cpu_t
, const char **);
53 static long extract_bo (unsigned long, ppc_cpu_t
, int *);
54 static unsigned long insert_boe (unsigned long, long, ppc_cpu_t
, const char **);
55 static long extract_boe (unsigned long, ppc_cpu_t
, int *);
56 static unsigned long insert_fxm (unsigned long, long, ppc_cpu_t
, const char **);
57 static long extract_fxm (unsigned long, ppc_cpu_t
, int *);
58 static unsigned long insert_li20 (unsigned long, long, ppc_cpu_t
, const char **);
59 static long extract_li20 (unsigned long, ppc_cpu_t
, int *);
60 static unsigned long insert_ls (unsigned long, long, ppc_cpu_t
, const char **);
61 static unsigned long insert_mbe (unsigned long, long, ppc_cpu_t
, const char **);
62 static long extract_mbe (unsigned long, ppc_cpu_t
, int *);
63 static unsigned long insert_mb6 (unsigned long, long, ppc_cpu_t
, const char **);
64 static long extract_mb6 (unsigned long, ppc_cpu_t
, int *);
65 static long extract_nb (unsigned long, ppc_cpu_t
, int *);
66 static unsigned long insert_nbi (unsigned long, long, ppc_cpu_t
, const char **);
67 static unsigned long insert_nsi (unsigned long, long, ppc_cpu_t
, const char **);
68 static long extract_nsi (unsigned long, ppc_cpu_t
, int *);
69 static unsigned long insert_oimm (unsigned long, long, ppc_cpu_t
, const char **);
70 static long extract_oimm (unsigned long, ppc_cpu_t
, int *);
71 static unsigned long insert_ral (unsigned long, long, ppc_cpu_t
, const char **);
72 static unsigned long insert_ram (unsigned long, long, ppc_cpu_t
, const char **);
73 static unsigned long insert_raq (unsigned long, long, ppc_cpu_t
, const char **);
74 static unsigned long insert_ras (unsigned long, long, ppc_cpu_t
, const char **);
75 static unsigned long insert_rbs (unsigned long, long, ppc_cpu_t
, const char **);
76 static long extract_rbs (unsigned long, ppc_cpu_t
, int *);
77 static unsigned long insert_rbx (unsigned long, long, ppc_cpu_t
, const char **);
78 static unsigned long insert_rx (unsigned long, long, ppc_cpu_t
, const char **);
79 static long extract_rx (unsigned long, ppc_cpu_t
, int *);
80 static unsigned long insert_ry (unsigned long, long, ppc_cpu_t
, const char **);
81 static long extract_ry (unsigned long, ppc_cpu_t
, int *);
82 static unsigned long insert_sh6 (unsigned long, long, ppc_cpu_t
, const char **);
83 static long extract_sh6 (unsigned long, ppc_cpu_t
, int *);
84 static unsigned long insert_sci8 (unsigned long, long, ppc_cpu_t
, const char **);
85 static long extract_sci8 (unsigned long, ppc_cpu_t
, int *);
86 static unsigned long insert_sci8n (unsigned long, long, ppc_cpu_t
, const char **);
87 static long extract_sci8n (unsigned long, ppc_cpu_t
, int *);
88 static unsigned long insert_sd4h (unsigned long, long, ppc_cpu_t
, const char **);
89 static long extract_sd4h (unsigned long, ppc_cpu_t
, int *);
90 static unsigned long insert_sd4w (unsigned long, long, ppc_cpu_t
, const char **);
91 static long extract_sd4w (unsigned long, ppc_cpu_t
, int *);
92 static unsigned long insert_spr (unsigned long, long, ppc_cpu_t
, const char **);
93 static long extract_spr (unsigned long, ppc_cpu_t
, int *);
94 static unsigned long insert_sprg (unsigned long, long, ppc_cpu_t
, const char **);
95 static long extract_sprg (unsigned long, ppc_cpu_t
, int *);
96 static unsigned long insert_tbr (unsigned long, long, ppc_cpu_t
, const char **);
97 static long extract_tbr (unsigned long, ppc_cpu_t
, int *);
98 static unsigned long insert_xt6 (unsigned long, long, ppc_cpu_t
, const char **);
99 static long extract_xt6 (unsigned long, ppc_cpu_t
, int *);
100 static unsigned long insert_xa6 (unsigned long, long, ppc_cpu_t
, const char **);
101 static long extract_xa6 (unsigned long, ppc_cpu_t
, int *);
102 static unsigned long insert_xb6 (unsigned long, long, ppc_cpu_t
, const char **);
103 static long extract_xb6 (unsigned long, ppc_cpu_t
, int *);
104 static unsigned long insert_xb6s (unsigned long, long, ppc_cpu_t
, const char **);
105 static long extract_xb6s (unsigned long, ppc_cpu_t
, int *);
106 static unsigned long insert_xc6 (unsigned long, long, ppc_cpu_t
, const char **);
107 static long extract_xc6 (unsigned long, ppc_cpu_t
, int *);
108 static unsigned long insert_dm (unsigned long, long, ppc_cpu_t
, const char **);
109 static long extract_dm (unsigned long, ppc_cpu_t
, int *);
110 static unsigned long insert_vlesi (unsigned long, long, ppc_cpu_t
, const char **);
111 static long extract_vlesi (unsigned long, ppc_cpu_t
, int *);
112 static unsigned long insert_vlensi (unsigned long, long, ppc_cpu_t
, const char **);
113 static long extract_vlensi (unsigned long, ppc_cpu_t
, int *);
114 static unsigned long insert_vleui (unsigned long, long, ppc_cpu_t
, const char **);
115 static long extract_vleui (unsigned long, ppc_cpu_t
, int *);
116 static unsigned long insert_vleil (unsigned long, long, ppc_cpu_t
, const char **);
117 static long extract_vleil (unsigned long, ppc_cpu_t
, int *);
119 /* The operands table.
121 The fields are bitm, shift, insert, extract, flags.
123 We used to put parens around the various additions, like the one
124 for BA just below. However, that caused trouble with feeble
125 compilers with a limit on depth of a parenthesized expression, like
126 (reportedly) the compiler in Microsoft Developer Studio 5. So we
127 omit the parens, since the macros are never used in a context where
128 the addition will be ambiguous. */
130 const struct powerpc_operand powerpc_operands
[] =
132 /* The zero index is used to indicate the end of the list of
135 { 0, 0, NULL
, NULL
, 0 },
137 /* The BA field in an XL form instruction. */
138 #define BA UNUSED + 1
139 /* The BI field in a B form or XL form instruction. */
141 #define BI_MASK (0x1f << 16)
142 { 0x1f, 16, NULL
, NULL
, PPC_OPERAND_CR_BIT
},
144 /* The BA field in an XL form instruction when it must be the same
145 as the BT field in the same instruction. */
147 { 0x1f, 16, insert_bat
, extract_bat
, PPC_OPERAND_FAKE
},
149 /* The BB field in an XL form instruction. */
151 #define BB_MASK (0x1f << 11)
152 { 0x1f, 11, NULL
, NULL
, PPC_OPERAND_CR_BIT
},
154 /* The BB field in an XL form instruction when it must be the same
155 as the BA field in the same instruction. */
157 /* The VB field in a VX form instruction when it must be the same
158 as the VA field in the same instruction. */
160 { 0x1f, 11, insert_bba
, extract_bba
, PPC_OPERAND_FAKE
},
162 /* The BD field in a B form instruction. The lower two bits are
165 { 0xfffc, 0, NULL
, NULL
, PPC_OPERAND_RELATIVE
| PPC_OPERAND_SIGNED
},
167 /* The BD field in a B form instruction when absolute addressing is
170 { 0xfffc, 0, NULL
, NULL
, PPC_OPERAND_ABSOLUTE
| PPC_OPERAND_SIGNED
},
172 /* The BD field in a B form instruction when the - modifier is used.
173 This sets the y bit of the BO field appropriately. */
175 { 0xfffc, 0, insert_bdm
, extract_bdm
,
176 PPC_OPERAND_RELATIVE
| PPC_OPERAND_SIGNED
},
178 /* The BD field in a B form instruction when the - modifier is used
179 and absolute address is used. */
181 { 0xfffc, 0, insert_bdm
, extract_bdm
,
182 PPC_OPERAND_ABSOLUTE
| PPC_OPERAND_SIGNED
},
184 /* The BD field in a B form instruction when the + modifier is used.
185 This sets the y bit of the BO field appropriately. */
187 { 0xfffc, 0, insert_bdp
, extract_bdp
,
188 PPC_OPERAND_RELATIVE
| PPC_OPERAND_SIGNED
},
190 /* The BD field in a B form instruction when the + modifier is used
191 and absolute addressing is used. */
193 { 0xfffc, 0, insert_bdp
, extract_bdp
,
194 PPC_OPERAND_ABSOLUTE
| PPC_OPERAND_SIGNED
},
196 /* The BF field in an X or XL form instruction. */
198 /* The CRFD field in an X form instruction. */
200 /* The CRD field in an XL form instruction. */
202 { 0x7, 23, NULL
, NULL
, PPC_OPERAND_CR_REG
},
204 /* The BF field in an X or XL form instruction. */
206 { 0x7, 23, NULL
, NULL
, 0 },
208 /* An optional BF field. This is used for comparison instructions,
209 in which an omitted BF field is taken as zero. */
211 { 0x7, 23, NULL
, NULL
, PPC_OPERAND_CR_REG
| PPC_OPERAND_OPTIONAL
},
213 /* The BFA field in an X or XL form instruction. */
215 { 0x7, 18, NULL
, NULL
, PPC_OPERAND_CR_REG
},
217 /* The BO field in a B form instruction. Certain values are
220 #define BO_MASK (0x1f << 21)
221 { 0x1f, 21, insert_bo
, extract_bo
, 0 },
223 /* The BO field in a B form instruction when the + or - modifier is
224 used. This is like the BO field, but it must be even. */
226 { 0x1e, 21, insert_boe
, extract_boe
, 0 },
229 { 0x3, 11, NULL
, NULL
, PPC_OPERAND_OPTIONAL
},
231 /* The BT field in an X or XL form instruction. */
233 { 0x1f, 21, NULL
, NULL
, PPC_OPERAND_CR_BIT
},
235 /* The BI16 field in a BD8 form instruction. */
237 { 0x3, 8, NULL
, NULL
, PPC_OPERAND_CR_BIT
},
239 /* The BI32 field in a BD15 form instruction. */
240 #define BI32 BI16 + 1
241 { 0xf, 16, NULL
, NULL
, PPC_OPERAND_CR_BIT
},
243 /* The BO32 field in a BD15 form instruction. */
244 #define BO32 BI32 + 1
245 { 0x3, 20, NULL
, NULL
, 0 },
247 /* The B8 field in a BD8 form instruction. */
249 { 0x1fe, -1, NULL
, NULL
, PPC_OPERAND_RELATIVE
| PPC_OPERAND_SIGNED
},
251 /* The B15 field in a BD15 form instruction. The lowest bit is
254 { 0xfffe, 0, NULL
, NULL
, PPC_OPERAND_RELATIVE
| PPC_OPERAND_SIGNED
},
256 /* The B24 field in a BD24 form instruction. The lowest bit is
259 { 0x1fffffe, 0, NULL
, NULL
, PPC_OPERAND_RELATIVE
| PPC_OPERAND_SIGNED
},
261 /* The condition register number portion of the BI field in a B form
262 or XL form instruction. This is used for the extended
263 conditional branch mnemonics, which set the lower two bits of the
264 BI field. This field is optional. */
266 { 0x7, 18, NULL
, NULL
, PPC_OPERAND_CR_REG
| PPC_OPERAND_OPTIONAL
},
268 /* The CRB field in an X form instruction. */
270 /* The MB field in an M form instruction. */
272 #define MB_MASK (0x1f << 6)
273 { 0x1f, 6, NULL
, NULL
, 0 },
275 /* The CRD32 field in an XL form instruction. */
276 #define CRD32 CRB + 1
277 { 0x3, 21, NULL
, NULL
, PPC_OPERAND_CR_REG
},
279 /* The CRFS field in an X form instruction. */
280 #define CRFS CRD32 + 1
281 { 0x7, 0, NULL
, NULL
, PPC_OPERAND_CR_REG
},
284 { 0x3, 18, NULL
, NULL
, PPC_OPERAND_CR_REG
| PPC_OPERAND_OPTIONAL
},
286 /* The CT field in an X form instruction. */
288 /* The MO field in an mbar instruction. */
290 { 0x1f, 21, NULL
, NULL
, PPC_OPERAND_OPTIONAL
},
292 /* The D field in a D form instruction. This is a displacement off
293 a register, and implies that the next operand is a register in
296 { 0xffff, 0, NULL
, NULL
, PPC_OPERAND_PARENS
| PPC_OPERAND_SIGNED
},
298 /* The D8 field in a D form instruction. This is a displacement off
299 a register, and implies that the next operand is a register in
302 { 0xff, 0, NULL
, NULL
, PPC_OPERAND_PARENS
| PPC_OPERAND_SIGNED
},
304 /* The DQ field in a DQ form instruction. This is like D, but the
305 lower four bits are forced to zero. */
307 { 0xfff0, 0, NULL
, NULL
,
308 PPC_OPERAND_PARENS
| PPC_OPERAND_SIGNED
| PPC_OPERAND_DQ
},
310 /* The DS field in a DS form instruction. This is like D, but the
311 lower two bits are forced to zero. */
313 { 0xfffc, 0, NULL
, NULL
,
314 PPC_OPERAND_PARENS
| PPC_OPERAND_SIGNED
| PPC_OPERAND_DS
},
316 /* The DUIS or BHRBE fields in a XFX form instruction, 10 bits
320 { 0x3ff, 11, NULL
, NULL
, 0 },
322 /* The E field in a wrteei instruction. */
323 /* And the W bit in the pair singles instructions. */
324 /* And the ST field in a VX form instruction. */
328 { 0x1, 15, NULL
, NULL
, 0 },
330 /* The FL1 field in a POWER SC form instruction. */
332 /* The U field in an X form instruction. */
334 { 0xf, 12, NULL
, NULL
, 0 },
336 /* The FL2 field in a POWER SC form instruction. */
338 { 0x7, 2, NULL
, NULL
, 0 },
340 /* The FLM field in an XFL form instruction. */
342 { 0xff, 17, NULL
, NULL
, 0 },
344 /* The FRA field in an X or A form instruction. */
346 #define FRA_MASK (0x1f << 16)
347 { 0x1f, 16, NULL
, NULL
, PPC_OPERAND_FPR
},
349 /* The FRAp field of DFP instructions. */
351 { 0x1e, 16, NULL
, NULL
, PPC_OPERAND_FPR
},
353 /* The FRB field in an X or A form instruction. */
355 #define FRB_MASK (0x1f << 11)
356 { 0x1f, 11, NULL
, NULL
, PPC_OPERAND_FPR
},
358 /* The FRBp field of DFP instructions. */
360 { 0x1e, 11, NULL
, NULL
, PPC_OPERAND_FPR
},
362 /* The FRC field in an A form instruction. */
364 #define FRC_MASK (0x1f << 6)
365 { 0x1f, 6, NULL
, NULL
, PPC_OPERAND_FPR
},
367 /* The FRS field in an X form instruction or the FRT field in a D, X
368 or A form instruction. */
371 { 0x1f, 21, NULL
, NULL
, PPC_OPERAND_FPR
},
373 /* The FRSp field of stfdp or the FRTp field of lfdp and DFP
377 { 0x1e, 21, NULL
, NULL
, PPC_OPERAND_FPR
},
379 /* The FXM field in an XFX instruction. */
381 { 0xff, 12, insert_fxm
, extract_fxm
, 0 },
383 /* Power4 version for mfcr. */
385 { 0xff, 12, insert_fxm
, extract_fxm
, PPC_OPERAND_OPTIONAL
},
387 /* The IMM20 field in an LI instruction. */
388 #define IMM20 FXM4 + 1
389 { 0xfffff, PPC_OPSHIFT_INV
, insert_li20
, extract_li20
, PPC_OPERAND_SIGNED
},
391 /* The L field in a D or X form instruction. */
393 /* The R field in a HTM X form instruction. */
395 { 0x1, 21, NULL
, NULL
, PPC_OPERAND_OPTIONAL
},
397 /* The LEV field in a POWER SVC form instruction. */
398 #define SVC_LEV L + 1
399 { 0x7f, 5, NULL
, NULL
, 0 },
401 /* The LEV field in an SC form instruction. */
402 #define LEV SVC_LEV + 1
403 { 0x7f, 5, NULL
, NULL
, PPC_OPERAND_OPTIONAL
},
405 /* The LI field in an I form instruction. The lower two bits are
408 { 0x3fffffc, 0, NULL
, NULL
, PPC_OPERAND_RELATIVE
| PPC_OPERAND_SIGNED
},
410 /* The LI field in an I form instruction when used as an absolute
413 { 0x3fffffc, 0, NULL
, NULL
, PPC_OPERAND_ABSOLUTE
| PPC_OPERAND_SIGNED
},
415 /* The LS or WC field in an X (sync or wait) form instruction. */
418 { 0x3, 21, NULL
, NULL
, PPC_OPERAND_OPTIONAL
},
420 /* The ME field in an M form instruction. */
422 #define ME_MASK (0x1f << 1)
423 { 0x1f, 1, NULL
, NULL
, 0 },
425 /* The MB and ME fields in an M form instruction expressed a single
426 operand which is a bitmask indicating which bits to select. This
427 is a two operand form using PPC_OPERAND_NEXT. See the
428 description in opcode/ppc.h for what this means. */
430 { 0x1f, 6, NULL
, NULL
, PPC_OPERAND_OPTIONAL
| PPC_OPERAND_NEXT
},
431 { -1, 0, insert_mbe
, extract_mbe
, 0 },
433 /* The MB or ME field in an MD or MDS form instruction. The high
434 bit is wrapped to the low end. */
437 #define MB6_MASK (0x3f << 5)
438 { 0x3f, 5, insert_mb6
, extract_mb6
, 0 },
440 /* The NB field in an X form instruction. The value 32 is stored as
443 { 0x1f, 11, NULL
, extract_nb
, PPC_OPERAND_PLUS1
},
445 /* The NBI field in an lswi instruction, which has special value
446 restrictions. The value 32 is stored as 0. */
448 { 0x1f, 11, insert_nbi
, extract_nb
, PPC_OPERAND_PLUS1
},
450 /* The NSI field in a D form instruction. This is the same as the
451 SI field, only negated. */
453 { 0xffff, 0, insert_nsi
, extract_nsi
,
454 PPC_OPERAND_NEGATIVE
| PPC_OPERAND_SIGNED
},
456 /* The RA field in an D, DS, DQ, X, XO, M, or MDS form instruction. */
458 #define RA_MASK (0x1f << 16)
459 { 0x1f, 16, NULL
, NULL
, PPC_OPERAND_GPR
},
461 /* As above, but 0 in the RA field means zero, not r0. */
463 { 0x1f, 16, NULL
, NULL
, PPC_OPERAND_GPR_0
},
465 /* The RA field in the DQ form lq or an lswx instruction, which have special
466 value restrictions. */
469 { 0x1f, 16, insert_raq
, NULL
, PPC_OPERAND_GPR_0
},
471 /* The RA field in a D or X form instruction which is an updating
472 load, which means that the RA field may not be zero and may not
473 equal the RT field. */
475 { 0x1f, 16, insert_ral
, NULL
, PPC_OPERAND_GPR_0
},
477 /* The RA field in an lmw instruction, which has special value
480 { 0x1f, 16, insert_ram
, NULL
, PPC_OPERAND_GPR_0
},
482 /* The RA field in a D or X form instruction which is an updating
483 store or an updating floating point load, which means that the RA
484 field may not be zero. */
486 { 0x1f, 16, insert_ras
, NULL
, PPC_OPERAND_GPR_0
},
488 /* The RA field of the tlbwe, dccci and iccci instructions,
489 which are optional. */
490 #define RAOPT RAS + 1
491 { 0x1f, 16, NULL
, NULL
, PPC_OPERAND_GPR
| PPC_OPERAND_OPTIONAL
},
493 /* The RB field in an X, XO, M, or MDS form instruction. */
495 #define RB_MASK (0x1f << 11)
496 { 0x1f, 11, NULL
, NULL
, PPC_OPERAND_GPR
},
498 /* The RB field in an X form instruction when it must be the same as
499 the RS field in the instruction. This is used for extended
500 mnemonics like mr. */
502 { 0x1f, 11, insert_rbs
, extract_rbs
, PPC_OPERAND_FAKE
},
504 /* The RB field in an lswx instruction, which has special value
507 { 0x1f, 11, insert_rbx
, NULL
, PPC_OPERAND_GPR
},
509 /* The RB field of the dccci and iccci instructions, which are optional. */
510 #define RBOPT RBX + 1
511 { 0x1f, 11, NULL
, NULL
, PPC_OPERAND_GPR
| PPC_OPERAND_OPTIONAL
},
513 /* The RS field in a D, DS, X, XFX, XS, M, MD or MDS form
514 instruction or the RT field in a D, DS, X, XFX or XO form
518 #define RT_MASK (0x1f << 21)
520 { 0x1f, 21, NULL
, NULL
, PPC_OPERAND_GPR
},
522 /* The RS and RT fields of the DS form stq and DQ form lq instructions,
523 which have special value restrictions. */
526 { 0x1e, 21, NULL
, NULL
, PPC_OPERAND_GPR
},
528 /* The RS field of the tlbwe instruction, which is optional. */
531 { 0x1f, 21, NULL
, NULL
, PPC_OPERAND_GPR
| PPC_OPERAND_OPTIONAL
},
533 /* The RX field of the SE_RR form instruction. */
535 { 0x1f, PPC_OPSHIFT_INV
, insert_rx
, extract_rx
, PPC_OPERAND_GPR
},
537 /* The ARX field of the SE_RR form instruction. */
539 { 0x1f, PPC_OPSHIFT_INV
, insert_arx
, extract_arx
, PPC_OPERAND_GPR
},
541 /* The RY field of the SE_RR form instruction. */
544 { 0x1f, PPC_OPSHIFT_INV
, insert_ry
, extract_ry
, PPC_OPERAND_GPR
},
546 /* The ARY field of the SE_RR form instruction. */
548 { 0x1f, PPC_OPSHIFT_INV
, insert_ary
, extract_ary
, PPC_OPERAND_GPR
},
550 /* The SCLSCI8 field in a D form instruction. */
551 #define SCLSCI8 ARY + 1
552 { 0xffffffff, PPC_OPSHIFT_INV
, insert_sci8
, extract_sci8
, 0 },
554 /* The SCLSCI8N field in a D form instruction. This is the same as the
555 SCLSCI8 field, only negated. */
556 #define SCLSCI8N SCLSCI8 + 1
557 { 0xffffffff, PPC_OPSHIFT_INV
, insert_sci8n
, extract_sci8n
,
558 PPC_OPERAND_NEGATIVE
| PPC_OPERAND_SIGNED
},
560 /* The SD field of the SD4 form instruction. */
561 #define SE_SD SCLSCI8N + 1
562 { 0xf, 8, NULL
, NULL
, PPC_OPERAND_PARENS
},
564 /* The SD field of the SD4 form instruction, for halfword. */
565 #define SE_SDH SE_SD + 1
566 { 0x1e, PPC_OPSHIFT_INV
, insert_sd4h
, extract_sd4h
, PPC_OPERAND_PARENS
},
568 /* The SD field of the SD4 form instruction, for word. */
569 #define SE_SDW SE_SDH + 1
570 { 0x3c, PPC_OPSHIFT_INV
, insert_sd4w
, extract_sd4w
, PPC_OPERAND_PARENS
},
572 /* The SH field in an X or M form instruction. */
573 #define SH SE_SDW + 1
574 #define SH_MASK (0x1f << 11)
575 /* The other UIMM field in a EVX form instruction. */
577 { 0x1f, 11, NULL
, NULL
, 0 },
579 /* The SI field in a HTM X form instruction. */
580 #define HTM_SI SH + 1
581 { 0x1f, 11, NULL
, NULL
, PPC_OPERAND_SIGNED
},
583 /* The SH field in an MD form instruction. This is split. */
584 #define SH6 HTM_SI + 1
585 #define SH6_MASK ((0x1f << 11) | (1 << 1))
586 { 0x3f, PPC_OPSHIFT_INV
, insert_sh6
, extract_sh6
, 0 },
588 /* The SH field of the tlbwe instruction, which is optional. */
590 { 0x1f, 11, NULL
, NULL
, PPC_OPERAND_OPTIONAL
},
592 /* The SI field in a D form instruction. */
594 { 0xffff, 0, NULL
, NULL
, PPC_OPERAND_SIGNED
},
596 /* The SI field in a D form instruction when we accept a wide range
597 of positive values. */
598 #define SISIGNOPT SI + 1
599 { 0xffff, 0, NULL
, NULL
, PPC_OPERAND_SIGNED
| PPC_OPERAND_SIGNOPT
},
601 /* The SI8 field in a D form instruction. */
602 #define SI8 SISIGNOPT + 1
603 { 0xff, 0, NULL
, NULL
, PPC_OPERAND_SIGNED
},
605 /* The SPR field in an XFX form instruction. This is flipped--the
606 lower 5 bits are stored in the upper 5 and vice- versa. */
610 #define SPR_MASK (0x3ff << 11)
611 { 0x3ff, 11, insert_spr
, extract_spr
, 0 },
613 /* The BAT index number in an XFX form m[ft]ibat[lu] instruction. */
614 #define SPRBAT SPR + 1
615 #define SPRBAT_MASK (0x3 << 17)
616 { 0x3, 17, NULL
, NULL
, 0 },
618 /* The SPRG register number in an XFX form m[ft]sprg instruction. */
619 #define SPRG SPRBAT + 1
620 { 0x1f, 16, insert_sprg
, extract_sprg
, 0 },
622 /* The SR field in an X form instruction. */
624 /* The 4-bit UIMM field in a VX form instruction. */
626 { 0xf, 16, NULL
, NULL
, 0 },
628 /* The STRM field in an X AltiVec form instruction. */
630 /* The T field in a tlbilx form instruction. */
632 { 0x3, 21, NULL
, NULL
, 0 },
634 /* The ESYNC field in an X (sync) form instruction. */
635 #define ESYNC STRM + 1
636 { 0xf, 16, insert_ls
, NULL
, PPC_OPERAND_OPTIONAL
},
638 /* The SV field in a POWER SC form instruction. */
640 { 0x3fff, 2, NULL
, NULL
, 0 },
642 /* The TBR field in an XFX form instruction. This is like the SPR
643 field, but it is optional. */
645 { 0x3ff, 11, insert_tbr
, extract_tbr
, PPC_OPERAND_OPTIONAL
},
647 /* The TO field in a D or X form instruction. */
650 #define TO_MASK (0x1f << 21)
651 { 0x1f, 21, NULL
, NULL
, 0 },
653 /* The UI field in a D form instruction. */
655 { 0xffff, 0, NULL
, NULL
, 0 },
657 #define UISIGNOPT UI + 1
658 { 0xffff, 0, NULL
, NULL
, PPC_OPERAND_SIGNOPT
},
660 /* The IMM field in an SE_IM5 instruction. */
661 #define UI5 UISIGNOPT + 1
662 { 0x1f, 4, NULL
, NULL
, 0 },
664 /* The OIMM field in an SE_OIM5 instruction. */
665 #define OIMM5 UI5 + 1
666 { 0x1f, PPC_OPSHIFT_INV
, insert_oimm
, extract_oimm
, PPC_OPERAND_PLUS1
},
668 /* The UI7 field in an SE_LI instruction. */
669 #define UI7 OIMM5 + 1
670 { 0x7f, 4, NULL
, NULL
, 0 },
672 /* The VA field in a VA, VX or VXR form instruction. */
674 { 0x1f, 16, NULL
, NULL
, PPC_OPERAND_VR
},
676 /* The VB field in a VA, VX or VXR form instruction. */
678 { 0x1f, 11, NULL
, NULL
, PPC_OPERAND_VR
},
680 /* The VC field in a VA form instruction. */
682 { 0x1f, 6, NULL
, NULL
, PPC_OPERAND_VR
},
684 /* The VD or VS field in a VA, VX, VXR or X form instruction. */
687 { 0x1f, 21, NULL
, NULL
, PPC_OPERAND_VR
},
689 /* The SIMM field in a VX form instruction, and TE in Z form. */
692 { 0x1f, 16, NULL
, NULL
, PPC_OPERAND_SIGNED
},
694 /* The UIMM field in a VX form instruction. */
695 #define UIMM SIMM + 1
697 { 0x1f, 16, NULL
, NULL
, 0 },
699 /* The 3-bit UIMM field in a VX form instruction. */
700 #define UIMM3 UIMM + 1
701 { 0x7, 16, NULL
, NULL
, 0 },
703 /* The SIX field in a VX form instruction. */
704 #define SIX UIMM3 + 1
705 { 0xf, 11, NULL
, NULL
, 0 },
707 /* The PS field in a VX form instruction. */
709 { 0x1, 9, NULL
, NULL
, 0 },
711 /* The SHB field in a VA form instruction. */
713 { 0xf, 6, NULL
, NULL
, 0 },
715 /* The other UIMM field in a half word EVX form instruction. */
716 #define EVUIMM_2 SHB + 1
717 { 0x3e, 10, NULL
, NULL
, PPC_OPERAND_PARENS
},
719 /* The other UIMM field in a word EVX form instruction. */
720 #define EVUIMM_4 EVUIMM_2 + 1
721 { 0x7c, 9, NULL
, NULL
, PPC_OPERAND_PARENS
},
723 /* The other UIMM field in a double EVX form instruction. */
724 #define EVUIMM_8 EVUIMM_4 + 1
725 { 0xf8, 8, NULL
, NULL
, PPC_OPERAND_PARENS
},
728 #define WS EVUIMM_8 + 1
729 { 0x7, 11, NULL
, NULL
, 0 },
731 /* PowerPC paired singles extensions. */
732 /* W bit in the pair singles instructions for x type instructions. */
734 /* The BO16 field in a BD8 form instruction. */
736 { 0x1, 10, 0, 0, 0 },
738 /* IDX bits for quantization in the pair singles instructions. */
740 { 0x7, 12, 0, 0, 0 },
742 /* IDX bits for quantization in the pair singles x-type instructions. */
746 /* Smaller D field for quantization in the pair singles instructions. */
748 { 0xfff, 0, 0, 0, PPC_OPERAND_PARENS
| PPC_OPERAND_SIGNED
},
753 { 0x1, 16, NULL
, NULL
, PPC_OPERAND_OPTIONAL
},
755 #define RMC MTMSRD_L + 1
756 { 0x3, 9, NULL
, NULL
, 0 },
759 { 0x1, 16, NULL
, NULL
, 0 },
762 { 0x3, 19, NULL
, NULL
, 0 },
765 { 0x1, 20, NULL
, NULL
, 0 },
767 /* The S field in a XL form instruction. */
769 { 0x1, 11, NULL
, NULL
, PPC_OPERAND_OPTIONAL
},
771 /* SH field starting at bit position 16. */
773 /* The DCM and DGM fields in a Z form instruction. */
776 { 0x3f, 10, NULL
, NULL
, 0 },
778 /* The EH field in larx instruction. */
780 { 0x1, 0, NULL
, NULL
, PPC_OPERAND_OPTIONAL
},
782 /* The L field in an mtfsf or XFL form instruction. */
783 /* The A field in a HTM X form instruction. */
786 { 0x1, 25, NULL
, NULL
, PPC_OPERAND_OPTIONAL
},
788 /* Xilinx APU related masks and macros */
789 #define FCRT XFL_L + 1
790 #define FCRT_MASK (0x1f << 21)
791 { 0x1f, 21, 0, 0, PPC_OPERAND_FCR
},
793 /* Xilinx FSL related masks and macros */
795 #define FSL_MASK (0x1f << 11)
796 { 0x1f, 11, 0, 0, PPC_OPERAND_FSL
},
798 /* Xilinx UDI related masks and macros */
800 { 0x1f, 21, 0, 0, PPC_OPERAND_UDI
},
803 { 0x1f, 16, 0, 0, PPC_OPERAND_UDI
},
806 { 0x1f, 11, 0, 0, PPC_OPERAND_UDI
},
809 { 0x1f, 6, 0, 0, PPC_OPERAND_UDI
},
811 /* The VLESIMM field in a D form instruction. */
812 #define VLESIMM URC + 1
813 { 0xffff, PPC_OPSHIFT_INV
, insert_vlesi
, extract_vlesi
,
814 PPC_OPERAND_SIGNED
| PPC_OPERAND_SIGNOPT
},
816 /* The VLENSIMM field in a D form instruction. */
817 #define VLENSIMM VLESIMM + 1
818 { 0xffff, PPC_OPSHIFT_INV
, insert_vlensi
, extract_vlensi
,
819 PPC_OPERAND_NEGATIVE
| PPC_OPERAND_SIGNED
| PPC_OPERAND_SIGNOPT
},
821 /* The VLEUIMM field in a D form instruction. */
822 #define VLEUIMM VLENSIMM + 1
823 { 0xffff, PPC_OPSHIFT_INV
, insert_vleui
, extract_vleui
, 0 },
825 /* The VLEUIMML field in a D form instruction. */
826 #define VLEUIMML VLEUIMM + 1
827 { 0xffff, PPC_OPSHIFT_INV
, insert_vleil
, extract_vleil
, 0 },
829 /* The XT and XS fields in an XX1 or XX3 form instruction. This is split. */
830 #define XS6 VLEUIMML + 1
832 { 0x3f, PPC_OPSHIFT_INV
, insert_xt6
, extract_xt6
, PPC_OPERAND_VSR
},
834 /* The XA field in an XX3 form instruction. This is split. */
836 { 0x3f, PPC_OPSHIFT_INV
, insert_xa6
, extract_xa6
, PPC_OPERAND_VSR
},
838 /* The XB field in an XX2 or XX3 form instruction. This is split. */
840 { 0x3f, PPC_OPSHIFT_INV
, insert_xb6
, extract_xb6
, PPC_OPERAND_VSR
},
842 /* The XB field in an XX3 form instruction when it must be the same as
843 the XA field in the instruction. This is used in extended mnemonics
844 like xvmovdp. This is split. */
846 { 0x3f, PPC_OPSHIFT_INV
, insert_xb6s
, extract_xb6s
, PPC_OPERAND_FAKE
},
848 /* The XC field in an XX4 form instruction. This is split. */
850 { 0x3f, PPC_OPSHIFT_INV
, insert_xc6
, extract_xc6
, PPC_OPERAND_VSR
},
852 /* The DM or SHW field in an XX3 form instruction. */
855 { 0x3, 8, NULL
, NULL
, 0 },
857 /* The DM field in an extended mnemonic XX3 form instruction. */
859 { 0x3, 8, insert_dm
, extract_dm
, 0 },
861 /* The UIM field in an XX2 form instruction. */
863 /* The 2-bit UIMM field in a VX form instruction. */
865 { 0x3, 16, NULL
, NULL
, 0 },
867 #define ERAT_T UIM + 1
868 { 0x7, 21, NULL
, NULL
, 0 },
870 #define IH ERAT_T + 1
871 { 0x7, 21, NULL
, NULL
, PPC_OPERAND_OPTIONAL
},
874 const unsigned int num_powerpc_operands
= (sizeof (powerpc_operands
)
875 / sizeof (powerpc_operands
[0]));
877 /* The functions used to insert and extract complicated operands. */
879 /* The ARX, ARY, RX and RY operands are alternate encodings of GPRs. */
882 insert_arx (unsigned long insn
,
884 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
885 const char **errmsg ATTRIBUTE_UNUSED
)
887 if (value
>= 8 && value
< 24)
888 return insn
| ((value
- 8) & 0xf);
891 *errmsg
= _("invalid register");
897 extract_arx (unsigned long insn
,
898 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
899 int *invalid ATTRIBUTE_UNUSED
)
901 return (insn
& 0xf) + 8;
905 insert_ary (unsigned long insn
,
907 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
908 const char **errmsg ATTRIBUTE_UNUSED
)
910 if (value
>= 8 && value
< 24)
911 return insn
| (((value
- 8) & 0xf) << 4);
914 *errmsg
= _("invalid register");
920 extract_ary (unsigned long insn
,
921 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
922 int *invalid ATTRIBUTE_UNUSED
)
924 return ((insn
>> 4) & 0xf) + 8;
928 insert_rx (unsigned long insn
,
930 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
933 if (value
>= 0 && value
< 8)
935 else if (value
>= 24 && value
<= 31)
936 return insn
| (value
- 16);
939 *errmsg
= _("invalid register");
945 extract_rx (unsigned long insn
,
946 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
947 int *invalid ATTRIBUTE_UNUSED
)
949 int value
= insn
& 0xf;
950 if (value
>= 0 && value
< 8)
957 insert_ry (unsigned long insn
,
959 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
962 if (value
>= 0 && value
< 8)
963 return insn
| (value
<< 4);
964 else if (value
>= 24 && value
<= 31)
965 return insn
| ((value
- 16) << 4);
968 *errmsg
= _("invalid register");
974 extract_ry (unsigned long insn
,
975 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
976 int *invalid ATTRIBUTE_UNUSED
)
978 int value
= (insn
>> 4) & 0xf;
979 if (value
>= 0 && value
< 8)
985 /* The BA field in an XL form instruction when it must be the same as
986 the BT field in the same instruction. This operand is marked FAKE.
987 The insertion function just copies the BT field into the BA field,
988 and the extraction function just checks that the fields are the
992 insert_bat (unsigned long insn
,
993 long value ATTRIBUTE_UNUSED
,
994 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
995 const char **errmsg ATTRIBUTE_UNUSED
)
997 return insn
| (((insn
>> 21) & 0x1f) << 16);
1001 extract_bat (unsigned long insn
,
1002 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1005 if (((insn
>> 21) & 0x1f) != ((insn
>> 16) & 0x1f))
1010 /* The BB field in an XL form instruction when it must be the same as
1011 the BA field in the same instruction. This operand is marked FAKE.
1012 The insertion function just copies the BA field into the BB field,
1013 and the extraction function just checks that the fields are the
1016 static unsigned long
1017 insert_bba (unsigned long insn
,
1018 long value ATTRIBUTE_UNUSED
,
1019 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1020 const char **errmsg ATTRIBUTE_UNUSED
)
1022 return insn
| (((insn
>> 16) & 0x1f) << 11);
1026 extract_bba (unsigned long insn
,
1027 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1030 if (((insn
>> 16) & 0x1f) != ((insn
>> 11) & 0x1f))
1035 /* The BD field in a B form instruction when the - modifier is used.
1036 This modifier means that the branch is not expected to be taken.
1037 For chips built to versions of the architecture prior to version 2
1038 (ie. not Power4 compatible), we set the y bit of the BO field to 1
1039 if the offset is negative. When extracting, we require that the y
1040 bit be 1 and that the offset be positive, since if the y bit is 0
1041 we just want to print the normal form of the instruction.
1042 Power4 compatible targets use two bits, "a", and "t", instead of
1043 the "y" bit. "at" == 00 => no hint, "at" == 01 => unpredictable,
1044 "at" == 10 => not taken, "at" == 11 => taken. The "t" bit is 00001
1045 in BO field, the "a" bit is 00010 for branch on CR(BI) and 01000
1046 for branch on CTR. We only handle the taken/not-taken hint here.
1047 Note that we don't relax the conditions tested here when
1048 disassembling with -Many because insns using extract_bdm and
1049 extract_bdp always occur in pairs. One or the other will always
1052 #define ISA_V2 (PPC_OPCODE_POWER4 | PPC_OPCODE_E500MC | PPC_OPCODE_TITAN)
1054 static unsigned long
1055 insert_bdm (unsigned long insn
,
1058 const char **errmsg ATTRIBUTE_UNUSED
)
1060 if ((dialect
& ISA_V2
) == 0)
1062 if ((value
& 0x8000) != 0)
1067 if ((insn
& (0x14 << 21)) == (0x04 << 21))
1069 else if ((insn
& (0x14 << 21)) == (0x10 << 21))
1072 return insn
| (value
& 0xfffc);
1076 extract_bdm (unsigned long insn
,
1080 if ((dialect
& ISA_V2
) == 0)
1082 if (((insn
& (1 << 21)) == 0) != ((insn
& (1 << 15)) == 0))
1087 if ((insn
& (0x17 << 21)) != (0x06 << 21)
1088 && (insn
& (0x1d << 21)) != (0x18 << 21))
1092 return ((insn
& 0xfffc) ^ 0x8000) - 0x8000;
1095 /* The BD field in a B form instruction when the + modifier is used.
1096 This is like BDM, above, except that the branch is expected to be
1099 static unsigned long
1100 insert_bdp (unsigned long insn
,
1103 const char **errmsg ATTRIBUTE_UNUSED
)
1105 if ((dialect
& ISA_V2
) == 0)
1107 if ((value
& 0x8000) == 0)
1112 if ((insn
& (0x14 << 21)) == (0x04 << 21))
1114 else if ((insn
& (0x14 << 21)) == (0x10 << 21))
1117 return insn
| (value
& 0xfffc);
1121 extract_bdp (unsigned long insn
,
1125 if ((dialect
& ISA_V2
) == 0)
1127 if (((insn
& (1 << 21)) == 0) == ((insn
& (1 << 15)) == 0))
1132 if ((insn
& (0x17 << 21)) != (0x07 << 21)
1133 && (insn
& (0x1d << 21)) != (0x19 << 21))
1137 return ((insn
& 0xfffc) ^ 0x8000) - 0x8000;
1141 valid_bo_pre_v2 (long value
)
1143 /* Certain encodings have bits that are required to be zero.
1144 These are (z must be zero, y may be anything):
1155 if ((value
& 0x14) == 0)
1157 else if ((value
& 0x14) == 0x4)
1158 return (value
& 0x2) == 0;
1159 else if ((value
& 0x14) == 0x10)
1160 return (value
& 0x8) == 0;
1162 return value
== 0x14;
1166 valid_bo_post_v2 (long value
)
1168 /* Certain encodings have bits that are required to be zero.
1169 These are (z must be zero, a & t may be anything):
1180 if ((value
& 0x14) == 0)
1181 return (value
& 0x1) == 0;
1182 else if ((value
& 0x14) == 0x14)
1183 return value
== 0x14;
1188 /* Check for legal values of a BO field. */
1191 valid_bo (long value
, ppc_cpu_t dialect
, int extract
)
1193 int valid_y
= valid_bo_pre_v2 (value
);
1194 int valid_at
= valid_bo_post_v2 (value
);
1196 /* When disassembling with -Many, accept either encoding on the
1197 second pass through opcodes. */
1198 if (extract
&& dialect
== ~(ppc_cpu_t
) PPC_OPCODE_ANY
)
1199 return valid_y
|| valid_at
;
1200 if ((dialect
& ISA_V2
) == 0)
1206 /* The BO field in a B form instruction. Warn about attempts to set
1207 the field to an illegal value. */
1209 static unsigned long
1210 insert_bo (unsigned long insn
,
1213 const char **errmsg
)
1215 if (!valid_bo (value
, dialect
, 0))
1216 *errmsg
= _("invalid conditional option");
1217 else if (PPC_OP (insn
) == 19 && (insn
& 0x400) && ! (value
& 4))
1218 *errmsg
= _("invalid counter access");
1219 return insn
| ((value
& 0x1f) << 21);
1223 extract_bo (unsigned long insn
,
1229 value
= (insn
>> 21) & 0x1f;
1230 if (!valid_bo (value
, dialect
, 1))
1235 /* The BO field in a B form instruction when the + or - modifier is
1236 used. This is like the BO field, but it must be even. When
1237 extracting it, we force it to be even. */
1239 static unsigned long
1240 insert_boe (unsigned long insn
,
1243 const char **errmsg
)
1245 if (!valid_bo (value
, dialect
, 0))
1246 *errmsg
= _("invalid conditional option");
1247 else if (PPC_OP (insn
) == 19 && (insn
& 0x400) && ! (value
& 4))
1248 *errmsg
= _("invalid counter access");
1249 else if ((value
& 1) != 0)
1250 *errmsg
= _("attempt to set y bit when using + or - modifier");
1252 return insn
| ((value
& 0x1f) << 21);
1256 extract_boe (unsigned long insn
,
1262 value
= (insn
>> 21) & 0x1f;
1263 if (!valid_bo (value
, dialect
, 1))
1265 return value
& 0x1e;
1268 /* FXM mask in mfcr and mtcrf instructions. */
1270 static unsigned long
1271 insert_fxm (unsigned long insn
,
1274 const char **errmsg
)
1276 /* If we're handling the mfocrf and mtocrf insns ensure that exactly
1277 one bit of the mask field is set. */
1278 if ((insn
& (1 << 20)) != 0)
1280 if (value
== 0 || (value
& -value
) != value
)
1282 *errmsg
= _("invalid mask field");
1287 /* If the optional field on mfcr is missing that means we want to use
1288 the old form of the instruction that moves the whole cr. In that
1289 case we'll have VALUE zero. There doesn't seem to be a way to
1290 distinguish this from the case where someone writes mfcr %r3,0. */
1291 else if (value
== 0)
1294 /* If only one bit of the FXM field is set, we can use the new form
1295 of the instruction, which is faster. Unlike the Power4 branch hint
1296 encoding, this is not backward compatible. Do not generate the
1297 new form unless -mpower4 has been given, or -many and the two
1298 operand form of mfcr was used. */
1299 else if ((value
& -value
) == value
1300 && ((dialect
& PPC_OPCODE_POWER4
) != 0
1301 || ((dialect
& PPC_OPCODE_ANY
) != 0
1302 && (insn
& (0x3ff << 1)) == 19 << 1)))
1305 /* Any other value on mfcr is an error. */
1306 else if ((insn
& (0x3ff << 1)) == 19 << 1)
1308 *errmsg
= _("ignoring invalid mfcr mask");
1312 return insn
| ((value
& 0xff) << 12);
1316 extract_fxm (unsigned long insn
,
1317 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1320 long mask
= (insn
>> 12) & 0xff;
1322 /* Is this a Power4 insn? */
1323 if ((insn
& (1 << 20)) != 0)
1325 /* Exactly one bit of MASK should be set. */
1326 if (mask
== 0 || (mask
& -mask
) != mask
)
1330 /* Check that non-power4 form of mfcr has a zero MASK. */
1331 else if ((insn
& (0x3ff << 1)) == 19 << 1)
1340 static unsigned long
1341 insert_li20 (unsigned long insn
,
1343 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1344 const char **errmsg ATTRIBUTE_UNUSED
)
1346 return insn
| ((value
& 0xf0000) >> 5) | ((value
& 0x0f800) << 5) | (value
& 0x7ff);
1350 extract_li20 (unsigned long insn
,
1351 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1352 int *invalid ATTRIBUTE_UNUSED
)
1354 long ext
= ((insn
& 0x4000) == 0x4000) ? 0xfff00000 : 0x00000000;
1357 | (((insn
>> 11) & 0xf) << 16)
1358 | (((insn
>> 17) & 0xf) << 12)
1359 | (((insn
>> 16) & 0x1) << 11)
1363 /* The LS field in a sync instruction that accepts 2 operands
1364 Values 2 and 3 are reserved,
1365 must be treated as 0 for future compatibility
1366 Values 0 and 1 can be accepted, if field ESYNC is zero
1367 Otherwise L = complement of ESYNC-bit2 (1<<18) */
1369 static unsigned long
1370 insert_ls (unsigned long insn
,
1372 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1373 const char **errmsg ATTRIBUTE_UNUSED
)
1377 ls
= (insn
>> 21) & 0x03;
1381 return insn
& ~(0x3 << 21);
1384 if ((value
& 0x2) != 0)
1385 return (insn
& ~(0x3 << 21)) | ((value
& 0xf) << 16);
1386 return (insn
& ~(0x3 << 21)) | (0x1 << 21) | ((value
& 0xf) << 16);
1389 /* The MB and ME fields in an M form instruction expressed as a single
1390 operand which is itself a bitmask. The extraction function always
1391 marks it as invalid, since we never want to recognize an
1392 instruction which uses a field of this type. */
1394 static unsigned long
1395 insert_mbe (unsigned long insn
,
1397 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1398 const char **errmsg
)
1400 unsigned long uval
, mask
;
1401 int mb
, me
, mx
, count
, last
;
1407 *errmsg
= _("illegal bitmask");
1413 if ((uval
& 1) != 0)
1419 /* mb: location of last 0->1 transition */
1420 /* me: location of last 1->0 transition */
1421 /* count: # transitions */
1423 for (mx
= 0, mask
= 1L << 31; mx
< 32; ++mx
, mask
>>= 1)
1425 if ((uval
& mask
) && !last
)
1431 else if (!(uval
& mask
) && last
)
1441 if (count
!= 2 && (count
!= 0 || ! last
))
1442 *errmsg
= _("illegal bitmask");
1444 return insn
| (mb
<< 6) | ((me
- 1) << 1);
1448 extract_mbe (unsigned long insn
,
1449 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1458 mb
= (insn
>> 6) & 0x1f;
1459 me
= (insn
>> 1) & 0x1f;
1463 for (i
= mb
; i
<= me
; i
++)
1464 ret
|= 1L << (31 - i
);
1466 else if (mb
== me
+ 1)
1468 else /* (mb > me + 1) */
1471 for (i
= me
+ 1; i
< mb
; i
++)
1472 ret
&= ~(1L << (31 - i
));
1477 /* The MB or ME field in an MD or MDS form instruction. The high bit
1478 is wrapped to the low end. */
1480 static unsigned long
1481 insert_mb6 (unsigned long insn
,
1483 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1484 const char **errmsg ATTRIBUTE_UNUSED
)
1486 return insn
| ((value
& 0x1f) << 6) | (value
& 0x20);
1490 extract_mb6 (unsigned long insn
,
1491 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1492 int *invalid ATTRIBUTE_UNUSED
)
1494 return ((insn
>> 6) & 0x1f) | (insn
& 0x20);
1497 /* The NB field in an X form instruction. The value 32 is stored as
1501 extract_nb (unsigned long insn
,
1502 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1503 int *invalid ATTRIBUTE_UNUSED
)
1507 ret
= (insn
>> 11) & 0x1f;
1513 /* The NB field in an lswi instruction, which has special value
1514 restrictions. The value 32 is stored as 0. */
1516 static unsigned long
1517 insert_nbi (unsigned long insn
,
1519 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1520 const char **errmsg ATTRIBUTE_UNUSED
)
1522 long rtvalue
= (insn
& RT_MASK
) >> 21;
1523 long ravalue
= (insn
& RA_MASK
) >> 16;
1527 if (rtvalue
+ (value
+ 3) / 4 > (rtvalue
> ravalue
? ravalue
+ 32
1529 *errmsg
= _("address register in load range");
1530 return insn
| ((value
& 0x1f) << 11);
1533 /* The NSI field in a D form instruction. This is the same as the SI
1534 field, only negated. The extraction function always marks it as
1535 invalid, since we never want to recognize an instruction which uses
1536 a field of this type. */
1538 static unsigned long
1539 insert_nsi (unsigned long insn
,
1541 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1542 const char **errmsg ATTRIBUTE_UNUSED
)
1544 return insn
| (-value
& 0xffff);
1548 extract_nsi (unsigned long insn
,
1549 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1553 return -(((insn
& 0xffff) ^ 0x8000) - 0x8000);
1556 /* The RA field in a D or X form instruction which is an updating
1557 load, which means that the RA field may not be zero and may not
1558 equal the RT field. */
1560 static unsigned long
1561 insert_ral (unsigned long insn
,
1563 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1564 const char **errmsg
)
1567 || (unsigned long) value
== ((insn
>> 21) & 0x1f))
1568 *errmsg
= "invalid register operand when updating";
1569 return insn
| ((value
& 0x1f) << 16);
1572 /* The RA field in an lmw instruction, which has special value
1575 static unsigned long
1576 insert_ram (unsigned long insn
,
1578 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1579 const char **errmsg
)
1581 if ((unsigned long) value
>= ((insn
>> 21) & 0x1f))
1582 *errmsg
= _("index register in load range");
1583 return insn
| ((value
& 0x1f) << 16);
1586 /* The RA field in the DQ form lq or an lswx instruction, which have special
1587 value restrictions. */
1589 static unsigned long
1590 insert_raq (unsigned long insn
,
1592 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1593 const char **errmsg
)
1595 long rtvalue
= (insn
& RT_MASK
) >> 21;
1597 if (value
== rtvalue
)
1598 *errmsg
= _("source and target register operands must be different");
1599 return insn
| ((value
& 0x1f) << 16);
1602 /* The RA field in a D or X form instruction which is an updating
1603 store or an updating floating point load, which means that the RA
1604 field may not be zero. */
1606 static unsigned long
1607 insert_ras (unsigned long insn
,
1609 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1610 const char **errmsg
)
1613 *errmsg
= _("invalid register operand when updating");
1614 return insn
| ((value
& 0x1f) << 16);
1617 /* The RB field in an X form instruction when it must be the same as
1618 the RS field in the instruction. This is used for extended
1619 mnemonics like mr. This operand is marked FAKE. The insertion
1620 function just copies the BT field into the BA field, and the
1621 extraction function just checks that the fields are the same. */
1623 static unsigned long
1624 insert_rbs (unsigned long insn
,
1625 long value ATTRIBUTE_UNUSED
,
1626 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1627 const char **errmsg ATTRIBUTE_UNUSED
)
1629 return insn
| (((insn
>> 21) & 0x1f) << 11);
1633 extract_rbs (unsigned long insn
,
1634 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1637 if (((insn
>> 21) & 0x1f) != ((insn
>> 11) & 0x1f))
1642 /* The RB field in an lswx instruction, which has special value
1645 static unsigned long
1646 insert_rbx (unsigned long insn
,
1648 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1649 const char **errmsg
)
1651 long rtvalue
= (insn
& RT_MASK
) >> 21;
1653 if (value
== rtvalue
)
1654 *errmsg
= _("source and target register operands must be different");
1655 return insn
| ((value
& 0x1f) << 11);
1658 /* The SCI8 field is made up of SCL and {U,N}I8 fields. */
1659 static unsigned long
1660 insert_sci8 (unsigned long insn
,
1662 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1663 const char **errmsg
)
1665 unsigned int fill_scale
= 0;
1666 unsigned long ui8
= value
;
1668 if ((ui8
& 0xffffff00) == 0)
1670 else if ((ui8
& 0xffffff00) == 0xffffff00)
1672 else if ((ui8
& 0xffff00ff) == 0)
1674 fill_scale
= 1 << 8;
1677 else if ((ui8
& 0xffff00ff) == 0xffff00ff)
1679 fill_scale
= 0x400 | (1 << 8);
1682 else if ((ui8
& 0xff00ffff) == 0)
1684 fill_scale
= 2 << 8;
1687 else if ((ui8
& 0xff00ffff) == 0xff00ffff)
1689 fill_scale
= 0x400 | (2 << 8);
1692 else if ((ui8
& 0x00ffffff) == 0)
1694 fill_scale
= 3 << 8;
1697 else if ((ui8
& 0x00ffffff) == 0x00ffffff)
1699 fill_scale
= 0x400 | (3 << 8);
1704 *errmsg
= _("illegal immediate value");
1708 return insn
| fill_scale
| (ui8
& 0xff);
1712 extract_sci8 (unsigned long insn
,
1713 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1714 int *invalid ATTRIBUTE_UNUSED
)
1716 int fill
= insn
& 0x400;
1717 int scale_factor
= (insn
& 0x300) >> 5;
1718 long value
= (insn
& 0xff) << scale_factor
;
1721 value
|= ~((long) 0xff << scale_factor
);
1725 static unsigned long
1726 insert_sci8n (unsigned long insn
,
1729 const char **errmsg
)
1731 return insert_sci8 (insn
, -value
, dialect
, errmsg
);
1735 extract_sci8n (unsigned long insn
,
1739 return -extract_sci8 (insn
, dialect
, invalid
);
1742 static unsigned long
1743 insert_sd4h (unsigned long insn
,
1745 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1746 const char **errmsg ATTRIBUTE_UNUSED
)
1748 return insn
| ((value
& 0x1e) << 7);
1752 extract_sd4h (unsigned long insn
,
1753 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1754 int *invalid ATTRIBUTE_UNUSED
)
1756 return ((insn
>> 8) & 0xf) << 1;
1759 static unsigned long
1760 insert_sd4w (unsigned long insn
,
1762 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1763 const char **errmsg ATTRIBUTE_UNUSED
)
1765 return insn
| ((value
& 0x3c) << 6);
1769 extract_sd4w (unsigned long insn
,
1770 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1771 int *invalid ATTRIBUTE_UNUSED
)
1773 return ((insn
>> 8) & 0xf) << 2;
1776 static unsigned long
1777 insert_oimm (unsigned long insn
,
1779 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1780 const char **errmsg ATTRIBUTE_UNUSED
)
1782 return insn
| (((value
- 1) & 0x1f) << 4);
1786 extract_oimm (unsigned long insn
,
1787 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1788 int *invalid ATTRIBUTE_UNUSED
)
1790 return ((insn
>> 4) & 0x1f) + 1;
1793 /* The SH field in an MD form instruction. This is split. */
1795 static unsigned long
1796 insert_sh6 (unsigned long insn
,
1798 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1799 const char **errmsg ATTRIBUTE_UNUSED
)
1801 return insn
| ((value
& 0x1f) << 11) | ((value
& 0x20) >> 4);
1805 extract_sh6 (unsigned long insn
,
1806 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1807 int *invalid ATTRIBUTE_UNUSED
)
1809 return ((insn
>> 11) & 0x1f) | ((insn
<< 4) & 0x20);
1812 /* The SPR field in an XFX form instruction. This is flipped--the
1813 lower 5 bits are stored in the upper 5 and vice- versa. */
1815 static unsigned long
1816 insert_spr (unsigned long insn
,
1818 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1819 const char **errmsg ATTRIBUTE_UNUSED
)
1821 return insn
| ((value
& 0x1f) << 16) | ((value
& 0x3e0) << 6);
1825 extract_spr (unsigned long insn
,
1826 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1827 int *invalid ATTRIBUTE_UNUSED
)
1829 return ((insn
>> 16) & 0x1f) | ((insn
>> 6) & 0x3e0);
1832 /* Some dialects have 8 SPRG registers instead of the standard 4. */
1833 #define ALLOW8_SPRG (PPC_OPCODE_BOOKE | PPC_OPCODE_405 | PPC_OPCODE_VLE)
1835 static unsigned long
1836 insert_sprg (unsigned long insn
,
1839 const char **errmsg
)
1842 || (value
> 3 && (dialect
& ALLOW8_SPRG
) == 0))
1843 *errmsg
= _("invalid sprg number");
1845 /* If this is mfsprg4..7 then use spr 260..263 which can be read in
1846 user mode. Anything else must use spr 272..279. */
1847 if (value
<= 3 || (insn
& 0x100) != 0)
1850 return insn
| ((value
& 0x17) << 16);
1854 extract_sprg (unsigned long insn
,
1858 unsigned long val
= (insn
>> 16) & 0x1f;
1860 /* mfsprg can use 260..263 and 272..279. mtsprg only uses spr 272..279
1861 If not BOOKE, 405 or VLE, then both use only 272..275. */
1862 if ((val
- 0x10 > 3 && (dialect
& ALLOW8_SPRG
) == 0)
1863 || (val
- 0x10 > 7 && (insn
& 0x100) != 0)
1870 /* The TBR field in an XFX instruction. This is just like SPR, but it
1871 is optional. When TBR is omitted, it must be inserted as 268 (the
1872 magic number of the TB register). These functions treat 0
1873 (indicating an omitted optional operand) as 268. This means that
1874 ``mftb 4,0'' is not handled correctly. This does not matter very
1875 much, since the architecture manual does not define mftb as
1876 accepting any values other than 268 or 269. */
1878 static unsigned long
1879 insert_tbr (unsigned long insn
,
1881 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1882 const char **errmsg
)
1886 if (value
!= 268 && value
!= 269)
1887 *errmsg
= _("invalid tbr number");
1888 return insn
| ((value
& 0x1f) << 16) | ((value
& 0x3e0) << 6);
1892 extract_tbr (unsigned long insn
,
1893 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1898 ret
= ((insn
>> 16) & 0x1f) | ((insn
>> 6) & 0x3e0);
1899 if (ret
!= 268 && ret
!= 269)
1906 /* The XT and XS fields in an XX1 or XX3 form instruction. This is split. */
1908 static unsigned long
1909 insert_xt6 (unsigned long insn
,
1911 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1912 const char **errmsg ATTRIBUTE_UNUSED
)
1914 return insn
| ((value
& 0x1f) << 21) | ((value
& 0x20) >> 5);
1918 extract_xt6 (unsigned long insn
,
1919 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1920 int *invalid ATTRIBUTE_UNUSED
)
1922 return ((insn
<< 5) & 0x20) | ((insn
>> 21) & 0x1f);
1925 /* The XA field in an XX3 form instruction. This is split. */
1927 static unsigned long
1928 insert_xa6 (unsigned long insn
,
1930 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1931 const char **errmsg ATTRIBUTE_UNUSED
)
1933 return insn
| ((value
& 0x1f) << 16) | ((value
& 0x20) >> 3);
1937 extract_xa6 (unsigned long insn
,
1938 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1939 int *invalid ATTRIBUTE_UNUSED
)
1941 return ((insn
<< 3) & 0x20) | ((insn
>> 16) & 0x1f);
1944 /* The XB field in an XX3 form instruction. This is split. */
1946 static unsigned long
1947 insert_xb6 (unsigned long insn
,
1949 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1950 const char **errmsg ATTRIBUTE_UNUSED
)
1952 return insn
| ((value
& 0x1f) << 11) | ((value
& 0x20) >> 4);
1956 extract_xb6 (unsigned long insn
,
1957 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1958 int *invalid ATTRIBUTE_UNUSED
)
1960 return ((insn
<< 4) & 0x20) | ((insn
>> 11) & 0x1f);
1963 /* The XB field in an XX3 form instruction when it must be the same as
1964 the XA field in the instruction. This is used for extended
1965 mnemonics like xvmovdp. This operand is marked FAKE. The insertion
1966 function just copies the XA field into the XB field, and the
1967 extraction function just checks that the fields are the same. */
1969 static unsigned long
1970 insert_xb6s (unsigned long insn
,
1971 long value ATTRIBUTE_UNUSED
,
1972 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1973 const char **errmsg ATTRIBUTE_UNUSED
)
1975 return insn
| (((insn
>> 16) & 0x1f) << 11) | (((insn
>> 2) & 0x1) << 1);
1979 extract_xb6s (unsigned long insn
,
1980 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1983 if ((((insn
>> 16) & 0x1f) != ((insn
>> 11) & 0x1f))
1984 || (((insn
>> 2) & 0x1) != ((insn
>> 1) & 0x1)))
1989 /* The XC field in an XX4 form instruction. This is split. */
1991 static unsigned long
1992 insert_xc6 (unsigned long insn
,
1994 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1995 const char **errmsg ATTRIBUTE_UNUSED
)
1997 return insn
| ((value
& 0x1f) << 6) | ((value
& 0x20) >> 2);
2001 extract_xc6 (unsigned long insn
,
2002 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
2003 int *invalid ATTRIBUTE_UNUSED
)
2005 return ((insn
<< 2) & 0x20) | ((insn
>> 6) & 0x1f);
2008 static unsigned long
2009 insert_dm (unsigned long insn
,
2011 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
2012 const char **errmsg
)
2014 if (value
!= 0 && value
!= 1)
2015 *errmsg
= _("invalid constant");
2016 return insn
| (((value
) ? 3 : 0) << 8);
2020 extract_dm (unsigned long insn
,
2021 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
2026 value
= (insn
>> 8) & 3;
2027 if (value
!= 0 && value
!= 3)
2029 return (value
) ? 1 : 0;
2031 /* The VLESIMM field in an I16A form instruction. This is split. */
2033 static unsigned long
2034 insert_vlesi (unsigned long insn
,
2036 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
2037 const char **errmsg ATTRIBUTE_UNUSED
)
2039 return insn
| ((value
& 0xf800) << 10) | (value
& 0x7ff);
2043 extract_vlesi (unsigned long insn
,
2044 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
2045 int *invalid ATTRIBUTE_UNUSED
)
2047 long value
= ((insn
>> 10) & 0xf800) | (insn
& 0x7ff);
2048 value
= (value
^ 0x8000) - 0x8000;
2052 static unsigned long
2053 insert_vlensi (unsigned long insn
,
2055 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
2056 const char **errmsg ATTRIBUTE_UNUSED
)
2059 return insn
| ((value
& 0xf800) << 10) | (value
& 0x7ff);
2062 extract_vlensi (unsigned long insn
,
2063 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
2064 int *invalid ATTRIBUTE_UNUSED
)
2066 long value
= ((insn
>> 10) & 0xf800) | (insn
& 0x7ff);
2067 value
= (value
^ 0x8000) - 0x8000;
2068 /* Don't use for disassembly. */
2073 /* The VLEUIMM field in an I16A form instruction. This is split. */
2075 static unsigned long
2076 insert_vleui (unsigned long insn
,
2078 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
2079 const char **errmsg ATTRIBUTE_UNUSED
)
2081 return insn
| ((value
& 0xf800) << 10) | (value
& 0x7ff);
2085 extract_vleui (unsigned long insn
,
2086 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
2087 int *invalid ATTRIBUTE_UNUSED
)
2089 return ((insn
>> 10) & 0xf800) | (insn
& 0x7ff);
2092 /* The VLEUIMML field in an I16L form instruction. This is split. */
2094 static unsigned long
2095 insert_vleil (unsigned long insn
,
2097 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
2098 const char **errmsg ATTRIBUTE_UNUSED
)
2100 return insn
| ((value
& 0xf800) << 5) | (value
& 0x7ff);
2104 extract_vleil (unsigned long insn
,
2105 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
2106 int *invalid ATTRIBUTE_UNUSED
)
2108 return ((insn
>> 5) & 0xf800) | (insn
& 0x7ff);
2112 /* Macros used to form opcodes. */
2114 /* The main opcode. */
2115 #define OP(x) ((((unsigned long)(x)) & 0x3f) << 26)
2116 #define OP_MASK OP (0x3f)
2118 /* The main opcode combined with a trap code in the TO field of a D
2119 form instruction. Used for extended mnemonics for the trap
2121 #define OPTO(x,to) (OP (x) | ((((unsigned long)(to)) & 0x1f) << 21))
2122 #define OPTO_MASK (OP_MASK | TO_MASK)
2124 /* The main opcode combined with a comparison size bit in the L field
2125 of a D form or X form instruction. Used for extended mnemonics for
2126 the comparison instructions. */
2127 #define OPL(x,l) (OP (x) | ((((unsigned long)(l)) & 1) << 21))
2128 #define OPL_MASK OPL (0x3f,1)
2130 /* The main opcode combined with an update code in D form instruction.
2131 Used for extended mnemonics for VLE memory instructions. */
2132 #define OPVUP(x,vup) (OP (x) | ((((unsigned long)(vup)) & 0xff) << 8))
2133 #define OPVUP_MASK OPVUP (0x3f, 0xff)
2135 /* An A form instruction. */
2136 #define A(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0x1f) << 1) | (((unsigned long)(rc)) & 1))
2137 #define A_MASK A (0x3f, 0x1f, 1)
2139 /* An A_MASK with the FRB field fixed. */
2140 #define AFRB_MASK (A_MASK | FRB_MASK)
2142 /* An A_MASK with the FRC field fixed. */
2143 #define AFRC_MASK (A_MASK | FRC_MASK)
2145 /* An A_MASK with the FRA and FRC fields fixed. */
2146 #define AFRAFRC_MASK (A_MASK | FRA_MASK | FRC_MASK)
2148 /* An AFRAFRC_MASK, but with L bit clear. */
2149 #define AFRALFRC_MASK (AFRAFRC_MASK & ~((unsigned long) 1 << 16))
2151 /* A B form instruction. */
2152 #define B(op, aa, lk) (OP (op) | ((((unsigned long)(aa)) & 1) << 1) | ((lk) & 1))
2153 #define B_MASK B (0x3f, 1, 1)
2155 /* A BD8 form instruction. This is a 16-bit instruction. */
2156 #define BD8(op, aa, lk) (((((unsigned long)(op)) & 0x3f) << 10) | (((aa) & 1) << 9) | (((lk) & 1) << 8))
2157 #define BD8_MASK BD8 (0x3f, 1, 1)
2159 /* Another BD8 form instruction. This is a 16-bit instruction. */
2160 #define BD8IO(op) ((((unsigned long)(op)) & 0x1f) << 11)
2161 #define BD8IO_MASK BD8IO (0x1f)
2163 /* A BD8 form instruction for simplified mnemonics. */
2164 #define EBD8IO(op, bo, bi) (BD8IO ((op)) | ((bo) << 10) | ((bi) << 8))
2165 /* A mask that excludes BO32 and BI32. */
2166 #define EBD8IO1_MASK 0xf800
2167 /* A mask that includes BO32 and excludes BI32. */
2168 #define EBD8IO2_MASK 0xfc00
2169 /* A mask that include BO32 AND BI32. */
2170 #define EBD8IO3_MASK 0xff00
2172 /* A BD15 form instruction. */
2173 #define BD15(op, aa, lk) (OP (op) | ((((unsigned long)(aa)) & 0xf) << 22) | ((lk) & 1))
2174 #define BD15_MASK BD15 (0x3f, 0xf, 1)
2176 /* A BD15 form instruction for extended conditional branch mnemonics. */
2177 #define EBD15(op, aa, bo, lk) (((op) & 0x3f) << 26) | (((aa) & 0xf) << 22) | (((bo) & 0x3) << 20) | ((lk) & 1)
2178 #define EBD15_MASK 0xfff00001
2180 /* A BD15 form instruction for extended conditional branch mnemonics with BI. */
2181 #define EBD15BI(op, aa, bo, bi, lk) (((op) & 0x3f) << 26) \
2182 | (((aa) & 0xf) << 22) \
2183 | (((bo) & 0x3) << 20) \
2184 | (((bi) & 0x3) << 16) \
2186 #define EBD15BI_MASK 0xfff30001
2188 /* A BD24 form instruction. */
2189 #define BD24(op, aa, lk) (OP (op) | ((((unsigned long)(aa)) & 1) << 25) | ((lk) & 1))
2190 #define BD24_MASK BD24 (0x3f, 1, 1)
2192 /* A B form instruction setting the BO field. */
2193 #define BBO(op, bo, aa, lk) (B ((op), (aa), (lk)) | ((((unsigned long)(bo)) & 0x1f) << 21))
2194 #define BBO_MASK BBO (0x3f, 0x1f, 1, 1)
2196 /* A BBO_MASK with the y bit of the BO field removed. This permits
2197 matching a conditional branch regardless of the setting of the y
2198 bit. Similarly for the 'at' bits used for power4 branch hints. */
2199 #define Y_MASK (((unsigned long) 1) << 21)
2200 #define AT1_MASK (((unsigned long) 3) << 21)
2201 #define AT2_MASK (((unsigned long) 9) << 21)
2202 #define BBOY_MASK (BBO_MASK &~ Y_MASK)
2203 #define BBOAT_MASK (BBO_MASK &~ AT1_MASK)
2205 /* A B form instruction setting the BO field and the condition bits of
2207 #define BBOCB(op, bo, cb, aa, lk) \
2208 (BBO ((op), (bo), (aa), (lk)) | ((((unsigned long)(cb)) & 0x3) << 16))
2209 #define BBOCB_MASK BBOCB (0x3f, 0x1f, 0x3, 1, 1)
2211 /* A BBOCB_MASK with the y bit of the BO field removed. */
2212 #define BBOYCB_MASK (BBOCB_MASK &~ Y_MASK)
2213 #define BBOATCB_MASK (BBOCB_MASK &~ AT1_MASK)
2214 #define BBOAT2CB_MASK (BBOCB_MASK &~ AT2_MASK)
2216 /* A BBOYCB_MASK in which the BI field is fixed. */
2217 #define BBOYBI_MASK (BBOYCB_MASK | BI_MASK)
2218 #define BBOATBI_MASK (BBOAT2CB_MASK | BI_MASK)
2220 /* A VLE C form instruction. */
2221 #define C_LK(x, lk) (((((unsigned long)(x)) & 0x7fff) << 1) | ((lk) & 1))
2222 #define C_LK_MASK C_LK(0x7fff, 1)
2223 #define C(x) ((((unsigned long)(x)) & 0xffff))
2224 #define C_MASK C(0xffff)
2226 /* An Context form instruction. */
2227 #define CTX(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x7))
2228 #define CTX_MASK CTX(0x3f, 0x7)
2230 /* An User Context form instruction. */
2231 #define UCTX(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x1f))
2232 #define UCTX_MASK UCTX(0x3f, 0x1f)
2234 /* The main opcode mask with the RA field clear. */
2235 #define DRA_MASK (OP_MASK | RA_MASK)
2237 /* A DS form instruction. */
2238 #define DSO(op, xop) (OP (op) | ((xop) & 0x3))
2239 #define DS_MASK DSO (0x3f, 3)
2241 /* An EVSEL form instruction. */
2242 #define EVSEL(op, xop) (OP (op) | (((unsigned long)(xop)) & 0xff) << 3)
2243 #define EVSEL_MASK EVSEL(0x3f, 0xff)
2245 /* An IA16 form instruction. */
2246 #define IA16(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x1f) << 11)
2247 #define IA16_MASK IA16(0x3f, 0x1f)
2249 /* An I16A form instruction. */
2250 #define I16A(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x1f) << 11)
2251 #define I16A_MASK I16A(0x3f, 0x1f)
2253 /* An I16L form instruction. */
2254 #define I16L(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x1f) << 11)
2255 #define I16L_MASK I16L(0x3f, 0x1f)
2257 /* An IM7 form instruction. */
2258 #define IM7(op) ((((unsigned long)(op)) & 0x1f) << 11)
2259 #define IM7_MASK IM7(0x1f)
2261 /* An M form instruction. */
2262 #define M(op, rc) (OP (op) | ((rc) & 1))
2263 #define M_MASK M (0x3f, 1)
2265 /* An LI20 form instruction. */
2266 #define LI20(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x1) << 15)
2267 #define LI20_MASK LI20(0x3f, 0x1)
2269 /* An M form instruction with the ME field specified. */
2270 #define MME(op, me, rc) (M ((op), (rc)) | ((((unsigned long)(me)) & 0x1f) << 1))
2272 /* An M_MASK with the MB and ME fields fixed. */
2273 #define MMBME_MASK (M_MASK | MB_MASK | ME_MASK)
2275 /* An M_MASK with the SH and ME fields fixed. */
2276 #define MSHME_MASK (M_MASK | SH_MASK | ME_MASK)
2278 /* An MD form instruction. */
2279 #define MD(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0x7) << 2) | ((rc) & 1))
2280 #define MD_MASK MD (0x3f, 0x7, 1)
2282 /* An MD_MASK with the MB field fixed. */
2283 #define MDMB_MASK (MD_MASK | MB6_MASK)
2285 /* An MD_MASK with the SH field fixed. */
2286 #define MDSH_MASK (MD_MASK | SH6_MASK)
2288 /* An MDS form instruction. */
2289 #define MDS(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0xf) << 1) | ((rc) & 1))
2290 #define MDS_MASK MDS (0x3f, 0xf, 1)
2292 /* An MDS_MASK with the MB field fixed. */
2293 #define MDSMB_MASK (MDS_MASK | MB6_MASK)
2295 /* An SC form instruction. */
2296 #define SC(op, sa, lk) (OP (op) | ((((unsigned long)(sa)) & 1) << 1) | ((lk) & 1))
2297 #define SC_MASK (OP_MASK | (((unsigned long)0x3ff) << 16) | (((unsigned long)1) << 1) | 1)
2299 /* An SCI8 form instruction. */
2300 #define SCI8(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x1f) << 11))
2301 #define SCI8_MASK SCI8(0x3f, 0x1f)
2303 /* An SCI8 form instruction. */
2304 #define SCI8BF(op, fop, xop) (OP (op) | ((((unsigned long)(xop)) & 0x1f) << 11) | (((fop) & 7) << 23))
2305 #define SCI8BF_MASK SCI8BF(0x3f, 7, 0x1f)
2307 /* An SD4 form instruction. This is a 16-bit instruction. */
2308 #define SD4(op) ((((unsigned long)(op)) & 0xf) << 12)
2309 #define SD4_MASK SD4(0xf)
2311 /* An SE_IM5 form instruction. This is a 16-bit instruction. */
2312 #define SE_IM5(op, xop) (((((unsigned long)(op)) & 0x3f) << 10) | (((xop) & 0x1) << 9))
2313 #define SE_IM5_MASK SE_IM5(0x3f, 1)
2315 /* An SE_R form instruction. This is a 16-bit instruction. */
2316 #define SE_R(op, xop) (((((unsigned long)(op)) & 0x3f) << 10) | (((xop) & 0x3f) << 4))
2317 #define SE_R_MASK SE_R(0x3f, 0x3f)
2319 /* An SE_RR form instruction. This is a 16-bit instruction. */
2320 #define SE_RR(op, xop) (((((unsigned long)(op)) & 0x3f) << 10) | (((xop) & 0x3) << 8))
2321 #define SE_RR_MASK SE_RR(0x3f, 3)
2323 /* A VX form instruction. */
2324 #define VX(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x7ff))
2326 /* The mask for an VX form instruction. */
2327 #define VX_MASK VX(0x3f, 0x7ff)
2329 /* A VX_MASK with the VA field fixed. */
2330 #define VXVA_MASK (VX_MASK | (0x1f << 16))
2332 /* A VX_MASK with the VB field fixed. */
2333 #define VXVB_MASK (VX_MASK | (0x1f << 11))
2335 /* A VX_MASK with the VA and VB fields fixed. */
2336 #define VXVAVB_MASK (VX_MASK | (0x1f << 16) | (0x1f << 11))
2338 /* A VX_MASK with the VD and VA fields fixed. */
2339 #define VXVDVA_MASK (VX_MASK | (0x1f << 21) | (0x1f << 16))
2341 /* A VX_MASK with a UIMM4 field. */
2342 #define VXUIMM4_MASK (VX_MASK | (0x1 << 20))
2344 /* A VX_MASK with a UIMM3 field. */
2345 #define VXUIMM3_MASK (VX_MASK | (0x3 << 19))
2347 /* A VX_MASK with a UIMM2 field. */
2348 #define VXUIMM2_MASK (VX_MASK | (0x7 << 18))
2350 /* A VX_MASK with a PS field. */
2351 #define VXPS_MASK (VX_MASK & ~(0x1 << 9))
2353 /* A VA form instruction. */
2354 #define VXA(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x03f))
2356 /* The mask for an VA form instruction. */
2357 #define VXA_MASK VXA(0x3f, 0x3f)
2359 /* A VXA_MASK with a SHB field. */
2360 #define VXASHB_MASK (VXA_MASK | (1 << 10))
2362 /* A VXR form instruction. */
2363 #define VXR(op, xop, rc) (OP (op) | (((rc) & 1) << 10) | (((unsigned long)(xop)) & 0x3ff))
2365 /* The mask for a VXR form instruction. */
2366 #define VXR_MASK VXR(0x3f, 0x3ff, 1)
2368 /* An X form instruction. */
2369 #define X(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x3ff) << 1))
2371 /* An EX form instruction. */
2372 #define EX(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x7ff))
2374 /* The mask for an EX form instruction. */
2375 #define EX_MASK EX (0x3f, 0x7ff)
2377 /* An XX2 form instruction. */
2378 #define XX2(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x1ff) << 2))
2380 /* An XX3 form instruction. */
2381 #define XX3(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0xff) << 3))
2383 /* An XX3 form instruction with the RC bit specified. */
2384 #define XX3RC(op, xop, rc) (OP (op) | (((rc) & 1) << 10) | ((((unsigned long)(xop)) & 0x7f) << 3))
2386 /* An XX4 form instruction. */
2387 #define XX4(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x3) << 4))
2389 /* A Z form instruction. */
2390 #define Z(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x1ff) << 1))
2392 /* An X form instruction with the RC bit specified. */
2393 #define XRC(op, xop, rc) (X ((op), (xop)) | ((rc) & 1))
2395 /* A Z form instruction with the RC bit specified. */
2396 #define ZRC(op, xop, rc) (Z ((op), (xop)) | ((rc) & 1))
2398 /* The mask for an X form instruction. */
2399 #define X_MASK XRC (0x3f, 0x3ff, 1)
2401 /* An X form wait instruction with everything filled in except the WC field. */
2402 #define XWC_MASK (XRC (0x3f, 0x3ff, 1) | (7 << 23) | RA_MASK | RB_MASK)
2404 /* The mask for an XX1 form instruction. */
2405 #define XX1_MASK X (0x3f, 0x3ff)
2407 /* An XX1_MASK with the RB field fixed. */
2408 #define XX1RB_MASK (XX1_MASK | RB_MASK)
2410 /* The mask for an XX2 form instruction. */
2411 #define XX2_MASK (XX2 (0x3f, 0x1ff) | (0x1f << 16))
2413 /* The mask for an XX2 form instruction with the UIM bits specified. */
2414 #define XX2UIM_MASK (XX2 (0x3f, 0x1ff) | (7 << 18))
2416 /* The mask for an XX2 form instruction with the BF bits specified. */
2417 #define XX2BF_MASK (XX2_MASK | (3 << 21) | (1))
2419 /* The mask for an XX3 form instruction. */
2420 #define XX3_MASK XX3 (0x3f, 0xff)
2422 /* The mask for an XX3 form instruction with the BF bits specified. */
2423 #define XX3BF_MASK (XX3 (0x3f, 0xff) | (3 << 21) | (1))
2425 /* The mask for an XX3 form instruction with the DM or SHW bits specified. */
2426 #define XX3DM_MASK (XX3 (0x3f, 0x1f) | (1 << 10))
2427 #define XX3SHW_MASK XX3DM_MASK
2429 /* The mask for an XX4 form instruction. */
2430 #define XX4_MASK XX4 (0x3f, 0x3)
2432 /* An X form wait instruction with everything filled in except the WC field. */
2433 #define XWC_MASK (XRC (0x3f, 0x3ff, 1) | (7 << 23) | RA_MASK | RB_MASK)
2435 /* The mask for a Z form instruction. */
2436 #define Z_MASK ZRC (0x3f, 0x1ff, 1)
2437 #define Z2_MASK ZRC (0x3f, 0xff, 1)
2439 /* An X_MASK with the RA field fixed. */
2440 #define XRA_MASK (X_MASK | RA_MASK)
2442 /* An XRA_MASK with the W field clear. */
2443 #define XWRA_MASK (XRA_MASK & ~((unsigned long) 1 << 16))
2445 /* An X_MASK with the RB field fixed. */
2446 #define XRB_MASK (X_MASK | RB_MASK)
2448 /* An X_MASK with the RT field fixed. */
2449 #define XRT_MASK (X_MASK | RT_MASK)
2451 /* An XRT_MASK mask with the L bits clear. */
2452 #define XLRT_MASK (XRT_MASK & ~((unsigned long) 0x3 << 21))
2454 /* An X_MASK with the RA and RB fields fixed. */
2455 #define XRARB_MASK (X_MASK | RA_MASK | RB_MASK)
2457 /* An XRARB_MASK, but with the L bit clear. */
2458 #define XRLARB_MASK (XRARB_MASK & ~((unsigned long) 1 << 16))
2460 /* An X_MASK with the RT and RA fields fixed. */
2461 #define XRTRA_MASK (X_MASK | RT_MASK | RA_MASK)
2463 /* An X_MASK with the RT and RB fields fixed. */
2464 #define XRTRB_MASK (X_MASK | RT_MASK | RB_MASK)
2466 /* An XRTRA_MASK, but with L bit clear. */
2467 #define XRTLRA_MASK (XRTRA_MASK & ~((unsigned long) 1 << 21))
2469 /* An X_MASK with the RT, RA and RB fields fixed. */
2470 #define XRTRARB_MASK (X_MASK | RT_MASK | RA_MASK | RB_MASK)
2472 /* An XRTRARB_MASK, but with L bit clear. */
2473 #define XRTLRARB_MASK (XRTRARB_MASK & ~((unsigned long) 1 << 21))
2475 /* An XRTRARB_MASK, but with A bit clear. */
2476 #define XRTARARB_MASK (XRTRARB_MASK & ~((unsigned long) 1 << 25))
2478 /* An XRTRARB_MASK, but with BF bits clear. */
2479 #define XRTBFRARB_MASK (XRTRARB_MASK & ~((unsigned long) 7 << 23))
2481 /* An X form instruction with the L bit specified. */
2482 #define XOPL(op, xop, l) (X ((op), (xop)) | ((((unsigned long)(l)) & 1) << 21))
2484 /* An X form instruction with the L bits specified. */
2485 #define XOPL2(op, xop, l) (X ((op), (xop)) | ((((unsigned long)(l)) & 3) << 21))
2487 /* An X form instruction with the L bit and RC bit specified. */
2488 #define XRCL(op, xop, l, rc) (XRC ((op), (xop), (rc)) | ((((unsigned long)(l)) & 1) << 21))
2490 /* An X form instruction with RT fields specified */
2491 #define XRT(op, xop, rt) (X ((op), (xop)) \
2492 | ((((unsigned long)(rt)) & 0x1f) << 21))
2494 /* An X form instruction with RT and RA fields specified */
2495 #define XRTRA(op, xop, rt, ra) (X ((op), (xop)) \
2496 | ((((unsigned long)(rt)) & 0x1f) << 21) \
2497 | ((((unsigned long)(ra)) & 0x1f) << 16))
2499 /* The mask for an X form comparison instruction. */
2500 #define XCMP_MASK (X_MASK | (((unsigned long)1) << 22))
2502 /* The mask for an X form comparison instruction with the L field
2504 #define XCMPL_MASK (XCMP_MASK | (((unsigned long)1) << 21))
2506 /* An X form trap instruction with the TO field specified. */
2507 #define XTO(op, xop, to) (X ((op), (xop)) | ((((unsigned long)(to)) & 0x1f) << 21))
2508 #define XTO_MASK (X_MASK | TO_MASK)
2510 /* An X form tlb instruction with the SH field specified. */
2511 #define XTLB(op, xop, sh) (X ((op), (xop)) | ((((unsigned long)(sh)) & 0x1f) << 11))
2512 #define XTLB_MASK (X_MASK | SH_MASK)
2514 /* An X form sync instruction. */
2515 #define XSYNC(op, xop, l) (X ((op), (xop)) | ((((unsigned long)(l)) & 3) << 21))
2517 /* An X form sync instruction with everything filled in except the LS field. */
2518 #define XSYNC_MASK (0xff9fffff)
2520 /* An X form sync instruction with everything filled in except the L and E fields. */
2521 #define XSYNCLE_MASK (0xff90ffff)
2523 /* An X_MASK, but with the EH bit clear. */
2524 #define XEH_MASK (X_MASK & ~((unsigned long )1))
2526 /* An X form AltiVec dss instruction. */
2527 #define XDSS(op, xop, a) (X ((op), (xop)) | ((((unsigned long)(a)) & 1) << 25))
2528 #define XDSS_MASK XDSS(0x3f, 0x3ff, 1)
2530 /* An XFL form instruction. */
2531 #define XFL(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0x3ff) << 1) | (((unsigned long)(rc)) & 1))
2532 #define XFL_MASK XFL (0x3f, 0x3ff, 1)
2534 /* An X form isel instruction. */
2535 #define XISEL(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x1f) << 1))
2536 #define XISEL_MASK XISEL(0x3f, 0x1f)
2538 /* An XL form instruction with the LK field set to 0. */
2539 #define XL(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x3ff) << 1))
2541 /* An XL form instruction which uses the LK field. */
2542 #define XLLK(op, xop, lk) (XL ((op), (xop)) | ((lk) & 1))
2544 /* The mask for an XL form instruction. */
2545 #define XL_MASK XLLK (0x3f, 0x3ff, 1)
2547 /* An XL_MASK with the RT, RA and RB fields fixed, but S bit clear. */
2548 #define XLS_MASK ((XL_MASK | RT_MASK | RA_MASK | RB_MASK) & ~(1 << 11))
2550 /* An XL form instruction which explicitly sets the BO field. */
2551 #define XLO(op, bo, xop, lk) \
2552 (XLLK ((op), (xop), (lk)) | ((((unsigned long)(bo)) & 0x1f) << 21))
2553 #define XLO_MASK (XL_MASK | BO_MASK)
2555 /* An XL form instruction which explicitly sets the y bit of the BO
2557 #define XLYLK(op, xop, y, lk) (XLLK ((op), (xop), (lk)) | ((((unsigned long)(y)) & 1) << 21))
2558 #define XLYLK_MASK (XL_MASK | Y_MASK)
2560 /* An XL form instruction which sets the BO field and the condition
2561 bits of the BI field. */
2562 #define XLOCB(op, bo, cb, xop, lk) \
2563 (XLO ((op), (bo), (xop), (lk)) | ((((unsigned long)(cb)) & 3) << 16))
2564 #define XLOCB_MASK XLOCB (0x3f, 0x1f, 0x3, 0x3ff, 1)
2566 /* An XL_MASK or XLYLK_MASK or XLOCB_MASK with the BB field fixed. */
2567 #define XLBB_MASK (XL_MASK | BB_MASK)
2568 #define XLYBB_MASK (XLYLK_MASK | BB_MASK)
2569 #define XLBOCBBB_MASK (XLOCB_MASK | BB_MASK)
2571 /* A mask for branch instructions using the BH field. */
2572 #define XLBH_MASK (XL_MASK | (0x1c << 11))
2574 /* An XL_MASK with the BO and BB fields fixed. */
2575 #define XLBOBB_MASK (XL_MASK | BO_MASK | BB_MASK)
2577 /* An XL_MASK with the BO, BI and BB fields fixed. */
2578 #define XLBOBIBB_MASK (XL_MASK | BO_MASK | BI_MASK | BB_MASK)
2580 /* An X form mbar instruction with MO field. */
2581 #define XMBAR(op, xop, mo) (X ((op), (xop)) | ((((unsigned long)(mo)) & 1) << 21))
2583 /* An XO form instruction. */
2584 #define XO(op, xop, oe, rc) \
2585 (OP (op) | ((((unsigned long)(xop)) & 0x1ff) << 1) | ((((unsigned long)(oe)) & 1) << 10) | (((unsigned long)(rc)) & 1))
2586 #define XO_MASK XO (0x3f, 0x1ff, 1, 1)
2588 /* An XO_MASK with the RB field fixed. */
2589 #define XORB_MASK (XO_MASK | RB_MASK)
2591 /* An XOPS form instruction for paired singles. */
2592 #define XOPS(op, xop, rc) \
2593 (OP (op) | ((((unsigned long)(xop)) & 0x3ff) << 1) | (((unsigned long)(rc)) & 1))
2594 #define XOPS_MASK XOPS (0x3f, 0x3ff, 1)
2597 /* An XS form instruction. */
2598 #define XS(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0x1ff) << 2) | (((unsigned long)(rc)) & 1))
2599 #define XS_MASK XS (0x3f, 0x1ff, 1)
2601 /* A mask for the FXM version of an XFX form instruction. */
2602 #define XFXFXM_MASK (X_MASK | (1 << 11) | (1 << 20))
2604 /* An XFX form instruction with the FXM field filled in. */
2605 #define XFXM(op, xop, fxm, p4) \
2606 (X ((op), (xop)) | ((((unsigned long)(fxm)) & 0xff) << 12) \
2607 | ((unsigned long)(p4) << 20))
2609 /* An XFX form instruction with the SPR field filled in. */
2610 #define XSPR(op, xop, spr) \
2611 (X ((op), (xop)) | ((((unsigned long)(spr)) & 0x1f) << 16) | ((((unsigned long)(spr)) & 0x3e0) << 6))
2612 #define XSPR_MASK (X_MASK | SPR_MASK)
2614 /* An XFX form instruction with the SPR field filled in except for the
2616 #define XSPRBAT_MASK (XSPR_MASK &~ SPRBAT_MASK)
2618 /* An XFX form instruction with the SPR field filled in except for the
2620 #define XSPRG_MASK (XSPR_MASK & ~(0x1f << 16))
2622 /* An X form instruction with everything filled in except the E field. */
2623 #define XE_MASK (0xffff7fff)
2625 /* An X form user context instruction. */
2626 #define XUC(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x1f))
2627 #define XUC_MASK XUC(0x3f, 0x1f)
2629 /* An XW form instruction. */
2630 #define XW(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0x3f) << 1) | ((rc) & 1))
2631 /* The mask for a G form instruction. rc not supported at present. */
2632 #define XW_MASK XW (0x3f, 0x3f, 0)
2634 /* An APU form instruction. */
2635 #define APU(op, xop, rc) (OP (op) | (((unsigned long)(xop)) & 0x3ff) << 1 | ((rc) & 1))
2637 /* The mask for an APU form instruction. */
2638 #define APU_MASK APU (0x3f, 0x3ff, 1)
2639 #define APU_RT_MASK (APU_MASK | RT_MASK)
2640 #define APU_RA_MASK (APU_MASK | RA_MASK)
2642 /* The BO encodings used in extended conditional branch mnemonics. */
2643 #define BODNZF (0x0)
2644 #define BODNZFP (0x1)
2646 #define BODZFP (0x3)
2647 #define BODNZT (0x8)
2648 #define BODNZTP (0x9)
2650 #define BODZTP (0xb)
2661 #define BODNZ (0x10)
2662 #define BODNZP (0x11)
2664 #define BODZP (0x13)
2665 #define BODNZM4 (0x18)
2666 #define BODNZP4 (0x19)
2667 #define BODZM4 (0x1a)
2668 #define BODZP4 (0x1b)
2672 /* The BO16 encodings used in extended VLE conditional branch mnemonics. */
2676 /* The BO32 encodings used in extended VLE conditional branch mnemonics. */
2679 #define BO32DNZ (0x2)
2680 #define BO32DZ (0x3)
2682 /* The BI condition bit encodings used in extended conditional branch
2689 /* The TO encodings used in extended trap mnemonics. */
2706 /* Smaller names for the flags so each entry in the opcodes table will
2707 fit on a single line. */
2710 #define PPC PPC_OPCODE_PPC
2711 #define PPCCOM PPC_OPCODE_PPC | PPC_OPCODE_COMMON
2712 #define POWER4 PPC_OPCODE_POWER4
2713 #define POWER5 PPC_OPCODE_POWER5
2714 #define POWER6 PPC_OPCODE_POWER6
2715 #define POWER7 PPC_OPCODE_POWER7
2716 #define POWER8 PPC_OPCODE_POWER8
2717 #define CELL PPC_OPCODE_CELL
2718 #define PPC64 PPC_OPCODE_64 | PPC_OPCODE_64_BRIDGE
2719 #define NON32 (PPC_OPCODE_64 | PPC_OPCODE_POWER4 \
2720 | PPC_OPCODE_EFS | PPC_OPCODE_E500MC | PPC_OPCODE_TITAN)
2721 #define PPC403 PPC_OPCODE_403
2722 #define PPC405 PPC_OPCODE_405
2723 #define PPC440 PPC_OPCODE_440
2724 #define PPC464 PPC440
2725 #define PPC476 PPC_OPCODE_476
2729 #define PPCPS PPC_OPCODE_PPCPS
2730 #define PPCVEC PPC_OPCODE_ALTIVEC
2731 #define PPCVEC2 PPC_OPCODE_ALTIVEC2
2732 #define PPCVSX PPC_OPCODE_VSX
2733 #define PPCVSX2 PPC_OPCODE_VSX
2734 #define POWER PPC_OPCODE_POWER
2735 #define POWER2 PPC_OPCODE_POWER | PPC_OPCODE_POWER2
2736 #define PWR2COM PPC_OPCODE_POWER | PPC_OPCODE_POWER2 | PPC_OPCODE_COMMON
2737 #define PPCPWR2 PPC_OPCODE_PPC | PPC_OPCODE_POWER | PPC_OPCODE_POWER2 | PPC_OPCODE_COMMON
2738 #define COM PPC_OPCODE_POWER | PPC_OPCODE_PPC | PPC_OPCODE_COMMON
2739 #define M601 PPC_OPCODE_POWER | PPC_OPCODE_601
2740 #define PWRCOM PPC_OPCODE_POWER | PPC_OPCODE_601 | PPC_OPCODE_COMMON
2741 #define MFDEC1 PPC_OPCODE_POWER
2742 #define MFDEC2 PPC_OPCODE_PPC | PPC_OPCODE_601 | PPC_OPCODE_BOOKE | PPC_OPCODE_TITAN
2743 #define BOOKE PPC_OPCODE_BOOKE
2744 #define NO371 PPC_OPCODE_BOOKE | PPC_OPCODE_PPCPS | PPC_OPCODE_EFS | PPC_OPCODE_VLE
2745 #define PPCE300 PPC_OPCODE_E300
2746 #define PPCSPE PPC_OPCODE_SPE | PPC_OPCODE_VLE
2747 #define PPCISEL PPC_OPCODE_ISEL | PPC_OPCODE_VLE
2748 #define PPCEFS PPC_OPCODE_EFS | PPC_OPCODE_VLE
2749 #define PPCBRLK PPC_OPCODE_BRLOCK
2750 #define PPCPMR PPC_OPCODE_PMR
2751 #define PPCTMR PPC_OPCODE_TMR
2752 #define PPCCHLK PPC_OPCODE_CACHELCK
2753 #define PPCRFMCI PPC_OPCODE_RFMCI
2754 #define E500MC PPC_OPCODE_E500MC
2755 #define PPCA2 PPC_OPCODE_A2
2756 #define TITAN PPC_OPCODE_TITAN
2757 #define MULHW PPC_OPCODE_405 | PPC_OPCODE_440 | TITAN | PPC_OPCODE_VLE
2758 #define E500 PPC_OPCODE_E500
2759 #define E6500 PPC_OPCODE_E6500
2760 #define PPCVLE PPC_OPCODE_VLE
2761 #define PPCHTM PPC_OPCODE_HTM
2762 /* The list of embedded processors that use the embedded operand ordering
2763 for the 3 operand dcbt and dcbtst instructions. */
2764 #define DCBT_EO (PPC_OPCODE_E500 | PPC_OPCODE_E500MC | PPC_OPCODE_476 \
2765 | PPC_OPCODE_A2 | PPC_OPCODE_VLE)
2769 /* The opcode table.
2771 The format of the opcode table is:
2773 NAME OPCODE MASK FLAGS ANTI {OPERANDS}
2775 NAME is the name of the instruction.
2776 OPCODE is the instruction opcode.
2777 MASK is the opcode mask; this is used to tell the disassembler
2778 which bits in the actual opcode must match OPCODE.
2779 FLAGS are flags indicating which processors support the instruction.
2780 ANTI indicates which processors don't support the instruction.
2781 OPERANDS is the list of operands.
2783 The disassembler reads the table in order and prints the first
2784 instruction which matches, so this table is sorted to put more
2785 specific instructions before more general instructions.
2787 This table must be sorted by major opcode. Please try to keep it
2788 vaguely sorted within major opcode too, except of course where
2789 constrained otherwise by disassembler operation. */
2791 const struct powerpc_opcode powerpc_opcodes
[] = {
2792 {"attn", X(0,256), X_MASK
, POWER4
|PPCA2
, PPC476
, {0}},
2793 {"tdlgti", OPTO(2,TOLGT
), OPTO_MASK
, PPC64
, PPCNONE
, {RA
, SI
}},
2794 {"tdllti", OPTO(2,TOLLT
), OPTO_MASK
, PPC64
, PPCNONE
, {RA
, SI
}},
2795 {"tdeqi", OPTO(2,TOEQ
), OPTO_MASK
, PPC64
, PPCNONE
, {RA
, SI
}},
2796 {"tdlgei", OPTO(2,TOLGE
), OPTO_MASK
, PPC64
, PPCNONE
, {RA
, SI
}},
2797 {"tdlnli", OPTO(2,TOLNL
), OPTO_MASK
, PPC64
, PPCNONE
, {RA
, SI
}},
2798 {"tdllei", OPTO(2,TOLLE
), OPTO_MASK
, PPC64
, PPCNONE
, {RA
, SI
}},
2799 {"tdlngi", OPTO(2,TOLNG
), OPTO_MASK
, PPC64
, PPCNONE
, {RA
, SI
}},
2800 {"tdgti", OPTO(2,TOGT
), OPTO_MASK
, PPC64
, PPCNONE
, {RA
, SI
}},
2801 {"tdgei", OPTO(2,TOGE
), OPTO_MASK
, PPC64
, PPCNONE
, {RA
, SI
}},
2802 {"tdnli", OPTO(2,TONL
), OPTO_MASK
, PPC64
, PPCNONE
, {RA
, SI
}},
2803 {"tdlti", OPTO(2,TOLT
), OPTO_MASK
, PPC64
, PPCNONE
, {RA
, SI
}},
2804 {"tdlei", OPTO(2,TOLE
), OPTO_MASK
, PPC64
, PPCNONE
, {RA
, SI
}},
2805 {"tdngi", OPTO(2,TONG
), OPTO_MASK
, PPC64
, PPCNONE
, {RA
, SI
}},
2806 {"tdnei", OPTO(2,TONE
), OPTO_MASK
, PPC64
, PPCNONE
, {RA
, SI
}},
2807 {"tdui", OPTO(2,TOU
), OPTO_MASK
, PPC64
, PPCNONE
, {RA
, SI
}},
2808 {"tdi", OP(2), OP_MASK
, PPC64
, PPCNONE
, {TO
, RA
, SI
}},
2810 {"twlgti", OPTO(3,TOLGT
), OPTO_MASK
, PPCCOM
, PPCNONE
, {RA
, SI
}},
2811 {"tlgti", OPTO(3,TOLGT
), OPTO_MASK
, PWRCOM
, PPCNONE
, {RA
, SI
}},
2812 {"twllti", OPTO(3,TOLLT
), OPTO_MASK
, PPCCOM
, PPCNONE
, {RA
, SI
}},
2813 {"tllti", OPTO(3,TOLLT
), OPTO_MASK
, PWRCOM
, PPCNONE
, {RA
, SI
}},
2814 {"tweqi", OPTO(3,TOEQ
), OPTO_MASK
, PPCCOM
, PPCNONE
, {RA
, SI
}},
2815 {"teqi", OPTO(3,TOEQ
), OPTO_MASK
, PWRCOM
, PPCNONE
, {RA
, SI
}},
2816 {"twlgei", OPTO(3,TOLGE
), OPTO_MASK
, PPCCOM
, PPCNONE
, {RA
, SI
}},
2817 {"tlgei", OPTO(3,TOLGE
), OPTO_MASK
, PWRCOM
, PPCNONE
, {RA
, SI
}},
2818 {"twlnli", OPTO(3,TOLNL
), OPTO_MASK
, PPCCOM
, PPCNONE
, {RA
, SI
}},
2819 {"tlnli", OPTO(3,TOLNL
), OPTO_MASK
, PWRCOM
, PPCNONE
, {RA
, SI
}},
2820 {"twllei", OPTO(3,TOLLE
), OPTO_MASK
, PPCCOM
, PPCNONE
, {RA
, SI
}},
2821 {"tllei", OPTO(3,TOLLE
), OPTO_MASK
, PWRCOM
, PPCNONE
, {RA
, SI
}},
2822 {"twlngi", OPTO(3,TOLNG
), OPTO_MASK
, PPCCOM
, PPCNONE
, {RA
, SI
}},
2823 {"tlngi", OPTO(3,TOLNG
), OPTO_MASK
, PWRCOM
, PPCNONE
, {RA
, SI
}},
2824 {"twgti", OPTO(3,TOGT
), OPTO_MASK
, PPCCOM
, PPCNONE
, {RA
, SI
}},
2825 {"tgti", OPTO(3,TOGT
), OPTO_MASK
, PWRCOM
, PPCNONE
, {RA
, SI
}},
2826 {"twgei", OPTO(3,TOGE
), OPTO_MASK
, PPCCOM
, PPCNONE
, {RA
, SI
}},
2827 {"tgei", OPTO(3,TOGE
), OPTO_MASK
, PWRCOM
, PPCNONE
, {RA
, SI
}},
2828 {"twnli", OPTO(3,TONL
), OPTO_MASK
, PPCCOM
, PPCNONE
, {RA
, SI
}},
2829 {"tnli", OPTO(3,TONL
), OPTO_MASK
, PWRCOM
, PPCNONE
, {RA
, SI
}},
2830 {"twlti", OPTO(3,TOLT
), OPTO_MASK
, PPCCOM
, PPCNONE
, {RA
, SI
}},
2831 {"tlti", OPTO(3,TOLT
), OPTO_MASK
, PWRCOM
, PPCNONE
, {RA
, SI
}},
2832 {"twlei", OPTO(3,TOLE
), OPTO_MASK
, PPCCOM
, PPCNONE
, {RA
, SI
}},
2833 {"tlei", OPTO(3,TOLE
), OPTO_MASK
, PWRCOM
, PPCNONE
, {RA
, SI
}},
2834 {"twngi", OPTO(3,TONG
), OPTO_MASK
, PPCCOM
, PPCNONE
, {RA
, SI
}},
2835 {"tngi", OPTO(3,TONG
), OPTO_MASK
, PWRCOM
, PPCNONE
, {RA
, SI
}},
2836 {"twnei", OPTO(3,TONE
), OPTO_MASK
, PPCCOM
, PPCNONE
, {RA
, SI
}},
2837 {"tnei", OPTO(3,TONE
), OPTO_MASK
, PWRCOM
, PPCNONE
, {RA
, SI
}},
2838 {"twui", OPTO(3,TOU
), OPTO_MASK
, PPCCOM
, PPCNONE
, {RA
, SI
}},
2839 {"tui", OPTO(3,TOU
), OPTO_MASK
, PWRCOM
, PPCNONE
, {RA
, SI
}},
2840 {"twi", OP(3), OP_MASK
, PPCCOM
, PPCNONE
, {TO
, RA
, SI
}},
2841 {"ti", OP(3), OP_MASK
, PWRCOM
, PPCNONE
, {TO
, RA
, SI
}},
2843 {"ps_cmpu0", X (4, 0), X_MASK
|(3<<21), PPCPS
, PPCNONE
, {BF
, FRA
, FRB
}},
2844 {"vaddubm", VX (4, 0), VX_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
2845 {"vmaxub", VX (4, 2), VX_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
2846 {"vrlb", VX (4, 4), VX_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
2847 {"vcmpequb", VXR(4, 6,0), VXR_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
2848 {"vmuloub", VX (4, 8), VX_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
2849 {"vaddfp", VX (4, 10), VX_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
2850 {"psq_lx", XW (4, 6,0), XW_MASK
, PPCPS
, PPCNONE
, {FRT
,RA
,RB
,PSWM
,PSQM
}},
2851 {"vmrghb", VX (4, 12), VX_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
2852 {"psq_stx", XW (4, 7,0), XW_MASK
, PPCPS
, PPCNONE
, {FRS
,RA
,RB
,PSWM
,PSQM
}},
2853 {"vpkuhum", VX (4, 14), VX_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
2854 {"mulhhwu", XRC(4, 8,0), X_MASK
, MULHW
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
2855 {"mulhhwu.", XRC(4, 8,1), X_MASK
, MULHW
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
2856 {"ps_sum0", A (4, 10,0), A_MASK
, PPCPS
, PPCNONE
, {FRT
, FRA
, FRC
, FRB
}},
2857 {"ps_sum0.", A (4, 10,1), A_MASK
, PPCPS
, PPCNONE
, {FRT
, FRA
, FRC
, FRB
}},
2858 {"ps_sum1", A (4, 11,0), A_MASK
, PPCPS
, PPCNONE
, {FRT
, FRA
, FRC
, FRB
}},
2859 {"ps_sum1.", A (4, 11,1), A_MASK
, PPCPS
, PPCNONE
, {FRT
, FRA
, FRC
, FRB
}},
2860 {"ps_muls0", A (4, 12,0), AFRB_MASK
, PPCPS
, PPCNONE
, {FRT
, FRA
, FRC
}},
2861 {"machhwu", XO (4, 12,0,0),XO_MASK
, MULHW
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
2862 {"ps_muls0.", A (4, 12,1), AFRB_MASK
, PPCPS
, PPCNONE
, {FRT
, FRA
, FRC
}},
2863 {"machhwu.", XO (4, 12,0,1),XO_MASK
, MULHW
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
2864 {"ps_muls1", A (4, 13,0), AFRB_MASK
, PPCPS
, PPCNONE
, {FRT
, FRA
, FRC
}},
2865 {"ps_muls1.", A (4, 13,1), AFRB_MASK
, PPCPS
, PPCNONE
, {FRT
, FRA
, FRC
}},
2866 {"ps_madds0", A (4, 14,0), A_MASK
, PPCPS
, PPCNONE
, {FRT
, FRA
, FRC
, FRB
}},
2867 {"ps_madds0.", A (4, 14,1), A_MASK
, PPCPS
, PPCNONE
, {FRT
, FRA
, FRC
, FRB
}},
2868 {"ps_madds1", A (4, 15,0), A_MASK
, PPCPS
, PPCNONE
, {FRT
, FRA
, FRC
, FRB
}},
2869 {"ps_madds1.", A (4, 15,1), A_MASK
, PPCPS
, PPCNONE
, {FRT
, FRA
, FRC
, FRB
}},
2870 {"vmhaddshs", VXA(4, 32), VXA_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
, VC
}},
2871 {"vmhraddshs", VXA(4, 33), VXA_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
, VC
}},
2872 {"vmladduhm", VXA(4, 34), VXA_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
, VC
}},
2873 {"ps_div", A (4, 18,0), AFRC_MASK
, PPCPS
, PPCNONE
, {FRT
, FRA
, FRB
}},
2874 {"vmsumubm", VXA(4, 36), VXA_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
, VC
}},
2875 {"ps_div.", A (4, 18,1), AFRC_MASK
, PPCPS
, PPCNONE
, {FRT
, FRA
, FRB
}},
2876 {"vmsummbm", VXA(4, 37), VXA_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
, VC
}},
2877 {"vmsumuhm", VXA(4, 38), VXA_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
, VC
}},
2878 {"vmsumuhs", VXA(4, 39), VXA_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
, VC
}},
2879 {"ps_sub", A (4, 20,0), AFRC_MASK
, PPCPS
, PPCNONE
, {FRT
, FRA
, FRB
}},
2880 {"vmsumshm", VXA(4, 40), VXA_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
, VC
}},
2881 {"ps_sub.", A (4, 20,1), AFRC_MASK
, PPCPS
, PPCNONE
, {FRT
, FRA
, FRB
}},
2882 {"vmsumshs", VXA(4, 41), VXA_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
, VC
}},
2883 {"ps_add", A (4, 21,0), AFRC_MASK
, PPCPS
, PPCNONE
, {FRT
, FRA
, FRB
}},
2884 {"vsel", VXA(4, 42), VXA_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
, VC
}},
2885 {"ps_add.", A (4, 21,1), AFRC_MASK
, PPCPS
, PPCNONE
, {FRT
, FRA
, FRB
}},
2886 {"vperm", VXA(4, 43), VXA_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
, VC
}},
2887 {"vsldoi", VXA(4, 44), VXASHB_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
, SHB
}},
2888 {"ps_sel", A (4, 23,0), A_MASK
, PPCPS
, PPCNONE
, {FRT
, FRA
, FRC
, FRB
}},
2889 {"vpermxor", VXA(4, 45), VXA_MASK
, PPCVEC2
, PPCNONE
, {VD
, VA
, VB
, VC
}},
2890 {"vmaddfp", VXA(4, 46), VXA_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VC
, VB
}},
2891 {"ps_sel.", A (4, 23,1), A_MASK
, PPCPS
, PPCNONE
, {FRT
, FRA
, FRC
, FRB
}},
2892 {"vnmsubfp", VXA(4, 47), VXA_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VC
, VB
}},
2893 {"ps_res", A (4, 24,0), AFRAFRC_MASK
, PPCPS
, PPCNONE
, {FRT
, FRB
}},
2894 {"ps_res.", A (4, 24,1), AFRAFRC_MASK
, PPCPS
, PPCNONE
, {FRT
, FRB
}},
2895 {"ps_mul", A (4, 25,0), AFRB_MASK
, PPCPS
, PPCNONE
, {FRT
, FRA
, FRC
}},
2896 {"ps_mul.", A (4, 25,1), AFRB_MASK
, PPCPS
, PPCNONE
, {FRT
, FRA
, FRC
}},
2897 {"ps_rsqrte", A (4, 26,0), AFRAFRC_MASK
, PPCPS
, PPCNONE
, {FRT
, FRB
}},
2898 {"ps_rsqrte.", A (4, 26,1), AFRAFRC_MASK
, PPCPS
, PPCNONE
, {FRT
, FRB
}},
2899 {"ps_msub", A (4, 28,0), A_MASK
, PPCPS
, PPCNONE
, {FRT
, FRA
, FRC
, FRB
}},
2900 {"ps_msub.", A (4, 28,1), A_MASK
, PPCPS
, PPCNONE
, {FRT
, FRA
, FRC
, FRB
}},
2901 {"ps_madd", A (4, 29,0), A_MASK
, PPCPS
, PPCNONE
, {FRT
, FRA
, FRC
, FRB
}},
2902 {"ps_madd.", A (4, 29,1), A_MASK
, PPCPS
, PPCNONE
, {FRT
, FRA
, FRC
, FRB
}},
2903 {"ps_nmsub", A (4, 30,0), A_MASK
, PPCPS
, PPCNONE
, {FRT
, FRA
, FRC
, FRB
}},
2904 {"ps_nmsub.", A (4, 30,1), A_MASK
, PPCPS
, PPCNONE
, {FRT
, FRA
, FRC
, FRB
}},
2905 {"ps_nmadd", A (4, 31,0), A_MASK
, PPCPS
, PPCNONE
, {FRT
, FRA
, FRC
, FRB
}},
2906 {"ps_nmadd.", A (4, 31,1), A_MASK
, PPCPS
, PPCNONE
, {FRT
, FRA
, FRC
, FRB
}},
2907 {"ps_cmpo0", X (4, 32), X_MASK
|(3<<21), PPCPS
, PPCNONE
, {BF
, FRA
, FRB
}},
2908 {"vaddeuqm", VXA(4, 60), VXA_MASK
, PPCVEC2
, PPCNONE
, {VD
, VA
, VB
, VC
}},
2909 {"vaddecuq", VXA(4, 61), VXA_MASK
, PPCVEC2
, PPCNONE
, {VD
, VA
, VB
, VC
}},
2910 {"vsubeuqm", VXA(4, 62), VXA_MASK
, PPCVEC2
, PPCNONE
, {VD
, VA
, VB
, VC
}},
2911 {"vsubecuq", VXA(4, 63), VXA_MASK
, PPCVEC2
, PPCNONE
, {VD
, VA
, VB
, VC
}},
2912 {"vadduhm", VX (4, 64), VX_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
2913 {"vmaxuh", VX (4, 66), VX_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
2914 {"vrlh", VX (4, 68), VX_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
2915 {"vcmpequh", VXR(4, 70,0), VXR_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
2916 {"vmulouh", VX (4, 72), VX_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
2917 {"vsubfp", VX (4, 74), VX_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
2918 {"psq_lux", XW (4, 38,0), XW_MASK
, PPCPS
, PPCNONE
, {FRT
,RA
,RB
,PSWM
,PSQM
}},
2919 {"vmrghh", VX (4, 76), VX_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
2920 {"psq_stux", XW (4, 39,0), XW_MASK
, PPCPS
, PPCNONE
, {FRS
,RA
,RB
,PSWM
,PSQM
}},
2921 {"vpkuwum", VX (4, 78), VX_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
2922 {"ps_neg", XRC(4, 40,0), XRA_MASK
, PPCPS
, PPCNONE
, {FRT
, FRB
}},
2923 {"mulhhw", XRC(4, 40,0), X_MASK
, MULHW
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
2924 {"ps_neg.", XRC(4, 40,1), XRA_MASK
, PPCPS
, PPCNONE
, {FRT
, FRB
}},
2925 {"mulhhw.", XRC(4, 40,1), X_MASK
, MULHW
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
2926 {"machhw", XO (4, 44,0,0),XO_MASK
, MULHW
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
2927 {"machhw.", XO (4, 44,0,1),XO_MASK
, MULHW
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
2928 {"nmachhw", XO (4, 46,0,0),XO_MASK
, MULHW
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
2929 {"nmachhw.", XO (4, 46,0,1),XO_MASK
, MULHW
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
2930 {"ps_cmpu1", X (4, 64), X_MASK
|(3<<21), PPCPS
, PPCNONE
, {BF
, FRA
, FRB
}},
2931 {"vadduwm", VX (4, 128), VX_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
2932 {"vmaxuw", VX (4, 130), VX_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
2933 {"vrlw", VX (4, 132), VX_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
2934 {"vcmpequw", VXR(4, 134,0), VXR_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
2935 {"vmulouw", VX (4, 136), VX_MASK
, PPCVEC2
, PPCNONE
, {VD
, VA
, VB
}},
2936 {"vmuluwm", VX (4, 137), VX_MASK
, PPCVEC2
, PPCNONE
, {VD
, VA
, VB
}},
2937 {"vmrghw", VX (4, 140), VX_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
2938 {"vpkuhus", VX (4, 142), VX_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
2939 {"ps_mr", XRC(4, 72,0), XRA_MASK
, PPCPS
, PPCNONE
, {FRT
, FRB
}},
2940 {"ps_mr.", XRC(4, 72,1), XRA_MASK
, PPCPS
, PPCNONE
, {FRT
, FRB
}},
2941 {"machhwsu", XO (4, 76,0,0),XO_MASK
, MULHW
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
2942 {"machhwsu.", XO (4, 76,0,1),XO_MASK
, MULHW
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
2943 {"ps_cmpo1", X (4, 96), X_MASK
|(3<<21), PPCPS
, PPCNONE
, {BF
, FRA
, FRB
}},
2944 {"vaddudm", VX (4, 192), VX_MASK
, PPCVEC2
, PPCNONE
, {VD
, VA
, VB
}},
2945 {"vmaxud", VX (4, 194), VX_MASK
, PPCVEC2
, PPCNONE
, {VD
, VA
, VB
}},
2946 {"vrld", VX (4, 196), VX_MASK
, PPCVEC2
, PPCNONE
, {VD
, VA
, VB
}},
2947 {"vcmpeqfp", VXR(4, 198,0), VXR_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
2948 {"vcmpequd", VXR(4, 199,0), VXR_MASK
, PPCVEC2
, PPCNONE
, {VD
, VA
, VB
}},
2949 {"vpkuwus", VX (4, 206), VX_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
2950 {"machhws", XO (4, 108,0,0),XO_MASK
, MULHW
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
2951 {"machhws.", XO (4, 108,0,1),XO_MASK
, MULHW
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
2952 {"nmachhws", XO (4, 110,0,0),XO_MASK
, MULHW
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
2953 {"nmachhws.", XO (4, 110,0,1),XO_MASK
, MULHW
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
2954 {"vadduqm", VX (4, 256), VX_MASK
, PPCVEC2
, PPCNONE
, {VD
, VA
, VB
}},
2955 {"vmaxsb", VX (4, 258), VX_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
2956 {"vslb", VX (4, 260), VX_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
2957 {"vmulosb", VX (4, 264), VX_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
2958 {"vrefp", VX (4, 266), VXVA_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VB
}},
2959 {"vmrglb", VX (4, 268), VX_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
2960 {"vpkshus", VX (4, 270), VX_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
2961 {"ps_nabs", XRC(4, 136,0), XRA_MASK
, PPCPS
, PPCNONE
, {FRT
, FRB
}},
2962 {"mulchwu", XRC(4, 136,0), X_MASK
, MULHW
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
2963 {"ps_nabs.", XRC(4, 136,1), XRA_MASK
, PPCPS
, PPCNONE
, {FRT
, FRB
}},
2964 {"mulchwu.", XRC(4, 136,1), X_MASK
, MULHW
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
2965 {"macchwu", XO (4, 140,0,0),XO_MASK
, MULHW
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
2966 {"macchwu.", XO (4, 140,0,1),XO_MASK
, MULHW
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
2967 {"vaddcuq", VX (4, 320), VX_MASK
, PPCVEC2
, PPCNONE
, {VD
, VA
, VB
}},
2968 {"vmaxsh", VX (4, 322), VX_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
2969 {"vslh", VX (4, 324), VX_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
2970 {"vmulosh", VX (4, 328), VX_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
2971 {"vrsqrtefp", VX (4, 330), VXVA_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VB
}},
2972 {"vmrglh", VX (4, 332), VX_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
2973 {"vpkswus", VX (4, 334), VX_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
2974 {"mulchw", XRC(4, 168,0), X_MASK
, MULHW
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
2975 {"mulchw.", XRC(4, 168,1), X_MASK
, MULHW
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
2976 {"macchw", XO (4, 172,0,0),XO_MASK
, MULHW
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
2977 {"macchw.", XO (4, 172,0,1),XO_MASK
, MULHW
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
2978 {"nmacchw", XO (4, 174,0,0),XO_MASK
, MULHW
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
2979 {"nmacchw.", XO (4, 174,0,1),XO_MASK
, MULHW
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
2980 {"vaddcuw", VX (4, 384), VX_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
2981 {"vmaxsw", VX (4, 386), VX_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
2982 {"vslw", VX (4, 388), VX_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
2983 {"vmulosw", VX (4, 392), VX_MASK
, PPCVEC2
, PPCNONE
, {VD
, VA
, VB
}},
2984 {"vexptefp", VX (4, 394), VXVA_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VB
}},
2985 {"vmrglw", VX (4, 396), VX_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
2986 {"vpkshss", VX (4, 398), VX_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
2987 {"macchwsu", XO (4, 204,0,0),XO_MASK
, MULHW
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
2988 {"macchwsu.", XO (4, 204,0,1),XO_MASK
, MULHW
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
2989 {"vmaxsd", VX (4, 450), VX_MASK
, PPCVEC2
, PPCNONE
, {VD
, VA
, VB
}},
2990 {"vsl", VX (4, 452), VX_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
2991 {"vcmpgefp", VXR(4, 454,0), VXR_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
2992 {"vlogefp", VX (4, 458), VXVA_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VB
}},
2993 {"vpkswss", VX (4, 462), VX_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
2994 {"macchws", XO (4, 236,0,0),XO_MASK
, MULHW
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
2995 {"macchws.", XO (4, 236,0,1),XO_MASK
, MULHW
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
2996 {"nmacchws", XO (4, 238,0,0),XO_MASK
, MULHW
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
2997 {"nmacchws.", XO (4, 238,0,1),XO_MASK
, MULHW
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
2998 {"evaddw", VX (4, 512), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
2999 {"vaddubs", VX (4, 512), VX_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
3000 {"evaddiw", VX (4, 514), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RB
, UIMM
}},
3001 {"vminub", VX (4, 514), VX_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
3002 {"evsubfw", VX (4, 516), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3003 {"evsubw", VX (4, 516), VX_MASK
, PPCSPE
, PPCNONE
, {RS
, RB
, RA
}},
3004 {"vsrb", VX (4, 516), VX_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
3005 {"evsubifw", VX (4, 518), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, UIMM
, RB
}},
3006 {"evsubiw", VX (4, 518), VX_MASK
, PPCSPE
, PPCNONE
, {RS
, RB
, UIMM
}},
3007 {"vcmpgtub", VXR(4, 518,0), VXR_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
3008 {"evabs", VX (4, 520), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
}},
3009 {"vmuleub", VX (4, 520), VX_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
3010 {"evneg", VX (4, 521), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
}},
3011 {"evextsb", VX (4, 522), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
}},
3012 {"vrfin", VX (4, 522), VXVA_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VB
}},
3013 {"evextsh", VX (4, 523), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
}},
3014 {"evrndw", VX (4, 524), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
}},
3015 {"vspltb", VX (4, 524), VXUIMM4_MASK
,PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VB
, UIMM4
}},
3016 {"evcntlzw", VX (4, 525), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
}},
3017 {"evcntlsw", VX (4, 526), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
}},
3018 {"vupkhsb", VX (4, 526), VXVA_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VB
}},
3019 {"brinc", VX (4, 527), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3020 {"ps_abs", XRC(4, 264,0), XRA_MASK
, PPCPS
, PPCNONE
, {FRT
, FRB
}},
3021 {"ps_abs.", XRC(4, 264,1), XRA_MASK
, PPCPS
, PPCNONE
, {FRT
, FRB
}},
3022 {"evand", VX (4, 529), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3023 {"evandc", VX (4, 530), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3024 {"evxor", VX (4, 534), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3025 {"evmr", VX (4, 535), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, BBA
}},
3026 {"evor", VX (4, 535), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3027 {"evnor", VX (4, 536), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3028 {"evnot", VX (4, 536), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, BBA
}},
3029 {"get", APU(4, 268,0), APU_RA_MASK
, PPC405
, PPCNONE
, {RT
, FSL
}},
3030 {"eveqv", VX (4, 537), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3031 {"evorc", VX (4, 539), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3032 {"evnand", VX (4, 542), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3033 {"evsrwu", VX (4, 544), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3034 {"evsrws", VX (4, 545), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3035 {"evsrwiu", VX (4, 546), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, EVUIMM
}},
3036 {"evsrwis", VX (4, 547), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, EVUIMM
}},
3037 {"evslw", VX (4, 548), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3038 {"evslwi", VX (4, 550), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, EVUIMM
}},
3039 {"evrlw", VX (4, 552), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3040 {"evsplati", VX (4, 553), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, SIMM
}},
3041 {"evrlwi", VX (4, 554), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, EVUIMM
}},
3042 {"evsplatfi", VX (4, 555), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, SIMM
}},
3043 {"evmergehi", VX (4, 556), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3044 {"evmergelo", VX (4, 557), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3045 {"evmergehilo", VX (4, 558), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3046 {"evmergelohi", VX (4, 559), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3047 {"evcmpgtu", VX (4, 560), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {CRFD
, RA
, RB
}},
3048 {"evcmpgts", VX (4, 561), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {CRFD
, RA
, RB
}},
3049 {"evcmpltu", VX (4, 562), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {CRFD
, RA
, RB
}},
3050 {"evcmplts", VX (4, 563), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {CRFD
, RA
, RB
}},
3051 {"evcmpeq", VX (4, 564), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {CRFD
, RA
, RB
}},
3052 {"cget", APU(4, 284,0), APU_RA_MASK
, PPC405
, PPCNONE
, {RT
, FSL
}},
3053 {"vadduhs", VX (4, 576), VX_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
3054 {"vminuh", VX (4, 578), VX_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
3055 {"vsrh", VX (4, 580), VX_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
3056 {"vcmpgtuh", VXR(4, 582,0), VXR_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
3057 {"vmuleuh", VX (4, 584), VX_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
3058 {"vrfiz", VX (4, 586), VXVA_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VB
}},
3059 {"vsplth", VX (4, 588), VXUIMM3_MASK
,PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VB
, UIMM3
}},
3060 {"vupkhsh", VX (4, 590), VXVA_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VB
}},
3061 {"nget", APU(4, 300,0), APU_RA_MASK
, PPC405
, PPCNONE
, {RT
, FSL
}},
3062 {"evsel", EVSEL(4,79), EVSEL_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
, CRFS
}},
3063 {"ncget", APU(4, 316,0), APU_RA_MASK
, PPC405
, PPCNONE
, {RT
, FSL
}},
3064 {"evfsadd", VX (4, 640), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3065 {"vadduws", VX (4, 640), VX_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
3066 {"evfssub", VX (4, 641), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3067 {"vminuw", VX (4, 642), VX_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
3068 {"evfsabs", VX (4, 644), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
}},
3069 {"vsrw", VX (4, 644), VX_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
3070 {"evfsnabs", VX (4, 645), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
}},
3071 {"evfsneg", VX (4, 646), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
}},
3072 {"vcmpgtuw", VXR(4, 646,0), VXR_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
3073 {"vmuleuw", VX (4, 648), VX_MASK
, PPCVEC2
, PPCNONE
, {VD
, VA
, VB
}},
3074 {"evfsmul", VX (4, 648), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3075 {"evfsdiv", VX (4, 649), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3076 {"vrfip", VX (4, 650), VXVA_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VB
}},
3077 {"evfscmpgt", VX (4, 652), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {CRFD
, RA
, RB
}},
3078 {"vspltw", VX (4, 652), VXUIMM2_MASK
,PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VB
, UIMM2
}},
3079 {"evfscmplt", VX (4, 653), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {CRFD
, RA
, RB
}},
3080 {"evfscmpeq", VX (4, 654), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {CRFD
, RA
, RB
}},
3081 {"vupklsb", VX (4, 654), VXVA_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VB
}},
3082 {"evfscfui", VX (4, 656), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RB
}},
3083 {"evfscfsi", VX (4, 657), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RB
}},
3084 {"evfscfuf", VX (4, 658), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RB
}},
3085 {"evfscfsf", VX (4, 659), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RB
}},
3086 {"evfsctui", VX (4, 660), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RB
}},
3087 {"evfsctsi", VX (4, 661), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RB
}},
3088 {"evfsctuf", VX (4, 662), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RB
}},
3089 {"evfsctsf", VX (4, 663), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RB
}},
3090 {"evfsctuiz", VX (4, 664), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RB
}},
3091 {"put", APU(4, 332,0), APU_RT_MASK
, PPC405
, PPCNONE
, {RA
, FSL
}},
3092 {"evfsctsiz", VX (4, 666), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RB
}},
3093 {"evfststgt", VX (4, 668), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {CRFD
, RA
, RB
}},
3094 {"evfststlt", VX (4, 669), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {CRFD
, RA
, RB
}},
3095 {"evfststeq", VX (4, 670), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {CRFD
, RA
, RB
}},
3096 {"cput", APU(4, 348,0), APU_RT_MASK
, PPC405
, PPCNONE
, {RA
, FSL
}},
3097 {"efsadd", VX (4, 704), VX_MASK
, PPCEFS
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3098 {"efssub", VX (4, 705), VX_MASK
, PPCEFS
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3099 {"vminud", VX (4, 706), VX_MASK
, PPCVEC2
, PPCNONE
, {VD
, VA
, VB
}},
3100 {"efsabs", VX (4, 708), VX_MASK
, PPCEFS
|PPCVLE
, PPCNONE
, {RS
, RA
}},
3101 {"vsr", VX (4, 708), VX_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
3102 {"efsnabs", VX (4, 709), VX_MASK
, PPCEFS
|PPCVLE
, PPCNONE
, {RS
, RA
}},
3103 {"efsneg", VX (4, 710), VX_MASK
, PPCEFS
|PPCVLE
, PPCNONE
, {RS
, RA
}},
3104 {"vcmpgtfp", VXR(4, 710,0), VXR_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
3105 {"vcmpgtud", VXR(4, 711,0), VXR_MASK
, PPCVEC2
, PPCNONE
, {VD
, VA
, VB
}},
3106 {"efsmul", VX (4, 712), VX_MASK
, PPCEFS
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3107 {"efsdiv", VX (4, 713), VX_MASK
, PPCEFS
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3108 {"vrfim", VX (4, 714), VXVA_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VB
}},
3109 {"efscmpgt", VX (4, 716), VX_MASK
, PPCEFS
|PPCVLE
, PPCNONE
, {CRFD
, RA
, RB
}},
3110 {"efscmplt", VX (4, 717), VX_MASK
, PPCEFS
|PPCVLE
, PPCNONE
, {CRFD
, RA
, RB
}},
3111 {"efscmpeq", VX (4, 718), VX_MASK
, PPCEFS
|PPCVLE
, PPCNONE
, {CRFD
, RA
, RB
}},
3112 {"vupklsh", VX (4, 718), VXVA_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VB
}},
3113 {"efscfd", VX (4, 719), VX_MASK
, PPCEFS
|PPCVLE
, PPCNONE
, {RS
, RB
}},
3114 {"efscfui", VX (4, 720), VX_MASK
, PPCEFS
|PPCVLE
, PPCNONE
, {RS
, RB
}},
3115 {"efscfsi", VX (4, 721), VX_MASK
, PPCEFS
|PPCVLE
, PPCNONE
, {RS
, RB
}},
3116 {"efscfuf", VX (4, 722), VX_MASK
, PPCEFS
|PPCVLE
, PPCNONE
, {RS
, RB
}},
3117 {"efscfsf", VX (4, 723), VX_MASK
, PPCEFS
|PPCVLE
, PPCNONE
, {RS
, RB
}},
3118 {"efsctui", VX (4, 724), VX_MASK
, PPCEFS
|PPCVLE
, PPCNONE
, {RS
, RB
}},
3119 {"efsctsi", VX (4, 725), VX_MASK
, PPCEFS
|PPCVLE
, PPCNONE
, {RS
, RB
}},
3120 {"efsctuf", VX (4, 726), VX_MASK
, PPCEFS
|PPCVLE
, PPCNONE
, {RS
, RB
}},
3121 {"efsctsf", VX (4, 727), VX_MASK
, PPCEFS
|PPCVLE
, PPCNONE
, {RS
, RB
}},
3122 {"efsctuiz", VX (4, 728), VX_MASK
, PPCEFS
|PPCVLE
, PPCNONE
, {RS
, RB
}},
3123 {"nput", APU(4, 364,0), APU_RT_MASK
, PPC405
, PPCNONE
, {RA
, FSL
}},
3124 {"efsctsiz", VX (4, 730), VX_MASK
, PPCEFS
|PPCVLE
, PPCNONE
, {RS
, RB
}},
3125 {"efststgt", VX (4, 732), VX_MASK
, PPCEFS
|PPCVLE
, PPCNONE
, {CRFD
, RA
, RB
}},
3126 {"efststlt", VX (4, 733), VX_MASK
, PPCEFS
|PPCVLE
, PPCNONE
, {CRFD
, RA
, RB
}},
3127 {"efststeq", VX (4, 734), VX_MASK
, PPCEFS
|PPCVLE
, PPCNONE
, {CRFD
, RA
, RB
}},
3128 {"efdadd", VX (4, 736), VX_MASK
, PPCEFS
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3129 {"efdsub", VX (4, 737), VX_MASK
, PPCEFS
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3130 {"efdcfuid", VX (4, 738), VX_MASK
, PPCEFS
|PPCVLE
, PPCNONE
, {RS
, RB
}},
3131 {"efdcfsid", VX (4, 739), VX_MASK
, PPCEFS
|PPCVLE
, PPCNONE
, {RS
, RB
}},
3132 {"efdabs", VX (4, 740), VX_MASK
, PPCEFS
|PPCVLE
, PPCNONE
, {RS
, RA
}},
3133 {"efdnabs", VX (4, 741), VX_MASK
, PPCEFS
|PPCVLE
, PPCNONE
, {RS
, RA
}},
3134 {"efdneg", VX (4, 742), VX_MASK
, PPCEFS
|PPCVLE
, PPCNONE
, {RS
, RA
}},
3135 {"efdmul", VX (4, 744), VX_MASK
, PPCEFS
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3136 {"efddiv", VX (4, 745), VX_MASK
, PPCEFS
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3137 {"efdctuidz", VX (4, 746), VX_MASK
, PPCEFS
|PPCVLE
, PPCNONE
, {RS
, RB
}},
3138 {"efdctsidz", VX (4, 747), VX_MASK
, PPCEFS
|PPCVLE
, PPCNONE
, {RS
, RB
}},
3139 {"efdcmpgt", VX (4, 748), VX_MASK
, PPCEFS
|PPCVLE
, PPCNONE
, {CRFD
, RA
, RB
}},
3140 {"efdcmplt", VX (4, 749), VX_MASK
, PPCEFS
|PPCVLE
, PPCNONE
, {CRFD
, RA
, RB
}},
3141 {"efdcmpeq", VX (4, 750), VX_MASK
, PPCEFS
|PPCVLE
, PPCNONE
, {CRFD
, RA
, RB
}},
3142 {"efdcfs", VX (4, 751), VX_MASK
, PPCEFS
|PPCVLE
, PPCNONE
, {RS
, RB
}},
3143 {"efdcfui", VX (4, 752), VX_MASK
, PPCEFS
|PPCVLE
, PPCNONE
, {RS
, RB
}},
3144 {"efdcfsi", VX (4, 753), VX_MASK
, PPCEFS
|PPCVLE
, PPCNONE
, {RS
, RB
}},
3145 {"efdcfuf", VX (4, 754), VX_MASK
, PPCEFS
|PPCVLE
, PPCNONE
, {RS
, RB
}},
3146 {"efdcfsf", VX (4, 755), VX_MASK
, PPCEFS
|PPCVLE
, PPCNONE
, {RS
, RB
}},
3147 {"efdctui", VX (4, 756), VX_MASK
, PPCEFS
|PPCVLE
, PPCNONE
, {RS
, RB
}},
3148 {"efdctsi", VX (4, 757), VX_MASK
, PPCEFS
|PPCVLE
, PPCNONE
, {RS
, RB
}},
3149 {"efdctuf", VX (4, 758), VX_MASK
, PPCEFS
|PPCVLE
, PPCNONE
, {RS
, RB
}},
3150 {"efdctsf", VX (4, 759), VX_MASK
, PPCEFS
|PPCVLE
, PPCNONE
, {RS
, RB
}},
3151 {"efdctuiz", VX (4, 760), VX_MASK
, PPCEFS
|PPCVLE
, PPCNONE
, {RS
, RB
}},
3152 {"ncput", APU(4, 380,0), APU_RT_MASK
, PPC405
, PPCNONE
, {RA
, FSL
}},
3153 {"efdctsiz", VX (4, 762), VX_MASK
, PPCEFS
|PPCVLE
, PPCNONE
, {RS
, RB
}},
3154 {"efdtstgt", VX (4, 764), VX_MASK
, PPCEFS
|PPCVLE
, PPCNONE
, {CRFD
, RA
, RB
}},
3155 {"efdtstlt", VX (4, 765), VX_MASK
, PPCEFS
|PPCVLE
, PPCNONE
, {CRFD
, RA
, RB
}},
3156 {"efdtsteq", VX (4, 766), VX_MASK
, PPCEFS
|PPCVLE
, PPCNONE
, {CRFD
, RA
, RB
}},
3157 {"evlddx", VX (4, 768), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3158 {"vaddsbs", VX (4, 768), VX_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
3159 {"evldd", VX (4, 769), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, EVUIMM_8
, RA
}},
3160 {"evldwx", VX (4, 770), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3161 {"vminsb", VX (4, 770), VX_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
3162 {"evldw", VX (4, 771), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, EVUIMM_8
, RA
}},
3163 {"evldhx", VX (4, 772), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3164 {"vsrab", VX (4, 772), VX_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
3165 {"evldh", VX (4, 773), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, EVUIMM_8
, RA
}},
3166 {"vcmpgtsb", VXR(4, 774,0), VXR_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
3167 {"evlhhesplatx",VX (4, 776), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3168 {"vmulesb", VX (4, 776), VX_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
3169 {"evlhhesplat", VX (4, 777), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, EVUIMM_2
, RA
}},
3170 {"vcfux", VX (4, 778), VX_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VB
, UIMM
}},
3171 {"vcuxwfp", VX (4, 778), VX_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VB
, UIMM
}},
3172 {"evlhhousplatx",VX(4, 780), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3173 {"vspltisb", VX (4, 780), VXVB_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, SIMM
}},
3174 {"evlhhousplat",VX (4, 781), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, EVUIMM_2
, RA
}},
3175 {"evlhhossplatx",VX(4, 782), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3176 {"vpkpx", VX (4, 782), VX_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
3177 {"evlhhossplat",VX (4, 783), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, EVUIMM_2
, RA
}},
3178 {"mullhwu", XRC(4, 392,0), X_MASK
, MULHW
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
3179 {"evlwhex", VX (4, 784), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3180 {"mullhwu.", XRC(4, 392,1), X_MASK
, MULHW
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
3181 {"evlwhe", VX (4, 785), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, EVUIMM_4
, RA
}},
3182 {"evlwhoux", VX (4, 788), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3183 {"evlwhou", VX (4, 789), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, EVUIMM_4
, RA
}},
3184 {"evlwhosx", VX (4, 790), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3185 {"evlwhos", VX (4, 791), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, EVUIMM_4
, RA
}},
3186 {"maclhwu", XO (4, 396,0,0),XO_MASK
, MULHW
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
3187 {"evlwwsplatx", VX (4, 792), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3188 {"maclhwu.", XO (4, 396,0,1),XO_MASK
, MULHW
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
3189 {"evlwwsplat", VX (4, 793), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, EVUIMM_4
, RA
}},
3190 {"evlwhsplatx", VX (4, 796), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3191 {"evlwhsplat", VX (4, 797), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, EVUIMM_4
, RA
}},
3192 {"evstddx", VX (4, 800), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3193 {"evstdd", VX (4, 801), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, EVUIMM_8
, RA
}},
3194 {"evstdwx", VX (4, 802), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3195 {"evstdw", VX (4, 803), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, EVUIMM_8
, RA
}},
3196 {"evstdhx", VX (4, 804), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3197 {"evstdh", VX (4, 805), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, EVUIMM_8
, RA
}},
3198 {"evstwhex", VX (4, 816), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3199 {"evstwhe", VX (4, 817), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, EVUIMM_4
, RA
}},
3200 {"evstwhox", VX (4, 820), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3201 {"evstwho", VX (4, 821), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, EVUIMM_4
, RA
}},
3202 {"evstwwex", VX (4, 824), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3203 {"evstwwe", VX (4, 825), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, EVUIMM_4
, RA
}},
3204 {"evstwwox", VX (4, 828), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3205 {"evstwwo", VX (4, 829), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, EVUIMM_4
, RA
}},
3206 {"vaddshs", VX (4, 832), VX_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
3207 {"vminsh", VX (4, 834), VX_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
3208 {"vsrah", VX (4, 836), VX_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
3209 {"vcmpgtsh", VXR(4, 838,0), VXR_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
3210 {"vmulesh", VX (4, 840), VX_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
3211 {"vcfsx", VX (4, 842), VX_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VB
, UIMM
}},
3212 {"vcsxwfp", VX (4, 842), VX_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VB
, UIMM
}},
3213 {"vspltish", VX (4, 844), VXVB_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, SIMM
}},
3214 {"vupkhpx", VX (4, 846), VXVA_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VB
}},
3215 {"mullhw", XRC(4, 424,0), X_MASK
, MULHW
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
3216 {"mullhw.", XRC(4, 424,1), X_MASK
, MULHW
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
3217 {"maclhw", XO (4, 428,0,0),XO_MASK
, MULHW
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
3218 {"maclhw.", XO (4, 428,0,1),XO_MASK
, MULHW
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
3219 {"nmaclhw", XO (4, 430,0,0),XO_MASK
, MULHW
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
3220 {"nmaclhw.", XO (4, 430,0,1),XO_MASK
, MULHW
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
3221 {"vaddsws", VX (4, 896), VX_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
3222 {"vminsw", VX (4, 898), VX_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
3223 {"vsraw", VX (4, 900), VX_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
3224 {"vcmpgtsw", VXR(4, 902,0), VXR_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
3225 {"vmulesw", VX (4, 904), VX_MASK
, PPCVEC2
, PPCNONE
, {VD
, VA
, VB
}},
3226 {"vctuxs", VX (4, 906), VX_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VB
, UIMM
}},
3227 {"vcfpuxws", VX (4, 906), VX_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VB
, UIMM
}},
3228 {"vspltisw", VX (4, 908), VXVB_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, SIMM
}},
3229 {"maclhwsu", XO (4, 460,0,0),XO_MASK
, MULHW
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
3230 {"maclhwsu.", XO (4, 460,0,1),XO_MASK
, MULHW
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
3231 {"vminsd", VX (4, 962), VX_MASK
, PPCVEC2
, PPCNONE
, {VD
, VA
, VB
}},
3232 {"vsrad", VX (4, 964), VX_MASK
, PPCVEC2
, PPCNONE
, {VD
, VA
, VB
}},
3233 {"vcmpbfp", VXR(4, 966,0), VXR_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
3234 {"vcmpgtsd", VXR(4, 967,0), VXR_MASK
, PPCVEC2
, PPCNONE
, {VD
, VA
, VB
}},
3235 {"vctsxs", VX (4, 970), VX_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VB
, UIMM
}},
3236 {"vcfpsxws", VX (4, 970), VX_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VB
, UIMM
}},
3237 {"vupklpx", VX (4, 974), VXVA_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VB
}},
3238 {"maclhws", XO (4, 492,0,0),XO_MASK
, MULHW
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
3239 {"maclhws.", XO (4, 492,0,1),XO_MASK
, MULHW
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
3240 {"nmaclhws", XO (4, 494,0,0),XO_MASK
, MULHW
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
3241 {"nmaclhws.", XO (4, 494,0,1),XO_MASK
, MULHW
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
3242 {"vsububm", VX (4,1024), VX_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
3243 {"bcdadd.", VX (4,1025), VXPS_MASK
, PPCVEC2
, PPCNONE
, {VD
, VA
, VB
, PS
}},
3244 {"vavgub", VX (4,1026), VX_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
3245 {"vabsdub", VX (4,1027), VX_MASK
, PPCVEC2
, PPCNONE
, {VD
, VA
, VB
}},
3246 {"evmhessf", VX (4,1027), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3247 {"vand", VX (4,1028), VX_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
3248 {"vcmpequb.", VXR(4, 6,1), VXR_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
3249 {"udi0fcm.", APU(4, 515,0), APU_MASK
, PPC405
|PPC440
, PPC476
, {URT
, URA
, URB
}},
3250 {"udi0fcm", APU(4, 515,1), APU_MASK
, PPC405
|PPC440
, PPC476
, {URT
, URA
, URB
}},
3251 {"evmhossf", VX (4,1031), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3252 {"vpmsumb", VX (4,1032), VX_MASK
, PPCVEC2
, PPCNONE
, {VD
, VA
, VB
}},
3253 {"evmheumi", VX (4,1032), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3254 {"evmhesmi", VX (4,1033), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3255 {"vmaxfp", VX (4,1034), VX_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
3256 {"evmhesmf", VX (4,1035), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3257 {"evmhoumi", VX (4,1036), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3258 {"vslo", VX (4,1036), VX_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
3259 {"evmhosmi", VX (4,1037), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3260 {"evmhosmf", VX (4,1039), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3261 {"machhwuo", XO (4, 12,1,0),XO_MASK
, MULHW
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
3262 {"machhwuo.", XO (4, 12,1,1),XO_MASK
, MULHW
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
3263 {"ps_merge00", XOPS(4,528,0), XOPS_MASK
, PPCPS
, PPCNONE
, {FRT
, FRA
, FRB
}},
3264 {"ps_merge00.", XOPS(4,528,1), XOPS_MASK
, PPCPS
, PPCNONE
, {FRT
, FRA
, FRB
}},
3265 {"evmhessfa", VX (4,1059), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3266 {"evmhossfa", VX (4,1063), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3267 {"evmheumia", VX (4,1064), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3268 {"evmhesmia", VX (4,1065), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3269 {"evmhesmfa", VX (4,1067), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3270 {"evmhoumia", VX (4,1068), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3271 {"evmhosmia", VX (4,1069), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3272 {"evmhosmfa", VX (4,1071), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3273 {"vsubuhm", VX (4,1088), VX_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
3274 {"bcdsub.", VX (4,1089), VXPS_MASK
, PPCVEC2
, PPCNONE
, {VD
, VA
, VB
, PS
}},
3275 {"vavguh", VX (4,1090), VX_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
3276 {"vabsduh", VX (4,1091), VX_MASK
, PPCVEC2
, PPCNONE
, {VD
, VA
, VB
}},
3277 {"vandc", VX (4,1092), VX_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
3278 {"vcmpequh.", VXR(4, 70,1), VXR_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
3279 {"udi1fcm.", APU(4, 547,0), APU_MASK
, PPC405
|PPC440
, PPC476
, {URT
, URA
, URB
}},
3280 {"udi1fcm", APU(4, 547,1), APU_MASK
, PPC405
|PPC440
, PPC476
, {URT
, URA
, URB
}},
3281 {"evmwhssf", VX (4,1095), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3282 {"vpmsumh", VX (4,1096), VX_MASK
, PPCVEC2
, PPCNONE
, {VD
, VA
, VB
}},
3283 {"evmwlumi", VX (4,1096), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3284 {"vminfp", VX (4,1098), VX_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
3285 {"evmwhumi", VX (4,1100), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3286 {"vsro", VX (4,1100), VX_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
3287 {"evmwhsmi", VX (4,1101), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3288 {"vpkudum", VX (4,1102), VX_MASK
, PPCVEC2
, PPCNONE
, {VD
, VA
, VB
}},
3289 {"evmwhsmf", VX (4,1103), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3290 {"evmwssf", VX (4,1107), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3291 {"machhwo", XO (4, 44,1,0),XO_MASK
, MULHW
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
3292 {"evmwumi", VX (4,1112), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3293 {"machhwo.", XO (4, 44,1,1),XO_MASK
, MULHW
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
3294 {"evmwsmi", VX (4,1113), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3295 {"evmwsmf", VX (4,1115), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3296 {"nmachhwo", XO (4, 46,1,0),XO_MASK
, MULHW
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
3297 {"nmachhwo.", XO (4, 46,1,1),XO_MASK
, MULHW
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
3298 {"ps_merge01", XOPS(4,560,0), XOPS_MASK
, PPCPS
, PPCNONE
, {FRT
, FRA
, FRB
}},
3299 {"ps_merge01.", XOPS(4,560,1), XOPS_MASK
, PPCPS
, PPCNONE
, {FRT
, FRA
, FRB
}},
3300 {"evmwhssfa", VX (4,1127), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3301 {"evmwlumia", VX (4,1128), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3302 {"evmwhumia", VX (4,1132), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3303 {"evmwhsmia", VX (4,1133), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3304 {"evmwhsmfa", VX (4,1135), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3305 {"evmwssfa", VX (4,1139), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3306 {"evmwumia", VX (4,1144), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3307 {"evmwsmia", VX (4,1145), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3308 {"evmwsmfa", VX (4,1147), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3309 {"vsubuwm", VX (4,1152), VX_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
3310 {"vavguw", VX (4,1154), VX_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
3311 {"vabsduw", VX (4,1155), VX_MASK
, PPCVEC2
, PPCNONE
, {VD
, VA
, VB
}},
3312 {"vmr", VX (4,1156), VX_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VBA
}},
3313 {"vor", VX (4,1156), VX_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
3314 {"vpmsumw", VX (4,1160), VX_MASK
, PPCVEC2
, PPCNONE
, {VD
, VA
, VB
}},
3315 {"vcmpequw.", VXR(4, 134,1), VXR_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
3316 {"udi2fcm.", APU(4, 579,0), APU_MASK
, PPC405
|PPC440
, PPC476
, {URT
, URA
, URB
}},
3317 {"udi2fcm", APU(4, 579,1), APU_MASK
, PPC405
|PPC440
, PPC476
, {URT
, URA
, URB
}},
3318 {"machhwsuo", XO (4, 76,1,0),XO_MASK
, MULHW
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
3319 {"machhwsuo.", XO (4, 76,1,1),XO_MASK
, MULHW
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
3320 {"ps_merge10", XOPS(4,592,0), XOPS_MASK
, PPCPS
, PPCNONE
, {FRT
, FRA
, FRB
}},
3321 {"ps_merge10.", XOPS(4,592,1), XOPS_MASK
, PPCPS
, PPCNONE
, {FRT
, FRA
, FRB
}},
3322 {"vsubudm", VX (4,1216), VX_MASK
, PPCVEC2
, PPCNONE
, {VD
, VA
, VB
}},
3323 {"evaddusiaaw", VX (4,1216), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
}},
3324 {"evaddssiaaw", VX (4,1217), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
}},
3325 {"evsubfusiaaw",VX (4,1218), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
}},
3326 {"evsubfssiaaw",VX (4,1219), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
}},
3327 {"evmra", VX (4,1220), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
}},
3328 {"vxor", VX (4,1220), VX_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
3329 {"evdivws", VX (4,1222), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3330 {"vcmpeqfp.", VXR(4, 198,1), VXR_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
3331 {"udi3fcm.", APU(4, 611,0), APU_MASK
, PPC405
|PPC440
, PPC476
, {URT
, URA
, URB
}},
3332 {"vcmpequd.", VXR(4, 199,1), VXR_MASK
, PPCVEC2
, PPCNONE
, {VD
, VA
, VB
}},
3333 {"udi3fcm", APU(4, 611,1), APU_MASK
, PPC405
|PPC440
, PPC476
, {URT
, URA
, URB
}},
3334 {"evdivwu", VX (4,1223), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3335 {"vpmsumd", VX (4,1224), VX_MASK
, PPCVEC2
, PPCNONE
, {VD
, VA
, VB
}},
3336 {"evaddumiaaw", VX (4,1224), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
}},
3337 {"evaddsmiaaw", VX (4,1225), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
}},
3338 {"evsubfumiaaw",VX (4,1226), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
}},
3339 {"evsubfsmiaaw",VX (4,1227), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
}},
3340 {"vpkudus", VX (4,1230), VX_MASK
, PPCVEC2
, PPCNONE
, {VD
, VA
, VB
}},
3341 {"machhwso", XO (4, 108,1,0),XO_MASK
, MULHW
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
3342 {"machhwso.", XO (4, 108,1,1),XO_MASK
, MULHW
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
3343 {"nmachhwso", XO (4, 110,1,0),XO_MASK
, MULHW
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
3344 {"nmachhwso.", XO (4, 110,1,1),XO_MASK
, MULHW
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
3345 {"ps_merge11", XOPS(4,624,0), XOPS_MASK
, PPCPS
, PPCNONE
, {FRT
, FRA
, FRB
}},
3346 {"ps_merge11.", XOPS(4,624,1), XOPS_MASK
, PPCPS
, PPCNONE
, {FRT
, FRA
, FRB
}},
3347 {"vsubuqm", VX (4,1280), VX_MASK
, PPCVEC2
, PPCNONE
, {VD
, VA
, VB
}},
3348 {"evmheusiaaw", VX (4,1280), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3349 {"evmhessiaaw", VX (4,1281), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3350 {"vavgsb", VX (4,1282), VX_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
3351 {"evmhessfaaw", VX (4,1283), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3352 {"evmhousiaaw", VX (4,1284), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3353 {"vnot", VX (4,1284), VX_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VBA
}},
3354 {"vnor", VX (4,1284), VX_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
3355 {"evmhossiaaw", VX (4,1285), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3356 {"udi4fcm.", APU(4, 643,0), APU_MASK
, PPC405
|PPC440
, PPC476
, {URT
, URA
, URB
}},
3357 {"udi4fcm", APU(4, 643,1), APU_MASK
, PPC405
|PPC440
, PPC476
, {URT
, URA
, URB
}},
3358 {"evmhossfaaw", VX (4,1287), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3359 {"evmheumiaaw", VX (4,1288), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3360 {"vcipher", VX (4,1288), VX_MASK
, PPCVEC2
, PPCNONE
, {VD
, VA
, VB
}},
3361 {"vcipherlast", VX (4,1289), VX_MASK
, PPCVEC2
, PPCNONE
, {VD
, VA
, VB
}},
3362 {"evmhesmiaaw", VX (4,1289), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3363 {"evmhesmfaaw", VX (4,1291), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3364 {"vgbbd", VX (4,1292), VXVA_MASK
, PPCVEC2
, PPCNONE
, {VD
, VB
}},
3365 {"evmhoumiaaw", VX (4,1292), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3366 {"evmhosmiaaw", VX (4,1293), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3367 {"evmhosmfaaw", VX (4,1295), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3368 {"macchwuo", XO (4, 140,1,0),XO_MASK
, MULHW
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
3369 {"macchwuo.", XO (4, 140,1,1),XO_MASK
, MULHW
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
3370 {"evmhegumiaa", VX (4,1320), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3371 {"evmhegsmiaa", VX (4,1321), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3372 {"evmhegsmfaa", VX (4,1323), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3373 {"evmhogumiaa", VX (4,1324), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3374 {"evmhogsmiaa", VX (4,1325), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3375 {"evmhogsmfaa", VX (4,1327), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3376 {"vsubcuq", VX (4,1344), VX_MASK
, PPCVEC2
, PPCNONE
, {VD
, VA
, VB
}},
3377 {"evmwlusiaaw", VX (4,1344), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3378 {"evmwlssiaaw", VX (4,1345), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3379 {"vavgsh", VX (4,1346), VX_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
3380 {"vorc", VX (4,1348), VX_MASK
, PPCVEC2
, PPCNONE
, {VD
, VA
, VB
}},
3381 {"udi5fcm.", APU(4, 675,0), APU_MASK
, PPC405
|PPC440
, PPC476
, {URT
, URA
, URB
}},
3382 {"udi5fcm", APU(4, 675,1), APU_MASK
, PPC405
|PPC440
, PPC476
, {URT
, URA
, URB
}},
3383 {"vncipher", VX (4,1352), VX_MASK
, PPCVEC2
, PPCNONE
, {VD
, VA
, VB
}},
3384 {"evmwlumiaaw", VX (4,1352), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3385 {"vncipherlast",VX (4,1353), VX_MASK
, PPCVEC2
, PPCNONE
, {VD
, VA
, VB
}},
3386 {"evmwlsmiaaw", VX (4,1353), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3387 {"vbpermq", VX (4,1356), VX_MASK
, PPCVEC2
, PPCNONE
, {VD
, VA
, VB
}},
3388 {"vpksdus", VX (4,1358), VX_MASK
, PPCVEC2
, PPCNONE
, {VD
, VA
, VB
}},
3389 {"evmwssfaa", VX (4,1363), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3390 {"macchwo", XO (4, 172,1,0),XO_MASK
, MULHW
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
3391 {"evmwumiaa", VX (4,1368), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3392 {"macchwo.", XO (4, 172,1,1),XO_MASK
, MULHW
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
3393 {"evmwsmiaa", VX (4,1369), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3394 {"evmwsmfaa", VX (4,1371), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3395 {"nmacchwo", XO (4, 174,1,0),XO_MASK
, MULHW
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
3396 {"nmacchwo.", XO (4, 174,1,1),XO_MASK
, MULHW
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
3397 {"evmheusianw", VX (4,1408), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3398 {"vsubcuw", VX (4,1408), VX_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
3399 {"evmhessianw", VX (4,1409), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3400 {"vavgsw", VX (4,1410), VX_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
3401 {"evmhessfanw", VX (4,1411), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3402 {"vnand", VX (4,1412), VX_MASK
, PPCVEC2
, PPCNONE
, {VD
, VA
, VB
}},
3403 {"evmhousianw", VX (4,1412), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3404 {"evmhossianw", VX (4,1413), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3405 {"udi6fcm.", APU(4, 707,0), APU_MASK
, PPC405
|PPC440
, PPC476
, {URT
, URA
, URB
}},
3406 {"udi6fcm", APU(4, 707,1), APU_MASK
, PPC405
|PPC440
, PPC476
, {URT
, URA
, URB
}},
3407 {"evmhossfanw", VX (4,1415), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3408 {"evmheumianw", VX (4,1416), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3409 {"evmhesmianw", VX (4,1417), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3410 {"evmhesmfanw", VX (4,1419), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3411 {"evmhoumianw", VX (4,1420), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3412 {"evmhosmianw", VX (4,1421), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3413 {"evmhosmfanw", VX (4,1423), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3414 {"macchwsuo", XO (4, 204,1,0),XO_MASK
, MULHW
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
3415 {"macchwsuo.", XO (4, 204,1,1),XO_MASK
, MULHW
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
3416 {"evmhegumian", VX (4,1448), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3417 {"evmhegsmian", VX (4,1449), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3418 {"evmhegsmfan", VX (4,1451), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3419 {"evmhogumian", VX (4,1452), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3420 {"evmhogsmian", VX (4,1453), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3421 {"evmhogsmfan", VX (4,1455), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3422 {"evmwlusianw", VX (4,1472), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3423 {"evmwlssianw", VX (4,1473), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3424 {"vsld", VX (4,1476), VX_MASK
, PPCVEC2
, PPCNONE
, {VD
, VA
, VB
}},
3425 {"vcmpgefp.", VXR(4, 454,1), VXR_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
3426 {"udi7fcm.", APU(4, 739,0), APU_MASK
, PPC405
|PPC440
, PPC476
, {URT
, URA
, URB
}},
3427 {"udi7fcm", APU(4, 739,1), APU_MASK
, PPC405
|PPC440
, PPC476
, {URT
, URA
, URB
}},
3428 {"vsbox", VX (4,1480), VXVB_MASK
, PPCVEC2
, PPCNONE
, {VD
, VA
}},
3429 {"evmwlumianw", VX (4,1480), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3430 {"evmwlsmianw", VX (4,1481), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3431 {"vpksdss", VX (4,1486), VX_MASK
, PPCVEC2
, PPCNONE
, {VD
, VA
, VB
}},
3432 {"evmwssfan", VX (4,1491), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3433 {"macchwso", XO (4, 236,1,0),XO_MASK
, MULHW
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
3434 {"evmwumian", VX (4,1496), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3435 {"macchwso.", XO (4, 236,1,1),XO_MASK
, MULHW
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
3436 {"evmwsmian", VX (4,1497), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3437 {"evmwsmfan", VX (4,1499), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3438 {"nmacchwso", XO (4, 238,1,0),XO_MASK
, MULHW
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
3439 {"nmacchwso.", XO (4, 238,1,1),XO_MASK
, MULHW
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
3440 {"vsububs", VX (4,1536), VX_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
3441 {"mfvscr", VX (4,1540), VXVAVB_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
}},
3442 {"vcmpgtub.", VXR(4, 518,1), VXR_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
3443 {"udi8fcm.", APU(4, 771,0), APU_MASK
, PPC440
, PPC476
, {URT
, URA
, URB
}},
3444 {"udi8fcm", APU(4, 771,1), APU_MASK
, PPC440
, PPC476
, {URT
, URA
, URB
}},
3445 {"vsum4ubs", VX (4,1544), VX_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
3446 {"vsubuhs", VX (4,1600), VX_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
3447 {"mtvscr", VX (4,1604), VXVDVA_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VB
}},
3448 {"vcmpgtuh.", VXR(4, 582,1), VXR_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
3449 {"vsum4shs", VX (4,1608), VX_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
3450 {"udi9fcm.", APU(4, 804,0), APU_MASK
, PPC440
, PPC476
, {URT
, URA
, URB
}},
3451 {"udi9fcm", APU(4, 804,1), APU_MASK
, PPC440
, PPC476
, {URT
, URA
, URB
}},
3452 {"vupkhsw", VX (4,1614), VXVA_MASK
, PPCVEC2
, PPCNONE
, {VD
, VB
}},
3453 {"vsubuws", VX (4,1664), VX_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
3454 {"vshasigmaw", VX (4,1666), VX_MASK
, PPCVEC2
, PPCNONE
, {VD
, VA
, ST
, SIX
}},
3455 {"veqv", VX (4,1668), VX_MASK
, PPCVEC2
, PPCNONE
, {VD
, VA
, VB
}},
3456 {"vcmpgtuw.", VXR(4, 646,1), VXR_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
3457 {"udi10fcm.", APU(4, 835,0), APU_MASK
, PPC440
, PPC476
, {URT
, URA
, URB
}},
3458 {"udi10fcm", APU(4, 835,1), APU_MASK
, PPC440
, PPC476
, {URT
, URA
, URB
}},
3459 {"vsum2sws", VX (4,1672), VX_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
3460 {"vmrgow", VX (4,1676), VX_MASK
, PPCVEC2
, PPCNONE
, {VD
, VA
, VB
}},
3461 {"vshasigmad", VX (4,1730), VX_MASK
, PPCVEC2
, PPCNONE
, {VD
, VA
, ST
, SIX
}},
3462 {"vsrd", VX (4,1732), VX_MASK
, PPCVEC2
, PPCNONE
, {VD
, VA
, VB
}},
3463 {"vcmpgtfp.", VXR(4, 710,1), VXR_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
3464 {"udi11fcm.", APU(4, 867,0), APU_MASK
, PPC440
, PPC476
, {URT
, URA
, URB
}},
3465 {"vcmpgtud.", VXR(4, 711,1), VXR_MASK
, PPCVEC2
, PPCNONE
, {VD
, VA
, VB
}},
3466 {"udi11fcm", APU(4, 867,1), APU_MASK
, PPC440
, PPC476
, {URT
, URA
, URB
}},
3467 {"vupklsw", VX (4,1742), VXVA_MASK
, PPCVEC2
, PPCNONE
, {VD
, VB
}},
3468 {"vsubsbs", VX (4,1792), VX_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
3469 {"vclzb", VX (4,1794), VXVA_MASK
, PPCVEC2
, PPCNONE
, {VD
, VB
}},
3470 {"vpopcntb", VX (4,1795), VXVA_MASK
, PPCVEC2
, PPCNONE
, {VD
, VB
}},
3471 {"vcmpgtsb.", VXR(4, 774,1), VXR_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
3472 {"udi12fcm.", APU(4, 899,0), APU_MASK
, PPC440
, PPC476
, {URT
, URA
, URB
}},
3473 {"udi12fcm", APU(4, 899,1), APU_MASK
, PPC440
, PPC476
, {URT
, URA
, URB
}},
3474 {"vsum4sbs", VX (4,1800), VX_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
3475 {"maclhwuo", XO (4, 396,1,0),XO_MASK
, MULHW
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
3476 {"maclhwuo.", XO (4, 396,1,1),XO_MASK
, MULHW
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
3477 {"vsubshs", VX (4,1856), VX_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
3478 {"vclzh", VX (4,1858), VXVA_MASK
, PPCVEC2
, PPCNONE
, {VD
, VB
}},
3479 {"vpopcnth", VX (4,1859), VXVA_MASK
, PPCVEC2
, PPCNONE
, {VD
, VB
}},
3480 {"vcmpgtsh.", VXR(4, 838,1), VXR_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
3481 {"udi13fcm.", APU(4, 931,0), APU_MASK
, PPC440
, PPC476
, {URT
, URA
, URB
}},
3482 {"udi13fcm", APU(4, 931,1), APU_MASK
, PPC440
, PPC476
, {URT
, URA
, URB
}},
3483 {"maclhwo", XO (4, 428,1,0),XO_MASK
, MULHW
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
3484 {"maclhwo.", XO (4, 428,1,1),XO_MASK
, MULHW
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
3485 {"nmaclhwo", XO (4, 430,1,0),XO_MASK
, MULHW
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
3486 {"nmaclhwo.", XO (4, 430,1,1),XO_MASK
, MULHW
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
3487 {"vsubsws", VX (4,1920), VX_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
3488 {"vclzw", VX (4,1922), VXVA_MASK
, PPCVEC2
, PPCNONE
, {VD
, VB
}},
3489 {"vpopcntw", VX (4,1923), VXVA_MASK
, PPCVEC2
, PPCNONE
, {VD
, VB
}},
3490 {"vcmpgtsw.", VXR(4, 902,1), VXR_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
3491 {"udi14fcm.", APU(4, 963,0), APU_MASK
, PPC440
, PPC476
, {URT
, URA
, URB
}},
3492 {"udi14fcm", APU(4, 963,1), APU_MASK
, PPC440
, PPC476
, {URT
, URA
, URB
}},
3493 {"vsumsws", VX (4,1928), VX_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
3494 {"vmrgew", VX (4,1932), VX_MASK
, PPCVEC2
, PPCNONE
, {VD
, VA
, VB
}},
3495 {"maclhwsuo", XO (4, 460,1,0),XO_MASK
, MULHW
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
3496 {"maclhwsuo.", XO (4, 460,1,1),XO_MASK
, MULHW
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
3497 {"vclzd", VX (4,1986), VXVA_MASK
, PPCVEC2
, PPCNONE
, {VD
, VB
}},
3498 {"vpopcntd", VX (4,1987), VXVA_MASK
, PPCVEC2
, PPCNONE
, {VD
, VB
}},
3499 {"vcmpbfp.", VXR(4, 966,1), VXR_MASK
, PPCVEC
, PPCNONE
, {VD
, VA
, VB
}},
3500 {"udi15fcm.", APU(4, 995,0), APU_MASK
, PPC440
, PPC476
, {URT
, URA
, URB
}},
3501 {"vcmpgtsd.", VXR(4, 967,1), VXR_MASK
, PPCVEC2
, PPCNONE
, {VD
, VA
, VB
}},
3502 {"udi15fcm", APU(4, 995,1), APU_MASK
, PPC440
, PPC476
, {URT
, URA
, URB
}},
3503 {"maclhwso", XO (4, 492,1,0),XO_MASK
, MULHW
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
3504 {"maclhwso.", XO (4, 492,1,1),XO_MASK
, MULHW
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
3505 {"nmaclhwso", XO (4, 494,1,0),XO_MASK
, MULHW
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
3506 {"nmaclhwso.", XO (4, 494,1,1),XO_MASK
, MULHW
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
3507 {"dcbz_l", X (4,1014), XRT_MASK
, PPCPS
, PPCNONE
, {RA
, RB
}},
3509 {"mulli", OP(7), OP_MASK
, PPCCOM
, PPCNONE
, {RT
, RA
, SI
}},
3510 {"muli", OP(7), OP_MASK
, PWRCOM
, PPCNONE
, {RT
, RA
, SI
}},
3512 {"subfic", OP(8), OP_MASK
, PPCCOM
, PPCNONE
, {RT
, RA
, SI
}},
3513 {"sfi", OP(8), OP_MASK
, PWRCOM
, PPCNONE
, {RT
, RA
, SI
}},
3515 {"dozi", OP(9), OP_MASK
, M601
, PPCNONE
, {RT
, RA
, SI
}},
3517 {"cmplwi", OPL(10,0), OPL_MASK
, PPCCOM
, PPCNONE
, {OBF
, RA
, UISIGNOPT
}},
3518 {"cmpldi", OPL(10,1), OPL_MASK
, PPC64
, PPCNONE
, {OBF
, RA
, UISIGNOPT
}},
3519 {"cmpli", OP(10), OP_MASK
, PPC
, PPCNONE
, {BF
, L
, RA
, UISIGNOPT
}},
3520 {"cmpli", OP(10), OP_MASK
, PWRCOM
, PPC
, {BF
, RA
, UISIGNOPT
}},
3522 {"cmpwi", OPL(11,0), OPL_MASK
, PPCCOM
, PPCNONE
, {OBF
, RA
, SI
}},
3523 {"cmpdi", OPL(11,1), OPL_MASK
, PPC64
, PPCNONE
, {OBF
, RA
, SI
}},
3524 {"cmpi", OP(11), OP_MASK
, PPC
, PPCNONE
, {BF
, L
, RA
, SI
}},
3525 {"cmpi", OP(11), OP_MASK
, PWRCOM
, PPC
, {BF
, RA
, SI
}},
3527 {"addic", OP(12), OP_MASK
, PPCCOM
, PPCNONE
, {RT
, RA
, SI
}},
3528 {"ai", OP(12), OP_MASK
, PWRCOM
, PPCNONE
, {RT
, RA
, SI
}},
3529 {"subic", OP(12), OP_MASK
, PPCCOM
, PPCNONE
, {RT
, RA
, NSI
}},
3531 {"addic.", OP(13), OP_MASK
, PPCCOM
, PPCNONE
, {RT
, RA
, SI
}},
3532 {"ai.", OP(13), OP_MASK
, PWRCOM
, PPCNONE
, {RT
, RA
, SI
}},
3533 {"subic.", OP(13), OP_MASK
, PPCCOM
, PPCNONE
, {RT
, RA
, NSI
}},
3535 {"li", OP(14), DRA_MASK
, PPCCOM
, PPCNONE
, {RT
, SI
}},
3536 {"lil", OP(14), DRA_MASK
, PWRCOM
, PPCNONE
, {RT
, SI
}},
3537 {"addi", OP(14), OP_MASK
, PPCCOM
, PPCNONE
, {RT
, RA0
, SI
}},
3538 {"cal", OP(14), OP_MASK
, PWRCOM
, PPCNONE
, {RT
, D
, RA0
}},
3539 {"subi", OP(14), OP_MASK
, PPCCOM
, PPCNONE
, {RT
, RA0
, NSI
}},
3540 {"la", OP(14), OP_MASK
, PPCCOM
, PPCNONE
, {RT
, D
, RA0
}},
3542 {"lis", OP(15), DRA_MASK
, PPCCOM
, PPCNONE
, {RT
, SISIGNOPT
}},
3543 {"liu", OP(15), DRA_MASK
, PWRCOM
, PPCNONE
, {RT
, SISIGNOPT
}},
3544 {"addis", OP(15), OP_MASK
, PPCCOM
, PPCNONE
, {RT
, RA0
, SISIGNOPT
}},
3545 {"cau", OP(15), OP_MASK
, PWRCOM
, PPCNONE
, {RT
, RA0
, SISIGNOPT
}},
3546 {"subis", OP(15), OP_MASK
, PPCCOM
, PPCNONE
, {RT
, RA0
, NSI
}},
3548 {"bdnz-", BBO(16,BODNZ
,0,0), BBOATBI_MASK
, PPCCOM
, PPCNONE
, {BDM
}},
3549 {"bdnz+", BBO(16,BODNZ
,0,0), BBOATBI_MASK
, PPCCOM
, PPCNONE
, {BDP
}},
3550 {"bdnz", BBO(16,BODNZ
,0,0), BBOATBI_MASK
, PPCCOM
, PPCNONE
, {BD
}},
3551 {"bdn", BBO(16,BODNZ
,0,0), BBOATBI_MASK
, PWRCOM
, PPCNONE
, {BD
}},
3552 {"bdnzl-", BBO(16,BODNZ
,0,1), BBOATBI_MASK
, PPCCOM
, PPCNONE
, {BDM
}},
3553 {"bdnzl+", BBO(16,BODNZ
,0,1), BBOATBI_MASK
, PPCCOM
, PPCNONE
, {BDP
}},
3554 {"bdnzl", BBO(16,BODNZ
,0,1), BBOATBI_MASK
, PPCCOM
, PPCNONE
, {BD
}},
3555 {"bdnl", BBO(16,BODNZ
,0,1), BBOATBI_MASK
, PWRCOM
, PPCNONE
, {BD
}},
3556 {"bdnza-", BBO(16,BODNZ
,1,0), BBOATBI_MASK
, PPCCOM
, PPCNONE
, {BDMA
}},
3557 {"bdnza+", BBO(16,BODNZ
,1,0), BBOATBI_MASK
, PPCCOM
, PPCNONE
, {BDPA
}},
3558 {"bdnza", BBO(16,BODNZ
,1,0), BBOATBI_MASK
, PPCCOM
, PPCNONE
, {BDA
}},
3559 {"bdna", BBO(16,BODNZ
,1,0), BBOATBI_MASK
, PWRCOM
, PPCNONE
, {BDA
}},
3560 {"bdnzla-", BBO(16,BODNZ
,1,1), BBOATBI_MASK
, PPCCOM
, PPCNONE
, {BDMA
}},
3561 {"bdnzla+", BBO(16,BODNZ
,1,1), BBOATBI_MASK
, PPCCOM
, PPCNONE
, {BDPA
}},
3562 {"bdnzla", BBO(16,BODNZ
,1,1), BBOATBI_MASK
, PPCCOM
, PPCNONE
, {BDA
}},
3563 {"bdnla", BBO(16,BODNZ
,1,1), BBOATBI_MASK
, PWRCOM
, PPCNONE
, {BDA
}},
3564 {"bdz-", BBO(16,BODZ
,0,0), BBOATBI_MASK
, PPCCOM
, PPCNONE
, {BDM
}},
3565 {"bdz+", BBO(16,BODZ
,0,0), BBOATBI_MASK
, PPCCOM
, PPCNONE
, {BDP
}},
3566 {"bdz", BBO(16,BODZ
,0,0), BBOATBI_MASK
, COM
, PPCNONE
, {BD
}},
3567 {"bdzl-", BBO(16,BODZ
,0,1), BBOATBI_MASK
, PPCCOM
, PPCNONE
, {BDM
}},
3568 {"bdzl+", BBO(16,BODZ
,0,1), BBOATBI_MASK
, PPCCOM
, PPCNONE
, {BDP
}},
3569 {"bdzl", BBO(16,BODZ
,0,1), BBOATBI_MASK
, COM
, PPCNONE
, {BD
}},
3570 {"bdza-", BBO(16,BODZ
,1,0), BBOATBI_MASK
, PPCCOM
, PPCNONE
, {BDMA
}},
3571 {"bdza+", BBO(16,BODZ
,1,0), BBOATBI_MASK
, PPCCOM
, PPCNONE
, {BDPA
}},
3572 {"bdza", BBO(16,BODZ
,1,0), BBOATBI_MASK
, COM
, PPCNONE
, {BDA
}},
3573 {"bdzla-", BBO(16,BODZ
,1,1), BBOATBI_MASK
, PPCCOM
, PPCNONE
, {BDMA
}},
3574 {"bdzla+", BBO(16,BODZ
,1,1), BBOATBI_MASK
, PPCCOM
, PPCNONE
, {BDPA
}},
3575 {"bdzla", BBO(16,BODZ
,1,1), BBOATBI_MASK
, COM
, PPCNONE
, {BDA
}},
3577 {"bge-", BBOCB(16,BOF
,CBLT
,0,0), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BDM
}},
3578 {"bge+", BBOCB(16,BOF
,CBLT
,0,0), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BDP
}},
3579 {"bge", BBOCB(16,BOF
,CBLT
,0,0), BBOATCB_MASK
, COM
, PPCNONE
, {CR
, BD
}},
3580 {"bnl-", BBOCB(16,BOF
,CBLT
,0,0), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BDM
}},
3581 {"bnl+", BBOCB(16,BOF
,CBLT
,0,0), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BDP
}},
3582 {"bnl", BBOCB(16,BOF
,CBLT
,0,0), BBOATCB_MASK
, COM
, PPCNONE
, {CR
, BD
}},
3583 {"bgel-", BBOCB(16,BOF
,CBLT
,0,1), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BDM
}},
3584 {"bgel+", BBOCB(16,BOF
,CBLT
,0,1), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BDP
}},
3585 {"bgel", BBOCB(16,BOF
,CBLT
,0,1), BBOATCB_MASK
, COM
, PPCNONE
, {CR
, BD
}},
3586 {"bnll-", BBOCB(16,BOF
,CBLT
,0,1), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BDM
}},
3587 {"bnll+", BBOCB(16,BOF
,CBLT
,0,1), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BDP
}},
3588 {"bnll", BBOCB(16,BOF
,CBLT
,0,1), BBOATCB_MASK
, COM
, PPCNONE
, {CR
, BD
}},
3589 {"bgea-", BBOCB(16,BOF
,CBLT
,1,0), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BDMA
}},
3590 {"bgea+", BBOCB(16,BOF
,CBLT
,1,0), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BDPA
}},
3591 {"bgea", BBOCB(16,BOF
,CBLT
,1,0), BBOATCB_MASK
, COM
, PPCNONE
, {CR
, BDA
}},
3592 {"bnla-", BBOCB(16,BOF
,CBLT
,1,0), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BDMA
}},
3593 {"bnla+", BBOCB(16,BOF
,CBLT
,1,0), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BDPA
}},
3594 {"bnla", BBOCB(16,BOF
,CBLT
,1,0), BBOATCB_MASK
, COM
, PPCNONE
, {CR
, BDA
}},
3595 {"bgela-", BBOCB(16,BOF
,CBLT
,1,1), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BDMA
}},
3596 {"bgela+", BBOCB(16,BOF
,CBLT
,1,1), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BDPA
}},
3597 {"bgela", BBOCB(16,BOF
,CBLT
,1,1), BBOATCB_MASK
, COM
, PPCNONE
, {CR
, BDA
}},
3598 {"bnlla-", BBOCB(16,BOF
,CBLT
,1,1), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BDMA
}},
3599 {"bnlla+", BBOCB(16,BOF
,CBLT
,1,1), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BDPA
}},
3600 {"bnlla", BBOCB(16,BOF
,CBLT
,1,1), BBOATCB_MASK
, COM
, PPCNONE
, {CR
, BDA
}},
3601 {"ble-", BBOCB(16,BOF
,CBGT
,0,0), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BDM
}},
3602 {"ble+", BBOCB(16,BOF
,CBGT
,0,0), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BDP
}},
3603 {"ble", BBOCB(16,BOF
,CBGT
,0,0), BBOATCB_MASK
, COM
, PPCNONE
, {CR
, BD
}},
3604 {"bng-", BBOCB(16,BOF
,CBGT
,0,0), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BDM
}},
3605 {"bng+", BBOCB(16,BOF
,CBGT
,0,0), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BDP
}},
3606 {"bng", BBOCB(16,BOF
,CBGT
,0,0), BBOATCB_MASK
, COM
, PPCNONE
, {CR
, BD
}},
3607 {"blel-", BBOCB(16,BOF
,CBGT
,0,1), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BDM
}},
3608 {"blel+", BBOCB(16,BOF
,CBGT
,0,1), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BDP
}},
3609 {"blel", BBOCB(16,BOF
,CBGT
,0,1), BBOATCB_MASK
, COM
, PPCNONE
, {CR
, BD
}},
3610 {"bngl-", BBOCB(16,BOF
,CBGT
,0,1), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BDM
}},
3611 {"bngl+", BBOCB(16,BOF
,CBGT
,0,1), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BDP
}},
3612 {"bngl", BBOCB(16,BOF
,CBGT
,0,1), BBOATCB_MASK
, COM
, PPCNONE
, {CR
, BD
}},
3613 {"blea-", BBOCB(16,BOF
,CBGT
,1,0), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BDMA
}},
3614 {"blea+", BBOCB(16,BOF
,CBGT
,1,0), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BDPA
}},
3615 {"blea", BBOCB(16,BOF
,CBGT
,1,0), BBOATCB_MASK
, COM
, PPCNONE
, {CR
, BDA
}},
3616 {"bnga-", BBOCB(16,BOF
,CBGT
,1,0), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BDMA
}},
3617 {"bnga+", BBOCB(16,BOF
,CBGT
,1,0), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BDPA
}},
3618 {"bnga", BBOCB(16,BOF
,CBGT
,1,0), BBOATCB_MASK
, COM
, PPCNONE
, {CR
, BDA
}},
3619 {"blela-", BBOCB(16,BOF
,CBGT
,1,1), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BDMA
}},
3620 {"blela+", BBOCB(16,BOF
,CBGT
,1,1), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BDPA
}},
3621 {"blela", BBOCB(16,BOF
,CBGT
,1,1), BBOATCB_MASK
, COM
, PPCNONE
, {CR
, BDA
}},
3622 {"bngla-", BBOCB(16,BOF
,CBGT
,1,1), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BDMA
}},
3623 {"bngla+", BBOCB(16,BOF
,CBGT
,1,1), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BDPA
}},
3624 {"bngla", BBOCB(16,BOF
,CBGT
,1,1), BBOATCB_MASK
, COM
, PPCNONE
, {CR
, BDA
}},
3625 {"bne-", BBOCB(16,BOF
,CBEQ
,0,0), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BDM
}},
3626 {"bne+", BBOCB(16,BOF
,CBEQ
,0,0), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BDP
}},
3627 {"bne", BBOCB(16,BOF
,CBEQ
,0,0), BBOATCB_MASK
, COM
, PPCNONE
, {CR
, BD
}},
3628 {"bnel-", BBOCB(16,BOF
,CBEQ
,0,1), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BDM
}},
3629 {"bnel+", BBOCB(16,BOF
,CBEQ
,0,1), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BDP
}},
3630 {"bnel", BBOCB(16,BOF
,CBEQ
,0,1), BBOATCB_MASK
, COM
, PPCNONE
, {CR
, BD
}},
3631 {"bnea-", BBOCB(16,BOF
,CBEQ
,1,0), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BDMA
}},
3632 {"bnea+", BBOCB(16,BOF
,CBEQ
,1,0), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BDPA
}},
3633 {"bnea", BBOCB(16,BOF
,CBEQ
,1,0), BBOATCB_MASK
, COM
, PPCNONE
, {CR
, BDA
}},
3634 {"bnela-", BBOCB(16,BOF
,CBEQ
,1,1), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BDMA
}},
3635 {"bnela+", BBOCB(16,BOF
,CBEQ
,1,1), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BDPA
}},
3636 {"bnela", BBOCB(16,BOF
,CBEQ
,1,1), BBOATCB_MASK
, COM
, PPCNONE
, {CR
, BDA
}},
3637 {"bns-", BBOCB(16,BOF
,CBSO
,0,0), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BDM
}},
3638 {"bns+", BBOCB(16,BOF
,CBSO
,0,0), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BDP
}},
3639 {"bns", BBOCB(16,BOF
,CBSO
,0,0), BBOATCB_MASK
, COM
, PPCNONE
, {CR
, BD
}},
3640 {"bnu-", BBOCB(16,BOF
,CBSO
,0,0), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BDM
}},
3641 {"bnu+", BBOCB(16,BOF
,CBSO
,0,0), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BDP
}},
3642 {"bnu", BBOCB(16,BOF
,CBSO
,0,0), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BD
}},
3643 {"bnsl-", BBOCB(16,BOF
,CBSO
,0,1), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BDM
}},
3644 {"bnsl+", BBOCB(16,BOF
,CBSO
,0,1), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BDP
}},
3645 {"bnsl", BBOCB(16,BOF
,CBSO
,0,1), BBOATCB_MASK
, COM
, PPCNONE
, {CR
, BD
}},
3646 {"bnul-", BBOCB(16,BOF
,CBSO
,0,1), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BDM
}},
3647 {"bnul+", BBOCB(16,BOF
,CBSO
,0,1), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BDP
}},
3648 {"bnul", BBOCB(16,BOF
,CBSO
,0,1), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BD
}},
3649 {"bnsa-", BBOCB(16,BOF
,CBSO
,1,0), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BDMA
}},
3650 {"bnsa+", BBOCB(16,BOF
,CBSO
,1,0), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BDPA
}},
3651 {"bnsa", BBOCB(16,BOF
,CBSO
,1,0), BBOATCB_MASK
, COM
, PPCNONE
, {CR
, BDA
}},
3652 {"bnua-", BBOCB(16,BOF
,CBSO
,1,0), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BDMA
}},
3653 {"bnua+", BBOCB(16,BOF
,CBSO
,1,0), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BDPA
}},
3654 {"bnua", BBOCB(16,BOF
,CBSO
,1,0), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BDA
}},
3655 {"bnsla-", BBOCB(16,BOF
,CBSO
,1,1), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BDMA
}},
3656 {"bnsla+", BBOCB(16,BOF
,CBSO
,1,1), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BDPA
}},
3657 {"bnsla", BBOCB(16,BOF
,CBSO
,1,1), BBOATCB_MASK
, COM
, PPCNONE
, {CR
, BDA
}},
3658 {"bnula-", BBOCB(16,BOF
,CBSO
,1,1), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BDMA
}},
3659 {"bnula+", BBOCB(16,BOF
,CBSO
,1,1), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BDPA
}},
3660 {"bnula", BBOCB(16,BOF
,CBSO
,1,1), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BDA
}},
3662 {"blt-", BBOCB(16,BOT
,CBLT
,0,0), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BDM
}},
3663 {"blt+", BBOCB(16,BOT
,CBLT
,0,0), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BDP
}},
3664 {"blt", BBOCB(16,BOT
,CBLT
,0,0), BBOATCB_MASK
, COM
, PPCNONE
, {CR
, BD
}},
3665 {"bltl-", BBOCB(16,BOT
,CBLT
,0,1), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BDM
}},
3666 {"bltl+", BBOCB(16,BOT
,CBLT
,0,1), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BDP
}},
3667 {"bltl", BBOCB(16,BOT
,CBLT
,0,1), BBOATCB_MASK
, COM
, PPCNONE
, {CR
, BD
}},
3668 {"blta-", BBOCB(16,BOT
,CBLT
,1,0), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BDMA
}},
3669 {"blta+", BBOCB(16,BOT
,CBLT
,1,0), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BDPA
}},
3670 {"blta", BBOCB(16,BOT
,CBLT
,1,0), BBOATCB_MASK
, COM
, PPCNONE
, {CR
, BDA
}},
3671 {"bltla-", BBOCB(16,BOT
,CBLT
,1,1), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BDMA
}},
3672 {"bltla+", BBOCB(16,BOT
,CBLT
,1,1), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BDPA
}},
3673 {"bltla", BBOCB(16,BOT
,CBLT
,1,1), BBOATCB_MASK
, COM
, PPCNONE
, {CR
, BDA
}},
3674 {"bgt-", BBOCB(16,BOT
,CBGT
,0,0), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BDM
}},
3675 {"bgt+", BBOCB(16,BOT
,CBGT
,0,0), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BDP
}},
3676 {"bgt", BBOCB(16,BOT
,CBGT
,0,0), BBOATCB_MASK
, COM
, PPCNONE
, {CR
, BD
}},
3677 {"bgtl-", BBOCB(16,BOT
,CBGT
,0,1), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BDM
}},
3678 {"bgtl+", BBOCB(16,BOT
,CBGT
,0,1), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BDP
}},
3679 {"bgtl", BBOCB(16,BOT
,CBGT
,0,1), BBOATCB_MASK
, COM
, PPCNONE
, {CR
, BD
}},
3680 {"bgta-", BBOCB(16,BOT
,CBGT
,1,0), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BDMA
}},
3681 {"bgta+", BBOCB(16,BOT
,CBGT
,1,0), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BDPA
}},
3682 {"bgta", BBOCB(16,BOT
,CBGT
,1,0), BBOATCB_MASK
, COM
, PPCNONE
, {CR
, BDA
}},
3683 {"bgtla-", BBOCB(16,BOT
,CBGT
,1,1), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BDMA
}},
3684 {"bgtla+", BBOCB(16,BOT
,CBGT
,1,1), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BDPA
}},
3685 {"bgtla", BBOCB(16,BOT
,CBGT
,1,1), BBOATCB_MASK
, COM
, PPCNONE
, {CR
, BDA
}},
3686 {"beq-", BBOCB(16,BOT
,CBEQ
,0,0), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BDM
}},
3687 {"beq+", BBOCB(16,BOT
,CBEQ
,0,0), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BDP
}},
3688 {"beq", BBOCB(16,BOT
,CBEQ
,0,0), BBOATCB_MASK
, COM
, PPCNONE
, {CR
, BD
}},
3689 {"beql-", BBOCB(16,BOT
,CBEQ
,0,1), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BDM
}},
3690 {"beql+", BBOCB(16,BOT
,CBEQ
,0,1), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BDP
}},
3691 {"beql", BBOCB(16,BOT
,CBEQ
,0,1), BBOATCB_MASK
, COM
, PPCNONE
, {CR
, BD
}},
3692 {"beqa-", BBOCB(16,BOT
,CBEQ
,1,0), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BDMA
}},
3693 {"beqa+", BBOCB(16,BOT
,CBEQ
,1,0), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BDPA
}},
3694 {"beqa", BBOCB(16,BOT
,CBEQ
,1,0), BBOATCB_MASK
, COM
, PPCNONE
, {CR
, BDA
}},
3695 {"beqla-", BBOCB(16,BOT
,CBEQ
,1,1), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BDMA
}},
3696 {"beqla+", BBOCB(16,BOT
,CBEQ
,1,1), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BDPA
}},
3697 {"beqla", BBOCB(16,BOT
,CBEQ
,1,1), BBOATCB_MASK
, COM
, PPCNONE
, {CR
, BDA
}},
3698 {"bso-", BBOCB(16,BOT
,CBSO
,0,0), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BDM
}},
3699 {"bso+", BBOCB(16,BOT
,CBSO
,0,0), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BDP
}},
3700 {"bso", BBOCB(16,BOT
,CBSO
,0,0), BBOATCB_MASK
, COM
, PPCNONE
, {CR
, BD
}},
3701 {"bun-", BBOCB(16,BOT
,CBSO
,0,0), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BDM
}},
3702 {"bun+", BBOCB(16,BOT
,CBSO
,0,0), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BDP
}},
3703 {"bun", BBOCB(16,BOT
,CBSO
,0,0), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BD
}},
3704 {"bsol-", BBOCB(16,BOT
,CBSO
,0,1), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BDM
}},
3705 {"bsol+", BBOCB(16,BOT
,CBSO
,0,1), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BDP
}},
3706 {"bsol", BBOCB(16,BOT
,CBSO
,0,1), BBOATCB_MASK
, COM
, PPCNONE
, {CR
, BD
}},
3707 {"bunl-", BBOCB(16,BOT
,CBSO
,0,1), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BDM
}},
3708 {"bunl+", BBOCB(16,BOT
,CBSO
,0,1), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BDP
}},
3709 {"bunl", BBOCB(16,BOT
,CBSO
,0,1), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BD
}},
3710 {"bsoa-", BBOCB(16,BOT
,CBSO
,1,0), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BDMA
}},
3711 {"bsoa+", BBOCB(16,BOT
,CBSO
,1,0), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BDPA
}},
3712 {"bsoa", BBOCB(16,BOT
,CBSO
,1,0), BBOATCB_MASK
, COM
, PPCNONE
, {CR
, BDA
}},
3713 {"buna-", BBOCB(16,BOT
,CBSO
,1,0), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BDMA
}},
3714 {"buna+", BBOCB(16,BOT
,CBSO
,1,0), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BDPA
}},
3715 {"buna", BBOCB(16,BOT
,CBSO
,1,0), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BDA
}},
3716 {"bsola-", BBOCB(16,BOT
,CBSO
,1,1), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BDMA
}},
3717 {"bsola+", BBOCB(16,BOT
,CBSO
,1,1), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BDPA
}},
3718 {"bsola", BBOCB(16,BOT
,CBSO
,1,1), BBOATCB_MASK
, COM
, PPCNONE
, {CR
, BDA
}},
3719 {"bunla-", BBOCB(16,BOT
,CBSO
,1,1), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BDMA
}},
3720 {"bunla+", BBOCB(16,BOT
,CBSO
,1,1), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BDPA
}},
3721 {"bunla", BBOCB(16,BOT
,CBSO
,1,1), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BDA
}},
3723 {"bdnzf-", BBO(16,BODNZF
,0,0), BBOY_MASK
, PPCCOM
, ISA_V2
, {BI
, BDM
}},
3724 {"bdnzf+", BBO(16,BODNZF
,0,0), BBOY_MASK
, PPCCOM
, ISA_V2
, {BI
, BDP
}},
3725 {"bdnzf", BBO(16,BODNZF
,0,0), BBOY_MASK
, PPCCOM
, PPCNONE
, {BI
, BD
}},
3726 {"bdnzfl-", BBO(16,BODNZF
,0,1), BBOY_MASK
, PPCCOM
, ISA_V2
, {BI
, BDM
}},
3727 {"bdnzfl+", BBO(16,BODNZF
,0,1), BBOY_MASK
, PPCCOM
, ISA_V2
, {BI
, BDP
}},
3728 {"bdnzfl", BBO(16,BODNZF
,0,1), BBOY_MASK
, PPCCOM
, PPCNONE
, {BI
, BD
}},
3729 {"bdnzfa-", BBO(16,BODNZF
,1,0), BBOY_MASK
, PPCCOM
, ISA_V2
, {BI
, BDMA
}},
3730 {"bdnzfa+", BBO(16,BODNZF
,1,0), BBOY_MASK
, PPCCOM
, ISA_V2
, {BI
, BDPA
}},
3731 {"bdnzfa", BBO(16,BODNZF
,1,0), BBOY_MASK
, PPCCOM
, PPCNONE
, {BI
, BDA
}},
3732 {"bdnzfla-", BBO(16,BODNZF
,1,1), BBOY_MASK
, PPCCOM
, ISA_V2
, {BI
, BDMA
}},
3733 {"bdnzfla+", BBO(16,BODNZF
,1,1), BBOY_MASK
, PPCCOM
, ISA_V2
, {BI
, BDPA
}},
3734 {"bdnzfla", BBO(16,BODNZF
,1,1), BBOY_MASK
, PPCCOM
, PPCNONE
, {BI
, BDA
}},
3735 {"bdzf-", BBO(16,BODZF
,0,0), BBOY_MASK
, PPCCOM
, ISA_V2
, {BI
, BDM
}},
3736 {"bdzf+", BBO(16,BODZF
,0,0), BBOY_MASK
, PPCCOM
, ISA_V2
, {BI
, BDP
}},
3737 {"bdzf", BBO(16,BODZF
,0,0), BBOY_MASK
, PPCCOM
, PPCNONE
, {BI
, BD
}},
3738 {"bdzfl-", BBO(16,BODZF
,0,1), BBOY_MASK
, PPCCOM
, ISA_V2
, {BI
, BDM
}},
3739 {"bdzfl+", BBO(16,BODZF
,0,1), BBOY_MASK
, PPCCOM
, ISA_V2
, {BI
, BDP
}},
3740 {"bdzfl", BBO(16,BODZF
,0,1), BBOY_MASK
, PPCCOM
, PPCNONE
, {BI
, BD
}},
3741 {"bdzfa-", BBO(16,BODZF
,1,0), BBOY_MASK
, PPCCOM
, ISA_V2
, {BI
, BDMA
}},
3742 {"bdzfa+", BBO(16,BODZF
,1,0), BBOY_MASK
, PPCCOM
, ISA_V2
, {BI
, BDPA
}},
3743 {"bdzfa", BBO(16,BODZF
,1,0), BBOY_MASK
, PPCCOM
, PPCNONE
, {BI
, BDA
}},
3744 {"bdzfla-", BBO(16,BODZF
,1,1), BBOY_MASK
, PPCCOM
, ISA_V2
, {BI
, BDMA
}},
3745 {"bdzfla+", BBO(16,BODZF
,1,1), BBOY_MASK
, PPCCOM
, ISA_V2
, {BI
, BDPA
}},
3746 {"bdzfla", BBO(16,BODZF
,1,1), BBOY_MASK
, PPCCOM
, PPCNONE
, {BI
, BDA
}},
3748 {"bf-", BBO(16,BOF
,0,0), BBOAT_MASK
, PPCCOM
, PPCNONE
, {BI
, BDM
}},
3749 {"bf+", BBO(16,BOF
,0,0), BBOAT_MASK
, PPCCOM
, PPCNONE
, {BI
, BDP
}},
3750 {"bf", BBO(16,BOF
,0,0), BBOAT_MASK
, PPCCOM
, PPCNONE
, {BI
, BD
}},
3751 {"bbf", BBO(16,BOF
,0,0), BBOAT_MASK
, PWRCOM
, PPCNONE
, {BI
, BD
}},
3752 {"bfl-", BBO(16,BOF
,0,1), BBOAT_MASK
, PPCCOM
, PPCNONE
, {BI
, BDM
}},
3753 {"bfl+", BBO(16,BOF
,0,1), BBOAT_MASK
, PPCCOM
, PPCNONE
, {BI
, BDP
}},
3754 {"bfl", BBO(16,BOF
,0,1), BBOAT_MASK
, PPCCOM
, PPCNONE
, {BI
, BD
}},
3755 {"bbfl", BBO(16,BOF
,0,1), BBOAT_MASK
, PWRCOM
, PPCNONE
, {BI
, BD
}},
3756 {"bfa-", BBO(16,BOF
,1,0), BBOAT_MASK
, PPCCOM
, PPCNONE
, {BI
, BDMA
}},
3757 {"bfa+", BBO(16,BOF
,1,0), BBOAT_MASK
, PPCCOM
, PPCNONE
, {BI
, BDPA
}},
3758 {"bfa", BBO(16,BOF
,1,0), BBOAT_MASK
, PPCCOM
, PPCNONE
, {BI
, BDA
}},
3759 {"bbfa", BBO(16,BOF
,1,0), BBOAT_MASK
, PWRCOM
, PPCNONE
, {BI
, BDA
}},
3760 {"bfla-", BBO(16,BOF
,1,1), BBOAT_MASK
, PPCCOM
, PPCNONE
, {BI
, BDMA
}},
3761 {"bfla+", BBO(16,BOF
,1,1), BBOAT_MASK
, PPCCOM
, PPCNONE
, {BI
, BDPA
}},
3762 {"bfla", BBO(16,BOF
,1,1), BBOAT_MASK
, PPCCOM
, PPCNONE
, {BI
, BDA
}},
3763 {"bbfla", BBO(16,BOF
,1,1), BBOAT_MASK
, PWRCOM
, PPCNONE
, {BI
, BDA
}},
3765 {"bdnzt-", BBO(16,BODNZT
,0,0), BBOY_MASK
, PPCCOM
, ISA_V2
, {BI
, BDM
}},
3766 {"bdnzt+", BBO(16,BODNZT
,0,0), BBOY_MASK
, PPCCOM
, ISA_V2
, {BI
, BDP
}},
3767 {"bdnzt", BBO(16,BODNZT
,0,0), BBOY_MASK
, PPCCOM
, PPCNONE
, {BI
, BD
}},
3768 {"bdnztl-", BBO(16,BODNZT
,0,1), BBOY_MASK
, PPCCOM
, ISA_V2
, {BI
, BDM
}},
3769 {"bdnztl+", BBO(16,BODNZT
,0,1), BBOY_MASK
, PPCCOM
, ISA_V2
, {BI
, BDP
}},
3770 {"bdnztl", BBO(16,BODNZT
,0,1), BBOY_MASK
, PPCCOM
, PPCNONE
, {BI
, BD
}},
3771 {"bdnzta-", BBO(16,BODNZT
,1,0), BBOY_MASK
, PPCCOM
, ISA_V2
, {BI
, BDMA
}},
3772 {"bdnzta+", BBO(16,BODNZT
,1,0), BBOY_MASK
, PPCCOM
, ISA_V2
, {BI
, BDPA
}},
3773 {"bdnzta", BBO(16,BODNZT
,1,0), BBOY_MASK
, PPCCOM
, PPCNONE
, {BI
, BDA
}},
3774 {"bdnztla-", BBO(16,BODNZT
,1,1), BBOY_MASK
, PPCCOM
, ISA_V2
, {BI
, BDMA
}},
3775 {"bdnztla+", BBO(16,BODNZT
,1,1), BBOY_MASK
, PPCCOM
, ISA_V2
, {BI
, BDPA
}},
3776 {"bdnztla", BBO(16,BODNZT
,1,1), BBOY_MASK
, PPCCOM
, PPCNONE
, {BI
, BDA
}},
3777 {"bdzt-", BBO(16,BODZT
,0,0), BBOY_MASK
, PPCCOM
, ISA_V2
, {BI
, BDM
}},
3778 {"bdzt+", BBO(16,BODZT
,0,0), BBOY_MASK
, PPCCOM
, ISA_V2
, {BI
, BDP
}},
3779 {"bdzt", BBO(16,BODZT
,0,0), BBOY_MASK
, PPCCOM
, PPCNONE
, {BI
, BD
}},
3780 {"bdztl-", BBO(16,BODZT
,0,1), BBOY_MASK
, PPCCOM
, ISA_V2
, {BI
, BDM
}},
3781 {"bdztl+", BBO(16,BODZT
,0,1), BBOY_MASK
, PPCCOM
, ISA_V2
, {BI
, BDP
}},
3782 {"bdztl", BBO(16,BODZT
,0,1), BBOY_MASK
, PPCCOM
, PPCNONE
, {BI
, BD
}},
3783 {"bdzta-", BBO(16,BODZT
,1,0), BBOY_MASK
, PPCCOM
, ISA_V2
, {BI
, BDMA
}},
3784 {"bdzta+", BBO(16,BODZT
,1,0), BBOY_MASK
, PPCCOM
, ISA_V2
, {BI
, BDPA
}},
3785 {"bdzta", BBO(16,BODZT
,1,0), BBOY_MASK
, PPCCOM
, PPCNONE
, {BI
, BDA
}},
3786 {"bdztla-", BBO(16,BODZT
,1,1), BBOY_MASK
, PPCCOM
, ISA_V2
, {BI
, BDMA
}},
3787 {"bdztla+", BBO(16,BODZT
,1,1), BBOY_MASK
, PPCCOM
, ISA_V2
, {BI
, BDPA
}},
3788 {"bdztla", BBO(16,BODZT
,1,1), BBOY_MASK
, PPCCOM
, PPCNONE
, {BI
, BDA
}},
3790 {"bt-", BBO(16,BOT
,0,0), BBOAT_MASK
, PPCCOM
, PPCNONE
, {BI
, BDM
}},
3791 {"bt+", BBO(16,BOT
,0,0), BBOAT_MASK
, PPCCOM
, PPCNONE
, {BI
, BDP
}},
3792 {"bt", BBO(16,BOT
,0,0), BBOAT_MASK
, PPCCOM
, PPCNONE
, {BI
, BD
}},
3793 {"bbt", BBO(16,BOT
,0,0), BBOAT_MASK
, PWRCOM
, PPCNONE
, {BI
, BD
}},
3794 {"btl-", BBO(16,BOT
,0,1), BBOAT_MASK
, PPCCOM
, PPCNONE
, {BI
, BDM
}},
3795 {"btl+", BBO(16,BOT
,0,1), BBOAT_MASK
, PPCCOM
, PPCNONE
, {BI
, BDP
}},
3796 {"btl", BBO(16,BOT
,0,1), BBOAT_MASK
, PPCCOM
, PPCNONE
, {BI
, BD
}},
3797 {"bbtl", BBO(16,BOT
,0,1), BBOAT_MASK
, PWRCOM
, PPCNONE
, {BI
, BD
}},
3798 {"bta-", BBO(16,BOT
,1,0), BBOAT_MASK
, PPCCOM
, PPCNONE
, {BI
, BDMA
}},
3799 {"bta+", BBO(16,BOT
,1,0), BBOAT_MASK
, PPCCOM
, PPCNONE
, {BI
, BDPA
}},
3800 {"bta", BBO(16,BOT
,1,0), BBOAT_MASK
, PPCCOM
, PPCNONE
, {BI
, BDA
}},
3801 {"bbta", BBO(16,BOT
,1,0), BBOAT_MASK
, PWRCOM
, PPCNONE
, {BI
, BDA
}},
3802 {"btla-", BBO(16,BOT
,1,1), BBOAT_MASK
, PPCCOM
, PPCNONE
, {BI
, BDMA
}},
3803 {"btla+", BBO(16,BOT
,1,1), BBOAT_MASK
, PPCCOM
, PPCNONE
, {BI
, BDPA
}},
3804 {"btla", BBO(16,BOT
,1,1), BBOAT_MASK
, PPCCOM
, PPCNONE
, {BI
, BDA
}},
3805 {"bbtla", BBO(16,BOT
,1,1), BBOAT_MASK
, PWRCOM
, PPCNONE
, {BI
, BDA
}},
3807 {"bc-", B(16,0,0), B_MASK
, PPCCOM
, PPCNONE
, {BOE
, BI
, BDM
}},
3808 {"bc+", B(16,0,0), B_MASK
, PPCCOM
, PPCNONE
, {BOE
, BI
, BDP
}},
3809 {"bc", B(16,0,0), B_MASK
, COM
, PPCNONE
, {BO
, BI
, BD
}},
3810 {"bcl-", B(16,0,1), B_MASK
, PPCCOM
, PPCNONE
, {BOE
, BI
, BDM
}},
3811 {"bcl+", B(16,0,1), B_MASK
, PPCCOM
, PPCNONE
, {BOE
, BI
, BDP
}},
3812 {"bcl", B(16,0,1), B_MASK
, COM
, PPCNONE
, {BO
, BI
, BD
}},
3813 {"bca-", B(16,1,0), B_MASK
, PPCCOM
, PPCNONE
, {BOE
, BI
, BDMA
}},
3814 {"bca+", B(16,1,0), B_MASK
, PPCCOM
, PPCNONE
, {BOE
, BI
, BDPA
}},
3815 {"bca", B(16,1,0), B_MASK
, COM
, PPCNONE
, {BO
, BI
, BDA
}},
3816 {"bcla-", B(16,1,1), B_MASK
, PPCCOM
, PPCNONE
, {BOE
, BI
, BDMA
}},
3817 {"bcla+", B(16,1,1), B_MASK
, PPCCOM
, PPCNONE
, {BOE
, BI
, BDPA
}},
3818 {"bcla", B(16,1,1), B_MASK
, COM
, PPCNONE
, {BO
, BI
, BDA
}},
3820 {"svc", SC(17,0,0), SC_MASK
, POWER
, PPCNONE
, {SVC_LEV
, FL1
, FL2
}},
3821 {"svcl", SC(17,0,1), SC_MASK
, POWER
, PPCNONE
, {SVC_LEV
, FL1
, FL2
}},
3822 {"sc", SC(17,1,0), SC_MASK
, PPC
, PPCNONE
, {LEV
}},
3823 {"svca", SC(17,1,0), SC_MASK
, PWRCOM
, PPCNONE
, {SV
}},
3824 {"svcla", SC(17,1,1), SC_MASK
, POWER
, PPCNONE
, {SV
}},
3826 {"b", B(18,0,0), B_MASK
, COM
, PPCNONE
, {LI
}},
3827 {"bl", B(18,0,1), B_MASK
, COM
, PPCNONE
, {LI
}},
3828 {"ba", B(18,1,0), B_MASK
, COM
, PPCNONE
, {LIA
}},
3829 {"bla", B(18,1,1), B_MASK
, COM
, PPCNONE
, {LIA
}},
3831 {"mcrf", XL(19,0), XLBB_MASK
|(3<<21)|(3<<16), COM
, PPCNONE
, {BF
, BFA
}},
3833 {"bdnzlr", XLO(19,BODNZ
,16,0), XLBOBIBB_MASK
, PPCCOM
, PPCNONE
, {0}},
3834 {"bdnzlr-", XLO(19,BODNZ
,16,0), XLBOBIBB_MASK
, PPCCOM
, ISA_V2
, {0}},
3835 {"bdnzlrl", XLO(19,BODNZ
,16,1), XLBOBIBB_MASK
, PPCCOM
, PPCNONE
, {0}},
3836 {"bdnzlrl-", XLO(19,BODNZ
,16,1), XLBOBIBB_MASK
, PPCCOM
, ISA_V2
, {0}},
3837 {"bdnzlr+", XLO(19,BODNZP
,16,0), XLBOBIBB_MASK
, PPCCOM
, ISA_V2
, {0}},
3838 {"bdnzlrl+", XLO(19,BODNZP
,16,1), XLBOBIBB_MASK
, PPCCOM
, ISA_V2
, {0}},
3839 {"bdzlr", XLO(19,BODZ
,16,0), XLBOBIBB_MASK
, PPCCOM
, PPCNONE
, {0}},
3840 {"bdzlr-", XLO(19,BODZ
,16,0), XLBOBIBB_MASK
, PPCCOM
, ISA_V2
, {0}},
3841 {"bdzlrl", XLO(19,BODZ
,16,1), XLBOBIBB_MASK
, PPCCOM
, PPCNONE
, {0}},
3842 {"bdzlrl-", XLO(19,BODZ
,16,1), XLBOBIBB_MASK
, PPCCOM
, ISA_V2
, {0}},
3843 {"bdzlr+", XLO(19,BODZP
,16,0), XLBOBIBB_MASK
, PPCCOM
, ISA_V2
, {0}},
3844 {"bdzlrl+", XLO(19,BODZP
,16,1), XLBOBIBB_MASK
, PPCCOM
, ISA_V2
, {0}},
3845 {"blr", XLO(19,BOU
,16,0), XLBOBIBB_MASK
, PPCCOM
, PPCNONE
, {0}},
3846 {"br", XLO(19,BOU
,16,0), XLBOBIBB_MASK
, PWRCOM
, PPCNONE
, {0}},
3847 {"blrl", XLO(19,BOU
,16,1), XLBOBIBB_MASK
, PPCCOM
, PPCNONE
, {0}},
3848 {"brl", XLO(19,BOU
,16,1), XLBOBIBB_MASK
, PWRCOM
, PPCNONE
, {0}},
3849 {"bdnzlr-", XLO(19,BODNZM4
,16,0), XLBOBIBB_MASK
, ISA_V2
, PPCNONE
, {0}},
3850 {"bdnzlrl-", XLO(19,BODNZM4
,16,1), XLBOBIBB_MASK
, ISA_V2
, PPCNONE
, {0}},
3851 {"bdnzlr+", XLO(19,BODNZP4
,16,0), XLBOBIBB_MASK
, ISA_V2
, PPCNONE
, {0}},
3852 {"bdnzlrl+", XLO(19,BODNZP4
,16,1), XLBOBIBB_MASK
, ISA_V2
, PPCNONE
, {0}},
3853 {"bdzlr-", XLO(19,BODZM4
,16,0), XLBOBIBB_MASK
, ISA_V2
, PPCNONE
, {0}},
3854 {"bdzlrl-", XLO(19,BODZM4
,16,1), XLBOBIBB_MASK
, ISA_V2
, PPCNONE
, {0}},
3855 {"bdzlr+", XLO(19,BODZP4
,16,0), XLBOBIBB_MASK
, ISA_V2
, PPCNONE
, {0}},
3856 {"bdzlrl+", XLO(19,BODZP4
,16,1), XLBOBIBB_MASK
, ISA_V2
, PPCNONE
, {0}},
3858 {"bgelr", XLOCB(19,BOF
,CBLT
,16,0), XLBOCBBB_MASK
, PPCCOM
, PPCNONE
, {CR
}},
3859 {"bgelr-", XLOCB(19,BOF
,CBLT
,16,0), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
, {CR
}},
3860 {"bger", XLOCB(19,BOF
,CBLT
,16,0), XLBOCBBB_MASK
, PWRCOM
, PPCNONE
, {CR
}},
3861 {"bnllr", XLOCB(19,BOF
,CBLT
,16,0), XLBOCBBB_MASK
, PPCCOM
, PPCNONE
, {CR
}},
3862 {"bnllr-", XLOCB(19,BOF
,CBLT
,16,0), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
, {CR
}},
3863 {"bnlr", XLOCB(19,BOF
,CBLT
,16,0), XLBOCBBB_MASK
, PWRCOM
, PPCNONE
, {CR
}},
3864 {"bgelrl", XLOCB(19,BOF
,CBLT
,16,1), XLBOCBBB_MASK
, PPCCOM
, PPCNONE
, {CR
}},
3865 {"bgelrl-", XLOCB(19,BOF
,CBLT
,16,1), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
, {CR
}},
3866 {"bgerl", XLOCB(19,BOF
,CBLT
,16,1), XLBOCBBB_MASK
, PWRCOM
, PPCNONE
, {CR
}},
3867 {"bnllrl", XLOCB(19,BOF
,CBLT
,16,1), XLBOCBBB_MASK
, PPCCOM
, PPCNONE
, {CR
}},
3868 {"bnllrl-", XLOCB(19,BOF
,CBLT
,16,1), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
, {CR
}},
3869 {"bnlrl", XLOCB(19,BOF
,CBLT
,16,1), XLBOCBBB_MASK
, PWRCOM
, PPCNONE
, {CR
}},
3870 {"blelr", XLOCB(19,BOF
,CBGT
,16,0), XLBOCBBB_MASK
, PPCCOM
, PPCNONE
, {CR
}},
3871 {"blelr-", XLOCB(19,BOF
,CBGT
,16,0), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
, {CR
}},
3872 {"bler", XLOCB(19,BOF
,CBGT
,16,0), XLBOCBBB_MASK
, PWRCOM
, PPCNONE
, {CR
}},
3873 {"bnglr", XLOCB(19,BOF
,CBGT
,16,0), XLBOCBBB_MASK
, PPCCOM
, PPCNONE
, {CR
}},
3874 {"bnglr-", XLOCB(19,BOF
,CBGT
,16,0), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
, {CR
}},
3875 {"bngr", XLOCB(19,BOF
,CBGT
,16,0), XLBOCBBB_MASK
, PWRCOM
, PPCNONE
, {CR
}},
3876 {"blelrl", XLOCB(19,BOF
,CBGT
,16,1), XLBOCBBB_MASK
, PPCCOM
, PPCNONE
, {CR
}},
3877 {"blelrl-", XLOCB(19,BOF
,CBGT
,16,1), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
, {CR
}},
3878 {"blerl", XLOCB(19,BOF
,CBGT
,16,1), XLBOCBBB_MASK
, PWRCOM
, PPCNONE
, {CR
}},
3879 {"bnglrl", XLOCB(19,BOF
,CBGT
,16,1), XLBOCBBB_MASK
, PPCCOM
, PPCNONE
, {CR
}},
3880 {"bnglrl-", XLOCB(19,BOF
,CBGT
,16,1), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
, {CR
}},
3881 {"bngrl", XLOCB(19,BOF
,CBGT
,16,1), XLBOCBBB_MASK
, PWRCOM
, PPCNONE
, {CR
}},
3882 {"bnelr", XLOCB(19,BOF
,CBEQ
,16,0), XLBOCBBB_MASK
, PPCCOM
, PPCNONE
, {CR
}},
3883 {"bnelr-", XLOCB(19,BOF
,CBEQ
,16,0), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
, {CR
}},
3884 {"bner", XLOCB(19,BOF
,CBEQ
,16,0), XLBOCBBB_MASK
, PWRCOM
, PPCNONE
, {CR
}},
3885 {"bnelrl", XLOCB(19,BOF
,CBEQ
,16,1), XLBOCBBB_MASK
, PPCCOM
, PPCNONE
, {CR
}},
3886 {"bnelrl-", XLOCB(19,BOF
,CBEQ
,16,1), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
, {CR
}},
3887 {"bnerl", XLOCB(19,BOF
,CBEQ
,16,1), XLBOCBBB_MASK
, PWRCOM
, PPCNONE
, {CR
}},
3888 {"bnslr", XLOCB(19,BOF
,CBSO
,16,0), XLBOCBBB_MASK
, PPCCOM
, PPCNONE
, {CR
}},
3889 {"bnslr-", XLOCB(19,BOF
,CBSO
,16,0), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
, {CR
}},
3890 {"bnsr", XLOCB(19,BOF
,CBSO
,16,0), XLBOCBBB_MASK
, PWRCOM
, PPCNONE
, {CR
}},
3891 {"bnulr", XLOCB(19,BOF
,CBSO
,16,0), XLBOCBBB_MASK
, PPCCOM
, PPCNONE
, {CR
}},
3892 {"bnulr-", XLOCB(19,BOF
,CBSO
,16,0), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
, {CR
}},
3893 {"bnslrl", XLOCB(19,BOF
,CBSO
,16,1), XLBOCBBB_MASK
, PPCCOM
, PPCNONE
, {CR
}},
3894 {"bnslrl-", XLOCB(19,BOF
,CBSO
,16,1), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
, {CR
}},
3895 {"bnsrl", XLOCB(19,BOF
,CBSO
,16,1), XLBOCBBB_MASK
, PWRCOM
, PPCNONE
, {CR
}},
3896 {"bnulrl", XLOCB(19,BOF
,CBSO
,16,1), XLBOCBBB_MASK
, PPCCOM
, PPCNONE
, {CR
}},
3897 {"bnulrl-", XLOCB(19,BOF
,CBSO
,16,1), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
, {CR
}},
3898 {"bgelr+", XLOCB(19,BOFP
,CBLT
,16,0), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
, {CR
}},
3899 {"bnllr+", XLOCB(19,BOFP
,CBLT
,16,0), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
, {CR
}},
3900 {"bgelrl+", XLOCB(19,BOFP
,CBLT
,16,1), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
, {CR
}},
3901 {"bnllrl+", XLOCB(19,BOFP
,CBLT
,16,1), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
, {CR
}},
3902 {"blelr+", XLOCB(19,BOFP
,CBGT
,16,0), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
, {CR
}},
3903 {"bnglr+", XLOCB(19,BOFP
,CBGT
,16,0), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
, {CR
}},
3904 {"blelrl+", XLOCB(19,BOFP
,CBGT
,16,1), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
, {CR
}},
3905 {"bnglrl+", XLOCB(19,BOFP
,CBGT
,16,1), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
, {CR
}},
3906 {"bnelr+", XLOCB(19,BOFP
,CBEQ
,16,0), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
, {CR
}},
3907 {"bnelrl+", XLOCB(19,BOFP
,CBEQ
,16,1), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
, {CR
}},
3908 {"bnslr+", XLOCB(19,BOFP
,CBSO
,16,0), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
, {CR
}},
3909 {"bnulr+", XLOCB(19,BOFP
,CBSO
,16,0), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
, {CR
}},
3910 {"bnslrl+", XLOCB(19,BOFP
,CBSO
,16,1), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
, {CR
}},
3911 {"bnulrl+", XLOCB(19,BOFP
,CBSO
,16,1), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
, {CR
}},
3912 {"bgelr-", XLOCB(19,BOFM4
,CBLT
,16,0), XLBOCBBB_MASK
, ISA_V2
, PPCNONE
, {CR
}},
3913 {"bnllr-", XLOCB(19,BOFM4
,CBLT
,16,0), XLBOCBBB_MASK
, ISA_V2
, PPCNONE
, {CR
}},
3914 {"bgelrl-", XLOCB(19,BOFM4
,CBLT
,16,1), XLBOCBBB_MASK
, ISA_V2
, PPCNONE
, {CR
}},
3915 {"bnllrl-", XLOCB(19,BOFM4
,CBLT
,16,1), XLBOCBBB_MASK
, ISA_V2
, PPCNONE
, {CR
}},
3916 {"blelr-", XLOCB(19,BOFM4
,CBGT
,16,0), XLBOCBBB_MASK
, ISA_V2
, PPCNONE
, {CR
}},
3917 {"bnglr-", XLOCB(19,BOFM4
,CBGT
,16,0), XLBOCBBB_MASK
, ISA_V2
, PPCNONE
, {CR
}},
3918 {"blelrl-", XLOCB(19,BOFM4
,CBGT
,16,1), XLBOCBBB_MASK
, ISA_V2
, PPCNONE
, {CR
}},
3919 {"bnglrl-", XLOCB(19,BOFM4
,CBGT
,16,1), XLBOCBBB_MASK
, ISA_V2
, PPCNONE
, {CR
}},
3920 {"bnelr-", XLOCB(19,BOFM4
,CBEQ
,16,0), XLBOCBBB_MASK
, ISA_V2
, PPCNONE
, {CR
}},
3921 {"bnelrl-", XLOCB(19,BOFM4
,CBEQ
,16,1), XLBOCBBB_MASK
, ISA_V2
, PPCNONE
, {CR
}},
3922 {"bnslr-", XLOCB(19,BOFM4
,CBSO
,16,0), XLBOCBBB_MASK
, ISA_V2
, PPCNONE
, {CR
}},
3923 {"bnulr-", XLOCB(19,BOFM4
,CBSO
,16,0), XLBOCBBB_MASK
, ISA_V2
, PPCNONE
, {CR
}},
3924 {"bnslrl-", XLOCB(19,BOFM4
,CBSO
,16,1), XLBOCBBB_MASK
, ISA_V2
, PPCNONE
, {CR
}},
3925 {"bnulrl-", XLOCB(19,BOFM4
,CBSO
,16,1), XLBOCBBB_MASK
, ISA_V2
, PPCNONE
, {CR
}},
3926 {"bgelr+", XLOCB(19,BOFP4
,CBLT
,16,0), XLBOCBBB_MASK
, ISA_V2
, PPCNONE
, {CR
}},
3927 {"bnllr+", XLOCB(19,BOFP4
,CBLT
,16,0), XLBOCBBB_MASK
, ISA_V2
, PPCNONE
, {CR
}},
3928 {"bgelrl+", XLOCB(19,BOFP4
,CBLT
,16,1), XLBOCBBB_MASK
, ISA_V2
, PPCNONE
, {CR
}},
3929 {"bnllrl+", XLOCB(19,BOFP4
,CBLT
,16,1), XLBOCBBB_MASK
, ISA_V2
, PPCNONE
, {CR
}},
3930 {"blelr+", XLOCB(19,BOFP4
,CBGT
,16,0), XLBOCBBB_MASK
, ISA_V2
, PPCNONE
, {CR
}},
3931 {"bnglr+", XLOCB(19,BOFP4
,CBGT
,16,0), XLBOCBBB_MASK
, ISA_V2
, PPCNONE
, {CR
}},
3932 {"blelrl+", XLOCB(19,BOFP4
,CBGT
,16,1), XLBOCBBB_MASK
, ISA_V2
, PPCNONE
, {CR
}},
3933 {"bnglrl+", XLOCB(19,BOFP4
,CBGT
,16,1), XLBOCBBB_MASK
, ISA_V2
, PPCNONE
, {CR
}},
3934 {"bnelr+", XLOCB(19,BOFP4
,CBEQ
,16,0), XLBOCBBB_MASK
, ISA_V2
, PPCNONE
, {CR
}},
3935 {"bnelrl+", XLOCB(19,BOFP4
,CBEQ
,16,1), XLBOCBBB_MASK
, ISA_V2
, PPCNONE
, {CR
}},
3936 {"bnslr+", XLOCB(19,BOFP4
,CBSO
,16,0), XLBOCBBB_MASK
, ISA_V2
, PPCNONE
, {CR
}},
3937 {"bnulr+", XLOCB(19,BOFP4
,CBSO
,16,0), XLBOCBBB_MASK
, ISA_V2
, PPCNONE
, {CR
}},
3938 {"bnslrl+", XLOCB(19,BOFP4
,CBSO
,16,1), XLBOCBBB_MASK
, ISA_V2
, PPCNONE
, {CR
}},
3939 {"bnulrl+", XLOCB(19,BOFP4
,CBSO
,16,1), XLBOCBBB_MASK
, ISA_V2
, PPCNONE
, {CR
}},
3940 {"bltlr", XLOCB(19,BOT
,CBLT
,16,0), XLBOCBBB_MASK
, PPCCOM
, PPCNONE
, {CR
}},
3941 {"bltlr-", XLOCB(19,BOT
,CBLT
,16,0), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
, {CR
}},
3942 {"bltr", XLOCB(19,BOT
,CBLT
,16,0), XLBOCBBB_MASK
, PWRCOM
, PPCNONE
, {CR
}},
3943 {"bltlrl", XLOCB(19,BOT
,CBLT
,16,1), XLBOCBBB_MASK
, PPCCOM
, PPCNONE
, {CR
}},
3944 {"bltlrl-", XLOCB(19,BOT
,CBLT
,16,1), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
, {CR
}},
3945 {"bltrl", XLOCB(19,BOT
,CBLT
,16,1), XLBOCBBB_MASK
, PWRCOM
, PPCNONE
, {CR
}},
3946 {"bgtlr", XLOCB(19,BOT
,CBGT
,16,0), XLBOCBBB_MASK
, PPCCOM
, PPCNONE
, {CR
}},
3947 {"bgtlr-", XLOCB(19,BOT
,CBGT
,16,0), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
, {CR
}},
3948 {"bgtr", XLOCB(19,BOT
,CBGT
,16,0), XLBOCBBB_MASK
, PWRCOM
, PPCNONE
, {CR
}},
3949 {"bgtlrl", XLOCB(19,BOT
,CBGT
,16,1), XLBOCBBB_MASK
, PPCCOM
, PPCNONE
, {CR
}},
3950 {"bgtlrl-", XLOCB(19,BOT
,CBGT
,16,1), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
, {CR
}},
3951 {"bgtrl", XLOCB(19,BOT
,CBGT
,16,1), XLBOCBBB_MASK
, PWRCOM
, PPCNONE
, {CR
}},
3952 {"beqlr", XLOCB(19,BOT
,CBEQ
,16,0), XLBOCBBB_MASK
, PPCCOM
, PPCNONE
, {CR
}},
3953 {"beqlr-", XLOCB(19,BOT
,CBEQ
,16,0), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
, {CR
}},
3954 {"beqr", XLOCB(19,BOT
,CBEQ
,16,0), XLBOCBBB_MASK
, PWRCOM
, PPCNONE
, {CR
}},
3955 {"beqlrl", XLOCB(19,BOT
,CBEQ
,16,1), XLBOCBBB_MASK
, PPCCOM
, PPCNONE
, {CR
}},
3956 {"beqlrl-", XLOCB(19,BOT
,CBEQ
,16,1), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
, {CR
}},
3957 {"beqrl", XLOCB(19,BOT
,CBEQ
,16,1), XLBOCBBB_MASK
, PWRCOM
, PPCNONE
, {CR
}},
3958 {"bsolr", XLOCB(19,BOT
,CBSO
,16,0), XLBOCBBB_MASK
, PPCCOM
, PPCNONE
, {CR
}},
3959 {"bsolr-", XLOCB(19,BOT
,CBSO
,16,0), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
, {CR
}},
3960 {"bsor", XLOCB(19,BOT
,CBSO
,16,0), XLBOCBBB_MASK
, PWRCOM
, PPCNONE
, {CR
}},
3961 {"bunlr", XLOCB(19,BOT
,CBSO
,16,0), XLBOCBBB_MASK
, PPCCOM
, PPCNONE
, {CR
}},
3962 {"bunlr-", XLOCB(19,BOT
,CBSO
,16,0), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
, {CR
}},
3963 {"bsolrl", XLOCB(19,BOT
,CBSO
,16,1), XLBOCBBB_MASK
, PPCCOM
, PPCNONE
, {CR
}},
3964 {"bsolrl-", XLOCB(19,BOT
,CBSO
,16,1), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
, {CR
}},
3965 {"bsorl", XLOCB(19,BOT
,CBSO
,16,1), XLBOCBBB_MASK
, PWRCOM
, PPCNONE
, {CR
}},
3966 {"bunlrl", XLOCB(19,BOT
,CBSO
,16,1), XLBOCBBB_MASK
, PPCCOM
, PPCNONE
, {CR
}},
3967 {"bunlrl-", XLOCB(19,BOT
,CBSO
,16,1), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
, {CR
}},
3968 {"bltlr+", XLOCB(19,BOTP
,CBLT
,16,0), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
, {CR
}},
3969 {"bltlrl+", XLOCB(19,BOTP
,CBLT
,16,1), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
, {CR
}},
3970 {"bgtlr+", XLOCB(19,BOTP
,CBGT
,16,0), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
, {CR
}},
3971 {"bgtlrl+", XLOCB(19,BOTP
,CBGT
,16,1), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
, {CR
}},
3972 {"beqlr+", XLOCB(19,BOTP
,CBEQ
,16,0), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
, {CR
}},
3973 {"beqlrl+", XLOCB(19,BOTP
,CBEQ
,16,1), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
, {CR
}},
3974 {"bsolr+", XLOCB(19,BOTP
,CBSO
,16,0), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
, {CR
}},
3975 {"bunlr+", XLOCB(19,BOTP
,CBSO
,16,0), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
, {CR
}},
3976 {"bsolrl+", XLOCB(19,BOTP
,CBSO
,16,1), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
, {CR
}},
3977 {"bunlrl+", XLOCB(19,BOTP
,CBSO
,16,1), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
, {CR
}},
3978 {"bltlr-", XLOCB(19,BOTM4
,CBLT
,16,0), XLBOCBBB_MASK
, ISA_V2
, PPCNONE
, {CR
}},
3979 {"bltlrl-", XLOCB(19,BOTM4
,CBLT
,16,1), XLBOCBBB_MASK
, ISA_V2
, PPCNONE
, {CR
}},
3980 {"bgtlr-", XLOCB(19,BOTM4
,CBGT
,16,0), XLBOCBBB_MASK
, ISA_V2
, PPCNONE
, {CR
}},
3981 {"bgtlrl-", XLOCB(19,BOTM4
,CBGT
,16,1), XLBOCBBB_MASK
, ISA_V2
, PPCNONE
, {CR
}},
3982 {"beqlr-", XLOCB(19,BOTM4
,CBEQ
,16,0), XLBOCBBB_MASK
, ISA_V2
, PPCNONE
, {CR
}},
3983 {"beqlrl-", XLOCB(19,BOTM4
,CBEQ
,16,1), XLBOCBBB_MASK
, ISA_V2
, PPCNONE
, {CR
}},
3984 {"bsolr-", XLOCB(19,BOTM4
,CBSO
,16,0), XLBOCBBB_MASK
, ISA_V2
, PPCNONE
, {CR
}},
3985 {"bunlr-", XLOCB(19,BOTM4
,CBSO
,16,0), XLBOCBBB_MASK
, ISA_V2
, PPCNONE
, {CR
}},
3986 {"bsolrl-", XLOCB(19,BOTM4
,CBSO
,16,1), XLBOCBBB_MASK
, ISA_V2
, PPCNONE
, {CR
}},
3987 {"bunlrl-", XLOCB(19,BOTM4
,CBSO
,16,1), XLBOCBBB_MASK
, ISA_V2
, PPCNONE
, {CR
}},
3988 {"bltlr+", XLOCB(19,BOTP4
,CBLT
,16,0), XLBOCBBB_MASK
, ISA_V2
, PPCNONE
, {CR
}},
3989 {"bltlrl+", XLOCB(19,BOTP4
,CBLT
,16,1), XLBOCBBB_MASK
, ISA_V2
, PPCNONE
, {CR
}},
3990 {"bgtlr+", XLOCB(19,BOTP4
,CBGT
,16,0), XLBOCBBB_MASK
, ISA_V2
, PPCNONE
, {CR
}},
3991 {"bgtlrl+", XLOCB(19,BOTP4
,CBGT
,16,1), XLBOCBBB_MASK
, ISA_V2
, PPCNONE
, {CR
}},
3992 {"beqlr+", XLOCB(19,BOTP4
,CBEQ
,16,0), XLBOCBBB_MASK
, ISA_V2
, PPCNONE
, {CR
}},
3993 {"beqlrl+", XLOCB(19,BOTP4
,CBEQ
,16,1), XLBOCBBB_MASK
, ISA_V2
, PPCNONE
, {CR
}},
3994 {"bsolr+", XLOCB(19,BOTP4
,CBSO
,16,0), XLBOCBBB_MASK
, ISA_V2
, PPCNONE
, {CR
}},
3995 {"bunlr+", XLOCB(19,BOTP4
,CBSO
,16,0), XLBOCBBB_MASK
, ISA_V2
, PPCNONE
, {CR
}},
3996 {"bsolrl+", XLOCB(19,BOTP4
,CBSO
,16,1), XLBOCBBB_MASK
, ISA_V2
, PPCNONE
, {CR
}},
3997 {"bunlrl+", XLOCB(19,BOTP4
,CBSO
,16,1), XLBOCBBB_MASK
, ISA_V2
, PPCNONE
, {CR
}},
3999 {"bdnzflr", XLO(19,BODNZF
,16,0), XLBOBB_MASK
, PPCCOM
, PPCNONE
, {BI
}},
4000 {"bdnzflr-", XLO(19,BODNZF
,16,0), XLBOBB_MASK
, PPCCOM
, ISA_V2
, {BI
}},
4001 {"bdnzflrl", XLO(19,BODNZF
,16,1), XLBOBB_MASK
, PPCCOM
, PPCNONE
, {BI
}},
4002 {"bdnzflrl-",XLO(19,BODNZF
,16,1), XLBOBB_MASK
, PPCCOM
, ISA_V2
, {BI
}},
4003 {"bdnzflr+", XLO(19,BODNZFP
,16,0), XLBOBB_MASK
, PPCCOM
, ISA_V2
, {BI
}},
4004 {"bdnzflrl+",XLO(19,BODNZFP
,16,1), XLBOBB_MASK
, PPCCOM
, ISA_V2
, {BI
}},
4005 {"bdzflr", XLO(19,BODZF
,16,0), XLBOBB_MASK
, PPCCOM
, PPCNONE
, {BI
}},
4006 {"bdzflr-", XLO(19,BODZF
,16,0), XLBOBB_MASK
, PPCCOM
, ISA_V2
, {BI
}},
4007 {"bdzflrl", XLO(19,BODZF
,16,1), XLBOBB_MASK
, PPCCOM
, PPCNONE
, {BI
}},
4008 {"bdzflrl-", XLO(19,BODZF
,16,1), XLBOBB_MASK
, PPCCOM
, ISA_V2
, {BI
}},
4009 {"bdzflr+", XLO(19,BODZFP
,16,0), XLBOBB_MASK
, PPCCOM
, ISA_V2
, {BI
}},
4010 {"bdzflrl+", XLO(19,BODZFP
,16,1), XLBOBB_MASK
, PPCCOM
, ISA_V2
, {BI
}},
4011 {"bflr", XLO(19,BOF
,16,0), XLBOBB_MASK
, PPCCOM
, PPCNONE
, {BI
}},
4012 {"bflr-", XLO(19,BOF
,16,0), XLBOBB_MASK
, PPCCOM
, ISA_V2
, {BI
}},
4013 {"bbfr", XLO(19,BOF
,16,0), XLBOBB_MASK
, PWRCOM
, PPCNONE
, {BI
}},
4014 {"bflrl", XLO(19,BOF
,16,1), XLBOBB_MASK
, PPCCOM
, PPCNONE
, {BI
}},
4015 {"bflrl-", XLO(19,BOF
,16,1), XLBOBB_MASK
, PPCCOM
, ISA_V2
, {BI
}},
4016 {"bbfrl", XLO(19,BOF
,16,1), XLBOBB_MASK
, PWRCOM
, PPCNONE
, {BI
}},
4017 {"bflr+", XLO(19,BOFP
,16,0), XLBOBB_MASK
, PPCCOM
, ISA_V2
, {BI
}},
4018 {"bflrl+", XLO(19,BOFP
,16,1), XLBOBB_MASK
, PPCCOM
, ISA_V2
, {BI
}},
4019 {"bflr-", XLO(19,BOFM4
,16,0), XLBOBB_MASK
, ISA_V2
, PPCNONE
, {BI
}},
4020 {"bflrl-", XLO(19,BOFM4
,16,1), XLBOBB_MASK
, ISA_V2
, PPCNONE
, {BI
}},
4021 {"bflr+", XLO(19,BOFP4
,16,0), XLBOBB_MASK
, ISA_V2
, PPCNONE
, {BI
}},
4022 {"bflrl+", XLO(19,BOFP4
,16,1), XLBOBB_MASK
, ISA_V2
, PPCNONE
, {BI
}},
4023 {"bdnztlr", XLO(19,BODNZT
,16,0), XLBOBB_MASK
, PPCCOM
, PPCNONE
, {BI
}},
4024 {"bdnztlr-", XLO(19,BODNZT
,16,0), XLBOBB_MASK
, PPCCOM
, ISA_V2
, {BI
}},
4025 {"bdnztlrl", XLO(19,BODNZT
,16,1), XLBOBB_MASK
, PPCCOM
, PPCNONE
, {BI
}},
4026 {"bdnztlrl-",XLO(19,BODNZT
,16,1), XLBOBB_MASK
, PPCCOM
, ISA_V2
, {BI
}},
4027 {"bdnztlr+", XLO(19,BODNZTP
,16,0), XLBOBB_MASK
, PPCCOM
, ISA_V2
, {BI
}},
4028 {"bdnztlrl+",XLO(19,BODNZTP
,16,1), XLBOBB_MASK
, PPCCOM
, ISA_V2
, {BI
}},
4029 {"bdztlr", XLO(19,BODZT
,16,0), XLBOBB_MASK
, PPCCOM
, PPCNONE
, {BI
}},
4030 {"bdztlr-", XLO(19,BODZT
,16,0), XLBOBB_MASK
, PPCCOM
, ISA_V2
, {BI
}},
4031 {"bdztlrl", XLO(19,BODZT
,16,1), XLBOBB_MASK
, PPCCOM
, PPCNONE
, {BI
}},
4032 {"bdztlrl-", XLO(19,BODZT
,16,1), XLBOBB_MASK
, PPCCOM
, ISA_V2
, {BI
}},
4033 {"bdztlr+", XLO(19,BODZTP
,16,0), XLBOBB_MASK
, PPCCOM
, ISA_V2
, {BI
}},
4034 {"bdztlrl+", XLO(19,BODZTP
,16,1), XLBOBB_MASK
, PPCCOM
, ISA_V2
, {BI
}},
4035 {"btlr", XLO(19,BOT
,16,0), XLBOBB_MASK
, PPCCOM
, PPCNONE
, {BI
}},
4036 {"btlr-", XLO(19,BOT
,16,0), XLBOBB_MASK
, PPCCOM
, ISA_V2
, {BI
}},
4037 {"bbtr", XLO(19,BOT
,16,0), XLBOBB_MASK
, PWRCOM
, PPCNONE
, {BI
}},
4038 {"btlrl", XLO(19,BOT
,16,1), XLBOBB_MASK
, PPCCOM
, PPCNONE
, {BI
}},
4039 {"btlrl-", XLO(19,BOT
,16,1), XLBOBB_MASK
, PPCCOM
, ISA_V2
, {BI
}},
4040 {"bbtrl", XLO(19,BOT
,16,1), XLBOBB_MASK
, PWRCOM
, PPCNONE
, {BI
}},
4041 {"btlr+", XLO(19,BOTP
,16,0), XLBOBB_MASK
, PPCCOM
, ISA_V2
, {BI
}},
4042 {"btlrl+", XLO(19,BOTP
,16,1), XLBOBB_MASK
, PPCCOM
, ISA_V2
, {BI
}},
4043 {"btlr-", XLO(19,BOTM4
,16,0), XLBOBB_MASK
, ISA_V2
, PPCNONE
, {BI
}},
4044 {"btlrl-", XLO(19,BOTM4
,16,1), XLBOBB_MASK
, ISA_V2
, PPCNONE
, {BI
}},
4045 {"btlr+", XLO(19,BOTP4
,16,0), XLBOBB_MASK
, ISA_V2
, PPCNONE
, {BI
}},
4046 {"btlrl+", XLO(19,BOTP4
,16,1), XLBOBB_MASK
, ISA_V2
, PPCNONE
, {BI
}},
4048 {"bclr-", XLYLK(19,16,0,0), XLYBB_MASK
, PPCCOM
, PPCNONE
, {BOE
, BI
}},
4049 {"bclrl-", XLYLK(19,16,0,1), XLYBB_MASK
, PPCCOM
, PPCNONE
, {BOE
, BI
}},
4050 {"bclr+", XLYLK(19,16,1,0), XLYBB_MASK
, PPCCOM
, PPCNONE
, {BOE
, BI
}},
4051 {"bclrl+", XLYLK(19,16,1,1), XLYBB_MASK
, PPCCOM
, PPCNONE
, {BOE
, BI
}},
4052 {"bclr", XLLK(19,16,0), XLBH_MASK
, PPCCOM
, PPCNONE
, {BO
, BI
, BH
}},
4053 {"bcr", XLLK(19,16,0), XLBB_MASK
, PWRCOM
, PPCNONE
, {BO
, BI
}},
4054 {"bclrl", XLLK(19,16,1), XLBH_MASK
, PPCCOM
, PPCNONE
, {BO
, BI
, BH
}},
4055 {"bcrl", XLLK(19,16,1), XLBB_MASK
, PWRCOM
, PPCNONE
, {BO
, BI
}},
4057 {"rfid", XL(19,18), 0xffffffff, PPC64
, PPCNONE
, {0}},
4059 {"crnot", XL(19,33), XL_MASK
, PPCCOM
, PPCNONE
, {BT
, BA
, BBA
}},
4060 {"crnor", XL(19,33), XL_MASK
, COM
, PPCNONE
, {BT
, BA
, BB
}},
4061 {"rfmci", X(19,38), 0xffffffff, PPCRFMCI
|PPCA2
|PPC476
, PPCNONE
, {0}},
4063 {"rfdi", XL(19,39), 0xffffffff, E500MC
, PPCNONE
, {0}},
4064 {"rfi", XL(19,50), 0xffffffff, COM
, PPCNONE
, {0}},
4065 {"rfci", XL(19,51), 0xffffffff, PPC403
|BOOKE
|PPCE300
|PPCA2
|PPC476
, PPCNONE
, {0}},
4067 {"rfsvc", XL(19,82), 0xffffffff, POWER
, PPCNONE
, {0}},
4069 {"rfgi", XL(19,102), 0xffffffff, E500MC
|PPCA2
, PPCNONE
, {0}},
4071 {"crandc", XL(19,129), XL_MASK
, COM
, PPCNONE
, {BT
, BA
, BB
}},
4073 {"rfebb", XL(19,146), XLS_MASK
, POWER8
, PPCNONE
, {SXL
}},
4075 {"isync", XL(19,150), 0xffffffff, PPCCOM
, PPCNONE
, {0}},
4076 {"ics", XL(19,150), 0xffffffff, PWRCOM
, PPCNONE
, {0}},
4078 {"crclr", XL(19,193), XL_MASK
, PPCCOM
, PPCNONE
, {BT
, BAT
, BBA
}},
4079 {"crxor", XL(19,193), XL_MASK
, COM
, PPCNONE
, {BT
, BA
, BB
}},
4081 {"dnh", X(19,198), X_MASK
, E500MC
, PPCNONE
, {DUI
, DUIS
}},
4083 {"crnand", XL(19,225), XL_MASK
, COM
, PPCNONE
, {BT
, BA
, BB
}},
4085 {"crand", XL(19,257), XL_MASK
, COM
, PPCNONE
, {BT
, BA
, BB
}},
4087 {"hrfid", XL(19,274), 0xffffffff, POWER5
|CELL
, PPC476
, {0}},
4089 {"crset", XL(19,289), XL_MASK
, PPCCOM
, PPCNONE
, {BT
, BAT
, BBA
}},
4090 {"creqv", XL(19,289), XL_MASK
, COM
, PPCNONE
, {BT
, BA
, BB
}},
4092 {"doze", XL(19,402), 0xffffffff, POWER6
, PPCNONE
, {0}},
4094 {"crorc", XL(19,417), XL_MASK
, COM
, PPCNONE
, {BT
, BA
, BB
}},
4096 {"nap", XL(19,434), 0xffffffff, POWER6
, PPCNONE
, {0}},
4098 {"crmove", XL(19,449), XL_MASK
, PPCCOM
, PPCNONE
, {BT
, BA
, BBA
}},
4099 {"cror", XL(19,449), XL_MASK
, COM
, PPCNONE
, {BT
, BA
, BB
}},
4101 {"sleep", XL(19,466), 0xffffffff, POWER6
, PPCNONE
, {0}},
4102 {"rvwinkle", XL(19,498), 0xffffffff, POWER6
, PPCNONE
, {0}},
4104 {"bctr", XLO(19,BOU
,528,0), XLBOBIBB_MASK
, COM
, PPCNONE
, {0}},
4105 {"bctrl", XLO(19,BOU
,528,1), XLBOBIBB_MASK
, COM
, PPCNONE
, {0}},
4107 {"bgectr", XLOCB(19,BOF
,CBLT
,528,0), XLBOCBBB_MASK
, PPCCOM
, PPCNONE
, {CR
}},
4108 {"bgectr-", XLOCB(19,BOF
,CBLT
,528,0), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
, {CR
}},
4109 {"bnlctr", XLOCB(19,BOF
,CBLT
,528,0), XLBOCBBB_MASK
, PPCCOM
, PPCNONE
, {CR
}},
4110 {"bnlctr-", XLOCB(19,BOF
,CBLT
,528,0), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
, {CR
}},
4111 {"bgectrl", XLOCB(19,BOF
,CBLT
,528,1), XLBOCBBB_MASK
, PPCCOM
, PPCNONE
, {CR
}},
4112 {"bgectrl-",XLOCB(19,BOF
,CBLT
,528,1), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
, {CR
}},
4113 {"bnlctrl", XLOCB(19,BOF
,CBLT
,528,1), XLBOCBBB_MASK
, PPCCOM
, PPCNONE
, {CR
}},
4114 {"bnlctrl-",XLOCB(19,BOF
,CBLT
,528,1), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
, {CR
}},
4115 {"blectr", XLOCB(19,BOF
,CBGT
,528,0), XLBOCBBB_MASK
, PPCCOM
, PPCNONE
, {CR
}},
4116 {"blectr-", XLOCB(19,BOF
,CBGT
,528,0), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
, {CR
}},
4117 {"bngctr", XLOCB(19,BOF
,CBGT
,528,0), XLBOCBBB_MASK
, PPCCOM
, PPCNONE
, {CR
}},
4118 {"bngctr-", XLOCB(19,BOF
,CBGT
,528,0), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
, {CR
}},
4119 {"blectrl", XLOCB(19,BOF
,CBGT
,528,1), XLBOCBBB_MASK
, PPCCOM
, PPCNONE
, {CR
}},
4120 {"blectrl-",XLOCB(19,BOF
,CBGT
,528,1), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
, {CR
}},
4121 {"bngctrl", XLOCB(19,BOF
,CBGT
,528,1), XLBOCBBB_MASK
, PPCCOM
, PPCNONE
, {CR
}},
4122 {"bngctrl-",XLOCB(19,BOF
,CBGT
,528,1), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
, {CR
}},
4123 {"bnectr", XLOCB(19,BOF
,CBEQ
,528,0), XLBOCBBB_MASK
, PPCCOM
, PPCNONE
, {CR
}},
4124 {"bnectr-", XLOCB(19,BOF
,CBEQ
,528,0), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
, {CR
}},
4125 {"bnectrl", XLOCB(19,BOF
,CBEQ
,528,1), XLBOCBBB_MASK
, PPCCOM
, PPCNONE
, {CR
}},
4126 {"bnectrl-",XLOCB(19,BOF
,CBEQ
,528,1), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
, {CR
}},
4127 {"bnsctr", XLOCB(19,BOF
,CBSO
,528,0), XLBOCBBB_MASK
, PPCCOM
, PPCNONE
, {CR
}},
4128 {"bnsctr-", XLOCB(19,BOF
,CBSO
,528,0), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
, {CR
}},
4129 {"bnuctr", XLOCB(19,BOF
,CBSO
,528,0), XLBOCBBB_MASK
, PPCCOM
, PPCNONE
, {CR
}},
4130 {"bnuctr-", XLOCB(19,BOF
,CBSO
,528,0), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
, {CR
}},
4131 {"bnsctrl", XLOCB(19,BOF
,CBSO
,528,1), XLBOCBBB_MASK
, PPCCOM
, PPCNONE
, {CR
}},
4132 {"bnsctrl-",XLOCB(19,BOF
,CBSO
,528,1), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
, {CR
}},
4133 {"bnuctrl", XLOCB(19,BOF
,CBSO
,528,1), XLBOCBBB_MASK
, PPCCOM
, PPCNONE
, {CR
}},
4134 {"bnuctrl-",XLOCB(19,BOF
,CBSO
,528,1), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
, {CR
}},
4135 {"bgectr+", XLOCB(19,BOFP
,CBLT
,528,0), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
, {CR
}},
4136 {"bnlctr+", XLOCB(19,BOFP
,CBLT
,528,0), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
, {CR
}},
4137 {"bgectrl+",XLOCB(19,BOFP
,CBLT
,528,1), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
, {CR
}},
4138 {"bnlctrl+",XLOCB(19,BOFP
,CBLT
,528,1), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
, {CR
}},
4139 {"blectr+", XLOCB(19,BOFP
,CBGT
,528,0), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
, {CR
}},
4140 {"bngctr+", XLOCB(19,BOFP
,CBGT
,528,0), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
, {CR
}},
4141 {"blectrl+",XLOCB(19,BOFP
,CBGT
,528,1), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
, {CR
}},
4142 {"bngctrl+",XLOCB(19,BOFP
,CBGT
,528,1), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
, {CR
}},
4143 {"bnectr+", XLOCB(19,BOFP
,CBEQ
,528,0), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
, {CR
}},
4144 {"bnectrl+",XLOCB(19,BOFP
,CBEQ
,528,1), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
, {CR
}},
4145 {"bnsctr+", XLOCB(19,BOFP
,CBSO
,528,0), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
, {CR
}},
4146 {"bnuctr+", XLOCB(19,BOFP
,CBSO
,528,0), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
, {CR
}},
4147 {"bnsctrl+",XLOCB(19,BOFP
,CBSO
,528,1), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
, {CR
}},
4148 {"bnuctrl+",XLOCB(19,BOFP
,CBSO
,528,1), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
, {CR
}},
4149 {"bgectr-", XLOCB(19,BOFM4
,CBLT
,528,0), XLBOCBBB_MASK
, ISA_V2
, PPCNONE
, {CR
}},
4150 {"bnlctr-", XLOCB(19,BOFM4
,CBLT
,528,0), XLBOCBBB_MASK
, ISA_V2
, PPCNONE
, {CR
}},
4151 {"bgectrl-",XLOCB(19,BOFM4
,CBLT
,528,1), XLBOCBBB_MASK
, ISA_V2
, PPCNONE
, {CR
}},
4152 {"bnlctrl-",XLOCB(19,BOFM4
,CBLT
,528,1), XLBOCBBB_MASK
, ISA_V2
, PPCNONE
, {CR
}},
4153 {"blectr-", XLOCB(19,BOFM4
,CBGT
,528,0), XLBOCBBB_MASK
, ISA_V2
, PPCNONE
, {CR
}},
4154 {"bngctr-", XLOCB(19,BOFM4
,CBGT
,528,0), XLBOCBBB_MASK
, ISA_V2
, PPCNONE
, {CR
}},
4155 {"blectrl-",XLOCB(19,BOFM4
,CBGT
,528,1), XLBOCBBB_MASK
, ISA_V2
, PPCNONE
, {CR
}},
4156 {"bngctrl-",XLOCB(19,BOFM4
,CBGT
,528,1), XLBOCBBB_MASK
, ISA_V2
, PPCNONE
, {CR
}},
4157 {"bnectr-", XLOCB(19,BOFM4
,CBEQ
,528,0), XLBOCBBB_MASK
, ISA_V2
, PPCNONE
, {CR
}},
4158 {"bnectrl-",XLOCB(19,BOFM4
,CBEQ
,528,1), XLBOCBBB_MASK
, ISA_V2
, PPCNONE
, {CR
}},
4159 {"bnsctr-", XLOCB(19,BOFM4
,CBSO
,528,0), XLBOCBBB_MASK
, ISA_V2
, PPCNONE
, {CR
}},
4160 {"bnuctr-", XLOCB(19,BOFM4
,CBSO
,528,0), XLBOCBBB_MASK
, ISA_V2
, PPCNONE
, {CR
}},
4161 {"bnsctrl-",XLOCB(19,BOFM4
,CBSO
,528,1), XLBOCBBB_MASK
, ISA_V2
, PPCNONE
, {CR
}},
4162 {"bnuctrl-",XLOCB(19,BOFM4
,CBSO
,528,1), XLBOCBBB_MASK
, ISA_V2
, PPCNONE
, {CR
}},
4163 {"bgectr+", XLOCB(19,BOFP4
,CBLT
,528,0), XLBOCBBB_MASK
, ISA_V2
, PPCNONE
, {CR
}},
4164 {"bnlctr+", XLOCB(19,BOFP4
,CBLT
,528,0), XLBOCBBB_MASK
, ISA_V2
, PPCNONE
, {CR
}},
4165 {"bgectrl+",XLOCB(19,BOFP4
,CBLT
,528,1), XLBOCBBB_MASK
, ISA_V2
, PPCNONE
, {CR
}},
4166 {"bnlctrl+",XLOCB(19,BOFP4
,CBLT
,528,1), XLBOCBBB_MASK
, ISA_V2
, PPCNONE
, {CR
}},
4167 {"blectr+", XLOCB(19,BOFP4
,CBGT
,528,0), XLBOCBBB_MASK
, ISA_V2
, PPCNONE
, {CR
}},
4168 {"bngctr+", XLOCB(19,BOFP4
,CBGT
,528,0), XLBOCBBB_MASK
, ISA_V2
, PPCNONE
, {CR
}},
4169 {"blectrl+",XLOCB(19,BOFP4
,CBGT
,528,1), XLBOCBBB_MASK
, ISA_V2
, PPCNONE
, {CR
}},
4170 {"bngctrl+",XLOCB(19,BOFP4
,CBGT
,528,1), XLBOCBBB_MASK
, ISA_V2
, PPCNONE
, {CR
}},
4171 {"bnectr+", XLOCB(19,BOFP4
,CBEQ
,528,0), XLBOCBBB_MASK
, ISA_V2
, PPCNONE
, {CR
}},
4172 {"bnectrl+",XLOCB(19,BOFP4
,CBEQ
,528,1), XLBOCBBB_MASK
, ISA_V2
, PPCNONE
, {CR
}},
4173 {"bnsctr+", XLOCB(19,BOFP4
,CBSO
,528,0), XLBOCBBB_MASK
, ISA_V2
, PPCNONE
, {CR
}},
4174 {"bnuctr+", XLOCB(19,BOFP4
,CBSO
,528,0), XLBOCBBB_MASK
, ISA_V2
, PPCNONE
, {CR
}},
4175 {"bnsctrl+",XLOCB(19,BOFP4
,CBSO
,528,1), XLBOCBBB_MASK
, ISA_V2
, PPCNONE
, {CR
}},
4176 {"bnuctrl+",XLOCB(19,BOFP4
,CBSO
,528,1), XLBOCBBB_MASK
, ISA_V2
, PPCNONE
, {CR
}},
4177 {"bltctr", XLOCB(19,BOT
,CBLT
,528,0), XLBOCBBB_MASK
, PPCCOM
, PPCNONE
, {CR
}},
4178 {"bltctr-", XLOCB(19,BOT
,CBLT
,528,0), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
, {CR
}},
4179 {"bltctrl", XLOCB(19,BOT
,CBLT
,528,1), XLBOCBBB_MASK
, PPCCOM
, PPCNONE
, {CR
}},
4180 {"bltctrl-",XLOCB(19,BOT
,CBLT
,528,1), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
, {CR
}},
4181 {"bgtctr", XLOCB(19,BOT
,CBGT
,528,0), XLBOCBBB_MASK
, PPCCOM
, PPCNONE
, {CR
}},
4182 {"bgtctr-", XLOCB(19,BOT
,CBGT
,528,0), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
, {CR
}},
4183 {"bgtctrl", XLOCB(19,BOT
,CBGT
,528,1), XLBOCBBB_MASK
, PPCCOM
, PPCNONE
, {CR
}},
4184 {"bgtctrl-",XLOCB(19,BOT
,CBGT
,528,1), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
, {CR
}},
4185 {"beqctr", XLOCB(19,BOT
,CBEQ
,528,0), XLBOCBBB_MASK
, PPCCOM
, PPCNONE
, {CR
}},
4186 {"beqctr-", XLOCB(19,BOT
,CBEQ
,528,0), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
, {CR
}},
4187 {"beqctrl", XLOCB(19,BOT
,CBEQ
,528,1), XLBOCBBB_MASK
, PPCCOM
, PPCNONE
, {CR
}},
4188 {"beqctrl-",XLOCB(19,BOT
,CBEQ
,528,1), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
, {CR
}},
4189 {"bsoctr", XLOCB(19,BOT
,CBSO
,528,0), XLBOCBBB_MASK
, PPCCOM
, PPCNONE
, {CR
}},
4190 {"bsoctr-", XLOCB(19,BOT
,CBSO
,528,0), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
, {CR
}},
4191 {"bunctr", XLOCB(19,BOT
,CBSO
,528,0), XLBOCBBB_MASK
, PPCCOM
, PPCNONE
, {CR
}},
4192 {"bunctr-", XLOCB(19,BOT
,CBSO
,528,0), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
, {CR
}},
4193 {"bsoctrl", XLOCB(19,BOT
,CBSO
,528,1), XLBOCBBB_MASK
, PPCCOM
, PPCNONE
, {CR
}},
4194 {"bsoctrl-",XLOCB(19,BOT
,CBSO
,528,1), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
, {CR
}},
4195 {"bunctrl", XLOCB(19,BOT
,CBSO
,528,1), XLBOCBBB_MASK
, PPCCOM
, PPCNONE
, {CR
}},
4196 {"bunctrl-",XLOCB(19,BOT
,CBSO
,528,1), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
, {CR
}},
4197 {"bltctr+", XLOCB(19,BOTP
,CBLT
,528,0), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
, {CR
}},
4198 {"bltctrl+",XLOCB(19,BOTP
,CBLT
,528,1), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
, {CR
}},
4199 {"bgtctr+", XLOCB(19,BOTP
,CBGT
,528,0), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
, {CR
}},
4200 {"bgtctrl+",XLOCB(19,BOTP
,CBGT
,528,1), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
, {CR
}},
4201 {"beqctr+", XLOCB(19,BOTP
,CBEQ
,528,0), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
, {CR
}},
4202 {"beqctrl+",XLOCB(19,BOTP
,CBEQ
,528,1), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
, {CR
}},
4203 {"bsoctr+", XLOCB(19,BOTP
,CBSO
,528,0), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
, {CR
}},
4204 {"bunctr+", XLOCB(19,BOTP
,CBSO
,528,0), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
, {CR
}},
4205 {"bsoctrl+",XLOCB(19,BOTP
,CBSO
,528,1), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
, {CR
}},
4206 {"bunctrl+",XLOCB(19,BOTP
,CBSO
,528,1), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
, {CR
}},
4207 {"bltctr-", XLOCB(19,BOTM4
,CBLT
,528,0), XLBOCBBB_MASK
, ISA_V2
, PPCNONE
, {CR
}},
4208 {"bltctrl-",XLOCB(19,BOTM4
,CBLT
,528,1), XLBOCBBB_MASK
, ISA_V2
, PPCNONE
, {CR
}},
4209 {"bgtctr-", XLOCB(19,BOTM4
,CBGT
,528,0), XLBOCBBB_MASK
, ISA_V2
, PPCNONE
, {CR
}},
4210 {"bgtctrl-",XLOCB(19,BOTM4
,CBGT
,528,1), XLBOCBBB_MASK
, ISA_V2
, PPCNONE
, {CR
}},
4211 {"beqctr-", XLOCB(19,BOTM4
,CBEQ
,528,0), XLBOCBBB_MASK
, ISA_V2
, PPCNONE
, {CR
}},
4212 {"beqctrl-",XLOCB(19,BOTM4
,CBEQ
,528,1), XLBOCBBB_MASK
, ISA_V2
, PPCNONE
, {CR
}},
4213 {"bsoctr-", XLOCB(19,BOTM4
,CBSO
,528,0), XLBOCBBB_MASK
, ISA_V2
, PPCNONE
, {CR
}},
4214 {"bunctr-", XLOCB(19,BOTM4
,CBSO
,528,0), XLBOCBBB_MASK
, ISA_V2
, PPCNONE
, {CR
}},
4215 {"bsoctrl-",XLOCB(19,BOTM4
,CBSO
,528,1), XLBOCBBB_MASK
, ISA_V2
, PPCNONE
, {CR
}},
4216 {"bunctrl-",XLOCB(19,BOTM4
,CBSO
,528,1), XLBOCBBB_MASK
, ISA_V2
, PPCNONE
, {CR
}},
4217 {"bltctr+", XLOCB(19,BOTP4
,CBLT
,528,0), XLBOCBBB_MASK
, ISA_V2
, PPCNONE
, {CR
}},
4218 {"bltctrl+",XLOCB(19,BOTP4
,CBLT
,528,1), XLBOCBBB_MASK
, ISA_V2
, PPCNONE
, {CR
}},
4219 {"bgtctr+", XLOCB(19,BOTP4
,CBGT
,528,0), XLBOCBBB_MASK
, ISA_V2
, PPCNONE
, {CR
}},
4220 {"bgtctrl+",XLOCB(19,BOTP4
,CBGT
,528,1), XLBOCBBB_MASK
, ISA_V2
, PPCNONE
, {CR
}},
4221 {"beqctr+", XLOCB(19,BOTP4
,CBEQ
,528,0), XLBOCBBB_MASK
, ISA_V2
, PPCNONE
, {CR
}},
4222 {"beqctrl+",XLOCB(19,BOTP4
,CBEQ
,528,1), XLBOCBBB_MASK
, ISA_V2
, PPCNONE
, {CR
}},
4223 {"bsoctr+", XLOCB(19,BOTP4
,CBSO
,528,0), XLBOCBBB_MASK
, ISA_V2
, PPCNONE
, {CR
}},
4224 {"bunctr+", XLOCB(19,BOTP4
,CBSO
,528,0), XLBOCBBB_MASK
, ISA_V2
, PPCNONE
, {CR
}},
4225 {"bsoctrl+",XLOCB(19,BOTP4
,CBSO
,528,1), XLBOCBBB_MASK
, ISA_V2
, PPCNONE
, {CR
}},
4226 {"bunctrl+",XLOCB(19,BOTP4
,CBSO
,528,1), XLBOCBBB_MASK
, ISA_V2
, PPCNONE
, {CR
}},
4228 {"bfctr", XLO(19,BOF
,528,0), XLBOBB_MASK
, PPCCOM
, PPCNONE
, {BI
}},
4229 {"bfctr-", XLO(19,BOF
,528,0), XLBOBB_MASK
, PPCCOM
, ISA_V2
, {BI
}},
4230 {"bfctrl", XLO(19,BOF
,528,1), XLBOBB_MASK
, PPCCOM
, PPCNONE
, {BI
}},
4231 {"bfctrl-", XLO(19,BOF
,528,1), XLBOBB_MASK
, PPCCOM
, ISA_V2
, {BI
}},
4232 {"bfctr+", XLO(19,BOFP
,528,0), XLBOBB_MASK
, PPCCOM
, ISA_V2
, {BI
}},
4233 {"bfctrl+", XLO(19,BOFP
,528,1), XLBOBB_MASK
, PPCCOM
, ISA_V2
, {BI
}},
4234 {"bfctr-", XLO(19,BOFM4
,528,0), XLBOBB_MASK
, ISA_V2
, PPCNONE
, {BI
}},
4235 {"bfctrl-", XLO(19,BOFM4
,528,1), XLBOBB_MASK
, ISA_V2
, PPCNONE
, {BI
}},
4236 {"bfctr+", XLO(19,BOFP4
,528,0), XLBOBB_MASK
, ISA_V2
, PPCNONE
, {BI
}},
4237 {"bfctrl+", XLO(19,BOFP4
,528,1), XLBOBB_MASK
, ISA_V2
, PPCNONE
, {BI
}},
4238 {"btctr", XLO(19,BOT
,528,0), XLBOBB_MASK
, PPCCOM
, PPCNONE
, {BI
}},
4239 {"btctr-", XLO(19,BOT
,528,0), XLBOBB_MASK
, PPCCOM
, ISA_V2
, {BI
}},
4240 {"btctrl", XLO(19,BOT
,528,1), XLBOBB_MASK
, PPCCOM
, PPCNONE
, {BI
}},
4241 {"btctrl-", XLO(19,BOT
,528,1), XLBOBB_MASK
, PPCCOM
, ISA_V2
, {BI
}},
4242 {"btctr+", XLO(19,BOTP
,528,0), XLBOBB_MASK
, PPCCOM
, ISA_V2
, {BI
}},
4243 {"btctrl+", XLO(19,BOTP
,528,1), XLBOBB_MASK
, PPCCOM
, ISA_V2
, {BI
}},
4244 {"btctr-", XLO(19,BOTM4
,528,0), XLBOBB_MASK
, ISA_V2
, PPCNONE
, {BI
}},
4245 {"btctrl-", XLO(19,BOTM4
,528,1), XLBOBB_MASK
, ISA_V2
, PPCNONE
, {BI
}},
4246 {"btctr+", XLO(19,BOTP4
,528,0), XLBOBB_MASK
, ISA_V2
, PPCNONE
, {BI
}},
4247 {"btctrl+", XLO(19,BOTP4
,528,1), XLBOBB_MASK
, ISA_V2
, PPCNONE
, {BI
}},
4249 {"bcctr-", XLYLK(19,528,0,0), XLYBB_MASK
, PPCCOM
, PPCNONE
, {BOE
, BI
}},
4250 {"bcctrl-", XLYLK(19,528,0,1), XLYBB_MASK
, PPCCOM
, PPCNONE
, {BOE
, BI
}},
4251 {"bcctr+", XLYLK(19,528,1,0), XLYBB_MASK
, PPCCOM
, PPCNONE
, {BOE
, BI
}},
4252 {"bcctrl+", XLYLK(19,528,1,1), XLYBB_MASK
, PPCCOM
, PPCNONE
, {BOE
, BI
}},
4253 {"bcctr", XLLK(19,528,0), XLBH_MASK
, PPCCOM
, PPCNONE
, {BO
, BI
, BH
}},
4254 {"bcc", XLLK(19,528,0), XLBB_MASK
, PWRCOM
, PPCNONE
, {BO
, BI
}},
4255 {"bcctrl", XLLK(19,528,1), XLBH_MASK
, PPCCOM
, PPCNONE
, {BO
, BI
, BH
}},
4256 {"bccl", XLLK(19,528,1), XLBB_MASK
, PWRCOM
, PPCNONE
, {BO
, BI
}},
4258 {"bctar-", XLYLK(19,560,0,0), XLYBB_MASK
, POWER8
, PPCNONE
, {BOE
, BI
}},
4259 {"bctarl-", XLYLK(19,560,0,1), XLYBB_MASK
, POWER8
, PPCNONE
, {BOE
, BI
}},
4260 {"bctar+", XLYLK(19,560,1,0), XLYBB_MASK
, POWER8
, PPCNONE
, {BOE
, BI
}},
4261 {"bctarl+", XLYLK(19,560,1,1), XLYBB_MASK
, POWER8
, PPCNONE
, {BOE
, BI
}},
4262 {"bctar", XLLK(19,560,0), XLBH_MASK
, POWER8
, PPCNONE
, {BO
, BI
, BH
}},
4263 {"bctarl", XLLK(19,560,1), XLBH_MASK
, POWER8
, PPCNONE
, {BO
, BI
, BH
}},
4265 {"rlwimi", M(20,0), M_MASK
, PPCCOM
, PPCNONE
, {RA
, RS
, SH
, MBE
, ME
}},
4266 {"rlimi", M(20,0), M_MASK
, PWRCOM
, PPCNONE
, {RA
, RS
, SH
, MBE
, ME
}},
4268 {"rlwimi.", M(20,1), M_MASK
, PPCCOM
, PPCNONE
, {RA
, RS
, SH
, MBE
, ME
}},
4269 {"rlimi.", M(20,1), M_MASK
, PWRCOM
, PPCNONE
, {RA
, RS
, SH
, MBE
, ME
}},
4271 {"rotlwi", MME(21,31,0), MMBME_MASK
, PPCCOM
, PPCNONE
, {RA
, RS
, SH
}},
4272 {"clrlwi", MME(21,31,0), MSHME_MASK
, PPCCOM
, PPCNONE
, {RA
, RS
, MB
}},
4273 {"rlwinm", M(21,0), M_MASK
, PPCCOM
, PPCNONE
, {RA
, RS
, SH
, MBE
, ME
}},
4274 {"rlinm", M(21,0), M_MASK
, PWRCOM
, PPCNONE
, {RA
, RS
, SH
, MBE
, ME
}},
4275 {"rotlwi.", MME(21,31,1), MMBME_MASK
, PPCCOM
, PPCNONE
, {RA
, RS
, SH
}},
4276 {"clrlwi.", MME(21,31,1), MSHME_MASK
, PPCCOM
, PPCNONE
, {RA
, RS
, MB
}},
4277 {"rlwinm.", M(21,1), M_MASK
, PPCCOM
, PPCNONE
, {RA
, RS
, SH
, MBE
, ME
}},
4278 {"rlinm.", M(21,1), M_MASK
, PWRCOM
, PPCNONE
, {RA
, RS
, SH
, MBE
, ME
}},
4280 {"rlmi", M(22,0), M_MASK
, M601
, PPCNONE
, {RA
, RS
, RB
, MBE
, ME
}},
4281 {"rlmi.", M(22,1), M_MASK
, M601
, PPCNONE
, {RA
, RS
, RB
, MBE
, ME
}},
4283 {"rotlw", MME(23,31,0), MMBME_MASK
, PPCCOM
, PPCNONE
, {RA
, RS
, RB
}},
4284 {"rlwnm", M(23,0), M_MASK
, PPCCOM
, PPCNONE
, {RA
, RS
, RB
, MBE
, ME
}},
4285 {"rlnm", M(23,0), M_MASK
, PWRCOM
, PPCNONE
, {RA
, RS
, RB
, MBE
, ME
}},
4286 {"rotlw.", MME(23,31,1), MMBME_MASK
, PPCCOM
, PPCNONE
, {RA
, RS
, RB
}},
4287 {"rlwnm.", M(23,1), M_MASK
, PPCCOM
, PPCNONE
, {RA
, RS
, RB
, MBE
, ME
}},
4288 {"rlnm.", M(23,1), M_MASK
, PWRCOM
, PPCNONE
, {RA
, RS
, RB
, MBE
, ME
}},
4290 {"nop", OP(24), 0xffffffff, PPCCOM
, PPCNONE
, {0}},
4291 {"ori", OP(24), OP_MASK
, PPCCOM
, PPCNONE
, {RA
, RS
, UI
}},
4292 {"oril", OP(24), OP_MASK
, PWRCOM
, PPCNONE
, {RA
, RS
, UI
}},
4294 {"oris", OP(25), OP_MASK
, PPCCOM
, PPCNONE
, {RA
, RS
, UI
}},
4295 {"oriu", OP(25), OP_MASK
, PWRCOM
, PPCNONE
, {RA
, RS
, UI
}},
4297 {"xnop", OP(26), 0xffffffff, PPCCOM
, PPCNONE
, {0}},
4298 {"xori", OP(26), OP_MASK
, PPCCOM
, PPCNONE
, {RA
, RS
, UI
}},
4299 {"xoril", OP(26), OP_MASK
, PWRCOM
, PPCNONE
, {RA
, RS
, UI
}},
4301 {"xoris", OP(27), OP_MASK
, PPCCOM
, PPCNONE
, {RA
, RS
, UI
}},
4302 {"xoriu", OP(27), OP_MASK
, PWRCOM
, PPCNONE
, {RA
, RS
, UI
}},
4304 {"andi.", OP(28), OP_MASK
, PPCCOM
, PPCNONE
, {RA
, RS
, UI
}},
4305 {"andil.", OP(28), OP_MASK
, PWRCOM
, PPCNONE
, {RA
, RS
, UI
}},
4307 {"andis.", OP(29), OP_MASK
, PPCCOM
, PPCNONE
, {RA
, RS
, UI
}},
4308 {"andiu.", OP(29), OP_MASK
, PWRCOM
, PPCNONE
, {RA
, RS
, UI
}},
4310 {"rotldi", MD(30,0,0), MDMB_MASK
, PPC64
, PPCNONE
, {RA
, RS
, SH6
}},
4311 {"clrldi", MD(30,0,0), MDSH_MASK
, PPC64
, PPCNONE
, {RA
, RS
, MB6
}},
4312 {"rldicl", MD(30,0,0), MD_MASK
, PPC64
, PPCNONE
, {RA
, RS
, SH6
, MB6
}},
4313 {"rotldi.", MD(30,0,1), MDMB_MASK
, PPC64
, PPCNONE
, {RA
, RS
, SH6
}},
4314 {"clrldi.", MD(30,0,1), MDSH_MASK
, PPC64
, PPCNONE
, {RA
, RS
, MB6
}},
4315 {"rldicl.", MD(30,0,1), MD_MASK
, PPC64
, PPCNONE
, {RA
, RS
, SH6
, MB6
}},
4317 {"rldicr", MD(30,1,0), MD_MASK
, PPC64
, PPCNONE
, {RA
, RS
, SH6
, ME6
}},
4318 {"rldicr.", MD(30,1,1), MD_MASK
, PPC64
, PPCNONE
, {RA
, RS
, SH6
, ME6
}},
4320 {"rldic", MD(30,2,0), MD_MASK
, PPC64
, PPCNONE
, {RA
, RS
, SH6
, MB6
}},
4321 {"rldic.", MD(30,2,1), MD_MASK
, PPC64
, PPCNONE
, {RA
, RS
, SH6
, MB6
}},
4323 {"rldimi", MD(30,3,0), MD_MASK
, PPC64
, PPCNONE
, {RA
, RS
, SH6
, MB6
}},
4324 {"rldimi.", MD(30,3,1), MD_MASK
, PPC64
, PPCNONE
, {RA
, RS
, SH6
, MB6
}},
4326 {"rotld", MDS(30,8,0), MDSMB_MASK
, PPC64
, PPCNONE
, {RA
, RS
, RB
}},
4327 {"rldcl", MDS(30,8,0), MDS_MASK
, PPC64
, PPCNONE
, {RA
, RS
, RB
, MB6
}},
4328 {"rotld.", MDS(30,8,1), MDSMB_MASK
, PPC64
, PPCNONE
, {RA
, RS
, RB
}},
4329 {"rldcl.", MDS(30,8,1), MDS_MASK
, PPC64
, PPCNONE
, {RA
, RS
, RB
, MB6
}},
4331 {"rldcr", MDS(30,9,0), MDS_MASK
, PPC64
, PPCNONE
, {RA
, RS
, RB
, ME6
}},
4332 {"rldcr.", MDS(30,9,1), MDS_MASK
, PPC64
, PPCNONE
, {RA
, RS
, RB
, ME6
}},
4334 {"cmpw", XOPL(31,0,0), XCMPL_MASK
, PPCCOM
, PPCNONE
, {OBF
, RA
, RB
}},
4335 {"cmpd", XOPL(31,0,1), XCMPL_MASK
, PPC64
, PPCNONE
, {OBF
, RA
, RB
}},
4336 {"cmp", X(31,0), XCMP_MASK
, PPC
|PPCVLE
, PPCNONE
, {BF
, L
, RA
, RB
}},
4337 {"cmp", X(31,0), XCMPL_MASK
, PWRCOM
, PPC
, {BF
, RA
, RB
}},
4339 {"twlgt", XTO(31,4,TOLGT
), XTO_MASK
, PPCCOM
|PPCVLE
, PPCNONE
, {RA
, RB
}},
4340 {"tlgt", XTO(31,4,TOLGT
), XTO_MASK
, PWRCOM
, PPCNONE
, {RA
, RB
}},
4341 {"twllt", XTO(31,4,TOLLT
), XTO_MASK
, PPCCOM
|PPCVLE
, PPCNONE
, {RA
, RB
}},
4342 {"tllt", XTO(31,4,TOLLT
), XTO_MASK
, PWRCOM
, PPCNONE
, {RA
, RB
}},
4343 {"tweq", XTO(31,4,TOEQ
), XTO_MASK
, PPCCOM
|PPCVLE
, PPCNONE
, {RA
, RB
}},
4344 {"teq", XTO(31,4,TOEQ
), XTO_MASK
, PWRCOM
, PPCNONE
, {RA
, RB
}},
4345 {"twlge", XTO(31,4,TOLGE
), XTO_MASK
, PPCCOM
|PPCVLE
, PPCNONE
, {RA
, RB
}},
4346 {"tlge", XTO(31,4,TOLGE
), XTO_MASK
, PWRCOM
, PPCNONE
, {RA
, RB
}},
4347 {"twlnl", XTO(31,4,TOLNL
), XTO_MASK
, PPCCOM
|PPCVLE
, PPCNONE
, {RA
, RB
}},
4348 {"tlnl", XTO(31,4,TOLNL
), XTO_MASK
, PWRCOM
, PPCNONE
, {RA
, RB
}},
4349 {"twlle", XTO(31,4,TOLLE
), XTO_MASK
, PPCCOM
|PPCVLE
, PPCNONE
, {RA
, RB
}},
4350 {"tlle", XTO(31,4,TOLLE
), XTO_MASK
, PWRCOM
, PPCNONE
, {RA
, RB
}},
4351 {"twlng", XTO(31,4,TOLNG
), XTO_MASK
, PPCCOM
|PPCVLE
, PPCNONE
, {RA
, RB
}},
4352 {"tlng", XTO(31,4,TOLNG
), XTO_MASK
, PWRCOM
, PPCNONE
, {RA
, RB
}},
4353 {"twgt", XTO(31,4,TOGT
), XTO_MASK
, PPCCOM
|PPCVLE
, PPCNONE
, {RA
, RB
}},
4354 {"tgt", XTO(31,4,TOGT
), XTO_MASK
, PWRCOM
, PPCNONE
, {RA
, RB
}},
4355 {"twge", XTO(31,4,TOGE
), XTO_MASK
, PPCCOM
|PPCVLE
, PPCNONE
, {RA
, RB
}},
4356 {"tge", XTO(31,4,TOGE
), XTO_MASK
, PWRCOM
, PPCNONE
, {RA
, RB
}},
4357 {"twnl", XTO(31,4,TONL
), XTO_MASK
, PPCCOM
|PPCVLE
, PPCNONE
, {RA
, RB
}},
4358 {"tnl", XTO(31,4,TONL
), XTO_MASK
, PWRCOM
, PPCNONE
, {RA
, RB
}},
4359 {"twlt", XTO(31,4,TOLT
), XTO_MASK
, PPCCOM
|PPCVLE
, PPCNONE
, {RA
, RB
}},
4360 {"tlt", XTO(31,4,TOLT
), XTO_MASK
, PWRCOM
, PPCNONE
, {RA
, RB
}},
4361 {"twle", XTO(31,4,TOLE
), XTO_MASK
, PPCCOM
|PPCVLE
, PPCNONE
, {RA
, RB
}},
4362 {"tle", XTO(31,4,TOLE
), XTO_MASK
, PWRCOM
, PPCNONE
, {RA
, RB
}},
4363 {"twng", XTO(31,4,TONG
), XTO_MASK
, PPCCOM
|PPCVLE
, PPCNONE
, {RA
, RB
}},
4364 {"tng", XTO(31,4,TONG
), XTO_MASK
, PWRCOM
, PPCNONE
, {RA
, RB
}},
4365 {"twne", XTO(31,4,TONE
), XTO_MASK
, PPCCOM
|PPCVLE
, PPCNONE
, {RA
, RB
}},
4366 {"tne", XTO(31,4,TONE
), XTO_MASK
, PWRCOM
, PPCNONE
, {RA
, RB
}},
4367 {"trap", XTO(31,4,TOU
), 0xffffffff, PPCCOM
|PPCVLE
, PPCNONE
, {0}},
4368 {"twu", XTO(31,4,TOU
), XTO_MASK
, PPCCOM
|PPCVLE
, PPCNONE
, {RA
, RB
}},
4369 {"tu", XTO(31,4,TOU
), XTO_MASK
, PWRCOM
, PPCNONE
, {RA
, RB
}},
4370 {"tw", X(31,4), X_MASK
, PPCCOM
|PPCVLE
, PPCNONE
, {TO
, RA
, RB
}},
4371 {"t", X(31,4), X_MASK
, PWRCOM
, PPCNONE
, {TO
, RA
, RB
}},
4373 {"lvsl", X(31,6), X_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, RA0
, RB
}},
4374 {"lvebx", X(31,7), X_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, RA0
, RB
}},
4375 {"lbfcmx", APU(31,7,0), APU_MASK
, PPC405
, PPCNONE
, {FCRT
, RA
, RB
}},
4377 {"subfc", XO(31,8,0,0), XO_MASK
, PPCCOM
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
4378 {"sf", XO(31,8,0,0), XO_MASK
, PWRCOM
, PPCNONE
, {RT
, RA
, RB
}},
4379 {"subc", XO(31,8,0,0), XO_MASK
, PPCCOM
|PPCVLE
, PPCNONE
, {RT
, RB
, RA
}},
4380 {"subfc.", XO(31,8,0,1), XO_MASK
, PPCCOM
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
4381 {"sf.", XO(31,8,0,1), XO_MASK
, PWRCOM
, PPCNONE
, {RT
, RA
, RB
}},
4382 {"subc.", XO(31,8,0,1), XO_MASK
, PPCCOM
|PPCVLE
, PPCNONE
, {RT
, RB
, RA
}},
4384 {"mulhdu", XO(31,9,0,0), XO_MASK
, PPC64
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
4385 {"mulhdu.", XO(31,9,0,1), XO_MASK
, PPC64
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
4387 {"addc", XO(31,10,0,0), XO_MASK
, PPCCOM
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
4388 {"a", XO(31,10,0,0), XO_MASK
, PWRCOM
, PPCNONE
, {RT
, RA
, RB
}},
4389 {"addc.", XO(31,10,0,1), XO_MASK
, PPCCOM
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
4390 {"a.", XO(31,10,0,1), XO_MASK
, PWRCOM
, PPCNONE
, {RT
, RA
, RB
}},
4392 {"mulhwu", XO(31,11,0,0), XO_MASK
, PPC
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
4393 {"mulhwu.", XO(31,11,0,1), XO_MASK
, PPC
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
4395 {"lxsiwzx", X(31,12), XX1_MASK
, PPCVSX2
, PPCNONE
, {XT6
, RA0
, RB
}},
4397 {"isellt", X(31,15), X_MASK
, PPCISEL
, PPCNONE
, {RT
, RA0
, RB
}},
4399 {"tlbilxlpid", XTO(31,18,0), XTO_MASK
, E500MC
|PPCA2
, PPCNONE
, {0}},
4400 {"tlbilxpid", XTO(31,18,1), XTO_MASK
, E500MC
|PPCA2
, PPCNONE
, {0}},
4401 {"tlbilxva", XTO(31,18,3), XTO_MASK
, E500MC
|PPCA2
, PPCNONE
, {RA0
, RB
}},
4402 {"tlbilx", X(31,18), X_MASK
, E500MC
|PPCA2
, PPCNONE
, {T
, RA0
, RB
}},
4404 {"mfcr", XFXM(31,19,0,0), XFXFXM_MASK
, POWER4
, PPCNONE
, {RT
, FXM4
}},
4405 {"mfcr", XFXM(31,19,0,0), XRARB_MASK
, COM
|PPCVLE
, POWER4
, {RT
}},
4406 {"mfocrf", XFXM(31,19,0,1), XFXFXM_MASK
, COM
|PPCVLE
, PPCNONE
, {RT
, FXM
}},
4408 {"lwarx", X(31,20), XEH_MASK
, PPC
|PPCVLE
, PPCNONE
, {RT
, RA0
, RB
, EH
}},
4410 {"ldx", X(31,21), X_MASK
, PPC64
|PPCVLE
, PPCNONE
, {RT
, RA0
, RB
}},
4412 {"icbt", X(31,22), X_MASK
, BOOKE
|PPCE300
|PPCA2
|PPC476
|PPCVLE
, PPCNONE
, {CT
, RA0
, RB
}},
4414 {"lwzx", X(31,23), X_MASK
, PPCCOM
|PPCVLE
, PPCNONE
, {RT
, RA0
, RB
}},
4415 {"lx", X(31,23), X_MASK
, PWRCOM
, PPCNONE
, {RT
, RA
, RB
}},
4417 {"slw", XRC(31,24,0), X_MASK
, PPCCOM
|PPCVLE
, PPCNONE
, {RA
, RS
, RB
}},
4418 {"sl", XRC(31,24,0), X_MASK
, PWRCOM
, PPCNONE
, {RA
, RS
, RB
}},
4419 {"slw.", XRC(31,24,1), X_MASK
, PPCCOM
|PPCVLE
, PPCNONE
, {RA
, RS
, RB
}},
4420 {"sl.", XRC(31,24,1), X_MASK
, PWRCOM
, PPCNONE
, {RA
, RS
, RB
}},
4422 {"cntlzw", XRC(31,26,0), XRB_MASK
, PPCCOM
|PPCVLE
, PPCNONE
, {RA
, RS
}},
4423 {"cntlz", XRC(31,26,0), XRB_MASK
, PWRCOM
, PPCNONE
, {RA
, RS
}},
4424 {"cntlzw.", XRC(31,26,1), XRB_MASK
, PPCCOM
|PPCVLE
, PPCNONE
, {RA
, RS
}},
4425 {"cntlz.", XRC(31,26,1), XRB_MASK
, PWRCOM
, PPCNONE
, {RA
, RS
}},
4427 {"sld", XRC(31,27,0), X_MASK
, PPC64
, PPCNONE
, {RA
, RS
, RB
}},
4428 {"sld.", XRC(31,27,1), X_MASK
, PPC64
, PPCNONE
, {RA
, RS
, RB
}},
4430 {"and", XRC(31,28,0), X_MASK
, COM
|PPCVLE
, PPCNONE
, {RA
, RS
, RB
}},
4431 {"and.", XRC(31,28,1), X_MASK
, COM
|PPCVLE
, PPCNONE
, {RA
, RS
, RB
}},
4433 {"maskg", XRC(31,29,0), X_MASK
, M601
, PPCA2
, {RA
, RS
, RB
}},
4434 {"maskg.", XRC(31,29,1), X_MASK
, M601
, PPCA2
, {RA
, RS
, RB
}},
4436 {"ldepx", X(31,29), X_MASK
, E500MC
|PPCA2
|PPCVLE
, PPCNONE
, {RT
, RA0
, RB
}},
4438 {"waitasec", X(31,30), XRTRARB_MASK
,POWER8
, PPCNONE
, {0}},
4440 {"lwepx", X(31,31), X_MASK
, E500MC
|PPCA2
|PPCVLE
, PPCNONE
, {RT
, RA0
, RB
}},
4442 {"cmplw", XOPL(31,32,0), XCMPL_MASK
, PPCCOM
|PPCVLE
, PPCNONE
, {OBF
, RA
, RB
}},
4443 {"cmpld", XOPL(31,32,1), XCMPL_MASK
, PPC64
, PPCNONE
, {OBF
, RA
, RB
}},
4444 {"cmpl", X(31,32), XCMP_MASK
, PPC
|PPCVLE
, PPCNONE
, {BF
, L
, RA
, RB
}},
4445 {"cmpl", X(31,32), XCMPL_MASK
, PWRCOM
, PPC
, {BF
, RA
, RB
}},
4447 {"lvsr", X(31,38), X_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, RA0
, RB
}},
4448 {"lvehx", X(31,39), X_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, RA0
, RB
}},
4449 {"lhfcmx", APU(31,39,0), APU_MASK
, PPC405
, PPCNONE
, {FCRT
, RA
, RB
}},
4451 {"mviwsplt", X(31,46), X_MASK
, PPCVEC2
, PPCNONE
, {VD
, RA
, RB
}},
4453 {"iselgt", X(31,47), X_MASK
, PPCISEL
, PPCNONE
, {RT
, RA0
, RB
}},
4455 {"lvewx", X(31,71), X_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, RA0
, RB
}},
4457 {"addg6s", XO(31,74,0,0), XO_MASK
, POWER6
, PPCNONE
, {RT
, RA
, RB
}},
4459 {"lxsiwax", X(31,76), XX1_MASK
, PPCVSX2
, PPCNONE
, {XT6
, RA0
, RB
}},
4461 {"iseleq", X(31,79), X_MASK
, PPCISEL
, PPCNONE
, {RT
, RA0
, RB
}},
4463 {"isel", XISEL(31,15), XISEL_MASK
, PPCISEL
|TITAN
|PPCVLE
, PPCNONE
, {RT
, RA0
, RB
, CRB
}},
4465 {"subf", XO(31,40,0,0), XO_MASK
, PPC
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
4466 {"sub", XO(31,40,0,0), XO_MASK
, PPC
|PPCVLE
, PPCNONE
, {RT
, RB
, RA
}},
4467 {"subf.", XO(31,40,0,1), XO_MASK
, PPC
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
4468 {"sub.", XO(31,40,0,1), XO_MASK
, PPC
|PPCVLE
, PPCNONE
, {RT
, RB
, RA
}},
4470 {"mfvsrd", X(31,51), XX1RB_MASK
, PPCVSX2
, PPCNONE
, {RA
, XS6
}},
4471 {"mffprd", X(31,51), XX1RB_MASK
|1, PPCVSX2
, PPCNONE
, {RA
, FRS
}},
4472 {"mfvrd", X(31,51)|1, XX1RB_MASK
|1, PPCVSX2
, PPCNONE
, {RA
, VS
}},
4473 {"eratilx", X(31,51), X_MASK
, PPCA2
, PPCNONE
, {ERAT_T
, RA
, RB
}},
4475 {"lbarx", X(31,52), XEH_MASK
, POWER8
|PPCVLE
, PPCNONE
, {RT
, RA0
, RB
, EH
}},
4477 {"ldux", X(31,53), X_MASK
, PPC64
|PPCVLE
, PPCNONE
, {RT
, RAL
, RB
}},
4479 {"dcbst", X(31,54), XRT_MASK
, PPC
|PPCVLE
, PPCNONE
, {RA0
, RB
}},
4481 {"lwzux", X(31,55), X_MASK
, PPCCOM
|PPCVLE
, PPCNONE
, {RT
, RAL
, RB
}},
4482 {"lux", X(31,55), X_MASK
, PWRCOM
, PPCNONE
, {RT
, RA
, RB
}},
4484 {"cntlzd", XRC(31,58,0), XRB_MASK
, PPC64
|PPCVLE
, PPCNONE
, {RA
, RS
}},
4485 {"cntlzd.", XRC(31,58,1), XRB_MASK
, PPC64
|PPCVLE
, PPCNONE
, {RA
, RS
}},
4487 {"andc", XRC(31,60,0), X_MASK
, COM
|PPCVLE
, PPCNONE
, {RA
, RS
, RB
}},
4488 {"andc.", XRC(31,60,1), X_MASK
, COM
|PPCVLE
, PPCNONE
, {RA
, RS
, RB
}},
4490 {"waitrsv", X(31,62)|(1<<21), 0xffffffff, E500MC
|PPCA2
, PPCNONE
, {0}},
4491 {"waitimpl", X(31,62)|(2<<21), 0xffffffff, E500MC
|PPCA2
, PPCNONE
, {0}},
4492 {"wait", X(31,62), XWC_MASK
, E500MC
|PPCA2
|PPCVLE
, PPCNONE
, {WC
}},
4494 {"dcbstep", XRT(31,63,0), XRT_MASK
, E500MC
|PPCA2
|PPCVLE
, PPCNONE
, {RA0
, RB
}},
4496 {"tdlgt", XTO(31,68,TOLGT
), XTO_MASK
, PPC64
, PPCNONE
, {RA
, RB
}},
4497 {"tdllt", XTO(31,68,TOLLT
), XTO_MASK
, PPC64
, PPCNONE
, {RA
, RB
}},
4498 {"tdeq", XTO(31,68,TOEQ
), XTO_MASK
, PPC64
, PPCNONE
, {RA
, RB
}},
4499 {"tdlge", XTO(31,68,TOLGE
), XTO_MASK
, PPC64
, PPCNONE
, {RA
, RB
}},
4500 {"tdlnl", XTO(31,68,TOLNL
), XTO_MASK
, PPC64
, PPCNONE
, {RA
, RB
}},
4501 {"tdlle", XTO(31,68,TOLLE
), XTO_MASK
, PPC64
, PPCNONE
, {RA
, RB
}},
4502 {"tdlng", XTO(31,68,TOLNG
), XTO_MASK
, PPC64
, PPCNONE
, {RA
, RB
}},
4503 {"tdgt", XTO(31,68,TOGT
), XTO_MASK
, PPC64
, PPCNONE
, {RA
, RB
}},
4504 {"tdge", XTO(31,68,TOGE
), XTO_MASK
, PPC64
, PPCNONE
, {RA
, RB
}},
4505 {"tdnl", XTO(31,68,TONL
), XTO_MASK
, PPC64
, PPCNONE
, {RA
, RB
}},
4506 {"tdlt", XTO(31,68,TOLT
), XTO_MASK
, PPC64
, PPCNONE
, {RA
, RB
}},
4507 {"tdle", XTO(31,68,TOLE
), XTO_MASK
, PPC64
, PPCNONE
, {RA
, RB
}},
4508 {"tdng", XTO(31,68,TONG
), XTO_MASK
, PPC64
, PPCNONE
, {RA
, RB
}},
4509 {"tdne", XTO(31,68,TONE
), XTO_MASK
, PPC64
, PPCNONE
, {RA
, RB
}},
4510 {"tdu", XTO(31,68,TOU
), XTO_MASK
, PPC64
, PPCNONE
, {RA
, RB
}},
4511 {"td", X(31,68), X_MASK
, PPC64
|PPCVLE
, PPCNONE
, {TO
, RA
, RB
}},
4513 {"lwfcmx", APU(31,71,0), APU_MASK
, PPC405
, PPCNONE
, {FCRT
, RA
, RB
}},
4514 {"mulhd", XO(31,73,0,0), XO_MASK
, PPC64
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
4515 {"mulhd.", XO(31,73,0,1), XO_MASK
, PPC64
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
4517 {"mulhw", XO(31,75,0,0), XO_MASK
, PPC
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
4518 {"mulhw.", XO(31,75,0,1), XO_MASK
, PPC
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
4520 {"dlmzb", XRC(31,78,0), X_MASK
, PPC403
|PPC440
|TITAN
|PPCVLE
, PPCNONE
, {RA
, RS
, RB
}},
4521 {"dlmzb.", XRC(31,78,1), X_MASK
, PPC403
|PPC440
|TITAN
|PPCVLE
, PPCNONE
, {RA
, RS
, RB
}},
4523 {"mtsrd", X(31,82), XRB_MASK
|(1<<20), PPC64
, PPCNONE
, {SR
, RS
}},
4525 {"mfmsr", X(31,83), XRARB_MASK
, COM
|PPCVLE
, PPCNONE
, {RT
}},
4527 {"ldarx", X(31,84), XEH_MASK
, PPC64
|PPCVLE
, PPCNONE
, {RT
, RA0
, RB
, EH
}},
4529 {"dcbfl", XOPL(31,86,1), XRT_MASK
, POWER5
, PPC476
, {RA0
, RB
}},
4530 {"dcbf", X(31,86), XLRT_MASK
, PPC
|PPCVLE
, PPCNONE
, {RA0
, RB
, L
}},
4532 {"lbzx", X(31,87), X_MASK
, COM
|PPCVLE
, PPCNONE
, {RT
, RA0
, RB
}},
4534 {"lbepx", X(31,95), X_MASK
, E500MC
|PPCA2
|PPCVLE
, PPCNONE
, {RT
, RA0
, RB
}},
4536 {"dni", XRC(31,97,1), XRB_MASK
, E6500
, PPCNONE
, {DUI
, DCTL
}},
4538 {"lvx", X(31,103), X_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, RA0
, RB
}},
4539 {"lqfcmx", APU(31,103,0), APU_MASK
, PPC405
, PPCNONE
, {FCRT
, RA
, RB
}},
4541 {"neg", XO(31,104,0,0), XORB_MASK
, COM
|PPCVLE
, PPCNONE
, {RT
, RA
}},
4542 {"neg.", XO(31,104,0,1), XORB_MASK
, COM
|PPCVLE
, PPCNONE
, {RT
, RA
}},
4544 {"mul", XO(31,107,0,0), XO_MASK
, M601
, PPCNONE
, {RT
, RA
, RB
}},
4545 {"mul.", XO(31,107,0,1), XO_MASK
, M601
, PPCNONE
, {RT
, RA
, RB
}},
4547 {"mvidsplt", X(31,110), X_MASK
, PPCVEC2
, PPCNONE
, {VD
, RA
, RB
}},
4549 {"mtsrdin", X(31,114), XRA_MASK
, PPC64
, PPCNONE
, {RS
, RB
}},
4551 {"mffprwz", X(31,115), XX1RB_MASK
|1, PPCVSX2
, PPCNONE
, {RA
, FRS
}},
4552 {"mfvrwz", X(31,115)|1, XX1RB_MASK
|1, PPCVSX2
, PPCNONE
, {RA
, VS
}},
4553 {"mfvsrwz", X(31,115), XX1RB_MASK
, PPCVSX2
, PPCNONE
, {RA
, XS6
}},
4555 {"lharx", X(31,116), XEH_MASK
, POWER8
|PPCVLE
, PPCNONE
, {RT
, RA0
, RB
, EH
}},
4557 {"clf", X(31,118), XTO_MASK
, POWER
, PPCNONE
, {RA
, RB
}},
4559 {"lbzux", X(31,119), X_MASK
, COM
|PPCVLE
, PPCNONE
, {RT
, RAL
, RB
}},
4561 {"popcntb", X(31,122), XRB_MASK
, POWER5
|PPCVLE
, PPCNONE
, {RA
, RS
}},
4563 {"not", XRC(31,124,0), X_MASK
, COM
, PPCNONE
, {RA
, RS
, RBS
}},
4564 {"nor", XRC(31,124,0), X_MASK
, COM
|PPCVLE
, PPCNONE
, {RA
, RS
, RB
}},
4565 {"not.", XRC(31,124,1), X_MASK
, COM
, PPCNONE
, {RA
, RS
, RBS
}},
4566 {"nor.", XRC(31,124,1), X_MASK
, COM
|PPCVLE
, PPCNONE
, {RA
, RS
, RB
}},
4568 {"dcbfep", XRT(31,127,0), XRT_MASK
, E500MC
|PPCA2
|PPCVLE
, PPCNONE
, {RA0
, RB
}},
4570 {"wrtee", X(31,131), XRARB_MASK
, PPC403
|BOOKE
|PPCA2
|PPC476
|PPCVLE
, PPCNONE
, {RS
}},
4572 {"dcbtstls", X(31,134), X_MASK
, PPCCHLK
|PPC476
|TITAN
|PPCVLE
, PPCNONE
, {CT
, RA0
, RB
}},
4574 {"stvebx", X(31,135), X_MASK
, PPCVEC
, PPCNONE
, {VS
, RA0
, RB
}},
4575 {"stbfcmx", APU(31,135,0), APU_MASK
, PPC405
, PPCNONE
, {FCRT
, RA
, RB
}},
4577 {"subfe", XO(31,136,0,0), XO_MASK
, PPCCOM
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
4578 {"sfe", XO(31,136,0,0), XO_MASK
, PWRCOM
, PPCNONE
, {RT
, RA
, RB
}},
4579 {"subfe.", XO(31,136,0,1), XO_MASK
, PPCCOM
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
4580 {"sfe.", XO(31,136,0,1), XO_MASK
, PWRCOM
, PPCNONE
, {RT
, RA
, RB
}},
4582 {"adde", XO(31,138,0,0), XO_MASK
, PPCCOM
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
4583 {"ae", XO(31,138,0,0), XO_MASK
, PWRCOM
, PPCNONE
, {RT
, RA
, RB
}},
4584 {"adde.", XO(31,138,0,1), XO_MASK
, PPCCOM
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
4585 {"ae.", XO(31,138,0,1), XO_MASK
, PWRCOM
, PPCNONE
, {RT
, RA
, RB
}},
4587 {"stxsiwx", X(31,140), XX1_MASK
, PPCVSX2
, PPCNONE
, {XS6
, RA0
, RB
}},
4589 {"msgsndp", XRTRA(31,142,0,0), XRTRA_MASK
, POWER8
, PPCNONE
, {RB
}},
4590 {"dcbtstlse", X(31,142), X_MASK
, PPCCHLK
, E500MC
, {CT
, RA0
, RB
}},
4592 {"mtcr", XFXM(31,144,0xff,0), XRARB_MASK
, COM
, PPCNONE
, {RS
}},
4593 {"mtcrf", XFXM(31,144,0,0), XFXFXM_MASK
, COM
|PPCVLE
, PPCNONE
, {FXM
, RS
}},
4594 {"mtocrf", XFXM(31,144,0,1), XFXFXM_MASK
, COM
|PPCVLE
, PPCNONE
, {FXM
, RS
}},
4596 {"mtmsr", X(31,146), XRLARB_MASK
, COM
|PPCVLE
, PPCNONE
, {RS
, A_L
}},
4598 {"mtsle", X(31,147), XRTLRARB_MASK
, POWER8
, PPCNONE
, {L
}},
4600 {"eratsx", XRC(31,147,0), X_MASK
, PPCA2
, PPCNONE
, {RT
, RA0
, RB
}},
4601 {"eratsx.", XRC(31,147,1), X_MASK
, PPCA2
, PPCNONE
, {RT
, RA0
, RB
}},
4603 {"stdx", X(31,149), X_MASK
, PPC64
|PPCVLE
, PPCNONE
, {RS
, RA0
, RB
}},
4605 {"stwcx.", XRC(31,150,1), X_MASK
, PPC
|PPCVLE
, PPCNONE
, {RS
, RA0
, RB
}},
4607 {"stwx", X(31,151), X_MASK
, PPCCOM
|PPCVLE
, PPCNONE
, {RS
, RA0
, RB
}},
4608 {"stx", X(31,151), X_MASK
, PWRCOM
, PPCNONE
, {RS
, RA
, RB
}},
4610 {"slq", XRC(31,152,0), X_MASK
, M601
, PPCNONE
, {RA
, RS
, RB
}},
4611 {"slq.", XRC(31,152,1), X_MASK
, M601
, PPCNONE
, {RA
, RS
, RB
}},
4613 {"sle", XRC(31,153,0), X_MASK
, M601
, PPCNONE
, {RA
, RS
, RB
}},
4614 {"sle.", XRC(31,153,1), X_MASK
, M601
, PPCNONE
, {RA
, RS
, RB
}},
4616 {"prtyw", X(31,154), XRB_MASK
, POWER6
|PPCA2
|PPC476
, PPCNONE
, {RA
, RS
}},
4618 {"stdepx", X(31,157), X_MASK
, E500MC
|PPCA2
|PPCVLE
, PPCNONE
, {RS
, RA0
, RB
}},
4620 {"stwepx", X(31,159), X_MASK
, E500MC
|PPCA2
|PPCVLE
, PPCNONE
, {RS
, RA0
, RB
}},
4622 {"wrteei", X(31,163), XE_MASK
, PPC403
|BOOKE
|PPCA2
|PPC476
|PPCVLE
, PPCNONE
, {E
}},
4624 {"dcbtls", X(31,166), X_MASK
, PPCCHLK
|PPC476
|TITAN
|PPCVLE
, PPCNONE
, {CT
, RA0
, RB
}},
4626 {"stvehx", X(31,167), X_MASK
, PPCVEC
, PPCNONE
, {VS
, RA0
, RB
}},
4627 {"sthfcmx", APU(31,167,0), APU_MASK
, PPC405
, PPCNONE
, {FCRT
, RA
, RB
}},
4629 {"msgclrp", XRTRA(31,174,0,0), XRTRA_MASK
, POWER8
, PPCNONE
, {RB
}},
4630 {"dcbtlse", X(31,174), X_MASK
, PPCCHLK
, E500MC
, {CT
, RA0
, RB
}},
4632 {"mtmsrd", X(31,178), XRLARB_MASK
, PPC64
, PPCNONE
, {RS
, A_L
}},
4634 {"mtvsrd", X(31,179), XX1RB_MASK
, PPCVSX2
, PPCNONE
, {XT6
, RA
}},
4635 {"mtfprd", X(31,179), XX1RB_MASK
|1, PPCVSX2
, PPCNONE
, {FRT
, RA
}},
4636 {"mtvrd", X(31,179)|1, XX1RB_MASK
|1, PPCVSX2
, PPCNONE
, {VD
, RA
}},
4637 {"eratre", X(31,179), X_MASK
, PPCA2
, PPCNONE
, {RT
, RA
, WS
}},
4639 {"stdux", X(31,181), X_MASK
, PPC64
|PPCVLE
, PPCNONE
, {RS
, RAS
, RB
}},
4641 {"stqcx.", XRC(31,182,1), X_MASK
, POWER8
, PPCNONE
, {RSQ
, RA0
, RB
}},
4642 {"wchkall", X(31,182), X_MASK
, PPCA2
, PPCNONE
, {OBF
}},
4644 {"stwux", X(31,183), X_MASK
, PPCCOM
|PPCVLE
, PPCNONE
, {RS
, RAS
, RB
}},
4645 {"stux", X(31,183), X_MASK
, PWRCOM
, PPCNONE
, {RS
, RA0
, RB
}},
4647 {"sliq", XRC(31,184,0), X_MASK
, M601
, PPCNONE
, {RA
, RS
, SH
}},
4648 {"sliq.", XRC(31,184,1), X_MASK
, M601
, PPCNONE
, {RA
, RS
, SH
}},
4650 {"prtyd", X(31,186), XRB_MASK
, POWER6
|PPCA2
, PPCNONE
, {RA
, RS
}},
4652 {"icblq.", XRC(31,198,1), X_MASK
, E6500
, PPCNONE
, {CT
, RA0
, RB
}},
4654 {"stvewx", X(31,199), X_MASK
, PPCVEC
, PPCNONE
, {VS
, RA0
, RB
}},
4655 {"stwfcmx", APU(31,199,0), APU_MASK
, PPC405
, PPCNONE
, {FCRT
, RA
, RB
}},
4657 {"subfze", XO(31,200,0,0), XORB_MASK
, PPCCOM
|PPCVLE
, PPCNONE
, {RT
, RA
}},
4658 {"sfze", XO(31,200,0,0), XORB_MASK
, PWRCOM
, PPCNONE
, {RT
, RA
}},
4659 {"subfze.", XO(31,200,0,1), XORB_MASK
, PPCCOM
|PPCVLE
, PPCNONE
, {RT
, RA
}},
4660 {"sfze.", XO(31,200,0,1), XORB_MASK
, PWRCOM
, PPCNONE
, {RT
, RA
}},
4662 {"addze", XO(31,202,0,0), XORB_MASK
, PPCCOM
|PPCVLE
, PPCNONE
, {RT
, RA
}},
4663 {"aze", XO(31,202,0,0), XORB_MASK
, PWRCOM
, PPCNONE
, {RT
, RA
}},
4664 {"addze.", XO(31,202,0,1), XORB_MASK
, PPCCOM
|PPCVLE
, PPCNONE
, {RT
, RA
}},
4665 {"aze.", XO(31,202,0,1), XORB_MASK
, PWRCOM
, PPCNONE
, {RT
, RA
}},
4667 {"msgsnd", XRTRA(31,206,0,0), XRTRA_MASK
, E500MC
|PPCA2
|POWER8
|PPCVLE
, PPCNONE
, {RB
}},
4669 {"mtsr", X(31,210), XRB_MASK
|(1<<20), COM
, NON32
, {SR
, RS
}},
4671 {"mtfprwa", X(31,211), XX1RB_MASK
|1, PPCVSX2
, PPCNONE
, {FRT
, RA
}},
4672 {"mtvrwa", X(31,211)|1, XX1RB_MASK
|1, PPCVSX2
, PPCNONE
, {VD
, RA
}},
4673 {"mtvsrwa", X(31,211), XX1RB_MASK
, PPCVSX2
, PPCNONE
, {XT6
, RA
}},
4674 {"eratwe", X(31,211), X_MASK
, PPCA2
, PPCNONE
, {RS
, RA
, WS
}},
4676 {"ldawx.", XRC(31,212,1), X_MASK
, PPCA2
, PPCNONE
, {RT
, RA0
, RB
}},
4678 {"stdcx.", XRC(31,214,1), X_MASK
, PPC64
|PPCVLE
, PPCNONE
, {RS
, RA0
, RB
}},
4680 {"stbx", X(31,215), X_MASK
, COM
|PPCVLE
, PPCNONE
, {RS
, RA0
, RB
}},
4682 {"sllq", XRC(31,216,0), X_MASK
, M601
, PPCNONE
, {RA
, RS
, RB
}},
4683 {"sllq.", XRC(31,216,1), X_MASK
, M601
, PPCNONE
, {RA
, RS
, RB
}},
4685 {"sleq", XRC(31,217,0), X_MASK
, M601
, PPCNONE
, {RA
, RS
, RB
}},
4686 {"sleq.", XRC(31,217,1), X_MASK
, M601
, PPCNONE
, {RA
, RS
, RB
}},
4688 {"stbepx", X(31,223), X_MASK
, E500MC
|PPCA2
|PPCVLE
, PPCNONE
, {RS
, RA0
, RB
}},
4690 {"icblc", X(31,230), X_MASK
, PPCCHLK
|PPC476
|TITAN
|PPCVLE
, PPCNONE
, {CT
, RA0
, RB
}},
4692 {"stvx", X(31,231), X_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VS
, RA0
, RB
}},
4693 {"stqfcmx", APU(31,231,0), APU_MASK
, PPC405
, PPCNONE
, {FCRT
, RA
, RB
}},
4695 {"subfme", XO(31,232,0,0), XORB_MASK
, PPCCOM
|PPCVLE
, PPCNONE
, {RT
, RA
}},
4696 {"sfme", XO(31,232,0,0), XORB_MASK
, PWRCOM
, PPCNONE
, {RT
, RA
}},
4697 {"subfme.", XO(31,232,0,1), XORB_MASK
, PPCCOM
|PPCVLE
, PPCNONE
, {RT
, RA
}},
4698 {"sfme.", XO(31,232,0,1), XORB_MASK
, PWRCOM
, PPCNONE
, {RT
, RA
}},
4700 {"mulld", XO(31,233,0,0), XO_MASK
, PPC64
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
4701 {"mulld.", XO(31,233,0,1), XO_MASK
, PPC64
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
4703 {"addme", XO(31,234,0,0), XORB_MASK
, PPCCOM
|PPCVLE
, PPCNONE
, {RT
, RA
}},
4704 {"ame", XO(31,234,0,0), XORB_MASK
, PWRCOM
, PPCNONE
, {RT
, RA
}},
4705 {"addme.", XO(31,234,0,1), XORB_MASK
, PPCCOM
|PPCVLE
, PPCNONE
, {RT
, RA
}},
4706 {"ame.", XO(31,234,0,1), XORB_MASK
, PWRCOM
, PPCNONE
, {RT
, RA
}},
4708 {"mullw", XO(31,235,0,0), XO_MASK
, PPCCOM
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
4709 {"muls", XO(31,235,0,0), XO_MASK
, PWRCOM
, PPCNONE
, {RT
, RA
, RB
}},
4710 {"mullw.", XO(31,235,0,1), XO_MASK
, PPCCOM
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
4711 {"muls.", XO(31,235,0,1), XO_MASK
, PWRCOM
, PPCNONE
, {RT
, RA
, RB
}},
4713 {"icblce", X(31,238), X_MASK
, PPCCHLK
, E500MC
|PPCA2
, {CT
, RA
, RB
}},
4714 {"msgclr", XRTRA(31,238,0,0), XRTRA_MASK
, E500MC
|PPCA2
|POWER8
|PPCVLE
, PPCNONE
, {RB
}},
4715 {"mtsrin", X(31,242), XRA_MASK
, PPC
, NON32
, {RS
, RB
}},
4716 {"mtsri", X(31,242), XRA_MASK
, POWER
, NON32
, {RS
, RB
}},
4718 {"mtfprwz", X(31,243), XX1RB_MASK
|1, PPCVSX2
, PPCNONE
, {FRT
, RA
}},
4719 {"mtvrwz", X(31,243)|1, XX1RB_MASK
|1, PPCVSX2
, PPCNONE
, {VD
, RA
}},
4720 {"mtvsrwz", X(31,243), XX1RB_MASK
, PPCVSX2
, PPCNONE
, {XT6
, RA
}},
4722 {"dcbtstt", XRT(31,246,0x10), XRT_MASK
, POWER7
, PPCNONE
, {RA0
, RB
}},
4723 {"dcbtst", X(31,246), X_MASK
, POWER4
, DCBT_EO
, {RA0
, RB
, CT
}},
4724 {"dcbtst", X(31,246), X_MASK
, DCBT_EO
, PPCNONE
, {CT
, RA0
, RB
}},
4725 {"dcbtst", X(31,246), X_MASK
, PPC
, POWER4
|DCBT_EO
, {RA0
, RB
}},
4727 {"stbux", X(31,247), X_MASK
, COM
|PPCVLE
, PPCNONE
, {RS
, RAS
, RB
}},
4729 {"slliq", XRC(31,248,0), X_MASK
, M601
, PPCNONE
, {RA
, RS
, SH
}},
4730 {"slliq.", XRC(31,248,1), X_MASK
, M601
, PPCNONE
, {RA
, RS
, SH
}},
4732 {"bpermd", X(31,252), X_MASK
, POWER7
|PPCA2
, PPCNONE
, {RA
, RS
, RB
}},
4734 {"dcbtstep", XRT(31,255,0), X_MASK
, E500MC
|PPCA2
|PPCVLE
, PPCNONE
, {RT
, RA0
, RB
}},
4736 {"mfdcrx", X(31,259), X_MASK
, BOOKE
|PPCA2
|PPC476
|PPCVLE
, TITAN
, {RS
, RA
}},
4737 {"mfdcrx.", XRC(31,259,1), X_MASK
, PPCA2
, PPCNONE
, {RS
, RA
}},
4739 {"lvexbx", X(31,261), X_MASK
, PPCVEC2
, PPCNONE
, {VD
, RA0
, RB
}},
4741 {"icbt", X(31,262), XRT_MASK
, PPC403
, PPCNONE
, {RA
, RB
}},
4743 {"lvepxl", X(31,263), X_MASK
, PPCVEC2
|PPCVLE
, PPCNONE
, {VD
, RA0
, RB
}},
4745 {"ldfcmx", APU(31,263,0), APU_MASK
, PPC405
, PPCNONE
, {FCRT
, RA
, RB
}},
4746 {"doz", XO(31,264,0,0), XO_MASK
, M601
, PPCNONE
, {RT
, RA
, RB
}},
4747 {"doz.", XO(31,264,0,1), XO_MASK
, M601
, PPCNONE
, {RT
, RA
, RB
}},
4749 {"add", XO(31,266,0,0), XO_MASK
, PPCCOM
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
4750 {"cax", XO(31,266,0,0), XO_MASK
, PWRCOM
, PPCNONE
, {RT
, RA
, RB
}},
4751 {"add.", XO(31,266,0,1), XO_MASK
, PPCCOM
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
4752 {"cax.", XO(31,266,0,1), XO_MASK
, PWRCOM
, PPCNONE
, {RT
, RA
, RB
}},
4754 {"ehpriv", X(31,270), 0xffffffff, E500MC
|PPCA2
|PPCVLE
, PPCNONE
, {0}},
4756 {"tlbiel", X(31,274), XRTLRA_MASK
, POWER4
, PPC476
, {RB
, L
}},
4758 {"mfapidi", X(31,275), X_MASK
, BOOKE
, TITAN
, {RT
, RA
}},
4760 {"lqarx", X(31,276), XEH_MASK
, POWER8
, PPCNONE
, {RTQ
, RAX
, RBX
, EH
}},
4762 {"lscbx", XRC(31,277,0), X_MASK
, M601
, PPCNONE
, {RT
, RA
, RB
}},
4763 {"lscbx.", XRC(31,277,1), X_MASK
, M601
, PPCNONE
, {RT
, RA
, RB
}},
4765 {"dcbtt", XRT(31,278,0x10), XRT_MASK
, POWER7
, PPCNONE
, {RA0
, RB
}},
4766 {"dcbt", X(31,278), X_MASK
, POWER4
, DCBT_EO
, {RA0
, RB
, CT
}},
4767 {"dcbt", X(31,278), X_MASK
, DCBT_EO
, PPCNONE
, {CT
, RA0
, RB
}},
4768 {"dcbt", X(31,278), X_MASK
, PPC
, POWER4
|DCBT_EO
, {RA0
, RB
}},
4770 {"lhzx", X(31,279), X_MASK
, COM
|PPCVLE
, PPCNONE
, {RT
, RA0
, RB
}},
4772 {"cdtbcd", X(31,282), XRB_MASK
, POWER6
, PPCNONE
, {RA
, RS
}},
4774 {"eqv", XRC(31,284,0), X_MASK
, COM
|PPCVLE
, PPCNONE
, {RA
, RS
, RB
}},
4775 {"eqv.", XRC(31,284,1), X_MASK
, COM
|PPCVLE
, PPCNONE
, {RA
, RS
, RB
}},
4777 {"lhepx", X(31,287), X_MASK
, E500MC
|PPCA2
|PPCVLE
, PPCNONE
, {RT
, RA0
, RB
}},
4779 {"mfdcrux", X(31,291), X_MASK
, PPC464
|PPCVLE
, PPCNONE
, {RS
, RA
}},
4781 {"lvexhx", X(31,293), X_MASK
, PPCVEC2
, PPCNONE
, {VD
, RA0
, RB
}},
4782 {"lvepx", X(31,295), X_MASK
, PPCVEC2
|PPCVLE
, PPCNONE
, {VD
, RA0
, RB
}},
4784 {"mfbhrbe", X(31,302), X_MASK
, POWER8
, PPCNONE
, {RT
, BHRBE
}},
4786 {"tlbie", X(31,306), XRA_MASK
, POWER7
, TITAN
, {RB
, RS
}},
4787 {"tlbie", X(31,306), XRTLRA_MASK
, PPC
, POWER7
|TITAN
, {RB
, L
}},
4788 {"tlbi", X(31,306), XRT_MASK
, POWER
, PPCNONE
, {RA0
, RB
}},
4790 {"eciwx", X(31,310), X_MASK
, PPC
, TITAN
, {RT
, RA0
, RB
}},
4792 {"lhzux", X(31,311), X_MASK
, COM
|PPCVLE
, PPCNONE
, {RT
, RAL
, RB
}},
4794 {"cbcdtd", X(31,314), XRB_MASK
, POWER6
, PPCNONE
, {RA
, RS
}},
4796 {"xor", XRC(31,316,0), X_MASK
, COM
|PPCVLE
, PPCNONE
, {RA
, RS
, RB
}},
4797 {"xor.", XRC(31,316,1), X_MASK
, COM
|PPCVLE
, PPCNONE
, {RA
, RS
, RB
}},
4799 {"dcbtep", XRT(31,319,0), X_MASK
, E500MC
|PPCA2
|PPCVLE
, PPCNONE
, {RT
, RA0
, RB
}},
4801 {"mfexisr", XSPR(31,323, 64), XSPR_MASK
, PPC403
, PPCNONE
, {RT
}},
4802 {"mfexier", XSPR(31,323, 66), XSPR_MASK
, PPC403
, PPCNONE
, {RT
}},
4803 {"mfbr0", XSPR(31,323,128), XSPR_MASK
, PPC403
, PPCNONE
, {RT
}},
4804 {"mfbr1", XSPR(31,323,129), XSPR_MASK
, PPC403
, PPCNONE
, {RT
}},
4805 {"mfbr2", XSPR(31,323,130), XSPR_MASK
, PPC403
, PPCNONE
, {RT
}},
4806 {"mfbr3", XSPR(31,323,131), XSPR_MASK
, PPC403
, PPCNONE
, {RT
}},
4807 {"mfbr4", XSPR(31,323,132), XSPR_MASK
, PPC403
, PPCNONE
, {RT
}},
4808 {"mfbr5", XSPR(31,323,133), XSPR_MASK
, PPC403
, PPCNONE
, {RT
}},
4809 {"mfbr6", XSPR(31,323,134), XSPR_MASK
, PPC403
, PPCNONE
, {RT
}},
4810 {"mfbr7", XSPR(31,323,135), XSPR_MASK
, PPC403
, PPCNONE
, {RT
}},
4811 {"mfbear", XSPR(31,323,144), XSPR_MASK
, PPC403
, PPCNONE
, {RT
}},
4812 {"mfbesr", XSPR(31,323,145), XSPR_MASK
, PPC403
, PPCNONE
, {RT
}},
4813 {"mfiocr", XSPR(31,323,160), XSPR_MASK
, PPC403
, PPCNONE
, {RT
}},
4814 {"mfdmacr0", XSPR(31,323,192), XSPR_MASK
, PPC403
, PPCNONE
, {RT
}},
4815 {"mfdmact0", XSPR(31,323,193), XSPR_MASK
, PPC403
, PPCNONE
, {RT
}},
4816 {"mfdmada0", XSPR(31,323,194), XSPR_MASK
, PPC403
, PPCNONE
, {RT
}},
4817 {"mfdmasa0", XSPR(31,323,195), XSPR_MASK
, PPC403
, PPCNONE
, {RT
}},
4818 {"mfdmacc0", XSPR(31,323,196), XSPR_MASK
, PPC403
, PPCNONE
, {RT
}},
4819 {"mfdmacr1", XSPR(31,323,200), XSPR_MASK
, PPC403
, PPCNONE
, {RT
}},
4820 {"mfdmact1", XSPR(31,323,201), XSPR_MASK
, PPC403
, PPCNONE
, {RT
}},
4821 {"mfdmada1", XSPR(31,323,202), XSPR_MASK
, PPC403
, PPCNONE
, {RT
}},
4822 {"mfdmasa1", XSPR(31,323,203), XSPR_MASK
, PPC403
, PPCNONE
, {RT
}},
4823 {"mfdmacc1", XSPR(31,323,204), XSPR_MASK
, PPC403
, PPCNONE
, {RT
}},
4824 {"mfdmacr2", XSPR(31,323,208), XSPR_MASK
, PPC403
, PPCNONE
, {RT
}},
4825 {"mfdmact2", XSPR(31,323,209), XSPR_MASK
, PPC403
, PPCNONE
, {RT
}},
4826 {"mfdmada2", XSPR(31,323,210), XSPR_MASK
, PPC403
, PPCNONE
, {RT
}},
4827 {"mfdmasa2", XSPR(31,323,211), XSPR_MASK
, PPC403
, PPCNONE
, {RT
}},
4828 {"mfdmacc2", XSPR(31,323,212), XSPR_MASK
, PPC403
, PPCNONE
, {RT
}},
4829 {"mfdmacr3", XSPR(31,323,216), XSPR_MASK
, PPC403
, PPCNONE
, {RT
}},
4830 {"mfdmact3", XSPR(31,323,217), XSPR_MASK
, PPC403
, PPCNONE
, {RT
}},
4831 {"mfdmada3", XSPR(31,323,218), XSPR_MASK
, PPC403
, PPCNONE
, {RT
}},
4832 {"mfdmasa3", XSPR(31,323,219), XSPR_MASK
, PPC403
, PPCNONE
, {RT
}},
4833 {"mfdmacc3", XSPR(31,323,220), XSPR_MASK
, PPC403
, PPCNONE
, {RT
}},
4834 {"mfdmasr", XSPR(31,323,224), XSPR_MASK
, PPC403
, PPCNONE
, {RT
}},
4835 {"mfdcr", X(31,323), X_MASK
, PPC403
|BOOKE
|PPCA2
|PPC476
|PPCVLE
, TITAN
, {RT
, SPR
}},
4836 {"mfdcr.", XRC(31,323,1), X_MASK
, PPCA2
, PPCNONE
, {RT
, SPR
}},
4838 {"lvexwx", X(31,325), X_MASK
, PPCVEC2
, PPCNONE
, {VD
, RA0
, RB
}},
4840 {"dcread", X(31,326), X_MASK
, PPC476
|TITAN
, PPCNONE
, {RT
, RA0
, RB
}},
4842 {"div", XO(31,331,0,0), XO_MASK
, M601
, PPCNONE
, {RT
, RA
, RB
}},
4843 {"div.", XO(31,331,0,1), XO_MASK
, M601
, PPCNONE
, {RT
, RA
, RB
}},
4845 {"lxvdsx", X(31,332), XX1_MASK
, PPCVSX
, PPCNONE
, {XT6
, RA0
, RB
}},
4847 {"mfpmr", X(31,334), X_MASK
, PPCPMR
|PPCE300
|PPCVLE
, PPCNONE
, {RT
, PMR
}},
4848 {"mftmr", X(31,366), X_MASK
, PPCTMR
|E6500
, PPCNONE
, {RT
, TMR
}},
4850 {"mfmq", XSPR(31,339, 0), XSPR_MASK
, M601
, PPCNONE
, {RT
}},
4851 {"mfxer", XSPR(31,339, 1), XSPR_MASK
, COM
|PPCVLE
, PPCNONE
, {RT
}},
4852 {"mfrtcu", XSPR(31,339, 4), XSPR_MASK
, COM
, TITAN
, {RT
}},
4853 {"mfrtcl", XSPR(31,339, 5), XSPR_MASK
, COM
, TITAN
, {RT
}},
4854 {"mfdec", XSPR(31,339, 6), XSPR_MASK
, MFDEC1
, PPCNONE
, {RT
}},
4855 {"mflr", XSPR(31,339, 8), XSPR_MASK
, COM
|PPCVLE
, PPCNONE
, {RT
}},
4856 {"mfctr", XSPR(31,339, 9), XSPR_MASK
, COM
|PPCVLE
, PPCNONE
, {RT
}},
4857 {"mftid", XSPR(31,339, 17), XSPR_MASK
, POWER
, PPCNONE
, {RT
}},
4858 {"mfdsisr", XSPR(31,339, 18), XSPR_MASK
, COM
, TITAN
, {RT
}},
4859 {"mfdar", XSPR(31,339, 19), XSPR_MASK
, COM
, TITAN
, {RT
}},
4860 {"mfdec", XSPR(31,339, 22), XSPR_MASK
, MFDEC2
, MFDEC1
, {RT
}},
4861 {"mfsdr0", XSPR(31,339, 24), XSPR_MASK
, POWER
, PPCNONE
, {RT
}},
4862 {"mfsdr1", XSPR(31,339, 25), XSPR_MASK
, COM
, TITAN
, {RT
}},
4863 {"mfsrr0", XSPR(31,339, 26), XSPR_MASK
, COM
, PPCNONE
, {RT
}},
4864 {"mfsrr1", XSPR(31,339, 27), XSPR_MASK
, COM
, PPCNONE
, {RT
}},
4865 {"mfcfar", XSPR(31,339, 28), XSPR_MASK
, POWER6
, PPCNONE
, {RT
}},
4866 {"mfpid", XSPR(31,339, 48), XSPR_MASK
, BOOKE
|PPCVLE
, PPCNONE
, {RT
}},
4867 {"mfcsrr0", XSPR(31,339, 58), XSPR_MASK
, BOOKE
|PPCVLE
, PPCNONE
, {RT
}},
4868 {"mfcsrr1", XSPR(31,339, 59), XSPR_MASK
, BOOKE
|PPCVLE
, PPCNONE
, {RT
}},
4869 {"mfdear", XSPR(31,339, 61), XSPR_MASK
, BOOKE
|PPCVLE
, PPCNONE
, {RT
}},
4870 {"mfesr", XSPR(31,339, 62), XSPR_MASK
, BOOKE
|PPCVLE
, PPCNONE
, {RT
}},
4871 {"mfivpr", XSPR(31,339, 63), XSPR_MASK
, BOOKE
|PPCVLE
, PPCNONE
, {RT
}},
4872 {"mfcmpa", XSPR(31,339,144), XSPR_MASK
, PPC860
, PPCNONE
, {RT
}},
4873 {"mfcmpb", XSPR(31,339,145), XSPR_MASK
, PPC860
, PPCNONE
, {RT
}},
4874 {"mfcmpc", XSPR(31,339,146), XSPR_MASK
, PPC860
, PPCNONE
, {RT
}},
4875 {"mfcmpd", XSPR(31,339,147), XSPR_MASK
, PPC860
, PPCNONE
, {RT
}},
4876 {"mficr", XSPR(31,339,148), XSPR_MASK
, PPC860
, PPCNONE
, {RT
}},
4877 {"mfder", XSPR(31,339,149), XSPR_MASK
, PPC860
, PPCNONE
, {RT
}},
4878 {"mfcounta", XSPR(31,339,150), XSPR_MASK
, PPC860
, PPCNONE
, {RT
}},
4879 {"mfcountb", XSPR(31,339,151), XSPR_MASK
, PPC860
, PPCNONE
, {RT
}},
4880 {"mfcmpe", XSPR(31,339,152), XSPR_MASK
, PPC860
, PPCNONE
, {RT
}},
4881 {"mfcmpf", XSPR(31,339,153), XSPR_MASK
, PPC860
, PPCNONE
, {RT
}},
4882 {"mfcmpg", XSPR(31,339,154), XSPR_MASK
, PPC860
, PPCNONE
, {RT
}},
4883 {"mfcmph", XSPR(31,339,155), XSPR_MASK
, PPC860
, PPCNONE
, {RT
}},
4884 {"mflctrl1", XSPR(31,339,156), XSPR_MASK
, PPC860
, PPCNONE
, {RT
}},
4885 {"mflctrl2", XSPR(31,339,157), XSPR_MASK
, PPC860
, PPCNONE
, {RT
}},
4886 {"mfictrl", XSPR(31,339,158), XSPR_MASK
, PPC860
, PPCNONE
, {RT
}},
4887 {"mfbar", XSPR(31,339,159), XSPR_MASK
, PPC860
, PPCNONE
, {RT
}},
4888 {"mfvrsave", XSPR(31,339,256), XSPR_MASK
, PPCVEC
, PPCNONE
, {RT
}},
4889 {"mfusprg0", XSPR(31,339,256), XSPR_MASK
, BOOKE
|PPCVLE
, PPCNONE
, {RT
}},
4890 {"mfsprg", XSPR(31,339,256), XSPRG_MASK
, PPC
|PPCVLE
, PPCNONE
, {RT
, SPRG
}},
4891 {"mfsprg4", XSPR(31,339,260), XSPR_MASK
, PPC405
|BOOKE
|PPCVLE
, PPCNONE
, {RT
}},
4892 {"mfsprg5", XSPR(31,339,261), XSPR_MASK
, PPC405
|BOOKE
|PPCVLE
, PPCNONE
, {RT
}},
4893 {"mfsprg6", XSPR(31,339,262), XSPR_MASK
, PPC405
|BOOKE
|PPCVLE
, PPCNONE
, {RT
}},
4894 {"mfsprg7", XSPR(31,339,263), XSPR_MASK
, PPC405
|BOOKE
|PPCVLE
, PPCNONE
, {RT
}},
4895 {"mftbu", XSPR(31,339,269), XSPR_MASK
, POWER4
|BOOKE
|PPCVLE
, PPCNONE
, {RT
}},
4896 {"mftb", X(31,339), X_MASK
, POWER4
|BOOKE
|PPCVLE
, PPCNONE
, {RT
, TBR
}},
4897 {"mftbl", XSPR(31,339,268), XSPR_MASK
, POWER4
|BOOKE
|PPCVLE
, PPCNONE
, {RT
}},
4898 {"mfsprg0", XSPR(31,339,272), XSPR_MASK
, PPC
|PPCVLE
, PPCNONE
, {RT
}},
4899 {"mfsprg1", XSPR(31,339,273), XSPR_MASK
, PPC
|PPCVLE
, PPCNONE
, {RT
}},
4900 {"mfsprg2", XSPR(31,339,274), XSPR_MASK
, PPC
|PPCVLE
, PPCNONE
, {RT
}},
4901 {"mfsprg3", XSPR(31,339,275), XSPR_MASK
, PPC
|PPCVLE
, PPCNONE
, {RT
}},
4902 {"mfasr", XSPR(31,339,280), XSPR_MASK
, PPC64
, PPCNONE
, {RT
}},
4903 {"mfear", XSPR(31,339,282), XSPR_MASK
, PPC
, TITAN
, {RT
}},
4904 {"mfpir", XSPR(31,339,286), XSPR_MASK
, BOOKE
|PPCVLE
, PPCNONE
, {RT
}},
4905 {"mfpvr", XSPR(31,339,287), XSPR_MASK
, PPC
|PPCVLE
, PPCNONE
, {RT
}},
4906 {"mfdbsr", XSPR(31,339,304), XSPR_MASK
, BOOKE
|PPCVLE
, PPCNONE
, {RT
}},
4907 {"mfdbcr0", XSPR(31,339,308), XSPR_MASK
, BOOKE
|PPCVLE
, PPCNONE
, {RT
}},
4908 {"mfdbcr1", XSPR(31,339,309), XSPR_MASK
, BOOKE
|PPCVLE
, PPCNONE
, {RT
}},
4909 {"mfdbcr2", XSPR(31,339,310), XSPR_MASK
, BOOKE
|PPCVLE
, PPCNONE
, {RT
}},
4910 {"mfiac1", XSPR(31,339,312), XSPR_MASK
, BOOKE
|PPCVLE
, PPCNONE
, {RT
}},
4911 {"mfiac2", XSPR(31,339,313), XSPR_MASK
, BOOKE
|PPCVLE
, PPCNONE
, {RT
}},
4912 {"mfiac3", XSPR(31,339,314), XSPR_MASK
, BOOKE
|PPCVLE
, PPCNONE
, {RT
}},
4913 {"mfiac4", XSPR(31,339,315), XSPR_MASK
, BOOKE
|PPCVLE
, PPCNONE
, {RT
}},
4914 {"mfdac1", XSPR(31,339,316), XSPR_MASK
, BOOKE
|PPCVLE
, PPCNONE
, {RT
}},
4915 {"mfdac2", XSPR(31,339,317), XSPR_MASK
, BOOKE
|PPCVLE
, PPCNONE
, {RT
}},
4916 {"mfdvc1", XSPR(31,339,318), XSPR_MASK
, BOOKE
|PPCVLE
, PPCNONE
, {RT
}},
4917 {"mfdvc2", XSPR(31,339,319), XSPR_MASK
, BOOKE
|PPCVLE
, PPCNONE
, {RT
}},
4918 {"mftsr", XSPR(31,339,336), XSPR_MASK
, BOOKE
|PPCVLE
, PPCNONE
, {RT
}},
4919 {"mftcr", XSPR(31,339,340), XSPR_MASK
, BOOKE
|PPCVLE
, PPCNONE
, {RT
}},
4920 {"mfivor0", XSPR(31,339,400), XSPR_MASK
, BOOKE
|PPCVLE
, PPCNONE
, {RT
}},
4921 {"mfivor1", XSPR(31,339,401), XSPR_MASK
, BOOKE
|PPCVLE
, PPCNONE
, {RT
}},
4922 {"mfivor2", XSPR(31,339,402), XSPR_MASK
, BOOKE
|PPCVLE
, PPCNONE
, {RT
}},
4923 {"mfivor3", XSPR(31,339,403), XSPR_MASK
, BOOKE
|PPCVLE
, PPCNONE
, {RT
}},
4924 {"mfivor4", XSPR(31,339,404), XSPR_MASK
, BOOKE
|PPCVLE
, PPCNONE
, {RT
}},
4925 {"mfivor5", XSPR(31,339,405), XSPR_MASK
, BOOKE
|PPCVLE
, PPCNONE
, {RT
}},
4926 {"mfivor6", XSPR(31,339,406), XSPR_MASK
, BOOKE
|PPCVLE
, PPCNONE
, {RT
}},
4927 {"mfivor7", XSPR(31,339,407), XSPR_MASK
, BOOKE
|PPCVLE
, PPCNONE
, {RT
}},
4928 {"mfivor8", XSPR(31,339,408), XSPR_MASK
, BOOKE
|PPCVLE
, PPCNONE
, {RT
}},
4929 {"mfivor9", XSPR(31,339,409), XSPR_MASK
, BOOKE
|PPCVLE
, PPCNONE
, {RT
}},
4930 {"mfivor10", XSPR(31,339,410), XSPR_MASK
, BOOKE
|PPCVLE
, PPCNONE
, {RT
}},
4931 {"mfivor11", XSPR(31,339,411), XSPR_MASK
, BOOKE
|PPCVLE
, PPCNONE
, {RT
}},
4932 {"mfivor12", XSPR(31,339,412), XSPR_MASK
, BOOKE
|PPCVLE
, PPCNONE
, {RT
}},
4933 {"mfivor13", XSPR(31,339,413), XSPR_MASK
, BOOKE
|PPCVLE
, PPCNONE
, {RT
}},
4934 {"mfivor14", XSPR(31,339,414), XSPR_MASK
, BOOKE
|PPCVLE
, PPCNONE
, {RT
}},
4935 {"mfivor15", XSPR(31,339,415), XSPR_MASK
, BOOKE
|PPCVLE
, PPCNONE
, {RT
}},
4936 {"mfspefscr", XSPR(31,339,512), XSPR_MASK
, PPCSPE
, PPCNONE
, {RT
}},
4937 {"mfbbear", XSPR(31,339,513), XSPR_MASK
, PPCBRLK
, PPCNONE
, {RT
}},
4938 {"mfbbtar", XSPR(31,339,514), XSPR_MASK
, PPCBRLK
, PPCNONE
, {RT
}},
4939 {"mfivor32", XSPR(31,339,528), XSPR_MASK
, PPCSPE
, PPCNONE
, {RT
}},
4940 {"mfibatu", XSPR(31,339,528), XSPRBAT_MASK
, PPC
, TITAN
, {RT
, SPRBAT
}},
4941 {"mfivor33", XSPR(31,339,529), XSPR_MASK
, PPCSPE
, PPCNONE
, {RT
}},
4942 {"mfibatl", XSPR(31,339,529), XSPRBAT_MASK
, PPC
, TITAN
, {RT
, SPRBAT
}},
4943 {"mfivor34", XSPR(31,339,530), XSPR_MASK
, PPCSPE
, PPCNONE
, {RT
}},
4944 {"mfivor35", XSPR(31,339,531), XSPR_MASK
, PPCPMR
, PPCNONE
, {RT
}},
4945 {"mfdbatu", XSPR(31,339,536), XSPRBAT_MASK
, PPC
, TITAN
, {RT
, SPRBAT
}},
4946 {"mfdbatl", XSPR(31,339,537), XSPRBAT_MASK
, PPC
, TITAN
, {RT
, SPRBAT
}},
4947 {"mfic_cst", XSPR(31,339,560), XSPR_MASK
, PPC860
, PPCNONE
, {RT
}},
4948 {"mfic_adr", XSPR(31,339,561), XSPR_MASK
, PPC860
, PPCNONE
, {RT
}},
4949 {"mfic_dat", XSPR(31,339,562), XSPR_MASK
, PPC860
, PPCNONE
, {RT
}},
4950 {"mfdc_cst", XSPR(31,339,568), XSPR_MASK
, PPC860
, PPCNONE
, {RT
}},
4951 {"mfdc_adr", XSPR(31,339,569), XSPR_MASK
, PPC860
, PPCNONE
, {RT
}},
4952 {"mfdc_dat", XSPR(31,339,570), XSPR_MASK
, PPC860
, PPCNONE
, {RT
}},
4953 {"mfmcsrr0", XSPR(31,339,570), XSPR_MASK
, PPCRFMCI
, PPCNONE
, {RT
}},
4954 {"mfmcsrr1", XSPR(31,339,571), XSPR_MASK
, PPCRFMCI
, PPCNONE
, {RT
}},
4955 {"mfmcsr", XSPR(31,339,572), XSPR_MASK
, PPCRFMCI
, PPCNONE
, {RT
}},
4956 {"mfmcar", XSPR(31,339,573), XSPR_MASK
, PPCRFMCI
, TITAN
, {RT
}},
4957 {"mfdpdr", XSPR(31,339,630), XSPR_MASK
, PPC860
, PPCNONE
, {RT
}},
4958 {"mfdpir", XSPR(31,339,631), XSPR_MASK
, PPC860
, PPCNONE
, {RT
}},
4959 {"mfimmr", XSPR(31,339,638), XSPR_MASK
, PPC860
, PPCNONE
, {RT
}},
4960 {"mfmi_ctr", XSPR(31,339,784), XSPR_MASK
, PPC860
, PPCNONE
, {RT
}},
4961 {"mfmi_ap", XSPR(31,339,786), XSPR_MASK
, PPC860
, PPCNONE
, {RT
}},
4962 {"mfmi_epn", XSPR(31,339,787), XSPR_MASK
, PPC860
, PPCNONE
, {RT
}},
4963 {"mfmi_twc", XSPR(31,339,789), XSPR_MASK
, PPC860
, PPCNONE
, {RT
}},
4964 {"mfmi_rpn", XSPR(31,339,790), XSPR_MASK
, PPC860
, PPCNONE
, {RT
}},
4965 {"mfmd_ctr", XSPR(31,339,792), XSPR_MASK
, PPC860
, PPCNONE
, {RT
}},
4966 {"mfm_casid", XSPR(31,339,793), XSPR_MASK
, PPC860
, PPCNONE
, {RT
}},
4967 {"mfmd_ap", XSPR(31,339,794), XSPR_MASK
, PPC860
, PPCNONE
, {RT
}},
4968 {"mfmd_epn", XSPR(31,339,795), XSPR_MASK
, PPC860
, PPCNONE
, {RT
}},
4969 {"mfmd_twb", XSPR(31,339,796), XSPR_MASK
, PPC860
, PPCNONE
, {RT
}},
4970 {"mfmd_twc", XSPR(31,339,797), XSPR_MASK
, PPC860
, PPCNONE
, {RT
}},
4971 {"mfmd_rpn", XSPR(31,339,798), XSPR_MASK
, PPC860
, PPCNONE
, {RT
}},
4972 {"mfm_tw", XSPR(31,339,799), XSPR_MASK
, PPC860
, PPCNONE
, {RT
}},
4973 {"mfmi_dbcam", XSPR(31,339,816), XSPR_MASK
, PPC860
, PPCNONE
, {RT
}},
4974 {"mfmi_dbram0", XSPR(31,339,817), XSPR_MASK
, PPC860
, PPCNONE
, {RT
}},
4975 {"mfmi_dbram1", XSPR(31,339,818), XSPR_MASK
, PPC860
, PPCNONE
, {RT
}},
4976 {"mfmd_dbcam", XSPR(31,339,824), XSPR_MASK
, PPC860
, PPCNONE
, {RT
}},
4977 {"mfmd_dbram0", XSPR(31,339,825), XSPR_MASK
, PPC860
, PPCNONE
, {RT
}},
4978 {"mfmd_dbram1", XSPR(31,339,826), XSPR_MASK
, PPC860
, PPCNONE
, {RT
}},
4979 {"mfivndx", XSPR(31,339,880), XSPR_MASK
, TITAN
, PPCNONE
, {RT
}},
4980 {"mfdvndx", XSPR(31,339,881), XSPR_MASK
, TITAN
, PPCNONE
, {RT
}},
4981 {"mfivlim", XSPR(31,339,882), XSPR_MASK
, TITAN
, PPCNONE
, {RT
}},
4982 {"mfdvlim", XSPR(31,339,883), XSPR_MASK
, TITAN
, PPCNONE
, {RT
}},
4983 {"mfclcsr", XSPR(31,339,884), XSPR_MASK
, TITAN
, PPCNONE
, {RT
}},
4984 {"mfccr1", XSPR(31,339,888), XSPR_MASK
, TITAN
, PPCNONE
, {RT
}},
4985 {"mfppr", XSPR(31,339,896), XSPR_MASK
, POWER7
, PPCNONE
, {RT
}},
4986 {"mfppr32", XSPR(31,339,898), XSPR_MASK
, POWER7
, PPCNONE
, {RT
}},
4987 {"mfrstcfg", XSPR(31,339,923), XSPR_MASK
, TITAN
, PPCNONE
, {RT
}},
4988 {"mfdcdbtrl", XSPR(31,339,924), XSPR_MASK
, TITAN
, PPCNONE
, {RT
}},
4989 {"mfdcdbtrh", XSPR(31,339,925), XSPR_MASK
, TITAN
, PPCNONE
, {RT
}},
4990 {"mficdbtr", XSPR(31,339,927), XSPR_MASK
, TITAN
, PPCNONE
, {RT
}},
4991 {"mfummcr0", XSPR(31,339,936), XSPR_MASK
, PPC750
, PPCNONE
, {RT
}},
4992 {"mfupmc1", XSPR(31,339,937), XSPR_MASK
, PPC750
, PPCNONE
, {RT
}},
4993 {"mfupmc2", XSPR(31,339,938), XSPR_MASK
, PPC750
, PPCNONE
, {RT
}},
4994 {"mfusia", XSPR(31,339,939), XSPR_MASK
, PPC750
, PPCNONE
, {RT
}},
4995 {"mfummcr1", XSPR(31,339,940), XSPR_MASK
, PPC750
, PPCNONE
, {RT
}},
4996 {"mfupmc3", XSPR(31,339,941), XSPR_MASK
, PPC750
, PPCNONE
, {RT
}},
4997 {"mfupmc4", XSPR(31,339,942), XSPR_MASK
, PPC750
, PPCNONE
, {RT
}},
4998 {"mfzpr", XSPR(31,339,944), XSPR_MASK
, PPC403
, PPCNONE
, {RT
}},
4999 {"mfpid", XSPR(31,339,945), XSPR_MASK
, PPC403
, PPCNONE
, {RT
}},
5000 {"mfmmucr", XSPR(31,339,946), XSPR_MASK
, TITAN
, PPCNONE
, {RT
}},
5001 {"mfccr0", XSPR(31,339,947), XSPR_MASK
, PPC405
|TITAN
, PPCNONE
, {RT
}},
5002 {"mfiac3", XSPR(31,339,948), XSPR_MASK
, PPC405
, PPCNONE
, {RT
}},
5003 {"mfiac4", XSPR(31,339,949), XSPR_MASK
, PPC405
, PPCNONE
, {RT
}},
5004 {"mfdvc1", XSPR(31,339,950), XSPR_MASK
, PPC405
, PPCNONE
, {RT
}},
5005 {"mfdvc2", XSPR(31,339,951), XSPR_MASK
, PPC405
, PPCNONE
, {RT
}},
5006 {"mfmmcr0", XSPR(31,339,952), XSPR_MASK
, PPC750
, PPCNONE
, {RT
}},
5007 {"mfpmc1", XSPR(31,339,953), XSPR_MASK
, PPC750
, PPCNONE
, {RT
}},
5008 {"mfsgr", XSPR(31,339,953), XSPR_MASK
, PPC403
, PPCNONE
, {RT
}},
5009 {"mfdcwr", XSPR(31,339,954), XSPR_MASK
, PPC403
, PPCNONE
, {RT
}},
5010 {"mfpmc2", XSPR(31,339,954), XSPR_MASK
, PPC750
, PPCNONE
, {RT
}},
5011 {"mfsia", XSPR(31,339,955), XSPR_MASK
, PPC750
, PPCNONE
, {RT
}},
5012 {"mfsler", XSPR(31,339,955), XSPR_MASK
, PPC405
, PPCNONE
, {RT
}},
5013 {"mfmmcr1", XSPR(31,339,956), XSPR_MASK
, PPC750
, PPCNONE
, {RT
}},
5014 {"mfsu0r", XSPR(31,339,956), XSPR_MASK
, PPC405
, PPCNONE
, {RT
}},
5015 {"mfdbcr1", XSPR(31,339,957), XSPR_MASK
, PPC405
, PPCNONE
, {RT
}},
5016 {"mfpmc3", XSPR(31,339,957), XSPR_MASK
, PPC750
, PPCNONE
, {RT
}},
5017 {"mfpmc4", XSPR(31,339,958), XSPR_MASK
, PPC750
, PPCNONE
, {RT
}},
5018 {"mficdbdr", XSPR(31,339,979), XSPR_MASK
, PPC403
|TITAN
, PPCNONE
, {RT
}},
5019 {"mfesr", XSPR(31,339,980), XSPR_MASK
, PPC403
, PPCNONE
, {RT
}},
5020 {"mfdear", XSPR(31,339,981), XSPR_MASK
, PPC403
, PPCNONE
, {RT
}},
5021 {"mfevpr", XSPR(31,339,982), XSPR_MASK
, PPC403
, PPCNONE
, {RT
}},
5022 {"mfcdbcr", XSPR(31,339,983), XSPR_MASK
, PPC403
, PPCNONE
, {RT
}},
5023 {"mftsr", XSPR(31,339,984), XSPR_MASK
, PPC403
, PPCNONE
, {RT
}},
5024 {"mftcr", XSPR(31,339,986), XSPR_MASK
, PPC403
, PPCNONE
, {RT
}},
5025 {"mfpit", XSPR(31,339,987), XSPR_MASK
, PPC403
, PPCNONE
, {RT
}},
5026 {"mftbhi", XSPR(31,339,988), XSPR_MASK
, PPC403
, PPCNONE
, {RT
}},
5027 {"mftblo", XSPR(31,339,989), XSPR_MASK
, PPC403
, PPCNONE
, {RT
}},
5028 {"mfsrr2", XSPR(31,339,990), XSPR_MASK
, PPC403
, PPCNONE
, {RT
}},
5029 {"mfsrr3", XSPR(31,339,991), XSPR_MASK
, PPC403
, PPCNONE
, {RT
}},
5030 {"mfdbsr", XSPR(31,339,1008), XSPR_MASK
, PPC403
, PPCNONE
, {RT
}},
5031 {"mfdbcr0", XSPR(31,339,1010), XSPR_MASK
, PPC405
, PPCNONE
, {RT
}},
5032 {"mfdbdr", XSPR(31,339,1011), XSPR_MASK
, TITAN
, PPCNONE
, {RS
}},
5033 {"mfiac1", XSPR(31,339,1012), XSPR_MASK
, PPC403
, PPCNONE
, {RT
}},
5034 {"mfiac2", XSPR(31,339,1013), XSPR_MASK
, PPC403
, PPCNONE
, {RT
}},
5035 {"mfdac1", XSPR(31,339,1014), XSPR_MASK
, PPC403
, PPCNONE
, {RT
}},
5036 {"mfdac2", XSPR(31,339,1015), XSPR_MASK
, PPC403
, PPCNONE
, {RT
}},
5037 {"mfl2cr", XSPR(31,339,1017), XSPR_MASK
, PPC750
, PPCNONE
, {RT
}},
5038 {"mfdccr", XSPR(31,339,1018), XSPR_MASK
, PPC403
, PPCNONE
, {RT
}},
5039 {"mficcr", XSPR(31,339,1019), XSPR_MASK
, PPC403
, PPCNONE
, {RT
}},
5040 {"mfictc", XSPR(31,339,1019), XSPR_MASK
, PPC750
, PPCNONE
, {RT
}},
5041 {"mfpbl1", XSPR(31,339,1020), XSPR_MASK
, PPC403
, PPCNONE
, {RT
}},
5042 {"mfthrm1", XSPR(31,339,1020), XSPR_MASK
, PPC750
, PPCNONE
, {RT
}},
5043 {"mfpbu1", XSPR(31,339,1021), XSPR_MASK
, PPC403
, PPCNONE
, {RT
}},
5044 {"mfthrm2", XSPR(31,339,1021), XSPR_MASK
, PPC750
, PPCNONE
, {RT
}},
5045 {"mfpbl2", XSPR(31,339,1022), XSPR_MASK
, PPC403
, PPCNONE
, {RT
}},
5046 {"mfthrm3", XSPR(31,339,1022), XSPR_MASK
, PPC750
, PPCNONE
, {RT
}},
5047 {"mfpbu2", XSPR(31,339,1023), XSPR_MASK
, PPC403
, PPCNONE
, {RT
}},
5048 {"mfspr", X(31,339), X_MASK
, COM
|PPCVLE
, PPCNONE
, {RT
, SPR
}},
5050 {"lwax", X(31,341), X_MASK
, PPC64
|PPCVLE
, PPCNONE
, {RT
, RA0
, RB
}},
5052 {"dst", XDSS(31,342,0), XDSS_MASK
, PPCVEC
, PPCNONE
, {RA
, RB
, STRM
}},
5054 {"lhax", X(31,343), X_MASK
, COM
|PPCVLE
, PPCNONE
, {RT
, RA0
, RB
}},
5056 {"lvxl", X(31,359), X_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, RA0
, RB
}},
5058 {"abs", XO(31,360,0,0), XORB_MASK
, M601
, PPCNONE
, {RT
, RA
}},
5059 {"abs.", XO(31,360,0,1), XORB_MASK
, M601
, PPCNONE
, {RT
, RA
}},
5061 {"divs", XO(31,363,0,0), XO_MASK
, M601
, PPCNONE
, {RT
, RA
, RB
}},
5062 {"divs.", XO(31,363,0,1), XO_MASK
, M601
, PPCNONE
, {RT
, RA
, RB
}},
5064 {"tlbia", X(31,370), 0xffffffff, PPC
, TITAN
, {0}},
5066 {"mftbu", XSPR(31,371,269), XSPR_MASK
, PPC
, NO371
|POWER4
, {RT
}},
5067 {"mftb", X(31,371), X_MASK
, PPC
, NO371
|POWER4
, {RT
, TBR
}},
5068 {"mftbl", XSPR(31,371,268), XSPR_MASK
, PPC
, NO371
|POWER4
, {RT
}},
5070 {"lwaux", X(31,373), X_MASK
, PPC64
|PPCVLE
, PPCNONE
, {RT
, RAL
, RB
}},
5072 {"dstst", XDSS(31,374,0), XDSS_MASK
, PPCVEC
, PPCNONE
, {RA
, RB
, STRM
}},
5074 {"lhaux", X(31,375), X_MASK
, COM
|PPCVLE
, PPCNONE
, {RT
, RAL
, RB
}},
5076 {"popcntw", X(31,378), XRB_MASK
, POWER7
|PPCA2
, PPCNONE
, {RA
, RS
}},
5078 {"mtdcrx", X(31,387), X_MASK
, BOOKE
|PPCA2
|PPC476
|PPCVLE
, TITAN
, {RA
, RS
}},
5079 {"mtdcrx.", XRC(31,387,1), X_MASK
, PPCA2
, PPCNONE
, {RA
, RS
}},
5081 {"stvexbx", X(31,389), X_MASK
, PPCVEC2
, PPCNONE
, {VS
, RA0
, RB
}},
5083 {"dcblc", X(31,390), X_MASK
, PPCCHLK
|PPC476
|TITAN
|PPCVLE
, PPCNONE
, {CT
, RA0
, RB
}},
5084 {"stdfcmx", APU(31,391,0), APU_MASK
, PPC405
, PPCNONE
, {FCRT
, RA
, RB
}},
5086 {"divdeu", XO(31,393,0,0), XO_MASK
, POWER7
|PPCA2
, PPCNONE
, {RT
, RA
, RB
}},
5087 {"divdeu.", XO(31,393,0,1), XO_MASK
, POWER7
|PPCA2
, PPCNONE
, {RT
, RA
, RB
}},
5088 {"divweu", XO(31,395,0,0), XO_MASK
, POWER7
|PPCA2
, PPCNONE
, {RT
, RA
, RB
}},
5089 {"divweu.", XO(31,395,0,1), XO_MASK
, POWER7
|PPCA2
, PPCNONE
, {RT
, RA
, RB
}},
5091 {"dcblce", X(31,398), X_MASK
, PPCCHLK
, E500MC
, {CT
, RA
, RB
}},
5093 {"slbmte", X(31,402), XRA_MASK
, PPC64
, PPCNONE
, {RS
, RB
}},
5095 {"pbt.", XRC(31,404,1), X_MASK
, POWER8
, PPCNONE
, {RS
, RA0
, RB
}},
5097 {"icswx", XRC(31,406,0), X_MASK
, POWER7
|PPCA2
, PPCNONE
, {RS
, RA
, RB
}},
5098 {"icswx.", XRC(31,406,1), X_MASK
, POWER7
|PPCA2
, PPCNONE
, {RS
, RA
, RB
}},
5100 {"sthx", X(31,407), X_MASK
, COM
|PPCVLE
, PPCNONE
, {RS
, RA0
, RB
}},
5102 {"orc", XRC(31,412,0), X_MASK
, COM
|PPCVLE
, PPCNONE
, {RA
, RS
, RB
}},
5103 {"orc.", XRC(31,412,1), X_MASK
, COM
|PPCVLE
, PPCNONE
, {RA
, RS
, RB
}},
5105 {"sthepx", X(31,415), X_MASK
, E500MC
|PPCA2
|PPCVLE
, PPCNONE
, {RS
, RA0
, RB
}},
5107 {"mtdcrux", X(31,419), X_MASK
, PPC464
|PPCVLE
, PPCNONE
, {RA
, RS
}},
5109 {"stvexhx", X(31,421), X_MASK
, PPCVEC2
, PPCNONE
, {VS
, RA0
, RB
}},
5111 {"dcblq.", XRC(31,422,1), X_MASK
, E6500
, PPCNONE
, {CT
, RA0
, RB
}},
5113 {"divde", XO(31,425,0,0), XO_MASK
, POWER7
|PPCA2
, PPCNONE
, {RT
, RA
, RB
}},
5114 {"divde.", XO(31,425,0,1), XO_MASK
, POWER7
|PPCA2
, PPCNONE
, {RT
, RA
, RB
}},
5115 {"divwe", XO(31,427,0,0), XO_MASK
, POWER7
|PPCA2
, PPCNONE
, {RT
, RA
, RB
}},
5116 {"divwe.", XO(31,427,0,1), XO_MASK
, POWER7
|PPCA2
, PPCNONE
, {RT
, RA
, RB
}},
5118 {"clrbhrb", X(31,430), 0xffffffff, POWER8
, PPCNONE
, {0}},
5120 {"slbie", X(31,434), XRTRA_MASK
, PPC64
, PPCNONE
, {RB
}},
5122 {"ecowx", X(31,438), X_MASK
, PPC
, TITAN
, {RT
, RA0
, RB
}},
5124 {"sthux", X(31,439), X_MASK
, COM
|PPCVLE
, PPCNONE
, {RS
, RAS
, RB
}},
5126 {"mdors", 0x7f9ce378, 0xffffffff, E500MC
, PPCNONE
, {0}},
5128 {"miso", 0x7f5ad378, 0xffffffff, E6500
, PPCNONE
, {0}},
5130 /* The "yield", "mdoio" and "mdoom" instructions are extended mnemonics for
5131 "or rX,rX,rX", with rX being r27, r29 and r30 respectively. */
5132 {"yield", 0x7f7bdb78, 0xffffffff, POWER7
, PPCNONE
, {0}},
5133 {"mdoio", 0x7fbdeb78, 0xffffffff, POWER7
, PPCNONE
, {0}},
5134 {"mdoom", 0x7fdef378, 0xffffffff, POWER7
, PPCNONE
, {0}},
5135 {"mr", XRC(31,444,0), X_MASK
, COM
|PPCVLE
, PPCNONE
, {RA
, RS
, RBS
}},
5136 {"or", XRC(31,444,0), X_MASK
, COM
|PPCVLE
, PPCNONE
, {RA
, RS
, RB
}},
5137 {"mr.", XRC(31,444,1), X_MASK
, COM
|PPCVLE
, PPCNONE
, {RA
, RS
, RBS
}},
5138 {"or.", XRC(31,444,1), X_MASK
, COM
|PPCVLE
, PPCNONE
, {RA
, RS
, RB
}},
5140 {"mtexisr", XSPR(31,451, 64), XSPR_MASK
, PPC403
, PPCNONE
, {RS
}},
5141 {"mtexier", XSPR(31,451, 66), XSPR_MASK
, PPC403
, PPCNONE
, {RS
}},
5142 {"mtbr0", XSPR(31,451,128), XSPR_MASK
, PPC403
, PPCNONE
, {RS
}},
5143 {"mtbr1", XSPR(31,451,129), XSPR_MASK
, PPC403
, PPCNONE
, {RS
}},
5144 {"mtbr2", XSPR(31,451,130), XSPR_MASK
, PPC403
, PPCNONE
, {RS
}},
5145 {"mtbr3", XSPR(31,451,131), XSPR_MASK
, PPC403
, PPCNONE
, {RS
}},
5146 {"mtbr4", XSPR(31,451,132), XSPR_MASK
, PPC403
, PPCNONE
, {RS
}},
5147 {"mtbr5", XSPR(31,451,133), XSPR_MASK
, PPC403
, PPCNONE
, {RS
}},
5148 {"mtbr6", XSPR(31,451,134), XSPR_MASK
, PPC403
, PPCNONE
, {RS
}},
5149 {"mtbr7", XSPR(31,451,135), XSPR_MASK
, PPC403
, PPCNONE
, {RS
}},
5150 {"mtbear", XSPR(31,451,144), XSPR_MASK
, PPC403
, PPCNONE
, {RS
}},
5151 {"mtbesr", XSPR(31,451,145), XSPR_MASK
, PPC403
, PPCNONE
, {RS
}},
5152 {"mtiocr", XSPR(31,451,160), XSPR_MASK
, PPC403
, PPCNONE
, {RS
}},
5153 {"mtdmacr0", XSPR(31,451,192), XSPR_MASK
, PPC403
, PPCNONE
, {RS
}},
5154 {"mtdmact0", XSPR(31,451,193), XSPR_MASK
, PPC403
, PPCNONE
, {RS
}},
5155 {"mtdmada0", XSPR(31,451,194), XSPR_MASK
, PPC403
, PPCNONE
, {RS
}},
5156 {"mtdmasa0", XSPR(31,451,195), XSPR_MASK
, PPC403
, PPCNONE
, {RS
}},
5157 {"mtdmacc0", XSPR(31,451,196), XSPR_MASK
, PPC403
, PPCNONE
, {RS
}},
5158 {"mtdmacr1", XSPR(31,451,200), XSPR_MASK
, PPC403
, PPCNONE
, {RS
}},
5159 {"mtdmact1", XSPR(31,451,201), XSPR_MASK
, PPC403
, PPCNONE
, {RS
}},
5160 {"mtdmada1", XSPR(31,451,202), XSPR_MASK
, PPC403
, PPCNONE
, {RS
}},
5161 {"mtdmasa1", XSPR(31,451,203), XSPR_MASK
, PPC403
, PPCNONE
, {RS
}},
5162 {"mtdmacc1", XSPR(31,451,204), XSPR_MASK
, PPC403
, PPCNONE
, {RS
}},
5163 {"mtdmacr2", XSPR(31,451,208), XSPR_MASK
, PPC403
, PPCNONE
, {RS
}},
5164 {"mtdmact2", XSPR(31,451,209), XSPR_MASK
, PPC403
, PPCNONE
, {RS
}},
5165 {"mtdmada2", XSPR(31,451,210), XSPR_MASK
, PPC403
, PPCNONE
, {RS
}},
5166 {"mtdmasa2", XSPR(31,451,211), XSPR_MASK
, PPC403
, PPCNONE
, {RS
}},
5167 {"mtdmacc2", XSPR(31,451,212), XSPR_MASK
, PPC403
, PPCNONE
, {RS
}},
5168 {"mtdmacr3", XSPR(31,451,216), XSPR_MASK
, PPC403
, PPCNONE
, {RS
}},
5169 {"mtdmact3", XSPR(31,451,217), XSPR_MASK
, PPC403
, PPCNONE
, {RS
}},
5170 {"mtdmada3", XSPR(31,451,218), XSPR_MASK
, PPC403
, PPCNONE
, {RS
}},
5171 {"mtdmasa3", XSPR(31,451,219), XSPR_MASK
, PPC403
, PPCNONE
, {RS
}},
5172 {"mtdmacc3", XSPR(31,451,220), XSPR_MASK
, PPC403
, PPCNONE
, {RS
}},
5173 {"mtdmasr", XSPR(31,451,224), XSPR_MASK
, PPC403
, PPCNONE
, {RS
}},
5174 {"mtdcr", X(31,451), X_MASK
, PPC403
|BOOKE
|PPCA2
|PPC476
|PPCVLE
, TITAN
, {SPR
, RS
}},
5175 {"mtdcr.", XRC(31,451,1), X_MASK
, PPCA2
, PPCNONE
, {SPR
, RS
}},
5177 {"stvexwx", X(31,453), X_MASK
, PPCVEC2
, PPCNONE
, {VS
, RA0
, RB
}},
5179 {"dccci", X(31,454), XRT_MASK
, PPC403
|PPC440
|TITAN
|PPCA2
, PPCNONE
, {RAOPT
, RBOPT
}},
5180 {"dci", X(31,454), XRARB_MASK
, PPCA2
|PPC476
|PPCVLE
, PPCNONE
, {CT
}},
5182 {"divdu", XO(31,457,0,0), XO_MASK
, PPC64
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
5183 {"divdu.", XO(31,457,0,1), XO_MASK
, PPC64
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
5185 {"divwu", XO(31,459,0,0), XO_MASK
, PPC
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
5186 {"divwu.", XO(31,459,0,1), XO_MASK
, PPC
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
5188 {"mtpmr", X(31,462), X_MASK
, PPCPMR
|PPCE300
|PPCVLE
, PPCNONE
, {PMR
, RS
}},
5189 {"mttmr", X(31,494), X_MASK
, PPCTMR
|E6500
, PPCNONE
, {TMR
, RS
}},
5191 {"mtmq", XSPR(31,467, 0), XSPR_MASK
, M601
, PPCNONE
, {RS
}},
5192 {"mtxer", XSPR(31,467, 1), XSPR_MASK
, COM
|PPCVLE
, PPCNONE
, {RS
}},
5193 {"mtlr", XSPR(31,467, 8), XSPR_MASK
, COM
|PPCVLE
, PPCNONE
, {RS
}},
5194 {"mtctr", XSPR(31,467, 9), XSPR_MASK
, COM
|PPCVLE
, PPCNONE
, {RS
}},
5195 {"mttid", XSPR(31,467, 17), XSPR_MASK
, POWER
, PPCNONE
, {RS
}},
5196 {"mtdsisr", XSPR(31,467, 18), XSPR_MASK
, COM
, TITAN
, {RS
}},
5197 {"mtdar", XSPR(31,467, 19), XSPR_MASK
, COM
, TITAN
, {RS
}},
5198 {"mtrtcu", XSPR(31,467, 20), XSPR_MASK
, COM
, TITAN
, {RS
}},
5199 {"mtrtcl", XSPR(31,467, 21), XSPR_MASK
, COM
, TITAN
, {RS
}},
5200 {"mtdec", XSPR(31,467, 22), XSPR_MASK
, COM
, PPCNONE
, {RS
}},
5201 {"mtsdr0", XSPR(31,467, 24), XSPR_MASK
, POWER
, PPCNONE
, {RS
}},
5202 {"mtsdr1", XSPR(31,467, 25), XSPR_MASK
, COM
, TITAN
, {RS
}},
5203 {"mtsrr0", XSPR(31,467, 26), XSPR_MASK
, COM
|PPCVLE
, PPCNONE
, {RS
}},
5204 {"mtsrr1", XSPR(31,467, 27), XSPR_MASK
, COM
|PPCVLE
, PPCNONE
, {RS
}},
5205 {"mtcfar", XSPR(31,467, 28), XSPR_MASK
, POWER6
, PPCNONE
, {RS
}},
5206 {"mtpid", XSPR(31,467, 48), XSPR_MASK
, BOOKE
|PPCVLE
, PPCNONE
, {RS
}},
5207 {"mtdecar", XSPR(31,467, 54), XSPR_MASK
, BOOKE
|PPCVLE
, PPCNONE
, {RS
}},
5208 {"mtcsrr0", XSPR(31,467, 58), XSPR_MASK
, BOOKE
|PPCVLE
, PPCNONE
, {RS
}},
5209 {"mtcsrr1", XSPR(31,467, 59), XSPR_MASK
, BOOKE
|PPCVLE
, PPCNONE
, {RS
}},
5210 {"mtdear", XSPR(31,467, 61), XSPR_MASK
, BOOKE
|PPCVLE
, PPCNONE
, {RS
}},
5211 {"mtesr", XSPR(31,467, 62), XSPR_MASK
, BOOKE
|PPCVLE
, PPCNONE
, {RS
}},
5212 {"mtivpr", XSPR(31,467, 63), XSPR_MASK
, BOOKE
|PPCVLE
, PPCNONE
, {RS
}},
5213 {"mtcmpa", XSPR(31,467,144), XSPR_MASK
, PPC860
, PPCNONE
, {RS
}},
5214 {"mtcmpb", XSPR(31,467,145), XSPR_MASK
, PPC860
, PPCNONE
, {RS
}},
5215 {"mtcmpc", XSPR(31,467,146), XSPR_MASK
, PPC860
, PPCNONE
, {RS
}},
5216 {"mtcmpd", XSPR(31,467,147), XSPR_MASK
, PPC860
, PPCNONE
, {RS
}},
5217 {"mticr", XSPR(31,467,148), XSPR_MASK
, PPC860
, PPCNONE
, {RS
}},
5218 {"mtder", XSPR(31,467,149), XSPR_MASK
, PPC860
, PPCNONE
, {RS
}},
5219 {"mtcounta", XSPR(31,467,150), XSPR_MASK
, PPC860
, PPCNONE
, {RS
}},
5220 {"mtcountb", XSPR(31,467,151), XSPR_MASK
, PPC860
, PPCNONE
, {RS
}},
5221 {"mtcmpe", XSPR(31,467,152), XSPR_MASK
, PPC860
, PPCNONE
, {RS
}},
5222 {"mtcmpf", XSPR(31,467,153), XSPR_MASK
, PPC860
, PPCNONE
, {RS
}},
5223 {"mtcmpg", XSPR(31,467,154), XSPR_MASK
, PPC860
, PPCNONE
, {RS
}},
5224 {"mtcmph", XSPR(31,467,155), XSPR_MASK
, PPC860
, PPCNONE
, {RS
}},
5225 {"mtlctrl1", XSPR(31,467,156), XSPR_MASK
, PPC860
, PPCNONE
, {RS
}},
5226 {"mtlctrl2", XSPR(31,467,157), XSPR_MASK
, PPC860
, PPCNONE
, {RS
}},
5227 {"mtictrl", XSPR(31,467,158), XSPR_MASK
, PPC860
, PPCNONE
, {RS
}},
5228 {"mtbar", XSPR(31,467,159), XSPR_MASK
, PPC860
, PPCNONE
, {RS
}},
5229 {"mtvrsave", XSPR(31,467,256), XSPR_MASK
, PPCVEC
, PPCNONE
, {RS
}},
5230 {"mtusprg0", XSPR(31,467,256), XSPR_MASK
, BOOKE
|PPCVLE
, PPCNONE
, {RS
}},
5231 {"mtsprg", XSPR(31,467,256), XSPRG_MASK
, PPC
|PPCVLE
, PPCNONE
, {SPRG
, RS
}},
5232 {"mtsprg0", XSPR(31,467,272), XSPR_MASK
, PPC
|PPCVLE
, PPCNONE
, {RS
}},
5233 {"mtsprg1", XSPR(31,467,273), XSPR_MASK
, PPC
|PPCVLE
, PPCNONE
, {RS
}},
5234 {"mtsprg2", XSPR(31,467,274), XSPR_MASK
, PPC
|PPCVLE
, PPCNONE
, {RS
}},
5235 {"mtsprg3", XSPR(31,467,275), XSPR_MASK
, PPC
|PPCVLE
, PPCNONE
, {RS
}},
5236 {"mtsprg4", XSPR(31,467,276), XSPR_MASK
, PPC405
|BOOKE
|PPCVLE
, PPCNONE
, {RS
}},
5237 {"mtsprg5", XSPR(31,467,277), XSPR_MASK
, PPC405
|BOOKE
|PPCVLE
, PPCNONE
, {RS
}},
5238 {"mtsprg6", XSPR(31,467,278), XSPR_MASK
, PPC405
|BOOKE
|PPCVLE
, PPCNONE
, {RS
}},
5239 {"mtsprg7", XSPR(31,467,279), XSPR_MASK
, PPC405
|BOOKE
|PPCVLE
, PPCNONE
, {RS
}},
5240 {"mtasr", XSPR(31,467,280), XSPR_MASK
, PPC64
, PPCNONE
, {RS
}},
5241 {"mtear", XSPR(31,467,282), XSPR_MASK
, PPC
, TITAN
, {RS
}},
5242 {"mttbl", XSPR(31,467,284), XSPR_MASK
, PPC
, PPCNONE
, {RS
}},
5243 {"mttbu", XSPR(31,467,285), XSPR_MASK
, PPC
, PPCNONE
, {RS
}},
5244 {"mtdbsr", XSPR(31,467,304), XSPR_MASK
, BOOKE
|PPCVLE
, PPCNONE
, {RS
}},
5245 {"mtdbcr0", XSPR(31,467,308), XSPR_MASK
, BOOKE
|PPCVLE
, PPCNONE
, {RS
}},
5246 {"mtdbcr1", XSPR(31,467,309), XSPR_MASK
, BOOKE
|PPCVLE
, PPCNONE
, {RS
}},
5247 {"mtdbcr2", XSPR(31,467,310), XSPR_MASK
, BOOKE
|PPCVLE
, PPCNONE
, {RS
}},
5248 {"mtiac1", XSPR(31,467,312), XSPR_MASK
, BOOKE
|PPCVLE
, PPCNONE
, {RS
}},
5249 {"mtiac2", XSPR(31,467,313), XSPR_MASK
, BOOKE
|PPCVLE
, PPCNONE
, {RS
}},
5250 {"mtiac3", XSPR(31,467,314), XSPR_MASK
, BOOKE
|PPCVLE
, PPCNONE
, {RS
}},
5251 {"mtiac4", XSPR(31,467,315), XSPR_MASK
, BOOKE
|PPCVLE
, PPCNONE
, {RS
}},
5252 {"mtdac1", XSPR(31,467,316), XSPR_MASK
, BOOKE
|PPCVLE
, PPCNONE
, {RS
}},
5253 {"mtdac2", XSPR(31,467,317), XSPR_MASK
, BOOKE
|PPCVLE
, PPCNONE
, {RS
}},
5254 {"mtdvc1", XSPR(31,467,318), XSPR_MASK
, BOOKE
|PPCVLE
, PPCNONE
, {RS
}},
5255 {"mtdvc2", XSPR(31,467,319), XSPR_MASK
, BOOKE
|PPCVLE
, PPCNONE
, {RS
}},
5256 {"mttsr", XSPR(31,467,336), XSPR_MASK
, BOOKE
|PPCVLE
, PPCNONE
, {RS
}},
5257 {"mttcr", XSPR(31,467,340), XSPR_MASK
, BOOKE
|PPCVLE
, PPCNONE
, {RS
}},
5258 {"mtivor0", XSPR(31,467,400), XSPR_MASK
, BOOKE
|PPCVLE
, PPCNONE
, {RS
}},
5259 {"mtivor1", XSPR(31,467,401), XSPR_MASK
, BOOKE
|PPCVLE
, PPCNONE
, {RS
}},
5260 {"mtivor2", XSPR(31,467,402), XSPR_MASK
, BOOKE
|PPCVLE
, PPCNONE
, {RS
}},
5261 {"mtivor3", XSPR(31,467,403), XSPR_MASK
, BOOKE
|PPCVLE
, PPCNONE
, {RS
}},
5262 {"mtivor4", XSPR(31,467,404), XSPR_MASK
, BOOKE
|PPCVLE
, PPCNONE
, {RS
}},
5263 {"mtivor5", XSPR(31,467,405), XSPR_MASK
, BOOKE
|PPCVLE
, PPCNONE
, {RS
}},
5264 {"mtivor6", XSPR(31,467,406), XSPR_MASK
, BOOKE
|PPCVLE
, PPCNONE
, {RS
}},
5265 {"mtivor7", XSPR(31,467,407), XSPR_MASK
, BOOKE
|PPCVLE
, PPCNONE
, {RS
}},
5266 {"mtivor8", XSPR(31,467,408), XSPR_MASK
, BOOKE
|PPCVLE
, PPCNONE
, {RS
}},
5267 {"mtivor9", XSPR(31,467,409), XSPR_MASK
, BOOKE
|PPCVLE
, PPCNONE
, {RS
}},
5268 {"mtivor10", XSPR(31,467,410), XSPR_MASK
, BOOKE
|PPCVLE
, PPCNONE
, {RS
}},
5269 {"mtivor11", XSPR(31,467,411), XSPR_MASK
, BOOKE
|PPCVLE
, PPCNONE
, {RS
}},
5270 {"mtivor12", XSPR(31,467,412), XSPR_MASK
, BOOKE
|PPCVLE
, PPCNONE
, {RS
}},
5271 {"mtivor13", XSPR(31,467,413), XSPR_MASK
, BOOKE
|PPCVLE
, PPCNONE
, {RS
}},
5272 {"mtivor14", XSPR(31,467,414), XSPR_MASK
, BOOKE
|PPCVLE
, PPCNONE
, {RS
}},
5273 {"mtivor15", XSPR(31,467,415), XSPR_MASK
, BOOKE
|PPCVLE
, PPCNONE
, {RS
}},
5274 {"mtspefscr", XSPR(31,467,512), XSPR_MASK
, PPCSPE
, PPCNONE
, {RS
}},
5275 {"mtbbear", XSPR(31,467,513), XSPR_MASK
, PPCBRLK
, PPCNONE
, {RS
}},
5276 {"mtbbtar", XSPR(31,467,514), XSPR_MASK
, PPCBRLK
, PPCNONE
, {RS
}},
5277 {"mtivor32", XSPR(31,467,528), XSPR_MASK
, PPCSPE
, PPCNONE
, {RS
}},
5278 {"mtibatu", XSPR(31,467,528), XSPRBAT_MASK
, PPC
, TITAN
, {SPRBAT
, RS
}},
5279 {"mtivor33", XSPR(31,467,529), XSPR_MASK
, PPCSPE
, PPCNONE
, {RS
}},
5280 {"mtibatl", XSPR(31,467,529), XSPRBAT_MASK
, PPC
, TITAN
, {SPRBAT
, RS
}},
5281 {"mtivor34", XSPR(31,467,530), XSPR_MASK
, PPCSPE
, PPCNONE
, {RS
}},
5282 {"mtivor35", XSPR(31,467,531), XSPR_MASK
, PPCPMR
, PPCNONE
, {RS
}},
5283 {"mtdbatu", XSPR(31,467,536), XSPRBAT_MASK
, PPC
, TITAN
, {SPRBAT
, RS
}},
5284 {"mtdbatl", XSPR(31,467,537), XSPRBAT_MASK
, PPC
, TITAN
, {SPRBAT
, RS
}},
5285 {"mtmcsrr0", XSPR(31,467,570), XSPR_MASK
, PPCRFMCI
|PPCVLE
, PPCNONE
, {RS
}},
5286 {"mtmcsrr1", XSPR(31,467,571), XSPR_MASK
, PPCRFMCI
|PPCVLE
, PPCNONE
, {RS
}},
5287 {"mtmcsr", XSPR(31,467,572), XSPR_MASK
, PPCRFMCI
, PPCNONE
, {RS
}},
5288 {"mtivndx", XSPR(31,467,880), XSPR_MASK
, TITAN
, PPCNONE
, {RS
}},
5289 {"mtdvndx", XSPR(31,467,881), XSPR_MASK
, TITAN
, PPCNONE
, {RS
}},
5290 {"mtivlim", XSPR(31,467,882), XSPR_MASK
, TITAN
, PPCNONE
, {RS
}},
5291 {"mtdvlim", XSPR(31,467,883), XSPR_MASK
, TITAN
, PPCNONE
, {RS
}},
5292 {"mtclcsr", XSPR(31,467,884), XSPR_MASK
, TITAN
, PPCNONE
, {RS
}},
5293 {"mtccr1", XSPR(31,467,888), XSPR_MASK
, TITAN
, PPCNONE
, {RS
}},
5294 {"mtppr", XSPR(31,467,896), XSPR_MASK
, POWER7
, PPCNONE
, {RS
}},
5295 {"mtppr32", XSPR(31,467,898), XSPR_MASK
, POWER7
, PPCNONE
, {RS
}},
5296 {"mtummcr0", XSPR(31,467,936), XSPR_MASK
, PPC750
, PPCNONE
, {RS
}},
5297 {"mtupmc1", XSPR(31,467,937), XSPR_MASK
, PPC750
, PPCNONE
, {RS
}},
5298 {"mtupmc2", XSPR(31,467,938), XSPR_MASK
, PPC750
, PPCNONE
, {RS
}},
5299 {"mtusia", XSPR(31,467,939), XSPR_MASK
, PPC750
, PPCNONE
, {RS
}},
5300 {"mtummcr1", XSPR(31,467,940), XSPR_MASK
, PPC750
, PPCNONE
, {RS
}},
5301 {"mtupmc3", XSPR(31,467,941), XSPR_MASK
, PPC750
, PPCNONE
, {RS
}},
5302 {"mtupmc4", XSPR(31,467,942), XSPR_MASK
, PPC750
, PPCNONE
, {RS
}},
5303 {"mtzpr", XSPR(31,467,944), XSPR_MASK
, PPC403
, PPCNONE
, {RS
}},
5304 {"mtpid", XSPR(31,467,945), XSPR_MASK
, PPC403
, PPCNONE
, {RS
}},
5305 {"mtrmmucr", XSPR(31,467,946), XSPR_MASK
, TITAN
, PPCNONE
, {RS
}},
5306 {"mtccr0", XSPR(31,467,947), XSPR_MASK
, PPC405
|TITAN
, PPCNONE
, {RS
}},
5307 {"mtiac3", XSPR(31,467,948), XSPR_MASK
, PPC405
, PPCNONE
, {RS
}},
5308 {"mtiac4", XSPR(31,467,949), XSPR_MASK
, PPC405
, PPCNONE
, {RS
}},
5309 {"mtdvc1", XSPR(31,467,950), XSPR_MASK
, PPC405
, PPCNONE
, {RS
}},
5310 {"mtdvc2", XSPR(31,467,951), XSPR_MASK
, PPC405
, PPCNONE
, {RS
}},
5311 {"mtmmcr0", XSPR(31,467,952), XSPR_MASK
, PPC750
, PPCNONE
, {RS
}},
5312 {"mtpmc1", XSPR(31,467,953), XSPR_MASK
, PPC750
, PPCNONE
, {RS
}},
5313 {"mtsgr", XSPR(31,467,953), XSPR_MASK
, PPC403
, PPCNONE
, {RS
}},
5314 {"mtdcwr", XSPR(31,467,954), XSPR_MASK
, PPC403
, PPCNONE
, {RS
}},
5315 {"mtpmc2", XSPR(31,467,954), XSPR_MASK
, PPC750
, PPCNONE
, {RS
}},
5316 {"mtsia", XSPR(31,467,955), XSPR_MASK
, PPC750
, PPCNONE
, {RS
}},
5317 {"mtsler", XSPR(31,467,955), XSPR_MASK
, PPC405
, PPCNONE
, {RS
}},
5318 {"mtmmcr1", XSPR(31,467,956), XSPR_MASK
, PPC750
, PPCNONE
, {RS
}},
5319 {"mtsu0r", XSPR(31,467,956), XSPR_MASK
, PPC405
, PPCNONE
, {RS
}},
5320 {"mtdbcr1", XSPR(31,467,957), XSPR_MASK
, PPC405
, PPCNONE
, {RS
}},
5321 {"mtpmc3", XSPR(31,467,957), XSPR_MASK
, PPC750
, PPCNONE
, {RS
}},
5322 {"mtpmc4", XSPR(31,467,958), XSPR_MASK
, PPC750
, PPCNONE
, {RS
}},
5323 {"mticdbdr", XSPR(31,467,979), XSPR_MASK
, PPC403
, PPCNONE
, {RS
}},
5324 {"mtesr", XSPR(31,467,980), XSPR_MASK
, PPC403
, PPCNONE
, {RS
}},
5325 {"mtdear", XSPR(31,467,981), XSPR_MASK
, PPC403
, PPCNONE
, {RS
}},
5326 {"mtevpr", XSPR(31,467,982), XSPR_MASK
, PPC403
, PPCNONE
, {RS
}},
5327 {"mtcdbcr", XSPR(31,467,983), XSPR_MASK
, PPC403
, PPCNONE
, {RS
}},
5328 {"mttsr", XSPR(31,467,984), XSPR_MASK
, PPC403
, PPCNONE
, {RS
}},
5329 {"mttcr", XSPR(31,467,986), XSPR_MASK
, PPC403
, PPCNONE
, {RS
}},
5330 {"mtpit", XSPR(31,467,987), XSPR_MASK
, PPC403
, PPCNONE
, {RS
}},
5331 {"mttbhi", XSPR(31,467,988), XSPR_MASK
, PPC403
, PPCNONE
, {RS
}},
5332 {"mttblo", XSPR(31,467,989), XSPR_MASK
, PPC403
, PPCNONE
, {RS
}},
5333 {"mtsrr2", XSPR(31,467,990), XSPR_MASK
, PPC403
, PPCNONE
, {RS
}},
5334 {"mtsrr3", XSPR(31,467,991), XSPR_MASK
, PPC403
, PPCNONE
, {RS
}},
5335 {"mtdbsr", XSPR(31,467,1008), XSPR_MASK
, PPC403
, PPCNONE
, {RS
}},
5336 {"mtdbdr", XSPR(31,467,1011), XSPR_MASK
, TITAN
, PPCNONE
, {RS
}},
5337 {"mtdbcr0", XSPR(31,467,1010), XSPR_MASK
, PPC405
, PPCNONE
, {RS
}},
5338 {"mtiac1", XSPR(31,467,1012), XSPR_MASK
, PPC403
, PPCNONE
, {RS
}},
5339 {"mtiac2", XSPR(31,467,1013), XSPR_MASK
, PPC403
, PPCNONE
, {RS
}},
5340 {"mtdac1", XSPR(31,467,1014), XSPR_MASK
, PPC403
, PPCNONE
, {RS
}},
5341 {"mtdac2", XSPR(31,467,1015), XSPR_MASK
, PPC403
, PPCNONE
, {RS
}},
5342 {"mtl2cr", XSPR(31,467,1017), XSPR_MASK
, PPC750
, PPCNONE
, {RS
}},
5343 {"mtdccr", XSPR(31,467,1018), XSPR_MASK
, PPC403
, PPCNONE
, {RS
}},
5344 {"mticcr", XSPR(31,467,1019), XSPR_MASK
, PPC403
, PPCNONE
, {RS
}},
5345 {"mtictc", XSPR(31,467,1019), XSPR_MASK
, PPC750
, PPCNONE
, {RS
}},
5346 {"mtpbl1", XSPR(31,467,1020), XSPR_MASK
, PPC403
, PPCNONE
, {RS
}},
5347 {"mtthrm1", XSPR(31,467,1020), XSPR_MASK
, PPC750
, PPCNONE
, {RS
}},
5348 {"mtpbu1", XSPR(31,467,1021), XSPR_MASK
, PPC403
, PPCNONE
, {RS
}},
5349 {"mtthrm2", XSPR(31,467,1021), XSPR_MASK
, PPC750
, PPCNONE
, {RS
}},
5350 {"mtpbl2", XSPR(31,467,1022), XSPR_MASK
, PPC403
, PPCNONE
, {RS
}},
5351 {"mtthrm3", XSPR(31,467,1022), XSPR_MASK
, PPC750
, PPCNONE
, {RS
}},
5352 {"mtpbu2", XSPR(31,467,1023), XSPR_MASK
, PPC403
, PPCNONE
, {RS
}},
5353 {"mtspr", X(31,467), X_MASK
, COM
|PPCVLE
, PPCNONE
, {SPR
, RS
}},
5355 {"dcbi", X(31,470), XRT_MASK
, PPC
|PPCVLE
, PPCNONE
, {RA0
, RB
}},
5357 {"nand", XRC(31,476,0), X_MASK
, COM
|PPCVLE
, PPCNONE
, {RA
, RS
, RB
}},
5358 {"nand.", XRC(31,476,1), X_MASK
, COM
|PPCVLE
, PPCNONE
, {RA
, RS
, RB
}},
5360 {"dsn", X(31,483), XRT_MASK
, E500MC
|PPCVLE
, PPCNONE
, {RA
, RB
}},
5362 {"dcread", X(31,486), X_MASK
, PPC403
|PPC440
|PPCVLE
, PPCA2
|PPC476
, {RT
, RA0
, RB
}},
5364 {"icbtls", X(31,486), X_MASK
, PPCCHLK
|PPC476
|TITAN
|PPCVLE
, PPCNONE
, {CT
, RA0
, RB
}},
5366 {"stvxl", X(31,487), X_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VS
, RA0
, RB
}},
5368 {"nabs", XO(31,488,0,0), XORB_MASK
, M601
, PPCNONE
, {RT
, RA
}},
5369 {"nabs.", XO(31,488,0,1), XORB_MASK
, M601
, PPCNONE
, {RT
, RA
}},
5371 {"divd", XO(31,489,0,0), XO_MASK
, PPC64
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
5372 {"divd.", XO(31,489,0,1), XO_MASK
, PPC64
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
5374 {"divw", XO(31,491,0,0), XO_MASK
, PPC
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
5375 {"divw.", XO(31,491,0,1), XO_MASK
, PPC
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
5377 {"icbtlse", X(31,494), X_MASK
, PPCCHLK
, E500MC
, {CT
, RA
, RB
}},
5379 {"slbia", X(31,498), 0xff1fffff, POWER6
, PPCNONE
, {IH
}},
5380 {"slbia", X(31,498), 0xffffffff, PPC64
, POWER6
, {0}},
5382 {"cli", X(31,502), XRB_MASK
, POWER
, PPCNONE
, {RT
, RA
}},
5384 {"popcntd", X(31,506), XRB_MASK
, POWER7
|PPCA2
, PPCNONE
, {RA
, RS
}},
5386 {"cmpb", X(31,508), X_MASK
, POWER6
|PPCA2
|PPC476
, PPCNONE
, {RA
, RS
, RB
}},
5388 {"mcrxr", X(31,512), XRARB_MASK
|(3<<21), COM
|PPCVLE
, POWER7
, {BF
}},
5390 {"lbdx", X(31,515), X_MASK
, E500MC
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
5392 {"bblels", X(31,518), X_MASK
, PPCBRLK
, PPCNONE
, {0}},
5394 {"lvlx", X(31,519), X_MASK
, CELL
, PPCNONE
, {VD
, RA0
, RB
}},
5395 {"lbfcmux", APU(31,519,0), APU_MASK
, PPC405
, PPCNONE
, {FCRT
, RA
, RB
}},
5397 {"subfco", XO(31,8,1,0), XO_MASK
, PPCCOM
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
5398 {"sfo", XO(31,8,1,0), XO_MASK
, PWRCOM
, PPCNONE
, {RT
, RA
, RB
}},
5399 {"subco", XO(31,8,1,0), XO_MASK
, PPCCOM
|PPCVLE
, PPCNONE
, {RT
, RB
, RA
}},
5400 {"subfco.", XO(31,8,1,1), XO_MASK
, PPCCOM
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
5401 {"sfo.", XO(31,8,1,1), XO_MASK
, PWRCOM
, PPCNONE
, {RT
, RA
, RB
}},
5402 {"subco.", XO(31,8,1,1), XO_MASK
, PPCCOM
|PPCVLE
, PPCNONE
, {RT
, RB
, RA
}},
5404 {"addco", XO(31,10,1,0), XO_MASK
, PPCCOM
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
5405 {"ao", XO(31,10,1,0), XO_MASK
, PWRCOM
, PPCNONE
, {RT
, RA
, RB
}},
5406 {"addco.", XO(31,10,1,1), XO_MASK
, PPCCOM
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
5407 {"ao.", XO(31,10,1,1), XO_MASK
, PWRCOM
, PPCNONE
, {RT
, RA
, RB
}},
5409 {"lxsspx", X(31,524), XX1_MASK
, PPCVSX2
, PPCNONE
, {XT6
, RA0
, RB
}},
5411 {"clcs", X(31,531), XRB_MASK
, M601
, PPCNONE
, {RT
, RA
}},
5413 {"ldbrx", X(31,532), X_MASK
, CELL
|POWER7
|PPCA2
, PPCNONE
, {RT
, RA0
, RB
}},
5415 {"lswx", X(31,533), X_MASK
, PPCCOM
|PPCVLE
, E500
|E500MC
, {RT
, RAX
, RBX
}},
5416 {"lsx", X(31,533), X_MASK
, PWRCOM
, PPCNONE
, {RT
, RA
, RB
}},
5418 {"lwbrx", X(31,534), X_MASK
, PPCCOM
|PPCVLE
, PPCNONE
, {RT
, RA0
, RB
}},
5419 {"lbrx", X(31,534), X_MASK
, PWRCOM
, PPCNONE
, {RT
, RA
, RB
}},
5421 {"lfsx", X(31,535), X_MASK
, COM
, PPCEFS
, {FRT
, RA0
, RB
}},
5423 {"srw", XRC(31,536,0), X_MASK
, PPCCOM
|PPCVLE
, PPCNONE
, {RA
, RS
, RB
}},
5424 {"sr", XRC(31,536,0), X_MASK
, PWRCOM
, PPCNONE
, {RA
, RS
, RB
}},
5425 {"srw.", XRC(31,536,1), X_MASK
, PPCCOM
|PPCVLE
, PPCNONE
, {RA
, RS
, RB
}},
5426 {"sr.", XRC(31,536,1), X_MASK
, PWRCOM
, PPCNONE
, {RA
, RS
, RB
}},
5428 {"rrib", XRC(31,537,0), X_MASK
, M601
, PPCNONE
, {RA
, RS
, RB
}},
5429 {"rrib.", XRC(31,537,1), X_MASK
, M601
, PPCNONE
, {RA
, RS
, RB
}},
5431 {"srd", XRC(31,539,0), X_MASK
, PPC64
, PPCNONE
, {RA
, RS
, RB
}},
5432 {"srd.", XRC(31,539,1), X_MASK
, PPC64
, PPCNONE
, {RA
, RS
, RB
}},
5434 {"maskir", XRC(31,541,0), X_MASK
, M601
, PPCNONE
, {RA
, RS
, RB
}},
5435 {"maskir.", XRC(31,541,1), X_MASK
, M601
, PPCNONE
, {RA
, RS
, RB
}},
5437 {"lhdx", X(31,547), X_MASK
, E500MC
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
5439 {"lvtrx", X(31,549), X_MASK
, PPCVEC2
, PPCNONE
, {VD
, RA0
, RB
}},
5441 {"bbelr", X(31,550), X_MASK
, PPCBRLK
, PPCNONE
, {0}},
5443 {"lvrx", X(31,551), X_MASK
, CELL
, PPCNONE
, {VD
, RA0
, RB
}},
5444 {"lhfcmux", APU(31,551,0), APU_MASK
, PPC405
, PPCNONE
, {FCRT
, RA
, RB
}},
5446 {"subfo", XO(31,40,1,0), XO_MASK
, PPC
, PPCNONE
, {RT
, RA
, RB
}},
5447 {"subo", XO(31,40,1,0), XO_MASK
, PPC
, PPCNONE
, {RT
, RB
, RA
}},
5448 {"subfo.", XO(31,40,1,1), XO_MASK
, PPC
, PPCNONE
, {RT
, RA
, RB
}},
5449 {"subo.", XO(31,40,1,1), XO_MASK
, PPC
, PPCNONE
, {RT
, RB
, RA
}},
5451 {"tlbsync", X(31,566), 0xffffffff, PPC
|PPCVLE
, PPCNONE
, {0}},
5453 {"lfsux", X(31,567), X_MASK
, COM
, PPCEFS
, {FRT
, RAS
, RB
}},
5455 {"lwdx", X(31,579), X_MASK
, E500MC
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
5457 {"lvtlx", X(31,581), X_MASK
, PPCVEC2
, PPCNONE
, {VD
, RA0
, RB
}},
5459 {"lwfcmux", APU(31,583,0), APU_MASK
, PPC405
, PPCNONE
, {FCRT
, RA
, RB
}},
5461 {"lxsdx", X(31,588), XX1_MASK
, PPCVSX
, PPCNONE
, {XT6
, RA0
, RB
}},
5463 {"mfsr", X(31,595), XRB_MASK
|(1<<20), COM
, NON32
, {RT
, SR
}},
5465 {"lswi", X(31,597), X_MASK
, PPCCOM
|PPCVLE
, E500
|E500MC
, {RT
, RAX
, NBI
}},
5466 {"lsi", X(31,597), X_MASK
, PWRCOM
, PPCNONE
, {RT
, RA0
, NB
}},
5468 {"lwsync", XSYNC(31,598,1), 0xffffffff, PPC
, E500
, {0}},
5469 {"ptesync", XSYNC(31,598,2), 0xffffffff, PPC64
, PPCNONE
, {0}},
5470 {"sync", X(31,598), XSYNCLE_MASK
,E6500
, PPCNONE
, {LS
, ESYNC
}},
5471 {"sync", X(31,598), XSYNC_MASK
, PPCCOM
|PPCVLE
, BOOKE
|PPC476
, {LS
}},
5472 {"msync", X(31,598), 0xffffffff, BOOKE
|PPCA2
|PPC476
, PPCNONE
, {0}},
5473 {"sync", X(31,598), 0xffffffff, BOOKE
|PPC476
, E6500
, {0}},
5474 {"lwsync", X(31,598), 0xffffffff, E500
, PPCNONE
, {0}},
5475 {"dcs", X(31,598), 0xffffffff, PWRCOM
, PPCNONE
, {0}},
5477 {"lfdx", X(31,599), X_MASK
, COM
, PPCEFS
, {FRT
, RA0
, RB
}},
5479 {"mffgpr", XRC(31,607,0), XRA_MASK
, POWER6
, POWER7
, {FRT
, RB
}},
5480 {"lfdepx", X(31,607), X_MASK
, E500MC
|PPCA2
|PPCVLE
, PPCNONE
, {FRT
, RA0
, RB
}},
5482 {"lddx", X(31,611), X_MASK
, E500MC
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
5484 {"lvswx", X(31,613), X_MASK
, PPCVEC2
, PPCNONE
, {VD
, RA0
, RB
}},
5486 {"lqfcmux", APU(31,615,0), APU_MASK
, PPC405
, PPCNONE
, {FCRT
, RA
, RB
}},
5488 {"nego", XO(31,104,1,0), XORB_MASK
, COM
|PPCVLE
, PPCNONE
, {RT
, RA
}},
5489 {"nego.", XO(31,104,1,1), XORB_MASK
, COM
|PPCVLE
, PPCNONE
, {RT
, RA
}},
5491 {"mulo", XO(31,107,1,0), XO_MASK
, M601
, PPCNONE
, {RT
, RA
, RB
}},
5492 {"mulo.", XO(31,107,1,1), XO_MASK
, M601
, PPCNONE
, {RT
, RA
, RB
}},
5494 {"mfsri", X(31,627), X_MASK
, M601
, PPCNONE
, {RT
, RA
, RB
}},
5496 {"dclst", X(31,630), XRB_MASK
, M601
, PPCNONE
, {RS
, RA
}},
5498 {"lfdux", X(31,631), X_MASK
, COM
, PPCEFS
, {FRT
, RAS
, RB
}},
5500 {"stbdx", X(31,643), X_MASK
, E500MC
, PPCNONE
, {RS
, RA
, RB
}},
5502 {"stvlx", X(31,647), X_MASK
, CELL
, PPCNONE
, {VS
, RA0
, RB
}},
5503 {"stbfcmux", APU(31,647,0), APU_MASK
, PPC405
, PPCNONE
, {FCRT
, RA
, RB
}},
5505 {"stxsspx", X(31,652), XX1_MASK
, PPCVSX2
, PPCNONE
, {XS6
, RA0
, RB
}},
5507 {"tbegin.", XRC(31,654,1), XRTLRARB_MASK
,PPCHTM
, PPCNONE
, {HTM_R
}},
5509 {"subfeo", XO(31,136,1,0), XO_MASK
, PPCCOM
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
5510 {"sfeo", XO(31,136,1,0), XO_MASK
, PWRCOM
, PPCNONE
, {RT
, RA
, RB
}},
5511 {"subfeo.", XO(31,136,1,1), XO_MASK
, PPCCOM
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
5512 {"sfeo.", XO(31,136,1,1), XO_MASK
, PWRCOM
, PPCNONE
, {RT
, RA
, RB
}},
5514 {"addeo", XO(31,138,1,0), XO_MASK
, PPCCOM
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
5515 {"aeo", XO(31,138,1,0), XO_MASK
, PWRCOM
, PPCNONE
, {RT
, RA
, RB
}},
5516 {"addeo.", XO(31,138,1,1), XO_MASK
, PPCCOM
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
5517 {"aeo.", XO(31,138,1,1), XO_MASK
, PWRCOM
, PPCNONE
, {RT
, RA
, RB
}},
5519 {"mfsrin", X(31,659), XRA_MASK
, PPC
, NON32
, {RT
, RB
}},
5521 {"stdbrx", X(31,660), X_MASK
, CELL
|POWER7
|PPCA2
, PPCNONE
, {RS
, RA0
, RB
}},
5523 {"stswx", X(31,661), X_MASK
, PPCCOM
|PPCVLE
, E500
|E500MC
, {RS
, RA0
, RB
}},
5524 {"stsx", X(31,661), X_MASK
, PWRCOM
, PPCNONE
, {RS
, RA0
, RB
}},
5526 {"stwbrx", X(31,662), X_MASK
, PPCCOM
|PPCVLE
, PPCNONE
, {RS
, RA0
, RB
}},
5527 {"stbrx", X(31,662), X_MASK
, PWRCOM
, PPCNONE
, {RS
, RA0
, RB
}},
5529 {"stfsx", X(31,663), X_MASK
, COM
, PPCEFS
, {FRS
, RA0
, RB
}},
5531 {"srq", XRC(31,664,0), X_MASK
, M601
, PPCNONE
, {RA
, RS
, RB
}},
5532 {"srq.", XRC(31,664,1), X_MASK
, M601
, PPCNONE
, {RA
, RS
, RB
}},
5534 {"sre", XRC(31,665,0), X_MASK
, M601
, PPCNONE
, {RA
, RS
, RB
}},
5535 {"sre.", XRC(31,665,1), X_MASK
, M601
, PPCNONE
, {RA
, RS
, RB
}},
5537 {"sthdx", X(31,675), X_MASK
, E500MC
, PPCNONE
, {RS
, RA
, RB
}},
5539 {"stvfrx", X(31,677), X_MASK
, PPCVEC2
, PPCNONE
, {VS
, RA0
, RB
}},
5541 {"stvrx", X(31,679), X_MASK
, CELL
, PPCNONE
, {VS
, RA0
, RB
}},
5542 {"sthfcmux", APU(31,679,0), APU_MASK
, PPC405
, PPCNONE
, {FCRT
, RA
, RB
}},
5544 {"tendall.", XRC(31,686,1)|(1<<25), XRTRARB_MASK
, PPCHTM
, PPCNONE
, {0}},
5545 {"tend.", XRC(31,686,1), XRTARARB_MASK
, PPCHTM
, PPCNONE
, {HTM_A
}},
5547 {"stbcx.", XRC(31,694,1), X_MASK
, POWER8
, PPCNONE
, {RS
, RA0
, RB
}},
5549 {"stfsux", X(31,695), X_MASK
, COM
, PPCEFS
, {FRS
, RAS
, RB
}},
5551 {"sriq", XRC(31,696,0), X_MASK
, M601
, PPCNONE
, {RA
, RS
, SH
}},
5552 {"sriq.", XRC(31,696,1), X_MASK
, M601
, PPCNONE
, {RA
, RS
, SH
}},
5554 {"stwdx", X(31,707), X_MASK
, E500MC
, PPCNONE
, {RS
, RA
, RB
}},
5556 {"stvflx", X(31,709), X_MASK
, PPCVEC2
, PPCNONE
, {VS
, RA0
, RB
}},
5558 {"stwfcmux", APU(31,711,0), APU_MASK
, PPC405
, PPCNONE
, {FCRT
, RA
, RB
}},
5560 {"stxsdx", X(31,716), XX1_MASK
, PPCVSX
, PPCNONE
, {XS6
, RA0
, RB
}},
5562 {"tcheck", X(31,718), XRTBFRARB_MASK
, PPCHTM
, PPCNONE
, {BF
}},
5564 {"subfzeo", XO(31,200,1,0), XORB_MASK
, PPCCOM
|PPCVLE
, PPCNONE
, {RT
, RA
}},
5565 {"sfzeo", XO(31,200,1,0), XORB_MASK
, PWRCOM
, PPCNONE
, {RT
, RA
}},
5566 {"subfzeo.", XO(31,200,1,1), XORB_MASK
, PPCCOM
|PPCVLE
, PPCNONE
, {RT
, RA
}},
5567 {"sfzeo.", XO(31,200,1,1), XORB_MASK
, PWRCOM
, PPCNONE
, {RT
, RA
}},
5569 {"addzeo", XO(31,202,1,0), XORB_MASK
, PPCCOM
|PPCVLE
, PPCNONE
, {RT
, RA
}},
5570 {"azeo", XO(31,202,1,0), XORB_MASK
, PWRCOM
, PPCNONE
, {RT
, RA
}},
5571 {"addzeo.", XO(31,202,1,1), XORB_MASK
, PPCCOM
|PPCVLE
, PPCNONE
, {RT
, RA
}},
5572 {"azeo.", XO(31,202,1,1), XORB_MASK
, PWRCOM
, PPCNONE
, {RT
, RA
}},
5574 {"stswi", X(31,725), X_MASK
, PPCCOM
|PPCVLE
, E500
|E500MC
, {RS
, RA0
, NB
}},
5575 {"stsi", X(31,725), X_MASK
, PWRCOM
, PPCNONE
, {RS
, RA0
, NB
}},
5577 {"sthcx.", XRC(31,726,1), X_MASK
, POWER8
, PPCNONE
, {RS
, RA0
, RB
}},
5579 {"stfdx", X(31,727), X_MASK
, COM
, PPCEFS
, {FRS
, RA0
, RB
}},
5581 {"srlq", XRC(31,728,0), X_MASK
, M601
, PPCNONE
, {RA
, RS
, RB
}},
5582 {"srlq.", XRC(31,728,1), X_MASK
, M601
, PPCNONE
, {RA
, RS
, RB
}},
5584 {"sreq", XRC(31,729,0), X_MASK
, M601
, PPCNONE
, {RA
, RS
, RB
}},
5585 {"sreq.", XRC(31,729,1), X_MASK
, M601
, PPCNONE
, {RA
, RS
, RB
}},
5587 {"mftgpr", XRC(31,735,0), XRA_MASK
, POWER6
, POWER7
, {RT
, FRB
}},
5588 {"stfdepx", X(31,735), X_MASK
, E500MC
|PPCA2
|PPCVLE
, PPCNONE
, {FRS
, RA0
, RB
}},
5590 {"stddx", X(31,739), X_MASK
, E500MC
, PPCNONE
, {RS
, RA
, RB
}},
5592 {"stvswx", X(31,741), X_MASK
, PPCVEC2
, PPCNONE
, {VS
, RA0
, RB
}},
5594 {"stqfcmux", APU(31,743,0), APU_MASK
, PPC405
, PPCNONE
, {FCRT
, RA
, RB
}},
5596 {"subfmeo", XO(31,232,1,0), XORB_MASK
, PPCCOM
, PPCNONE
, {RT
, RA
}},
5597 {"sfmeo", XO(31,232,1,0), XORB_MASK
, PWRCOM
, PPCNONE
, {RT
, RA
}},
5598 {"subfmeo.", XO(31,232,1,1), XORB_MASK
, PPCCOM
, PPCNONE
, {RT
, RA
}},
5599 {"sfmeo.", XO(31,232,1,1), XORB_MASK
, PWRCOM
, PPCNONE
, {RT
, RA
}},
5601 {"mulldo", XO(31,233,1,0), XO_MASK
, PPC64
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
5602 {"mulldo.", XO(31,233,1,1), XO_MASK
, PPC64
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
5604 {"addmeo", XO(31,234,1,0), XORB_MASK
, PPCCOM
|PPCVLE
, PPCNONE
, {RT
, RA
}},
5605 {"ameo", XO(31,234,1,0), XORB_MASK
, PWRCOM
, PPCNONE
, {RT
, RA
}},
5606 {"addmeo.", XO(31,234,1,1), XORB_MASK
, PPCCOM
|PPCVLE
, PPCNONE
, {RT
, RA
}},
5607 {"ameo.", XO(31,234,1,1), XORB_MASK
, PWRCOM
, PPCNONE
, {RT
, RA
}},
5609 {"mullwo", XO(31,235,1,0), XO_MASK
, PPCCOM
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
5610 {"mulso", XO(31,235,1,0), XO_MASK
, PWRCOM
, PPCNONE
, {RT
, RA
, RB
}},
5611 {"mullwo.", XO(31,235,1,1), XO_MASK
, PPCCOM
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
5612 {"mulso.", XO(31,235,1,1), XO_MASK
, PWRCOM
, PPCNONE
, {RT
, RA
, RB
}},
5614 {"tsuspend.", XRCL(31,750,0,1), XRTRARB_MASK
,PPCHTM
, PPCNONE
, {0}},
5615 {"tresume.", XRCL(31,750,1,1), XRTRARB_MASK
,PPCHTM
, PPCNONE
, {0}},
5616 {"tsr.", XRC(31,750,1), XRTLRARB_MASK
,PPCHTM
, PPCNONE
, {L
}},
5618 {"dcba", X(31,758), XRT_MASK
, PPC405
|PPC7450
|BOOKE
|PPCA2
|PPC476
|PPCVLE
, PPCNONE
, {RA0
, RB
}},
5619 {"dcbal", XOPL(31,758,1), XRT_MASK
, E500MC
, PPCNONE
, {RA0
, RB
}},
5621 {"stfdux", X(31,759), X_MASK
, COM
, PPCEFS
, {FRS
, RAS
, RB
}},
5623 {"srliq", XRC(31,760,0), X_MASK
, M601
, PPCNONE
, {RA
, RS
, SH
}},
5624 {"srliq.", XRC(31,760,1), X_MASK
, M601
, PPCNONE
, {RA
, RS
, SH
}},
5626 {"lvsm", X(31,773), X_MASK
, PPCVEC2
, PPCNONE
, {VD
, RA0
, RB
}},
5627 {"stvepxl", X(31,775), X_MASK
, PPCVEC2
, PPCNONE
, {VS
, RA0
, RB
}},
5628 {"lvlxl", X(31,775), X_MASK
, CELL
, PPCNONE
, {VD
, RA0
, RB
}},
5629 {"ldfcmux", APU(31,775,0), APU_MASK
, PPC405
, PPCNONE
, {FCRT
, RA
, RB
}},
5631 {"dozo", XO(31,264,1,0), XO_MASK
, M601
, PPCNONE
, {RT
, RA
, RB
}},
5632 {"dozo.", XO(31,264,1,1), XO_MASK
, M601
, PPCNONE
, {RT
, RA
, RB
}},
5634 {"addo", XO(31,266,1,0), XO_MASK
, PPCCOM
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
5635 {"caxo", XO(31,266,1,0), XO_MASK
, PWRCOM
, PPCNONE
, {RT
, RA
, RB
}},
5636 {"addo.", XO(31,266,1,1), XO_MASK
, PPCCOM
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
5637 {"caxo.", XO(31,266,1,1), XO_MASK
, PWRCOM
, PPCNONE
, {RT
, RA
, RB
}},
5639 {"lxvw4x", X(31,780), XX1_MASK
, PPCVSX
, PPCNONE
, {XT6
, RA0
, RB
}},
5641 {"tabortwc.", XRC(31,782,1), X_MASK
, PPCHTM
, PPCNONE
, {TO
, RA
, RB
}},
5643 {"tlbivax", X(31,786), XRT_MASK
, BOOKE
|PPCA2
|PPC476
|PPCVLE
, PPCNONE
, {RA0
, RB
}},
5645 {"lwzcix", X(31,789), X_MASK
, POWER6
, PPCNONE
, {RT
, RA0
, RB
}},
5647 {"lhbrx", X(31,790), X_MASK
, COM
|PPCVLE
, PPCNONE
, {RT
, RA0
, RB
}},
5649 {"lfdpx", X(31,791), X_MASK
, POWER6
, POWER7
, {FRTp
, RA0
, RB
}},
5650 {"lfqx", X(31,791), X_MASK
, POWER2
, PPCNONE
, {FRT
, RA
, RB
}},
5652 {"sraw", XRC(31,792,0), X_MASK
, PPCCOM
|PPCVLE
, PPCNONE
, {RA
, RS
, RB
}},
5653 {"sra", XRC(31,792,0), X_MASK
, PWRCOM
, PPCNONE
, {RA
, RS
, RB
}},
5654 {"sraw.", XRC(31,792,1), X_MASK
, PPCCOM
|PPCVLE
, PPCNONE
, {RA
, RS
, RB
}},
5655 {"sra.", XRC(31,792,1), X_MASK
, PWRCOM
, PPCNONE
, {RA
, RS
, RB
}},
5657 {"srad", XRC(31,794,0), X_MASK
, PPC64
, PPCNONE
, {RA
, RS
, RB
}},
5658 {"srad.", XRC(31,794,1), X_MASK
, PPC64
, PPCNONE
, {RA
, RS
, RB
}},
5660 {"lfddx", X(31,803), X_MASK
, E500MC
|PPCVLE
, PPCNONE
, {FRT
, RA
, RB
}},
5662 {"lvtrxl", X(31,805), X_MASK
, PPCVEC2
, PPCNONE
, {VD
, RA0
, RB
}},
5663 {"stvepx", X(31,807), X_MASK
, PPCVEC2
, PPCNONE
, {VS
, RA0
, RB
}},
5664 {"lvrxl", X(31,807), X_MASK
, CELL
, PPCNONE
, {VD
, RA0
, RB
}},
5666 {"tabortdc.", XRC(31,814,1), X_MASK
, PPCHTM
, PPCNONE
, {TO
, RA
, RB
}},
5668 {"rac", X(31,818), X_MASK
, M601
, PPCNONE
, {RT
, RA
, RB
}},
5670 {"erativax", X(31,819), X_MASK
, PPCA2
, PPCNONE
, {RS
, RA0
, RB
}},
5672 {"lhzcix", X(31,821), X_MASK
, POWER6
, PPCNONE
, {RT
, RA0
, RB
}},
5674 {"dss", XDSS(31,822,0), XDSS_MASK
, PPCVEC
, PPCNONE
, {STRM
}},
5676 {"lfqux", X(31,823), X_MASK
, POWER2
, PPCNONE
, {FRT
, RA
, RB
}},
5678 {"srawi", XRC(31,824,0), X_MASK
, PPCCOM
|PPCVLE
, PPCNONE
, {RA
, RS
, SH
}},
5679 {"srai", XRC(31,824,0), X_MASK
, PWRCOM
, PPCNONE
, {RA
, RS
, SH
}},
5680 {"srawi.", XRC(31,824,1), X_MASK
, PPCCOM
|PPCVLE
, PPCNONE
, {RA
, RS
, SH
}},
5681 {"srai.", XRC(31,824,1), X_MASK
, PWRCOM
, PPCNONE
, {RA
, RS
, SH
}},
5683 {"sradi", XS(31,413,0), XS_MASK
, PPC64
|PPCVLE
, PPCNONE
, {RA
, RS
, SH6
}},
5684 {"sradi.", XS(31,413,1), XS_MASK
, PPC64
|PPCVLE
, PPCNONE
, {RA
, RS
, SH6
}},
5686 {"lvtlxl", X(31,837), X_MASK
, PPCVEC2
, PPCNONE
, {VD
, RA0
, RB
}},
5688 {"divo", XO(31,331,1,0), XO_MASK
, M601
, PPCNONE
, {RT
, RA
, RB
}},
5689 {"divo.", XO(31,331,1,1), XO_MASK
, M601
, PPCNONE
, {RT
, RA
, RB
}},
5691 {"lxvd2x", X(31,844), XX1_MASK
, PPCVSX
, PPCNONE
, {XT6
, RA0
, RB
}},
5692 {"lxvx", X(31,844), XX1_MASK
, PPCVSX
, PPCNONE
, {XT6
, RA0
, RB
}},
5694 {"tabortwci.", XRC(31,846,1), X_MASK
, PPCHTM
, PPCNONE
, {TO
, RA
, HTM_SI
}},
5696 {"tlbsrx.", XRC(31,850,1), XRT_MASK
, PPCA2
, PPCNONE
, {RA0
, RB
}},
5698 {"slbmfev", X(31,851), XRA_MASK
, PPC64
, PPCNONE
, {RT
, RB
}},
5700 {"lbzcix", X(31,853), X_MASK
, POWER6
, PPCNONE
, {RT
, RA0
, RB
}},
5702 {"eieio", X(31,854), 0xffffffff, PPC
, BOOKE
|PPCA2
|PPC476
, {0}},
5703 {"mbar", X(31,854), X_MASK
, BOOKE
|PPCA2
|PPC476
|PPCVLE
, PPCNONE
, {MO
}},
5704 {"eieio", XMBAR(31,854,1),0xffffffff, E500
, PPCNONE
, {0}},
5705 {"eieio", X(31,854), 0xffffffff, PPCA2
|PPC476
, PPCNONE
, {0}},
5707 {"lfiwax", X(31,855), X_MASK
, POWER6
|PPCA2
|PPC476
, PPCNONE
, {FRT
, RA0
, RB
}},
5709 {"lvswxl", X(31,869), X_MASK
, PPCVEC2
, PPCNONE
, {VD
, RA0
, RB
}},
5711 {"abso", XO(31,360,1,0), XORB_MASK
, M601
, PPCNONE
, {RT
, RA
}},
5712 {"abso.", XO(31,360,1,1), XORB_MASK
, M601
, PPCNONE
, {RT
, RA
}},
5714 {"divso", XO(31,363,1,0), XO_MASK
, M601
, PPCNONE
, {RT
, RA
, RB
}},
5715 {"divso.", XO(31,363,1,1), XO_MASK
, M601
, PPCNONE
, {RT
, RA
, RB
}},
5717 {"tabortdci.", XRC(31,878,1), X_MASK
, PPCHTM
, PPCNONE
, {TO
, RA
, HTM_SI
}},
5719 {"ldcix", X(31,885), X_MASK
, POWER6
, PPCNONE
, {RT
, RA0
, RB
}},
5721 {"lfiwzx", X(31,887), X_MASK
, POWER7
|PPCA2
, PPCNONE
, {FRT
, RA0
, RB
}},
5723 {"stvlxl", X(31,903), X_MASK
, CELL
, PPCNONE
, {VS
, RA0
, RB
}},
5724 {"stdfcmux", APU(31,903,0), APU_MASK
, PPC405
, PPCNONE
, {FCRT
, RA
, RB
}},
5726 {"divdeuo", XO(31,393,1,0), XO_MASK
, POWER7
|PPCA2
, PPCNONE
, {RT
, RA
, RB
}},
5727 {"divdeuo.", XO(31,393,1,1), XO_MASK
, POWER7
|PPCA2
, PPCNONE
, {RT
, RA
, RB
}},
5728 {"divweuo", XO(31,395,1,0), XO_MASK
, POWER7
|PPCA2
, PPCNONE
, {RT
, RA
, RB
}},
5729 {"divweuo.", XO(31,395,1,1), XO_MASK
, POWER7
|PPCA2
, PPCNONE
, {RT
, RA
, RB
}},
5731 {"stxvw4x", X(31,908), XX1_MASK
, PPCVSX
, PPCNONE
, {XS6
, RA0
, RB
}},
5733 {"tabort.", XRC(31,910,1), XRTRB_MASK
, PPCHTM
, PPCNONE
, {RA
}},
5735 {"tlbsx", XRC(31,914,0), X_MASK
, PPC403
|BOOKE
|PPCA2
|PPC476
, PPCNONE
, {RTO
, RA0
, RB
}},
5736 {"tlbsx.", XRC(31,914,1), X_MASK
, PPC403
|BOOKE
|PPCA2
|PPC476
, PPCNONE
, {RTO
, RA0
, RB
}},
5738 {"slbmfee", X(31,915), XRA_MASK
, PPC64
, PPCNONE
, {RT
, RB
}},
5740 {"stwcix", X(31,917), X_MASK
, POWER6
, PPCNONE
, {RS
, RA0
, RB
}},
5742 {"sthbrx", X(31,918), X_MASK
, COM
, PPCNONE
, {RS
, RA0
, RB
}},
5744 {"stfdpx", X(31,919), X_MASK
, POWER6
, POWER7
, {FRSp
, RA0
, RB
}},
5745 {"stfqx", X(31,919), X_MASK
, POWER2
, PPCNONE
, {FRS
, RA0
, RB
}},
5747 {"sraq", XRC(31,920,0), X_MASK
, M601
, PPCNONE
, {RA
, RS
, RB
}},
5748 {"sraq.", XRC(31,920,1), X_MASK
, M601
, PPCNONE
, {RA
, RS
, RB
}},
5750 {"srea", XRC(31,921,0), X_MASK
, M601
, PPCNONE
, {RA
, RS
, RB
}},
5751 {"srea.", XRC(31,921,1), X_MASK
, M601
, PPCNONE
, {RA
, RS
, RB
}},
5753 {"extsh", XRC(31,922,0), XRB_MASK
, PPCCOM
|PPCVLE
, PPCNONE
, {RA
, RS
}},
5754 {"exts", XRC(31,922,0), XRB_MASK
, PWRCOM
, PPCNONE
, {RA
, RS
}},
5755 {"extsh.", XRC(31,922,1), XRB_MASK
, PPCCOM
|PPCVLE
, PPCNONE
, {RA
, RS
}},
5756 {"exts.", XRC(31,922,1), XRB_MASK
, PWRCOM
, PPCNONE
, {RA
, RS
}},
5758 {"stfddx", X(31,931), X_MASK
, E500MC
, PPCNONE
, {FRS
, RA
, RB
}},
5760 {"stvfrxl", X(31,933), X_MASK
, PPCVEC2
, PPCNONE
, {VS
, RA0
, RB
}},
5762 {"wclrone", XOPL2(31,934,2),XRT_MASK
, PPCA2
, PPCNONE
, {RA0
, RB
}},
5763 {"wclrall", X(31,934), XRARB_MASK
, PPCA2
, PPCNONE
, {L
}},
5764 {"wclr", X(31,934), X_MASK
, PPCA2
, PPCNONE
, {L
, RA0
, RB
}},
5766 {"stvrxl", X(31,935), X_MASK
, CELL
, PPCNONE
, {VS
, RA0
, RB
}},
5768 {"divdeo", XO(31,425,1,0), XO_MASK
, POWER7
|PPCA2
, PPCNONE
, {RT
, RA
, RB
}},
5769 {"divdeo.", XO(31,425,1,1), XO_MASK
, POWER7
|PPCA2
, PPCNONE
, {RT
, RA
, RB
}},
5770 {"divweo", XO(31,427,1,0), XO_MASK
, POWER7
|PPCA2
, PPCNONE
, {RT
, RA
, RB
}},
5771 {"divweo.", XO(31,427,1,1), XO_MASK
, POWER7
|PPCA2
, PPCNONE
, {RT
, RA
, RB
}},
5773 {"treclaim.", XRC(31,942,1), XRTRB_MASK
, PPCHTM
, PPCNONE
, {RA
}},
5775 {"tlbrehi", XTLB(31,946,0), XTLB_MASK
, PPC403
, PPCA2
, {RT
, RA
}},
5776 {"tlbrelo", XTLB(31,946,1), XTLB_MASK
, PPC403
, PPCA2
, {RT
, RA
}},
5777 {"tlbre", X(31,946), X_MASK
, PPC403
|BOOKE
|PPCA2
|PPC476
, PPCNONE
, {RSO
, RAOPT
, SHO
}},
5779 {"sthcix", X(31,949), X_MASK
, POWER6
, PPCNONE
, {RS
, RA0
, RB
}},
5781 {"icswepx", XRC(31,950,0), X_MASK
, PPCA2
, PPCNONE
, {RS
, RA
, RB
}},
5782 {"icswepx.", XRC(31,950,1), X_MASK
, PPCA2
, PPCNONE
, {RS
, RA
, RB
}},
5784 {"stfqux", X(31,951), X_MASK
, POWER2
, PPCNONE
, {FRS
, RA
, RB
}},
5786 {"sraiq", XRC(31,952,0), X_MASK
, M601
, PPCNONE
, {RA
, RS
, SH
}},
5787 {"sraiq.", XRC(31,952,1), X_MASK
, M601
, PPCNONE
, {RA
, RS
, SH
}},
5789 {"extsb", XRC(31,954,0), XRB_MASK
, PPC
|PPCVLE
, PPCNONE
, {RA
, RS
}},
5790 {"extsb.", XRC(31,954,1), XRB_MASK
, PPC
|PPCVLE
, PPCNONE
, {RA
, RS
}},
5792 {"stvflxl", X(31,965), X_MASK
, PPCVEC2
, PPCNONE
, {VS
, RA0
, RB
}},
5794 {"iccci", X(31,966), XRT_MASK
, PPC403
|PPC440
|TITAN
|PPCA2
, PPCNONE
, {RAOPT
, RBOPT
}},
5795 {"ici", X(31,966), XRARB_MASK
, PPCA2
|PPC476
|PPCVLE
, PPCNONE
, {CT
}},
5797 {"divduo", XO(31,457,1,0), XO_MASK
, PPC64
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
5798 {"divduo.", XO(31,457,1,1), XO_MASK
, PPC64
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
5800 {"divwuo", XO(31,459,1,0), XO_MASK
, PPC
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
5801 {"divwuo.", XO(31,459,1,1), XO_MASK
, PPC
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
5803 {"stxvd2x", X(31,972), XX1_MASK
, PPCVSX
, PPCNONE
, {XS6
, RA0
, RB
}},
5804 {"stxvx", X(31,972), XX1_MASK
, PPCVSX
, PPCNONE
, {XS6
, RA0
, RB
}},
5806 {"tlbld", X(31,978), XRTRA_MASK
, PPC
, PPC403
|BOOKE
|PPCA2
|PPC476
, {RB
}},
5807 {"tlbwehi", XTLB(31,978,0), XTLB_MASK
, PPC403
, PPCNONE
, {RT
, RA
}},
5808 {"tlbwelo", XTLB(31,978,1), XTLB_MASK
, PPC403
, PPCNONE
, {RT
, RA
}},
5809 {"tlbwe", X(31,978), X_MASK
, PPC403
|BOOKE
|PPCA2
|PPC476
, PPCNONE
, {RSO
, RAOPT
, SHO
}},
5811 {"slbfee.", XRC(31,979,1), XRA_MASK
, POWER6
, PPCNONE
, {RT
, RB
}},
5813 {"stbcix", X(31,981), X_MASK
, POWER6
, PPCNONE
, {RS
, RA0
, RB
}},
5815 {"icbi", X(31,982), XRT_MASK
, PPC
|PPCVLE
, PPCNONE
, {RA0
, RB
}},
5817 {"stfiwx", X(31,983), X_MASK
, PPC
, PPCEFS
, {FRS
, RA0
, RB
}},
5819 {"extsw", XRC(31,986,0), XRB_MASK
, PPC64
|PPCVLE
, PPCNONE
, {RA
, RS
}},
5820 {"extsw.", XRC(31,986,1), XRB_MASK
, PPC64
|PPCVLE
, PPCNONE
, {RA
, RS
}},
5822 {"icbiep", XRT(31,991,0), XRT_MASK
, E500MC
|PPCA2
|PPCVLE
, PPCNONE
, {RA0
, RB
}},
5824 {"stvswxl", X(31,997), X_MASK
, PPCVEC2
, PPCNONE
, {VS
, RA0
, RB
}},
5826 {"icread", X(31,998), XRT_MASK
, PPC403
|PPC440
|PPC476
|TITAN
|PPCVLE
, PPCNONE
, {RA0
, RB
}},
5828 {"nabso", XO(31,488,1,0), XORB_MASK
, M601
, PPCNONE
, {RT
, RA
}},
5829 {"nabso.", XO(31,488,1,1), XORB_MASK
, M601
, PPCNONE
, {RT
, RA
}},
5831 {"divdo", XO(31,489,1,0), XO_MASK
, PPC64
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
5832 {"divdo.", XO(31,489,1,1), XO_MASK
, PPC64
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
5834 {"divwo", XO(31,491,1,0), XO_MASK
, PPC
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
5835 {"divwo.", XO(31,491,1,1), XO_MASK
, PPC
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
5837 {"trechkpt.", XRC(31,1006,1), XRTRARB_MASK
,PPCHTM
, PPCNONE
, {0}},
5839 {"tlbli", X(31,1010), XRTRA_MASK
, PPC
, TITAN
, {RB
}},
5841 {"stdcix", X(31,1013), X_MASK
, POWER6
, PPCNONE
, {RS
, RA0
, RB
}},
5843 {"dcbz", X(31,1014), XRT_MASK
, PPC
|PPCVLE
, PPCNONE
, {RA0
, RB
}},
5844 {"dclz", X(31,1014), XRT_MASK
, PPC
, PPCNONE
, {RA0
, RB
}},
5846 {"dcbzep", XRT(31,1023,0), XRT_MASK
, E500MC
|PPCA2
|PPCVLE
, PPCNONE
, {RA0
, RB
}},
5848 {"dcbzl", XOPL(31,1014,1), XRT_MASK
, POWER4
|E500MC
, PPC476
, {RA0
, RB
}},
5850 {"cctpl", 0x7c210b78, 0xffffffff, CELL
, PPCNONE
, {0}},
5851 {"cctpm", 0x7c421378, 0xffffffff, CELL
, PPCNONE
, {0}},
5852 {"cctph", 0x7c631b78, 0xffffffff, CELL
, PPCNONE
, {0}},
5854 {"dstt", XDSS(31,342,1), XDSS_MASK
, PPCVEC
, PPCNONE
, {RA
, RB
, STRM
}},
5855 {"dststt", XDSS(31,374,1), XDSS_MASK
, PPCVEC
, PPCNONE
, {RA
, RB
, STRM
}},
5856 {"dssall", XDSS(31,822,1), XDSS_MASK
, PPCVEC
, PPCNONE
, {0}},
5858 {"db8cyc", 0x7f9ce378, 0xffffffff, CELL
, PPCNONE
, {0}},
5859 {"db10cyc", 0x7fbdeb78, 0xffffffff, CELL
, PPCNONE
, {0}},
5860 {"db12cyc", 0x7fdef378, 0xffffffff, CELL
, PPCNONE
, {0}},
5861 {"db16cyc", 0x7ffffb78, 0xffffffff, CELL
, PPCNONE
, {0}},
5863 {"lwz", OP(32), OP_MASK
, PPCCOM
, PPCNONE
, {RT
, D
, RA0
}},
5864 {"l", OP(32), OP_MASK
, PWRCOM
, PPCNONE
, {RT
, D
, RA0
}},
5866 {"lwzu", OP(33), OP_MASK
, PPCCOM
, PPCNONE
, {RT
, D
, RAL
}},
5867 {"lu", OP(33), OP_MASK
, PWRCOM
, PPCNONE
, {RT
, D
, RA0
}},
5869 {"lbz", OP(34), OP_MASK
, COM
, PPCNONE
, {RT
, D
, RA0
}},
5871 {"lbzu", OP(35), OP_MASK
, COM
, PPCNONE
, {RT
, D
, RAL
}},
5873 {"stw", OP(36), OP_MASK
, PPCCOM
, PPCNONE
, {RS
, D
, RA0
}},
5874 {"st", OP(36), OP_MASK
, PWRCOM
, PPCNONE
, {RS
, D
, RA0
}},
5876 {"stwu", OP(37), OP_MASK
, PPCCOM
, PPCNONE
, {RS
, D
, RAS
}},
5877 {"stu", OP(37), OP_MASK
, PWRCOM
, PPCNONE
, {RS
, D
, RA0
}},
5879 {"stb", OP(38), OP_MASK
, COM
, PPCNONE
, {RS
, D
, RA0
}},
5881 {"stbu", OP(39), OP_MASK
, COM
, PPCNONE
, {RS
, D
, RAS
}},
5883 {"lhz", OP(40), OP_MASK
, COM
, PPCNONE
, {RT
, D
, RA0
}},
5885 {"lhzu", OP(41), OP_MASK
, COM
, PPCNONE
, {RT
, D
, RAL
}},
5887 {"lha", OP(42), OP_MASK
, COM
, PPCNONE
, {RT
, D
, RA0
}},
5889 {"lhau", OP(43), OP_MASK
, COM
, PPCNONE
, {RT
, D
, RAL
}},
5891 {"sth", OP(44), OP_MASK
, COM
, PPCNONE
, {RS
, D
, RA0
}},
5893 {"sthu", OP(45), OP_MASK
, COM
, PPCNONE
, {RS
, D
, RAS
}},
5895 {"lmw", OP(46), OP_MASK
, PPCCOM
, PPCNONE
, {RT
, D
, RAM
}},
5896 {"lm", OP(46), OP_MASK
, PWRCOM
, PPCNONE
, {RT
, D
, RA0
}},
5898 {"stmw", OP(47), OP_MASK
, PPCCOM
, PPCNONE
, {RS
, D
, RA0
}},
5899 {"stm", OP(47), OP_MASK
, PWRCOM
, PPCNONE
, {RS
, D
, RA0
}},
5901 {"lfs", OP(48), OP_MASK
, COM
, PPCEFS
, {FRT
, D
, RA0
}},
5903 {"lfsu", OP(49), OP_MASK
, COM
, PPCEFS
, {FRT
, D
, RAS
}},
5905 {"lfd", OP(50), OP_MASK
, COM
, PPCEFS
, {FRT
, D
, RA0
}},
5907 {"lfdu", OP(51), OP_MASK
, COM
, PPCEFS
, {FRT
, D
, RAS
}},
5909 {"stfs", OP(52), OP_MASK
, COM
, PPCEFS
, {FRS
, D
, RA0
}},
5911 {"stfsu", OP(53), OP_MASK
, COM
, PPCEFS
, {FRS
, D
, RAS
}},
5913 {"stfd", OP(54), OP_MASK
, COM
, PPCEFS
, {FRS
, D
, RA0
}},
5915 {"stfdu", OP(55), OP_MASK
, COM
, PPCEFS
, {FRS
, D
, RAS
}},
5917 {"lq", OP(56), OP_MASK
, POWER4
, PPC476
, {RTQ
, DQ
, RAQ
}},
5918 {"psq_l", OP(56), OP_MASK
, PPCPS
, PPCNONE
, {FRT
,PSD
,RA
,PSW
,PSQ
}},
5919 {"lfq", OP(56), OP_MASK
, POWER2
, PPCNONE
, {FRT
, D
, RA0
}},
5921 {"lfdp", OP(57), OP_MASK
, POWER6
, POWER7
, {FRTp
, DS
, RA0
}},
5922 {"psq_lu", OP(57), OP_MASK
, PPCPS
, PPCNONE
, {FRT
,PSD
,RA
,PSW
,PSQ
}},
5923 {"lfqu", OP(57), OP_MASK
, POWER2
, PPCNONE
, {FRT
, D
, RA0
}},
5925 {"ld", DSO(58,0), DS_MASK
, PPC64
, PPCNONE
, {RT
, DS
, RA0
}},
5926 {"ldu", DSO(58,1), DS_MASK
, PPC64
, PPCNONE
, {RT
, DS
, RAL
}},
5927 {"lwa", DSO(58,2), DS_MASK
, PPC64
, PPCNONE
, {RT
, DS
, RA0
}},
5929 {"dadd", XRC(59,2,0), X_MASK
, POWER6
, PPCNONE
, {FRT
, FRA
, FRB
}},
5930 {"dadd.", XRC(59,2,1), X_MASK
, POWER6
, PPCNONE
, {FRT
, FRA
, FRB
}},
5932 {"dqua", ZRC(59,3,0), Z2_MASK
, POWER6
, PPCNONE
, {FRT
,FRA
,FRB
,RMC
}},
5933 {"dqua.", ZRC(59,3,1), Z2_MASK
, POWER6
, PPCNONE
, {FRT
,FRA
,FRB
,RMC
}},
5935 {"fdivs", A(59,18,0), AFRC_MASK
, PPC
, PPCEFS
, {FRT
, FRA
, FRB
}},
5936 {"fdivs.", A(59,18,1), AFRC_MASK
, PPC
, PPCEFS
, {FRT
, FRA
, FRB
}},
5938 {"fsubs", A(59,20,0), AFRC_MASK
, PPC
, PPCEFS
, {FRT
, FRA
, FRB
}},
5939 {"fsubs.", A(59,20,1), AFRC_MASK
, PPC
, PPCEFS
, {FRT
, FRA
, FRB
}},
5941 {"fadds", A(59,21,0), AFRC_MASK
, PPC
, PPCEFS
, {FRT
, FRA
, FRB
}},
5942 {"fadds.", A(59,21,1), AFRC_MASK
, PPC
, PPCEFS
, {FRT
, FRA
, FRB
}},
5944 {"fsqrts", A(59,22,0), AFRAFRC_MASK
, PPC
, TITAN
, {FRT
, FRB
}},
5945 {"fsqrts.", A(59,22,1), AFRAFRC_MASK
, PPC
, TITAN
, {FRT
, FRB
}},
5947 {"fres", A(59,24,0), AFRAFRC_MASK
, POWER7
, PPCNONE
, {FRT
, FRB
}},
5948 {"fres", A(59,24,0), AFRALFRC_MASK
, PPC
, POWER7
, {FRT
, FRB
, A_L
}},
5949 {"fres.", A(59,24,1), AFRAFRC_MASK
, POWER7
, PPCNONE
, {FRT
, FRB
}},
5950 {"fres.", A(59,24,1), AFRALFRC_MASK
, PPC
, POWER7
, {FRT
, FRB
, A_L
}},
5952 {"fmuls", A(59,25,0), AFRB_MASK
, PPC
, PPCEFS
, {FRT
, FRA
, FRC
}},
5953 {"fmuls.", A(59,25,1), AFRB_MASK
, PPC
, PPCEFS
, {FRT
, FRA
, FRC
}},
5955 {"frsqrtes", A(59,26,0), AFRAFRC_MASK
, POWER7
, PPCNONE
, {FRT
, FRB
}},
5956 {"frsqrtes", A(59,26,0), AFRALFRC_MASK
, POWER5
, POWER7
, {FRT
, FRB
, A_L
}},
5957 {"frsqrtes.", A(59,26,1), AFRAFRC_MASK
, POWER7
, PPCNONE
, {FRT
, FRB
}},
5958 {"frsqrtes.", A(59,26,1), AFRALFRC_MASK
, POWER5
, POWER7
, {FRT
, FRB
, A_L
}},
5960 {"fmsubs", A(59,28,0), A_MASK
, PPC
, PPCEFS
, {FRT
, FRA
, FRC
, FRB
}},
5961 {"fmsubs.", A(59,28,1), A_MASK
, PPC
, PPCEFS
, {FRT
, FRA
, FRC
, FRB
}},
5963 {"fmadds", A(59,29,0), A_MASK
, PPC
, PPCEFS
, {FRT
, FRA
, FRC
, FRB
}},
5964 {"fmadds.", A(59,29,1), A_MASK
, PPC
, PPCEFS
, {FRT
, FRA
, FRC
, FRB
}},
5966 {"fnmsubs", A(59,30,0), A_MASK
, PPC
, PPCEFS
, {FRT
, FRA
, FRC
, FRB
}},
5967 {"fnmsubs.", A(59,30,1), A_MASK
, PPC
, PPCEFS
, {FRT
, FRA
, FRC
, FRB
}},
5969 {"fnmadds", A(59,31,0), A_MASK
, PPC
, PPCEFS
, {FRT
, FRA
, FRC
, FRB
}},
5970 {"fnmadds.", A(59,31,1), A_MASK
, PPC
, PPCEFS
, {FRT
, FRA
, FRC
, FRB
}},
5972 {"dmul", XRC(59,34,0), X_MASK
, POWER6
, PPCNONE
, {FRT
, FRA
, FRB
}},
5973 {"dmul.", XRC(59,34,1), X_MASK
, POWER6
, PPCNONE
, {FRT
, FRA
, FRB
}},
5975 {"drrnd", ZRC(59,35,0), Z2_MASK
, POWER6
, PPCNONE
, {FRT
, FRA
, FRB
, RMC
}},
5976 {"drrnd.", ZRC(59,35,1), Z2_MASK
, POWER6
, PPCNONE
, {FRT
, FRA
, FRB
, RMC
}},
5978 {"dscli", ZRC(59,66,0), Z_MASK
, POWER6
, PPCNONE
, {FRT
, FRA
, SH16
}},
5979 {"dscli.", ZRC(59,66,1), Z_MASK
, POWER6
, PPCNONE
, {FRT
, FRA
, SH16
}},
5981 {"dquai", ZRC(59,67,0), Z2_MASK
, POWER6
, PPCNONE
, {TE
, FRT
,FRB
,RMC
}},
5982 {"dquai.", ZRC(59,67,1), Z2_MASK
, POWER6
, PPCNONE
, {TE
, FRT
,FRB
,RMC
}},
5984 {"dscri", ZRC(59,98,0), Z_MASK
, POWER6
, PPCNONE
, {FRT
, FRA
, SH16
}},
5985 {"dscri.", ZRC(59,98,1), Z_MASK
, POWER6
, PPCNONE
, {FRT
, FRA
, SH16
}},
5987 {"drintx", ZRC(59,99,0), Z2_MASK
, POWER6
, PPCNONE
, {R
, FRT
, FRB
, RMC
}},
5988 {"drintx.", ZRC(59,99,1), Z2_MASK
, POWER6
, PPCNONE
, {R
, FRT
, FRB
, RMC
}},
5990 {"dcmpo", X(59,130), X_MASK
, POWER6
, PPCNONE
, {BF
, FRA
, FRB
}},
5992 {"dtstex", X(59,162), X_MASK
, POWER6
, PPCNONE
, {BF
, FRA
, FRB
}},
5993 {"dtstdc", Z(59,194), Z_MASK
, POWER6
, PPCNONE
, {BF
, FRA
, DCM
}},
5994 {"dtstdg", Z(59,226), Z_MASK
, POWER6
, PPCNONE
, {BF
, FRA
, DGM
}},
5996 {"drintn", ZRC(59,227,0), Z2_MASK
, POWER6
, PPCNONE
, {R
, FRT
, FRB
, RMC
}},
5997 {"drintn.", ZRC(59,227,1), Z2_MASK
, POWER6
, PPCNONE
, {R
, FRT
, FRB
, RMC
}},
5999 {"dctdp", XRC(59,258,0), X_MASK
, POWER6
, PPCNONE
, {FRT
, FRB
}},
6000 {"dctdp.", XRC(59,258,1), X_MASK
, POWER6
, PPCNONE
, {FRT
, FRB
}},
6002 {"dctfix", XRC(59,290,0), X_MASK
, POWER6
, PPCNONE
, {FRT
, FRB
}},
6003 {"dctfix.", XRC(59,290,1), X_MASK
, POWER6
, PPCNONE
, {FRT
, FRB
}},
6005 {"ddedpd", XRC(59,322,0), X_MASK
, POWER6
, PPCNONE
, {SP
, FRT
, FRB
}},
6006 {"ddedpd.", XRC(59,322,1), X_MASK
, POWER6
, PPCNONE
, {SP
, FRT
, FRB
}},
6008 {"dxex", XRC(59,354,0), X_MASK
, POWER6
, PPCNONE
, {FRT
, FRB
}},
6009 {"dxex.", XRC(59,354,1), X_MASK
, POWER6
, PPCNONE
, {FRT
, FRB
}},
6011 {"dsub", XRC(59,514,0), X_MASK
, POWER6
, PPCNONE
, {FRT
, FRA
, FRB
}},
6012 {"dsub.", XRC(59,514,1), X_MASK
, POWER6
, PPCNONE
, {FRT
, FRA
, FRB
}},
6014 {"ddiv", XRC(59,546,0), X_MASK
, POWER6
, PPCNONE
, {FRT
, FRA
, FRB
}},
6015 {"ddiv.", XRC(59,546,1), X_MASK
, POWER6
, PPCNONE
, {FRT
, FRA
, FRB
}},
6017 {"dcmpu", X(59,642), X_MASK
, POWER6
, PPCNONE
, {BF
, FRA
, FRB
}},
6019 {"dtstsf", X(59,674), X_MASK
, POWER6
, PPCNONE
, {BF
, FRA
, FRB
}},
6021 {"drsp", XRC(59,770,0), X_MASK
, POWER6
, PPCNONE
, {FRT
, FRB
}},
6022 {"drsp.", XRC(59,770,1), X_MASK
, POWER6
, PPCNONE
, {FRT
, FRB
}},
6024 {"dcffix", XRC(59,802,0), X_MASK
|FRA_MASK
, POWER7
, PPCNONE
, {FRT
, FRB
}},
6025 {"dcffix.", XRC(59,802,1), X_MASK
|FRA_MASK
, POWER7
, PPCNONE
, {FRT
, FRB
}},
6027 {"denbcd", XRC(59,834,0), X_MASK
, POWER6
, PPCNONE
, {S
, FRT
, FRB
}},
6028 {"denbcd.", XRC(59,834,1), X_MASK
, POWER6
, PPCNONE
, {S
, FRT
, FRB
}},
6030 {"fcfids", XRC(59,846,0), XRA_MASK
, POWER7
|PPCA2
, PPCNONE
, {FRT
, FRB
}},
6031 {"fcfids.", XRC(59,846,1), XRA_MASK
, POWER7
|PPCA2
, PPCNONE
, {FRT
, FRB
}},
6033 {"diex", XRC(59,866,0), X_MASK
, POWER6
, PPCNONE
, {FRT
, FRA
, FRB
}},
6034 {"diex.", XRC(59,866,1), X_MASK
, POWER6
, PPCNONE
, {FRT
, FRA
, FRB
}},
6036 {"fcfidus", XRC(59,974,0), XRA_MASK
, POWER7
|PPCA2
, PPCNONE
, {FRT
, FRB
}},
6037 {"fcfidus.", XRC(59,974,1), XRA_MASK
, POWER7
|PPCA2
, PPCNONE
, {FRT
, FRB
}},
6039 {"xsaddsp", XX3(60,0), XX3_MASK
, PPCVSX2
, PPCNONE
, {XT6
, XA6
, XB6
}},
6040 {"xsmaddasp", XX3(60,1), XX3_MASK
, PPCVSX2
, PPCNONE
, {XT6
, XA6
, XB6
}},
6041 {"xxsldwi", XX3(60,2), XX3SHW_MASK
, PPCVSX
, PPCNONE
, {XT6
, XA6
, XB6
, SHW
}},
6042 {"xxsel", XX4(60,3), XX4_MASK
, PPCVSX
, PPCNONE
, {XT6
, XA6
, XB6
, XC6
}},
6043 {"xssubsp", XX3(60,8), XX3_MASK
, PPCVSX2
, PPCNONE
, {XT6
, XA6
, XB6
}},
6044 {"xsmaddmsp", XX3(60,9), XX3_MASK
, PPCVSX2
, PPCNONE
, {XT6
, XA6
, XB6
}},
6045 {"xxspltd", XX3(60,10), XX3DM_MASK
, PPCVSX
, PPCNONE
, {XT6
, XA6
, XB6S
, DMEX
}},
6046 {"xxmrghd", XX3(60,10), XX3_MASK
, PPCVSX
, PPCNONE
, {XT6
, XA6
, XB6
}},
6047 {"xxswapd", XX3(60,10)|(2<<8), XX3_MASK
, PPCVSX
, PPCNONE
, {XT6
, XA6
, XB6S
}},
6048 {"xxmrgld", XX3(60,10)|(3<<8), XX3_MASK
, PPCVSX
, PPCNONE
, {XT6
, XA6
, XB6
}},
6049 {"xxpermdi", XX3(60,10), XX3DM_MASK
, PPCVSX
, PPCNONE
, {XT6
, XA6
, XB6
, DM
}},
6050 {"xsrsqrtesp", XX2(60,10), XX2_MASK
, PPCVSX2
, PPCNONE
, {XT6
, XB6
}},
6051 {"xssqrtsp", XX2(60,11), XX2_MASK
, PPCVSX2
, PPCNONE
, {XT6
, XB6
}},
6052 {"xsmulsp", XX3(60,16), XX3_MASK
, PPCVSX2
, PPCNONE
, {XT6
, XA6
, XB6
}},
6053 {"xsmsubasp", XX3(60,17), XX3_MASK
, PPCVSX2
, PPCNONE
, {XT6
, XA6
, XB6
}},
6054 {"xxmrghw", XX3(60,18), XX3_MASK
, PPCVSX
, PPCNONE
, {XT6
, XA6
, XB6
}},
6055 {"xsdivsp", XX3(60,24), XX3_MASK
, PPCVSX2
, PPCNONE
, {XT6
, XA6
, XB6
}},
6056 {"xsmsubmsp", XX3(60,25), XX3_MASK
, PPCVSX2
, PPCNONE
, {XT6
, XA6
, XB6
}},
6057 {"xsresp", XX2(60,26), XX2_MASK
, PPCVSX2
, PPCNONE
, {XT6
, XB6
}},
6058 {"xsadddp", XX3(60,32), XX3_MASK
, PPCVSX
, PPCNONE
, {XT6
, XA6
, XB6
}},
6059 {"xsmaddadp", XX3(60,33), XX3_MASK
, PPCVSX
, PPCNONE
, {XT6
, XA6
, XB6
}},
6060 {"xscmpudp", XX3(60,35), XX3BF_MASK
, PPCVSX
, PPCNONE
, {BF
, XA6
, XB6
}},
6061 {"xssubdp", XX3(60,40), XX3_MASK
, PPCVSX
, PPCNONE
, {XT6
, XA6
, XB6
}},
6062 {"xsmaddmdp", XX3(60,41), XX3_MASK
, PPCVSX
, PPCNONE
, {XT6
, XA6
, XB6
}},
6063 {"xscmpodp", XX3(60,43), XX3BF_MASK
, PPCVSX
, PPCNONE
, {BF
, XA6
, XB6
}},
6064 {"xsmuldp", XX3(60,48), XX3_MASK
, PPCVSX
, PPCNONE
, {XT6
, XA6
, XB6
}},
6065 {"xsmsubadp", XX3(60,49), XX3_MASK
, PPCVSX
, PPCNONE
, {XT6
, XA6
, XB6
}},
6066 {"xxmrglw", XX3(60,50), XX3_MASK
, PPCVSX
, PPCNONE
, {XT6
, XA6
, XB6
}},
6067 {"xsdivdp", XX3(60,56), XX3_MASK
, PPCVSX
, PPCNONE
, {XT6
, XA6
, XB6
}},
6068 {"xsmsubmdp", XX3(60,57), XX3_MASK
, PPCVSX
, PPCNONE
, {XT6
, XA6
, XB6
}},
6069 {"xstdivdp", XX3(60,61), XX3BF_MASK
, PPCVSX
, PPCNONE
, {BF
, XA6
, XB6
}},
6070 {"xvaddsp", XX3(60,64), XX3_MASK
, PPCVSX
, PPCNONE
, {XT6
, XA6
, XB6
}},
6071 {"xvmaddasp", XX3(60,65), XX3_MASK
, PPCVSX
, PPCNONE
, {XT6
, XA6
, XB6
}},
6072 {"xvcmpeqsp", XX3RC(60,67,0), XX3_MASK
, PPCVSX
, PPCNONE
, {XT6
, XA6
, XB6
}},
6073 {"xvcmpeqsp.", XX3RC(60,67,1), XX3_MASK
, PPCVSX
, PPCNONE
, {XT6
, XA6
, XB6
}},
6074 {"xvsubsp", XX3(60,72), XX3_MASK
, PPCVSX
, PPCNONE
, {XT6
, XA6
, XB6
}},
6075 {"xscvdpuxws", XX2(60,72), XX2_MASK
, PPCVSX
, PPCNONE
, {XT6
, XB6
}},
6076 {"xvmaddmsp", XX3(60,73), XX3_MASK
, PPCVSX
, PPCNONE
, {XT6
, XA6
, XB6
}},
6077 {"xsrdpi", XX2(60,73), XX2_MASK
, PPCVSX
, PPCNONE
, {XT6
, XB6
}},
6078 {"xsrsqrtedp", XX2(60,74), XX2_MASK
, PPCVSX
, PPCNONE
, {XT6
, XB6
}},
6079 {"xssqrtdp", XX2(60,75), XX2_MASK
, PPCVSX
, PPCNONE
, {XT6
, XB6
}},
6080 {"xvcmpgtsp", XX3RC(60,75,0), XX3_MASK
, PPCVSX
, PPCNONE
, {XT6
, XA6
, XB6
}},
6081 {"xvcmpgtsp.", XX3RC(60,75,1), XX3_MASK
, PPCVSX
, PPCNONE
, {XT6
, XA6
, XB6
}},
6082 {"xvmulsp", XX3(60,80), XX3_MASK
, PPCVSX
, PPCNONE
, {XT6
, XA6
, XB6
}},
6083 {"xvmsubasp", XX3(60,81), XX3_MASK
, PPCVSX
, PPCNONE
, {XT6
, XA6
, XB6
}},
6084 {"xvcmpgesp", XX3RC(60,83,0), XX3_MASK
, PPCVSX
, PPCNONE
, {XT6
, XA6
, XB6
}},
6085 {"xvcmpgesp.", XX3RC(60,83,1), XX3_MASK
, PPCVSX
, PPCNONE
, {XT6
, XA6
, XB6
}},
6086 {"xvdivsp", XX3(60,88), XX3_MASK
, PPCVSX
, PPCNONE
, {XT6
, XA6
, XB6
}},
6087 {"xscvdpsxws", XX2(60,88), XX2_MASK
, PPCVSX
, PPCNONE
, {XT6
, XB6
}},
6088 {"xvmsubmsp", XX3(60,89), XX3_MASK
, PPCVSX
, PPCNONE
, {XT6
, XA6
, XB6
}},
6089 {"xsrdpiz", XX2(60,89), XX2_MASK
, PPCVSX
, PPCNONE
, {XT6
, XB6
}},
6090 {"xsredp", XX2(60,90), XX2_MASK
, PPCVSX
, PPCNONE
, {XT6
, XB6
}},
6091 {"xvtdivsp", XX3(60,93), XX3BF_MASK
, PPCVSX
, PPCNONE
, {BF
, XA6
, XB6
}},
6092 {"xvadddp", XX3(60,96), XX3_MASK
, PPCVSX
, PPCNONE
, {XT6
, XA6
, XB6
}},
6093 {"xvmaddadp", XX3(60,97), XX3_MASK
, PPCVSX
, PPCNONE
, {XT6
, XA6
, XB6
}},
6094 {"xvcmpeqdp", XX3RC(60,99,0), XX3_MASK
, PPCVSX
, PPCNONE
, {XT6
, XA6
, XB6
}},
6095 {"xvcmpeqdp.", XX3RC(60,99,1), XX3_MASK
, PPCVSX
, PPCNONE
, {XT6
, XA6
, XB6
}},
6096 {"xvsubdp", XX3(60,104), XX3_MASK
, PPCVSX
, PPCNONE
, {XT6
, XA6
, XB6
}},
6097 {"xvmaddmdp", XX3(60,105), XX3_MASK
, PPCVSX
, PPCNONE
, {XT6
, XA6
, XB6
}},
6098 {"xsrdpip", XX2(60,105), XX2_MASK
, PPCVSX
, PPCNONE
, {XT6
, XB6
}},
6099 {"xstsqrtdp", XX2(60,106), XX2BF_MASK
, PPCVSX
, PPCNONE
, {BF
, XB6
}},
6100 {"xsrdpic", XX2(60,107), XX2_MASK
, PPCVSX
, PPCNONE
, {XT6
, XB6
}},
6101 {"xvcmpgtdp", XX3RC(60,107,0), XX3_MASK
, PPCVSX
, PPCNONE
, {XT6
, XA6
, XB6
}},
6102 {"xvcmpgtdp.", XX3RC(60,107,1), XX3_MASK
, PPCVSX
, PPCNONE
, {XT6
, XA6
, XB6
}},
6103 {"xvmuldp", XX3(60,112), XX3_MASK
, PPCVSX
, PPCNONE
, {XT6
, XA6
, XB6
}},
6104 {"xvmsubadp", XX3(60,113), XX3_MASK
, PPCVSX
, PPCNONE
, {XT6
, XA6
, XB6
}},
6105 {"xvcmpgedp", XX3RC(60,115,0), XX3_MASK
, PPCVSX
, PPCNONE
, {XT6
, XA6
, XB6
}},
6106 {"xvcmpgedp.", XX3RC(60,115,1), XX3_MASK
, PPCVSX
, PPCNONE
, {XT6
, XA6
, XB6
}},
6107 {"xvdivdp", XX3(60,120), XX3_MASK
, PPCVSX
, PPCNONE
, {XT6
, XA6
, XB6
}},
6108 {"xvmsubmdp", XX3(60,121), XX3_MASK
, PPCVSX
, PPCNONE
, {XT6
, XA6
, XB6
}},
6109 {"xsrdpim", XX2(60,121), XX2_MASK
, PPCVSX
, PPCNONE
, {XT6
, XB6
}},
6110 {"xvtdivdp", XX3(60,125), XX3BF_MASK
, PPCVSX
, PPCNONE
, {BF
, XA6
, XB6
}},
6111 {"xsnmaddasp", XX3(60,129), XX3_MASK
, PPCVSX2
, PPCNONE
, {XT6
, XA6
, XB6
}},
6112 {"xxland", XX3(60,130), XX3_MASK
, PPCVSX
, PPCNONE
, {XT6
, XA6
, XB6
}},
6113 {"xvcvspuxws", XX2(60,136), XX2_MASK
, PPCVSX
, PPCNONE
, {XT6
, XB6
}},
6114 {"xsnmaddmsp", XX3(60,137), XX3_MASK
, PPCVSX2
, PPCNONE
, {XT6
, XA6
, XB6
}},
6115 {"xvrspi", XX2(60,137), XX2_MASK
, PPCVSX
, PPCNONE
, {XT6
, XB6
}},
6116 {"xxlandc", XX3(60,138), XX3_MASK
, PPCVSX
, PPCNONE
, {XT6
, XA6
, XB6
}},
6117 {"xvrsqrtesp", XX2(60,138), XX2_MASK
, PPCVSX
, PPCNONE
, {XT6
, XB6
}},
6118 {"xvsqrtsp", XX2(60,139), XX2_MASK
, PPCVSX
, PPCNONE
, {XT6
, XB6
}},
6119 {"xsnmsubasp", XX3(60,145), XX3_MASK
, PPCVSX2
, PPCNONE
, {XT6
, XA6
, XB6
}},
6120 {"xxlor", XX3(60,146), XX3_MASK
, PPCVSX
, PPCNONE
, {XT6
, XA6
, XB6
}},
6121 {"xvcvspsxws", XX2(60,152), XX2_MASK
, PPCVSX
, PPCNONE
, {XT6
, XB6
}},
6122 {"xsnmsubmsp", XX3(60,153), XX3_MASK
, PPCVSX2
, PPCNONE
, {XT6
, XA6
, XB6
}},
6123 {"xvrspiz", XX2(60,153), XX2_MASK
, PPCVSX
, PPCNONE
, {XT6
, XB6
}},
6124 {"xxlxor", XX3(60,154), XX3_MASK
, PPCVSX
, PPCNONE
, {XT6
, XA6
, XB6
}},
6125 {"xvresp", XX2(60,154), XX2_MASK
, PPCVSX
, PPCNONE
, {XT6
, XB6
}},
6126 {"xsmaxdp", XX3(60,160), XX3_MASK
, PPCVSX
, PPCNONE
, {XT6
, XA6
, XB6
}},
6127 {"xsnmaddadp", XX3(60,161), XX3_MASK
, PPCVSX
, PPCNONE
, {XT6
, XA6
, XB6
}},
6128 {"xxlnor", XX3(60,162), XX3_MASK
, PPCVSX
, PPCNONE
, {XT6
, XA6
, XB6
}},
6129 {"xxspltw", XX2(60,164), XX2UIM_MASK
, PPCVSX
, PPCNONE
, {XT6
, XB6
, UIM
}},
6130 {"xsmindp", XX3(60,168), XX3_MASK
, PPCVSX
, PPCNONE
, {XT6
, XA6
, XB6
}},
6131 {"xvcvuxwsp", XX2(60,168), XX2_MASK
, PPCVSX
, PPCNONE
, {XT6
, XB6
}},
6132 {"xsnmaddmdp", XX3(60,169), XX3_MASK
, PPCVSX
, PPCNONE
, {XT6
, XA6
, XB6
}},
6133 {"xvrspip", XX2(60,169), XX2_MASK
, PPCVSX
, PPCNONE
, {XT6
, XB6
}},
6134 {"xvtsqrtsp", XX2(60,170), XX2BF_MASK
, PPCVSX
, PPCNONE
, {BF
, XB6
}},
6135 {"xxlorc", XX3(60,170), XX3_MASK
, PPCVSX2
, PPCNONE
, {XT6
, XA6
, XB6
}},
6136 {"xvrspic", XX2(60,171), XX2_MASK
, PPCVSX
, PPCNONE
, {XT6
, XB6
}},
6137 {"xscpsgndp", XX3(60,176), XX3_MASK
, PPCVSX
, PPCNONE
, {XT6
, XA6
, XB6
}},
6138 {"xsnmsubadp", XX3(60,177), XX3_MASK
, PPCVSX
, PPCNONE
, {XT6
, XA6
, XB6
}},
6139 {"xxlnand", XX3(60,178), XX3_MASK
, PPCVSX2
, PPCNONE
, {XT6
, XA6
, XB6
}},
6140 {"xvcvsxwsp", XX2(60,184), XX2_MASK
, PPCVSX
, PPCNONE
, {XT6
, XB6
}},
6141 {"xsnmsubmdp", XX3(60,185), XX3_MASK
, PPCVSX
, PPCNONE
, {XT6
, XA6
, XB6
}},
6142 {"xvrspim", XX2(60,185), XX2_MASK
, PPCVSX
, PPCNONE
, {XT6
, XB6
}},
6143 {"xxleqv", XX3(60,186), XX3_MASK
, PPCVSX2
, PPCNONE
, {XT6
, XA6
, XB6
}},
6144 {"xvmaxsp", XX3(60,192), XX3_MASK
, PPCVSX
, PPCNONE
, {XT6
, XA6
, XB6
}},
6145 {"xvnmaddasp", XX3(60,193), XX3_MASK
, PPCVSX
, PPCNONE
, {XT6
, XA6
, XB6
}},
6146 {"xvminsp", XX3(60,200), XX3_MASK
, PPCVSX
, PPCNONE
, {XT6
, XA6
, XB6
}},
6147 {"xvcvdpuxws", XX2(60,200), XX2_MASK
, PPCVSX
, PPCNONE
, {XT6
, XB6
}},
6148 {"xvnmaddmsp", XX3(60,201), XX3_MASK
, PPCVSX
, PPCNONE
, {XT6
, XA6
, XB6
}},
6149 {"xvrdpi", XX2(60,201), XX2_MASK
, PPCVSX
, PPCNONE
, {XT6
, XB6
}},
6150 {"xvrsqrtedp", XX2(60,202), XX2_MASK
, PPCVSX
, PPCNONE
, {XT6
, XB6
}},
6151 {"xvsqrtdp", XX2(60,203), XX2_MASK
, PPCVSX
, PPCNONE
, {XT6
, XB6
}},
6152 {"xvmovsp", XX3(60,208), XX3_MASK
, PPCVSX
, PPCNONE
, {XT6
, XA6
, XB6S
}},
6153 {"xvcpsgnsp", XX3(60,208), XX3_MASK
, PPCVSX
, PPCNONE
, {XT6
, XA6
, XB6
}},
6154 {"xvnmsubasp", XX3(60,209), XX3_MASK
, PPCVSX
, PPCNONE
, {XT6
, XA6
, XB6
}},
6155 {"xvcvdpsxws", XX2(60,216), XX2_MASK
, PPCVSX
, PPCNONE
, {XT6
, XB6
}},
6156 {"xvnmsubmsp", XX3(60,217), XX3_MASK
, PPCVSX
, PPCNONE
, {XT6
, XA6
, XB6
}},
6157 {"xvrdpiz", XX2(60,217), XX2_MASK
, PPCVSX
, PPCNONE
, {XT6
, XB6
}},
6158 {"xvredp", XX2(60,218), XX2_MASK
, PPCVSX
, PPCNONE
, {XT6
, XB6
}},
6159 {"xvmaxdp", XX3(60,224), XX3_MASK
, PPCVSX
, PPCNONE
, {XT6
, XA6
, XB6
}},
6160 {"xvnmaddadp", XX3(60,225), XX3_MASK
, PPCVSX
, PPCNONE
, {XT6
, XA6
, XB6
}},
6161 {"xvmindp", XX3(60,232), XX3_MASK
, PPCVSX
, PPCNONE
, {XT6
, XA6
, XB6
}},
6162 {"xvnmaddmdp", XX3(60,233), XX3_MASK
, PPCVSX
, PPCNONE
, {XT6
, XA6
, XB6
}},
6163 {"xvcvuxwdp", XX2(60,232), XX2_MASK
, PPCVSX
, PPCNONE
, {XT6
, XB6
}},
6164 {"xvrdpip", XX2(60,233), XX2_MASK
, PPCVSX
, PPCNONE
, {XT6
, XB6
}},
6165 {"xvtsqrtdp", XX2(60,234), XX2BF_MASK
, PPCVSX
, PPCNONE
, {BF
, XB6
}},
6166 {"xvrdpic", XX2(60,235), XX2_MASK
, PPCVSX
, PPCNONE
, {XT6
, XB6
}},
6167 {"xvmovdp", XX3(60,240), XX3_MASK
, PPCVSX
, PPCNONE
, {XT6
, XA6
, XB6S
}},
6168 {"xvcpsgndp", XX3(60,240), XX3_MASK
, PPCVSX
, PPCNONE
, {XT6
, XA6
, XB6
}},
6169 {"xvnmsubadp", XX3(60,241), XX3_MASK
, PPCVSX
, PPCNONE
, {XT6
, XA6
, XB6
}},
6170 {"xvcvsxwdp", XX2(60,248), XX2_MASK
, PPCVSX
, PPCNONE
, {XT6
, XB6
}},
6171 {"xvnmsubmdp", XX3(60,249), XX3_MASK
, PPCVSX
, PPCNONE
, {XT6
, XA6
, XB6
}},
6172 {"xvrdpim", XX2(60,249), XX2_MASK
, PPCVSX
, PPCNONE
, {XT6
, XB6
}},
6173 {"xscvdpsp", XX2(60,265), XX2_MASK
, PPCVSX
, PPCNONE
, {XT6
, XB6
}},
6174 {"xscvdpspn", XX2(60,267), XX2_MASK
, PPCVSX2
, PPCNONE
, {XT6
, XB6
}},
6175 {"xsrsp", XX2(60,281), XX2_MASK
, PPCVSX2
, PPCNONE
, {XT6
, XB6
}},
6176 {"xscvuxdsp", XX2(60,296), XX2_MASK
, PPCVSX2
, PPCNONE
, {XT6
, XB6
}},
6177 {"xscvsxdsp", XX2(60,312), XX2_MASK
, PPCVSX2
, PPCNONE
, {XT6
, XB6
}},
6178 {"xscvdpuxds", XX2(60,328), XX2_MASK
, PPCVSX
, PPCNONE
, {XT6
, XB6
}},
6179 {"xscvspdp", XX2(60,329), XX2_MASK
, PPCVSX
, PPCNONE
, {XT6
, XB6
}},
6180 {"xscvspdpn", XX2(60,331), XX2_MASK
, PPCVSX2
, PPCNONE
, {XT6
, XB6
}},
6181 {"xscvdpsxds", XX2(60,344), XX2_MASK
, PPCVSX
, PPCNONE
, {XT6
, XB6
}},
6182 {"xsabsdp", XX2(60,345), XX2_MASK
, PPCVSX
, PPCNONE
, {XT6
, XB6
}},
6183 {"xscvuxddp", XX2(60,360), XX2_MASK
, PPCVSX
, PPCNONE
, {XT6
, XB6
}},
6184 {"xsnabsdp", XX2(60,361), XX2_MASK
, PPCVSX
, PPCNONE
, {XT6
, XB6
}},
6185 {"xscvsxddp", XX2(60,376), XX2_MASK
, PPCVSX
, PPCNONE
, {XT6
, XB6
}},
6186 {"xsnegdp", XX2(60,377), XX2_MASK
, PPCVSX
, PPCNONE
, {XT6
, XB6
}},
6187 {"xvcvspuxds", XX2(60,392), XX2_MASK
, PPCVSX
, PPCNONE
, {XT6
, XB6
}},
6188 {"xvcvdpsp", XX2(60,393), XX2_MASK
, PPCVSX
, PPCNONE
, {XT6
, XB6
}},
6189 {"xvcvspsxds", XX2(60,408), XX2_MASK
, PPCVSX
, PPCNONE
, {XT6
, XB6
}},
6190 {"xvabssp", XX2(60,409), XX2_MASK
, PPCVSX
, PPCNONE
, {XT6
, XB6
}},
6191 {"xvcvuxdsp", XX2(60,424), XX2_MASK
, PPCVSX
, PPCNONE
, {XT6
, XB6
}},
6192 {"xvnabssp", XX2(60,425), XX2_MASK
, PPCVSX
, PPCNONE
, {XT6
, XB6
}},
6193 {"xvcvsxdsp", XX2(60,440), XX2_MASK
, PPCVSX
, PPCNONE
, {XT6
, XB6
}},
6194 {"xvnegsp", XX2(60,441), XX2_MASK
, PPCVSX
, PPCNONE
, {XT6
, XB6
}},
6195 {"xvcvdpuxds", XX2(60,456), XX2_MASK
, PPCVSX
, PPCNONE
, {XT6
, XB6
}},
6196 {"xvcvspdp", XX2(60,457), XX2_MASK
, PPCVSX
, PPCNONE
, {XT6
, XB6
}},
6197 {"xvcvdpsxds", XX2(60,472), XX2_MASK
, PPCVSX
, PPCNONE
, {XT6
, XB6
}},
6198 {"xvabsdp", XX2(60,473), XX2_MASK
, PPCVSX
, PPCNONE
, {XT6
, XB6
}},
6199 {"xvcvuxddp", XX2(60,488), XX2_MASK
, PPCVSX
, PPCNONE
, {XT6
, XB6
}},
6200 {"xvnabsdp", XX2(60,489), XX2_MASK
, PPCVSX
, PPCNONE
, {XT6
, XB6
}},
6201 {"xvcvsxddp", XX2(60,504), XX2_MASK
, PPCVSX
, PPCNONE
, {XT6
, XB6
}},
6202 {"xvnegdp", XX2(60,505), XX2_MASK
, PPCVSX
, PPCNONE
, {XT6
, XB6
}},
6204 {"psq_st", OP(60), OP_MASK
, PPCPS
, PPCNONE
, {FRS
,PSD
,RA
,PSW
,PSQ
}},
6205 {"stfq", OP(60), OP_MASK
, POWER2
, PPCNONE
, {FRS
, D
, RA
}},
6207 {"stfdp", OP(61), OP_MASK
, POWER6
, POWER7
, {FRSp
, DS
, RA0
}},
6208 {"psq_stu", OP(61), OP_MASK
, PPCPS
, PPCNONE
, {FRS
,PSD
,RA
,PSW
,PSQ
}},
6209 {"stfqu", OP(61), OP_MASK
, POWER2
, PPCNONE
, {FRS
, D
, RA
}},
6211 {"std", DSO(62,0), DS_MASK
, PPC64
, PPCNONE
, {RS
, DS
, RA0
}},
6212 {"stdu", DSO(62,1), DS_MASK
, PPC64
, PPCNONE
, {RS
, DS
, RAS
}},
6213 {"stq", DSO(62,2), DS_MASK
, POWER4
, PPC476
, {RSQ
, DS
, RA0
}},
6215 {"fcmpu", X(63,0), X_MASK
|(3<<21), COM
, PPCEFS
, {BF
, FRA
, FRB
}},
6217 {"daddq", XRC(63,2,0), X_MASK
, POWER6
, PPCNONE
, {FRTp
, FRAp
, FRBp
}},
6218 {"daddq.", XRC(63,2,1), X_MASK
, POWER6
, PPCNONE
, {FRTp
, FRAp
, FRBp
}},
6220 {"dquaq", ZRC(63,3,0), Z2_MASK
, POWER6
, PPCNONE
, {FRTp
, FRAp
, FRBp
, RMC
}},
6221 {"dquaq.", ZRC(63,3,1), Z2_MASK
, POWER6
, PPCNONE
, {FRTp
, FRAp
, FRBp
, RMC
}},
6223 {"fcpsgn", XRC(63,8,0), X_MASK
, POWER6
|PPCA2
|PPC476
, PPCNONE
, {FRT
, FRA
, FRB
}},
6224 {"fcpsgn.", XRC(63,8,1), X_MASK
, POWER6
|PPCA2
|PPC476
, PPCNONE
, {FRT
, FRA
, FRB
}},
6226 {"frsp", XRC(63,12,0), XRA_MASK
, COM
, PPCEFS
, {FRT
, FRB
}},
6227 {"frsp.", XRC(63,12,1), XRA_MASK
, COM
, PPCEFS
, {FRT
, FRB
}},
6229 {"fctiw", XRC(63,14,0), XRA_MASK
, PPCCOM
, PPCEFS
, {FRT
, FRB
}},
6230 {"fcir", XRC(63,14,0), XRA_MASK
, PWR2COM
, PPCNONE
, {FRT
, FRB
}},
6231 {"fctiw.", XRC(63,14,1), XRA_MASK
, PPCCOM
, PPCEFS
, {FRT
, FRB
}},
6232 {"fcir.", XRC(63,14,1), XRA_MASK
, PWR2COM
, PPCNONE
, {FRT
, FRB
}},
6234 {"fctiwz", XRC(63,15,0), XRA_MASK
, PPCCOM
, PPCEFS
, {FRT
, FRB
}},
6235 {"fcirz", XRC(63,15,0), XRA_MASK
, PWR2COM
, PPCNONE
, {FRT
, FRB
}},
6236 {"fctiwz.", XRC(63,15,1), XRA_MASK
, PPCCOM
, PPCEFS
, {FRT
, FRB
}},
6237 {"fcirz.", XRC(63,15,1), XRA_MASK
, PWR2COM
, PPCNONE
, {FRT
, FRB
}},
6239 {"fdiv", A(63,18,0), AFRC_MASK
, PPCCOM
, PPCEFS
, {FRT
, FRA
, FRB
}},
6240 {"fd", A(63,18,0), AFRC_MASK
, PWRCOM
, PPCNONE
, {FRT
, FRA
, FRB
}},
6241 {"fdiv.", A(63,18,1), AFRC_MASK
, PPCCOM
, PPCEFS
, {FRT
, FRA
, FRB
}},
6242 {"fd.", A(63,18,1), AFRC_MASK
, PWRCOM
, PPCNONE
, {FRT
, FRA
, FRB
}},
6244 {"fsub", A(63,20,0), AFRC_MASK
, PPCCOM
, PPCEFS
, {FRT
, FRA
, FRB
}},
6245 {"fs", A(63,20,0), AFRC_MASK
, PWRCOM
, PPCNONE
, {FRT
, FRA
, FRB
}},
6246 {"fsub.", A(63,20,1), AFRC_MASK
, PPCCOM
, PPCEFS
, {FRT
, FRA
, FRB
}},
6247 {"fs.", A(63,20,1), AFRC_MASK
, PWRCOM
, PPCNONE
, {FRT
, FRA
, FRB
}},
6249 {"fadd", A(63,21,0), AFRC_MASK
, PPCCOM
, PPCEFS
, {FRT
, FRA
, FRB
}},
6250 {"fa", A(63,21,0), AFRC_MASK
, PWRCOM
, PPCNONE
, {FRT
, FRA
, FRB
}},
6251 {"fadd.", A(63,21,1), AFRC_MASK
, PPCCOM
, PPCEFS
, {FRT
, FRA
, FRB
}},
6252 {"fa.", A(63,21,1), AFRC_MASK
, PWRCOM
, PPCNONE
, {FRT
, FRA
, FRB
}},
6254 {"fsqrt", A(63,22,0), AFRAFRC_MASK
, PPCPWR2
, TITAN
, {FRT
, FRB
}},
6255 {"fsqrt.", A(63,22,1), AFRAFRC_MASK
, PPCPWR2
, TITAN
, {FRT
, FRB
}},
6257 {"fsel", A(63,23,0), A_MASK
, PPC
, PPCEFS
, {FRT
, FRA
, FRC
, FRB
}},
6258 {"fsel.", A(63,23,1), A_MASK
, PPC
, PPCEFS
, {FRT
, FRA
, FRC
, FRB
}},
6260 {"fre", A(63,24,0), AFRAFRC_MASK
, POWER7
, PPCNONE
, {FRT
, FRB
}},
6261 {"fre", A(63,24,0), AFRALFRC_MASK
, POWER5
, POWER7
, {FRT
, FRB
, A_L
}},
6262 {"fre.", A(63,24,1), AFRAFRC_MASK
, POWER7
, PPCNONE
, {FRT
, FRB
}},
6263 {"fre.", A(63,24,1), AFRALFRC_MASK
, POWER5
, POWER7
, {FRT
, FRB
, A_L
}},
6265 {"fmul", A(63,25,0), AFRB_MASK
, PPCCOM
, PPCEFS
, {FRT
, FRA
, FRC
}},
6266 {"fm", A(63,25,0), AFRB_MASK
, PWRCOM
, PPCNONE
, {FRT
, FRA
, FRC
}},
6267 {"fmul.", A(63,25,1), AFRB_MASK
, PPCCOM
, PPCEFS
, {FRT
, FRA
, FRC
}},
6268 {"fm.", A(63,25,1), AFRB_MASK
, PWRCOM
, PPCNONE
, {FRT
, FRA
, FRC
}},
6270 {"frsqrte", A(63,26,0), AFRAFRC_MASK
, POWER7
, PPCNONE
, {FRT
, FRB
}},
6271 {"frsqrte", A(63,26,0), AFRALFRC_MASK
, PPC
, POWER7
, {FRT
, FRB
, A_L
}},
6272 {"frsqrte.", A(63,26,1), AFRAFRC_MASK
, POWER7
, PPCNONE
, {FRT
, FRB
}},
6273 {"frsqrte.", A(63,26,1), AFRALFRC_MASK
, PPC
, POWER7
, {FRT
, FRB
, A_L
}},
6275 {"fmsub", A(63,28,0), A_MASK
, PPCCOM
, PPCEFS
, {FRT
, FRA
, FRC
, FRB
}},
6276 {"fms", A(63,28,0), A_MASK
, PWRCOM
, PPCNONE
, {FRT
, FRA
, FRC
, FRB
}},
6277 {"fmsub.", A(63,28,1), A_MASK
, PPCCOM
, PPCEFS
, {FRT
, FRA
, FRC
, FRB
}},
6278 {"fms.", A(63,28,1), A_MASK
, PWRCOM
, PPCNONE
, {FRT
, FRA
, FRC
, FRB
}},
6280 {"fmadd", A(63,29,0), A_MASK
, PPCCOM
, PPCEFS
, {FRT
, FRA
, FRC
, FRB
}},
6281 {"fma", A(63,29,0), A_MASK
, PWRCOM
, PPCNONE
, {FRT
, FRA
, FRC
, FRB
}},
6282 {"fmadd.", A(63,29,1), A_MASK
, PPCCOM
, PPCEFS
, {FRT
, FRA
, FRC
, FRB
}},
6283 {"fma.", A(63,29,1), A_MASK
, PWRCOM
, PPCNONE
, {FRT
, FRA
, FRC
, FRB
}},
6285 {"fnmsub", A(63,30,0), A_MASK
, PPCCOM
, PPCEFS
, {FRT
, FRA
, FRC
, FRB
}},
6286 {"fnms", A(63,30,0), A_MASK
, PWRCOM
, PPCNONE
, {FRT
, FRA
, FRC
, FRB
}},
6287 {"fnmsub.", A(63,30,1), A_MASK
, PPCCOM
, PPCEFS
, {FRT
, FRA
, FRC
, FRB
}},
6288 {"fnms.", A(63,30,1), A_MASK
, PWRCOM
, PPCNONE
, {FRT
, FRA
, FRC
, FRB
}},
6290 {"fnmadd", A(63,31,0), A_MASK
, PPCCOM
, PPCEFS
, {FRT
, FRA
, FRC
, FRB
}},
6291 {"fnma", A(63,31,0), A_MASK
, PWRCOM
, PPCNONE
, {FRT
, FRA
, FRC
, FRB
}},
6292 {"fnmadd.", A(63,31,1), A_MASK
, PPCCOM
, PPCEFS
, {FRT
, FRA
, FRC
, FRB
}},
6293 {"fnma.", A(63,31,1), A_MASK
, PWRCOM
, PPCNONE
, {FRT
, FRA
, FRC
, FRB
}},
6295 {"fcmpo", X(63,32), X_MASK
|(3<<21), COM
, PPCEFS
, {BF
, FRA
, FRB
}},
6297 {"dmulq", XRC(63,34,0), X_MASK
, POWER6
, PPCNONE
, {FRTp
, FRAp
, FRBp
}},
6298 {"dmulq.", XRC(63,34,1), X_MASK
, POWER6
, PPCNONE
, {FRTp
, FRAp
, FRBp
}},
6300 {"drrndq", ZRC(63,35,0), Z2_MASK
, POWER6
, PPCNONE
, {FRTp
, FRA
, FRBp
, RMC
}},
6301 {"drrndq.", ZRC(63,35,1), Z2_MASK
, POWER6
, PPCNONE
, {FRTp
, FRA
, FRBp
, RMC
}},
6303 {"mtfsb1", XRC(63,38,0), XRARB_MASK
, COM
, PPCNONE
, {BT
}},
6304 {"mtfsb1.", XRC(63,38,1), XRARB_MASK
, COM
, PPCNONE
, {BT
}},
6306 {"fneg", XRC(63,40,0), XRA_MASK
, COM
, PPCEFS
, {FRT
, FRB
}},
6307 {"fneg.", XRC(63,40,1), XRA_MASK
, COM
, PPCEFS
, {FRT
, FRB
}},
6309 {"mcrfs", X(63,64), XRB_MASK
|(3<<21)|(3<<16), COM
, PPCNONE
, {BF
, BFA
}},
6311 {"dscliq", ZRC(63,66,0), Z_MASK
, POWER6
, PPCNONE
, {FRTp
, FRAp
, SH16
}},
6312 {"dscliq.", ZRC(63,66,1), Z_MASK
, POWER6
, PPCNONE
, {FRTp
, FRAp
, SH16
}},
6314 {"dquaiq", ZRC(63,67,0), Z2_MASK
, POWER6
, PPCNONE
, {TE
, FRTp
, FRBp
, RMC
}},
6315 {"dquaiq.", ZRC(63,67,1), Z2_MASK
, POWER6
, PPCNONE
, {TE
, FRTp
, FRBp
, RMC
}},
6317 {"mtfsb0", XRC(63,70,0), XRARB_MASK
, COM
, PPCNONE
, {BT
}},
6318 {"mtfsb0.", XRC(63,70,1), XRARB_MASK
, COM
, PPCNONE
, {BT
}},
6320 {"fmr", XRC(63,72,0), XRA_MASK
, COM
, PPCEFS
, {FRT
, FRB
}},
6321 {"fmr.", XRC(63,72,1), XRA_MASK
, COM
, PPCEFS
, {FRT
, FRB
}},
6323 {"dscriq", ZRC(63,98,0), Z_MASK
, POWER6
, PPCNONE
, {FRTp
, FRAp
, SH16
}},
6324 {"dscriq.", ZRC(63,98,1), Z_MASK
, POWER6
, PPCNONE
, {FRTp
, FRAp
, SH16
}},
6326 {"drintxq", ZRC(63,99,0), Z2_MASK
, POWER6
, PPCNONE
, {R
, FRTp
, FRBp
, RMC
}},
6327 {"drintxq.", ZRC(63,99,1), Z2_MASK
, POWER6
, PPCNONE
, {R
, FRTp
, FRBp
, RMC
}},
6329 {"ftdiv", X(63,128), X_MASK
|(3<<21), POWER7
, PPCNONE
, {BF
, FRA
, FRB
}},
6331 {"dcmpoq", X(63,130), X_MASK
, POWER6
, PPCNONE
, {BF
, FRAp
, FRBp
}},
6333 {"mtfsfi", XRC(63,134,0), XWRA_MASK
|(3<<21)|(1<<11), POWER6
|PPCA2
|PPC476
, PPCNONE
, {BFF
, U
, W
}},
6334 {"mtfsfi", XRC(63,134,0), XRA_MASK
|(3<<21)|(1<<11), COM
, POWER6
|PPCA2
|PPC476
, {BFF
, U
}},
6335 {"mtfsfi.", XRC(63,134,1), XWRA_MASK
|(3<<21)|(1<<11), POWER6
|PPCA2
|PPC476
, PPCNONE
, {BFF
, U
, W
}},
6336 {"mtfsfi.", XRC(63,134,1), XRA_MASK
|(3<<21)|(1<<11), COM
, POWER6
|PPCA2
|PPC476
, {BFF
, U
}},
6338 {"fnabs", XRC(63,136,0), XRA_MASK
, COM
, PPCEFS
, {FRT
, FRB
}},
6339 {"fnabs.", XRC(63,136,1), XRA_MASK
, COM
, PPCEFS
, {FRT
, FRB
}},
6341 {"fctiwu", XRC(63,142,0), XRA_MASK
, POWER7
, PPCNONE
, {FRT
, FRB
}},
6342 {"fctiwu.", XRC(63,142,1), XRA_MASK
, POWER7
, PPCNONE
, {FRT
, FRB
}},
6343 {"fctiwuz", XRC(63,143,0), XRA_MASK
, POWER7
, PPCNONE
, {FRT
, FRB
}},
6344 {"fctiwuz.", XRC(63,143,1), XRA_MASK
, POWER7
, PPCNONE
, {FRT
, FRB
}},
6346 {"ftsqrt", X(63,160), X_MASK
|(3<<21|FRA_MASK
), POWER7
, PPCNONE
, {BF
, FRB
}},
6348 {"dtstexq", X(63,162), X_MASK
, POWER6
, PPCNONE
, {BF
, FRAp
, FRBp
}},
6349 {"dtstdcq", Z(63,194), Z_MASK
, POWER6
, PPCNONE
, {BF
, FRAp
, DCM
}},
6350 {"dtstdgq", Z(63,226), Z_MASK
, POWER6
, PPCNONE
, {BF
, FRAp
, DGM
}},
6352 {"drintnq", ZRC(63,227,0), Z2_MASK
, POWER6
, PPCNONE
, {R
, FRTp
, FRBp
, RMC
}},
6353 {"drintnq.", ZRC(63,227,1), Z2_MASK
, POWER6
, PPCNONE
, {R
, FRTp
, FRBp
, RMC
}},
6355 {"dctqpq", XRC(63,258,0), X_MASK
, POWER6
, PPCNONE
, {FRTp
, FRB
}},
6356 {"dctqpq.", XRC(63,258,1), X_MASK
, POWER6
, PPCNONE
, {FRTp
, FRB
}},
6358 {"fabs", XRC(63,264,0), XRA_MASK
, COM
, PPCEFS
, {FRT
, FRB
}},
6359 {"fabs.", XRC(63,264,1), XRA_MASK
, COM
, PPCEFS
, {FRT
, FRB
}},
6361 {"dctfixq", XRC(63,290,0), X_MASK
, POWER6
, PPCNONE
, {FRT
, FRBp
}},
6362 {"dctfixq.", XRC(63,290,1), X_MASK
, POWER6
, PPCNONE
, {FRT
, FRBp
}},
6364 {"ddedpdq", XRC(63,322,0), X_MASK
, POWER6
, PPCNONE
, {SP
, FRTp
, FRBp
}},
6365 {"ddedpdq.", XRC(63,322,1), X_MASK
, POWER6
, PPCNONE
, {SP
, FRTp
, FRBp
}},
6367 {"dxexq", XRC(63,354,0), X_MASK
, POWER6
, PPCNONE
, {FRT
, FRBp
}},
6368 {"dxexq.", XRC(63,354,1), X_MASK
, POWER6
, PPCNONE
, {FRT
, FRBp
}},
6370 {"frin", XRC(63,392,0), XRA_MASK
, POWER5
, PPCNONE
, {FRT
, FRB
}},
6371 {"frin.", XRC(63,392,1), XRA_MASK
, POWER5
, PPCNONE
, {FRT
, FRB
}},
6372 {"friz", XRC(63,424,0), XRA_MASK
, POWER5
, PPCNONE
, {FRT
, FRB
}},
6373 {"friz.", XRC(63,424,1), XRA_MASK
, POWER5
, PPCNONE
, {FRT
, FRB
}},
6374 {"frip", XRC(63,456,0), XRA_MASK
, POWER5
, PPCNONE
, {FRT
, FRB
}},
6375 {"frip.", XRC(63,456,1), XRA_MASK
, POWER5
, PPCNONE
, {FRT
, FRB
}},
6376 {"frim", XRC(63,488,0), XRA_MASK
, POWER5
, PPCNONE
, {FRT
, FRB
}},
6377 {"frim.", XRC(63,488,1), XRA_MASK
, POWER5
, PPCNONE
, {FRT
, FRB
}},
6379 {"dsubq", XRC(63,514,0), X_MASK
, POWER6
, PPCNONE
, {FRTp
, FRAp
, FRBp
}},
6380 {"dsubq.", XRC(63,514,1), X_MASK
, POWER6
, PPCNONE
, {FRTp
, FRAp
, FRBp
}},
6382 {"ddivq", XRC(63,546,0), X_MASK
, POWER6
, PPCNONE
, {FRTp
, FRAp
, FRBp
}},
6383 {"ddivq.", XRC(63,546,1), X_MASK
, POWER6
, PPCNONE
, {FRTp
, FRAp
, FRBp
}},
6385 {"mffs", XRC(63,583,0), XRARB_MASK
, COM
, PPCEFS
, {FRT
}},
6386 {"mffs.", XRC(63,583,1), XRARB_MASK
, COM
, PPCEFS
, {FRT
}},
6388 {"dcmpuq", X(63,642), X_MASK
, POWER6
, PPCNONE
, {BF
, FRAp
, FRBp
}},
6390 {"dtstsfq", X(63,674), X_MASK
, POWER6
, PPCNONE
, {BF
, FRA
, FRBp
}},
6392 {"mtfsf", XFL(63,711,0), XFL_MASK
, POWER6
|PPCA2
|PPC476
, PPCNONE
, {FLM
, FRB
, XFL_L
, W
}},
6393 {"mtfsf", XFL(63,711,0), XFL_MASK
, COM
, POWER6
|PPCA2
|PPC476
|PPCEFS
, {FLM
, FRB
}},
6394 {"mtfsf.", XFL(63,711,1), XFL_MASK
, POWER6
|PPCA2
|PPC476
, PPCNONE
, {FLM
, FRB
, XFL_L
, W
}},
6395 {"mtfsf.", XFL(63,711,1), XFL_MASK
, COM
, POWER6
|PPCA2
|PPC476
|PPCEFS
, {FLM
, FRB
}},
6397 {"drdpq", XRC(63,770,0), X_MASK
, POWER6
, PPCNONE
, {FRTp
, FRBp
}},
6398 {"drdpq.", XRC(63,770,1), X_MASK
, POWER6
, PPCNONE
, {FRTp
, FRBp
}},
6400 {"dcffixq", XRC(63,802,0), X_MASK
, POWER6
, PPCNONE
, {FRTp
, FRB
}},
6401 {"dcffixq.", XRC(63,802,1), X_MASK
, POWER6
, PPCNONE
, {FRTp
, FRB
}},
6403 {"fctid", XRC(63,814,0), XRA_MASK
, PPC64
, PPCNONE
, {FRT
, FRB
}},
6404 {"fctid", XRC(63,814,0), XRA_MASK
, PPC476
, PPCNONE
, {FRT
, FRB
}},
6405 {"fctid.", XRC(63,814,1), XRA_MASK
, PPC64
, PPCNONE
, {FRT
, FRB
}},
6406 {"fctid.", XRC(63,814,1), XRA_MASK
, PPC476
, PPCNONE
, {FRT
, FRB
}},
6408 {"fctidz", XRC(63,815,0), XRA_MASK
, PPC64
, PPCNONE
, {FRT
, FRB
}},
6409 {"fctidz", XRC(63,815,0), XRA_MASK
, PPC476
, PPCNONE
, {FRT
, FRB
}},
6410 {"fctidz.", XRC(63,815,1), XRA_MASK
, PPC64
, PPCNONE
, {FRT
, FRB
}},
6411 {"fctidz.", XRC(63,815,1), XRA_MASK
, PPC476
, PPCNONE
, {FRT
, FRB
}},
6413 {"denbcdq", XRC(63,834,0), X_MASK
, POWER6
, PPCNONE
, {S
, FRTp
, FRBp
}},
6414 {"denbcdq.", XRC(63,834,1), X_MASK
, POWER6
, PPCNONE
, {S
, FRTp
, FRBp
}},
6416 {"fmrgow", X(63,838), X_MASK
, PPCVSX2
, PPCNONE
, {FRT
, FRA
, FRB
}},
6418 {"fcfid", XRC(63,846,0), XRA_MASK
, PPC64
, PPCNONE
, {FRT
, FRB
}},
6419 {"fcfid", XRC(63,846,0), XRA_MASK
, PPC476
, PPCNONE
, {FRT
, FRB
}},
6420 {"fcfid.", XRC(63,846,1), XRA_MASK
, PPC64
, PPCNONE
, {FRT
, FRB
}},
6421 {"fcfid.", XRC(63,846,1), XRA_MASK
, PPC476
, PPCNONE
, {FRT
, FRB
}},
6423 {"diexq", XRC(63,866,0), X_MASK
, POWER6
, PPCNONE
, {FRTp
, FRA
, FRBp
}},
6424 {"diexq.", XRC(63,866,1), X_MASK
, POWER6
, PPCNONE
, {FRTp
, FRA
, FRBp
}},
6426 {"fctidu", XRC(63,942,0), XRA_MASK
, POWER7
|PPCA2
, PPCNONE
, {FRT
, FRB
}},
6427 {"fctidu.", XRC(63,942,1), XRA_MASK
, POWER7
|PPCA2
, PPCNONE
, {FRT
, FRB
}},
6429 {"fctiduz", XRC(63,943,0), XRA_MASK
, POWER7
|PPCA2
, PPCNONE
, {FRT
, FRB
}},
6430 {"fctiduz.", XRC(63,943,1), XRA_MASK
, POWER7
|PPCA2
, PPCNONE
, {FRT
, FRB
}},
6432 {"fmrgew", X(63,966), X_MASK
, PPCVSX2
, PPCNONE
, {FRT
, FRA
, FRB
}},
6434 {"fcfidu", XRC(63,974,0), XRA_MASK
, POWER7
|PPCA2
, PPCNONE
, {FRT
, FRB
}},
6435 {"fcfidu.", XRC(63,974,1), XRA_MASK
, POWER7
|PPCA2
, PPCNONE
, {FRT
, FRB
}},
6438 const int powerpc_num_opcodes
=
6439 sizeof (powerpc_opcodes
) / sizeof (powerpc_opcodes
[0]);
6441 /* The VLE opcode table.
6443 The format of this opcode table is the same as the main opcode table. */
6445 const struct powerpc_opcode vle_opcodes
[] = {
6447 {"se_illegal", C(0), C_MASK
, PPCVLE
, PPCNONE
, {}},
6448 {"se_isync", C(1), C_MASK
, PPCVLE
, PPCNONE
, {}},
6449 {"se_sc", C(2), C_MASK
, PPCVLE
, PPCNONE
, {}},
6450 {"se_blr", C_LK(2,0), C_LK_MASK
, PPCVLE
, PPCNONE
, {}},
6451 {"se_blrl", C_LK(2,1), C_LK_MASK
, PPCVLE
, PPCNONE
, {}},
6452 {"se_bctr", C_LK(3,0), C_LK_MASK
, PPCVLE
, PPCNONE
, {}},
6453 {"se_bctrl", C_LK(3,1), C_LK_MASK
, PPCVLE
, PPCNONE
, {}},
6454 {"se_rfi", C(8), C_MASK
, PPCVLE
, PPCNONE
, {}},
6455 {"se_rfci", C(9), C_MASK
, PPCVLE
, PPCNONE
, {}},
6456 {"se_rfdi", C(10), C_MASK
, PPCVLE
, PPCNONE
, {}},
6457 {"se_rfmci", C(11), C_MASK
, PPCVLE
, PPCNONE
, {}},
6458 {"se_not", SE_R(0,2), SE_R_MASK
, PPCVLE
, PPCNONE
, {RX
}},
6459 {"se_neg", SE_R(0,3), SE_R_MASK
, PPCVLE
, PPCNONE
, {RX
}},
6460 {"se_mflr", SE_R(0,8), SE_R_MASK
, PPCVLE
, PPCNONE
, {RX
}},
6461 {"se_mtlr", SE_R(0,9), SE_R_MASK
, PPCVLE
, PPCNONE
, {RX
}},
6462 {"se_mfctr", SE_R(0,10), SE_R_MASK
, PPCVLE
, PPCNONE
, {RX
}},
6463 {"se_mtctr", SE_R(0,11), SE_R_MASK
, PPCVLE
, PPCNONE
, {RX
}},
6464 {"se_extzb", SE_R(0,12), SE_R_MASK
, PPCVLE
, PPCNONE
, {RX
}},
6465 {"se_extsb", SE_R(0,13), SE_R_MASK
, PPCVLE
, PPCNONE
, {RX
}},
6466 {"se_extzh", SE_R(0,14), SE_R_MASK
, PPCVLE
, PPCNONE
, {RX
}},
6467 {"se_extsh", SE_R(0,15), SE_R_MASK
, PPCVLE
, PPCNONE
, {RX
}},
6468 {"se_mr", SE_RR(0,1), SE_RR_MASK
, PPCVLE
, PPCNONE
, {RX
, RY
}},
6469 {"se_mtar", SE_RR(0,2), SE_RR_MASK
, PPCVLE
, PPCNONE
, {ARX
, RY
}},
6470 {"se_mfar", SE_RR(0,3), SE_RR_MASK
, PPCVLE
, PPCNONE
, {RX
, ARY
}},
6471 {"se_add", SE_RR(1,0), SE_RR_MASK
, PPCVLE
, PPCNONE
, {RX
, RY
}},
6472 {"se_mullw", SE_RR(1,1), SE_RR_MASK
, PPCVLE
, PPCNONE
, {RX
, RY
}},
6473 {"se_sub", SE_RR(1,2), SE_RR_MASK
, PPCVLE
, PPCNONE
, {RX
, RY
}},
6474 {"se_subf", SE_RR(1,3), SE_RR_MASK
, PPCVLE
, PPCNONE
, {RX
, RY
}},
6475 {"se_cmp", SE_RR(3,0), SE_RR_MASK
, PPCVLE
, PPCNONE
, {RX
, RY
}},
6476 {"se_cmpl", SE_RR(3,1), SE_RR_MASK
, PPCVLE
, PPCNONE
, {RX
, RY
}},
6477 {"se_cmph", SE_RR(3,2), SE_RR_MASK
, PPCVLE
, PPCNONE
, {RX
, RY
}},
6478 {"se_cmphl", SE_RR(3,3), SE_RR_MASK
, PPCVLE
, PPCNONE
, {RX
, RY
}},
6480 {"e_cmpi", SCI8BF(6,0,21), SCI8BF_MASK
, PPCVLE
, PPCNONE
, {CRD32
, RA
, SCLSCI8
}},
6481 {"e_cmpli", SCI8BF(6,1,21), SCI8BF_MASK
, PPCVLE
, PPCNONE
, {CRD32
, RA
, SCLSCI8
}},
6482 {"e_addi", SCI8(6,16), SCI8_MASK
, PPCVLE
, PPCNONE
, {RT
, RA
, SCLSCI8
}},
6483 {"e_subi", SCI8(6,16), SCI8_MASK
, PPCVLE
, PPCNONE
, {RT
, RA
, SCLSCI8N
}},
6484 {"e_addi.", SCI8(6,17), SCI8_MASK
, PPCVLE
, PPCNONE
, {RT
, RA
, SCLSCI8
}},
6485 {"e_addic", SCI8(6,18), SCI8_MASK
, PPCVLE
, PPCNONE
, {RT
, RA
, SCLSCI8
}},
6486 {"e_subic", SCI8(6,18), SCI8_MASK
, PPCVLE
, PPCNONE
, {RT
, RA
, SCLSCI8N
}},
6487 {"e_addic.", SCI8(6,19), SCI8_MASK
, PPCVLE
, PPCNONE
, {RT
, RA
, SCLSCI8
}},
6488 {"e_subic.", SCI8(6,19), SCI8_MASK
, PPCVLE
, PPCNONE
, {RT
, RA
, SCLSCI8N
}},
6489 {"e_mulli", SCI8(6,20), SCI8_MASK
, PPCVLE
, PPCNONE
, {RT
, RA
, SCLSCI8
}},
6490 {"e_subfic", SCI8(6,22), SCI8_MASK
, PPCVLE
, PPCNONE
, {RT
, RA
, SCLSCI8
}},
6491 {"e_subfic.", SCI8(6,23), SCI8_MASK
, PPCVLE
, PPCNONE
, {RT
, RA
, SCLSCI8
}},
6492 {"e_andi", SCI8(6,24), SCI8_MASK
, PPCVLE
, PPCNONE
, {RA
, RS
, SCLSCI8
}},
6493 {"e_andi.", SCI8(6,25), SCI8_MASK
, PPCVLE
, PPCNONE
, {RA
, RS
, SCLSCI8
}},
6494 {"e_nop", SCI8(6,26), 0xffffffff, PPCVLE
, PPCNONE
, {0}},
6495 {"e_ori", SCI8(6,26), SCI8_MASK
, PPCVLE
, PPCNONE
, {RA
, RS
, SCLSCI8
}},
6496 {"e_ori.", SCI8(6,27), SCI8_MASK
, PPCVLE
, PPCNONE
, {RA
, RS
, SCLSCI8
}},
6497 {"e_xori", SCI8(6,28), SCI8_MASK
, PPCVLE
, PPCNONE
, {RA
, RS
, SCLSCI8
}},
6498 {"e_xori.", SCI8(6,29), SCI8_MASK
, PPCVLE
, PPCNONE
, {RA
, RS
, SCLSCI8
}},
6499 {"e_lbzu", OPVUP(6,0), OPVUP_MASK
, PPCVLE
, PPCNONE
, {RT
, D8
, RA0
}},
6500 {"e_lhau", OPVUP(6,3), OPVUP_MASK
, PPCVLE
, PPCNONE
, {RT
, D8
, RA0
}},
6501 {"e_lhzu", OPVUP(6,1), OPVUP_MASK
, PPCVLE
, PPCNONE
, {RT
, D8
, RA0
}},
6502 {"e_lmw", OPVUP(6,8), OPVUP_MASK
, PPCVLE
, PPCNONE
, {RT
, D8
, RA0
}},
6503 {"e_lwzu", OPVUP(6,2), OPVUP_MASK
, PPCVLE
, PPCNONE
, {RT
, D8
, RA0
}},
6504 {"e_stbu", OPVUP(6,4), OPVUP_MASK
, PPCVLE
, PPCNONE
, {RT
, D8
, RA0
}},
6505 {"e_sthu", OPVUP(6,5), OPVUP_MASK
, PPCVLE
, PPCNONE
, {RT
, D8
, RA0
}},
6506 {"e_stwu", OPVUP(6,6), OPVUP_MASK
, PPCVLE
, PPCNONE
, {RT
, D8
, RA0
}},
6507 {"e_stmw", OPVUP(6,9), OPVUP_MASK
, PPCVLE
, PPCNONE
, {RT
, D8
, RA0
}},
6508 {"e_add16i", OP(7), OP_MASK
, PPCVLE
, PPCNONE
, {RT
, RA
, SI
}},
6509 {"e_la", OP(7), OP_MASK
, PPCVLE
, PPCNONE
, {RT
, D
, RA0
}},
6510 {"e_sub16i", OP(7), OP_MASK
, PPCVLE
, PPCNONE
, {RT
, RA
, NSI
}},
6512 {"se_addi", SE_IM5(8,0), SE_IM5_MASK
, PPCVLE
, PPCNONE
, {RX
, OIMM5
}},
6513 {"se_cmpli", SE_IM5(8,1), SE_IM5_MASK
, PPCVLE
, PPCNONE
, {RX
, OIMM5
}},
6514 {"se_subi", SE_IM5(9,0), SE_IM5_MASK
, PPCVLE
, PPCNONE
, {RX
, OIMM5
}},
6515 {"se_subi.", SE_IM5(9,1), SE_IM5_MASK
, PPCVLE
, PPCNONE
, {RX
, OIMM5
}},
6516 {"se_cmpi", SE_IM5(10,1), SE_IM5_MASK
, PPCVLE
, PPCNONE
, {RX
, UI5
}},
6517 {"se_bmaski", SE_IM5(11,0), SE_IM5_MASK
, PPCVLE
, PPCNONE
, {RX
, UI5
}},
6518 {"se_andi", SE_IM5(11,1), SE_IM5_MASK
, PPCVLE
, PPCNONE
, {RX
, UI5
}},
6520 {"e_lbz", OP(12), OP_MASK
, PPCVLE
, PPCNONE
, {RT
, D
, RA0
}},
6521 {"e_stb", OP(13), OP_MASK
, PPCVLE
, PPCNONE
, {RT
, D
, RA0
}},
6522 {"e_lha", OP(14), OP_MASK
, PPCVLE
, PPCNONE
, {RT
, D
, RA0
}},
6524 {"se_srw", SE_RR(16,0), SE_RR_MASK
, PPCVLE
, PPCNONE
, {RX
, RY
}},
6525 {"se_sraw", SE_RR(16,1), SE_RR_MASK
, PPCVLE
, PPCNONE
, {RX
, RY
}},
6526 {"se_slw", SE_RR(16,2), SE_RR_MASK
, PPCVLE
, PPCNONE
, {RX
, RY
}},
6527 {"se_nop", SE_RR(17,0), 0xffff, PPCVLE
, PPCNONE
, {0}},
6528 {"se_or", SE_RR(17,0), SE_RR_MASK
, PPCVLE
, PPCNONE
, {RX
, RY
}},
6529 {"se_andc", SE_RR(17,1), SE_RR_MASK
, PPCVLE
, PPCNONE
, {RX
, RY
}},
6530 {"se_and", SE_RR(17,2), SE_RR_MASK
, PPCVLE
, PPCNONE
, {RX
, RY
}},
6531 {"se_and.", SE_RR(17,3), SE_RR_MASK
, PPCVLE
, PPCNONE
, {RX
, RY
}},
6532 {"se_li", IM7(9), IM7_MASK
, PPCVLE
, PPCNONE
, {RX
, UI7
}},
6534 {"e_lwz", OP(20), OP_MASK
, PPCVLE
, PPCNONE
, {RT
, D
, RA0
}},
6535 {"e_stw", OP(21), OP_MASK
, PPCVLE
, PPCNONE
, {RT
, D
, RA0
}},
6536 {"e_lhz", OP(22), OP_MASK
, PPCVLE
, PPCNONE
, {RT
, D
, RA0
}},
6537 {"e_sth", OP(23), OP_MASK
, PPCVLE
, PPCNONE
, {RT
, D
, RA0
}},
6539 {"se_bclri", SE_IM5(24,0), SE_IM5_MASK
, PPCVLE
, PPCNONE
, {RX
, UI5
}},
6540 {"se_bgeni", SE_IM5(24,1), SE_IM5_MASK
, PPCVLE
, PPCNONE
, {RX
, UI5
}},
6541 {"se_bseti", SE_IM5(25,0), SE_IM5_MASK
, PPCVLE
, PPCNONE
, {RX
, UI5
}},
6542 {"se_btsti", SE_IM5(25,1), SE_IM5_MASK
, PPCVLE
, PPCNONE
, {RX
, UI5
}},
6543 {"se_srwi", SE_IM5(26,0), SE_IM5_MASK
, PPCVLE
, PPCNONE
, {RX
, UI5
}},
6544 {"se_srawi", SE_IM5(26,1), SE_IM5_MASK
, PPCVLE
, PPCNONE
, {RX
, UI5
}},
6545 {"se_slwi", SE_IM5(27,0), SE_IM5_MASK
, PPCVLE
, PPCNONE
, {RX
, UI5
}},
6547 {"e_lis", I16L(28,28), I16L_MASK
, PPCVLE
, PPCNONE
, {RD
, VLEUIMML
}},
6548 {"e_and2is.", I16L(28,29), I16L_MASK
, PPCVLE
, PPCNONE
, {RD
, VLEUIMML
}},
6549 {"e_or2is", I16L(28,26), I16L_MASK
, PPCVLE
, PPCNONE
, {RD
, VLEUIMML
}},
6550 {"e_and2i.", I16L(28,25), I16L_MASK
, PPCVLE
, PPCNONE
, {RD
, VLEUIMML
}},
6551 {"e_or2i", I16L(28,24), I16L_MASK
, PPCVLE
, PPCNONE
, {RD
, VLEUIMML
}},
6552 {"e_cmphl16i", IA16(28,23), IA16_MASK
, PPCVLE
, PPCNONE
, {RA
, VLEUIMM
}},
6553 {"e_cmph16i", IA16(28,22), IA16_MASK
, PPCVLE
, PPCNONE
, {RA
, VLESIMM
}},
6554 {"e_cmpl16i", I16A(28,21), I16A_MASK
, PPCVLE
, PPCNONE
, {RA
, VLEUIMM
}},
6555 {"e_cmplwi", I16A(28,21), I16A_MASK
, PPCVLE
, PPCNONE
, {RA
, VLESIMM
}},
6556 {"e_mull2i", I16A(28,20), I16A_MASK
, PPCVLE
, PPCNONE
, {RA
, VLESIMM
}},
6557 {"e_cmp16i", IA16(28,19), IA16_MASK
, PPCVLE
, PPCNONE
, {RA
, VLESIMM
}},
6558 {"e_cmpwi", IA16(28,19), IA16_MASK
, PPCVLE
, PPCNONE
, {RA
, VLESIMM
}},
6559 {"e_sub2is", I16A(28,18), I16A_MASK
, PPCVLE
, PPCNONE
, {RA
, VLENSIMM
}},
6560 {"e_add2is", I16A(28,18), I16A_MASK
, PPCVLE
, PPCNONE
, {RA
, VLESIMM
}},
6561 {"e_sub2i.", I16A(28,17), I16A_MASK
, PPCVLE
, PPCNONE
, {RA
, VLENSIMM
}},
6562 {"e_add2i.", I16A(28,17), I16A_MASK
, PPCVLE
, PPCNONE
, {RA
, VLESIMM
}},
6563 {"e_li", LI20(28,0), LI20_MASK
, PPCVLE
, PPCNONE
, {RT
, IMM20
}},
6564 {"e_rlwimi", M(29,0), M_MASK
, PPCVLE
, PPCNONE
, {RA
, RS
, SH
, MB
, ME
}},
6565 {"e_rlwinm", M(29,1), M_MASK
, PPCVLE
, PPCNONE
, {RA
, RT
, SH
, MBE
, ME
}},
6566 {"e_b", BD24(30,0,0), BD24_MASK
, PPCVLE
, PPCNONE
, {B24
}},
6567 {"e_bl", BD24(30,0,1), BD24_MASK
, PPCVLE
, PPCNONE
, {B24
}},
6568 {"e_bdnz", EBD15(30,8,BO32DNZ
,0), EBD15_MASK
, PPCVLE
, PPCNONE
, {B15
}},
6569 {"e_bdnzl", EBD15(30,8,BO32DNZ
,1), EBD15_MASK
, PPCVLE
, PPCNONE
, {B15
}},
6570 {"e_bdz", EBD15(30,8,BO32DZ
,0), EBD15_MASK
, PPCVLE
, PPCNONE
, {B15
}},
6571 {"e_bdzl", EBD15(30,8,BO32DZ
,1), EBD15_MASK
, PPCVLE
, PPCNONE
, {B15
}},
6572 {"e_bge", EBD15BI(30,8,BO32F
,CBLT
,0), EBD15BI_MASK
, PPCVLE
, PPCNONE
, {CRS
,B15
}},
6573 {"e_bgel", EBD15BI(30,8,BO32F
,CBLT
,1), EBD15BI_MASK
, PPCVLE
, PPCNONE
, {CRS
,B15
}},
6574 {"e_bnl", EBD15BI(30,8,BO32F
,CBLT
,0), EBD15BI_MASK
, PPCVLE
, PPCNONE
, {CRS
,B15
}},
6575 {"e_bnll", EBD15BI(30,8,BO32F
,CBLT
,1), EBD15BI_MASK
, PPCVLE
, PPCNONE
, {CRS
,B15
}},
6576 {"e_blt", EBD15BI(30,8,BO32T
,CBLT
,0), EBD15BI_MASK
, PPCVLE
, PPCNONE
, {CRS
,B15
}},
6577 {"e_bltl", EBD15BI(30,8,BO32T
,CBLT
,1), EBD15BI_MASK
, PPCVLE
, PPCNONE
, {CRS
,B15
}},
6578 {"e_bgt", EBD15BI(30,8,BO32T
,CBGT
,0), EBD15BI_MASK
, PPCVLE
, PPCNONE
, {CRS
,B15
}},
6579 {"e_bgtl", EBD15BI(30,8,BO32T
,CBGT
,1), EBD15BI_MASK
, PPCVLE
, PPCNONE
, {CRS
,B15
}},
6580 {"e_ble", EBD15BI(30,8,BO32F
,CBGT
,0), EBD15BI_MASK
, PPCVLE
, PPCNONE
, {CRS
,B15
}},
6581 {"e_blel", EBD15BI(30,8,BO32F
,CBGT
,1), EBD15BI_MASK
, PPCVLE
, PPCNONE
, {CRS
,B15
}},
6582 {"e_bng", EBD15BI(30,8,BO32F
,CBGT
,0), EBD15BI_MASK
, PPCVLE
, PPCNONE
, {CRS
,B15
}},
6583 {"e_bngl", EBD15BI(30,8,BO32F
,CBGT
,1), EBD15BI_MASK
, PPCVLE
, PPCNONE
, {CRS
,B15
}},
6584 {"e_bne", EBD15BI(30,8,BO32F
,CBEQ
,0), EBD15BI_MASK
, PPCVLE
, PPCNONE
, {CRS
,B15
}},
6585 {"e_bnel", EBD15BI(30,8,BO32F
,CBEQ
,1), EBD15BI_MASK
, PPCVLE
, PPCNONE
, {CRS
,B15
}},
6586 {"e_beq", EBD15BI(30,8,BO32T
,CBEQ
,0), EBD15BI_MASK
, PPCVLE
, PPCNONE
, {CRS
,B15
}},
6587 {"e_beql", EBD15BI(30,8,BO32T
,CBEQ
,1), EBD15BI_MASK
, PPCVLE
, PPCNONE
, {CRS
,B15
}},
6588 {"e_bso", EBD15BI(30,8,BO32T
,CBSO
,0), EBD15BI_MASK
, PPCVLE
, PPCNONE
, {CRS
,B15
}},
6589 {"e_bsol", EBD15BI(30,8,BO32T
,CBSO
,1), EBD15BI_MASK
, PPCVLE
, PPCNONE
, {CRS
,B15
}},
6590 {"e_bun", EBD15BI(30,8,BO32T
,CBSO
,0), EBD15BI_MASK
, PPCVLE
, PPCNONE
, {CRS
,B15
}},
6591 {"e_bunl", EBD15BI(30,8,BO32T
,CBSO
,1), EBD15BI_MASK
, PPCVLE
, PPCNONE
, {CRS
,B15
}},
6592 {"e_bns", EBD15BI(30,8,BO32F
,CBSO
,0), EBD15BI_MASK
, PPCVLE
, PPCNONE
, {CRS
,B15
}},
6593 {"e_bnsl", EBD15BI(30,8,BO32F
,CBSO
,1), EBD15BI_MASK
, PPCVLE
, PPCNONE
, {CRS
,B15
}},
6594 {"e_bnu", EBD15BI(30,8,BO32F
,CBSO
,0), EBD15BI_MASK
, PPCVLE
, PPCNONE
, {CRS
,B15
}},
6595 {"e_bnul", EBD15BI(30,8,BO32F
,CBSO
,1), EBD15BI_MASK
, PPCVLE
, PPCNONE
, {CRS
,B15
}},
6596 {"e_bc", BD15(30,8,0), BD15_MASK
, PPCVLE
, PPCNONE
, {BO32
, BI32
, B15
}},
6597 {"e_bcl", BD15(30,8,1), BD15_MASK
, PPCVLE
, PPCNONE
, {BO32
, BI32
, B15
}},
6599 {"e_bf", EBD15(30,8,BO32F
,0), EBD15_MASK
, PPCVLE
, PPCNONE
, {BI32
,B15
}},
6600 {"e_bfl", EBD15(30,8,BO32F
,1), EBD15_MASK
, PPCVLE
, PPCNONE
, {BI32
,B15
}},
6601 {"e_bt", EBD15(30,8,BO32T
,0), EBD15_MASK
, PPCVLE
, PPCNONE
, {BI32
,B15
}},
6602 {"e_btl", EBD15(30,8,BO32T
,1), EBD15_MASK
, PPCVLE
, PPCNONE
, {BI32
,B15
}},
6604 {"e_cmph", X(31,14), X_MASK
, PPCVLE
, PPCNONE
, {CRD
, RA
, RB
}},
6605 {"e_cmphl", X(31,46), X_MASK
, PPCVLE
, PPCNONE
, {CRD
, RA
, RB
}},
6606 {"e_crandc", XL(31,129), XL_MASK
, PPCVLE
, PPCNONE
, {BT
, BA
, BB
}},
6607 {"e_crnand", XL(31,225), XL_MASK
, PPCVLE
, PPCNONE
, {BT
, BA
, BB
}},
6608 {"e_crnot", XL(31,33), XL_MASK
, PPCVLE
, PPCNONE
, {BT
, BA
, BBA
}},
6609 {"e_crnor", XL(31,33), XL_MASK
, PPCVLE
, PPCNONE
, {BT
, BA
, BB
}},
6610 {"e_crclr", XL(31,193), XL_MASK
, PPCVLE
, PPCNONE
, {BT
, BAT
, BBA
}},
6611 {"e_crxor", XL(31,193), XL_MASK
, PPCVLE
, PPCNONE
, {BT
, BA
, BB
}},
6612 {"e_mcrf", XL(31,16), XL_MASK
, PPCVLE
, PPCNONE
, {CRD
, CR
}},
6613 {"e_slwi", EX(31,112), EX_MASK
, PPCVLE
, PPCNONE
, {RA
, RS
, SH
}},
6614 {"e_slwi.", EX(31,113), EX_MASK
, PPCVLE
, PPCNONE
, {RA
, RS
, SH
}},
6616 {"e_crand", XL(31,257), XL_MASK
, PPCVLE
, PPCNONE
, {BT
, BA
, BB
}},
6618 {"e_rlw", EX(31,560), EX_MASK
, PPCVLE
, PPCNONE
, {RA
, RS
, RB
}},
6619 {"e_rlw.", EX(31,561), EX_MASK
, PPCVLE
, PPCNONE
, {RA
, RS
, RB
}},
6621 {"e_crset", XL(31,289), XL_MASK
, PPCVLE
, PPCNONE
, {BT
, BAT
, BBA
}},
6622 {"e_creqv", XL(31,289), XL_MASK
, PPCVLE
, PPCNONE
, {BT
, BA
, BB
}},
6624 {"e_rlwi", EX(31,624), EX_MASK
, PPCVLE
, PPCNONE
, {RA
, RS
, SH
}},
6625 {"e_rlwi.", EX(31,625), EX_MASK
, PPCVLE
, PPCNONE
, {RA
, RS
, SH
}},
6627 {"e_crorc", XL(31,417), XL_MASK
, PPCVLE
, PPCNONE
, {BT
, BA
, BB
}},
6629 {"e_crmove", XL(31,449), XL_MASK
, PPCVLE
, PPCNONE
, {BT
, BA
, BBA
}},
6630 {"e_cror", XL(31,449), XL_MASK
, PPCVLE
, PPCNONE
, {BT
, BA
, BB
}},
6632 {"mtmas1", XSPR(31,467,625), XSPR_MASK
, PPCVLE
, PPCNONE
, {RS
}},
6634 {"e_srwi", EX(31,1136), EX_MASK
, PPCVLE
, PPCNONE
, {RA
, RS
, SH
}},
6635 {"e_srwi.", EX(31,1137), EX_MASK
, PPCVLE
, PPCNONE
, {RA
, RS
, SH
}},
6637 {"se_lbz", SD4(8), SD4_MASK
, PPCVLE
, PPCNONE
, {RZ
, SE_SD
, RX
}},
6639 {"se_stb", SD4(9), SD4_MASK
, PPCVLE
, PPCNONE
, {RZ
, SE_SD
, RX
}},
6641 {"se_lhz", SD4(10), SD4_MASK
, PPCVLE
, PPCNONE
, {RZ
, SE_SDH
, RX
}},
6643 {"se_sth", SD4(11), SD4_MASK
, PPCVLE
, PPCNONE
, {RZ
, SE_SDH
, RX
}},
6645 {"se_lwz", SD4(12), SD4_MASK
, PPCVLE
, PPCNONE
, {RZ
, SE_SDW
, RX
}},
6647 {"se_stw", SD4(13), SD4_MASK
, PPCVLE
, PPCNONE
, {RZ
, SE_SDW
, RX
}},
6649 {"se_bge", EBD8IO(28,0,0), EBD8IO3_MASK
, PPCVLE
, PPCNONE
, {B8
}},
6650 {"se_bnl", EBD8IO(28,0,0), EBD8IO3_MASK
, PPCVLE
, PPCNONE
, {B8
}},
6651 {"se_ble", EBD8IO(28,0,1), EBD8IO3_MASK
, PPCVLE
, PPCNONE
, {B8
}},
6652 {"se_bng", EBD8IO(28,0,1), EBD8IO3_MASK
, PPCVLE
, PPCNONE
, {B8
}},
6653 {"se_bne", EBD8IO(28,0,2), EBD8IO3_MASK
, PPCVLE
, PPCNONE
, {B8
}},
6654 {"se_bns", EBD8IO(28,0,3), EBD8IO3_MASK
, PPCVLE
, PPCNONE
, {B8
}},
6655 {"se_bnu", EBD8IO(28,0,3), EBD8IO3_MASK
, PPCVLE
, PPCNONE
, {B8
}},
6656 {"se_bf", EBD8IO(28,0,0), EBD8IO2_MASK
, PPCVLE
, PPCNONE
, {BI16
, B8
}},
6657 {"se_blt", EBD8IO(28,1,0), EBD8IO3_MASK
, PPCVLE
, PPCNONE
, {B8
}},
6658 {"se_bgt", EBD8IO(28,1,1), EBD8IO3_MASK
, PPCVLE
, PPCNONE
, {B8
}},
6659 {"se_beq", EBD8IO(28,1,2), EBD8IO3_MASK
, PPCVLE
, PPCNONE
, {B8
}},
6660 {"se_bso", EBD8IO(28,1,3), EBD8IO3_MASK
, PPCVLE
, PPCNONE
, {B8
}},
6661 {"se_bun", EBD8IO(28,1,3), EBD8IO3_MASK
, PPCVLE
, PPCNONE
, {B8
}},
6662 {"se_bt", EBD8IO(28,1,0), EBD8IO2_MASK
, PPCVLE
, PPCNONE
, {BI16
, B8
}},
6663 {"se_bc", BD8IO(28), BD8IO_MASK
, PPCVLE
, PPCNONE
, {BO16
, BI16
, B8
}},
6664 {"se_b", BD8(58,0,0), BD8_MASK
, PPCVLE
, PPCNONE
, {B8
}},
6665 {"se_bl", BD8(58,0,1), BD8_MASK
, PPCVLE
, PPCNONE
, {B8
}},
6668 const int vle_num_opcodes
=
6669 sizeof (vle_opcodes
) / sizeof (vle_opcodes
[0]);
6671 /* The macro table. This is only used by the assembler. */
6673 /* The expressions of the form (-x ! 31) & (x | 31) have the value 0
6674 when x=0; 32-x when x is between 1 and 31; are negative if x is
6675 negative; and are 32 or more otherwise. This is what you want
6676 when, for instance, you are emulating a right shift by a
6677 rotate-left-and-mask, because the underlying instructions support
6678 shifts of size 0 but not shifts of size 32. By comparison, when
6679 extracting x bits from some word you want to use just 32-x, because
6680 the underlying instructions don't support extracting 0 bits but do
6681 support extracting the whole word (32 bits in this case). */
6683 const struct powerpc_macro powerpc_macros
[] = {
6684 {"extldi", 4, PPC64
, "rldicr %0,%1,%3,(%2)-1"},
6685 {"extldi.", 4, PPC64
, "rldicr. %0,%1,%3,(%2)-1"},
6686 {"extrdi", 4, PPC64
, "rldicl %0,%1,((%2)+(%3))&((%2)+(%3)<>64),64-(%2)"},
6687 {"extrdi.", 4, PPC64
, "rldicl. %0,%1,((%2)+(%3))&((%2)+(%3)<>64),64-(%2)"},
6688 {"insrdi", 4, PPC64
, "rldimi %0,%1,64-((%2)+(%3)),%3"},
6689 {"insrdi.", 4, PPC64
, "rldimi. %0,%1,64-((%2)+(%3)),%3"},
6690 {"rotrdi", 3, PPC64
, "rldicl %0,%1,(-(%2)!63)&((%2)|63),0"},
6691 {"rotrdi.", 3, PPC64
, "rldicl. %0,%1,(-(%2)!63)&((%2)|63),0"},
6692 {"sldi", 3, PPC64
, "rldicr %0,%1,%2,63-(%2)"},
6693 {"sldi.", 3, PPC64
, "rldicr. %0,%1,%2,63-(%2)"},
6694 {"srdi", 3, PPC64
, "rldicl %0,%1,(-(%2)!63)&((%2)|63),%2"},
6695 {"srdi.", 3, PPC64
, "rldicl. %0,%1,(-(%2)!63)&((%2)|63),%2"},
6696 {"clrrdi", 3, PPC64
, "rldicr %0,%1,0,63-(%2)"},
6697 {"clrrdi.", 3, PPC64
, "rldicr. %0,%1,0,63-(%2)"},
6698 {"clrlsldi", 4, PPC64
, "rldic %0,%1,%3,(%2)-(%3)"},
6699 {"clrlsldi.",4, PPC64
, "rldic. %0,%1,%3,(%2)-(%3)"},
6701 {"extlwi", 4, PPCCOM
, "rlwinm %0,%1,%3,0,(%2)-1"},
6702 {"extlwi.", 4, PPCCOM
, "rlwinm. %0,%1,%3,0,(%2)-1"},
6703 {"extrwi", 4, PPCCOM
, "rlwinm %0,%1,((%2)+(%3))&((%2)+(%3)<>32),32-(%2),31"},
6704 {"extrwi.", 4, PPCCOM
, "rlwinm. %0,%1,((%2)+(%3))&((%2)+(%3)<>32),32-(%2),31"},
6705 {"inslwi", 4, PPCCOM
, "rlwimi %0,%1,(-(%3)!31)&((%3)|31),%3,(%2)+(%3)-1"},
6706 {"inslwi.", 4, PPCCOM
, "rlwimi. %0,%1,(-(%3)!31)&((%3)|31),%3,(%2)+(%3)-1"},
6707 {"insrwi", 4, PPCCOM
, "rlwimi %0,%1,32-((%2)+(%3)),%3,(%2)+(%3)-1"},
6708 {"insrwi.", 4, PPCCOM
, "rlwimi. %0,%1,32-((%2)+(%3)),%3,(%2)+(%3)-1"},
6709 {"rotrwi", 3, PPCCOM
, "rlwinm %0,%1,(-(%2)!31)&((%2)|31),0,31"},
6710 {"rotrwi.", 3, PPCCOM
, "rlwinm. %0,%1,(-(%2)!31)&((%2)|31),0,31"},
6711 {"slwi", 3, PPCCOM
, "rlwinm %0,%1,%2,0,31-(%2)"},
6712 {"sli", 3, PWRCOM
, "rlinm %0,%1,%2,0,31-(%2)"},
6713 {"slwi.", 3, PPCCOM
, "rlwinm. %0,%1,%2,0,31-(%2)"},
6714 {"sli.", 3, PWRCOM
, "rlinm. %0,%1,%2,0,31-(%2)"},
6715 {"srwi", 3, PPCCOM
, "rlwinm %0,%1,(-(%2)!31)&((%2)|31),%2,31"},
6716 {"sri", 3, PWRCOM
, "rlinm %0,%1,(-(%2)!31)&((%2)|31),%2,31"},
6717 {"srwi.", 3, PPCCOM
, "rlwinm. %0,%1,(-(%2)!31)&((%2)|31),%2,31"},
6718 {"sri.", 3, PWRCOM
, "rlinm. %0,%1,(-(%2)!31)&((%2)|31),%2,31"},
6719 {"clrrwi", 3, PPCCOM
, "rlwinm %0,%1,0,0,31-(%2)"},
6720 {"clrrwi.", 3, PPCCOM
, "rlwinm. %0,%1,0,0,31-(%2)"},
6721 {"clrlslwi", 4, PPCCOM
, "rlwinm %0,%1,%3,(%2)-(%3),31-(%3)"},
6722 {"clrlslwi.",4, PPCCOM
, "rlwinm. %0,%1,%3,(%2)-(%3),31-(%3)"},
6724 {"e_extlwi", 4, PPCVLE
, "e_rlwinm %0,%1,%3,0,(%2)-1"},
6725 {"e_extrwi", 4, PPCVLE
, "e_rlwinm %0,%1,((%2)+(%3))&((%2)+(%3)<>32),32-(%2),31"},
6726 {"e_inslwi", 4, PPCVLE
, "e_rlwimi %0,%1,(-(%3)!31)&((%3)|31),%3,(%2)+(%3)-1"},
6727 {"e_insrwi", 4, PPCVLE
, "e_rlwimi %0,%1,32-((%2)+(%3)),%3,(%2)+(%3)-1"},
6728 {"e_rotlwi", 3, PPCVLE
, "e_rlwinm %0,%1,%2,0,31"},
6729 {"e_rotrwi", 3, PPCVLE
, "e_rlwinm %0,%1,(-(%2)!31)&((%2)|31),0,31"},
6730 {"e_slwi", 3, PPCVLE
, "e_rlwinm %0,%1,%2,0,31-(%2)"},
6731 {"e_srwi", 3, PPCVLE
, "e_rlwinm %0,%1,(-(%2)!31)&((%2)|31),%2,31"},
6732 {"e_clrlwi", 3, PPCVLE
, "e_rlwinm %0,%1,0,%2,31"},
6733 {"e_clrrwi", 3, PPCVLE
, "e_rlwinm %0,%1,0,0,31-(%2)"},
6734 {"e_clrlslwi",4, PPCVLE
, "e_rlwinm %0,%1,%3,(%2)-(%3),31-(%3)"},
6737 const int powerpc_num_macros
=
6738 sizeof (powerpc_macros
) / sizeof (powerpc_macros
[0]);