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* ppc-opc.c (UIMM4, UIMM3, UIMM2, VXVA_MASK, VXVB_MASK, VXVAVB_MASK,
[deliverable/binutils-gdb.git] / opcodes / ppc-opc.c
1 /* ppc-opc.c -- PowerPC opcode list
2 Copyright 1994, 1995, 1996, 1997, 1998, 2000, 2001, 2002, 2003, 2004,
3 2005, 2006, 2007, 2008, 2009, 2010, 2011, 2012
4 Free Software Foundation, Inc.
5 Written by Ian Lance Taylor, Cygnus Support
6
7 This file is part of the GNU opcodes library.
8
9 This library is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 3, or (at your option)
12 any later version.
13
14 It is distributed in the hope that it will be useful, but WITHOUT
15 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
16 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
17 License for more details.
18
19 You should have received a copy of the GNU General Public License
20 along with this file; see the file COPYING. If not, write to the
21 Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston,
22 MA 02110-1301, USA. */
23
24 #include "sysdep.h"
25 #include <stdio.h>
26 #include "opcode/ppc.h"
27 #include "opintl.h"
28
29 /* This file holds the PowerPC opcode table. The opcode table
30 includes almost all of the extended instruction mnemonics. This
31 permits the disassembler to use them, and simplifies the assembler
32 logic, at the cost of increasing the table size. The table is
33 strictly constant data, so the compiler should be able to put it in
34 the .text section.
35
36 This file also holds the operand table. All knowledge about
37 inserting operands into instructions and vice-versa is kept in this
38 file. */
39 \f
40 /* Local insertion and extraction functions. */
41
42 static unsigned long insert_arx (unsigned long, long, ppc_cpu_t, const char **);
43 static long extract_arx (unsigned long, ppc_cpu_t, int *);
44 static unsigned long insert_ary (unsigned long, long, ppc_cpu_t, const char **);
45 static long extract_ary (unsigned long, ppc_cpu_t, int *);
46 static unsigned long insert_bat (unsigned long, long, ppc_cpu_t, const char **);
47 static long extract_bat (unsigned long, ppc_cpu_t, int *);
48 static unsigned long insert_bba (unsigned long, long, ppc_cpu_t, const char **);
49 static long extract_bba (unsigned long, ppc_cpu_t, int *);
50 static unsigned long insert_bdm (unsigned long, long, ppc_cpu_t, const char **);
51 static long extract_bdm (unsigned long, ppc_cpu_t, int *);
52 static unsigned long insert_bdp (unsigned long, long, ppc_cpu_t, const char **);
53 static long extract_bdp (unsigned long, ppc_cpu_t, int *);
54 static unsigned long insert_bo (unsigned long, long, ppc_cpu_t, const char **);
55 static long extract_bo (unsigned long, ppc_cpu_t, int *);
56 static unsigned long insert_boe (unsigned long, long, ppc_cpu_t, const char **);
57 static long extract_boe (unsigned long, ppc_cpu_t, int *);
58 static unsigned long insert_fxm (unsigned long, long, ppc_cpu_t, const char **);
59 static long extract_fxm (unsigned long, ppc_cpu_t, int *);
60 static unsigned long insert_li20 (unsigned long, long, ppc_cpu_t, const char **);
61 static long extract_li20 (unsigned long, ppc_cpu_t, int *);
62 static unsigned long insert_ls (unsigned long, long, ppc_cpu_t, const char **);
63 static unsigned long insert_mbe (unsigned long, long, ppc_cpu_t, const char **);
64 static long extract_mbe (unsigned long, ppc_cpu_t, int *);
65 static unsigned long insert_mb6 (unsigned long, long, ppc_cpu_t, const char **);
66 static long extract_mb6 (unsigned long, ppc_cpu_t, int *);
67 static long extract_nb (unsigned long, ppc_cpu_t, int *);
68 static unsigned long insert_nbi (unsigned long, long, ppc_cpu_t, const char **);
69 static unsigned long insert_nsi (unsigned long, long, ppc_cpu_t, const char **);
70 static long extract_nsi (unsigned long, ppc_cpu_t, int *);
71 static unsigned long insert_oimm (unsigned long, long, ppc_cpu_t, const char **);
72 static long extract_oimm (unsigned long, ppc_cpu_t, int *);
73 static unsigned long insert_ral (unsigned long, long, ppc_cpu_t, const char **);
74 static unsigned long insert_ram (unsigned long, long, ppc_cpu_t, const char **);
75 static unsigned long insert_raq (unsigned long, long, ppc_cpu_t, const char **);
76 static unsigned long insert_ras (unsigned long, long, ppc_cpu_t, const char **);
77 static unsigned long insert_rbs (unsigned long, long, ppc_cpu_t, const char **);
78 static long extract_rbs (unsigned long, ppc_cpu_t, int *);
79 static unsigned long insert_rbx (unsigned long, long, ppc_cpu_t, const char **);
80 static unsigned long insert_rx (unsigned long, long, ppc_cpu_t, const char **);
81 static long extract_rx (unsigned long, ppc_cpu_t, int *);
82 static unsigned long insert_ry (unsigned long, long, ppc_cpu_t, const char **);
83 static long extract_ry (unsigned long, ppc_cpu_t, int *);
84 static unsigned long insert_sh6 (unsigned long, long, ppc_cpu_t, const char **);
85 static long extract_sh6 (unsigned long, ppc_cpu_t, int *);
86 static unsigned long insert_sci8 (unsigned long, long, ppc_cpu_t, const char **);
87 static long extract_sci8 (unsigned long, ppc_cpu_t, int *);
88 static unsigned long insert_sci8n (unsigned long, long, ppc_cpu_t, const char **);
89 static long extract_sci8n (unsigned long, ppc_cpu_t, int *);
90 static unsigned long insert_sd4h (unsigned long, long, ppc_cpu_t, const char **);
91 static long extract_sd4h (unsigned long, ppc_cpu_t, int *);
92 static unsigned long insert_sd4w (unsigned long, long, ppc_cpu_t, const char **);
93 static long extract_sd4w (unsigned long, ppc_cpu_t, int *);
94 static unsigned long insert_spr (unsigned long, long, ppc_cpu_t, const char **);
95 static long extract_spr (unsigned long, ppc_cpu_t, int *);
96 static unsigned long insert_sprg (unsigned long, long, ppc_cpu_t, const char **);
97 static long extract_sprg (unsigned long, ppc_cpu_t, int *);
98 static unsigned long insert_tbr (unsigned long, long, ppc_cpu_t, const char **);
99 static long extract_tbr (unsigned long, ppc_cpu_t, int *);
100 static unsigned long insert_xt6 (unsigned long, long, ppc_cpu_t, const char **);
101 static long extract_xt6 (unsigned long, ppc_cpu_t, int *);
102 static unsigned long insert_xa6 (unsigned long, long, ppc_cpu_t, const char **);
103 static long extract_xa6 (unsigned long, ppc_cpu_t, int *);
104 static unsigned long insert_xb6 (unsigned long, long, ppc_cpu_t, const char **);
105 static long extract_xb6 (unsigned long, ppc_cpu_t, int *);
106 static unsigned long insert_xb6s (unsigned long, long, ppc_cpu_t, const char **);
107 static long extract_xb6s (unsigned long, ppc_cpu_t, int *);
108 static unsigned long insert_xc6 (unsigned long, long, ppc_cpu_t, const char **);
109 static long extract_xc6 (unsigned long, ppc_cpu_t, int *);
110 static unsigned long insert_dm (unsigned long, long, ppc_cpu_t, const char **);
111 static long extract_dm (unsigned long, ppc_cpu_t, int *);
112 static unsigned long insert_vlesi (unsigned long, long, ppc_cpu_t, const char **);
113 static long extract_vlesi (unsigned long, ppc_cpu_t, int *);
114 static unsigned long insert_vlensi (unsigned long, long, ppc_cpu_t, const char **);
115 static long extract_vlensi (unsigned long, ppc_cpu_t, int *);
116 static unsigned long insert_vleui (unsigned long, long, ppc_cpu_t, const char **);
117 static long extract_vleui (unsigned long, ppc_cpu_t, int *);
118 static unsigned long insert_vleil (unsigned long, long, ppc_cpu_t, const char **);
119 static long extract_vleil (unsigned long, ppc_cpu_t, int *);
120 \f
121 /* The operands table.
122
123 The fields are bitm, shift, insert, extract, flags.
124
125 We used to put parens around the various additions, like the one
126 for BA just below. However, that caused trouble with feeble
127 compilers with a limit on depth of a parenthesized expression, like
128 (reportedly) the compiler in Microsoft Developer Studio 5. So we
129 omit the parens, since the macros are never used in a context where
130 the addition will be ambiguous. */
131
132 const struct powerpc_operand powerpc_operands[] =
133 {
134 /* The zero index is used to indicate the end of the list of
135 operands. */
136 #define UNUSED 0
137 { 0, 0, NULL, NULL, 0 },
138
139 /* The BA field in an XL form instruction. */
140 #define BA UNUSED + 1
141 /* The BI field in a B form or XL form instruction. */
142 #define BI BA
143 #define BI_MASK (0x1f << 16)
144 { 0x1f, 16, NULL, NULL, PPC_OPERAND_CR_BIT },
145
146 /* The BA field in an XL form instruction when it must be the same
147 as the BT field in the same instruction. */
148 #define BAT BA + 1
149 { 0x1f, 16, insert_bat, extract_bat, PPC_OPERAND_FAKE },
150
151 /* The BB field in an XL form instruction. */
152 #define BB BAT + 1
153 #define BB_MASK (0x1f << 11)
154 { 0x1f, 11, NULL, NULL, PPC_OPERAND_CR_BIT },
155
156 /* The BB field in an XL form instruction when it must be the same
157 as the BA field in the same instruction. */
158 #define BBA BB + 1
159 { 0x1f, 11, insert_bba, extract_bba, PPC_OPERAND_FAKE },
160
161 /* The BD field in a B form instruction. The lower two bits are
162 forced to zero. */
163 #define BD BBA + 1
164 { 0xfffc, 0, NULL, NULL, PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED },
165
166 /* The BD field in a B form instruction when absolute addressing is
167 used. */
168 #define BDA BD + 1
169 { 0xfffc, 0, NULL, NULL, PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED },
170
171 /* The BD field in a B form instruction when the - modifier is used.
172 This sets the y bit of the BO field appropriately. */
173 #define BDM BDA + 1
174 { 0xfffc, 0, insert_bdm, extract_bdm,
175 PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED },
176
177 /* The BD field in a B form instruction when the - modifier is used
178 and absolute address is used. */
179 #define BDMA BDM + 1
180 { 0xfffc, 0, insert_bdm, extract_bdm,
181 PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED },
182
183 /* The BD field in a B form instruction when the + modifier is used.
184 This sets the y bit of the BO field appropriately. */
185 #define BDP BDMA + 1
186 { 0xfffc, 0, insert_bdp, extract_bdp,
187 PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED },
188
189 /* The BD field in a B form instruction when the + modifier is used
190 and absolute addressing is used. */
191 #define BDPA BDP + 1
192 { 0xfffc, 0, insert_bdp, extract_bdp,
193 PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED },
194
195 /* The BF field in an X or XL form instruction. */
196 #define BF BDPA + 1
197 /* The CRFD field in an X form instruction. */
198 #define CRFD BF
199 /* The CRD field in an XL form instruction. */
200 #define CRD BF
201 { 0x7, 23, NULL, NULL, PPC_OPERAND_CR_REG },
202
203 /* The BF field in an X or XL form instruction. */
204 #define BFF BF + 1
205 { 0x7, 23, NULL, NULL, 0 },
206
207 /* An optional BF field. This is used for comparison instructions,
208 in which an omitted BF field is taken as zero. */
209 #define OBF BFF + 1
210 { 0x7, 23, NULL, NULL, PPC_OPERAND_CR_REG | PPC_OPERAND_OPTIONAL },
211
212 /* The BFA field in an X or XL form instruction. */
213 #define BFA OBF + 1
214 { 0x7, 18, NULL, NULL, PPC_OPERAND_CR_REG },
215
216 /* The BO field in a B form instruction. Certain values are
217 illegal. */
218 #define BO BFA + 1
219 #define BO_MASK (0x1f << 21)
220 { 0x1f, 21, insert_bo, extract_bo, 0 },
221
222 /* The BO field in a B form instruction when the + or - modifier is
223 used. This is like the BO field, but it must be even. */
224 #define BOE BO + 1
225 { 0x1e, 21, insert_boe, extract_boe, 0 },
226
227 #define BH BOE + 1
228 { 0x3, 11, NULL, NULL, PPC_OPERAND_OPTIONAL },
229
230 /* The BT field in an X or XL form instruction. */
231 #define BT BH + 1
232 { 0x1f, 21, NULL, NULL, PPC_OPERAND_CR_BIT },
233
234 /* The BI16 field in a BD8 form instruction. */
235 #define BI16 BT + 1
236 { 0x3, 8, NULL, NULL, PPC_OPERAND_CR_BIT },
237
238 /* The BI32 field in a BD15 form instruction. */
239 #define BI32 BI16 + 1
240 { 0xf, 16, NULL, NULL, PPC_OPERAND_CR_BIT },
241
242 /* The BO32 field in a BD15 form instruction. */
243 #define BO32 BI32 + 1
244 { 0x3, 20, NULL, NULL, 0 },
245
246 /* The B8 field in a BD8 form instruction. */
247 #define B8 BO32 + 1
248 { 0x1fe, -1, NULL, NULL, PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED },
249
250 /* The B15 field in a BD15 form instruction. The lowest bit is
251 forced to zero. */
252 #define B15 B8 + 1
253 { 0xfffe, 0, NULL, NULL, PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED },
254
255 /* The B24 field in a BD24 form instruction. The lowest bit is
256 forced to zero. */
257 #define B24 B15 + 1
258 { 0x1fffffe, 0, NULL, NULL, PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED },
259
260 /* The condition register number portion of the BI field in a B form
261 or XL form instruction. This is used for the extended
262 conditional branch mnemonics, which set the lower two bits of the
263 BI field. This field is optional. */
264 #define CR B24 + 1
265 { 0x7, 18, NULL, NULL, PPC_OPERAND_CR_REG | PPC_OPERAND_OPTIONAL },
266
267 /* The CRB field in an X form instruction. */
268 #define CRB CR + 1
269 /* The MB field in an M form instruction. */
270 #define MB CRB
271 #define MB_MASK (0x1f << 6)
272 { 0x1f, 6, NULL, NULL, 0 },
273
274 /* The CRD32 field in an XL form instruction. */
275 #define CRD32 CRB + 1
276 { 0x3, 21, NULL, NULL, PPC_OPERAND_CR_REG },
277
278 /* The CRFS field in an X form instruction. */
279 #define CRFS CRD32 + 1
280 { 0x7, 0, NULL, NULL, PPC_OPERAND_CR_REG },
281
282 #define CRS CRFS + 1
283 { 0x3, 18, NULL, NULL, PPC_OPERAND_CR_REG | PPC_OPERAND_OPTIONAL },
284
285 /* The CT field in an X form instruction. */
286 #define CT CRS + 1
287 /* The MO field in an mbar instruction. */
288 #define MO CT
289 { 0x1f, 21, NULL, NULL, PPC_OPERAND_OPTIONAL },
290
291 /* The D field in a D form instruction. This is a displacement off
292 a register, and implies that the next operand is a register in
293 parentheses. */
294 #define D CT + 1
295 { 0xffff, 0, NULL, NULL, PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED },
296
297 /* The D8 field in a D form instruction. This is a displacement off
298 a register, and implies that the next operand is a register in
299 parentheses. */
300 #define D8 D + 1
301 { 0xff, 0, NULL, NULL, PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED },
302
303 /* The DQ field in a DQ form instruction. This is like D, but the
304 lower four bits are forced to zero. */
305 #define DQ D8 + 1
306 { 0xfff0, 0, NULL, NULL,
307 PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED | PPC_OPERAND_DQ },
308
309 /* The DS field in a DS form instruction. This is like D, but the
310 lower two bits are forced to zero. */
311 #define DS DQ + 1
312 { 0xfffc, 0, NULL, NULL,
313 PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED | PPC_OPERAND_DS },
314
315 /* The DUIS field in a XFX form instruction, 10 bits unsigned imediate */
316 #define DUIS DS + 1
317 { 0x3ff, 11, NULL, NULL, 0 },
318
319 /* The E field in a wrteei instruction. */
320 /* And the W bit in the pair singles instructions. */
321 #define E DUIS + 1
322 #define PSW E
323 { 0x1, 15, NULL, NULL, 0 },
324
325 /* The FL1 field in a POWER SC form instruction. */
326 #define FL1 E + 1
327 /* The U field in an X form instruction. */
328 #define U FL1
329 { 0xf, 12, NULL, NULL, 0 },
330
331 /* The FL2 field in a POWER SC form instruction. */
332 #define FL2 FL1 + 1
333 { 0x7, 2, NULL, NULL, 0 },
334
335 /* The FLM field in an XFL form instruction. */
336 #define FLM FL2 + 1
337 { 0xff, 17, NULL, NULL, 0 },
338
339 /* The FRA field in an X or A form instruction. */
340 #define FRA FLM + 1
341 #define FRA_MASK (0x1f << 16)
342 { 0x1f, 16, NULL, NULL, PPC_OPERAND_FPR },
343
344 /* The FRAp field of DFP instructions. */
345 #define FRAp FRA + 1
346 { 0x1e, 16, NULL, NULL, PPC_OPERAND_FPR },
347
348 /* The FRB field in an X or A form instruction. */
349 #define FRB FRAp + 1
350 #define FRB_MASK (0x1f << 11)
351 { 0x1f, 11, NULL, NULL, PPC_OPERAND_FPR },
352
353 /* The FRBp field of DFP instructions. */
354 #define FRBp FRB + 1
355 { 0x1e, 11, NULL, NULL, PPC_OPERAND_FPR },
356
357 /* The FRC field in an A form instruction. */
358 #define FRC FRBp + 1
359 #define FRC_MASK (0x1f << 6)
360 { 0x1f, 6, NULL, NULL, PPC_OPERAND_FPR },
361
362 /* The FRS field in an X form instruction or the FRT field in a D, X
363 or A form instruction. */
364 #define FRS FRC + 1
365 #define FRT FRS
366 { 0x1f, 21, NULL, NULL, PPC_OPERAND_FPR },
367
368 /* The FRSp field of stfdp or the FRTp field of lfdp and DFP
369 instructions. */
370 #define FRSp FRS + 1
371 #define FRTp FRSp
372 { 0x1e, 21, NULL, NULL, PPC_OPERAND_FPR },
373
374 /* The FXM field in an XFX instruction. */
375 #define FXM FRSp + 1
376 { 0xff, 12, insert_fxm, extract_fxm, 0 },
377
378 /* Power4 version for mfcr. */
379 #define FXM4 FXM + 1
380 { 0xff, 12, insert_fxm, extract_fxm, PPC_OPERAND_OPTIONAL },
381
382 /* The IMM20 field in an LI instruction. */
383 #define IMM20 FXM4 + 1
384 { 0xfffff, PPC_OPSHIFT_INV, insert_li20, extract_li20, PPC_OPERAND_SIGNED},
385
386 /* The L field in a D or X form instruction. */
387 #define L IMM20 + 1
388 { 0x1, 21, NULL, NULL, PPC_OPERAND_OPTIONAL },
389
390 /* The LEV field in a POWER SVC form instruction. */
391 #define SVC_LEV L + 1
392 { 0x7f, 5, NULL, NULL, 0 },
393
394 /* The LEV field in an SC form instruction. */
395 #define LEV SVC_LEV + 1
396 { 0x7f, 5, NULL, NULL, PPC_OPERAND_OPTIONAL },
397
398 /* The LI field in an I form instruction. The lower two bits are
399 forced to zero. */
400 #define LI LEV + 1
401 { 0x3fffffc, 0, NULL, NULL, PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED },
402
403 /* The LI field in an I form instruction when used as an absolute
404 address. */
405 #define LIA LI + 1
406 { 0x3fffffc, 0, NULL, NULL, PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED },
407
408 /* The LS or WC field in an X (sync or wait) form instruction. */
409 #define LS LIA + 1
410 #define WC LS
411 { 0x3, 21, NULL, NULL, PPC_OPERAND_OPTIONAL },
412
413 /* The ME field in an M form instruction. */
414 #define ME LS + 1
415 #define ME_MASK (0x1f << 1)
416 { 0x1f, 1, NULL, NULL, 0 },
417
418 /* The MB and ME fields in an M form instruction expressed a single
419 operand which is a bitmask indicating which bits to select. This
420 is a two operand form using PPC_OPERAND_NEXT. See the
421 description in opcode/ppc.h for what this means. */
422 #define MBE ME + 1
423 { 0x1f, 6, NULL, NULL, PPC_OPERAND_OPTIONAL | PPC_OPERAND_NEXT },
424 { -1, 0, insert_mbe, extract_mbe, 0 },
425
426 /* The MB or ME field in an MD or MDS form instruction. The high
427 bit is wrapped to the low end. */
428 #define MB6 MBE + 2
429 #define ME6 MB6
430 #define MB6_MASK (0x3f << 5)
431 { 0x3f, 5, insert_mb6, extract_mb6, 0 },
432
433 /* The NB field in an X form instruction. The value 32 is stored as
434 0. */
435 #define NB MB6 + 1
436 { 0x1f, 11, NULL, extract_nb, PPC_OPERAND_PLUS1 },
437
438 /* The NBI field in an lswi instruction, which has special value
439 restrictions. The value 32 is stored as 0. */
440 #define NBI NB + 1
441 { 0x1f, 11, insert_nbi, extract_nb, PPC_OPERAND_PLUS1 },
442
443 /* The NSI field in a D form instruction. This is the same as the
444 SI field, only negated. */
445 #define NSI NBI + 1
446 { 0xffff, 0, insert_nsi, extract_nsi,
447 PPC_OPERAND_NEGATIVE | PPC_OPERAND_SIGNED },
448
449 /* The RA field in an D, DS, DQ, X, XO, M, or MDS form instruction. */
450 #define RA NSI + 1
451 #define RA_MASK (0x1f << 16)
452 { 0x1f, 16, NULL, NULL, PPC_OPERAND_GPR },
453
454 /* As above, but 0 in the RA field means zero, not r0. */
455 #define RA0 RA + 1
456 { 0x1f, 16, NULL, NULL, PPC_OPERAND_GPR_0 },
457
458 /* The RA field in the DQ form lq or an lswx instruction, which have special
459 value restrictions. */
460 #define RAQ RA0 + 1
461 #define RAX RAQ
462 { 0x1f, 16, insert_raq, NULL, PPC_OPERAND_GPR_0 },
463
464 /* The RA field in a D or X form instruction which is an updating
465 load, which means that the RA field may not be zero and may not
466 equal the RT field. */
467 #define RAL RAQ + 1
468 { 0x1f, 16, insert_ral, NULL, PPC_OPERAND_GPR_0 },
469
470 /* The RA field in an lmw instruction, which has special value
471 restrictions. */
472 #define RAM RAL + 1
473 { 0x1f, 16, insert_ram, NULL, PPC_OPERAND_GPR_0 },
474
475 /* The RA field in a D or X form instruction which is an updating
476 store or an updating floating point load, which means that the RA
477 field may not be zero. */
478 #define RAS RAM + 1
479 { 0x1f, 16, insert_ras, NULL, PPC_OPERAND_GPR_0 },
480
481 /* The RA field of the tlbwe, dccci and iccci instructions,
482 which are optional. */
483 #define RAOPT RAS + 1
484 { 0x1f, 16, NULL, NULL, PPC_OPERAND_GPR | PPC_OPERAND_OPTIONAL },
485
486 /* The RB field in an X, XO, M, or MDS form instruction. */
487 #define RB RAOPT + 1
488 #define RB_MASK (0x1f << 11)
489 { 0x1f, 11, NULL, NULL, PPC_OPERAND_GPR },
490
491 /* The RB field in an X form instruction when it must be the same as
492 the RS field in the instruction. This is used for extended
493 mnemonics like mr. */
494 #define RBS RB + 1
495 { 0x1f, 11, insert_rbs, extract_rbs, PPC_OPERAND_FAKE },
496
497 /* The RB field in an lswx instruction, which has special value
498 restrictions. */
499 #define RBX RBS + 1
500 { 0x1f, 11, insert_rbx, NULL, PPC_OPERAND_GPR },
501
502 /* The RB field of the dccci and iccci instructions, which are optional. */
503 #define RBOPT RBX + 1
504 { 0x1f, 11, NULL, NULL, PPC_OPERAND_GPR | PPC_OPERAND_OPTIONAL },
505
506 /* The RS field in a D, DS, X, XFX, XS, M, MD or MDS form
507 instruction or the RT field in a D, DS, X, XFX or XO form
508 instruction. */
509 #define RS RBOPT + 1
510 #define RT RS
511 #define RT_MASK (0x1f << 21)
512 #define RD RS
513 { 0x1f, 21, NULL, NULL, PPC_OPERAND_GPR },
514
515 /* The RS and RT fields of the DS form stq and DQ form lq instructions,
516 which have special value restrictions. */
517 #define RSQ RS + 1
518 #define RTQ RSQ
519 { 0x1e, 21, NULL, NULL, PPC_OPERAND_GPR },
520
521 /* The RS field of the tlbwe instruction, which is optional. */
522 #define RSO RSQ + 1
523 #define RTO RSO
524 { 0x1f, 21, NULL, NULL, PPC_OPERAND_GPR | PPC_OPERAND_OPTIONAL },
525
526 /* The RX field of the SE_RR form instruction. */
527 #define RX RSO + 1
528 { 0x1f, PPC_OPSHIFT_INV, insert_rx, extract_rx, PPC_OPERAND_GPR },
529
530 /* The ARX field of the SE_RR form instruction. */
531 #define ARX RX + 1
532 { 0x1f, PPC_OPSHIFT_INV, insert_arx, extract_arx, PPC_OPERAND_GPR },
533
534 /* The RY field of the SE_RR form instruction. */
535 #define RY ARX + 1
536 #define RZ RY
537 { 0x1f, PPC_OPSHIFT_INV, insert_ry, extract_ry, PPC_OPERAND_GPR },
538
539 /* The ARY field of the SE_RR form instruction. */
540 #define ARY RY + 1
541 { 0x1f, PPC_OPSHIFT_INV, insert_ary, extract_ary, PPC_OPERAND_GPR },
542
543 /* The SCLSCI8 field in a D form instruction. */
544 #define SCLSCI8 ARY + 1
545 { 0xffffffff, PPC_OPSHIFT_INV, insert_sci8, extract_sci8, 0 },
546
547 /* The SCLSCI8N field in a D form instruction. This is the same as the
548 SCLSCI8 field, only negated. */
549 #define SCLSCI8N SCLSCI8 + 1
550 { 0xffffffff, PPC_OPSHIFT_INV, insert_sci8n, extract_sci8n,
551 PPC_OPERAND_NEGATIVE | PPC_OPERAND_SIGNED },
552
553 /* The SD field of the SD4 form instruction. */
554 #define SE_SD SCLSCI8N + 1
555 { 0xf, 8, NULL, NULL, PPC_OPERAND_PARENS },
556
557 /* The SD field of the SD4 form instruction, for halfword. */
558 #define SE_SDH SE_SD + 1
559 { 0x1e, PPC_OPSHIFT_INV, insert_sd4h, extract_sd4h, PPC_OPERAND_PARENS },
560
561 /* The SD field of the SD4 form instruction, for word. */
562 #define SE_SDW SE_SDH + 1
563 { 0x3c, PPC_OPSHIFT_INV, insert_sd4w, extract_sd4w, PPC_OPERAND_PARENS },
564
565 /* The SH field in an X or M form instruction. */
566 #define SH SE_SDW + 1
567 #define SH_MASK (0x1f << 11)
568 /* The other UIMM field in a EVX form instruction. */
569 #define EVUIMM SH
570 { 0x1f, 11, NULL, NULL, 0 },
571
572 /* The SH field in an MD form instruction. This is split. */
573 #define SH6 SH + 1
574 #define SH6_MASK ((0x1f << 11) | (1 << 1))
575 { 0x3f, PPC_OPSHIFT_INV, insert_sh6, extract_sh6, 0 },
576
577 /* The SH field of the tlbwe instruction, which is optional. */
578 #define SHO SH6 + 1
579 { 0x1f, 11, NULL, NULL, PPC_OPERAND_OPTIONAL },
580
581 /* The SI field in a D form instruction. */
582 #define SI SHO + 1
583 { 0xffff, 0, NULL, NULL, PPC_OPERAND_SIGNED },
584
585 /* The SI field in a D form instruction when we accept a wide range
586 of positive values. */
587 #define SISIGNOPT SI + 1
588 { 0xffff, 0, NULL, NULL, PPC_OPERAND_SIGNED | PPC_OPERAND_SIGNOPT },
589
590 /* The SI8 field in a D form instruction. */
591 #define SI8 SISIGNOPT + 1
592 { 0xff, 0, NULL, NULL, PPC_OPERAND_SIGNED },
593
594 /* The SPR field in an XFX form instruction. This is flipped--the
595 lower 5 bits are stored in the upper 5 and vice- versa. */
596 #define SPR SI8 + 1
597 #define PMR SPR
598 #define TMR SPR
599 #define SPR_MASK (0x3ff << 11)
600 { 0x3ff, 11, insert_spr, extract_spr, 0 },
601
602 /* The BAT index number in an XFX form m[ft]ibat[lu] instruction. */
603 #define SPRBAT SPR + 1
604 #define SPRBAT_MASK (0x3 << 17)
605 { 0x3, 17, NULL, NULL, 0 },
606
607 /* The SPRG register number in an XFX form m[ft]sprg instruction. */
608 #define SPRG SPRBAT + 1
609 { 0x1f, 16, insert_sprg, extract_sprg, 0 },
610
611 /* The SR field in an X form instruction. */
612 #define SR SPRG + 1
613 /* The 4-bit UIMM field in a VX form instruction. */
614 #define UIMM4 SR
615 { 0xf, 16, NULL, NULL, 0 },
616
617 /* The STRM field in an X AltiVec form instruction. */
618 #define STRM SR + 1
619 /* The T field in a tlbilx form instruction. */
620 #define T STRM
621 { 0x3, 21, NULL, NULL, 0 },
622
623 /* The ESYNC field in an X (sync) form instruction. */
624 #define ESYNC STRM + 1
625 { 0xf, 16, insert_ls, NULL, PPC_OPERAND_OPTIONAL },
626
627 /* The SV field in a POWER SC form instruction. */
628 #define SV ESYNC + 1
629 { 0x3fff, 2, NULL, NULL, 0 },
630
631 /* The TBR field in an XFX form instruction. This is like the SPR
632 field, but it is optional. */
633 #define TBR SV + 1
634 { 0x3ff, 11, insert_tbr, extract_tbr, PPC_OPERAND_OPTIONAL },
635
636 /* The TO field in a D or X form instruction. */
637 #define TO TBR + 1
638 #define DUI TO
639 #define TO_MASK (0x1f << 21)
640 { 0x1f, 21, NULL, NULL, 0 },
641
642 /* The UI field in a D form instruction. */
643 #define UI TO + 1
644 { 0xffff, 0, NULL, NULL, 0 },
645
646 /* The IMM field in an SE_IM5 instruction. */
647 #define UI5 UI + 1
648 { 0x1f, 4, NULL, NULL, 0 },
649
650 /* The OIMM field in an SE_OIM5 instruction. */
651 #define OIMM5 UI5 + 1
652 { 0x1f, PPC_OPSHIFT_INV, insert_oimm, extract_oimm, PPC_OPERAND_PLUS1 },
653
654 /* The UI7 field in an SE_LI instruction. */
655 #define UI7 OIMM5 + 1
656 { 0x7f, 4, NULL, NULL, 0 },
657
658 /* The VA field in a VA, VX or VXR form instruction. */
659 #define VA UI7 + 1
660 { 0x1f, 16, NULL, NULL, PPC_OPERAND_VR },
661
662 /* The VB field in a VA, VX or VXR form instruction. */
663 #define VB VA + 1
664 { 0x1f, 11, NULL, NULL, PPC_OPERAND_VR },
665
666 /* The VC field in a VA form instruction. */
667 #define VC VB + 1
668 { 0x1f, 6, NULL, NULL, PPC_OPERAND_VR },
669
670 /* The VD or VS field in a VA, VX, VXR or X form instruction. */
671 #define VD VC + 1
672 #define VS VD
673 { 0x1f, 21, NULL, NULL, PPC_OPERAND_VR },
674
675 /* The SIMM field in a VX form instruction, and TE in Z form. */
676 #define SIMM VD + 1
677 #define TE SIMM
678 { 0x1f, 16, NULL, NULL, PPC_OPERAND_SIGNED},
679
680 /* The UIMM field in a VX form instruction. */
681 #define UIMM SIMM + 1
682 #define DCTL UIMM
683 { 0x1f, 16, NULL, NULL, 0 },
684
685 /* The 3-bit UIMM field in a VX form instruction. */
686 #define UIMM3 UIMM + 1
687 { 0x7, 16, NULL, NULL, 0 },
688
689 /* The SHB field in a VA form instruction. */
690 #define SHB UIMM3 + 1
691 { 0xf, 6, NULL, NULL, 0 },
692
693 /* The other UIMM field in a half word EVX form instruction. */
694 #define EVUIMM_2 SHB + 1
695 { 0x3e, 10, NULL, NULL, PPC_OPERAND_PARENS },
696
697 /* The other UIMM field in a word EVX form instruction. */
698 #define EVUIMM_4 EVUIMM_2 + 1
699 { 0x7c, 9, NULL, NULL, PPC_OPERAND_PARENS },
700
701 /* The other UIMM field in a double EVX form instruction. */
702 #define EVUIMM_8 EVUIMM_4 + 1
703 { 0xf8, 8, NULL, NULL, PPC_OPERAND_PARENS },
704
705 /* The WS field. */
706 #define WS EVUIMM_8 + 1
707 { 0x7, 11, NULL, NULL, 0 },
708
709 /* PowerPC paired singles extensions. */
710 /* W bit in the pair singles instructions for x type instructions. */
711 #define PSWM WS + 1
712 /* The BO16 field in a BD8 form instruction. */
713 #define BO16 PSWM
714 { 0x1, 10, 0, 0, 0 },
715
716 /* IDX bits for quantization in the pair singles instructions. */
717 #define PSQ PSWM + 1
718 { 0x7, 12, 0, 0, 0 },
719
720 /* IDX bits for quantization in the pair singles x-type instructions. */
721 #define PSQM PSQ + 1
722 { 0x7, 7, 0, 0, 0 },
723
724 /* Smaller D field for quantization in the pair singles instructions. */
725 #define PSD PSQM + 1
726 { 0xfff, 0, 0, 0, PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED },
727
728 #define A_L PSD + 1
729 #define W A_L
730 #define MTMSRD_L W
731 { 0x1, 16, NULL, NULL, PPC_OPERAND_OPTIONAL },
732
733 #define RMC MTMSRD_L + 1
734 { 0x3, 9, NULL, NULL, 0 },
735
736 #define R RMC + 1
737 { 0x1, 16, NULL, NULL, 0 },
738
739 #define SP R + 1
740 { 0x3, 19, NULL, NULL, 0 },
741
742 #define S SP + 1
743 { 0x1, 20, NULL, NULL, 0 },
744
745 /* SH field starting at bit position 16. */
746 #define SH16 S + 1
747 /* The DCM and DGM fields in a Z form instruction. */
748 #define DCM SH16
749 #define DGM DCM
750 { 0x3f, 10, NULL, NULL, 0 },
751
752 /* The EH field in larx instruction. */
753 #define EH SH16 + 1
754 { 0x1, 0, NULL, NULL, PPC_OPERAND_OPTIONAL },
755
756 /* The L field in an mtfsf or XFL form instruction. */
757 #define XFL_L EH + 1
758 { 0x1, 25, NULL, NULL, PPC_OPERAND_OPTIONAL},
759
760 /* Xilinx APU related masks and macros */
761 #define FCRT XFL_L + 1
762 #define FCRT_MASK (0x1f << 21)
763 { 0x1f, 21, 0, 0, PPC_OPERAND_FCR },
764
765 /* Xilinx FSL related masks and macros */
766 #define FSL FCRT + 1
767 #define FSL_MASK (0x1f << 11)
768 { 0x1f, 11, 0, 0, PPC_OPERAND_FSL },
769
770 /* Xilinx UDI related masks and macros */
771 #define URT FSL + 1
772 { 0x1f, 21, 0, 0, PPC_OPERAND_UDI },
773
774 #define URA URT + 1
775 { 0x1f, 16, 0, 0, PPC_OPERAND_UDI },
776
777 #define URB URA + 1
778 { 0x1f, 11, 0, 0, PPC_OPERAND_UDI },
779
780 #define URC URB + 1
781 { 0x1f, 6, 0, 0, PPC_OPERAND_UDI },
782
783 /* The VLESIMM field in a D form instruction. */
784 #define VLESIMM URC + 1
785 { 0xffff, PPC_OPSHIFT_INV, insert_vlesi, extract_vlesi,
786 PPC_OPERAND_SIGNED | PPC_OPERAND_SIGNOPT },
787
788 /* The VLENSIMM field in a D form instruction. */
789 #define VLENSIMM VLESIMM + 1
790 { 0xffff, PPC_OPSHIFT_INV, insert_vlensi, extract_vlensi,
791 PPC_OPERAND_NEGATIVE | PPC_OPERAND_SIGNED | PPC_OPERAND_SIGNOPT },
792
793 /* The VLEUIMM field in a D form instruction. */
794 #define VLEUIMM VLENSIMM + 1
795 { 0xffff, PPC_OPSHIFT_INV, insert_vleui, extract_vleui, 0 },
796
797 /* The VLEUIMML field in a D form instruction. */
798 #define VLEUIMML VLEUIMM + 1
799 { 0xffff, PPC_OPSHIFT_INV, insert_vleil, extract_vleil, 0 },
800
801 /* The XT and XS fields in an XX1 or XX3 form instruction. This is split. */
802 #define XS6 VLEUIMML + 1
803 #define XT6 XS6
804 { 0x3f, PPC_OPSHIFT_INV, insert_xt6, extract_xt6, PPC_OPERAND_VSR },
805
806 /* The XA field in an XX3 form instruction. This is split. */
807 #define XA6 XT6 + 1
808 { 0x3f, PPC_OPSHIFT_INV, insert_xa6, extract_xa6, PPC_OPERAND_VSR },
809
810 /* The XB field in an XX2 or XX3 form instruction. This is split. */
811 #define XB6 XA6 + 1
812 { 0x3f, PPC_OPSHIFT_INV, insert_xb6, extract_xb6, PPC_OPERAND_VSR },
813
814 /* The XB field in an XX3 form instruction when it must be the same as
815 the XA field in the instruction. This is used in extended mnemonics
816 like xvmovdp. This is split. */
817 #define XB6S XB6 + 1
818 { 0x3f, PPC_OPSHIFT_INV, insert_xb6s, extract_xb6s, PPC_OPERAND_FAKE },
819
820 /* The XC field in an XX4 form instruction. This is split. */
821 #define XC6 XB6S + 1
822 { 0x3f, PPC_OPSHIFT_INV, insert_xc6, extract_xc6, PPC_OPERAND_VSR },
823
824 /* The DM or SHW field in an XX3 form instruction. */
825 #define DM XC6 + 1
826 #define SHW DM
827 { 0x3, 8, NULL, NULL, 0 },
828
829 /* The DM field in an extended mnemonic XX3 form instruction. */
830 #define DMEX DM + 1
831 { 0x3, 8, insert_dm, extract_dm, 0 },
832
833 /* The UIM field in an XX2 form instruction. */
834 #define UIM DMEX + 1
835 /* The 2-bit UIMM field in a VX form instruction. */
836 #define UIMM2 UIM
837 { 0x3, 16, NULL, NULL, 0 },
838
839 #define ERAT_T UIM + 1
840 { 0x7, 21, NULL, NULL, 0 },
841 };
842
843 const unsigned int num_powerpc_operands = (sizeof (powerpc_operands)
844 / sizeof (powerpc_operands[0]));
845
846 /* The functions used to insert and extract complicated operands. */
847
848 /* The ARX, ARY, RX and RY operands are alternate encodings of GPRs. */
849
850 static unsigned long
851 insert_arx (unsigned long insn,
852 long value,
853 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
854 const char **errmsg ATTRIBUTE_UNUSED)
855 {
856 if (value >= 8 && value < 24)
857 return insn | ((value - 8) & 0xf);
858 else
859 {
860 *errmsg = _("invalid register");
861 return 0;
862 }
863 }
864
865 static long
866 extract_arx (unsigned long insn,
867 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
868 int *invalid ATTRIBUTE_UNUSED)
869 {
870 return (insn & 0xf) + 8;
871 }
872
873 static unsigned long
874 insert_ary (unsigned long insn,
875 long value,
876 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
877 const char **errmsg ATTRIBUTE_UNUSED)
878 {
879 if (value >= 8 && value < 24)
880 return insn | (((value - 8) & 0xf) << 4);
881 else
882 {
883 *errmsg = _("invalid register");
884 return 0;
885 }
886 }
887
888 static long
889 extract_ary (unsigned long insn,
890 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
891 int *invalid ATTRIBUTE_UNUSED)
892 {
893 return ((insn >> 4) & 0xf) + 8;
894 }
895
896 static unsigned long
897 insert_rx (unsigned long insn,
898 long value,
899 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
900 const char **errmsg)
901 {
902 if (value >= 0 && value < 8)
903 return insn | value;
904 else if (value >= 24 && value <= 31)
905 return insn | (value - 16);
906 else
907 {
908 *errmsg = _("invalid register");
909 return 0;
910 }
911 }
912
913 static long
914 extract_rx (unsigned long insn,
915 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
916 int *invalid ATTRIBUTE_UNUSED)
917 {
918 int value = insn & 0xf;
919 if (value >= 0 && value < 8)
920 return value;
921 else
922 return value + 16;
923 }
924
925 static unsigned long
926 insert_ry (unsigned long insn,
927 long value,
928 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
929 const char **errmsg)
930 {
931 if (value >= 0 && value < 8)
932 return insn | (value << 4);
933 else if (value >= 24 && value <= 31)
934 return insn | ((value - 16) << 4);
935 else
936 {
937 *errmsg = _("invalid register");
938 return 0;
939 }
940 }
941
942 static long
943 extract_ry (unsigned long insn,
944 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
945 int *invalid ATTRIBUTE_UNUSED)
946 {
947 int value = (insn >> 4) & 0xf;
948 if (value >= 0 && value < 8)
949 return value;
950 else
951 return value + 16;
952 }
953
954 /* The BA field in an XL form instruction when it must be the same as
955 the BT field in the same instruction. This operand is marked FAKE.
956 The insertion function just copies the BT field into the BA field,
957 and the extraction function just checks that the fields are the
958 same. */
959
960 static unsigned long
961 insert_bat (unsigned long insn,
962 long value ATTRIBUTE_UNUSED,
963 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
964 const char **errmsg ATTRIBUTE_UNUSED)
965 {
966 return insn | (((insn >> 21) & 0x1f) << 16);
967 }
968
969 static long
970 extract_bat (unsigned long insn,
971 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
972 int *invalid)
973 {
974 if (((insn >> 21) & 0x1f) != ((insn >> 16) & 0x1f))
975 *invalid = 1;
976 return 0;
977 }
978
979 /* The BB field in an XL form instruction when it must be the same as
980 the BA field in the same instruction. This operand is marked FAKE.
981 The insertion function just copies the BA field into the BB field,
982 and the extraction function just checks that the fields are the
983 same. */
984
985 static unsigned long
986 insert_bba (unsigned long insn,
987 long value ATTRIBUTE_UNUSED,
988 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
989 const char **errmsg ATTRIBUTE_UNUSED)
990 {
991 return insn | (((insn >> 16) & 0x1f) << 11);
992 }
993
994 static long
995 extract_bba (unsigned long insn,
996 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
997 int *invalid)
998 {
999 if (((insn >> 16) & 0x1f) != ((insn >> 11) & 0x1f))
1000 *invalid = 1;
1001 return 0;
1002 }
1003
1004 /* The BD field in a B form instruction when the - modifier is used.
1005 This modifier means that the branch is not expected to be taken.
1006 For chips built to versions of the architecture prior to version 2
1007 (ie. not Power4 compatible), we set the y bit of the BO field to 1
1008 if the offset is negative. When extracting, we require that the y
1009 bit be 1 and that the offset be positive, since if the y bit is 0
1010 we just want to print the normal form of the instruction.
1011 Power4 compatible targets use two bits, "a", and "t", instead of
1012 the "y" bit. "at" == 00 => no hint, "at" == 01 => unpredictable,
1013 "at" == 10 => not taken, "at" == 11 => taken. The "t" bit is 00001
1014 in BO field, the "a" bit is 00010 for branch on CR(BI) and 01000
1015 for branch on CTR. We only handle the taken/not-taken hint here.
1016 Note that we don't relax the conditions tested here when
1017 disassembling with -Many because insns using extract_bdm and
1018 extract_bdp always occur in pairs. One or the other will always
1019 be valid. */
1020
1021 #define ISA_V2 (PPC_OPCODE_POWER4 | PPC_OPCODE_E500MC | PPC_OPCODE_TITAN)
1022
1023 static unsigned long
1024 insert_bdm (unsigned long insn,
1025 long value,
1026 ppc_cpu_t dialect,
1027 const char **errmsg ATTRIBUTE_UNUSED)
1028 {
1029 if ((dialect & ISA_V2) == 0)
1030 {
1031 if ((value & 0x8000) != 0)
1032 insn |= 1 << 21;
1033 }
1034 else
1035 {
1036 if ((insn & (0x14 << 21)) == (0x04 << 21))
1037 insn |= 0x02 << 21;
1038 else if ((insn & (0x14 << 21)) == (0x10 << 21))
1039 insn |= 0x08 << 21;
1040 }
1041 return insn | (value & 0xfffc);
1042 }
1043
1044 static long
1045 extract_bdm (unsigned long insn,
1046 ppc_cpu_t dialect,
1047 int *invalid)
1048 {
1049 if ((dialect & ISA_V2) == 0)
1050 {
1051 if (((insn & (1 << 21)) == 0) != ((insn & (1 << 15)) == 0))
1052 *invalid = 1;
1053 }
1054 else
1055 {
1056 if ((insn & (0x17 << 21)) != (0x06 << 21)
1057 && (insn & (0x1d << 21)) != (0x18 << 21))
1058 *invalid = 1;
1059 }
1060
1061 return ((insn & 0xfffc) ^ 0x8000) - 0x8000;
1062 }
1063
1064 /* The BD field in a B form instruction when the + modifier is used.
1065 This is like BDM, above, except that the branch is expected to be
1066 taken. */
1067
1068 static unsigned long
1069 insert_bdp (unsigned long insn,
1070 long value,
1071 ppc_cpu_t dialect,
1072 const char **errmsg ATTRIBUTE_UNUSED)
1073 {
1074 if ((dialect & ISA_V2) == 0)
1075 {
1076 if ((value & 0x8000) == 0)
1077 insn |= 1 << 21;
1078 }
1079 else
1080 {
1081 if ((insn & (0x14 << 21)) == (0x04 << 21))
1082 insn |= 0x03 << 21;
1083 else if ((insn & (0x14 << 21)) == (0x10 << 21))
1084 insn |= 0x09 << 21;
1085 }
1086 return insn | (value & 0xfffc);
1087 }
1088
1089 static long
1090 extract_bdp (unsigned long insn,
1091 ppc_cpu_t dialect,
1092 int *invalid)
1093 {
1094 if ((dialect & ISA_V2) == 0)
1095 {
1096 if (((insn & (1 << 21)) == 0) == ((insn & (1 << 15)) == 0))
1097 *invalid = 1;
1098 }
1099 else
1100 {
1101 if ((insn & (0x17 << 21)) != (0x07 << 21)
1102 && (insn & (0x1d << 21)) != (0x19 << 21))
1103 *invalid = 1;
1104 }
1105
1106 return ((insn & 0xfffc) ^ 0x8000) - 0x8000;
1107 }
1108
1109 static inline int
1110 valid_bo_pre_v2 (long value)
1111 {
1112 /* Certain encodings have bits that are required to be zero.
1113 These are (z must be zero, y may be anything):
1114 0000y
1115 0001y
1116 001zy
1117 0100y
1118 0101y
1119 011zy
1120 1z00y
1121 1z01y
1122 1z1zz
1123 */
1124 if ((value & 0x14) == 0)
1125 return 1;
1126 else if ((value & 0x14) == 0x4)
1127 return (value & 0x2) == 0;
1128 else if ((value & 0x14) == 0x10)
1129 return (value & 0x8) == 0;
1130 else
1131 return value == 0x14;
1132 }
1133
1134 static inline int
1135 valid_bo_post_v2 (long value)
1136 {
1137 /* Certain encodings have bits that are required to be zero.
1138 These are (z must be zero, a & t may be anything):
1139 0000z
1140 0001z
1141 001at
1142 0100z
1143 0101z
1144 011at
1145 1a00t
1146 1a01t
1147 1z1zz
1148 */
1149 if ((value & 0x14) == 0)
1150 return (value & 0x1) == 0;
1151 else if ((value & 0x14) == 0x14)
1152 return value == 0x14;
1153 else
1154 return 1;
1155 }
1156
1157 /* Check for legal values of a BO field. */
1158
1159 static int
1160 valid_bo (long value, ppc_cpu_t dialect, int extract)
1161 {
1162 int valid_y = valid_bo_pre_v2 (value);
1163 int valid_at = valid_bo_post_v2 (value);
1164
1165 /* When disassembling with -Many, accept either encoding on the
1166 second pass through opcodes. */
1167 if (extract && dialect == ~(ppc_cpu_t) PPC_OPCODE_ANY)
1168 return valid_y || valid_at;
1169 if ((dialect & ISA_V2) == 0)
1170 return valid_y;
1171 else
1172 return valid_at;
1173 }
1174
1175 /* The BO field in a B form instruction. Warn about attempts to set
1176 the field to an illegal value. */
1177
1178 static unsigned long
1179 insert_bo (unsigned long insn,
1180 long value,
1181 ppc_cpu_t dialect,
1182 const char **errmsg)
1183 {
1184 if (!valid_bo (value, dialect, 0))
1185 *errmsg = _("invalid conditional option");
1186 else if (PPC_OP (insn) == 19 && (insn & 0x400) && ! (value & 4))
1187 *errmsg = _("invalid counter access");
1188 return insn | ((value & 0x1f) << 21);
1189 }
1190
1191 static long
1192 extract_bo (unsigned long insn,
1193 ppc_cpu_t dialect,
1194 int *invalid)
1195 {
1196 long value;
1197
1198 value = (insn >> 21) & 0x1f;
1199 if (!valid_bo (value, dialect, 1))
1200 *invalid = 1;
1201 return value;
1202 }
1203
1204 /* The BO field in a B form instruction when the + or - modifier is
1205 used. This is like the BO field, but it must be even. When
1206 extracting it, we force it to be even. */
1207
1208 static unsigned long
1209 insert_boe (unsigned long insn,
1210 long value,
1211 ppc_cpu_t dialect,
1212 const char **errmsg)
1213 {
1214 if (!valid_bo (value, dialect, 0))
1215 *errmsg = _("invalid conditional option");
1216 else if (PPC_OP (insn) == 19 && (insn & 0x400) && ! (value & 4))
1217 *errmsg = _("invalid counter access");
1218 else if ((value & 1) != 0)
1219 *errmsg = _("attempt to set y bit when using + or - modifier");
1220
1221 return insn | ((value & 0x1f) << 21);
1222 }
1223
1224 static long
1225 extract_boe (unsigned long insn,
1226 ppc_cpu_t dialect,
1227 int *invalid)
1228 {
1229 long value;
1230
1231 value = (insn >> 21) & 0x1f;
1232 if (!valid_bo (value, dialect, 1))
1233 *invalid = 1;
1234 return value & 0x1e;
1235 }
1236
1237 /* FXM mask in mfcr and mtcrf instructions. */
1238
1239 static unsigned long
1240 insert_fxm (unsigned long insn,
1241 long value,
1242 ppc_cpu_t dialect,
1243 const char **errmsg)
1244 {
1245 /* If we're handling the mfocrf and mtocrf insns ensure that exactly
1246 one bit of the mask field is set. */
1247 if ((insn & (1 << 20)) != 0)
1248 {
1249 if (value == 0 || (value & -value) != value)
1250 {
1251 *errmsg = _("invalid mask field");
1252 value = 0;
1253 }
1254 }
1255
1256 /* If the optional field on mfcr is missing that means we want to use
1257 the old form of the instruction that moves the whole cr. In that
1258 case we'll have VALUE zero. There doesn't seem to be a way to
1259 distinguish this from the case where someone writes mfcr %r3,0. */
1260 else if (value == 0)
1261 ;
1262
1263 /* If only one bit of the FXM field is set, we can use the new form
1264 of the instruction, which is faster. Unlike the Power4 branch hint
1265 encoding, this is not backward compatible. Do not generate the
1266 new form unless -mpower4 has been given, or -many and the two
1267 operand form of mfcr was used. */
1268 else if ((value & -value) == value
1269 && ((dialect & PPC_OPCODE_POWER4) != 0
1270 || ((dialect & PPC_OPCODE_ANY) != 0
1271 && (insn & (0x3ff << 1)) == 19 << 1)))
1272 insn |= 1 << 20;
1273
1274 /* Any other value on mfcr is an error. */
1275 else if ((insn & (0x3ff << 1)) == 19 << 1)
1276 {
1277 *errmsg = _("ignoring invalid mfcr mask");
1278 value = 0;
1279 }
1280
1281 return insn | ((value & 0xff) << 12);
1282 }
1283
1284 static long
1285 extract_fxm (unsigned long insn,
1286 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1287 int *invalid)
1288 {
1289 long mask = (insn >> 12) & 0xff;
1290
1291 /* Is this a Power4 insn? */
1292 if ((insn & (1 << 20)) != 0)
1293 {
1294 /* Exactly one bit of MASK should be set. */
1295 if (mask == 0 || (mask & -mask) != mask)
1296 *invalid = 1;
1297 }
1298
1299 /* Check that non-power4 form of mfcr has a zero MASK. */
1300 else if ((insn & (0x3ff << 1)) == 19 << 1)
1301 {
1302 if (mask != 0)
1303 *invalid = 1;
1304 }
1305
1306 return mask;
1307 }
1308
1309 static unsigned long
1310 insert_li20 (unsigned long insn,
1311 long value,
1312 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1313 const char **errmsg ATTRIBUTE_UNUSED)
1314 {
1315 return insn | ((value & 0xf0000) >> 5) | ((value & 0x0f800) << 5) | (value & 0x7ff);
1316 }
1317
1318 static long
1319 extract_li20 (unsigned long insn,
1320 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1321 int *invalid ATTRIBUTE_UNUSED)
1322 {
1323 long ext = ((insn & 0x4000) == 0x4000) ? 0xfff00000 : 0x00000000;
1324
1325 return ext
1326 | (((insn >> 11) & 0xf) << 16)
1327 | (((insn >> 17) & 0xf) << 12)
1328 | (((insn >> 16) & 0x1) << 11)
1329 | (insn & 0x7ff);
1330 }
1331
1332 /* The LS field in a sync instruction that accepts 2 operands
1333 Values 2 and 3 are reserved,
1334 must be treated as 0 for future compatibility
1335 Values 0 and 1 can be accepted, if field ESYNC is zero
1336 Otherwise L = complement of ESYNC-bit2 (1<<18) */
1337
1338 static unsigned long
1339 insert_ls (unsigned long insn,
1340 long value,
1341 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1342 const char **errmsg ATTRIBUTE_UNUSED)
1343 {
1344 unsigned long ls;
1345
1346 ls = (insn >> 21) & 0x03;
1347 if (value == 0)
1348 {
1349 if (ls > 1)
1350 return insn & ~(0x3 << 21);
1351 return insn;
1352 }
1353 if ((value & 0x2) != 0)
1354 return (insn & ~(0x3 << 21)) | ((value & 0xf) << 16);
1355 return (insn & ~(0x3 << 21)) | (0x1 << 21) | ((value & 0xf) << 16);
1356 }
1357
1358 /* The MB and ME fields in an M form instruction expressed as a single
1359 operand which is itself a bitmask. The extraction function always
1360 marks it as invalid, since we never want to recognize an
1361 instruction which uses a field of this type. */
1362
1363 static unsigned long
1364 insert_mbe (unsigned long insn,
1365 long value,
1366 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1367 const char **errmsg)
1368 {
1369 unsigned long uval, mask;
1370 int mb, me, mx, count, last;
1371
1372 uval = value;
1373
1374 if (uval == 0)
1375 {
1376 *errmsg = _("illegal bitmask");
1377 return insn;
1378 }
1379
1380 mb = 0;
1381 me = 32;
1382 if ((uval & 1) != 0)
1383 last = 1;
1384 else
1385 last = 0;
1386 count = 0;
1387
1388 /* mb: location of last 0->1 transition */
1389 /* me: location of last 1->0 transition */
1390 /* count: # transitions */
1391
1392 for (mx = 0, mask = 1L << 31; mx < 32; ++mx, mask >>= 1)
1393 {
1394 if ((uval & mask) && !last)
1395 {
1396 ++count;
1397 mb = mx;
1398 last = 1;
1399 }
1400 else if (!(uval & mask) && last)
1401 {
1402 ++count;
1403 me = mx;
1404 last = 0;
1405 }
1406 }
1407 if (me == 0)
1408 me = 32;
1409
1410 if (count != 2 && (count != 0 || ! last))
1411 *errmsg = _("illegal bitmask");
1412
1413 return insn | (mb << 6) | ((me - 1) << 1);
1414 }
1415
1416 static long
1417 extract_mbe (unsigned long insn,
1418 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1419 int *invalid)
1420 {
1421 long ret;
1422 int mb, me;
1423 int i;
1424
1425 *invalid = 1;
1426
1427 mb = (insn >> 6) & 0x1f;
1428 me = (insn >> 1) & 0x1f;
1429 if (mb < me + 1)
1430 {
1431 ret = 0;
1432 for (i = mb; i <= me; i++)
1433 ret |= 1L << (31 - i);
1434 }
1435 else if (mb == me + 1)
1436 ret = ~0;
1437 else /* (mb > me + 1) */
1438 {
1439 ret = ~0;
1440 for (i = me + 1; i < mb; i++)
1441 ret &= ~(1L << (31 - i));
1442 }
1443 return ret;
1444 }
1445
1446 /* The MB or ME field in an MD or MDS form instruction. The high bit
1447 is wrapped to the low end. */
1448
1449 static unsigned long
1450 insert_mb6 (unsigned long insn,
1451 long value,
1452 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1453 const char **errmsg ATTRIBUTE_UNUSED)
1454 {
1455 return insn | ((value & 0x1f) << 6) | (value & 0x20);
1456 }
1457
1458 static long
1459 extract_mb6 (unsigned long insn,
1460 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1461 int *invalid ATTRIBUTE_UNUSED)
1462 {
1463 return ((insn >> 6) & 0x1f) | (insn & 0x20);
1464 }
1465
1466 /* The NB field in an X form instruction. The value 32 is stored as
1467 0. */
1468
1469 static long
1470 extract_nb (unsigned long insn,
1471 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1472 int *invalid ATTRIBUTE_UNUSED)
1473 {
1474 long ret;
1475
1476 ret = (insn >> 11) & 0x1f;
1477 if (ret == 0)
1478 ret = 32;
1479 return ret;
1480 }
1481
1482 /* The NB field in an lswi instruction, which has special value
1483 restrictions. The value 32 is stored as 0. */
1484
1485 static unsigned long
1486 insert_nbi (unsigned long insn,
1487 long value,
1488 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1489 const char **errmsg ATTRIBUTE_UNUSED)
1490 {
1491 long rtvalue = (insn & RT_MASK) >> 21;
1492 long ravalue = (insn & RA_MASK) >> 16;
1493
1494 if (value == 0)
1495 value = 32;
1496 if (rtvalue + (value + 3) / 4 > (rtvalue > ravalue ? ravalue + 32
1497 : ravalue))
1498 *errmsg = _("address register in load range");
1499 return insn | ((value & 0x1f) << 11);
1500 }
1501
1502 /* The NSI field in a D form instruction. This is the same as the SI
1503 field, only negated. The extraction function always marks it as
1504 invalid, since we never want to recognize an instruction which uses
1505 a field of this type. */
1506
1507 static unsigned long
1508 insert_nsi (unsigned long insn,
1509 long value,
1510 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1511 const char **errmsg ATTRIBUTE_UNUSED)
1512 {
1513 return insn | (-value & 0xffff);
1514 }
1515
1516 static long
1517 extract_nsi (unsigned long insn,
1518 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1519 int *invalid)
1520 {
1521 *invalid = 1;
1522 return -(((insn & 0xffff) ^ 0x8000) - 0x8000);
1523 }
1524
1525 /* The RA field in a D or X form instruction which is an updating
1526 load, which means that the RA field may not be zero and may not
1527 equal the RT field. */
1528
1529 static unsigned long
1530 insert_ral (unsigned long insn,
1531 long value,
1532 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1533 const char **errmsg)
1534 {
1535 if (value == 0
1536 || (unsigned long) value == ((insn >> 21) & 0x1f))
1537 *errmsg = "invalid register operand when updating";
1538 return insn | ((value & 0x1f) << 16);
1539 }
1540
1541 /* The RA field in an lmw instruction, which has special value
1542 restrictions. */
1543
1544 static unsigned long
1545 insert_ram (unsigned long insn,
1546 long value,
1547 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1548 const char **errmsg)
1549 {
1550 if ((unsigned long) value >= ((insn >> 21) & 0x1f))
1551 *errmsg = _("index register in load range");
1552 return insn | ((value & 0x1f) << 16);
1553 }
1554
1555 /* The RA field in the DQ form lq or an lswx instruction, which have special
1556 value restrictions. */
1557
1558 static unsigned long
1559 insert_raq (unsigned long insn,
1560 long value,
1561 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1562 const char **errmsg)
1563 {
1564 long rtvalue = (insn & RT_MASK) >> 21;
1565
1566 if (value == rtvalue)
1567 *errmsg = _("source and target register operands must be different");
1568 return insn | ((value & 0x1f) << 16);
1569 }
1570
1571 /* The RA field in a D or X form instruction which is an updating
1572 store or an updating floating point load, which means that the RA
1573 field may not be zero. */
1574
1575 static unsigned long
1576 insert_ras (unsigned long insn,
1577 long value,
1578 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1579 const char **errmsg)
1580 {
1581 if (value == 0)
1582 *errmsg = _("invalid register operand when updating");
1583 return insn | ((value & 0x1f) << 16);
1584 }
1585
1586 /* The RB field in an X form instruction when it must be the same as
1587 the RS field in the instruction. This is used for extended
1588 mnemonics like mr. This operand is marked FAKE. The insertion
1589 function just copies the BT field into the BA field, and the
1590 extraction function just checks that the fields are the same. */
1591
1592 static unsigned long
1593 insert_rbs (unsigned long insn,
1594 long value ATTRIBUTE_UNUSED,
1595 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1596 const char **errmsg ATTRIBUTE_UNUSED)
1597 {
1598 return insn | (((insn >> 21) & 0x1f) << 11);
1599 }
1600
1601 static long
1602 extract_rbs (unsigned long insn,
1603 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1604 int *invalid)
1605 {
1606 if (((insn >> 21) & 0x1f) != ((insn >> 11) & 0x1f))
1607 *invalid = 1;
1608 return 0;
1609 }
1610
1611 /* The RB field in an lswx instruction, which has special value
1612 restrictions. */
1613
1614 static unsigned long
1615 insert_rbx (unsigned long insn,
1616 long value,
1617 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1618 const char **errmsg)
1619 {
1620 long rtvalue = (insn & RT_MASK) >> 21;
1621
1622 if (value == rtvalue)
1623 *errmsg = _("source and target register operands must be different");
1624 return insn | ((value & 0x1f) << 11);
1625 }
1626
1627 /* The SCI8 field is made up of SCL and {U,N}I8 fields. */
1628 static unsigned long
1629 insert_sci8 (unsigned long insn,
1630 long value,
1631 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1632 const char **errmsg)
1633 {
1634 int fill = 0;
1635 int scale_factor = 0;
1636 long ui8 = value;
1637
1638 if ((value & 0xff000000) == (unsigned int) value)
1639 {
1640 scale_factor = 3;
1641 ui8 = value >> 24;
1642 fill = 0;
1643 }
1644 else if ((value & 0xff0000) == (unsigned int) value)
1645 {
1646 scale_factor = 2;
1647 ui8 = value >> 16;
1648 fill = 0;
1649 }
1650 else if ((value & 0xff00) == (unsigned int) value)
1651 {
1652 scale_factor = 1;
1653 ui8 = value >> 8;
1654 fill = 0;
1655 }
1656 else if ((value & 0xff) == value)
1657 {
1658 scale_factor = 0;
1659 ui8 = value;
1660 fill = 0;
1661 }
1662 else if ((value & 0xffffff00) == 0xffffff00)
1663 {
1664 scale_factor = 0;
1665 ui8 = (value & 0xff);
1666 fill = 1;
1667 }
1668 else if ((value & 0xffff00ff) == 0xffff00ff)
1669 {
1670 scale_factor = 1;
1671 ui8 = (value & 0xff00) >> 8;
1672 fill = 1;
1673 }
1674 else if ((value & 0xff00ffff) == 0xff00ffff)
1675 {
1676 scale_factor = 2;
1677 ui8 = (value & 0xff0000) >> 16;
1678 fill = 1;
1679 }
1680 else if ((value & 0x00ffffff) == 0x00ffffff)
1681 {
1682 scale_factor = 3;
1683 ui8 = (value & 0xff000000) >> 24;
1684 fill = 1;
1685 }
1686 else
1687 *errmsg = _("illegal immediate value");
1688
1689 return insn | (fill << 10) | (scale_factor << 8) | (ui8 & 0xff);
1690 }
1691
1692 static long
1693 extract_sci8 (unsigned long insn,
1694 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1695 int *invalid ATTRIBUTE_UNUSED)
1696 {
1697 int scale_factor, fill;
1698 scale_factor = (insn & 0x300) >> 8;
1699 fill = (insn & 0x00000400) >> 10;
1700
1701 if (fill == 0)
1702 return (insn & 0xff) << (scale_factor << 3);
1703
1704 /* Fill is one. */
1705 if (scale_factor == 0)
1706 return (insn & 0xff) | 0xffffff00;
1707 else if (scale_factor == 1)
1708 return 0xffff00ff | ((insn & 0xff) << (scale_factor << 3));
1709 else if (scale_factor == 2)
1710 return 0xff00ffff | (insn & 0xff << (scale_factor << 3));
1711 else /* scale_factor 3 */
1712 return 0x00ffffff | (insn & 0xff << (scale_factor << 3));
1713 }
1714
1715 static unsigned long
1716 insert_sci8n (unsigned long insn,
1717 long value,
1718 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1719 const char **errmsg)
1720 {
1721 insn = insert_sci8 (insn, -(value & 0xff) & 0xff, 0, errmsg);
1722 /* Set the F bit. */
1723 return insn | 0x400;
1724 }
1725
1726 static long
1727 extract_sci8n (unsigned long insn,
1728 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1729 int *invalid ATTRIBUTE_UNUSED)
1730 {
1731 int scale_factor;
1732 scale_factor = (insn & 0x300) >> 8;
1733 return -(((insn & 0xff) ^ 0x80) - 0x80) << (scale_factor << 3);
1734 }
1735
1736 static unsigned long
1737 insert_sd4h (unsigned long insn,
1738 long value,
1739 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1740 const char **errmsg ATTRIBUTE_UNUSED)
1741 {
1742 return insn | ((value & 0x1e) << 7);
1743 }
1744
1745 static long
1746 extract_sd4h (unsigned long insn,
1747 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1748 int *invalid ATTRIBUTE_UNUSED)
1749 {
1750 return ((insn >> 8) & 0xf) << 1;
1751 }
1752
1753 static unsigned long
1754 insert_sd4w (unsigned long insn,
1755 long value,
1756 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1757 const char **errmsg ATTRIBUTE_UNUSED)
1758 {
1759 return insn | ((value & 0x3c) << 6);
1760 }
1761
1762 static long
1763 extract_sd4w (unsigned long insn,
1764 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1765 int *invalid ATTRIBUTE_UNUSED)
1766 {
1767 return ((insn >> 8) & 0xf) << 2;
1768 }
1769
1770 static unsigned long
1771 insert_oimm (unsigned long insn,
1772 long value,
1773 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1774 const char **errmsg ATTRIBUTE_UNUSED)
1775 {
1776 return insn | (((value - 1) & 0x1f) << 4);
1777 }
1778
1779 static long
1780 extract_oimm (unsigned long insn,
1781 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1782 int *invalid ATTRIBUTE_UNUSED)
1783 {
1784 return ((insn >> 4) & 0x1f) + 1;
1785 }
1786
1787 /* The SH field in an MD form instruction. This is split. */
1788
1789 static unsigned long
1790 insert_sh6 (unsigned long insn,
1791 long value,
1792 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1793 const char **errmsg ATTRIBUTE_UNUSED)
1794 {
1795 return insn | ((value & 0x1f) << 11) | ((value & 0x20) >> 4);
1796 }
1797
1798 static long
1799 extract_sh6 (unsigned long insn,
1800 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1801 int *invalid ATTRIBUTE_UNUSED)
1802 {
1803 return ((insn >> 11) & 0x1f) | ((insn << 4) & 0x20);
1804 }
1805
1806 /* The SPR field in an XFX form instruction. This is flipped--the
1807 lower 5 bits are stored in the upper 5 and vice- versa. */
1808
1809 static unsigned long
1810 insert_spr (unsigned long insn,
1811 long value,
1812 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1813 const char **errmsg ATTRIBUTE_UNUSED)
1814 {
1815 return insn | ((value & 0x1f) << 16) | ((value & 0x3e0) << 6);
1816 }
1817
1818 static long
1819 extract_spr (unsigned long insn,
1820 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1821 int *invalid ATTRIBUTE_UNUSED)
1822 {
1823 return ((insn >> 16) & 0x1f) | ((insn >> 6) & 0x3e0);
1824 }
1825
1826 /* Some dialects have 8 SPRG registers instead of the standard 4. */
1827 #define ALLOW8_SPRG (PPC_OPCODE_BOOKE | PPC_OPCODE_405 | PPC_OPCODE_VLE)
1828
1829 static unsigned long
1830 insert_sprg (unsigned long insn,
1831 long value,
1832 ppc_cpu_t dialect,
1833 const char **errmsg)
1834 {
1835 if (value > 7
1836 || (value > 3 && (dialect & ALLOW8_SPRG) == 0))
1837 *errmsg = _("invalid sprg number");
1838
1839 /* If this is mfsprg4..7 then use spr 260..263 which can be read in
1840 user mode. Anything else must use spr 272..279. */
1841 if (value <= 3 || (insn & 0x100) != 0)
1842 value |= 0x10;
1843
1844 return insn | ((value & 0x17) << 16);
1845 }
1846
1847 static long
1848 extract_sprg (unsigned long insn,
1849 ppc_cpu_t dialect,
1850 int *invalid)
1851 {
1852 unsigned long val = (insn >> 16) & 0x1f;
1853
1854 /* mfsprg can use 260..263 and 272..279. mtsprg only uses spr 272..279
1855 If not BOOKE, 405 or VLE, then both use only 272..275. */
1856 if ((val - 0x10 > 3 && (dialect & ALLOW8_SPRG) == 0)
1857 || (val - 0x10 > 7 && (insn & 0x100) != 0)
1858 || val <= 3
1859 || (val & 8) != 0)
1860 *invalid = 1;
1861 return val & 7;
1862 }
1863
1864 /* The TBR field in an XFX instruction. This is just like SPR, but it
1865 is optional. When TBR is omitted, it must be inserted as 268 (the
1866 magic number of the TB register). These functions treat 0
1867 (indicating an omitted optional operand) as 268. This means that
1868 ``mftb 4,0'' is not handled correctly. This does not matter very
1869 much, since the architecture manual does not define mftb as
1870 accepting any values other than 268 or 269. */
1871
1872 #define TB (268)
1873
1874 static unsigned long
1875 insert_tbr (unsigned long insn,
1876 long value,
1877 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1878 const char **errmsg ATTRIBUTE_UNUSED)
1879 {
1880 if (value == 0)
1881 value = TB;
1882 return insn | ((value & 0x1f) << 16) | ((value & 0x3e0) << 6);
1883 }
1884
1885 static long
1886 extract_tbr (unsigned long insn,
1887 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1888 int *invalid ATTRIBUTE_UNUSED)
1889 {
1890 long ret;
1891
1892 ret = ((insn >> 16) & 0x1f) | ((insn >> 6) & 0x3e0);
1893 if (ret == TB)
1894 ret = 0;
1895 return ret;
1896 }
1897
1898 /* The XT and XS fields in an XX1 or XX3 form instruction. This is split. */
1899
1900 static unsigned long
1901 insert_xt6 (unsigned long insn,
1902 long value,
1903 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1904 const char **errmsg ATTRIBUTE_UNUSED)
1905 {
1906 return insn | ((value & 0x1f) << 21) | ((value & 0x20) >> 5);
1907 }
1908
1909 static long
1910 extract_xt6 (unsigned long insn,
1911 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1912 int *invalid ATTRIBUTE_UNUSED)
1913 {
1914 return ((insn << 5) & 0x20) | ((insn >> 21) & 0x1f);
1915 }
1916
1917 /* The XA field in an XX3 form instruction. This is split. */
1918
1919 static unsigned long
1920 insert_xa6 (unsigned long insn,
1921 long value,
1922 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1923 const char **errmsg ATTRIBUTE_UNUSED)
1924 {
1925 return insn | ((value & 0x1f) << 16) | ((value & 0x20) >> 3);
1926 }
1927
1928 static long
1929 extract_xa6 (unsigned long insn,
1930 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1931 int *invalid ATTRIBUTE_UNUSED)
1932 {
1933 return ((insn << 3) & 0x20) | ((insn >> 16) & 0x1f);
1934 }
1935
1936 /* The XB field in an XX3 form instruction. This is split. */
1937
1938 static unsigned long
1939 insert_xb6 (unsigned long insn,
1940 long value,
1941 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1942 const char **errmsg ATTRIBUTE_UNUSED)
1943 {
1944 return insn | ((value & 0x1f) << 11) | ((value & 0x20) >> 4);
1945 }
1946
1947 static long
1948 extract_xb6 (unsigned long insn,
1949 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1950 int *invalid ATTRIBUTE_UNUSED)
1951 {
1952 return ((insn << 4) & 0x20) | ((insn >> 11) & 0x1f);
1953 }
1954
1955 /* The XB field in an XX3 form instruction when it must be the same as
1956 the XA field in the instruction. This is used for extended
1957 mnemonics like xvmovdp. This operand is marked FAKE. The insertion
1958 function just copies the XA field into the XB field, and the
1959 extraction function just checks that the fields are the same. */
1960
1961 static unsigned long
1962 insert_xb6s (unsigned long insn,
1963 long value ATTRIBUTE_UNUSED,
1964 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1965 const char **errmsg ATTRIBUTE_UNUSED)
1966 {
1967 return insn | (((insn >> 16) & 0x1f) << 11) | (((insn >> 2) & 0x1) << 1);
1968 }
1969
1970 static long
1971 extract_xb6s (unsigned long insn,
1972 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1973 int *invalid)
1974 {
1975 if ((((insn >> 16) & 0x1f) != ((insn >> 11) & 0x1f))
1976 || (((insn >> 2) & 0x1) != ((insn >> 1) & 0x1)))
1977 *invalid = 1;
1978 return 0;
1979 }
1980
1981 /* The XC field in an XX4 form instruction. This is split. */
1982
1983 static unsigned long
1984 insert_xc6 (unsigned long insn,
1985 long value,
1986 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1987 const char **errmsg ATTRIBUTE_UNUSED)
1988 {
1989 return insn | ((value & 0x1f) << 6) | ((value & 0x20) >> 2);
1990 }
1991
1992 static long
1993 extract_xc6 (unsigned long insn,
1994 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1995 int *invalid ATTRIBUTE_UNUSED)
1996 {
1997 return ((insn << 2) & 0x20) | ((insn >> 6) & 0x1f);
1998 }
1999
2000 static unsigned long
2001 insert_dm (unsigned long insn,
2002 long value,
2003 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2004 const char **errmsg)
2005 {
2006 if (value != 0 && value != 1)
2007 *errmsg = _("invalid constant");
2008 return insn | (((value) ? 3 : 0) << 8);
2009 }
2010
2011 static long
2012 extract_dm (unsigned long insn,
2013 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2014 int *invalid)
2015 {
2016 long value;
2017
2018 value = (insn >> 8) & 3;
2019 if (value != 0 && value != 3)
2020 *invalid = 1;
2021 return (value) ? 1 : 0;
2022 }
2023 /* The VLESIMM field in an I16A form instruction. This is split. */
2024
2025 static unsigned long
2026 insert_vlesi (unsigned long insn,
2027 long value,
2028 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2029 const char **errmsg ATTRIBUTE_UNUSED)
2030 {
2031 return insn | ((value & 0xf800) << 10) | (value & 0x7ff);
2032 }
2033
2034 static long
2035 extract_vlesi (unsigned long insn,
2036 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2037 int *invalid ATTRIBUTE_UNUSED)
2038 {
2039 /* RWRW Because I don't know how to make int be 16 and long be 32 */
2040 /* I can't rely on casting an int to long to get sign extension. */
2041 long value = ((insn >> 10) & 0xf800) | (insn & 0x7ff);
2042 if (value & 0x8000)
2043 value |= 0xffff0000;
2044 return value;
2045 }
2046
2047 static unsigned long
2048 insert_vlensi (unsigned long insn,
2049 long value,
2050 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2051 const char **errmsg ATTRIBUTE_UNUSED)
2052 {
2053 value = -value;
2054 return insn | ((value & 0xf800) << 10) | (value & 0x7ff);
2055 }
2056 static long
2057 extract_vlensi (unsigned long insn,
2058 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2059 int *invalid ATTRIBUTE_UNUSED)
2060 {
2061 long value = ((insn >> 10) & 0xf800) | (insn & 0x7ff);
2062 if (value & 0x8000)
2063 value |= 0xffff0000;
2064 *invalid = 1;
2065 return -value;
2066 }
2067
2068 /* The VLEUIMM field in an I16A form instruction. This is split. */
2069
2070 static unsigned long
2071 insert_vleui (unsigned long insn,
2072 long value,
2073 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2074 const char **errmsg ATTRIBUTE_UNUSED)
2075 {
2076 return insn | ((value & 0xf800) << 10) | (value & 0x7ff);
2077 }
2078
2079 static long
2080 extract_vleui (unsigned long insn,
2081 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2082 int *invalid ATTRIBUTE_UNUSED)
2083 {
2084 return ((insn >> 10) & 0xf800) | (insn & 0x7ff);
2085 }
2086
2087 /* The VLEUIMML field in an I16L form instruction. This is split. */
2088
2089 static unsigned long
2090 insert_vleil (unsigned long insn,
2091 long value,
2092 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2093 const char **errmsg ATTRIBUTE_UNUSED)
2094 {
2095 return insn | ((value & 0xf800) << 5) | (value & 0x7ff);
2096 }
2097
2098 static long
2099 extract_vleil (unsigned long insn,
2100 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2101 int *invalid ATTRIBUTE_UNUSED)
2102 {
2103 return ((insn >> 5) & 0xf800) | (insn & 0x7ff);
2104 }
2105
2106 \f
2107 /* Macros used to form opcodes. */
2108
2109 /* The main opcode. */
2110 #define OP(x) ((((unsigned long)(x)) & 0x3f) << 26)
2111 #define OP_MASK OP (0x3f)
2112
2113 /* The main opcode combined with a trap code in the TO field of a D
2114 form instruction. Used for extended mnemonics for the trap
2115 instructions. */
2116 #define OPTO(x,to) (OP (x) | ((((unsigned long)(to)) & 0x1f) << 21))
2117 #define OPTO_MASK (OP_MASK | TO_MASK)
2118
2119 /* The main opcode combined with a comparison size bit in the L field
2120 of a D form or X form instruction. Used for extended mnemonics for
2121 the comparison instructions. */
2122 #define OPL(x,l) (OP (x) | ((((unsigned long)(l)) & 1) << 21))
2123 #define OPL_MASK OPL (0x3f,1)
2124
2125 /* The main opcode combined with an update code in D form instruction.
2126 Used for extended mnemonics for VLE memory instructions. */
2127 #define OPVUP(x,vup) (OP (x) | ((((unsigned long)(vup)) & 0xff) << 8))
2128 #define OPVUP_MASK OPVUP (0x3f, 0xff)
2129
2130 /* An A form instruction. */
2131 #define A(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0x1f) << 1) | (((unsigned long)(rc)) & 1))
2132 #define A_MASK A (0x3f, 0x1f, 1)
2133
2134 /* An A_MASK with the FRB field fixed. */
2135 #define AFRB_MASK (A_MASK | FRB_MASK)
2136
2137 /* An A_MASK with the FRC field fixed. */
2138 #define AFRC_MASK (A_MASK | FRC_MASK)
2139
2140 /* An A_MASK with the FRA and FRC fields fixed. */
2141 #define AFRAFRC_MASK (A_MASK | FRA_MASK | FRC_MASK)
2142
2143 /* An AFRAFRC_MASK, but with L bit clear. */
2144 #define AFRALFRC_MASK (AFRAFRC_MASK & ~((unsigned long) 1 << 16))
2145
2146 /* A B form instruction. */
2147 #define B(op, aa, lk) (OP (op) | ((((unsigned long)(aa)) & 1) << 1) | ((lk) & 1))
2148 #define B_MASK B (0x3f, 1, 1)
2149
2150 /* A BD8 form instruction. This is a 16-bit instruction. */
2151 #define BD8(op, aa, lk) (((((unsigned long)(op)) & 0x3f) << 10) | (((aa) & 1) << 9) | (((lk) & 1) << 8))
2152 #define BD8_MASK BD8 (0x3f, 1, 1)
2153
2154 /* Another BD8 form instruction. This is a 16-bit instruction. */
2155 #define BD8IO(op) ((((unsigned long)(op)) & 0x1f) << 11)
2156 #define BD8IO_MASK BD8IO (0x1f)
2157
2158 /* A BD8 form instruction for simplified mnemonics. */
2159 #define EBD8IO(op, bo, bi) (BD8IO ((op)) | ((bo) << 10) | ((bi) << 8))
2160 /* A mask that excludes BO32 and BI32. */
2161 #define EBD8IO1_MASK 0xf800
2162 /* A mask that includes BO32 and excludes BI32. */
2163 #define EBD8IO2_MASK 0xfc00
2164 /* A mask that include BO32 AND BI32. */
2165 #define EBD8IO3_MASK 0xff00
2166
2167 /* A BD15 form instruction. */
2168 #define BD15(op, aa, lk) (OP (op) | ((((unsigned long)(aa)) & 0xf) << 22) | ((lk) & 1))
2169 #define BD15_MASK BD15 (0x3f, 0xf, 1)
2170
2171 /* A BD15 form instruction for extended conditional branch mnemonics. */
2172 #define EBD15(op, aa, bo, lk) (((op) & 0x3f) << 26) | (((aa) & 0xf) << 22) | (((bo) & 0x3) << 20) | ((lk) & 1)
2173 #define EBD15_MASK 0xfff00001
2174
2175 /* A BD15 form instruction for extended conditional branch mnemonics with BI. */
2176 #define EBD15BI(op, aa, bo, bi, lk) (((op) & 0x3f) << 26) \
2177 | (((aa) & 0xf) << 22) \
2178 | (((bo) & 0x3) << 20) \
2179 | (((bi) & 0x3) << 16) \
2180 | ((lk) & 1)
2181 #define EBD15BI_MASK 0xfff30001
2182
2183 /* A BD24 form instruction. */
2184 #define BD24(op, aa, lk) (OP (op) | ((((unsigned long)(aa)) & 1) << 25) | ((lk) & 1))
2185 #define BD24_MASK BD24 (0x3f, 1, 1)
2186
2187 /* A B form instruction setting the BO field. */
2188 #define BBO(op, bo, aa, lk) (B ((op), (aa), (lk)) | ((((unsigned long)(bo)) & 0x1f) << 21))
2189 #define BBO_MASK BBO (0x3f, 0x1f, 1, 1)
2190
2191 /* A BBO_MASK with the y bit of the BO field removed. This permits
2192 matching a conditional branch regardless of the setting of the y
2193 bit. Similarly for the 'at' bits used for power4 branch hints. */
2194 #define Y_MASK (((unsigned long) 1) << 21)
2195 #define AT1_MASK (((unsigned long) 3) << 21)
2196 #define AT2_MASK (((unsigned long) 9) << 21)
2197 #define BBOY_MASK (BBO_MASK &~ Y_MASK)
2198 #define BBOAT_MASK (BBO_MASK &~ AT1_MASK)
2199
2200 /* A B form instruction setting the BO field and the condition bits of
2201 the BI field. */
2202 #define BBOCB(op, bo, cb, aa, lk) \
2203 (BBO ((op), (bo), (aa), (lk)) | ((((unsigned long)(cb)) & 0x3) << 16))
2204 #define BBOCB_MASK BBOCB (0x3f, 0x1f, 0x3, 1, 1)
2205
2206 /* A BBOCB_MASK with the y bit of the BO field removed. */
2207 #define BBOYCB_MASK (BBOCB_MASK &~ Y_MASK)
2208 #define BBOATCB_MASK (BBOCB_MASK &~ AT1_MASK)
2209 #define BBOAT2CB_MASK (BBOCB_MASK &~ AT2_MASK)
2210
2211 /* A BBOYCB_MASK in which the BI field is fixed. */
2212 #define BBOYBI_MASK (BBOYCB_MASK | BI_MASK)
2213 #define BBOATBI_MASK (BBOAT2CB_MASK | BI_MASK)
2214
2215 /* A VLE C form instruction. */
2216 #define C_LK(x, lk) (((((unsigned long)(x)) & 0x7fff) << 1) | ((lk) & 1))
2217 #define C_LK_MASK C_LK(0x7fff, 1)
2218 #define C(x) ((((unsigned long)(x)) & 0xffff))
2219 #define C_MASK C(0xffff)
2220
2221 /* An Context form instruction. */
2222 #define CTX(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x7))
2223 #define CTX_MASK CTX(0x3f, 0x7)
2224
2225 /* An User Context form instruction. */
2226 #define UCTX(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x1f))
2227 #define UCTX_MASK UCTX(0x3f, 0x1f)
2228
2229 /* The main opcode mask with the RA field clear. */
2230 #define DRA_MASK (OP_MASK | RA_MASK)
2231
2232 /* A DS form instruction. */
2233 #define DSO(op, xop) (OP (op) | ((xop) & 0x3))
2234 #define DS_MASK DSO (0x3f, 3)
2235
2236 /* An EVSEL form instruction. */
2237 #define EVSEL(op, xop) (OP (op) | (((unsigned long)(xop)) & 0xff) << 3)
2238 #define EVSEL_MASK EVSEL(0x3f, 0xff)
2239
2240 /* An IA16 form instruction. */
2241 #define IA16(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x1f) << 11)
2242 #define IA16_MASK IA16(0x3f, 0x1f)
2243
2244 /* An I16A form instruction. */
2245 #define I16A(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x1f) << 11)
2246 #define I16A_MASK I16A(0x3f, 0x1f)
2247
2248 /* An I16L form instruction. */
2249 #define I16L(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x1f) << 11)
2250 #define I16L_MASK I16L(0x3f, 0x1f)
2251
2252 /* An IM7 form instruction. */
2253 #define IM7(op) ((((unsigned long)(op)) & 0x1f) << 11)
2254 #define IM7_MASK IM7(0x1f)
2255
2256 /* An M form instruction. */
2257 #define M(op, rc) (OP (op) | ((rc) & 1))
2258 #define M_MASK M (0x3f, 1)
2259
2260 /* An LI20 form instruction. */
2261 #define LI20(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x1) << 15)
2262 #define LI20_MASK LI20(0x3f, 0x1)
2263
2264 /* An M form instruction with the ME field specified. */
2265 #define MME(op, me, rc) (M ((op), (rc)) | ((((unsigned long)(me)) & 0x1f) << 1))
2266
2267 /* An M_MASK with the MB and ME fields fixed. */
2268 #define MMBME_MASK (M_MASK | MB_MASK | ME_MASK)
2269
2270 /* An M_MASK with the SH and ME fields fixed. */
2271 #define MSHME_MASK (M_MASK | SH_MASK | ME_MASK)
2272
2273 /* An MD form instruction. */
2274 #define MD(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0x7) << 2) | ((rc) & 1))
2275 #define MD_MASK MD (0x3f, 0x7, 1)
2276
2277 /* An MD_MASK with the MB field fixed. */
2278 #define MDMB_MASK (MD_MASK | MB6_MASK)
2279
2280 /* An MD_MASK with the SH field fixed. */
2281 #define MDSH_MASK (MD_MASK | SH6_MASK)
2282
2283 /* An MDS form instruction. */
2284 #define MDS(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0xf) << 1) | ((rc) & 1))
2285 #define MDS_MASK MDS (0x3f, 0xf, 1)
2286
2287 /* An MDS_MASK with the MB field fixed. */
2288 #define MDSMB_MASK (MDS_MASK | MB6_MASK)
2289
2290 /* An SC form instruction. */
2291 #define SC(op, sa, lk) (OP (op) | ((((unsigned long)(sa)) & 1) << 1) | ((lk) & 1))
2292 #define SC_MASK (OP_MASK | (((unsigned long)0x3ff) << 16) | (((unsigned long)1) << 1) | 1)
2293
2294 /* An SCI8 form instruction. */
2295 #define SCI8(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x1f) << 11))
2296 #define SCI8_MASK SCI8(0x3f, 0x1f)
2297
2298 /* An SCI8 form instruction. */
2299 #define SCI8BF(op, fop, xop) (OP (op) | ((((unsigned long)(xop)) & 0x1f) << 11) | (((fop) & 7) << 23))
2300 #define SCI8BF_MASK SCI8BF(0x3f, 7, 0x1f)
2301
2302 /* An SD4 form instruction. This is a 16-bit instruction. */
2303 #define SD4(op) ((((unsigned long)(op)) & 0xf) << 12)
2304 #define SD4_MASK SD4(0xf)
2305
2306 /* An SE_IM5 form instruction. This is a 16-bit instruction. */
2307 #define SE_IM5(op, xop) (((((unsigned long)(op)) & 0x3f) << 10) | (((xop) & 0x1) << 9))
2308 #define SE_IM5_MASK SE_IM5(0x3f, 1)
2309
2310 /* An SE_R form instruction. This is a 16-bit instruction. */
2311 #define SE_R(op, xop) (((((unsigned long)(op)) & 0x3f) << 10) | (((xop) & 0x3f) << 4))
2312 #define SE_R_MASK SE_R(0x3f, 0x3f)
2313
2314 /* An SE_RR form instruction. This is a 16-bit instruction. */
2315 #define SE_RR(op, xop) (((((unsigned long)(op)) & 0x3f) << 10) | (((xop) & 0x3) << 8))
2316 #define SE_RR_MASK SE_RR(0x3f, 3)
2317
2318 /* A VX form instruction. */
2319 #define VX(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x7ff))
2320
2321 /* The mask for an VX form instruction. */
2322 #define VX_MASK VX(0x3f, 0x7ff)
2323
2324 /* A VX_MASK with the VA field fixed. */
2325 #define VXVA_MASK (VX_MASK | (0x1f << 16))
2326
2327 /* A VX_MASK with the VB field fixed. */
2328 #define VXVB_MASK (VX_MASK | (0x1f << 11))
2329
2330 /* A VX_MASK with the VA and VB fields fixed. */
2331 #define VXVAVB_MASK (VX_MASK | (0x1f << 16) | (0x1f << 11))
2332
2333 /* A VX_MASK with the VD and VA fields fixed. */
2334 #define VXVDVA_MASK (VX_MASK | (0x1f << 21) | (0x1f << 16))
2335
2336 /* A VX_MASK with a UIMM4 field. */
2337 #define VXUIMM4_MASK (VX_MASK | (0x1 << 20))
2338
2339 /* A VX_MASK with a UIMM3 field. */
2340 #define VXUIMM3_MASK (VX_MASK | (0x3 << 19))
2341
2342 /* A VX_MASK with a UIMM2 field. */
2343 #define VXUIMM2_MASK (VX_MASK | (0x7 << 18))
2344
2345 /* A VA form instruction. */
2346 #define VXA(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x03f))
2347
2348 /* The mask for an VA form instruction. */
2349 #define VXA_MASK VXA(0x3f, 0x3f)
2350
2351 /* A VXR form instruction. */
2352 #define VXR(op, xop, rc) (OP (op) | (((rc) & 1) << 10) | (((unsigned long)(xop)) & 0x3ff))
2353
2354 /* The mask for a VXR form instruction. */
2355 #define VXR_MASK VXR(0x3f, 0x3ff, 1)
2356
2357 /* An X form instruction. */
2358 #define X(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x3ff) << 1))
2359
2360 /* An EX form instruction. */
2361 #define EX(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x7ff))
2362
2363 /* The mask for an EX form instruction. */
2364 #define EX_MASK EX (0x3f, 0x7ff)
2365
2366 /* An XX2 form instruction. */
2367 #define XX2(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x1ff) << 2))
2368
2369 /* An XX3 form instruction. */
2370 #define XX3(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0xff) << 3))
2371
2372 /* An XX3 form instruction with the RC bit specified. */
2373 #define XX3RC(op, xop, rc) (OP (op) | (((rc) & 1) << 10) | ((((unsigned long)(xop)) & 0x7f) << 3))
2374
2375 /* An XX4 form instruction. */
2376 #define XX4(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x3) << 4))
2377
2378 /* A Z form instruction. */
2379 #define Z(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x1ff) << 1))
2380
2381 /* An X form instruction with the RC bit specified. */
2382 #define XRC(op, xop, rc) (X ((op), (xop)) | ((rc) & 1))
2383
2384 /* A Z form instruction with the RC bit specified. */
2385 #define ZRC(op, xop, rc) (Z ((op), (xop)) | ((rc) & 1))
2386
2387 /* The mask for an X form instruction. */
2388 #define X_MASK XRC (0x3f, 0x3ff, 1)
2389
2390 /* An X form wait instruction with everything filled in except the WC field. */
2391 #define XWC_MASK (XRC (0x3f, 0x3ff, 1) | (7 << 23) | RA_MASK | RB_MASK)
2392
2393 /* The mask for an XX1 form instruction. */
2394 #define XX1_MASK X (0x3f, 0x3ff)
2395
2396 /* The mask for an XX2 form instruction. */
2397 #define XX2_MASK (XX2 (0x3f, 0x1ff) | (0x1f << 16))
2398
2399 /* The mask for an XX2 form instruction with the UIM bits specified. */
2400 #define XX2UIM_MASK (XX2 (0x3f, 0x1ff) | (7 << 18))
2401
2402 /* The mask for an XX2 form instruction with the BF bits specified. */
2403 #define XX2BF_MASK (XX2_MASK | (3 << 21) | (1))
2404
2405 /* The mask for an XX3 form instruction. */
2406 #define XX3_MASK XX3 (0x3f, 0xff)
2407
2408 /* The mask for an XX3 form instruction with the BF bits specified. */
2409 #define XX3BF_MASK (XX3 (0x3f, 0xff) | (3 << 21) | (1))
2410
2411 /* The mask for an XX3 form instruction with the DM or SHW bits specified. */
2412 #define XX3DM_MASK (XX3 (0x3f, 0x1f) | (1 << 10))
2413 #define XX3SHW_MASK XX3DM_MASK
2414
2415 /* The mask for an XX4 form instruction. */
2416 #define XX4_MASK XX4 (0x3f, 0x3)
2417
2418 /* An X form wait instruction with everything filled in except the WC field. */
2419 #define XWC_MASK (XRC (0x3f, 0x3ff, 1) | (7 << 23) | RA_MASK | RB_MASK)
2420
2421 /* The mask for a Z form instruction. */
2422 #define Z_MASK ZRC (0x3f, 0x1ff, 1)
2423 #define Z2_MASK ZRC (0x3f, 0xff, 1)
2424
2425 /* An X_MASK with the RA field fixed. */
2426 #define XRA_MASK (X_MASK | RA_MASK)
2427
2428 /* An XRA_MASK with the W field clear. */
2429 #define XWRA_MASK (XRA_MASK & ~((unsigned long) 1 << 16))
2430
2431 /* An X_MASK with the RB field fixed. */
2432 #define XRB_MASK (X_MASK | RB_MASK)
2433
2434 /* An X_MASK with the RT field fixed. */
2435 #define XRT_MASK (X_MASK | RT_MASK)
2436
2437 /* An XRT_MASK mask with the L bits clear. */
2438 #define XLRT_MASK (XRT_MASK & ~((unsigned long) 0x3 << 21))
2439
2440 /* An X_MASK with the RA and RB fields fixed. */
2441 #define XRARB_MASK (X_MASK | RA_MASK | RB_MASK)
2442
2443 /* An XRARB_MASK, but with the L bit clear. */
2444 #define XRLARB_MASK (XRARB_MASK & ~((unsigned long) 1 << 16))
2445
2446 /* An X_MASK with the RT and RA fields fixed. */
2447 #define XRTRA_MASK (X_MASK | RT_MASK | RA_MASK)
2448
2449 /* An XRTRA_MASK, but with L bit clear. */
2450 #define XRTLRA_MASK (XRTRA_MASK & ~((unsigned long) 1 << 21))
2451
2452 /* An X form instruction with the L bit specified. */
2453 #define XOPL(op, xop, l) (X ((op), (xop)) | ((((unsigned long)(l)) & 1) << 21))
2454
2455 /* An X form instruction with the L bits specified. */
2456 #define XOPL2(op, xop, l) (X ((op), (xop)) | ((((unsigned long)(l)) & 3) << 21))
2457
2458 /* An X form instruction with RT fields specified */
2459 #define XRT(op, xop, rt) (X ((op), (xop)) \
2460 | ((((unsigned long)(rt)) & 0x1f) << 21))
2461
2462 /* An X form instruction with RT and RA fields specified */
2463 #define XRTRA(op, xop, rt, ra) (X ((op), (xop)) \
2464 | ((((unsigned long)(rt)) & 0x1f) << 21) \
2465 | ((((unsigned long)(ra)) & 0x1f) << 16))
2466
2467 /* The mask for an X form comparison instruction. */
2468 #define XCMP_MASK (X_MASK | (((unsigned long)1) << 22))
2469
2470 /* The mask for an X form comparison instruction with the L field
2471 fixed. */
2472 #define XCMPL_MASK (XCMP_MASK | (((unsigned long)1) << 21))
2473
2474 /* An X form trap instruction with the TO field specified. */
2475 #define XTO(op, xop, to) (X ((op), (xop)) | ((((unsigned long)(to)) & 0x1f) << 21))
2476 #define XTO_MASK (X_MASK | TO_MASK)
2477
2478 /* An X form tlb instruction with the SH field specified. */
2479 #define XTLB(op, xop, sh) (X ((op), (xop)) | ((((unsigned long)(sh)) & 0x1f) << 11))
2480 #define XTLB_MASK (X_MASK | SH_MASK)
2481
2482 /* An X form sync instruction. */
2483 #define XSYNC(op, xop, l) (X ((op), (xop)) | ((((unsigned long)(l)) & 3) << 21))
2484
2485 /* An X form sync instruction with everything filled in except the LS field. */
2486 #define XSYNC_MASK (0xff9fffff)
2487
2488 /* An X form sync instruction with everything filled in except the L and E fields. */
2489 #define XSYNCLE_MASK (0xff90ffff)
2490
2491 /* An X_MASK, but with the EH bit clear. */
2492 #define XEH_MASK (X_MASK & ~((unsigned long )1))
2493
2494 /* An X form AltiVec dss instruction. */
2495 #define XDSS(op, xop, a) (X ((op), (xop)) | ((((unsigned long)(a)) & 1) << 25))
2496 #define XDSS_MASK XDSS(0x3f, 0x3ff, 1)
2497
2498 /* An XFL form instruction. */
2499 #define XFL(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0x3ff) << 1) | (((unsigned long)(rc)) & 1))
2500 #define XFL_MASK XFL (0x3f, 0x3ff, 1)
2501
2502 /* An X form isel instruction. */
2503 #define XISEL(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x1f) << 1))
2504 #define XISEL_MASK XISEL(0x3f, 0x1f)
2505
2506 /* An XL form instruction with the LK field set to 0. */
2507 #define XL(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x3ff) << 1))
2508
2509 /* An XL form instruction which uses the LK field. */
2510 #define XLLK(op, xop, lk) (XL ((op), (xop)) | ((lk) & 1))
2511
2512 /* The mask for an XL form instruction. */
2513 #define XL_MASK XLLK (0x3f, 0x3ff, 1)
2514
2515 /* An XL form instruction which explicitly sets the BO field. */
2516 #define XLO(op, bo, xop, lk) \
2517 (XLLK ((op), (xop), (lk)) | ((((unsigned long)(bo)) & 0x1f) << 21))
2518 #define XLO_MASK (XL_MASK | BO_MASK)
2519
2520 /* An XL form instruction which explicitly sets the y bit of the BO
2521 field. */
2522 #define XLYLK(op, xop, y, lk) (XLLK ((op), (xop), (lk)) | ((((unsigned long)(y)) & 1) << 21))
2523 #define XLYLK_MASK (XL_MASK | Y_MASK)
2524
2525 /* An XL form instruction which sets the BO field and the condition
2526 bits of the BI field. */
2527 #define XLOCB(op, bo, cb, xop, lk) \
2528 (XLO ((op), (bo), (xop), (lk)) | ((((unsigned long)(cb)) & 3) << 16))
2529 #define XLOCB_MASK XLOCB (0x3f, 0x1f, 0x3, 0x3ff, 1)
2530
2531 /* An XL_MASK or XLYLK_MASK or XLOCB_MASK with the BB field fixed. */
2532 #define XLBB_MASK (XL_MASK | BB_MASK)
2533 #define XLYBB_MASK (XLYLK_MASK | BB_MASK)
2534 #define XLBOCBBB_MASK (XLOCB_MASK | BB_MASK)
2535
2536 /* A mask for branch instructions using the BH field. */
2537 #define XLBH_MASK (XL_MASK | (0x1c << 11))
2538
2539 /* An XL_MASK with the BO and BB fields fixed. */
2540 #define XLBOBB_MASK (XL_MASK | BO_MASK | BB_MASK)
2541
2542 /* An XL_MASK with the BO, BI and BB fields fixed. */
2543 #define XLBOBIBB_MASK (XL_MASK | BO_MASK | BI_MASK | BB_MASK)
2544
2545 /* An X form mbar instruction with MO field. */
2546 #define XMBAR(op, xop, mo) (X ((op), (xop)) | ((((unsigned long)(mo)) & 1) << 21))
2547
2548 /* An XO form instruction. */
2549 #define XO(op, xop, oe, rc) \
2550 (OP (op) | ((((unsigned long)(xop)) & 0x1ff) << 1) | ((((unsigned long)(oe)) & 1) << 10) | (((unsigned long)(rc)) & 1))
2551 #define XO_MASK XO (0x3f, 0x1ff, 1, 1)
2552
2553 /* An XO_MASK with the RB field fixed. */
2554 #define XORB_MASK (XO_MASK | RB_MASK)
2555
2556 /* An XOPS form instruction for paired singles. */
2557 #define XOPS(op, xop, rc) \
2558 (OP (op) | ((((unsigned long)(xop)) & 0x3ff) << 1) | (((unsigned long)(rc)) & 1))
2559 #define XOPS_MASK XOPS (0x3f, 0x3ff, 1)
2560
2561
2562 /* An XS form instruction. */
2563 #define XS(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0x1ff) << 2) | (((unsigned long)(rc)) & 1))
2564 #define XS_MASK XS (0x3f, 0x1ff, 1)
2565
2566 /* A mask for the FXM version of an XFX form instruction. */
2567 #define XFXFXM_MASK (X_MASK | (1 << 11) | (1 << 20))
2568
2569 /* An XFX form instruction with the FXM field filled in. */
2570 #define XFXM(op, xop, fxm, p4) \
2571 (X ((op), (xop)) | ((((unsigned long)(fxm)) & 0xff) << 12) \
2572 | ((unsigned long)(p4) << 20))
2573
2574 /* An XFX form instruction with the SPR field filled in. */
2575 #define XSPR(op, xop, spr) \
2576 (X ((op), (xop)) | ((((unsigned long)(spr)) & 0x1f) << 16) | ((((unsigned long)(spr)) & 0x3e0) << 6))
2577 #define XSPR_MASK (X_MASK | SPR_MASK)
2578
2579 /* An XFX form instruction with the SPR field filled in except for the
2580 SPRBAT field. */
2581 #define XSPRBAT_MASK (XSPR_MASK &~ SPRBAT_MASK)
2582
2583 /* An XFX form instruction with the SPR field filled in except for the
2584 SPRG field. */
2585 #define XSPRG_MASK (XSPR_MASK & ~(0x1f << 16))
2586
2587 /* An X form instruction with everything filled in except the E field. */
2588 #define XE_MASK (0xffff7fff)
2589
2590 /* An X form user context instruction. */
2591 #define XUC(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x1f))
2592 #define XUC_MASK XUC(0x3f, 0x1f)
2593
2594 /* An XW form instruction. */
2595 #define XW(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0x3f) << 1) | ((rc) & 1))
2596 /* The mask for a G form instruction. rc not supported at present. */
2597 #define XW_MASK XW (0x3f, 0x3f, 0)
2598
2599 /* An APU form instruction. */
2600 #define APU(op, xop, rc) (OP (op) | (((unsigned long)(xop)) & 0x3ff) << 1 | ((rc) & 1))
2601
2602 /* The mask for an APU form instruction. */
2603 #define APU_MASK APU (0x3f, 0x3ff, 1)
2604 #define APU_RT_MASK (APU_MASK | RT_MASK)
2605 #define APU_RA_MASK (APU_MASK | RA_MASK)
2606
2607 /* The BO encodings used in extended conditional branch mnemonics. */
2608 #define BODNZF (0x0)
2609 #define BODNZFP (0x1)
2610 #define BODZF (0x2)
2611 #define BODZFP (0x3)
2612 #define BODNZT (0x8)
2613 #define BODNZTP (0x9)
2614 #define BODZT (0xa)
2615 #define BODZTP (0xb)
2616
2617 #define BOF (0x4)
2618 #define BOFP (0x5)
2619 #define BOFM4 (0x6)
2620 #define BOFP4 (0x7)
2621 #define BOT (0xc)
2622 #define BOTP (0xd)
2623 #define BOTM4 (0xe)
2624 #define BOTP4 (0xf)
2625
2626 #define BODNZ (0x10)
2627 #define BODNZP (0x11)
2628 #define BODZ (0x12)
2629 #define BODZP (0x13)
2630 #define BODNZM4 (0x18)
2631 #define BODNZP4 (0x19)
2632 #define BODZM4 (0x1a)
2633 #define BODZP4 (0x1b)
2634
2635 #define BOU (0x14)
2636
2637 /* The BO16 encodings used in extended VLE conditional branch mnemonics. */
2638 #define BO16F (0x0)
2639 #define BO16T (0x1)
2640
2641 /* The BO32 encodings used in extended VLE conditional branch mnemonics. */
2642 #define BO32F (0x0)
2643 #define BO32T (0x1)
2644 #define BO32DNZ (0x2)
2645 #define BO32DZ (0x3)
2646
2647 /* The BI condition bit encodings used in extended conditional branch
2648 mnemonics. */
2649 #define CBLT (0)
2650 #define CBGT (1)
2651 #define CBEQ (2)
2652 #define CBSO (3)
2653
2654 /* The TO encodings used in extended trap mnemonics. */
2655 #define TOLGT (0x1)
2656 #define TOLLT (0x2)
2657 #define TOEQ (0x4)
2658 #define TOLGE (0x5)
2659 #define TOLNL (0x5)
2660 #define TOLLE (0x6)
2661 #define TOLNG (0x6)
2662 #define TOGT (0x8)
2663 #define TOGE (0xc)
2664 #define TONL (0xc)
2665 #define TOLT (0x10)
2666 #define TOLE (0x14)
2667 #define TONG (0x14)
2668 #define TONE (0x18)
2669 #define TOU (0x1f)
2670 \f
2671 /* Smaller names for the flags so each entry in the opcodes table will
2672 fit on a single line. */
2673 #define PPCNONE 0
2674 #undef PPC
2675 #define PPC PPC_OPCODE_PPC
2676 #define PPCCOM PPC_OPCODE_PPC | PPC_OPCODE_COMMON
2677 #define POWER4 PPC_OPCODE_POWER4
2678 #define POWER5 PPC_OPCODE_POWER5
2679 #define POWER6 PPC_OPCODE_POWER6
2680 #define POWER7 PPC_OPCODE_POWER7
2681 #define CELL PPC_OPCODE_CELL
2682 #define PPC64 PPC_OPCODE_64 | PPC_OPCODE_64_BRIDGE
2683 #define NON32 (PPC_OPCODE_64 | PPC_OPCODE_POWER4 \
2684 | PPC_OPCODE_EFS | PPC_OPCODE_E500MC | PPC_OPCODE_TITAN)
2685 #define PPC403 PPC_OPCODE_403
2686 #define PPC405 PPC_OPCODE_405
2687 #define PPC440 PPC_OPCODE_440
2688 #define PPC464 PPC440
2689 #define PPC476 PPC_OPCODE_476
2690 #define PPC750 PPC
2691 #define PPC7450 PPC
2692 #define PPC860 PPC
2693 #define PPCPS PPC_OPCODE_PPCPS
2694 #define PPCVEC PPC_OPCODE_ALTIVEC
2695 #define PPCVEC2 PPC_OPCODE_ALTIVEC2
2696 #define PPCVSX PPC_OPCODE_VSX
2697 #define POWER PPC_OPCODE_POWER
2698 #define POWER2 PPC_OPCODE_POWER | PPC_OPCODE_POWER2
2699 #define PWR2COM PPC_OPCODE_POWER | PPC_OPCODE_POWER2 | PPC_OPCODE_COMMON
2700 #define PPCPWR2 PPC_OPCODE_PPC | PPC_OPCODE_POWER | PPC_OPCODE_POWER2 | PPC_OPCODE_COMMON
2701 #define COM PPC_OPCODE_POWER | PPC_OPCODE_PPC | PPC_OPCODE_COMMON
2702 #define M601 PPC_OPCODE_POWER | PPC_OPCODE_601
2703 #define PWRCOM PPC_OPCODE_POWER | PPC_OPCODE_601 | PPC_OPCODE_COMMON
2704 #define MFDEC1 PPC_OPCODE_POWER
2705 #define MFDEC2 PPC_OPCODE_PPC | PPC_OPCODE_601 | PPC_OPCODE_BOOKE | PPC_OPCODE_TITAN
2706 #define BOOKE PPC_OPCODE_BOOKE
2707 #define NO371 PPC_OPCODE_BOOKE | PPC_OPCODE_PPCPS | PPC_OPCODE_EFS | PPC_OPCODE_VLE
2708 #define PPCE300 PPC_OPCODE_E300
2709 #define PPCSPE PPC_OPCODE_SPE | PPC_OPCODE_VLE
2710 #define PPCISEL PPC_OPCODE_ISEL | PPC_OPCODE_VLE
2711 #define PPCEFS PPC_OPCODE_EFS | PPC_OPCODE_VLE
2712 #define PPCBRLK PPC_OPCODE_BRLOCK
2713 #define PPCPMR PPC_OPCODE_PMR
2714 #define PPCTMR PPC_OPCODE_TMR
2715 #define PPCCHLK PPC_OPCODE_CACHELCK
2716 #define PPCRFMCI PPC_OPCODE_RFMCI
2717 #define E500MC PPC_OPCODE_E500MC
2718 #define PPCA2 PPC_OPCODE_A2
2719 #define TITAN PPC_OPCODE_TITAN
2720 #define MULHW PPC_OPCODE_405 | PPC_OPCODE_440 | TITAN | PPC_OPCODE_VLE
2721 #define E500 PPC_OPCODE_E500
2722 #define E6500 PPC_OPCODE_E6500
2723 #define PPCVLE PPC_OPCODE_VLE
2724 \f
2725 /* The opcode table.
2726
2727 The format of the opcode table is:
2728
2729 NAME OPCODE MASK FLAGS ANTI {OPERANDS}
2730
2731 NAME is the name of the instruction.
2732 OPCODE is the instruction opcode.
2733 MASK is the opcode mask; this is used to tell the disassembler
2734 which bits in the actual opcode must match OPCODE.
2735 FLAGS are flags indicating which processors support the instruction.
2736 ANTI indicates which processors don't support the instruction.
2737 OPERANDS is the list of operands.
2738
2739 The disassembler reads the table in order and prints the first
2740 instruction which matches, so this table is sorted to put more
2741 specific instructions before more general instructions.
2742
2743 This table must be sorted by major opcode. Please try to keep it
2744 vaguely sorted within major opcode too, except of course where
2745 constrained otherwise by disassembler operation. */
2746
2747 const struct powerpc_opcode powerpc_opcodes[] = {
2748 {"attn", X(0,256), X_MASK, POWER4|PPCA2, PPC476, {0}},
2749 {"tdlgti", OPTO(2,TOLGT), OPTO_MASK, PPC64, PPCNONE, {RA, SI}},
2750 {"tdllti", OPTO(2,TOLLT), OPTO_MASK, PPC64, PPCNONE, {RA, SI}},
2751 {"tdeqi", OPTO(2,TOEQ), OPTO_MASK, PPC64, PPCNONE, {RA, SI}},
2752 {"tdlgei", OPTO(2,TOLGE), OPTO_MASK, PPC64, PPCNONE, {RA, SI}},
2753 {"tdlnli", OPTO(2,TOLNL), OPTO_MASK, PPC64, PPCNONE, {RA, SI}},
2754 {"tdllei", OPTO(2,TOLLE), OPTO_MASK, PPC64, PPCNONE, {RA, SI}},
2755 {"tdlngi", OPTO(2,TOLNG), OPTO_MASK, PPC64, PPCNONE, {RA, SI}},
2756 {"tdgti", OPTO(2,TOGT), OPTO_MASK, PPC64, PPCNONE, {RA, SI}},
2757 {"tdgei", OPTO(2,TOGE), OPTO_MASK, PPC64, PPCNONE, {RA, SI}},
2758 {"tdnli", OPTO(2,TONL), OPTO_MASK, PPC64, PPCNONE, {RA, SI}},
2759 {"tdlti", OPTO(2,TOLT), OPTO_MASK, PPC64, PPCNONE, {RA, SI}},
2760 {"tdlei", OPTO(2,TOLE), OPTO_MASK, PPC64, PPCNONE, {RA, SI}},
2761 {"tdngi", OPTO(2,TONG), OPTO_MASK, PPC64, PPCNONE, {RA, SI}},
2762 {"tdnei", OPTO(2,TONE), OPTO_MASK, PPC64, PPCNONE, {RA, SI}},
2763 {"tdi", OP(2), OP_MASK, PPC64, PPCNONE, {TO, RA, SI}},
2764
2765 {"twlgti", OPTO(3,TOLGT), OPTO_MASK, PPCCOM, PPCNONE, {RA, SI}},
2766 {"tlgti", OPTO(3,TOLGT), OPTO_MASK, PWRCOM, PPCNONE, {RA, SI}},
2767 {"twllti", OPTO(3,TOLLT), OPTO_MASK, PPCCOM, PPCNONE, {RA, SI}},
2768 {"tllti", OPTO(3,TOLLT), OPTO_MASK, PWRCOM, PPCNONE, {RA, SI}},
2769 {"tweqi", OPTO(3,TOEQ), OPTO_MASK, PPCCOM, PPCNONE, {RA, SI}},
2770 {"teqi", OPTO(3,TOEQ), OPTO_MASK, PWRCOM, PPCNONE, {RA, SI}},
2771 {"twlgei", OPTO(3,TOLGE), OPTO_MASK, PPCCOM, PPCNONE, {RA, SI}},
2772 {"tlgei", OPTO(3,TOLGE), OPTO_MASK, PWRCOM, PPCNONE, {RA, SI}},
2773 {"twlnli", OPTO(3,TOLNL), OPTO_MASK, PPCCOM, PPCNONE, {RA, SI}},
2774 {"tlnli", OPTO(3,TOLNL), OPTO_MASK, PWRCOM, PPCNONE, {RA, SI}},
2775 {"twllei", OPTO(3,TOLLE), OPTO_MASK, PPCCOM, PPCNONE, {RA, SI}},
2776 {"tllei", OPTO(3,TOLLE), OPTO_MASK, PWRCOM, PPCNONE, {RA, SI}},
2777 {"twlngi", OPTO(3,TOLNG), OPTO_MASK, PPCCOM, PPCNONE, {RA, SI}},
2778 {"tlngi", OPTO(3,TOLNG), OPTO_MASK, PWRCOM, PPCNONE, {RA, SI}},
2779 {"twgti", OPTO(3,TOGT), OPTO_MASK, PPCCOM, PPCNONE, {RA, SI}},
2780 {"tgti", OPTO(3,TOGT), OPTO_MASK, PWRCOM, PPCNONE, {RA, SI}},
2781 {"twgei", OPTO(3,TOGE), OPTO_MASK, PPCCOM, PPCNONE, {RA, SI}},
2782 {"tgei", OPTO(3,TOGE), OPTO_MASK, PWRCOM, PPCNONE, {RA, SI}},
2783 {"twnli", OPTO(3,TONL), OPTO_MASK, PPCCOM, PPCNONE, {RA, SI}},
2784 {"tnli", OPTO(3,TONL), OPTO_MASK, PWRCOM, PPCNONE, {RA, SI}},
2785 {"twlti", OPTO(3,TOLT), OPTO_MASK, PPCCOM, PPCNONE, {RA, SI}},
2786 {"tlti", OPTO(3,TOLT), OPTO_MASK, PWRCOM, PPCNONE, {RA, SI}},
2787 {"twlei", OPTO(3,TOLE), OPTO_MASK, PPCCOM, PPCNONE, {RA, SI}},
2788 {"tlei", OPTO(3,TOLE), OPTO_MASK, PWRCOM, PPCNONE, {RA, SI}},
2789 {"twngi", OPTO(3,TONG), OPTO_MASK, PPCCOM, PPCNONE, {RA, SI}},
2790 {"tngi", OPTO(3,TONG), OPTO_MASK, PWRCOM, PPCNONE, {RA, SI}},
2791 {"twnei", OPTO(3,TONE), OPTO_MASK, PPCCOM, PPCNONE, {RA, SI}},
2792 {"tnei", OPTO(3,TONE), OPTO_MASK, PWRCOM, PPCNONE, {RA, SI}},
2793 {"twi", OP(3), OP_MASK, PPCCOM, PPCNONE, {TO, RA, SI}},
2794 {"ti", OP(3), OP_MASK, PWRCOM, PPCNONE, {TO, RA, SI}},
2795
2796 {"ps_cmpu0", X (4, 0), X_MASK|(3<<21), PPCPS, PPCNONE, {BF, FRA, FRB}},
2797 {"vaddubm", VX (4, 0), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}},
2798 {"vmaxub", VX (4, 2), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}},
2799 {"vrlb", VX (4, 4), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}},
2800 {"vcmpequb", VXR(4, 6,0), VXR_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}},
2801 {"vmuloub", VX (4, 8), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}},
2802 {"vaddfp", VX (4, 10), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}},
2803 {"psq_lx", XW (4, 6,0), XW_MASK, PPCPS, PPCNONE, {FRT,RA,RB,PSWM,PSQM}},
2804 {"vmrghb", VX (4, 12), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}},
2805 {"psq_stx", XW (4, 7,0), XW_MASK, PPCPS, PPCNONE, {FRS,RA,RB,PSWM,PSQM}},
2806 {"vpkuhum", VX (4, 14), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}},
2807 {"mulhhwu", XRC(4, 8,0), X_MASK, MULHW|PPCVLE, PPCNONE, {RT, RA, RB}},
2808 {"mulhhwu.", XRC(4, 8,1), X_MASK, MULHW|PPCVLE, PPCNONE, {RT, RA, RB}},
2809 {"ps_sum0", A (4, 10,0), A_MASK, PPCPS, PPCNONE, {FRT, FRA, FRC, FRB}},
2810 {"ps_sum0.", A (4, 10,1), A_MASK, PPCPS, PPCNONE, {FRT, FRA, FRC, FRB}},
2811 {"ps_sum1", A (4, 11,0), A_MASK, PPCPS, PPCNONE, {FRT, FRA, FRC, FRB}},
2812 {"ps_sum1.", A (4, 11,1), A_MASK, PPCPS, PPCNONE, {FRT, FRA, FRC, FRB}},
2813 {"ps_muls0", A (4, 12,0), AFRB_MASK, PPCPS, PPCNONE, {FRT, FRA, FRC}},
2814 {"machhwu", XO (4, 12,0,0),XO_MASK, MULHW|PPCVLE, PPCNONE, {RT, RA, RB}},
2815 {"ps_muls0.", A (4, 12,1), AFRB_MASK, PPCPS, PPCNONE, {FRT, FRA, FRC}},
2816 {"machhwu.", XO (4, 12,0,1),XO_MASK, MULHW|PPCVLE, PPCNONE, {RT, RA, RB}},
2817 {"ps_muls1", A (4, 13,0), AFRB_MASK, PPCPS, PPCNONE, {FRT, FRA, FRC}},
2818 {"ps_muls1.", A (4, 13,1), AFRB_MASK, PPCPS, PPCNONE, {FRT, FRA, FRC}},
2819 {"ps_madds0", A (4, 14,0), A_MASK, PPCPS, PPCNONE, {FRT, FRA, FRC, FRB}},
2820 {"ps_madds0.", A (4, 14,1), A_MASK, PPCPS, PPCNONE, {FRT, FRA, FRC, FRB}},
2821 {"ps_madds1", A (4, 15,0), A_MASK, PPCPS, PPCNONE, {FRT, FRA, FRC, FRB}},
2822 {"ps_madds1.", A (4, 15,1), A_MASK, PPCPS, PPCNONE, {FRT, FRA, FRC, FRB}},
2823 {"vmhaddshs", VXA(4, 32), VXA_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB, VC}},
2824 {"vmhraddshs", VXA(4, 33), VXA_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB, VC}},
2825 {"vmladduhm", VXA(4, 34), VXA_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB, VC}},
2826 {"ps_div", A (4, 18,0), AFRC_MASK, PPCPS, PPCNONE, {FRT, FRA, FRB}},
2827 {"vmsumubm", VXA(4, 36), VXA_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB, VC}},
2828 {"ps_div.", A (4, 18,1), AFRC_MASK, PPCPS, PPCNONE, {FRT, FRA, FRB}},
2829 {"vmsummbm", VXA(4, 37), VXA_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB, VC}},
2830 {"vmsumuhm", VXA(4, 38), VXA_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB, VC}},
2831 {"vmsumuhs", VXA(4, 39), VXA_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB, VC}},
2832 {"ps_sub", A (4, 20,0), AFRC_MASK, PPCPS, PPCNONE, {FRT, FRA, FRB}},
2833 {"vmsumshm", VXA(4, 40), VXA_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB, VC}},
2834 {"ps_sub.", A (4, 20,1), AFRC_MASK, PPCPS, PPCNONE, {FRT, FRA, FRB}},
2835 {"vmsumshs", VXA(4, 41), VXA_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB, VC}},
2836 {"ps_add", A (4, 21,0), AFRC_MASK, PPCPS, PPCNONE, {FRT, FRA, FRB}},
2837 {"vsel", VXA(4, 42), VXA_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB, VC}},
2838 {"ps_add.", A (4, 21,1), AFRC_MASK, PPCPS, PPCNONE, {FRT, FRA, FRB}},
2839 {"vperm", VXA(4, 43), VXA_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB, VC}},
2840 {"vsldoi", VXA(4, 44), VXA_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB, SHB}},
2841 {"ps_sel", A (4, 23,0), A_MASK, PPCPS, PPCNONE, {FRT, FRA, FRC, FRB}},
2842 {"vmaddfp", VXA(4, 46), VXA_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VC, VB}},
2843 {"ps_sel.", A (4, 23,1), A_MASK, PPCPS, PPCNONE, {FRT, FRA, FRC, FRB}},
2844 {"vnmsubfp", VXA(4, 47), VXA_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VC, VB}},
2845 {"ps_res", A (4, 24,0), AFRAFRC_MASK, PPCPS, PPCNONE, {FRT, FRB}},
2846 {"ps_res.", A (4, 24,1), AFRAFRC_MASK, PPCPS, PPCNONE, {FRT, FRB}},
2847 {"ps_mul", A (4, 25,0), AFRB_MASK, PPCPS, PPCNONE, {FRT, FRA, FRC}},
2848 {"ps_mul.", A (4, 25,1), AFRB_MASK, PPCPS, PPCNONE, {FRT, FRA, FRC}},
2849 {"ps_rsqrte", A (4, 26,0), AFRAFRC_MASK, PPCPS, PPCNONE, {FRT, FRB}},
2850 {"ps_rsqrte.", A (4, 26,1), AFRAFRC_MASK, PPCPS, PPCNONE, {FRT, FRB}},
2851 {"ps_msub", A (4, 28,0), A_MASK, PPCPS, PPCNONE, {FRT, FRA, FRC, FRB}},
2852 {"ps_msub.", A (4, 28,1), A_MASK, PPCPS, PPCNONE, {FRT, FRA, FRC, FRB}},
2853 {"ps_madd", A (4, 29,0), A_MASK, PPCPS, PPCNONE, {FRT, FRA, FRC, FRB}},
2854 {"ps_madd.", A (4, 29,1), A_MASK, PPCPS, PPCNONE, {FRT, FRA, FRC, FRB}},
2855 {"ps_nmsub", A (4, 30,0), A_MASK, PPCPS, PPCNONE, {FRT, FRA, FRC, FRB}},
2856 {"ps_nmsub.", A (4, 30,1), A_MASK, PPCPS, PPCNONE, {FRT, FRA, FRC, FRB}},
2857 {"ps_nmadd", A (4, 31,0), A_MASK, PPCPS, PPCNONE, {FRT, FRA, FRC, FRB}},
2858 {"ps_nmadd.", A (4, 31,1), A_MASK, PPCPS, PPCNONE, {FRT, FRA, FRC, FRB}},
2859 {"ps_cmpo0", X (4, 32), X_MASK|(3<<21), PPCPS, PPCNONE, {BF, FRA, FRB}},
2860 {"vadduhm", VX (4, 64), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}},
2861 {"vmaxuh", VX (4, 66), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}},
2862 {"vrlh", VX (4, 68), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}},
2863 {"vcmpequh", VXR(4, 70,0), VXR_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}},
2864 {"vmulouh", VX (4, 72), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}},
2865 {"vsubfp", VX (4, 74), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}},
2866 {"psq_lux", XW (4, 38,0), XW_MASK, PPCPS, PPCNONE, {FRT,RA,RB,PSWM,PSQM}},
2867 {"vmrghh", VX (4, 76), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}},
2868 {"psq_stux", XW (4, 39,0), XW_MASK, PPCPS, PPCNONE, {FRS,RA,RB,PSWM,PSQM}},
2869 {"vpkuwum", VX (4, 78), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}},
2870 {"ps_neg", XRC(4, 40,0), XRA_MASK, PPCPS, PPCNONE, {FRT, FRB}},
2871 {"mulhhw", XRC(4, 40,0), X_MASK, MULHW|PPCVLE, PPCNONE, {RT, RA, RB}},
2872 {"ps_neg.", XRC(4, 40,1), XRA_MASK, PPCPS, PPCNONE, {FRT, FRB}},
2873 {"mulhhw.", XRC(4, 40,1), X_MASK, MULHW|PPCVLE, PPCNONE, {RT, RA, RB}},
2874 {"machhw", XO (4, 44,0,0),XO_MASK, MULHW|PPCVLE, PPCNONE, {RT, RA, RB}},
2875 {"machhw.", XO (4, 44,0,1),XO_MASK, MULHW|PPCVLE, PPCNONE, {RT, RA, RB}},
2876 {"nmachhw", XO (4, 46,0,0),XO_MASK, MULHW|PPCVLE, PPCNONE, {RT, RA, RB}},
2877 {"nmachhw.", XO (4, 46,0,1),XO_MASK, MULHW|PPCVLE, PPCNONE, {RT, RA, RB}},
2878 {"ps_cmpu1", X (4, 64), X_MASK|(3<<21), PPCPS, PPCNONE, {BF, FRA, FRB}},
2879 {"vadduwm", VX (4, 128), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}},
2880 {"vmaxuw", VX (4, 130), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}},
2881 {"vrlw", VX (4, 132), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}},
2882 {"vcmpequw", VXR(4, 134,0), VXR_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}},
2883 {"vmrghw", VX (4, 140), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}},
2884 {"vpkuhus", VX (4, 142), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}},
2885 {"ps_mr", XRC(4, 72,0), XRA_MASK, PPCPS, PPCNONE, {FRT, FRB}},
2886 {"ps_mr.", XRC(4, 72,1), XRA_MASK, PPCPS, PPCNONE, {FRT, FRB}},
2887 {"machhwsu", XO (4, 76,0,0),XO_MASK, MULHW|PPCVLE, PPCNONE, {RT, RA, RB}},
2888 {"machhwsu.", XO (4, 76,0,1),XO_MASK, MULHW|PPCVLE, PPCNONE, {RT, RA, RB}},
2889 {"ps_cmpo1", X (4, 96), X_MASK|(3<<21), PPCPS, PPCNONE, {BF, FRA, FRB}},
2890 {"vcmpeqfp", VXR(4, 198,0), VXR_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}},
2891 {"vpkuwus", VX (4, 206), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}},
2892 {"machhws", XO (4, 108,0,0),XO_MASK, MULHW|PPCVLE, PPCNONE, {RT, RA, RB}},
2893 {"machhws.", XO (4, 108,0,1),XO_MASK, MULHW|PPCVLE, PPCNONE, {RT, RA, RB}},
2894 {"nmachhws", XO (4, 110,0,0),XO_MASK, MULHW|PPCVLE, PPCNONE, {RT, RA, RB}},
2895 {"nmachhws.", XO (4, 110,0,1),XO_MASK, MULHW|PPCVLE, PPCNONE, {RT, RA, RB}},
2896 {"vmaxsb", VX (4, 258), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}},
2897 {"vslb", VX (4, 260), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}},
2898 {"vmulosb", VX (4, 264), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}},
2899 {"vrefp", VX (4, 266), VXVA_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VB}},
2900 {"vmrglb", VX (4, 268), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}},
2901 {"vpkshus", VX (4, 270), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}},
2902 {"ps_nabs", XRC(4, 136,0), XRA_MASK, PPCPS, PPCNONE, {FRT, FRB}},
2903 {"mulchwu", XRC(4, 136,0), X_MASK, MULHW|PPCVLE, PPCNONE, {RT, RA, RB}},
2904 {"ps_nabs.", XRC(4, 136,1), XRA_MASK, PPCPS, PPCNONE, {FRT, FRB}},
2905 {"mulchwu.", XRC(4, 136,1), X_MASK, MULHW|PPCVLE, PPCNONE, {RT, RA, RB}},
2906 {"macchwu", XO (4, 140,0,0),XO_MASK, MULHW|PPCVLE, PPCNONE, {RT, RA, RB}},
2907 {"macchwu.", XO (4, 140,0,1),XO_MASK, MULHW|PPCVLE, PPCNONE, {RT, RA, RB}},
2908 {"vmaxsh", VX (4, 322), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}},
2909 {"vslh", VX (4, 324), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}},
2910 {"vmulosh", VX (4, 328), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}},
2911 {"vrsqrtefp", VX (4, 330), VXVA_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VB}},
2912 {"vmrglh", VX (4, 332), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}},
2913 {"vpkswus", VX (4, 334), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}},
2914 {"mulchw", XRC(4, 168,0), X_MASK, MULHW|PPCVLE, PPCNONE, {RT, RA, RB}},
2915 {"mulchw.", XRC(4, 168,1), X_MASK, MULHW|PPCVLE, PPCNONE, {RT, RA, RB}},
2916 {"macchw", XO (4, 172,0,0),XO_MASK, MULHW|PPCVLE, PPCNONE, {RT, RA, RB}},
2917 {"macchw.", XO (4, 172,0,1),XO_MASK, MULHW|PPCVLE, PPCNONE, {RT, RA, RB}},
2918 {"nmacchw", XO (4, 174,0,0),XO_MASK, MULHW|PPCVLE, PPCNONE, {RT, RA, RB}},
2919 {"nmacchw.", XO (4, 174,0,1),XO_MASK, MULHW|PPCVLE, PPCNONE, {RT, RA, RB}},
2920 {"vaddcuw", VX (4, 384), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}},
2921 {"vmaxsw", VX (4, 386), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}},
2922 {"vslw", VX (4, 388), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}},
2923 {"vexptefp", VX (4, 394), VXVA_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VB}},
2924 {"vmrglw", VX (4, 396), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}},
2925 {"vpkshss", VX (4, 398), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}},
2926 {"macchwsu", XO (4, 204,0,0),XO_MASK, MULHW|PPCVLE, PPCNONE, {RT, RA, RB}},
2927 {"macchwsu.", XO (4, 204,0,1),XO_MASK, MULHW|PPCVLE, PPCNONE, {RT, RA, RB}},
2928 {"vsl", VX (4, 452), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}},
2929 {"vcmpgefp", VXR(4, 454,0), VXR_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}},
2930 {"vlogefp", VX (4, 458), VXVA_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VB}},
2931 {"vpkswss", VX (4, 462), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}},
2932 {"macchws", XO (4, 236,0,0),XO_MASK, MULHW|PPCVLE, PPCNONE, {RT, RA, RB}},
2933 {"macchws.", XO (4, 236,0,1),XO_MASK, MULHW|PPCVLE, PPCNONE, {RT, RA, RB}},
2934 {"nmacchws", XO (4, 238,0,0),XO_MASK, MULHW|PPCVLE, PPCNONE, {RT, RA, RB}},
2935 {"nmacchws.", XO (4, 238,0,1),XO_MASK, MULHW|PPCVLE, PPCNONE, {RT, RA, RB}},
2936 {"evaddw", VX (4, 512), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}},
2937 {"vaddubs", VX (4, 512), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}},
2938 {"evaddiw", VX (4, 514), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RB, UIMM}},
2939 {"vminub", VX (4, 514), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}},
2940 {"evsubfw", VX (4, 516), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}},
2941 {"evsubw", VX (4, 516), VX_MASK, PPCSPE, PPCNONE, {RS, RB, RA}},
2942 {"vsrb", VX (4, 516), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}},
2943 {"evsubifw", VX (4, 518), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, UIMM, RB}},
2944 {"evsubiw", VX (4, 518), VX_MASK, PPCSPE, PPCNONE, {RS, RB, UIMM}},
2945 {"vcmpgtub", VXR(4, 518,0), VXR_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}},
2946 {"evabs", VX (4, 520), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA}},
2947 {"vmuleub", VX (4, 520), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}},
2948 {"evneg", VX (4, 521), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA}},
2949 {"evextsb", VX (4, 522), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA}},
2950 {"vrfin", VX (4, 522), VXVA_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VB}},
2951 {"evextsh", VX (4, 523), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA}},
2952 {"evrndw", VX (4, 524), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA}},
2953 {"vspltb", VX (4, 524), VXUIMM4_MASK,PPCVEC|PPCVLE, PPCNONE, {VD, VB, UIMM4}},
2954 {"evcntlzw", VX (4, 525), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA}},
2955 {"evcntlsw", VX (4, 526), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA}},
2956 {"vupkhsb", VX (4, 526), VXVA_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VB}},
2957 {"brinc", VX (4, 527), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}},
2958 {"ps_abs", XRC(4, 264,0), XRA_MASK, PPCPS, PPCNONE, {FRT, FRB}},
2959 {"ps_abs.", XRC(4, 264,1), XRA_MASK, PPCPS, PPCNONE, {FRT, FRB}},
2960 {"evand", VX (4, 529), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}},
2961 {"evandc", VX (4, 530), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}},
2962 {"evxor", VX (4, 534), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}},
2963 {"evmr", VX (4, 535), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, BBA}},
2964 {"evor", VX (4, 535), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}},
2965 {"evnor", VX (4, 536), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}},
2966 {"evnot", VX (4, 536), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, BBA}},
2967 {"get", APU(4, 268,0), APU_RA_MASK, PPC405, PPCNONE, {RT, FSL}},
2968 {"eveqv", VX (4, 537), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}},
2969 {"evorc", VX (4, 539), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}},
2970 {"evnand", VX (4, 542), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}},
2971 {"evsrwu", VX (4, 544), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}},
2972 {"evsrws", VX (4, 545), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}},
2973 {"evsrwiu", VX (4, 546), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, EVUIMM}},
2974 {"evsrwis", VX (4, 547), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, EVUIMM}},
2975 {"evslw", VX (4, 548), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}},
2976 {"evslwi", VX (4, 550), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, EVUIMM}},
2977 {"evrlw", VX (4, 552), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}},
2978 {"evsplati", VX (4, 553), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, SIMM}},
2979 {"evrlwi", VX (4, 554), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, EVUIMM}},
2980 {"evsplatfi", VX (4, 555), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, SIMM}},
2981 {"evmergehi", VX (4, 556), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}},
2982 {"evmergelo", VX (4, 557), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}},
2983 {"evmergehilo", VX (4, 558), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}},
2984 {"evmergelohi", VX (4, 559), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}},
2985 {"evcmpgtu", VX (4, 560), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {CRFD, RA, RB}},
2986 {"evcmpgts", VX (4, 561), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {CRFD, RA, RB}},
2987 {"evcmpltu", VX (4, 562), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {CRFD, RA, RB}},
2988 {"evcmplts", VX (4, 563), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {CRFD, RA, RB}},
2989 {"evcmpeq", VX (4, 564), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {CRFD, RA, RB}},
2990 {"cget", APU(4, 284,0), APU_RA_MASK, PPC405, PPCNONE, {RT, FSL}},
2991 {"vadduhs", VX (4, 576), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}},
2992 {"vminuh", VX (4, 578), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}},
2993 {"vsrh", VX (4, 580), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}},
2994 {"vcmpgtuh", VXR(4, 582,0), VXR_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}},
2995 {"vmuleuh", VX (4, 584), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}},
2996 {"vrfiz", VX (4, 586), VXVA_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VB}},
2997 {"vsplth", VX (4, 588), VXUIMM3_MASK,PPCVEC|PPCVLE, PPCNONE, {VD, VB, UIMM3}},
2998 {"vupkhsh", VX (4, 590), VXVA_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VB}},
2999 {"nget", APU(4, 300,0), APU_RA_MASK, PPC405, PPCNONE, {RT, FSL}},
3000 {"evsel", EVSEL(4,79), EVSEL_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB, CRFS}},
3001 {"ncget", APU(4, 316,0), APU_RA_MASK, PPC405, PPCNONE, {RT, FSL}},
3002 {"evfsadd", VX (4, 640), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}},
3003 {"vadduws", VX (4, 640), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}},
3004 {"evfssub", VX (4, 641), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}},
3005 {"vminuw", VX (4, 642), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}},
3006 {"evfsabs", VX (4, 644), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA}},
3007 {"vsrw", VX (4, 644), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}},
3008 {"evfsnabs", VX (4, 645), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA}},
3009 {"evfsneg", VX (4, 646), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA}},
3010 {"vcmpgtuw", VXR(4, 646,0), VXR_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}},
3011 {"evfsmul", VX (4, 648), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}},
3012 {"evfsdiv", VX (4, 649), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}},
3013 {"vrfip", VX (4, 650), VXVA_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VB}},
3014 {"evfscmpgt", VX (4, 652), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {CRFD, RA, RB}},
3015 {"vspltw", VX (4, 652), VXUIMM2_MASK,PPCVEC|PPCVLE, PPCNONE, {VD, VB, UIMM2}},
3016 {"evfscmplt", VX (4, 653), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {CRFD, RA, RB}},
3017 {"evfscmpeq", VX (4, 654), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {CRFD, RA, RB}},
3018 {"vupklsb", VX (4, 654), VXVA_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VB}},
3019 {"evfscfui", VX (4, 656), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RB}},
3020 {"evfscfsi", VX (4, 657), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RB}},
3021 {"evfscfuf", VX (4, 658), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RB}},
3022 {"evfscfsf", VX (4, 659), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RB}},
3023 {"evfsctui", VX (4, 660), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RB}},
3024 {"evfsctsi", VX (4, 661), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RB}},
3025 {"evfsctuf", VX (4, 662), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RB}},
3026 {"evfsctsf", VX (4, 663), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RB}},
3027 {"evfsctuiz", VX (4, 664), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RB}},
3028 {"put", APU(4, 332,0), APU_RT_MASK, PPC405, PPCNONE, {RA, FSL}},
3029 {"evfsctsiz", VX (4, 666), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RB}},
3030 {"evfststgt", VX (4, 668), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {CRFD, RA, RB}},
3031 {"evfststlt", VX (4, 669), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {CRFD, RA, RB}},
3032 {"evfststeq", VX (4, 670), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {CRFD, RA, RB}},
3033 {"cput", APU(4, 348,0), APU_RT_MASK, PPC405, PPCNONE, {RA, FSL}},
3034 {"efsadd", VX (4, 704), VX_MASK, PPCEFS|PPCVLE, PPCNONE, {RS, RA, RB}},
3035 {"efssub", VX (4, 705), VX_MASK, PPCEFS|PPCVLE, PPCNONE, {RS, RA, RB}},
3036 {"efsabs", VX (4, 708), VX_MASK, PPCEFS|PPCVLE, PPCNONE, {RS, RA}},
3037 {"vsr", VX (4, 708), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}},
3038 {"efsnabs", VX (4, 709), VX_MASK, PPCEFS|PPCVLE, PPCNONE, {RS, RA}},
3039 {"efsneg", VX (4, 710), VX_MASK, PPCEFS|PPCVLE, PPCNONE, {RS, RA}},
3040 {"vcmpgtfp", VXR(4, 710,0), VXR_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}},
3041 {"efsmul", VX (4, 712), VX_MASK, PPCEFS|PPCVLE, PPCNONE, {RS, RA, RB}},
3042 {"efsdiv", VX (4, 713), VX_MASK, PPCEFS|PPCVLE, PPCNONE, {RS, RA, RB}},
3043 {"vrfim", VX (4, 714), VXVA_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VB}},
3044 {"efscmpgt", VX (4, 716), VX_MASK, PPCEFS|PPCVLE, PPCNONE, {CRFD, RA, RB}},
3045 {"efscmplt", VX (4, 717), VX_MASK, PPCEFS|PPCVLE, PPCNONE, {CRFD, RA, RB}},
3046 {"efscmpeq", VX (4, 718), VX_MASK, PPCEFS|PPCVLE, PPCNONE, {CRFD, RA, RB}},
3047 {"vupklsh", VX (4, 718), VXVA_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VB}},
3048 {"efscfd", VX (4, 719), VX_MASK, PPCEFS|PPCVLE, PPCNONE, {RS, RB}},
3049 {"efscfui", VX (4, 720), VX_MASK, PPCEFS|PPCVLE, PPCNONE, {RS, RB}},
3050 {"efscfsi", VX (4, 721), VX_MASK, PPCEFS|PPCVLE, PPCNONE, {RS, RB}},
3051 {"efscfuf", VX (4, 722), VX_MASK, PPCEFS|PPCVLE, PPCNONE, {RS, RB}},
3052 {"efscfsf", VX (4, 723), VX_MASK, PPCEFS|PPCVLE, PPCNONE, {RS, RB}},
3053 {"efsctui", VX (4, 724), VX_MASK, PPCEFS|PPCVLE, PPCNONE, {RS, RB}},
3054 {"efsctsi", VX (4, 725), VX_MASK, PPCEFS|PPCVLE, PPCNONE, {RS, RB}},
3055 {"efsctuf", VX (4, 726), VX_MASK, PPCEFS|PPCVLE, PPCNONE, {RS, RB}},
3056 {"efsctsf", VX (4, 727), VX_MASK, PPCEFS|PPCVLE, PPCNONE, {RS, RB}},
3057 {"efsctuiz", VX (4, 728), VX_MASK, PPCEFS|PPCVLE, PPCNONE, {RS, RB}},
3058 {"nput", APU(4, 364,0), APU_RT_MASK, PPC405, PPCNONE, {RA, FSL}},
3059 {"efsctsiz", VX (4, 730), VX_MASK, PPCEFS|PPCVLE, PPCNONE, {RS, RB}},
3060 {"efststgt", VX (4, 732), VX_MASK, PPCEFS|PPCVLE, PPCNONE, {CRFD, RA, RB}},
3061 {"efststlt", VX (4, 733), VX_MASK, PPCEFS|PPCVLE, PPCNONE, {CRFD, RA, RB}},
3062 {"efststeq", VX (4, 734), VX_MASK, PPCEFS|PPCVLE, PPCNONE, {CRFD, RA, RB}},
3063 {"efdadd", VX (4, 736), VX_MASK, PPCEFS|PPCVLE, PPCNONE, {RS, RA, RB}},
3064 {"efdsub", VX (4, 737), VX_MASK, PPCEFS|PPCVLE, PPCNONE, {RS, RA, RB}},
3065 {"efdcfuid", VX (4, 738), VX_MASK, PPCEFS|PPCVLE, PPCNONE, {RS, RB}},
3066 {"efdcfsid", VX (4, 739), VX_MASK, PPCEFS|PPCVLE, PPCNONE, {RS, RB}},
3067 {"efdabs", VX (4, 740), VX_MASK, PPCEFS|PPCVLE, PPCNONE, {RS, RA}},
3068 {"efdnabs", VX (4, 741), VX_MASK, PPCEFS|PPCVLE, PPCNONE, {RS, RA}},
3069 {"efdneg", VX (4, 742), VX_MASK, PPCEFS|PPCVLE, PPCNONE, {RS, RA}},
3070 {"efdmul", VX (4, 744), VX_MASK, PPCEFS|PPCVLE, PPCNONE, {RS, RA, RB}},
3071 {"efddiv", VX (4, 745), VX_MASK, PPCEFS|PPCVLE, PPCNONE, {RS, RA, RB}},
3072 {"efdctuidz", VX (4, 746), VX_MASK, PPCEFS|PPCVLE, PPCNONE, {RS, RB}},
3073 {"efdctsidz", VX (4, 747), VX_MASK, PPCEFS|PPCVLE, PPCNONE, {RS, RB}},
3074 {"efdcmpgt", VX (4, 748), VX_MASK, PPCEFS|PPCVLE, PPCNONE, {CRFD, RA, RB}},
3075 {"efdcmplt", VX (4, 749), VX_MASK, PPCEFS|PPCVLE, PPCNONE, {CRFD, RA, RB}},
3076 {"efdcmpeq", VX (4, 750), VX_MASK, PPCEFS|PPCVLE, PPCNONE, {CRFD, RA, RB}},
3077 {"efdcfs", VX (4, 751), VX_MASK, PPCEFS|PPCVLE, PPCNONE, {RS, RB}},
3078 {"efdcfui", VX (4, 752), VX_MASK, PPCEFS|PPCVLE, PPCNONE, {RS, RB}},
3079 {"efdcfsi", VX (4, 753), VX_MASK, PPCEFS|PPCVLE, PPCNONE, {RS, RB}},
3080 {"efdcfuf", VX (4, 754), VX_MASK, PPCEFS|PPCVLE, PPCNONE, {RS, RB}},
3081 {"efdcfsf", VX (4, 755), VX_MASK, PPCEFS|PPCVLE, PPCNONE, {RS, RB}},
3082 {"efdctui", VX (4, 756), VX_MASK, PPCEFS|PPCVLE, PPCNONE, {RS, RB}},
3083 {"efdctsi", VX (4, 757), VX_MASK, PPCEFS|PPCVLE, PPCNONE, {RS, RB}},
3084 {"efdctuf", VX (4, 758), VX_MASK, PPCEFS|PPCVLE, PPCNONE, {RS, RB}},
3085 {"efdctsf", VX (4, 759), VX_MASK, PPCEFS|PPCVLE, PPCNONE, {RS, RB}},
3086 {"efdctuiz", VX (4, 760), VX_MASK, PPCEFS|PPCVLE, PPCNONE, {RS, RB}},
3087 {"ncput", APU(4, 380,0), APU_RT_MASK, PPC405, PPCNONE, {RA, FSL}},
3088 {"efdctsiz", VX (4, 762), VX_MASK, PPCEFS|PPCVLE, PPCNONE, {RS, RB}},
3089 {"efdtstgt", VX (4, 764), VX_MASK, PPCEFS|PPCVLE, PPCNONE, {CRFD, RA, RB}},
3090 {"efdtstlt", VX (4, 765), VX_MASK, PPCEFS|PPCVLE, PPCNONE, {CRFD, RA, RB}},
3091 {"efdtsteq", VX (4, 766), VX_MASK, PPCEFS|PPCVLE, PPCNONE, {CRFD, RA, RB}},
3092 {"evlddx", VX (4, 768), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}},
3093 {"vaddsbs", VX (4, 768), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}},
3094 {"evldd", VX (4, 769), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, EVUIMM_8, RA}},
3095 {"evldwx", VX (4, 770), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}},
3096 {"vminsb", VX (4, 770), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}},
3097 {"evldw", VX (4, 771), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, EVUIMM_8, RA}},
3098 {"evldhx", VX (4, 772), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}},
3099 {"vsrab", VX (4, 772), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}},
3100 {"evldh", VX (4, 773), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, EVUIMM_8, RA}},
3101 {"vcmpgtsb", VXR(4, 774,0), VXR_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}},
3102 {"evlhhesplatx",VX (4, 776), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}},
3103 {"vmulesb", VX (4, 776), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}},
3104 {"evlhhesplat", VX (4, 777), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, EVUIMM_2, RA}},
3105 {"vcfux", VX (4, 778), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VB, UIMM}},
3106 {"evlhhousplatx",VX(4, 780), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}},
3107 {"vspltisb", VX (4, 780), VXVB_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, SIMM}},
3108 {"evlhhousplat",VX (4, 781), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, EVUIMM_2, RA}},
3109 {"evlhhossplatx",VX(4, 782), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}},
3110 {"vpkpx", VX (4, 782), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}},
3111 {"evlhhossplat",VX (4, 783), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, EVUIMM_2, RA}},
3112 {"mullhwu", XRC(4, 392,0), X_MASK, MULHW|PPCVLE, PPCNONE, {RT, RA, RB}},
3113 {"evlwhex", VX (4, 784), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}},
3114 {"mullhwu.", XRC(4, 392,1), X_MASK, MULHW|PPCVLE, PPCNONE, {RT, RA, RB}},
3115 {"evlwhe", VX (4, 785), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, EVUIMM_4, RA}},
3116 {"evlwhoux", VX (4, 788), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}},
3117 {"evlwhou", VX (4, 789), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, EVUIMM_4, RA}},
3118 {"evlwhosx", VX (4, 790), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}},
3119 {"evlwhos", VX (4, 791), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, EVUIMM_4, RA}},
3120 {"maclhwu", XO (4, 396,0,0),XO_MASK, MULHW|PPCVLE, PPCNONE, {RT, RA, RB}},
3121 {"evlwwsplatx", VX (4, 792), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}},
3122 {"maclhwu.", XO (4, 396,0,1),XO_MASK, MULHW|PPCVLE, PPCNONE, {RT, RA, RB}},
3123 {"evlwwsplat", VX (4, 793), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, EVUIMM_4, RA}},
3124 {"evlwhsplatx", VX (4, 796), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}},
3125 {"evlwhsplat", VX (4, 797), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, EVUIMM_4, RA}},
3126 {"evstddx", VX (4, 800), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}},
3127 {"evstdd", VX (4, 801), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, EVUIMM_8, RA}},
3128 {"evstdwx", VX (4, 802), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}},
3129 {"evstdw", VX (4, 803), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, EVUIMM_8, RA}},
3130 {"evstdhx", VX (4, 804), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}},
3131 {"evstdh", VX (4, 805), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, EVUIMM_8, RA}},
3132 {"evstwhex", VX (4, 816), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}},
3133 {"evstwhe", VX (4, 817), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, EVUIMM_4, RA}},
3134 {"evstwhox", VX (4, 820), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}},
3135 {"evstwho", VX (4, 821), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, EVUIMM_4, RA}},
3136 {"evstwwex", VX (4, 824), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}},
3137 {"evstwwe", VX (4, 825), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, EVUIMM_4, RA}},
3138 {"evstwwox", VX (4, 828), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}},
3139 {"evstwwo", VX (4, 829), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, EVUIMM_4, RA}},
3140 {"vaddshs", VX (4, 832), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}},
3141 {"vminsh", VX (4, 834), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}},
3142 {"vsrah", VX (4, 836), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}},
3143 {"vcmpgtsh", VXR(4, 838,0), VXR_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}},
3144 {"vmulesh", VX (4, 840), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}},
3145 {"vcfsx", VX (4, 842), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VB, UIMM}},
3146 {"vspltish", VX (4, 844), VXVB_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, SIMM}},
3147 {"vupkhpx", VX (4, 846), VXVA_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VB}},
3148 {"mullhw", XRC(4, 424,0), X_MASK, MULHW|PPCVLE, PPCNONE, {RT, RA, RB}},
3149 {"mullhw.", XRC(4, 424,1), X_MASK, MULHW|PPCVLE, PPCNONE, {RT, RA, RB}},
3150 {"maclhw", XO (4, 428,0,0),XO_MASK, MULHW|PPCVLE, PPCNONE, {RT, RA, RB}},
3151 {"maclhw.", XO (4, 428,0,1),XO_MASK, MULHW|PPCVLE, PPCNONE, {RT, RA, RB}},
3152 {"nmaclhw", XO (4, 430,0,0),XO_MASK, MULHW|PPCVLE, PPCNONE, {RT, RA, RB}},
3153 {"nmaclhw.", XO (4, 430,0,1),XO_MASK, MULHW|PPCVLE, PPCNONE, {RT, RA, RB}},
3154 {"vaddsws", VX (4, 896), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}},
3155 {"vminsw", VX (4, 898), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}},
3156 {"vsraw", VX (4, 900), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}},
3157 {"vcmpgtsw", VXR(4, 902,0), VXR_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}},
3158 {"vctuxs", VX (4, 906), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VB, UIMM}},
3159 {"vspltisw", VX (4, 908), VXVB_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, SIMM}},
3160 {"maclhwsu", XO (4, 460,0,0),XO_MASK, MULHW|PPCVLE, PPCNONE, {RT, RA, RB}},
3161 {"maclhwsu.", XO (4, 460,0,1),XO_MASK, MULHW|PPCVLE, PPCNONE, {RT, RA, RB}},
3162 {"vcmpbfp", VXR(4, 966,0), VXR_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}},
3163 {"vctsxs", VX (4, 970), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VB, UIMM}},
3164 {"vupklpx", VX (4, 974), VXVA_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VB}},
3165 {"maclhws", XO (4, 492,0,0),XO_MASK, MULHW|PPCVLE, PPCNONE, {RT, RA, RB}},
3166 {"maclhws.", XO (4, 492,0,1),XO_MASK, MULHW|PPCVLE, PPCNONE, {RT, RA, RB}},
3167 {"nmaclhws", XO (4, 494,0,0),XO_MASK, MULHW|PPCVLE, PPCNONE, {RT, RA, RB}},
3168 {"nmaclhws.", XO (4, 494,0,1),XO_MASK, MULHW|PPCVLE, PPCNONE, {RT, RA, RB}},
3169 {"vsububm", VX (4,1024), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}},
3170 {"vavgub", VX (4,1026), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}},
3171 {"vabsdub", VX (4,1027), VX_MASK, PPCVEC2, PPCNONE, {VD, VA, VB}},
3172 {"evmhessf", VX (4,1027), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}},
3173 {"vand", VX (4,1028), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}},
3174 {"vcmpequb.", VXR(4, 6,1), VXR_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}},
3175 {"udi0fcm.", APU(4, 515,0), APU_MASK, PPC405|PPC440, PPC476, {URT, URA, URB}},
3176 {"udi0fcm", APU(4, 515,1), APU_MASK, PPC405|PPC440, PPC476, {URT, URA, URB}},
3177 {"evmhossf", VX (4,1031), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}},
3178 {"evmheumi", VX (4,1032), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}},
3179 {"evmhesmi", VX (4,1033), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}},
3180 {"vmaxfp", VX (4,1034), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}},
3181 {"evmhesmf", VX (4,1035), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}},
3182 {"evmhoumi", VX (4,1036), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}},
3183 {"vslo", VX (4,1036), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}},
3184 {"evmhosmi", VX (4,1037), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}},
3185 {"evmhosmf", VX (4,1039), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}},
3186 {"machhwuo", XO (4, 12,1,0),XO_MASK, MULHW|PPCVLE, PPCNONE, {RT, RA, RB}},
3187 {"machhwuo.", XO (4, 12,1,1),XO_MASK, MULHW|PPCVLE, PPCNONE, {RT, RA, RB}},
3188 {"ps_merge00", XOPS(4,528,0), XOPS_MASK, PPCPS, PPCNONE, {FRT, FRA, FRB}},
3189 {"ps_merge00.", XOPS(4,528,1), XOPS_MASK, PPCPS, PPCNONE, {FRT, FRA, FRB}},
3190 {"evmhessfa", VX (4,1059), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}},
3191 {"evmhossfa", VX (4,1063), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}},
3192 {"evmheumia", VX (4,1064), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}},
3193 {"evmhesmia", VX (4,1065), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}},
3194 {"evmhesmfa", VX (4,1067), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}},
3195 {"evmhoumia", VX (4,1068), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}},
3196 {"evmhosmia", VX (4,1069), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}},
3197 {"evmhosmfa", VX (4,1071), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}},
3198 {"vsubuhm", VX (4,1088), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}},
3199 {"vavguh", VX (4,1090), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}},
3200 {"vabsduh", VX (4,1091), VX_MASK, PPCVEC2, PPCNONE, {VD, VA, VB}},
3201 {"vandc", VX (4,1092), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}},
3202 {"vcmpequh.", VXR(4, 70,1), VXR_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}},
3203 {"udi1fcm.", APU(4, 547,0), APU_MASK, PPC405|PPC440, PPC476, {URT, URA, URB}},
3204 {"udi1fcm", APU(4, 547,1), APU_MASK, PPC405|PPC440, PPC476, {URT, URA, URB}},
3205 {"evmwhssf", VX (4,1095), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}},
3206 {"evmwlumi", VX (4,1096), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}},
3207 {"vminfp", VX (4,1098), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}},
3208 {"evmwhumi", VX (4,1100), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}},
3209 {"vsro", VX (4,1100), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}},
3210 {"evmwhsmi", VX (4,1101), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}},
3211 {"evmwhsmf", VX (4,1103), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}},
3212 {"evmwssf", VX (4,1107), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}},
3213 {"machhwo", XO (4, 44,1,0),XO_MASK, MULHW|PPCVLE, PPCNONE, {RT, RA, RB}},
3214 {"evmwumi", VX (4,1112), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}},
3215 {"machhwo.", XO (4, 44,1,1),XO_MASK, MULHW|PPCVLE, PPCNONE, {RT, RA, RB}},
3216 {"evmwsmi", VX (4,1113), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}},
3217 {"evmwsmf", VX (4,1115), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}},
3218 {"nmachhwo", XO (4, 46,1,0),XO_MASK, MULHW|PPCVLE, PPCNONE, {RT, RA, RB}},
3219 {"nmachhwo.", XO (4, 46,1,1),XO_MASK, MULHW|PPCVLE, PPCNONE, {RT, RA, RB}},
3220 {"ps_merge01", XOPS(4,560,0), XOPS_MASK, PPCPS, PPCNONE, {FRT, FRA, FRB}},
3221 {"ps_merge01.", XOPS(4,560,1), XOPS_MASK, PPCPS, PPCNONE, {FRT, FRA, FRB}},
3222 {"evmwhssfa", VX (4,1127), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}},
3223 {"evmwlumia", VX (4,1128), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}},
3224 {"evmwhumia", VX (4,1132), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}},
3225 {"evmwhsmia", VX (4,1133), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}},
3226 {"evmwhsmfa", VX (4,1135), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}},
3227 {"evmwssfa", VX (4,1139), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}},
3228 {"evmwumia", VX (4,1144), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}},
3229 {"evmwsmia", VX (4,1145), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}},
3230 {"evmwsmfa", VX (4,1147), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}},
3231 {"vsubuwm", VX (4,1152), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}},
3232 {"vavguw", VX (4,1154), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}},
3233 {"vabsduw", VX (4,1155), VX_MASK, PPCVEC2, PPCNONE, {VD, VA, VB}},
3234 {"vor", VX (4,1156), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}},
3235 {"vcmpequw.", VXR(4, 134,1), VXR_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}},
3236 {"udi2fcm.", APU(4, 579,0), APU_MASK, PPC405|PPC440, PPC476, {URT, URA, URB}},
3237 {"udi2fcm", APU(4, 579,1), APU_MASK, PPC405|PPC440, PPC476, {URT, URA, URB}},
3238 {"machhwsuo", XO (4, 76,1,0),XO_MASK, MULHW|PPCVLE, PPCNONE, {RT, RA, RB}},
3239 {"machhwsuo.", XO (4, 76,1,1),XO_MASK, MULHW|PPCVLE, PPCNONE, {RT, RA, RB}},
3240 {"ps_merge10", XOPS(4,592,0), XOPS_MASK, PPCPS, PPCNONE, {FRT, FRA, FRB}},
3241 {"ps_merge10.", XOPS(4,592,1), XOPS_MASK, PPCPS, PPCNONE, {FRT, FRA, FRB}},
3242 {"evaddusiaaw", VX (4,1216), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA}},
3243 {"evaddssiaaw", VX (4,1217), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA}},
3244 {"evsubfusiaaw",VX (4,1218), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA}},
3245 {"evsubfssiaaw",VX (4,1219), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA}},
3246 {"evmra", VX (4,1220), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA}},
3247 {"vxor", VX (4,1220), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}},
3248 {"evdivws", VX (4,1222), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}},
3249 {"vcmpeqfp.", VXR(4, 198,1), VXR_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}},
3250 {"udi3fcm.", APU(4, 611,0), APU_MASK, PPC405|PPC440, PPC476, {URT, URA, URB}},
3251 {"udi3fcm", APU(4, 611,1), APU_MASK, PPC405|PPC440, PPC476, {URT, URA, URB}},
3252 {"evdivwu", VX (4,1223), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}},
3253 {"evaddumiaaw", VX (4,1224), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA}},
3254 {"evaddsmiaaw", VX (4,1225), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA}},
3255 {"evsubfumiaaw",VX (4,1226), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA}},
3256 {"evsubfsmiaaw",VX (4,1227), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA}},
3257 {"machhwso", XO (4, 108,1,0),XO_MASK, MULHW|PPCVLE, PPCNONE, {RT, RA, RB}},
3258 {"machhwso.", XO (4, 108,1,1),XO_MASK, MULHW|PPCVLE, PPCNONE, {RT, RA, RB}},
3259 {"nmachhwso", XO (4, 110,1,0),XO_MASK, MULHW|PPCVLE, PPCNONE, {RT, RA, RB}},
3260 {"nmachhwso.", XO (4, 110,1,1),XO_MASK, MULHW|PPCVLE, PPCNONE, {RT, RA, RB}},
3261 {"ps_merge11", XOPS(4,624,0), XOPS_MASK, PPCPS, PPCNONE, {FRT, FRA, FRB}},
3262 {"ps_merge11.", XOPS(4,624,1), XOPS_MASK, PPCPS, PPCNONE, {FRT, FRA, FRB}},
3263 {"evmheusiaaw", VX (4,1280), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}},
3264 {"evmhessiaaw", VX (4,1281), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}},
3265 {"vavgsb", VX (4,1282), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}},
3266 {"evmhessfaaw", VX (4,1283), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}},
3267 {"evmhousiaaw", VX (4,1284), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}},
3268 {"vnor", VX (4,1284), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}},
3269 {"evmhossiaaw", VX (4,1285), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}},
3270 {"udi4fcm.", APU(4, 643,0), APU_MASK, PPC405|PPC440, PPC476, {URT, URA, URB}},
3271 {"udi4fcm", APU(4, 643,1), APU_MASK, PPC405|PPC440, PPC476, {URT, URA, URB}},
3272 {"evmhossfaaw", VX (4,1287), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}},
3273 {"evmheumiaaw", VX (4,1288), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}},
3274 {"evmhesmiaaw", VX (4,1289), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}},
3275 {"evmhesmfaaw", VX (4,1291), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}},
3276 {"evmhoumiaaw", VX (4,1292), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}},
3277 {"evmhosmiaaw", VX (4,1293), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}},
3278 {"evmhosmfaaw", VX (4,1295), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}},
3279 {"macchwuo", XO (4, 140,1,0),XO_MASK, MULHW|PPCVLE, PPCNONE, {RT, RA, RB}},
3280 {"macchwuo.", XO (4, 140,1,1),XO_MASK, MULHW|PPCVLE, PPCNONE, {RT, RA, RB}},
3281 {"evmhegumiaa", VX (4,1320), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}},
3282 {"evmhegsmiaa", VX (4,1321), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}},
3283 {"evmhegsmfaa", VX (4,1323), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}},
3284 {"evmhogumiaa", VX (4,1324), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}},
3285 {"evmhogsmiaa", VX (4,1325), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}},
3286 {"evmhogsmfaa", VX (4,1327), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}},
3287 {"evmwlusiaaw", VX (4,1344), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}},
3288 {"evmwlssiaaw", VX (4,1345), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}},
3289 {"vavgsh", VX (4,1346), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}},
3290 {"udi5fcm.", APU(4, 675,0), APU_MASK, PPC405|PPC440, PPC476, {URT, URA, URB}},
3291 {"udi5fcm", APU(4, 675,1), APU_MASK, PPC405|PPC440, PPC476, {URT, URA, URB}},
3292 {"evmwlumiaaw", VX (4,1352), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}},
3293 {"evmwlsmiaaw", VX (4,1353), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}},
3294 {"evmwssfaa", VX (4,1363), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}},
3295 {"macchwo", XO (4, 172,1,0),XO_MASK, MULHW|PPCVLE, PPCNONE, {RT, RA, RB}},
3296 {"evmwumiaa", VX (4,1368), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}},
3297 {"macchwo.", XO (4, 172,1,1),XO_MASK, MULHW|PPCVLE, PPCNONE, {RT, RA, RB}},
3298 {"evmwsmiaa", VX (4,1369), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}},
3299 {"evmwsmfaa", VX (4,1371), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}},
3300 {"nmacchwo", XO (4, 174,1,0),XO_MASK, MULHW|PPCVLE, PPCNONE, {RT, RA, RB}},
3301 {"nmacchwo.", XO (4, 174,1,1),XO_MASK, MULHW|PPCVLE, PPCNONE, {RT, RA, RB}},
3302 {"evmheusianw", VX (4,1408), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}},
3303 {"vsubcuw", VX (4,1408), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}},
3304 {"evmhessianw", VX (4,1409), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}},
3305 {"vavgsw", VX (4,1410), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}},
3306 {"evmhessfanw", VX (4,1411), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}},
3307 {"evmhousianw", VX (4,1412), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}},
3308 {"evmhossianw", VX (4,1413), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}},
3309 {"udi6fcm.", APU(4, 707,0), APU_MASK, PPC405|PPC440, PPC476, {URT, URA, URB}},
3310 {"udi6fcm", APU(4, 707,1), APU_MASK, PPC405|PPC440, PPC476, {URT, URA, URB}},
3311 {"evmhossfanw", VX (4,1415), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}},
3312 {"evmheumianw", VX (4,1416), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}},
3313 {"evmhesmianw", VX (4,1417), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}},
3314 {"evmhesmfanw", VX (4,1419), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}},
3315 {"evmhoumianw", VX (4,1420), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}},
3316 {"evmhosmianw", VX (4,1421), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}},
3317 {"evmhosmfanw", VX (4,1423), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}},
3318 {"macchwsuo", XO (4, 204,1,0),XO_MASK, MULHW|PPCVLE, PPCNONE, {RT, RA, RB}},
3319 {"macchwsuo.", XO (4, 204,1,1),XO_MASK, MULHW|PPCVLE, PPCNONE, {RT, RA, RB}},
3320 {"evmhegumian", VX (4,1448), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}},
3321 {"evmhegsmian", VX (4,1449), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}},
3322 {"evmhegsmfan", VX (4,1451), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}},
3323 {"evmhogumian", VX (4,1452), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}},
3324 {"evmhogsmian", VX (4,1453), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}},
3325 {"evmhogsmfan", VX (4,1455), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}},
3326 {"evmwlusianw", VX (4,1472), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}},
3327 {"evmwlssianw", VX (4,1473), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}},
3328 {"vcmpgefp.", VXR(4, 454,1), VXR_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}},
3329 {"udi7fcm.", APU(4, 739,0), APU_MASK, PPC405|PPC440, PPC476, {URT, URA, URB}},
3330 {"udi7fcm", APU(4, 739,1), APU_MASK, PPC405|PPC440, PPC476, {URT, URA, URB}},
3331 {"evmwlumianw", VX (4,1480), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}},
3332 {"evmwlsmianw", VX (4,1481), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}},
3333 {"evmwssfan", VX (4,1491), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}},
3334 {"macchwso", XO (4, 236,1,0),XO_MASK, MULHW|PPCVLE, PPCNONE, {RT, RA, RB}},
3335 {"evmwumian", VX (4,1496), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}},
3336 {"macchwso.", XO (4, 236,1,1),XO_MASK, MULHW|PPCVLE, PPCNONE, {RT, RA, RB}},
3337 {"evmwsmian", VX (4,1497), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}},
3338 {"evmwsmfan", VX (4,1499), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}},
3339 {"nmacchwso", XO (4, 238,1,0),XO_MASK, MULHW|PPCVLE, PPCNONE, {RT, RA, RB}},
3340 {"nmacchwso.", XO (4, 238,1,1),XO_MASK, MULHW|PPCVLE, PPCNONE, {RT, RA, RB}},
3341 {"vsububs", VX (4,1536), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}},
3342 {"mfvscr", VX (4,1540), VXVAVB_MASK, PPCVEC|PPCVLE, PPCNONE, {VD}},
3343 {"vcmpgtub.", VXR(4, 518,1), VXR_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}},
3344 {"udi8fcm.", APU(4, 771,0), APU_MASK, PPC440, PPC476, {URT, URA, URB}},
3345 {"udi8fcm", APU(4, 771,1), APU_MASK, PPC440, PPC476, {URT, URA, URB}},
3346 {"vsum4ubs", VX (4,1544), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}},
3347 {"vsubuhs", VX (4,1600), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}},
3348 {"mtvscr", VX (4,1604), VXVDVA_MASK, PPCVEC|PPCVLE, PPCNONE, {VB}},
3349 {"vcmpgtuh.", VXR(4, 582,1), VXR_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}},
3350 {"vsum4shs", VX (4,1608), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}},
3351 {"udi9fcm.", APU(4, 804,0), APU_MASK, PPC440, PPC476, {URT, URA, URB}},
3352 {"udi9fcm", APU(4, 804,1), APU_MASK, PPC440, PPC476, {URT, URA, URB}},
3353 {"vsubuws", VX (4,1664), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}},
3354 {"vcmpgtuw.", VXR(4, 646,1), VXR_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}},
3355 {"udi10fcm.", APU(4, 835,0), APU_MASK, PPC440, PPC476, {URT, URA, URB}},
3356 {"udi10fcm", APU(4, 835,1), APU_MASK, PPC440, PPC476, {URT, URA, URB}},
3357 {"vsum2sws", VX (4,1672), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}},
3358 {"vcmpgtfp.", VXR(4, 710,1), VXR_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}},
3359 {"udi11fcm.", APU(4, 867,0), APU_MASK, PPC440, PPC476, {URT, URA, URB}},
3360 {"udi11fcm", APU(4, 867,1), APU_MASK, PPC440, PPC476, {URT, URA, URB}},
3361 {"vsubsbs", VX (4,1792), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}},
3362 {"vcmpgtsb.", VXR(4, 774,1), VXR_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}},
3363 {"udi12fcm.", APU(4, 899,0), APU_MASK, PPC440, PPC476, {URT, URA, URB}},
3364 {"udi12fcm", APU(4, 899,1), APU_MASK, PPC440, PPC476, {URT, URA, URB}},
3365 {"vsum4sbs", VX (4,1800), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}},
3366 {"maclhwuo", XO (4, 396,1,0),XO_MASK, MULHW|PPCVLE, PPCNONE, {RT, RA, RB}},
3367 {"maclhwuo.", XO (4, 396,1,1),XO_MASK, MULHW|PPCVLE, PPCNONE, {RT, RA, RB}},
3368 {"vsubshs", VX (4,1856), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}},
3369 {"vcmpgtsh.", VXR(4, 838,1), VXR_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}},
3370 {"udi13fcm.", APU(4, 931,0), APU_MASK, PPC440, PPC476, {URT, URA, URB}},
3371 {"udi13fcm", APU(4, 931,1), APU_MASK, PPC440, PPC476, {URT, URA, URB}},
3372 {"maclhwo", XO (4, 428,1,0),XO_MASK, MULHW|PPCVLE, PPCNONE, {RT, RA, RB}},
3373 {"maclhwo.", XO (4, 428,1,1),XO_MASK, MULHW|PPCVLE, PPCNONE, {RT, RA, RB}},
3374 {"nmaclhwo", XO (4, 430,1,0),XO_MASK, MULHW|PPCVLE, PPCNONE, {RT, RA, RB}},
3375 {"nmaclhwo.", XO (4, 430,1,1),XO_MASK, MULHW|PPCVLE, PPCNONE, {RT, RA, RB}},
3376 {"vsubsws", VX (4,1920), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}},
3377 {"vcmpgtsw.", VXR(4, 902,1), VXR_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}},
3378 {"udi14fcm.", APU(4, 963,0), APU_MASK, PPC440, PPC476, {URT, URA, URB}},
3379 {"udi14fcm", APU(4, 963,1), APU_MASK, PPC440, PPC476, {URT, URA, URB}},
3380 {"vsumsws", VX (4,1928), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}},
3381 {"maclhwsuo", XO (4, 460,1,0),XO_MASK, MULHW|PPCVLE, PPCNONE, {RT, RA, RB}},
3382 {"maclhwsuo.", XO (4, 460,1,1),XO_MASK, MULHW|PPCVLE, PPCNONE, {RT, RA, RB}},
3383 {"vcmpbfp.", VXR(4, 966,1), VXR_MASK, PPCVEC, PPCNONE, {VD, VA, VB}},
3384 {"udi15fcm.", APU(4, 995,0), APU_MASK, PPC440, PPC476, {URT, URA, URB}},
3385 {"udi15fcm", APU(4, 995,1), APU_MASK, PPC440, PPC476, {URT, URA, URB}},
3386 {"maclhwso", XO (4, 492,1,0),XO_MASK, MULHW|PPCVLE, PPCNONE, {RT, RA, RB}},
3387 {"maclhwso.", XO (4, 492,1,1),XO_MASK, MULHW|PPCVLE, PPCNONE, {RT, RA, RB}},
3388 {"nmaclhwso", XO (4, 494,1,0),XO_MASK, MULHW|PPCVLE, PPCNONE, {RT, RA, RB}},
3389 {"nmaclhwso.", XO (4, 494,1,1),XO_MASK, MULHW|PPCVLE, PPCNONE, {RT, RA, RB}},
3390 {"dcbz_l", X (4,1014), XRT_MASK, PPCPS, PPCNONE, {RA, RB}},
3391
3392 {"mulli", OP(7), OP_MASK, PPCCOM, PPCNONE, {RT, RA, SI}},
3393 {"muli", OP(7), OP_MASK, PWRCOM, PPCNONE, {RT, RA, SI}},
3394
3395 {"subfic", OP(8), OP_MASK, PPCCOM, PPCNONE, {RT, RA, SI}},
3396 {"sfi", OP(8), OP_MASK, PWRCOM, PPCNONE, {RT, RA, SI}},
3397
3398 {"dozi", OP(9), OP_MASK, M601, PPCNONE, {RT, RA, SI}},
3399
3400 {"cmplwi", OPL(10,0), OPL_MASK, PPCCOM, PPCNONE, {OBF, RA, UI}},
3401 {"cmpldi", OPL(10,1), OPL_MASK, PPC64, PPCNONE, {OBF, RA, UI}},
3402 {"cmpli", OP(10), OP_MASK, PPC, PPCNONE, {BF, L, RA, UI}},
3403 {"cmpli", OP(10), OP_MASK, PWRCOM, PPC, {BF, RA, UI}},
3404
3405 {"cmpwi", OPL(11,0), OPL_MASK, PPCCOM, PPCNONE, {OBF, RA, SI}},
3406 {"cmpdi", OPL(11,1), OPL_MASK, PPC64, PPCNONE, {OBF, RA, SI}},
3407 {"cmpi", OP(11), OP_MASK, PPC, PPCNONE, {BF, L, RA, SI}},
3408 {"cmpi", OP(11), OP_MASK, PWRCOM, PPC, {BF, RA, SI}},
3409
3410 {"addic", OP(12), OP_MASK, PPCCOM, PPCNONE, {RT, RA, SI}},
3411 {"ai", OP(12), OP_MASK, PWRCOM, PPCNONE, {RT, RA, SI}},
3412 {"subic", OP(12), OP_MASK, PPCCOM, PPCNONE, {RT, RA, NSI}},
3413
3414 {"addic.", OP(13), OP_MASK, PPCCOM, PPCNONE, {RT, RA, SI}},
3415 {"ai.", OP(13), OP_MASK, PWRCOM, PPCNONE, {RT, RA, SI}},
3416 {"subic.", OP(13), OP_MASK, PPCCOM, PPCNONE, {RT, RA, NSI}},
3417
3418 {"li", OP(14), DRA_MASK, PPCCOM, PPCNONE, {RT, SI}},
3419 {"lil", OP(14), DRA_MASK, PWRCOM, PPCNONE, {RT, SI}},
3420 {"addi", OP(14), OP_MASK, PPCCOM, PPCNONE, {RT, RA0, SI}},
3421 {"cal", OP(14), OP_MASK, PWRCOM, PPCNONE, {RT, D, RA0}},
3422 {"subi", OP(14), OP_MASK, PPCCOM, PPCNONE, {RT, RA0, NSI}},
3423 {"la", OP(14), OP_MASK, PPCCOM, PPCNONE, {RT, D, RA0}},
3424
3425 {"lis", OP(15), DRA_MASK, PPCCOM, PPCNONE, {RT, SISIGNOPT}},
3426 {"liu", OP(15), DRA_MASK, PWRCOM, PPCNONE, {RT, SISIGNOPT}},
3427 {"addis", OP(15), OP_MASK, PPCCOM, PPCNONE, {RT, RA0, SISIGNOPT}},
3428 {"cau", OP(15), OP_MASK, PWRCOM, PPCNONE, {RT, RA0, SISIGNOPT}},
3429 {"subis", OP(15), OP_MASK, PPCCOM, PPCNONE, {RT, RA0, NSI}},
3430
3431 {"bdnz-", BBO(16,BODNZ,0,0), BBOATBI_MASK, PPCCOM, PPCNONE, {BDM}},
3432 {"bdnz+", BBO(16,BODNZ,0,0), BBOATBI_MASK, PPCCOM, PPCNONE, {BDP}},
3433 {"bdnz", BBO(16,BODNZ,0,0), BBOATBI_MASK, PPCCOM, PPCNONE, {BD}},
3434 {"bdn", BBO(16,BODNZ,0,0), BBOATBI_MASK, PWRCOM, PPCNONE, {BD}},
3435 {"bdnzl-", BBO(16,BODNZ,0,1), BBOATBI_MASK, PPCCOM, PPCNONE, {BDM}},
3436 {"bdnzl+", BBO(16,BODNZ,0,1), BBOATBI_MASK, PPCCOM, PPCNONE, {BDP}},
3437 {"bdnzl", BBO(16,BODNZ,0,1), BBOATBI_MASK, PPCCOM, PPCNONE, {BD}},
3438 {"bdnl", BBO(16,BODNZ,0,1), BBOATBI_MASK, PWRCOM, PPCNONE, {BD}},
3439 {"bdnza-", BBO(16,BODNZ,1,0), BBOATBI_MASK, PPCCOM, PPCNONE, {BDMA}},
3440 {"bdnza+", BBO(16,BODNZ,1,0), BBOATBI_MASK, PPCCOM, PPCNONE, {BDPA}},
3441 {"bdnza", BBO(16,BODNZ,1,0), BBOATBI_MASK, PPCCOM, PPCNONE, {BDA}},
3442 {"bdna", BBO(16,BODNZ,1,0), BBOATBI_MASK, PWRCOM, PPCNONE, {BDA}},
3443 {"bdnzla-", BBO(16,BODNZ,1,1), BBOATBI_MASK, PPCCOM, PPCNONE, {BDMA}},
3444 {"bdnzla+", BBO(16,BODNZ,1,1), BBOATBI_MASK, PPCCOM, PPCNONE, {BDPA}},
3445 {"bdnzla", BBO(16,BODNZ,1,1), BBOATBI_MASK, PPCCOM, PPCNONE, {BDA}},
3446 {"bdnla", BBO(16,BODNZ,1,1), BBOATBI_MASK, PWRCOM, PPCNONE, {BDA}},
3447 {"bdz-", BBO(16,BODZ,0,0), BBOATBI_MASK, PPCCOM, PPCNONE, {BDM}},
3448 {"bdz+", BBO(16,BODZ,0,0), BBOATBI_MASK, PPCCOM, PPCNONE, {BDP}},
3449 {"bdz", BBO(16,BODZ,0,0), BBOATBI_MASK, COM, PPCNONE, {BD}},
3450 {"bdzl-", BBO(16,BODZ,0,1), BBOATBI_MASK, PPCCOM, PPCNONE, {BDM}},
3451 {"bdzl+", BBO(16,BODZ,0,1), BBOATBI_MASK, PPCCOM, PPCNONE, {BDP}},
3452 {"bdzl", BBO(16,BODZ,0,1), BBOATBI_MASK, COM, PPCNONE, {BD}},
3453 {"bdza-", BBO(16,BODZ,1,0), BBOATBI_MASK, PPCCOM, PPCNONE, {BDMA}},
3454 {"bdza+", BBO(16,BODZ,1,0), BBOATBI_MASK, PPCCOM, PPCNONE, {BDPA}},
3455 {"bdza", BBO(16,BODZ,1,0), BBOATBI_MASK, COM, PPCNONE, {BDA}},
3456 {"bdzla-", BBO(16,BODZ,1,1), BBOATBI_MASK, PPCCOM, PPCNONE, {BDMA}},
3457 {"bdzla+", BBO(16,BODZ,1,1), BBOATBI_MASK, PPCCOM, PPCNONE, {BDPA}},
3458 {"bdzla", BBO(16,BODZ,1,1), BBOATBI_MASK, COM, PPCNONE, {BDA}},
3459
3460 {"bge-", BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDM}},
3461 {"bge+", BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDP}},
3462 {"bge", BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, COM, PPCNONE, {CR, BD}},
3463 {"bnl-", BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDM}},
3464 {"bnl+", BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDP}},
3465 {"bnl", BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, COM, PPCNONE, {CR, BD}},
3466 {"bgel-", BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDM}},
3467 {"bgel+", BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDP}},
3468 {"bgel", BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, COM, PPCNONE, {CR, BD}},
3469 {"bnll-", BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDM}},
3470 {"bnll+", BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDP}},
3471 {"bnll", BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, COM, PPCNONE, {CR, BD}},
3472 {"bgea-", BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDMA}},
3473 {"bgea+", BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDPA}},
3474 {"bgea", BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, COM, PPCNONE, {CR, BDA}},
3475 {"bnla-", BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDMA}},
3476 {"bnla+", BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDPA}},
3477 {"bnla", BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, COM, PPCNONE, {CR, BDA}},
3478 {"bgela-", BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDMA}},
3479 {"bgela+", BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDPA}},
3480 {"bgela", BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, COM, PPCNONE, {CR, BDA}},
3481 {"bnlla-", BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDMA}},
3482 {"bnlla+", BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDPA}},
3483 {"bnlla", BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, COM, PPCNONE, {CR, BDA}},
3484 {"ble-", BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDM}},
3485 {"ble+", BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDP}},
3486 {"ble", BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, COM, PPCNONE, {CR, BD}},
3487 {"bng-", BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDM}},
3488 {"bng+", BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDP}},
3489 {"bng", BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, COM, PPCNONE, {CR, BD}},
3490 {"blel-", BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDM}},
3491 {"blel+", BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDP}},
3492 {"blel", BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, COM, PPCNONE, {CR, BD}},
3493 {"bngl-", BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDM}},
3494 {"bngl+", BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDP}},
3495 {"bngl", BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, COM, PPCNONE, {CR, BD}},
3496 {"blea-", BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDMA}},
3497 {"blea+", BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDPA}},
3498 {"blea", BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, COM, PPCNONE, {CR, BDA}},
3499 {"bnga-", BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDMA}},
3500 {"bnga+", BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDPA}},
3501 {"bnga", BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, COM, PPCNONE, {CR, BDA}},
3502 {"blela-", BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDMA}},
3503 {"blela+", BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDPA}},
3504 {"blela", BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, COM, PPCNONE, {CR, BDA}},
3505 {"bngla-", BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDMA}},
3506 {"bngla+", BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDPA}},
3507 {"bngla", BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, COM, PPCNONE, {CR, BDA}},
3508 {"bne-", BBOCB(16,BOF,CBEQ,0,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDM}},
3509 {"bne+", BBOCB(16,BOF,CBEQ,0,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDP}},
3510 {"bne", BBOCB(16,BOF,CBEQ,0,0), BBOATCB_MASK, COM, PPCNONE, {CR, BD}},
3511 {"bnel-", BBOCB(16,BOF,CBEQ,0,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDM}},
3512 {"bnel+", BBOCB(16,BOF,CBEQ,0,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDP}},
3513 {"bnel", BBOCB(16,BOF,CBEQ,0,1), BBOATCB_MASK, COM, PPCNONE, {CR, BD}},
3514 {"bnea-", BBOCB(16,BOF,CBEQ,1,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDMA}},
3515 {"bnea+", BBOCB(16,BOF,CBEQ,1,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDPA}},
3516 {"bnea", BBOCB(16,BOF,CBEQ,1,0), BBOATCB_MASK, COM, PPCNONE, {CR, BDA}},
3517 {"bnela-", BBOCB(16,BOF,CBEQ,1,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDMA}},
3518 {"bnela+", BBOCB(16,BOF,CBEQ,1,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDPA}},
3519 {"bnela", BBOCB(16,BOF,CBEQ,1,1), BBOATCB_MASK, COM, PPCNONE, {CR, BDA}},
3520 {"bns-", BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDM}},
3521 {"bns+", BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDP}},
3522 {"bns", BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, COM, PPCNONE, {CR, BD}},
3523 {"bnu-", BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDM}},
3524 {"bnu+", BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDP}},
3525 {"bnu", BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BD}},
3526 {"bnsl-", BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDM}},
3527 {"bnsl+", BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDP}},
3528 {"bnsl", BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, COM, PPCNONE, {CR, BD}},
3529 {"bnul-", BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDM}},
3530 {"bnul+", BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDP}},
3531 {"bnul", BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BD}},
3532 {"bnsa-", BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDMA}},
3533 {"bnsa+", BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDPA}},
3534 {"bnsa", BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, COM, PPCNONE, {CR, BDA}},
3535 {"bnua-", BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDMA}},
3536 {"bnua+", BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDPA}},
3537 {"bnua", BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDA}},
3538 {"bnsla-", BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDMA}},
3539 {"bnsla+", BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDPA}},
3540 {"bnsla", BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, COM, PPCNONE, {CR, BDA}},
3541 {"bnula-", BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDMA}},
3542 {"bnula+", BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDPA}},
3543 {"bnula", BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDA}},
3544
3545 {"blt-", BBOCB(16,BOT,CBLT,0,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDM}},
3546 {"blt+", BBOCB(16,BOT,CBLT,0,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDP}},
3547 {"blt", BBOCB(16,BOT,CBLT,0,0), BBOATCB_MASK, COM, PPCNONE, {CR, BD}},
3548 {"bltl-", BBOCB(16,BOT,CBLT,0,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDM}},
3549 {"bltl+", BBOCB(16,BOT,CBLT,0,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDP}},
3550 {"bltl", BBOCB(16,BOT,CBLT,0,1), BBOATCB_MASK, COM, PPCNONE, {CR, BD}},
3551 {"blta-", BBOCB(16,BOT,CBLT,1,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDMA}},
3552 {"blta+", BBOCB(16,BOT,CBLT,1,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDPA}},
3553 {"blta", BBOCB(16,BOT,CBLT,1,0), BBOATCB_MASK, COM, PPCNONE, {CR, BDA}},
3554 {"bltla-", BBOCB(16,BOT,CBLT,1,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDMA}},
3555 {"bltla+", BBOCB(16,BOT,CBLT,1,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDPA}},
3556 {"bltla", BBOCB(16,BOT,CBLT,1,1), BBOATCB_MASK, COM, PPCNONE, {CR, BDA}},
3557 {"bgt-", BBOCB(16,BOT,CBGT,0,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDM}},
3558 {"bgt+", BBOCB(16,BOT,CBGT,0,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDP}},
3559 {"bgt", BBOCB(16,BOT,CBGT,0,0), BBOATCB_MASK, COM, PPCNONE, {CR, BD}},
3560 {"bgtl-", BBOCB(16,BOT,CBGT,0,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDM}},
3561 {"bgtl+", BBOCB(16,BOT,CBGT,0,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDP}},
3562 {"bgtl", BBOCB(16,BOT,CBGT,0,1), BBOATCB_MASK, COM, PPCNONE, {CR, BD}},
3563 {"bgta-", BBOCB(16,BOT,CBGT,1,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDMA}},
3564 {"bgta+", BBOCB(16,BOT,CBGT,1,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDPA}},
3565 {"bgta", BBOCB(16,BOT,CBGT,1,0), BBOATCB_MASK, COM, PPCNONE, {CR, BDA}},
3566 {"bgtla-", BBOCB(16,BOT,CBGT,1,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDMA}},
3567 {"bgtla+", BBOCB(16,BOT,CBGT,1,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDPA}},
3568 {"bgtla", BBOCB(16,BOT,CBGT,1,1), BBOATCB_MASK, COM, PPCNONE, {CR, BDA}},
3569 {"beq-", BBOCB(16,BOT,CBEQ,0,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDM}},
3570 {"beq+", BBOCB(16,BOT,CBEQ,0,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDP}},
3571 {"beq", BBOCB(16,BOT,CBEQ,0,0), BBOATCB_MASK, COM, PPCNONE, {CR, BD}},
3572 {"beql-", BBOCB(16,BOT,CBEQ,0,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDM}},
3573 {"beql+", BBOCB(16,BOT,CBEQ,0,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDP}},
3574 {"beql", BBOCB(16,BOT,CBEQ,0,1), BBOATCB_MASK, COM, PPCNONE, {CR, BD}},
3575 {"beqa-", BBOCB(16,BOT,CBEQ,1,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDMA}},
3576 {"beqa+", BBOCB(16,BOT,CBEQ,1,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDPA}},
3577 {"beqa", BBOCB(16,BOT,CBEQ,1,0), BBOATCB_MASK, COM, PPCNONE, {CR, BDA}},
3578 {"beqla-", BBOCB(16,BOT,CBEQ,1,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDMA}},
3579 {"beqla+", BBOCB(16,BOT,CBEQ,1,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDPA}},
3580 {"beqla", BBOCB(16,BOT,CBEQ,1,1), BBOATCB_MASK, COM, PPCNONE, {CR, BDA}},
3581 {"bso-", BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDM}},
3582 {"bso+", BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDP}},
3583 {"bso", BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, COM, PPCNONE, {CR, BD}},
3584 {"bun-", BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDM}},
3585 {"bun+", BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDP}},
3586 {"bun", BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BD}},
3587 {"bsol-", BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDM}},
3588 {"bsol+", BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDP}},
3589 {"bsol", BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, COM, PPCNONE, {CR, BD}},
3590 {"bunl-", BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDM}},
3591 {"bunl+", BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDP}},
3592 {"bunl", BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BD}},
3593 {"bsoa-", BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDMA}},
3594 {"bsoa+", BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDPA}},
3595 {"bsoa", BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, COM, PPCNONE, {CR, BDA}},
3596 {"buna-", BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDMA}},
3597 {"buna+", BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDPA}},
3598 {"buna", BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDA}},
3599 {"bsola-", BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDMA}},
3600 {"bsola+", BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDPA}},
3601 {"bsola", BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, COM, PPCNONE, {CR, BDA}},
3602 {"bunla-", BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDMA}},
3603 {"bunla+", BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDPA}},
3604 {"bunla", BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDA}},
3605
3606 {"bdnzf-", BBO(16,BODNZF,0,0), BBOY_MASK, PPCCOM, ISA_V2, {BI, BDM}},
3607 {"bdnzf+", BBO(16,BODNZF,0,0), BBOY_MASK, PPCCOM, ISA_V2, {BI, BDP}},
3608 {"bdnzf", BBO(16,BODNZF,0,0), BBOY_MASK, PPCCOM, PPCNONE, {BI, BD}},
3609 {"bdnzfl-", BBO(16,BODNZF,0,1), BBOY_MASK, PPCCOM, ISA_V2, {BI, BDM}},
3610 {"bdnzfl+", BBO(16,BODNZF,0,1), BBOY_MASK, PPCCOM, ISA_V2, {BI, BDP}},
3611 {"bdnzfl", BBO(16,BODNZF,0,1), BBOY_MASK, PPCCOM, PPCNONE, {BI, BD}},
3612 {"bdnzfa-", BBO(16,BODNZF,1,0), BBOY_MASK, PPCCOM, ISA_V2, {BI, BDMA}},
3613 {"bdnzfa+", BBO(16,BODNZF,1,0), BBOY_MASK, PPCCOM, ISA_V2, {BI, BDPA}},
3614 {"bdnzfa", BBO(16,BODNZF,1,0), BBOY_MASK, PPCCOM, PPCNONE, {BI, BDA}},
3615 {"bdnzfla-", BBO(16,BODNZF,1,1), BBOY_MASK, PPCCOM, ISA_V2, {BI, BDMA}},
3616 {"bdnzfla+", BBO(16,BODNZF,1,1), BBOY_MASK, PPCCOM, ISA_V2, {BI, BDPA}},
3617 {"bdnzfla", BBO(16,BODNZF,1,1), BBOY_MASK, PPCCOM, PPCNONE, {BI, BDA}},
3618 {"bdzf-", BBO(16,BODZF,0,0), BBOY_MASK, PPCCOM, ISA_V2, {BI, BDM}},
3619 {"bdzf+", BBO(16,BODZF,0,0), BBOY_MASK, PPCCOM, ISA_V2, {BI, BDP}},
3620 {"bdzf", BBO(16,BODZF,0,0), BBOY_MASK, PPCCOM, PPCNONE, {BI, BD}},
3621 {"bdzfl-", BBO(16,BODZF,0,1), BBOY_MASK, PPCCOM, ISA_V2, {BI, BDM}},
3622 {"bdzfl+", BBO(16,BODZF,0,1), BBOY_MASK, PPCCOM, ISA_V2, {BI, BDP}},
3623 {"bdzfl", BBO(16,BODZF,0,1), BBOY_MASK, PPCCOM, PPCNONE, {BI, BD}},
3624 {"bdzfa-", BBO(16,BODZF,1,0), BBOY_MASK, PPCCOM, ISA_V2, {BI, BDMA}},
3625 {"bdzfa+", BBO(16,BODZF,1,0), BBOY_MASK, PPCCOM, ISA_V2, {BI, BDPA}},
3626 {"bdzfa", BBO(16,BODZF,1,0), BBOY_MASK, PPCCOM, PPCNONE, {BI, BDA}},
3627 {"bdzfla-", BBO(16,BODZF,1,1), BBOY_MASK, PPCCOM, ISA_V2, {BI, BDMA}},
3628 {"bdzfla+", BBO(16,BODZF,1,1), BBOY_MASK, PPCCOM, ISA_V2, {BI, BDPA}},
3629 {"bdzfla", BBO(16,BODZF,1,1), BBOY_MASK, PPCCOM, PPCNONE, {BI, BDA}},
3630
3631 {"bf-", BBO(16,BOF,0,0), BBOAT_MASK, PPCCOM, PPCNONE, {BI, BDM}},
3632 {"bf+", BBO(16,BOF,0,0), BBOAT_MASK, PPCCOM, PPCNONE, {BI, BDP}},
3633 {"bf", BBO(16,BOF,0,0), BBOAT_MASK, PPCCOM, PPCNONE, {BI, BD}},
3634 {"bbf", BBO(16,BOF,0,0), BBOAT_MASK, PWRCOM, PPCNONE, {BI, BD}},
3635 {"bfl-", BBO(16,BOF,0,1), BBOAT_MASK, PPCCOM, PPCNONE, {BI, BDM}},
3636 {"bfl+", BBO(16,BOF,0,1), BBOAT_MASK, PPCCOM, PPCNONE, {BI, BDP}},
3637 {"bfl", BBO(16,BOF,0,1), BBOAT_MASK, PPCCOM, PPCNONE, {BI, BD}},
3638 {"bbfl", BBO(16,BOF,0,1), BBOAT_MASK, PWRCOM, PPCNONE, {BI, BD}},
3639 {"bfa-", BBO(16,BOF,1,0), BBOAT_MASK, PPCCOM, PPCNONE, {BI, BDMA}},
3640 {"bfa+", BBO(16,BOF,1,0), BBOAT_MASK, PPCCOM, PPCNONE, {BI, BDPA}},
3641 {"bfa", BBO(16,BOF,1,0), BBOAT_MASK, PPCCOM, PPCNONE, {BI, BDA}},
3642 {"bbfa", BBO(16,BOF,1,0), BBOAT_MASK, PWRCOM, PPCNONE, {BI, BDA}},
3643 {"bfla-", BBO(16,BOF,1,1), BBOAT_MASK, PPCCOM, PPCNONE, {BI, BDMA}},
3644 {"bfla+", BBO(16,BOF,1,1), BBOAT_MASK, PPCCOM, PPCNONE, {BI, BDPA}},
3645 {"bfla", BBO(16,BOF,1,1), BBOAT_MASK, PPCCOM, PPCNONE, {BI, BDA}},
3646 {"bbfla", BBO(16,BOF,1,1), BBOAT_MASK, PWRCOM, PPCNONE, {BI, BDA}},
3647
3648 {"bdnzt-", BBO(16,BODNZT,0,0), BBOY_MASK, PPCCOM, ISA_V2, {BI, BDM}},
3649 {"bdnzt+", BBO(16,BODNZT,0,0), BBOY_MASK, PPCCOM, ISA_V2, {BI, BDP}},
3650 {"bdnzt", BBO(16,BODNZT,0,0), BBOY_MASK, PPCCOM, PPCNONE, {BI, BD}},
3651 {"bdnztl-", BBO(16,BODNZT,0,1), BBOY_MASK, PPCCOM, ISA_V2, {BI, BDM}},
3652 {"bdnztl+", BBO(16,BODNZT,0,1), BBOY_MASK, PPCCOM, ISA_V2, {BI, BDP}},
3653 {"bdnztl", BBO(16,BODNZT,0,1), BBOY_MASK, PPCCOM, PPCNONE, {BI, BD}},
3654 {"bdnzta-", BBO(16,BODNZT,1,0), BBOY_MASK, PPCCOM, ISA_V2, {BI, BDMA}},
3655 {"bdnzta+", BBO(16,BODNZT,1,0), BBOY_MASK, PPCCOM, ISA_V2, {BI, BDPA}},
3656 {"bdnzta", BBO(16,BODNZT,1,0), BBOY_MASK, PPCCOM, PPCNONE, {BI, BDA}},
3657 {"bdnztla-", BBO(16,BODNZT,1,1), BBOY_MASK, PPCCOM, ISA_V2, {BI, BDMA}},
3658 {"bdnztla+", BBO(16,BODNZT,1,1), BBOY_MASK, PPCCOM, ISA_V2, {BI, BDPA}},
3659 {"bdnztla", BBO(16,BODNZT,1,1), BBOY_MASK, PPCCOM, PPCNONE, {BI, BDA}},
3660 {"bdzt-", BBO(16,BODZT,0,0), BBOY_MASK, PPCCOM, ISA_V2, {BI, BDM}},
3661 {"bdzt+", BBO(16,BODZT,0,0), BBOY_MASK, PPCCOM, ISA_V2, {BI, BDP}},
3662 {"bdzt", BBO(16,BODZT,0,0), BBOY_MASK, PPCCOM, PPCNONE, {BI, BD}},
3663 {"bdztl-", BBO(16,BODZT,0,1), BBOY_MASK, PPCCOM, ISA_V2, {BI, BDM}},
3664 {"bdztl+", BBO(16,BODZT,0,1), BBOY_MASK, PPCCOM, ISA_V2, {BI, BDP}},
3665 {"bdztl", BBO(16,BODZT,0,1), BBOY_MASK, PPCCOM, PPCNONE, {BI, BD}},
3666 {"bdzta-", BBO(16,BODZT,1,0), BBOY_MASK, PPCCOM, ISA_V2, {BI, BDMA}},
3667 {"bdzta+", BBO(16,BODZT,1,0), BBOY_MASK, PPCCOM, ISA_V2, {BI, BDPA}},
3668 {"bdzta", BBO(16,BODZT,1,0), BBOY_MASK, PPCCOM, PPCNONE, {BI, BDA}},
3669 {"bdztla-", BBO(16,BODZT,1,1), BBOY_MASK, PPCCOM, ISA_V2, {BI, BDMA}},
3670 {"bdztla+", BBO(16,BODZT,1,1), BBOY_MASK, PPCCOM, ISA_V2, {BI, BDPA}},
3671 {"bdztla", BBO(16,BODZT,1,1), BBOY_MASK, PPCCOM, PPCNONE, {BI, BDA}},
3672
3673 {"bt-", BBO(16,BOT,0,0), BBOAT_MASK, PPCCOM, PPCNONE, {BI, BDM}},
3674 {"bt+", BBO(16,BOT,0,0), BBOAT_MASK, PPCCOM, PPCNONE, {BI, BDP}},
3675 {"bt", BBO(16,BOT,0,0), BBOAT_MASK, PPCCOM, PPCNONE, {BI, BD}},
3676 {"bbt", BBO(16,BOT,0,0), BBOAT_MASK, PWRCOM, PPCNONE, {BI, BD}},
3677 {"btl-", BBO(16,BOT,0,1), BBOAT_MASK, PPCCOM, PPCNONE, {BI, BDM}},
3678 {"btl+", BBO(16,BOT,0,1), BBOAT_MASK, PPCCOM, PPCNONE, {BI, BDP}},
3679 {"btl", BBO(16,BOT,0,1), BBOAT_MASK, PPCCOM, PPCNONE, {BI, BD}},
3680 {"bbtl", BBO(16,BOT,0,1), BBOAT_MASK, PWRCOM, PPCNONE, {BI, BD}},
3681 {"bta-", BBO(16,BOT,1,0), BBOAT_MASK, PPCCOM, PPCNONE, {BI, BDMA}},
3682 {"bta+", BBO(16,BOT,1,0), BBOAT_MASK, PPCCOM, PPCNONE, {BI, BDPA}},
3683 {"bta", BBO(16,BOT,1,0), BBOAT_MASK, PPCCOM, PPCNONE, {BI, BDA}},
3684 {"bbta", BBO(16,BOT,1,0), BBOAT_MASK, PWRCOM, PPCNONE, {BI, BDA}},
3685 {"btla-", BBO(16,BOT,1,1), BBOAT_MASK, PPCCOM, PPCNONE, {BI, BDMA}},
3686 {"btla+", BBO(16,BOT,1,1), BBOAT_MASK, PPCCOM, PPCNONE, {BI, BDPA}},
3687 {"btla", BBO(16,BOT,1,1), BBOAT_MASK, PPCCOM, PPCNONE, {BI, BDA}},
3688 {"bbtla", BBO(16,BOT,1,1), BBOAT_MASK, PWRCOM, PPCNONE, {BI, BDA}},
3689
3690 {"bc-", B(16,0,0), B_MASK, PPCCOM, PPCNONE, {BOE, BI, BDM}},
3691 {"bc+", B(16,0,0), B_MASK, PPCCOM, PPCNONE, {BOE, BI, BDP}},
3692 {"bc", B(16,0,0), B_MASK, COM, PPCNONE, {BO, BI, BD}},
3693 {"bcl-", B(16,0,1), B_MASK, PPCCOM, PPCNONE, {BOE, BI, BDM}},
3694 {"bcl+", B(16,0,1), B_MASK, PPCCOM, PPCNONE, {BOE, BI, BDP}},
3695 {"bcl", B(16,0,1), B_MASK, COM, PPCNONE, {BO, BI, BD}},
3696 {"bca-", B(16,1,0), B_MASK, PPCCOM, PPCNONE, {BOE, BI, BDMA}},
3697 {"bca+", B(16,1,0), B_MASK, PPCCOM, PPCNONE, {BOE, BI, BDPA}},
3698 {"bca", B(16,1,0), B_MASK, COM, PPCNONE, {BO, BI, BDA}},
3699 {"bcla-", B(16,1,1), B_MASK, PPCCOM, PPCNONE, {BOE, BI, BDMA}},
3700 {"bcla+", B(16,1,1), B_MASK, PPCCOM, PPCNONE, {BOE, BI, BDPA}},
3701 {"bcla", B(16,1,1), B_MASK, COM, PPCNONE, {BO, BI, BDA}},
3702
3703 {"svc", SC(17,0,0), SC_MASK, POWER, PPCNONE, {SVC_LEV, FL1, FL2}},
3704 {"svcl", SC(17,0,1), SC_MASK, POWER, PPCNONE, {SVC_LEV, FL1, FL2}},
3705 {"sc", SC(17,1,0), SC_MASK, PPC, PPCNONE, {LEV}},
3706 {"svca", SC(17,1,0), SC_MASK, PWRCOM, PPCNONE, {SV}},
3707 {"svcla", SC(17,1,1), SC_MASK, POWER, PPCNONE, {SV}},
3708
3709 {"b", B(18,0,0), B_MASK, COM, PPCNONE, {LI}},
3710 {"bl", B(18,0,1), B_MASK, COM, PPCNONE, {LI}},
3711 {"ba", B(18,1,0), B_MASK, COM, PPCNONE, {LIA}},
3712 {"bla", B(18,1,1), B_MASK, COM, PPCNONE, {LIA}},
3713
3714 {"mcrf", XL(19,0), XLBB_MASK|(3<<21)|(3<<16), COM, PPCNONE, {BF, BFA}},
3715
3716 {"bdnzlr", XLO(19,BODNZ,16,0), XLBOBIBB_MASK, PPCCOM, PPCNONE, {0}},
3717 {"bdnzlr-", XLO(19,BODNZ,16,0), XLBOBIBB_MASK, PPCCOM, ISA_V2, {0}},
3718 {"bdnzlrl", XLO(19,BODNZ,16,1), XLBOBIBB_MASK, PPCCOM, PPCNONE, {0}},
3719 {"bdnzlrl-", XLO(19,BODNZ,16,1), XLBOBIBB_MASK, PPCCOM, ISA_V2, {0}},
3720 {"bdnzlr+", XLO(19,BODNZP,16,0), XLBOBIBB_MASK, PPCCOM, ISA_V2, {0}},
3721 {"bdnzlrl+", XLO(19,BODNZP,16,1), XLBOBIBB_MASK, PPCCOM, ISA_V2, {0}},
3722 {"bdzlr", XLO(19,BODZ,16,0), XLBOBIBB_MASK, PPCCOM, PPCNONE, {0}},
3723 {"bdzlr-", XLO(19,BODZ,16,0), XLBOBIBB_MASK, PPCCOM, ISA_V2, {0}},
3724 {"bdzlrl", XLO(19,BODZ,16,1), XLBOBIBB_MASK, PPCCOM, PPCNONE, {0}},
3725 {"bdzlrl-", XLO(19,BODZ,16,1), XLBOBIBB_MASK, PPCCOM, ISA_V2, {0}},
3726 {"bdzlr+", XLO(19,BODZP,16,0), XLBOBIBB_MASK, PPCCOM, ISA_V2, {0}},
3727 {"bdzlrl+", XLO(19,BODZP,16,1), XLBOBIBB_MASK, PPCCOM, ISA_V2, {0}},
3728 {"blr", XLO(19,BOU,16,0), XLBOBIBB_MASK, PPCCOM, PPCNONE, {0}},
3729 {"br", XLO(19,BOU,16,0), XLBOBIBB_MASK, PWRCOM, PPCNONE, {0}},
3730 {"blrl", XLO(19,BOU,16,1), XLBOBIBB_MASK, PPCCOM, PPCNONE, {0}},
3731 {"brl", XLO(19,BOU,16,1), XLBOBIBB_MASK, PWRCOM, PPCNONE, {0}},
3732 {"bdnzlr-", XLO(19,BODNZM4,16,0), XLBOBIBB_MASK, ISA_V2, PPCNONE, {0}},
3733 {"bdnzlrl-", XLO(19,BODNZM4,16,1), XLBOBIBB_MASK, ISA_V2, PPCNONE, {0}},
3734 {"bdnzlr+", XLO(19,BODNZP4,16,0), XLBOBIBB_MASK, ISA_V2, PPCNONE, {0}},
3735 {"bdnzlrl+", XLO(19,BODNZP4,16,1), XLBOBIBB_MASK, ISA_V2, PPCNONE, {0}},
3736 {"bdzlr-", XLO(19,BODZM4,16,0), XLBOBIBB_MASK, ISA_V2, PPCNONE, {0}},
3737 {"bdzlrl-", XLO(19,BODZM4,16,1), XLBOBIBB_MASK, ISA_V2, PPCNONE, {0}},
3738 {"bdzlr+", XLO(19,BODZP4,16,0), XLBOBIBB_MASK, ISA_V2, PPCNONE, {0}},
3739 {"bdzlrl+", XLO(19,BODZP4,16,1), XLBOBIBB_MASK, ISA_V2, PPCNONE, {0}},
3740
3741 {"bgelr", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, PPCNONE, {CR}},
3742 {"bgelr-", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2, {CR}},
3743 {"bger", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PWRCOM, PPCNONE, {CR}},
3744 {"bnllr", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, PPCNONE, {CR}},
3745 {"bnllr-", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2, {CR}},
3746 {"bnlr", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PWRCOM, PPCNONE, {CR}},
3747 {"bgelrl", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, PPCNONE, {CR}},
3748 {"bgelrl-", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2, {CR}},
3749 {"bgerl", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PWRCOM, PPCNONE, {CR}},
3750 {"bnllrl", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, PPCNONE, {CR}},
3751 {"bnllrl-", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2, {CR}},
3752 {"bnlrl", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PWRCOM, PPCNONE, {CR}},
3753 {"blelr", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, PPCNONE, {CR}},
3754 {"blelr-", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2, {CR}},
3755 {"bler", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PWRCOM, PPCNONE, {CR}},
3756 {"bnglr", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, PPCNONE, {CR}},
3757 {"bnglr-", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2, {CR}},
3758 {"bngr", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PWRCOM, PPCNONE, {CR}},
3759 {"blelrl", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, PPCNONE, {CR}},
3760 {"blelrl-", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2, {CR}},
3761 {"blerl", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PWRCOM, PPCNONE, {CR}},
3762 {"bnglrl", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, PPCNONE, {CR}},
3763 {"bnglrl-", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2, {CR}},
3764 {"bngrl", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PWRCOM, PPCNONE, {CR}},
3765 {"bnelr", XLOCB(19,BOF,CBEQ,16,0), XLBOCBBB_MASK, PPCCOM, PPCNONE, {CR}},
3766 {"bnelr-", XLOCB(19,BOF,CBEQ,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2, {CR}},
3767 {"bner", XLOCB(19,BOF,CBEQ,16,0), XLBOCBBB_MASK, PWRCOM, PPCNONE, {CR}},
3768 {"bnelrl", XLOCB(19,BOF,CBEQ,16,1), XLBOCBBB_MASK, PPCCOM, PPCNONE, {CR}},
3769 {"bnelrl-", XLOCB(19,BOF,CBEQ,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2, {CR}},
3770 {"bnerl", XLOCB(19,BOF,CBEQ,16,1), XLBOCBBB_MASK, PWRCOM, PPCNONE, {CR}},
3771 {"bnslr", XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, PPCNONE, {CR}},
3772 {"bnslr-", XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2, {CR}},
3773 {"bnsr", XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, PWRCOM, PPCNONE, {CR}},
3774 {"bnulr", XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, PPCNONE, {CR}},
3775 {"bnulr-", XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2, {CR}},
3776 {"bnslrl", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, PPCNONE, {CR}},
3777 {"bnslrl-", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2, {CR}},
3778 {"bnsrl", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, PWRCOM, PPCNONE, {CR}},
3779 {"bnulrl", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, PPCNONE, {CR}},
3780 {"bnulrl-", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2, {CR}},
3781 {"bgelr+", XLOCB(19,BOFP,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2, {CR}},
3782 {"bnllr+", XLOCB(19,BOFP,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2, {CR}},
3783 {"bgelrl+", XLOCB(19,BOFP,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2, {CR}},
3784 {"bnllrl+", XLOCB(19,BOFP,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2, {CR}},
3785 {"blelr+", XLOCB(19,BOFP,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2, {CR}},
3786 {"bnglr+", XLOCB(19,BOFP,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2, {CR}},
3787 {"blelrl+", XLOCB(19,BOFP,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2, {CR}},
3788 {"bnglrl+", XLOCB(19,BOFP,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2, {CR}},
3789 {"bnelr+", XLOCB(19,BOFP,CBEQ,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2, {CR}},
3790 {"bnelrl+", XLOCB(19,BOFP,CBEQ,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2, {CR}},
3791 {"bnslr+", XLOCB(19,BOFP,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2, {CR}},
3792 {"bnulr+", XLOCB(19,BOFP,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2, {CR}},
3793 {"bnslrl+", XLOCB(19,BOFP,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2, {CR}},
3794 {"bnulrl+", XLOCB(19,BOFP,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2, {CR}},
3795 {"bgelr-", XLOCB(19,BOFM4,CBLT,16,0), XLBOCBBB_MASK, ISA_V2, PPCNONE, {CR}},
3796 {"bnllr-", XLOCB(19,BOFM4,CBLT,16,0), XLBOCBBB_MASK, ISA_V2, PPCNONE, {CR}},
3797 {"bgelrl-", XLOCB(19,BOFM4,CBLT,16,1), XLBOCBBB_MASK, ISA_V2, PPCNONE, {CR}},
3798 {"bnllrl-", XLOCB(19,BOFM4,CBLT,16,1), XLBOCBBB_MASK, ISA_V2, PPCNONE, {CR}},
3799 {"blelr-", XLOCB(19,BOFM4,CBGT,16,0), XLBOCBBB_MASK, ISA_V2, PPCNONE, {CR}},
3800 {"bnglr-", XLOCB(19,BOFM4,CBGT,16,0), XLBOCBBB_MASK, ISA_V2, PPCNONE, {CR}},
3801 {"blelrl-", XLOCB(19,BOFM4,CBGT,16,1), XLBOCBBB_MASK, ISA_V2, PPCNONE, {CR}},
3802 {"bnglrl-", XLOCB(19,BOFM4,CBGT,16,1), XLBOCBBB_MASK, ISA_V2, PPCNONE, {CR}},
3803 {"bnelr-", XLOCB(19,BOFM4,CBEQ,16,0), XLBOCBBB_MASK, ISA_V2, PPCNONE, {CR}},
3804 {"bnelrl-", XLOCB(19,BOFM4,CBEQ,16,1), XLBOCBBB_MASK, ISA_V2, PPCNONE, {CR}},
3805 {"bnslr-", XLOCB(19,BOFM4,CBSO,16,0), XLBOCBBB_MASK, ISA_V2, PPCNONE, {CR}},
3806 {"bnulr-", XLOCB(19,BOFM4,CBSO,16,0), XLBOCBBB_MASK, ISA_V2, PPCNONE, {CR}},
3807 {"bnslrl-", XLOCB(19,BOFM4,CBSO,16,1), XLBOCBBB_MASK, ISA_V2, PPCNONE, {CR}},
3808 {"bnulrl-", XLOCB(19,BOFM4,CBSO,16,1), XLBOCBBB_MASK, ISA_V2, PPCNONE, {CR}},
3809 {"bgelr+", XLOCB(19,BOFP4,CBLT,16,0), XLBOCBBB_MASK, ISA_V2, PPCNONE, {CR}},
3810 {"bnllr+", XLOCB(19,BOFP4,CBLT,16,0), XLBOCBBB_MASK, ISA_V2, PPCNONE, {CR}},
3811 {"bgelrl+", XLOCB(19,BOFP4,CBLT,16,1), XLBOCBBB_MASK, ISA_V2, PPCNONE, {CR}},
3812 {"bnllrl+", XLOCB(19,BOFP4,CBLT,16,1), XLBOCBBB_MASK, ISA_V2, PPCNONE, {CR}},
3813 {"blelr+", XLOCB(19,BOFP4,CBGT,16,0), XLBOCBBB_MASK, ISA_V2, PPCNONE, {CR}},
3814 {"bnglr+", XLOCB(19,BOFP4,CBGT,16,0), XLBOCBBB_MASK, ISA_V2, PPCNONE, {CR}},
3815 {"blelrl+", XLOCB(19,BOFP4,CBGT,16,1), XLBOCBBB_MASK, ISA_V2, PPCNONE, {CR}},
3816 {"bnglrl+", XLOCB(19,BOFP4,CBGT,16,1), XLBOCBBB_MASK, ISA_V2, PPCNONE, {CR}},
3817 {"bnelr+", XLOCB(19,BOFP4,CBEQ,16,0), XLBOCBBB_MASK, ISA_V2, PPCNONE, {CR}},
3818 {"bnelrl+", XLOCB(19,BOFP4,CBEQ,16,1), XLBOCBBB_MASK, ISA_V2, PPCNONE, {CR}},
3819 {"bnslr+", XLOCB(19,BOFP4,CBSO,16,0), XLBOCBBB_MASK, ISA_V2, PPCNONE, {CR}},
3820 {"bnulr+", XLOCB(19,BOFP4,CBSO,16,0), XLBOCBBB_MASK, ISA_V2, PPCNONE, {CR}},
3821 {"bnslrl+", XLOCB(19,BOFP4,CBSO,16,1), XLBOCBBB_MASK, ISA_V2, PPCNONE, {CR}},
3822 {"bnulrl+", XLOCB(19,BOFP4,CBSO,16,1), XLBOCBBB_MASK, ISA_V2, PPCNONE, {CR}},
3823 {"bltlr", XLOCB(19,BOT,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, PPCNONE, {CR}},
3824 {"bltlr-", XLOCB(19,BOT,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2, {CR}},
3825 {"bltr", XLOCB(19,BOT,CBLT,16,0), XLBOCBBB_MASK, PWRCOM, PPCNONE, {CR}},
3826 {"bltlrl", XLOCB(19,BOT,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, PPCNONE, {CR}},
3827 {"bltlrl-", XLOCB(19,BOT,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2, {CR}},
3828 {"bltrl", XLOCB(19,BOT,CBLT,16,1), XLBOCBBB_MASK, PWRCOM, PPCNONE, {CR}},
3829 {"bgtlr", XLOCB(19,BOT,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, PPCNONE, {CR}},
3830 {"bgtlr-", XLOCB(19,BOT,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2, {CR}},
3831 {"bgtr", XLOCB(19,BOT,CBGT,16,0), XLBOCBBB_MASK, PWRCOM, PPCNONE, {CR}},
3832 {"bgtlrl", XLOCB(19,BOT,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, PPCNONE, {CR}},
3833 {"bgtlrl-", XLOCB(19,BOT,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2, {CR}},
3834 {"bgtrl", XLOCB(19,BOT,CBGT,16,1), XLBOCBBB_MASK, PWRCOM, PPCNONE, {CR}},
3835 {"beqlr", XLOCB(19,BOT,CBEQ,16,0), XLBOCBBB_MASK, PPCCOM, PPCNONE, {CR}},
3836 {"beqlr-", XLOCB(19,BOT,CBEQ,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2, {CR}},
3837 {"beqr", XLOCB(19,BOT,CBEQ,16,0), XLBOCBBB_MASK, PWRCOM, PPCNONE, {CR}},
3838 {"beqlrl", XLOCB(19,BOT,CBEQ,16,1), XLBOCBBB_MASK, PPCCOM, PPCNONE, {CR}},
3839 {"beqlrl-", XLOCB(19,BOT,CBEQ,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2, {CR}},
3840 {"beqrl", XLOCB(19,BOT,CBEQ,16,1), XLBOCBBB_MASK, PWRCOM, PPCNONE, {CR}},
3841 {"bsolr", XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, PPCNONE, {CR}},
3842 {"bsolr-", XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2, {CR}},
3843 {"bsor", XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, PWRCOM, PPCNONE, {CR}},
3844 {"bunlr", XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, PPCNONE, {CR}},
3845 {"bunlr-", XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2, {CR}},
3846 {"bsolrl", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, PPCNONE, {CR}},
3847 {"bsolrl-", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2, {CR}},
3848 {"bsorl", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, PWRCOM, PPCNONE, {CR}},
3849 {"bunlrl", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, PPCNONE, {CR}},
3850 {"bunlrl-", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2, {CR}},
3851 {"bltlr+", XLOCB(19,BOTP,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2, {CR}},
3852 {"bltlrl+", XLOCB(19,BOTP,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2, {CR}},
3853 {"bgtlr+", XLOCB(19,BOTP,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2, {CR}},
3854 {"bgtlrl+", XLOCB(19,BOTP,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2, {CR}},
3855 {"beqlr+", XLOCB(19,BOTP,CBEQ,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2, {CR}},
3856 {"beqlrl+", XLOCB(19,BOTP,CBEQ,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2, {CR}},
3857 {"bsolr+", XLOCB(19,BOTP,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2, {CR}},
3858 {"bunlr+", XLOCB(19,BOTP,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2, {CR}},
3859 {"bsolrl+", XLOCB(19,BOTP,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2, {CR}},
3860 {"bunlrl+", XLOCB(19,BOTP,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2, {CR}},
3861 {"bltlr-", XLOCB(19,BOTM4,CBLT,16,0), XLBOCBBB_MASK, ISA_V2, PPCNONE, {CR}},
3862 {"bltlrl-", XLOCB(19,BOTM4,CBLT,16,1), XLBOCBBB_MASK, ISA_V2, PPCNONE, {CR}},
3863 {"bgtlr-", XLOCB(19,BOTM4,CBGT,16,0), XLBOCBBB_MASK, ISA_V2, PPCNONE, {CR}},
3864 {"bgtlrl-", XLOCB(19,BOTM4,CBGT,16,1), XLBOCBBB_MASK, ISA_V2, PPCNONE, {CR}},
3865 {"beqlr-", XLOCB(19,BOTM4,CBEQ,16,0), XLBOCBBB_MASK, ISA_V2, PPCNONE, {CR}},
3866 {"beqlrl-", XLOCB(19,BOTM4,CBEQ,16,1), XLBOCBBB_MASK, ISA_V2, PPCNONE, {CR}},
3867 {"bsolr-", XLOCB(19,BOTM4,CBSO,16,0), XLBOCBBB_MASK, ISA_V2, PPCNONE, {CR}},
3868 {"bunlr-", XLOCB(19,BOTM4,CBSO,16,0), XLBOCBBB_MASK, ISA_V2, PPCNONE, {CR}},
3869 {"bsolrl-", XLOCB(19,BOTM4,CBSO,16,1), XLBOCBBB_MASK, ISA_V2, PPCNONE, {CR}},
3870 {"bunlrl-", XLOCB(19,BOTM4,CBSO,16,1), XLBOCBBB_MASK, ISA_V2, PPCNONE, {CR}},
3871 {"bltlr+", XLOCB(19,BOTP4,CBLT,16,0), XLBOCBBB_MASK, ISA_V2, PPCNONE, {CR}},
3872 {"bltlrl+", XLOCB(19,BOTP4,CBLT,16,1), XLBOCBBB_MASK, ISA_V2, PPCNONE, {CR}},
3873 {"bgtlr+", XLOCB(19,BOTP4,CBGT,16,0), XLBOCBBB_MASK, ISA_V2, PPCNONE, {CR}},
3874 {"bgtlrl+", XLOCB(19,BOTP4,CBGT,16,1), XLBOCBBB_MASK, ISA_V2, PPCNONE, {CR}},
3875 {"beqlr+", XLOCB(19,BOTP4,CBEQ,16,0), XLBOCBBB_MASK, ISA_V2, PPCNONE, {CR}},
3876 {"beqlrl+", XLOCB(19,BOTP4,CBEQ,16,1), XLBOCBBB_MASK, ISA_V2, PPCNONE, {CR}},
3877 {"bsolr+", XLOCB(19,BOTP4,CBSO,16,0), XLBOCBBB_MASK, ISA_V2, PPCNONE, {CR}},
3878 {"bunlr+", XLOCB(19,BOTP4,CBSO,16,0), XLBOCBBB_MASK, ISA_V2, PPCNONE, {CR}},
3879 {"bsolrl+", XLOCB(19,BOTP4,CBSO,16,1), XLBOCBBB_MASK, ISA_V2, PPCNONE, {CR}},
3880 {"bunlrl+", XLOCB(19,BOTP4,CBSO,16,1), XLBOCBBB_MASK, ISA_V2, PPCNONE, {CR}},
3881
3882 {"bdnzflr", XLO(19,BODNZF,16,0), XLBOBB_MASK, PPCCOM, PPCNONE, {BI}},
3883 {"bdnzflr-", XLO(19,BODNZF,16,0), XLBOBB_MASK, PPCCOM, ISA_V2, {BI}},
3884 {"bdnzflrl", XLO(19,BODNZF,16,1), XLBOBB_MASK, PPCCOM, PPCNONE, {BI}},
3885 {"bdnzflrl-",XLO(19,BODNZF,16,1), XLBOBB_MASK, PPCCOM, ISA_V2, {BI}},
3886 {"bdnzflr+", XLO(19,BODNZFP,16,0), XLBOBB_MASK, PPCCOM, ISA_V2, {BI}},
3887 {"bdnzflrl+",XLO(19,BODNZFP,16,1), XLBOBB_MASK, PPCCOM, ISA_V2, {BI}},
3888 {"bdzflr", XLO(19,BODZF,16,0), XLBOBB_MASK, PPCCOM, PPCNONE, {BI}},
3889 {"bdzflr-", XLO(19,BODZF,16,0), XLBOBB_MASK, PPCCOM, ISA_V2, {BI}},
3890 {"bdzflrl", XLO(19,BODZF,16,1), XLBOBB_MASK, PPCCOM, PPCNONE, {BI}},
3891 {"bdzflrl-", XLO(19,BODZF,16,1), XLBOBB_MASK, PPCCOM, ISA_V2, {BI}},
3892 {"bdzflr+", XLO(19,BODZFP,16,0), XLBOBB_MASK, PPCCOM, ISA_V2, {BI}},
3893 {"bdzflrl+", XLO(19,BODZFP,16,1), XLBOBB_MASK, PPCCOM, ISA_V2, {BI}},
3894 {"bflr", XLO(19,BOF,16,0), XLBOBB_MASK, PPCCOM, PPCNONE, {BI}},
3895 {"bflr-", XLO(19,BOF,16,0), XLBOBB_MASK, PPCCOM, ISA_V2, {BI}},
3896 {"bbfr", XLO(19,BOF,16,0), XLBOBB_MASK, PWRCOM, PPCNONE, {BI}},
3897 {"bflrl", XLO(19,BOF,16,1), XLBOBB_MASK, PPCCOM, PPCNONE, {BI}},
3898 {"bflrl-", XLO(19,BOF,16,1), XLBOBB_MASK, PPCCOM, ISA_V2, {BI}},
3899 {"bbfrl", XLO(19,BOF,16,1), XLBOBB_MASK, PWRCOM, PPCNONE, {BI}},
3900 {"bflr+", XLO(19,BOFP,16,0), XLBOBB_MASK, PPCCOM, ISA_V2, {BI}},
3901 {"bflrl+", XLO(19,BOFP,16,1), XLBOBB_MASK, PPCCOM, ISA_V2, {BI}},
3902 {"bflr-", XLO(19,BOFM4,16,0), XLBOBB_MASK, ISA_V2, PPCNONE, {BI}},
3903 {"bflrl-", XLO(19,BOFM4,16,1), XLBOBB_MASK, ISA_V2, PPCNONE, {BI}},
3904 {"bflr+", XLO(19,BOFP4,16,0), XLBOBB_MASK, ISA_V2, PPCNONE, {BI}},
3905 {"bflrl+", XLO(19,BOFP4,16,1), XLBOBB_MASK, ISA_V2, PPCNONE, {BI}},
3906 {"bdnztlr", XLO(19,BODNZT,16,0), XLBOBB_MASK, PPCCOM, PPCNONE, {BI}},
3907 {"bdnztlr-", XLO(19,BODNZT,16,0), XLBOBB_MASK, PPCCOM, ISA_V2, {BI}},
3908 {"bdnztlrl", XLO(19,BODNZT,16,1), XLBOBB_MASK, PPCCOM, PPCNONE, {BI}},
3909 {"bdnztlrl-",XLO(19,BODNZT,16,1), XLBOBB_MASK, PPCCOM, ISA_V2, {BI}},
3910 {"bdnztlr+", XLO(19,BODNZTP,16,0), XLBOBB_MASK, PPCCOM, ISA_V2, {BI}},
3911 {"bdnztlrl+",XLO(19,BODNZTP,16,1), XLBOBB_MASK, PPCCOM, ISA_V2, {BI}},
3912 {"bdztlr", XLO(19,BODZT,16,0), XLBOBB_MASK, PPCCOM, PPCNONE, {BI}},
3913 {"bdztlr-", XLO(19,BODZT,16,0), XLBOBB_MASK, PPCCOM, ISA_V2, {BI}},
3914 {"bdztlrl", XLO(19,BODZT,16,1), XLBOBB_MASK, PPCCOM, PPCNONE, {BI}},
3915 {"bdztlrl-", XLO(19,BODZT,16,1), XLBOBB_MASK, PPCCOM, ISA_V2, {BI}},
3916 {"bdztlr+", XLO(19,BODZTP,16,0), XLBOBB_MASK, PPCCOM, ISA_V2, {BI}},
3917 {"bdztlrl+", XLO(19,BODZTP,16,1), XLBOBB_MASK, PPCCOM, ISA_V2, {BI}},
3918 {"btlr", XLO(19,BOT,16,0), XLBOBB_MASK, PPCCOM, PPCNONE, {BI}},
3919 {"btlr-", XLO(19,BOT,16,0), XLBOBB_MASK, PPCCOM, ISA_V2, {BI}},
3920 {"bbtr", XLO(19,BOT,16,0), XLBOBB_MASK, PWRCOM, PPCNONE, {BI}},
3921 {"btlrl", XLO(19,BOT,16,1), XLBOBB_MASK, PPCCOM, PPCNONE, {BI}},
3922 {"btlrl-", XLO(19,BOT,16,1), XLBOBB_MASK, PPCCOM, ISA_V2, {BI}},
3923 {"bbtrl", XLO(19,BOT,16,1), XLBOBB_MASK, PWRCOM, PPCNONE, {BI}},
3924 {"btlr+", XLO(19,BOTP,16,0), XLBOBB_MASK, PPCCOM, ISA_V2, {BI}},
3925 {"btlrl+", XLO(19,BOTP,16,1), XLBOBB_MASK, PPCCOM, ISA_V2, {BI}},
3926 {"btlr-", XLO(19,BOTM4,16,0), XLBOBB_MASK, ISA_V2, PPCNONE, {BI}},
3927 {"btlrl-", XLO(19,BOTM4,16,1), XLBOBB_MASK, ISA_V2, PPCNONE, {BI}},
3928 {"btlr+", XLO(19,BOTP4,16,0), XLBOBB_MASK, ISA_V2, PPCNONE, {BI}},
3929 {"btlrl+", XLO(19,BOTP4,16,1), XLBOBB_MASK, ISA_V2, PPCNONE, {BI}},
3930
3931 {"bclr-", XLYLK(19,16,0,0), XLYBB_MASK, PPCCOM, PPCNONE, {BOE, BI}},
3932 {"bclrl-", XLYLK(19,16,0,1), XLYBB_MASK, PPCCOM, PPCNONE, {BOE, BI}},
3933 {"bclr+", XLYLK(19,16,1,0), XLYBB_MASK, PPCCOM, PPCNONE, {BOE, BI}},
3934 {"bclrl+", XLYLK(19,16,1,1), XLYBB_MASK, PPCCOM, PPCNONE, {BOE, BI}},
3935 {"bclr", XLLK(19,16,0), XLBH_MASK, PPCCOM, PPCNONE, {BO, BI, BH}},
3936 {"bcr", XLLK(19,16,0), XLBB_MASK, PWRCOM, PPCNONE, {BO, BI}},
3937 {"bclrl", XLLK(19,16,1), XLBH_MASK, PPCCOM, PPCNONE, {BO, BI, BH}},
3938 {"bcrl", XLLK(19,16,1), XLBB_MASK, PWRCOM, PPCNONE, {BO, BI}},
3939
3940 {"rfid", XL(19,18), 0xffffffff, PPC64, PPCNONE, {0}},
3941
3942 {"crnot", XL(19,33), XL_MASK, PPCCOM, PPCNONE, {BT, BA, BBA}},
3943 {"crnor", XL(19,33), XL_MASK, COM, PPCNONE, {BT, BA, BB}},
3944 {"rfmci", X(19,38), 0xffffffff, PPCRFMCI|PPCA2|PPC476, PPCNONE, {0}},
3945
3946 {"rfdi", XL(19,39), 0xffffffff, E500MC, PPCNONE, {0}},
3947 {"rfi", XL(19,50), 0xffffffff, COM, PPCNONE, {0}},
3948 {"rfci", XL(19,51), 0xffffffff, PPC403|BOOKE|PPCE300|PPCA2|PPC476, PPCNONE, {0}},
3949
3950 {"rfsvc", XL(19,82), 0xffffffff, POWER, PPCNONE, {0}},
3951
3952 {"rfgi", XL(19,102), 0xffffffff, E500MC|PPCA2, PPCNONE, {0}},
3953
3954 {"crandc", XL(19,129), XL_MASK, COM, PPCNONE, {BT, BA, BB}},
3955
3956 {"isync", XL(19,150), 0xffffffff, PPCCOM, PPCNONE, {0}},
3957 {"ics", XL(19,150), 0xffffffff, PWRCOM, PPCNONE, {0}},
3958
3959 {"crclr", XL(19,193), XL_MASK, PPCCOM, PPCNONE, {BT, BAT, BBA}},
3960 {"crxor", XL(19,193), XL_MASK, COM, PPCNONE, {BT, BA, BB}},
3961
3962 {"dnh", X(19,198), X_MASK, E500MC, PPCNONE, {DUI, DUIS}},
3963
3964 {"crnand", XL(19,225), XL_MASK, COM, PPCNONE, {BT, BA, BB}},
3965
3966 {"crand", XL(19,257), XL_MASK, COM, PPCNONE, {BT, BA, BB}},
3967
3968 {"hrfid", XL(19,274), 0xffffffff, POWER5|CELL, PPC476, {0}},
3969
3970 {"crset", XL(19,289), XL_MASK, PPCCOM, PPCNONE, {BT, BAT, BBA}},
3971 {"creqv", XL(19,289), XL_MASK, COM, PPCNONE, {BT, BA, BB}},
3972
3973 {"doze", XL(19,402), 0xffffffff, POWER6, PPCNONE, {0}},
3974
3975 {"crorc", XL(19,417), XL_MASK, COM, PPCNONE, {BT, BA, BB}},
3976
3977 {"nap", XL(19,434), 0xffffffff, POWER6, PPCNONE, {0}},
3978
3979 {"crmove", XL(19,449), XL_MASK, PPCCOM, PPCNONE, {BT, BA, BBA}},
3980 {"cror", XL(19,449), XL_MASK, COM, PPCNONE, {BT, BA, BB}},
3981
3982 {"sleep", XL(19,466), 0xffffffff, POWER6, PPCNONE, {0}},
3983 {"rvwinkle", XL(19,498), 0xffffffff, POWER6, PPCNONE, {0}},
3984
3985 {"bctr", XLO(19,BOU,528,0), XLBOBIBB_MASK, COM, PPCNONE, {0}},
3986 {"bctrl", XLO(19,BOU,528,1), XLBOBIBB_MASK, COM, PPCNONE, {0}},
3987
3988 {"bgectr", XLOCB(19,BOF,CBLT,528,0), XLBOCBBB_MASK, PPCCOM, PPCNONE, {CR}},
3989 {"bgectr-", XLOCB(19,BOF,CBLT,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2, {CR}},
3990 {"bnlctr", XLOCB(19,BOF,CBLT,528,0), XLBOCBBB_MASK, PPCCOM, PPCNONE, {CR}},
3991 {"bnlctr-", XLOCB(19,BOF,CBLT,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2, {CR}},
3992 {"bgectrl", XLOCB(19,BOF,CBLT,528,1), XLBOCBBB_MASK, PPCCOM, PPCNONE, {CR}},
3993 {"bgectrl-",XLOCB(19,BOF,CBLT,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2, {CR}},
3994 {"bnlctrl", XLOCB(19,BOF,CBLT,528,1), XLBOCBBB_MASK, PPCCOM, PPCNONE, {CR}},
3995 {"bnlctrl-",XLOCB(19,BOF,CBLT,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2, {CR}},
3996 {"blectr", XLOCB(19,BOF,CBGT,528,0), XLBOCBBB_MASK, PPCCOM, PPCNONE, {CR}},
3997 {"blectr-", XLOCB(19,BOF,CBGT,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2, {CR}},
3998 {"bngctr", XLOCB(19,BOF,CBGT,528,0), XLBOCBBB_MASK, PPCCOM, PPCNONE, {CR}},
3999 {"bngctr-", XLOCB(19,BOF,CBGT,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2, {CR}},
4000 {"blectrl", XLOCB(19,BOF,CBGT,528,1), XLBOCBBB_MASK, PPCCOM, PPCNONE, {CR}},
4001 {"blectrl-",XLOCB(19,BOF,CBGT,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2, {CR}},
4002 {"bngctrl", XLOCB(19,BOF,CBGT,528,1), XLBOCBBB_MASK, PPCCOM, PPCNONE, {CR}},
4003 {"bngctrl-",XLOCB(19,BOF,CBGT,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2, {CR}},
4004 {"bnectr", XLOCB(19,BOF,CBEQ,528,0), XLBOCBBB_MASK, PPCCOM, PPCNONE, {CR}},
4005 {"bnectr-", XLOCB(19,BOF,CBEQ,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2, {CR}},
4006 {"bnectrl", XLOCB(19,BOF,CBEQ,528,1), XLBOCBBB_MASK, PPCCOM, PPCNONE, {CR}},
4007 {"bnectrl-",XLOCB(19,BOF,CBEQ,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2, {CR}},
4008 {"bnsctr", XLOCB(19,BOF,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, PPCNONE, {CR}},
4009 {"bnsctr-", XLOCB(19,BOF,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2, {CR}},
4010 {"bnuctr", XLOCB(19,BOF,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, PPCNONE, {CR}},
4011 {"bnuctr-", XLOCB(19,BOF,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2, {CR}},
4012 {"bnsctrl", XLOCB(19,BOF,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, PPCNONE, {CR}},
4013 {"bnsctrl-",XLOCB(19,BOF,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2, {CR}},
4014 {"bnuctrl", XLOCB(19,BOF,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, PPCNONE, {CR}},
4015 {"bnuctrl-",XLOCB(19,BOF,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2, {CR}},
4016 {"bgectr+", XLOCB(19,BOFP,CBLT,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2, {CR}},
4017 {"bnlctr+", XLOCB(19,BOFP,CBLT,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2, {CR}},
4018 {"bgectrl+",XLOCB(19,BOFP,CBLT,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2, {CR}},
4019 {"bnlctrl+",XLOCB(19,BOFP,CBLT,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2, {CR}},
4020 {"blectr+", XLOCB(19,BOFP,CBGT,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2, {CR}},
4021 {"bngctr+", XLOCB(19,BOFP,CBGT,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2, {CR}},
4022 {"blectrl+",XLOCB(19,BOFP,CBGT,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2, {CR}},
4023 {"bngctrl+",XLOCB(19,BOFP,CBGT,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2, {CR}},
4024 {"bnectr+", XLOCB(19,BOFP,CBEQ,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2, {CR}},
4025 {"bnectrl+",XLOCB(19,BOFP,CBEQ,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2, {CR}},
4026 {"bnsctr+", XLOCB(19,BOFP,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2, {CR}},
4027 {"bnuctr+", XLOCB(19,BOFP,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2, {CR}},
4028 {"bnsctrl+",XLOCB(19,BOFP,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2, {CR}},
4029 {"bnuctrl+",XLOCB(19,BOFP,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2, {CR}},
4030 {"bgectr-", XLOCB(19,BOFM4,CBLT,528,0), XLBOCBBB_MASK, ISA_V2, PPCNONE, {CR}},
4031 {"bnlctr-", XLOCB(19,BOFM4,CBLT,528,0), XLBOCBBB_MASK, ISA_V2, PPCNONE, {CR}},
4032 {"bgectrl-",XLOCB(19,BOFM4,CBLT,528,1), XLBOCBBB_MASK, ISA_V2, PPCNONE, {CR}},
4033 {"bnlctrl-",XLOCB(19,BOFM4,CBLT,528,1), XLBOCBBB_MASK, ISA_V2, PPCNONE, {CR}},
4034 {"blectr-", XLOCB(19,BOFM4,CBGT,528,0), XLBOCBBB_MASK, ISA_V2, PPCNONE, {CR}},
4035 {"bngctr-", XLOCB(19,BOFM4,CBGT,528,0), XLBOCBBB_MASK, ISA_V2, PPCNONE, {CR}},
4036 {"blectrl-",XLOCB(19,BOFM4,CBGT,528,1), XLBOCBBB_MASK, ISA_V2, PPCNONE, {CR}},
4037 {"bngctrl-",XLOCB(19,BOFM4,CBGT,528,1), XLBOCBBB_MASK, ISA_V2, PPCNONE, {CR}},
4038 {"bnectr-", XLOCB(19,BOFM4,CBEQ,528,0), XLBOCBBB_MASK, ISA_V2, PPCNONE, {CR}},
4039 {"bnectrl-",XLOCB(19,BOFM4,CBEQ,528,1), XLBOCBBB_MASK, ISA_V2, PPCNONE, {CR}},
4040 {"bnsctr-", XLOCB(19,BOFM4,CBSO,528,0), XLBOCBBB_MASK, ISA_V2, PPCNONE, {CR}},
4041 {"bnuctr-", XLOCB(19,BOFM4,CBSO,528,0), XLBOCBBB_MASK, ISA_V2, PPCNONE, {CR}},
4042 {"bnsctrl-",XLOCB(19,BOFM4,CBSO,528,1), XLBOCBBB_MASK, ISA_V2, PPCNONE, {CR}},
4043 {"bnuctrl-",XLOCB(19,BOFM4,CBSO,528,1), XLBOCBBB_MASK, ISA_V2, PPCNONE, {CR}},
4044 {"bgectr+", XLOCB(19,BOFP4,CBLT,528,0), XLBOCBBB_MASK, ISA_V2, PPCNONE, {CR}},
4045 {"bnlctr+", XLOCB(19,BOFP4,CBLT,528,0), XLBOCBBB_MASK, ISA_V2, PPCNONE, {CR}},
4046 {"bgectrl+",XLOCB(19,BOFP4,CBLT,528,1), XLBOCBBB_MASK, ISA_V2, PPCNONE, {CR}},
4047 {"bnlctrl+",XLOCB(19,BOFP4,CBLT,528,1), XLBOCBBB_MASK, ISA_V2, PPCNONE, {CR}},
4048 {"blectr+", XLOCB(19,BOFP4,CBGT,528,0), XLBOCBBB_MASK, ISA_V2, PPCNONE, {CR}},
4049 {"bngctr+", XLOCB(19,BOFP4,CBGT,528,0), XLBOCBBB_MASK, ISA_V2, PPCNONE, {CR}},
4050 {"blectrl+",XLOCB(19,BOFP4,CBGT,528,1), XLBOCBBB_MASK, ISA_V2, PPCNONE, {CR}},
4051 {"bngctrl+",XLOCB(19,BOFP4,CBGT,528,1), XLBOCBBB_MASK, ISA_V2, PPCNONE, {CR}},
4052 {"bnectr+", XLOCB(19,BOFP4,CBEQ,528,0), XLBOCBBB_MASK, ISA_V2, PPCNONE, {CR}},
4053 {"bnectrl+",XLOCB(19,BOFP4,CBEQ,528,1), XLBOCBBB_MASK, ISA_V2, PPCNONE, {CR}},
4054 {"bnsctr+", XLOCB(19,BOFP4,CBSO,528,0), XLBOCBBB_MASK, ISA_V2, PPCNONE, {CR}},
4055 {"bnuctr+", XLOCB(19,BOFP4,CBSO,528,0), XLBOCBBB_MASK, ISA_V2, PPCNONE, {CR}},
4056 {"bnsctrl+",XLOCB(19,BOFP4,CBSO,528,1), XLBOCBBB_MASK, ISA_V2, PPCNONE, {CR}},
4057 {"bnuctrl+",XLOCB(19,BOFP4,CBSO,528,1), XLBOCBBB_MASK, ISA_V2, PPCNONE, {CR}},
4058 {"bltctr", XLOCB(19,BOT,CBLT,528,0), XLBOCBBB_MASK, PPCCOM, PPCNONE, {CR}},
4059 {"bltctr-", XLOCB(19,BOT,CBLT,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2, {CR}},
4060 {"bltctrl", XLOCB(19,BOT,CBLT,528,1), XLBOCBBB_MASK, PPCCOM, PPCNONE, {CR}},
4061 {"bltctrl-",XLOCB(19,BOT,CBLT,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2, {CR}},
4062 {"bgtctr", XLOCB(19,BOT,CBGT,528,0), XLBOCBBB_MASK, PPCCOM, PPCNONE, {CR}},
4063 {"bgtctr-", XLOCB(19,BOT,CBGT,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2, {CR}},
4064 {"bgtctrl", XLOCB(19,BOT,CBGT,528,1), XLBOCBBB_MASK, PPCCOM, PPCNONE, {CR}},
4065 {"bgtctrl-",XLOCB(19,BOT,CBGT,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2, {CR}},
4066 {"beqctr", XLOCB(19,BOT,CBEQ,528,0), XLBOCBBB_MASK, PPCCOM, PPCNONE, {CR}},
4067 {"beqctr-", XLOCB(19,BOT,CBEQ,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2, {CR}},
4068 {"beqctrl", XLOCB(19,BOT,CBEQ,528,1), XLBOCBBB_MASK, PPCCOM, PPCNONE, {CR}},
4069 {"beqctrl-",XLOCB(19,BOT,CBEQ,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2, {CR}},
4070 {"bsoctr", XLOCB(19,BOT,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, PPCNONE, {CR}},
4071 {"bsoctr-", XLOCB(19,BOT,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2, {CR}},
4072 {"bunctr", XLOCB(19,BOT,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, PPCNONE, {CR}},
4073 {"bunctr-", XLOCB(19,BOT,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2, {CR}},
4074 {"bsoctrl", XLOCB(19,BOT,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, PPCNONE, {CR}},
4075 {"bsoctrl-",XLOCB(19,BOT,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2, {CR}},
4076 {"bunctrl", XLOCB(19,BOT,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, PPCNONE, {CR}},
4077 {"bunctrl-",XLOCB(19,BOT,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2, {CR}},
4078 {"bltctr+", XLOCB(19,BOTP,CBLT,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2, {CR}},
4079 {"bltctrl+",XLOCB(19,BOTP,CBLT,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2, {CR}},
4080 {"bgtctr+", XLOCB(19,BOTP,CBGT,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2, {CR}},
4081 {"bgtctrl+",XLOCB(19,BOTP,CBGT,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2, {CR}},
4082 {"beqctr+", XLOCB(19,BOTP,CBEQ,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2, {CR}},
4083 {"beqctrl+",XLOCB(19,BOTP,CBEQ,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2, {CR}},
4084 {"bsoctr+", XLOCB(19,BOTP,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2, {CR}},
4085 {"bunctr+", XLOCB(19,BOTP,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2, {CR}},
4086 {"bsoctrl+",XLOCB(19,BOTP,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2, {CR}},
4087 {"bunctrl+",XLOCB(19,BOTP,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2, {CR}},
4088 {"bltctr-", XLOCB(19,BOTM4,CBLT,528,0), XLBOCBBB_MASK, ISA_V2, PPCNONE, {CR}},
4089 {"bltctrl-",XLOCB(19,BOTM4,CBLT,528,1), XLBOCBBB_MASK, ISA_V2, PPCNONE, {CR}},
4090 {"bgtctr-", XLOCB(19,BOTM4,CBGT,528,0), XLBOCBBB_MASK, ISA_V2, PPCNONE, {CR}},
4091 {"bgtctrl-",XLOCB(19,BOTM4,CBGT,528,1), XLBOCBBB_MASK, ISA_V2, PPCNONE, {CR}},
4092 {"beqctr-", XLOCB(19,BOTM4,CBEQ,528,0), XLBOCBBB_MASK, ISA_V2, PPCNONE, {CR}},
4093 {"beqctrl-",XLOCB(19,BOTM4,CBEQ,528,1), XLBOCBBB_MASK, ISA_V2, PPCNONE, {CR}},
4094 {"bsoctr-", XLOCB(19,BOTM4,CBSO,528,0), XLBOCBBB_MASK, ISA_V2, PPCNONE, {CR}},
4095 {"bunctr-", XLOCB(19,BOTM4,CBSO,528,0), XLBOCBBB_MASK, ISA_V2, PPCNONE, {CR}},
4096 {"bsoctrl-",XLOCB(19,BOTM4,CBSO,528,1), XLBOCBBB_MASK, ISA_V2, PPCNONE, {CR}},
4097 {"bunctrl-",XLOCB(19,BOTM4,CBSO,528,1), XLBOCBBB_MASK, ISA_V2, PPCNONE, {CR}},
4098 {"bltctr+", XLOCB(19,BOTP4,CBLT,528,0), XLBOCBBB_MASK, ISA_V2, PPCNONE, {CR}},
4099 {"bltctrl+",XLOCB(19,BOTP4,CBLT,528,1), XLBOCBBB_MASK, ISA_V2, PPCNONE, {CR}},
4100 {"bgtctr+", XLOCB(19,BOTP4,CBGT,528,0), XLBOCBBB_MASK, ISA_V2, PPCNONE, {CR}},
4101 {"bgtctrl+",XLOCB(19,BOTP4,CBGT,528,1), XLBOCBBB_MASK, ISA_V2, PPCNONE, {CR}},
4102 {"beqctr+", XLOCB(19,BOTP4,CBEQ,528,0), XLBOCBBB_MASK, ISA_V2, PPCNONE, {CR}},
4103 {"beqctrl+",XLOCB(19,BOTP4,CBEQ,528,1), XLBOCBBB_MASK, ISA_V2, PPCNONE, {CR}},
4104 {"bsoctr+", XLOCB(19,BOTP4,CBSO,528,0), XLBOCBBB_MASK, ISA_V2, PPCNONE, {CR}},
4105 {"bunctr+", XLOCB(19,BOTP4,CBSO,528,0), XLBOCBBB_MASK, ISA_V2, PPCNONE, {CR}},
4106 {"bsoctrl+",XLOCB(19,BOTP4,CBSO,528,1), XLBOCBBB_MASK, ISA_V2, PPCNONE, {CR}},
4107 {"bunctrl+",XLOCB(19,BOTP4,CBSO,528,1), XLBOCBBB_MASK, ISA_V2, PPCNONE, {CR}},
4108
4109 {"bfctr", XLO(19,BOF,528,0), XLBOBB_MASK, PPCCOM, PPCNONE, {BI}},
4110 {"bfctr-", XLO(19,BOF,528,0), XLBOBB_MASK, PPCCOM, ISA_V2, {BI}},
4111 {"bfctrl", XLO(19,BOF,528,1), XLBOBB_MASK, PPCCOM, PPCNONE, {BI}},
4112 {"bfctrl-", XLO(19,BOF,528,1), XLBOBB_MASK, PPCCOM, ISA_V2, {BI}},
4113 {"bfctr+", XLO(19,BOFP,528,0), XLBOBB_MASK, PPCCOM, ISA_V2, {BI}},
4114 {"bfctrl+", XLO(19,BOFP,528,1), XLBOBB_MASK, PPCCOM, ISA_V2, {BI}},
4115 {"bfctr-", XLO(19,BOFM4,528,0), XLBOBB_MASK, ISA_V2, PPCNONE, {BI}},
4116 {"bfctrl-", XLO(19,BOFM4,528,1), XLBOBB_MASK, ISA_V2, PPCNONE, {BI}},
4117 {"bfctr+", XLO(19,BOFP4,528,0), XLBOBB_MASK, ISA_V2, PPCNONE, {BI}},
4118 {"bfctrl+", XLO(19,BOFP4,528,1), XLBOBB_MASK, ISA_V2, PPCNONE, {BI}},
4119 {"btctr", XLO(19,BOT,528,0), XLBOBB_MASK, PPCCOM, PPCNONE, {BI}},
4120 {"btctr-", XLO(19,BOT,528,0), XLBOBB_MASK, PPCCOM, ISA_V2, {BI}},
4121 {"btctrl", XLO(19,BOT,528,1), XLBOBB_MASK, PPCCOM, PPCNONE, {BI}},
4122 {"btctrl-", XLO(19,BOT,528,1), XLBOBB_MASK, PPCCOM, ISA_V2, {BI}},
4123 {"btctr+", XLO(19,BOTP,528,0), XLBOBB_MASK, PPCCOM, ISA_V2, {BI}},
4124 {"btctrl+", XLO(19,BOTP,528,1), XLBOBB_MASK, PPCCOM, ISA_V2, {BI}},
4125 {"btctr-", XLO(19,BOTM4,528,0), XLBOBB_MASK, ISA_V2, PPCNONE, {BI}},
4126 {"btctrl-", XLO(19,BOTM4,528,1), XLBOBB_MASK, ISA_V2, PPCNONE, {BI}},
4127 {"btctr+", XLO(19,BOTP4,528,0), XLBOBB_MASK, ISA_V2, PPCNONE, {BI}},
4128 {"btctrl+", XLO(19,BOTP4,528,1), XLBOBB_MASK, ISA_V2, PPCNONE, {BI}},
4129
4130 {"bcctr-", XLYLK(19,528,0,0), XLYBB_MASK, PPCCOM, PPCNONE, {BOE, BI}},
4131 {"bcctrl-", XLYLK(19,528,0,1), XLYBB_MASK, PPCCOM, PPCNONE, {BOE, BI}},
4132 {"bcctr+", XLYLK(19,528,1,0), XLYBB_MASK, PPCCOM, PPCNONE, {BOE, BI}},
4133 {"bcctrl+", XLYLK(19,528,1,1), XLYBB_MASK, PPCCOM, PPCNONE, {BOE, BI}},
4134 {"bcctr", XLLK(19,528,0), XLBH_MASK, PPCCOM, PPCNONE, {BO, BI, BH}},
4135 {"bcc", XLLK(19,528,0), XLBB_MASK, PWRCOM, PPCNONE, {BO, BI}},
4136 {"bcctrl", XLLK(19,528,1), XLBH_MASK, PPCCOM, PPCNONE, {BO, BI, BH}},
4137 {"bccl", XLLK(19,528,1), XLBB_MASK, PWRCOM, PPCNONE, {BO, BI}},
4138
4139 {"rlwimi", M(20,0), M_MASK, PPCCOM, PPCNONE, {RA, RS, SH, MBE, ME}},
4140 {"rlimi", M(20,0), M_MASK, PWRCOM, PPCNONE, {RA, RS, SH, MBE, ME}},
4141
4142 {"rlwimi.", M(20,1), M_MASK, PPCCOM, PPCNONE, {RA, RS, SH, MBE, ME}},
4143 {"rlimi.", M(20,1), M_MASK, PWRCOM, PPCNONE, {RA, RS, SH, MBE, ME}},
4144
4145 {"rotlwi", MME(21,31,0), MMBME_MASK, PPCCOM, PPCNONE, {RA, RS, SH}},
4146 {"clrlwi", MME(21,31,0), MSHME_MASK, PPCCOM, PPCNONE, {RA, RS, MB}},
4147 {"rlwinm", M(21,0), M_MASK, PPCCOM, PPCNONE, {RA, RS, SH, MBE, ME}},
4148 {"rlinm", M(21,0), M_MASK, PWRCOM, PPCNONE, {RA, RS, SH, MBE, ME}},
4149 {"rotlwi.", MME(21,31,1), MMBME_MASK, PPCCOM, PPCNONE, {RA, RS, SH}},
4150 {"clrlwi.", MME(21,31,1), MSHME_MASK, PPCCOM, PPCNONE, {RA, RS, MB}},
4151 {"rlwinm.", M(21,1), M_MASK, PPCCOM, PPCNONE, {RA, RS, SH, MBE, ME}},
4152 {"rlinm.", M(21,1), M_MASK, PWRCOM, PPCNONE, {RA, RS, SH, MBE, ME}},
4153
4154 {"rlmi", M(22,0), M_MASK, M601, PPCNONE, {RA, RS, RB, MBE, ME}},
4155 {"rlmi.", M(22,1), M_MASK, M601, PPCNONE, {RA, RS, RB, MBE, ME}},
4156
4157 {"rotlw", MME(23,31,0), MMBME_MASK, PPCCOM, PPCNONE, {RA, RS, RB}},
4158 {"rlwnm", M(23,0), M_MASK, PPCCOM, PPCNONE, {RA, RS, RB, MBE, ME}},
4159 {"rlnm", M(23,0), M_MASK, PWRCOM, PPCNONE, {RA, RS, RB, MBE, ME}},
4160 {"rotlw.", MME(23,31,1), MMBME_MASK, PPCCOM, PPCNONE, {RA, RS, RB}},
4161 {"rlwnm.", M(23,1), M_MASK, PPCCOM, PPCNONE, {RA, RS, RB, MBE, ME}},
4162 {"rlnm.", M(23,1), M_MASK, PWRCOM, PPCNONE, {RA, RS, RB, MBE, ME}},
4163
4164 {"nop", OP(24), 0xffffffff, PPCCOM, PPCNONE, {0}},
4165 {"ori", OP(24), OP_MASK, PPCCOM, PPCNONE, {RA, RS, UI}},
4166 {"oril", OP(24), OP_MASK, PWRCOM, PPCNONE, {RA, RS, UI}},
4167
4168 {"oris", OP(25), OP_MASK, PPCCOM, PPCNONE, {RA, RS, UI}},
4169 {"oriu", OP(25), OP_MASK, PWRCOM, PPCNONE, {RA, RS, UI}},
4170
4171 {"xnop", OP(26), 0xffffffff, PPCCOM, PPCNONE, {0}},
4172 {"xori", OP(26), OP_MASK, PPCCOM, PPCNONE, {RA, RS, UI}},
4173 {"xoril", OP(26), OP_MASK, PWRCOM, PPCNONE, {RA, RS, UI}},
4174
4175 {"xoris", OP(27), OP_MASK, PPCCOM, PPCNONE, {RA, RS, UI}},
4176 {"xoriu", OP(27), OP_MASK, PWRCOM, PPCNONE, {RA, RS, UI}},
4177
4178 {"andi.", OP(28), OP_MASK, PPCCOM, PPCNONE, {RA, RS, UI}},
4179 {"andil.", OP(28), OP_MASK, PWRCOM, PPCNONE, {RA, RS, UI}},
4180
4181 {"andis.", OP(29), OP_MASK, PPCCOM, PPCNONE, {RA, RS, UI}},
4182 {"andiu.", OP(29), OP_MASK, PWRCOM, PPCNONE, {RA, RS, UI}},
4183
4184 {"rotldi", MD(30,0,0), MDMB_MASK, PPC64, PPCNONE, {RA, RS, SH6}},
4185 {"clrldi", MD(30,0,0), MDSH_MASK, PPC64, PPCNONE, {RA, RS, MB6}},
4186 {"rldicl", MD(30,0,0), MD_MASK, PPC64, PPCNONE, {RA, RS, SH6, MB6}},
4187 {"rotldi.", MD(30,0,1), MDMB_MASK, PPC64, PPCNONE, {RA, RS, SH6}},
4188 {"clrldi.", MD(30,0,1), MDSH_MASK, PPC64, PPCNONE, {RA, RS, MB6}},
4189 {"rldicl.", MD(30,0,1), MD_MASK, PPC64, PPCNONE, {RA, RS, SH6, MB6}},
4190
4191 {"rldicr", MD(30,1,0), MD_MASK, PPC64, PPCNONE, {RA, RS, SH6, ME6}},
4192 {"rldicr.", MD(30,1,1), MD_MASK, PPC64, PPCNONE, {RA, RS, SH6, ME6}},
4193
4194 {"rldic", MD(30,2,0), MD_MASK, PPC64, PPCNONE, {RA, RS, SH6, MB6}},
4195 {"rldic.", MD(30,2,1), MD_MASK, PPC64, PPCNONE, {RA, RS, SH6, MB6}},
4196
4197 {"rldimi", MD(30,3,0), MD_MASK, PPC64, PPCNONE, {RA, RS, SH6, MB6}},
4198 {"rldimi.", MD(30,3,1), MD_MASK, PPC64, PPCNONE, {RA, RS, SH6, MB6}},
4199
4200 {"rotld", MDS(30,8,0), MDSMB_MASK, PPC64, PPCNONE, {RA, RS, RB}},
4201 {"rldcl", MDS(30,8,0), MDS_MASK, PPC64, PPCNONE, {RA, RS, RB, MB6}},
4202 {"rotld.", MDS(30,8,1), MDSMB_MASK, PPC64, PPCNONE, {RA, RS, RB}},
4203 {"rldcl.", MDS(30,8,1), MDS_MASK, PPC64, PPCNONE, {RA, RS, RB, MB6}},
4204
4205 {"rldcr", MDS(30,9,0), MDS_MASK, PPC64, PPCNONE, {RA, RS, RB, ME6}},
4206 {"rldcr.", MDS(30,9,1), MDS_MASK, PPC64, PPCNONE, {RA, RS, RB, ME6}},
4207
4208 {"cmpw", XOPL(31,0,0), XCMPL_MASK, PPCCOM, PPCNONE, {OBF, RA, RB}},
4209 {"cmpd", XOPL(31,0,1), XCMPL_MASK, PPC64, PPCNONE, {OBF, RA, RB}},
4210 {"cmp", X(31,0), XCMP_MASK, PPC|PPCVLE, PPCNONE, {BF, L, RA, RB}},
4211 {"cmp", X(31,0), XCMPL_MASK, PWRCOM, PPC, {BF, RA, RB}},
4212
4213 {"twlgt", XTO(31,4,TOLGT), XTO_MASK, PPCCOM|PPCVLE, PPCNONE, {RA, RB}},
4214 {"tlgt", XTO(31,4,TOLGT), XTO_MASK, PWRCOM, PPCNONE, {RA, RB}},
4215 {"twllt", XTO(31,4,TOLLT), XTO_MASK, PPCCOM|PPCVLE, PPCNONE, {RA, RB}},
4216 {"tllt", XTO(31,4,TOLLT), XTO_MASK, PWRCOM, PPCNONE, {RA, RB}},
4217 {"tweq", XTO(31,4,TOEQ), XTO_MASK, PPCCOM|PPCVLE, PPCNONE, {RA, RB}},
4218 {"teq", XTO(31,4,TOEQ), XTO_MASK, PWRCOM, PPCNONE, {RA, RB}},
4219 {"twlge", XTO(31,4,TOLGE), XTO_MASK, PPCCOM|PPCVLE, PPCNONE, {RA, RB}},
4220 {"tlge", XTO(31,4,TOLGE), XTO_MASK, PWRCOM, PPCNONE, {RA, RB}},
4221 {"twlnl", XTO(31,4,TOLNL), XTO_MASK, PPCCOM|PPCVLE, PPCNONE, {RA, RB}},
4222 {"tlnl", XTO(31,4,TOLNL), XTO_MASK, PWRCOM, PPCNONE, {RA, RB}},
4223 {"twlle", XTO(31,4,TOLLE), XTO_MASK, PPCCOM|PPCVLE, PPCNONE, {RA, RB}},
4224 {"tlle", XTO(31,4,TOLLE), XTO_MASK, PWRCOM, PPCNONE, {RA, RB}},
4225 {"twlng", XTO(31,4,TOLNG), XTO_MASK, PPCCOM|PPCVLE, PPCNONE, {RA, RB}},
4226 {"tlng", XTO(31,4,TOLNG), XTO_MASK, PWRCOM, PPCNONE, {RA, RB}},
4227 {"twgt", XTO(31,4,TOGT), XTO_MASK, PPCCOM|PPCVLE, PPCNONE, {RA, RB}},
4228 {"tgt", XTO(31,4,TOGT), XTO_MASK, PWRCOM, PPCNONE, {RA, RB}},
4229 {"twge", XTO(31,4,TOGE), XTO_MASK, PPCCOM|PPCVLE, PPCNONE, {RA, RB}},
4230 {"tge", XTO(31,4,TOGE), XTO_MASK, PWRCOM, PPCNONE, {RA, RB}},
4231 {"twnl", XTO(31,4,TONL), XTO_MASK, PPCCOM|PPCVLE, PPCNONE, {RA, RB}},
4232 {"tnl", XTO(31,4,TONL), XTO_MASK, PWRCOM, PPCNONE, {RA, RB}},
4233 {"twlt", XTO(31,4,TOLT), XTO_MASK, PPCCOM|PPCVLE, PPCNONE, {RA, RB}},
4234 {"tlt", XTO(31,4,TOLT), XTO_MASK, PWRCOM, PPCNONE, {RA, RB}},
4235 {"twle", XTO(31,4,TOLE), XTO_MASK, PPCCOM|PPCVLE, PPCNONE, {RA, RB}},
4236 {"tle", XTO(31,4,TOLE), XTO_MASK, PWRCOM, PPCNONE, {RA, RB}},
4237 {"twng", XTO(31,4,TONG), XTO_MASK, PPCCOM|PPCVLE, PPCNONE, {RA, RB}},
4238 {"tng", XTO(31,4,TONG), XTO_MASK, PWRCOM, PPCNONE, {RA, RB}},
4239 {"twne", XTO(31,4,TONE), XTO_MASK, PPCCOM|PPCVLE, PPCNONE, {RA, RB}},
4240 {"tne", XTO(31,4,TONE), XTO_MASK, PWRCOM, PPCNONE, {RA, RB}},
4241 {"trap", XTO(31,4,TOU), 0xffffffff, PPCCOM|PPCVLE, PPCNONE, {0}},
4242 {"tw", X(31,4), X_MASK, PPCCOM|PPCVLE, PPCNONE, {TO, RA, RB}},
4243 {"t", X(31,4), X_MASK, PWRCOM, PPCNONE, {TO, RA, RB}},
4244
4245 {"lvsl", X(31,6), X_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, RA0, RB}},
4246 {"lvebx", X(31,7), X_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, RA0, RB}},
4247 {"lbfcmx", APU(31,7,0), APU_MASK, PPC405, PPCNONE, {FCRT, RA, RB}},
4248
4249 {"subfc", XO(31,8,0,0), XO_MASK, PPCCOM|PPCVLE, PPCNONE, {RT, RA, RB}},
4250 {"sf", XO(31,8,0,0), XO_MASK, PWRCOM, PPCNONE, {RT, RA, RB}},
4251 {"subc", XO(31,8,0,0), XO_MASK, PPCCOM|PPCVLE, PPCNONE, {RT, RB, RA}},
4252 {"subfc.", XO(31,8,0,1), XO_MASK, PPCCOM|PPCVLE, PPCNONE, {RT, RA, RB}},
4253 {"sf.", XO(31,8,0,1), XO_MASK, PWRCOM, PPCNONE, {RT, RA, RB}},
4254 {"subc.", XO(31,8,0,1), XO_MASK, PPCCOM|PPCVLE, PPCNONE, {RT, RB, RA}},
4255
4256 {"mulhdu", XO(31,9,0,0), XO_MASK, PPC64|PPCVLE, PPCNONE, {RT, RA, RB}},
4257 {"mulhdu.", XO(31,9,0,1), XO_MASK, PPC64|PPCVLE, PPCNONE, {RT, RA, RB}},
4258
4259 {"addc", XO(31,10,0,0), XO_MASK, PPCCOM|PPCVLE, PPCNONE, {RT, RA, RB}},
4260 {"a", XO(31,10,0,0), XO_MASK, PWRCOM, PPCNONE, {RT, RA, RB}},
4261 {"addc.", XO(31,10,0,1), XO_MASK, PPCCOM|PPCVLE, PPCNONE, {RT, RA, RB}},
4262 {"a.", XO(31,10,0,1), XO_MASK, PWRCOM, PPCNONE, {RT, RA, RB}},
4263
4264 {"mulhwu", XO(31,11,0,0), XO_MASK, PPC|PPCVLE, PPCNONE, {RT, RA, RB}},
4265 {"mulhwu.", XO(31,11,0,1), XO_MASK, PPC|PPCVLE, PPCNONE, {RT, RA, RB}},
4266
4267 {"isellt", X(31,15), X_MASK, PPCISEL, PPCNONE, {RT, RA0, RB}},
4268
4269 {"tlbilxlpid", XTO(31,18,0), XTO_MASK, E500MC|PPCA2, PPCNONE, {0}},
4270 {"tlbilxpid", XTO(31,18,1), XTO_MASK, E500MC|PPCA2, PPCNONE, {0}},
4271 {"tlbilxva", XTO(31,18,3), XTO_MASK, E500MC|PPCA2, PPCNONE, {RA0, RB}},
4272 {"tlbilx", X(31,18), X_MASK, E500MC|PPCA2, PPCNONE, {T, RA0, RB}},
4273
4274 {"mfcr", XFXM(31,19,0,0), XFXFXM_MASK, POWER4, PPCNONE, {RT, FXM4}},
4275 {"mfcr", XFXM(31,19,0,0), XRARB_MASK, COM|PPCVLE, POWER4, {RT}},
4276 {"mfocrf", XFXM(31,19,0,1), XFXFXM_MASK, COM|PPCVLE, PPCNONE, {RT, FXM}},
4277
4278 {"lwarx", X(31,20), XEH_MASK, PPC|PPCVLE, PPCNONE, {RT, RA0, RB, EH}},
4279
4280 {"ldx", X(31,21), X_MASK, PPC64|PPCVLE, PPCNONE, {RT, RA0, RB}},
4281
4282 {"icbt", X(31,22), X_MASK, BOOKE|PPCE300|PPCA2|PPC476|PPCVLE, PPCNONE, {CT, RA0, RB}},
4283
4284 {"lwzx", X(31,23), X_MASK, PPCCOM|PPCVLE, PPCNONE, {RT, RA0, RB}},
4285 {"lx", X(31,23), X_MASK, PWRCOM, PPCNONE, {RT, RA, RB}},
4286
4287 {"slw", XRC(31,24,0), X_MASK, PPCCOM|PPCVLE, PPCNONE, {RA, RS, RB}},
4288 {"sl", XRC(31,24,0), X_MASK, PWRCOM, PPCNONE, {RA, RS, RB}},
4289 {"slw.", XRC(31,24,1), X_MASK, PPCCOM|PPCVLE, PPCNONE, {RA, RS, RB}},
4290 {"sl.", XRC(31,24,1), X_MASK, PWRCOM, PPCNONE, {RA, RS, RB}},
4291
4292 {"cntlzw", XRC(31,26,0), XRB_MASK, PPCCOM|PPCVLE, PPCNONE, {RA, RS}},
4293 {"cntlz", XRC(31,26,0), XRB_MASK, PWRCOM, PPCNONE, {RA, RS}},
4294 {"cntlzw.", XRC(31,26,1), XRB_MASK, PPCCOM|PPCVLE, PPCNONE, {RA, RS}},
4295 {"cntlz.", XRC(31,26,1), XRB_MASK, PWRCOM, PPCNONE, {RA, RS}},
4296
4297 {"sld", XRC(31,27,0), X_MASK, PPC64, PPCNONE, {RA, RS, RB}},
4298 {"sld.", XRC(31,27,1), X_MASK, PPC64, PPCNONE, {RA, RS, RB}},
4299
4300 {"and", XRC(31,28,0), X_MASK, COM|PPCVLE, PPCNONE, {RA, RS, RB}},
4301 {"and.", XRC(31,28,1), X_MASK, COM|PPCVLE, PPCNONE, {RA, RS, RB}},
4302
4303 {"maskg", XRC(31,29,0), X_MASK, M601, PPCA2, {RA, RS, RB}},
4304 {"maskg.", XRC(31,29,1), X_MASK, M601, PPCA2, {RA, RS, RB}},
4305
4306 {"ldepx", X(31,29), X_MASK, E500MC|PPCA2|PPCVLE, PPCNONE, {RT, RA0, RB}},
4307 {"lwepx", X(31,31), X_MASK, E500MC|PPCA2|PPCVLE, PPCNONE, {RT, RA0, RB}},
4308
4309 {"cmplw", XOPL(31,32,0), XCMPL_MASK, PPCCOM|PPCVLE, PPCNONE, {OBF, RA, RB}},
4310 {"cmpld", XOPL(31,32,1), XCMPL_MASK, PPC64, PPCNONE, {OBF, RA, RB}},
4311 {"cmpl", X(31,32), XCMP_MASK, PPC|PPCVLE, PPCNONE, {BF, L, RA, RB}},
4312 {"cmpl", X(31,32), XCMPL_MASK, PWRCOM, PPC, {BF, RA, RB}},
4313
4314 {"lvsr", X(31,38), X_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, RA0, RB}},
4315 {"lvehx", X(31,39), X_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, RA0, RB}},
4316 {"lhfcmx", APU(31,39,0), APU_MASK, PPC405, PPCNONE, {FCRT, RA, RB}},
4317
4318 {"mviwsplt", X(31,46), X_MASK, PPCVEC2, PPCNONE, {VD, RA, RB}},
4319
4320 {"iselgt", X(31,47), X_MASK, PPCISEL, PPCNONE, {RT, RA0, RB}},
4321
4322 {"lvewx", X(31,71), X_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, RA0, RB}},
4323
4324 {"addg6s", XO(31,74,0,0), XO_MASK, POWER6, PPCNONE, {RT, RA, RB}},
4325
4326 {"iseleq", X(31,79), X_MASK, PPCISEL, PPCNONE, {RT, RA0, RB}},
4327
4328 {"isel", XISEL(31,15), XISEL_MASK, PPCISEL|TITAN|PPCVLE, PPCNONE, {RT, RA0, RB, CRB}},
4329
4330 {"subf", XO(31,40,0,0), XO_MASK, PPC|PPCVLE, PPCNONE, {RT, RA, RB}},
4331 {"sub", XO(31,40,0,0), XO_MASK, PPC|PPCVLE, PPCNONE, {RT, RB, RA}},
4332 {"subf.", XO(31,40,0,1), XO_MASK, PPC|PPCVLE, PPCNONE, {RT, RA, RB}},
4333 {"sub.", XO(31,40,0,1), XO_MASK, PPC|PPCVLE, PPCNONE, {RT, RB, RA}},
4334
4335 {"eratilx", X(31,51), X_MASK, PPCA2, PPCNONE, {ERAT_T, RA, RB}},
4336
4337 {"lbarx", X(31,52), XEH_MASK, POWER7|PPCVLE, PPCNONE, {RT, RA0, RB, EH}},
4338
4339 {"ldux", X(31,53), X_MASK, PPC64|PPCVLE, PPCNONE, {RT, RAL, RB}},
4340
4341 {"dcbst", X(31,54), XRT_MASK, PPC|PPCVLE, PPCNONE, {RA0, RB}},
4342
4343 {"lwzux", X(31,55), X_MASK, PPCCOM|PPCVLE, PPCNONE, {RT, RAL, RB}},
4344 {"lux", X(31,55), X_MASK, PWRCOM, PPCNONE, {RT, RA, RB}},
4345
4346 {"cntlzd", XRC(31,58,0), XRB_MASK, PPC64|PPCVLE, PPCNONE, {RA, RS}},
4347 {"cntlzd.", XRC(31,58,1), XRB_MASK, PPC64|PPCVLE, PPCNONE, {RA, RS}},
4348
4349 {"andc", XRC(31,60,0), X_MASK, COM|PPCVLE, PPCNONE, {RA, RS, RB}},
4350 {"andc.", XRC(31,60,1), X_MASK, COM|PPCVLE, PPCNONE, {RA, RS, RB}},
4351
4352 {"waitrsv", X(31,62)|(1<<21), 0xffffffff, POWER7|E500MC|PPCA2, PPCNONE, {0}},
4353 {"waitimpl", X(31,62)|(2<<21), 0xffffffff, POWER7|E500MC|PPCA2, PPCNONE, {0}},
4354 {"wait", X(31,62), XWC_MASK, POWER7|E500MC|PPCA2|PPCVLE, PPCNONE, {WC}},
4355
4356 {"dcbstep", XRT(31,63,0), XRT_MASK, E500MC|PPCA2|PPCVLE, PPCNONE, {RA0, RB}},
4357
4358 {"tdlgt", XTO(31,68,TOLGT), XTO_MASK, PPC64, PPCNONE, {RA, RB}},
4359 {"tdllt", XTO(31,68,TOLLT), XTO_MASK, PPC64, PPCNONE, {RA, RB}},
4360 {"tdeq", XTO(31,68,TOEQ), XTO_MASK, PPC64, PPCNONE, {RA, RB}},
4361 {"tdlge", XTO(31,68,TOLGE), XTO_MASK, PPC64, PPCNONE, {RA, RB}},
4362 {"tdlnl", XTO(31,68,TOLNL), XTO_MASK, PPC64, PPCNONE, {RA, RB}},
4363 {"tdlle", XTO(31,68,TOLLE), XTO_MASK, PPC64, PPCNONE, {RA, RB}},
4364 {"tdlng", XTO(31,68,TOLNG), XTO_MASK, PPC64, PPCNONE, {RA, RB}},
4365 {"tdgt", XTO(31,68,TOGT), XTO_MASK, PPC64, PPCNONE, {RA, RB}},
4366 {"tdge", XTO(31,68,TOGE), XTO_MASK, PPC64, PPCNONE, {RA, RB}},
4367 {"tdnl", XTO(31,68,TONL), XTO_MASK, PPC64, PPCNONE, {RA, RB}},
4368 {"tdlt", XTO(31,68,TOLT), XTO_MASK, PPC64, PPCNONE, {RA, RB}},
4369 {"tdle", XTO(31,68,TOLE), XTO_MASK, PPC64, PPCNONE, {RA, RB}},
4370 {"tdng", XTO(31,68,TONG), XTO_MASK, PPC64, PPCNONE, {RA, RB}},
4371 {"tdne", XTO(31,68,TONE), XTO_MASK, PPC64, PPCNONE, {RA, RB}},
4372 {"td", X(31,68), X_MASK, PPC64|PPCVLE, PPCNONE, {TO, RA, RB}},
4373
4374 {"lwfcmx", APU(31,71,0), APU_MASK, PPC405, PPCNONE, {FCRT, RA, RB}},
4375 {"mulhd", XO(31,73,0,0), XO_MASK, PPC64|PPCVLE, PPCNONE, {RT, RA, RB}},
4376 {"mulhd.", XO(31,73,0,1), XO_MASK, PPC64|PPCVLE, PPCNONE, {RT, RA, RB}},
4377
4378 {"mulhw", XO(31,75,0,0), XO_MASK, PPC|PPCVLE, PPCNONE, {RT, RA, RB}},
4379 {"mulhw.", XO(31,75,0,1), XO_MASK, PPC|PPCVLE, PPCNONE, {RT, RA, RB}},
4380
4381 {"dlmzb", XRC(31,78,0), X_MASK, PPC403|PPC440|TITAN|PPCVLE, PPCNONE, {RA, RS, RB}},
4382 {"dlmzb.", XRC(31,78,1), X_MASK, PPC403|PPC440|TITAN|PPCVLE, PPCNONE, {RA, RS, RB}},
4383
4384 {"mtsrd", X(31,82), XRB_MASK|(1<<20), PPC64, PPCNONE, {SR, RS}},
4385
4386 {"mfmsr", X(31,83), XRARB_MASK, COM|PPCVLE, PPCNONE, {RT}},
4387
4388 {"ldarx", X(31,84), XEH_MASK, PPC64|PPCVLE, PPCNONE, {RT, RA0, RB, EH}},
4389
4390 {"dcbfl", XOPL(31,86,1), XRT_MASK, POWER5, PPC476, {RA0, RB}},
4391 {"dcbf", X(31,86), XLRT_MASK, PPC|PPCVLE, PPCNONE, {RA0, RB, L}},
4392
4393 {"lbzx", X(31,87), X_MASK, COM|PPCVLE, PPCNONE, {RT, RA0, RB}},
4394
4395 {"lbepx", X(31,95), X_MASK, E500MC|PPCA2|PPCVLE, PPCNONE, {RT, RA0, RB}},
4396
4397 {"dni", XRC(31,97,1), XRB_MASK, E6500, PPCNONE, {DUI, DCTL}},
4398
4399 {"lvx", X(31,103), X_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, RA0, RB}},
4400 {"lqfcmx", APU(31,103,0), APU_MASK, PPC405, PPCNONE, {FCRT, RA, RB}},
4401
4402 {"neg", XO(31,104,0,0), XORB_MASK, COM|PPCVLE, PPCNONE, {RT, RA}},
4403 {"neg.", XO(31,104,0,1), XORB_MASK, COM|PPCVLE, PPCNONE, {RT, RA}},
4404
4405 {"mul", XO(31,107,0,0), XO_MASK, M601, PPCNONE, {RT, RA, RB}},
4406 {"mul.", XO(31,107,0,1), XO_MASK, M601, PPCNONE, {RT, RA, RB}},
4407
4408 {"mvidsplt", X(31,110), X_MASK, PPCVEC2, PPCNONE, {VD, RA, RB}},
4409
4410 {"mtsrdin", X(31,114), XRA_MASK, PPC64, PPCNONE, {RS, RB}},
4411
4412 {"lharx", X(31,116), XEH_MASK, POWER7|PPCVLE, PPCNONE, {RT, RA0, RB, EH}},
4413
4414 {"clf", X(31,118), XTO_MASK, POWER, PPCNONE, {RA, RB}},
4415
4416 {"lbzux", X(31,119), X_MASK, COM|PPCVLE, PPCNONE, {RT, RAL, RB}},
4417
4418 {"popcntb", X(31,122), XRB_MASK, POWER5|PPCVLE, PPCNONE, {RA, RS}},
4419
4420 {"not", XRC(31,124,0), X_MASK, COM, PPCNONE, {RA, RS, RBS}},
4421 {"nor", XRC(31,124,0), X_MASK, COM|PPCVLE, PPCNONE, {RA, RS, RB}},
4422 {"not.", XRC(31,124,1), X_MASK, COM, PPCNONE, {RA, RS, RBS}},
4423 {"nor.", XRC(31,124,1), X_MASK, COM|PPCVLE, PPCNONE, {RA, RS, RB}},
4424
4425 {"dcbfep", XRT(31,127,0), XRT_MASK, E500MC|PPCA2|PPCVLE, PPCNONE, {RA0, RB}},
4426
4427 {"wrtee", X(31,131), XRARB_MASK, PPC403|BOOKE|PPCA2|PPC476|PPCVLE, PPCNONE, {RS}},
4428
4429 {"dcbtstls", X(31,134), X_MASK, PPCCHLK|PPC476|TITAN|PPCVLE, PPCNONE, {CT, RA0, RB}},
4430
4431 {"stvebx", X(31,135), X_MASK, PPCVEC, PPCNONE, {VS, RA0, RB}},
4432 {"stbfcmx", APU(31,135,0), APU_MASK, PPC405, PPCNONE, {FCRT, RA, RB}},
4433
4434 {"subfe", XO(31,136,0,0), XO_MASK, PPCCOM|PPCVLE, PPCNONE, {RT, RA, RB}},
4435 {"sfe", XO(31,136,0,0), XO_MASK, PWRCOM, PPCNONE, {RT, RA, RB}},
4436 {"subfe.", XO(31,136,0,1), XO_MASK, PPCCOM|PPCVLE, PPCNONE, {RT, RA, RB}},
4437 {"sfe.", XO(31,136,0,1), XO_MASK, PWRCOM, PPCNONE, {RT, RA, RB}},
4438
4439 {"adde", XO(31,138,0,0), XO_MASK, PPCCOM|PPCVLE, PPCNONE, {RT, RA, RB}},
4440 {"ae", XO(31,138,0,0), XO_MASK, PWRCOM, PPCNONE, {RT, RA, RB}},
4441 {"adde.", XO(31,138,0,1), XO_MASK, PPCCOM|PPCVLE, PPCNONE, {RT, RA, RB}},
4442 {"ae.", XO(31,138,0,1), XO_MASK, PWRCOM, PPCNONE, {RT, RA, RB}},
4443
4444 {"dcbtstlse", X(31,142), X_MASK, PPCCHLK, E500MC, {CT, RA0, RB}},
4445
4446 {"mtcr", XFXM(31,144,0xff,0), XRARB_MASK, COM, PPCNONE, {RS}},
4447 {"mtcrf", XFXM(31,144,0,0), XFXFXM_MASK, COM|PPCVLE, PPCNONE, {FXM, RS}},
4448 {"mtocrf", XFXM(31,144,0,1), XFXFXM_MASK, COM|PPCVLE, PPCNONE, {FXM, RS}},
4449
4450 {"mtmsr", X(31,146), XRLARB_MASK, COM|PPCVLE, PPCNONE, {RS, A_L}},
4451
4452 {"eratsx", XRC(31,147,0), X_MASK, PPCA2, PPCNONE, {RT, RA0, RB}},
4453 {"eratsx.", XRC(31,147,1), X_MASK, PPCA2, PPCNONE, {RT, RA0, RB}},
4454
4455 {"stdx", X(31,149), X_MASK, PPC64|PPCVLE, PPCNONE, {RS, RA0, RB}},
4456
4457 {"stwcx.", XRC(31,150,1), X_MASK, PPC|PPCVLE, PPCNONE, {RS, RA0, RB}},
4458
4459 {"stwx", X(31,151), X_MASK, PPCCOM|PPCVLE, PPCNONE, {RS, RA0, RB}},
4460 {"stx", X(31,151), X_MASK, PWRCOM, PPCNONE, {RS, RA, RB}},
4461
4462 {"slq", XRC(31,152,0), X_MASK, M601, PPCNONE, {RA, RS, RB}},
4463 {"slq.", XRC(31,152,1), X_MASK, M601, PPCNONE, {RA, RS, RB}},
4464
4465 {"sle", XRC(31,153,0), X_MASK, M601, PPCNONE, {RA, RS, RB}},
4466 {"sle.", XRC(31,153,1), X_MASK, M601, PPCNONE, {RA, RS, RB}},
4467
4468 {"prtyw", X(31,154), XRB_MASK, POWER6|PPCA2|PPC476, PPCNONE, {RA, RS}},
4469
4470 {"stdepx", X(31,157), X_MASK, E500MC|PPCA2|PPCVLE, PPCNONE, {RS, RA0, RB}},
4471
4472 {"stwepx", X(31,159), X_MASK, E500MC|PPCA2|PPCVLE, PPCNONE, {RS, RA0, RB}},
4473
4474 {"wrteei", X(31,163), XE_MASK, PPC403|BOOKE|PPCA2|PPC476|PPCVLE, PPCNONE, {E}},
4475
4476 {"dcbtls", X(31,166), X_MASK, PPCCHLK|PPC476|TITAN|PPCVLE, PPCNONE, {CT, RA0, RB}},
4477
4478 {"stvehx", X(31,167), X_MASK, PPCVEC, PPCNONE, {VS, RA0, RB}},
4479 {"sthfcmx", APU(31,167,0), APU_MASK, PPC405, PPCNONE, {FCRT, RA, RB}},
4480
4481 {"dcbtlse", X(31,174), X_MASK, PPCCHLK, E500MC, {CT, RA0, RB}},
4482
4483 {"mtmsrd", X(31,178), XRLARB_MASK, PPC64, PPCNONE, {RS, A_L}},
4484
4485 {"eratre", X(31,179), X_MASK, PPCA2, PPCNONE, {RT, RA, WS}},
4486
4487 {"stdux", X(31,181), X_MASK, PPC64|PPCVLE, PPCNONE, {RS, RAS, RB}},
4488
4489 {"wchkall", X(31,182), X_MASK, PPCA2, PPCNONE, {OBF}},
4490
4491 {"stwux", X(31,183), X_MASK, PPCCOM|PPCVLE, PPCNONE, {RS, RAS, RB}},
4492 {"stux", X(31,183), X_MASK, PWRCOM, PPCNONE, {RS, RA0, RB}},
4493
4494 {"sliq", XRC(31,184,0), X_MASK, M601, PPCNONE, {RA, RS, SH}},
4495 {"sliq.", XRC(31,184,1), X_MASK, M601, PPCNONE, {RA, RS, SH}},
4496
4497 {"prtyd", X(31,186), XRB_MASK, POWER6|PPCA2, PPCNONE, {RA, RS}},
4498
4499 {"icblq.", XRC(31,198,1), X_MASK, E6500, PPCNONE, {CT, RA0, RB}},
4500
4501 {"stvewx", X(31,199), X_MASK, PPCVEC, PPCNONE, {VS, RA0, RB}},
4502 {"stwfcmx", APU(31,199,0), APU_MASK, PPC405, PPCNONE, {FCRT, RA, RB}},
4503
4504 {"subfze", XO(31,200,0,0), XORB_MASK, PPCCOM|PPCVLE, PPCNONE, {RT, RA}},
4505 {"sfze", XO(31,200,0,0), XORB_MASK, PWRCOM, PPCNONE, {RT, RA}},
4506 {"subfze.", XO(31,200,0,1), XORB_MASK, PPCCOM|PPCVLE, PPCNONE, {RT, RA}},
4507 {"sfze.", XO(31,200,0,1), XORB_MASK, PWRCOM, PPCNONE, {RT, RA}},
4508
4509 {"addze", XO(31,202,0,0), XORB_MASK, PPCCOM|PPCVLE, PPCNONE, {RT, RA}},
4510 {"aze", XO(31,202,0,0), XORB_MASK, PWRCOM, PPCNONE, {RT, RA}},
4511 {"addze.", XO(31,202,0,1), XORB_MASK, PPCCOM|PPCVLE, PPCNONE, {RT, RA}},
4512 {"aze.", XO(31,202,0,1), XORB_MASK, PWRCOM, PPCNONE, {RT, RA}},
4513
4514 {"msgsnd", XRTRA(31,206,0,0), XRTRA_MASK, E500MC|PPCA2|PPCVLE, PPCNONE, {RB}},
4515
4516 {"mtsr", X(31,210), XRB_MASK|(1<<20), COM, NON32, {SR, RS}},
4517
4518 {"eratwe", X(31,211), X_MASK, PPCA2, PPCNONE, {RS, RA, WS}},
4519
4520 {"ldawx.", XRC(31,212,1), X_MASK, PPCA2, PPCNONE, {RT, RA0, RB}},
4521
4522 {"stdcx.", XRC(31,214,1), X_MASK, PPC64|PPCVLE, PPCNONE, {RS, RA0, RB}},
4523
4524 {"stbx", X(31,215), X_MASK, COM|PPCVLE, PPCNONE, {RS, RA0, RB}},
4525
4526 {"sllq", XRC(31,216,0), X_MASK, M601, PPCNONE, {RA, RS, RB}},
4527 {"sllq.", XRC(31,216,1), X_MASK, M601, PPCNONE, {RA, RS, RB}},
4528
4529 {"sleq", XRC(31,217,0), X_MASK, M601, PPCNONE, {RA, RS, RB}},
4530 {"sleq.", XRC(31,217,1), X_MASK, M601, PPCNONE, {RA, RS, RB}},
4531
4532 {"stbepx", X(31,223), X_MASK, E500MC|PPCA2|PPCVLE, PPCNONE, {RS, RA0, RB}},
4533
4534 {"icblc", X(31,230), X_MASK, PPCCHLK|PPC476|TITAN|PPCVLE, PPCNONE, {CT, RA0, RB}},
4535
4536 {"stvx", X(31,231), X_MASK, PPCVEC|PPCVLE, PPCNONE, {VS, RA0, RB}},
4537 {"stqfcmx", APU(31,231,0), APU_MASK, PPC405, PPCNONE, {FCRT, RA, RB}},
4538
4539 {"subfme", XO(31,232,0,0), XORB_MASK, PPCCOM|PPCVLE, PPCNONE, {RT, RA}},
4540 {"sfme", XO(31,232,0,0), XORB_MASK, PWRCOM, PPCNONE, {RT, RA}},
4541 {"subfme.", XO(31,232,0,1), XORB_MASK, PPCCOM|PPCVLE, PPCNONE, {RT, RA}},
4542 {"sfme.", XO(31,232,0,1), XORB_MASK, PWRCOM, PPCNONE, {RT, RA}},
4543
4544 {"mulld", XO(31,233,0,0), XO_MASK, PPC64|PPCVLE, PPCNONE, {RT, RA, RB}},
4545 {"mulld.", XO(31,233,0,1), XO_MASK, PPC64|PPCVLE, PPCNONE, {RT, RA, RB}},
4546
4547 {"addme", XO(31,234,0,0), XORB_MASK, PPCCOM|PPCVLE, PPCNONE, {RT, RA}},
4548 {"ame", XO(31,234,0,0), XORB_MASK, PWRCOM, PPCNONE, {RT, RA}},
4549 {"addme.", XO(31,234,0,1), XORB_MASK, PPCCOM|PPCVLE, PPCNONE, {RT, RA}},
4550 {"ame.", XO(31,234,0,1), XORB_MASK, PWRCOM, PPCNONE, {RT, RA}},
4551
4552 {"mullw", XO(31,235,0,0), XO_MASK, PPCCOM|PPCVLE, PPCNONE, {RT, RA, RB}},
4553 {"muls", XO(31,235,0,0), XO_MASK, PWRCOM, PPCNONE, {RT, RA, RB}},
4554 {"mullw.", XO(31,235,0,1), XO_MASK, PPCCOM|PPCVLE, PPCNONE, {RT, RA, RB}},
4555 {"muls.", XO(31,235,0,1), XO_MASK, PWRCOM, PPCNONE, {RT, RA, RB}},
4556
4557 {"icblce", X(31,238), X_MASK, PPCCHLK, E500MC|PPCA2, {CT, RA, RB}},
4558 {"msgclr", XRTRA(31,238,0,0),XRTRA_MASK, E500MC|PPCA2|PPCVLE, PPCNONE, {RB}},
4559 {"mtsrin", X(31,242), XRA_MASK, PPC, NON32, {RS, RB}},
4560 {"mtsri", X(31,242), XRA_MASK, POWER, NON32, {RS, RB}},
4561
4562 {"dcbtstt", XRT(31,246,0x10), XRT_MASK, POWER7, PPCNONE, {RA0, RB}},
4563 {"dcbtst", X(31,246), X_MASK, POWER4, PPCNONE, {RA0, RB, CT}},
4564 {"dcbtst", X(31,246), X_MASK, PPC|PPCVLE, POWER4, {CT, RA0, RB}},
4565
4566 {"stbux", X(31,247), X_MASK, COM|PPCVLE, PPCNONE, {RS, RAS, RB}},
4567
4568 {"slliq", XRC(31,248,0), X_MASK, M601, PPCNONE, {RA, RS, SH}},
4569 {"slliq.", XRC(31,248,1), X_MASK, M601, PPCNONE, {RA, RS, SH}},
4570
4571 {"bpermd", X(31,252), X_MASK, POWER7|PPCA2, PPCNONE, {RA, RS, RB}},
4572
4573 {"dcbtstep", XRT(31,255,0), X_MASK, E500MC|PPCA2|PPCVLE, PPCNONE, {RT, RA0, RB}},
4574
4575 {"mfdcrx", X(31,259), X_MASK, BOOKE|PPCA2|PPC476|PPCVLE, TITAN, {RS, RA}},
4576 {"mfdcrx.", XRC(31,259,1), X_MASK, PPCA2, PPCNONE, {RS, RA}},
4577
4578 {"lvexbx", X(31,261), X_MASK, PPCVEC2, PPCNONE, {VD, RA0, RB}},
4579
4580 {"icbt", X(31,262), XRT_MASK, PPC403, PPCNONE, {RA, RB}},
4581
4582 {"lvepxl", X(31,263), X_MASK, PPCVEC2|PPCVLE, PPCNONE, {VD, RA0, RB}},
4583
4584 {"ldfcmx", APU(31,263,0), APU_MASK, PPC405, PPCNONE, {FCRT, RA, RB}},
4585 {"doz", XO(31,264,0,0), XO_MASK, M601, PPCNONE, {RT, RA, RB}},
4586 {"doz.", XO(31,264,0,1), XO_MASK, M601, PPCNONE, {RT, RA, RB}},
4587
4588 {"add", XO(31,266,0,0), XO_MASK, PPCCOM|PPCVLE, PPCNONE, {RT, RA, RB}},
4589 {"cax", XO(31,266,0,0), XO_MASK, PWRCOM, PPCNONE, {RT, RA, RB}},
4590 {"add.", XO(31,266,0,1), XO_MASK, PPCCOM|PPCVLE, PPCNONE, {RT, RA, RB}},
4591 {"cax.", XO(31,266,0,1), XO_MASK, PWRCOM, PPCNONE, {RT, RA, RB}},
4592
4593 {"ehpriv", X(31,270), 0xffffffff, E500MC|PPCA2|PPCVLE, PPCNONE, {0}},
4594
4595 {"tlbiel", X(31,274), XRTLRA_MASK, POWER4, PPC476, {RB, L}},
4596
4597 {"mfapidi", X(31,275), X_MASK, BOOKE, TITAN, {RT, RA}},
4598
4599 {"lscbx", XRC(31,277,0), X_MASK, M601, PPCNONE, {RT, RA, RB}},
4600 {"lscbx.", XRC(31,277,1), X_MASK, M601, PPCNONE, {RT, RA, RB}},
4601
4602 {"dcbtt", XRT(31,278,0x10), XRT_MASK, POWER7, PPCNONE, {RA0, RB}},
4603 {"dcbt", X(31,278), X_MASK, POWER4, PPCNONE, {RA0, RB, CT}},
4604 {"dcbt", X(31,278), X_MASK, PPC|PPCVLE, POWER4, {CT, RA0, RB}},
4605
4606 {"lhzx", X(31,279), X_MASK, COM|PPCVLE, PPCNONE, {RT, RA0, RB}},
4607
4608 {"cdtbcd", X(31,282), XRB_MASK, POWER6, PPCNONE, {RA, RS}},
4609
4610 {"eqv", XRC(31,284,0), X_MASK, COM|PPCVLE, PPCNONE, {RA, RS, RB}},
4611 {"eqv.", XRC(31,284,1), X_MASK, COM|PPCVLE, PPCNONE, {RA, RS, RB}},
4612
4613 {"lhepx", X(31,287), X_MASK, E500MC|PPCA2|PPCVLE, PPCNONE, {RT, RA0, RB}},
4614
4615 {"mfdcrux", X(31,291), X_MASK, PPC464|PPCVLE, PPCNONE, {RS, RA}},
4616
4617 {"lvexhx", X(31,293), X_MASK, PPCVEC2, PPCNONE, {VD, RA0, RB}},
4618 {"lvepx", X(31,295), X_MASK, PPCVEC2|PPCVLE, PPCNONE, {VD, RA0, RB}},
4619
4620 {"tlbie", X(31,306), XRTLRA_MASK, PPC, TITAN, {RB, L}},
4621 {"tlbi", X(31,306), XRT_MASK, POWER, PPCNONE, {RA0, RB}},
4622
4623 {"eciwx", X(31,310), X_MASK, PPC, TITAN, {RT, RA0, RB}},
4624
4625 {"lhzux", X(31,311), X_MASK, COM|PPCVLE, PPCNONE, {RT, RAL, RB}},
4626
4627 {"cbcdtd", X(31,314), XRB_MASK, POWER6, PPCNONE, {RA, RS}},
4628
4629 {"xor", XRC(31,316,0), X_MASK, COM|PPCVLE, PPCNONE, {RA, RS, RB}},
4630 {"xor.", XRC(31,316,1), X_MASK, COM|PPCVLE, PPCNONE, {RA, RS, RB}},
4631
4632 {"dcbtep", XRT(31,319,0), X_MASK, E500MC|PPCA2|PPCVLE, PPCNONE, {RT, RA0, RB}},
4633
4634 {"mfexisr", XSPR(31,323, 64), XSPR_MASK, PPC403, PPCNONE, {RT}},
4635 {"mfexier", XSPR(31,323, 66), XSPR_MASK, PPC403, PPCNONE, {RT}},
4636 {"mfbr0", XSPR(31,323,128), XSPR_MASK, PPC403, PPCNONE, {RT}},
4637 {"mfbr1", XSPR(31,323,129), XSPR_MASK, PPC403, PPCNONE, {RT}},
4638 {"mfbr2", XSPR(31,323,130), XSPR_MASK, PPC403, PPCNONE, {RT}},
4639 {"mfbr3", XSPR(31,323,131), XSPR_MASK, PPC403, PPCNONE, {RT}},
4640 {"mfbr4", XSPR(31,323,132), XSPR_MASK, PPC403, PPCNONE, {RT}},
4641 {"mfbr5", XSPR(31,323,133), XSPR_MASK, PPC403, PPCNONE, {RT}},
4642 {"mfbr6", XSPR(31,323,134), XSPR_MASK, PPC403, PPCNONE, {RT}},
4643 {"mfbr7", XSPR(31,323,135), XSPR_MASK, PPC403, PPCNONE, {RT}},
4644 {"mfbear", XSPR(31,323,144), XSPR_MASK, PPC403, PPCNONE, {RT}},
4645 {"mfbesr", XSPR(31,323,145), XSPR_MASK, PPC403, PPCNONE, {RT}},
4646 {"mfiocr", XSPR(31,323,160), XSPR_MASK, PPC403, PPCNONE, {RT}},
4647 {"mfdmacr0", XSPR(31,323,192), XSPR_MASK, PPC403, PPCNONE, {RT}},
4648 {"mfdmact0", XSPR(31,323,193), XSPR_MASK, PPC403, PPCNONE, {RT}},
4649 {"mfdmada0", XSPR(31,323,194), XSPR_MASK, PPC403, PPCNONE, {RT}},
4650 {"mfdmasa0", XSPR(31,323,195), XSPR_MASK, PPC403, PPCNONE, {RT}},
4651 {"mfdmacc0", XSPR(31,323,196), XSPR_MASK, PPC403, PPCNONE, {RT}},
4652 {"mfdmacr1", XSPR(31,323,200), XSPR_MASK, PPC403, PPCNONE, {RT}},
4653 {"mfdmact1", XSPR(31,323,201), XSPR_MASK, PPC403, PPCNONE, {RT}},
4654 {"mfdmada1", XSPR(31,323,202), XSPR_MASK, PPC403, PPCNONE, {RT}},
4655 {"mfdmasa1", XSPR(31,323,203), XSPR_MASK, PPC403, PPCNONE, {RT}},
4656 {"mfdmacc1", XSPR(31,323,204), XSPR_MASK, PPC403, PPCNONE, {RT}},
4657 {"mfdmacr2", XSPR(31,323,208), XSPR_MASK, PPC403, PPCNONE, {RT}},
4658 {"mfdmact2", XSPR(31,323,209), XSPR_MASK, PPC403, PPCNONE, {RT}},
4659 {"mfdmada2", XSPR(31,323,210), XSPR_MASK, PPC403, PPCNONE, {RT}},
4660 {"mfdmasa2", XSPR(31,323,211), XSPR_MASK, PPC403, PPCNONE, {RT}},
4661 {"mfdmacc2", XSPR(31,323,212), XSPR_MASK, PPC403, PPCNONE, {RT}},
4662 {"mfdmacr3", XSPR(31,323,216), XSPR_MASK, PPC403, PPCNONE, {RT}},
4663 {"mfdmact3", XSPR(31,323,217), XSPR_MASK, PPC403, PPCNONE, {RT}},
4664 {"mfdmada3", XSPR(31,323,218), XSPR_MASK, PPC403, PPCNONE, {RT}},
4665 {"mfdmasa3", XSPR(31,323,219), XSPR_MASK, PPC403, PPCNONE, {RT}},
4666 {"mfdmacc3", XSPR(31,323,220), XSPR_MASK, PPC403, PPCNONE, {RT}},
4667 {"mfdmasr", XSPR(31,323,224), XSPR_MASK, PPC403, PPCNONE, {RT}},
4668 {"mfdcr", X(31,323), X_MASK, PPC403|BOOKE|PPCA2|PPC476|PPCVLE, TITAN, {RT, SPR}},
4669 {"mfdcr.", XRC(31,323,1), X_MASK, PPCA2, PPCNONE, {RT, SPR}},
4670
4671 {"lvexwx", X(31,325), X_MASK, PPCVEC2, PPCNONE, {VD, RA0, RB}},
4672
4673 {"dcread", X(31,326), X_MASK, PPC476|TITAN, PPCNONE, {RT, RA0, RB}},
4674
4675 {"div", XO(31,331,0,0), XO_MASK, M601, PPCNONE, {RT, RA, RB}},
4676 {"div.", XO(31,331,0,1), XO_MASK, M601, PPCNONE, {RT, RA, RB}},
4677
4678 {"lxvdsx", X(31,332), XX1_MASK, PPCVSX, PPCNONE, {XT6, RA0, RB}},
4679
4680 {"mfpmr", X(31,334), X_MASK, PPCPMR|PPCE300|PPCVLE, PPCNONE, {RT, PMR}},
4681 {"mftmr", X(31,366), X_MASK, PPCTMR|E6500, PPCNONE, {RT, TMR}},
4682
4683 {"mfmq", XSPR(31,339, 0), XSPR_MASK, M601, PPCNONE, {RT}},
4684 {"mfxer", XSPR(31,339, 1), XSPR_MASK, COM|PPCVLE, PPCNONE, {RT}},
4685 {"mfrtcu", XSPR(31,339, 4), XSPR_MASK, COM, TITAN, {RT}},
4686 {"mfrtcl", XSPR(31,339, 5), XSPR_MASK, COM, TITAN, {RT}},
4687 {"mfdec", XSPR(31,339, 6), XSPR_MASK, MFDEC1, PPCNONE, {RT}},
4688 {"mflr", XSPR(31,339, 8), XSPR_MASK, COM|PPCVLE, PPCNONE, {RT}},
4689 {"mfctr", XSPR(31,339, 9), XSPR_MASK, COM|PPCVLE, PPCNONE, {RT}},
4690 {"mftid", XSPR(31,339, 17), XSPR_MASK, POWER, PPCNONE, {RT}},
4691 {"mfdsisr", XSPR(31,339, 18), XSPR_MASK, COM, TITAN, {RT}},
4692 {"mfdar", XSPR(31,339, 19), XSPR_MASK, COM, TITAN, {RT}},
4693 {"mfdec", XSPR(31,339, 22), XSPR_MASK, MFDEC2, MFDEC1, {RT}},
4694 {"mfsdr0", XSPR(31,339, 24), XSPR_MASK, POWER, PPCNONE, {RT}},
4695 {"mfsdr1", XSPR(31,339, 25), XSPR_MASK, COM, TITAN, {RT}},
4696 {"mfsrr0", XSPR(31,339, 26), XSPR_MASK, COM, PPCNONE, {RT}},
4697 {"mfsrr1", XSPR(31,339, 27), XSPR_MASK, COM, PPCNONE, {RT}},
4698 {"mfcfar", XSPR(31,339, 28), XSPR_MASK, POWER6, PPCNONE, {RT}},
4699 {"mfpid", XSPR(31,339, 48), XSPR_MASK, BOOKE|PPCVLE, PPCNONE, {RT}},
4700 {"mfcsrr0", XSPR(31,339, 58), XSPR_MASK, BOOKE|PPCVLE, PPCNONE, {RT}},
4701 {"mfcsrr1", XSPR(31,339, 59), XSPR_MASK, BOOKE|PPCVLE, PPCNONE, {RT}},
4702 {"mfdear", XSPR(31,339, 61), XSPR_MASK, BOOKE|PPCVLE, PPCNONE, {RT}},
4703 {"mfesr", XSPR(31,339, 62), XSPR_MASK, BOOKE|PPCVLE, PPCNONE, {RT}},
4704 {"mfivpr", XSPR(31,339, 63), XSPR_MASK, BOOKE|PPCVLE, PPCNONE, {RT}},
4705 {"mfcmpa", XSPR(31,339,144), XSPR_MASK, PPC860, PPCNONE, {RT}},
4706 {"mfcmpb", XSPR(31,339,145), XSPR_MASK, PPC860, PPCNONE, {RT}},
4707 {"mfcmpc", XSPR(31,339,146), XSPR_MASK, PPC860, PPCNONE, {RT}},
4708 {"mfcmpd", XSPR(31,339,147), XSPR_MASK, PPC860, PPCNONE, {RT}},
4709 {"mficr", XSPR(31,339,148), XSPR_MASK, PPC860, PPCNONE, {RT}},
4710 {"mfder", XSPR(31,339,149), XSPR_MASK, PPC860, PPCNONE, {RT}},
4711 {"mfcounta", XSPR(31,339,150), XSPR_MASK, PPC860, PPCNONE, {RT}},
4712 {"mfcountb", XSPR(31,339,151), XSPR_MASK, PPC860, PPCNONE, {RT}},
4713 {"mfcmpe", XSPR(31,339,152), XSPR_MASK, PPC860, PPCNONE, {RT}},
4714 {"mfcmpf", XSPR(31,339,153), XSPR_MASK, PPC860, PPCNONE, {RT}},
4715 {"mfcmpg", XSPR(31,339,154), XSPR_MASK, PPC860, PPCNONE, {RT}},
4716 {"mfcmph", XSPR(31,339,155), XSPR_MASK, PPC860, PPCNONE, {RT}},
4717 {"mflctrl1", XSPR(31,339,156), XSPR_MASK, PPC860, PPCNONE, {RT}},
4718 {"mflctrl2", XSPR(31,339,157), XSPR_MASK, PPC860, PPCNONE, {RT}},
4719 {"mfictrl", XSPR(31,339,158), XSPR_MASK, PPC860, PPCNONE, {RT}},
4720 {"mfbar", XSPR(31,339,159), XSPR_MASK, PPC860, PPCNONE, {RT}},
4721 {"mfvrsave", XSPR(31,339,256), XSPR_MASK, PPCVEC, PPCNONE, {RT}},
4722 {"mfusprg0", XSPR(31,339,256), XSPR_MASK, BOOKE|PPCVLE, PPCNONE, {RT}},
4723 {"mfsprg", XSPR(31,339,256), XSPRG_MASK, PPC|PPCVLE, PPCNONE, {RT, SPRG}},
4724 {"mfsprg4", XSPR(31,339,260), XSPR_MASK, PPC405|BOOKE|PPCVLE, PPCNONE, {RT}},
4725 {"mfsprg5", XSPR(31,339,261), XSPR_MASK, PPC405|BOOKE|PPCVLE, PPCNONE, {RT}},
4726 {"mfsprg6", XSPR(31,339,262), XSPR_MASK, PPC405|BOOKE|PPCVLE, PPCNONE, {RT}},
4727 {"mfsprg7", XSPR(31,339,263), XSPR_MASK, PPC405|BOOKE|PPCVLE, PPCNONE, {RT}},
4728 {"mftb", XSPR(31,339,268), XSPR_MASK, BOOKE|PPCVLE, PPCNONE, {RT}},
4729 {"mftbl", XSPR(31,339,268), XSPR_MASK, BOOKE|PPCVLE, PPCNONE, {RT}},
4730 {"mftbu", XSPR(31,339,269), XSPR_MASK, BOOKE|PPCVLE, PPCNONE, {RT}},
4731 {"mfsprg0", XSPR(31,339,272), XSPR_MASK, PPC|PPCVLE, PPCNONE, {RT}},
4732 {"mfsprg1", XSPR(31,339,273), XSPR_MASK, PPC|PPCVLE, PPCNONE, {RT}},
4733 {"mfsprg2", XSPR(31,339,274), XSPR_MASK, PPC|PPCVLE, PPCNONE, {RT}},
4734 {"mfsprg3", XSPR(31,339,275), XSPR_MASK, PPC|PPCVLE, PPCNONE, {RT}},
4735 {"mfasr", XSPR(31,339,280), XSPR_MASK, PPC64, PPCNONE, {RT}},
4736 {"mfear", XSPR(31,339,282), XSPR_MASK, PPC, TITAN, {RT}},
4737 {"mfpir", XSPR(31,339,286), XSPR_MASK, BOOKE|PPCVLE, PPCNONE, {RT}},
4738 {"mfpvr", XSPR(31,339,287), XSPR_MASK, PPC|PPCVLE, PPCNONE, {RT}},
4739 {"mfdbsr", XSPR(31,339,304), XSPR_MASK, BOOKE|PPCVLE, PPCNONE, {RT}},
4740 {"mfdbcr0", XSPR(31,339,308), XSPR_MASK, BOOKE|PPCVLE, PPCNONE, {RT}},
4741 {"mfdbcr1", XSPR(31,339,309), XSPR_MASK, BOOKE|PPCVLE, PPCNONE, {RT}},
4742 {"mfdbcr2", XSPR(31,339,310), XSPR_MASK, BOOKE|PPCVLE, PPCNONE, {RT}},
4743 {"mfiac1", XSPR(31,339,312), XSPR_MASK, BOOKE|PPCVLE, PPCNONE, {RT}},
4744 {"mfiac2", XSPR(31,339,313), XSPR_MASK, BOOKE|PPCVLE, PPCNONE, {RT}},
4745 {"mfiac3", XSPR(31,339,314), XSPR_MASK, BOOKE|PPCVLE, PPCNONE, {RT}},
4746 {"mfiac4", XSPR(31,339,315), XSPR_MASK, BOOKE|PPCVLE, PPCNONE, {RT}},
4747 {"mfdac1", XSPR(31,339,316), XSPR_MASK, BOOKE|PPCVLE, PPCNONE, {RT}},
4748 {"mfdac2", XSPR(31,339,317), XSPR_MASK, BOOKE|PPCVLE, PPCNONE, {RT}},
4749 {"mfdvc1", XSPR(31,339,318), XSPR_MASK, BOOKE|PPCVLE, PPCNONE, {RT}},
4750 {"mfdvc2", XSPR(31,339,319), XSPR_MASK, BOOKE|PPCVLE, PPCNONE, {RT}},
4751 {"mftsr", XSPR(31,339,336), XSPR_MASK, BOOKE|PPCVLE, PPCNONE, {RT}},
4752 {"mftcr", XSPR(31,339,340), XSPR_MASK, BOOKE|PPCVLE, PPCNONE, {RT}},
4753 {"mfivor0", XSPR(31,339,400), XSPR_MASK, BOOKE|PPCVLE, PPCNONE, {RT}},
4754 {"mfivor1", XSPR(31,339,401), XSPR_MASK, BOOKE|PPCVLE, PPCNONE, {RT}},
4755 {"mfivor2", XSPR(31,339,402), XSPR_MASK, BOOKE|PPCVLE, PPCNONE, {RT}},
4756 {"mfivor3", XSPR(31,339,403), XSPR_MASK, BOOKE|PPCVLE, PPCNONE, {RT}},
4757 {"mfivor4", XSPR(31,339,404), XSPR_MASK, BOOKE|PPCVLE, PPCNONE, {RT}},
4758 {"mfivor5", XSPR(31,339,405), XSPR_MASK, BOOKE|PPCVLE, PPCNONE, {RT}},
4759 {"mfivor6", XSPR(31,339,406), XSPR_MASK, BOOKE|PPCVLE, PPCNONE, {RT}},
4760 {"mfivor7", XSPR(31,339,407), XSPR_MASK, BOOKE|PPCVLE, PPCNONE, {RT}},
4761 {"mfivor8", XSPR(31,339,408), XSPR_MASK, BOOKE|PPCVLE, PPCNONE, {RT}},
4762 {"mfivor9", XSPR(31,339,409), XSPR_MASK, BOOKE|PPCVLE, PPCNONE, {RT}},
4763 {"mfivor10", XSPR(31,339,410), XSPR_MASK, BOOKE|PPCVLE, PPCNONE, {RT}},
4764 {"mfivor11", XSPR(31,339,411), XSPR_MASK, BOOKE|PPCVLE, PPCNONE, {RT}},
4765 {"mfivor12", XSPR(31,339,412), XSPR_MASK, BOOKE|PPCVLE, PPCNONE, {RT}},
4766 {"mfivor13", XSPR(31,339,413), XSPR_MASK, BOOKE|PPCVLE, PPCNONE, {RT}},
4767 {"mfivor14", XSPR(31,339,414), XSPR_MASK, BOOKE|PPCVLE, PPCNONE, {RT}},
4768 {"mfivor15", XSPR(31,339,415), XSPR_MASK, BOOKE|PPCVLE, PPCNONE, {RT}},
4769 {"mfspefscr", XSPR(31,339,512), XSPR_MASK, PPCSPE, PPCNONE, {RT}},
4770 {"mfbbear", XSPR(31,339,513), XSPR_MASK, PPCBRLK, PPCNONE, {RT}},
4771 {"mfbbtar", XSPR(31,339,514), XSPR_MASK, PPCBRLK, PPCNONE, {RT}},
4772 {"mfivor32", XSPR(31,339,528), XSPR_MASK, PPCSPE, PPCNONE, {RT}},
4773 {"mfibatu", XSPR(31,339,528), XSPRBAT_MASK, PPC, TITAN, {RT, SPRBAT}},
4774 {"mfivor33", XSPR(31,339,529), XSPR_MASK, PPCSPE, PPCNONE, {RT}},
4775 {"mfibatl", XSPR(31,339,529), XSPRBAT_MASK, PPC, TITAN, {RT, SPRBAT}},
4776 {"mfivor34", XSPR(31,339,530), XSPR_MASK, PPCSPE, PPCNONE, {RT}},
4777 {"mfivor35", XSPR(31,339,531), XSPR_MASK, PPCPMR, PPCNONE, {RT}},
4778 {"mfdbatu", XSPR(31,339,536), XSPRBAT_MASK, PPC, TITAN, {RT, SPRBAT}},
4779 {"mfdbatl", XSPR(31,339,537), XSPRBAT_MASK, PPC, TITAN, {RT, SPRBAT}},
4780 {"mfic_cst", XSPR(31,339,560), XSPR_MASK, PPC860, PPCNONE, {RT}},
4781 {"mfic_adr", XSPR(31,339,561), XSPR_MASK, PPC860, PPCNONE, {RT}},
4782 {"mfic_dat", XSPR(31,339,562), XSPR_MASK, PPC860, PPCNONE, {RT}},
4783 {"mfdc_cst", XSPR(31,339,568), XSPR_MASK, PPC860, PPCNONE, {RT}},
4784 {"mfdc_adr", XSPR(31,339,569), XSPR_MASK, PPC860, PPCNONE, {RT}},
4785 {"mfdc_dat", XSPR(31,339,570), XSPR_MASK, PPC860, PPCNONE, {RT}},
4786 {"mfmcsrr0", XSPR(31,339,570), XSPR_MASK, PPCRFMCI, PPCNONE, {RT}},
4787 {"mfmcsrr1", XSPR(31,339,571), XSPR_MASK, PPCRFMCI, PPCNONE, {RT}},
4788 {"mfmcsr", XSPR(31,339,572), XSPR_MASK, PPCRFMCI, PPCNONE, {RT}},
4789 {"mfmcar", XSPR(31,339,573), XSPR_MASK, PPCRFMCI, TITAN, {RT}},
4790 {"mfdpdr", XSPR(31,339,630), XSPR_MASK, PPC860, PPCNONE, {RT}},
4791 {"mfdpir", XSPR(31,339,631), XSPR_MASK, PPC860, PPCNONE, {RT}},
4792 {"mfimmr", XSPR(31,339,638), XSPR_MASK, PPC860, PPCNONE, {RT}},
4793 {"mfmi_ctr", XSPR(31,339,784), XSPR_MASK, PPC860, PPCNONE, {RT}},
4794 {"mfmi_ap", XSPR(31,339,786), XSPR_MASK, PPC860, PPCNONE, {RT}},
4795 {"mfmi_epn", XSPR(31,339,787), XSPR_MASK, PPC860, PPCNONE, {RT}},
4796 {"mfmi_twc", XSPR(31,339,789), XSPR_MASK, PPC860, PPCNONE, {RT}},
4797 {"mfmi_rpn", XSPR(31,339,790), XSPR_MASK, PPC860, PPCNONE, {RT}},
4798 {"mfmd_ctr", XSPR(31,339,792), XSPR_MASK, PPC860, PPCNONE, {RT}},
4799 {"mfm_casid", XSPR(31,339,793), XSPR_MASK, PPC860, PPCNONE, {RT}},
4800 {"mfmd_ap", XSPR(31,339,794), XSPR_MASK, PPC860, PPCNONE, {RT}},
4801 {"mfmd_epn", XSPR(31,339,795), XSPR_MASK, PPC860, PPCNONE, {RT}},
4802 {"mfmd_twb", XSPR(31,339,796), XSPR_MASK, PPC860, PPCNONE, {RT}},
4803 {"mfmd_twc", XSPR(31,339,797), XSPR_MASK, PPC860, PPCNONE, {RT}},
4804 {"mfmd_rpn", XSPR(31,339,798), XSPR_MASK, PPC860, PPCNONE, {RT}},
4805 {"mfm_tw", XSPR(31,339,799), XSPR_MASK, PPC860, PPCNONE, {RT}},
4806 {"mfmi_dbcam", XSPR(31,339,816), XSPR_MASK, PPC860, PPCNONE, {RT}},
4807 {"mfmi_dbram0", XSPR(31,339,817), XSPR_MASK, PPC860, PPCNONE, {RT}},
4808 {"mfmi_dbram1", XSPR(31,339,818), XSPR_MASK, PPC860, PPCNONE, {RT}},
4809 {"mfmd_dbcam", XSPR(31,339,824), XSPR_MASK, PPC860, PPCNONE, {RT}},
4810 {"mfmd_dbram0", XSPR(31,339,825), XSPR_MASK, PPC860, PPCNONE, {RT}},
4811 {"mfmd_dbram1", XSPR(31,339,826), XSPR_MASK, PPC860, PPCNONE, {RT}},
4812 {"mfivndx", XSPR(31,339,880), XSPR_MASK, TITAN, PPCNONE, {RT}},
4813 {"mfdvndx", XSPR(31,339,881), XSPR_MASK, TITAN, PPCNONE, {RT}},
4814 {"mfivlim", XSPR(31,339,882), XSPR_MASK, TITAN, PPCNONE, {RT}},
4815 {"mfdvlim", XSPR(31,339,883), XSPR_MASK, TITAN, PPCNONE, {RT}},
4816 {"mfclcsr", XSPR(31,339,884), XSPR_MASK, TITAN, PPCNONE, {RT}},
4817 {"mfccr1", XSPR(31,339,888), XSPR_MASK, TITAN, PPCNONE, {RT}},
4818 {"mfrstcfg", XSPR(31,339,923), XSPR_MASK, TITAN, PPCNONE, {RT}},
4819 {"mfdcdbtrl", XSPR(31,339,924), XSPR_MASK, TITAN, PPCNONE, {RT}},
4820 {"mfdcdbtrh", XSPR(31,339,925), XSPR_MASK, TITAN, PPCNONE, {RT}},
4821 {"mficdbtr", XSPR(31,339,927), XSPR_MASK, TITAN, PPCNONE, {RT}},
4822 {"mfummcr0", XSPR(31,339,936), XSPR_MASK, PPC750, PPCNONE, {RT}},
4823 {"mfupmc1", XSPR(31,339,937), XSPR_MASK, PPC750, PPCNONE, {RT}},
4824 {"mfupmc2", XSPR(31,339,938), XSPR_MASK, PPC750, PPCNONE, {RT}},
4825 {"mfusia", XSPR(31,339,939), XSPR_MASK, PPC750, PPCNONE, {RT}},
4826 {"mfummcr1", XSPR(31,339,940), XSPR_MASK, PPC750, PPCNONE, {RT}},
4827 {"mfupmc3", XSPR(31,339,941), XSPR_MASK, PPC750, PPCNONE, {RT}},
4828 {"mfupmc4", XSPR(31,339,942), XSPR_MASK, PPC750, PPCNONE, {RT}},
4829 {"mfzpr", XSPR(31,339,944), XSPR_MASK, PPC403, PPCNONE, {RT}},
4830 {"mfpid", XSPR(31,339,945), XSPR_MASK, PPC403, PPCNONE, {RT}},
4831 {"mfmmucr", XSPR(31,339,946), XSPR_MASK, TITAN, PPCNONE, {RT}},
4832 {"mfccr0", XSPR(31,339,947), XSPR_MASK, PPC405|TITAN, PPCNONE, {RT}},
4833 {"mfiac3", XSPR(31,339,948), XSPR_MASK, PPC405, PPCNONE, {RT}},
4834 {"mfiac4", XSPR(31,339,949), XSPR_MASK, PPC405, PPCNONE, {RT}},
4835 {"mfdvc1", XSPR(31,339,950), XSPR_MASK, PPC405, PPCNONE, {RT}},
4836 {"mfdvc2", XSPR(31,339,951), XSPR_MASK, PPC405, PPCNONE, {RT}},
4837 {"mfmmcr0", XSPR(31,339,952), XSPR_MASK, PPC750, PPCNONE, {RT}},
4838 {"mfpmc1", XSPR(31,339,953), XSPR_MASK, PPC750, PPCNONE, {RT}},
4839 {"mfsgr", XSPR(31,339,953), XSPR_MASK, PPC403, PPCNONE, {RT}},
4840 {"mfdcwr", XSPR(31,339,954), XSPR_MASK, PPC403, PPCNONE, {RT}},
4841 {"mfpmc2", XSPR(31,339,954), XSPR_MASK, PPC750, PPCNONE, {RT}},
4842 {"mfsia", XSPR(31,339,955), XSPR_MASK, PPC750, PPCNONE, {RT}},
4843 {"mfsler", XSPR(31,339,955), XSPR_MASK, PPC405, PPCNONE, {RT}},
4844 {"mfmmcr1", XSPR(31,339,956), XSPR_MASK, PPC750, PPCNONE, {RT}},
4845 {"mfsu0r", XSPR(31,339,956), XSPR_MASK, PPC405, PPCNONE, {RT}},
4846 {"mfdbcr1", XSPR(31,339,957), XSPR_MASK, PPC405, PPCNONE, {RT}},
4847 {"mfpmc3", XSPR(31,339,957), XSPR_MASK, PPC750, PPCNONE, {RT}},
4848 {"mfpmc4", XSPR(31,339,958), XSPR_MASK, PPC750, PPCNONE, {RT}},
4849 {"mficdbdr", XSPR(31,339,979), XSPR_MASK, PPC403|TITAN, PPCNONE, {RT}},
4850 {"mfesr", XSPR(31,339,980), XSPR_MASK, PPC403, PPCNONE, {RT}},
4851 {"mfdear", XSPR(31,339,981), XSPR_MASK, PPC403, PPCNONE, {RT}},
4852 {"mfevpr", XSPR(31,339,982), XSPR_MASK, PPC403, PPCNONE, {RT}},
4853 {"mfcdbcr", XSPR(31,339,983), XSPR_MASK, PPC403, PPCNONE, {RT}},
4854 {"mftsr", XSPR(31,339,984), XSPR_MASK, PPC403, PPCNONE, {RT}},
4855 {"mftcr", XSPR(31,339,986), XSPR_MASK, PPC403, PPCNONE, {RT}},
4856 {"mfpit", XSPR(31,339,987), XSPR_MASK, PPC403, PPCNONE, {RT}},
4857 {"mftbhi", XSPR(31,339,988), XSPR_MASK, PPC403, PPCNONE, {RT}},
4858 {"mftblo", XSPR(31,339,989), XSPR_MASK, PPC403, PPCNONE, {RT}},
4859 {"mfsrr2", XSPR(31,339,990), XSPR_MASK, PPC403, PPCNONE, {RT}},
4860 {"mfsrr3", XSPR(31,339,991), XSPR_MASK, PPC403, PPCNONE, {RT}},
4861 {"mfdbsr", XSPR(31,339,1008), XSPR_MASK, PPC403, PPCNONE, {RT}},
4862 {"mfdbcr0", XSPR(31,339,1010), XSPR_MASK, PPC405, PPCNONE, {RT}},
4863 {"mfdbdr", XSPR(31,339,1011), XSPR_MASK, TITAN, PPCNONE, {RS}},
4864 {"mfiac1", XSPR(31,339,1012), XSPR_MASK, PPC403, PPCNONE, {RT}},
4865 {"mfiac2", XSPR(31,339,1013), XSPR_MASK, PPC403, PPCNONE, {RT}},
4866 {"mfdac1", XSPR(31,339,1014), XSPR_MASK, PPC403, PPCNONE, {RT}},
4867 {"mfdac2", XSPR(31,339,1015), XSPR_MASK, PPC403, PPCNONE, {RT}},
4868 {"mfl2cr", XSPR(31,339,1017), XSPR_MASK, PPC750, PPCNONE, {RT}},
4869 {"mfdccr", XSPR(31,339,1018), XSPR_MASK, PPC403, PPCNONE, {RT}},
4870 {"mficcr", XSPR(31,339,1019), XSPR_MASK, PPC403, PPCNONE, {RT}},
4871 {"mfictc", XSPR(31,339,1019), XSPR_MASK, PPC750, PPCNONE, {RT}},
4872 {"mfpbl1", XSPR(31,339,1020), XSPR_MASK, PPC403, PPCNONE, {RT}},
4873 {"mfthrm1", XSPR(31,339,1020), XSPR_MASK, PPC750, PPCNONE, {RT}},
4874 {"mfpbu1", XSPR(31,339,1021), XSPR_MASK, PPC403, PPCNONE, {RT}},
4875 {"mfthrm2", XSPR(31,339,1021), XSPR_MASK, PPC750, PPCNONE, {RT}},
4876 {"mfpbl2", XSPR(31,339,1022), XSPR_MASK, PPC403, PPCNONE, {RT}},
4877 {"mfthrm3", XSPR(31,339,1022), XSPR_MASK, PPC750, PPCNONE, {RT}},
4878 {"mfpbu2", XSPR(31,339,1023), XSPR_MASK, PPC403, PPCNONE, {RT}},
4879 {"mfspr", X(31,339), X_MASK, COM|PPCVLE, PPCNONE, {RT, SPR}},
4880
4881 {"lwax", X(31,341), X_MASK, PPC64|PPCVLE, PPCNONE, {RT, RA0, RB}},
4882
4883 {"dst", XDSS(31,342,0), XDSS_MASK, PPCVEC, PPCNONE, {RA, RB, STRM}},
4884
4885 {"lhax", X(31,343), X_MASK, COM|PPCVLE, PPCNONE, {RT, RA0, RB}},
4886
4887 {"lvxl", X(31,359), X_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, RA0, RB}},
4888
4889 {"abs", XO(31,360,0,0), XORB_MASK, M601, PPCNONE, {RT, RA}},
4890 {"abs.", XO(31,360,0,1), XORB_MASK, M601, PPCNONE, {RT, RA}},
4891
4892 {"divs", XO(31,363,0,0), XO_MASK, M601, PPCNONE, {RT, RA, RB}},
4893 {"divs.", XO(31,363,0,1), XO_MASK, M601, PPCNONE, {RT, RA, RB}},
4894
4895 {"tlbia", X(31,370), 0xffffffff, PPC, TITAN, {0}},
4896
4897 {"mftbl", XSPR(31,371,268), XSPR_MASK, PPC, NO371, {RT}},
4898 {"mftbu", XSPR(31,371,269), XSPR_MASK, PPC, NO371, {RT}},
4899 {"mftb", X(31,371), X_MASK, PPC|PPCA2, NO371|POWER7, {RT, TBR}},
4900
4901 {"lwaux", X(31,373), X_MASK, PPC64|PPCVLE, PPCNONE, {RT, RAL, RB}},
4902
4903 {"dstst", XDSS(31,374,0), XDSS_MASK, PPCVEC, PPCNONE, {RA, RB, STRM}},
4904
4905 {"lhaux", X(31,375), X_MASK, COM|PPCVLE, PPCNONE, {RT, RAL, RB}},
4906
4907 {"popcntw", X(31,378), XRB_MASK, POWER7|PPCA2, PPCNONE, {RA, RS}},
4908
4909 {"mtdcrx", X(31,387), X_MASK, BOOKE|PPCA2|PPC476|PPCVLE, TITAN, {RA, RS}},
4910 {"mtdcrx.", XRC(31,387,1), X_MASK, PPCA2, PPCNONE, {RA, RS}},
4911
4912 {"stvexbx", X(31,389), X_MASK, PPCVEC2, PPCNONE, {VS, RA0, RB}},
4913
4914 {"dcblc", X(31,390), X_MASK, PPCCHLK|PPC476|TITAN|PPCVLE, PPCNONE, {CT, RA0, RB}},
4915 {"stdfcmx", APU(31,391,0), APU_MASK, PPC405, PPCNONE, {FCRT, RA, RB}},
4916
4917 {"divdeu", XO(31,393,0,0), XO_MASK, POWER7|PPCA2, PPCNONE, {RT, RA, RB}},
4918 {"divdeu.", XO(31,393,0,1), XO_MASK, POWER7|PPCA2, PPCNONE, {RT, RA, RB}},
4919 {"divweu", XO(31,395,0,0), XO_MASK, POWER7|PPCA2, PPCNONE, {RT, RA, RB}},
4920 {"divweu.", XO(31,395,0,1), XO_MASK, POWER7|PPCA2, PPCNONE, {RT, RA, RB}},
4921
4922 {"dcblce", X(31,398), X_MASK, PPCCHLK, E500MC, {CT, RA, RB}},
4923
4924 {"slbmte", X(31,402), XRA_MASK, PPC64, PPCNONE, {RS, RB}},
4925
4926 {"icswx", XRC(31,406,0), X_MASK, POWER7|PPCA2, PPCNONE, {RS, RA, RB}},
4927 {"icswx.", XRC(31,406,1), X_MASK, POWER7|PPCA2, PPCNONE, {RS, RA, RB}},
4928
4929 {"sthx", X(31,407), X_MASK, COM|PPCVLE, PPCNONE, {RS, RA0, RB}},
4930
4931 {"orc", XRC(31,412,0), X_MASK, COM|PPCVLE, PPCNONE, {RA, RS, RB}},
4932 {"orc.", XRC(31,412,1), X_MASK, COM|PPCVLE, PPCNONE, {RA, RS, RB}},
4933
4934 {"sthepx", X(31,415), X_MASK, E500MC|PPCA2|PPCVLE, PPCNONE, {RS, RA0, RB}},
4935
4936 {"mtdcrux", X(31,419), X_MASK, PPC464|PPCVLE, PPCNONE, {RA, RS}},
4937
4938 {"stvexhx", X(31,421), X_MASK, PPCVEC2, PPCNONE, {VS, RA0, RB}},
4939
4940 {"dcblq.", XRC(31,422,1), X_MASK, E6500, PPCNONE, {CT, RA0, RB}},
4941
4942 {"divde", XO(31,425,0,0), XO_MASK, POWER7|PPCA2, PPCNONE, {RT, RA, RB}},
4943 {"divde.", XO(31,425,0,1), XO_MASK, POWER7|PPCA2, PPCNONE, {RT, RA, RB}},
4944 {"divwe", XO(31,427,0,0), XO_MASK, POWER7|PPCA2, PPCNONE, {RT, RA, RB}},
4945 {"divwe.", XO(31,427,0,1), XO_MASK, POWER7|PPCA2, PPCNONE, {RT, RA, RB}},
4946
4947 {"slbie", X(31,434), XRTRA_MASK, PPC64, PPCNONE, {RB}},
4948
4949 {"ecowx", X(31,438), X_MASK, PPC, TITAN, {RT, RA0, RB}},
4950
4951 {"sthux", X(31,439), X_MASK, COM|PPCVLE, PPCNONE, {RS, RAS, RB}},
4952
4953 {"mdors", 0x7f9ce378, 0xffffffff, E500MC, PPCNONE, {0}},
4954
4955 {"miso", 0x7f5ad378, 0xffffffff, E6500, PPCNONE, {0}},
4956
4957 /* The "yield", "mdoio" and "mdoom" instructions are extended mnemonics for
4958 "or rX,rX,rX", with rX being r27, r29 and r30 respectively. */
4959 {"yield", 0x7f7bdb78, 0xffffffff, POWER7, PPCNONE, {0}},
4960 {"mdoio", 0x7fbdeb78, 0xffffffff, POWER7, PPCNONE, {0}},
4961 {"mdoom", 0x7fdef378, 0xffffffff, POWER7, PPCNONE, {0}},
4962 {"mr", XRC(31,444,0), X_MASK, COM|PPCVLE, PPCNONE, {RA, RS, RBS}},
4963 {"or", XRC(31,444,0), X_MASK, COM|PPCVLE, PPCNONE, {RA, RS, RB}},
4964 {"mr.", XRC(31,444,1), X_MASK, COM|PPCVLE, PPCNONE, {RA, RS, RBS}},
4965 {"or.", XRC(31,444,1), X_MASK, COM|PPCVLE, PPCNONE, {RA, RS, RB}},
4966
4967 {"mtexisr", XSPR(31,451, 64), XSPR_MASK, PPC403, PPCNONE, {RS}},
4968 {"mtexier", XSPR(31,451, 66), XSPR_MASK, PPC403, PPCNONE, {RS}},
4969 {"mtbr0", XSPR(31,451,128), XSPR_MASK, PPC403, PPCNONE, {RS}},
4970 {"mtbr1", XSPR(31,451,129), XSPR_MASK, PPC403, PPCNONE, {RS}},
4971 {"mtbr2", XSPR(31,451,130), XSPR_MASK, PPC403, PPCNONE, {RS}},
4972 {"mtbr3", XSPR(31,451,131), XSPR_MASK, PPC403, PPCNONE, {RS}},
4973 {"mtbr4", XSPR(31,451,132), XSPR_MASK, PPC403, PPCNONE, {RS}},
4974 {"mtbr5", XSPR(31,451,133), XSPR_MASK, PPC403, PPCNONE, {RS}},
4975 {"mtbr6", XSPR(31,451,134), XSPR_MASK, PPC403, PPCNONE, {RS}},
4976 {"mtbr7", XSPR(31,451,135), XSPR_MASK, PPC403, PPCNONE, {RS}},
4977 {"mtbear", XSPR(31,451,144), XSPR_MASK, PPC403, PPCNONE, {RS}},
4978 {"mtbesr", XSPR(31,451,145), XSPR_MASK, PPC403, PPCNONE, {RS}},
4979 {"mtiocr", XSPR(31,451,160), XSPR_MASK, PPC403, PPCNONE, {RS}},
4980 {"mtdmacr0", XSPR(31,451,192), XSPR_MASK, PPC403, PPCNONE, {RS}},
4981 {"mtdmact0", XSPR(31,451,193), XSPR_MASK, PPC403, PPCNONE, {RS}},
4982 {"mtdmada0", XSPR(31,451,194), XSPR_MASK, PPC403, PPCNONE, {RS}},
4983 {"mtdmasa0", XSPR(31,451,195), XSPR_MASK, PPC403, PPCNONE, {RS}},
4984 {"mtdmacc0", XSPR(31,451,196), XSPR_MASK, PPC403, PPCNONE, {RS}},
4985 {"mtdmacr1", XSPR(31,451,200), XSPR_MASK, PPC403, PPCNONE, {RS}},
4986 {"mtdmact1", XSPR(31,451,201), XSPR_MASK, PPC403, PPCNONE, {RS}},
4987 {"mtdmada1", XSPR(31,451,202), XSPR_MASK, PPC403, PPCNONE, {RS}},
4988 {"mtdmasa1", XSPR(31,451,203), XSPR_MASK, PPC403, PPCNONE, {RS}},
4989 {"mtdmacc1", XSPR(31,451,204), XSPR_MASK, PPC403, PPCNONE, {RS}},
4990 {"mtdmacr2", XSPR(31,451,208), XSPR_MASK, PPC403, PPCNONE, {RS}},
4991 {"mtdmact2", XSPR(31,451,209), XSPR_MASK, PPC403, PPCNONE, {RS}},
4992 {"mtdmada2", XSPR(31,451,210), XSPR_MASK, PPC403, PPCNONE, {RS}},
4993 {"mtdmasa2", XSPR(31,451,211), XSPR_MASK, PPC403, PPCNONE, {RS}},
4994 {"mtdmacc2", XSPR(31,451,212), XSPR_MASK, PPC403, PPCNONE, {RS}},
4995 {"mtdmacr3", XSPR(31,451,216), XSPR_MASK, PPC403, PPCNONE, {RS}},
4996 {"mtdmact3", XSPR(31,451,217), XSPR_MASK, PPC403, PPCNONE, {RS}},
4997 {"mtdmada3", XSPR(31,451,218), XSPR_MASK, PPC403, PPCNONE, {RS}},
4998 {"mtdmasa3", XSPR(31,451,219), XSPR_MASK, PPC403, PPCNONE, {RS}},
4999 {"mtdmacc3", XSPR(31,451,220), XSPR_MASK, PPC403, PPCNONE, {RS}},
5000 {"mtdmasr", XSPR(31,451,224), XSPR_MASK, PPC403, PPCNONE, {RS}},
5001 {"mtdcr", X(31,451), X_MASK, PPC403|BOOKE|PPCA2|PPC476|PPCVLE, TITAN, {SPR, RS}},
5002 {"mtdcr.", XRC(31,451,1), X_MASK, PPCA2, PPCNONE, {SPR, RS}},
5003
5004 {"stvexwx", X(31,453), X_MASK, PPCVEC2, PPCNONE, {VS, RA0, RB}},
5005
5006 {"dccci", X(31,454), XRT_MASK, PPC403|PPC440|TITAN|PPCA2, PPCNONE, {RAOPT, RBOPT}},
5007 {"dci", X(31,454), XRARB_MASK, PPCA2|PPC476|PPCVLE, PPCNONE, {CT}},
5008
5009 {"divdu", XO(31,457,0,0), XO_MASK, PPC64|PPCVLE, PPCNONE, {RT, RA, RB}},
5010 {"divdu.", XO(31,457,0,1), XO_MASK, PPC64|PPCVLE, PPCNONE, {RT, RA, RB}},
5011
5012 {"divwu", XO(31,459,0,0), XO_MASK, PPC|PPCVLE, PPCNONE, {RT, RA, RB}},
5013 {"divwu.", XO(31,459,0,1), XO_MASK, PPC|PPCVLE, PPCNONE, {RT, RA, RB}},
5014
5015 {"mtpmr", X(31,462), X_MASK, PPCPMR|PPCE300|PPCVLE, PPCNONE, {PMR, RS}},
5016 {"mttmr", X(31,494), X_MASK, PPCTMR|E6500, PPCNONE, {TMR, RS}},
5017
5018 {"mtmq", XSPR(31,467, 0), XSPR_MASK, M601, PPCNONE, {RS}},
5019 {"mtxer", XSPR(31,467, 1), XSPR_MASK, COM|PPCVLE, PPCNONE, {RS}},
5020 {"mtlr", XSPR(31,467, 8), XSPR_MASK, COM|PPCVLE, PPCNONE, {RS}},
5021 {"mtctr", XSPR(31,467, 9), XSPR_MASK, COM|PPCVLE, PPCNONE, {RS}},
5022 {"mttid", XSPR(31,467, 17), XSPR_MASK, POWER, PPCNONE, {RS}},
5023 {"mtdsisr", XSPR(31,467, 18), XSPR_MASK, COM, TITAN, {RS}},
5024 {"mtdar", XSPR(31,467, 19), XSPR_MASK, COM, TITAN, {RS}},
5025 {"mtrtcu", XSPR(31,467, 20), XSPR_MASK, COM, TITAN, {RS}},
5026 {"mtrtcl", XSPR(31,467, 21), XSPR_MASK, COM, TITAN, {RS}},
5027 {"mtdec", XSPR(31,467, 22), XSPR_MASK, COM, PPCNONE, {RS}},
5028 {"mtsdr0", XSPR(31,467, 24), XSPR_MASK, POWER, PPCNONE, {RS}},
5029 {"mtsdr1", XSPR(31,467, 25), XSPR_MASK, COM, TITAN, {RS}},
5030 {"mtsrr0", XSPR(31,467, 26), XSPR_MASK, COM|PPCVLE, PPCNONE, {RS}},
5031 {"mtsrr1", XSPR(31,467, 27), XSPR_MASK, COM|PPCVLE, PPCNONE, {RS}},
5032 {"mtcfar", XSPR(31,467, 28), XSPR_MASK, POWER6, PPCNONE, {RS}},
5033 {"mtpid", XSPR(31,467, 48), XSPR_MASK, BOOKE|PPCVLE, PPCNONE, {RS}},
5034 {"mtdecar", XSPR(31,467, 54), XSPR_MASK, BOOKE|PPCVLE, PPCNONE, {RS}},
5035 {"mtcsrr0", XSPR(31,467, 58), XSPR_MASK, BOOKE|PPCVLE, PPCNONE, {RS}},
5036 {"mtcsrr1", XSPR(31,467, 59), XSPR_MASK, BOOKE|PPCVLE, PPCNONE, {RS}},
5037 {"mtdear", XSPR(31,467, 61), XSPR_MASK, BOOKE|PPCVLE, PPCNONE, {RS}},
5038 {"mtesr", XSPR(31,467, 62), XSPR_MASK, BOOKE|PPCVLE, PPCNONE, {RS}},
5039 {"mtivpr", XSPR(31,467, 63), XSPR_MASK, BOOKE|PPCVLE, PPCNONE, {RS}},
5040 {"mtcmpa", XSPR(31,467,144), XSPR_MASK, PPC860, PPCNONE, {RS}},
5041 {"mtcmpb", XSPR(31,467,145), XSPR_MASK, PPC860, PPCNONE, {RS}},
5042 {"mtcmpc", XSPR(31,467,146), XSPR_MASK, PPC860, PPCNONE, {RS}},
5043 {"mtcmpd", XSPR(31,467,147), XSPR_MASK, PPC860, PPCNONE, {RS}},
5044 {"mticr", XSPR(31,467,148), XSPR_MASK, PPC860, PPCNONE, {RS}},
5045 {"mtder", XSPR(31,467,149), XSPR_MASK, PPC860, PPCNONE, {RS}},
5046 {"mtcounta", XSPR(31,467,150), XSPR_MASK, PPC860, PPCNONE, {RS}},
5047 {"mtcountb", XSPR(31,467,151), XSPR_MASK, PPC860, PPCNONE, {RS}},
5048 {"mtcmpe", XSPR(31,467,152), XSPR_MASK, PPC860, PPCNONE, {RS}},
5049 {"mtcmpf", XSPR(31,467,153), XSPR_MASK, PPC860, PPCNONE, {RS}},
5050 {"mtcmpg", XSPR(31,467,154), XSPR_MASK, PPC860, PPCNONE, {RS}},
5051 {"mtcmph", XSPR(31,467,155), XSPR_MASK, PPC860, PPCNONE, {RS}},
5052 {"mtlctrl1", XSPR(31,467,156), XSPR_MASK, PPC860, PPCNONE, {RS}},
5053 {"mtlctrl2", XSPR(31,467,157), XSPR_MASK, PPC860, PPCNONE, {RS}},
5054 {"mtictrl", XSPR(31,467,158), XSPR_MASK, PPC860, PPCNONE, {RS}},
5055 {"mtbar", XSPR(31,467,159), XSPR_MASK, PPC860, PPCNONE, {RS}},
5056 {"mtvrsave", XSPR(31,467,256), XSPR_MASK, PPCVEC, PPCNONE, {RS}},
5057 {"mtusprg0", XSPR(31,467,256), XSPR_MASK, BOOKE|PPCVLE, PPCNONE, {RS}},
5058 {"mtsprg", XSPR(31,467,256), XSPRG_MASK, PPC|PPCVLE, PPCNONE, {SPRG, RS}},
5059 {"mtsprg0", XSPR(31,467,272), XSPR_MASK, PPC|PPCVLE, PPCNONE, {RS}},
5060 {"mtsprg1", XSPR(31,467,273), XSPR_MASK, PPC|PPCVLE, PPCNONE, {RS}},
5061 {"mtsprg2", XSPR(31,467,274), XSPR_MASK, PPC|PPCVLE, PPCNONE, {RS}},
5062 {"mtsprg3", XSPR(31,467,275), XSPR_MASK, PPC|PPCVLE, PPCNONE, {RS}},
5063 {"mtsprg4", XSPR(31,467,276), XSPR_MASK, PPC405|BOOKE|PPCVLE, PPCNONE, {RS}},
5064 {"mtsprg5", XSPR(31,467,277), XSPR_MASK, PPC405|BOOKE|PPCVLE, PPCNONE, {RS}},
5065 {"mtsprg6", XSPR(31,467,278), XSPR_MASK, PPC405|BOOKE|PPCVLE, PPCNONE, {RS}},
5066 {"mtsprg7", XSPR(31,467,279), XSPR_MASK, PPC405|BOOKE|PPCVLE, PPCNONE, {RS}},
5067 {"mtasr", XSPR(31,467,280), XSPR_MASK, PPC64, PPCNONE, {RS}},
5068 {"mtear", XSPR(31,467,282), XSPR_MASK, PPC, TITAN, {RS}},
5069 {"mttbl", XSPR(31,467,284), XSPR_MASK, PPC, PPCNONE, {RS}},
5070 {"mttbu", XSPR(31,467,285), XSPR_MASK, PPC, PPCNONE, {RS}},
5071 {"mtdbsr", XSPR(31,467,304), XSPR_MASK, BOOKE|PPCVLE, PPCNONE, {RS}},
5072 {"mtdbcr0", XSPR(31,467,308), XSPR_MASK, BOOKE|PPCVLE, PPCNONE, {RS}},
5073 {"mtdbcr1", XSPR(31,467,309), XSPR_MASK, BOOKE|PPCVLE, PPCNONE, {RS}},
5074 {"mtdbcr2", XSPR(31,467,310), XSPR_MASK, BOOKE|PPCVLE, PPCNONE, {RS}},
5075 {"mtiac1", XSPR(31,467,312), XSPR_MASK, BOOKE|PPCVLE, PPCNONE, {RS}},
5076 {"mtiac2", XSPR(31,467,313), XSPR_MASK, BOOKE|PPCVLE, PPCNONE, {RS}},
5077 {"mtiac3", XSPR(31,467,314), XSPR_MASK, BOOKE|PPCVLE, PPCNONE, {RS}},
5078 {"mtiac4", XSPR(31,467,315), XSPR_MASK, BOOKE|PPCVLE, PPCNONE, {RS}},
5079 {"mtdac1", XSPR(31,467,316), XSPR_MASK, BOOKE|PPCVLE, PPCNONE, {RS}},
5080 {"mtdac2", XSPR(31,467,317), XSPR_MASK, BOOKE|PPCVLE, PPCNONE, {RS}},
5081 {"mtdvc1", XSPR(31,467,318), XSPR_MASK, BOOKE|PPCVLE, PPCNONE, {RS}},
5082 {"mtdvc2", XSPR(31,467,319), XSPR_MASK, BOOKE|PPCVLE, PPCNONE, {RS}},
5083 {"mttsr", XSPR(31,467,336), XSPR_MASK, BOOKE|PPCVLE, PPCNONE, {RS}},
5084 {"mttcr", XSPR(31,467,340), XSPR_MASK, BOOKE|PPCVLE, PPCNONE, {RS}},
5085 {"mtivor0", XSPR(31,467,400), XSPR_MASK, BOOKE|PPCVLE, PPCNONE, {RS}},
5086 {"mtivor1", XSPR(31,467,401), XSPR_MASK, BOOKE|PPCVLE, PPCNONE, {RS}},
5087 {"mtivor2", XSPR(31,467,402), XSPR_MASK, BOOKE|PPCVLE, PPCNONE, {RS}},
5088 {"mtivor3", XSPR(31,467,403), XSPR_MASK, BOOKE|PPCVLE, PPCNONE, {RS}},
5089 {"mtivor4", XSPR(31,467,404), XSPR_MASK, BOOKE|PPCVLE, PPCNONE, {RS}},
5090 {"mtivor5", XSPR(31,467,405), XSPR_MASK, BOOKE|PPCVLE, PPCNONE, {RS}},
5091 {"mtivor6", XSPR(31,467,406), XSPR_MASK, BOOKE|PPCVLE, PPCNONE, {RS}},
5092 {"mtivor7", XSPR(31,467,407), XSPR_MASK, BOOKE|PPCVLE, PPCNONE, {RS}},
5093 {"mtivor8", XSPR(31,467,408), XSPR_MASK, BOOKE|PPCVLE, PPCNONE, {RS}},
5094 {"mtivor9", XSPR(31,467,409), XSPR_MASK, BOOKE|PPCVLE, PPCNONE, {RS}},
5095 {"mtivor10", XSPR(31,467,410), XSPR_MASK, BOOKE|PPCVLE, PPCNONE, {RS}},
5096 {"mtivor11", XSPR(31,467,411), XSPR_MASK, BOOKE|PPCVLE, PPCNONE, {RS}},
5097 {"mtivor12", XSPR(31,467,412), XSPR_MASK, BOOKE|PPCVLE, PPCNONE, {RS}},
5098 {"mtivor13", XSPR(31,467,413), XSPR_MASK, BOOKE|PPCVLE, PPCNONE, {RS}},
5099 {"mtivor14", XSPR(31,467,414), XSPR_MASK, BOOKE|PPCVLE, PPCNONE, {RS}},
5100 {"mtivor15", XSPR(31,467,415), XSPR_MASK, BOOKE|PPCVLE, PPCNONE, {RS}},
5101 {"mtspefscr", XSPR(31,467,512), XSPR_MASK, PPCSPE, PPCNONE, {RS}},
5102 {"mtbbear", XSPR(31,467,513), XSPR_MASK, PPCBRLK, PPCNONE, {RS}},
5103 {"mtbbtar", XSPR(31,467,514), XSPR_MASK, PPCBRLK, PPCNONE, {RS}},
5104 {"mtivor32", XSPR(31,467,528), XSPR_MASK, PPCSPE, PPCNONE, {RS}},
5105 {"mtibatu", XSPR(31,467,528), XSPRBAT_MASK, PPC, TITAN, {SPRBAT, RS}},
5106 {"mtivor33", XSPR(31,467,529), XSPR_MASK, PPCSPE, PPCNONE, {RS}},
5107 {"mtibatl", XSPR(31,467,529), XSPRBAT_MASK, PPC, TITAN, {SPRBAT, RS}},
5108 {"mtivor34", XSPR(31,467,530), XSPR_MASK, PPCSPE, PPCNONE, {RS}},
5109 {"mtivor35", XSPR(31,467,531), XSPR_MASK, PPCPMR, PPCNONE, {RS}},
5110 {"mtdbatu", XSPR(31,467,536), XSPRBAT_MASK, PPC, TITAN, {SPRBAT, RS}},
5111 {"mtdbatl", XSPR(31,467,537), XSPRBAT_MASK, PPC, TITAN, {SPRBAT, RS}},
5112 {"mtmcsrr0", XSPR(31,467,570), XSPR_MASK, PPCRFMCI|PPCVLE, PPCNONE, {RS}},
5113 {"mtmcsrr1", XSPR(31,467,571), XSPR_MASK, PPCRFMCI|PPCVLE, PPCNONE, {RS}},
5114 {"mtmcsr", XSPR(31,467,572), XSPR_MASK, PPCRFMCI, PPCNONE, {RS}},
5115 {"mtivndx", XSPR(31,467,880), XSPR_MASK, TITAN, PPCNONE, {RS}},
5116 {"mtdvndx", XSPR(31,467,881), XSPR_MASK, TITAN, PPCNONE, {RS}},
5117 {"mtivlim", XSPR(31,467,882), XSPR_MASK, TITAN, PPCNONE, {RS}},
5118 {"mtdvlim", XSPR(31,467,883), XSPR_MASK, TITAN, PPCNONE, {RS}},
5119 {"mtclcsr", XSPR(31,467,884), XSPR_MASK, TITAN, PPCNONE, {RS}},
5120 {"mtccr1", XSPR(31,467,888), XSPR_MASK, TITAN, PPCNONE, {RS}},
5121 {"mtummcr0", XSPR(31,467,936), XSPR_MASK, PPC750, PPCNONE, {RS}},
5122 {"mtupmc1", XSPR(31,467,937), XSPR_MASK, PPC750, PPCNONE, {RS}},
5123 {"mtupmc2", XSPR(31,467,938), XSPR_MASK, PPC750, PPCNONE, {RS}},
5124 {"mtusia", XSPR(31,467,939), XSPR_MASK, PPC750, PPCNONE, {RS}},
5125 {"mtummcr1", XSPR(31,467,940), XSPR_MASK, PPC750, PPCNONE, {RS}},
5126 {"mtupmc3", XSPR(31,467,941), XSPR_MASK, PPC750, PPCNONE, {RS}},
5127 {"mtupmc4", XSPR(31,467,942), XSPR_MASK, PPC750, PPCNONE, {RS}},
5128 {"mtzpr", XSPR(31,467,944), XSPR_MASK, PPC403, PPCNONE, {RS}},
5129 {"mtpid", XSPR(31,467,945), XSPR_MASK, PPC403, PPCNONE, {RS}},
5130 {"mtrmmucr", XSPR(31,467,946), XSPR_MASK, TITAN, PPCNONE, {RS}},
5131 {"mtccr0", XSPR(31,467,947), XSPR_MASK, PPC405|TITAN, PPCNONE, {RS}},
5132 {"mtiac3", XSPR(31,467,948), XSPR_MASK, PPC405, PPCNONE, {RS}},
5133 {"mtiac4", XSPR(31,467,949), XSPR_MASK, PPC405, PPCNONE, {RS}},
5134 {"mtdvc1", XSPR(31,467,950), XSPR_MASK, PPC405, PPCNONE, {RS}},
5135 {"mtdvc2", XSPR(31,467,951), XSPR_MASK, PPC405, PPCNONE, {RS}},
5136 {"mtmmcr0", XSPR(31,467,952), XSPR_MASK, PPC750, PPCNONE, {RS}},
5137 {"mtpmc1", XSPR(31,467,953), XSPR_MASK, PPC750, PPCNONE, {RS}},
5138 {"mtsgr", XSPR(31,467,953), XSPR_MASK, PPC403, PPCNONE, {RS}},
5139 {"mtdcwr", XSPR(31,467,954), XSPR_MASK, PPC403, PPCNONE, {RS}},
5140 {"mtpmc2", XSPR(31,467,954), XSPR_MASK, PPC750, PPCNONE, {RS}},
5141 {"mtsia", XSPR(31,467,955), XSPR_MASK, PPC750, PPCNONE, {RS}},
5142 {"mtsler", XSPR(31,467,955), XSPR_MASK, PPC405, PPCNONE, {RS}},
5143 {"mtmmcr1", XSPR(31,467,956), XSPR_MASK, PPC750, PPCNONE, {RS}},
5144 {"mtsu0r", XSPR(31,467,956), XSPR_MASK, PPC405, PPCNONE, {RS}},
5145 {"mtdbcr1", XSPR(31,467,957), XSPR_MASK, PPC405, PPCNONE, {RS}},
5146 {"mtpmc3", XSPR(31,467,957), XSPR_MASK, PPC750, PPCNONE, {RS}},
5147 {"mtpmc4", XSPR(31,467,958), XSPR_MASK, PPC750, PPCNONE, {RS}},
5148 {"mticdbdr", XSPR(31,467,979), XSPR_MASK, PPC403, PPCNONE, {RS}},
5149 {"mtesr", XSPR(31,467,980), XSPR_MASK, PPC403, PPCNONE, {RS}},
5150 {"mtdear", XSPR(31,467,981), XSPR_MASK, PPC403, PPCNONE, {RS}},
5151 {"mtevpr", XSPR(31,467,982), XSPR_MASK, PPC403, PPCNONE, {RS}},
5152 {"mtcdbcr", XSPR(31,467,983), XSPR_MASK, PPC403, PPCNONE, {RS}},
5153 {"mttsr", XSPR(31,467,984), XSPR_MASK, PPC403, PPCNONE, {RS}},
5154 {"mttcr", XSPR(31,467,986), XSPR_MASK, PPC403, PPCNONE, {RS}},
5155 {"mtpit", XSPR(31,467,987), XSPR_MASK, PPC403, PPCNONE, {RS}},
5156 {"mttbhi", XSPR(31,467,988), XSPR_MASK, PPC403, PPCNONE, {RS}},
5157 {"mttblo", XSPR(31,467,989), XSPR_MASK, PPC403, PPCNONE, {RS}},
5158 {"mtsrr2", XSPR(31,467,990), XSPR_MASK, PPC403, PPCNONE, {RS}},
5159 {"mtsrr3", XSPR(31,467,991), XSPR_MASK, PPC403, PPCNONE, {RS}},
5160 {"mtdbsr", XSPR(31,467,1008), XSPR_MASK, PPC403, PPCNONE, {RS}},
5161 {"mtdbdr", XSPR(31,467,1011), XSPR_MASK, TITAN, PPCNONE, {RS}},
5162 {"mtdbcr0", XSPR(31,467,1010), XSPR_MASK, PPC405, PPCNONE, {RS}},
5163 {"mtiac1", XSPR(31,467,1012), XSPR_MASK, PPC403, PPCNONE, {RS}},
5164 {"mtiac2", XSPR(31,467,1013), XSPR_MASK, PPC403, PPCNONE, {RS}},
5165 {"mtdac1", XSPR(31,467,1014), XSPR_MASK, PPC403, PPCNONE, {RS}},
5166 {"mtdac2", XSPR(31,467,1015), XSPR_MASK, PPC403, PPCNONE, {RS}},
5167 {"mtl2cr", XSPR(31,467,1017), XSPR_MASK, PPC750, PPCNONE, {RS}},
5168 {"mtdccr", XSPR(31,467,1018), XSPR_MASK, PPC403, PPCNONE, {RS}},
5169 {"mticcr", XSPR(31,467,1019), XSPR_MASK, PPC403, PPCNONE, {RS}},
5170 {"mtictc", XSPR(31,467,1019), XSPR_MASK, PPC750, PPCNONE, {RS}},
5171 {"mtpbl1", XSPR(31,467,1020), XSPR_MASK, PPC403, PPCNONE, {RS}},
5172 {"mtthrm1", XSPR(31,467,1020), XSPR_MASK, PPC750, PPCNONE, {RS}},
5173 {"mtpbu1", XSPR(31,467,1021), XSPR_MASK, PPC403, PPCNONE, {RS}},
5174 {"mtthrm2", XSPR(31,467,1021), XSPR_MASK, PPC750, PPCNONE, {RS}},
5175 {"mtpbl2", XSPR(31,467,1022), XSPR_MASK, PPC403, PPCNONE, {RS}},
5176 {"mtthrm3", XSPR(31,467,1022), XSPR_MASK, PPC750, PPCNONE, {RS}},
5177 {"mtpbu2", XSPR(31,467,1023), XSPR_MASK, PPC403, PPCNONE, {RS}},
5178 {"mtspr", X(31,467), X_MASK, COM|PPCVLE, PPCNONE, {SPR, RS}},
5179
5180 {"dcbi", X(31,470), XRT_MASK, PPC|PPCVLE, PPCNONE, {RA0, RB}},
5181
5182 {"nand", XRC(31,476,0), X_MASK, COM|PPCVLE, PPCNONE, {RA, RS, RB}},
5183 {"nand.", XRC(31,476,1), X_MASK, COM|PPCVLE, PPCNONE, {RA, RS, RB}},
5184
5185 {"dsn", X(31,483), XRT_MASK, E500MC|PPCVLE, PPCNONE, {RA, RB}},
5186
5187 {"dcread", X(31,486), X_MASK, PPC403|PPC440|PPCVLE, PPCA2|PPC476, {RT, RA0, RB}},
5188
5189 {"icbtls", X(31,486), X_MASK, PPCCHLK|PPC476|TITAN|PPCVLE, PPCNONE, {CT, RA0, RB}},
5190
5191 {"stvxl", X(31,487), X_MASK, PPCVEC|PPCVLE, PPCNONE, {VS, RA0, RB}},
5192
5193 {"nabs", XO(31,488,0,0), XORB_MASK, M601, PPCNONE, {RT, RA}},
5194 {"nabs.", XO(31,488,0,1), XORB_MASK, M601, PPCNONE, {RT, RA}},
5195
5196 {"divd", XO(31,489,0,0), XO_MASK, PPC64|PPCVLE, PPCNONE, {RT, RA, RB}},
5197 {"divd.", XO(31,489,0,1), XO_MASK, PPC64|PPCVLE, PPCNONE, {RT, RA, RB}},
5198
5199 {"divw", XO(31,491,0,0), XO_MASK, PPC|PPCVLE, PPCNONE, {RT, RA, RB}},
5200 {"divw.", XO(31,491,0,1), XO_MASK, PPC|PPCVLE, PPCNONE, {RT, RA, RB}},
5201
5202 {"icbtlse", X(31,494), X_MASK, PPCCHLK, E500MC, {CT, RA, RB}},
5203
5204 {"slbia", X(31,498), 0xffffffff, PPC64, PPCNONE, {0}},
5205
5206 {"cli", X(31,502), XRB_MASK, POWER, PPCNONE, {RT, RA}},
5207
5208 {"popcntd", X(31,506), XRB_MASK, POWER7|PPCA2, PPCNONE, {RA, RS}},
5209
5210 {"cmpb", X(31,508), X_MASK, POWER6|PPCA2|PPC476, PPCNONE, {RA, RS, RB}},
5211
5212 {"mcrxr", X(31,512), XRARB_MASK|(3<<21), COM|PPCVLE, POWER7, {BF}},
5213
5214 {"lbdx", X(31,515), X_MASK, E500MC|PPCVLE, PPCNONE, {RT, RA, RB}},
5215
5216 {"bblels", X(31,518), X_MASK, PPCBRLK, PPCNONE, {0}},
5217
5218 {"lvlx", X(31,519), X_MASK, CELL, PPCNONE, {VD, RA0, RB}},
5219 {"lbfcmux", APU(31,519,0), APU_MASK, PPC405, PPCNONE, {FCRT, RA, RB}},
5220
5221 {"subfco", XO(31,8,1,0), XO_MASK, PPCCOM|PPCVLE, PPCNONE, {RT, RA, RB}},
5222 {"sfo", XO(31,8,1,0), XO_MASK, PWRCOM, PPCNONE, {RT, RA, RB}},
5223 {"subco", XO(31,8,1,0), XO_MASK, PPCCOM|PPCVLE, PPCNONE, {RT, RB, RA}},
5224 {"subfco.", XO(31,8,1,1), XO_MASK, PPCCOM|PPCVLE, PPCNONE, {RT, RA, RB}},
5225 {"sfo.", XO(31,8,1,1), XO_MASK, PWRCOM, PPCNONE, {RT, RA, RB}},
5226 {"subco.", XO(31,8,1,1), XO_MASK, PPCCOM|PPCVLE, PPCNONE, {RT, RB, RA}},
5227
5228 {"addco", XO(31,10,1,0), XO_MASK, PPCCOM|PPCVLE, PPCNONE, {RT, RA, RB}},
5229 {"ao", XO(31,10,1,0), XO_MASK, PWRCOM, PPCNONE, {RT, RA, RB}},
5230 {"addco.", XO(31,10,1,1), XO_MASK, PPCCOM|PPCVLE, PPCNONE, {RT, RA, RB}},
5231 {"ao.", XO(31,10,1,1), XO_MASK, PWRCOM, PPCNONE, {RT, RA, RB}},
5232
5233 {"clcs", X(31,531), XRB_MASK, M601, PPCNONE, {RT, RA}},
5234
5235 {"ldbrx", X(31,532), X_MASK, CELL|POWER7|PPCA2, PPCNONE, {RT, RA0, RB}},
5236
5237 {"lswx", X(31,533), X_MASK, PPCCOM|PPCVLE, E500|E500MC, {RT, RAX, RBX}},
5238 {"lsx", X(31,533), X_MASK, PWRCOM, PPCNONE, {RT, RA, RB}},
5239
5240 {"lwbrx", X(31,534), X_MASK, PPCCOM|PPCVLE, PPCNONE, {RT, RA0, RB}},
5241 {"lbrx", X(31,534), X_MASK, PWRCOM, PPCNONE, {RT, RA, RB}},
5242
5243 {"lfsx", X(31,535), X_MASK, COM, PPCEFS, {FRT, RA0, RB}},
5244
5245 {"srw", XRC(31,536,0), X_MASK, PPCCOM|PPCVLE, PPCNONE, {RA, RS, RB}},
5246 {"sr", XRC(31,536,0), X_MASK, PWRCOM, PPCNONE, {RA, RS, RB}},
5247 {"srw.", XRC(31,536,1), X_MASK, PPCCOM|PPCVLE, PPCNONE, {RA, RS, RB}},
5248 {"sr.", XRC(31,536,1), X_MASK, PWRCOM, PPCNONE, {RA, RS, RB}},
5249
5250 {"rrib", XRC(31,537,0), X_MASK, M601, PPCNONE, {RA, RS, RB}},
5251 {"rrib.", XRC(31,537,1), X_MASK, M601, PPCNONE, {RA, RS, RB}},
5252
5253 {"srd", XRC(31,539,0), X_MASK, PPC64, PPCNONE, {RA, RS, RB}},
5254 {"srd.", XRC(31,539,1), X_MASK, PPC64, PPCNONE, {RA, RS, RB}},
5255
5256 {"maskir", XRC(31,541,0), X_MASK, M601, PPCNONE, {RA, RS, RB}},
5257 {"maskir.", XRC(31,541,1), X_MASK, M601, PPCNONE, {RA, RS, RB}},
5258
5259 {"lhdx", X(31,547), X_MASK, E500MC|PPCVLE, PPCNONE, {RT, RA, RB}},
5260
5261 {"lvtrx", X(31,549), X_MASK, PPCVEC2, PPCNONE, {VD, RA0, RB}},
5262
5263 {"bbelr", X(31,550), X_MASK, PPCBRLK, PPCNONE, {0}},
5264
5265 {"lvrx", X(31,551), X_MASK, CELL, PPCNONE, {VD, RA0, RB}},
5266 {"lhfcmux", APU(31,551,0), APU_MASK, PPC405, PPCNONE, {FCRT, RA, RB}},
5267
5268 {"subfo", XO(31,40,1,0), XO_MASK, PPC, PPCNONE, {RT, RA, RB}},
5269 {"subo", XO(31,40,1,0), XO_MASK, PPC, PPCNONE, {RT, RB, RA}},
5270 {"subfo.", XO(31,40,1,1), XO_MASK, PPC, PPCNONE, {RT, RA, RB}},
5271 {"subo.", XO(31,40,1,1), XO_MASK, PPC, PPCNONE, {RT, RB, RA}},
5272
5273 {"tlbsync", X(31,566), 0xffffffff, PPC|PPCVLE, PPCNONE, {0}},
5274
5275 {"lfsux", X(31,567), X_MASK, COM, PPCEFS, {FRT, RAS, RB}},
5276
5277 {"lwdx", X(31,579), X_MASK, E500MC|PPCVLE, PPCNONE, {RT, RA, RB}},
5278
5279 {"lvtlx", X(31,581), X_MASK, PPCVEC2, PPCNONE, {VD, RA0, RB}},
5280
5281 {"lwfcmux", APU(31,583,0), APU_MASK, PPC405, PPCNONE, {FCRT, RA, RB}},
5282
5283 {"lxsdx", X(31,588), XX1_MASK, PPCVSX, PPCNONE, {XT6, RA0, RB}},
5284
5285 {"mfsr", X(31,595), XRB_MASK|(1<<20), COM, NON32, {RT, SR}},
5286
5287 {"lswi", X(31,597), X_MASK, PPCCOM|PPCVLE, E500|E500MC, {RT, RAX, NBI}},
5288 {"lsi", X(31,597), X_MASK, PWRCOM, PPCNONE, {RT, RA0, NB}},
5289
5290 {"lwsync", XSYNC(31,598,1), 0xffffffff, PPC, E500, {0}},
5291 {"ptesync", XSYNC(31,598,2), 0xffffffff, PPC64, PPCNONE, {0}},
5292 {"sync", X(31,598), XSYNCLE_MASK,E6500, PPCNONE, {LS, ESYNC}},
5293 {"sync", X(31,598), XSYNC_MASK, PPCCOM|PPCVLE, BOOKE|PPC476, {LS}},
5294 {"msync", X(31,598), 0xffffffff, BOOKE|PPCA2|PPC476, PPCNONE, {0}},
5295 {"sync", X(31,598), 0xffffffff, BOOKE|PPC476, E6500, {0}},
5296 {"lwsync", X(31,598), 0xffffffff, E500, PPCNONE, {0}},
5297 {"dcs", X(31,598), 0xffffffff, PWRCOM, PPCNONE, {0}},
5298
5299 {"lfdx", X(31,599), X_MASK, COM, PPCEFS, {FRT, RA0, RB}},
5300
5301 {"mffgpr", XRC(31,607,0), XRA_MASK, POWER6, POWER7, {FRT, RB}},
5302 {"lfdepx", X(31,607), X_MASK, E500MC|PPCA2|PPCVLE, PPCNONE, {FRT, RA0, RB}},
5303
5304 {"lddx", X(31,611), X_MASK, E500MC|PPCVLE, PPCNONE, {RT, RA, RB}},
5305
5306 {"lvswx", X(31,613), X_MASK, PPCVEC2, PPCNONE, {VD, RA0, RB}},
5307
5308 {"lqfcmux", APU(31,615,0), APU_MASK, PPC405, PPCNONE, {FCRT, RA, RB}},
5309
5310 {"nego", XO(31,104,1,0), XORB_MASK, COM|PPCVLE, PPCNONE, {RT, RA}},
5311 {"nego.", XO(31,104,1,1), XORB_MASK, COM|PPCVLE, PPCNONE, {RT, RA}},
5312
5313 {"mulo", XO(31,107,1,0), XO_MASK, M601, PPCNONE, {RT, RA, RB}},
5314 {"mulo.", XO(31,107,1,1), XO_MASK, M601, PPCNONE, {RT, RA, RB}},
5315
5316 {"mfsri", X(31,627), X_MASK, M601, PPCNONE, {RT, RA, RB}},
5317
5318 {"dclst", X(31,630), XRB_MASK, M601, PPCNONE, {RS, RA}},
5319
5320 {"lfdux", X(31,631), X_MASK, COM, PPCEFS, {FRT, RAS, RB}},
5321
5322 {"stbdx", X(31,643), X_MASK, E500MC, PPCNONE, {RS, RA, RB}},
5323
5324 {"stvlx", X(31,647), X_MASK, CELL, PPCNONE, {VS, RA0, RB}},
5325 {"stbfcmux", APU(31,647,0), APU_MASK, PPC405, PPCNONE, {FCRT, RA, RB}},
5326
5327 {"subfeo", XO(31,136,1,0), XO_MASK, PPCCOM|PPCVLE, PPCNONE, {RT, RA, RB}},
5328 {"sfeo", XO(31,136,1,0), XO_MASK, PWRCOM, PPCNONE, {RT, RA, RB}},
5329 {"subfeo.", XO(31,136,1,1), XO_MASK, PPCCOM|PPCVLE, PPCNONE, {RT, RA, RB}},
5330 {"sfeo.", XO(31,136,1,1), XO_MASK, PWRCOM, PPCNONE, {RT, RA, RB}},
5331
5332 {"addeo", XO(31,138,1,0), XO_MASK, PPCCOM|PPCVLE, PPCNONE, {RT, RA, RB}},
5333 {"aeo", XO(31,138,1,0), XO_MASK, PWRCOM, PPCNONE, {RT, RA, RB}},
5334 {"addeo.", XO(31,138,1,1), XO_MASK, PPCCOM|PPCVLE, PPCNONE, {RT, RA, RB}},
5335 {"aeo.", XO(31,138,1,1), XO_MASK, PWRCOM, PPCNONE, {RT, RA, RB}},
5336
5337 {"mfsrin", X(31,659), XRA_MASK, PPC, NON32, {RT, RB}},
5338
5339 {"stdbrx", X(31,660), X_MASK, CELL|POWER7|PPCA2, PPCNONE, {RS, RA0, RB}},
5340
5341 {"stswx", X(31,661), X_MASK, PPCCOM|PPCVLE, E500|E500MC, {RS, RA0, RB}},
5342 {"stsx", X(31,661), X_MASK, PWRCOM, PPCNONE, {RS, RA0, RB}},
5343
5344 {"stwbrx", X(31,662), X_MASK, PPCCOM|PPCVLE, PPCNONE, {RS, RA0, RB}},
5345 {"stbrx", X(31,662), X_MASK, PWRCOM, PPCNONE, {RS, RA0, RB}},
5346
5347 {"stfsx", X(31,663), X_MASK, COM, PPCEFS, {FRS, RA0, RB}},
5348
5349 {"srq", XRC(31,664,0), X_MASK, M601, PPCNONE, {RA, RS, RB}},
5350 {"srq.", XRC(31,664,1), X_MASK, M601, PPCNONE, {RA, RS, RB}},
5351
5352 {"sre", XRC(31,665,0), X_MASK, M601, PPCNONE, {RA, RS, RB}},
5353 {"sre.", XRC(31,665,1), X_MASK, M601, PPCNONE, {RA, RS, RB}},
5354
5355 {"sthdx", X(31,675), X_MASK, E500MC, PPCNONE, {RS, RA, RB}},
5356
5357 {"stvfrx", X(31,677), X_MASK, PPCVEC2, PPCNONE, {VS, RA0, RB}},
5358
5359 {"stvrx", X(31,679), X_MASK, CELL, PPCNONE, {VS, RA0, RB}},
5360 {"sthfcmux", APU(31,679,0), APU_MASK, PPC405, PPCNONE, {FCRT, RA, RB}},
5361
5362 {"stbcx.", XRC(31,694,1), X_MASK, POWER7, PPCNONE, {RS, RA0, RB}},
5363
5364 {"stfsux", X(31,695), X_MASK, COM, PPCEFS, {FRS, RAS, RB}},
5365
5366 {"sriq", XRC(31,696,0), X_MASK, M601, PPCNONE, {RA, RS, SH}},
5367 {"sriq.", XRC(31,696,1), X_MASK, M601, PPCNONE, {RA, RS, SH}},
5368
5369 {"stwdx", X(31,707), X_MASK, E500MC, PPCNONE, {RS, RA, RB}},
5370
5371 {"stvflx", X(31,709), X_MASK, PPCVEC2, PPCNONE, {VS, RA0, RB}},
5372
5373 {"stwfcmux", APU(31,711,0), APU_MASK, PPC405, PPCNONE, {FCRT, RA, RB}},
5374
5375 {"stxsdx", X(31,716), XX1_MASK, PPCVSX, PPCNONE, {XS6, RA0, RB}},
5376
5377 {"subfzeo", XO(31,200,1,0), XORB_MASK, PPCCOM|PPCVLE, PPCNONE, {RT, RA}},
5378 {"sfzeo", XO(31,200,1,0), XORB_MASK, PWRCOM, PPCNONE, {RT, RA}},
5379 {"subfzeo.", XO(31,200,1,1), XORB_MASK, PPCCOM|PPCVLE, PPCNONE, {RT, RA}},
5380 {"sfzeo.", XO(31,200,1,1), XORB_MASK, PWRCOM, PPCNONE, {RT, RA}},
5381
5382 {"addzeo", XO(31,202,1,0), XORB_MASK, PPCCOM|PPCVLE, PPCNONE, {RT, RA}},
5383 {"azeo", XO(31,202,1,0), XORB_MASK, PWRCOM, PPCNONE, {RT, RA}},
5384 {"addzeo.", XO(31,202,1,1), XORB_MASK, PPCCOM|PPCVLE, PPCNONE, {RT, RA}},
5385 {"azeo.", XO(31,202,1,1), XORB_MASK, PWRCOM, PPCNONE, {RT, RA}},
5386
5387 {"stswi", X(31,725), X_MASK, PPCCOM|PPCVLE, E500|E500MC, {RS, RA0, NB}},
5388 {"stsi", X(31,725), X_MASK, PWRCOM, PPCNONE, {RS, RA0, NB}},
5389
5390 {"sthcx.", XRC(31,726,1), X_MASK, POWER7, PPCNONE, {RS, RA0, RB}},
5391
5392 {"stfdx", X(31,727), X_MASK, COM, PPCEFS, {FRS, RA0, RB}},
5393
5394 {"srlq", XRC(31,728,0), X_MASK, M601, PPCNONE, {RA, RS, RB}},
5395 {"srlq.", XRC(31,728,1), X_MASK, M601, PPCNONE, {RA, RS, RB}},
5396
5397 {"sreq", XRC(31,729,0), X_MASK, M601, PPCNONE, {RA, RS, RB}},
5398 {"sreq.", XRC(31,729,1), X_MASK, M601, PPCNONE, {RA, RS, RB}},
5399
5400 {"mftgpr", XRC(31,735,0), XRA_MASK, POWER6, POWER7, {RT, FRB}},
5401 {"stfdepx", X(31,735), X_MASK, E500MC|PPCA2|PPCVLE, PPCNONE, {FRS, RA0, RB}},
5402
5403 {"stddx", X(31,739), X_MASK, E500MC, PPCNONE, {RS, RA, RB}},
5404
5405 {"stvswx", X(31,741), X_MASK, PPCVEC2, PPCNONE, {VS, RA0, RB}},
5406
5407 {"stqfcmux", APU(31,743,0), APU_MASK, PPC405, PPCNONE, {FCRT, RA, RB}},
5408
5409 {"subfmeo", XO(31,232,1,0), XORB_MASK, PPCCOM, PPCNONE, {RT, RA}},
5410 {"sfmeo", XO(31,232,1,0), XORB_MASK, PWRCOM, PPCNONE, {RT, RA}},
5411 {"subfmeo.", XO(31,232,1,1), XORB_MASK, PPCCOM, PPCNONE, {RT, RA}},
5412 {"sfmeo.", XO(31,232,1,1), XORB_MASK, PWRCOM, PPCNONE, {RT, RA}},
5413
5414 {"mulldo", XO(31,233,1,0), XO_MASK, PPC64|PPCVLE, PPCNONE, {RT, RA, RB}},
5415 {"mulldo.", XO(31,233,1,1), XO_MASK, PPC64|PPCVLE, PPCNONE, {RT, RA, RB}},
5416
5417 {"addmeo", XO(31,234,1,0), XORB_MASK, PPCCOM|PPCVLE, PPCNONE, {RT, RA}},
5418 {"ameo", XO(31,234,1,0), XORB_MASK, PWRCOM, PPCNONE, {RT, RA}},
5419 {"addmeo.", XO(31,234,1,1), XORB_MASK, PPCCOM|PPCVLE, PPCNONE, {RT, RA}},
5420 {"ameo.", XO(31,234,1,1), XORB_MASK, PWRCOM, PPCNONE, {RT, RA}},
5421
5422 {"mullwo", XO(31,235,1,0), XO_MASK, PPCCOM|PPCVLE, PPCNONE, {RT, RA, RB}},
5423 {"mulso", XO(31,235,1,0), XO_MASK, PWRCOM, PPCNONE, {RT, RA, RB}},
5424 {"mullwo.", XO(31,235,1,1), XO_MASK, PPCCOM|PPCVLE, PPCNONE, {RT, RA, RB}},
5425 {"mulso.", XO(31,235,1,1), XO_MASK, PWRCOM, PPCNONE, {RT, RA, RB}},
5426
5427 {"dcba", X(31,758), XRT_MASK, PPC405|PPC7450|BOOKE|PPCA2|PPC476|PPCVLE, PPCNONE, {RA0, RB}},
5428 {"dcbal", XOPL(31,758,1), XRT_MASK, E500MC, PPCNONE, {RA0, RB}},
5429
5430 {"stfdux", X(31,759), X_MASK, COM, PPCEFS, {FRS, RAS, RB}},
5431
5432 {"srliq", XRC(31,760,0), X_MASK, M601, PPCNONE, {RA, RS, SH}},
5433 {"srliq.", XRC(31,760,1), X_MASK, M601, PPCNONE, {RA, RS, SH}},
5434
5435 {"lvsm", X(31,773), X_MASK, PPCVEC2, PPCNONE, {VD, RA0, RB}},
5436 {"stvepxl", X(31,775), X_MASK, PPCVEC2, PPCNONE, {VS, RA0, RB}},
5437 {"lvlxl", X(31,775), X_MASK, CELL, PPCNONE, {VD, RA0, RB}},
5438 {"ldfcmux", APU(31,775,0), APU_MASK, PPC405, PPCNONE, {FCRT, RA, RB}},
5439
5440 {"dozo", XO(31,264,1,0), XO_MASK, M601, PPCNONE, {RT, RA, RB}},
5441 {"dozo.", XO(31,264,1,1), XO_MASK, M601, PPCNONE, {RT, RA, RB}},
5442
5443 {"addo", XO(31,266,1,0), XO_MASK, PPCCOM|PPCVLE, PPCNONE, {RT, RA, RB}},
5444 {"caxo", XO(31,266,1,0), XO_MASK, PWRCOM, PPCNONE, {RT, RA, RB}},
5445 {"addo.", XO(31,266,1,1), XO_MASK, PPCCOM|PPCVLE, PPCNONE, {RT, RA, RB}},
5446 {"caxo.", XO(31,266,1,1), XO_MASK, PWRCOM, PPCNONE, {RT, RA, RB}},
5447
5448 {"lxvw4x", X(31,780), XX1_MASK, PPCVSX, PPCNONE, {XT6, RA0, RB}},
5449
5450 {"tlbivax", X(31,786), XRT_MASK, BOOKE|PPCA2|PPC476|PPCVLE, PPCNONE, {RA0, RB}},
5451
5452 {"lwzcix", X(31,789), X_MASK, POWER6, PPCNONE, {RT, RA0, RB}},
5453
5454 {"lhbrx", X(31,790), X_MASK, COM|PPCVLE, PPCNONE, {RT, RA0, RB}},
5455
5456 {"lfdpx", X(31,791), X_MASK, POWER6, POWER7, {FRTp, RA0, RB}},
5457 {"lfqx", X(31,791), X_MASK, POWER2, PPCNONE, {FRT, RA, RB}},
5458
5459 {"sraw", XRC(31,792,0), X_MASK, PPCCOM|PPCVLE, PPCNONE, {RA, RS, RB}},
5460 {"sra", XRC(31,792,0), X_MASK, PWRCOM, PPCNONE, {RA, RS, RB}},
5461 {"sraw.", XRC(31,792,1), X_MASK, PPCCOM|PPCVLE, PPCNONE, {RA, RS, RB}},
5462 {"sra.", XRC(31,792,1), X_MASK, PWRCOM, PPCNONE, {RA, RS, RB}},
5463
5464 {"srad", XRC(31,794,0), X_MASK, PPC64, PPCNONE, {RA, RS, RB}},
5465 {"srad.", XRC(31,794,1), X_MASK, PPC64, PPCNONE, {RA, RS, RB}},
5466
5467 {"lfddx", X(31,803), X_MASK, E500MC|PPCVLE, PPCNONE, {FRT, RA, RB}},
5468
5469 {"lvtrxl", X(31,805), X_MASK, PPCVEC2, PPCNONE, {VD, RA0, RB}},
5470 {"stvepx", X(31,807), X_MASK, PPCVEC2, PPCNONE, {VS, RA0, RB}},
5471 {"lvrxl", X(31,807), X_MASK, CELL, PPCNONE, {VD, RA0, RB}},
5472
5473 {"rac", X(31,818), X_MASK, M601, PPCNONE, {RT, RA, RB}},
5474
5475 {"erativax", X(31,819), X_MASK, PPCA2, PPCNONE, {RS, RA0, RB}},
5476
5477 {"lhzcix", X(31,821), X_MASK, POWER6, PPCNONE, {RT, RA0, RB}},
5478
5479 {"dss", XDSS(31,822,0), XDSS_MASK, PPCVEC, PPCNONE, {STRM}},
5480
5481 {"lfqux", X(31,823), X_MASK, POWER2, PPCNONE, {FRT, RA, RB}},
5482
5483 {"srawi", XRC(31,824,0), X_MASK, PPCCOM|PPCVLE, PPCNONE, {RA, RS, SH}},
5484 {"srai", XRC(31,824,0), X_MASK, PWRCOM, PPCNONE, {RA, RS, SH}},
5485 {"srawi.", XRC(31,824,1), X_MASK, PPCCOM|PPCVLE, PPCNONE, {RA, RS, SH}},
5486 {"srai.", XRC(31,824,1), X_MASK, PWRCOM, PPCNONE, {RA, RS, SH}},
5487
5488 {"sradi", XS(31,413,0), XS_MASK, PPC64|PPCVLE, PPCNONE, {RA, RS, SH6}},
5489 {"sradi.", XS(31,413,1), XS_MASK, PPC64|PPCVLE, PPCNONE, {RA, RS, SH6}},
5490
5491 {"lvtlxl", X(31,837), X_MASK, PPCVEC2, PPCNONE, {VD, RA0, RB}},
5492
5493 {"divo", XO(31,331,1,0), XO_MASK, M601, PPCNONE, {RT, RA, RB}},
5494 {"divo.", XO(31,331,1,1), XO_MASK, M601, PPCNONE, {RT, RA, RB}},
5495
5496 {"lxvd2x", X(31,844), XX1_MASK, PPCVSX, PPCNONE, {XT6, RA0, RB}},
5497
5498 {"tlbsrx.", XRC(31,850,1), XRT_MASK, PPCA2, PPCNONE, {RA0, RB}},
5499
5500 {"slbmfev", X(31,851), XRA_MASK, PPC64, PPCNONE, {RT, RB}},
5501
5502 {"lbzcix", X(31,853), X_MASK, POWER6, PPCNONE, {RT, RA0, RB}},
5503
5504 {"eieio", X(31,854), 0xffffffff, PPC, BOOKE|PPCA2|PPC476, {0}},
5505 {"mbar", X(31,854), X_MASK, BOOKE|PPCA2|PPC476|PPCVLE, PPCNONE, {MO}},
5506 {"eieio", XMBAR(31,854,1),0xffffffff, E500, PPCNONE, {0}},
5507 {"eieio", X(31,854), 0xffffffff, PPCA2|PPC476, PPCNONE, {0}},
5508
5509 {"lfiwax", X(31,855), X_MASK, POWER6|PPCA2|PPC476, PPCNONE, {FRT, RA0, RB}},
5510
5511 {"lvswxl", X(31,869), X_MASK, PPCVEC2, PPCNONE, {VD, RA0, RB}},
5512
5513 {"abso", XO(31,360,1,0), XORB_MASK, M601, PPCNONE, {RT, RA}},
5514 {"abso.", XO(31,360,1,1), XORB_MASK, M601, PPCNONE, {RT, RA}},
5515
5516 {"divso", XO(31,363,1,0), XO_MASK, M601, PPCNONE, {RT, RA, RB}},
5517 {"divso.", XO(31,363,1,1), XO_MASK, M601, PPCNONE, {RT, RA, RB}},
5518
5519 {"ldcix", X(31,885), X_MASK, POWER6, PPCNONE, {RT, RA0, RB}},
5520
5521 {"lfiwzx", X(31,887), X_MASK, POWER7|PPCA2, PPCNONE, {FRT, RA0, RB}},
5522
5523 {"stvlxl", X(31,903), X_MASK, CELL, PPCNONE, {VS, RA0, RB}},
5524 {"stdfcmux", APU(31,903,0), APU_MASK, PPC405, PPCNONE, {FCRT, RA, RB}},
5525
5526 {"divdeuo", XO(31,393,1,0), XO_MASK, POWER7|PPCA2, PPCNONE, {RT, RA, RB}},
5527 {"divdeuo.", XO(31,393,1,1), XO_MASK, POWER7|PPCA2, PPCNONE, {RT, RA, RB}},
5528 {"divweuo", XO(31,395,1,0), XO_MASK, POWER7|PPCA2, PPCNONE, {RT, RA, RB}},
5529 {"divweuo.", XO(31,395,1,1), XO_MASK, POWER7|PPCA2, PPCNONE, {RT, RA, RB}},
5530
5531 {"stxvw4x", X(31,908), XX1_MASK, PPCVSX, PPCNONE, {XS6, RA0, RB}},
5532
5533 {"tlbsx", XRC(31,914,0), X_MASK, PPC403|BOOKE|PPCA2|PPC476, PPCNONE, {RTO, RA0, RB}},
5534 {"tlbsx.", XRC(31,914,1), X_MASK, PPC403|BOOKE|PPCA2|PPC476, PPCNONE, {RTO, RA0, RB}},
5535
5536 {"slbmfee", X(31,915), XRA_MASK, PPC64, PPCNONE, {RT, RB}},
5537
5538 {"stwcix", X(31,917), X_MASK, POWER6, PPCNONE, {RS, RA0, RB}},
5539
5540 {"sthbrx", X(31,918), X_MASK, COM, PPCNONE, {RS, RA0, RB}},
5541
5542 {"stfdpx", X(31,919), X_MASK, POWER6, POWER7, {FRSp, RA0, RB}},
5543 {"stfqx", X(31,919), X_MASK, POWER2, PPCNONE, {FRS, RA0, RB}},
5544
5545 {"sraq", XRC(31,920,0), X_MASK, M601, PPCNONE, {RA, RS, RB}},
5546 {"sraq.", XRC(31,920,1), X_MASK, M601, PPCNONE, {RA, RS, RB}},
5547
5548 {"srea", XRC(31,921,0), X_MASK, M601, PPCNONE, {RA, RS, RB}},
5549 {"srea.", XRC(31,921,1), X_MASK, M601, PPCNONE, {RA, RS, RB}},
5550
5551 {"extsh", XRC(31,922,0), XRB_MASK, PPCCOM|PPCVLE, PPCNONE, {RA, RS}},
5552 {"exts", XRC(31,922,0), XRB_MASK, PWRCOM, PPCNONE, {RA, RS}},
5553 {"extsh.", XRC(31,922,1), XRB_MASK, PPCCOM|PPCVLE, PPCNONE, {RA, RS}},
5554 {"exts.", XRC(31,922,1), XRB_MASK, PWRCOM, PPCNONE, {RA, RS}},
5555
5556 {"stfddx", X(31,931), X_MASK, E500MC, PPCNONE, {FRS, RA, RB}},
5557
5558 {"stvfrxl", X(31,933), X_MASK, PPCVEC2, PPCNONE, {VS, RA0, RB}},
5559
5560 {"wclrone", XOPL2(31,934,2),XRT_MASK, PPCA2, PPCNONE, {RA0, RB}},
5561 {"wclrall", X(31,934), XRARB_MASK, PPCA2, PPCNONE, {L}},
5562 {"wclr", X(31,934), X_MASK, PPCA2, PPCNONE, {L, RA0, RB}},
5563
5564 {"stvrxl", X(31,935), X_MASK, CELL, PPCNONE, {VS, RA0, RB}},
5565
5566 {"divdeo", XO(31,425,1,0), XO_MASK, POWER7|PPCA2, PPCNONE, {RT, RA, RB}},
5567 {"divdeo.", XO(31,425,1,1), XO_MASK, POWER7|PPCA2, PPCNONE, {RT, RA, RB}},
5568 {"divweo", XO(31,427,1,0), XO_MASK, POWER7|PPCA2, PPCNONE, {RT, RA, RB}},
5569 {"divweo.", XO(31,427,1,1), XO_MASK, POWER7|PPCA2, PPCNONE, {RT, RA, RB}},
5570
5571 {"tlbrehi", XTLB(31,946,0), XTLB_MASK, PPC403, PPCA2, {RT, RA}},
5572 {"tlbrelo", XTLB(31,946,1), XTLB_MASK, PPC403, PPCA2, {RT, RA}},
5573 {"tlbre", X(31,946), X_MASK, PPC403|BOOKE|PPCA2|PPC476, PPCNONE, {RSO, RAOPT, SHO}},
5574
5575 {"sthcix", X(31,949), X_MASK, POWER6, PPCNONE, {RS, RA0, RB}},
5576
5577 {"icswepx", XRC(31,950,0), X_MASK, PPCA2, PPCNONE, {RS, RA, RB}},
5578 {"icswepx.", XRC(31,950,1), X_MASK, PPCA2, PPCNONE, {RS, RA, RB}},
5579
5580 {"stfqux", X(31,951), X_MASK, POWER2, PPCNONE, {FRS, RA, RB}},
5581
5582 {"sraiq", XRC(31,952,0), X_MASK, M601, PPCNONE, {RA, RS, SH}},
5583 {"sraiq.", XRC(31,952,1), X_MASK, M601, PPCNONE, {RA, RS, SH}},
5584
5585 {"extsb", XRC(31,954,0), XRB_MASK, PPC|PPCVLE, PPCNONE, {RA, RS}},
5586 {"extsb.", XRC(31,954,1), XRB_MASK, PPC|PPCVLE, PPCNONE, {RA, RS}},
5587
5588 {"stvflxl", X(31,965), X_MASK, PPCVEC2, PPCNONE, {VS, RA0, RB}},
5589
5590 {"iccci", X(31,966), XRT_MASK, PPC403|PPC440|TITAN|PPCA2, PPCNONE, {RAOPT, RBOPT}},
5591 {"ici", X(31,966), XRARB_MASK, PPCA2|PPC476|PPCVLE, PPCNONE, {CT}},
5592
5593 {"divduo", XO(31,457,1,0), XO_MASK, PPC64|PPCVLE, PPCNONE, {RT, RA, RB}},
5594 {"divduo.", XO(31,457,1,1), XO_MASK, PPC64|PPCVLE, PPCNONE, {RT, RA, RB}},
5595
5596 {"divwuo", XO(31,459,1,0), XO_MASK, PPC|PPCVLE, PPCNONE, {RT, RA, RB}},
5597 {"divwuo.", XO(31,459,1,1), XO_MASK, PPC|PPCVLE, PPCNONE, {RT, RA, RB}},
5598
5599 {"stxvd2x", X(31,972), XX1_MASK, PPCVSX, PPCNONE, {XS6, RA0, RB}},
5600
5601 {"tlbld", X(31,978), XRTRA_MASK, PPC, PPC403|BOOKE|PPCA2|PPC476, {RB}},
5602 {"tlbwehi", XTLB(31,978,0), XTLB_MASK, PPC403, PPCNONE, {RT, RA}},
5603 {"tlbwelo", XTLB(31,978,1), XTLB_MASK, PPC403, PPCNONE, {RT, RA}},
5604 {"tlbwe", X(31,978), X_MASK, PPC403|BOOKE|PPCA2|PPC476, PPCNONE, {RSO, RAOPT, SHO}},
5605
5606 {"stbcix", X(31,981), X_MASK, POWER6, PPCNONE, {RS, RA0, RB}},
5607
5608 {"icbi", X(31,982), XRT_MASK, PPC|PPCVLE, PPCNONE, {RA0, RB}},
5609
5610 {"stfiwx", X(31,983), X_MASK, PPC, PPCEFS, {FRS, RA0, RB}},
5611
5612 {"extsw", XRC(31,986,0), XRB_MASK, PPC64|PPCVLE, PPCNONE, {RA, RS}},
5613 {"extsw.", XRC(31,986,1), XRB_MASK, PPC64|PPCVLE, PPCNONE, {RA, RS}},
5614
5615 {"icbiep", XRT(31,991,0), XRT_MASK, E500MC|PPCA2|PPCVLE, PPCNONE, {RA0, RB}},
5616
5617 {"stvswxl", X(31,997), X_MASK, PPCVEC2, PPCNONE, {VS, RA0, RB}},
5618
5619 {"icread", X(31,998), XRT_MASK, PPC403|PPC440|PPC476|TITAN|PPCVLE, PPCNONE, {RA0, RB}},
5620
5621 {"nabso", XO(31,488,1,0), XORB_MASK, M601, PPCNONE, {RT, RA}},
5622 {"nabso.", XO(31,488,1,1), XORB_MASK, M601, PPCNONE, {RT, RA}},
5623
5624 {"divdo", XO(31,489,1,0), XO_MASK, PPC64|PPCVLE, PPCNONE, {RT, RA, RB}},
5625 {"divdo.", XO(31,489,1,1), XO_MASK, PPC64|PPCVLE, PPCNONE, {RT, RA, RB}},
5626
5627 {"divwo", XO(31,491,1,0), XO_MASK, PPC|PPCVLE, PPCNONE, {RT, RA, RB}},
5628 {"divwo.", XO(31,491,1,1), XO_MASK, PPC|PPCVLE, PPCNONE, {RT, RA, RB}},
5629
5630
5631 {"tlbli", X(31,1010), XRTRA_MASK, PPC, TITAN, {RB}},
5632
5633 {"stdcix", X(31,1013), X_MASK, POWER6, PPCNONE, {RS, RA0, RB}},
5634
5635 {"dcbz", X(31,1014), XRT_MASK, PPC|PPCVLE, PPCNONE, {RA0, RB}},
5636 {"dclz", X(31,1014), XRT_MASK, PPC, PPCNONE, {RA0, RB}},
5637
5638 {"dcbzep", XRT(31,1023,0), XRT_MASK, E500MC|PPCA2|PPCVLE, PPCNONE, {RA0, RB}},
5639
5640 {"dcbzl", XOPL(31,1014,1), XRT_MASK, POWER4|E500MC, PPC476, {RA0, RB}},
5641
5642 {"cctpl", 0x7c210b78, 0xffffffff, CELL, PPCNONE, {0}},
5643 {"cctpm", 0x7c421378, 0xffffffff, CELL, PPCNONE, {0}},
5644 {"cctph", 0x7c631b78, 0xffffffff, CELL, PPCNONE, {0}},
5645
5646 {"dstt", XDSS(31,342,1), XDSS_MASK, PPCVEC, PPCNONE, {RA, RB, STRM}},
5647 {"dststt", XDSS(31,374,1), XDSS_MASK, PPCVEC, PPCNONE, {RA, RB, STRM}},
5648 {"dssall", XDSS(31,822,1), XDSS_MASK, PPCVEC, PPCNONE, {0}},
5649
5650 {"db8cyc", 0x7f9ce378, 0xffffffff, CELL, PPCNONE, {0}},
5651 {"db10cyc", 0x7fbdeb78, 0xffffffff, CELL, PPCNONE, {0}},
5652 {"db12cyc", 0x7fdef378, 0xffffffff, CELL, PPCNONE, {0}},
5653 {"db16cyc", 0x7ffffb78, 0xffffffff, CELL, PPCNONE, {0}},
5654
5655 {"lwz", OP(32), OP_MASK, PPCCOM, PPCNONE, {RT, D, RA0}},
5656 {"l", OP(32), OP_MASK, PWRCOM, PPCNONE, {RT, D, RA0}},
5657
5658 {"lwzu", OP(33), OP_MASK, PPCCOM, PPCNONE, {RT, D, RAL}},
5659 {"lu", OP(33), OP_MASK, PWRCOM, PPCNONE, {RT, D, RA0}},
5660
5661 {"lbz", OP(34), OP_MASK, COM, PPCNONE, {RT, D, RA0}},
5662
5663 {"lbzu", OP(35), OP_MASK, COM, PPCNONE, {RT, D, RAL}},
5664
5665 {"stw", OP(36), OP_MASK, PPCCOM, PPCNONE, {RS, D, RA0}},
5666 {"st", OP(36), OP_MASK, PWRCOM, PPCNONE, {RS, D, RA0}},
5667
5668 {"stwu", OP(37), OP_MASK, PPCCOM, PPCNONE, {RS, D, RAS}},
5669 {"stu", OP(37), OP_MASK, PWRCOM, PPCNONE, {RS, D, RA0}},
5670
5671 {"stb", OP(38), OP_MASK, COM, PPCNONE, {RS, D, RA0}},
5672
5673 {"stbu", OP(39), OP_MASK, COM, PPCNONE, {RS, D, RAS}},
5674
5675 {"lhz", OP(40), OP_MASK, COM, PPCNONE, {RT, D, RA0}},
5676
5677 {"lhzu", OP(41), OP_MASK, COM, PPCNONE, {RT, D, RAL}},
5678
5679 {"lha", OP(42), OP_MASK, COM, PPCNONE, {RT, D, RA0}},
5680
5681 {"lhau", OP(43), OP_MASK, COM, PPCNONE, {RT, D, RAL}},
5682
5683 {"sth", OP(44), OP_MASK, COM, PPCNONE, {RS, D, RA0}},
5684
5685 {"sthu", OP(45), OP_MASK, COM, PPCNONE, {RS, D, RAS}},
5686
5687 {"lmw", OP(46), OP_MASK, PPCCOM, PPCNONE, {RT, D, RAM}},
5688 {"lm", OP(46), OP_MASK, PWRCOM, PPCNONE, {RT, D, RA0}},
5689
5690 {"stmw", OP(47), OP_MASK, PPCCOM, PPCNONE, {RS, D, RA0}},
5691 {"stm", OP(47), OP_MASK, PWRCOM, PPCNONE, {RS, D, RA0}},
5692
5693 {"lfs", OP(48), OP_MASK, COM, PPCEFS, {FRT, D, RA0}},
5694
5695 {"lfsu", OP(49), OP_MASK, COM, PPCEFS, {FRT, D, RAS}},
5696
5697 {"lfd", OP(50), OP_MASK, COM, PPCEFS, {FRT, D, RA0}},
5698
5699 {"lfdu", OP(51), OP_MASK, COM, PPCEFS, {FRT, D, RAS}},
5700
5701 {"stfs", OP(52), OP_MASK, COM, PPCEFS, {FRS, D, RA0}},
5702
5703 {"stfsu", OP(53), OP_MASK, COM, PPCEFS, {FRS, D, RAS}},
5704
5705 {"stfd", OP(54), OP_MASK, COM, PPCEFS, {FRS, D, RA0}},
5706
5707 {"stfdu", OP(55), OP_MASK, COM, PPCEFS, {FRS, D, RAS}},
5708
5709 {"lq", OP(56), OP_MASK, POWER4, PPC476, {RTQ, DQ, RAQ}},
5710 {"psq_l", OP(56), OP_MASK, PPCPS, PPCNONE, {FRT,PSD,RA,PSW,PSQ}},
5711 {"lfq", OP(56), OP_MASK, POWER2, PPCNONE, {FRT, D, RA0}},
5712
5713 {"lfdp", OP(57), OP_MASK, POWER6, POWER7, {FRTp, D, RA0}},
5714 {"psq_lu", OP(57), OP_MASK, PPCPS, PPCNONE, {FRT,PSD,RA,PSW,PSQ}},
5715 {"lfqu", OP(57), OP_MASK, POWER2, PPCNONE, {FRT, D, RA0}},
5716
5717 {"ld", DSO(58,0), DS_MASK, PPC64, PPCNONE, {RT, DS, RA0}},
5718 {"ldu", DSO(58,1), DS_MASK, PPC64, PPCNONE, {RT, DS, RAL}},
5719 {"lwa", DSO(58,2), DS_MASK, PPC64, PPCNONE, {RT, DS, RA0}},
5720
5721 {"dadd", XRC(59,2,0), X_MASK, POWER6, PPCNONE, {FRT, FRA, FRB}},
5722 {"dadd.", XRC(59,2,1), X_MASK, POWER6, PPCNONE, {FRT, FRA, FRB}},
5723
5724 {"dqua", ZRC(59,3,0), Z2_MASK, POWER6, PPCNONE, {FRT,FRA,FRB,RMC}},
5725 {"dqua.", ZRC(59,3,1), Z2_MASK, POWER6, PPCNONE, {FRT,FRA,FRB,RMC}},
5726
5727 {"fdivs", A(59,18,0), AFRC_MASK, PPC, PPCEFS, {FRT, FRA, FRB}},
5728 {"fdivs.", A(59,18,1), AFRC_MASK, PPC, PPCEFS, {FRT, FRA, FRB}},
5729
5730 {"fsubs", A(59,20,0), AFRC_MASK, PPC, PPCEFS, {FRT, FRA, FRB}},
5731 {"fsubs.", A(59,20,1), AFRC_MASK, PPC, PPCEFS, {FRT, FRA, FRB}},
5732
5733 {"fadds", A(59,21,0), AFRC_MASK, PPC, PPCEFS, {FRT, FRA, FRB}},
5734 {"fadds.", A(59,21,1), AFRC_MASK, PPC, PPCEFS, {FRT, FRA, FRB}},
5735
5736 {"fsqrts", A(59,22,0), AFRAFRC_MASK, PPC, TITAN, {FRT, FRB}},
5737 {"fsqrts.", A(59,22,1), AFRAFRC_MASK, PPC, TITAN, {FRT, FRB}},
5738
5739 {"fres", A(59,24,0), AFRAFRC_MASK, POWER7, PPCNONE, {FRT, FRB}},
5740 {"fres", A(59,24,0), AFRALFRC_MASK, PPC, POWER7, {FRT, FRB, A_L}},
5741 {"fres.", A(59,24,1), AFRAFRC_MASK, POWER7, PPCNONE, {FRT, FRB}},
5742 {"fres.", A(59,24,1), AFRALFRC_MASK, PPC, POWER7, {FRT, FRB, A_L}},
5743
5744 {"fmuls", A(59,25,0), AFRB_MASK, PPC, PPCEFS, {FRT, FRA, FRC}},
5745 {"fmuls.", A(59,25,1), AFRB_MASK, PPC, PPCEFS, {FRT, FRA, FRC}},
5746
5747 {"frsqrtes", A(59,26,0), AFRAFRC_MASK, POWER7, PPCNONE, {FRT, FRB}},
5748 {"frsqrtes", A(59,26,0), AFRALFRC_MASK, POWER5, POWER7, {FRT, FRB, A_L}},
5749 {"frsqrtes.", A(59,26,1), AFRAFRC_MASK, POWER7, PPCNONE, {FRT, FRB}},
5750 {"frsqrtes.", A(59,26,1), AFRALFRC_MASK, POWER5, POWER7, {FRT, FRB, A_L}},
5751
5752 {"fmsubs", A(59,28,0), A_MASK, PPC, PPCEFS, {FRT, FRA, FRC, FRB}},
5753 {"fmsubs.", A(59,28,1), A_MASK, PPC, PPCEFS, {FRT, FRA, FRC, FRB}},
5754
5755 {"fmadds", A(59,29,0), A_MASK, PPC, PPCEFS, {FRT, FRA, FRC, FRB}},
5756 {"fmadds.", A(59,29,1), A_MASK, PPC, PPCEFS, {FRT, FRA, FRC, FRB}},
5757
5758 {"fnmsubs", A(59,30,0), A_MASK, PPC, PPCEFS, {FRT, FRA, FRC, FRB}},
5759 {"fnmsubs.", A(59,30,1), A_MASK, PPC, PPCEFS, {FRT, FRA, FRC, FRB}},
5760
5761 {"fnmadds", A(59,31,0), A_MASK, PPC, PPCEFS, {FRT, FRA, FRC, FRB}},
5762 {"fnmadds.", A(59,31,1), A_MASK, PPC, PPCEFS, {FRT, FRA, FRC, FRB}},
5763
5764 {"dmul", XRC(59,34,0), X_MASK, POWER6, PPCNONE, {FRT, FRA, FRB}},
5765 {"dmul.", XRC(59,34,1), X_MASK, POWER6, PPCNONE, {FRT, FRA, FRB}},
5766
5767 {"drrnd", ZRC(59,35,0), Z2_MASK, POWER6, PPCNONE, {FRT, FRA, FRB, RMC}},
5768 {"drrnd.", ZRC(59,35,1), Z2_MASK, POWER6, PPCNONE, {FRT, FRA, FRB, RMC}},
5769
5770 {"dscli", ZRC(59,66,0), Z_MASK, POWER6, PPCNONE, {FRT, FRA, SH16}},
5771 {"dscli.", ZRC(59,66,1), Z_MASK, POWER6, PPCNONE, {FRT, FRA, SH16}},
5772
5773 {"dquai", ZRC(59,67,0), Z2_MASK, POWER6, PPCNONE, {TE, FRT,FRB,RMC}},
5774 {"dquai.", ZRC(59,67,1), Z2_MASK, POWER6, PPCNONE, {TE, FRT,FRB,RMC}},
5775
5776 {"dscri", ZRC(59,98,0), Z_MASK, POWER6, PPCNONE, {FRT, FRA, SH16}},
5777 {"dscri.", ZRC(59,98,1), Z_MASK, POWER6, PPCNONE, {FRT, FRA, SH16}},
5778
5779 {"drintx", ZRC(59,99,0), Z2_MASK, POWER6, PPCNONE, {R, FRT, FRB, RMC}},
5780 {"drintx.", ZRC(59,99,1), Z2_MASK, POWER6, PPCNONE, {R, FRT, FRB, RMC}},
5781
5782 {"dcmpo", X(59,130), X_MASK, POWER6, PPCNONE, {BF, FRA, FRB}},
5783
5784 {"dtstex", X(59,162), X_MASK, POWER6, PPCNONE, {BF, FRA, FRB}},
5785 {"dtstdc", Z(59,194), Z_MASK, POWER6, PPCNONE, {BF, FRA, DCM}},
5786 {"dtstdg", Z(59,226), Z_MASK, POWER6, PPCNONE, {BF, FRA, DGM}},
5787
5788 {"drintn", ZRC(59,227,0), Z2_MASK, POWER6, PPCNONE, {R, FRT, FRB, RMC}},
5789 {"drintn.", ZRC(59,227,1), Z2_MASK, POWER6, PPCNONE, {R, FRT, FRB, RMC}},
5790
5791 {"dctdp", XRC(59,258,0), X_MASK, POWER6, PPCNONE, {FRT, FRB}},
5792 {"dctdp.", XRC(59,258,1), X_MASK, POWER6, PPCNONE, {FRT, FRB}},
5793
5794 {"dctfix", XRC(59,290,0), X_MASK, POWER6, PPCNONE, {FRT, FRB}},
5795 {"dctfix.", XRC(59,290,1), X_MASK, POWER6, PPCNONE, {FRT, FRB}},
5796
5797 {"ddedpd", XRC(59,322,0), X_MASK, POWER6, PPCNONE, {SP, FRT, FRB}},
5798 {"ddedpd.", XRC(59,322,1), X_MASK, POWER6, PPCNONE, {SP, FRT, FRB}},
5799
5800 {"dxex", XRC(59,354,0), X_MASK, POWER6, PPCNONE, {FRT, FRB}},
5801 {"dxex.", XRC(59,354,1), X_MASK, POWER6, PPCNONE, {FRT, FRB}},
5802
5803 {"dsub", XRC(59,514,0), X_MASK, POWER6, PPCNONE, {FRT, FRA, FRB}},
5804 {"dsub.", XRC(59,514,1), X_MASK, POWER6, PPCNONE, {FRT, FRA, FRB}},
5805
5806 {"ddiv", XRC(59,546,0), X_MASK, POWER6, PPCNONE, {FRT, FRA, FRB}},
5807 {"ddiv.", XRC(59,546,1), X_MASK, POWER6, PPCNONE, {FRT, FRA, FRB}},
5808
5809 {"dcmpu", X(59,642), X_MASK, POWER6, PPCNONE, {BF, FRA, FRB}},
5810
5811 {"dtstsf", X(59,674), X_MASK, POWER6, PPCNONE, {BF, FRA, FRB}},
5812
5813 {"drsp", XRC(59,770,0), X_MASK, POWER6, PPCNONE, {FRT, FRB}},
5814 {"drsp.", XRC(59,770,1), X_MASK, POWER6, PPCNONE, {FRT, FRB}},
5815
5816 {"dcffix", XRC(59,802,0), X_MASK|FRA_MASK, POWER7, PPCNONE, {FRT, FRB}},
5817 {"dcffix.", XRC(59,802,1), X_MASK|FRA_MASK, POWER7, PPCNONE, {FRT, FRB}},
5818
5819 {"denbcd", XRC(59,834,0), X_MASK, POWER6, PPCNONE, {S, FRT, FRB}},
5820 {"denbcd.", XRC(59,834,1), X_MASK, POWER6, PPCNONE, {S, FRT, FRB}},
5821
5822 {"fcfids", XRC(59,846,0), XRA_MASK, POWER7|PPCA2, PPCNONE, {FRT, FRB}},
5823 {"fcfids.", XRC(59,846,1), XRA_MASK, POWER7|PPCA2, PPCNONE, {FRT, FRB}},
5824
5825 {"diex", XRC(59,866,0), X_MASK, POWER6, PPCNONE, {FRT, FRA, FRB}},
5826 {"diex.", XRC(59,866,1), X_MASK, POWER6, PPCNONE, {FRT, FRA, FRB}},
5827
5828 {"fcfidus", XRC(59,974,0), XRA_MASK, POWER7|PPCA2, PPCNONE, {FRT, FRB}},
5829 {"fcfidus.", XRC(59,974,1), XRA_MASK, POWER7|PPCA2, PPCNONE, {FRT, FRB}},
5830
5831 {"xxsldwi", XX3(60,2), XX3SHW_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6, SHW}},
5832 {"xxsel", XX4(60,3), XX4_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6, XC6}},
5833 {"xxspltd", XX3(60,10), XX3DM_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6S, DMEX}},
5834 {"xxmrghd", XX3(60,10), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}},
5835 {"xxswapd", XX3(60,10)|(2<<8), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6S}},
5836 {"xxmrgld", XX3(60,10)|(3<<8), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}},
5837 {"xxpermdi", XX3(60,10), XX3DM_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6, DM}},
5838 {"xxmrghw", XX3(60,18), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}},
5839 {"xsadddp", XX3(60,32), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}},
5840 {"xsmaddadp", XX3(60,33), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}},
5841 {"xscmpudp", XX3(60,35), XX3BF_MASK, PPCVSX, PPCNONE, {BF, XA6, XB6}},
5842 {"xssubdp", XX3(60,40), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}},
5843 {"xsmaddmdp", XX3(60,41), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}},
5844 {"xscmpodp", XX3(60,43), XX3BF_MASK, PPCVSX, PPCNONE, {BF, XA6, XB6}},
5845 {"xsmuldp", XX3(60,48), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}},
5846 {"xsmsubadp", XX3(60,49), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}},
5847 {"xxmrglw", XX3(60,50), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}},
5848 {"xsdivdp", XX3(60,56), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}},
5849 {"xsmsubmdp", XX3(60,57), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}},
5850 {"xstdivdp", XX3(60,61), XX3BF_MASK, PPCVSX, PPCNONE, {BF, XA6, XB6}},
5851 {"xvaddsp", XX3(60,64), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}},
5852 {"xvmaddasp", XX3(60,65), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}},
5853 {"xvcmpeqsp", XX3RC(60,67,0), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}},
5854 {"xvcmpeqsp.", XX3RC(60,67,1), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}},
5855 {"xvsubsp", XX3(60,72), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}},
5856 {"xscvdpuxws", XX2(60,72), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}},
5857 {"xvmaddmsp", XX3(60,73), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}},
5858 {"xsrdpi", XX2(60,73), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}},
5859 {"xsrsqrtedp", XX2(60,74), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}},
5860 {"xssqrtdp", XX2(60,75), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}},
5861 {"xvcmpgtsp", XX3RC(60,75,0), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}},
5862 {"xvcmpgtsp.", XX3RC(60,75,1), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}},
5863 {"xvmulsp", XX3(60,80), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}},
5864 {"xvmsubasp", XX3(60,81), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}},
5865 {"xvcmpgesp", XX3RC(60,83,0), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}},
5866 {"xvcmpgesp.", XX3RC(60,83,1), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}},
5867 {"xvdivsp", XX3(60,88), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}},
5868 {"xscvdpsxws", XX2(60,88), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}},
5869 {"xvmsubmsp", XX3(60,89), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}},
5870 {"xsrdpiz", XX2(60,89), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}},
5871 {"xsredp", XX2(60,90), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}},
5872 {"xvtdivsp", XX3(60,93), XX3BF_MASK, PPCVSX, PPCNONE, {BF, XA6, XB6}},
5873 {"xvadddp", XX3(60,96), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}},
5874 {"xvmaddadp", XX3(60,97), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}},
5875 {"xvcmpeqdp", XX3RC(60,99,0), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}},
5876 {"xvcmpeqdp.", XX3RC(60,99,1), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}},
5877 {"xvsubdp", XX3(60,104), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}},
5878 {"xvmaddmdp", XX3(60,105), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}},
5879 {"xsrdpip", XX2(60,105), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}},
5880 {"xstsqrtdp", XX2(60,106), XX2BF_MASK, PPCVSX, PPCNONE, {BF, XB6}},
5881 {"xsrdpic", XX2(60,107), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}},
5882 {"xvcmpgtdp", XX3RC(60,107,0), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}},
5883 {"xvcmpgtdp.", XX3RC(60,107,1), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}},
5884 {"xvmuldp", XX3(60,112), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}},
5885 {"xvmsubadp", XX3(60,113), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}},
5886 {"xvcmpgedp", XX3RC(60,115,0), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}},
5887 {"xvcmpgedp.", XX3RC(60,115,1), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}},
5888 {"xvdivdp", XX3(60,120), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}},
5889 {"xvmsubmdp", XX3(60,121), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}},
5890 {"xsrdpim", XX2(60,121), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}},
5891 {"xvtdivdp", XX3(60,125), XX3BF_MASK, PPCVSX, PPCNONE, {BF, XA6, XB6}},
5892 {"xxland", XX3(60,130), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}},
5893 {"xvcvspuxws", XX2(60,136), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}},
5894 {"xvrspi", XX2(60,137), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}},
5895 {"xxlandc", XX3(60,138), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}},
5896 {"xvrsqrtesp", XX2(60,138), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}},
5897 {"xvsqrtsp", XX2(60,139), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}},
5898 {"xxlor", XX3(60,146), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}},
5899 {"xvcvspsxws", XX2(60,152), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}},
5900 {"xvrspiz", XX2(60,153), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}},
5901 {"xxlxor", XX3(60,154), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}},
5902 {"xvresp", XX2(60,154), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}},
5903 {"xsmaxdp", XX3(60,160), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}},
5904 {"xsnmaddadp", XX3(60,161), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}},
5905 {"xxlnor", XX3(60,162), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}},
5906 {"xxspltw", XX2(60,164), XX2UIM_MASK, PPCVSX, PPCNONE, {XT6, XB6, UIM}},
5907 {"xsmindp", XX3(60,168), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}},
5908 {"xvcvuxwsp", XX2(60,168), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}},
5909 {"xsnmaddmdp", XX3(60,169), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}},
5910 {"xvrspip", XX2(60,169), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}},
5911 {"xvtsqrtsp", XX2(60,170), XX2BF_MASK, PPCVSX, PPCNONE, {BF, XB6}},
5912 {"xvrspic", XX2(60,171), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}},
5913 {"xscpsgndp", XX3(60,176), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}},
5914 {"xsnmsubadp", XX3(60,177), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}},
5915 {"xvcvsxwsp", XX2(60,184), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}},
5916 {"xsnmsubmdp", XX3(60,185), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}},
5917 {"xvrspim", XX2(60,185), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}},
5918 {"xvmaxsp", XX3(60,192), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}},
5919 {"xvnmaddasp", XX3(60,193), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}},
5920 {"xvminsp", XX3(60,200), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}},
5921 {"xvcvdpuxws", XX2(60,200), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}},
5922 {"xvnmaddmsp", XX3(60,201), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}},
5923 {"xvrdpi", XX2(60,201), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}},
5924 {"xvrsqrtedp", XX2(60,202), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}},
5925 {"xvsqrtdp", XX2(60,203), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}},
5926 {"xvmovsp", XX3(60,208), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6S}},
5927 {"xvcpsgnsp", XX3(60,208), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}},
5928 {"xvnmsubasp", XX3(60,209), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}},
5929 {"xvcvdpsxws", XX2(60,216), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}},
5930 {"xvnmsubmsp", XX3(60,217), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}},
5931 {"xvrdpiz", XX2(60,217), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}},
5932 {"xvredp", XX2(60,218), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}},
5933 {"xvmaxdp", XX3(60,224), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}},
5934 {"xvnmaddadp", XX3(60,225), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}},
5935 {"xvmindp", XX3(60,232), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}},
5936 {"xvnmaddmdp", XX3(60,233), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}},
5937 {"xvcvuxwdp", XX2(60,232), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}},
5938 {"xvrdpip", XX2(60,233), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}},
5939 {"xvtsqrtdp", XX2(60,234), XX2BF_MASK, PPCVSX, PPCNONE, {BF, XB6}},
5940 {"xvrdpic", XX2(60,235), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}},
5941 {"xvmovdp", XX3(60,240), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6S}},
5942 {"xvcpsgndp", XX3(60,240), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}},
5943 {"xvnmsubadp", XX3(60,241), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}},
5944 {"xvcvsxwdp", XX2(60,248), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}},
5945 {"xvnmsubmdp", XX3(60,249), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}},
5946 {"xvrdpim", XX2(60,249), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}},
5947 {"xscvdpsp", XX2(60,265), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}},
5948 {"xscvdpuxds", XX2(60,328), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}},
5949 {"xscvspdp", XX2(60,329), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}},
5950 {"xscvdpsxds", XX2(60,344), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}},
5951 {"xsabsdp", XX2(60,345), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}},
5952 {"xscvuxddp", XX2(60,360), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}},
5953 {"xsnabsdp", XX2(60,361), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}},
5954 {"xscvsxddp", XX2(60,376), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}},
5955 {"xsnegdp", XX2(60,377), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}},
5956 {"xvcvspuxds", XX2(60,392), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}},
5957 {"xvcvdpsp", XX2(60,393), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}},
5958 {"xvcvspsxds", XX2(60,408), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}},
5959 {"xvabssp", XX2(60,409), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}},
5960 {"xvcvuxdsp", XX2(60,424), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}},
5961 {"xvnabssp", XX2(60,425), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}},
5962 {"xvcvsxdsp", XX2(60,440), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}},
5963 {"xvnegsp", XX2(60,441), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}},
5964 {"xvcvdpuxds", XX2(60,456), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}},
5965 {"xvcvspdp", XX2(60,457), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}},
5966 {"xvcvdpsxds", XX2(60,472), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}},
5967 {"xvabsdp", XX2(60,473), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}},
5968 {"xvcvuxddp", XX2(60,488), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}},
5969 {"xvnabsdp", XX2(60,489), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}},
5970 {"xvcvsxddp", XX2(60,504), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}},
5971 {"xvnegdp", XX2(60,505), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}},
5972
5973 {"psq_st", OP(60), OP_MASK, PPCPS, PPCNONE, {FRS,PSD,RA,PSW,PSQ}},
5974 {"stfq", OP(60), OP_MASK, POWER2, PPCNONE, {FRS, D, RA}},
5975
5976 {"stfdp", OP(61), OP_MASK, POWER6, POWER7, {FRSp, D, RA0}},
5977 {"psq_stu", OP(61), OP_MASK, PPCPS, PPCNONE, {FRS,PSD,RA,PSW,PSQ}},
5978 {"stfqu", OP(61), OP_MASK, POWER2, PPCNONE, {FRS, D, RA}},
5979
5980 {"std", DSO(62,0), DS_MASK, PPC64, PPCNONE, {RS, DS, RA0}},
5981 {"stdu", DSO(62,1), DS_MASK, PPC64, PPCNONE, {RS, DS, RAS}},
5982 {"stq", DSO(62,2), DS_MASK, POWER4, PPC476, {RSQ, DS, RA0}},
5983
5984 {"fcmpu", X(63,0), X_MASK|(3<<21), COM, PPCEFS, {BF, FRA, FRB}},
5985
5986 {"daddq", XRC(63,2,0), X_MASK, POWER6, PPCNONE, {FRTp, FRAp, FRBp}},
5987 {"daddq.", XRC(63,2,1), X_MASK, POWER6, PPCNONE, {FRTp, FRAp, FRBp}},
5988
5989 {"dquaq", ZRC(63,3,0), Z2_MASK, POWER6, PPCNONE, {FRTp, FRAp, FRBp, RMC}},
5990 {"dquaq.", ZRC(63,3,1), Z2_MASK, POWER6, PPCNONE, {FRTp, FRAp, FRBp, RMC}},
5991
5992 {"fcpsgn", XRC(63,8,0), X_MASK, POWER6|PPCA2|PPC476, PPCNONE, {FRT, FRA, FRB}},
5993 {"fcpsgn.", XRC(63,8,1), X_MASK, POWER6|PPCA2|PPC476, PPCNONE, {FRT, FRA, FRB}},
5994
5995 {"frsp", XRC(63,12,0), XRA_MASK, COM, PPCEFS, {FRT, FRB}},
5996 {"frsp.", XRC(63,12,1), XRA_MASK, COM, PPCEFS, {FRT, FRB}},
5997
5998 {"fctiw", XRC(63,14,0), XRA_MASK, PPCCOM, PPCEFS, {FRT, FRB}},
5999 {"fcir", XRC(63,14,0), XRA_MASK, PWR2COM, PPCNONE, {FRT, FRB}},
6000 {"fctiw.", XRC(63,14,1), XRA_MASK, PPCCOM, PPCEFS, {FRT, FRB}},
6001 {"fcir.", XRC(63,14,1), XRA_MASK, PWR2COM, PPCNONE, {FRT, FRB}},
6002
6003 {"fctiwz", XRC(63,15,0), XRA_MASK, PPCCOM, PPCEFS, {FRT, FRB}},
6004 {"fcirz", XRC(63,15,0), XRA_MASK, PWR2COM, PPCNONE, {FRT, FRB}},
6005 {"fctiwz.", XRC(63,15,1), XRA_MASK, PPCCOM, PPCEFS, {FRT, FRB}},
6006 {"fcirz.", XRC(63,15,1), XRA_MASK, PWR2COM, PPCNONE, {FRT, FRB}},
6007
6008 {"fdiv", A(63,18,0), AFRC_MASK, PPCCOM, PPCEFS, {FRT, FRA, FRB}},
6009 {"fd", A(63,18,0), AFRC_MASK, PWRCOM, PPCNONE, {FRT, FRA, FRB}},
6010 {"fdiv.", A(63,18,1), AFRC_MASK, PPCCOM, PPCEFS, {FRT, FRA, FRB}},
6011 {"fd.", A(63,18,1), AFRC_MASK, PWRCOM, PPCNONE, {FRT, FRA, FRB}},
6012
6013 {"fsub", A(63,20,0), AFRC_MASK, PPCCOM, PPCEFS, {FRT, FRA, FRB}},
6014 {"fs", A(63,20,0), AFRC_MASK, PWRCOM, PPCNONE, {FRT, FRA, FRB}},
6015 {"fsub.", A(63,20,1), AFRC_MASK, PPCCOM, PPCEFS, {FRT, FRA, FRB}},
6016 {"fs.", A(63,20,1), AFRC_MASK, PWRCOM, PPCNONE, {FRT, FRA, FRB}},
6017
6018 {"fadd", A(63,21,0), AFRC_MASK, PPCCOM, PPCEFS, {FRT, FRA, FRB}},
6019 {"fa", A(63,21,0), AFRC_MASK, PWRCOM, PPCNONE, {FRT, FRA, FRB}},
6020 {"fadd.", A(63,21,1), AFRC_MASK, PPCCOM, PPCEFS, {FRT, FRA, FRB}},
6021 {"fa.", A(63,21,1), AFRC_MASK, PWRCOM, PPCNONE, {FRT, FRA, FRB}},
6022
6023 {"fsqrt", A(63,22,0), AFRAFRC_MASK, PPCPWR2, TITAN, {FRT, FRB}},
6024 {"fsqrt.", A(63,22,1), AFRAFRC_MASK, PPCPWR2, TITAN, {FRT, FRB}},
6025
6026 {"fsel", A(63,23,0), A_MASK, PPC, PPCEFS, {FRT, FRA, FRC, FRB}},
6027 {"fsel.", A(63,23,1), A_MASK, PPC, PPCEFS, {FRT, FRA, FRC, FRB}},
6028
6029 {"fre", A(63,24,0), AFRAFRC_MASK, POWER7, PPCNONE, {FRT, FRB}},
6030 {"fre", A(63,24,0), AFRALFRC_MASK, POWER5, POWER7, {FRT, FRB, A_L}},
6031 {"fre.", A(63,24,1), AFRAFRC_MASK, POWER7, PPCNONE, {FRT, FRB}},
6032 {"fre.", A(63,24,1), AFRALFRC_MASK, POWER5, POWER7, {FRT, FRB, A_L}},
6033
6034 {"fmul", A(63,25,0), AFRB_MASK, PPCCOM, PPCEFS, {FRT, FRA, FRC}},
6035 {"fm", A(63,25,0), AFRB_MASK, PWRCOM, PPCNONE, {FRT, FRA, FRC}},
6036 {"fmul.", A(63,25,1), AFRB_MASK, PPCCOM, PPCEFS, {FRT, FRA, FRC}},
6037 {"fm.", A(63,25,1), AFRB_MASK, PWRCOM, PPCNONE, {FRT, FRA, FRC}},
6038
6039 {"frsqrte", A(63,26,0), AFRAFRC_MASK, POWER7, PPCNONE, {FRT, FRB}},
6040 {"frsqrte", A(63,26,0), AFRALFRC_MASK, PPC, POWER7, {FRT, FRB, A_L}},
6041 {"frsqrte.", A(63,26,1), AFRAFRC_MASK, POWER7, PPCNONE, {FRT, FRB}},
6042 {"frsqrte.", A(63,26,1), AFRALFRC_MASK, PPC, POWER7, {FRT, FRB, A_L}},
6043
6044 {"fmsub", A(63,28,0), A_MASK, PPCCOM, PPCEFS, {FRT, FRA, FRC, FRB}},
6045 {"fms", A(63,28,0), A_MASK, PWRCOM, PPCNONE, {FRT, FRA, FRC, FRB}},
6046 {"fmsub.", A(63,28,1), A_MASK, PPCCOM, PPCEFS, {FRT, FRA, FRC, FRB}},
6047 {"fms.", A(63,28,1), A_MASK, PWRCOM, PPCNONE, {FRT, FRA, FRC, FRB}},
6048
6049 {"fmadd", A(63,29,0), A_MASK, PPCCOM, PPCEFS, {FRT, FRA, FRC, FRB}},
6050 {"fma", A(63,29,0), A_MASK, PWRCOM, PPCNONE, {FRT, FRA, FRC, FRB}},
6051 {"fmadd.", A(63,29,1), A_MASK, PPCCOM, PPCEFS, {FRT, FRA, FRC, FRB}},
6052 {"fma.", A(63,29,1), A_MASK, PWRCOM, PPCNONE, {FRT, FRA, FRC, FRB}},
6053
6054 {"fnmsub", A(63,30,0), A_MASK, PPCCOM, PPCEFS, {FRT, FRA, FRC, FRB}},
6055 {"fnms", A(63,30,0), A_MASK, PWRCOM, PPCNONE, {FRT, FRA, FRC, FRB}},
6056 {"fnmsub.", A(63,30,1), A_MASK, PPCCOM, PPCEFS, {FRT, FRA, FRC, FRB}},
6057 {"fnms.", A(63,30,1), A_MASK, PWRCOM, PPCNONE, {FRT, FRA, FRC, FRB}},
6058
6059 {"fnmadd", A(63,31,0), A_MASK, PPCCOM, PPCEFS, {FRT, FRA, FRC, FRB}},
6060 {"fnma", A(63,31,0), A_MASK, PWRCOM, PPCNONE, {FRT, FRA, FRC, FRB}},
6061 {"fnmadd.", A(63,31,1), A_MASK, PPCCOM, PPCEFS, {FRT, FRA, FRC, FRB}},
6062 {"fnma.", A(63,31,1), A_MASK, PWRCOM, PPCNONE, {FRT, FRA, FRC, FRB}},
6063
6064 {"fcmpo", X(63,32), X_MASK|(3<<21), COM, PPCEFS, {BF, FRA, FRB}},
6065
6066 {"dmulq", XRC(63,34,0), X_MASK, POWER6, PPCNONE, {FRTp, FRAp, FRBp}},
6067 {"dmulq.", XRC(63,34,1), X_MASK, POWER6, PPCNONE, {FRTp, FRAp, FRBp}},
6068
6069 {"drrndq", ZRC(63,35,0), Z2_MASK, POWER6, PPCNONE, {FRTp, FRA, FRBp, RMC}},
6070 {"drrndq.", ZRC(63,35,1), Z2_MASK, POWER6, PPCNONE, {FRTp, FRA, FRBp, RMC}},
6071
6072 {"mtfsb1", XRC(63,38,0), XRARB_MASK, COM, PPCNONE, {BT}},
6073 {"mtfsb1.", XRC(63,38,1), XRARB_MASK, COM, PPCNONE, {BT}},
6074
6075 {"fneg", XRC(63,40,0), XRA_MASK, COM, PPCEFS, {FRT, FRB}},
6076 {"fneg.", XRC(63,40,1), XRA_MASK, COM, PPCEFS, {FRT, FRB}},
6077
6078 {"mcrfs", X(63,64), XRB_MASK|(3<<21)|(3<<16), COM, PPCNONE, {BF, BFA}},
6079
6080 {"dscliq", ZRC(63,66,0), Z_MASK, POWER6, PPCNONE, {FRTp, FRAp, SH16}},
6081 {"dscliq.", ZRC(63,66,1), Z_MASK, POWER6, PPCNONE, {FRTp, FRAp, SH16}},
6082
6083 {"dquaiq", ZRC(63,67,0), Z2_MASK, POWER6, PPCNONE, {TE, FRTp, FRBp, RMC}},
6084 {"dquaiq.", ZRC(63,67,1), Z2_MASK, POWER6, PPCNONE, {TE, FRTp, FRBp, RMC}},
6085
6086 {"mtfsb0", XRC(63,70,0), XRARB_MASK, COM, PPCNONE, {BT}},
6087 {"mtfsb0.", XRC(63,70,1), XRARB_MASK, COM, PPCNONE, {BT}},
6088
6089 {"fmr", XRC(63,72,0), XRA_MASK, COM, PPCEFS, {FRT, FRB}},
6090 {"fmr.", XRC(63,72,1), XRA_MASK, COM, PPCEFS, {FRT, FRB}},
6091
6092 {"dscriq", ZRC(63,98,0), Z_MASK, POWER6, PPCNONE, {FRTp, FRAp, SH16}},
6093 {"dscriq.", ZRC(63,98,1), Z_MASK, POWER6, PPCNONE, {FRTp, FRAp, SH16}},
6094
6095 {"drintxq", ZRC(63,99,0), Z2_MASK, POWER6, PPCNONE, {R, FRTp, FRBp, RMC}},
6096 {"drintxq.", ZRC(63,99,1), Z2_MASK, POWER6, PPCNONE, {R, FRTp, FRBp, RMC}},
6097
6098 {"ftdiv", X(63,128), X_MASK|(3<<21), POWER7, PPCNONE, {BF, FRA, FRB}},
6099
6100 {"dcmpoq", X(63,130), X_MASK, POWER6, PPCNONE, {BF, FRAp, FRBp}},
6101
6102 {"mtfsfi", XRC(63,134,0), XWRA_MASK|(3<<21)|(1<<11), POWER6|PPCA2|PPC476, PPCNONE, {BFF, U, W}},
6103 {"mtfsfi", XRC(63,134,0), XRA_MASK|(3<<21)|(1<<11), COM, POWER6|PPCA2|PPC476, {BFF, U}},
6104 {"mtfsfi.", XRC(63,134,1), XWRA_MASK|(3<<21)|(1<<11), POWER6|PPCA2|PPC476, PPCNONE, {BFF, U, W}},
6105 {"mtfsfi.", XRC(63,134,1), XRA_MASK|(3<<21)|(1<<11), COM, POWER6|PPCA2|PPC476, {BFF, U}},
6106
6107 {"fnabs", XRC(63,136,0), XRA_MASK, COM, PPCEFS, {FRT, FRB}},
6108 {"fnabs.", XRC(63,136,1), XRA_MASK, COM, PPCEFS, {FRT, FRB}},
6109
6110 {"fctiwu", XRC(63,142,0), XRA_MASK, POWER7, PPCNONE, {FRT, FRB}},
6111 {"fctiwu.", XRC(63,142,1), XRA_MASK, POWER7, PPCNONE, {FRT, FRB}},
6112 {"fctiwuz", XRC(63,143,0), XRA_MASK, POWER7, PPCNONE, {FRT, FRB}},
6113 {"fctiwuz.", XRC(63,143,1), XRA_MASK, POWER7, PPCNONE, {FRT, FRB}},
6114
6115 {"ftsqrt", X(63,160), X_MASK|(3<<21|FRA_MASK), POWER7, PPCNONE, {BF, FRB}},
6116
6117 {"dtstexq", X(63,162), X_MASK, POWER6, PPCNONE, {BF, FRAp, FRBp}},
6118 {"dtstdcq", Z(63,194), Z_MASK, POWER6, PPCNONE, {BF, FRAp, DCM}},
6119 {"dtstdgq", Z(63,226), Z_MASK, POWER6, PPCNONE, {BF, FRAp, DGM}},
6120
6121 {"drintnq", ZRC(63,227,0), Z2_MASK, POWER6, PPCNONE, {R, FRTp, FRBp, RMC}},
6122 {"drintnq.", ZRC(63,227,1), Z2_MASK, POWER6, PPCNONE, {R, FRTp, FRBp, RMC}},
6123
6124 {"dctqpq", XRC(63,258,0), X_MASK, POWER6, PPCNONE, {FRTp, FRB}},
6125 {"dctqpq.", XRC(63,258,1), X_MASK, POWER6, PPCNONE, {FRTp, FRB}},
6126
6127 {"fabs", XRC(63,264,0), XRA_MASK, COM, PPCEFS, {FRT, FRB}},
6128 {"fabs.", XRC(63,264,1), XRA_MASK, COM, PPCEFS, {FRT, FRB}},
6129
6130 {"dctfixq", XRC(63,290,0), X_MASK, POWER6, PPCNONE, {FRT, FRBp}},
6131 {"dctfixq.", XRC(63,290,1), X_MASK, POWER6, PPCNONE, {FRT, FRBp}},
6132
6133 {"ddedpdq", XRC(63,322,0), X_MASK, POWER6, PPCNONE, {SP, FRTp, FRBp}},
6134 {"ddedpdq.", XRC(63,322,1), X_MASK, POWER6, PPCNONE, {SP, FRTp, FRBp}},
6135
6136 {"dxexq", XRC(63,354,0), X_MASK, POWER6, PPCNONE, {FRT, FRBp}},
6137 {"dxexq.", XRC(63,354,1), X_MASK, POWER6, PPCNONE, {FRT, FRBp}},
6138
6139 {"frin", XRC(63,392,0), XRA_MASK, POWER5, PPCNONE, {FRT, FRB}},
6140 {"frin.", XRC(63,392,1), XRA_MASK, POWER5, PPCNONE, {FRT, FRB}},
6141 {"friz", XRC(63,424,0), XRA_MASK, POWER5, PPCNONE, {FRT, FRB}},
6142 {"friz.", XRC(63,424,1), XRA_MASK, POWER5, PPCNONE, {FRT, FRB}},
6143 {"frip", XRC(63,456,0), XRA_MASK, POWER5, PPCNONE, {FRT, FRB}},
6144 {"frip.", XRC(63,456,1), XRA_MASK, POWER5, PPCNONE, {FRT, FRB}},
6145 {"frim", XRC(63,488,0), XRA_MASK, POWER5, PPCNONE, {FRT, FRB}},
6146 {"frim.", XRC(63,488,1), XRA_MASK, POWER5, PPCNONE, {FRT, FRB}},
6147
6148 {"dsubq", XRC(63,514,0), X_MASK, POWER6, PPCNONE, {FRTp, FRAp, FRBp}},
6149 {"dsubq.", XRC(63,514,1), X_MASK, POWER6, PPCNONE, {FRTp, FRAp, FRBp}},
6150
6151 {"ddivq", XRC(63,546,0), X_MASK, POWER6, PPCNONE, {FRTp, FRAp, FRBp}},
6152 {"ddivq.", XRC(63,546,1), X_MASK, POWER6, PPCNONE, {FRTp, FRAp, FRBp}},
6153
6154 {"mffs", XRC(63,583,0), XRARB_MASK, COM, PPCEFS, {FRT}},
6155 {"mffs.", XRC(63,583,1), XRARB_MASK, COM, PPCEFS, {FRT}},
6156
6157 {"dcmpuq", X(63,642), X_MASK, POWER6, PPCNONE, {BF, FRAp, FRBp}},
6158
6159 {"dtstsfq", X(63,674), X_MASK, POWER6, PPCNONE, {BF, FRA, FRBp}},
6160
6161 {"mtfsf", XFL(63,711,0), XFL_MASK, POWER6|PPCA2|PPC476, PPCNONE, {FLM, FRB, XFL_L, W}},
6162 {"mtfsf", XFL(63,711,0), XFL_MASK, COM, POWER6|PPCA2|PPC476|PPCEFS, {FLM, FRB}},
6163 {"mtfsf.", XFL(63,711,1), XFL_MASK, POWER6|PPCA2|PPC476, PPCNONE, {FLM, FRB, XFL_L, W}},
6164 {"mtfsf.", XFL(63,711,1), XFL_MASK, COM, POWER6|PPCA2|PPC476|PPCEFS, {FLM, FRB}},
6165
6166 {"drdpq", XRC(63,770,0), X_MASK, POWER6, PPCNONE, {FRTp, FRBp}},
6167 {"drdpq.", XRC(63,770,1), X_MASK, POWER6, PPCNONE, {FRTp, FRBp}},
6168
6169 {"dcffixq", XRC(63,802,0), X_MASK, POWER6, PPCNONE, {FRTp, FRB}},
6170 {"dcffixq.", XRC(63,802,1), X_MASK, POWER6, PPCNONE, {FRTp, FRB}},
6171
6172 {"fctid", XRC(63,814,0), XRA_MASK, PPC64, PPCNONE, {FRT, FRB}},
6173 {"fctid", XRC(63,814,0), XRA_MASK, PPC476, PPCNONE, {FRT, FRB}},
6174 {"fctid.", XRC(63,814,1), XRA_MASK, PPC64, PPCNONE, {FRT, FRB}},
6175 {"fctid.", XRC(63,814,1), XRA_MASK, PPC476, PPCNONE, {FRT, FRB}},
6176
6177 {"fctidz", XRC(63,815,0), XRA_MASK, PPC64, PPCNONE, {FRT, FRB}},
6178 {"fctidz", XRC(63,815,0), XRA_MASK, PPC476, PPCNONE, {FRT, FRB}},
6179 {"fctidz.", XRC(63,815,1), XRA_MASK, PPC64, PPCNONE, {FRT, FRB}},
6180 {"fctidz.", XRC(63,815,1), XRA_MASK, PPC476, PPCNONE, {FRT, FRB}},
6181
6182 {"denbcdq", XRC(63,834,0), X_MASK, POWER6, PPCNONE, {S, FRTp, FRBp}},
6183 {"denbcdq.", XRC(63,834,1), X_MASK, POWER6, PPCNONE, {S, FRTp, FRBp}},
6184
6185 {"fcfid", XRC(63,846,0), XRA_MASK, PPC64, PPCNONE, {FRT, FRB}},
6186 {"fcfid", XRC(63,846,0), XRA_MASK, PPC476, PPCNONE, {FRT, FRB}},
6187 {"fcfid.", XRC(63,846,1), XRA_MASK, PPC64, PPCNONE, {FRT, FRB}},
6188 {"fcfid.", XRC(63,846,1), XRA_MASK, PPC476, PPCNONE, {FRT, FRB}},
6189
6190 {"diexq", XRC(63,866,0), X_MASK, POWER6, PPCNONE, {FRTp, FRA, FRBp}},
6191 {"diexq.", XRC(63,866,1), X_MASK, POWER6, PPCNONE, {FRTp, FRA, FRBp}},
6192
6193 {"fctidu", XRC(63,942,0), XRA_MASK, POWER7|PPCA2, PPCNONE, {FRT, FRB}},
6194 {"fctidu.", XRC(63,942,1), XRA_MASK, POWER7|PPCA2, PPCNONE, {FRT, FRB}},
6195
6196 {"fctiduz", XRC(63,943,0), XRA_MASK, POWER7|PPCA2, PPCNONE, {FRT, FRB}},
6197 {"fctiduz.", XRC(63,943,1), XRA_MASK, POWER7|PPCA2, PPCNONE, {FRT, FRB}},
6198
6199 {"fcfidu", XRC(63,974,0), XRA_MASK, POWER7|PPCA2, PPCNONE, {FRT, FRB}},
6200 {"fcfidu.", XRC(63,974,1), XRA_MASK, POWER7|PPCA2, PPCNONE, {FRT, FRB}},
6201 };
6202
6203 const int powerpc_num_opcodes =
6204 sizeof (powerpc_opcodes) / sizeof (powerpc_opcodes[0]);
6205 \f
6206 /* The VLE opcode table.
6207
6208 The format of this opcode table is the same as the main opcode table. */
6209
6210 const struct powerpc_opcode vle_opcodes[] = {
6211
6212 {"se_illegal", C(0), C_MASK, PPCVLE, PPCNONE, {}},
6213 {"se_isync", C(1), C_MASK, PPCVLE, PPCNONE, {}},
6214 {"se_sc", C(2), C_MASK, PPCVLE, PPCNONE, {}},
6215 {"se_blr", C_LK(2,0), C_LK_MASK, PPCVLE, PPCNONE, {}},
6216 {"se_blrl", C_LK(2,1), C_LK_MASK, PPCVLE, PPCNONE, {}},
6217 {"se_bctr", C_LK(3,0), C_LK_MASK, PPCVLE, PPCNONE, {}},
6218 {"se_bctrl", C_LK(3,1), C_LK_MASK, PPCVLE, PPCNONE, {}},
6219 {"se_rfi", C(8), C_MASK, PPCVLE, PPCNONE, {}},
6220 {"se_rfci", C(9), C_MASK, PPCVLE, PPCNONE, {}},
6221 {"se_rfdi", C(10), C_MASK, PPCVLE, PPCNONE, {}},
6222 {"se_rfmci", C(11), C_MASK, PPCVLE, PPCNONE, {}},
6223 {"se_not", SE_R(0,2), SE_R_MASK, PPCVLE, PPCNONE, {RX}},
6224 {"se_neg", SE_R(0,3), SE_R_MASK, PPCVLE, PPCNONE, {RX}},
6225 {"se_mflr", SE_R(0,8), SE_R_MASK, PPCVLE, PPCNONE, {RX}},
6226 {"se_mtlr", SE_R(0,9), SE_R_MASK, PPCVLE, PPCNONE, {RX}},
6227 {"se_mfctr", SE_R(0,10), SE_R_MASK, PPCVLE, PPCNONE, {RX}},
6228 {"se_mtctr", SE_R(0,11), SE_R_MASK, PPCVLE, PPCNONE, {RX}},
6229 {"se_extzb", SE_R(0,12), SE_R_MASK, PPCVLE, PPCNONE, {RX}},
6230 {"se_extsb", SE_R(0,13), SE_R_MASK, PPCVLE, PPCNONE, {RX}},
6231 {"se_extzh", SE_R(0,14), SE_R_MASK, PPCVLE, PPCNONE, {RX}},
6232 {"se_extsh", SE_R(0,15), SE_R_MASK, PPCVLE, PPCNONE, {RX}},
6233 {"se_mr", SE_RR(0,1), SE_RR_MASK, PPCVLE, PPCNONE, {RX, RY}},
6234 {"se_mtar", SE_RR(0,2), SE_RR_MASK, PPCVLE, PPCNONE, {ARX, RY}},
6235 {"se_mfar", SE_RR(0,3), SE_RR_MASK, PPCVLE, PPCNONE, {RX, ARY}},
6236 {"se_add", SE_RR(1,0), SE_RR_MASK, PPCVLE, PPCNONE, {RX, RY}},
6237 {"se_mullw", SE_RR(1,1), SE_RR_MASK, PPCVLE, PPCNONE, {RX, RY}},
6238 {"se_sub", SE_RR(1,2), SE_RR_MASK, PPCVLE, PPCNONE, {RX, RY}},
6239 {"se_subf", SE_RR(1,3), SE_RR_MASK, PPCVLE, PPCNONE, {RX, RY}},
6240 {"se_cmp", SE_RR(3,0), SE_RR_MASK, PPCVLE, PPCNONE, {RX, RY}},
6241 {"se_cmpl", SE_RR(3,1), SE_RR_MASK, PPCVLE, PPCNONE, {RX, RY}},
6242 {"se_cmph", SE_RR(3,2), SE_RR_MASK, PPCVLE, PPCNONE, {RX, RY}},
6243 {"se_cmphl", SE_RR(3,3), SE_RR_MASK, PPCVLE, PPCNONE, {RX, RY}},
6244
6245 {"e_cmpi", SCI8BF(6,0,21), SCI8BF_MASK, PPCVLE, PPCNONE, {CRD32, RA, SCLSCI8}},
6246 {"e_cmpli", SCI8BF(6,1,21), SCI8BF_MASK, PPCVLE, PPCNONE, {CRD32, RA, SCLSCI8}},
6247 {"e_addi", SCI8(6,16), SCI8_MASK, PPCVLE, PPCNONE, {RT, RA, SCLSCI8}},
6248 {"e_subi", SCI8(6,16), SCI8_MASK, PPCVLE, PPCNONE, {RT, RA, SCLSCI8N}},
6249 {"e_addi.", SCI8(6,17), SCI8_MASK, PPCVLE, PPCNONE, {RT, RA, SCLSCI8}},
6250 {"e_addic", SCI8(6,18), SCI8_MASK, PPCVLE, PPCNONE, {RT, RA, SCLSCI8}},
6251 {"e_subic", SCI8(6,18), SCI8_MASK, PPCVLE, PPCNONE, {RT, RA, SCLSCI8N}},
6252 {"e_addic.", SCI8(6,19), SCI8_MASK, PPCVLE, PPCNONE, {RT, RA, SCLSCI8}},
6253 {"e_subic.", SCI8(6,19), SCI8_MASK, PPCVLE, PPCNONE, {RT, RA, SCLSCI8N}},
6254 {"e_mulli", SCI8(6,20), SCI8_MASK, PPCVLE, PPCNONE, {RT, RA, SCLSCI8}},
6255 {"e_subfic", SCI8(6,22), SCI8_MASK, PPCVLE, PPCNONE, {RT, RA, SCLSCI8}},
6256 {"e_subfic.", SCI8(6,23), SCI8_MASK, PPCVLE, PPCNONE, {RT, RA, SCLSCI8}},
6257 {"e_andi", SCI8(6,24), SCI8_MASK, PPCVLE, PPCNONE, {RA, RS, SCLSCI8}},
6258 {"e_andi.", SCI8(6,25), SCI8_MASK, PPCVLE, PPCNONE, {RA, RS, SCLSCI8}},
6259 {"e_nop", SCI8(6,26), 0xffffffff, PPCVLE, PPCNONE, {0}},
6260 {"e_ori", SCI8(6,26), SCI8_MASK, PPCVLE, PPCNONE, {RA, RS, SCLSCI8}},
6261 {"e_ori.", SCI8(6,27), SCI8_MASK, PPCVLE, PPCNONE, {RA, RS, SCLSCI8}},
6262 {"e_xori", SCI8(6,28), SCI8_MASK, PPCVLE, PPCNONE, {RA, RS, SCLSCI8}},
6263 {"e_xori.", SCI8(6,29), SCI8_MASK, PPCVLE, PPCNONE, {RA, RS, SCLSCI8}},
6264 {"e_lbzu", OPVUP(6,0), OPVUP_MASK, PPCVLE, PPCNONE, {RT, D8, RA0}},
6265 {"e_lhau", OPVUP(6,3), OPVUP_MASK, PPCVLE, PPCNONE, {RT, D8, RA0}},
6266 {"e_lhzu", OPVUP(6,1), OPVUP_MASK, PPCVLE, PPCNONE, {RT, D8, RA0}},
6267 {"e_lmw", OPVUP(6,8), OPVUP_MASK, PPCVLE, PPCNONE, {RT, D8, RA0}},
6268 {"e_lwzu", OPVUP(6,2), OPVUP_MASK, PPCVLE, PPCNONE, {RT, D8, RA0}},
6269 {"e_stbu", OPVUP(6,4), OPVUP_MASK, PPCVLE, PPCNONE, {RT, D8, RA0}},
6270 {"e_sthu", OPVUP(6,5), OPVUP_MASK, PPCVLE, PPCNONE, {RT, D8, RA0}},
6271 {"e_stwu", OPVUP(6,6), OPVUP_MASK, PPCVLE, PPCNONE, {RT, D8, RA0}},
6272 {"e_stmw", OPVUP(6,9), OPVUP_MASK, PPCVLE, PPCNONE, {RT, D8, RA0}},
6273 {"e_add16i", OP(7), OP_MASK, PPCVLE, PPCNONE, {RT, RA, SI}},
6274 {"e_la", OP(7), OP_MASK, PPCVLE, PPCNONE, {RT, D, RA0}},
6275 {"e_sub16i", OP(7), OP_MASK, PPCVLE, PPCNONE, {RT, RA, NSI}},
6276
6277 {"se_addi", SE_IM5(8,0), SE_IM5_MASK, PPCVLE, PPCNONE, {RX, OIMM5}},
6278 {"se_cmpli", SE_IM5(8,1), SE_IM5_MASK, PPCVLE, PPCNONE, {RX, OIMM5}},
6279 {"se_subi", SE_IM5(9,0), SE_IM5_MASK, PPCVLE, PPCNONE, {RX, OIMM5}},
6280 {"se_subi.", SE_IM5(9,1), SE_IM5_MASK, PPCVLE, PPCNONE, {RX, OIMM5}},
6281 {"se_cmpi", SE_IM5(10,1), SE_IM5_MASK, PPCVLE, PPCNONE, {RX, UI5}},
6282 {"se_bmaski", SE_IM5(11,0), SE_IM5_MASK, PPCVLE, PPCNONE, {RX, UI5}},
6283 {"se_andi", SE_IM5(11,1), SE_IM5_MASK, PPCVLE, PPCNONE, {RX, UI5}},
6284
6285 {"e_lbz", OP(12), OP_MASK, PPCVLE, PPCNONE, {RT, D, RA0}},
6286 {"e_stb", OP(13), OP_MASK, PPCVLE, PPCNONE, {RT, D, RA0}},
6287 {"e_lha", OP(14), OP_MASK, PPCVLE, PPCNONE, {RT, D, RA0}},
6288
6289 {"se_srw", SE_RR(16,0), SE_RR_MASK, PPCVLE, PPCNONE, {RX, RY}},
6290 {"se_sraw", SE_RR(16,1), SE_RR_MASK, PPCVLE, PPCNONE, {RX, RY}},
6291 {"se_slw", SE_RR(16,2), SE_RR_MASK, PPCVLE, PPCNONE, {RX, RY}},
6292 {"se_nop", SE_RR(17,0), 0xffff, PPCVLE, PPCNONE, {0}},
6293 {"se_or", SE_RR(17,0), SE_RR_MASK, PPCVLE, PPCNONE, {RX, RY}},
6294 {"se_andc", SE_RR(17,1), SE_RR_MASK, PPCVLE, PPCNONE, {RX, RY}},
6295 {"se_and", SE_RR(17,2), SE_RR_MASK, PPCVLE, PPCNONE, {RX, RY}},
6296 {"se_and.", SE_RR(17,3), SE_RR_MASK, PPCVLE, PPCNONE, {RX, RY}},
6297 {"se_li", IM7(9), IM7_MASK, PPCVLE, PPCNONE, {RX, UI7}},
6298
6299 {"e_lwz", OP(20), OP_MASK, PPCVLE, PPCNONE, {RT, D, RA0}},
6300 {"e_stw", OP(21), OP_MASK, PPCVLE, PPCNONE, {RT, D, RA0}},
6301 {"e_lhz", OP(22), OP_MASK, PPCVLE, PPCNONE, {RT, D, RA0}},
6302 {"e_sth", OP(23), OP_MASK, PPCVLE, PPCNONE, {RT, D, RA0}},
6303
6304 {"se_bclri", SE_IM5(24,0), SE_IM5_MASK, PPCVLE, PPCNONE, {RX, UI5}},
6305 {"se_bgeni", SE_IM5(24,1), SE_IM5_MASK, PPCVLE, PPCNONE, {RX, UI5}},
6306 {"se_bseti", SE_IM5(25,0), SE_IM5_MASK, PPCVLE, PPCNONE, {RX, UI5}},
6307 {"se_btsti", SE_IM5(25,1), SE_IM5_MASK, PPCVLE, PPCNONE, {RX, UI5}},
6308 {"se_srwi", SE_IM5(26,0), SE_IM5_MASK, PPCVLE, PPCNONE, {RX, UI5}},
6309 {"se_srawi", SE_IM5(26,1), SE_IM5_MASK, PPCVLE, PPCNONE, {RX, UI5}},
6310 {"se_slwi", SE_IM5(27,0), SE_IM5_MASK, PPCVLE, PPCNONE, {RX, UI5}},
6311
6312 {"e_lis", I16L(28,28), I16L_MASK, PPCVLE, PPCNONE, {RD, VLEUIMML}},
6313 {"e_and2is.", I16L(28,29), I16L_MASK, PPCVLE, PPCNONE, {RD, VLEUIMML}},
6314 {"e_or2is", I16L(28,26), I16L_MASK, PPCVLE, PPCNONE, {RD, VLEUIMML}},
6315 {"e_and2i.", I16L(28,25), I16L_MASK, PPCVLE, PPCNONE, {RD, VLEUIMML}},
6316 {"e_or2i", I16L(28,24), I16L_MASK, PPCVLE, PPCNONE, {RD, VLEUIMML}},
6317 {"e_cmphl16i", IA16(28,23), IA16_MASK, PPCVLE, PPCNONE, {RA, VLEUIMM}},
6318 {"e_cmph16i", IA16(28,22), IA16_MASK, PPCVLE, PPCNONE, {RA, VLESIMM}},
6319 {"e_cmpl16i", I16A(28,21), I16A_MASK, PPCVLE, PPCNONE, {RA, VLEUIMM}},
6320 {"e_cmplwi", I16A(28,21), I16A_MASK, PPCVLE, PPCNONE, {RA, VLESIMM}},
6321 {"e_mull2i", I16A(28,20), I16A_MASK, PPCVLE, PPCNONE, {RA, VLESIMM}},
6322 {"e_cmp16i", IA16(28,19), IA16_MASK, PPCVLE, PPCNONE, {RA, VLESIMM}},
6323 {"e_cmpwi", IA16(28,19), IA16_MASK, PPCVLE, PPCNONE, {RA, VLESIMM}},
6324 {"e_sub2is", I16A(28,18), I16A_MASK, PPCVLE, PPCNONE, {RA, VLENSIMM}},
6325 {"e_add2is", I16A(28,18), I16A_MASK, PPCVLE, PPCNONE, {RA, VLESIMM}},
6326 {"e_sub2i.", I16A(28,17), I16A_MASK, PPCVLE, PPCNONE, {RA, VLENSIMM}},
6327 {"e_add2i.", I16A(28,17), I16A_MASK, PPCVLE, PPCNONE, {RA, VLESIMM}},
6328 {"e_li", LI20(28,0), LI20_MASK, PPCVLE, PPCNONE, {RT, IMM20}},
6329 {"e_rlwimi", M(29,0), M_MASK, PPCVLE, PPCNONE, {RA, RS, SH, MB, ME}},
6330 {"e_rlwinm", M(29,1), M_MASK, PPCVLE, PPCNONE, {RA, RT, SH, MBE, ME}},
6331 {"e_b", BD24(30,0,0), BD24_MASK, PPCVLE, PPCNONE, {B24}},
6332 {"e_bl", BD24(30,0,1), BD24_MASK, PPCVLE, PPCNONE, {B24}},
6333 {"e_bdnz", EBD15(30,8,BO32DNZ,0), EBD15_MASK, PPCVLE, PPCNONE, {B15}},
6334 {"e_bdnzl", EBD15(30,8,BO32DNZ,1), EBD15_MASK, PPCVLE, PPCNONE, {B15}},
6335 {"e_bdz", EBD15(30,8,BO32DZ,0), EBD15_MASK, PPCVLE, PPCNONE, {B15}},
6336 {"e_bdzl", EBD15(30,8,BO32DZ,1), EBD15_MASK, PPCVLE, PPCNONE, {B15}},
6337 {"e_bge", EBD15BI(30,8,BO32F,CBLT,0), EBD15BI_MASK, PPCVLE, PPCNONE, {CRS,B15}},
6338 {"e_bgel", EBD15BI(30,8,BO32F,CBLT,1), EBD15BI_MASK, PPCVLE, PPCNONE, {CRS,B15}},
6339 {"e_bnl", EBD15BI(30,8,BO32F,CBLT,0), EBD15BI_MASK, PPCVLE, PPCNONE, {CRS,B15}},
6340 {"e_bnll", EBD15BI(30,8,BO32F,CBLT,1), EBD15BI_MASK, PPCVLE, PPCNONE, {CRS,B15}},
6341 {"e_blt", EBD15BI(30,8,BO32T,CBLT,0), EBD15BI_MASK, PPCVLE, PPCNONE, {CRS,B15}},
6342 {"e_bltl", EBD15BI(30,8,BO32T,CBLT,1), EBD15BI_MASK, PPCVLE, PPCNONE, {CRS,B15}},
6343 {"e_bgt", EBD15BI(30,8,BO32T,CBGT,0), EBD15BI_MASK, PPCVLE, PPCNONE, {CRS,B15}},
6344 {"e_bgtl", EBD15BI(30,8,BO32T,CBGT,1), EBD15BI_MASK, PPCVLE, PPCNONE, {CRS,B15}},
6345 {"e_ble", EBD15BI(30,8,BO32F,CBGT,0), EBD15BI_MASK, PPCVLE, PPCNONE, {CRS,B15}},
6346 {"e_blel", EBD15BI(30,8,BO32F,CBGT,1), EBD15BI_MASK, PPCVLE, PPCNONE, {CRS,B15}},
6347 {"e_bng", EBD15BI(30,8,BO32F,CBGT,0), EBD15BI_MASK, PPCVLE, PPCNONE, {CRS,B15}},
6348 {"e_bngl", EBD15BI(30,8,BO32F,CBGT,1), EBD15BI_MASK, PPCVLE, PPCNONE, {CRS,B15}},
6349 {"e_bne", EBD15BI(30,8,BO32F,CBEQ,0), EBD15BI_MASK, PPCVLE, PPCNONE, {CRS,B15}},
6350 {"e_bnel", EBD15BI(30,8,BO32F,CBEQ,1), EBD15BI_MASK, PPCVLE, PPCNONE, {CRS,B15}},
6351 {"e_beq", EBD15BI(30,8,BO32T,CBEQ,0), EBD15BI_MASK, PPCVLE, PPCNONE, {CRS,B15}},
6352 {"e_beql", EBD15BI(30,8,BO32T,CBEQ,1), EBD15BI_MASK, PPCVLE, PPCNONE, {CRS,B15}},
6353 {"e_bso", EBD15BI(30,8,BO32T,CBSO,0), EBD15BI_MASK, PPCVLE, PPCNONE, {CRS,B15}},
6354 {"e_bsol", EBD15BI(30,8,BO32T,CBSO,1), EBD15BI_MASK, PPCVLE, PPCNONE, {CRS,B15}},
6355 {"e_bun", EBD15BI(30,8,BO32T,CBSO,0), EBD15BI_MASK, PPCVLE, PPCNONE, {CRS,B15}},
6356 {"e_bunl", EBD15BI(30,8,BO32T,CBSO,1), EBD15BI_MASK, PPCVLE, PPCNONE, {CRS,B15}},
6357 {"e_bns", EBD15BI(30,8,BO32F,CBSO,0), EBD15BI_MASK, PPCVLE, PPCNONE, {CRS,B15}},
6358 {"e_bnsl", EBD15BI(30,8,BO32F,CBSO,1), EBD15BI_MASK, PPCVLE, PPCNONE, {CRS,B15}},
6359 {"e_bnu", EBD15BI(30,8,BO32F,CBSO,0), EBD15BI_MASK, PPCVLE, PPCNONE, {CRS,B15}},
6360 {"e_bnul", EBD15BI(30,8,BO32F,CBSO,1), EBD15BI_MASK, PPCVLE, PPCNONE, {CRS,B15}},
6361 {"e_bc", BD15(30,8,0), BD15_MASK, PPCVLE, PPCNONE, {BO32, BI32, B15}},
6362 {"e_bcl", BD15(30,8,1), BD15_MASK, PPCVLE, PPCNONE, {BO32, BI32, B15}},
6363
6364 {"e_bf", EBD15(30,8,BO32F,0), EBD15_MASK, PPCVLE, PPCNONE, {BI32,B15}},
6365 {"e_bfl", EBD15(30,8,BO32F,1), EBD15_MASK, PPCVLE, PPCNONE, {BI32,B15}},
6366 {"e_bt", EBD15(30,8,BO32T,0), EBD15_MASK, PPCVLE, PPCNONE, {BI32,B15}},
6367 {"e_btl", EBD15(30,8,BO32T,1), EBD15_MASK, PPCVLE, PPCNONE, {BI32,B15}},
6368
6369 {"e_cmph", X(31,14), X_MASK, PPCVLE, PPCNONE, {CRD, RA, RB}},
6370 {"e_cmphl", X(31,46), X_MASK, PPCVLE, PPCNONE, {CRD, RA, RB}},
6371 {"e_crandc", XL(31,129), XL_MASK, PPCVLE, PPCNONE, {BT, BA, BB}},
6372 {"e_crnand", XL(31,225), XL_MASK, PPCVLE, PPCNONE, {BT, BA, BB}},
6373 {"e_crnot", XL(31,33), XL_MASK, PPCVLE, PPCNONE, {BT, BA, BBA}},
6374 {"e_crnor", XL(31,33), XL_MASK, PPCVLE, PPCNONE, {BT, BA, BB}},
6375 {"e_crclr", XL(31,193), XL_MASK, PPCVLE, PPCNONE, {BT, BAT, BBA}},
6376 {"e_crxor", XL(31,193), XL_MASK, PPCVLE, PPCNONE, {BT, BA, BB}},
6377 {"e_mcrf", XL(31,16), XL_MASK, PPCVLE, PPCNONE, {CRD, CR}},
6378 {"e_slwi", EX(31,112), EX_MASK, PPCVLE, PPCNONE, {RA, RS, SH}},
6379 {"e_slwi.", EX(31,113), EX_MASK, PPCVLE, PPCNONE, {RA, RS, SH}},
6380
6381 {"e_crand", XL(31,257), XL_MASK, PPCVLE, PPCNONE, {BT, BA, BB}},
6382
6383 {"e_rlw", EX(31,560), EX_MASK, PPCVLE, PPCNONE, {RA, RS, RB}},
6384 {"e_rlw.", EX(31,561), EX_MASK, PPCVLE, PPCNONE, {RA, RS, RB}},
6385
6386 {"e_crset", XL(31,289), XL_MASK, PPCVLE, PPCNONE, {BT, BAT, BBA}},
6387 {"e_creqv", XL(31,289), XL_MASK, PPCVLE, PPCNONE, {BT, BA, BB}},
6388
6389 {"e_rlwi", EX(31,624), EX_MASK, PPCVLE, PPCNONE, {RA, RS, SH}},
6390 {"e_rlwi.", EX(31,625), EX_MASK, PPCVLE, PPCNONE, {RA, RS, SH}},
6391
6392 {"e_crorc", XL(31,417), XL_MASK, PPCVLE, PPCNONE, {BT, BA, BB}},
6393
6394 {"e_crmove", XL(31,449), XL_MASK, PPCVLE, PPCNONE, {BT, BA, BBA}},
6395 {"e_cror", XL(31,449), XL_MASK, PPCVLE, PPCNONE, {BT, BA, BB}},
6396
6397 {"mtmas1", XSPR(31,467,625), XSPR_MASK, PPCVLE, PPCNONE, {RS}},
6398
6399 {"e_srwi", EX(31,1136), EX_MASK, PPCVLE, PPCNONE, {RA, RS, SH}},
6400 {"e_srwi.", EX(31,1137), EX_MASK, PPCVLE, PPCNONE, {RA, RS, SH}},
6401
6402 {"se_lbz", SD4(8), SD4_MASK, PPCVLE, PPCNONE, {RZ, SE_SD, RX}},
6403
6404 {"se_stb", SD4(9), SD4_MASK, PPCVLE, PPCNONE, {RZ, SE_SD, RX}},
6405
6406 {"se_lhz", SD4(10), SD4_MASK, PPCVLE, PPCNONE, {RZ, SE_SDH, RX}},
6407
6408 {"se_sth", SD4(11), SD4_MASK, PPCVLE, PPCNONE, {RZ, SE_SDH, RX}},
6409
6410 {"se_lwz", SD4(12), SD4_MASK, PPCVLE, PPCNONE, {RZ, SE_SDW, RX}},
6411
6412 {"se_stw", SD4(13), SD4_MASK, PPCVLE, PPCNONE, {RZ, SE_SDW, RX}},
6413
6414 {"se_bge", EBD8IO(28,0,0), EBD8IO3_MASK, PPCVLE, PPCNONE, {B8}},
6415 {"se_bnl", EBD8IO(28,0,0), EBD8IO3_MASK, PPCVLE, PPCNONE, {B8}},
6416 {"se_ble", EBD8IO(28,0,1), EBD8IO3_MASK, PPCVLE, PPCNONE, {B8}},
6417 {"se_bng", EBD8IO(28,0,1), EBD8IO3_MASK, PPCVLE, PPCNONE, {B8}},
6418 {"se_bne", EBD8IO(28,0,2), EBD8IO3_MASK, PPCVLE, PPCNONE, {B8}},
6419 {"se_bns", EBD8IO(28,0,3), EBD8IO3_MASK, PPCVLE, PPCNONE, {B8}},
6420 {"se_bnu", EBD8IO(28,0,3), EBD8IO3_MASK, PPCVLE, PPCNONE, {B8}},
6421 {"se_bf", EBD8IO(28,0,0), EBD8IO2_MASK, PPCVLE, PPCNONE, {BI16, B8}},
6422 {"se_blt", EBD8IO(28,1,0), EBD8IO3_MASK, PPCVLE, PPCNONE, {B8}},
6423 {"se_bgt", EBD8IO(28,1,1), EBD8IO3_MASK, PPCVLE, PPCNONE, {B8}},
6424 {"se_beq", EBD8IO(28,1,2), EBD8IO3_MASK, PPCVLE, PPCNONE, {B8}},
6425 {"se_bso", EBD8IO(28,1,3), EBD8IO3_MASK, PPCVLE, PPCNONE, {B8}},
6426 {"se_bun", EBD8IO(28,1,3), EBD8IO3_MASK, PPCVLE, PPCNONE, {B8}},
6427 {"se_bt", EBD8IO(28,1,0), EBD8IO2_MASK, PPCVLE, PPCNONE, {BI16, B8}},
6428 {"se_bc", BD8IO(28), BD8IO_MASK, PPCVLE, PPCNONE, {BO16, BI16, B8}},
6429 {"se_b", BD8(58,0,0), BD8_MASK, PPCVLE, PPCNONE, {B8}},
6430 {"se_bl", BD8(58,0,1), BD8_MASK, PPCVLE, PPCNONE, {B8}},
6431 };
6432
6433 const int vle_num_opcodes =
6434 sizeof (vle_opcodes) / sizeof (vle_opcodes[0]);
6435 \f
6436 /* The macro table. This is only used by the assembler. */
6437
6438 /* The expressions of the form (-x ! 31) & (x | 31) have the value 0
6439 when x=0; 32-x when x is between 1 and 31; are negative if x is
6440 negative; and are 32 or more otherwise. This is what you want
6441 when, for instance, you are emulating a right shift by a
6442 rotate-left-and-mask, because the underlying instructions support
6443 shifts of size 0 but not shifts of size 32. By comparison, when
6444 extracting x bits from some word you want to use just 32-x, because
6445 the underlying instructions don't support extracting 0 bits but do
6446 support extracting the whole word (32 bits in this case). */
6447
6448 const struct powerpc_macro powerpc_macros[] = {
6449 {"extldi", 4, PPC64, "rldicr %0,%1,%3,(%2)-1"},
6450 {"extldi.", 4, PPC64, "rldicr. %0,%1,%3,(%2)-1"},
6451 {"extrdi", 4, PPC64, "rldicl %0,%1,((%2)+(%3))&((%2)+(%3)<>64),64-(%2)"},
6452 {"extrdi.", 4, PPC64, "rldicl. %0,%1,((%2)+(%3))&((%2)+(%3)<>64),64-(%2)"},
6453 {"insrdi", 4, PPC64, "rldimi %0,%1,64-((%2)+(%3)),%3"},
6454 {"insrdi.", 4, PPC64, "rldimi. %0,%1,64-((%2)+(%3)),%3"},
6455 {"rotrdi", 3, PPC64, "rldicl %0,%1,(-(%2)!63)&((%2)|63),0"},
6456 {"rotrdi.", 3, PPC64, "rldicl. %0,%1,(-(%2)!63)&((%2)|63),0"},
6457 {"sldi", 3, PPC64, "rldicr %0,%1,%2,63-(%2)"},
6458 {"sldi.", 3, PPC64, "rldicr. %0,%1,%2,63-(%2)"},
6459 {"srdi", 3, PPC64, "rldicl %0,%1,(-(%2)!63)&((%2)|63),%2"},
6460 {"srdi.", 3, PPC64, "rldicl. %0,%1,(-(%2)!63)&((%2)|63),%2"},
6461 {"clrrdi", 3, PPC64, "rldicr %0,%1,0,63-(%2)"},
6462 {"clrrdi.", 3, PPC64, "rldicr. %0,%1,0,63-(%2)"},
6463 {"clrlsldi", 4, PPC64, "rldic %0,%1,%3,(%2)-(%3)"},
6464 {"clrlsldi.",4, PPC64, "rldic. %0,%1,%3,(%2)-(%3)"},
6465
6466 {"extlwi", 4, PPCCOM, "rlwinm %0,%1,%3,0,(%2)-1"},
6467 {"extlwi.", 4, PPCCOM, "rlwinm. %0,%1,%3,0,(%2)-1"},
6468 {"extrwi", 4, PPCCOM, "rlwinm %0,%1,((%2)+(%3))&((%2)+(%3)<>32),32-(%2),31"},
6469 {"extrwi.", 4, PPCCOM, "rlwinm. %0,%1,((%2)+(%3))&((%2)+(%3)<>32),32-(%2),31"},
6470 {"inslwi", 4, PPCCOM, "rlwimi %0,%1,(-(%3)!31)&((%3)|31),%3,(%2)+(%3)-1"},
6471 {"inslwi.", 4, PPCCOM, "rlwimi. %0,%1,(-(%3)!31)&((%3)|31),%3,(%2)+(%3)-1"},
6472 {"insrwi", 4, PPCCOM, "rlwimi %0,%1,32-((%2)+(%3)),%3,(%2)+(%3)-1"},
6473 {"insrwi.", 4, PPCCOM, "rlwimi. %0,%1,32-((%2)+(%3)),%3,(%2)+(%3)-1"},
6474 {"rotrwi", 3, PPCCOM, "rlwinm %0,%1,(-(%2)!31)&((%2)|31),0,31"},
6475 {"rotrwi.", 3, PPCCOM, "rlwinm. %0,%1,(-(%2)!31)&((%2)|31),0,31"},
6476 {"slwi", 3, PPCCOM, "rlwinm %0,%1,%2,0,31-(%2)"},
6477 {"sli", 3, PWRCOM, "rlinm %0,%1,%2,0,31-(%2)"},
6478 {"slwi.", 3, PPCCOM, "rlwinm. %0,%1,%2,0,31-(%2)"},
6479 {"sli.", 3, PWRCOM, "rlinm. %0,%1,%2,0,31-(%2)"},
6480 {"srwi", 3, PPCCOM, "rlwinm %0,%1,(-(%2)!31)&((%2)|31),%2,31"},
6481 {"sri", 3, PWRCOM, "rlinm %0,%1,(-(%2)!31)&((%2)|31),%2,31"},
6482 {"srwi.", 3, PPCCOM, "rlwinm. %0,%1,(-(%2)!31)&((%2)|31),%2,31"},
6483 {"sri.", 3, PWRCOM, "rlinm. %0,%1,(-(%2)!31)&((%2)|31),%2,31"},
6484 {"clrrwi", 3, PPCCOM, "rlwinm %0,%1,0,0,31-(%2)"},
6485 {"clrrwi.", 3, PPCCOM, "rlwinm. %0,%1,0,0,31-(%2)"},
6486 {"clrlslwi", 4, PPCCOM, "rlwinm %0,%1,%3,(%2)-(%3),31-(%3)"},
6487 {"clrlslwi.",4, PPCCOM, "rlwinm. %0,%1,%3,(%2)-(%3),31-(%3)"},
6488
6489 {"e_extlwi", 4, PPCVLE, "e_rlwinm %0,%1,%3,0,(%2)-1"},
6490 {"e_extrwi", 4, PPCVLE, "e_rlwinm %0,%1,((%2)+(%3))&((%2)+(%3)<>32),32-(%2),31"},
6491 {"e_inslwi", 4, PPCVLE, "e_rlwimi %0,%1,(-(%3)!31)&((%3)|31),%3,(%2)+(%3)-1"},
6492 {"e_insrwi", 4, PPCVLE, "e_rlwimi %0,%1,32-((%2)+(%3)),%3,(%2)+(%3)-1"},
6493 {"e_rotlwi", 3, PPCVLE, "e_rlwinm %0,%1,%2,0,31"},
6494 {"e_rotrwi", 3, PPCVLE, "e_rlwinm %0,%1,(-(%2)!31)&((%2)|31),0,31"},
6495 {"e_slwi", 3, PPCVLE, "e_rlwinm %0,%1,%2,0,31-(%2)"},
6496 {"e_srwi", 3, PPCVLE, "e_rlwinm %0,%1,(-(%2)!31)&((%2)|31),%2,31"},
6497 {"e_clrlwi", 3, PPCVLE, "e_rlwinm %0,%1,0,%2,31"},
6498 {"e_clrrwi", 3, PPCVLE, "e_rlwinm %0,%1,0,0,31-(%2)"},
6499 {"e_clrlslwi",4, PPCVLE, "e_rlwinm %0,%1,%3,(%2)-(%3),31-(%3)"},
6500 };
6501
6502 const int powerpc_num_macros =
6503 sizeof (powerpc_macros) / sizeof (powerpc_macros[0]);
GDB Binutils - Deliverables
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