1 /* ppc-opc.c -- PowerPC opcode list
2 Copyright 1994, 1995, 1996, 1997, 1998, 2000, 2001, 2002, 2003, 2004,
3 2005, 2006, 2007, 2008 Free Software Foundation, Inc.
4 Written by Ian Lance Taylor, Cygnus Support
6 This file is part of the GNU opcodes library.
8 This library is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3, or (at your option)
13 It is distributed in the hope that it will be useful, but WITHOUT
14 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
15 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
16 License for more details.
18 You should have received a copy of the GNU General Public License
19 along with this file; see the file COPYING. If not, write to the
20 Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston,
21 MA 02110-1301, USA. */
25 #include "opcode/ppc.h"
28 /* This file holds the PowerPC opcode table. The opcode table
29 includes almost all of the extended instruction mnemonics. This
30 permits the disassembler to use them, and simplifies the assembler
31 logic, at the cost of increasing the table size. The table is
32 strictly constant data, so the compiler should be able to put it in
35 This file also holds the operand table. All knowledge about
36 inserting operands into instructions and vice-versa is kept in this
39 /* Local insertion and extraction functions. */
41 static unsigned long insert_bat (unsigned long, long, ppc_cpu_t
, const char **);
42 static long extract_bat (unsigned long, ppc_cpu_t
, int *);
43 static unsigned long insert_bba (unsigned long, long, ppc_cpu_t
, const char **);
44 static long extract_bba (unsigned long, ppc_cpu_t
, int *);
45 static unsigned long insert_bdm (unsigned long, long, ppc_cpu_t
, const char **);
46 static long extract_bdm (unsigned long, ppc_cpu_t
, int *);
47 static unsigned long insert_bdp (unsigned long, long, ppc_cpu_t
, const char **);
48 static long extract_bdp (unsigned long, ppc_cpu_t
, int *);
49 static unsigned long insert_bo (unsigned long, long, ppc_cpu_t
, const char **);
50 static long extract_bo (unsigned long, ppc_cpu_t
, int *);
51 static unsigned long insert_boe (unsigned long, long, ppc_cpu_t
, const char **);
52 static long extract_boe (unsigned long, ppc_cpu_t
, int *);
53 static unsigned long insert_fxm (unsigned long, long, ppc_cpu_t
, const char **);
54 static long extract_fxm (unsigned long, ppc_cpu_t
, int *);
55 static unsigned long insert_mbe (unsigned long, long, ppc_cpu_t
, const char **);
56 static long extract_mbe (unsigned long, ppc_cpu_t
, int *);
57 static unsigned long insert_mb6 (unsigned long, long, ppc_cpu_t
, const char **);
58 static long extract_mb6 (unsigned long, ppc_cpu_t
, int *);
59 static long extract_nb (unsigned long, ppc_cpu_t
, int *);
60 static unsigned long insert_nsi (unsigned long, long, ppc_cpu_t
, const char **);
61 static long extract_nsi (unsigned long, ppc_cpu_t
, int *);
62 static unsigned long insert_ral (unsigned long, long, ppc_cpu_t
, const char **);
63 static unsigned long insert_ram (unsigned long, long, ppc_cpu_t
, const char **);
64 static unsigned long insert_raq (unsigned long, long, ppc_cpu_t
, const char **);
65 static unsigned long insert_ras (unsigned long, long, ppc_cpu_t
, const char **);
66 static unsigned long insert_rbs (unsigned long, long, ppc_cpu_t
, const char **);
67 static long extract_rbs (unsigned long, ppc_cpu_t
, int *);
68 static unsigned long insert_sh6 (unsigned long, long, ppc_cpu_t
, const char **);
69 static long extract_sh6 (unsigned long, ppc_cpu_t
, int *);
70 static unsigned long insert_spr (unsigned long, long, ppc_cpu_t
, const char **);
71 static long extract_spr (unsigned long, ppc_cpu_t
, int *);
72 static unsigned long insert_sprg (unsigned long, long, ppc_cpu_t
, const char **);
73 static long extract_sprg (unsigned long, ppc_cpu_t
, int *);
74 static unsigned long insert_tbr (unsigned long, long, ppc_cpu_t
, const char **);
75 static long extract_tbr (unsigned long, ppc_cpu_t
, int *);
77 /* The operands table.
79 The fields are bitm, shift, insert, extract, flags.
81 We used to put parens around the various additions, like the one
82 for BA just below. However, that caused trouble with feeble
83 compilers with a limit on depth of a parenthesized expression, like
84 (reportedly) the compiler in Microsoft Developer Studio 5. So we
85 omit the parens, since the macros are never used in a context where
86 the addition will be ambiguous. */
88 const struct powerpc_operand powerpc_operands
[] =
90 /* The zero index is used to indicate the end of the list of
93 { 0, 0, NULL
, NULL
, 0 },
95 /* The BA field in an XL form instruction. */
97 /* The BI field in a B form or XL form instruction. */
99 #define BI_MASK (0x1f << 16)
100 { 0x1f, 16, NULL
, NULL
, PPC_OPERAND_CR
},
102 /* The BA field in an XL form instruction when it must be the same
103 as the BT field in the same instruction. */
105 { 0x1f, 16, insert_bat
, extract_bat
, PPC_OPERAND_FAKE
},
107 /* The BB field in an XL form instruction. */
109 #define BB_MASK (0x1f << 11)
110 { 0x1f, 11, NULL
, NULL
, PPC_OPERAND_CR
},
112 /* The BB field in an XL form instruction when it must be the same
113 as the BA field in the same instruction. */
115 { 0x1f, 11, insert_bba
, extract_bba
, PPC_OPERAND_FAKE
},
117 /* The BD field in a B form instruction. The lower two bits are
120 { 0xfffc, 0, NULL
, NULL
, PPC_OPERAND_RELATIVE
| PPC_OPERAND_SIGNED
},
122 /* The BD field in a B form instruction when absolute addressing is
125 { 0xfffc, 0, NULL
, NULL
, PPC_OPERAND_ABSOLUTE
| PPC_OPERAND_SIGNED
},
127 /* The BD field in a B form instruction when the - modifier is used.
128 This sets the y bit of the BO field appropriately. */
130 { 0xfffc, 0, insert_bdm
, extract_bdm
,
131 PPC_OPERAND_RELATIVE
| PPC_OPERAND_SIGNED
},
133 /* The BD field in a B form instruction when the - modifier is used
134 and absolute address is used. */
136 { 0xfffc, 0, insert_bdm
, extract_bdm
,
137 PPC_OPERAND_ABSOLUTE
| PPC_OPERAND_SIGNED
},
139 /* The BD field in a B form instruction when the + modifier is used.
140 This sets the y bit of the BO field appropriately. */
142 { 0xfffc, 0, insert_bdp
, extract_bdp
,
143 PPC_OPERAND_RELATIVE
| PPC_OPERAND_SIGNED
},
145 /* The BD field in a B form instruction when the + modifier is used
146 and absolute addressing is used. */
148 { 0xfffc, 0, insert_bdp
, extract_bdp
,
149 PPC_OPERAND_ABSOLUTE
| PPC_OPERAND_SIGNED
},
151 /* The BF field in an X or XL form instruction. */
153 /* The CRFD field in an X form instruction. */
155 { 0x7, 23, NULL
, NULL
, PPC_OPERAND_CR
},
157 /* The BF field in an X or XL form instruction. */
159 { 0x7, 23, NULL
, NULL
, 0 },
161 /* An optional BF field. This is used for comparison instructions,
162 in which an omitted BF field is taken as zero. */
164 { 0x7, 23, NULL
, NULL
, PPC_OPERAND_CR
| PPC_OPERAND_OPTIONAL
},
166 /* The BFA field in an X or XL form instruction. */
168 { 0x7, 18, NULL
, NULL
, PPC_OPERAND_CR
},
170 /* The BO field in a B form instruction. Certain values are
173 #define BO_MASK (0x1f << 21)
174 { 0x1f, 21, insert_bo
, extract_bo
, 0 },
176 /* The BO field in a B form instruction when the + or - modifier is
177 used. This is like the BO field, but it must be even. */
179 { 0x1e, 21, insert_boe
, extract_boe
, 0 },
182 { 0x3, 11, NULL
, NULL
, PPC_OPERAND_OPTIONAL
},
184 /* The BT field in an X or XL form instruction. */
186 { 0x1f, 21, NULL
, NULL
, PPC_OPERAND_CR
},
188 /* The condition register number portion of the BI field in a B form
189 or XL form instruction. This is used for the extended
190 conditional branch mnemonics, which set the lower two bits of the
191 BI field. This field is optional. */
193 { 0x7, 18, NULL
, NULL
, PPC_OPERAND_CR
| PPC_OPERAND_OPTIONAL
},
195 /* The CRB field in an X form instruction. */
197 /* The MB field in an M form instruction. */
199 #define MB_MASK (0x1f << 6)
200 { 0x1f, 6, NULL
, NULL
, 0 },
202 /* The CRFS field in an X form instruction. */
204 { 0x7, 0, NULL
, NULL
, PPC_OPERAND_CR
},
206 /* The CT field in an X form instruction. */
208 /* The MO field in an mbar instruction. */
210 { 0x1f, 21, NULL
, NULL
, PPC_OPERAND_OPTIONAL
},
212 /* The D field in a D form instruction. This is a displacement off
213 a register, and implies that the next operand is a register in
216 { 0xffff, 0, NULL
, NULL
, PPC_OPERAND_PARENS
| PPC_OPERAND_SIGNED
},
218 /* The DE field in a DE form instruction. This is like D, but is 12
221 { 0xfff, 4, NULL
, NULL
, PPC_OPERAND_PARENS
| PPC_OPERAND_SIGNED
},
223 /* The DES field in a DES form instruction. This is like DS, but is 14
224 bits only (12 stored.) */
226 { 0x3ffc, 2, NULL
, NULL
, PPC_OPERAND_PARENS
| PPC_OPERAND_SIGNED
},
228 /* The DQ field in a DQ form instruction. This is like D, but the
229 lower four bits are forced to zero. */
231 { 0xfff0, 0, NULL
, NULL
,
232 PPC_OPERAND_PARENS
| PPC_OPERAND_SIGNED
| PPC_OPERAND_DQ
},
234 /* The DS field in a DS form instruction. This is like D, but the
235 lower two bits are forced to zero. */
237 { 0xfffc, 0, NULL
, NULL
,
238 PPC_OPERAND_PARENS
| PPC_OPERAND_SIGNED
| PPC_OPERAND_DS
},
240 /* The DUIS field in a XFX form instruction, 10 bits unsigned imediate */
242 { 0x3ff, 11, NULL
, NULL
, 0 },
244 /* The E field in a wrteei instruction. */
245 /* And the W bit in the pair singles instructions. */
248 { 0x1, 15, NULL
, NULL
, 0 },
250 /* The FL1 field in a POWER SC form instruction. */
252 /* The U field in an X form instruction. */
254 { 0xf, 12, NULL
, NULL
, 0 },
256 /* The FL2 field in a POWER SC form instruction. */
258 { 0x7, 2, NULL
, NULL
, 0 },
260 /* The FLM field in an XFL form instruction. */
262 { 0xff, 17, NULL
, NULL
, 0 },
264 /* The FRA field in an X or A form instruction. */
266 #define FRA_MASK (0x1f << 16)
267 { 0x1f, 16, NULL
, NULL
, PPC_OPERAND_FPR
},
269 /* The FRB field in an X or A form instruction. */
271 #define FRB_MASK (0x1f << 11)
272 { 0x1f, 11, NULL
, NULL
, PPC_OPERAND_FPR
},
274 /* The FRC field in an A form instruction. */
276 #define FRC_MASK (0x1f << 6)
277 { 0x1f, 6, NULL
, NULL
, PPC_OPERAND_FPR
},
279 /* The FRS field in an X form instruction or the FRT field in a D, X
280 or A form instruction. */
283 { 0x1f, 21, NULL
, NULL
, PPC_OPERAND_FPR
},
285 /* The FXM field in an XFX instruction. */
287 { 0xff, 12, insert_fxm
, extract_fxm
, 0 },
289 /* Power4 version for mfcr. */
291 { 0xff, 12, insert_fxm
, extract_fxm
, PPC_OPERAND_OPTIONAL
},
293 /* The L field in a D or X form instruction. */
295 { 0x1, 21, NULL
, NULL
, PPC_OPERAND_OPTIONAL
},
297 /* The LEV field in a POWER SVC form instruction. */
298 #define SVC_LEV L + 1
299 { 0x7f, 5, NULL
, NULL
, 0 },
301 /* The LEV field in an SC form instruction. */
302 #define LEV SVC_LEV + 1
303 { 0x7f, 5, NULL
, NULL
, PPC_OPERAND_OPTIONAL
},
305 /* The LI field in an I form instruction. The lower two bits are
308 { 0x3fffffc, 0, NULL
, NULL
, PPC_OPERAND_RELATIVE
| PPC_OPERAND_SIGNED
},
310 /* The LI field in an I form instruction when used as an absolute
313 { 0x3fffffc, 0, NULL
, NULL
, PPC_OPERAND_ABSOLUTE
| PPC_OPERAND_SIGNED
},
315 /* The LS field in an X (sync) form instruction. */
317 { 0x3, 21, NULL
, NULL
, PPC_OPERAND_OPTIONAL
},
319 /* The ME field in an M form instruction. */
321 #define ME_MASK (0x1f << 1)
322 { 0x1f, 1, NULL
, NULL
, 0 },
324 /* The MB and ME fields in an M form instruction expressed a single
325 operand which is a bitmask indicating which bits to select. This
326 is a two operand form using PPC_OPERAND_NEXT. See the
327 description in opcode/ppc.h for what this means. */
329 { 0x1f, 6, NULL
, NULL
, PPC_OPERAND_OPTIONAL
| PPC_OPERAND_NEXT
},
330 { -1, 0, insert_mbe
, extract_mbe
, 0 },
332 /* The MB or ME field in an MD or MDS form instruction. The high
333 bit is wrapped to the low end. */
336 #define MB6_MASK (0x3f << 5)
337 { 0x3f, 5, insert_mb6
, extract_mb6
, 0 },
339 /* The NB field in an X form instruction. The value 32 is stored as
342 { 0x1f, 11, NULL
, extract_nb
, PPC_OPERAND_PLUS1
},
344 /* The NSI field in a D form instruction. This is the same as the
345 SI field, only negated. */
347 { 0xffff, 0, insert_nsi
, extract_nsi
,
348 PPC_OPERAND_NEGATIVE
| PPC_OPERAND_SIGNED
},
350 /* The RA field in an D, DS, DQ, X, XO, M, or MDS form instruction. */
352 #define RA_MASK (0x1f << 16)
353 { 0x1f, 16, NULL
, NULL
, PPC_OPERAND_GPR
},
355 /* As above, but 0 in the RA field means zero, not r0. */
357 { 0x1f, 16, NULL
, NULL
, PPC_OPERAND_GPR_0
},
359 /* The RA field in the DQ form lq instruction, which has special
360 value restrictions. */
362 { 0x1f, 16, insert_raq
, NULL
, PPC_OPERAND_GPR_0
},
364 /* The RA field in a D or X form instruction which is an updating
365 load, which means that the RA field may not be zero and may not
366 equal the RT field. */
368 { 0x1f, 16, insert_ral
, NULL
, PPC_OPERAND_GPR_0
},
370 /* The RA field in an lmw instruction, which has special value
373 { 0x1f, 16, insert_ram
, NULL
, PPC_OPERAND_GPR_0
},
375 /* The RA field in a D or X form instruction which is an updating
376 store or an updating floating point load, which means that the RA
377 field may not be zero. */
379 { 0x1f, 16, insert_ras
, NULL
, PPC_OPERAND_GPR_0
},
381 /* The RA field of the tlbwe instruction, which is optional. */
382 #define RAOPT RAS + 1
383 { 0x1f, 16, NULL
, NULL
, PPC_OPERAND_GPR
| PPC_OPERAND_OPTIONAL
},
385 /* The RB field in an X, XO, M, or MDS form instruction. */
387 #define RB_MASK (0x1f << 11)
388 { 0x1f, 11, NULL
, NULL
, PPC_OPERAND_GPR
},
390 /* The RB field in an X form instruction when it must be the same as
391 the RS field in the instruction. This is used for extended
392 mnemonics like mr. */
394 { 0x1f, 11, insert_rbs
, extract_rbs
, PPC_OPERAND_FAKE
},
396 /* The RS field in a D, DS, X, XFX, XS, M, MD or MDS form
397 instruction or the RT field in a D, DS, X, XFX or XO form
401 #define RT_MASK (0x1f << 21)
402 { 0x1f, 21, NULL
, NULL
, PPC_OPERAND_GPR
},
404 /* The RS and RT fields of the DS form stq instruction, which have
405 special value restrictions. */
408 { 0x1e, 21, NULL
, NULL
, PPC_OPERAND_GPR_0
},
410 /* The RS field of the tlbwe instruction, which is optional. */
413 { 0x1f, 21, NULL
, NULL
, PPC_OPERAND_GPR
| PPC_OPERAND_OPTIONAL
},
415 /* The SH field in an X or M form instruction. */
417 #define SH_MASK (0x1f << 11)
418 /* The other UIMM field in a EVX form instruction. */
420 { 0x1f, 11, NULL
, NULL
, 0 },
422 /* The SH field in an MD form instruction. This is split. */
424 #define SH6_MASK ((0x1f << 11) | (1 << 1))
425 { 0x3f, -1, insert_sh6
, extract_sh6
, 0 },
427 /* The SH field of the tlbwe instruction, which is optional. */
429 { 0x1f, 11, NULL
, NULL
, PPC_OPERAND_OPTIONAL
},
431 /* The SI field in a D form instruction. */
433 { 0xffff, 0, NULL
, NULL
, PPC_OPERAND_SIGNED
},
435 /* The SI field in a D form instruction when we accept a wide range
436 of positive values. */
437 #define SISIGNOPT SI + 1
438 { 0xffff, 0, NULL
, NULL
, PPC_OPERAND_SIGNED
| PPC_OPERAND_SIGNOPT
},
440 /* The SPR field in an XFX form instruction. This is flipped--the
441 lower 5 bits are stored in the upper 5 and vice- versa. */
442 #define SPR SISIGNOPT + 1
444 #define SPR_MASK (0x3ff << 11)
445 { 0x3ff, 11, insert_spr
, extract_spr
, 0 },
447 /* The BAT index number in an XFX form m[ft]ibat[lu] instruction. */
448 #define SPRBAT SPR + 1
449 #define SPRBAT_MASK (0x3 << 17)
450 { 0x3, 17, NULL
, NULL
, 0 },
452 /* The SPRG register number in an XFX form m[ft]sprg instruction. */
453 #define SPRG SPRBAT + 1
454 { 0x1f, 16, insert_sprg
, extract_sprg
, 0 },
456 /* The SR field in an X form instruction. */
458 { 0xf, 16, NULL
, NULL
, 0 },
460 /* The STRM field in an X AltiVec form instruction. */
462 /* The T field in a tlbilx form instruction. */
464 { 0x3, 21, NULL
, NULL
, 0 },
466 /* The SV field in a POWER SC form instruction. */
468 { 0x3fff, 2, NULL
, NULL
, 0 },
470 /* The TBR field in an XFX form instruction. This is like the SPR
471 field, but it is optional. */
473 { 0x3ff, 11, insert_tbr
, extract_tbr
, PPC_OPERAND_OPTIONAL
},
475 /* The TO field in a D or X form instruction. */
478 #define TO_MASK (0x1f << 21)
479 { 0x1f, 21, NULL
, NULL
, 0 },
481 /* The UI field in a D form instruction. */
483 { 0xffff, 0, NULL
, NULL
, 0 },
485 /* The VA field in a VA, VX or VXR form instruction. */
487 { 0x1f, 16, NULL
, NULL
, PPC_OPERAND_VR
},
489 /* The VB field in a VA, VX or VXR form instruction. */
491 { 0x1f, 11, NULL
, NULL
, PPC_OPERAND_VR
},
493 /* The VC field in a VA form instruction. */
495 { 0x1f, 6, NULL
, NULL
, PPC_OPERAND_VR
},
497 /* The VD or VS field in a VA, VX, VXR or X form instruction. */
500 { 0x1f, 21, NULL
, NULL
, PPC_OPERAND_VR
},
502 /* The SIMM field in a VX form instruction, and TE in Z form. */
505 { 0x1f, 16, NULL
, NULL
, PPC_OPERAND_SIGNED
},
507 /* The UIMM field in a VX form instruction. */
508 #define UIMM SIMM + 1
509 { 0x1f, 16, NULL
, NULL
, 0 },
511 /* The SHB field in a VA form instruction. */
513 { 0xf, 6, NULL
, NULL
, 0 },
515 /* The other UIMM field in a half word EVX form instruction. */
516 #define EVUIMM_2 SHB + 1
517 { 0x3e, 10, NULL
, NULL
, PPC_OPERAND_PARENS
},
519 /* The other UIMM field in a word EVX form instruction. */
520 #define EVUIMM_4 EVUIMM_2 + 1
521 { 0x7c, 9, NULL
, NULL
, PPC_OPERAND_PARENS
},
523 /* The other UIMM field in a double EVX form instruction. */
524 #define EVUIMM_8 EVUIMM_4 + 1
525 { 0xf8, 8, NULL
, NULL
, PPC_OPERAND_PARENS
},
528 #define WS EVUIMM_8 + 1
529 { 0x7, 11, NULL
, NULL
, 0 },
531 /* PowerPC paired singles extensions. */
532 /* W bit in the pair singles instructions for x type instructions. */
534 { 0x1, 10, 0, 0, 0 },
536 /* IDX bits for quantization in the pair singles instructions. */
538 { 0x7, 12, 0, 0, 0 },
540 /* IDX bits for quantization in the pair singles x-type instructions. */
544 /* Smaller D field for quantization in the pair singles instructions. */
546 { 0xfff, 0, 0, 0, PPC_OPERAND_PARENS
| PPC_OPERAND_SIGNED
},
551 { 0x1, 16, NULL
, NULL
, PPC_OPERAND_OPTIONAL
},
553 #define RMC MTMSRD_L + 1
554 { 0x3, 9, NULL
, NULL
, 0 },
557 { 0x1, 16, NULL
, NULL
, 0 },
560 { 0x3, 19, NULL
, NULL
, 0 },
563 { 0x1, 20, NULL
, NULL
, 0 },
565 /* SH field starting at bit position 16. */
567 /* The DCM and DGM fields in a Z form instruction. */
570 { 0x3f, 10, NULL
, NULL
, 0 },
572 /* The EH field in larx instruction. */
574 { 0x1, 0, NULL
, NULL
, PPC_OPERAND_OPTIONAL
},
576 /* The L field in an mtfsf or XFL form instruction. */
578 { 0x1, 25, NULL
, NULL
, PPC_OPERAND_OPTIONAL
},
580 /* Xilinx APU related masks and macros */
581 #define FCRT XFL_L + 1
582 #define FCRT_MASK (0x1f << 21)
583 { 0x1f, 21, 0, 0, PPC_OPERAND_FCR
},
585 /* Xilinx FSL related masks and macros */
587 #define FSL_MASK (0x1f << 11)
588 { 0x1f, 11, 0, 0, PPC_OPERAND_FSL
},
590 /* Xilinx UDI related masks and macros */
592 { 0x1f, 21, 0, 0, PPC_OPERAND_UDI
},
595 { 0x1f, 16, 0, 0, PPC_OPERAND_UDI
},
598 { 0x1f, 11, 0, 0, PPC_OPERAND_UDI
},
601 { 0x1f, 6, 0, 0, PPC_OPERAND_UDI
},
605 const unsigned int num_powerpc_operands
= (sizeof (powerpc_operands
)
606 / sizeof (powerpc_operands
[0]));
608 /* The functions used to insert and extract complicated operands. */
610 /* The BA field in an XL form instruction when it must be the same as
611 the BT field in the same instruction. This operand is marked FAKE.
612 The insertion function just copies the BT field into the BA field,
613 and the extraction function just checks that the fields are the
617 insert_bat (unsigned long insn
,
618 long value ATTRIBUTE_UNUSED
,
619 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
620 const char **errmsg ATTRIBUTE_UNUSED
)
622 return insn
| (((insn
>> 21) & 0x1f) << 16);
626 extract_bat (unsigned long insn
,
627 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
630 if (((insn
>> 21) & 0x1f) != ((insn
>> 16) & 0x1f))
635 /* The BB field in an XL form instruction when it must be the same as
636 the BA field in the same instruction. This operand is marked FAKE.
637 The insertion function just copies the BA field into the BB field,
638 and the extraction function just checks that the fields are the
642 insert_bba (unsigned long insn
,
643 long value ATTRIBUTE_UNUSED
,
644 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
645 const char **errmsg ATTRIBUTE_UNUSED
)
647 return insn
| (((insn
>> 16) & 0x1f) << 11);
651 extract_bba (unsigned long insn
,
652 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
655 if (((insn
>> 16) & 0x1f) != ((insn
>> 11) & 0x1f))
660 /* The BD field in a B form instruction when the - modifier is used.
661 This modifier means that the branch is not expected to be taken.
662 For chips built to versions of the architecture prior to version 2
663 (ie. not Power4 compatible), we set the y bit of the BO field to 1
664 if the offset is negative. When extracting, we require that the y
665 bit be 1 and that the offset be positive, since if the y bit is 0
666 we just want to print the normal form of the instruction.
667 Power4 compatible targets use two bits, "a", and "t", instead of
668 the "y" bit. "at" == 00 => no hint, "at" == 01 => unpredictable,
669 "at" == 10 => not taken, "at" == 11 => taken. The "t" bit is 00001
670 in BO field, the "a" bit is 00010 for branch on CR(BI) and 01000
671 for branch on CTR. We only handle the taken/not-taken hint here.
672 Note that we don't relax the conditions tested here when
673 disassembling with -Many because insns using extract_bdm and
674 extract_bdp always occur in pairs. One or the other will always
678 insert_bdm (unsigned long insn
,
681 const char **errmsg ATTRIBUTE_UNUSED
)
683 if ((dialect
& PPC_OPCODE_POWER4
) == 0)
685 if ((value
& 0x8000) != 0)
690 if ((insn
& (0x14 << 21)) == (0x04 << 21))
692 else if ((insn
& (0x14 << 21)) == (0x10 << 21))
695 return insn
| (value
& 0xfffc);
699 extract_bdm (unsigned long insn
,
703 if ((dialect
& PPC_OPCODE_POWER4
) == 0)
705 if (((insn
& (1 << 21)) == 0) != ((insn
& (1 << 15)) == 0))
710 if ((insn
& (0x17 << 21)) != (0x06 << 21)
711 && (insn
& (0x1d << 21)) != (0x18 << 21))
715 return ((insn
& 0xfffc) ^ 0x8000) - 0x8000;
718 /* The BD field in a B form instruction when the + modifier is used.
719 This is like BDM, above, except that the branch is expected to be
723 insert_bdp (unsigned long insn
,
726 const char **errmsg ATTRIBUTE_UNUSED
)
728 if ((dialect
& PPC_OPCODE_POWER4
) == 0)
730 if ((value
& 0x8000) == 0)
735 if ((insn
& (0x14 << 21)) == (0x04 << 21))
737 else if ((insn
& (0x14 << 21)) == (0x10 << 21))
740 return insn
| (value
& 0xfffc);
744 extract_bdp (unsigned long insn
,
748 if ((dialect
& PPC_OPCODE_POWER4
) == 0)
750 if (((insn
& (1 << 21)) == 0) == ((insn
& (1 << 15)) == 0))
755 if ((insn
& (0x17 << 21)) != (0x07 << 21)
756 && (insn
& (0x1d << 21)) != (0x19 << 21))
760 return ((insn
& 0xfffc) ^ 0x8000) - 0x8000;
763 /* Check for legal values of a BO field. */
766 valid_bo (long value
, ppc_cpu_t dialect
, int extract
)
768 if ((dialect
& PPC_OPCODE_POWER4
) == 0)
771 /* Certain encodings have bits that are required to be zero.
772 These are (z must be zero, y may be anything):
779 switch (value
& 0x14)
786 valid
= (value
& 0x2) == 0;
789 valid
= (value
& 0x8) == 0;
792 valid
= value
== 0x14;
795 /* When disassembling with -Many, accept power4 encodings too. */
797 || (dialect
& PPC_OPCODE_ANY
) == 0
802 /* Certain encodings have bits that are required to be zero.
803 These are (z must be zero, a & t may be anything):
814 if ((value
& 0x14) == 0)
815 return (value
& 0x1) == 0;
816 else if ((value
& 0x14) == 0x14)
817 return value
== 0x14;
822 /* The BO field in a B form instruction. Warn about attempts to set
823 the field to an illegal value. */
826 insert_bo (unsigned long insn
,
831 if (!valid_bo (value
, dialect
, 0))
832 *errmsg
= _("invalid conditional option");
833 return insn
| ((value
& 0x1f) << 21);
837 extract_bo (unsigned long insn
,
843 value
= (insn
>> 21) & 0x1f;
844 if (!valid_bo (value
, dialect
, 1))
849 /* The BO field in a B form instruction when the + or - modifier is
850 used. This is like the BO field, but it must be even. When
851 extracting it, we force it to be even. */
854 insert_boe (unsigned long insn
,
859 if (!valid_bo (value
, dialect
, 0))
860 *errmsg
= _("invalid conditional option");
861 else if ((value
& 1) != 0)
862 *errmsg
= _("attempt to set y bit when using + or - modifier");
864 return insn
| ((value
& 0x1f) << 21);
868 extract_boe (unsigned long insn
,
874 value
= (insn
>> 21) & 0x1f;
875 if (!valid_bo (value
, dialect
, 1))
880 /* FXM mask in mfcr and mtcrf instructions. */
883 insert_fxm (unsigned long insn
,
888 /* If we're handling the mfocrf and mtocrf insns ensure that exactly
889 one bit of the mask field is set. */
890 if ((insn
& (1 << 20)) != 0)
892 if (value
== 0 || (value
& -value
) != value
)
894 *errmsg
= _("invalid mask field");
899 /* If the optional field on mfcr is missing that means we want to use
900 the old form of the instruction that moves the whole cr. In that
901 case we'll have VALUE zero. There doesn't seem to be a way to
902 distinguish this from the case where someone writes mfcr %r3,0. */
906 /* If only one bit of the FXM field is set, we can use the new form
907 of the instruction, which is faster. Unlike the Power4 branch hint
908 encoding, this is not backward compatible. Do not generate the
909 new form unless -mpower4 has been given, or -many and the two
910 operand form of mfcr was used. */
911 else if ((value
& -value
) == value
912 && ((dialect
& PPC_OPCODE_POWER4
) != 0
913 || ((dialect
& PPC_OPCODE_ANY
) != 0
914 && (insn
& (0x3ff << 1)) == 19 << 1)))
917 /* Any other value on mfcr is an error. */
918 else if ((insn
& (0x3ff << 1)) == 19 << 1)
920 *errmsg
= _("ignoring invalid mfcr mask");
924 return insn
| ((value
& 0xff) << 12);
928 extract_fxm (unsigned long insn
,
929 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
932 long mask
= (insn
>> 12) & 0xff;
934 /* Is this a Power4 insn? */
935 if ((insn
& (1 << 20)) != 0)
937 /* Exactly one bit of MASK should be set. */
938 if (mask
== 0 || (mask
& -mask
) != mask
)
942 /* Check that non-power4 form of mfcr has a zero MASK. */
943 else if ((insn
& (0x3ff << 1)) == 19 << 1)
952 /* The MB and ME fields in an M form instruction expressed as a single
953 operand which is itself a bitmask. The extraction function always
954 marks it as invalid, since we never want to recognize an
955 instruction which uses a field of this type. */
958 insert_mbe (unsigned long insn
,
960 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
963 unsigned long uval
, mask
;
964 int mb
, me
, mx
, count
, last
;
970 *errmsg
= _("illegal bitmask");
982 /* mb: location of last 0->1 transition */
983 /* me: location of last 1->0 transition */
984 /* count: # transitions */
986 for (mx
= 0, mask
= 1L << 31; mx
< 32; ++mx
, mask
>>= 1)
988 if ((uval
& mask
) && !last
)
994 else if (!(uval
& mask
) && last
)
1004 if (count
!= 2 && (count
!= 0 || ! last
))
1005 *errmsg
= _("illegal bitmask");
1007 return insn
| (mb
<< 6) | ((me
- 1) << 1);
1011 extract_mbe (unsigned long insn
,
1012 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1021 mb
= (insn
>> 6) & 0x1f;
1022 me
= (insn
>> 1) & 0x1f;
1026 for (i
= mb
; i
<= me
; i
++)
1027 ret
|= 1L << (31 - i
);
1029 else if (mb
== me
+ 1)
1031 else /* (mb > me + 1) */
1034 for (i
= me
+ 1; i
< mb
; i
++)
1035 ret
&= ~(1L << (31 - i
));
1040 /* The MB or ME field in an MD or MDS form instruction. The high bit
1041 is wrapped to the low end. */
1043 static unsigned long
1044 insert_mb6 (unsigned long insn
,
1046 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1047 const char **errmsg ATTRIBUTE_UNUSED
)
1049 return insn
| ((value
& 0x1f) << 6) | (value
& 0x20);
1053 extract_mb6 (unsigned long insn
,
1054 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1055 int *invalid ATTRIBUTE_UNUSED
)
1057 return ((insn
>> 6) & 0x1f) | (insn
& 0x20);
1060 /* The NB field in an X form instruction. The value 32 is stored as
1064 extract_nb (unsigned long insn
,
1065 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1066 int *invalid ATTRIBUTE_UNUSED
)
1070 ret
= (insn
>> 11) & 0x1f;
1076 /* The NSI field in a D form instruction. This is the same as the SI
1077 field, only negated. The extraction function always marks it as
1078 invalid, since we never want to recognize an instruction which uses
1079 a field of this type. */
1081 static unsigned long
1082 insert_nsi (unsigned long insn
,
1084 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1085 const char **errmsg ATTRIBUTE_UNUSED
)
1087 return insn
| (-value
& 0xffff);
1091 extract_nsi (unsigned long insn
,
1092 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1096 return -(((insn
& 0xffff) ^ 0x8000) - 0x8000);
1099 /* The RA field in a D or X form instruction which is an updating
1100 load, which means that the RA field may not be zero and may not
1101 equal the RT field. */
1103 static unsigned long
1104 insert_ral (unsigned long insn
,
1106 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1107 const char **errmsg
)
1110 || (unsigned long) value
== ((insn
>> 21) & 0x1f))
1111 *errmsg
= "invalid register operand when updating";
1112 return insn
| ((value
& 0x1f) << 16);
1115 /* The RA field in an lmw instruction, which has special value
1118 static unsigned long
1119 insert_ram (unsigned long insn
,
1121 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1122 const char **errmsg
)
1124 if ((unsigned long) value
>= ((insn
>> 21) & 0x1f))
1125 *errmsg
= _("index register in load range");
1126 return insn
| ((value
& 0x1f) << 16);
1129 /* The RA field in the DQ form lq instruction, which has special
1130 value restrictions. */
1132 static unsigned long
1133 insert_raq (unsigned long insn
,
1135 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1136 const char **errmsg
)
1138 long rtvalue
= (insn
& RT_MASK
) >> 21;
1140 if (value
== rtvalue
)
1141 *errmsg
= _("source and target register operands must be different");
1142 return insn
| ((value
& 0x1f) << 16);
1145 /* The RA field in a D or X form instruction which is an updating
1146 store or an updating floating point load, which means that the RA
1147 field may not be zero. */
1149 static unsigned long
1150 insert_ras (unsigned long insn
,
1152 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1153 const char **errmsg
)
1156 *errmsg
= _("invalid register operand when updating");
1157 return insn
| ((value
& 0x1f) << 16);
1160 /* The RB field in an X form instruction when it must be the same as
1161 the RS field in the instruction. This is used for extended
1162 mnemonics like mr. This operand is marked FAKE. The insertion
1163 function just copies the BT field into the BA field, and the
1164 extraction function just checks that the fields are the same. */
1166 static unsigned long
1167 insert_rbs (unsigned long insn
,
1168 long value ATTRIBUTE_UNUSED
,
1169 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1170 const char **errmsg ATTRIBUTE_UNUSED
)
1172 return insn
| (((insn
>> 21) & 0x1f) << 11);
1176 extract_rbs (unsigned long insn
,
1177 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1180 if (((insn
>> 21) & 0x1f) != ((insn
>> 11) & 0x1f))
1185 /* The SH field in an MD form instruction. This is split. */
1187 static unsigned long
1188 insert_sh6 (unsigned long insn
,
1190 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1191 const char **errmsg ATTRIBUTE_UNUSED
)
1193 return insn
| ((value
& 0x1f) << 11) | ((value
& 0x20) >> 4);
1197 extract_sh6 (unsigned long insn
,
1198 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1199 int *invalid ATTRIBUTE_UNUSED
)
1201 return ((insn
>> 11) & 0x1f) | ((insn
<< 4) & 0x20);
1204 /* The SPR field in an XFX form instruction. This is flipped--the
1205 lower 5 bits are stored in the upper 5 and vice- versa. */
1207 static unsigned long
1208 insert_spr (unsigned long insn
,
1210 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1211 const char **errmsg ATTRIBUTE_UNUSED
)
1213 return insn
| ((value
& 0x1f) << 16) | ((value
& 0x3e0) << 6);
1217 extract_spr (unsigned long insn
,
1218 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1219 int *invalid ATTRIBUTE_UNUSED
)
1221 return ((insn
>> 16) & 0x1f) | ((insn
>> 6) & 0x3e0);
1224 /* Some dialects have 8 SPRG registers instead of the standard 4. */
1226 static unsigned long
1227 insert_sprg (unsigned long insn
,
1230 const char **errmsg
)
1234 && (dialect
& (PPC_OPCODE_BOOKE
| PPC_OPCODE_405
)) == 0))
1235 *errmsg
= _("invalid sprg number");
1237 /* If this is mfsprg4..7 then use spr 260..263 which can be read in
1238 user mode. Anything else must use spr 272..279. */
1239 if (value
<= 3 || (insn
& 0x100) != 0)
1242 return insn
| ((value
& 0x17) << 16);
1246 extract_sprg (unsigned long insn
,
1250 unsigned long val
= (insn
>> 16) & 0x1f;
1252 /* mfsprg can use 260..263 and 272..279. mtsprg only uses spr 272..279
1253 If not BOOKE or 405, then both use only 272..275. */
1255 || (val
< 0x10 && (insn
& 0x100) != 0)
1257 && (dialect
& (PPC_OPCODE_BOOKE
| PPC_OPCODE_403
)) == 0))
1262 /* The TBR field in an XFX instruction. This is just like SPR, but it
1263 is optional. When TBR is omitted, it must be inserted as 268 (the
1264 magic number of the TB register). These functions treat 0
1265 (indicating an omitted optional operand) as 268. This means that
1266 ``mftb 4,0'' is not handled correctly. This does not matter very
1267 much, since the architecture manual does not define mftb as
1268 accepting any values other than 268 or 269. */
1272 static unsigned long
1273 insert_tbr (unsigned long insn
,
1275 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1276 const char **errmsg ATTRIBUTE_UNUSED
)
1280 return insn
| ((value
& 0x1f) << 16) | ((value
& 0x3e0) << 6);
1284 extract_tbr (unsigned long insn
,
1285 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1286 int *invalid ATTRIBUTE_UNUSED
)
1290 ret
= ((insn
>> 16) & 0x1f) | ((insn
>> 6) & 0x3e0);
1296 /* Macros used to form opcodes. */
1298 /* The main opcode. */
1299 #define OP(x) ((((unsigned long)(x)) & 0x3f) << 26)
1300 #define OP_MASK OP (0x3f)
1302 /* The main opcode combined with a trap code in the TO field of a D
1303 form instruction. Used for extended mnemonics for the trap
1305 #define OPTO(x,to) (OP (x) | ((((unsigned long)(to)) & 0x1f) << 21))
1306 #define OPTO_MASK (OP_MASK | TO_MASK)
1308 /* The main opcode combined with a comparison size bit in the L field
1309 of a D form or X form instruction. Used for extended mnemonics for
1310 the comparison instructions. */
1311 #define OPL(x,l) (OP (x) | ((((unsigned long)(l)) & 1) << 21))
1312 #define OPL_MASK OPL (0x3f,1)
1314 /* An A form instruction. */
1315 #define A(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0x1f) << 1) | (((unsigned long)(rc)) & 1))
1316 #define A_MASK A (0x3f, 0x1f, 1)
1318 /* An A_MASK with the FRB field fixed. */
1319 #define AFRB_MASK (A_MASK | FRB_MASK)
1321 /* An A_MASK with the FRC field fixed. */
1322 #define AFRC_MASK (A_MASK | FRC_MASK)
1324 /* An A_MASK with the FRA and FRC fields fixed. */
1325 #define AFRAFRC_MASK (A_MASK | FRA_MASK | FRC_MASK)
1327 /* An AFRAFRC_MASK, but with L bit clear. */
1328 #define AFRALFRC_MASK (AFRAFRC_MASK & ~((unsigned long) 1 << 16))
1330 /* A B form instruction. */
1331 #define B(op, aa, lk) (OP (op) | ((((unsigned long)(aa)) & 1) << 1) | ((lk) & 1))
1332 #define B_MASK B (0x3f, 1, 1)
1334 /* A B form instruction setting the BO field. */
1335 #define BBO(op, bo, aa, lk) (B ((op), (aa), (lk)) | ((((unsigned long)(bo)) & 0x1f) << 21))
1336 #define BBO_MASK BBO (0x3f, 0x1f, 1, 1)
1338 /* A BBO_MASK with the y bit of the BO field removed. This permits
1339 matching a conditional branch regardless of the setting of the y
1340 bit. Similarly for the 'at' bits used for power4 branch hints. */
1341 #define Y_MASK (((unsigned long) 1) << 21)
1342 #define AT1_MASK (((unsigned long) 3) << 21)
1343 #define AT2_MASK (((unsigned long) 9) << 21)
1344 #define BBOY_MASK (BBO_MASK &~ Y_MASK)
1345 #define BBOAT_MASK (BBO_MASK &~ AT1_MASK)
1347 /* A B form instruction setting the BO field and the condition bits of
1349 #define BBOCB(op, bo, cb, aa, lk) \
1350 (BBO ((op), (bo), (aa), (lk)) | ((((unsigned long)(cb)) & 0x3) << 16))
1351 #define BBOCB_MASK BBOCB (0x3f, 0x1f, 0x3, 1, 1)
1353 /* A BBOCB_MASK with the y bit of the BO field removed. */
1354 #define BBOYCB_MASK (BBOCB_MASK &~ Y_MASK)
1355 #define BBOATCB_MASK (BBOCB_MASK &~ AT1_MASK)
1356 #define BBOAT2CB_MASK (BBOCB_MASK &~ AT2_MASK)
1358 /* A BBOYCB_MASK in which the BI field is fixed. */
1359 #define BBOYBI_MASK (BBOYCB_MASK | BI_MASK)
1360 #define BBOATBI_MASK (BBOAT2CB_MASK | BI_MASK)
1362 /* An Context form instruction. */
1363 #define CTX(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x7))
1364 #define CTX_MASK CTX(0x3f, 0x7)
1366 /* An User Context form instruction. */
1367 #define UCTX(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x1f))
1368 #define UCTX_MASK UCTX(0x3f, 0x1f)
1370 /* The main opcode mask with the RA field clear. */
1371 #define DRA_MASK (OP_MASK | RA_MASK)
1373 /* A DS form instruction. */
1374 #define DSO(op, xop) (OP (op) | ((xop) & 0x3))
1375 #define DS_MASK DSO (0x3f, 3)
1377 /* A DE form instruction. */
1378 #define DEO(op, xop) (OP (op) | ((xop) & 0xf))
1379 #define DE_MASK DEO (0x3e, 0xf)
1381 /* An EVSEL form instruction. */
1382 #define EVSEL(op, xop) (OP (op) | (((unsigned long)(xop)) & 0xff) << 3)
1383 #define EVSEL_MASK EVSEL(0x3f, 0xff)
1385 /* An M form instruction. */
1386 #define M(op, rc) (OP (op) | ((rc) & 1))
1387 #define M_MASK M (0x3f, 1)
1389 /* An M form instruction with the ME field specified. */
1390 #define MME(op, me, rc) (M ((op), (rc)) | ((((unsigned long)(me)) & 0x1f) << 1))
1392 /* An M_MASK with the MB and ME fields fixed. */
1393 #define MMBME_MASK (M_MASK | MB_MASK | ME_MASK)
1395 /* An M_MASK with the SH and ME fields fixed. */
1396 #define MSHME_MASK (M_MASK | SH_MASK | ME_MASK)
1398 /* An MD form instruction. */
1399 #define MD(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0x7) << 2) | ((rc) & 1))
1400 #define MD_MASK MD (0x3f, 0x7, 1)
1402 /* An MD_MASK with the MB field fixed. */
1403 #define MDMB_MASK (MD_MASK | MB6_MASK)
1405 /* An MD_MASK with the SH field fixed. */
1406 #define MDSH_MASK (MD_MASK | SH6_MASK)
1408 /* An MDS form instruction. */
1409 #define MDS(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0xf) << 1) | ((rc) & 1))
1410 #define MDS_MASK MDS (0x3f, 0xf, 1)
1412 /* An MDS_MASK with the MB field fixed. */
1413 #define MDSMB_MASK (MDS_MASK | MB6_MASK)
1415 /* An SC form instruction. */
1416 #define SC(op, sa, lk) (OP (op) | ((((unsigned long)(sa)) & 1) << 1) | ((lk) & 1))
1417 #define SC_MASK (OP_MASK | (((unsigned long)0x3ff) << 16) | (((unsigned long)1) << 1) | 1)
1419 /* An VX form instruction. */
1420 #define VX(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x7ff))
1422 /* The mask for an VX form instruction. */
1423 #define VX_MASK VX(0x3f, 0x7ff)
1425 /* An VA form instruction. */
1426 #define VXA(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x03f))
1428 /* The mask for an VA form instruction. */
1429 #define VXA_MASK VXA(0x3f, 0x3f)
1431 /* An VXR form instruction. */
1432 #define VXR(op, xop, rc) (OP (op) | (((rc) & 1) << 10) | (((unsigned long)(xop)) & 0x3ff))
1434 /* The mask for a VXR form instruction. */
1435 #define VXR_MASK VXR(0x3f, 0x3ff, 1)
1437 /* An X form instruction. */
1438 #define X(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x3ff) << 1))
1440 /* A Z form instruction. */
1441 #define Z(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x1ff) << 1))
1443 /* An X form instruction with the RC bit specified. */
1444 #define XRC(op, xop, rc) (X ((op), (xop)) | ((rc) & 1))
1446 /* A Z form instruction with the RC bit specified. */
1447 #define ZRC(op, xop, rc) (Z ((op), (xop)) | ((rc) & 1))
1449 /* The mask for an X form instruction. */
1450 #define X_MASK XRC (0x3f, 0x3ff, 1)
1452 /* The mask for a Z form instruction. */
1453 #define Z_MASK ZRC (0x3f, 0x1ff, 1)
1454 #define Z2_MASK ZRC (0x3f, 0xff, 1)
1456 /* An X_MASK with the RA field fixed. */
1457 #define XRA_MASK (X_MASK | RA_MASK)
1459 /* An XRA_MASK with the W field clear. */
1460 #define XWRA_MASK (XRA_MASK & ~((unsigned long) 1 << 16))
1462 /* An X_MASK with the RB field fixed. */
1463 #define XRB_MASK (X_MASK | RB_MASK)
1465 /* An X_MASK with the RT field fixed. */
1466 #define XRT_MASK (X_MASK | RT_MASK)
1468 /* An XRT_MASK mask with the L bits clear. */
1469 #define XLRT_MASK (XRT_MASK & ~((unsigned long) 0x3 << 21))
1471 /* An X_MASK with the RA and RB fields fixed. */
1472 #define XRARB_MASK (X_MASK | RA_MASK | RB_MASK)
1474 /* An XRARB_MASK, but with the L bit clear. */
1475 #define XRLARB_MASK (XRARB_MASK & ~((unsigned long) 1 << 16))
1477 /* An X_MASK with the RT and RA fields fixed. */
1478 #define XRTRA_MASK (X_MASK | RT_MASK | RA_MASK)
1480 /* An XRTRA_MASK, but with L bit clear. */
1481 #define XRTLRA_MASK (XRTRA_MASK & ~((unsigned long) 1 << 21))
1483 /* An X form instruction with the L bit specified. */
1484 #define XOPL(op, xop, l) (X ((op), (xop)) | ((((unsigned long)(l)) & 1) << 21))
1486 /* An X form instruction with RT fields specified */
1487 #define XRT(op, xop, rt) (X ((op), (xop)) \
1488 | ((((unsigned long)(rt)) & 0x1f) << 21))
1490 /* An X form instruction with RT and RA fields specified */
1491 #define XRTRA(op, xop, rt, ra) (X ((op), (xop)) \
1492 | ((((unsigned long)(rt)) & 0x1f) << 21) \
1493 | ((((unsigned long)(ra)) & 0x1f) << 16))
1495 /* The mask for an X form comparison instruction. */
1496 #define XCMP_MASK (X_MASK | (((unsigned long)1) << 22))
1498 /* The mask for an X form comparison instruction with the L field
1500 #define XCMPL_MASK (XCMP_MASK | (((unsigned long)1) << 21))
1502 /* An X form trap instruction with the TO field specified. */
1503 #define XTO(op, xop, to) (X ((op), (xop)) | ((((unsigned long)(to)) & 0x1f) << 21))
1504 #define XTO_MASK (X_MASK | TO_MASK)
1506 /* An X form tlb instruction with the SH field specified. */
1507 #define XTLB(op, xop, sh) (X ((op), (xop)) | ((((unsigned long)(sh)) & 0x1f) << 11))
1508 #define XTLB_MASK (X_MASK | SH_MASK)
1510 /* An X form sync instruction. */
1511 #define XSYNC(op, xop, l) (X ((op), (xop)) | ((((unsigned long)(l)) & 3) << 21))
1513 /* An X form sync instruction with everything filled in except the LS field. */
1514 #define XSYNC_MASK (0xff9fffff)
1516 /* An X_MASK, but with the EH bit clear. */
1517 #define XEH_MASK (X_MASK & ~((unsigned long )1))
1519 /* An X form AltiVec dss instruction. */
1520 #define XDSS(op, xop, a) (X ((op), (xop)) | ((((unsigned long)(a)) & 1) << 25))
1521 #define XDSS_MASK XDSS(0x3f, 0x3ff, 1)
1523 /* An XFL form instruction. */
1524 #define XFL(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0x3ff) << 1) | (((unsigned long)(rc)) & 1))
1525 #define XFL_MASK XFL (0x3f, 0x3ff, 1)
1527 /* An X form isel instruction. */
1528 #define XISEL(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x1f) << 1))
1529 #define XISEL_MASK XISEL(0x3f, 0x1f)
1531 /* An XL form instruction with the LK field set to 0. */
1532 #define XL(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x3ff) << 1))
1534 /* An XL form instruction which uses the LK field. */
1535 #define XLLK(op, xop, lk) (XL ((op), (xop)) | ((lk) & 1))
1537 /* The mask for an XL form instruction. */
1538 #define XL_MASK XLLK (0x3f, 0x3ff, 1)
1540 /* An XL form instruction which explicitly sets the BO field. */
1541 #define XLO(op, bo, xop, lk) \
1542 (XLLK ((op), (xop), (lk)) | ((((unsigned long)(bo)) & 0x1f) << 21))
1543 #define XLO_MASK (XL_MASK | BO_MASK)
1545 /* An XL form instruction which explicitly sets the y bit of the BO
1547 #define XLYLK(op, xop, y, lk) (XLLK ((op), (xop), (lk)) | ((((unsigned long)(y)) & 1) << 21))
1548 #define XLYLK_MASK (XL_MASK | Y_MASK)
1550 /* An XL form instruction which sets the BO field and the condition
1551 bits of the BI field. */
1552 #define XLOCB(op, bo, cb, xop, lk) \
1553 (XLO ((op), (bo), (xop), (lk)) | ((((unsigned long)(cb)) & 3) << 16))
1554 #define XLOCB_MASK XLOCB (0x3f, 0x1f, 0x3, 0x3ff, 1)
1556 /* An XL_MASK or XLYLK_MASK or XLOCB_MASK with the BB field fixed. */
1557 #define XLBB_MASK (XL_MASK | BB_MASK)
1558 #define XLYBB_MASK (XLYLK_MASK | BB_MASK)
1559 #define XLBOCBBB_MASK (XLOCB_MASK | BB_MASK)
1561 /* A mask for branch instructions using the BH field. */
1562 #define XLBH_MASK (XL_MASK | (0x1c << 11))
1564 /* An XL_MASK with the BO and BB fields fixed. */
1565 #define XLBOBB_MASK (XL_MASK | BO_MASK | BB_MASK)
1567 /* An XL_MASK with the BO, BI and BB fields fixed. */
1568 #define XLBOBIBB_MASK (XL_MASK | BO_MASK | BI_MASK | BB_MASK)
1570 /* An XO form instruction. */
1571 #define XO(op, xop, oe, rc) \
1572 (OP (op) | ((((unsigned long)(xop)) & 0x1ff) << 1) | ((((unsigned long)(oe)) & 1) << 10) | (((unsigned long)(rc)) & 1))
1573 #define XO_MASK XO (0x3f, 0x1ff, 1, 1)
1575 /* An XO_MASK with the RB field fixed. */
1576 #define XORB_MASK (XO_MASK | RB_MASK)
1578 /* An XOPS form instruction for paired singles. */
1579 #define XOPS(op, xop, rc) \
1580 (OP (op) | ((((unsigned long)(xop)) & 0x3ff) << 1) | (((unsigned long)(rc)) & 1))
1581 #define XOPS_MASK XOPS (0x3f, 0x3ff, 1)
1584 /* An XS form instruction. */
1585 #define XS(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0x1ff) << 2) | (((unsigned long)(rc)) & 1))
1586 #define XS_MASK XS (0x3f, 0x1ff, 1)
1588 /* A mask for the FXM version of an XFX form instruction. */
1589 #define XFXFXM_MASK (X_MASK | (1 << 11) | (1 << 20))
1591 /* An XFX form instruction with the FXM field filled in. */
1592 #define XFXM(op, xop, fxm, p4) \
1593 (X ((op), (xop)) | ((((unsigned long)(fxm)) & 0xff) << 12) \
1594 | ((unsigned long)(p4) << 20))
1596 /* An XFX form instruction with the SPR field filled in. */
1597 #define XSPR(op, xop, spr) \
1598 (X ((op), (xop)) | ((((unsigned long)(spr)) & 0x1f) << 16) | ((((unsigned long)(spr)) & 0x3e0) << 6))
1599 #define XSPR_MASK (X_MASK | SPR_MASK)
1601 /* An XFX form instruction with the SPR field filled in except for the
1603 #define XSPRBAT_MASK (XSPR_MASK &~ SPRBAT_MASK)
1605 /* An XFX form instruction with the SPR field filled in except for the
1607 #define XSPRG_MASK (XSPR_MASK & ~(0x1f << 16))
1609 /* An X form instruction with everything filled in except the E field. */
1610 #define XE_MASK (0xffff7fff)
1612 /* An X form user context instruction. */
1613 #define XUC(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x1f))
1614 #define XUC_MASK XUC(0x3f, 0x1f)
1616 /* An XW form instruction. */
1617 #define XW(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0x3f) << 1) | ((rc) & 1))
1618 /* The mask for a G form instruction. rc not supported at present. */
1619 #define XW_MASK XW (0x3f, 0x3f, 0)
1621 /* An APU form instruction. */
1622 #define APU(op, xop, rc) (OP (op) | (((unsigned long)(xop)) & 0x3ff) << 1 | ((rc) & 1))
1624 /* The mask for an APU form instruction. */
1625 #define APU_MASK APU (0x3f, 0x3ff, 1)
1626 #define APU_RT_MASK (APU_MASK | RT_MASK)
1627 #define APU_RA_MASK (APU_MASK | RA_MASK)
1629 /* The BO encodings used in extended conditional branch mnemonics. */
1630 #define BODNZF (0x0)
1631 #define BODNZFP (0x1)
1633 #define BODZFP (0x3)
1634 #define BODNZT (0x8)
1635 #define BODNZTP (0x9)
1637 #define BODZTP (0xb)
1648 #define BODNZ (0x10)
1649 #define BODNZP (0x11)
1651 #define BODZP (0x13)
1652 #define BODNZM4 (0x18)
1653 #define BODNZP4 (0x19)
1654 #define BODZM4 (0x1a)
1655 #define BODZP4 (0x1b)
1659 /* The BI condition bit encodings used in extended conditional branch
1666 /* The TO encodings used in extended trap mnemonics. */
1683 /* Smaller names for the flags so each entry in the opcodes table will
1684 fit on a single line. */
1686 #define PPC PPC_OPCODE_PPC
1687 #define PPCCOM PPC_OPCODE_PPC | PPC_OPCODE_COMMON
1688 #define NOPOWER4 PPC_OPCODE_NOPOWER4 | PPCCOM
1689 #define POWER4 PPC_OPCODE_POWER4
1690 #define POWER5 PPC_OPCODE_POWER5
1691 #define POWER6 PPC_OPCODE_POWER6
1692 #define CELL PPC_OPCODE_CELL
1693 #define PPC32 PPC_OPCODE_32 | PPC_OPCODE_PPC
1694 #define PPC64 PPC_OPCODE_64 | PPC_OPCODE_PPC
1695 #define PPC403 PPC_OPCODE_403
1696 #define PPC405 PPC_OPCODE_405
1697 #define PPC440 PPC_OPCODE_440
1698 #define PPC464 PPC440
1702 #define PPCPS PPC_OPCODE_PPCPS
1703 #define PPCVEC PPC_OPCODE_ALTIVEC
1704 #define POWER PPC_OPCODE_POWER
1705 #define POWER2 PPC_OPCODE_POWER | PPC_OPCODE_POWER2
1706 #define PPCPWR2 PPC_OPCODE_PPC | PPC_OPCODE_POWER | PPC_OPCODE_POWER2
1707 #define POWER32 PPC_OPCODE_POWER | PPC_OPCODE_32
1708 #define COM PPC_OPCODE_POWER | PPC_OPCODE_PPC | PPC_OPCODE_COMMON
1709 #define COM32 PPC_OPCODE_POWER | PPC_OPCODE_PPC | PPC_OPCODE_COMMON | PPC_OPCODE_32
1710 #define M601 PPC_OPCODE_POWER | PPC_OPCODE_601
1711 #define PWRCOM PPC_OPCODE_POWER | PPC_OPCODE_601 | PPC_OPCODE_COMMON
1712 #define MFDEC1 PPC_OPCODE_POWER
1713 #define MFDEC2 PPC_OPCODE_PPC | PPC_OPCODE_601 | PPC_OPCODE_BOOKE
1714 #define BOOKE PPC_OPCODE_BOOKE
1715 #define BOOKE64 PPC_OPCODE_BOOKE64
1716 #define CLASSIC PPC_OPCODE_CLASSIC
1717 #define PPCE300 PPC_OPCODE_E300
1718 #define PPCSPE PPC_OPCODE_SPE
1719 #define PPCISEL PPC_OPCODE_ISEL
1720 #define PPCEFS PPC_OPCODE_EFS
1721 #define PPCBRLK PPC_OPCODE_BRLOCK
1722 #define PPCPMR PPC_OPCODE_PMR
1723 #define PPCCHLK PPC_OPCODE_CACHELCK
1724 #define PPCCHLK64 PPC_OPCODE_CACHELCK | PPC_OPCODE_BOOKE64
1725 #define PPCRFMCI PPC_OPCODE_RFMCI
1726 #define E500MC PPC_OPCODE_E500MC
1728 /* The opcode table.
1730 The format of the opcode table is:
1732 NAME OPCODE MASK FLAGS {OPERANDS}
1734 NAME is the name of the instruction.
1735 OPCODE is the instruction opcode.
1736 MASK is the opcode mask; this is used to tell the disassembler
1737 which bits in the actual opcode must match OPCODE.
1738 FLAGS are flags indicated what processors support the instruction.
1739 OPERANDS is the list of operands.
1741 The disassembler reads the table in order and prints the first
1742 instruction which matches, so this table is sorted to put more
1743 specific instructions before more general instructions.
1745 This table must be sorted by major opcode. Please try to keep it
1746 vaguely sorted within major opcode too, except of course where
1747 constrained otherwise by disassembler operation. */
1749 const struct powerpc_opcode powerpc_opcodes
[] = {
1750 {"attn", X(0,256), X_MASK
, POWER4
, {0}},
1751 {"tdlgti", OPTO(2,TOLGT
), OPTO_MASK
, PPC64
, {RA
, SI
}},
1752 {"tdllti", OPTO(2,TOLLT
), OPTO_MASK
, PPC64
, {RA
, SI
}},
1753 {"tdeqi", OPTO(2,TOEQ
), OPTO_MASK
, PPC64
, {RA
, SI
}},
1754 {"tdlgei", OPTO(2,TOLGE
), OPTO_MASK
, PPC64
, {RA
, SI
}},
1755 {"tdlnli", OPTO(2,TOLNL
), OPTO_MASK
, PPC64
, {RA
, SI
}},
1756 {"tdllei", OPTO(2,TOLLE
), OPTO_MASK
, PPC64
, {RA
, SI
}},
1757 {"tdlngi", OPTO(2,TOLNG
), OPTO_MASK
, PPC64
, {RA
, SI
}},
1758 {"tdgti", OPTO(2,TOGT
), OPTO_MASK
, PPC64
, {RA
, SI
}},
1759 {"tdgei", OPTO(2,TOGE
), OPTO_MASK
, PPC64
, {RA
, SI
}},
1760 {"tdnli", OPTO(2,TONL
), OPTO_MASK
, PPC64
, {RA
, SI
}},
1761 {"tdlti", OPTO(2,TOLT
), OPTO_MASK
, PPC64
, {RA
, SI
}},
1762 {"tdlei", OPTO(2,TOLE
), OPTO_MASK
, PPC64
, {RA
, SI
}},
1763 {"tdngi", OPTO(2,TONG
), OPTO_MASK
, PPC64
, {RA
, SI
}},
1764 {"tdnei", OPTO(2,TONE
), OPTO_MASK
, PPC64
, {RA
, SI
}},
1765 {"tdi", OP(2), OP_MASK
, PPC64
, {TO
, RA
, SI
}},
1767 {"twlgti", OPTO(3,TOLGT
), OPTO_MASK
, PPCCOM
, {RA
, SI
}},
1768 {"tlgti", OPTO(3,TOLGT
), OPTO_MASK
, PWRCOM
, {RA
, SI
}},
1769 {"twllti", OPTO(3,TOLLT
), OPTO_MASK
, PPCCOM
, {RA
, SI
}},
1770 {"tllti", OPTO(3,TOLLT
), OPTO_MASK
, PWRCOM
, {RA
, SI
}},
1771 {"tweqi", OPTO(3,TOEQ
), OPTO_MASK
, PPCCOM
, {RA
, SI
}},
1772 {"teqi", OPTO(3,TOEQ
), OPTO_MASK
, PWRCOM
, {RA
, SI
}},
1773 {"twlgei", OPTO(3,TOLGE
), OPTO_MASK
, PPCCOM
, {RA
, SI
}},
1774 {"tlgei", OPTO(3,TOLGE
), OPTO_MASK
, PWRCOM
, {RA
, SI
}},
1775 {"twlnli", OPTO(3,TOLNL
), OPTO_MASK
, PPCCOM
, {RA
, SI
}},
1776 {"tlnli", OPTO(3,TOLNL
), OPTO_MASK
, PWRCOM
, {RA
, SI
}},
1777 {"twllei", OPTO(3,TOLLE
), OPTO_MASK
, PPCCOM
, {RA
, SI
}},
1778 {"tllei", OPTO(3,TOLLE
), OPTO_MASK
, PWRCOM
, {RA
, SI
}},
1779 {"twlngi", OPTO(3,TOLNG
), OPTO_MASK
, PPCCOM
, {RA
, SI
}},
1780 {"tlngi", OPTO(3,TOLNG
), OPTO_MASK
, PWRCOM
, {RA
, SI
}},
1781 {"twgti", OPTO(3,TOGT
), OPTO_MASK
, PPCCOM
, {RA
, SI
}},
1782 {"tgti", OPTO(3,TOGT
), OPTO_MASK
, PWRCOM
, {RA
, SI
}},
1783 {"twgei", OPTO(3,TOGE
), OPTO_MASK
, PPCCOM
, {RA
, SI
}},
1784 {"tgei", OPTO(3,TOGE
), OPTO_MASK
, PWRCOM
, {RA
, SI
}},
1785 {"twnli", OPTO(3,TONL
), OPTO_MASK
, PPCCOM
, {RA
, SI
}},
1786 {"tnli", OPTO(3,TONL
), OPTO_MASK
, PWRCOM
, {RA
, SI
}},
1787 {"twlti", OPTO(3,TOLT
), OPTO_MASK
, PPCCOM
, {RA
, SI
}},
1788 {"tlti", OPTO(3,TOLT
), OPTO_MASK
, PWRCOM
, {RA
, SI
}},
1789 {"twlei", OPTO(3,TOLE
), OPTO_MASK
, PPCCOM
, {RA
, SI
}},
1790 {"tlei", OPTO(3,TOLE
), OPTO_MASK
, PWRCOM
, {RA
, SI
}},
1791 {"twngi", OPTO(3,TONG
), OPTO_MASK
, PPCCOM
, {RA
, SI
}},
1792 {"tngi", OPTO(3,TONG
), OPTO_MASK
, PWRCOM
, {RA
, SI
}},
1793 {"twnei", OPTO(3,TONE
), OPTO_MASK
, PPCCOM
, {RA
, SI
}},
1794 {"tnei", OPTO(3,TONE
), OPTO_MASK
, PWRCOM
, {RA
, SI
}},
1795 {"twi", OP(3), OP_MASK
, PPCCOM
, {TO
, RA
, SI
}},
1796 {"ti", OP(3), OP_MASK
, PWRCOM
, {TO
, RA
, SI
}},
1798 {"ps_cmpu0", X (4, 0), X_MASK
|(3<<21), PPCPS
, {BF
, FRA
, FRB
}},
1799 {"vaddubm", VX (4, 0), VX_MASK
, PPCVEC
, {VD
, VA
, VB
}},
1800 {"vmaxub", VX (4, 2), VX_MASK
, PPCVEC
, {VD
, VA
, VB
}},
1801 {"vrlb", VX (4, 4), VX_MASK
, PPCVEC
, {VD
, VA
, VB
}},
1802 {"vcmpequb", VXR(4, 6,0), VXR_MASK
, PPCVEC
, {VD
, VA
, VB
}},
1803 {"vmuloub", VX (4, 8), VX_MASK
, PPCVEC
, {VD
, VA
, VB
}},
1804 {"vaddfp", VX (4, 10), VX_MASK
, PPCVEC
, {VD
, VA
, VB
}},
1805 {"psq_lx", XW (4, 6,0), XW_MASK
, PPCPS
, {FRT
,RA
,RB
,PSWM
,PSQM
}},
1806 {"vmrghb", VX (4, 12), VX_MASK
, PPCVEC
, {VD
, VA
, VB
}},
1807 {"psq_stx", XW (4, 7,0), XW_MASK
, PPCPS
, {FRS
,RA
,RB
,PSWM
,PSQM
}},
1808 {"vpkuhum", VX (4, 14), VX_MASK
, PPCVEC
, {VD
, VA
, VB
}},
1809 {"mulhhwu", XRC(4, 8,0), X_MASK
, PPC405
|PPC440
, {RT
, RA
, RB
}},
1810 {"mulhhwu.", XRC(4, 8,1), X_MASK
, PPC405
|PPC440
, {RT
, RA
, RB
}},
1811 {"ps_sum0", A (4, 10,0), A_MASK
, PPCPS
, {FRT
, FRA
, FRC
, FRB
}},
1812 {"ps_sum0.", A (4, 10,1), A_MASK
, PPCPS
, {FRT
, FRA
, FRC
, FRB
}},
1813 {"ps_sum1", A (4, 11,0), A_MASK
, PPCPS
, {FRT
, FRA
, FRC
, FRB
}},
1814 {"ps_sum1.", A (4, 11,1), A_MASK
, PPCPS
, {FRT
, FRA
, FRC
, FRB
}},
1815 {"ps_muls0", A (4, 12,0), AFRB_MASK
, PPCPS
, {FRT
, FRA
, FRC
}},
1816 {"machhwu", XO (4, 12,0,0),XO_MASK
, PPC405
|PPC440
, {RT
, RA
, RB
}},
1817 {"ps_muls0.", A (4, 12,1), AFRB_MASK
, PPCPS
, {FRT
, FRA
, FRC
}},
1818 {"machhwu.", XO (4, 12,0,1),XO_MASK
, PPC405
|PPC440
, {RT
, RA
, RB
}},
1819 {"ps_muls1", A (4, 13,0), AFRB_MASK
, PPCPS
, {FRT
, FRA
, FRC
}},
1820 {"ps_muls1.", A (4, 13,1), AFRB_MASK
, PPCPS
, {FRT
, FRA
, FRC
}},
1821 {"ps_madds0", A (4, 14,0), A_MASK
, PPCPS
, {FRT
, FRA
, FRC
, FRB
}},
1822 {"ps_madds0.", A (4, 14,1), A_MASK
, PPCPS
, {FRT
, FRA
, FRC
, FRB
}},
1823 {"ps_madds1", A (4, 15,0), A_MASK
, PPCPS
, {FRT
, FRA
, FRC
, FRB
}},
1824 {"ps_madds1.", A (4, 15,1), A_MASK
, PPCPS
, {FRT
, FRA
, FRC
, FRB
}},
1825 {"vmhaddshs", VXA(4, 32), VXA_MASK
, PPCVEC
, {VD
, VA
, VB
, VC
}},
1826 {"vmhraddshs", VXA(4, 33), VXA_MASK
, PPCVEC
, {VD
, VA
, VB
, VC
}},
1827 {"vmladduhm", VXA(4, 34), VXA_MASK
, PPCVEC
, {VD
, VA
, VB
, VC
}},
1828 {"ps_div", A (4, 18,0), AFRC_MASK
, PPCPS
, {FRT
, FRA
, FRB
}},
1829 {"vmsumubm", VXA(4, 36), VXA_MASK
, PPCVEC
, {VD
, VA
, VB
, VC
}},
1830 {"ps_div.", A (4, 18,1), AFRC_MASK
, PPCPS
, {FRT
, FRA
, FRB
}},
1831 {"vmsummbm", VXA(4, 37), VXA_MASK
, PPCVEC
, {VD
, VA
, VB
, VC
}},
1832 {"vmsumuhm", VXA(4, 38), VXA_MASK
, PPCVEC
, {VD
, VA
, VB
, VC
}},
1833 {"vmsumuhs", VXA(4, 39), VXA_MASK
, PPCVEC
, {VD
, VA
, VB
, VC
}},
1834 {"ps_sub", A (4, 20,0), AFRC_MASK
, PPCPS
, {FRT
, FRA
, FRB
}},
1835 {"vmsumshm", VXA(4, 40), VXA_MASK
, PPCVEC
, {VD
, VA
, VB
, VC
}},
1836 {"ps_sub.", A (4, 20,1), AFRC_MASK
, PPCPS
, {FRT
, FRA
, FRB
}},
1837 {"vmsumshs", VXA(4, 41), VXA_MASK
, PPCVEC
, {VD
, VA
, VB
, VC
}},
1838 {"ps_add", A (4, 21,0), AFRC_MASK
, PPCPS
, {FRT
, FRA
, FRB
}},
1839 {"vsel", VXA(4, 42), VXA_MASK
, PPCVEC
, {VD
, VA
, VB
, VC
}},
1840 {"ps_add.", A (4, 21,1), AFRC_MASK
, PPCPS
, {FRT
, FRA
, FRB
}},
1841 {"vperm", VXA(4, 43), VXA_MASK
, PPCVEC
, {VD
, VA
, VB
, VC
}},
1842 {"vsldoi", VXA(4, 44), VXA_MASK
, PPCVEC
, {VD
, VA
, VB
, SHB
}},
1843 {"ps_sel", A (4, 23,0), A_MASK
, PPCPS
, {FRT
, FRA
, FRC
, FRB
}},
1844 {"vmaddfp", VXA(4, 46), VXA_MASK
, PPCVEC
, {VD
, VA
, VC
, VB
}},
1845 {"ps_sel.", A (4, 23,1), A_MASK
, PPCPS
, {FRT
, FRA
, FRC
, FRB
}},
1846 {"vnmsubfp", VXA(4, 47), VXA_MASK
, PPCVEC
, {VD
, VA
, VC
, VB
}},
1847 {"ps_res", A (4, 24,0), AFRAFRC_MASK
, PPCPS
, {FRT
, FRB
}},
1848 {"ps_res.", A (4, 24,1), AFRAFRC_MASK
, PPCPS
, {FRT
, FRB
}},
1849 {"ps_mul", A (4, 25,0), AFRB_MASK
, PPCPS
, {FRT
, FRA
, FRC
}},
1850 {"ps_mul.", A (4, 25,1), AFRB_MASK
, PPCPS
, {FRT
, FRA
, FRC
}},
1851 {"ps_rsqrte", A (4, 26,0), AFRAFRC_MASK
, PPCPS
, {FRT
, FRB
}},
1852 {"ps_rsqrte.", A (4, 26,1), AFRAFRC_MASK
, PPCPS
, {FRT
, FRB
}},
1853 {"ps_msub", A (4, 28,0), A_MASK
, PPCPS
, {FRT
, FRA
, FRC
, FRB
}},
1854 {"ps_msub.", A (4, 28,1), A_MASK
, PPCPS
, {FRT
, FRA
, FRC
, FRB
}},
1855 {"ps_madd", A (4, 29,0), A_MASK
, PPCPS
, {FRT
, FRA
, FRC
, FRB
}},
1856 {"ps_madd.", A (4, 29,1), A_MASK
, PPCPS
, {FRT
, FRA
, FRC
, FRB
}},
1857 {"ps_nmsub", A (4, 30,0), A_MASK
, PPCPS
, {FRT
, FRA
, FRC
, FRB
}},
1858 {"ps_nmsub.", A (4, 30,1), A_MASK
, PPCPS
, {FRT
, FRA
, FRC
, FRB
}},
1859 {"ps_nmadd", A (4, 31,0), A_MASK
, PPCPS
, {FRT
, FRA
, FRC
, FRB
}},
1860 {"ps_nmadd.", A (4, 31,1), A_MASK
, PPCPS
, {FRT
, FRA
, FRC
, FRB
}},
1861 {"ps_cmpo0", X (4, 32), X_MASK
|(3<<21), PPCPS
, {BF
, FRA
, FRB
}},
1862 {"vadduhm", VX (4, 64), VX_MASK
, PPCVEC
, {VD
, VA
, VB
}},
1863 {"vmaxuh", VX (4, 66), VX_MASK
, PPCVEC
, {VD
, VA
, VB
}},
1864 {"vrlh", VX (4, 68), VX_MASK
, PPCVEC
, {VD
, VA
, VB
}},
1865 {"vcmpequh", VXR(4, 70,0), VXR_MASK
, PPCVEC
, {VD
, VA
, VB
}},
1866 {"vmulouh", VX (4, 72), VX_MASK
, PPCVEC
, {VD
, VA
, VB
}},
1867 {"vsubfp", VX (4, 74), VX_MASK
, PPCVEC
, {VD
, VA
, VB
}},
1868 {"psq_lux", XW (4, 38,0), XW_MASK
, PPCPS
, {FRT
,RA
,RB
,PSWM
,PSQM
}},
1869 {"vmrghh", VX (4, 76), VX_MASK
, PPCVEC
, {VD
, VA
, VB
}},
1870 {"psq_stux", XW (4, 39,0), XW_MASK
, PPCPS
, {FRS
,RA
,RB
,PSWM
,PSQM
}},
1871 {"vpkuwum", VX (4, 78), VX_MASK
, PPCVEC
, {VD
, VA
, VB
}},
1872 {"ps_neg", XRC(4, 40,0), XRA_MASK
, PPCPS
, {FRT
, FRB
}},
1873 {"mulhhw", XRC(4, 40,0), X_MASK
, PPC405
|PPC440
, {RT
, RA
, RB
}},
1874 {"ps_neg.", XRC(4, 40,1), XRA_MASK
, PPCPS
, {FRT
, FRB
}},
1875 {"mulhhw.", XRC(4, 40,1), X_MASK
, PPC405
|PPC440
, {RT
, RA
, RB
}},
1876 {"machhw", XO (4, 44,0,0),XO_MASK
, PPC405
|PPC440
, {RT
, RA
, RB
}},
1877 {"machhw.", XO (4, 44,0,1),XO_MASK
, PPC405
|PPC440
, {RT
, RA
, RB
}},
1878 {"nmachhw", XO (4, 46,0,0),XO_MASK
, PPC405
|PPC440
, {RT
, RA
, RB
}},
1879 {"nmachhw.", XO (4, 46,0,1),XO_MASK
, PPC405
|PPC440
, {RT
, RA
, RB
}},
1880 {"ps_cmpu1", X (4, 64), X_MASK
|(3<<21), PPCPS
, {BF
, FRA
, FRB
}},
1881 {"vadduwm", VX (4, 128), VX_MASK
, PPCVEC
, {VD
, VA
, VB
}},
1882 {"vmaxuw", VX (4, 130), VX_MASK
, PPCVEC
, {VD
, VA
, VB
}},
1883 {"vrlw", VX (4, 132), VX_MASK
, PPCVEC
, {VD
, VA
, VB
}},
1884 {"vcmpequw", VXR(4, 134,0), VXR_MASK
, PPCVEC
, {VD
, VA
, VB
}},
1885 {"vmrghw", VX (4, 140), VX_MASK
, PPCVEC
, {VD
, VA
, VB
}},
1886 {"vpkuhus", VX (4, 142), VX_MASK
, PPCVEC
, {VD
, VA
, VB
}},
1887 {"ps_mr", XRC(4, 72,0), XRA_MASK
, PPCPS
, {FRT
, FRB
}},
1888 {"ps_mr.", XRC(4, 72,1), XRA_MASK
, PPCPS
, {FRT
, FRB
}},
1889 {"machhwsu", XO (4, 76,0,0),XO_MASK
, PPC405
|PPC440
, {RT
, RA
, RB
}},
1890 {"machhwsu.", XO (4, 76,0,1),XO_MASK
, PPC405
|PPC440
, {RT
, RA
, RB
}},
1891 {"ps_cmpo1", X (4, 96), X_MASK
|(3<<21), PPCPS
, {BF
, FRA
, FRB
}},
1892 {"vcmpeqfp", VXR(4, 198,0), VXR_MASK
, PPCVEC
, {VD
, VA
, VB
}},
1893 {"vpkuwus", VX (4, 206), VX_MASK
, PPCVEC
, {VD
, VA
, VB
}},
1894 {"machhws", XO (4, 108,0,0),XO_MASK
, PPC405
|PPC440
, {RT
, RA
, RB
}},
1895 {"machhws.", XO (4, 108,0,1),XO_MASK
, PPC405
|PPC440
, {RT
, RA
, RB
}},
1896 {"nmachhws", XO (4, 110,0,0),XO_MASK
, PPC405
|PPC440
, {RT
, RA
, RB
}},
1897 {"nmachhws.", XO (4, 110,0,1),XO_MASK
, PPC405
|PPC440
, {RT
, RA
, RB
}},
1898 {"vmaxsb", VX (4, 258), VX_MASK
, PPCVEC
, {VD
, VA
, VB
}},
1899 {"vslb", VX (4, 260), VX_MASK
, PPCVEC
, {VD
, VA
, VB
}},
1900 {"vmulosb", VX (4, 264), VX_MASK
, PPCVEC
, {VD
, VA
, VB
}},
1901 {"vrefp", VX (4, 266), VX_MASK
, PPCVEC
, {VD
, VB
}},
1902 {"vmrglb", VX (4, 268), VX_MASK
, PPCVEC
, {VD
, VA
, VB
}},
1903 {"vpkshus", VX (4, 270), VX_MASK
, PPCVEC
, {VD
, VA
, VB
}},
1904 {"ps_nabs", XRC(4, 136,0), XRA_MASK
, PPCPS
, {FRT
, FRB
}},
1905 {"mulchwu", XRC(4, 136,0), X_MASK
, PPC405
|PPC440
, {RT
, RA
, RB
}},
1906 {"ps_nabs.", XRC(4, 136,1), XRA_MASK
, PPCPS
, {FRT
, FRB
}},
1907 {"mulchwu.", XRC(4, 136,1), X_MASK
, PPC405
|PPC440
, {RT
, RA
, RB
}},
1908 {"macchwu", XO (4, 140,0,0),XO_MASK
, PPC405
|PPC440
, {RT
, RA
, RB
}},
1909 {"macchwu.", XO (4, 140,0,1),XO_MASK
, PPC405
|PPC440
, {RT
, RA
, RB
}},
1910 {"vmaxsh", VX (4, 322), VX_MASK
, PPCVEC
, {VD
, VA
, VB
}},
1911 {"vslh", VX (4, 324), VX_MASK
, PPCVEC
, {VD
, VA
, VB
}},
1912 {"vmulosh", VX (4, 328), VX_MASK
, PPCVEC
, {VD
, VA
, VB
}},
1913 {"vrsqrtefp", VX (4, 330), VX_MASK
, PPCVEC
, {VD
, VB
}},
1914 {"vmrglh", VX (4, 332), VX_MASK
, PPCVEC
, {VD
, VA
, VB
}},
1915 {"vpkswus", VX (4, 334), VX_MASK
, PPCVEC
, {VD
, VA
, VB
}},
1916 {"mulchw", XRC(4, 168,0), X_MASK
, PPC405
|PPC440
, {RT
, RA
, RB
}},
1917 {"mulchw.", XRC(4, 168,1), X_MASK
, PPC405
|PPC440
, {RT
, RA
, RB
}},
1918 {"macchw", XO (4, 172,0,0),XO_MASK
, PPC405
|PPC440
, {RT
, RA
, RB
}},
1919 {"macchw.", XO (4, 172,0,1),XO_MASK
, PPC405
|PPC440
, {RT
, RA
, RB
}},
1920 {"nmacchw", XO (4, 174,0,0),XO_MASK
, PPC405
|PPC440
, {RT
, RA
, RB
}},
1921 {"nmacchw.", XO (4, 174,0,1),XO_MASK
, PPC405
|PPC440
, {RT
, RA
, RB
}},
1922 {"vaddcuw", VX (4, 384), VX_MASK
, PPCVEC
, {VD
, VA
, VB
}},
1923 {"vmaxsw", VX (4, 386), VX_MASK
, PPCVEC
, {VD
, VA
, VB
}},
1924 {"vslw", VX (4, 388), VX_MASK
, PPCVEC
, {VD
, VA
, VB
}},
1925 {"vexptefp", VX (4, 394), VX_MASK
, PPCVEC
, {VD
, VB
}},
1926 {"vmrglw", VX (4, 396), VX_MASK
, PPCVEC
, {VD
, VA
, VB
}},
1927 {"vpkshss", VX (4, 398), VX_MASK
, PPCVEC
, {VD
, VA
, VB
}},
1928 {"macchwsu", XO (4, 204,0,0),XO_MASK
, PPC405
|PPC440
, {RT
, RA
, RB
}},
1929 {"macchwsu.", XO (4, 204,0,1),XO_MASK
, PPC405
|PPC440
, {RT
, RA
, RB
}},
1930 {"vsl", VX (4, 452), VX_MASK
, PPCVEC
, {VD
, VA
, VB
}},
1931 {"vcmpgefp", VXR(4, 454,0), VXR_MASK
, PPCVEC
, {VD
, VA
, VB
}},
1932 {"vlogefp", VX (4, 458), VX_MASK
, PPCVEC
, {VD
, VB
}},
1933 {"vpkswss", VX (4, 462), VX_MASK
, PPCVEC
, {VD
, VA
, VB
}},
1934 {"macchws", XO (4, 236,0,0),XO_MASK
, PPC405
|PPC440
, {RT
, RA
, RB
}},
1935 {"macchws.", XO (4, 236,0,1),XO_MASK
, PPC405
|PPC440
, {RT
, RA
, RB
}},
1936 {"nmacchws", XO (4, 238,0,0),XO_MASK
, PPC405
|PPC440
, {RT
, RA
, RB
}},
1937 {"nmacchws.", XO (4, 238,0,1),XO_MASK
, PPC405
|PPC440
, {RT
, RA
, RB
}},
1938 {"evaddw", VX (4, 512), VX_MASK
, PPCSPE
, {RS
, RA
, RB
}},
1939 {"vaddubs", VX (4, 512), VX_MASK
, PPCVEC
, {VD
, VA
, VB
}},
1940 {"evaddiw", VX (4, 514), VX_MASK
, PPCSPE
, {RS
, RB
, UIMM
}},
1941 {"vminub", VX (4, 514), VX_MASK
, PPCVEC
, {VD
, VA
, VB
}},
1942 {"evsubfw", VX (4, 516), VX_MASK
, PPCSPE
, {RS
, RA
, RB
}},
1943 {"evsubw", VX (4, 516), VX_MASK
, PPCSPE
, {RS
, RB
, RA
}},
1944 {"vsrb", VX (4, 516), VX_MASK
, PPCVEC
, {VD
, VA
, VB
}},
1945 {"evsubifw", VX (4, 518), VX_MASK
, PPCSPE
, {RS
, UIMM
, RB
}},
1946 {"evsubiw", VX (4, 518), VX_MASK
, PPCSPE
, {RS
, RB
, UIMM
}},
1947 {"vcmpgtub", VXR(4, 518,0), VXR_MASK
, PPCVEC
, {VD
, VA
, VB
}},
1948 {"evabs", VX (4, 520), VX_MASK
, PPCSPE
, {RS
, RA
}},
1949 {"vmuleub", VX (4, 520), VX_MASK
, PPCVEC
, {VD
, VA
, VB
}},
1950 {"evneg", VX (4, 521), VX_MASK
, PPCSPE
, {RS
, RA
}},
1951 {"evextsb", VX (4, 522), VX_MASK
, PPCSPE
, {RS
, RA
}},
1952 {"vrfin", VX (4, 522), VX_MASK
, PPCVEC
, {VD
, VB
}},
1953 {"evextsh", VX (4, 523), VX_MASK
, PPCSPE
, {RS
, RA
}},
1954 {"evrndw", VX (4, 524), VX_MASK
, PPCSPE
, {RS
, RA
}},
1955 {"vspltb", VX (4, 524), VX_MASK
, PPCVEC
, {VD
, VB
, UIMM
}},
1956 {"evcntlzw", VX (4, 525), VX_MASK
, PPCSPE
, {RS
, RA
}},
1957 {"evcntlsw", VX (4, 526), VX_MASK
, PPCSPE
, {RS
, RA
}},
1958 {"vupkhsb", VX (4, 526), VX_MASK
, PPCVEC
, {VD
, VB
}},
1959 {"brinc", VX (4, 527), VX_MASK
, PPCSPE
, {RS
, RA
, RB
}},
1960 {"ps_abs", XRC(4, 264,0), XRA_MASK
, PPCPS
, {FRT
, FRB
}},
1961 {"ps_abs.", XRC(4, 264,1), XRA_MASK
, PPCPS
, {FRT
, FRB
}},
1962 {"evand", VX (4, 529), VX_MASK
, PPCSPE
, {RS
, RA
, RB
}},
1963 {"evandc", VX (4, 530), VX_MASK
, PPCSPE
, {RS
, RA
, RB
}},
1964 {"evxor", VX (4, 534), VX_MASK
, PPCSPE
, {RS
, RA
, RB
}},
1965 {"evmr", VX (4, 535), VX_MASK
, PPCSPE
, {RS
, RA
, BBA
}},
1966 {"evor", VX (4, 535), VX_MASK
, PPCSPE
, {RS
, RA
, RB
}},
1967 {"evnor", VX (4, 536), VX_MASK
, PPCSPE
, {RS
, RA
, RB
}},
1968 {"evnot", VX (4, 536), VX_MASK
, PPCSPE
, {RS
, RA
, BBA
}},
1969 {"get", APU(4, 268,0), APU_RA_MASK
, PPC405
, {RT
, FSL
}},
1970 {"eveqv", VX (4, 537), VX_MASK
, PPCSPE
, {RS
, RA
, RB
}},
1971 {"evorc", VX (4, 539), VX_MASK
, PPCSPE
, {RS
, RA
, RB
}},
1972 {"evnand", VX (4, 542), VX_MASK
, PPCSPE
, {RS
, RA
, RB
}},
1973 {"evsrwu", VX (4, 544), VX_MASK
, PPCSPE
, {RS
, RA
, RB
}},
1974 {"evsrws", VX (4, 545), VX_MASK
, PPCSPE
, {RS
, RA
, RB
}},
1975 {"evsrwiu", VX (4, 546), VX_MASK
, PPCSPE
, {RS
, RA
, EVUIMM
}},
1976 {"evsrwis", VX (4, 547), VX_MASK
, PPCSPE
, {RS
, RA
, EVUIMM
}},
1977 {"evslw", VX (4, 548), VX_MASK
, PPCSPE
, {RS
, RA
, RB
}},
1978 {"evslwi", VX (4, 550), VX_MASK
, PPCSPE
, {RS
, RA
, EVUIMM
}},
1979 {"evrlw", VX (4, 552), VX_MASK
, PPCSPE
, {RS
, RA
, RB
}},
1980 {"evsplati", VX (4, 553), VX_MASK
, PPCSPE
, {RS
, SIMM
}},
1981 {"evrlwi", VX (4, 554), VX_MASK
, PPCSPE
, {RS
, RA
, EVUIMM
}},
1982 {"evsplatfi", VX (4, 555), VX_MASK
, PPCSPE
, {RS
, SIMM
}},
1983 {"evmergehi", VX (4, 556), VX_MASK
, PPCSPE
, {RS
, RA
, RB
}},
1984 {"evmergelo", VX (4, 557), VX_MASK
, PPCSPE
, {RS
, RA
, RB
}},
1985 {"evmergehilo", VX (4, 558), VX_MASK
, PPCSPE
, {RS
, RA
, RB
}},
1986 {"evmergelohi", VX (4, 559), VX_MASK
, PPCSPE
, {RS
, RA
, RB
}},
1987 {"evcmpgtu", VX (4, 560), VX_MASK
, PPCSPE
, {CRFD
, RA
, RB
}},
1988 {"evcmpgts", VX (4, 561), VX_MASK
, PPCSPE
, {CRFD
, RA
, RB
}},
1989 {"evcmpltu", VX (4, 562), VX_MASK
, PPCSPE
, {CRFD
, RA
, RB
}},
1990 {"evcmplts", VX (4, 563), VX_MASK
, PPCSPE
, {CRFD
, RA
, RB
}},
1991 {"evcmpeq", VX (4, 564), VX_MASK
, PPCSPE
, {CRFD
, RA
, RB
}},
1992 {"cget", APU(4, 284,0), APU_RA_MASK
, PPC405
, {RT
, FSL
}},
1993 {"vadduhs", VX (4, 576), VX_MASK
, PPCVEC
, {VD
, VA
, VB
}},
1994 {"vminuh", VX (4, 578), VX_MASK
, PPCVEC
, {VD
, VA
, VB
}},
1995 {"vsrh", VX (4, 580), VX_MASK
, PPCVEC
, {VD
, VA
, VB
}},
1996 {"vcmpgtuh", VXR(4, 582,0), VXR_MASK
, PPCVEC
, {VD
, VA
, VB
}},
1997 {"vmuleuh", VX (4, 584), VX_MASK
, PPCVEC
, {VD
, VA
, VB
}},
1998 {"vrfiz", VX (4, 586), VX_MASK
, PPCVEC
, {VD
, VB
}},
1999 {"vsplth", VX (4, 588), VX_MASK
, PPCVEC
, {VD
, VB
, UIMM
}},
2000 {"vupkhsh", VX (4, 590), VX_MASK
, PPCVEC
, {VD
, VB
}},
2001 {"nget", APU(4, 300,0), APU_RA_MASK
, PPC405
, {RT
, FSL
}},
2002 {"evsel", EVSEL(4,79), EVSEL_MASK
, PPCSPE
, {RS
, RA
, RB
, CRFS
}},
2003 {"ncget", APU(4, 316,0), APU_RA_MASK
, PPC405
, {RT
, FSL
}},
2004 {"evfsadd", VX (4, 640), VX_MASK
, PPCSPE
, {RS
, RA
, RB
}},
2005 {"vadduws", VX (4, 640), VX_MASK
, PPCVEC
, {VD
, VA
, VB
}},
2006 {"evfssub", VX (4, 641), VX_MASK
, PPCSPE
, {RS
, RA
, RB
}},
2007 {"vminuw", VX (4, 642), VX_MASK
, PPCVEC
, {VD
, VA
, VB
}},
2008 {"evfsabs", VX (4, 644), VX_MASK
, PPCSPE
, {RS
, RA
}},
2009 {"vsrw", VX (4, 644), VX_MASK
, PPCVEC
, {VD
, VA
, VB
}},
2010 {"evfsnabs", VX (4, 645), VX_MASK
, PPCSPE
, {RS
, RA
}},
2011 {"evfsneg", VX (4, 646), VX_MASK
, PPCSPE
, {RS
, RA
}},
2012 {"vcmpgtuw", VXR(4, 646,0), VXR_MASK
, PPCVEC
, {VD
, VA
, VB
}},
2013 {"evfsmul", VX (4, 648), VX_MASK
, PPCSPE
, {RS
, RA
, RB
}},
2014 {"evfsdiv", VX (4, 649), VX_MASK
, PPCSPE
, {RS
, RA
, RB
}},
2015 {"vrfip", VX (4, 650), VX_MASK
, PPCVEC
, {VD
, VB
}},
2016 {"evfscmpgt", VX (4, 652), VX_MASK
, PPCSPE
, {CRFD
, RA
, RB
}},
2017 {"vspltw", VX (4, 652), VX_MASK
, PPCVEC
, {VD
, VB
, UIMM
}},
2018 {"evfscmplt", VX (4, 653), VX_MASK
, PPCSPE
, {CRFD
, RA
, RB
}},
2019 {"evfscmpeq", VX (4, 654), VX_MASK
, PPCSPE
, {CRFD
, RA
, RB
}},
2020 {"vupklsb", VX (4, 654), VX_MASK
, PPCVEC
, {VD
, VB
}},
2021 {"evfscfui", VX (4, 656), VX_MASK
, PPCSPE
, {RS
, RB
}},
2022 {"evfscfsi", VX (4, 657), VX_MASK
, PPCSPE
, {RS
, RB
}},
2023 {"evfscfuf", VX (4, 658), VX_MASK
, PPCSPE
, {RS
, RB
}},
2024 {"evfscfsf", VX (4, 659), VX_MASK
, PPCSPE
, {RS
, RB
}},
2025 {"evfsctui", VX (4, 660), VX_MASK
, PPCSPE
, {RS
, RB
}},
2026 {"evfsctsi", VX (4, 661), VX_MASK
, PPCSPE
, {RS
, RB
}},
2027 {"evfsctuf", VX (4, 662), VX_MASK
, PPCSPE
, {RS
, RB
}},
2028 {"evfsctsf", VX (4, 663), VX_MASK
, PPCSPE
, {RS
, RB
}},
2029 {"evfsctuiz", VX (4, 664), VX_MASK
, PPCSPE
, {RS
, RB
}},
2030 {"put", APU(4, 332,0), APU_RT_MASK
, PPC405
, {RA
, FSL
}},
2031 {"evfsctsiz", VX (4, 666), VX_MASK
, PPCSPE
, {RS
, RB
}},
2032 {"evfststgt", VX (4, 668), VX_MASK
, PPCSPE
, {CRFD
, RA
, RB
}},
2033 {"evfststlt", VX (4, 669), VX_MASK
, PPCSPE
, {CRFD
, RA
, RB
}},
2034 {"evfststeq", VX (4, 670), VX_MASK
, PPCSPE
, {CRFD
, RA
, RB
}},
2035 {"cput", APU(4, 348,0), APU_RT_MASK
, PPC405
, {RA
, FSL
}},
2036 {"efsadd", VX (4, 704), VX_MASK
, PPCEFS
, {RS
, RA
, RB
}},
2037 {"efssub", VX (4, 705), VX_MASK
, PPCEFS
, {RS
, RA
, RB
}},
2038 {"efsabs", VX (4, 708), VX_MASK
, PPCEFS
, {RS
, RA
}},
2039 {"vsr", VX (4, 708), VX_MASK
, PPCVEC
, {VD
, VA
, VB
}},
2040 {"efsnabs", VX (4, 709), VX_MASK
, PPCEFS
, {RS
, RA
}},
2041 {"efsneg", VX (4, 710), VX_MASK
, PPCEFS
, {RS
, RA
}},
2042 {"vcmpgtfp", VXR(4, 710,0), VXR_MASK
, PPCVEC
, {VD
, VA
, VB
}},
2043 {"efsmul", VX (4, 712), VX_MASK
, PPCEFS
, {RS
, RA
, RB
}},
2044 {"efsdiv", VX (4, 713), VX_MASK
, PPCEFS
, {RS
, RA
, RB
}},
2045 {"vrfim", VX (4, 714), VX_MASK
, PPCVEC
, {VD
, VB
}},
2046 {"efscmpgt", VX (4, 716), VX_MASK
, PPCEFS
, {CRFD
, RA
, RB
}},
2047 {"efscmplt", VX (4, 717), VX_MASK
, PPCEFS
, {CRFD
, RA
, RB
}},
2048 {"efscmpeq", VX (4, 718), VX_MASK
, PPCEFS
, {CRFD
, RA
, RB
}},
2049 {"vupklsh", VX (4, 718), VX_MASK
, PPCVEC
, {VD
, VB
}},
2050 {"efscfd", VX (4, 719), VX_MASK
, PPCEFS
, {RS
, RB
}},
2051 {"efscfui", VX (4, 720), VX_MASK
, PPCEFS
, {RS
, RB
}},
2052 {"efscfsi", VX (4, 721), VX_MASK
, PPCEFS
, {RS
, RB
}},
2053 {"efscfuf", VX (4, 722), VX_MASK
, PPCEFS
, {RS
, RB
}},
2054 {"efscfsf", VX (4, 723), VX_MASK
, PPCEFS
, {RS
, RB
}},
2055 {"efsctui", VX (4, 724), VX_MASK
, PPCEFS
, {RS
, RB
}},
2056 {"efsctsi", VX (4, 725), VX_MASK
, PPCEFS
, {RS
, RB
}},
2057 {"efsctuf", VX (4, 726), VX_MASK
, PPCEFS
, {RS
, RB
}},
2058 {"efsctsf", VX (4, 727), VX_MASK
, PPCEFS
, {RS
, RB
}},
2059 {"efsctuiz", VX (4, 728), VX_MASK
, PPCEFS
, {RS
, RB
}},
2060 {"nput", APU(4, 364,0), APU_RT_MASK
, PPC405
, {RA
, FSL
}},
2061 {"efsctsiz", VX (4, 730), VX_MASK
, PPCEFS
, {RS
, RB
}},
2062 {"efststgt", VX (4, 732), VX_MASK
, PPCEFS
, {CRFD
, RA
, RB
}},
2063 {"efststlt", VX (4, 733), VX_MASK
, PPCEFS
, {CRFD
, RA
, RB
}},
2064 {"efststeq", VX (4, 734), VX_MASK
, PPCEFS
, {CRFD
, RA
, RB
}},
2065 {"efdadd", VX (4, 736), VX_MASK
, PPCEFS
, {RS
, RA
, RB
}},
2066 {"efdsub", VX (4, 737), VX_MASK
, PPCEFS
, {RS
, RA
, RB
}},
2067 {"efdcfuid", VX (4, 738), VX_MASK
, PPCEFS
, {RS
, RB
}},
2068 {"efdcfsid", VX (4, 739), VX_MASK
, PPCEFS
, {RS
, RB
}},
2069 {"efdabs", VX (4, 740), VX_MASK
, PPCEFS
, {RS
, RA
}},
2070 {"efdnabs", VX (4, 741), VX_MASK
, PPCEFS
, {RS
, RA
}},
2071 {"efdneg", VX (4, 742), VX_MASK
, PPCEFS
, {RS
, RA
}},
2072 {"efdmul", VX (4, 744), VX_MASK
, PPCEFS
, {RS
, RA
, RB
}},
2073 {"efddiv", VX (4, 745), VX_MASK
, PPCEFS
, {RS
, RA
, RB
}},
2074 {"efdctuidz", VX (4, 746), VX_MASK
, PPCEFS
, {RS
, RB
}},
2075 {"efdctsidz", VX (4, 747), VX_MASK
, PPCEFS
, {RS
, RB
}},
2076 {"efdcmpgt", VX (4, 748), VX_MASK
, PPCEFS
, {CRFD
, RA
, RB
}},
2077 {"efdcmplt", VX (4, 749), VX_MASK
, PPCEFS
, {CRFD
, RA
, RB
}},
2078 {"efdcmpeq", VX (4, 750), VX_MASK
, PPCEFS
, {CRFD
, RA
, RB
}},
2079 {"efdcfs", VX (4, 751), VX_MASK
, PPCEFS
, {RS
, RB
}},
2080 {"efdcfui", VX (4, 752), VX_MASK
, PPCEFS
, {RS
, RB
}},
2081 {"efdcfsi", VX (4, 753), VX_MASK
, PPCEFS
, {RS
, RB
}},
2082 {"efdcfuf", VX (4, 754), VX_MASK
, PPCEFS
, {RS
, RB
}},
2083 {"efdcfsf", VX (4, 755), VX_MASK
, PPCEFS
, {RS
, RB
}},
2084 {"efdctui", VX (4, 756), VX_MASK
, PPCEFS
, {RS
, RB
}},
2085 {"efdctsi", VX (4, 757), VX_MASK
, PPCEFS
, {RS
, RB
}},
2086 {"efdctuf", VX (4, 758), VX_MASK
, PPCEFS
, {RS
, RB
}},
2087 {"efdctsf", VX (4, 759), VX_MASK
, PPCEFS
, {RS
, RB
}},
2088 {"efdctuiz", VX (4, 760), VX_MASK
, PPCEFS
, {RS
, RB
}},
2089 {"ncput", APU(4, 380,0), APU_RT_MASK
, PPC405
, {RA
, FSL
}},
2090 {"efdctsiz", VX (4, 762), VX_MASK
, PPCEFS
, {RS
, RB
}},
2091 {"efdtstgt", VX (4, 764), VX_MASK
, PPCEFS
, {CRFD
, RA
, RB
}},
2092 {"efdtstlt", VX (4, 765), VX_MASK
, PPCEFS
, {CRFD
, RA
, RB
}},
2093 {"efdtsteq", VX (4, 766), VX_MASK
, PPCEFS
, {CRFD
, RA
, RB
}},
2094 {"evlddx", VX (4, 768), VX_MASK
, PPCSPE
, {RS
, RA
, RB
}},
2095 {"vaddsbs", VX (4, 768), VX_MASK
, PPCVEC
, {VD
, VA
, VB
}},
2096 {"evldd", VX (4, 769), VX_MASK
, PPCSPE
, {RS
, EVUIMM_8
, RA
}},
2097 {"evldwx", VX (4, 770), VX_MASK
, PPCSPE
, {RS
, RA
, RB
}},
2098 {"vminsb", VX (4, 770), VX_MASK
, PPCVEC
, {VD
, VA
, VB
}},
2099 {"evldw", VX (4, 771), VX_MASK
, PPCSPE
, {RS
, EVUIMM_8
, RA
}},
2100 {"evldhx", VX (4, 772), VX_MASK
, PPCSPE
, {RS
, RA
, RB
}},
2101 {"vsrab", VX (4, 772), VX_MASK
, PPCVEC
, {VD
, VA
, VB
}},
2102 {"evldh", VX (4, 773), VX_MASK
, PPCSPE
, {RS
, EVUIMM_8
, RA
}},
2103 {"vcmpgtsb", VXR(4, 774,0), VXR_MASK
, PPCVEC
, {VD
, VA
, VB
}},
2104 {"evlhhesplatx",VX (4, 776), VX_MASK
, PPCSPE
, {RS
, RA
, RB
}},
2105 {"vmulesb", VX (4, 776), VX_MASK
, PPCVEC
, {VD
, VA
, VB
}},
2106 {"evlhhesplat", VX (4, 777), VX_MASK
, PPCSPE
, {RS
, EVUIMM_2
, RA
}},
2107 {"vcfux", VX (4, 778), VX_MASK
, PPCVEC
, {VD
, VB
, UIMM
}},
2108 {"evlhhousplatx",VX(4, 780), VX_MASK
, PPCSPE
, {RS
, RA
, RB
}},
2109 {"vspltisb", VX (4, 780), VX_MASK
, PPCVEC
, {VD
, SIMM
}},
2110 {"evlhhousplat",VX (4, 781), VX_MASK
, PPCSPE
, {RS
, EVUIMM_2
, RA
}},
2111 {"evlhhossplatx",VX(4, 782), VX_MASK
, PPCSPE
, {RS
, RA
, RB
}},
2112 {"vpkpx", VX (4, 782), VX_MASK
, PPCVEC
, {VD
, VA
, VB
}},
2113 {"evlhhossplat",VX (4, 783), VX_MASK
, PPCSPE
, {RS
, EVUIMM_2
, RA
}},
2114 {"mullhwu", XRC(4, 392,0), X_MASK
, PPC405
|PPC440
, {RT
, RA
, RB
}},
2115 {"evlwhex", VX (4, 784), VX_MASK
, PPCSPE
, {RS
, RA
, RB
}},
2116 {"mullhwu.", XRC(4, 392,1), X_MASK
, PPC405
|PPC440
, {RT
, RA
, RB
}},
2117 {"evlwhe", VX (4, 785), VX_MASK
, PPCSPE
, {RS
, EVUIMM_4
, RA
}},
2118 {"evlwhoux", VX (4, 788), VX_MASK
, PPCSPE
, {RS
, RA
, RB
}},
2119 {"evlwhou", VX (4, 789), VX_MASK
, PPCSPE
, {RS
, EVUIMM_4
, RA
}},
2120 {"evlwhosx", VX (4, 790), VX_MASK
, PPCSPE
, {RS
, RA
, RB
}},
2121 {"evlwhos", VX (4, 791), VX_MASK
, PPCSPE
, {RS
, EVUIMM_4
, RA
}},
2122 {"maclhwu", XO (4, 396,0,0),XO_MASK
, PPC405
|PPC440
, {RT
, RA
, RB
}},
2123 {"evlwwsplatx", VX (4, 792), VX_MASK
, PPCSPE
, {RS
, RA
, RB
}},
2124 {"maclhwu.", XO (4, 396,0,1),XO_MASK
, PPC405
|PPC440
, {RT
, RA
, RB
}},
2125 {"evlwwsplat", VX (4, 793), VX_MASK
, PPCSPE
, {RS
, EVUIMM_4
, RA
}},
2126 {"evlwhsplatx", VX (4, 796), VX_MASK
, PPCSPE
, {RS
, RA
, RB
}},
2127 {"evlwhsplat", VX (4, 797), VX_MASK
, PPCSPE
, {RS
, EVUIMM_4
, RA
}},
2128 {"evstddx", VX (4, 800), VX_MASK
, PPCSPE
, {RS
, RA
, RB
}},
2129 {"evstdd", VX (4, 801), VX_MASK
, PPCSPE
, {RS
, EVUIMM_8
, RA
}},
2130 {"evstdwx", VX (4, 802), VX_MASK
, PPCSPE
, {RS
, RA
, RB
}},
2131 {"evstdw", VX (4, 803), VX_MASK
, PPCSPE
, {RS
, EVUIMM_8
, RA
}},
2132 {"evstdhx", VX (4, 804), VX_MASK
, PPCSPE
, {RS
, RA
, RB
}},
2133 {"evstdh", VX (4, 805), VX_MASK
, PPCSPE
, {RS
, EVUIMM_8
, RA
}},
2134 {"evstwhex", VX (4, 816), VX_MASK
, PPCSPE
, {RS
, RA
, RB
}},
2135 {"evstwhe", VX (4, 817), VX_MASK
, PPCSPE
, {RS
, EVUIMM_4
, RA
}},
2136 {"evstwhox", VX (4, 820), VX_MASK
, PPCSPE
, {RS
, RA
, RB
}},
2137 {"evstwho", VX (4, 821), VX_MASK
, PPCSPE
, {RS
, EVUIMM_4
, RA
}},
2138 {"evstwwex", VX (4, 824), VX_MASK
, PPCSPE
, {RS
, RA
, RB
}},
2139 {"evstwwe", VX (4, 825), VX_MASK
, PPCSPE
, {RS
, EVUIMM_4
, RA
}},
2140 {"evstwwox", VX (4, 828), VX_MASK
, PPCSPE
, {RS
, RA
, RB
}},
2141 {"evstwwo", VX (4, 829), VX_MASK
, PPCSPE
, {RS
, EVUIMM_4
, RA
}},
2142 {"vaddshs", VX (4, 832), VX_MASK
, PPCVEC
, {VD
, VA
, VB
}},
2143 {"vminsh", VX (4, 834), VX_MASK
, PPCVEC
, {VD
, VA
, VB
}},
2144 {"vsrah", VX (4, 836), VX_MASK
, PPCVEC
, {VD
, VA
, VB
}},
2145 {"vcmpgtsh", VXR(4, 838,0), VXR_MASK
, PPCVEC
, {VD
, VA
, VB
}},
2146 {"vmulesh", VX (4, 840), VX_MASK
, PPCVEC
, {VD
, VA
, VB
}},
2147 {"vcfsx", VX (4, 842), VX_MASK
, PPCVEC
, {VD
, VB
, UIMM
}},
2148 {"vspltish", VX (4, 844), VX_MASK
, PPCVEC
, {VD
, SIMM
}},
2149 {"vupkhpx", VX (4, 846), VX_MASK
, PPCVEC
, {VD
, VB
}},
2150 {"mullhw", XRC(4, 424,0), X_MASK
, PPC405
|PPC440
, {RT
, RA
, RB
}},
2151 {"mullhw.", XRC(4, 424,1), X_MASK
, PPC405
|PPC440
, {RT
, RA
, RB
}},
2152 {"maclhw", XO (4, 428,0,0),XO_MASK
, PPC405
|PPC440
, {RT
, RA
, RB
}},
2153 {"maclhw.", XO (4, 428,0,1),XO_MASK
, PPC405
|PPC440
, {RT
, RA
, RB
}},
2154 {"nmaclhw", XO (4, 430,0,0),XO_MASK
, PPC405
|PPC440
, {RT
, RA
, RB
}},
2155 {"nmaclhw.", XO (4, 430,0,1),XO_MASK
, PPC405
|PPC440
, {RT
, RA
, RB
}},
2156 {"vaddsws", VX (4, 896), VX_MASK
, PPCVEC
, {VD
, VA
, VB
}},
2157 {"vminsw", VX (4, 898), VX_MASK
, PPCVEC
, {VD
, VA
, VB
}},
2158 {"vsraw", VX (4, 900), VX_MASK
, PPCVEC
, {VD
, VA
, VB
}},
2159 {"vcmpgtsw", VXR(4, 902,0), VXR_MASK
, PPCVEC
, {VD
, VA
, VB
}},
2160 {"vctuxs", VX (4, 906), VX_MASK
, PPCVEC
, {VD
, VB
, UIMM
}},
2161 {"vspltisw", VX (4, 908), VX_MASK
, PPCVEC
, {VD
, SIMM
}},
2162 {"maclhwsu", XO (4, 460,0,0),XO_MASK
, PPC405
|PPC440
, {RT
, RA
, RB
}},
2163 {"maclhwsu.", XO (4, 460,0,1),XO_MASK
, PPC405
|PPC440
, {RT
, RA
, RB
}},
2164 {"vcmpbfp", VXR(4, 966,0), VXR_MASK
, PPCVEC
, {VD
, VA
, VB
}},
2165 {"vctsxs", VX (4, 970), VX_MASK
, PPCVEC
, {VD
, VB
, UIMM
}},
2166 {"vupklpx", VX (4, 974), VX_MASK
, PPCVEC
, {VD
, VB
}},
2167 {"maclhws", XO (4, 492,0,0),XO_MASK
, PPC405
|PPC440
, {RT
, RA
, RB
}},
2168 {"maclhws.", XO (4, 492,0,1),XO_MASK
, PPC405
|PPC440
, {RT
, RA
, RB
}},
2169 {"nmaclhws", XO (4, 494,0,0),XO_MASK
, PPC405
|PPC440
, {RT
, RA
, RB
}},
2170 {"nmaclhws.", XO (4, 494,0,1),XO_MASK
, PPC405
|PPC440
, {RT
, RA
, RB
}},
2171 {"vsububm", VX (4,1024), VX_MASK
, PPCVEC
, {VD
, VA
, VB
}},
2172 {"vavgub", VX (4,1026), VX_MASK
, PPCVEC
, {VD
, VA
, VB
}},
2173 {"evmhessf", VX (4,1027), VX_MASK
, PPCSPE
, {RS
, RA
, RB
}},
2174 {"vand", VX (4,1028), VX_MASK
, PPCVEC
, {VD
, VA
, VB
}},
2175 {"vcmpequb.", VXR(4, 6,1), VXR_MASK
, PPCVEC
, {VD
, VA
, VB
}},
2176 {"udi0fcm.", APU(4, 515,0), APU_MASK
, PPC405
|PPC440
, {URT
, URA
, URB
}},
2177 {"udi0fcm", APU(4, 515,1), APU_MASK
, PPC405
|PPC440
, {URT
, URA
, URB
}},
2178 {"evmhossf", VX (4,1031), VX_MASK
, PPCSPE
, {RS
, RA
, RB
}},
2179 {"evmheumi", VX (4,1032), VX_MASK
, PPCSPE
, {RS
, RA
, RB
}},
2180 {"evmhesmi", VX (4,1033), VX_MASK
, PPCSPE
, {RS
, RA
, RB
}},
2181 {"vmaxfp", VX (4,1034), VX_MASK
, PPCVEC
, {VD
, VA
, VB
}},
2182 {"evmhesmf", VX (4,1035), VX_MASK
, PPCSPE
, {RS
, RA
, RB
}},
2183 {"evmhoumi", VX (4,1036), VX_MASK
, PPCSPE
, {RS
, RA
, RB
}},
2184 {"vslo", VX (4,1036), VX_MASK
, PPCVEC
, {VD
, VA
, VB
}},
2185 {"evmhosmi", VX (4,1037), VX_MASK
, PPCSPE
, {RS
, RA
, RB
}},
2186 {"evmhosmf", VX (4,1039), VX_MASK
, PPCSPE
, {RS
, RA
, RB
}},
2187 {"machhwuo", XO (4, 12,1,0),XO_MASK
, PPC405
|PPC440
, {RT
, RA
, RB
}},
2188 {"machhwuo.", XO (4, 12,1,1),XO_MASK
, PPC405
|PPC440
, {RT
, RA
, RB
}},
2189 {"ps_merge00", XOPS(4,528,0), XOPS_MASK
, PPCPS
, {FRT
, FRA
, FRB
}},
2190 {"ps_merge00.", XOPS(4,528,1), XOPS_MASK
, PPCPS
, {FRT
, FRA
, FRB
}},
2191 {"evmhessfa", VX (4,1059), VX_MASK
, PPCSPE
, {RS
, RA
, RB
}},
2192 {"evmhossfa", VX (4,1063), VX_MASK
, PPCSPE
, {RS
, RA
, RB
}},
2193 {"evmheumia", VX (4,1064), VX_MASK
, PPCSPE
, {RS
, RA
, RB
}},
2194 {"evmhesmia", VX (4,1065), VX_MASK
, PPCSPE
, {RS
, RA
, RB
}},
2195 {"evmhesmfa", VX (4,1067), VX_MASK
, PPCSPE
, {RS
, RA
, RB
}},
2196 {"evmhoumia", VX (4,1068), VX_MASK
, PPCSPE
, {RS
, RA
, RB
}},
2197 {"evmhosmia", VX (4,1069), VX_MASK
, PPCSPE
, {RS
, RA
, RB
}},
2198 {"evmhosmfa", VX (4,1071), VX_MASK
, PPCSPE
, {RS
, RA
, RB
}},
2199 {"vsubuhm", VX (4,1088), VX_MASK
, PPCVEC
, {VD
, VA
, VB
}},
2200 {"vavguh", VX (4,1090), VX_MASK
, PPCVEC
, {VD
, VA
, VB
}},
2201 {"vandc", VX (4,1092), VX_MASK
, PPCVEC
, {VD
, VA
, VB
}},
2202 {"vcmpequh.", VXR(4, 70,1), VXR_MASK
, PPCVEC
, {VD
, VA
, VB
}},
2203 {"udi1fcm.", APU(4, 547,0), APU_MASK
, PPC405
|PPC440
, {URT
, URA
, URB
}},
2204 {"udi1fcm", APU(4, 547,1), APU_MASK
, PPC405
|PPC440
, {URT
, URA
, URB
}},
2205 {"evmwhssf", VX (4,1095), VX_MASK
, PPCSPE
, {RS
, RA
, RB
}},
2206 {"evmwlumi", VX (4,1096), VX_MASK
, PPCSPE
, {RS
, RA
, RB
}},
2207 {"vminfp", VX (4,1098), VX_MASK
, PPCVEC
, {VD
, VA
, VB
}},
2208 {"evmwhumi", VX (4,1100), VX_MASK
, PPCSPE
, {RS
, RA
, RB
}},
2209 {"vsro", VX (4,1100), VX_MASK
, PPCVEC
, {VD
, VA
, VB
}},
2210 {"evmwhsmi", VX (4,1101), VX_MASK
, PPCSPE
, {RS
, RA
, RB
}},
2211 {"evmwhsmf", VX (4,1103), VX_MASK
, PPCSPE
, {RS
, RA
, RB
}},
2212 {"evmwssf", VX (4,1107), VX_MASK
, PPCSPE
, {RS
, RA
, RB
}},
2213 {"machhwo", XO (4, 44,1,0),XO_MASK
, PPC405
|PPC440
, {RT
, RA
, RB
}},
2214 {"evmwumi", VX (4,1112), VX_MASK
, PPCSPE
, {RS
, RA
, RB
}},
2215 {"machhwo.", XO (4, 44,1,1),XO_MASK
, PPC405
|PPC440
, {RT
, RA
, RB
}},
2216 {"evmwsmi", VX (4,1113), VX_MASK
, PPCSPE
, {RS
, RA
, RB
}},
2217 {"evmwsmf", VX (4,1115), VX_MASK
, PPCSPE
, {RS
, RA
, RB
}},
2218 {"nmachhwo", XO (4, 46,1,0),XO_MASK
, PPC405
|PPC440
, {RT
, RA
, RB
}},
2219 {"nmachhwo.", XO (4, 46,1,1),XO_MASK
, PPC405
|PPC440
, {RT
, RA
, RB
}},
2220 {"ps_merge01", XOPS(4,560,0), XOPS_MASK
, PPCPS
, {FRT
, FRA
, FRB
}},
2221 {"ps_merge01.", XOPS(4,560,1), XOPS_MASK
, PPCPS
, {FRT
, FRA
, FRB
}},
2222 {"evmwhssfa", VX (4,1127), VX_MASK
, PPCSPE
, {RS
, RA
, RB
}},
2223 {"evmwlumia", VX (4,1128), VX_MASK
, PPCSPE
, {RS
, RA
, RB
}},
2224 {"evmwhumia", VX (4,1132), VX_MASK
, PPCSPE
, {RS
, RA
, RB
}},
2225 {"evmwhsmia", VX (4,1133), VX_MASK
, PPCSPE
, {RS
, RA
, RB
}},
2226 {"evmwhsmfa", VX (4,1135), VX_MASK
, PPCSPE
, {RS
, RA
, RB
}},
2227 {"evmwssfa", VX (4,1139), VX_MASK
, PPCSPE
, {RS
, RA
, RB
}},
2228 {"evmwumia", VX (4,1144), VX_MASK
, PPCSPE
, {RS
, RA
, RB
}},
2229 {"evmwsmia", VX (4,1145), VX_MASK
, PPCSPE
, {RS
, RA
, RB
}},
2230 {"evmwsmfa", VX (4,1147), VX_MASK
, PPCSPE
, {RS
, RA
, RB
}},
2231 {"vsubuwm", VX (4,1152), VX_MASK
, PPCVEC
, {VD
, VA
, VB
}},
2232 {"vavguw", VX (4,1154), VX_MASK
, PPCVEC
, {VD
, VA
, VB
}},
2233 {"vor", VX (4,1156), VX_MASK
, PPCVEC
, {VD
, VA
, VB
}},
2234 {"vcmpequw.", VXR(4, 134,1), VXR_MASK
, PPCVEC
, {VD
, VA
, VB
}},
2235 {"udi2fcm.", APU(4, 579,0), APU_MASK
, PPC405
|PPC440
, {URT
, URA
, URB
}},
2236 {"udi2fcm", APU(4, 579,1), APU_MASK
, PPC405
|PPC440
, {URT
, URA
, URB
}},
2237 {"machhwsuo", XO (4, 76,1,0),XO_MASK
, PPC405
|PPC440
, {RT
, RA
, RB
}},
2238 {"machhwsuo.", XO (4, 76,1,1),XO_MASK
, PPC405
|PPC440
, {RT
, RA
, RB
}},
2239 {"ps_merge10", XOPS(4,592,0), XOPS_MASK
, PPCPS
, {FRT
, FRA
, FRB
}},
2240 {"ps_merge10.", XOPS(4,592,1), XOPS_MASK
, PPCPS
, {FRT
, FRA
, FRB
}},
2241 {"evaddusiaaw", VX (4,1216), VX_MASK
, PPCSPE
, {RS
, RA
}},
2242 {"evaddssiaaw", VX (4,1217), VX_MASK
, PPCSPE
, {RS
, RA
}},
2243 {"evsubfusiaaw",VX (4,1218), VX_MASK
, PPCSPE
, {RS
, RA
}},
2244 {"evsubfssiaaw",VX (4,1219), VX_MASK
, PPCSPE
, {RS
, RA
}},
2245 {"evmra", VX (4,1220), VX_MASK
, PPCSPE
, {RS
, RA
}},
2246 {"vxor", VX (4,1220), VX_MASK
, PPCVEC
, {VD
, VA
, VB
}},
2247 {"evdivws", VX (4,1222), VX_MASK
, PPCSPE
, {RS
, RA
, RB
}},
2248 {"vcmpeqfp.", VXR(4, 198,1), VXR_MASK
, PPCVEC
, {VD
, VA
, VB
}},
2249 {"udi3fcm.", APU(4, 611,0), APU_MASK
, PPC405
|PPC440
, {URT
, URA
, URB
}},
2250 {"udi3fcm", APU(4, 611,1), APU_MASK
, PPC405
|PPC440
, {URT
, URA
, URB
}},
2251 {"evdivwu", VX (4,1223), VX_MASK
, PPCSPE
, {RS
, RA
, RB
}},
2252 {"evaddumiaaw", VX (4,1224), VX_MASK
, PPCSPE
, {RS
, RA
}},
2253 {"evaddsmiaaw", VX (4,1225), VX_MASK
, PPCSPE
, {RS
, RA
}},
2254 {"evsubfumiaaw",VX (4,1226), VX_MASK
, PPCSPE
, {RS
, RA
}},
2255 {"evsubfsmiaaw",VX (4,1227), VX_MASK
, PPCSPE
, {RS
, RA
}},
2256 {"machhwso", XO (4, 108,1,0),XO_MASK
, PPC405
|PPC440
, {RT
, RA
, RB
}},
2257 {"machhwso.", XO (4, 108,1,1),XO_MASK
, PPC405
|PPC440
, {RT
, RA
, RB
}},
2258 {"nmachhwso", XO (4, 110,1,0),XO_MASK
, PPC405
|PPC440
, {RT
, RA
, RB
}},
2259 {"nmachhwso.", XO (4, 110,1,1),XO_MASK
, PPC405
|PPC440
, {RT
, RA
, RB
}},
2260 {"ps_merge11", XOPS(4,624,0), XOPS_MASK
, PPCPS
, {FRT
, FRA
, FRB
}},
2261 {"ps_merge11.", XOPS(4,624,1), XOPS_MASK
, PPCPS
, {FRT
, FRA
, FRB
}},
2262 {"evmheusiaaw", VX (4,1280), VX_MASK
, PPCSPE
, {RS
, RA
, RB
}},
2263 {"evmhessiaaw", VX (4,1281), VX_MASK
, PPCSPE
, {RS
, RA
, RB
}},
2264 {"vavgsb", VX (4,1282), VX_MASK
, PPCVEC
, {VD
, VA
, VB
}},
2265 {"evmhessfaaw", VX (4,1283), VX_MASK
, PPCSPE
, {RS
, RA
, RB
}},
2266 {"evmhousiaaw", VX (4,1284), VX_MASK
, PPCSPE
, {RS
, RA
, RB
}},
2267 {"vnor", VX (4,1284), VX_MASK
, PPCVEC
, {VD
, VA
, VB
}},
2268 {"evmhossiaaw", VX (4,1285), VX_MASK
, PPCSPE
, {RS
, RA
, RB
}},
2269 {"udi4fcm.", APU(4, 643,0), APU_MASK
, PPC405
|PPC440
, {URT
, URA
, URB
}},
2270 {"udi4fcm", APU(4, 643,1), APU_MASK
, PPC405
|PPC440
, {URT
, URA
, URB
}},
2271 {"evmhossfaaw", VX (4,1287), VX_MASK
, PPCSPE
, {RS
, RA
, RB
}},
2272 {"evmheumiaaw", VX (4,1288), VX_MASK
, PPCSPE
, {RS
, RA
, RB
}},
2273 {"evmhesmiaaw", VX (4,1289), VX_MASK
, PPCSPE
, {RS
, RA
, RB
}},
2274 {"evmhesmfaaw", VX (4,1291), VX_MASK
, PPCSPE
, {RS
, RA
, RB
}},
2275 {"evmhoumiaaw", VX (4,1292), VX_MASK
, PPCSPE
, {RS
, RA
, RB
}},
2276 {"evmhosmiaaw", VX (4,1293), VX_MASK
, PPCSPE
, {RS
, RA
, RB
}},
2277 {"evmhosmfaaw", VX (4,1295), VX_MASK
, PPCSPE
, {RS
, RA
, RB
}},
2278 {"macchwuo", XO (4, 140,1,0),XO_MASK
, PPC405
|PPC440
, {RT
, RA
, RB
}},
2279 {"macchwuo.", XO (4, 140,1,1),XO_MASK
, PPC405
|PPC440
, {RT
, RA
, RB
}},
2280 {"evmhegumiaa", VX (4,1320), VX_MASK
, PPCSPE
, {RS
, RA
, RB
}},
2281 {"evmhegsmiaa", VX (4,1321), VX_MASK
, PPCSPE
, {RS
, RA
, RB
}},
2282 {"evmhegsmfaa", VX (4,1323), VX_MASK
, PPCSPE
, {RS
, RA
, RB
}},
2283 {"evmhogumiaa", VX (4,1324), VX_MASK
, PPCSPE
, {RS
, RA
, RB
}},
2284 {"evmhogsmiaa", VX (4,1325), VX_MASK
, PPCSPE
, {RS
, RA
, RB
}},
2285 {"evmhogsmfaa", VX (4,1327), VX_MASK
, PPCSPE
, {RS
, RA
, RB
}},
2286 {"evmwlusiaaw", VX (4,1344), VX_MASK
, PPCSPE
, {RS
, RA
, RB
}},
2287 {"evmwlssiaaw", VX (4,1345), VX_MASK
, PPCSPE
, {RS
, RA
, RB
}},
2288 {"vavgsh", VX (4,1346), VX_MASK
, PPCVEC
, {VD
, VA
, VB
}},
2289 {"udi5fcm.", APU(4, 675,0), APU_MASK
, PPC405
|PPC440
, {URT
, URA
, URB
}},
2290 {"udi5fcm", APU(4, 675,1), APU_MASK
, PPC405
|PPC440
, {URT
, URA
, URB
}},
2291 {"evmwlumiaaw", VX (4,1352), VX_MASK
, PPCSPE
, {RS
, RA
, RB
}},
2292 {"evmwlsmiaaw", VX (4,1353), VX_MASK
, PPCSPE
, {RS
, RA
, RB
}},
2293 {"evmwssfaa", VX (4,1363), VX_MASK
, PPCSPE
, {RS
, RA
, RB
}},
2294 {"macchwo", XO (4, 172,1,0),XO_MASK
, PPC405
|PPC440
, {RT
, RA
, RB
}},
2295 {"evmwumiaa", VX (4,1368), VX_MASK
, PPCSPE
, {RS
, RA
, RB
}},
2296 {"macchwo.", XO (4, 172,1,1),XO_MASK
, PPC405
|PPC440
, {RT
, RA
, RB
}},
2297 {"evmwsmiaa", VX (4,1369), VX_MASK
, PPCSPE
, {RS
, RA
, RB
}},
2298 {"evmwsmfaa", VX (4,1371), VX_MASK
, PPCSPE
, {RS
, RA
, RB
}},
2299 {"nmacchwo", XO (4, 174,1,0),XO_MASK
, PPC405
|PPC440
, {RT
, RA
, RB
}},
2300 {"nmacchwo.", XO (4, 174,1,1),XO_MASK
, PPC405
|PPC440
, {RT
, RA
, RB
}},
2301 {"evmheusianw", VX (4,1408), VX_MASK
, PPCSPE
, {RS
, RA
, RB
}},
2302 {"vsubcuw", VX (4,1408), VX_MASK
, PPCVEC
, {VD
, VA
, VB
}},
2303 {"evmhessianw", VX (4,1409), VX_MASK
, PPCSPE
, {RS
, RA
, RB
}},
2304 {"vavgsw", VX (4,1410), VX_MASK
, PPCVEC
, {VD
, VA
, VB
}},
2305 {"evmhessfanw", VX (4,1411), VX_MASK
, PPCSPE
, {RS
, RA
, RB
}},
2306 {"evmhousianw", VX (4,1412), VX_MASK
, PPCSPE
, {RS
, RA
, RB
}},
2307 {"evmhossianw", VX (4,1413), VX_MASK
, PPCSPE
, {RS
, RA
, RB
}},
2308 {"udi6fcm.", APU(4, 707,0), APU_MASK
, PPC405
|PPC440
, {URT
, URA
, URB
}},
2309 {"udi6fcm", APU(4, 707,1), APU_MASK
, PPC405
|PPC440
, {URT
, URA
, URB
}},
2310 {"evmhossfanw", VX (4,1415), VX_MASK
, PPCSPE
, {RS
, RA
, RB
}},
2311 {"evmheumianw", VX (4,1416), VX_MASK
, PPCSPE
, {RS
, RA
, RB
}},
2312 {"evmhesmianw", VX (4,1417), VX_MASK
, PPCSPE
, {RS
, RA
, RB
}},
2313 {"evmhesmfanw", VX (4,1419), VX_MASK
, PPCSPE
, {RS
, RA
, RB
}},
2314 {"evmhoumianw", VX (4,1420), VX_MASK
, PPCSPE
, {RS
, RA
, RB
}},
2315 {"evmhosmianw", VX (4,1421), VX_MASK
, PPCSPE
, {RS
, RA
, RB
}},
2316 {"evmhosmfanw", VX (4,1423), VX_MASK
, PPCSPE
, {RS
, RA
, RB
}},
2317 {"macchwsuo", XO (4, 204,1,0),XO_MASK
, PPC405
|PPC440
, {RT
, RA
, RB
}},
2318 {"macchwsuo.", XO (4, 204,1,1),XO_MASK
, PPC405
|PPC440
, {RT
, RA
, RB
}},
2319 {"evmhegumian", VX (4,1448), VX_MASK
, PPCSPE
, {RS
, RA
, RB
}},
2320 {"evmhegsmian", VX (4,1449), VX_MASK
, PPCSPE
, {RS
, RA
, RB
}},
2321 {"evmhegsmfan", VX (4,1451), VX_MASK
, PPCSPE
, {RS
, RA
, RB
}},
2322 {"evmhogumian", VX (4,1452), VX_MASK
, PPCSPE
, {RS
, RA
, RB
}},
2323 {"evmhogsmian", VX (4,1453), VX_MASK
, PPCSPE
, {RS
, RA
, RB
}},
2324 {"evmhogsmfan", VX (4,1455), VX_MASK
, PPCSPE
, {RS
, RA
, RB
}},
2325 {"evmwlusianw", VX (4,1472), VX_MASK
, PPCSPE
, {RS
, RA
, RB
}},
2326 {"evmwlssianw", VX (4,1473), VX_MASK
, PPCSPE
, {RS
, RA
, RB
}},
2327 {"vcmpgefp.", VXR(4, 454,1), VXR_MASK
, PPCVEC
, {VD
, VA
, VB
}},
2328 {"udi7fcm.", APU(4, 739,0), APU_MASK
, PPC405
|PPC440
, {URT
, URA
, URB
}},
2329 {"udi7fcm", APU(4, 739,1), APU_MASK
, PPC405
|PPC440
, {URT
, URA
, URB
}},
2330 {"evmwlumianw", VX (4,1480), VX_MASK
, PPCSPE
, {RS
, RA
, RB
}},
2331 {"evmwlsmianw", VX (4,1481), VX_MASK
, PPCSPE
, {RS
, RA
, RB
}},
2332 {"evmwssfan", VX (4,1491), VX_MASK
, PPCSPE
, {RS
, RA
, RB
}},
2333 {"macchwso", XO (4, 236,1,0),XO_MASK
, PPC405
|PPC440
, {RT
, RA
, RB
}},
2334 {"evmwumian", VX (4,1496), VX_MASK
, PPCSPE
, {RS
, RA
, RB
}},
2335 {"macchwso.", XO (4, 236,1,1),XO_MASK
, PPC405
|PPC440
, {RT
, RA
, RB
}},
2336 {"evmwsmian", VX (4,1497), VX_MASK
, PPCSPE
, {RS
, RA
, RB
}},
2337 {"evmwsmfan", VX (4,1499), VX_MASK
, PPCSPE
, {RS
, RA
, RB
}},
2338 {"nmacchwso", XO (4, 238,1,0),XO_MASK
, PPC405
|PPC440
, {RT
, RA
, RB
}},
2339 {"nmacchwso.", XO (4, 238,1,1),XO_MASK
, PPC405
|PPC440
, {RT
, RA
, RB
}},
2340 {"vsububs", VX (4,1536), VX_MASK
, PPCVEC
, {VD
, VA
, VB
}},
2341 {"mfvscr", VX (4,1540), VX_MASK
, PPCVEC
, {VD
}},
2342 {"vcmpgtub.", VXR(4, 518,1), VXR_MASK
, PPCVEC
, {VD
, VA
, VB
}},
2343 {"udi8fcm.", APU(4, 771,0), APU_MASK
, PPC440
, {URT
, URA
, URB
}},
2344 {"udi8fcm", APU(4, 771,1), APU_MASK
, PPC440
, {URT
, URA
, URB
}},
2345 {"vsum4ubs", VX (4,1544), VX_MASK
, PPCVEC
, {VD
, VA
, VB
}},
2346 {"vsubuhs", VX (4,1600), VX_MASK
, PPCVEC
, {VD
, VA
, VB
}},
2347 {"mtvscr", VX (4,1604), VX_MASK
, PPCVEC
, {VB
}},
2348 {"vcmpgtuh.", VXR(4, 582,1), VXR_MASK
, PPCVEC
, {VD
, VA
, VB
}},
2349 {"vsum4shs", VX (4,1608), VX_MASK
, PPCVEC
, {VD
, VA
, VB
}},
2350 {"udi9fcm.", APU(4, 804,0), APU_MASK
, PPC440
, {URT
, URA
, URB
}},
2351 {"udi9fcm", APU(4, 804,1), APU_MASK
, PPC440
, {URT
, URA
, URB
}},
2352 {"vsubuws", VX (4,1664), VX_MASK
, PPCVEC
, {VD
, VA
, VB
}},
2353 {"vcmpgtuw.", VXR(4, 646,1), VXR_MASK
, PPCVEC
, {VD
, VA
, VB
}},
2354 {"udi10fcm.", APU(4, 835,0), APU_MASK
, PPC440
, {URT
, URA
, URB
}},
2355 {"udi10fcm", APU(4, 835,1), APU_MASK
, PPC440
, {URT
, URA
, URB
}},
2356 {"vsum2sws", VX (4,1672), VX_MASK
, PPCVEC
, {VD
, VA
, VB
}},
2357 {"vcmpgtfp.", VXR(4, 710,1), VXR_MASK
, PPCVEC
, {VD
, VA
, VB
}},
2358 {"udi11fcm.", APU(4, 867,0), APU_MASK
, PPC440
, {URT
, URA
, URB
}},
2359 {"udi11fcm", APU(4, 867,1), APU_MASK
, PPC440
, {URT
, URA
, URB
}},
2360 {"vsubsbs", VX (4,1792), VX_MASK
, PPCVEC
, {VD
, VA
, VB
}},
2361 {"vcmpgtsb.", VXR(4, 774,1), VXR_MASK
, PPCVEC
, {VD
, VA
, VB
}},
2362 {"udi12fcm.", APU(4, 899,0), APU_MASK
, PPC440
, {URT
, URA
, URB
}},
2363 {"udi12fcm", APU(4, 899,1), APU_MASK
, PPC440
, {URT
, URA
, URB
}},
2364 {"vsum4sbs", VX (4,1800), VX_MASK
, PPCVEC
, {VD
, VA
, VB
}},
2365 {"maclhwuo", XO (4, 396,1,0),XO_MASK
, PPC405
|PPC440
, {RT
, RA
, RB
}},
2366 {"maclhwuo.", XO (4, 396,1,1),XO_MASK
, PPC405
|PPC440
, {RT
, RA
, RB
}},
2367 {"vsubshs", VX (4,1856), VX_MASK
, PPCVEC
, {VD
, VA
, VB
}},
2368 {"vcmpgtsh.", VXR(4, 838,1), VXR_MASK
, PPCVEC
, {VD
, VA
, VB
}},
2369 {"udi13fcm.", APU(4, 931,0), APU_MASK
, PPC440
, {URT
, URA
, URB
}},
2370 {"udi13fcm", APU(4, 931,1), APU_MASK
, PPC440
, {URT
, URA
, URB
}},
2371 {"maclhwo", XO (4, 428,1,0),XO_MASK
, PPC405
|PPC440
, {RT
, RA
, RB
}},
2372 {"maclhwo.", XO (4, 428,1,1),XO_MASK
, PPC405
|PPC440
, {RT
, RA
, RB
}},
2373 {"nmaclhwo", XO (4, 430,1,0),XO_MASK
, PPC405
|PPC440
, {RT
, RA
, RB
}},
2374 {"nmaclhwo.", XO (4, 430,1,1),XO_MASK
, PPC405
|PPC440
, {RT
, RA
, RB
}},
2375 {"vsubsws", VX (4,1920), VX_MASK
, PPCVEC
, {VD
, VA
, VB
}},
2376 {"vcmpgtsw.", VXR(4, 902,1), VXR_MASK
, PPCVEC
, {VD
, VA
, VB
}},
2377 {"udi14fcm.", APU(4, 963,0), APU_MASK
, PPC440
, {URT
, URA
, URB
}},
2378 {"udi14fcm", APU(4, 963,1), APU_MASK
, PPC440
, {URT
, URA
, URB
}},
2379 {"vsumsws", VX (4,1928), VX_MASK
, PPCVEC
, {VD
, VA
, VB
}},
2380 {"maclhwsuo", XO (4, 460,1,0),XO_MASK
, PPC405
|PPC440
, {RT
, RA
, RB
}},
2381 {"maclhwsuo.", XO (4, 460,1,1),XO_MASK
, PPC405
|PPC440
, {RT
, RA
, RB
}},
2382 {"vcmpbfp.", VXR(4, 966,1), VXR_MASK
, PPCVEC
, {VD
, VA
, VB
}},
2383 {"udi15fcm.", APU(4, 995,0), APU_MASK
, PPC440
, {URT
, URA
, URB
}},
2384 {"udi15fcm", APU(4, 995,1), APU_MASK
, PPC440
, {URT
, URA
, URB
}},
2385 {"maclhwso", XO (4, 492,1,0),XO_MASK
, PPC405
|PPC440
, {RT
, RA
, RB
}},
2386 {"maclhwso.", XO (4, 492,1,1),XO_MASK
, PPC405
|PPC440
, {RT
, RA
, RB
}},
2387 {"nmaclhwso", XO (4, 494,1,0),XO_MASK
, PPC405
|PPC440
, {RT
, RA
, RB
}},
2388 {"nmaclhwso.", XO (4, 494,1,1),XO_MASK
, PPC405
|PPC440
, {RT
, RA
, RB
}},
2389 {"dcbz_l", X (4,1014), XRT_MASK
, PPCPS
, {RA
, RB
}},
2391 {"mulli", OP(7), OP_MASK
, PPCCOM
, {RT
, RA
, SI
}},
2392 {"muli", OP(7), OP_MASK
, PWRCOM
, {RT
, RA
, SI
}},
2394 {"subfic", OP(8), OP_MASK
, PPCCOM
, {RT
, RA
, SI
}},
2395 {"sfi", OP(8), OP_MASK
, PWRCOM
, {RT
, RA
, SI
}},
2397 {"dozi", OP(9), OP_MASK
, M601
, {RT
, RA
, SI
}},
2399 {"bce", B(9,0,0), B_MASK
, BOOKE64
, {BO
, BI
, BD
}},
2400 {"bcel", B(9,0,1), B_MASK
, BOOKE64
, {BO
, BI
, BD
}},
2401 {"bcea", B(9,1,0), B_MASK
, BOOKE64
, {BO
, BI
, BDA
}},
2402 {"bcela", B(9,1,1), B_MASK
, BOOKE64
, {BO
, BI
, BDA
}},
2404 {"cmplwi", OPL(10,0), OPL_MASK
, PPCCOM
, {OBF
, RA
, UI
}},
2405 {"cmpldi", OPL(10,1), OPL_MASK
, PPC64
, {OBF
, RA
, UI
}},
2406 {"cmpli", OP(10), OP_MASK
, PPC
, {BF
, L
, RA
, UI
}},
2407 {"cmpli", OP(10), OP_MASK
, PWRCOM
, {BF
, RA
, UI
}},
2409 {"cmpwi", OPL(11,0), OPL_MASK
, PPCCOM
, {OBF
, RA
, SI
}},
2410 {"cmpdi", OPL(11,1), OPL_MASK
, PPC64
, {OBF
, RA
, SI
}},
2411 {"cmpi", OP(11), OP_MASK
, PPC
, {BF
, L
, RA
, SI
}},
2412 {"cmpi", OP(11), OP_MASK
, PWRCOM
, {BF
, RA
, SI
}},
2414 {"addic", OP(12), OP_MASK
, PPCCOM
, {RT
, RA
, SI
}},
2415 {"ai", OP(12), OP_MASK
, PWRCOM
, {RT
, RA
, SI
}},
2416 {"subic", OP(12), OP_MASK
, PPCCOM
, {RT
, RA
, NSI
}},
2418 {"addic.", OP(13), OP_MASK
, PPCCOM
, {RT
, RA
, SI
}},
2419 {"ai.", OP(13), OP_MASK
, PWRCOM
, {RT
, RA
, SI
}},
2420 {"subic.", OP(13), OP_MASK
, PPCCOM
, {RT
, RA
, NSI
}},
2422 {"li", OP(14), DRA_MASK
, PPCCOM
, {RT
, SI
}},
2423 {"lil", OP(14), DRA_MASK
, PWRCOM
, {RT
, SI
}},
2424 {"addi", OP(14), OP_MASK
, PPCCOM
, {RT
, RA0
, SI
}},
2425 {"cal", OP(14), OP_MASK
, PWRCOM
, {RT
, D
, RA0
}},
2426 {"subi", OP(14), OP_MASK
, PPCCOM
, {RT
, RA0
, NSI
}},
2427 {"la", OP(14), OP_MASK
, PPCCOM
, {RT
, D
, RA0
}},
2429 {"lis", OP(15), DRA_MASK
, PPCCOM
, {RT
, SISIGNOPT
}},
2430 {"liu", OP(15), DRA_MASK
, PWRCOM
, {RT
, SISIGNOPT
}},
2431 {"addis", OP(15), OP_MASK
, PPCCOM
, {RT
, RA0
, SISIGNOPT
}},
2432 {"cau", OP(15), OP_MASK
, PWRCOM
, {RT
, RA0
, SISIGNOPT
}},
2433 {"subis", OP(15), OP_MASK
, PPCCOM
, {RT
, RA0
, NSI
}},
2435 {"bdnz-", BBO(16,BODNZ
,0,0), BBOATBI_MASK
, PPCCOM
, {BDM
}},
2436 {"bdnz+", BBO(16,BODNZ
,0,0), BBOATBI_MASK
, PPCCOM
, {BDP
}},
2437 {"bdnz", BBO(16,BODNZ
,0,0), BBOATBI_MASK
, PPCCOM
, {BD
}},
2438 {"bdn", BBO(16,BODNZ
,0,0), BBOATBI_MASK
, PWRCOM
, {BD
}},
2439 {"bdnzl-", BBO(16,BODNZ
,0,1), BBOATBI_MASK
, PPCCOM
, {BDM
}},
2440 {"bdnzl+", BBO(16,BODNZ
,0,1), BBOATBI_MASK
, PPCCOM
, {BDP
}},
2441 {"bdnzl", BBO(16,BODNZ
,0,1), BBOATBI_MASK
, PPCCOM
, {BD
}},
2442 {"bdnl", BBO(16,BODNZ
,0,1), BBOATBI_MASK
, PWRCOM
, {BD
}},
2443 {"bdnza-", BBO(16,BODNZ
,1,0), BBOATBI_MASK
, PPCCOM
, {BDMA
}},
2444 {"bdnza+", BBO(16,BODNZ
,1,0), BBOATBI_MASK
, PPCCOM
, {BDPA
}},
2445 {"bdnza", BBO(16,BODNZ
,1,0), BBOATBI_MASK
, PPCCOM
, {BDA
}},
2446 {"bdna", BBO(16,BODNZ
,1,0), BBOATBI_MASK
, PWRCOM
, {BDA
}},
2447 {"bdnzla-", BBO(16,BODNZ
,1,1), BBOATBI_MASK
, PPCCOM
, {BDMA
}},
2448 {"bdnzla+", BBO(16,BODNZ
,1,1), BBOATBI_MASK
, PPCCOM
, {BDPA
}},
2449 {"bdnzla", BBO(16,BODNZ
,1,1), BBOATBI_MASK
, PPCCOM
, {BDA
}},
2450 {"bdnla", BBO(16,BODNZ
,1,1), BBOATBI_MASK
, PWRCOM
, {BDA
}},
2451 {"bdz-", BBO(16,BODZ
,0,0), BBOATBI_MASK
, PPCCOM
, {BDM
}},
2452 {"bdz+", BBO(16,BODZ
,0,0), BBOATBI_MASK
, PPCCOM
, {BDP
}},
2453 {"bdz", BBO(16,BODZ
,0,0), BBOATBI_MASK
, COM
, {BD
}},
2454 {"bdzl-", BBO(16,BODZ
,0,1), BBOATBI_MASK
, PPCCOM
, {BDM
}},
2455 {"bdzl+", BBO(16,BODZ
,0,1), BBOATBI_MASK
, PPCCOM
, {BDP
}},
2456 {"bdzl", BBO(16,BODZ
,0,1), BBOATBI_MASK
, COM
, {BD
}},
2457 {"bdza-", BBO(16,BODZ
,1,0), BBOATBI_MASK
, PPCCOM
, {BDMA
}},
2458 {"bdza+", BBO(16,BODZ
,1,0), BBOATBI_MASK
, PPCCOM
, {BDPA
}},
2459 {"bdza", BBO(16,BODZ
,1,0), BBOATBI_MASK
, COM
, {BDA
}},
2460 {"bdzla-", BBO(16,BODZ
,1,1), BBOATBI_MASK
, PPCCOM
, {BDMA
}},
2461 {"bdzla+", BBO(16,BODZ
,1,1), BBOATBI_MASK
, PPCCOM
, {BDPA
}},
2462 {"bdzla", BBO(16,BODZ
,1,1), BBOATBI_MASK
, COM
, {BDA
}},
2464 {"bge-", BBOCB(16,BOF
,CBLT
,0,0), BBOATCB_MASK
, PPCCOM
, {CR
, BDM
}},
2465 {"bge+", BBOCB(16,BOF
,CBLT
,0,0), BBOATCB_MASK
, PPCCOM
, {CR
, BDP
}},
2466 {"bge", BBOCB(16,BOF
,CBLT
,0,0), BBOATCB_MASK
, COM
, {CR
, BD
}},
2467 {"bnl-", BBOCB(16,BOF
,CBLT
,0,0), BBOATCB_MASK
, PPCCOM
, {CR
, BDM
}},
2468 {"bnl+", BBOCB(16,BOF
,CBLT
,0,0), BBOATCB_MASK
, PPCCOM
, {CR
, BDP
}},
2469 {"bnl", BBOCB(16,BOF
,CBLT
,0,0), BBOATCB_MASK
, COM
, {CR
, BD
}},
2470 {"bgel-", BBOCB(16,BOF
,CBLT
,0,1), BBOATCB_MASK
, PPCCOM
, {CR
, BDM
}},
2471 {"bgel+", BBOCB(16,BOF
,CBLT
,0,1), BBOATCB_MASK
, PPCCOM
, {CR
, BDP
}},
2472 {"bgel", BBOCB(16,BOF
,CBLT
,0,1), BBOATCB_MASK
, COM
, {CR
, BD
}},
2473 {"bnll-", BBOCB(16,BOF
,CBLT
,0,1), BBOATCB_MASK
, PPCCOM
, {CR
, BDM
}},
2474 {"bnll+", BBOCB(16,BOF
,CBLT
,0,1), BBOATCB_MASK
, PPCCOM
, {CR
, BDP
}},
2475 {"bnll", BBOCB(16,BOF
,CBLT
,0,1), BBOATCB_MASK
, COM
, {CR
, BD
}},
2476 {"bgea-", BBOCB(16,BOF
,CBLT
,1,0), BBOATCB_MASK
, PPCCOM
, {CR
, BDMA
}},
2477 {"bgea+", BBOCB(16,BOF
,CBLT
,1,0), BBOATCB_MASK
, PPCCOM
, {CR
, BDPA
}},
2478 {"bgea", BBOCB(16,BOF
,CBLT
,1,0), BBOATCB_MASK
, COM
, {CR
, BDA
}},
2479 {"bnla-", BBOCB(16,BOF
,CBLT
,1,0), BBOATCB_MASK
, PPCCOM
, {CR
, BDMA
}},
2480 {"bnla+", BBOCB(16,BOF
,CBLT
,1,0), BBOATCB_MASK
, PPCCOM
, {CR
, BDPA
}},
2481 {"bnla", BBOCB(16,BOF
,CBLT
,1,0), BBOATCB_MASK
, COM
, {CR
, BDA
}},
2482 {"bgela-", BBOCB(16,BOF
,CBLT
,1,1), BBOATCB_MASK
, PPCCOM
, {CR
, BDMA
}},
2483 {"bgela+", BBOCB(16,BOF
,CBLT
,1,1), BBOATCB_MASK
, PPCCOM
, {CR
, BDPA
}},
2484 {"bgela", BBOCB(16,BOF
,CBLT
,1,1), BBOATCB_MASK
, COM
, {CR
, BDA
}},
2485 {"bnlla-", BBOCB(16,BOF
,CBLT
,1,1), BBOATCB_MASK
, PPCCOM
, {CR
, BDMA
}},
2486 {"bnlla+", BBOCB(16,BOF
,CBLT
,1,1), BBOATCB_MASK
, PPCCOM
, {CR
, BDPA
}},
2487 {"bnlla", BBOCB(16,BOF
,CBLT
,1,1), BBOATCB_MASK
, COM
, {CR
, BDA
}},
2488 {"ble-", BBOCB(16,BOF
,CBGT
,0,0), BBOATCB_MASK
, PPCCOM
, {CR
, BDM
}},
2489 {"ble+", BBOCB(16,BOF
,CBGT
,0,0), BBOATCB_MASK
, PPCCOM
, {CR
, BDP
}},
2490 {"ble", BBOCB(16,BOF
,CBGT
,0,0), BBOATCB_MASK
, COM
, {CR
, BD
}},
2491 {"bng-", BBOCB(16,BOF
,CBGT
,0,0), BBOATCB_MASK
, PPCCOM
, {CR
, BDM
}},
2492 {"bng+", BBOCB(16,BOF
,CBGT
,0,0), BBOATCB_MASK
, PPCCOM
, {CR
, BDP
}},
2493 {"bng", BBOCB(16,BOF
,CBGT
,0,0), BBOATCB_MASK
, COM
, {CR
, BD
}},
2494 {"blel-", BBOCB(16,BOF
,CBGT
,0,1), BBOATCB_MASK
, PPCCOM
, {CR
, BDM
}},
2495 {"blel+", BBOCB(16,BOF
,CBGT
,0,1), BBOATCB_MASK
, PPCCOM
, {CR
, BDP
}},
2496 {"blel", BBOCB(16,BOF
,CBGT
,0,1), BBOATCB_MASK
, COM
, {CR
, BD
}},
2497 {"bngl-", BBOCB(16,BOF
,CBGT
,0,1), BBOATCB_MASK
, PPCCOM
, {CR
, BDM
}},
2498 {"bngl+", BBOCB(16,BOF
,CBGT
,0,1), BBOATCB_MASK
, PPCCOM
, {CR
, BDP
}},
2499 {"bngl", BBOCB(16,BOF
,CBGT
,0,1), BBOATCB_MASK
, COM
, {CR
, BD
}},
2500 {"blea-", BBOCB(16,BOF
,CBGT
,1,0), BBOATCB_MASK
, PPCCOM
, {CR
, BDMA
}},
2501 {"blea+", BBOCB(16,BOF
,CBGT
,1,0), BBOATCB_MASK
, PPCCOM
, {CR
, BDPA
}},
2502 {"blea", BBOCB(16,BOF
,CBGT
,1,0), BBOATCB_MASK
, COM
, {CR
, BDA
}},
2503 {"bnga-", BBOCB(16,BOF
,CBGT
,1,0), BBOATCB_MASK
, PPCCOM
, {CR
, BDMA
}},
2504 {"bnga+", BBOCB(16,BOF
,CBGT
,1,0), BBOATCB_MASK
, PPCCOM
, {CR
, BDPA
}},
2505 {"bnga", BBOCB(16,BOF
,CBGT
,1,0), BBOATCB_MASK
, COM
, {CR
, BDA
}},
2506 {"blela-", BBOCB(16,BOF
,CBGT
,1,1), BBOATCB_MASK
, PPCCOM
, {CR
, BDMA
}},
2507 {"blela+", BBOCB(16,BOF
,CBGT
,1,1), BBOATCB_MASK
, PPCCOM
, {CR
, BDPA
}},
2508 {"blela", BBOCB(16,BOF
,CBGT
,1,1), BBOATCB_MASK
, COM
, {CR
, BDA
}},
2509 {"bngla-", BBOCB(16,BOF
,CBGT
,1,1), BBOATCB_MASK
, PPCCOM
, {CR
, BDMA
}},
2510 {"bngla+", BBOCB(16,BOF
,CBGT
,1,1), BBOATCB_MASK
, PPCCOM
, {CR
, BDPA
}},
2511 {"bngla", BBOCB(16,BOF
,CBGT
,1,1), BBOATCB_MASK
, COM
, {CR
, BDA
}},
2512 {"bne-", BBOCB(16,BOF
,CBEQ
,0,0), BBOATCB_MASK
, PPCCOM
, {CR
, BDM
}},
2513 {"bne+", BBOCB(16,BOF
,CBEQ
,0,0), BBOATCB_MASK
, PPCCOM
, {CR
, BDP
}},
2514 {"bne", BBOCB(16,BOF
,CBEQ
,0,0), BBOATCB_MASK
, COM
, {CR
, BD
}},
2515 {"bnel-", BBOCB(16,BOF
,CBEQ
,0,1), BBOATCB_MASK
, PPCCOM
, {CR
, BDM
}},
2516 {"bnel+", BBOCB(16,BOF
,CBEQ
,0,1), BBOATCB_MASK
, PPCCOM
, {CR
, BDP
}},
2517 {"bnel", BBOCB(16,BOF
,CBEQ
,0,1), BBOATCB_MASK
, COM
, {CR
, BD
}},
2518 {"bnea-", BBOCB(16,BOF
,CBEQ
,1,0), BBOATCB_MASK
, PPCCOM
, {CR
, BDMA
}},
2519 {"bnea+", BBOCB(16,BOF
,CBEQ
,1,0), BBOATCB_MASK
, PPCCOM
, {CR
, BDPA
}},
2520 {"bnea", BBOCB(16,BOF
,CBEQ
,1,0), BBOATCB_MASK
, COM
, {CR
, BDA
}},
2521 {"bnela-", BBOCB(16,BOF
,CBEQ
,1,1), BBOATCB_MASK
, PPCCOM
, {CR
, BDMA
}},
2522 {"bnela+", BBOCB(16,BOF
,CBEQ
,1,1), BBOATCB_MASK
, PPCCOM
, {CR
, BDPA
}},
2523 {"bnela", BBOCB(16,BOF
,CBEQ
,1,1), BBOATCB_MASK
, COM
, {CR
, BDA
}},
2524 {"bns-", BBOCB(16,BOF
,CBSO
,0,0), BBOATCB_MASK
, PPCCOM
, {CR
, BDM
}},
2525 {"bns+", BBOCB(16,BOF
,CBSO
,0,0), BBOATCB_MASK
, PPCCOM
, {CR
, BDP
}},
2526 {"bns", BBOCB(16,BOF
,CBSO
,0,0), BBOATCB_MASK
, COM
, {CR
, BD
}},
2527 {"bnu-", BBOCB(16,BOF
,CBSO
,0,0), BBOATCB_MASK
, PPCCOM
, {CR
, BDM
}},
2528 {"bnu+", BBOCB(16,BOF
,CBSO
,0,0), BBOATCB_MASK
, PPCCOM
, {CR
, BDP
}},
2529 {"bnu", BBOCB(16,BOF
,CBSO
,0,0), BBOATCB_MASK
, PPCCOM
, {CR
, BD
}},
2530 {"bnsl-", BBOCB(16,BOF
,CBSO
,0,1), BBOATCB_MASK
, PPCCOM
, {CR
, BDM
}},
2531 {"bnsl+", BBOCB(16,BOF
,CBSO
,0,1), BBOATCB_MASK
, PPCCOM
, {CR
, BDP
}},
2532 {"bnsl", BBOCB(16,BOF
,CBSO
,0,1), BBOATCB_MASK
, COM
, {CR
, BD
}},
2533 {"bnul-", BBOCB(16,BOF
,CBSO
,0,1), BBOATCB_MASK
, PPCCOM
, {CR
, BDM
}},
2534 {"bnul+", BBOCB(16,BOF
,CBSO
,0,1), BBOATCB_MASK
, PPCCOM
, {CR
, BDP
}},
2535 {"bnul", BBOCB(16,BOF
,CBSO
,0,1), BBOATCB_MASK
, PPCCOM
, {CR
, BD
}},
2536 {"bnsa-", BBOCB(16,BOF
,CBSO
,1,0), BBOATCB_MASK
, PPCCOM
, {CR
, BDMA
}},
2537 {"bnsa+", BBOCB(16,BOF
,CBSO
,1,0), BBOATCB_MASK
, PPCCOM
, {CR
, BDPA
}},
2538 {"bnsa", BBOCB(16,BOF
,CBSO
,1,0), BBOATCB_MASK
, COM
, {CR
, BDA
}},
2539 {"bnua-", BBOCB(16,BOF
,CBSO
,1,0), BBOATCB_MASK
, PPCCOM
, {CR
, BDMA
}},
2540 {"bnua+", BBOCB(16,BOF
,CBSO
,1,0), BBOATCB_MASK
, PPCCOM
, {CR
, BDPA
}},
2541 {"bnua", BBOCB(16,BOF
,CBSO
,1,0), BBOATCB_MASK
, PPCCOM
, {CR
, BDA
}},
2542 {"bnsla-", BBOCB(16,BOF
,CBSO
,1,1), BBOATCB_MASK
, PPCCOM
, {CR
, BDMA
}},
2543 {"bnsla+", BBOCB(16,BOF
,CBSO
,1,1), BBOATCB_MASK
, PPCCOM
, {CR
, BDPA
}},
2544 {"bnsla", BBOCB(16,BOF
,CBSO
,1,1), BBOATCB_MASK
, COM
, {CR
, BDA
}},
2545 {"bnula-", BBOCB(16,BOF
,CBSO
,1,1), BBOATCB_MASK
, PPCCOM
, {CR
, BDMA
}},
2546 {"bnula+", BBOCB(16,BOF
,CBSO
,1,1), BBOATCB_MASK
, PPCCOM
, {CR
, BDPA
}},
2547 {"bnula", BBOCB(16,BOF
,CBSO
,1,1), BBOATCB_MASK
, PPCCOM
, {CR
, BDA
}},
2549 {"blt-", BBOCB(16,BOT
,CBLT
,0,0), BBOATCB_MASK
, PPCCOM
, {CR
, BDM
}},
2550 {"blt+", BBOCB(16,BOT
,CBLT
,0,0), BBOATCB_MASK
, PPCCOM
, {CR
, BDP
}},
2551 {"blt", BBOCB(16,BOT
,CBLT
,0,0), BBOATCB_MASK
, COM
, {CR
, BD
}},
2552 {"bltl-", BBOCB(16,BOT
,CBLT
,0,1), BBOATCB_MASK
, PPCCOM
, {CR
, BDM
}},
2553 {"bltl+", BBOCB(16,BOT
,CBLT
,0,1), BBOATCB_MASK
, PPCCOM
, {CR
, BDP
}},
2554 {"bltl", BBOCB(16,BOT
,CBLT
,0,1), BBOATCB_MASK
, COM
, {CR
, BD
}},
2555 {"blta-", BBOCB(16,BOT
,CBLT
,1,0), BBOATCB_MASK
, PPCCOM
, {CR
, BDMA
}},
2556 {"blta+", BBOCB(16,BOT
,CBLT
,1,0), BBOATCB_MASK
, PPCCOM
, {CR
, BDPA
}},
2557 {"blta", BBOCB(16,BOT
,CBLT
,1,0), BBOATCB_MASK
, COM
, {CR
, BDA
}},
2558 {"bltla-", BBOCB(16,BOT
,CBLT
,1,1), BBOATCB_MASK
, PPCCOM
, {CR
, BDMA
}},
2559 {"bltla+", BBOCB(16,BOT
,CBLT
,1,1), BBOATCB_MASK
, PPCCOM
, {CR
, BDPA
}},
2560 {"bltla", BBOCB(16,BOT
,CBLT
,1,1), BBOATCB_MASK
, COM
, {CR
, BDA
}},
2561 {"bgt-", BBOCB(16,BOT
,CBGT
,0,0), BBOATCB_MASK
, PPCCOM
, {CR
, BDM
}},
2562 {"bgt+", BBOCB(16,BOT
,CBGT
,0,0), BBOATCB_MASK
, PPCCOM
, {CR
, BDP
}},
2563 {"bgt", BBOCB(16,BOT
,CBGT
,0,0), BBOATCB_MASK
, COM
, {CR
, BD
}},
2564 {"bgtl-", BBOCB(16,BOT
,CBGT
,0,1), BBOATCB_MASK
, PPCCOM
, {CR
, BDM
}},
2565 {"bgtl+", BBOCB(16,BOT
,CBGT
,0,1), BBOATCB_MASK
, PPCCOM
, {CR
, BDP
}},
2566 {"bgtl", BBOCB(16,BOT
,CBGT
,0,1), BBOATCB_MASK
, COM
, {CR
, BD
}},
2567 {"bgta-", BBOCB(16,BOT
,CBGT
,1,0), BBOATCB_MASK
, PPCCOM
, {CR
, BDMA
}},
2568 {"bgta+", BBOCB(16,BOT
,CBGT
,1,0), BBOATCB_MASK
, PPCCOM
, {CR
, BDPA
}},
2569 {"bgta", BBOCB(16,BOT
,CBGT
,1,0), BBOATCB_MASK
, COM
, {CR
, BDA
}},
2570 {"bgtla-", BBOCB(16,BOT
,CBGT
,1,1), BBOATCB_MASK
, PPCCOM
, {CR
, BDMA
}},
2571 {"bgtla+", BBOCB(16,BOT
,CBGT
,1,1), BBOATCB_MASK
, PPCCOM
, {CR
, BDPA
}},
2572 {"bgtla", BBOCB(16,BOT
,CBGT
,1,1), BBOATCB_MASK
, COM
, {CR
, BDA
}},
2573 {"beq-", BBOCB(16,BOT
,CBEQ
,0,0), BBOATCB_MASK
, PPCCOM
, {CR
, BDM
}},
2574 {"beq+", BBOCB(16,BOT
,CBEQ
,0,0), BBOATCB_MASK
, PPCCOM
, {CR
, BDP
}},
2575 {"beq", BBOCB(16,BOT
,CBEQ
,0,0), BBOATCB_MASK
, COM
, {CR
, BD
}},
2576 {"beql-", BBOCB(16,BOT
,CBEQ
,0,1), BBOATCB_MASK
, PPCCOM
, {CR
, BDM
}},
2577 {"beql+", BBOCB(16,BOT
,CBEQ
,0,1), BBOATCB_MASK
, PPCCOM
, {CR
, BDP
}},
2578 {"beql", BBOCB(16,BOT
,CBEQ
,0,1), BBOATCB_MASK
, COM
, {CR
, BD
}},
2579 {"beqa-", BBOCB(16,BOT
,CBEQ
,1,0), BBOATCB_MASK
, PPCCOM
, {CR
, BDMA
}},
2580 {"beqa+", BBOCB(16,BOT
,CBEQ
,1,0), BBOATCB_MASK
, PPCCOM
, {CR
, BDPA
}},
2581 {"beqa", BBOCB(16,BOT
,CBEQ
,1,0), BBOATCB_MASK
, COM
, {CR
, BDA
}},
2582 {"beqla-", BBOCB(16,BOT
,CBEQ
,1,1), BBOATCB_MASK
, PPCCOM
, {CR
, BDMA
}},
2583 {"beqla+", BBOCB(16,BOT
,CBEQ
,1,1), BBOATCB_MASK
, PPCCOM
, {CR
, BDPA
}},
2584 {"beqla", BBOCB(16,BOT
,CBEQ
,1,1), BBOATCB_MASK
, COM
, {CR
, BDA
}},
2585 {"bso-", BBOCB(16,BOT
,CBSO
,0,0), BBOATCB_MASK
, PPCCOM
, {CR
, BDM
}},
2586 {"bso+", BBOCB(16,BOT
,CBSO
,0,0), BBOATCB_MASK
, PPCCOM
, {CR
, BDP
}},
2587 {"bso", BBOCB(16,BOT
,CBSO
,0,0), BBOATCB_MASK
, COM
, {CR
, BD
}},
2588 {"bun-", BBOCB(16,BOT
,CBSO
,0,0), BBOATCB_MASK
, PPCCOM
, {CR
, BDM
}},
2589 {"bun+", BBOCB(16,BOT
,CBSO
,0,0), BBOATCB_MASK
, PPCCOM
, {CR
, BDP
}},
2590 {"bun", BBOCB(16,BOT
,CBSO
,0,0), BBOATCB_MASK
, PPCCOM
, {CR
, BD
}},
2591 {"bsol-", BBOCB(16,BOT
,CBSO
,0,1), BBOATCB_MASK
, PPCCOM
, {CR
, BDM
}},
2592 {"bsol+", BBOCB(16,BOT
,CBSO
,0,1), BBOATCB_MASK
, PPCCOM
, {CR
, BDP
}},
2593 {"bsol", BBOCB(16,BOT
,CBSO
,0,1), BBOATCB_MASK
, COM
, {CR
, BD
}},
2594 {"bunl-", BBOCB(16,BOT
,CBSO
,0,1), BBOATCB_MASK
, PPCCOM
, {CR
, BDM
}},
2595 {"bunl+", BBOCB(16,BOT
,CBSO
,0,1), BBOATCB_MASK
, PPCCOM
, {CR
, BDP
}},
2596 {"bunl", BBOCB(16,BOT
,CBSO
,0,1), BBOATCB_MASK
, PPCCOM
, {CR
, BD
}},
2597 {"bsoa-", BBOCB(16,BOT
,CBSO
,1,0), BBOATCB_MASK
, PPCCOM
, {CR
, BDMA
}},
2598 {"bsoa+", BBOCB(16,BOT
,CBSO
,1,0), BBOATCB_MASK
, PPCCOM
, {CR
, BDPA
}},
2599 {"bsoa", BBOCB(16,BOT
,CBSO
,1,0), BBOATCB_MASK
, COM
, {CR
, BDA
}},
2600 {"buna-", BBOCB(16,BOT
,CBSO
,1,0), BBOATCB_MASK
, PPCCOM
, {CR
, BDMA
}},
2601 {"buna+", BBOCB(16,BOT
,CBSO
,1,0), BBOATCB_MASK
, PPCCOM
, {CR
, BDPA
}},
2602 {"buna", BBOCB(16,BOT
,CBSO
,1,0), BBOATCB_MASK
, PPCCOM
, {CR
, BDA
}},
2603 {"bsola-", BBOCB(16,BOT
,CBSO
,1,1), BBOATCB_MASK
, PPCCOM
, {CR
, BDMA
}},
2604 {"bsola+", BBOCB(16,BOT
,CBSO
,1,1), BBOATCB_MASK
, PPCCOM
, {CR
, BDPA
}},
2605 {"bsola", BBOCB(16,BOT
,CBSO
,1,1), BBOATCB_MASK
, COM
, {CR
, BDA
}},
2606 {"bunla-", BBOCB(16,BOT
,CBSO
,1,1), BBOATCB_MASK
, PPCCOM
, {CR
, BDMA
}},
2607 {"bunla+", BBOCB(16,BOT
,CBSO
,1,1), BBOATCB_MASK
, PPCCOM
, {CR
, BDPA
}},
2608 {"bunla", BBOCB(16,BOT
,CBSO
,1,1), BBOATCB_MASK
, PPCCOM
, {CR
, BDA
}},
2610 {"bdnzf-", BBO(16,BODNZF
,0,0), BBOY_MASK
, NOPOWER4
, {BI
, BDM
}},
2611 {"bdnzf+", BBO(16,BODNZF
,0,0), BBOY_MASK
, NOPOWER4
, {BI
, BDP
}},
2612 {"bdnzf", BBO(16,BODNZF
,0,0), BBOY_MASK
, PPCCOM
, {BI
, BD
}},
2613 {"bdnzfl-", BBO(16,BODNZF
,0,1), BBOY_MASK
, NOPOWER4
, {BI
, BDM
}},
2614 {"bdnzfl+", BBO(16,BODNZF
,0,1), BBOY_MASK
, NOPOWER4
, {BI
, BDP
}},
2615 {"bdnzfl", BBO(16,BODNZF
,0,1), BBOY_MASK
, PPCCOM
, {BI
, BD
}},
2616 {"bdnzfa-", BBO(16,BODNZF
,1,0), BBOY_MASK
, NOPOWER4
, {BI
, BDMA
}},
2617 {"bdnzfa+", BBO(16,BODNZF
,1,0), BBOY_MASK
, NOPOWER4
, {BI
, BDPA
}},
2618 {"bdnzfa", BBO(16,BODNZF
,1,0), BBOY_MASK
, PPCCOM
, {BI
, BDA
}},
2619 {"bdnzfla-", BBO(16,BODNZF
,1,1), BBOY_MASK
, NOPOWER4
, {BI
, BDMA
}},
2620 {"bdnzfla+", BBO(16,BODNZF
,1,1), BBOY_MASK
, NOPOWER4
, {BI
, BDPA
}},
2621 {"bdnzfla", BBO(16,BODNZF
,1,1), BBOY_MASK
, PPCCOM
, {BI
, BDA
}},
2622 {"bdzf-", BBO(16,BODZF
,0,0), BBOY_MASK
, NOPOWER4
, {BI
, BDM
}},
2623 {"bdzf+", BBO(16,BODZF
,0,0), BBOY_MASK
, NOPOWER4
, {BI
, BDP
}},
2624 {"bdzf", BBO(16,BODZF
,0,0), BBOY_MASK
, PPCCOM
, {BI
, BD
}},
2625 {"bdzfl-", BBO(16,BODZF
,0,1), BBOY_MASK
, NOPOWER4
, {BI
, BDM
}},
2626 {"bdzfl+", BBO(16,BODZF
,0,1), BBOY_MASK
, NOPOWER4
, {BI
, BDP
}},
2627 {"bdzfl", BBO(16,BODZF
,0,1), BBOY_MASK
, PPCCOM
, {BI
, BD
}},
2628 {"bdzfa-", BBO(16,BODZF
,1,0), BBOY_MASK
, NOPOWER4
, {BI
, BDMA
}},
2629 {"bdzfa+", BBO(16,BODZF
,1,0), BBOY_MASK
, NOPOWER4
, {BI
, BDPA
}},
2630 {"bdzfa", BBO(16,BODZF
,1,0), BBOY_MASK
, PPCCOM
, {BI
, BDA
}},
2631 {"bdzfla-", BBO(16,BODZF
,1,1), BBOY_MASK
, NOPOWER4
, {BI
, BDMA
}},
2632 {"bdzfla+", BBO(16,BODZF
,1,1), BBOY_MASK
, NOPOWER4
, {BI
, BDPA
}},
2633 {"bdzfla", BBO(16,BODZF
,1,1), BBOY_MASK
, PPCCOM
, {BI
, BDA
}},
2635 {"bf-", BBO(16,BOF
,0,0), BBOAT_MASK
, PPCCOM
, {BI
, BDM
}},
2636 {"bf+", BBO(16,BOF
,0,0), BBOAT_MASK
, PPCCOM
, {BI
, BDP
}},
2637 {"bf", BBO(16,BOF
,0,0), BBOAT_MASK
, PPCCOM
, {BI
, BD
}},
2638 {"bbf", BBO(16,BOF
,0,0), BBOAT_MASK
, PWRCOM
, {BI
, BD
}},
2639 {"bfl-", BBO(16,BOF
,0,1), BBOAT_MASK
, PPCCOM
, {BI
, BDM
}},
2640 {"bfl+", BBO(16,BOF
,0,1), BBOAT_MASK
, PPCCOM
, {BI
, BDP
}},
2641 {"bfl", BBO(16,BOF
,0,1), BBOAT_MASK
, PPCCOM
, {BI
, BD
}},
2642 {"bbfl", BBO(16,BOF
,0,1), BBOAT_MASK
, PWRCOM
, {BI
, BD
}},
2643 {"bfa-", BBO(16,BOF
,1,0), BBOAT_MASK
, PPCCOM
, {BI
, BDMA
}},
2644 {"bfa+", BBO(16,BOF
,1,0), BBOAT_MASK
, PPCCOM
, {BI
, BDPA
}},
2645 {"bfa", BBO(16,BOF
,1,0), BBOAT_MASK
, PPCCOM
, {BI
, BDA
}},
2646 {"bbfa", BBO(16,BOF
,1,0), BBOAT_MASK
, PWRCOM
, {BI
, BDA
}},
2647 {"bfla-", BBO(16,BOF
,1,1), BBOAT_MASK
, PPCCOM
, {BI
, BDMA
}},
2648 {"bfla+", BBO(16,BOF
,1,1), BBOAT_MASK
, PPCCOM
, {BI
, BDPA
}},
2649 {"bfla", BBO(16,BOF
,1,1), BBOAT_MASK
, PPCCOM
, {BI
, BDA
}},
2650 {"bbfla", BBO(16,BOF
,1,1), BBOAT_MASK
, PWRCOM
, {BI
, BDA
}},
2652 {"bdnzt-", BBO(16,BODNZT
,0,0), BBOY_MASK
, NOPOWER4
, {BI
, BDM
}},
2653 {"bdnzt+", BBO(16,BODNZT
,0,0), BBOY_MASK
, NOPOWER4
, {BI
, BDP
}},
2654 {"bdnzt", BBO(16,BODNZT
,0,0), BBOY_MASK
, PPCCOM
, {BI
, BD
}},
2655 {"bdnztl-", BBO(16,BODNZT
,0,1), BBOY_MASK
, NOPOWER4
, {BI
, BDM
}},
2656 {"bdnztl+", BBO(16,BODNZT
,0,1), BBOY_MASK
, NOPOWER4
, {BI
, BDP
}},
2657 {"bdnztl", BBO(16,BODNZT
,0,1), BBOY_MASK
, PPCCOM
, {BI
, BD
}},
2658 {"bdnzta-", BBO(16,BODNZT
,1,0), BBOY_MASK
, NOPOWER4
, {BI
, BDMA
}},
2659 {"bdnzta+", BBO(16,BODNZT
,1,0), BBOY_MASK
, NOPOWER4
, {BI
, BDPA
}},
2660 {"bdnzta", BBO(16,BODNZT
,1,0), BBOY_MASK
, PPCCOM
, {BI
, BDA
}},
2661 {"bdnztla-", BBO(16,BODNZT
,1,1), BBOY_MASK
, NOPOWER4
, {BI
, BDMA
}},
2662 {"bdnztla+", BBO(16,BODNZT
,1,1), BBOY_MASK
, NOPOWER4
, {BI
, BDPA
}},
2663 {"bdnztla", BBO(16,BODNZT
,1,1), BBOY_MASK
, PPCCOM
, {BI
, BDA
}},
2664 {"bdzt-", BBO(16,BODZT
,0,0), BBOY_MASK
, NOPOWER4
, {BI
, BDM
}},
2665 {"bdzt+", BBO(16,BODZT
,0,0), BBOY_MASK
, NOPOWER4
, {BI
, BDP
}},
2666 {"bdzt", BBO(16,BODZT
,0,0), BBOY_MASK
, PPCCOM
, {BI
, BD
}},
2667 {"bdztl-", BBO(16,BODZT
,0,1), BBOY_MASK
, NOPOWER4
, {BI
, BDM
}},
2668 {"bdztl+", BBO(16,BODZT
,0,1), BBOY_MASK
, NOPOWER4
, {BI
, BDP
}},
2669 {"bdztl", BBO(16,BODZT
,0,1), BBOY_MASK
, PPCCOM
, {BI
, BD
}},
2670 {"bdzta-", BBO(16,BODZT
,1,0), BBOY_MASK
, NOPOWER4
, {BI
, BDMA
}},
2671 {"bdzta+", BBO(16,BODZT
,1,0), BBOY_MASK
, NOPOWER4
, {BI
, BDPA
}},
2672 {"bdzta", BBO(16,BODZT
,1,0), BBOY_MASK
, PPCCOM
, {BI
, BDA
}},
2673 {"bdztla-", BBO(16,BODZT
,1,1), BBOY_MASK
, NOPOWER4
, {BI
, BDMA
}},
2674 {"bdztla+", BBO(16,BODZT
,1,1), BBOY_MASK
, NOPOWER4
, {BI
, BDPA
}},
2675 {"bdztla", BBO(16,BODZT
,1,1), BBOY_MASK
, PPCCOM
, {BI
, BDA
}},
2677 {"bt-", BBO(16,BOT
,0,0), BBOAT_MASK
, PPCCOM
, {BI
, BDM
}},
2678 {"bt+", BBO(16,BOT
,0,0), BBOAT_MASK
, PPCCOM
, {BI
, BDP
}},
2679 {"bt", BBO(16,BOT
,0,0), BBOAT_MASK
, PPCCOM
, {BI
, BD
}},
2680 {"bbt", BBO(16,BOT
,0,0), BBOAT_MASK
, PWRCOM
, {BI
, BD
}},
2681 {"btl-", BBO(16,BOT
,0,1), BBOAT_MASK
, PPCCOM
, {BI
, BDM
}},
2682 {"btl+", BBO(16,BOT
,0,1), BBOAT_MASK
, PPCCOM
, {BI
, BDP
}},
2683 {"btl", BBO(16,BOT
,0,1), BBOAT_MASK
, PPCCOM
, {BI
, BD
}},
2684 {"bbtl", BBO(16,BOT
,0,1), BBOAT_MASK
, PWRCOM
, {BI
, BD
}},
2685 {"bta-", BBO(16,BOT
,1,0), BBOAT_MASK
, PPCCOM
, {BI
, BDMA
}},
2686 {"bta+", BBO(16,BOT
,1,0), BBOAT_MASK
, PPCCOM
, {BI
, BDPA
}},
2687 {"bta", BBO(16,BOT
,1,0), BBOAT_MASK
, PPCCOM
, {BI
, BDA
}},
2688 {"bbta", BBO(16,BOT
,1,0), BBOAT_MASK
, PWRCOM
, {BI
, BDA
}},
2689 {"btla-", BBO(16,BOT
,1,1), BBOAT_MASK
, PPCCOM
, {BI
, BDMA
}},
2690 {"btla+", BBO(16,BOT
,1,1), BBOAT_MASK
, PPCCOM
, {BI
, BDPA
}},
2691 {"btla", BBO(16,BOT
,1,1), BBOAT_MASK
, PPCCOM
, {BI
, BDA
}},
2692 {"bbtla", BBO(16,BOT
,1,1), BBOAT_MASK
, PWRCOM
, {BI
, BDA
}},
2694 {"bc-", B(16,0,0), B_MASK
, PPCCOM
, {BOE
, BI
, BDM
}},
2695 {"bc+", B(16,0,0), B_MASK
, PPCCOM
, {BOE
, BI
, BDP
}},
2696 {"bc", B(16,0,0), B_MASK
, COM
, {BO
, BI
, BD
}},
2697 {"bcl-", B(16,0,1), B_MASK
, PPCCOM
, {BOE
, BI
, BDM
}},
2698 {"bcl+", B(16,0,1), B_MASK
, PPCCOM
, {BOE
, BI
, BDP
}},
2699 {"bcl", B(16,0,1), B_MASK
, COM
, {BO
, BI
, BD
}},
2700 {"bca-", B(16,1,0), B_MASK
, PPCCOM
, {BOE
, BI
, BDMA
}},
2701 {"bca+", B(16,1,0), B_MASK
, PPCCOM
, {BOE
, BI
, BDPA
}},
2702 {"bca", B(16,1,0), B_MASK
, COM
, {BO
, BI
, BDA
}},
2703 {"bcla-", B(16,1,1), B_MASK
, PPCCOM
, {BOE
, BI
, BDMA
}},
2704 {"bcla+", B(16,1,1), B_MASK
, PPCCOM
, {BOE
, BI
, BDPA
}},
2705 {"bcla", B(16,1,1), B_MASK
, COM
, {BO
, BI
, BDA
}},
2707 {"svc", SC(17,0,0), SC_MASK
, POWER
, {SVC_LEV
, FL1
, FL2
}},
2708 {"svcl", SC(17,0,1), SC_MASK
, POWER
, {SVC_LEV
, FL1
, FL2
}},
2709 {"sc", SC(17,1,0), SC_MASK
, PPC
, {LEV
}},
2710 {"svca", SC(17,1,0), SC_MASK
, PWRCOM
, {SV
}},
2711 {"svcla", SC(17,1,1), SC_MASK
, POWER
, {SV
}},
2713 {"b", B(18,0,0), B_MASK
, COM
, {LI
}},
2714 {"bl", B(18,0,1), B_MASK
, COM
, {LI
}},
2715 {"ba", B(18,1,0), B_MASK
, COM
, {LIA
}},
2716 {"bla", B(18,1,1), B_MASK
, COM
, {LIA
}},
2718 {"mcrf", XL(19,0), XLBB_MASK
|(3<<21)|(3<<16), COM
, {BF
, BFA
}},
2720 {"bdnzlr", XLO(19,BODNZ
,16,0), XLBOBIBB_MASK
, PPCCOM
, {0}},
2721 {"bdnzlr-", XLO(19,BODNZ
,16,0), XLBOBIBB_MASK
, NOPOWER4
, {0}},
2722 {"bdnzlrl", XLO(19,BODNZ
,16,1), XLBOBIBB_MASK
, PPCCOM
, {0}},
2723 {"bdnzlrl-", XLO(19,BODNZ
,16,1), XLBOBIBB_MASK
, NOPOWER4
, {0}},
2724 {"bdnzlr+", XLO(19,BODNZP
,16,0), XLBOBIBB_MASK
, NOPOWER4
, {0}},
2725 {"bdnzlrl+", XLO(19,BODNZP
,16,1), XLBOBIBB_MASK
, NOPOWER4
, {0}},
2726 {"bdzlr", XLO(19,BODZ
,16,0), XLBOBIBB_MASK
, PPCCOM
, {0}},
2727 {"bdzlr-", XLO(19,BODZ
,16,0), XLBOBIBB_MASK
, NOPOWER4
, {0}},
2728 {"bdzlrl", XLO(19,BODZ
,16,1), XLBOBIBB_MASK
, PPCCOM
, {0}},
2729 {"bdzlrl-", XLO(19,BODZ
,16,1), XLBOBIBB_MASK
, NOPOWER4
, {0}},
2730 {"bdzlr+", XLO(19,BODZP
,16,0), XLBOBIBB_MASK
, NOPOWER4
, {0}},
2731 {"bdzlrl+", XLO(19,BODZP
,16,1), XLBOBIBB_MASK
, NOPOWER4
, {0}},
2732 {"blr", XLO(19,BOU
,16,0), XLBOBIBB_MASK
, PPCCOM
, {0}},
2733 {"br", XLO(19,BOU
,16,0), XLBOBIBB_MASK
, PWRCOM
, {0}},
2734 {"blrl", XLO(19,BOU
,16,1), XLBOBIBB_MASK
, PPCCOM
, {0}},
2735 {"brl", XLO(19,BOU
,16,1), XLBOBIBB_MASK
, PWRCOM
, {0}},
2736 {"bdnzlr-", XLO(19,BODNZM4
,16,0), XLBOBIBB_MASK
, POWER4
, {0}},
2737 {"bdnzlrl-", XLO(19,BODNZM4
,16,1), XLBOBIBB_MASK
, POWER4
, {0}},
2738 {"bdnzlr+", XLO(19,BODNZP4
,16,0), XLBOBIBB_MASK
, POWER4
, {0}},
2739 {"bdnzlrl+", XLO(19,BODNZP4
,16,1), XLBOBIBB_MASK
, POWER4
, {0}},
2740 {"bdzlr-", XLO(19,BODZM4
,16,0), XLBOBIBB_MASK
, POWER4
, {0}},
2741 {"bdzlrl-", XLO(19,BODZM4
,16,1), XLBOBIBB_MASK
, POWER4
, {0}},
2742 {"bdzlr+", XLO(19,BODZP4
,16,0), XLBOBIBB_MASK
, POWER4
, {0}},
2743 {"bdzlrl+", XLO(19,BODZP4
,16,1), XLBOBIBB_MASK
, POWER4
, {0}},
2745 {"bgelr", XLOCB(19,BOF
,CBLT
,16,0), XLBOCBBB_MASK
, PPCCOM
, {CR
}},
2746 {"bgelr-", XLOCB(19,BOF
,CBLT
,16,0), XLBOCBBB_MASK
, NOPOWER4
, {CR
}},
2747 {"bger", XLOCB(19,BOF
,CBLT
,16,0), XLBOCBBB_MASK
, PWRCOM
, {CR
}},
2748 {"bnllr", XLOCB(19,BOF
,CBLT
,16,0), XLBOCBBB_MASK
, PPCCOM
, {CR
}},
2749 {"bnllr-", XLOCB(19,BOF
,CBLT
,16,0), XLBOCBBB_MASK
, NOPOWER4
, {CR
}},
2750 {"bnlr", XLOCB(19,BOF
,CBLT
,16,0), XLBOCBBB_MASK
, PWRCOM
, {CR
}},
2751 {"bgelrl", XLOCB(19,BOF
,CBLT
,16,1), XLBOCBBB_MASK
, PPCCOM
, {CR
}},
2752 {"bgelrl-", XLOCB(19,BOF
,CBLT
,16,1), XLBOCBBB_MASK
, NOPOWER4
, {CR
}},
2753 {"bgerl", XLOCB(19,BOF
,CBLT
,16,1), XLBOCBBB_MASK
, PWRCOM
, {CR
}},
2754 {"bnllrl", XLOCB(19,BOF
,CBLT
,16,1), XLBOCBBB_MASK
, PPCCOM
, {CR
}},
2755 {"bnllrl-", XLOCB(19,BOF
,CBLT
,16,1), XLBOCBBB_MASK
, NOPOWER4
, {CR
}},
2756 {"bnlrl", XLOCB(19,BOF
,CBLT
,16,1), XLBOCBBB_MASK
, PWRCOM
, {CR
}},
2757 {"blelr", XLOCB(19,BOF
,CBGT
,16,0), XLBOCBBB_MASK
, PPCCOM
, {CR
}},
2758 {"blelr-", XLOCB(19,BOF
,CBGT
,16,0), XLBOCBBB_MASK
, NOPOWER4
, {CR
}},
2759 {"bler", XLOCB(19,BOF
,CBGT
,16,0), XLBOCBBB_MASK
, PWRCOM
, {CR
}},
2760 {"bnglr", XLOCB(19,BOF
,CBGT
,16,0), XLBOCBBB_MASK
, PPCCOM
, {CR
}},
2761 {"bnglr-", XLOCB(19,BOF
,CBGT
,16,0), XLBOCBBB_MASK
, NOPOWER4
, {CR
}},
2762 {"bngr", XLOCB(19,BOF
,CBGT
,16,0), XLBOCBBB_MASK
, PWRCOM
, {CR
}},
2763 {"blelrl", XLOCB(19,BOF
,CBGT
,16,1), XLBOCBBB_MASK
, PPCCOM
, {CR
}},
2764 {"blelrl-", XLOCB(19,BOF
,CBGT
,16,1), XLBOCBBB_MASK
, NOPOWER4
, {CR
}},
2765 {"blerl", XLOCB(19,BOF
,CBGT
,16,1), XLBOCBBB_MASK
, PWRCOM
, {CR
}},
2766 {"bnglrl", XLOCB(19,BOF
,CBGT
,16,1), XLBOCBBB_MASK
, PPCCOM
, {CR
}},
2767 {"bnglrl-", XLOCB(19,BOF
,CBGT
,16,1), XLBOCBBB_MASK
, NOPOWER4
, {CR
}},
2768 {"bngrl", XLOCB(19,BOF
,CBGT
,16,1), XLBOCBBB_MASK
, PWRCOM
, {CR
}},
2769 {"bnelr", XLOCB(19,BOF
,CBEQ
,16,0), XLBOCBBB_MASK
, PPCCOM
, {CR
}},
2770 {"bnelr-", XLOCB(19,BOF
,CBEQ
,16,0), XLBOCBBB_MASK
, NOPOWER4
, {CR
}},
2771 {"bner", XLOCB(19,BOF
,CBEQ
,16,0), XLBOCBBB_MASK
, PWRCOM
, {CR
}},
2772 {"bnelrl", XLOCB(19,BOF
,CBEQ
,16,1), XLBOCBBB_MASK
, PPCCOM
, {CR
}},
2773 {"bnelrl-", XLOCB(19,BOF
,CBEQ
,16,1), XLBOCBBB_MASK
, NOPOWER4
, {CR
}},
2774 {"bnerl", XLOCB(19,BOF
,CBEQ
,16,1), XLBOCBBB_MASK
, PWRCOM
, {CR
}},
2775 {"bnslr", XLOCB(19,BOF
,CBSO
,16,0), XLBOCBBB_MASK
, PPCCOM
, {CR
}},
2776 {"bnslr-", XLOCB(19,BOF
,CBSO
,16,0), XLBOCBBB_MASK
, NOPOWER4
, {CR
}},
2777 {"bnsr", XLOCB(19,BOF
,CBSO
,16,0), XLBOCBBB_MASK
, PWRCOM
, {CR
}},
2778 {"bnulr", XLOCB(19,BOF
,CBSO
,16,0), XLBOCBBB_MASK
, PPCCOM
, {CR
}},
2779 {"bnulr-", XLOCB(19,BOF
,CBSO
,16,0), XLBOCBBB_MASK
, NOPOWER4
, {CR
}},
2780 {"bnslrl", XLOCB(19,BOF
,CBSO
,16,1), XLBOCBBB_MASK
, PPCCOM
, {CR
}},
2781 {"bnslrl-", XLOCB(19,BOF
,CBSO
,16,1), XLBOCBBB_MASK
, NOPOWER4
, {CR
}},
2782 {"bnsrl", XLOCB(19,BOF
,CBSO
,16,1), XLBOCBBB_MASK
, PWRCOM
, {CR
}},
2783 {"bnulrl", XLOCB(19,BOF
,CBSO
,16,1), XLBOCBBB_MASK
, PPCCOM
, {CR
}},
2784 {"bnulrl-", XLOCB(19,BOF
,CBSO
,16,1), XLBOCBBB_MASK
, NOPOWER4
, {CR
}},
2785 {"bgelr+", XLOCB(19,BOFP
,CBLT
,16,0), XLBOCBBB_MASK
, NOPOWER4
, {CR
}},
2786 {"bnllr+", XLOCB(19,BOFP
,CBLT
,16,0), XLBOCBBB_MASK
, NOPOWER4
, {CR
}},
2787 {"bgelrl+", XLOCB(19,BOFP
,CBLT
,16,1), XLBOCBBB_MASK
, NOPOWER4
, {CR
}},
2788 {"bnllrl+", XLOCB(19,BOFP
,CBLT
,16,1), XLBOCBBB_MASK
, NOPOWER4
, {CR
}},
2789 {"blelr+", XLOCB(19,BOFP
,CBGT
,16,0), XLBOCBBB_MASK
, NOPOWER4
, {CR
}},
2790 {"bnglr+", XLOCB(19,BOFP
,CBGT
,16,0), XLBOCBBB_MASK
, NOPOWER4
, {CR
}},
2791 {"blelrl+", XLOCB(19,BOFP
,CBGT
,16,1), XLBOCBBB_MASK
, NOPOWER4
, {CR
}},
2792 {"bnglrl+", XLOCB(19,BOFP
,CBGT
,16,1), XLBOCBBB_MASK
, NOPOWER4
, {CR
}},
2793 {"bnelr+", XLOCB(19,BOFP
,CBEQ
,16,0), XLBOCBBB_MASK
, NOPOWER4
, {CR
}},
2794 {"bnelrl+", XLOCB(19,BOFP
,CBEQ
,16,1), XLBOCBBB_MASK
, NOPOWER4
, {CR
}},
2795 {"bnslr+", XLOCB(19,BOFP
,CBSO
,16,0), XLBOCBBB_MASK
, NOPOWER4
, {CR
}},
2796 {"bnulr+", XLOCB(19,BOFP
,CBSO
,16,0), XLBOCBBB_MASK
, NOPOWER4
, {CR
}},
2797 {"bnslrl+", XLOCB(19,BOFP
,CBSO
,16,1), XLBOCBBB_MASK
, NOPOWER4
, {CR
}},
2798 {"bnulrl+", XLOCB(19,BOFP
,CBSO
,16,1), XLBOCBBB_MASK
, NOPOWER4
, {CR
}},
2799 {"bgelr-", XLOCB(19,BOFM4
,CBLT
,16,0), XLBOCBBB_MASK
, POWER4
, {CR
}},
2800 {"bnllr-", XLOCB(19,BOFM4
,CBLT
,16,0), XLBOCBBB_MASK
, POWER4
, {CR
}},
2801 {"bgelrl-", XLOCB(19,BOFM4
,CBLT
,16,1), XLBOCBBB_MASK
, POWER4
, {CR
}},
2802 {"bnllrl-", XLOCB(19,BOFM4
,CBLT
,16,1), XLBOCBBB_MASK
, POWER4
, {CR
}},
2803 {"blelr-", XLOCB(19,BOFM4
,CBGT
,16,0), XLBOCBBB_MASK
, POWER4
, {CR
}},
2804 {"bnglr-", XLOCB(19,BOFM4
,CBGT
,16,0), XLBOCBBB_MASK
, POWER4
, {CR
}},
2805 {"blelrl-", XLOCB(19,BOFM4
,CBGT
,16,1), XLBOCBBB_MASK
, POWER4
, {CR
}},
2806 {"bnglrl-", XLOCB(19,BOFM4
,CBGT
,16,1), XLBOCBBB_MASK
, POWER4
, {CR
}},
2807 {"bnelr-", XLOCB(19,BOFM4
,CBEQ
,16,0), XLBOCBBB_MASK
, POWER4
, {CR
}},
2808 {"bnelrl-", XLOCB(19,BOFM4
,CBEQ
,16,1), XLBOCBBB_MASK
, POWER4
, {CR
}},
2809 {"bnslr-", XLOCB(19,BOFM4
,CBSO
,16,0), XLBOCBBB_MASK
, POWER4
, {CR
}},
2810 {"bnulr-", XLOCB(19,BOFM4
,CBSO
,16,0), XLBOCBBB_MASK
, POWER4
, {CR
}},
2811 {"bnslrl-", XLOCB(19,BOFM4
,CBSO
,16,1), XLBOCBBB_MASK
, POWER4
, {CR
}},
2812 {"bnulrl-", XLOCB(19,BOFM4
,CBSO
,16,1), XLBOCBBB_MASK
, POWER4
, {CR
}},
2813 {"bgelr+", XLOCB(19,BOFP4
,CBLT
,16,0), XLBOCBBB_MASK
, POWER4
, {CR
}},
2814 {"bnllr+", XLOCB(19,BOFP4
,CBLT
,16,0), XLBOCBBB_MASK
, POWER4
, {CR
}},
2815 {"bgelrl+", XLOCB(19,BOFP4
,CBLT
,16,1), XLBOCBBB_MASK
, POWER4
, {CR
}},
2816 {"bnllrl+", XLOCB(19,BOFP4
,CBLT
,16,1), XLBOCBBB_MASK
, POWER4
, {CR
}},
2817 {"blelr+", XLOCB(19,BOFP4
,CBGT
,16,0), XLBOCBBB_MASK
, POWER4
, {CR
}},
2818 {"bnglr+", XLOCB(19,BOFP4
,CBGT
,16,0), XLBOCBBB_MASK
, POWER4
, {CR
}},
2819 {"blelrl+", XLOCB(19,BOFP4
,CBGT
,16,1), XLBOCBBB_MASK
, POWER4
, {CR
}},
2820 {"bnglrl+", XLOCB(19,BOFP4
,CBGT
,16,1), XLBOCBBB_MASK
, POWER4
, {CR
}},
2821 {"bnelr+", XLOCB(19,BOFP4
,CBEQ
,16,0), XLBOCBBB_MASK
, POWER4
, {CR
}},
2822 {"bnelrl+", XLOCB(19,BOFP4
,CBEQ
,16,1), XLBOCBBB_MASK
, POWER4
, {CR
}},
2823 {"bnslr+", XLOCB(19,BOFP4
,CBSO
,16,0), XLBOCBBB_MASK
, POWER4
, {CR
}},
2824 {"bnulr+", XLOCB(19,BOFP4
,CBSO
,16,0), XLBOCBBB_MASK
, POWER4
, {CR
}},
2825 {"bnslrl+", XLOCB(19,BOFP4
,CBSO
,16,1), XLBOCBBB_MASK
, POWER4
, {CR
}},
2826 {"bnulrl+", XLOCB(19,BOFP4
,CBSO
,16,1), XLBOCBBB_MASK
, POWER4
, {CR
}},
2827 {"bltlr", XLOCB(19,BOT
,CBLT
,16,0), XLBOCBBB_MASK
, PPCCOM
, {CR
}},
2828 {"bltlr-", XLOCB(19,BOT
,CBLT
,16,0), XLBOCBBB_MASK
, NOPOWER4
, {CR
}},
2829 {"bltr", XLOCB(19,BOT
,CBLT
,16,0), XLBOCBBB_MASK
, PWRCOM
, {CR
}},
2830 {"bltlrl", XLOCB(19,BOT
,CBLT
,16,1), XLBOCBBB_MASK
, PPCCOM
, {CR
}},
2831 {"bltlrl-", XLOCB(19,BOT
,CBLT
,16,1), XLBOCBBB_MASK
, NOPOWER4
, {CR
}},
2832 {"bltrl", XLOCB(19,BOT
,CBLT
,16,1), XLBOCBBB_MASK
, PWRCOM
, {CR
}},
2833 {"bgtlr", XLOCB(19,BOT
,CBGT
,16,0), XLBOCBBB_MASK
, PPCCOM
, {CR
}},
2834 {"bgtlr-", XLOCB(19,BOT
,CBGT
,16,0), XLBOCBBB_MASK
, NOPOWER4
, {CR
}},
2835 {"bgtr", XLOCB(19,BOT
,CBGT
,16,0), XLBOCBBB_MASK
, PWRCOM
, {CR
}},
2836 {"bgtlrl", XLOCB(19,BOT
,CBGT
,16,1), XLBOCBBB_MASK
, PPCCOM
, {CR
}},
2837 {"bgtlrl-", XLOCB(19,BOT
,CBGT
,16,1), XLBOCBBB_MASK
, NOPOWER4
, {CR
}},
2838 {"bgtrl", XLOCB(19,BOT
,CBGT
,16,1), XLBOCBBB_MASK
, PWRCOM
, {CR
}},
2839 {"beqlr", XLOCB(19,BOT
,CBEQ
,16,0), XLBOCBBB_MASK
, PPCCOM
, {CR
}},
2840 {"beqlr-", XLOCB(19,BOT
,CBEQ
,16,0), XLBOCBBB_MASK
, NOPOWER4
, {CR
}},
2841 {"beqr", XLOCB(19,BOT
,CBEQ
,16,0), XLBOCBBB_MASK
, PWRCOM
, {CR
}},
2842 {"beqlrl", XLOCB(19,BOT
,CBEQ
,16,1), XLBOCBBB_MASK
, PPCCOM
, {CR
}},
2843 {"beqlrl-", XLOCB(19,BOT
,CBEQ
,16,1), XLBOCBBB_MASK
, NOPOWER4
, {CR
}},
2844 {"beqrl", XLOCB(19,BOT
,CBEQ
,16,1), XLBOCBBB_MASK
, PWRCOM
, {CR
}},
2845 {"bsolr", XLOCB(19,BOT
,CBSO
,16,0), XLBOCBBB_MASK
, PPCCOM
, {CR
}},
2846 {"bsolr-", XLOCB(19,BOT
,CBSO
,16,0), XLBOCBBB_MASK
, NOPOWER4
, {CR
}},
2847 {"bsor", XLOCB(19,BOT
,CBSO
,16,0), XLBOCBBB_MASK
, PWRCOM
, {CR
}},
2848 {"bunlr", XLOCB(19,BOT
,CBSO
,16,0), XLBOCBBB_MASK
, PPCCOM
, {CR
}},
2849 {"bunlr-", XLOCB(19,BOT
,CBSO
,16,0), XLBOCBBB_MASK
, NOPOWER4
, {CR
}},
2850 {"bsolrl", XLOCB(19,BOT
,CBSO
,16,1), XLBOCBBB_MASK
, PPCCOM
, {CR
}},
2851 {"bsolrl-", XLOCB(19,BOT
,CBSO
,16,1), XLBOCBBB_MASK
, NOPOWER4
, {CR
}},
2852 {"bsorl", XLOCB(19,BOT
,CBSO
,16,1), XLBOCBBB_MASK
, PWRCOM
, {CR
}},
2853 {"bunlrl", XLOCB(19,BOT
,CBSO
,16,1), XLBOCBBB_MASK
, PPCCOM
, {CR
}},
2854 {"bunlrl-", XLOCB(19,BOT
,CBSO
,16,1), XLBOCBBB_MASK
, NOPOWER4
, {CR
}},
2855 {"bltlr+", XLOCB(19,BOTP
,CBLT
,16,0), XLBOCBBB_MASK
, NOPOWER4
, {CR
}},
2856 {"bltlrl+", XLOCB(19,BOTP
,CBLT
,16,1), XLBOCBBB_MASK
, NOPOWER4
, {CR
}},
2857 {"bgtlr+", XLOCB(19,BOTP
,CBGT
,16,0), XLBOCBBB_MASK
, NOPOWER4
, {CR
}},
2858 {"bgtlrl+", XLOCB(19,BOTP
,CBGT
,16,1), XLBOCBBB_MASK
, NOPOWER4
, {CR
}},
2859 {"beqlr+", XLOCB(19,BOTP
,CBEQ
,16,0), XLBOCBBB_MASK
, NOPOWER4
, {CR
}},
2860 {"beqlrl+", XLOCB(19,BOTP
,CBEQ
,16,1), XLBOCBBB_MASK
, NOPOWER4
, {CR
}},
2861 {"bsolr+", XLOCB(19,BOTP
,CBSO
,16,0), XLBOCBBB_MASK
, NOPOWER4
, {CR
}},
2862 {"bunlr+", XLOCB(19,BOTP
,CBSO
,16,0), XLBOCBBB_MASK
, NOPOWER4
, {CR
}},
2863 {"bsolrl+", XLOCB(19,BOTP
,CBSO
,16,1), XLBOCBBB_MASK
, NOPOWER4
, {CR
}},
2864 {"bunlrl+", XLOCB(19,BOTP
,CBSO
,16,1), XLBOCBBB_MASK
, NOPOWER4
, {CR
}},
2865 {"bltlr-", XLOCB(19,BOTM4
,CBLT
,16,0), XLBOCBBB_MASK
, POWER4
, {CR
}},
2866 {"bltlrl-", XLOCB(19,BOTM4
,CBLT
,16,1), XLBOCBBB_MASK
, POWER4
, {CR
}},
2867 {"bgtlr-", XLOCB(19,BOTM4
,CBGT
,16,0), XLBOCBBB_MASK
, POWER4
, {CR
}},
2868 {"bgtlrl-", XLOCB(19,BOTM4
,CBGT
,16,1), XLBOCBBB_MASK
, POWER4
, {CR
}},
2869 {"beqlr-", XLOCB(19,BOTM4
,CBEQ
,16,0), XLBOCBBB_MASK
, POWER4
, {CR
}},
2870 {"beqlrl-", XLOCB(19,BOTM4
,CBEQ
,16,1), XLBOCBBB_MASK
, POWER4
, {CR
}},
2871 {"bsolr-", XLOCB(19,BOTM4
,CBSO
,16,0), XLBOCBBB_MASK
, POWER4
, {CR
}},
2872 {"bunlr-", XLOCB(19,BOTM4
,CBSO
,16,0), XLBOCBBB_MASK
, POWER4
, {CR
}},
2873 {"bsolrl-", XLOCB(19,BOTM4
,CBSO
,16,1), XLBOCBBB_MASK
, POWER4
, {CR
}},
2874 {"bunlrl-", XLOCB(19,BOTM4
,CBSO
,16,1), XLBOCBBB_MASK
, POWER4
, {CR
}},
2875 {"bltlr+", XLOCB(19,BOTP4
,CBLT
,16,0), XLBOCBBB_MASK
, POWER4
, {CR
}},
2876 {"bltlrl+", XLOCB(19,BOTP4
,CBLT
,16,1), XLBOCBBB_MASK
, POWER4
, {CR
}},
2877 {"bgtlr+", XLOCB(19,BOTP4
,CBGT
,16,0), XLBOCBBB_MASK
, POWER4
, {CR
}},
2878 {"bgtlrl+", XLOCB(19,BOTP4
,CBGT
,16,1), XLBOCBBB_MASK
, POWER4
, {CR
}},
2879 {"beqlr+", XLOCB(19,BOTP4
,CBEQ
,16,0), XLBOCBBB_MASK
, POWER4
, {CR
}},
2880 {"beqlrl+", XLOCB(19,BOTP4
,CBEQ
,16,1), XLBOCBBB_MASK
, POWER4
, {CR
}},
2881 {"bsolr+", XLOCB(19,BOTP4
,CBSO
,16,0), XLBOCBBB_MASK
, POWER4
, {CR
}},
2882 {"bunlr+", XLOCB(19,BOTP4
,CBSO
,16,0), XLBOCBBB_MASK
, POWER4
, {CR
}},
2883 {"bsolrl+", XLOCB(19,BOTP4
,CBSO
,16,1), XLBOCBBB_MASK
, POWER4
, {CR
}},
2884 {"bunlrl+", XLOCB(19,BOTP4
,CBSO
,16,1), XLBOCBBB_MASK
, POWER4
, {CR
}},
2886 {"bdnzflr", XLO(19,BODNZF
,16,0), XLBOBB_MASK
, PPCCOM
, {BI
}},
2887 {"bdnzflr-", XLO(19,BODNZF
,16,0), XLBOBB_MASK
, NOPOWER4
, {BI
}},
2888 {"bdnzflrl", XLO(19,BODNZF
,16,1), XLBOBB_MASK
, PPCCOM
, {BI
}},
2889 {"bdnzflrl-",XLO(19,BODNZF
,16,1), XLBOBB_MASK
, NOPOWER4
, {BI
}},
2890 {"bdnzflr+", XLO(19,BODNZFP
,16,0), XLBOBB_MASK
, NOPOWER4
, {BI
}},
2891 {"bdnzflrl+",XLO(19,BODNZFP
,16,1), XLBOBB_MASK
, NOPOWER4
, {BI
}},
2892 {"bdzflr", XLO(19,BODZF
,16,0), XLBOBB_MASK
, PPCCOM
, {BI
}},
2893 {"bdzflr-", XLO(19,BODZF
,16,0), XLBOBB_MASK
, NOPOWER4
, {BI
}},
2894 {"bdzflrl", XLO(19,BODZF
,16,1), XLBOBB_MASK
, PPCCOM
, {BI
}},
2895 {"bdzflrl-", XLO(19,BODZF
,16,1), XLBOBB_MASK
, NOPOWER4
, {BI
}},
2896 {"bdzflr+", XLO(19,BODZFP
,16,0), XLBOBB_MASK
, NOPOWER4
, {BI
}},
2897 {"bdzflrl+", XLO(19,BODZFP
,16,1), XLBOBB_MASK
, NOPOWER4
, {BI
}},
2898 {"bflr", XLO(19,BOF
,16,0), XLBOBB_MASK
, PPCCOM
, {BI
}},
2899 {"bflr-", XLO(19,BOF
,16,0), XLBOBB_MASK
, NOPOWER4
, {BI
}},
2900 {"bbfr", XLO(19,BOF
,16,0), XLBOBB_MASK
, PWRCOM
, {BI
}},
2901 {"bflrl", XLO(19,BOF
,16,1), XLBOBB_MASK
, PPCCOM
, {BI
}},
2902 {"bflrl-", XLO(19,BOF
,16,1), XLBOBB_MASK
, NOPOWER4
, {BI
}},
2903 {"bbfrl", XLO(19,BOF
,16,1), XLBOBB_MASK
, PWRCOM
, {BI
}},
2904 {"bflr+", XLO(19,BOFP
,16,0), XLBOBB_MASK
, NOPOWER4
, {BI
}},
2905 {"bflrl+", XLO(19,BOFP
,16,1), XLBOBB_MASK
, NOPOWER4
, {BI
}},
2906 {"bflr-", XLO(19,BOFM4
,16,0), XLBOBB_MASK
, POWER4
, {BI
}},
2907 {"bflrl-", XLO(19,BOFM4
,16,1), XLBOBB_MASK
, POWER4
, {BI
}},
2908 {"bflr+", XLO(19,BOFP4
,16,0), XLBOBB_MASK
, POWER4
, {BI
}},
2909 {"bflrl+", XLO(19,BOFP4
,16,1), XLBOBB_MASK
, POWER4
, {BI
}},
2910 {"bdnztlr", XLO(19,BODNZT
,16,0), XLBOBB_MASK
, PPCCOM
, {BI
}},
2911 {"bdnztlr-", XLO(19,BODNZT
,16,0), XLBOBB_MASK
, NOPOWER4
, {BI
}},
2912 {"bdnztlrl", XLO(19,BODNZT
,16,1), XLBOBB_MASK
, PPCCOM
, {BI
}},
2913 {"bdnztlrl-",XLO(19,BODNZT
,16,1), XLBOBB_MASK
, NOPOWER4
, {BI
}},
2914 {"bdnztlr+", XLO(19,BODNZTP
,16,0), XLBOBB_MASK
, NOPOWER4
, {BI
}},
2915 {"bdnztlrl+",XLO(19,BODNZTP
,16,1), XLBOBB_MASK
, NOPOWER4
, {BI
}},
2916 {"bdztlr", XLO(19,BODZT
,16,0), XLBOBB_MASK
, PPCCOM
, {BI
}},
2917 {"bdztlr-", XLO(19,BODZT
,16,0), XLBOBB_MASK
, NOPOWER4
, {BI
}},
2918 {"bdztlrl", XLO(19,BODZT
,16,1), XLBOBB_MASK
, PPCCOM
, {BI
}},
2919 {"bdztlrl-", XLO(19,BODZT
,16,1), XLBOBB_MASK
, NOPOWER4
, {BI
}},
2920 {"bdztlr+", XLO(19,BODZTP
,16,0), XLBOBB_MASK
, NOPOWER4
, {BI
}},
2921 {"bdztlrl+", XLO(19,BODZTP
,16,1), XLBOBB_MASK
, NOPOWER4
, {BI
}},
2922 {"btlr", XLO(19,BOT
,16,0), XLBOBB_MASK
, PPCCOM
, {BI
}},
2923 {"btlr-", XLO(19,BOT
,16,0), XLBOBB_MASK
, NOPOWER4
, {BI
}},
2924 {"bbtr", XLO(19,BOT
,16,0), XLBOBB_MASK
, PWRCOM
, {BI
}},
2925 {"btlrl", XLO(19,BOT
,16,1), XLBOBB_MASK
, PPCCOM
, {BI
}},
2926 {"btlrl-", XLO(19,BOT
,16,1), XLBOBB_MASK
, NOPOWER4
, {BI
}},
2927 {"bbtrl", XLO(19,BOT
,16,1), XLBOBB_MASK
, PWRCOM
, {BI
}},
2928 {"btlr+", XLO(19,BOTP
,16,0), XLBOBB_MASK
, NOPOWER4
, {BI
}},
2929 {"btlrl+", XLO(19,BOTP
,16,1), XLBOBB_MASK
, NOPOWER4
, {BI
}},
2930 {"btlr-", XLO(19,BOTM4
,16,0), XLBOBB_MASK
, POWER4
, {BI
}},
2931 {"btlrl-", XLO(19,BOTM4
,16,1), XLBOBB_MASK
, POWER4
, {BI
}},
2932 {"btlr+", XLO(19,BOTP4
,16,0), XLBOBB_MASK
, POWER4
, {BI
}},
2933 {"btlrl+", XLO(19,BOTP4
,16,1), XLBOBB_MASK
, POWER4
, {BI
}},
2935 {"bclr-", XLYLK(19,16,0,0), XLYBB_MASK
, PPCCOM
, {BOE
, BI
}},
2936 {"bclrl-", XLYLK(19,16,0,1), XLYBB_MASK
, PPCCOM
, {BOE
, BI
}},
2937 {"bclr+", XLYLK(19,16,1,0), XLYBB_MASK
, PPCCOM
, {BOE
, BI
}},
2938 {"bclrl+", XLYLK(19,16,1,1), XLYBB_MASK
, PPCCOM
, {BOE
, BI
}},
2939 {"bclr", XLLK(19,16,0), XLBH_MASK
, PPCCOM
, {BO
, BI
, BH
}},
2940 {"bcr", XLLK(19,16,0), XLBB_MASK
, PWRCOM
, {BO
, BI
}},
2941 {"bclrl", XLLK(19,16,1), XLBH_MASK
, PPCCOM
, {BO
, BI
, BH
}},
2942 {"bcrl", XLLK(19,16,1), XLBB_MASK
, PWRCOM
, {BO
, BI
}},
2944 {"bclre", XLLK(19,17,0), XLBB_MASK
, BOOKE64
, {BO
, BI
}},
2945 {"bclrel", XLLK(19,17,1), XLBB_MASK
, BOOKE64
, {BO
, BI
}},
2947 {"rfid", XL(19,18), 0xffffffff, PPC64
, {0}},
2949 {"crnot", XL(19,33), XL_MASK
, PPCCOM
, {BT
, BA
, BBA
}},
2950 {"crnor", XL(19,33), XL_MASK
, COM
, {BT
, BA
, BB
}},
2951 {"rfmci", X(19,38), 0xffffffff, PPCRFMCI
, {0}},
2953 {"rfdi", XL(19,39), 0xffffffff, E500MC
, {0}},
2954 {"rfi", XL(19,50), 0xffffffff, COM
, {0}},
2955 {"rfci", XL(19,51), 0xffffffff, PPC403
|BOOKE
, {0}},
2957 {"rfsvc", XL(19,82), 0xffffffff, POWER
, {0}},
2959 {"rfgi", XL(19,102), 0xffffffff, E500MC
, {0}},
2961 {"crandc", XL(19,129), XL_MASK
, COM
, {BT
, BA
, BB
}},
2963 {"isync", XL(19,150), 0xffffffff, PPCCOM
, {0}},
2964 {"ics", XL(19,150), 0xffffffff, PWRCOM
, {0}},
2966 {"crclr", XL(19,193), XL_MASK
, PPCCOM
, {BT
, BAT
, BBA
}},
2967 {"crxor", XL(19,193), XL_MASK
, COM
, {BT
, BA
, BB
}},
2969 {"dnh", X(19,198), X_MASK
, E500MC
, {DUI
, DUIS
}},
2971 {"crnand", XL(19,225), XL_MASK
, COM
, {BT
, BA
, BB
}},
2973 {"crand", XL(19,257), XL_MASK
, COM
, {BT
, BA
, BB
}},
2975 {"hrfid", XL(19,274), 0xffffffff, POWER5
|CELL
, {0}},
2977 {"crset", XL(19,289), XL_MASK
, PPCCOM
, {BT
, BAT
, BBA
}},
2978 {"creqv", XL(19,289), XL_MASK
, COM
, {BT
, BA
, BB
}},
2980 {"doze", XL(19,402), 0xffffffff, POWER6
, {0}},
2982 {"crorc", XL(19,417), XL_MASK
, COM
, {BT
, BA
, BB
}},
2984 {"nap", XL(19,434), 0xffffffff, POWER6
, {0}},
2986 {"crmove", XL(19,449), XL_MASK
, PPCCOM
, {BT
, BA
, BBA
}},
2987 {"cror", XL(19,449), XL_MASK
, COM
, {BT
, BA
, BB
}},
2989 {"sleep", XL(19,466), 0xffffffff, POWER6
, {0}},
2990 {"rvwinkle", XL(19,498), 0xffffffff, POWER6
, {0}},
2992 {"bctr", XLO(19,BOU
,528,0), XLBOBIBB_MASK
, COM
, {0}},
2993 {"bctrl", XLO(19,BOU
,528,1), XLBOBIBB_MASK
, COM
, {0}},
2995 {"bgectr", XLOCB(19,BOF
,CBLT
,528,0), XLBOCBBB_MASK
, PPCCOM
, {CR
}},
2996 {"bgectr-", XLOCB(19,BOF
,CBLT
,528,0), XLBOCBBB_MASK
, NOPOWER4
, {CR
}},
2997 {"bnlctr", XLOCB(19,BOF
,CBLT
,528,0), XLBOCBBB_MASK
, PPCCOM
, {CR
}},
2998 {"bnlctr-", XLOCB(19,BOF
,CBLT
,528,0), XLBOCBBB_MASK
, NOPOWER4
, {CR
}},
2999 {"bgectrl", XLOCB(19,BOF
,CBLT
,528,1), XLBOCBBB_MASK
, PPCCOM
, {CR
}},
3000 {"bgectrl-",XLOCB(19,BOF
,CBLT
,528,1), XLBOCBBB_MASK
, NOPOWER4
, {CR
}},
3001 {"bnlctrl", XLOCB(19,BOF
,CBLT
,528,1), XLBOCBBB_MASK
, PPCCOM
, {CR
}},
3002 {"bnlctrl-",XLOCB(19,BOF
,CBLT
,528,1), XLBOCBBB_MASK
, NOPOWER4
, {CR
}},
3003 {"blectr", XLOCB(19,BOF
,CBGT
,528,0), XLBOCBBB_MASK
, PPCCOM
, {CR
}},
3004 {"blectr-", XLOCB(19,BOF
,CBGT
,528,0), XLBOCBBB_MASK
, NOPOWER4
, {CR
}},
3005 {"bngctr", XLOCB(19,BOF
,CBGT
,528,0), XLBOCBBB_MASK
, PPCCOM
, {CR
}},
3006 {"bngctr-", XLOCB(19,BOF
,CBGT
,528,0), XLBOCBBB_MASK
, NOPOWER4
, {CR
}},
3007 {"blectrl", XLOCB(19,BOF
,CBGT
,528,1), XLBOCBBB_MASK
, PPCCOM
, {CR
}},
3008 {"blectrl-",XLOCB(19,BOF
,CBGT
,528,1), XLBOCBBB_MASK
, NOPOWER4
, {CR
}},
3009 {"bngctrl", XLOCB(19,BOF
,CBGT
,528,1), XLBOCBBB_MASK
, PPCCOM
, {CR
}},
3010 {"bngctrl-",XLOCB(19,BOF
,CBGT
,528,1), XLBOCBBB_MASK
, NOPOWER4
, {CR
}},
3011 {"bnectr", XLOCB(19,BOF
,CBEQ
,528,0), XLBOCBBB_MASK
, PPCCOM
, {CR
}},
3012 {"bnectr-", XLOCB(19,BOF
,CBEQ
,528,0), XLBOCBBB_MASK
, NOPOWER4
, {CR
}},
3013 {"bnectrl", XLOCB(19,BOF
,CBEQ
,528,1), XLBOCBBB_MASK
, PPCCOM
, {CR
}},
3014 {"bnectrl-",XLOCB(19,BOF
,CBEQ
,528,1), XLBOCBBB_MASK
, NOPOWER4
, {CR
}},
3015 {"bnsctr", XLOCB(19,BOF
,CBSO
,528,0), XLBOCBBB_MASK
, PPCCOM
, {CR
}},
3016 {"bnsctr-", XLOCB(19,BOF
,CBSO
,528,0), XLBOCBBB_MASK
, NOPOWER4
, {CR
}},
3017 {"bnuctr", XLOCB(19,BOF
,CBSO
,528,0), XLBOCBBB_MASK
, PPCCOM
, {CR
}},
3018 {"bnuctr-", XLOCB(19,BOF
,CBSO
,528,0), XLBOCBBB_MASK
, NOPOWER4
, {CR
}},
3019 {"bnsctrl", XLOCB(19,BOF
,CBSO
,528,1), XLBOCBBB_MASK
, PPCCOM
, {CR
}},
3020 {"bnsctrl-",XLOCB(19,BOF
,CBSO
,528,1), XLBOCBBB_MASK
, NOPOWER4
, {CR
}},
3021 {"bnuctrl", XLOCB(19,BOF
,CBSO
,528,1), XLBOCBBB_MASK
, PPCCOM
, {CR
}},
3022 {"bnuctrl-",XLOCB(19,BOF
,CBSO
,528,1), XLBOCBBB_MASK
, NOPOWER4
, {CR
}},
3023 {"bgectr+", XLOCB(19,BOFP
,CBLT
,528,0), XLBOCBBB_MASK
, NOPOWER4
, {CR
}},
3024 {"bnlctr+", XLOCB(19,BOFP
,CBLT
,528,0), XLBOCBBB_MASK
, NOPOWER4
, {CR
}},
3025 {"bgectrl+",XLOCB(19,BOFP
,CBLT
,528,1), XLBOCBBB_MASK
, NOPOWER4
, {CR
}},
3026 {"bnlctrl+",XLOCB(19,BOFP
,CBLT
,528,1), XLBOCBBB_MASK
, NOPOWER4
, {CR
}},
3027 {"blectr+", XLOCB(19,BOFP
,CBGT
,528,0), XLBOCBBB_MASK
, NOPOWER4
, {CR
}},
3028 {"bngctr+", XLOCB(19,BOFP
,CBGT
,528,0), XLBOCBBB_MASK
, NOPOWER4
, {CR
}},
3029 {"blectrl+",XLOCB(19,BOFP
,CBGT
,528,1), XLBOCBBB_MASK
, NOPOWER4
, {CR
}},
3030 {"bngctrl+",XLOCB(19,BOFP
,CBGT
,528,1), XLBOCBBB_MASK
, NOPOWER4
, {CR
}},
3031 {"bnectr+", XLOCB(19,BOFP
,CBEQ
,528,0), XLBOCBBB_MASK
, NOPOWER4
, {CR
}},
3032 {"bnectrl+",XLOCB(19,BOFP
,CBEQ
,528,1), XLBOCBBB_MASK
, NOPOWER4
, {CR
}},
3033 {"bnsctr+", XLOCB(19,BOFP
,CBSO
,528,0), XLBOCBBB_MASK
, NOPOWER4
, {CR
}},
3034 {"bnuctr+", XLOCB(19,BOFP
,CBSO
,528,0), XLBOCBBB_MASK
, NOPOWER4
, {CR
}},
3035 {"bnsctrl+",XLOCB(19,BOFP
,CBSO
,528,1), XLBOCBBB_MASK
, NOPOWER4
, {CR
}},
3036 {"bnuctrl+",XLOCB(19,BOFP
,CBSO
,528,1), XLBOCBBB_MASK
, NOPOWER4
, {CR
}},
3037 {"bgectr-", XLOCB(19,BOFM4
,CBLT
,528,0), XLBOCBBB_MASK
, POWER4
, {CR
}},
3038 {"bnlctr-", XLOCB(19,BOFM4
,CBLT
,528,0), XLBOCBBB_MASK
, POWER4
, {CR
}},
3039 {"bgectrl-",XLOCB(19,BOFM4
,CBLT
,528,1), XLBOCBBB_MASK
, POWER4
, {CR
}},
3040 {"bnlctrl-",XLOCB(19,BOFM4
,CBLT
,528,1), XLBOCBBB_MASK
, POWER4
, {CR
}},
3041 {"blectr-", XLOCB(19,BOFM4
,CBGT
,528,0), XLBOCBBB_MASK
, POWER4
, {CR
}},
3042 {"bngctr-", XLOCB(19,BOFM4
,CBGT
,528,0), XLBOCBBB_MASK
, POWER4
, {CR
}},
3043 {"blectrl-",XLOCB(19,BOFM4
,CBGT
,528,1), XLBOCBBB_MASK
, POWER4
, {CR
}},
3044 {"bngctrl-",XLOCB(19,BOFM4
,CBGT
,528,1), XLBOCBBB_MASK
, POWER4
, {CR
}},
3045 {"bnectr-", XLOCB(19,BOFM4
,CBEQ
,528,0), XLBOCBBB_MASK
, POWER4
, {CR
}},
3046 {"bnectrl-",XLOCB(19,BOFM4
,CBEQ
,528,1), XLBOCBBB_MASK
, POWER4
, {CR
}},
3047 {"bnsctr-", XLOCB(19,BOFM4
,CBSO
,528,0), XLBOCBBB_MASK
, POWER4
, {CR
}},
3048 {"bnuctr-", XLOCB(19,BOFM4
,CBSO
,528,0), XLBOCBBB_MASK
, POWER4
, {CR
}},
3049 {"bnsctrl-",XLOCB(19,BOFM4
,CBSO
,528,1), XLBOCBBB_MASK
, POWER4
, {CR
}},
3050 {"bnuctrl-",XLOCB(19,BOFM4
,CBSO
,528,1), XLBOCBBB_MASK
, POWER4
, {CR
}},
3051 {"bgectr+", XLOCB(19,BOFP4
,CBLT
,528,0), XLBOCBBB_MASK
, POWER4
, {CR
}},
3052 {"bnlctr+", XLOCB(19,BOFP4
,CBLT
,528,0), XLBOCBBB_MASK
, POWER4
, {CR
}},
3053 {"bgectrl+",XLOCB(19,BOFP4
,CBLT
,528,1), XLBOCBBB_MASK
, POWER4
, {CR
}},
3054 {"bnlctrl+",XLOCB(19,BOFP4
,CBLT
,528,1), XLBOCBBB_MASK
, POWER4
, {CR
}},
3055 {"blectr+", XLOCB(19,BOFP4
,CBGT
,528,0), XLBOCBBB_MASK
, POWER4
, {CR
}},
3056 {"bngctr+", XLOCB(19,BOFP4
,CBGT
,528,0), XLBOCBBB_MASK
, POWER4
, {CR
}},
3057 {"blectrl+",XLOCB(19,BOFP4
,CBGT
,528,1), XLBOCBBB_MASK
, POWER4
, {CR
}},
3058 {"bngctrl+",XLOCB(19,BOFP4
,CBGT
,528,1), XLBOCBBB_MASK
, POWER4
, {CR
}},
3059 {"bnectr+", XLOCB(19,BOFP4
,CBEQ
,528,0), XLBOCBBB_MASK
, POWER4
, {CR
}},
3060 {"bnectrl+",XLOCB(19,BOFP4
,CBEQ
,528,1), XLBOCBBB_MASK
, POWER4
, {CR
}},
3061 {"bnsctr+", XLOCB(19,BOFP4
,CBSO
,528,0), XLBOCBBB_MASK
, POWER4
, {CR
}},
3062 {"bnuctr+", XLOCB(19,BOFP4
,CBSO
,528,0), XLBOCBBB_MASK
, POWER4
, {CR
}},
3063 {"bnsctrl+",XLOCB(19,BOFP4
,CBSO
,528,1), XLBOCBBB_MASK
, POWER4
, {CR
}},
3064 {"bnuctrl+",XLOCB(19,BOFP4
,CBSO
,528,1), XLBOCBBB_MASK
, POWER4
, {CR
}},
3065 {"bltctr", XLOCB(19,BOT
,CBLT
,528,0), XLBOCBBB_MASK
, PPCCOM
, {CR
}},
3066 {"bltctr-", XLOCB(19,BOT
,CBLT
,528,0), XLBOCBBB_MASK
, NOPOWER4
, {CR
}},
3067 {"bltctrl", XLOCB(19,BOT
,CBLT
,528,1), XLBOCBBB_MASK
, PPCCOM
, {CR
}},
3068 {"bltctrl-",XLOCB(19,BOT
,CBLT
,528,1), XLBOCBBB_MASK
, NOPOWER4
, {CR
}},
3069 {"bgtctr", XLOCB(19,BOT
,CBGT
,528,0), XLBOCBBB_MASK
, PPCCOM
, {CR
}},
3070 {"bgtctr-", XLOCB(19,BOT
,CBGT
,528,0), XLBOCBBB_MASK
, NOPOWER4
, {CR
}},
3071 {"bgtctrl", XLOCB(19,BOT
,CBGT
,528,1), XLBOCBBB_MASK
, PPCCOM
, {CR
}},
3072 {"bgtctrl-",XLOCB(19,BOT
,CBGT
,528,1), XLBOCBBB_MASK
, NOPOWER4
, {CR
}},
3073 {"beqctr", XLOCB(19,BOT
,CBEQ
,528,0), XLBOCBBB_MASK
, PPCCOM
, {CR
}},
3074 {"beqctr-", XLOCB(19,BOT
,CBEQ
,528,0), XLBOCBBB_MASK
, NOPOWER4
, {CR
}},
3075 {"beqctrl", XLOCB(19,BOT
,CBEQ
,528,1), XLBOCBBB_MASK
, PPCCOM
, {CR
}},
3076 {"beqctrl-",XLOCB(19,BOT
,CBEQ
,528,1), XLBOCBBB_MASK
, NOPOWER4
, {CR
}},
3077 {"bsoctr", XLOCB(19,BOT
,CBSO
,528,0), XLBOCBBB_MASK
, PPCCOM
, {CR
}},
3078 {"bsoctr-", XLOCB(19,BOT
,CBSO
,528,0), XLBOCBBB_MASK
, NOPOWER4
, {CR
}},
3079 {"bunctr", XLOCB(19,BOT
,CBSO
,528,0), XLBOCBBB_MASK
, PPCCOM
, {CR
}},
3080 {"bunctr-", XLOCB(19,BOT
,CBSO
,528,0), XLBOCBBB_MASK
, NOPOWER4
, {CR
}},
3081 {"bsoctrl", XLOCB(19,BOT
,CBSO
,528,1), XLBOCBBB_MASK
, PPCCOM
, {CR
}},
3082 {"bsoctrl-",XLOCB(19,BOT
,CBSO
,528,1), XLBOCBBB_MASK
, NOPOWER4
, {CR
}},
3083 {"bunctrl", XLOCB(19,BOT
,CBSO
,528,1), XLBOCBBB_MASK
, PPCCOM
, {CR
}},
3084 {"bunctrl-",XLOCB(19,BOT
,CBSO
,528,1), XLBOCBBB_MASK
, NOPOWER4
, {CR
}},
3085 {"bltctr+", XLOCB(19,BOTP
,CBLT
,528,0), XLBOCBBB_MASK
, NOPOWER4
, {CR
}},
3086 {"bltctrl+",XLOCB(19,BOTP
,CBLT
,528,1), XLBOCBBB_MASK
, NOPOWER4
, {CR
}},
3087 {"bgtctr+", XLOCB(19,BOTP
,CBGT
,528,0), XLBOCBBB_MASK
, NOPOWER4
, {CR
}},
3088 {"bgtctrl+",XLOCB(19,BOTP
,CBGT
,528,1), XLBOCBBB_MASK
, NOPOWER4
, {CR
}},
3089 {"beqctr+", XLOCB(19,BOTP
,CBEQ
,528,0), XLBOCBBB_MASK
, NOPOWER4
, {CR
}},
3090 {"beqctrl+",XLOCB(19,BOTP
,CBEQ
,528,1), XLBOCBBB_MASK
, NOPOWER4
, {CR
}},
3091 {"bsoctr+", XLOCB(19,BOTP
,CBSO
,528,0), XLBOCBBB_MASK
, NOPOWER4
, {CR
}},
3092 {"bunctr+", XLOCB(19,BOTP
,CBSO
,528,0), XLBOCBBB_MASK
, NOPOWER4
, {CR
}},
3093 {"bsoctrl+",XLOCB(19,BOTP
,CBSO
,528,1), XLBOCBBB_MASK
, NOPOWER4
, {CR
}},
3094 {"bunctrl+",XLOCB(19,BOTP
,CBSO
,528,1), XLBOCBBB_MASK
, NOPOWER4
, {CR
}},
3095 {"bltctr-", XLOCB(19,BOTM4
,CBLT
,528,0), XLBOCBBB_MASK
, POWER4
, {CR
}},
3096 {"bltctrl-",XLOCB(19,BOTM4
,CBLT
,528,1), XLBOCBBB_MASK
, POWER4
, {CR
}},
3097 {"bgtctr-", XLOCB(19,BOTM4
,CBGT
,528,0), XLBOCBBB_MASK
, POWER4
, {CR
}},
3098 {"bgtctrl-",XLOCB(19,BOTM4
,CBGT
,528,1), XLBOCBBB_MASK
, POWER4
, {CR
}},
3099 {"beqctr-", XLOCB(19,BOTM4
,CBEQ
,528,0), XLBOCBBB_MASK
, POWER4
, {CR
}},
3100 {"beqctrl-",XLOCB(19,BOTM4
,CBEQ
,528,1), XLBOCBBB_MASK
, POWER4
, {CR
}},
3101 {"bsoctr-", XLOCB(19,BOTM4
,CBSO
,528,0), XLBOCBBB_MASK
, POWER4
, {CR
}},
3102 {"bunctr-", XLOCB(19,BOTM4
,CBSO
,528,0), XLBOCBBB_MASK
, POWER4
, {CR
}},
3103 {"bsoctrl-",XLOCB(19,BOTM4
,CBSO
,528,1), XLBOCBBB_MASK
, POWER4
, {CR
}},
3104 {"bunctrl-",XLOCB(19,BOTM4
,CBSO
,528,1), XLBOCBBB_MASK
, POWER4
, {CR
}},
3105 {"bltctr+", XLOCB(19,BOTP4
,CBLT
,528,0), XLBOCBBB_MASK
, POWER4
, {CR
}},
3106 {"bltctrl+",XLOCB(19,BOTP4
,CBLT
,528,1), XLBOCBBB_MASK
, POWER4
, {CR
}},
3107 {"bgtctr+", XLOCB(19,BOTP4
,CBGT
,528,0), XLBOCBBB_MASK
, POWER4
, {CR
}},
3108 {"bgtctrl+",XLOCB(19,BOTP4
,CBGT
,528,1), XLBOCBBB_MASK
, POWER4
, {CR
}},
3109 {"beqctr+", XLOCB(19,BOTP4
,CBEQ
,528,0), XLBOCBBB_MASK
, POWER4
, {CR
}},
3110 {"beqctrl+",XLOCB(19,BOTP4
,CBEQ
,528,1), XLBOCBBB_MASK
, POWER4
, {CR
}},
3111 {"bsoctr+", XLOCB(19,BOTP4
,CBSO
,528,0), XLBOCBBB_MASK
, POWER4
, {CR
}},
3112 {"bunctr+", XLOCB(19,BOTP4
,CBSO
,528,0), XLBOCBBB_MASK
, POWER4
, {CR
}},
3113 {"bsoctrl+",XLOCB(19,BOTP4
,CBSO
,528,1), XLBOCBBB_MASK
, POWER4
, {CR
}},
3114 {"bunctrl+",XLOCB(19,BOTP4
,CBSO
,528,1), XLBOCBBB_MASK
, POWER4
, {CR
}},
3116 {"bfctr", XLO(19,BOF
,528,0), XLBOBB_MASK
, PPCCOM
, {BI
}},
3117 {"bfctr-", XLO(19,BOF
,528,0), XLBOBB_MASK
, NOPOWER4
, {BI
}},
3118 {"bfctrl", XLO(19,BOF
,528,1), XLBOBB_MASK
, PPCCOM
, {BI
}},
3119 {"bfctrl-", XLO(19,BOF
,528,1), XLBOBB_MASK
, NOPOWER4
, {BI
}},
3120 {"bfctr+", XLO(19,BOFP
,528,0), XLBOBB_MASK
, NOPOWER4
, {BI
}},
3121 {"bfctrl+", XLO(19,BOFP
,528,1), XLBOBB_MASK
, NOPOWER4
, {BI
}},
3122 {"bfctr-", XLO(19,BOFM4
,528,0), XLBOBB_MASK
, POWER4
, {BI
}},
3123 {"bfctrl-", XLO(19,BOFM4
,528,1), XLBOBB_MASK
, POWER4
, {BI
}},
3124 {"bfctr+", XLO(19,BOFP4
,528,0), XLBOBB_MASK
, POWER4
, {BI
}},
3125 {"bfctrl+", XLO(19,BOFP4
,528,1), XLBOBB_MASK
, POWER4
, {BI
}},
3126 {"btctr", XLO(19,BOT
,528,0), XLBOBB_MASK
, PPCCOM
, {BI
}},
3127 {"btctr-", XLO(19,BOT
,528,0), XLBOBB_MASK
, NOPOWER4
, {BI
}},
3128 {"btctrl", XLO(19,BOT
,528,1), XLBOBB_MASK
, PPCCOM
, {BI
}},
3129 {"btctrl-", XLO(19,BOT
,528,1), XLBOBB_MASK
, NOPOWER4
, {BI
}},
3130 {"btctr+", XLO(19,BOTP
,528,0), XLBOBB_MASK
, NOPOWER4
, {BI
}},
3131 {"btctrl+", XLO(19,BOTP
,528,1), XLBOBB_MASK
, NOPOWER4
, {BI
}},
3132 {"btctr-", XLO(19,BOTM4
,528,0), XLBOBB_MASK
, POWER4
, {BI
}},
3133 {"btctrl-", XLO(19,BOTM4
,528,1), XLBOBB_MASK
, POWER4
, {BI
}},
3134 {"btctr+", XLO(19,BOTP4
,528,0), XLBOBB_MASK
, POWER4
, {BI
}},
3135 {"btctrl+", XLO(19,BOTP4
,528,1), XLBOBB_MASK
, POWER4
, {BI
}},
3137 {"bcctr-", XLYLK(19,528,0,0), XLYBB_MASK
, PPCCOM
, {BOE
, BI
}},
3138 {"bcctrl-", XLYLK(19,528,0,1), XLYBB_MASK
, PPCCOM
, {BOE
, BI
}},
3139 {"bcctr+", XLYLK(19,528,1,0), XLYBB_MASK
, PPCCOM
, {BOE
, BI
}},
3140 {"bcctrl+", XLYLK(19,528,1,1), XLYBB_MASK
, PPCCOM
, {BOE
, BI
}},
3141 {"bcctr", XLLK(19,528,0), XLBH_MASK
, PPCCOM
, {BO
, BI
, BH
}},
3142 {"bcc", XLLK(19,528,0), XLBB_MASK
, PWRCOM
, {BO
, BI
}},
3143 {"bcctrl", XLLK(19,528,1), XLBH_MASK
, PPCCOM
, {BO
, BI
, BH
}},
3144 {"bccl", XLLK(19,528,1), XLBB_MASK
, PWRCOM
, {BO
, BI
}},
3146 {"bcctre", XLLK(19,529,0), XLBB_MASK
, BOOKE64
, {BO
, BI
}},
3147 {"bcctrel", XLLK(19,529,1), XLBB_MASK
, BOOKE64
, {BO
, BI
}},
3149 {"rlwimi", M(20,0), M_MASK
, PPCCOM
, {RA
, RS
, SH
, MBE
, ME
}},
3150 {"rlimi", M(20,0), M_MASK
, PWRCOM
, {RA
, RS
, SH
, MBE
, ME
}},
3152 {"rlwimi.", M(20,1), M_MASK
, PPCCOM
, {RA
, RS
, SH
, MBE
, ME
}},
3153 {"rlimi.", M(20,1), M_MASK
, PWRCOM
, {RA
, RS
, SH
, MBE
, ME
}},
3155 {"rotlwi", MME(21,31,0), MMBME_MASK
, PPCCOM
, {RA
, RS
, SH
}},
3156 {"clrlwi", MME(21,31,0), MSHME_MASK
, PPCCOM
, {RA
, RS
, MB
}},
3157 {"rlwinm", M(21,0), M_MASK
, PPCCOM
, {RA
, RS
, SH
, MBE
, ME
}},
3158 {"rlinm", M(21,0), M_MASK
, PWRCOM
, {RA
, RS
, SH
, MBE
, ME
}},
3159 {"rotlwi.", MME(21,31,1), MMBME_MASK
, PPCCOM
, {RA
, RS
, SH
}},
3160 {"clrlwi.", MME(21,31,1), MSHME_MASK
, PPCCOM
, {RA
, RS
, MB
}},
3161 {"rlwinm.", M(21,1), M_MASK
, PPCCOM
, {RA
, RS
, SH
, MBE
, ME
}},
3162 {"rlinm.", M(21,1), M_MASK
, PWRCOM
, {RA
, RS
, SH
, MBE
, ME
}},
3164 {"rlmi", M(22,0), M_MASK
, M601
, {RA
, RS
, RB
, MBE
, ME
}},
3165 {"be", B(22,0,0), B_MASK
, BOOKE64
, {LI
}},
3166 {"bel", B(22,0,1), B_MASK
, BOOKE64
, {LI
}},
3167 {"rlmi.", M(22,1), M_MASK
, M601
, {RA
, RS
, RB
, MBE
, ME
}},
3168 {"bea", B(22,1,0), B_MASK
, BOOKE64
, {LIA
}},
3169 {"bela", B(22,1,1), B_MASK
, BOOKE64
, {LIA
}},
3171 {"rotlw", MME(23,31,0), MMBME_MASK
, PPCCOM
, {RA
, RS
, RB
}},
3172 {"rlwnm", M(23,0), M_MASK
, PPCCOM
, {RA
, RS
, RB
, MBE
, ME
}},
3173 {"rlnm", M(23,0), M_MASK
, PWRCOM
, {RA
, RS
, RB
, MBE
, ME
}},
3174 {"rotlw.", MME(23,31,1), MMBME_MASK
, PPCCOM
, {RA
, RS
, RB
}},
3175 {"rlwnm.", M(23,1), M_MASK
, PPCCOM
, {RA
, RS
, RB
, MBE
, ME
}},
3176 {"rlnm.", M(23,1), M_MASK
, PWRCOM
, {RA
, RS
, RB
, MBE
, ME
}},
3178 {"nop", OP(24), 0xffffffff, PPCCOM
, {0}},
3179 {"ori", OP(24), OP_MASK
, PPCCOM
, {RA
, RS
, UI
}},
3180 {"oril", OP(24), OP_MASK
, PWRCOM
, {RA
, RS
, UI
}},
3182 {"oris", OP(25), OP_MASK
, PPCCOM
, {RA
, RS
, UI
}},
3183 {"oriu", OP(25), OP_MASK
, PWRCOM
, {RA
, RS
, UI
}},
3185 {"xori", OP(26), OP_MASK
, PPCCOM
, {RA
, RS
, UI
}},
3186 {"xoril", OP(26), OP_MASK
, PWRCOM
, {RA
, RS
, UI
}},
3188 {"xoris", OP(27), OP_MASK
, PPCCOM
, {RA
, RS
, UI
}},
3189 {"xoriu", OP(27), OP_MASK
, PWRCOM
, {RA
, RS
, UI
}},
3191 {"andi.", OP(28), OP_MASK
, PPCCOM
, {RA
, RS
, UI
}},
3192 {"andil.", OP(28), OP_MASK
, PWRCOM
, {RA
, RS
, UI
}},
3194 {"andis.", OP(29), OP_MASK
, PPCCOM
, {RA
, RS
, UI
}},
3195 {"andiu.", OP(29), OP_MASK
, PWRCOM
, {RA
, RS
, UI
}},
3197 {"rotldi", MD(30,0,0), MDMB_MASK
, PPC64
, {RA
, RS
, SH6
}},
3198 {"clrldi", MD(30,0,0), MDSH_MASK
, PPC64
, {RA
, RS
, MB6
}},
3199 {"rldicl", MD(30,0,0), MD_MASK
, PPC64
, {RA
, RS
, SH6
, MB6
}},
3200 {"rotldi.", MD(30,0,1), MDMB_MASK
, PPC64
, {RA
, RS
, SH6
}},
3201 {"clrldi.", MD(30,0,1), MDSH_MASK
, PPC64
, {RA
, RS
, MB6
}},
3202 {"rldicl.", MD(30,0,1), MD_MASK
, PPC64
, {RA
, RS
, SH6
, MB6
}},
3204 {"rldicr", MD(30,1,0), MD_MASK
, PPC64
, {RA
, RS
, SH6
, ME6
}},
3205 {"rldicr.", MD(30,1,1), MD_MASK
, PPC64
, {RA
, RS
, SH6
, ME6
}},
3207 {"rldic", MD(30,2,0), MD_MASK
, PPC64
, {RA
, RS
, SH6
, MB6
}},
3208 {"rldic.", MD(30,2,1), MD_MASK
, PPC64
, {RA
, RS
, SH6
, MB6
}},
3210 {"rldimi", MD(30,3,0), MD_MASK
, PPC64
, {RA
, RS
, SH6
, MB6
}},
3211 {"rldimi.", MD(30,3,1), MD_MASK
, PPC64
, {RA
, RS
, SH6
, MB6
}},
3213 {"rotld", MDS(30,8,0), MDSMB_MASK
, PPC64
, {RA
, RS
, RB
}},
3214 {"rldcl", MDS(30,8,0), MDS_MASK
, PPC64
, {RA
, RS
, RB
, MB6
}},
3215 {"rotld.", MDS(30,8,1), MDSMB_MASK
, PPC64
, {RA
, RS
, RB
}},
3216 {"rldcl.", MDS(30,8,1), MDS_MASK
, PPC64
, {RA
, RS
, RB
, MB6
}},
3218 {"rldcr", MDS(30,9,0), MDS_MASK
, PPC64
, {RA
, RS
, RB
, ME6
}},
3219 {"rldcr.", MDS(30,9,1), MDS_MASK
, PPC64
, {RA
, RS
, RB
, ME6
}},
3221 {"cmpw", XOPL(31,0,0), XCMPL_MASK
, PPCCOM
, {OBF
, RA
, RB
}},
3222 {"cmpd", XOPL(31,0,1), XCMPL_MASK
, PPC64
, {OBF
, RA
, RB
}},
3223 {"cmp", X(31,0), XCMP_MASK
, PPC
, {BF
, L
, RA
, RB
}},
3224 {"cmp", X(31,0), XCMPL_MASK
, PWRCOM
, {BF
, RA
, RB
}},
3226 {"twlgt", XTO(31,4,TOLGT
), XTO_MASK
, PPCCOM
, {RA
, RB
}},
3227 {"tlgt", XTO(31,4,TOLGT
), XTO_MASK
, PWRCOM
, {RA
, RB
}},
3228 {"twllt", XTO(31,4,TOLLT
), XTO_MASK
, PPCCOM
, {RA
, RB
}},
3229 {"tllt", XTO(31,4,TOLLT
), XTO_MASK
, PWRCOM
, {RA
, RB
}},
3230 {"tweq", XTO(31,4,TOEQ
), XTO_MASK
, PPCCOM
, {RA
, RB
}},
3231 {"teq", XTO(31,4,TOEQ
), XTO_MASK
, PWRCOM
, {RA
, RB
}},
3232 {"twlge", XTO(31,4,TOLGE
), XTO_MASK
, PPCCOM
, {RA
, RB
}},
3233 {"tlge", XTO(31,4,TOLGE
), XTO_MASK
, PWRCOM
, {RA
, RB
}},
3234 {"twlnl", XTO(31,4,TOLNL
), XTO_MASK
, PPCCOM
, {RA
, RB
}},
3235 {"tlnl", XTO(31,4,TOLNL
), XTO_MASK
, PWRCOM
, {RA
, RB
}},
3236 {"twlle", XTO(31,4,TOLLE
), XTO_MASK
, PPCCOM
, {RA
, RB
}},
3237 {"tlle", XTO(31,4,TOLLE
), XTO_MASK
, PWRCOM
, {RA
, RB
}},
3238 {"twlng", XTO(31,4,TOLNG
), XTO_MASK
, PPCCOM
, {RA
, RB
}},
3239 {"tlng", XTO(31,4,TOLNG
), XTO_MASK
, PWRCOM
, {RA
, RB
}},
3240 {"twgt", XTO(31,4,TOGT
), XTO_MASK
, PPCCOM
, {RA
, RB
}},
3241 {"tgt", XTO(31,4,TOGT
), XTO_MASK
, PWRCOM
, {RA
, RB
}},
3242 {"twge", XTO(31,4,TOGE
), XTO_MASK
, PPCCOM
, {RA
, RB
}},
3243 {"tge", XTO(31,4,TOGE
), XTO_MASK
, PWRCOM
, {RA
, RB
}},
3244 {"twnl", XTO(31,4,TONL
), XTO_MASK
, PPCCOM
, {RA
, RB
}},
3245 {"tnl", XTO(31,4,TONL
), XTO_MASK
, PWRCOM
, {RA
, RB
}},
3246 {"twlt", XTO(31,4,TOLT
), XTO_MASK
, PPCCOM
, {RA
, RB
}},
3247 {"tlt", XTO(31,4,TOLT
), XTO_MASK
, PWRCOM
, {RA
, RB
}},
3248 {"twle", XTO(31,4,TOLE
), XTO_MASK
, PPCCOM
, {RA
, RB
}},
3249 {"tle", XTO(31,4,TOLE
), XTO_MASK
, PWRCOM
, {RA
, RB
}},
3250 {"twng", XTO(31,4,TONG
), XTO_MASK
, PPCCOM
, {RA
, RB
}},
3251 {"tng", XTO(31,4,TONG
), XTO_MASK
, PWRCOM
, {RA
, RB
}},
3252 {"twne", XTO(31,4,TONE
), XTO_MASK
, PPCCOM
, {RA
, RB
}},
3253 {"tne", XTO(31,4,TONE
), XTO_MASK
, PWRCOM
, {RA
, RB
}},
3254 {"trap", XTO(31,4,TOU
), 0xffffffff, PPCCOM
, {0}},
3255 {"tw", X(31,4), X_MASK
, PPCCOM
, {TO
, RA
, RB
}},
3256 {"t", X(31,4), X_MASK
, PWRCOM
, {TO
, RA
, RB
}},
3258 {"lvsl", X(31,6), X_MASK
, PPCVEC
, {VD
, RA
, RB
}},
3259 {"lvebx", X(31,7), X_MASK
, PPCVEC
, {VD
, RA
, RB
}},
3260 {"lbfcmx", APU(31,7,0), APU_MASK
, PPC405
, {FCRT
, RA
, RB
}},
3262 {"subfc", XO(31,8,0,0), XO_MASK
, PPCCOM
, {RT
, RA
, RB
}},
3263 {"sf", XO(31,8,0,0), XO_MASK
, PWRCOM
, {RT
, RA
, RB
}},
3264 {"subc", XO(31,8,0,0), XO_MASK
, PPC
, {RT
, RB
, RA
}},
3265 {"subfc.", XO(31,8,0,1), XO_MASK
, PPCCOM
, {RT
, RA
, RB
}},
3266 {"sf.", XO(31,8,0,1), XO_MASK
, PWRCOM
, {RT
, RA
, RB
}},
3267 {"subc.", XO(31,8,0,1), XO_MASK
, PPCCOM
, {RT
, RB
, RA
}},
3269 {"mulhdu", XO(31,9,0,0), XO_MASK
, PPC64
, {RT
, RA
, RB
}},
3270 {"mulhdu.", XO(31,9,0,1), XO_MASK
, PPC64
, {RT
, RA
, RB
}},
3272 {"addc", XO(31,10,0,0), XO_MASK
, PPCCOM
, {RT
, RA
, RB
}},
3273 {"a", XO(31,10,0,0), XO_MASK
, PWRCOM
, {RT
, RA
, RB
}},
3274 {"addc.", XO(31,10,0,1), XO_MASK
, PPCCOM
, {RT
, RA
, RB
}},
3275 {"a.", XO(31,10,0,1), XO_MASK
, PWRCOM
, {RT
, RA
, RB
}},
3277 {"mulhwu", XO(31,11,0,0), XO_MASK
, PPC
, {RT
, RA
, RB
}},
3278 {"mulhwu.", XO(31,11,0,1), XO_MASK
, PPC
, {RT
, RA
, RB
}},
3280 {"isellt", X(31,15), X_MASK
, PPCISEL
, {RT
, RA
, RB
}},
3282 {"mfcr", XFXM(31,19,0,0), XRARB_MASK
, NOPOWER4
|COM
, {RT
}},
3283 {"mfcr", XFXM(31,19,0,0), XFXFXM_MASK
, POWER4
, {RT
, FXM4
}},
3284 {"mfocrf", XFXM(31,19,0,1), XFXFXM_MASK
, COM
, {RT
, FXM
}},
3286 {"lwarx", X(31,20), XEH_MASK
, PPC
, {RT
, RA0
, RB
, EH
}},
3288 {"ldx", X(31,21), X_MASK
, PPC64
, {RT
, RA0
, RB
}},
3290 {"icbt", X(31,22), X_MASK
, BOOKE
|PPCE300
, {CT
, RA
, RB
}},
3292 {"lwzx", X(31,23), X_MASK
, PPCCOM
, {RT
, RA0
, RB
}},
3293 {"lx", X(31,23), X_MASK
, PWRCOM
, {RT
, RA
, RB
}},
3295 {"slw", XRC(31,24,0), X_MASK
, PPCCOM
, {RA
, RS
, RB
}},
3296 {"sl", XRC(31,24,0), X_MASK
, PWRCOM
, {RA
, RS
, RB
}},
3297 {"slw.", XRC(31,24,1), X_MASK
, PPCCOM
, {RA
, RS
, RB
}},
3298 {"sl.", XRC(31,24,1), X_MASK
, PWRCOM
, {RA
, RS
, RB
}},
3300 {"cntlzw", XRC(31,26,0), XRB_MASK
, PPCCOM
, {RA
, RS
}},
3301 {"cntlz", XRC(31,26,0), XRB_MASK
, PWRCOM
, {RA
, RS
}},
3302 {"cntlzw.", XRC(31,26,1), XRB_MASK
, PPCCOM
, {RA
, RS
}},
3303 {"cntlz.", XRC(31,26,1), XRB_MASK
, PWRCOM
, {RA
, RS
}},
3305 {"sld", XRC(31,27,0), X_MASK
, PPC64
, {RA
, RS
, RB
}},
3306 {"sld.", XRC(31,27,1), X_MASK
, PPC64
, {RA
, RS
, RB
}},
3308 {"and", XRC(31,28,0), X_MASK
, COM
, {RA
, RS
, RB
}},
3309 {"and.", XRC(31,28,1), X_MASK
, COM
, {RA
, RS
, RB
}},
3311 {"maskg", XRC(31,29,0), X_MASK
, M601
, {RA
, RS
, RB
}},
3312 {"maskg.", XRC(31,29,1), X_MASK
, M601
, {RA
, RS
, RB
}},
3314 {"ldepx", X(31,29), X_MASK
, E500MC
, {RT
, RA
, RB
}},
3316 {"icbte", X(31,30), X_MASK
, BOOKE64
, {CT
, RA
, RB
}},
3318 {"lwzxe", X(31,31), X_MASK
, BOOKE64
, {RT
, RA0
, RB
}},
3319 {"lwepx", X(31,31), X_MASK
, E500MC
, {RT
, RA
, RB
}},
3321 {"cmplw", XOPL(31,32,0), XCMPL_MASK
, PPCCOM
, {OBF
, RA
, RB
}},
3322 {"cmpld", XOPL(31,32,1), XCMPL_MASK
, PPC64
, {OBF
, RA
, RB
}},
3323 {"cmpl", X(31,32), XCMP_MASK
, PPC
, {BF
, L
, RA
, RB
}},
3324 {"cmpl", X(31,32), XCMPL_MASK
, PWRCOM
, {BF
, RA
, RB
}},
3326 {"lvsr", X(31,38), X_MASK
, PPCVEC
, {VD
, RA
, RB
}},
3327 {"lvehx", X(31,39), X_MASK
, PPCVEC
, {VD
, RA
, RB
}},
3328 {"lhfcmx", APU(31,39,0), APU_MASK
, PPC405
, {FCRT
, RA
, RB
}},
3330 {"iselgt", X(31,47), X_MASK
, PPCISEL
, {RT
, RA
, RB
}},
3332 {"lvewx", X(31,71), X_MASK
, PPCVEC
, {VD
, RA
, RB
}},
3334 {"iseleq", X(31,79), X_MASK
, PPCISEL
, {RT
, RA
, RB
}},
3336 {"isel", XISEL(31,15), XISEL_MASK
, PPCISEL
, {RT
, RA
, RB
, CRB
}},
3338 {"subf", XO(31,40,0,0), XO_MASK
, PPC
, {RT
, RA
, RB
}},
3339 {"sub", XO(31,40,0,0), XO_MASK
, PPC
, {RT
, RB
, RA
}},
3340 {"subf.", XO(31,40,0,1), XO_MASK
, PPC
, {RT
, RA
, RB
}},
3341 {"sub.", XO(31,40,0,1), XO_MASK
, PPC
, {RT
, RB
, RA
}},
3343 {"ldux", X(31,53), X_MASK
, PPC64
, {RT
, RAL
, RB
}},
3345 {"dcbst", X(31,54), XRT_MASK
, PPC
, {RA
, RB
}},
3347 {"lwzux", X(31,55), X_MASK
, PPCCOM
, {RT
, RAL
, RB
}},
3348 {"lux", X(31,55), X_MASK
, PWRCOM
, {RT
, RA
, RB
}},
3350 {"cntlzd", XRC(31,58,0), XRB_MASK
, PPC64
, {RA
, RS
}},
3351 {"cntlzd.", XRC(31,58,1), XRB_MASK
, PPC64
, {RA
, RS
}},
3353 {"andc", XRC(31,60,0), X_MASK
, COM
, {RA
, RS
, RB
}},
3354 {"andc.", XRC(31,60,1), X_MASK
, COM
, {RA
, RS
, RB
}},
3356 {"dcbste", X(31,62), XRT_MASK
, BOOKE64
, {RA
, RB
}},
3358 {"wait", X(31,62), 0xffffffff, E500MC
, {0}},
3360 {"lwzuxe", X(31,63), X_MASK
, BOOKE64
, {RT
, RAL
, RB
}},
3362 {"dcbstep", XRT(31,63,0), XRT_MASK
, E500MC
, {RA
, RB
}},
3364 {"tdlgt", XTO(31,68,TOLGT
), XTO_MASK
, PPC64
, {RA
, RB
}},
3365 {"tdllt", XTO(31,68,TOLLT
), XTO_MASK
, PPC64
, {RA
, RB
}},
3366 {"tdeq", XTO(31,68,TOEQ
), XTO_MASK
, PPC64
, {RA
, RB
}},
3367 {"tdlge", XTO(31,68,TOLGE
), XTO_MASK
, PPC64
, {RA
, RB
}},
3368 {"tdlnl", XTO(31,68,TOLNL
), XTO_MASK
, PPC64
, {RA
, RB
}},
3369 {"tdlle", XTO(31,68,TOLLE
), XTO_MASK
, PPC64
, {RA
, RB
}},
3370 {"tdlng", XTO(31,68,TOLNG
), XTO_MASK
, PPC64
, {RA
, RB
}},
3371 {"tdgt", XTO(31,68,TOGT
), XTO_MASK
, PPC64
, {RA
, RB
}},
3372 {"tdge", XTO(31,68,TOGE
), XTO_MASK
, PPC64
, {RA
, RB
}},
3373 {"tdnl", XTO(31,68,TONL
), XTO_MASK
, PPC64
, {RA
, RB
}},
3374 {"tdlt", XTO(31,68,TOLT
), XTO_MASK
, PPC64
, {RA
, RB
}},
3375 {"tdle", XTO(31,68,TOLE
), XTO_MASK
, PPC64
, {RA
, RB
}},
3376 {"tdng", XTO(31,68,TONG
), XTO_MASK
, PPC64
, {RA
, RB
}},
3377 {"tdne", XTO(31,68,TONE
), XTO_MASK
, PPC64
, {RA
, RB
}},
3378 {"td", X(31,68), X_MASK
, PPC64
, {TO
, RA
, RB
}},
3380 {"lwfcmx", APU(31,71,0), APU_MASK
, PPC405
, {FCRT
, RA
, RB
}},
3381 {"mulhd", XO(31,73,0,0), XO_MASK
, PPC64
, {RT
, RA
, RB
}},
3382 {"mulhd.", XO(31,73,0,1), XO_MASK
, PPC64
, {RT
, RA
, RB
}},
3384 {"mulhw", XO(31,75,0,0), XO_MASK
, PPC
, {RT
, RA
, RB
}},
3385 {"mulhw.", XO(31,75,0,1), XO_MASK
, PPC
, {RT
, RA
, RB
}},
3387 {"dlmzb", XRC(31,78,0), X_MASK
, PPC403
|PPC440
, {RA
, RS
, RB
}},
3388 {"dlmzb.", XRC(31,78,1), X_MASK
, PPC403
|PPC440
, {RA
, RS
, RB
}},
3390 {"mtsrd", X(31,82), XRB_MASK
|(1<<20), PPC64
, {SR
, RS
}},
3392 {"mfmsr", X(31,83), XRARB_MASK
, COM
, {RT
}},
3394 {"ldarx", X(31,84), XEH_MASK
, PPC64
, {RT
, RA0
, RB
, EH
}},
3396 {"dcbfl", XOPL(31,86,1), XRT_MASK
, POWER5
, {RA
, RB
}},
3397 {"dcbf", X(31,86), XLRT_MASK
, PPC
, {RA
, RB
, L
}},
3399 {"lbzx", X(31,87), X_MASK
, COM
, {RT
, RA0
, RB
}},
3401 {"dcbfe", X(31,94), XRT_MASK
, BOOKE64
, {RA
, RB
}},
3403 {"lbzxe", X(31,95), X_MASK
, BOOKE64
, {RT
, RA0
, RB
}},
3404 {"lbepx", X(31,95), X_MASK
, E500MC
, {RT
, RA
, RB
}},
3406 {"lvx", X(31,103), X_MASK
, PPCVEC
, {VD
, RA
, RB
}},
3407 {"lqfcmx", APU(31,103,0), APU_MASK
, PPC405
, {FCRT
, RA
, RB
}},
3409 {"neg", XO(31,104,0,0), XORB_MASK
, COM
, {RT
, RA
}},
3410 {"neg.", XO(31,104,0,1), XORB_MASK
, COM
, {RT
, RA
}},
3412 {"mul", XO(31,107,0,0), XO_MASK
, M601
, {RT
, RA
, RB
}},
3413 {"mul.", XO(31,107,0,1), XO_MASK
, M601
, {RT
, RA
, RB
}},
3415 {"mtsrdin", X(31,114), XRA_MASK
, PPC64
, {RS
, RB
}},
3417 {"clf", X(31,118), XTO_MASK
, POWER
, {RA
, RB
}},
3419 {"lbzux", X(31,119), X_MASK
, COM
, {RT
, RAL
, RB
}},
3421 {"popcntb", X(31,122), XRB_MASK
, POWER5
, {RA
, RS
}},
3423 {"not", XRC(31,124,0), X_MASK
, COM
, {RA
, RS
, RBS
}},
3424 {"nor", XRC(31,124,0), X_MASK
, COM
, {RA
, RS
, RB
}},
3425 {"not.", XRC(31,124,1), X_MASK
, COM
, {RA
, RS
, RBS
}},
3426 {"nor.", XRC(31,124,1), X_MASK
, COM
, {RA
, RS
, RB
}},
3428 {"lwarxe", X(31,126), X_MASK
, BOOKE64
, {RT
, RA0
, RB
}},
3430 {"lbzuxe", X(31,127), X_MASK
, BOOKE64
, {RT
, RAL
, RB
}},
3432 {"dcbfep", XRT(31,127,0), XRT_MASK
, E500MC
, {RA
, RB
}},
3434 {"wrtee", X(31,131), XRARB_MASK
, PPC403
|BOOKE
, {RS
}},
3436 {"dcbtstls", X(31,134), X_MASK
, PPCCHLK
, {CT
, RA
, RB
}},
3438 {"stvebx", X(31,135), X_MASK
, PPCVEC
, {VS
, RA
, RB
}},
3439 {"stbfcmx", APU(31,135,0), APU_MASK
, PPC405
, {FCRT
, RA
, RB
}},
3441 {"subfe", XO(31,136,0,0), XO_MASK
, PPCCOM
, {RT
, RA
, RB
}},
3442 {"sfe", XO(31,136,0,0), XO_MASK
, PWRCOM
, {RT
, RA
, RB
}},
3443 {"subfe.", XO(31,136,0,1), XO_MASK
, PPCCOM
, {RT
, RA
, RB
}},
3444 {"sfe.", XO(31,136,0,1), XO_MASK
, PWRCOM
, {RT
, RA
, RB
}},
3446 {"adde", XO(31,138,0,0), XO_MASK
, PPCCOM
, {RT
, RA
, RB
}},
3447 {"ae", XO(31,138,0,0), XO_MASK
, PWRCOM
, {RT
, RA
, RB
}},
3448 {"adde.", XO(31,138,0,1), XO_MASK
, PPCCOM
, {RT
, RA
, RB
}},
3449 {"ae.", XO(31,138,0,1), XO_MASK
, PWRCOM
, {RT
, RA
, RB
}},
3451 {"dcbtstlse", X(31,142), X_MASK
, PPCCHLK64
, {CT
, RA
, RB
}},
3453 {"mtcr", XFXM(31,144,0xff,0), XRARB_MASK
, COM
, {RS
}},
3454 {"mtcrf", XFXM(31,144,0,0), XFXFXM_MASK
, COM
, {FXM
, RS
}},
3455 {"mtocrf", XFXM(31,144,0,1), XFXFXM_MASK
, COM
, {FXM
, RS
}},
3457 {"mtmsr", X(31,146), XRLARB_MASK
, COM
, {RS
, A_L
}},
3459 {"stdx", X(31,149), X_MASK
, PPC64
, {RS
, RA0
, RB
}},
3461 {"stwcx.", XRC(31,150,1), X_MASK
, PPC
, {RS
, RA0
, RB
}},
3463 {"stwx", X(31,151), X_MASK
, PPCCOM
, {RS
, RA0
, RB
}},
3464 {"stx", X(31,151), X_MASK
, PWRCOM
, {RS
, RA
, RB
}},
3466 {"slq", XRC(31,152,0), X_MASK
, M601
, {RA
, RS
, RB
}},
3467 {"slq.", XRC(31,152,1), X_MASK
, M601
, {RA
, RS
, RB
}},
3469 {"sle", XRC(31,153,0), X_MASK
, M601
, {RA
, RS
, RB
}},
3470 {"sle.", XRC(31,153,1), X_MASK
, M601
, {RA
, RS
, RB
}},
3472 {"prtyw", X(31,154), XRB_MASK
, POWER6
, {RA
, RS
}},
3474 {"stdepx", X(31,157), X_MASK
, E500MC
, {RS
, RA
, RB
}},
3476 {"stwcxe.", XRC(31,158,1), X_MASK
, BOOKE64
, {RS
, RA0
, RB
}},
3478 {"stwxe", X(31,159), X_MASK
, BOOKE64
, {RS
, RA0
, RB
}},
3479 {"stwepx", X(31,159), X_MASK
, E500MC
, {RS
, RA
, RB
}},
3481 {"wrteei", X(31,163), XE_MASK
, PPC403
|BOOKE
, {E
}},
3483 {"dcbtls", X(31,166), X_MASK
, PPCCHLK
, {CT
, RA
, RB
}},
3485 {"stvehx", X(31,167), X_MASK
, PPCVEC
, {VS
, RA
, RB
}},
3486 {"sthfcmx", APU(31,167,0), APU_MASK
, PPC405
, {FCRT
, RA
, RB
}},
3488 {"dcbtlse", X(31,174), X_MASK
, PPCCHLK64
, {CT
, RA
, RB
}},
3490 {"mtmsrd", X(31,178), XRLARB_MASK
, PPC64
, {RS
, A_L
}},
3492 {"stdux", X(31,181), X_MASK
, PPC64
, {RS
, RAS
, RB
}},
3494 {"stwux", X(31,183), X_MASK
, PPCCOM
, {RS
, RAS
, RB
}},
3495 {"stux", X(31,183), X_MASK
, PWRCOM
, {RS
, RA0
, RB
}},
3497 {"sliq", XRC(31,184,0), X_MASK
, M601
, {RA
, RS
, SH
}},
3498 {"sliq.", XRC(31,184,1), X_MASK
, M601
, {RA
, RS
, SH
}},
3500 {"prtyd", X(31,186), XRB_MASK
, POWER6
, {RA
, RS
}},
3502 {"stwuxe", X(31,191), X_MASK
, BOOKE64
, {RS
, RAS
, RB
}},
3504 {"stvewx", X(31,199), X_MASK
, PPCVEC
, {VS
, RA
, RB
}},
3505 {"stwfcmx", APU(31,199,0), APU_MASK
, PPC405
, {FCRT
, RA
, RB
}},
3507 {"subfze", XO(31,200,0,0), XORB_MASK
, PPCCOM
, {RT
, RA
}},
3508 {"sfze", XO(31,200,0,0), XORB_MASK
, PWRCOM
, {RT
, RA
}},
3509 {"subfze.", XO(31,200,0,1), XORB_MASK
, PPCCOM
, {RT
, RA
}},
3510 {"sfze.", XO(31,200,0,1), XORB_MASK
, PWRCOM
, {RT
, RA
}},
3512 {"addze", XO(31,202,0,0), XORB_MASK
, PPCCOM
, {RT
, RA
}},
3513 {"aze", XO(31,202,0,0), XORB_MASK
, PWRCOM
, {RT
, RA
}},
3514 {"addze.", XO(31,202,0,1), XORB_MASK
, PPCCOM
, {RT
, RA
}},
3515 {"aze.", XO(31,202,0,1), XORB_MASK
, PWRCOM
, {RT
, RA
}},
3517 {"msgsnd", XRTRA(31,206,0,0),XRTRA_MASK
,E500MC
, {RB
}},
3519 {"mtsr", X(31,210), XRB_MASK
|(1<<20), COM32
, {SR
, RS
}},
3521 {"stdcx.", XRC(31,214,1), X_MASK
, PPC64
, {RS
, RA0
, RB
}},
3523 {"stbx", X(31,215), X_MASK
, COM
, {RS
, RA0
, RB
}},
3525 {"sllq", XRC(31,216,0), X_MASK
, M601
, {RA
, RS
, RB
}},
3526 {"sllq.", XRC(31,216,1), X_MASK
, M601
, {RA
, RS
, RB
}},
3528 {"sleq", XRC(31,217,0), X_MASK
, M601
, {RA
, RS
, RB
}},
3529 {"sleq.", XRC(31,217,1), X_MASK
, M601
, {RA
, RS
, RB
}},
3531 {"stbxe", X(31,223), X_MASK
, BOOKE64
, {RS
, RA0
, RB
}},
3532 {"stbepx", X(31,223), X_MASK
, E500MC
, {RS
, RA
, RB
}},
3534 {"icblc", X(31,230), X_MASK
, PPCCHLK
, {CT
, RA
, RB
}},
3536 {"stvx", X(31,231), X_MASK
, PPCVEC
, {VS
, RA
, RB
}},
3537 {"stqfcmx", APU(31,231,0), APU_MASK
, PPC405
, {FCRT
, RA
, RB
}},
3539 {"subfme", XO(31,232,0,0), XORB_MASK
, PPCCOM
, {RT
, RA
}},
3540 {"sfme", XO(31,232,0,0), XORB_MASK
, PWRCOM
, {RT
, RA
}},
3541 {"subfme.", XO(31,232,0,1), XORB_MASK
, PPCCOM
, {RT
, RA
}},
3542 {"sfme.", XO(31,232,0,1), XORB_MASK
, PWRCOM
, {RT
, RA
}},
3544 {"mulld", XO(31,233,0,0), XO_MASK
, PPC64
, {RT
, RA
, RB
}},
3545 {"mulld.", XO(31,233,0,1), XO_MASK
, PPC64
, {RT
, RA
, RB
}},
3547 {"addme", XO(31,234,0,0), XORB_MASK
, PPCCOM
, {RT
, RA
}},
3548 {"ame", XO(31,234,0,0), XORB_MASK
, PWRCOM
, {RT
, RA
}},
3549 {"addme.", XO(31,234,0,1), XORB_MASK
, PPCCOM
, {RT
, RA
}},
3550 {"ame.", XO(31,234,0,1), XORB_MASK
, PWRCOM
, {RT
, RA
}},
3552 {"mullw", XO(31,235,0,0), XO_MASK
, PPCCOM
, {RT
, RA
, RB
}},
3553 {"muls", XO(31,235,0,0), XO_MASK
, PWRCOM
, {RT
, RA
, RB
}},
3554 {"mullw.", XO(31,235,0,1), XO_MASK
, PPCCOM
, {RT
, RA
, RB
}},
3555 {"muls.", XO(31,235,0,1), XO_MASK
, PWRCOM
, {RT
, RA
, RB
}},
3557 {"msgclr", XRTRA(31,238,0,0),XRTRA_MASK
,E500MC
, {RB
}},
3558 {"icblce", X(31,238), X_MASK
, PPCCHLK64
, {CT
, RA
, RB
}},
3559 {"mtsrin", X(31,242), XRA_MASK
, PPC32
, {RS
, RB
}},
3560 {"mtsri", X(31,242), XRA_MASK
, POWER32
, {RS
, RB
}},
3562 {"dcbtst", X(31,246), X_MASK
, PPC
, {CT
, RA
, RB
}},
3564 {"stbux", X(31,247), X_MASK
, COM
, {RS
, RAS
, RB
}},
3566 {"slliq", XRC(31,248,0), X_MASK
, M601
, {RA
, RS
, SH
}},
3567 {"slliq.", XRC(31,248,1), X_MASK
, M601
, {RA
, RS
, SH
}},
3569 {"dcbtste", X(31,253), X_MASK
, BOOKE64
, {CT
, RA
, RB
}},
3571 {"stbuxe", X(31,255), X_MASK
, BOOKE64
, {RS
, RAS
, RB
}},
3573 {"dcbtstep", XRT(31,255,0), X_MASK
, E500MC
, {RT
, RA
, RB
}},
3575 {"mfdcrx", X(31,259), X_MASK
, BOOKE
, {RS
, RA
}},
3577 {"icbt", X(31,262), XRT_MASK
, PPC403
, {RA
, RB
}},
3579 {"ldfcmx", APU(31,263,0), APU_MASK
, PPC405
, {FCRT
, RA
, RB
}},
3580 {"doz", XO(31,264,0,0), XO_MASK
, M601
, {RT
, RA
, RB
}},
3581 {"doz.", XO(31,264,0,1), XO_MASK
, M601
, {RT
, RA
, RB
}},
3583 {"add", XO(31,266,0,0), XO_MASK
, PPCCOM
, {RT
, RA
, RB
}},
3584 {"cax", XO(31,266,0,0), XO_MASK
, PWRCOM
, {RT
, RA
, RB
}},
3585 {"add.", XO(31,266,0,1), XO_MASK
, PPCCOM
, {RT
, RA
, RB
}},
3586 {"cax.", XO(31,266,0,1), XO_MASK
, PWRCOM
, {RT
, RA
, RB
}},
3588 {"ehpriv", X(31,270), 0xffffffff, E500MC
, {0}},
3590 {"tlbiel", X(31,274), XRTLRA_MASK
, POWER4
, {RB
, L
}},
3592 {"mfapidi", X(31,275), X_MASK
, BOOKE
, {RT
, RA
}},
3594 {"lscbx", XRC(31,277,0), X_MASK
, M601
, {RT
, RA
, RB
}},
3595 {"lscbx.", XRC(31,277,1), X_MASK
, M601
, {RT
, RA
, RB
}},
3597 {"dcbt", X(31,278), X_MASK
, PPC
, {CT
, RA
, RB
}},
3599 {"lhzx", X(31,279), X_MASK
, COM
, {RT
, RA0
, RB
}},
3601 {"eqv", XRC(31,284,0), X_MASK
, COM
, {RA
, RS
, RB
}},
3602 {"eqv.", XRC(31,284,1), X_MASK
, COM
, {RA
, RS
, RB
}},
3604 {"dcbte", X(31,286), X_MASK
, BOOKE64
, {CT
, RA
, RB
}},
3606 {"lhzxe", X(31,287), X_MASK
, BOOKE64
, {RT
, RA0
, RB
}},
3607 {"lhepx", X(31,287), X_MASK
, E500MC
, {RT
, RA
, RB
}},
3609 {"mfdcrux", X(31,291), X_MASK
, PPC464
, {RS
, RA
}},
3611 {"tlbie", X(31,306), XRTLRA_MASK
, PPC
, {RB
, L
}},
3612 {"tlbi", X(31,306), XRT_MASK
, POWER
, {RA0
, RB
}},
3614 {"eciwx", X(31,310), X_MASK
, PPC
, {RT
, RA
, RB
}},
3616 {"lhzux", X(31,311), X_MASK
, COM
, {RT
, RAL
, RB
}},
3618 {"xor", XRC(31,316,0), X_MASK
, COM
, {RA
, RS
, RB
}},
3619 {"xor.", XRC(31,316,1), X_MASK
, COM
, {RA
, RS
, RB
}},
3621 {"lhzuxe", X(31,319), X_MASK
, BOOKE64
, {RT
, RAL
, RB
}},
3623 {"dcbtep", XRT(31,319,0), X_MASK
, E500MC
, {RT
, RA
, RB
}},
3625 {"mfexisr", XSPR(31,323, 64), XSPR_MASK
, PPC403
, {RT
}},
3626 {"mfexier", XSPR(31,323, 66), XSPR_MASK
, PPC403
, {RT
}},
3627 {"mfbr0", XSPR(31,323,128), XSPR_MASK
, PPC403
, {RT
}},
3628 {"mfbr1", XSPR(31,323,129), XSPR_MASK
, PPC403
, {RT
}},
3629 {"mfbr2", XSPR(31,323,130), XSPR_MASK
, PPC403
, {RT
}},
3630 {"mfbr3", XSPR(31,323,131), XSPR_MASK
, PPC403
, {RT
}},
3631 {"mfbr4", XSPR(31,323,132), XSPR_MASK
, PPC403
, {RT
}},
3632 {"mfbr5", XSPR(31,323,133), XSPR_MASK
, PPC403
, {RT
}},
3633 {"mfbr6", XSPR(31,323,134), XSPR_MASK
, PPC403
, {RT
}},
3634 {"mfbr7", XSPR(31,323,135), XSPR_MASK
, PPC403
, {RT
}},
3635 {"mfbear", XSPR(31,323,144), XSPR_MASK
, PPC403
, {RT
}},
3636 {"mfbesr", XSPR(31,323,145), XSPR_MASK
, PPC403
, {RT
}},
3637 {"mfiocr", XSPR(31,323,160), XSPR_MASK
, PPC403
, {RT
}},
3638 {"mfdmacr0", XSPR(31,323,192), XSPR_MASK
, PPC403
, {RT
}},
3639 {"mfdmact0", XSPR(31,323,193), XSPR_MASK
, PPC403
, {RT
}},
3640 {"mfdmada0", XSPR(31,323,194), XSPR_MASK
, PPC403
, {RT
}},
3641 {"mfdmasa0", XSPR(31,323,195), XSPR_MASK
, PPC403
, {RT
}},
3642 {"mfdmacc0", XSPR(31,323,196), XSPR_MASK
, PPC403
, {RT
}},
3643 {"mfdmacr1", XSPR(31,323,200), XSPR_MASK
, PPC403
, {RT
}},
3644 {"mfdmact1", XSPR(31,323,201), XSPR_MASK
, PPC403
, {RT
}},
3645 {"mfdmada1", XSPR(31,323,202), XSPR_MASK
, PPC403
, {RT
}},
3646 {"mfdmasa1", XSPR(31,323,203), XSPR_MASK
, PPC403
, {RT
}},
3647 {"mfdmacc1", XSPR(31,323,204), XSPR_MASK
, PPC403
, {RT
}},
3648 {"mfdmacr2", XSPR(31,323,208), XSPR_MASK
, PPC403
, {RT
}},
3649 {"mfdmact2", XSPR(31,323,209), XSPR_MASK
, PPC403
, {RT
}},
3650 {"mfdmada2", XSPR(31,323,210), XSPR_MASK
, PPC403
, {RT
}},
3651 {"mfdmasa2", XSPR(31,323,211), XSPR_MASK
, PPC403
, {RT
}},
3652 {"mfdmacc2", XSPR(31,323,212), XSPR_MASK
, PPC403
, {RT
}},
3653 {"mfdmacr3", XSPR(31,323,216), XSPR_MASK
, PPC403
, {RT
}},
3654 {"mfdmact3", XSPR(31,323,217), XSPR_MASK
, PPC403
, {RT
}},
3655 {"mfdmada3", XSPR(31,323,218), XSPR_MASK
, PPC403
, {RT
}},
3656 {"mfdmasa3", XSPR(31,323,219), XSPR_MASK
, PPC403
, {RT
}},
3657 {"mfdmacc3", XSPR(31,323,220), XSPR_MASK
, PPC403
, {RT
}},
3658 {"mfdmasr", XSPR(31,323,224), XSPR_MASK
, PPC403
, {RT
}},
3659 {"mfdcr", X(31,323), X_MASK
, PPC403
|BOOKE
, {RT
, SPR
}},
3661 {"div", XO(31,331,0,0), XO_MASK
, M601
, {RT
, RA
, RB
}},
3662 {"div.", XO(31,331,0,1), XO_MASK
, M601
, {RT
, RA
, RB
}},
3664 {"mfpmr", X(31,334), X_MASK
, PPCPMR
, {RT
, PMR
}},
3666 {"mfmq", XSPR(31,339, 0), XSPR_MASK
, M601
, {RT
}},
3667 {"mfxer", XSPR(31,339, 1), XSPR_MASK
, COM
, {RT
}},
3668 {"mfrtcu", XSPR(31,339, 4), XSPR_MASK
, COM
, {RT
}},
3669 {"mfrtcl", XSPR(31,339, 5), XSPR_MASK
, COM
, {RT
}},
3670 {"mfdec", XSPR(31,339, 6), XSPR_MASK
, MFDEC1
, {RT
}},
3671 {"mflr", XSPR(31,339, 8), XSPR_MASK
, COM
, {RT
}},
3672 {"mfctr", XSPR(31,339, 9), XSPR_MASK
, COM
, {RT
}},
3673 {"mftid", XSPR(31,339, 17), XSPR_MASK
, POWER
, {RT
}},
3674 {"mfdsisr", XSPR(31,339, 18), XSPR_MASK
, COM
, {RT
}},
3675 {"mfdar", XSPR(31,339, 19), XSPR_MASK
, COM
, {RT
}},
3676 {"mfdec", XSPR(31,339, 22), XSPR_MASK
, MFDEC2
, {RT
}},
3677 {"mfsdr0", XSPR(31,339, 24), XSPR_MASK
, POWER
, {RT
}},
3678 {"mfsdr1", XSPR(31,339, 25), XSPR_MASK
, COM
, {RT
}},
3679 {"mfsrr0", XSPR(31,339, 26), XSPR_MASK
, COM
, {RT
}},
3680 {"mfsrr1", XSPR(31,339, 27), XSPR_MASK
, COM
, {RT
}},
3681 {"mfcfar", XSPR(31,339, 28), XSPR_MASK
, POWER6
, {RT
}},
3682 {"mfpid", XSPR(31,339, 48), XSPR_MASK
, BOOKE
, {RT
}},
3683 {"mfcsrr0", XSPR(31,339, 58), XSPR_MASK
, BOOKE
, {RT
}},
3684 {"mfcsrr1", XSPR(31,339, 59), XSPR_MASK
, BOOKE
, {RT
}},
3685 {"mfdear", XSPR(31,339, 61), XSPR_MASK
, BOOKE
, {RT
}},
3686 {"mfesr", XSPR(31,339, 62), XSPR_MASK
, BOOKE
, {RT
}},
3687 {"mfivpr", XSPR(31,339, 63), XSPR_MASK
, BOOKE
, {RT
}},
3688 {"mfcmpa", XSPR(31,339,144), XSPR_MASK
, PPC860
, {RT
}},
3689 {"mfcmpb", XSPR(31,339,145), XSPR_MASK
, PPC860
, {RT
}},
3690 {"mfcmpc", XSPR(31,339,146), XSPR_MASK
, PPC860
, {RT
}},
3691 {"mfcmpd", XSPR(31,339,147), XSPR_MASK
, PPC860
, {RT
}},
3692 {"mficr", XSPR(31,339,148), XSPR_MASK
, PPC860
, {RT
}},
3693 {"mfder", XSPR(31,339,149), XSPR_MASK
, PPC860
, {RT
}},
3694 {"mfcounta", XSPR(31,339,150), XSPR_MASK
, PPC860
, {RT
}},
3695 {"mfcountb", XSPR(31,339,151), XSPR_MASK
, PPC860
, {RT
}},
3696 {"mfcmpe", XSPR(31,339,152), XSPR_MASK
, PPC860
, {RT
}},
3697 {"mfcmpf", XSPR(31,339,153), XSPR_MASK
, PPC860
, {RT
}},
3698 {"mfcmpg", XSPR(31,339,154), XSPR_MASK
, PPC860
, {RT
}},
3699 {"mfcmph", XSPR(31,339,155), XSPR_MASK
, PPC860
, {RT
}},
3700 {"mflctrl1", XSPR(31,339,156), XSPR_MASK
, PPC860
, {RT
}},
3701 {"mflctrl2", XSPR(31,339,157), XSPR_MASK
, PPC860
, {RT
}},
3702 {"mfictrl", XSPR(31,339,158), XSPR_MASK
, PPC860
, {RT
}},
3703 {"mfbar", XSPR(31,339,159), XSPR_MASK
, PPC860
, {RT
}},
3704 {"mfvrsave", XSPR(31,339,256), XSPR_MASK
, PPCVEC
, {RT
}},
3705 {"mfusprg0", XSPR(31,339,256), XSPR_MASK
, BOOKE
, {RT
}},
3706 {"mfsprg", XSPR(31,339,256), XSPRG_MASK
, PPC
, {RT
, SPRG
}},
3707 {"mfsprg4", XSPR(31,339,260), XSPR_MASK
, PPC405
|BOOKE
, {RT
}},
3708 {"mfsprg5", XSPR(31,339,261), XSPR_MASK
, PPC405
|BOOKE
, {RT
}},
3709 {"mfsprg6", XSPR(31,339,262), XSPR_MASK
, PPC405
|BOOKE
, {RT
}},
3710 {"mfsprg7", XSPR(31,339,263), XSPR_MASK
, PPC405
|BOOKE
, {RT
}},
3711 {"mftb", XSPR(31,339,268), XSPR_MASK
, BOOKE
, {RT
}},
3712 {"mftbl", XSPR(31,339,268), XSPR_MASK
, BOOKE
, {RT
}},
3713 {"mftbu", XSPR(31,339,269), XSPR_MASK
, BOOKE
, {RT
}},
3714 {"mfsprg0", XSPR(31,339,272), XSPR_MASK
, PPC
, {RT
}},
3715 {"mfsprg1", XSPR(31,339,273), XSPR_MASK
, PPC
, {RT
}},
3716 {"mfsprg2", XSPR(31,339,274), XSPR_MASK
, PPC
, {RT
}},
3717 {"mfsprg3", XSPR(31,339,275), XSPR_MASK
, PPC
, {RT
}},
3718 {"mfasr", XSPR(31,339,280), XSPR_MASK
, PPC64
, {RT
}},
3719 {"mfear", XSPR(31,339,282), XSPR_MASK
, PPC
, {RT
}},
3720 {"mfpir", XSPR(31,339,286), XSPR_MASK
, BOOKE
, {RT
}},
3721 {"mfpvr", XSPR(31,339,287), XSPR_MASK
, PPC
, {RT
}},
3722 {"mfdbsr", XSPR(31,339,304), XSPR_MASK
, BOOKE
, {RT
}},
3723 {"mfdbcr0", XSPR(31,339,308), XSPR_MASK
, BOOKE
, {RT
}},
3724 {"mfdbcr1", XSPR(31,339,309), XSPR_MASK
, BOOKE
, {RT
}},
3725 {"mfdbcr2", XSPR(31,339,310), XSPR_MASK
, BOOKE
, {RT
}},
3726 {"mfiac1", XSPR(31,339,312), XSPR_MASK
, BOOKE
, {RT
}},
3727 {"mfiac2", XSPR(31,339,313), XSPR_MASK
, BOOKE
, {RT
}},
3728 {"mfiac3", XSPR(31,339,314), XSPR_MASK
, BOOKE
, {RT
}},
3729 {"mfiac4", XSPR(31,339,315), XSPR_MASK
, BOOKE
, {RT
}},
3730 {"mfdac1", XSPR(31,339,316), XSPR_MASK
, BOOKE
, {RT
}},
3731 {"mfdac2", XSPR(31,339,317), XSPR_MASK
, BOOKE
, {RT
}},
3732 {"mfdvc1", XSPR(31,339,318), XSPR_MASK
, BOOKE
, {RT
}},
3733 {"mfdvc2", XSPR(31,339,319), XSPR_MASK
, BOOKE
, {RT
}},
3734 {"mftsr", XSPR(31,339,336), XSPR_MASK
, BOOKE
, {RT
}},
3735 {"mftcr", XSPR(31,339,340), XSPR_MASK
, BOOKE
, {RT
}},
3736 {"mfivor0", XSPR(31,339,400), XSPR_MASK
, BOOKE
, {RT
}},
3737 {"mfivor1", XSPR(31,339,401), XSPR_MASK
, BOOKE
, {RT
}},
3738 {"mfivor2", XSPR(31,339,402), XSPR_MASK
, BOOKE
, {RT
}},
3739 {"mfivor3", XSPR(31,339,403), XSPR_MASK
, BOOKE
, {RT
}},
3740 {"mfivor4", XSPR(31,339,404), XSPR_MASK
, BOOKE
, {RT
}},
3741 {"mfivor5", XSPR(31,339,405), XSPR_MASK
, BOOKE
, {RT
}},
3742 {"mfivor6", XSPR(31,339,406), XSPR_MASK
, BOOKE
, {RT
}},
3743 {"mfivor7", XSPR(31,339,407), XSPR_MASK
, BOOKE
, {RT
}},
3744 {"mfivor8", XSPR(31,339,408), XSPR_MASK
, BOOKE
, {RT
}},
3745 {"mfivor9", XSPR(31,339,409), XSPR_MASK
, BOOKE
, {RT
}},
3746 {"mfivor10", XSPR(31,339,410), XSPR_MASK
, BOOKE
, {RT
}},
3747 {"mfivor11", XSPR(31,339,411), XSPR_MASK
, BOOKE
, {RT
}},
3748 {"mfivor12", XSPR(31,339,412), XSPR_MASK
, BOOKE
, {RT
}},
3749 {"mfivor13", XSPR(31,339,413), XSPR_MASK
, BOOKE
, {RT
}},
3750 {"mfivor14", XSPR(31,339,414), XSPR_MASK
, BOOKE
, {RT
}},
3751 {"mfivor15", XSPR(31,339,415), XSPR_MASK
, BOOKE
, {RT
}},
3752 {"mfspefscr", XSPR(31,339,512), XSPR_MASK
, PPCSPE
, {RT
}},
3753 {"mfbbear", XSPR(31,339,513), XSPR_MASK
, PPCBRLK
, {RT
}},
3754 {"mfbbtar", XSPR(31,339,514), XSPR_MASK
, PPCBRLK
, {RT
}},
3755 {"mfivor32", XSPR(31,339,528), XSPR_MASK
, PPCSPE
, {RT
}},
3756 {"mfibatu", XSPR(31,339,528), XSPRBAT_MASK
, PPC
, {RT
, SPRBAT
}},
3757 {"mfivor33", XSPR(31,339,529), XSPR_MASK
, PPCSPE
, {RT
}},
3758 {"mfibatl", XSPR(31,339,529), XSPRBAT_MASK
, PPC
, {RT
, SPRBAT
}},
3759 {"mfivor34", XSPR(31,339,530), XSPR_MASK
, PPCSPE
, {RT
}},
3760 {"mfivor35", XSPR(31,339,531), XSPR_MASK
, PPCPMR
, {RT
}},
3761 {"mfdbatu", XSPR(31,339,536), XSPRBAT_MASK
, PPC
, {RT
, SPRBAT
}},
3762 {"mfdbatl", XSPR(31,339,537), XSPRBAT_MASK
, PPC
, {RT
, SPRBAT
}},
3763 {"mfic_cst", XSPR(31,339,560), XSPR_MASK
, PPC860
, {RT
}},
3764 {"mfic_adr", XSPR(31,339,561), XSPR_MASK
, PPC860
, {RT
}},
3765 {"mfic_dat", XSPR(31,339,562), XSPR_MASK
, PPC860
, {RT
}},
3766 {"mfdc_cst", XSPR(31,339,568), XSPR_MASK
, PPC860
, {RT
}},
3767 {"mfdc_adr", XSPR(31,339,569), XSPR_MASK
, PPC860
, {RT
}},
3768 {"mfdc_dat", XSPR(31,339,570), XSPR_MASK
, PPC860
, {RT
}},
3769 {"mfmcsrr0", XSPR(31,339,570), XSPR_MASK
, PPCRFMCI
, {RT
}},
3770 {"mfmcsrr1", XSPR(31,339,571), XSPR_MASK
, PPCRFMCI
, {RT
}},
3771 {"mfmcsr", XSPR(31,339,572), XSPR_MASK
, PPCRFMCI
, {RT
}},
3772 {"mfmcar", XSPR(31,339,573), XSPR_MASK
, PPCRFMCI
, {RT
}},
3773 {"mfdpdr", XSPR(31,339,630), XSPR_MASK
, PPC860
, {RT
}},
3774 {"mfdpir", XSPR(31,339,631), XSPR_MASK
, PPC860
, {RT
}},
3775 {"mfimmr", XSPR(31,339,638), XSPR_MASK
, PPC860
, {RT
}},
3776 {"mfmi_ctr", XSPR(31,339,784), XSPR_MASK
, PPC860
, {RT
}},
3777 {"mfmi_ap", XSPR(31,339,786), XSPR_MASK
, PPC860
, {RT
}},
3778 {"mfmi_epn", XSPR(31,339,787), XSPR_MASK
, PPC860
, {RT
}},
3779 {"mfmi_twc", XSPR(31,339,789), XSPR_MASK
, PPC860
, {RT
}},
3780 {"mfmi_rpn", XSPR(31,339,790), XSPR_MASK
, PPC860
, {RT
}},
3781 {"mfmd_ctr", XSPR(31,339,792), XSPR_MASK
, PPC860
, {RT
}},
3782 {"mfm_casid", XSPR(31,339,793), XSPR_MASK
, PPC860
, {RT
}},
3783 {"mfmd_ap", XSPR(31,339,794), XSPR_MASK
, PPC860
, {RT
}},
3784 {"mfmd_epn", XSPR(31,339,795), XSPR_MASK
, PPC860
, {RT
}},
3785 {"mfmd_twb", XSPR(31,339,796), XSPR_MASK
, PPC860
, {RT
}},
3786 {"mfmd_twc", XSPR(31,339,797), XSPR_MASK
, PPC860
, {RT
}},
3787 {"mfmd_rpn", XSPR(31,339,798), XSPR_MASK
, PPC860
, {RT
}},
3788 {"mfm_tw", XSPR(31,339,799), XSPR_MASK
, PPC860
, {RT
}},
3789 {"mfmi_dbcam", XSPR(31,339,816), XSPR_MASK
, PPC860
, {RT
}},
3790 {"mfmi_dbram0", XSPR(31,339,817), XSPR_MASK
, PPC860
, {RT
}},
3791 {"mfmi_dbram1", XSPR(31,339,818), XSPR_MASK
, PPC860
, {RT
}},
3792 {"mfmd_dbcam", XSPR(31,339,824), XSPR_MASK
, PPC860
, {RT
}},
3793 {"mfmd_dbram0", XSPR(31,339,825), XSPR_MASK
, PPC860
, {RT
}},
3794 {"mfmd_dbram1", XSPR(31,339,826), XSPR_MASK
, PPC860
, {RT
}},
3795 {"mfummcr0", XSPR(31,339,936), XSPR_MASK
, PPC750
, {RT
}},
3796 {"mfupmc1", XSPR(31,339,937), XSPR_MASK
, PPC750
, {RT
}},
3797 {"mfupmc2", XSPR(31,339,938), XSPR_MASK
, PPC750
, {RT
}},
3798 {"mfusia", XSPR(31,339,939), XSPR_MASK
, PPC750
, {RT
}},
3799 {"mfummcr1", XSPR(31,339,940), XSPR_MASK
, PPC750
, {RT
}},
3800 {"mfupmc3", XSPR(31,339,941), XSPR_MASK
, PPC750
, {RT
}},
3801 {"mfupmc4", XSPR(31,339,942), XSPR_MASK
, PPC750
, {RT
}},
3802 {"mfzpr", XSPR(31,339,944), XSPR_MASK
, PPC403
, {RT
}},
3803 {"mfpid", XSPR(31,339,945), XSPR_MASK
, PPC403
, {RT
}},
3804 {"mfccr0", XSPR(31,339,947), XSPR_MASK
, PPC405
, {RT
}},
3805 {"mfiac3", XSPR(31,339,948), XSPR_MASK
, PPC405
, {RT
}},
3806 {"mfiac4", XSPR(31,339,949), XSPR_MASK
, PPC405
, {RT
}},
3807 {"mfdvc1", XSPR(31,339,950), XSPR_MASK
, PPC405
, {RT
}},
3808 {"mfdvc2", XSPR(31,339,951), XSPR_MASK
, PPC405
, {RT
}},
3809 {"mfmmcr0", XSPR(31,339,952), XSPR_MASK
, PPC750
, {RT
}},
3810 {"mfpmc1", XSPR(31,339,953), XSPR_MASK
, PPC750
, {RT
}},
3811 {"mfsgr", XSPR(31,339,953), XSPR_MASK
, PPC403
, {RT
}},
3812 {"mfdcwr", XSPR(31,339,954), XSPR_MASK
, PPC403
, {RT
}},
3813 {"mfpmc2", XSPR(31,339,954), XSPR_MASK
, PPC750
, {RT
}},
3814 {"mfsia", XSPR(31,339,955), XSPR_MASK
, PPC750
, {RT
}},
3815 {"mfsler", XSPR(31,339,955), XSPR_MASK
, PPC405
, {RT
}},
3816 {"mfmmcr1", XSPR(31,339,956), XSPR_MASK
, PPC750
, {RT
}},
3817 {"mfsu0r", XSPR(31,339,956), XSPR_MASK
, PPC405
, {RT
}},
3818 {"mfdbcr1", XSPR(31,339,957), XSPR_MASK
, PPC405
, {RT
}},
3819 {"mfpmc3", XSPR(31,339,957), XSPR_MASK
, PPC750
, {RT
}},
3820 {"mfpmc4", XSPR(31,339,958), XSPR_MASK
, PPC750
, {RT
}},
3821 {"mficdbdr", XSPR(31,339,979), XSPR_MASK
, PPC403
, {RT
}},
3822 {"mfesr", XSPR(31,339,980), XSPR_MASK
, PPC403
, {RT
}},
3823 {"mfdear", XSPR(31,339,981), XSPR_MASK
, PPC403
, {RT
}},
3824 {"mfevpr", XSPR(31,339,982), XSPR_MASK
, PPC403
, {RT
}},
3825 {"mfcdbcr", XSPR(31,339,983), XSPR_MASK
, PPC403
, {RT
}},
3826 {"mftsr", XSPR(31,339,984), XSPR_MASK
, PPC403
, {RT
}},
3827 {"mftcr", XSPR(31,339,986), XSPR_MASK
, PPC403
, {RT
}},
3828 {"mfpit", XSPR(31,339,987), XSPR_MASK
, PPC403
, {RT
}},
3829 {"mftbhi", XSPR(31,339,988), XSPR_MASK
, PPC403
, {RT
}},
3830 {"mftblo", XSPR(31,339,989), XSPR_MASK
, PPC403
, {RT
}},
3831 {"mfsrr2", XSPR(31,339,990), XSPR_MASK
, PPC403
, {RT
}},
3832 {"mfsrr3", XSPR(31,339,991), XSPR_MASK
, PPC403
, {RT
}},
3833 {"mfdbsr", XSPR(31,339,1008), XSPR_MASK
, PPC403
, {RT
}},
3834 {"mfdbcr0", XSPR(31,339,1010), XSPR_MASK
, PPC405
, {RT
}},
3835 {"mfiac1", XSPR(31,339,1012), XSPR_MASK
, PPC403
, {RT
}},
3836 {"mfiac2", XSPR(31,339,1013), XSPR_MASK
, PPC403
, {RT
}},
3837 {"mfdac1", XSPR(31,339,1014), XSPR_MASK
, PPC403
, {RT
}},
3838 {"mfdac2", XSPR(31,339,1015), XSPR_MASK
, PPC403
, {RT
}},
3839 {"mfl2cr", XSPR(31,339,1017), XSPR_MASK
, PPC750
, {RT
}},
3840 {"mfdccr", XSPR(31,339,1018), XSPR_MASK
, PPC403
, {RT
}},
3841 {"mficcr", XSPR(31,339,1019), XSPR_MASK
, PPC403
, {RT
}},
3842 {"mfictc", XSPR(31,339,1019), XSPR_MASK
, PPC750
, {RT
}},
3843 {"mfpbl1", XSPR(31,339,1020), XSPR_MASK
, PPC403
, {RT
}},
3844 {"mfthrm1", XSPR(31,339,1020), XSPR_MASK
, PPC750
, {RT
}},
3845 {"mfpbu1", XSPR(31,339,1021), XSPR_MASK
, PPC403
, {RT
}},
3846 {"mfthrm2", XSPR(31,339,1021), XSPR_MASK
, PPC750
, {RT
}},
3847 {"mfpbl2", XSPR(31,339,1022), XSPR_MASK
, PPC403
, {RT
}},
3848 {"mfthrm3", XSPR(31,339,1022), XSPR_MASK
, PPC750
, {RT
}},
3849 {"mfpbu2", XSPR(31,339,1023), XSPR_MASK
, PPC403
, {RT
}},
3850 {"mfspr", X(31,339), X_MASK
, COM
, {RT
, SPR
}},
3852 {"lwax", X(31,341), X_MASK
, PPC64
, {RT
, RA0
, RB
}},
3854 {"dst", XDSS(31,342,0), XDSS_MASK
, PPCVEC
, {RA
, RB
, STRM
}},
3856 {"lhax", X(31,343), X_MASK
, COM
, {RT
, RA0
, RB
}},
3858 {"lhaxe", X(31,351), X_MASK
, BOOKE64
, {RT
, RA0
, RB
}},
3860 {"lvxl", X(31,359), X_MASK
, PPCVEC
, {VD
, RA
, RB
}},
3862 {"abs", XO(31,360,0,0), XORB_MASK
, M601
, {RT
, RA
}},
3863 {"abs.", XO(31,360,0,1), XORB_MASK
, M601
, {RT
, RA
}},
3865 {"divs", XO(31,363,0,0), XO_MASK
, M601
, {RT
, RA
, RB
}},
3866 {"divs.", XO(31,363,0,1), XO_MASK
, M601
, {RT
, RA
, RB
}},
3868 {"tlbia", X(31,370), 0xffffffff, PPC
, {0}},
3870 {"mftbl", XSPR(31,371,268), XSPR_MASK
, CLASSIC
, {RT
}},
3871 {"mftbu", XSPR(31,371,269), XSPR_MASK
, CLASSIC
, {RT
}},
3872 {"mftb", X(31,371), X_MASK
, CLASSIC
, {RT
, TBR
}},
3874 {"lwaux", X(31,373), X_MASK
, PPC64
, {RT
, RAL
, RB
}},
3876 {"dstst", XDSS(31,374,0), XDSS_MASK
, PPCVEC
, {RA
, RB
, STRM
}},
3878 {"lhaux", X(31,375), X_MASK
, COM
, {RT
, RAL
, RB
}},
3880 {"lhauxe", X(31,383), X_MASK
, BOOKE64
, {RT
, RAL
, RB
}},
3882 {"mtdcrx", X(31,387), X_MASK
, BOOKE
, {RA
, RS
}},
3884 {"dcblc", X(31,390), X_MASK
, PPCCHLK
, {CT
, RA
, RB
}},
3885 {"stdfcmx", APU(31,391,0), APU_MASK
, PPC405
, {FCRT
, RA
, RB
}},
3887 {"subfe64", XO(31,392,0,0), XO_MASK
, BOOKE64
, {RT
, RA
, RB
}},
3889 {"adde64", XO(31,394,0,0), XO_MASK
, BOOKE64
, {RT
, RA
, RB
}},
3891 {"dcblce", X(31,398), X_MASK
, PPCCHLK64
, {CT
, RA
, RB
}},
3893 {"slbmte", X(31,402), XRA_MASK
, PPC64
, {RS
, RB
}},
3895 {"sthx", X(31,407), X_MASK
, COM
, {RS
, RA0
, RB
}},
3897 {"orc", XRC(31,412,0), X_MASK
, COM
, {RA
, RS
, RB
}},
3898 {"orc.", XRC(31,412,1), X_MASK
, COM
, {RA
, RS
, RB
}},
3900 {"sthxe", X(31,415), X_MASK
, BOOKE64
, {RS
, RA0
, RB
}},
3901 {"sthepx", X(31,415), X_MASK
, E500MC
, {RS
, RA
, RB
}},
3903 {"mtdcrux", X(31,419), X_MASK
, PPC464
, {RA
, RS
}},
3905 {"slbie", X(31,434), XRTRA_MASK
, PPC64
, {RB
}},
3907 {"ecowx", X(31,438), X_MASK
, PPC
, {RT
, RA
, RB
}},
3909 {"sthux", X(31,439), X_MASK
, COM
, {RS
, RAS
, RB
}},
3911 {"mdors", 0x7f9ce378, 0xffffffff, E500MC
, {0}},
3913 {"mr", XRC(31,444,0), X_MASK
, COM
, {RA
, RS
, RBS
}},
3914 {"or", XRC(31,444,0), X_MASK
, COM
, {RA
, RS
, RB
}},
3915 {"mr.", XRC(31,444,1), X_MASK
, COM
, {RA
, RS
, RBS
}},
3916 {"or.", XRC(31,444,1), X_MASK
, COM
, {RA
, RS
, RB
}},
3918 {"sthuxe", X(31,447), X_MASK
, BOOKE64
, {RS
, RAS
, RB
}},
3920 {"mtexisr", XSPR(31,451, 64), XSPR_MASK
, PPC403
, {RS
}},
3921 {"mtexier", XSPR(31,451, 66), XSPR_MASK
, PPC403
, {RS
}},
3922 {"mtbr0", XSPR(31,451,128), XSPR_MASK
, PPC403
, {RS
}},
3923 {"mtbr1", XSPR(31,451,129), XSPR_MASK
, PPC403
, {RS
}},
3924 {"mtbr2", XSPR(31,451,130), XSPR_MASK
, PPC403
, {RS
}},
3925 {"mtbr3", XSPR(31,451,131), XSPR_MASK
, PPC403
, {RS
}},
3926 {"mtbr4", XSPR(31,451,132), XSPR_MASK
, PPC403
, {RS
}},
3927 {"mtbr5", XSPR(31,451,133), XSPR_MASK
, PPC403
, {RS
}},
3928 {"mtbr6", XSPR(31,451,134), XSPR_MASK
, PPC403
, {RS
}},
3929 {"mtbr7", XSPR(31,451,135), XSPR_MASK
, PPC403
, {RS
}},
3930 {"mtbear", XSPR(31,451,144), XSPR_MASK
, PPC403
, {RS
}},
3931 {"mtbesr", XSPR(31,451,145), XSPR_MASK
, PPC403
, {RS
}},
3932 {"mtiocr", XSPR(31,451,160), XSPR_MASK
, PPC403
, {RS
}},
3933 {"mtdmacr0", XSPR(31,451,192), XSPR_MASK
, PPC403
, {RS
}},
3934 {"mtdmact0", XSPR(31,451,193), XSPR_MASK
, PPC403
, {RS
}},
3935 {"mtdmada0", XSPR(31,451,194), XSPR_MASK
, PPC403
, {RS
}},
3936 {"mtdmasa0", XSPR(31,451,195), XSPR_MASK
, PPC403
, {RS
}},
3937 {"mtdmacc0", XSPR(31,451,196), XSPR_MASK
, PPC403
, {RS
}},
3938 {"mtdmacr1", XSPR(31,451,200), XSPR_MASK
, PPC403
, {RS
}},
3939 {"mtdmact1", XSPR(31,451,201), XSPR_MASK
, PPC403
, {RS
}},
3940 {"mtdmada1", XSPR(31,451,202), XSPR_MASK
, PPC403
, {RS
}},
3941 {"mtdmasa1", XSPR(31,451,203), XSPR_MASK
, PPC403
, {RS
}},
3942 {"mtdmacc1", XSPR(31,451,204), XSPR_MASK
, PPC403
, {RS
}},
3943 {"mtdmacr2", XSPR(31,451,208), XSPR_MASK
, PPC403
, {RS
}},
3944 {"mtdmact2", XSPR(31,451,209), XSPR_MASK
, PPC403
, {RS
}},
3945 {"mtdmada2", XSPR(31,451,210), XSPR_MASK
, PPC403
, {RS
}},
3946 {"mtdmasa2", XSPR(31,451,211), XSPR_MASK
, PPC403
, {RS
}},
3947 {"mtdmacc2", XSPR(31,451,212), XSPR_MASK
, PPC403
, {RS
}},
3948 {"mtdmacr3", XSPR(31,451,216), XSPR_MASK
, PPC403
, {RS
}},
3949 {"mtdmact3", XSPR(31,451,217), XSPR_MASK
, PPC403
, {RS
}},
3950 {"mtdmada3", XSPR(31,451,218), XSPR_MASK
, PPC403
, {RS
}},
3951 {"mtdmasa3", XSPR(31,451,219), XSPR_MASK
, PPC403
, {RS
}},
3952 {"mtdmacc3", XSPR(31,451,220), XSPR_MASK
, PPC403
, {RS
}},
3953 {"mtdmasr", XSPR(31,451,224), XSPR_MASK
, PPC403
, {RS
}},
3954 {"mtdcr", X(31,451), X_MASK
, PPC403
|BOOKE
, {SPR
, RS
}},
3956 {"dccci", X(31,454), XRT_MASK
, PPC403
|PPC440
, {RA
, RB
}},
3958 {"subfze64", XO(31,456,0,0), XORB_MASK
, BOOKE64
, {RT
, RA
}},
3960 {"divdu", XO(31,457,0,0), XO_MASK
, PPC64
, {RT
, RA
, RB
}},
3961 {"divdu.", XO(31,457,0,1), XO_MASK
, PPC64
, {RT
, RA
, RB
}},
3963 {"addze64", XO(31,458,0,0), XORB_MASK
, BOOKE64
, {RT
, RA
}},
3965 {"divwu", XO(31,459,0,0), XO_MASK
, PPC
, {RT
, RA
, RB
}},
3966 {"divwu.", XO(31,459,0,1), XO_MASK
, PPC
, {RT
, RA
, RB
}},
3968 {"mtpmr", X(31,462), X_MASK
, PPCPMR
, {PMR
, RS
}},
3970 {"mtmq", XSPR(31,467, 0), XSPR_MASK
, M601
, {RS
}},
3971 {"mtxer", XSPR(31,467, 1), XSPR_MASK
, COM
, {RS
}},
3972 {"mtlr", XSPR(31,467, 8), XSPR_MASK
, COM
, {RS
}},
3973 {"mtctr", XSPR(31,467, 9), XSPR_MASK
, COM
, {RS
}},
3974 {"mttid", XSPR(31,467, 17), XSPR_MASK
, POWER
, {RS
}},
3975 {"mtdsisr", XSPR(31,467, 18), XSPR_MASK
, COM
, {RS
}},
3976 {"mtdar", XSPR(31,467, 19), XSPR_MASK
, COM
, {RS
}},
3977 {"mtrtcu", XSPR(31,467, 20), XSPR_MASK
, COM
, {RS
}},
3978 {"mtrtcl", XSPR(31,467, 21), XSPR_MASK
, COM
, {RS
}},
3979 {"mtdec", XSPR(31,467, 22), XSPR_MASK
, COM
, {RS
}},
3980 {"mtsdr0", XSPR(31,467, 24), XSPR_MASK
, POWER
, {RS
}},
3981 {"mtsdr1", XSPR(31,467, 25), XSPR_MASK
, COM
, {RS
}},
3982 {"mtsrr0", XSPR(31,467, 26), XSPR_MASK
, COM
, {RS
}},
3983 {"mtsrr1", XSPR(31,467, 27), XSPR_MASK
, COM
, {RS
}},
3984 {"mtcfar", XSPR(31,467, 28), XSPR_MASK
, POWER6
, {RS
}},
3985 {"mtpid", XSPR(31,467, 48), XSPR_MASK
, BOOKE
, {RS
}},
3986 {"mtdecar", XSPR(31,467, 54), XSPR_MASK
, BOOKE
, {RS
}},
3987 {"mtcsrr0", XSPR(31,467, 58), XSPR_MASK
, BOOKE
, {RS
}},
3988 {"mtcsrr1", XSPR(31,467, 59), XSPR_MASK
, BOOKE
, {RS
}},
3989 {"mtdear", XSPR(31,467, 61), XSPR_MASK
, BOOKE
, {RS
}},
3990 {"mtesr", XSPR(31,467, 62), XSPR_MASK
, BOOKE
, {RS
}},
3991 {"mtivpr", XSPR(31,467, 63), XSPR_MASK
, BOOKE
, {RS
}},
3992 {"mtcmpa", XSPR(31,467,144), XSPR_MASK
, PPC860
, {RS
}},
3993 {"mtcmpb", XSPR(31,467,145), XSPR_MASK
, PPC860
, {RS
}},
3994 {"mtcmpc", XSPR(31,467,146), XSPR_MASK
, PPC860
, {RS
}},
3995 {"mtcmpd", XSPR(31,467,147), XSPR_MASK
, PPC860
, {RS
}},
3996 {"mticr", XSPR(31,467,148), XSPR_MASK
, PPC860
, {RS
}},
3997 {"mtder", XSPR(31,467,149), XSPR_MASK
, PPC860
, {RS
}},
3998 {"mtcounta", XSPR(31,467,150), XSPR_MASK
, PPC860
, {RS
}},
3999 {"mtcountb", XSPR(31,467,151), XSPR_MASK
, PPC860
, {RS
}},
4000 {"mtcmpe", XSPR(31,467,152), XSPR_MASK
, PPC860
, {RS
}},
4001 {"mtcmpf", XSPR(31,467,153), XSPR_MASK
, PPC860
, {RS
}},
4002 {"mtcmpg", XSPR(31,467,154), XSPR_MASK
, PPC860
, {RS
}},
4003 {"mtcmph", XSPR(31,467,155), XSPR_MASK
, PPC860
, {RS
}},
4004 {"mtlctrl1", XSPR(31,467,156), XSPR_MASK
, PPC860
, {RS
}},
4005 {"mtlctrl2", XSPR(31,467,157), XSPR_MASK
, PPC860
, {RS
}},
4006 {"mtictrl", XSPR(31,467,158), XSPR_MASK
, PPC860
, {RS
}},
4007 {"mtbar", XSPR(31,467,159), XSPR_MASK
, PPC860
, {RS
}},
4008 {"mtvrsave", XSPR(31,467,256), XSPR_MASK
, PPCVEC
, {RS
}},
4009 {"mtusprg0", XSPR(31,467,256), XSPR_MASK
, BOOKE
, {RS
}},
4010 {"mtsprg", XSPR(31,467,256), XSPRG_MASK
,PPC
, {SPRG
, RS
}},
4011 {"mtsprg0", XSPR(31,467,272), XSPR_MASK
, PPC
, {RS
}},
4012 {"mtsprg1", XSPR(31,467,273), XSPR_MASK
, PPC
, {RS
}},
4013 {"mtsprg2", XSPR(31,467,274), XSPR_MASK
, PPC
, {RS
}},
4014 {"mtsprg3", XSPR(31,467,275), XSPR_MASK
, PPC
, {RS
}},
4015 {"mtsprg4", XSPR(31,467,276), XSPR_MASK
, PPC405
|BOOKE
, {RS
}},
4016 {"mtsprg5", XSPR(31,467,277), XSPR_MASK
, PPC405
|BOOKE
, {RS
}},
4017 {"mtsprg6", XSPR(31,467,278), XSPR_MASK
, PPC405
|BOOKE
, {RS
}},
4018 {"mtsprg7", XSPR(31,467,279), XSPR_MASK
, PPC405
|BOOKE
, {RS
}},
4019 {"mtasr", XSPR(31,467,280), XSPR_MASK
, PPC64
, {RS
}},
4020 {"mtear", XSPR(31,467,282), XSPR_MASK
, PPC
, {RS
}},
4021 {"mttbl", XSPR(31,467,284), XSPR_MASK
, PPC
, {RS
}},
4022 {"mttbu", XSPR(31,467,285), XSPR_MASK
, PPC
, {RS
}},
4023 {"mtdbsr", XSPR(31,467,304), XSPR_MASK
, BOOKE
, {RS
}},
4024 {"mtdbcr0", XSPR(31,467,308), XSPR_MASK
, BOOKE
, {RS
}},
4025 {"mtdbcr1", XSPR(31,467,309), XSPR_MASK
, BOOKE
, {RS
}},
4026 {"mtdbcr2", XSPR(31,467,310), XSPR_MASK
, BOOKE
, {RS
}},
4027 {"mtiac1", XSPR(31,467,312), XSPR_MASK
, BOOKE
, {RS
}},
4028 {"mtiac2", XSPR(31,467,313), XSPR_MASK
, BOOKE
, {RS
}},
4029 {"mtiac3", XSPR(31,467,314), XSPR_MASK
, BOOKE
, {RS
}},
4030 {"mtiac4", XSPR(31,467,315), XSPR_MASK
, BOOKE
, {RS
}},
4031 {"mtdac1", XSPR(31,467,316), XSPR_MASK
, BOOKE
, {RS
}},
4032 {"mtdac2", XSPR(31,467,317), XSPR_MASK
, BOOKE
, {RS
}},
4033 {"mtdvc1", XSPR(31,467,318), XSPR_MASK
, BOOKE
, {RS
}},
4034 {"mtdvc2", XSPR(31,467,319), XSPR_MASK
, BOOKE
, {RS
}},
4035 {"mttsr", XSPR(31,467,336), XSPR_MASK
, BOOKE
, {RS
}},
4036 {"mttcr", XSPR(31,467,340), XSPR_MASK
, BOOKE
, {RS
}},
4037 {"mtivor0", XSPR(31,467,400), XSPR_MASK
, BOOKE
, {RS
}},
4038 {"mtivor1", XSPR(31,467,401), XSPR_MASK
, BOOKE
, {RS
}},
4039 {"mtivor2", XSPR(31,467,402), XSPR_MASK
, BOOKE
, {RS
}},
4040 {"mtivor3", XSPR(31,467,403), XSPR_MASK
, BOOKE
, {RS
}},
4041 {"mtivor4", XSPR(31,467,404), XSPR_MASK
, BOOKE
, {RS
}},
4042 {"mtivor5", XSPR(31,467,405), XSPR_MASK
, BOOKE
, {RS
}},
4043 {"mtivor6", XSPR(31,467,406), XSPR_MASK
, BOOKE
, {RS
}},
4044 {"mtivor7", XSPR(31,467,407), XSPR_MASK
, BOOKE
, {RS
}},
4045 {"mtivor8", XSPR(31,467,408), XSPR_MASK
, BOOKE
, {RS
}},
4046 {"mtivor9", XSPR(31,467,409), XSPR_MASK
, BOOKE
, {RS
}},
4047 {"mtivor10", XSPR(31,467,410), XSPR_MASK
, BOOKE
, {RS
}},
4048 {"mtivor11", XSPR(31,467,411), XSPR_MASK
, BOOKE
, {RS
}},
4049 {"mtivor12", XSPR(31,467,412), XSPR_MASK
, BOOKE
, {RS
}},
4050 {"mtivor13", XSPR(31,467,413), XSPR_MASK
, BOOKE
, {RS
}},
4051 {"mtivor14", XSPR(31,467,414), XSPR_MASK
, BOOKE
, {RS
}},
4052 {"mtivor15", XSPR(31,467,415), XSPR_MASK
, BOOKE
, {RS
}},
4053 {"mtspefscr", XSPR(31,467,512), XSPR_MASK
, PPCSPE
, {RS
}},
4054 {"mtbbear", XSPR(31,467,513), XSPR_MASK
, PPCBRLK
, {RS
}},
4055 {"mtbbtar", XSPR(31,467,514), XSPR_MASK
, PPCBRLK
, {RS
}},
4056 {"mtivor32", XSPR(31,467,528), XSPR_MASK
, PPCSPE
, {RS
}},
4057 {"mtibatu", XSPR(31,467,528), XSPRBAT_MASK
, PPC
, {SPRBAT
, RS
}},
4058 {"mtivor33", XSPR(31,467,529), XSPR_MASK
, PPCSPE
, {RS
}},
4059 {"mtibatl", XSPR(31,467,529), XSPRBAT_MASK
, PPC
, {SPRBAT
, RS
}},
4060 {"mtivor34", XSPR(31,467,530), XSPR_MASK
, PPCSPE
, {RS
}},
4061 {"mtivor35", XSPR(31,467,531), XSPR_MASK
, PPCPMR
, {RS
}},
4062 {"mtdbatu", XSPR(31,467,536), XSPRBAT_MASK
, PPC
, {SPRBAT
, RS
}},
4063 {"mtdbatl", XSPR(31,467,537), XSPRBAT_MASK
, PPC
, {SPRBAT
, RS
}},
4064 {"mtmcsrr0", XSPR(31,467,570), XSPR_MASK
, PPCRFMCI
, {RS
}},
4065 {"mtmcsrr1", XSPR(31,467,571), XSPR_MASK
, PPCRFMCI
, {RS
}},
4066 {"mtmcsr", XSPR(31,467,572), XSPR_MASK
, PPCRFMCI
, {RS
}},
4067 {"mtummcr0", XSPR(31,467,936), XSPR_MASK
, PPC750
, {RS
}},
4068 {"mtupmc1", XSPR(31,467,937), XSPR_MASK
, PPC750
, {RS
}},
4069 {"mtupmc2", XSPR(31,467,938), XSPR_MASK
, PPC750
, {RS
}},
4070 {"mtusia", XSPR(31,467,939), XSPR_MASK
, PPC750
, {RS
}},
4071 {"mtummcr1", XSPR(31,467,940), XSPR_MASK
, PPC750
, {RS
}},
4072 {"mtupmc3", XSPR(31,467,941), XSPR_MASK
, PPC750
, {RS
}},
4073 {"mtupmc4", XSPR(31,467,942), XSPR_MASK
, PPC750
, {RS
}},
4074 {"mtzpr", XSPR(31,467,944), XSPR_MASK
, PPC403
, {RS
}},
4075 {"mtpid", XSPR(31,467,945), XSPR_MASK
, PPC403
, {RS
}},
4076 {"mtccr0", XSPR(31,467,947), XSPR_MASK
, PPC405
, {RS
}},
4077 {"mtiac3", XSPR(31,467,948), XSPR_MASK
, PPC405
, {RS
}},
4078 {"mtiac4", XSPR(31,467,949), XSPR_MASK
, PPC405
, {RS
}},
4079 {"mtdvc1", XSPR(31,467,950), XSPR_MASK
, PPC405
, {RS
}},
4080 {"mtdvc2", XSPR(31,467,951), XSPR_MASK
, PPC405
, {RS
}},
4081 {"mtmmcr0", XSPR(31,467,952), XSPR_MASK
, PPC750
, {RS
}},
4082 {"mtpmc1", XSPR(31,467,953), XSPR_MASK
, PPC750
, {RS
}},
4083 {"mtsgr", XSPR(31,467,953), XSPR_MASK
, PPC403
, {RS
}},
4084 {"mtdcwr", XSPR(31,467,954), XSPR_MASK
, PPC403
, {RS
}},
4085 {"mtpmc2", XSPR(31,467,954), XSPR_MASK
, PPC750
, {RS
}},
4086 {"mtsia", XSPR(31,467,955), XSPR_MASK
, PPC750
, {RS
}},
4087 {"mtsler", XSPR(31,467,955), XSPR_MASK
, PPC405
, {RS
}},
4088 {"mtmmcr1", XSPR(31,467,956), XSPR_MASK
, PPC750
, {RS
}},
4089 {"mtsu0r", XSPR(31,467,956), XSPR_MASK
, PPC405
, {RS
}},
4090 {"mtdbcr1", XSPR(31,467,957), XSPR_MASK
, PPC405
, {RS
}},
4091 {"mtpmc3", XSPR(31,467,957), XSPR_MASK
, PPC750
, {RS
}},
4092 {"mtpmc4", XSPR(31,467,958), XSPR_MASK
, PPC750
, {RS
}},
4093 {"mticdbdr", XSPR(31,467,979), XSPR_MASK
, PPC403
, {RS
}},
4094 {"mtesr", XSPR(31,467,980), XSPR_MASK
, PPC403
, {RS
}},
4095 {"mtdear", XSPR(31,467,981), XSPR_MASK
, PPC403
, {RS
}},
4096 {"mtevpr", XSPR(31,467,982), XSPR_MASK
, PPC403
, {RS
}},
4097 {"mtcdbcr", XSPR(31,467,983), XSPR_MASK
, PPC403
, {RS
}},
4098 {"mttsr", XSPR(31,467,984), XSPR_MASK
, PPC403
, {RS
}},
4099 {"mttcr", XSPR(31,467,986), XSPR_MASK
, PPC403
, {RS
}},
4100 {"mtpit", XSPR(31,467,987), XSPR_MASK
, PPC403
, {RS
}},
4101 {"mttbhi", XSPR(31,467,988), XSPR_MASK
, PPC403
, {RS
}},
4102 {"mttblo", XSPR(31,467,989), XSPR_MASK
, PPC403
, {RS
}},
4103 {"mtsrr2", XSPR(31,467,990), XSPR_MASK
, PPC403
, {RS
}},
4104 {"mtsrr3", XSPR(31,467,991), XSPR_MASK
, PPC403
, {RS
}},
4105 {"mtdbsr", XSPR(31,467,1008), XSPR_MASK
, PPC403
, {RS
}},
4106 {"mtdbcr0", XSPR(31,467,1010), XSPR_MASK
, PPC405
, {RS
}},
4107 {"mtiac1", XSPR(31,467,1012), XSPR_MASK
, PPC403
, {RS
}},
4108 {"mtiac2", XSPR(31,467,1013), XSPR_MASK
, PPC403
, {RS
}},
4109 {"mtdac1", XSPR(31,467,1014), XSPR_MASK
, PPC403
, {RS
}},
4110 {"mtdac2", XSPR(31,467,1015), XSPR_MASK
, PPC403
, {RS
}},
4111 {"mtl2cr", XSPR(31,467,1017), XSPR_MASK
, PPC750
, {RS
}},
4112 {"mtdccr", XSPR(31,467,1018), XSPR_MASK
, PPC403
, {RS
}},
4113 {"mticcr", XSPR(31,467,1019), XSPR_MASK
, PPC403
, {RS
}},
4114 {"mtictc", XSPR(31,467,1019), XSPR_MASK
, PPC750
, {RS
}},
4115 {"mtpbl1", XSPR(31,467,1020), XSPR_MASK
, PPC403
, {RS
}},
4116 {"mtthrm1", XSPR(31,467,1020), XSPR_MASK
, PPC750
, {RS
}},
4117 {"mtpbu1", XSPR(31,467,1021), XSPR_MASK
, PPC403
, {RS
}},
4118 {"mtthrm2", XSPR(31,467,1021), XSPR_MASK
, PPC750
, {RS
}},
4119 {"mtpbl2", XSPR(31,467,1022), XSPR_MASK
, PPC403
, {RS
}},
4120 {"mtthrm3", XSPR(31,467,1022), XSPR_MASK
, PPC750
, {RS
}},
4121 {"mtpbu2", XSPR(31,467,1023), XSPR_MASK
, PPC403
, {RS
}},
4122 {"mtspr", X(31,467), X_MASK
, COM
, {SPR
, RS
}},
4124 {"dcbi", X(31,470), XRT_MASK
, PPC
, {RA
, RB
}},
4126 {"nand", XRC(31,476,0), X_MASK
, COM
, {RA
, RS
, RB
}},
4127 {"nand.", XRC(31,476,1), X_MASK
, COM
, {RA
, RS
, RB
}},
4129 {"dcbie", X(31,478), XRT_MASK
, BOOKE64
, {RA
, RB
}},
4131 {"dsn", X(31,483), XRT_MASK
, E500MC
, {RA
, RB
}},
4133 {"dcread", X(31,486), X_MASK
, PPC403
|PPC440
, {RT
, RA
, RB
}},
4135 {"icbtls", X(31,486), X_MASK
, PPCCHLK
, {CT
, RA
, RB
}},
4137 {"stvxl", X(31,487), X_MASK
, PPCVEC
, {VS
, RA
, RB
}},
4139 {"nabs", XO(31,488,0,0), XORB_MASK
, M601
, {RT
, RA
}},
4140 {"subfme64", XO(31,488,0,0), XORB_MASK
, BOOKE64
, {RT
, RA
}},
4141 {"nabs.", XO(31,488,0,1), XORB_MASK
, M601
, {RT
, RA
}},
4143 {"divd", XO(31,489,0,0), XO_MASK
, PPC64
, {RT
, RA
, RB
}},
4144 {"divd.", XO(31,489,0,1), XO_MASK
, PPC64
, {RT
, RA
, RB
}},
4146 {"addme64", XO(31,490,0,0), XORB_MASK
, BOOKE64
, {RT
, RA
}},
4148 {"divw", XO(31,491,0,0), XO_MASK
, PPC
, {RT
, RA
, RB
}},
4149 {"divw.", XO(31,491,0,1), XO_MASK
, PPC
, {RT
, RA
, RB
}},
4151 {"icbtlse", X(31,494), X_MASK
, PPCCHLK64
, {CT
, RA
, RB
}},
4153 {"slbia", X(31,498), 0xffffffff, PPC64
, {0}},
4155 {"cli", X(31,502), XRB_MASK
, POWER
, {RT
, RA
}},
4157 {"cmpb", X(31,508), X_MASK
, POWER6
, {RA
, RS
, RB
}},
4159 {"stdcxe.", XRC(31,511,1), X_MASK
, BOOKE64
, {RS
, RA
, RB
}},
4161 {"mcrxr", X(31,512), XRARB_MASK
|(3<<21), COM
, {BF
}},
4163 {"lbdx", X(31,515), X_MASK
, E500MC
, {RT
, RA
, RB
}},
4165 {"bblels", X(31,518), X_MASK
, PPCBRLK
, {0}},
4167 {"lvlx", X(31,519), X_MASK
, CELL
, {VD
, RA0
, RB
}},
4168 {"lbfcmux", APU(31,519,0), APU_MASK
, PPC405
, {FCRT
, RA
, RB
}},
4170 {"subfco", XO(31,8,1,0), XO_MASK
, PPCCOM
, {RT
, RA
, RB
}},
4171 {"sfo", XO(31,8,1,0), XO_MASK
, PWRCOM
, {RT
, RA
, RB
}},
4172 {"subco", XO(31,8,1,0), XO_MASK
, PPC
, {RT
, RB
, RA
}},
4173 {"subfco.", XO(31,8,1,1), XO_MASK
, PPCCOM
, {RT
, RA
, RB
}},
4174 {"sfo.", XO(31,8,1,1), XO_MASK
, PWRCOM
, {RT
, RA
, RB
}},
4175 {"subco.", XO(31,8,1,1), XO_MASK
, PPC
, {RT
, RB
, RA
}},
4177 {"addco", XO(31,10,1,0), XO_MASK
, PPCCOM
, {RT
, RA
, RB
}},
4178 {"ao", XO(31,10,1,0), XO_MASK
, PWRCOM
, {RT
, RA
, RB
}},
4179 {"addco.", XO(31,10,1,1), XO_MASK
, PPCCOM
, {RT
, RA
, RB
}},
4180 {"ao.", XO(31,10,1,1), XO_MASK
, PWRCOM
, {RT
, RA
, RB
}},
4182 {"clcs", X(31,531), XRB_MASK
, M601
, {RT
, RA
}},
4184 {"ldbrx", X(31,532), X_MASK
, CELL
, {RT
, RA0
, RB
}},
4186 {"lswx", X(31,533), X_MASK
, PPCCOM
, {RT
, RA0
, RB
}},
4187 {"lsx", X(31,533), X_MASK
, PWRCOM
, {RT
, RA
, RB
}},
4189 {"lwbrx", X(31,534), X_MASK
, PPCCOM
, {RT
, RA0
, RB
}},
4190 {"lbrx", X(31,534), X_MASK
, PWRCOM
, {RT
, RA
, RB
}},
4192 {"lfsx", X(31,535), X_MASK
, COM
, {FRT
, RA0
, RB
}},
4194 {"srw", XRC(31,536,0), X_MASK
, PPCCOM
, {RA
, RS
, RB
}},
4195 {"sr", XRC(31,536,0), X_MASK
, PWRCOM
, {RA
, RS
, RB
}},
4196 {"srw.", XRC(31,536,1), X_MASK
, PPCCOM
, {RA
, RS
, RB
}},
4197 {"sr.", XRC(31,536,1), X_MASK
, PWRCOM
, {RA
, RS
, RB
}},
4199 {"rrib", XRC(31,537,0), X_MASK
, M601
, {RA
, RS
, RB
}},
4200 {"rrib.", XRC(31,537,1), X_MASK
, M601
, {RA
, RS
, RB
}},
4202 {"srd", XRC(31,539,0), X_MASK
, PPC64
, {RA
, RS
, RB
}},
4203 {"srd.", XRC(31,539,1), X_MASK
, PPC64
, {RA
, RS
, RB
}},
4205 {"maskir", XRC(31,541,0), X_MASK
, M601
, {RA
, RS
, RB
}},
4206 {"maskir.", XRC(31,541,1), X_MASK
, M601
, {RA
, RS
, RB
}},
4208 {"lwbrxe", X(31,542), X_MASK
, BOOKE64
, {RT
, RA0
, RB
}},
4210 {"lfsxe", X(31,543), X_MASK
, BOOKE64
, {FRT
, RA0
, RB
}},
4212 {"mcrxr64", X(31,544), XRARB_MASK
|(3<<21), BOOKE64
, {BF
}},
4214 {"lhdx", X(31,547), X_MASK
, E500MC
, {RT
, RA
, RB
}},
4216 {"bbelr", X(31,550), X_MASK
, PPCBRLK
, {0}},
4218 {"lvrx", X(31,551), X_MASK
, CELL
, {VD
, RA0
, RB
}},
4219 {"lhfcmux", APU(31,551,0), APU_MASK
, PPC405
, {FCRT
, RA
, RB
}},
4221 {"subfo", XO(31,40,1,0), XO_MASK
, PPC
, {RT
, RA
, RB
}},
4222 {"subo", XO(31,40,1,0), XO_MASK
, PPC
, {RT
, RB
, RA
}},
4223 {"subfo.", XO(31,40,1,1), XO_MASK
, PPC
, {RT
, RA
, RB
}},
4224 {"subo.", XO(31,40,1,1), XO_MASK
, PPC
, {RT
, RB
, RA
}},
4226 {"tlbsync", X(31,566), 0xffffffff, PPC
, {0}},
4228 {"lfsux", X(31,567), X_MASK
, COM
, {FRT
, RAS
, RB
}},
4230 {"lfsuxe", X(31,575), X_MASK
, BOOKE64
, {FRT
, RAS
, RB
}},
4232 {"lwdx", X(31,579), X_MASK
, E500MC
, {RT
, RA
, RB
}},
4234 {"lwfcmux", APU(31,583,0), APU_MASK
, PPC405
, {FCRT
, RA
, RB
}},
4236 {"mfsr", X(31,595), XRB_MASK
|(1<<20), COM32
, {RT
, SR
}},
4238 {"lswi", X(31,597), X_MASK
, PPCCOM
, {RT
, RA0
, NB
}},
4239 {"lsi", X(31,597), X_MASK
, PWRCOM
, {RT
, RA0
, NB
}},
4241 {"msync", X(31,598), 0xffffffff, BOOKE
, {0}},
4242 {"lwsync", XSYNC(31,598,1), 0xffffffff, PPC
, {0}},
4243 {"ptesync", XSYNC(31,598,2), 0xffffffff, PPC64
, {0}},
4244 {"sync", X(31,598), XSYNC_MASK
, PPCCOM
, {LS
}},
4245 {"dcs", X(31,598), 0xffffffff, PWRCOM
, {0}},
4247 {"lfdx", X(31,599), X_MASK
, COM
, {FRT
, RA0
, RB
}},
4249 {"lfdxe", X(31,607), X_MASK
, BOOKE64
, {FRT
, RA0
, RB
}},
4250 {"lfdepx", X(31,607), X_MASK
, E500MC
, {RT
, RA
, RB
}},
4251 {"mffgpr", XRC(31,607,0), XRA_MASK
, POWER6
, {FRT
, RB
}},
4253 {"lddx", X(31,611), X_MASK
, E500MC
, {RT
, RA
, RB
}},
4255 {"lqfcmux", APU(31,615,0), APU_MASK
, PPC405
, {FCRT
, RA
, RB
}},
4257 {"nego", XO(31,104,1,0), XORB_MASK
, COM
, {RT
, RA
}},
4258 {"nego.", XO(31,104,1,1), XORB_MASK
, COM
, {RT
, RA
}},
4260 {"mulo", XO(31,107,1,0), XO_MASK
, M601
, {RT
, RA
, RB
}},
4261 {"mulo.", XO(31,107,1,1), XO_MASK
, M601
, {RT
, RA
, RB
}},
4263 {"mfsri", X(31,627), X_MASK
, PWRCOM
, {RT
, RA
, RB
}},
4265 {"dclst", X(31,630), XRB_MASK
, PWRCOM
, {RS
, RA
}},
4267 {"lfdux", X(31,631), X_MASK
, COM
, {FRT
, RAS
, RB
}},
4269 {"lfduxe", X(31,639), X_MASK
, BOOKE64
, {FRT
, RAS
, RB
}},
4271 {"stbdx", X(31,643), X_MASK
, E500MC
, {RS
, RA
, RB
}},
4273 {"stvlx", X(31,647), X_MASK
, CELL
, {VS
, RA0
, RB
}},
4274 {"stbfcmux", APU(31,647,0), APU_MASK
, PPC405
, {FCRT
, RA
, RB
}},
4276 {"subfeo", XO(31,136,1,0), XO_MASK
, PPCCOM
, {RT
, RA
, RB
}},
4277 {"sfeo", XO(31,136,1,0), XO_MASK
, PWRCOM
, {RT
, RA
, RB
}},
4278 {"subfeo.", XO(31,136,1,1), XO_MASK
, PPCCOM
, {RT
, RA
, RB
}},
4279 {"sfeo.", XO(31,136,1,1), XO_MASK
, PWRCOM
, {RT
, RA
, RB
}},
4281 {"addeo", XO(31,138,1,0), XO_MASK
, PPCCOM
, {RT
, RA
, RB
}},
4282 {"aeo", XO(31,138,1,0), XO_MASK
, PWRCOM
, {RT
, RA
, RB
}},
4283 {"addeo.", XO(31,138,1,1), XO_MASK
, PPCCOM
, {RT
, RA
, RB
}},
4284 {"aeo.", XO(31,138,1,1), XO_MASK
, PWRCOM
, {RT
, RA
, RB
}},
4286 {"mfsrin", X(31,659), XRA_MASK
, PPC32
, {RT
, RB
}},
4288 {"stdbrx", X(31,660), X_MASK
, CELL
, {RS
, RA0
, RB
}},
4290 {"stswx", X(31,661), X_MASK
, PPCCOM
, {RS
, RA0
, RB
}},
4291 {"stsx", X(31,661), X_MASK
, PWRCOM
, {RS
, RA0
, RB
}},
4293 {"stwbrx", X(31,662), X_MASK
, PPCCOM
, {RS
, RA0
, RB
}},
4294 {"stbrx", X(31,662), X_MASK
, PWRCOM
, {RS
, RA0
, RB
}},
4296 {"stfsx", X(31,663), X_MASK
, COM
, {FRS
, RA0
, RB
}},
4298 {"srq", XRC(31,664,0), X_MASK
, M601
, {RA
, RS
, RB
}},
4299 {"srq.", XRC(31,664,1), X_MASK
, M601
, {RA
, RS
, RB
}},
4301 {"sre", XRC(31,665,0), X_MASK
, M601
, {RA
, RS
, RB
}},
4302 {"sre.", XRC(31,665,1), X_MASK
, M601
, {RA
, RS
, RB
}},
4304 {"stwbrxe", X(31,670), X_MASK
, BOOKE64
, {RS
, RA0
, RB
}},
4306 {"stfsxe", X(31,671), X_MASK
, BOOKE64
, {FRS
, RA0
, RB
}},
4308 {"sthdx", X(31,675), X_MASK
, E500MC
, {RS
, RA
, RB
}},
4310 {"stvrx", X(31,679), X_MASK
, CELL
, {VS
, RA0
, RB
}},
4311 {"sthfcmux", APU(31,679,0), APU_MASK
, PPC405
, {FCRT
, RA
, RB
}},
4313 {"stfsux", X(31,695), X_MASK
, COM
, {FRS
, RAS
, RB
}},
4315 {"sriq", XRC(31,696,0), X_MASK
, M601
, {RA
, RS
, SH
}},
4316 {"sriq.", XRC(31,696,1), X_MASK
, M601
, {RA
, RS
, SH
}},
4318 {"stfsuxe", X(31,703), X_MASK
, BOOKE64
, {FRS
, RAS
, RB
}},
4320 {"stwdx", X(31,707), X_MASK
, E500MC
, {RS
, RA
, RB
}},
4322 {"stwfcmux", APU(31,711,0), APU_MASK
, PPC405
, {FCRT
, RA
, RB
}},
4324 {"subfzeo", XO(31,200,1,0), XORB_MASK
, PPCCOM
, {RT
, RA
}},
4325 {"sfzeo", XO(31,200,1,0), XORB_MASK
, PWRCOM
, {RT
, RA
}},
4326 {"subfzeo.", XO(31,200,1,1), XORB_MASK
, PPCCOM
, {RT
, RA
}},
4327 {"sfzeo.", XO(31,200,1,1), XORB_MASK
, PWRCOM
, {RT
, RA
}},
4329 {"addzeo", XO(31,202,1,0), XORB_MASK
, PPCCOM
, {RT
, RA
}},
4330 {"azeo", XO(31,202,1,0), XORB_MASK
, PWRCOM
, {RT
, RA
}},
4331 {"addzeo.", XO(31,202,1,1), XORB_MASK
, PPCCOM
, {RT
, RA
}},
4332 {"azeo.", XO(31,202,1,1), XORB_MASK
, PWRCOM
, {RT
, RA
}},
4334 {"stswi", X(31,725), X_MASK
, PPCCOM
, {RS
, RA0
, NB
}},
4335 {"stsi", X(31,725), X_MASK
, PWRCOM
, {RS
, RA0
, NB
}},
4337 {"stfdx", X(31,727), X_MASK
, COM
, {FRS
, RA0
, RB
}},
4339 {"srlq", XRC(31,728,0), X_MASK
, M601
, {RA
, RS
, RB
}},
4340 {"srlq.", XRC(31,728,1), X_MASK
, M601
, {RA
, RS
, RB
}},
4342 {"sreq", XRC(31,729,0), X_MASK
, M601
, {RA
, RS
, RB
}},
4343 {"sreq.", XRC(31,729,1), X_MASK
, M601
, {RA
, RS
, RB
}},
4345 {"stfdxe", X(31,735), X_MASK
, BOOKE64
, {FRS
, RA0
, RB
}},
4346 {"stfdepx", X(31,735), X_MASK
, E500MC
, {RS
, RA
, RB
}},
4347 {"mftgpr", XRC(31,735,0), XRA_MASK
, POWER6
, {RT
, FRB
}},
4349 {"stddx", X(31,739), X_MASK
, E500MC
, {RS
, RA
, RB
}},
4351 {"stqfcmux", APU(31,743,0), APU_MASK
, PPC405
, {FCRT
, RA
, RB
}},
4353 {"subfmeo", XO(31,232,1,0), XORB_MASK
, PPCCOM
, {RT
, RA
}},
4354 {"sfmeo", XO(31,232,1,0), XORB_MASK
, PWRCOM
, {RT
, RA
}},
4355 {"subfmeo.", XO(31,232,1,1), XORB_MASK
, PPCCOM
, {RT
, RA
}},
4356 {"sfmeo.", XO(31,232,1,1), XORB_MASK
, PWRCOM
, {RT
, RA
}},
4358 {"mulldo", XO(31,233,1,0), XO_MASK
, PPC64
, {RT
, RA
, RB
}},
4359 {"mulldo.", XO(31,233,1,1), XO_MASK
, PPC64
, {RT
, RA
, RB
}},
4361 {"addmeo", XO(31,234,1,0), XORB_MASK
, PPCCOM
, {RT
, RA
}},
4362 {"ameo", XO(31,234,1,0), XORB_MASK
, PWRCOM
, {RT
, RA
}},
4363 {"addmeo.", XO(31,234,1,1), XORB_MASK
, PPCCOM
, {RT
, RA
}},
4364 {"ameo.", XO(31,234,1,1), XORB_MASK
, PWRCOM
, {RT
, RA
}},
4366 {"mullwo", XO(31,235,1,0), XO_MASK
, PPCCOM
, {RT
, RA
, RB
}},
4367 {"mulso", XO(31,235,1,0), XO_MASK
, PWRCOM
, {RT
, RA
, RB
}},
4368 {"mullwo.", XO(31,235,1,1), XO_MASK
, PPCCOM
, {RT
, RA
, RB
}},
4369 {"mulso.", XO(31,235,1,1), XO_MASK
, PWRCOM
, {RT
, RA
, RB
}},
4371 {"dcba", X(31,758), XRT_MASK
, PPC405
|PPC7450
|BOOKE
, {RA
, RB
}},
4372 {"dcbal", XOPL(31,758,1), XRT_MASK
, E500MC
, {RA
, RB
}},
4374 {"stfdux", X(31,759), X_MASK
, COM
, {FRS
, RAS
, RB
}},
4376 {"srliq", XRC(31,760,0), X_MASK
, M601
, {RA
, RS
, SH
}},
4377 {"srliq.", XRC(31,760,1), X_MASK
, M601
, {RA
, RS
, SH
}},
4379 {"dcbae", X(31,766), XRT_MASK
, BOOKE64
, {RA
, RB
}},
4381 {"stfduxe", X(31,767), X_MASK
, BOOKE64
, {FRS
, RAS
, RB
}},
4383 {"lvlxl", X(31,775), X_MASK
, CELL
, {VD
, RA0
, RB
}},
4384 {"ldfcmux", APU(31,775,0), APU_MASK
, PPC405
, {FCRT
, RA
, RB
}},
4386 {"dozo", XO(31,264,1,0), XO_MASK
, M601
, {RT
, RA
, RB
}},
4387 {"dozo.", XO(31,264,1,1), XO_MASK
, M601
, {RT
, RA
, RB
}},
4389 {"addo", XO(31,266,1,0), XO_MASK
, PPCCOM
, {RT
, RA
, RB
}},
4390 {"caxo", XO(31,266,1,0), XO_MASK
, PWRCOM
, {RT
, RA
, RB
}},
4391 {"addo.", XO(31,266,1,1), XO_MASK
, PPCCOM
, {RT
, RA
, RB
}},
4392 {"caxo.", XO(31,266,1,1), XO_MASK
, PWRCOM
, {RT
, RA
, RB
}},
4394 {"tlbivax", X(31,786), XRT_MASK
, BOOKE
, {RA
, RB
}},
4395 {"tlbivaxe", X(31,787), XRT_MASK
, BOOKE64
, {RA
, RB
}},
4396 {"tlbilx", X(31,787), X_MASK
, E500MC
, {T
, RA0
, RB
}},
4397 {"tlbilxlpid", XTO(31,787,0), XTO_MASK
, E500MC
, {0}},
4398 {"tlbilxpid", XTO(31,787,1), XTO_MASK
, E500MC
, {0}},
4399 {"tlbilxva", XTO(31,787,3), XTO_MASK
, E500MC
, {RA0
, RB
}},
4401 {"lwzcix", X(31,789), X_MASK
, POWER6
, {RT
, RA0
, RB
}},
4403 {"lhbrx", X(31,790), X_MASK
, COM
, {RT
, RA0
, RB
}},
4405 {"lfqx", X(31,791), X_MASK
, POWER2
, {FRT
, RA
, RB
}},
4406 {"lfdpx", X(31,791), X_MASK
, POWER6
, {FRT
, RA
, RB
}},
4408 {"sraw", XRC(31,792,0), X_MASK
, PPCCOM
, {RA
, RS
, RB
}},
4409 {"sra", XRC(31,792,0), X_MASK
, PWRCOM
, {RA
, RS
, RB
}},
4410 {"sraw.", XRC(31,792,1), X_MASK
, PPCCOM
, {RA
, RS
, RB
}},
4411 {"sra.", XRC(31,792,1), X_MASK
, PWRCOM
, {RA
, RS
, RB
}},
4413 {"srad", XRC(31,794,0), X_MASK
, PPC64
, {RA
, RS
, RB
}},
4414 {"srad.", XRC(31,794,1), X_MASK
, PPC64
, {RA
, RS
, RB
}},
4416 {"lhbrxe", X(31,798), X_MASK
, BOOKE64
, {RT
, RA0
, RB
}},
4418 {"ldxe", X(31,799), X_MASK
, BOOKE64
, {RT
, RA0
, RB
}},
4420 {"lfddx", X(31,803), X_MASK
, E500MC
, {FRT
, RA
, RB
}},
4422 {"lvrxl", X(31,807), X_MASK
, CELL
, {VD
, RA0
, RB
}},
4424 {"rac", X(31,818), X_MASK
, PWRCOM
, {RT
, RA
, RB
}},
4426 {"lhzcix", X(31,821), X_MASK
, POWER6
, {RT
, RA0
, RB
}},
4428 {"dss", XDSS(31,822,0), XDSS_MASK
, PPCVEC
, {STRM
}},
4430 {"lfqux", X(31,823), X_MASK
, POWER2
, {FRT
, RA
, RB
}},
4432 {"srawi", XRC(31,824,0), X_MASK
, PPCCOM
, {RA
, RS
, SH
}},
4433 {"srai", XRC(31,824,0), X_MASK
, PWRCOM
, {RA
, RS
, SH
}},
4434 {"srawi.", XRC(31,824,1), X_MASK
, PPCCOM
, {RA
, RS
, SH
}},
4435 {"srai.", XRC(31,824,1), X_MASK
, PWRCOM
, {RA
, RS
, SH
}},
4437 {"sradi", XS(31,413,0), XS_MASK
, PPC64
, {RA
, RS
, SH6
}},
4438 {"sradi.", XS(31,413,1), XS_MASK
, PPC64
, {RA
, RS
, SH6
}},
4440 {"divo", XO(31,331,1,0), XO_MASK
, M601
, {RT
, RA
, RB
}},
4441 {"divo.", XO(31,331,1,1), XO_MASK
, M601
, {RT
, RA
, RB
}},
4442 {"lduxe", X(31,831), X_MASK
, BOOKE64
, {RT
, RA0
, RB
}},
4444 {"slbmfev", X(31,851), XRA_MASK
, PPC64
, {RT
, RB
}},
4446 {"lbzcix", X(31,853), X_MASK
, POWER6
, {RT
, RA0
, RB
}},
4448 {"mbar", X(31,854), X_MASK
, BOOKE
, {MO
}},
4449 {"eieio", X(31,854), 0xffffffff, PPC
, {0}},
4451 {"lfiwax", X(31,855), X_MASK
, POWER6
, {FRT
, RA0
, RB
}},
4453 {"abso", XO(31,360,1,0), XORB_MASK
, M601
, {RT
, RA
}},
4454 {"abso.", XO(31,360,1,1), XORB_MASK
, M601
, {RT
, RA
}},
4456 {"divso", XO(31,363,1,0), XO_MASK
, M601
, {RT
, RA
, RB
}},
4457 {"divso.", XO(31,363,1,1), XO_MASK
, M601
, {RT
, RA
, RB
}},
4459 {"ldcix", X(31,885), X_MASK
, POWER6
, {RT
, RA0
, RB
}},
4461 {"stvlxl", X(31,903), X_MASK
, CELL
, {VS
, RA0
, RB
}},
4462 {"stdfcmux", APU(31,903,0), APU_MASK
, PPC405
, {FCRT
, RA
, RB
}},
4464 {"subfe64o", XO(31,392,1,0), XO_MASK
, BOOKE64
, {RT
, RA
, RB
}},
4466 {"adde64o", XO(31,394,1,0), XO_MASK
, BOOKE64
, {RT
, RA
, RB
}},
4468 {"tlbsx", XRC(31,914,0), X_MASK
, PPC403
|BOOKE
, {RTO
, RA
, RB
}},
4469 {"tlbsx.", XRC(31,914,1), X_MASK
, PPC403
|BOOKE
, {RTO
, RA
, RB
}},
4471 {"tlbsxe", XRC(31,915,0), X_MASK
, BOOKE64
, {RTO
, RA
, RB
}},
4472 {"tlbsxe.", XRC(31,915,1), X_MASK
, BOOKE64
, {RTO
, RA
, RB
}},
4473 {"slbmfee", X(31,915), XRA_MASK
, PPC64
, {RT
, RB
}},
4475 {"stwcix", X(31,917), X_MASK
, POWER6
, {RS
, RA0
, RB
}},
4477 {"sthbrx", X(31,918), X_MASK
, COM
, {RS
, RA0
, RB
}},
4479 {"stfqx", X(31,919), X_MASK
, POWER2
, {FRS
, RA
, RB
}},
4480 {"stfdpx", X(31,919), X_MASK
, POWER6
, {FRS
, RA
, RB
}},
4482 {"sraq", XRC(31,920,0), X_MASK
, M601
, {RA
, RS
, RB
}},
4483 {"sraq.", XRC(31,920,1), X_MASK
, M601
, {RA
, RS
, RB
}},
4485 {"srea", XRC(31,921,0), X_MASK
, M601
, {RA
, RS
, RB
}},
4486 {"srea.", XRC(31,921,1), X_MASK
, M601
, {RA
, RS
, RB
}},
4488 {"extsh", XRC(31,922,0), XRB_MASK
, PPCCOM
, {RA
, RS
}},
4489 {"exts", XRC(31,922,0), XRB_MASK
, PWRCOM
, {RA
, RS
}},
4490 {"extsh.", XRC(31,922,1), XRB_MASK
, PPCCOM
, {RA
, RS
}},
4491 {"exts.", XRC(31,922,1), XRB_MASK
, PWRCOM
, {RA
, RS
}},
4493 {"sthbrxe", X(31,926), X_MASK
, BOOKE64
, {RS
, RA0
, RB
}},
4495 {"stdxe", X(31,927), X_MASK
, BOOKE64
, {RS
, RA0
, RB
}},
4497 {"stfddx", X(31,931), X_MASK
, E500MC
, {FRS
, RA
, RB
}},
4499 {"stvrxl", X(31,935), X_MASK
, CELL
, {VS
, RA0
, RB
}},
4501 {"tlbrehi", XTLB(31,946,0), XTLB_MASK
, PPC403
, {RT
, RA
}},
4502 {"tlbrelo", XTLB(31,946,1), XTLB_MASK
, PPC403
, {RT
, RA
}},
4503 {"tlbre", X(31,946), X_MASK
, PPC403
|BOOKE
, {RSO
, RAOPT
, SHO
}},
4505 {"sthcix", X(31,949), X_MASK
, POWER6
, {RS
, RA0
, RB
}},
4507 {"stfqux", X(31,951), X_MASK
, POWER2
, {FRS
, RA
, RB
}},
4509 {"sraiq", XRC(31,952,0), X_MASK
, M601
, {RA
, RS
, SH
}},
4510 {"sraiq.", XRC(31,952,1), X_MASK
, M601
, {RA
, RS
, SH
}},
4512 {"extsb", XRC(31,954,0), XRB_MASK
, PPC
, {RA
, RS
}},
4513 {"extsb.", XRC(31,954,1), XRB_MASK
, PPC
, {RA
, RS
}},
4515 {"stduxe", X(31,959), X_MASK
, BOOKE64
, {RS
, RAS
, RB
}},
4517 {"iccci", X(31,966), XRT_MASK
, PPC403
|PPC440
, {RA
, RB
}},
4519 {"subfze64o", XO(31,456,1,0), XORB_MASK
, BOOKE64
, {RT
, RA
}},
4521 {"divduo", XO(31,457,1,0), XO_MASK
, PPC64
, {RT
, RA
, RB
}},
4522 {"divduo.", XO(31,457,1,1), XO_MASK
, PPC64
, {RT
, RA
, RB
}},
4524 {"addze64o", XO(31,458,1,0), XORB_MASK
, BOOKE64
, {RT
, RA
}},
4526 {"divwuo", XO(31,459,1,0), XO_MASK
, PPC
, {RT
, RA
, RB
}},
4527 {"divwuo.", XO(31,459,1,1), XO_MASK
, PPC
, {RT
, RA
, RB
}},
4529 {"tlbwehi", XTLB(31,978,0), XTLB_MASK
, PPC403
, {RT
, RA
}},
4530 {"tlbwelo", XTLB(31,978,1), XTLB_MASK
, PPC403
, {RT
, RA
}},
4531 {"tlbwe", X(31,978), X_MASK
, PPC403
|BOOKE
, {RSO
, RAOPT
, SHO
}},
4532 {"tlbld", X(31,978), XRTRA_MASK
, PPC
, {RB
}},
4534 {"stbcix", X(31,981), X_MASK
, POWER6
, {RS
, RA0
, RB
}},
4536 {"icbi", X(31,982), XRT_MASK
, PPC
, {RA
, RB
}},
4538 {"stfiwx", X(31,983), X_MASK
, PPC
, {FRS
, RA0
, RB
}},
4540 {"extsw", XRC(31,986,0), XRB_MASK
, PPC64
|BOOKE64
, {RA
, RS
}},
4541 {"extsw.", XRC(31,986,1), XRB_MASK
, PPC64
, {RA
, RS
}},
4543 {"icbie", X(31,990), XRT_MASK
, BOOKE64
, {RA
, RB
}},
4544 {"stfiwxe", X(31,991), X_MASK
, BOOKE64
, {FRS
, RA0
, RB
}},
4546 {"icbiep", XRT(31,991,0), XRT_MASK
, E500MC
, {RA
, RB
}},
4548 {"icread", X(31,998), XRT_MASK
, PPC403
|PPC440
, {RA
, RB
}},
4550 {"nabso", XO(31,488,1,0), XORB_MASK
, M601
, {RT
, RA
}},
4551 {"subfme64o", XO(31,488,1,0), XORB_MASK
, BOOKE64
, {RT
, RA
}},
4552 {"nabso.", XO(31,488,1,1), XORB_MASK
, M601
, {RT
, RA
}},
4554 {"divdo", XO(31,489,1,0), XO_MASK
, PPC64
, {RT
, RA
, RB
}},
4555 {"divdo.", XO(31,489,1,1), XO_MASK
, PPC64
, {RT
, RA
, RB
}},
4557 {"addme64o", XO(31,490,1,0), XORB_MASK
, BOOKE64
, {RT
, RA
}},
4559 {"divwo", XO(31,491,1,0), XO_MASK
, PPC
, {RT
, RA
, RB
}},
4560 {"divwo.", XO(31,491,1,1), XO_MASK
, PPC
, {RT
, RA
, RB
}},
4562 {"tlbli", X(31,1010), XRTRA_MASK
, PPC
, {RB
}},
4564 {"stdcix", X(31,1013), X_MASK
, POWER6
, {RS
, RA0
, RB
}},
4566 {"dcbz", X(31,1014), XRT_MASK
, PPC
, {RA
, RB
}},
4567 {"dclz", X(31,1014), XRT_MASK
, PPC
, {RA
, RB
}},
4569 {"dcbze", X(31,1022), XRT_MASK
, BOOKE64
, {RA
, RB
}},
4570 {"dcbzep", XRT(31,1023,0), XRT_MASK
, E500MC
, {RA
, RB
}},
4572 {"dcbzl", XOPL(31,1014,1), XRT_MASK
, POWER4
, {RA
, RB
}},
4573 {"dcbzl", XOPL(31,1014,1), XRT_MASK
, NOPOWER4
|E500MC
,{RA
, RB
}},
4575 {"cctpl", 0x7c210b78, 0xffffffff, CELL
, {0}},
4576 {"cctpm", 0x7c421378, 0xffffffff, CELL
, {0}},
4577 {"cctph", 0x7c631b78, 0xffffffff, CELL
, {0}},
4579 {"dstt", XDSS(31,342,1), XDSS_MASK
, PPCVEC
, {RA
, RB
, STRM
}},
4580 {"dststt", XDSS(31,374,1), XDSS_MASK
, PPCVEC
, {RA
, RB
, STRM
}},
4581 {"dssall", XDSS(31,822,1), XDSS_MASK
, PPCVEC
, {0}},
4583 {"db8cyc", 0x7f9ce378, 0xffffffff, CELL
, {0}},
4584 {"db10cyc", 0x7fbdeb78, 0xffffffff, CELL
, {0}},
4585 {"db12cyc", 0x7fdef378, 0xffffffff, CELL
, {0}},
4586 {"db16cyc", 0x7ffffb78, 0xffffffff, CELL
, {0}},
4588 {"lwz", OP(32), OP_MASK
, PPCCOM
, {RT
, D
, RA0
}},
4589 {"l", OP(32), OP_MASK
, PWRCOM
, {RT
, D
, RA0
}},
4591 {"lwzu", OP(33), OP_MASK
, PPCCOM
, {RT
, D
, RAL
}},
4592 {"lu", OP(33), OP_MASK
, PWRCOM
, {RT
, D
, RA0
}},
4594 {"lbz", OP(34), OP_MASK
, COM
, {RT
, D
, RA0
}},
4596 {"lbzu", OP(35), OP_MASK
, COM
, {RT
, D
, RAL
}},
4598 {"stw", OP(36), OP_MASK
, PPCCOM
, {RS
, D
, RA0
}},
4599 {"st", OP(36), OP_MASK
, PWRCOM
, {RS
, D
, RA0
}},
4601 {"stwu", OP(37), OP_MASK
, PPCCOM
, {RS
, D
, RAS
}},
4602 {"stu", OP(37), OP_MASK
, PWRCOM
, {RS
, D
, RA0
}},
4604 {"stb", OP(38), OP_MASK
, COM
, {RS
, D
, RA0
}},
4606 {"stbu", OP(39), OP_MASK
, COM
, {RS
, D
, RAS
}},
4608 {"lhz", OP(40), OP_MASK
, COM
, {RT
, D
, RA0
}},
4610 {"lhzu", OP(41), OP_MASK
, COM
, {RT
, D
, RAL
}},
4612 {"lha", OP(42), OP_MASK
, COM
, {RT
, D
, RA0
}},
4614 {"lhau", OP(43), OP_MASK
, COM
, {RT
, D
, RAL
}},
4616 {"sth", OP(44), OP_MASK
, COM
, {RS
, D
, RA0
}},
4618 {"sthu", OP(45), OP_MASK
, COM
, {RS
, D
, RAS
}},
4620 {"lmw", OP(46), OP_MASK
, PPCCOM
, {RT
, D
, RAM
}},
4621 {"lm", OP(46), OP_MASK
, PWRCOM
, {RT
, D
, RA0
}},
4623 {"stmw", OP(47), OP_MASK
, PPCCOM
, {RS
, D
, RA0
}},
4624 {"stm", OP(47), OP_MASK
, PWRCOM
, {RS
, D
, RA0
}},
4626 {"lfs", OP(48), OP_MASK
, COM
, {FRT
, D
, RA0
}},
4628 {"lfsu", OP(49), OP_MASK
, COM
, {FRT
, D
, RAS
}},
4630 {"lfd", OP(50), OP_MASK
, COM
, {FRT
, D
, RA0
}},
4632 {"lfdu", OP(51), OP_MASK
, COM
, {FRT
, D
, RAS
}},
4634 {"stfs", OP(52), OP_MASK
, COM
, {FRS
, D
, RA0
}},
4636 {"stfsu", OP(53), OP_MASK
, COM
, {FRS
, D
, RAS
}},
4638 {"stfd", OP(54), OP_MASK
, COM
, {FRS
, D
, RA0
}},
4640 {"stfdu", OP(55), OP_MASK
, COM
, {FRS
, D
, RAS
}},
4642 {"lq", OP(56), OP_MASK
, POWER4
, {RTQ
, DQ
, RAQ
}},
4644 {"lfq", OP(56), OP_MASK
, POWER2
, {FRT
, D
, RA0
}},
4646 {"psq_l", OP(56), OP_MASK
, PPCPS
, {FRT
,PSD
,RA
,PSW
,PSQ
}},
4648 {"lfqu", OP(57), OP_MASK
, POWER2
, {FRT
, D
, RA0
}},
4650 {"psq_lu", OP(57), OP_MASK
, PPCPS
, {FRT
,PSD
,RA
,PSW
,PSQ
}},
4652 {"lfdp", OP(57), OP_MASK
, POWER6
, {FRT
, D
, RA0
}},
4654 {"lbze", DEO(58,0), DE_MASK
, BOOKE64
, {RT
, DE
, RA0
}},
4655 {"lbzue", DEO(58,1), DE_MASK
, BOOKE64
, {RT
, DE
, RAL
}},
4656 {"lhze", DEO(58,2), DE_MASK
, BOOKE64
, {RT
, DE
, RA0
}},
4657 {"lhzue", DEO(58,3), DE_MASK
, BOOKE64
, {RT
, DE
, RAL
}},
4658 {"lhae", DEO(58,4), DE_MASK
, BOOKE64
, {RT
, DE
, RA0
}},
4659 {"lhaue", DEO(58,5), DE_MASK
, BOOKE64
, {RT
, DE
, RAL
}},
4660 {"lwze", DEO(58,6), DE_MASK
, BOOKE64
, {RT
, DE
, RA0
}},
4661 {"lwzue", DEO(58,7), DE_MASK
, BOOKE64
, {RT
, DE
, RAL
}},
4662 {"stbe", DEO(58,8), DE_MASK
, BOOKE64
, {RS
, DE
, RA0
}},
4663 {"stbue", DEO(58,9), DE_MASK
, BOOKE64
, {RS
, DE
, RAS
}},
4664 {"sthe", DEO(58,10), DE_MASK
, BOOKE64
, {RS
, DE
, RA0
}},
4665 {"sthue", DEO(58,11), DE_MASK
, BOOKE64
, {RS
, DE
, RAS
}},
4666 {"stwe", DEO(58,14), DE_MASK
, BOOKE64
, {RS
, DE
, RA0
}},
4667 {"stwue", DEO(58,15), DE_MASK
, BOOKE64
, {RS
, DE
, RAS
}},
4669 {"ld", DSO(58,0), DS_MASK
, PPC64
, {RT
, DS
, RA0
}},
4670 {"ldu", DSO(58,1), DS_MASK
, PPC64
, {RT
, DS
, RAL
}},
4671 {"lwa", DSO(58,2), DS_MASK
, PPC64
, {RT
, DS
, RA0
}},
4673 {"dadd", XRC(59,2,0), X_MASK
, POWER6
, {FRT
, FRA
, FRB
}},
4674 {"dadd.", XRC(59,2,1), X_MASK
, POWER6
, {FRT
, FRA
, FRB
}},
4676 {"dqua", ZRC(59,3,0), Z2_MASK
, POWER6
, {FRT
,FRA
,FRB
,RMC
}},
4677 {"dqua.", ZRC(59,3,1), Z2_MASK
, POWER6
, {FRT
,FRA
,FRB
,RMC
}},
4679 {"fdivs", A(59,18,0), AFRC_MASK
, PPC
, {FRT
, FRA
, FRB
}},
4680 {"fdivs.", A(59,18,1), AFRC_MASK
, PPC
, {FRT
, FRA
, FRB
}},
4682 {"fsubs", A(59,20,0), AFRC_MASK
, PPC
, {FRT
, FRA
, FRB
}},
4683 {"fsubs.", A(59,20,1), AFRC_MASK
, PPC
, {FRT
, FRA
, FRB
}},
4685 {"fadds", A(59,21,0), AFRC_MASK
, PPC
, {FRT
, FRA
, FRB
}},
4686 {"fadds.", A(59,21,1), AFRC_MASK
, PPC
, {FRT
, FRA
, FRB
}},
4688 {"fsqrts", A(59,22,0), AFRAFRC_MASK
, PPC
, {FRT
, FRB
}},
4689 {"fsqrts.", A(59,22,1), AFRAFRC_MASK
, PPC
, {FRT
, FRB
}},
4691 {"fres", A(59,24,0), AFRALFRC_MASK
, PPC
, {FRT
, FRB
, A_L
}},
4692 {"fres.", A(59,24,1), AFRALFRC_MASK
, PPC
, {FRT
, FRB
, A_L
}},
4694 {"fmuls", A(59,25,0), AFRB_MASK
, PPC
, {FRT
, FRA
, FRC
}},
4695 {"fmuls.", A(59,25,1), AFRB_MASK
, PPC
, {FRT
, FRA
, FRC
}},
4697 {"frsqrtes", A(59,26,0), AFRALFRC_MASK
, POWER5
, {FRT
, FRB
, A_L
}},
4698 {"frsqrtes.", A(59,26,1), AFRALFRC_MASK
, POWER5
, {FRT
, FRB
, A_L
}},
4700 {"fmsubs", A(59,28,0), A_MASK
, PPC
, {FRT
, FRA
, FRC
, FRB
}},
4701 {"fmsubs.", A(59,28,1), A_MASK
, PPC
, {FRT
, FRA
, FRC
, FRB
}},
4703 {"fmadds", A(59,29,0), A_MASK
, PPC
, {FRT
, FRA
, FRC
, FRB
}},
4704 {"fmadds.", A(59,29,1), A_MASK
, PPC
, {FRT
, FRA
, FRC
, FRB
}},
4706 {"fnmsubs", A(59,30,0), A_MASK
, PPC
, {FRT
, FRA
, FRC
, FRB
}},
4707 {"fnmsubs.", A(59,30,1), A_MASK
, PPC
, {FRT
, FRA
, FRC
, FRB
}},
4709 {"fnmadds", A(59,31,0), A_MASK
, PPC
, {FRT
, FRA
, FRC
, FRB
}},
4710 {"fnmadds.", A(59,31,1), A_MASK
, PPC
, {FRT
, FRA
, FRC
, FRB
}},
4712 {"dmul", XRC(59,34,0), X_MASK
, POWER6
, {FRT
, FRA
, FRB
}},
4713 {"dmul.", XRC(59,34,1), X_MASK
, POWER6
, {FRT
, FRA
, FRB
}},
4715 {"drrnd", ZRC(59,35,0), Z2_MASK
, POWER6
, {FRT
, FRA
, FRB
, RMC
}},
4716 {"drrnd.", ZRC(59,35,1), Z2_MASK
, POWER6
, {FRT
, FRA
, FRB
, RMC
}},
4718 {"dscli", ZRC(59,66,0), Z_MASK
, POWER6
, {FRT
, FRA
, SH16
}},
4719 {"dscli.", ZRC(59,66,1), Z_MASK
, POWER6
, {FRT
, FRA
, SH16
}},
4721 {"dquai", ZRC(59,67,0), Z2_MASK
, POWER6
, {TE
, FRT
,FRB
,RMC
}},
4722 {"dquai.", ZRC(59,67,1), Z2_MASK
, POWER6
, {TE
, FRT
,FRB
,RMC
}},
4724 {"dscri", ZRC(59,98,0), Z_MASK
, POWER6
, {FRT
, FRA
, SH16
}},
4725 {"dscri.", ZRC(59,98,1), Z_MASK
, POWER6
, {FRT
, FRA
, SH16
}},
4727 {"drintx", ZRC(59,99,0), Z2_MASK
, POWER6
, {R
, FRT
, FRB
, RMC
}},
4728 {"drintx.", ZRC(59,99,1), Z2_MASK
, POWER6
, {R
, FRT
, FRB
, RMC
}},
4730 {"dcmpo", X(59,130), X_MASK
, POWER6
, {BF
, FRA
, FRB
}},
4732 {"dtstex", X(59,162), X_MASK
, POWER6
, {BF
, FRA
, FRB
}},
4733 {"dtstdc", Z(59,194), Z_MASK
, POWER6
, {BF
, FRA
, DCM
}},
4734 {"dtstdg", Z(59,226), Z_MASK
, POWER6
, {BF
, FRA
, DGM
}},
4736 {"drintn", ZRC(59,227,0), Z2_MASK
, POWER6
, {R
, FRT
, FRB
, RMC
}},
4737 {"drintn.", ZRC(59,227,1), Z2_MASK
, POWER6
, {R
, FRT
, FRB
, RMC
}},
4739 {"dctdp", XRC(59,258,0), X_MASK
, POWER6
, {FRT
, FRB
}},
4740 {"dctdp.", XRC(59,258,1), X_MASK
, POWER6
, {FRT
, FRB
}},
4742 {"dctfix", XRC(59,290,0), X_MASK
, POWER6
, {FRT
, FRB
}},
4743 {"dctfix.", XRC(59,290,1), X_MASK
, POWER6
, {FRT
, FRB
}},
4745 {"ddedpd", XRC(59,322,0), X_MASK
, POWER6
, {SP
, FRT
, FRB
}},
4746 {"ddedpd.", XRC(59,322,1), X_MASK
, POWER6
, {SP
, FRT
, FRB
}},
4748 {"dxex", XRC(59,354,0), X_MASK
, POWER6
, {FRT
, FRB
}},
4749 {"dxex.", XRC(59,354,1), X_MASK
, POWER6
, {FRT
, FRB
}},
4751 {"dsub", XRC(59,514,0), X_MASK
, POWER6
, {FRT
, FRA
, FRB
}},
4752 {"dsub.", XRC(59,514,1), X_MASK
, POWER6
, {FRT
, FRA
, FRB
}},
4754 {"ddiv", XRC(59,546,0), X_MASK
, POWER6
, {FRT
, FRA
, FRB
}},
4755 {"ddiv.", XRC(59,546,1), X_MASK
, POWER6
, {FRT
, FRA
, FRB
}},
4757 {"dcmpu", X(59,642), X_MASK
, POWER6
, {BF
, FRA
, FRB
}},
4759 {"dtstsf", X(59,674), X_MASK
, POWER6
, {BF
, FRA
, FRB
}},
4761 {"drsp", XRC(59,770,0), X_MASK
, POWER6
, {FRT
, FRB
}},
4762 {"drsp.", XRC(59,770,1), X_MASK
, POWER6
, {FRT
, FRB
}},
4764 {"denbcd", XRC(59,834,0), X_MASK
, POWER6
, {S
, FRT
, FRB
}},
4765 {"denbcd.", XRC(59,834,1), X_MASK
, POWER6
, {S
, FRT
, FRB
}},
4767 {"diex", XRC(59,866,0), X_MASK
, POWER6
, {FRT
, FRA
, FRB
}},
4768 {"diex.", XRC(59,866,1), X_MASK
, POWER6
, {FRT
, FRA
, FRB
}},
4770 {"stfq", OP(60), OP_MASK
, POWER2
, {FRS
, D
, RA
}},
4772 {"psq_st", OP(60), OP_MASK
, PPCPS
, {FRS
,PSD
,RA
,PSW
,PSQ
}},
4773 {"psq_stu", OP(61), OP_MASK
, PPCPS
, {FRS
,PSD
,RA
,PSW
,PSQ
}},
4775 {"stfqu", OP(61), OP_MASK
, POWER2
, {FRS
, D
, RA
}},
4777 {"stfdp", OP(61), OP_MASK
, POWER6
, {FRT
, D
, RA0
}},
4779 {"lde", DEO(62,0), DE_MASK
, BOOKE64
, {RT
, DES
, RA0
}},
4780 {"ldue", DEO(62,1), DE_MASK
, BOOKE64
, {RT
, DES
, RA0
}},
4781 {"lfse", DEO(62,4), DE_MASK
, BOOKE64
, {FRT
, DES
, RA0
}},
4782 {"lfsue", DEO(62,5), DE_MASK
, BOOKE64
, {FRT
, DES
, RAS
}},
4783 {"lfde", DEO(62,6), DE_MASK
, BOOKE64
, {FRT
, DES
, RA0
}},
4784 {"lfdue", DEO(62,7), DE_MASK
, BOOKE64
, {FRT
, DES
, RAS
}},
4785 {"stde", DEO(62,8), DE_MASK
, BOOKE64
, {RS
, DES
, RA0
}},
4786 {"stdue", DEO(62,9), DE_MASK
, BOOKE64
, {RS
, DES
, RAS
}},
4787 {"stfse", DEO(62,12), DE_MASK
, BOOKE64
, {FRS
, DES
, RA0
}},
4788 {"stfsue", DEO(62,13), DE_MASK
, BOOKE64
, {FRS
, DES
, RAS
}},
4789 {"stfde", DEO(62,14), DE_MASK
, BOOKE64
, {FRS
, DES
, RA0
}},
4790 {"stfdue", DEO(62,15), DE_MASK
, BOOKE64
, {FRS
, DES
, RAS
}},
4792 {"std", DSO(62,0), DS_MASK
, PPC64
, {RS
, DS
, RA0
}},
4793 {"stdu", DSO(62,1), DS_MASK
, PPC64
, {RS
, DS
, RAS
}},
4794 {"stq", DSO(62,2), DS_MASK
, POWER4
, {RSQ
, DS
, RA0
}},
4796 {"fcmpu", X(63,0), X_MASK
|(3<<21), COM
, {BF
, FRA
, FRB
}},
4798 {"daddq", XRC(63,2,0), X_MASK
, POWER6
, {FRT
, FRA
, FRB
}},
4799 {"daddq.", XRC(63,2,1), X_MASK
, POWER6
, {FRT
, FRA
, FRB
}},
4801 {"dquaq", ZRC(63,3,0), Z2_MASK
, POWER6
, {FRT
, FRA
, FRB
, RMC
}},
4802 {"dquaq.", ZRC(63,3,1), Z2_MASK
, POWER6
, {FRT
, FRA
, FRB
, RMC
}},
4804 {"fcpsgn", XRC(63,8,0), X_MASK
, POWER6
, {FRT
, FRA
, FRB
}},
4805 {"fcpsgn.", XRC(63,8,1), X_MASK
, POWER6
, {FRT
, FRA
, FRB
}},
4807 {"frsp", XRC(63,12,0), XRA_MASK
, COM
, {FRT
, FRB
}},
4808 {"frsp.", XRC(63,12,1), XRA_MASK
, COM
, {FRT
, FRB
}},
4810 {"fctiw", XRC(63,14,0), XRA_MASK
, PPCCOM
, {FRT
, FRB
}},
4811 {"fcir", XRC(63,14,0), XRA_MASK
, POWER2
, {FRT
, FRB
}},
4812 {"fctiw.", XRC(63,14,1), XRA_MASK
, PPCCOM
, {FRT
, FRB
}},
4813 {"fcir.", XRC(63,14,1), XRA_MASK
, POWER2
, {FRT
, FRB
}},
4815 {"fctiwz", XRC(63,15,0), XRA_MASK
, PPCCOM
, {FRT
, FRB
}},
4816 {"fcirz", XRC(63,15,0), XRA_MASK
, POWER2
, {FRT
, FRB
}},
4817 {"fctiwz.", XRC(63,15,1), XRA_MASK
, PPCCOM
, {FRT
, FRB
}},
4818 {"fcirz.", XRC(63,15,1), XRA_MASK
, POWER2
, {FRT
, FRB
}},
4820 {"fdiv", A(63,18,0), AFRC_MASK
, PPCCOM
, {FRT
, FRA
, FRB
}},
4821 {"fd", A(63,18,0), AFRC_MASK
, PWRCOM
, {FRT
, FRA
, FRB
}},
4822 {"fdiv.", A(63,18,1), AFRC_MASK
, PPCCOM
, {FRT
, FRA
, FRB
}},
4823 {"fd.", A(63,18,1), AFRC_MASK
, PWRCOM
, {FRT
, FRA
, FRB
}},
4825 {"fsub", A(63,20,0), AFRC_MASK
, PPCCOM
, {FRT
, FRA
, FRB
}},
4826 {"fs", A(63,20,0), AFRC_MASK
, PWRCOM
, {FRT
, FRA
, FRB
}},
4827 {"fsub.", A(63,20,1), AFRC_MASK
, PPCCOM
, {FRT
, FRA
, FRB
}},
4828 {"fs.", A(63,20,1), AFRC_MASK
, PWRCOM
, {FRT
, FRA
, FRB
}},
4830 {"fadd", A(63,21,0), AFRC_MASK
, PPCCOM
, {FRT
, FRA
, FRB
}},
4831 {"fa", A(63,21,0), AFRC_MASK
, PWRCOM
, {FRT
, FRA
, FRB
}},
4832 {"fadd.", A(63,21,1), AFRC_MASK
, PPCCOM
, {FRT
, FRA
, FRB
}},
4833 {"fa.", A(63,21,1), AFRC_MASK
, PWRCOM
, {FRT
, FRA
, FRB
}},
4835 {"fsqrt", A(63,22,0), AFRAFRC_MASK
, PPCPWR2
, {FRT
, FRB
}},
4836 {"fsqrt.", A(63,22,1), AFRAFRC_MASK
, PPCPWR2
, {FRT
, FRB
}},
4838 {"fsel", A(63,23,0), A_MASK
, PPC
, {FRT
, FRA
, FRC
, FRB
}},
4839 {"fsel.", A(63,23,1), A_MASK
, PPC
, {FRT
, FRA
, FRC
, FRB
}},
4841 {"fre", A(63,24,0), AFRALFRC_MASK
, POWER5
, {FRT
, FRB
, A_L
}},
4842 {"fre.", A(63,24,1), AFRALFRC_MASK
, POWER5
, {FRT
, FRB
, A_L
}},
4844 {"fmul", A(63,25,0), AFRB_MASK
, PPCCOM
, {FRT
, FRA
, FRC
}},
4845 {"fm", A(63,25,0), AFRB_MASK
, PWRCOM
, {FRT
, FRA
, FRC
}},
4846 {"fmul.", A(63,25,1), AFRB_MASK
, PPCCOM
, {FRT
, FRA
, FRC
}},
4847 {"fm.", A(63,25,1), AFRB_MASK
, PWRCOM
, {FRT
, FRA
, FRC
}},
4849 {"frsqrte", A(63,26,0), AFRALFRC_MASK
, PPC
, {FRT
, FRB
, A_L
}},
4850 {"frsqrte.", A(63,26,1), AFRALFRC_MASK
, PPC
, {FRT
, FRB
, A_L
}},
4852 {"fmsub", A(63,28,0), A_MASK
, PPCCOM
, {FRT
, FRA
, FRC
, FRB
}},
4853 {"fms", A(63,28,0), A_MASK
, PWRCOM
, {FRT
, FRA
, FRC
, FRB
}},
4854 {"fmsub.", A(63,28,1), A_MASK
, PPCCOM
, {FRT
, FRA
, FRC
, FRB
}},
4855 {"fms.", A(63,28,1), A_MASK
, PWRCOM
, {FRT
, FRA
, FRC
, FRB
}},
4857 {"fmadd", A(63,29,0), A_MASK
, PPCCOM
, {FRT
, FRA
, FRC
, FRB
}},
4858 {"fma", A(63,29,0), A_MASK
, PWRCOM
, {FRT
, FRA
, FRC
, FRB
}},
4859 {"fmadd.", A(63,29,1), A_MASK
, PPCCOM
, {FRT
, FRA
, FRC
, FRB
}},
4860 {"fma.", A(63,29,1), A_MASK
, PWRCOM
, {FRT
, FRA
, FRC
, FRB
}},
4862 {"fnmsub", A(63,30,0), A_MASK
, PPCCOM
, {FRT
, FRA
, FRC
, FRB
}},
4863 {"fnms", A(63,30,0), A_MASK
, PWRCOM
, {FRT
, FRA
, FRC
, FRB
}},
4864 {"fnmsub.", A(63,30,1), A_MASK
, PPCCOM
, {FRT
, FRA
, FRC
, FRB
}},
4865 {"fnms.", A(63,30,1), A_MASK
, PWRCOM
, {FRT
, FRA
, FRC
, FRB
}},
4867 {"fnmadd", A(63,31,0), A_MASK
, PPCCOM
, {FRT
, FRA
, FRC
, FRB
}},
4868 {"fnma", A(63,31,0), A_MASK
, PWRCOM
, {FRT
, FRA
, FRC
, FRB
}},
4869 {"fnmadd.", A(63,31,1), A_MASK
, PPCCOM
, {FRT
, FRA
, FRC
, FRB
}},
4870 {"fnma.", A(63,31,1), A_MASK
, PWRCOM
, {FRT
, FRA
, FRC
, FRB
}},
4872 {"fcmpo", X(63,32), X_MASK
|(3<<21), COM
, {BF
, FRA
, FRB
}},
4874 {"dmulq", XRC(63,34,0), X_MASK
, POWER6
, {FRT
, FRA
, FRB
}},
4875 {"dmulq.", XRC(63,34,1), X_MASK
, POWER6
, {FRT
, FRA
, FRB
}},
4877 {"drrndq", ZRC(63,35,0), Z2_MASK
, POWER6
, {FRT
, FRA
, FRB
, RMC
}},
4878 {"drrndq.", ZRC(63,35,1), Z2_MASK
, POWER6
, {FRT
, FRA
, FRB
, RMC
}},
4880 {"mtfsb1", XRC(63,38,0), XRARB_MASK
, COM
, {BT
}},
4881 {"mtfsb1.", XRC(63,38,1), XRARB_MASK
, COM
, {BT
}},
4883 {"fneg", XRC(63,40,0), XRA_MASK
, COM
, {FRT
, FRB
}},
4884 {"fneg.", XRC(63,40,1), XRA_MASK
, COM
, {FRT
, FRB
}},
4886 {"mcrfs", X(63,64), XRB_MASK
|(3<<21)|(3<<16), COM
, {BF
, BFA
}},
4888 {"dscliq", ZRC(63,66,0), Z_MASK
, POWER6
, {FRT
, FRA
, SH16
}},
4889 {"dscliq.", ZRC(63,66,1), Z_MASK
, POWER6
, {FRT
, FRA
, SH16
}},
4891 {"dquaiq", ZRC(63,67,0), Z2_MASK
, POWER6
, {TE
, FRT
, FRB
, RMC
}},
4892 {"dquaiq.", ZRC(63,67,1), Z2_MASK
, POWER6
, {TE
, FRT
, FRB
, RMC
}},
4894 {"mtfsb0", XRC(63,70,0), XRARB_MASK
, COM
, {BT
}},
4895 {"mtfsb0.", XRC(63,70,1), XRARB_MASK
, COM
, {BT
}},
4897 {"fmr", XRC(63,72,0), XRA_MASK
, COM
, {FRT
, FRB
}},
4898 {"fmr.", XRC(63,72,1), XRA_MASK
, COM
, {FRT
, FRB
}},
4900 {"dscriq", ZRC(63,98,0), Z_MASK
, POWER6
, {FRT
, FRA
, SH16
}},
4901 {"dscriq.", ZRC(63,98,1), Z_MASK
, POWER6
, {FRT
, FRA
, SH16
}},
4903 {"drintxq", ZRC(63,99,0), Z2_MASK
, POWER6
, {R
, FRT
, FRB
, RMC
}},
4904 {"drintxq.", ZRC(63,99,1), Z2_MASK
, POWER6
, {R
, FRT
, FRB
, RMC
}},
4906 {"dcmpoq", X(63,130), X_MASK
, POWER6
, {BF
, FRA
, FRB
}},
4908 {"mtfsfi", XRC(63,134,0), XWRA_MASK
|(3<<21)|(1<<11), COM
, {BFF
, U
, W
}},
4909 {"mtfsfi.", XRC(63,134,1), XWRA_MASK
|(3<<21)|(1<<11), COM
, {BFF
, U
, W
}},
4911 {"fnabs", XRC(63,136,0), XRA_MASK
, COM
, {FRT
, FRB
}},
4912 {"fnabs.", XRC(63,136,1), XRA_MASK
, COM
, {FRT
, FRB
}},
4914 {"dtstexq", X(63,162), X_MASK
, POWER6
, {BF
, FRA
, FRB
}},
4915 {"dtstdcq", Z(63,194), Z_MASK
, POWER6
, {BF
, FRA
, DCM
}},
4916 {"dtstdgq", Z(63,226), Z_MASK
, POWER6
, {BF
, FRA
, DGM
}},
4918 {"drintnq", ZRC(63,227,0), Z2_MASK
, POWER6
, {R
, FRT
, FRB
, RMC
}},
4919 {"drintnq.", ZRC(63,227,1), Z2_MASK
, POWER6
, {R
, FRT
, FRB
, RMC
}},
4921 {"dctqpq", XRC(63,258,0), X_MASK
, POWER6
, {FRT
, FRB
}},
4922 {"dctqpq.", XRC(63,258,1), X_MASK
, POWER6
, {FRT
, FRB
}},
4924 {"fabs", XRC(63,264,0), XRA_MASK
, COM
, {FRT
, FRB
}},
4925 {"fabs.", XRC(63,264,1), XRA_MASK
, COM
, {FRT
, FRB
}},
4927 {"dctfixq", XRC(63,290,0), X_MASK
, POWER6
, {FRT
, FRB
}},
4928 {"dctfixq.", XRC(63,290,1), X_MASK
, POWER6
, {FRT
, FRB
}},
4930 {"ddedpdq", XRC(63,322,0), X_MASK
, POWER6
, {SP
, FRT
, FRB
}},
4931 {"ddedpdq.", XRC(63,322,1), X_MASK
, POWER6
, {SP
, FRT
, FRB
}},
4933 {"dxexq", XRC(63,354,0), X_MASK
, POWER6
, {FRT
, FRB
}},
4934 {"dxexq.", XRC(63,354,1), X_MASK
, POWER6
, {FRT
, FRB
}},
4936 {"frin", XRC(63,392,0), XRA_MASK
, POWER5
, {FRT
, FRB
}},
4937 {"frin.", XRC(63,392,1), XRA_MASK
, POWER5
, {FRT
, FRB
}},
4938 {"friz", XRC(63,424,0), XRA_MASK
, POWER5
, {FRT
, FRB
}},
4939 {"friz.", XRC(63,424,1), XRA_MASK
, POWER5
, {FRT
, FRB
}},
4940 {"frip", XRC(63,456,0), XRA_MASK
, POWER5
, {FRT
, FRB
}},
4941 {"frip.", XRC(63,456,1), XRA_MASK
, POWER5
, {FRT
, FRB
}},
4942 {"frim", XRC(63,488,0), XRA_MASK
, POWER5
, {FRT
, FRB
}},
4943 {"frim.", XRC(63,488,1), XRA_MASK
, POWER5
, {FRT
, FRB
}},
4945 {"dsubq", XRC(63,514,0), X_MASK
, POWER6
, {FRT
, FRA
, FRB
}},
4946 {"dsubq.", XRC(63,514,1), X_MASK
, POWER6
, {FRT
, FRA
, FRB
}},
4948 {"ddivq", XRC(63,546,0), X_MASK
, POWER6
, {FRT
, FRA
, FRB
}},
4949 {"ddivq.", XRC(63,546,1), X_MASK
, POWER6
, {FRT
, FRA
, FRB
}},
4951 {"mffs", XRC(63,583,0), XRARB_MASK
, COM
, {FRT
}},
4952 {"mffs.", XRC(63,583,1), XRARB_MASK
, COM
, {FRT
}},
4954 {"dcmpuq", X(63,642), X_MASK
, POWER6
, {BF
, FRA
, FRB
}},
4956 {"dtstsfq", X(63,674), X_MASK
, POWER6
, {BF
, FRA
, FRB
}},
4958 {"mtfsf", XFL(63,711,0), XFL_MASK
, COM
, {FLM
, FRB
, XFL_L
, W
}},
4959 {"mtfsf.", XFL(63,711,1), XFL_MASK
, COM
, {FLM
, FRB
, XFL_L
, W
}},
4961 {"drdpq", XRC(63,770,0), X_MASK
, POWER6
, {FRT
, FRB
}},
4962 {"drdpq.", XRC(63,770,1), X_MASK
, POWER6
, {FRT
, FRB
}},
4964 {"dcffixq", XRC(63,802,0), X_MASK
, POWER6
, {FRT
, FRB
}},
4965 {"dcffixq.", XRC(63,802,1), X_MASK
, POWER6
, {FRT
, FRB
}},
4967 {"fctid", XRC(63,814,0), XRA_MASK
, PPC64
, {FRT
, FRB
}},
4968 {"fctid.", XRC(63,814,1), XRA_MASK
, PPC64
, {FRT
, FRB
}},
4970 {"fctidz", XRC(63,815,0), XRA_MASK
, PPC64
, {FRT
, FRB
}},
4971 {"fctidz.", XRC(63,815,1), XRA_MASK
, PPC64
, {FRT
, FRB
}},
4973 {"denbcdq", XRC(63,834,0), X_MASK
, POWER6
, {S
, FRT
, FRB
}},
4974 {"denbcdq.", XRC(63,834,1), X_MASK
, POWER6
, {S
, FRT
, FRB
}},
4976 {"fcfid", XRC(63,846,0), XRA_MASK
, PPC64
, {FRT
, FRB
}},
4977 {"fcfid.", XRC(63,846,1), XRA_MASK
, PPC64
, {FRT
, FRB
}},
4979 {"diexq", XRC(63,866,0), X_MASK
, POWER6
, {FRT
, FRA
, FRB
}},
4980 {"diexq.", XRC(63,866,1), X_MASK
, POWER6
, {FRT
, FRA
, FRB
}},
4984 const int powerpc_num_opcodes
=
4985 sizeof (powerpc_opcodes
) / sizeof (powerpc_opcodes
[0]);
4987 /* The macro table. This is only used by the assembler. */
4989 /* The expressions of the form (-x ! 31) & (x | 31) have the value 0
4990 when x=0; 32-x when x is between 1 and 31; are negative if x is
4991 negative; and are 32 or more otherwise. This is what you want
4992 when, for instance, you are emulating a right shift by a
4993 rotate-left-and-mask, because the underlying instructions support
4994 shifts of size 0 but not shifts of size 32. By comparison, when
4995 extracting x bits from some word you want to use just 32-x, because
4996 the underlying instructions don't support extracting 0 bits but do
4997 support extracting the whole word (32 bits in this case). */
4999 const struct powerpc_macro powerpc_macros
[] = {
5000 {"extldi", 4, PPC64
, "rldicr %0,%1,%3,(%2)-1"},
5001 {"extldi.", 4, PPC64
, "rldicr. %0,%1,%3,(%2)-1"},
5002 {"extrdi", 4, PPC64
, "rldicl %0,%1,(%2)+(%3),64-(%2)"},
5003 {"extrdi.", 4, PPC64
, "rldicl. %0,%1,(%2)+(%3),64-(%2)"},
5004 {"insrdi", 4, PPC64
, "rldimi %0,%1,64-((%2)+(%3)),%3"},
5005 {"insrdi.", 4, PPC64
, "rldimi. %0,%1,64-((%2)+(%3)),%3"},
5006 {"rotrdi", 3, PPC64
, "rldicl %0,%1,(-(%2)!63)&((%2)|63),0"},
5007 {"rotrdi.", 3, PPC64
, "rldicl. %0,%1,(-(%2)!63)&((%2)|63),0"},
5008 {"sldi", 3, PPC64
, "rldicr %0,%1,%2,63-(%2)"},
5009 {"sldi.", 3, PPC64
, "rldicr. %0,%1,%2,63-(%2)"},
5010 {"srdi", 3, PPC64
, "rldicl %0,%1,(-(%2)!63)&((%2)|63),%2"},
5011 {"srdi.", 3, PPC64
, "rldicl. %0,%1,(-(%2)!63)&((%2)|63),%2"},
5012 {"clrrdi", 3, PPC64
, "rldicr %0,%1,0,63-(%2)"},
5013 {"clrrdi.", 3, PPC64
, "rldicr. %0,%1,0,63-(%2)"},
5014 {"clrlsldi", 4, PPC64
, "rldic %0,%1,%3,(%2)-(%3)"},
5015 {"clrlsldi.",4, PPC64
, "rldic. %0,%1,%3,(%2)-(%3)"},
5017 {"extlwi", 4, PPCCOM
, "rlwinm %0,%1,%3,0,(%2)-1"},
5018 {"extlwi.", 4, PPCCOM
, "rlwinm. %0,%1,%3,0,(%2)-1"},
5019 {"extrwi", 4, PPCCOM
, "rlwinm %0,%1,((%2)+(%3))&((%2)+(%3)<>32),32-(%2),31"},
5020 {"extrwi.", 4, PPCCOM
, "rlwinm. %0,%1,((%2)+(%3))&((%2)+(%3)<>32),32-(%2),31"},
5021 {"inslwi", 4, PPCCOM
, "rlwimi %0,%1,(-(%3)!31)&((%3)|31),%3,(%2)+(%3)-1"},
5022 {"inslwi.", 4, PPCCOM
, "rlwimi. %0,%1,(-(%3)!31)&((%3)|31),%3,(%2)+(%3)-1"},
5023 {"insrwi", 4, PPCCOM
, "rlwimi %0,%1,32-((%2)+(%3)),%3,(%2)+(%3)-1"},
5024 {"insrwi.", 4, PPCCOM
, "rlwimi. %0,%1,32-((%2)+(%3)),%3,(%2)+(%3)-1"},
5025 {"rotrwi", 3, PPCCOM
, "rlwinm %0,%1,(-(%2)!31)&((%2)|31),0,31"},
5026 {"rotrwi.", 3, PPCCOM
, "rlwinm. %0,%1,(-(%2)!31)&((%2)|31),0,31"},
5027 {"slwi", 3, PPCCOM
, "rlwinm %0,%1,%2,0,31-(%2)"},
5028 {"sli", 3, PWRCOM
, "rlinm %0,%1,%2,0,31-(%2)"},
5029 {"slwi.", 3, PPCCOM
, "rlwinm. %0,%1,%2,0,31-(%2)"},
5030 {"sli.", 3, PWRCOM
, "rlinm. %0,%1,%2,0,31-(%2)"},
5031 {"srwi", 3, PPCCOM
, "rlwinm %0,%1,(-(%2)!31)&((%2)|31),%2,31"},
5032 {"sri", 3, PWRCOM
, "rlinm %0,%1,(-(%2)!31)&((%2)|31),%2,31"},
5033 {"srwi.", 3, PPCCOM
, "rlwinm. %0,%1,(-(%2)!31)&((%2)|31),%2,31"},
5034 {"sri.", 3, PWRCOM
, "rlinm. %0,%1,(-(%2)!31)&((%2)|31),%2,31"},
5035 {"clrrwi", 3, PPCCOM
, "rlwinm %0,%1,0,0,31-(%2)"},
5036 {"clrrwi.", 3, PPCCOM
, "rlwinm. %0,%1,0,0,31-(%2)"},
5037 {"clrlslwi", 4, PPCCOM
, "rlwinm %0,%1,%3,(%2)-(%3),31-(%3)"},
5038 {"clrlslwi.",4, PPCCOM
, "rlwinm. %0,%1,%3,(%2)-(%3),31-(%3)"},
5041 const int powerpc_num_macros
=
5042 sizeof (powerpc_macros
) / sizeof (powerpc_macros
[0]);