1 /* ppc-opc.c -- PowerPC opcode list
2 Copyright 1994, 1995, 1996, 1997, 1998, 2000, 2001, 2002, 2003, 2004,
3 2005, 2006, 2007, 2008, 2009, 2010, 2011, 2012
4 Free Software Foundation, Inc.
5 Written by Ian Lance Taylor, Cygnus Support
7 This file is part of the GNU opcodes library.
9 This library is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 3, or (at your option)
14 It is distributed in the hope that it will be useful, but WITHOUT
15 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
16 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
17 License for more details.
19 You should have received a copy of the GNU General Public License
20 along with this file; see the file COPYING. If not, write to the
21 Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston,
22 MA 02110-1301, USA. */
26 #include "opcode/ppc.h"
29 /* This file holds the PowerPC opcode table. The opcode table
30 includes almost all of the extended instruction mnemonics. This
31 permits the disassembler to use them, and simplifies the assembler
32 logic, at the cost of increasing the table size. The table is
33 strictly constant data, so the compiler should be able to put it in
36 This file also holds the operand table. All knowledge about
37 inserting operands into instructions and vice-versa is kept in this
40 /* Local insertion and extraction functions. */
42 static unsigned long insert_arx (unsigned long, long, ppc_cpu_t
, const char **);
43 static long extract_arx (unsigned long, ppc_cpu_t
, int *);
44 static unsigned long insert_ary (unsigned long, long, ppc_cpu_t
, const char **);
45 static long extract_ary (unsigned long, ppc_cpu_t
, int *);
46 static unsigned long insert_bat (unsigned long, long, ppc_cpu_t
, const char **);
47 static long extract_bat (unsigned long, ppc_cpu_t
, int *);
48 static unsigned long insert_bba (unsigned long, long, ppc_cpu_t
, const char **);
49 static long extract_bba (unsigned long, ppc_cpu_t
, int *);
50 static unsigned long insert_bdm (unsigned long, long, ppc_cpu_t
, const char **);
51 static long extract_bdm (unsigned long, ppc_cpu_t
, int *);
52 static unsigned long insert_bdp (unsigned long, long, ppc_cpu_t
, const char **);
53 static long extract_bdp (unsigned long, ppc_cpu_t
, int *);
54 static unsigned long insert_bo (unsigned long, long, ppc_cpu_t
, const char **);
55 static long extract_bo (unsigned long, ppc_cpu_t
, int *);
56 static unsigned long insert_boe (unsigned long, long, ppc_cpu_t
, const char **);
57 static long extract_boe (unsigned long, ppc_cpu_t
, int *);
58 static unsigned long insert_fxm (unsigned long, long, ppc_cpu_t
, const char **);
59 static long extract_fxm (unsigned long, ppc_cpu_t
, int *);
60 static unsigned long insert_li20 (unsigned long, long, ppc_cpu_t
, const char **);
61 static long extract_li20 (unsigned long, ppc_cpu_t
, int *);
62 static unsigned long insert_ls (unsigned long, long, ppc_cpu_t
, const char **);
63 static unsigned long insert_mbe (unsigned long, long, ppc_cpu_t
, const char **);
64 static long extract_mbe (unsigned long, ppc_cpu_t
, int *);
65 static unsigned long insert_mb6 (unsigned long, long, ppc_cpu_t
, const char **);
66 static long extract_mb6 (unsigned long, ppc_cpu_t
, int *);
67 static long extract_nb (unsigned long, ppc_cpu_t
, int *);
68 static unsigned long insert_nbi (unsigned long, long, ppc_cpu_t
, const char **);
69 static unsigned long insert_nsi (unsigned long, long, ppc_cpu_t
, const char **);
70 static long extract_nsi (unsigned long, ppc_cpu_t
, int *);
71 static unsigned long insert_oimm (unsigned long, long, ppc_cpu_t
, const char **);
72 static long extract_oimm (unsigned long, ppc_cpu_t
, int *);
73 static unsigned long insert_ral (unsigned long, long, ppc_cpu_t
, const char **);
74 static unsigned long insert_ram (unsigned long, long, ppc_cpu_t
, const char **);
75 static unsigned long insert_raq (unsigned long, long, ppc_cpu_t
, const char **);
76 static unsigned long insert_ras (unsigned long, long, ppc_cpu_t
, const char **);
77 static unsigned long insert_rbs (unsigned long, long, ppc_cpu_t
, const char **);
78 static long extract_rbs (unsigned long, ppc_cpu_t
, int *);
79 static unsigned long insert_rbx (unsigned long, long, ppc_cpu_t
, const char **);
80 static unsigned long insert_rx (unsigned long, long, ppc_cpu_t
, const char **);
81 static long extract_rx (unsigned long, ppc_cpu_t
, int *);
82 static unsigned long insert_ry (unsigned long, long, ppc_cpu_t
, const char **);
83 static long extract_ry (unsigned long, ppc_cpu_t
, int *);
84 static unsigned long insert_sh6 (unsigned long, long, ppc_cpu_t
, const char **);
85 static long extract_sh6 (unsigned long, ppc_cpu_t
, int *);
86 static unsigned long insert_sci8 (unsigned long, long, ppc_cpu_t
, const char **);
87 static long extract_sci8 (unsigned long, ppc_cpu_t
, int *);
88 static unsigned long insert_sci8n (unsigned long, long, ppc_cpu_t
, const char **);
89 static long extract_sci8n (unsigned long, ppc_cpu_t
, int *);
90 static unsigned long insert_sd4h (unsigned long, long, ppc_cpu_t
, const char **);
91 static long extract_sd4h (unsigned long, ppc_cpu_t
, int *);
92 static unsigned long insert_sd4w (unsigned long, long, ppc_cpu_t
, const char **);
93 static long extract_sd4w (unsigned long, ppc_cpu_t
, int *);
94 static unsigned long insert_spr (unsigned long, long, ppc_cpu_t
, const char **);
95 static long extract_spr (unsigned long, ppc_cpu_t
, int *);
96 static unsigned long insert_sprg (unsigned long, long, ppc_cpu_t
, const char **);
97 static long extract_sprg (unsigned long, ppc_cpu_t
, int *);
98 static unsigned long insert_tbr (unsigned long, long, ppc_cpu_t
, const char **);
99 static long extract_tbr (unsigned long, ppc_cpu_t
, int *);
100 static unsigned long insert_xt6 (unsigned long, long, ppc_cpu_t
, const char **);
101 static long extract_xt6 (unsigned long, ppc_cpu_t
, int *);
102 static unsigned long insert_xa6 (unsigned long, long, ppc_cpu_t
, const char **);
103 static long extract_xa6 (unsigned long, ppc_cpu_t
, int *);
104 static unsigned long insert_xb6 (unsigned long, long, ppc_cpu_t
, const char **);
105 static long extract_xb6 (unsigned long, ppc_cpu_t
, int *);
106 static unsigned long insert_xb6s (unsigned long, long, ppc_cpu_t
, const char **);
107 static long extract_xb6s (unsigned long, ppc_cpu_t
, int *);
108 static unsigned long insert_xc6 (unsigned long, long, ppc_cpu_t
, const char **);
109 static long extract_xc6 (unsigned long, ppc_cpu_t
, int *);
110 static unsigned long insert_dm (unsigned long, long, ppc_cpu_t
, const char **);
111 static long extract_dm (unsigned long, ppc_cpu_t
, int *);
112 static unsigned long insert_vlesi (unsigned long, long, ppc_cpu_t
, const char **);
113 static long extract_vlesi (unsigned long, ppc_cpu_t
, int *);
114 static unsigned long insert_vlensi (unsigned long, long, ppc_cpu_t
, const char **);
115 static long extract_vlensi (unsigned long, ppc_cpu_t
, int *);
116 static unsigned long insert_vleui (unsigned long, long, ppc_cpu_t
, const char **);
117 static long extract_vleui (unsigned long, ppc_cpu_t
, int *);
118 static unsigned long insert_vleil (unsigned long, long, ppc_cpu_t
, const char **);
119 static long extract_vleil (unsigned long, ppc_cpu_t
, int *);
121 /* The operands table.
123 The fields are bitm, shift, insert, extract, flags.
125 We used to put parens around the various additions, like the one
126 for BA just below. However, that caused trouble with feeble
127 compilers with a limit on depth of a parenthesized expression, like
128 (reportedly) the compiler in Microsoft Developer Studio 5. So we
129 omit the parens, since the macros are never used in a context where
130 the addition will be ambiguous. */
132 const struct powerpc_operand powerpc_operands
[] =
134 /* The zero index is used to indicate the end of the list of
137 { 0, 0, NULL
, NULL
, 0 },
139 /* The BA field in an XL form instruction. */
140 #define BA UNUSED + 1
141 /* The BI field in a B form or XL form instruction. */
143 #define BI_MASK (0x1f << 16)
144 { 0x1f, 16, NULL
, NULL
, PPC_OPERAND_CR_BIT
},
146 /* The BA field in an XL form instruction when it must be the same
147 as the BT field in the same instruction. */
149 { 0x1f, 16, insert_bat
, extract_bat
, PPC_OPERAND_FAKE
},
151 /* The BB field in an XL form instruction. */
153 #define BB_MASK (0x1f << 11)
154 { 0x1f, 11, NULL
, NULL
, PPC_OPERAND_CR_BIT
},
156 /* The BB field in an XL form instruction when it must be the same
157 as the BA field in the same instruction. */
159 { 0x1f, 11, insert_bba
, extract_bba
, PPC_OPERAND_FAKE
},
161 /* The BD field in a B form instruction. The lower two bits are
164 { 0xfffc, 0, NULL
, NULL
, PPC_OPERAND_RELATIVE
| PPC_OPERAND_SIGNED
},
166 /* The BD field in a B form instruction when absolute addressing is
169 { 0xfffc, 0, NULL
, NULL
, PPC_OPERAND_ABSOLUTE
| PPC_OPERAND_SIGNED
},
171 /* The BD field in a B form instruction when the - modifier is used.
172 This sets the y bit of the BO field appropriately. */
174 { 0xfffc, 0, insert_bdm
, extract_bdm
,
175 PPC_OPERAND_RELATIVE
| PPC_OPERAND_SIGNED
},
177 /* The BD field in a B form instruction when the - modifier is used
178 and absolute address is used. */
180 { 0xfffc, 0, insert_bdm
, extract_bdm
,
181 PPC_OPERAND_ABSOLUTE
| PPC_OPERAND_SIGNED
},
183 /* The BD field in a B form instruction when the + modifier is used.
184 This sets the y bit of the BO field appropriately. */
186 { 0xfffc, 0, insert_bdp
, extract_bdp
,
187 PPC_OPERAND_RELATIVE
| PPC_OPERAND_SIGNED
},
189 /* The BD field in a B form instruction when the + modifier is used
190 and absolute addressing is used. */
192 { 0xfffc, 0, insert_bdp
, extract_bdp
,
193 PPC_OPERAND_ABSOLUTE
| PPC_OPERAND_SIGNED
},
195 /* The BF field in an X or XL form instruction. */
197 /* The CRFD field in an X form instruction. */
199 /* The CRD field in an XL form instruction. */
201 { 0x7, 23, NULL
, NULL
, PPC_OPERAND_CR_REG
},
203 /* The BF field in an X or XL form instruction. */
205 { 0x7, 23, NULL
, NULL
, 0 },
207 /* An optional BF field. This is used for comparison instructions,
208 in which an omitted BF field is taken as zero. */
210 { 0x7, 23, NULL
, NULL
, PPC_OPERAND_CR_REG
| PPC_OPERAND_OPTIONAL
},
212 /* The BFA field in an X or XL form instruction. */
214 { 0x7, 18, NULL
, NULL
, PPC_OPERAND_CR_REG
},
216 /* The BO field in a B form instruction. Certain values are
219 #define BO_MASK (0x1f << 21)
220 { 0x1f, 21, insert_bo
, extract_bo
, 0 },
222 /* The BO field in a B form instruction when the + or - modifier is
223 used. This is like the BO field, but it must be even. */
225 { 0x1e, 21, insert_boe
, extract_boe
, 0 },
228 { 0x3, 11, NULL
, NULL
, PPC_OPERAND_OPTIONAL
},
230 /* The BT field in an X or XL form instruction. */
232 { 0x1f, 21, NULL
, NULL
, PPC_OPERAND_CR_BIT
},
234 /* The BI16 field in a BD8 form instruction. */
236 { 0x3, 8, NULL
, NULL
, PPC_OPERAND_CR_BIT
},
238 /* The BI32 field in a BD15 form instruction. */
239 #define BI32 BI16 + 1
240 { 0xf, 16, NULL
, NULL
, PPC_OPERAND_CR_BIT
},
242 /* The BO32 field in a BD15 form instruction. */
243 #define BO32 BI32 + 1
244 { 0x3, 20, NULL
, NULL
, 0 },
246 /* The B8 field in a BD8 form instruction. */
248 { 0x1fe, -1, NULL
, NULL
, PPC_OPERAND_RELATIVE
| PPC_OPERAND_SIGNED
},
250 /* The B15 field in a BD15 form instruction. The lowest bit is
253 { 0xfffe, 0, NULL
, NULL
, PPC_OPERAND_RELATIVE
| PPC_OPERAND_SIGNED
},
255 /* The B24 field in a BD24 form instruction. The lowest bit is
258 { 0x1fffffe, 0, NULL
, NULL
, PPC_OPERAND_RELATIVE
| PPC_OPERAND_SIGNED
},
260 /* The condition register number portion of the BI field in a B form
261 or XL form instruction. This is used for the extended
262 conditional branch mnemonics, which set the lower two bits of the
263 BI field. This field is optional. */
265 { 0x7, 18, NULL
, NULL
, PPC_OPERAND_CR_REG
| PPC_OPERAND_OPTIONAL
},
267 /* The CRB field in an X form instruction. */
269 /* The MB field in an M form instruction. */
271 #define MB_MASK (0x1f << 6)
272 { 0x1f, 6, NULL
, NULL
, 0 },
274 /* The CRD32 field in an XL form instruction. */
275 #define CRD32 CRB + 1
276 { 0x3, 21, NULL
, NULL
, PPC_OPERAND_CR_REG
},
278 /* The CRFS field in an X form instruction. */
279 #define CRFS CRD32 + 1
280 { 0x7, 0, NULL
, NULL
, PPC_OPERAND_CR_REG
},
283 { 0x3, 18, NULL
, NULL
, PPC_OPERAND_CR_REG
| PPC_OPERAND_OPTIONAL
},
285 /* The CT field in an X form instruction. */
287 /* The MO field in an mbar instruction. */
289 { 0x1f, 21, NULL
, NULL
, PPC_OPERAND_OPTIONAL
},
291 /* The D field in a D form instruction. This is a displacement off
292 a register, and implies that the next operand is a register in
295 { 0xffff, 0, NULL
, NULL
, PPC_OPERAND_PARENS
| PPC_OPERAND_SIGNED
},
297 /* The D8 field in a D form instruction. This is a displacement off
298 a register, and implies that the next operand is a register in
301 { 0xff, 0, NULL
, NULL
, PPC_OPERAND_PARENS
| PPC_OPERAND_SIGNED
},
303 /* The DQ field in a DQ form instruction. This is like D, but the
304 lower four bits are forced to zero. */
306 { 0xfff0, 0, NULL
, NULL
,
307 PPC_OPERAND_PARENS
| PPC_OPERAND_SIGNED
| PPC_OPERAND_DQ
},
309 /* The DS field in a DS form instruction. This is like D, but the
310 lower two bits are forced to zero. */
312 { 0xfffc, 0, NULL
, NULL
,
313 PPC_OPERAND_PARENS
| PPC_OPERAND_SIGNED
| PPC_OPERAND_DS
},
315 /* The DUIS field in a XFX form instruction, 10 bits unsigned imediate */
317 { 0x3ff, 11, NULL
, NULL
, 0 },
319 /* The E field in a wrteei instruction. */
320 /* And the W bit in the pair singles instructions. */
323 { 0x1, 15, NULL
, NULL
, 0 },
325 /* The FL1 field in a POWER SC form instruction. */
327 /* The U field in an X form instruction. */
329 { 0xf, 12, NULL
, NULL
, 0 },
331 /* The FL2 field in a POWER SC form instruction. */
333 { 0x7, 2, NULL
, NULL
, 0 },
335 /* The FLM field in an XFL form instruction. */
337 { 0xff, 17, NULL
, NULL
, 0 },
339 /* The FRA field in an X or A form instruction. */
341 #define FRA_MASK (0x1f << 16)
342 { 0x1f, 16, NULL
, NULL
, PPC_OPERAND_FPR
},
344 /* The FRAp field of DFP instructions. */
346 { 0x1e, 16, NULL
, NULL
, PPC_OPERAND_FPR
},
348 /* The FRB field in an X or A form instruction. */
350 #define FRB_MASK (0x1f << 11)
351 { 0x1f, 11, NULL
, NULL
, PPC_OPERAND_FPR
},
353 /* The FRBp field of DFP instructions. */
355 { 0x1e, 11, NULL
, NULL
, PPC_OPERAND_FPR
},
357 /* The FRC field in an A form instruction. */
359 #define FRC_MASK (0x1f << 6)
360 { 0x1f, 6, NULL
, NULL
, PPC_OPERAND_FPR
},
362 /* The FRS field in an X form instruction or the FRT field in a D, X
363 or A form instruction. */
366 { 0x1f, 21, NULL
, NULL
, PPC_OPERAND_FPR
},
368 /* The FRSp field of stfdp or the FRTp field of lfdp and DFP
372 { 0x1e, 21, NULL
, NULL
, PPC_OPERAND_FPR
},
374 /* The FXM field in an XFX instruction. */
376 { 0xff, 12, insert_fxm
, extract_fxm
, 0 },
378 /* Power4 version for mfcr. */
380 { 0xff, 12, insert_fxm
, extract_fxm
, PPC_OPERAND_OPTIONAL
},
382 /* The IMM20 field in an LI instruction. */
383 #define IMM20 FXM4 + 1
384 { 0xfffff, PPC_OPSHIFT_INV
, insert_li20
, extract_li20
, PPC_OPERAND_SIGNED
},
386 /* The L field in a D or X form instruction. */
388 { 0x1, 21, NULL
, NULL
, PPC_OPERAND_OPTIONAL
},
390 /* The LEV field in a POWER SVC form instruction. */
391 #define SVC_LEV L + 1
392 { 0x7f, 5, NULL
, NULL
, 0 },
394 /* The LEV field in an SC form instruction. */
395 #define LEV SVC_LEV + 1
396 { 0x7f, 5, NULL
, NULL
, PPC_OPERAND_OPTIONAL
},
398 /* The LI field in an I form instruction. The lower two bits are
401 { 0x3fffffc, 0, NULL
, NULL
, PPC_OPERAND_RELATIVE
| PPC_OPERAND_SIGNED
},
403 /* The LI field in an I form instruction when used as an absolute
406 { 0x3fffffc, 0, NULL
, NULL
, PPC_OPERAND_ABSOLUTE
| PPC_OPERAND_SIGNED
},
408 /* The LS or WC field in an X (sync or wait) form instruction. */
411 { 0x3, 21, NULL
, NULL
, PPC_OPERAND_OPTIONAL
},
413 /* The ME field in an M form instruction. */
415 #define ME_MASK (0x1f << 1)
416 { 0x1f, 1, NULL
, NULL
, 0 },
418 /* The MB and ME fields in an M form instruction expressed a single
419 operand which is a bitmask indicating which bits to select. This
420 is a two operand form using PPC_OPERAND_NEXT. See the
421 description in opcode/ppc.h for what this means. */
423 { 0x1f, 6, NULL
, NULL
, PPC_OPERAND_OPTIONAL
| PPC_OPERAND_NEXT
},
424 { -1, 0, insert_mbe
, extract_mbe
, 0 },
426 /* The MB or ME field in an MD or MDS form instruction. The high
427 bit is wrapped to the low end. */
430 #define MB6_MASK (0x3f << 5)
431 { 0x3f, 5, insert_mb6
, extract_mb6
, 0 },
433 /* The NB field in an X form instruction. The value 32 is stored as
436 { 0x1f, 11, NULL
, extract_nb
, PPC_OPERAND_PLUS1
},
438 /* The NBI field in an lswi instruction, which has special value
439 restrictions. The value 32 is stored as 0. */
441 { 0x1f, 11, insert_nbi
, extract_nb
, PPC_OPERAND_PLUS1
},
443 /* The NSI field in a D form instruction. This is the same as the
444 SI field, only negated. */
446 { 0xffff, 0, insert_nsi
, extract_nsi
,
447 PPC_OPERAND_NEGATIVE
| PPC_OPERAND_SIGNED
},
449 /* The RA field in an D, DS, DQ, X, XO, M, or MDS form instruction. */
451 #define RA_MASK (0x1f << 16)
452 { 0x1f, 16, NULL
, NULL
, PPC_OPERAND_GPR
},
454 /* As above, but 0 in the RA field means zero, not r0. */
456 { 0x1f, 16, NULL
, NULL
, PPC_OPERAND_GPR_0
},
458 /* The RA field in the DQ form lq or an lswx instruction, which have special
459 value restrictions. */
462 { 0x1f, 16, insert_raq
, NULL
, PPC_OPERAND_GPR_0
},
464 /* The RA field in a D or X form instruction which is an updating
465 load, which means that the RA field may not be zero and may not
466 equal the RT field. */
468 { 0x1f, 16, insert_ral
, NULL
, PPC_OPERAND_GPR_0
},
470 /* The RA field in an lmw instruction, which has special value
473 { 0x1f, 16, insert_ram
, NULL
, PPC_OPERAND_GPR_0
},
475 /* The RA field in a D or X form instruction which is an updating
476 store or an updating floating point load, which means that the RA
477 field may not be zero. */
479 { 0x1f, 16, insert_ras
, NULL
, PPC_OPERAND_GPR_0
},
481 /* The RA field of the tlbwe, dccci and iccci instructions,
482 which are optional. */
483 #define RAOPT RAS + 1
484 { 0x1f, 16, NULL
, NULL
, PPC_OPERAND_GPR
| PPC_OPERAND_OPTIONAL
},
486 /* The RB field in an X, XO, M, or MDS form instruction. */
488 #define RB_MASK (0x1f << 11)
489 { 0x1f, 11, NULL
, NULL
, PPC_OPERAND_GPR
},
491 /* The RB field in an X form instruction when it must be the same as
492 the RS field in the instruction. This is used for extended
493 mnemonics like mr. */
495 { 0x1f, 11, insert_rbs
, extract_rbs
, PPC_OPERAND_FAKE
},
497 /* The RB field in an lswx instruction, which has special value
500 { 0x1f, 11, insert_rbx
, NULL
, PPC_OPERAND_GPR
},
502 /* The RB field of the dccci and iccci instructions, which are optional. */
503 #define RBOPT RBX + 1
504 { 0x1f, 11, NULL
, NULL
, PPC_OPERAND_GPR
| PPC_OPERAND_OPTIONAL
},
506 /* The RS field in a D, DS, X, XFX, XS, M, MD or MDS form
507 instruction or the RT field in a D, DS, X, XFX or XO form
511 #define RT_MASK (0x1f << 21)
513 { 0x1f, 21, NULL
, NULL
, PPC_OPERAND_GPR
},
515 /* The RS and RT fields of the DS form stq and DQ form lq instructions,
516 which have special value restrictions. */
519 { 0x1e, 21, NULL
, NULL
, PPC_OPERAND_GPR
},
521 /* The RS field of the tlbwe instruction, which is optional. */
524 { 0x1f, 21, NULL
, NULL
, PPC_OPERAND_GPR
| PPC_OPERAND_OPTIONAL
},
526 /* The RX field of the SE_RR form instruction. */
528 { 0x1f, PPC_OPSHIFT_INV
, insert_rx
, extract_rx
, PPC_OPERAND_GPR
},
530 /* The ARX field of the SE_RR form instruction. */
532 { 0x1f, PPC_OPSHIFT_INV
, insert_arx
, extract_arx
, PPC_OPERAND_GPR
},
534 /* The RY field of the SE_RR form instruction. */
537 { 0x1f, PPC_OPSHIFT_INV
, insert_ry
, extract_ry
, PPC_OPERAND_GPR
},
539 /* The ARY field of the SE_RR form instruction. */
541 { 0x1f, PPC_OPSHIFT_INV
, insert_ary
, extract_ary
, PPC_OPERAND_GPR
},
543 /* The SCLSCI8 field in a D form instruction. */
544 #define SCLSCI8 ARY + 1
545 { 0xffffffff, PPC_OPSHIFT_INV
, insert_sci8
, extract_sci8
, 0 },
547 /* The SCLSCI8N field in a D form instruction. This is the same as the
548 SCLSCI8 field, only negated. */
549 #define SCLSCI8N SCLSCI8 + 1
550 { 0xffffffff, PPC_OPSHIFT_INV
, insert_sci8n
, extract_sci8n
,
551 PPC_OPERAND_NEGATIVE
| PPC_OPERAND_SIGNED
},
553 /* The SD field of the SD4 form instruction. */
554 #define SE_SD SCLSCI8N + 1
555 { 0xf, 8, NULL
, NULL
, PPC_OPERAND_PARENS
},
557 /* The SD field of the SD4 form instruction, for halfword. */
558 #define SE_SDH SE_SD + 1
559 { 0x1e, PPC_OPSHIFT_INV
, insert_sd4h
, extract_sd4h
, PPC_OPERAND_PARENS
},
561 /* The SD field of the SD4 form instruction, for word. */
562 #define SE_SDW SE_SDH + 1
563 { 0x3c, PPC_OPSHIFT_INV
, insert_sd4w
, extract_sd4w
, PPC_OPERAND_PARENS
},
565 /* The SH field in an X or M form instruction. */
566 #define SH SE_SDW + 1
567 #define SH_MASK (0x1f << 11)
568 /* The other UIMM field in a EVX form instruction. */
570 { 0x1f, 11, NULL
, NULL
, 0 },
572 /* The SH field in an MD form instruction. This is split. */
574 #define SH6_MASK ((0x1f << 11) | (1 << 1))
575 { 0x3f, PPC_OPSHIFT_INV
, insert_sh6
, extract_sh6
, 0 },
577 /* The SH field of the tlbwe instruction, which is optional. */
579 { 0x1f, 11, NULL
, NULL
, PPC_OPERAND_OPTIONAL
},
581 /* The SI field in a D form instruction. */
583 { 0xffff, 0, NULL
, NULL
, PPC_OPERAND_SIGNED
},
585 /* The SI field in a D form instruction when we accept a wide range
586 of positive values. */
587 #define SISIGNOPT SI + 1
588 { 0xffff, 0, NULL
, NULL
, PPC_OPERAND_SIGNED
| PPC_OPERAND_SIGNOPT
},
590 /* The SI8 field in a D form instruction. */
591 #define SI8 SISIGNOPT + 1
592 { 0xff, 0, NULL
, NULL
, PPC_OPERAND_SIGNED
},
594 /* The SPR field in an XFX form instruction. This is flipped--the
595 lower 5 bits are stored in the upper 5 and vice- versa. */
599 #define SPR_MASK (0x3ff << 11)
600 { 0x3ff, 11, insert_spr
, extract_spr
, 0 },
602 /* The BAT index number in an XFX form m[ft]ibat[lu] instruction. */
603 #define SPRBAT SPR + 1
604 #define SPRBAT_MASK (0x3 << 17)
605 { 0x3, 17, NULL
, NULL
, 0 },
607 /* The SPRG register number in an XFX form m[ft]sprg instruction. */
608 #define SPRG SPRBAT + 1
609 { 0x1f, 16, insert_sprg
, extract_sprg
, 0 },
611 /* The SR field in an X form instruction. */
613 /* The 4-bit UIMM field in a VX form instruction. */
615 { 0xf, 16, NULL
, NULL
, 0 },
617 /* The STRM field in an X AltiVec form instruction. */
619 /* The T field in a tlbilx form instruction. */
621 { 0x3, 21, NULL
, NULL
, 0 },
623 /* The ESYNC field in an X (sync) form instruction. */
624 #define ESYNC STRM + 1
625 { 0xf, 16, insert_ls
, NULL
, PPC_OPERAND_OPTIONAL
},
627 /* The SV field in a POWER SC form instruction. */
629 { 0x3fff, 2, NULL
, NULL
, 0 },
631 /* The TBR field in an XFX form instruction. This is like the SPR
632 field, but it is optional. */
634 { 0x3ff, 11, insert_tbr
, extract_tbr
, PPC_OPERAND_OPTIONAL
},
636 /* The TO field in a D or X form instruction. */
639 #define TO_MASK (0x1f << 21)
640 { 0x1f, 21, NULL
, NULL
, 0 },
642 /* The UI field in a D form instruction. */
644 { 0xffff, 0, NULL
, NULL
, 0 },
646 /* The IMM field in an SE_IM5 instruction. */
648 { 0x1f, 4, NULL
, NULL
, 0 },
650 /* The OIMM field in an SE_OIM5 instruction. */
651 #define OIMM5 UI5 + 1
652 { 0x1f, PPC_OPSHIFT_INV
, insert_oimm
, extract_oimm
, PPC_OPERAND_PLUS1
},
654 /* The UI7 field in an SE_LI instruction. */
655 #define UI7 OIMM5 + 1
656 { 0x7f, 4, NULL
, NULL
, 0 },
658 /* The VA field in a VA, VX or VXR form instruction. */
660 { 0x1f, 16, NULL
, NULL
, PPC_OPERAND_VR
},
662 /* The VB field in a VA, VX or VXR form instruction. */
664 { 0x1f, 11, NULL
, NULL
, PPC_OPERAND_VR
},
666 /* The VC field in a VA form instruction. */
668 { 0x1f, 6, NULL
, NULL
, PPC_OPERAND_VR
},
670 /* The VD or VS field in a VA, VX, VXR or X form instruction. */
673 { 0x1f, 21, NULL
, NULL
, PPC_OPERAND_VR
},
675 /* The SIMM field in a VX form instruction, and TE in Z form. */
678 { 0x1f, 16, NULL
, NULL
, PPC_OPERAND_SIGNED
},
680 /* The UIMM field in a VX form instruction. */
681 #define UIMM SIMM + 1
683 { 0x1f, 16, NULL
, NULL
, 0 },
685 /* The 3-bit UIMM field in a VX form instruction. */
686 #define UIMM3 UIMM + 1
687 { 0x7, 16, NULL
, NULL
, 0 },
689 /* The SHB field in a VA form instruction. */
690 #define SHB UIMM3 + 1
691 { 0xf, 6, NULL
, NULL
, 0 },
693 /* The other UIMM field in a half word EVX form instruction. */
694 #define EVUIMM_2 SHB + 1
695 { 0x3e, 10, NULL
, NULL
, PPC_OPERAND_PARENS
},
697 /* The other UIMM field in a word EVX form instruction. */
698 #define EVUIMM_4 EVUIMM_2 + 1
699 { 0x7c, 9, NULL
, NULL
, PPC_OPERAND_PARENS
},
701 /* The other UIMM field in a double EVX form instruction. */
702 #define EVUIMM_8 EVUIMM_4 + 1
703 { 0xf8, 8, NULL
, NULL
, PPC_OPERAND_PARENS
},
706 #define WS EVUIMM_8 + 1
707 { 0x7, 11, NULL
, NULL
, 0 },
709 /* PowerPC paired singles extensions. */
710 /* W bit in the pair singles instructions for x type instructions. */
712 /* The BO16 field in a BD8 form instruction. */
714 { 0x1, 10, 0, 0, 0 },
716 /* IDX bits for quantization in the pair singles instructions. */
718 { 0x7, 12, 0, 0, 0 },
720 /* IDX bits for quantization in the pair singles x-type instructions. */
724 /* Smaller D field for quantization in the pair singles instructions. */
726 { 0xfff, 0, 0, 0, PPC_OPERAND_PARENS
| PPC_OPERAND_SIGNED
},
731 { 0x1, 16, NULL
, NULL
, PPC_OPERAND_OPTIONAL
},
733 #define RMC MTMSRD_L + 1
734 { 0x3, 9, NULL
, NULL
, 0 },
737 { 0x1, 16, NULL
, NULL
, 0 },
740 { 0x3, 19, NULL
, NULL
, 0 },
743 { 0x1, 20, NULL
, NULL
, 0 },
745 /* SH field starting at bit position 16. */
747 /* The DCM and DGM fields in a Z form instruction. */
750 { 0x3f, 10, NULL
, NULL
, 0 },
752 /* The EH field in larx instruction. */
754 { 0x1, 0, NULL
, NULL
, PPC_OPERAND_OPTIONAL
},
756 /* The L field in an mtfsf or XFL form instruction. */
758 { 0x1, 25, NULL
, NULL
, PPC_OPERAND_OPTIONAL
},
760 /* Xilinx APU related masks and macros */
761 #define FCRT XFL_L + 1
762 #define FCRT_MASK (0x1f << 21)
763 { 0x1f, 21, 0, 0, PPC_OPERAND_FCR
},
765 /* Xilinx FSL related masks and macros */
767 #define FSL_MASK (0x1f << 11)
768 { 0x1f, 11, 0, 0, PPC_OPERAND_FSL
},
770 /* Xilinx UDI related masks and macros */
772 { 0x1f, 21, 0, 0, PPC_OPERAND_UDI
},
775 { 0x1f, 16, 0, 0, PPC_OPERAND_UDI
},
778 { 0x1f, 11, 0, 0, PPC_OPERAND_UDI
},
781 { 0x1f, 6, 0, 0, PPC_OPERAND_UDI
},
783 /* The VLESIMM field in a D form instruction. */
784 #define VLESIMM URC + 1
785 { 0xffff, PPC_OPSHIFT_INV
, insert_vlesi
, extract_vlesi
,
786 PPC_OPERAND_SIGNED
| PPC_OPERAND_SIGNOPT
},
788 /* The VLENSIMM field in a D form instruction. */
789 #define VLENSIMM VLESIMM + 1
790 { 0xffff, PPC_OPSHIFT_INV
, insert_vlensi
, extract_vlensi
,
791 PPC_OPERAND_NEGATIVE
| PPC_OPERAND_SIGNED
| PPC_OPERAND_SIGNOPT
},
793 /* The VLEUIMM field in a D form instruction. */
794 #define VLEUIMM VLENSIMM + 1
795 { 0xffff, PPC_OPSHIFT_INV
, insert_vleui
, extract_vleui
, 0 },
797 /* The VLEUIMML field in a D form instruction. */
798 #define VLEUIMML VLEUIMM + 1
799 { 0xffff, PPC_OPSHIFT_INV
, insert_vleil
, extract_vleil
, 0 },
801 /* The XT and XS fields in an XX1 or XX3 form instruction. This is split. */
802 #define XS6 VLEUIMML + 1
804 { 0x3f, PPC_OPSHIFT_INV
, insert_xt6
, extract_xt6
, PPC_OPERAND_VSR
},
806 /* The XA field in an XX3 form instruction. This is split. */
808 { 0x3f, PPC_OPSHIFT_INV
, insert_xa6
, extract_xa6
, PPC_OPERAND_VSR
},
810 /* The XB field in an XX2 or XX3 form instruction. This is split. */
812 { 0x3f, PPC_OPSHIFT_INV
, insert_xb6
, extract_xb6
, PPC_OPERAND_VSR
},
814 /* The XB field in an XX3 form instruction when it must be the same as
815 the XA field in the instruction. This is used in extended mnemonics
816 like xvmovdp. This is split. */
818 { 0x3f, PPC_OPSHIFT_INV
, insert_xb6s
, extract_xb6s
, PPC_OPERAND_FAKE
},
820 /* The XC field in an XX4 form instruction. This is split. */
822 { 0x3f, PPC_OPSHIFT_INV
, insert_xc6
, extract_xc6
, PPC_OPERAND_VSR
},
824 /* The DM or SHW field in an XX3 form instruction. */
827 { 0x3, 8, NULL
, NULL
, 0 },
829 /* The DM field in an extended mnemonic XX3 form instruction. */
831 { 0x3, 8, insert_dm
, extract_dm
, 0 },
833 /* The UIM field in an XX2 form instruction. */
835 /* The 2-bit UIMM field in a VX form instruction. */
837 { 0x3, 16, NULL
, NULL
, 0 },
839 #define ERAT_T UIM + 1
840 { 0x7, 21, NULL
, NULL
, 0 },
843 const unsigned int num_powerpc_operands
= (sizeof (powerpc_operands
)
844 / sizeof (powerpc_operands
[0]));
846 /* The functions used to insert and extract complicated operands. */
848 /* The ARX, ARY, RX and RY operands are alternate encodings of GPRs. */
851 insert_arx (unsigned long insn
,
853 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
854 const char **errmsg ATTRIBUTE_UNUSED
)
856 if (value
>= 8 && value
< 24)
857 return insn
| ((value
- 8) & 0xf);
860 *errmsg
= _("invalid register");
866 extract_arx (unsigned long insn
,
867 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
868 int *invalid ATTRIBUTE_UNUSED
)
870 return (insn
& 0xf) + 8;
874 insert_ary (unsigned long insn
,
876 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
877 const char **errmsg ATTRIBUTE_UNUSED
)
879 if (value
>= 8 && value
< 24)
880 return insn
| (((value
- 8) & 0xf) << 4);
883 *errmsg
= _("invalid register");
889 extract_ary (unsigned long insn
,
890 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
891 int *invalid ATTRIBUTE_UNUSED
)
893 return ((insn
>> 4) & 0xf) + 8;
897 insert_rx (unsigned long insn
,
899 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
902 if (value
>= 0 && value
< 8)
904 else if (value
>= 24 && value
<= 31)
905 return insn
| (value
- 16);
908 *errmsg
= _("invalid register");
914 extract_rx (unsigned long insn
,
915 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
916 int *invalid ATTRIBUTE_UNUSED
)
918 int value
= insn
& 0xf;
919 if (value
>= 0 && value
< 8)
926 insert_ry (unsigned long insn
,
928 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
931 if (value
>= 0 && value
< 8)
932 return insn
| (value
<< 4);
933 else if (value
>= 24 && value
<= 31)
934 return insn
| ((value
- 16) << 4);
937 *errmsg
= _("invalid register");
943 extract_ry (unsigned long insn
,
944 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
945 int *invalid ATTRIBUTE_UNUSED
)
947 int value
= (insn
>> 4) & 0xf;
948 if (value
>= 0 && value
< 8)
954 /* The BA field in an XL form instruction when it must be the same as
955 the BT field in the same instruction. This operand is marked FAKE.
956 The insertion function just copies the BT field into the BA field,
957 and the extraction function just checks that the fields are the
961 insert_bat (unsigned long insn
,
962 long value ATTRIBUTE_UNUSED
,
963 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
964 const char **errmsg ATTRIBUTE_UNUSED
)
966 return insn
| (((insn
>> 21) & 0x1f) << 16);
970 extract_bat (unsigned long insn
,
971 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
974 if (((insn
>> 21) & 0x1f) != ((insn
>> 16) & 0x1f))
979 /* The BB field in an XL form instruction when it must be the same as
980 the BA field in the same instruction. This operand is marked FAKE.
981 The insertion function just copies the BA field into the BB field,
982 and the extraction function just checks that the fields are the
986 insert_bba (unsigned long insn
,
987 long value ATTRIBUTE_UNUSED
,
988 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
989 const char **errmsg ATTRIBUTE_UNUSED
)
991 return insn
| (((insn
>> 16) & 0x1f) << 11);
995 extract_bba (unsigned long insn
,
996 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
999 if (((insn
>> 16) & 0x1f) != ((insn
>> 11) & 0x1f))
1004 /* The BD field in a B form instruction when the - modifier is used.
1005 This modifier means that the branch is not expected to be taken.
1006 For chips built to versions of the architecture prior to version 2
1007 (ie. not Power4 compatible), we set the y bit of the BO field to 1
1008 if the offset is negative. When extracting, we require that the y
1009 bit be 1 and that the offset be positive, since if the y bit is 0
1010 we just want to print the normal form of the instruction.
1011 Power4 compatible targets use two bits, "a", and "t", instead of
1012 the "y" bit. "at" == 00 => no hint, "at" == 01 => unpredictable,
1013 "at" == 10 => not taken, "at" == 11 => taken. The "t" bit is 00001
1014 in BO field, the "a" bit is 00010 for branch on CR(BI) and 01000
1015 for branch on CTR. We only handle the taken/not-taken hint here.
1016 Note that we don't relax the conditions tested here when
1017 disassembling with -Many because insns using extract_bdm and
1018 extract_bdp always occur in pairs. One or the other will always
1021 #define ISA_V2 (PPC_OPCODE_POWER4 | PPC_OPCODE_E500MC | PPC_OPCODE_TITAN)
1023 static unsigned long
1024 insert_bdm (unsigned long insn
,
1027 const char **errmsg ATTRIBUTE_UNUSED
)
1029 if ((dialect
& ISA_V2
) == 0)
1031 if ((value
& 0x8000) != 0)
1036 if ((insn
& (0x14 << 21)) == (0x04 << 21))
1038 else if ((insn
& (0x14 << 21)) == (0x10 << 21))
1041 return insn
| (value
& 0xfffc);
1045 extract_bdm (unsigned long insn
,
1049 if ((dialect
& ISA_V2
) == 0)
1051 if (((insn
& (1 << 21)) == 0) != ((insn
& (1 << 15)) == 0))
1056 if ((insn
& (0x17 << 21)) != (0x06 << 21)
1057 && (insn
& (0x1d << 21)) != (0x18 << 21))
1061 return ((insn
& 0xfffc) ^ 0x8000) - 0x8000;
1064 /* The BD field in a B form instruction when the + modifier is used.
1065 This is like BDM, above, except that the branch is expected to be
1068 static unsigned long
1069 insert_bdp (unsigned long insn
,
1072 const char **errmsg ATTRIBUTE_UNUSED
)
1074 if ((dialect
& ISA_V2
) == 0)
1076 if ((value
& 0x8000) == 0)
1081 if ((insn
& (0x14 << 21)) == (0x04 << 21))
1083 else if ((insn
& (0x14 << 21)) == (0x10 << 21))
1086 return insn
| (value
& 0xfffc);
1090 extract_bdp (unsigned long insn
,
1094 if ((dialect
& ISA_V2
) == 0)
1096 if (((insn
& (1 << 21)) == 0) == ((insn
& (1 << 15)) == 0))
1101 if ((insn
& (0x17 << 21)) != (0x07 << 21)
1102 && (insn
& (0x1d << 21)) != (0x19 << 21))
1106 return ((insn
& 0xfffc) ^ 0x8000) - 0x8000;
1110 valid_bo_pre_v2 (long value
)
1112 /* Certain encodings have bits that are required to be zero.
1113 These are (z must be zero, y may be anything):
1124 if ((value
& 0x14) == 0)
1126 else if ((value
& 0x14) == 0x4)
1127 return (value
& 0x2) == 0;
1128 else if ((value
& 0x14) == 0x10)
1129 return (value
& 0x8) == 0;
1131 return value
== 0x14;
1135 valid_bo_post_v2 (long value
)
1137 /* Certain encodings have bits that are required to be zero.
1138 These are (z must be zero, a & t may be anything):
1149 if ((value
& 0x14) == 0)
1150 return (value
& 0x1) == 0;
1151 else if ((value
& 0x14) == 0x14)
1152 return value
== 0x14;
1157 /* Check for legal values of a BO field. */
1160 valid_bo (long value
, ppc_cpu_t dialect
, int extract
)
1162 int valid_y
= valid_bo_pre_v2 (value
);
1163 int valid_at
= valid_bo_post_v2 (value
);
1165 /* When disassembling with -Many, accept either encoding on the
1166 second pass through opcodes. */
1167 if (extract
&& dialect
== ~(ppc_cpu_t
) PPC_OPCODE_ANY
)
1168 return valid_y
|| valid_at
;
1169 if ((dialect
& ISA_V2
) == 0)
1175 /* The BO field in a B form instruction. Warn about attempts to set
1176 the field to an illegal value. */
1178 static unsigned long
1179 insert_bo (unsigned long insn
,
1182 const char **errmsg
)
1184 if (!valid_bo (value
, dialect
, 0))
1185 *errmsg
= _("invalid conditional option");
1186 else if (PPC_OP (insn
) == 19 && (insn
& 0x400) && ! (value
& 4))
1187 *errmsg
= _("invalid counter access");
1188 return insn
| ((value
& 0x1f) << 21);
1192 extract_bo (unsigned long insn
,
1198 value
= (insn
>> 21) & 0x1f;
1199 if (!valid_bo (value
, dialect
, 1))
1204 /* The BO field in a B form instruction when the + or - modifier is
1205 used. This is like the BO field, but it must be even. When
1206 extracting it, we force it to be even. */
1208 static unsigned long
1209 insert_boe (unsigned long insn
,
1212 const char **errmsg
)
1214 if (!valid_bo (value
, dialect
, 0))
1215 *errmsg
= _("invalid conditional option");
1216 else if (PPC_OP (insn
) == 19 && (insn
& 0x400) && ! (value
& 4))
1217 *errmsg
= _("invalid counter access");
1218 else if ((value
& 1) != 0)
1219 *errmsg
= _("attempt to set y bit when using + or - modifier");
1221 return insn
| ((value
& 0x1f) << 21);
1225 extract_boe (unsigned long insn
,
1231 value
= (insn
>> 21) & 0x1f;
1232 if (!valid_bo (value
, dialect
, 1))
1234 return value
& 0x1e;
1237 /* FXM mask in mfcr and mtcrf instructions. */
1239 static unsigned long
1240 insert_fxm (unsigned long insn
,
1243 const char **errmsg
)
1245 /* If we're handling the mfocrf and mtocrf insns ensure that exactly
1246 one bit of the mask field is set. */
1247 if ((insn
& (1 << 20)) != 0)
1249 if (value
== 0 || (value
& -value
) != value
)
1251 *errmsg
= _("invalid mask field");
1256 /* If the optional field on mfcr is missing that means we want to use
1257 the old form of the instruction that moves the whole cr. In that
1258 case we'll have VALUE zero. There doesn't seem to be a way to
1259 distinguish this from the case where someone writes mfcr %r3,0. */
1260 else if (value
== 0)
1263 /* If only one bit of the FXM field is set, we can use the new form
1264 of the instruction, which is faster. Unlike the Power4 branch hint
1265 encoding, this is not backward compatible. Do not generate the
1266 new form unless -mpower4 has been given, or -many and the two
1267 operand form of mfcr was used. */
1268 else if ((value
& -value
) == value
1269 && ((dialect
& PPC_OPCODE_POWER4
) != 0
1270 || ((dialect
& PPC_OPCODE_ANY
) != 0
1271 && (insn
& (0x3ff << 1)) == 19 << 1)))
1274 /* Any other value on mfcr is an error. */
1275 else if ((insn
& (0x3ff << 1)) == 19 << 1)
1277 *errmsg
= _("ignoring invalid mfcr mask");
1281 return insn
| ((value
& 0xff) << 12);
1285 extract_fxm (unsigned long insn
,
1286 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1289 long mask
= (insn
>> 12) & 0xff;
1291 /* Is this a Power4 insn? */
1292 if ((insn
& (1 << 20)) != 0)
1294 /* Exactly one bit of MASK should be set. */
1295 if (mask
== 0 || (mask
& -mask
) != mask
)
1299 /* Check that non-power4 form of mfcr has a zero MASK. */
1300 else if ((insn
& (0x3ff << 1)) == 19 << 1)
1309 static unsigned long
1310 insert_li20 (unsigned long insn
,
1312 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1313 const char **errmsg ATTRIBUTE_UNUSED
)
1315 return insn
| ((value
& 0xf0000) >> 5) | ((value
& 0x0f800) << 5) | (value
& 0x7ff);
1319 extract_li20 (unsigned long insn
,
1320 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1321 int *invalid ATTRIBUTE_UNUSED
)
1323 long ext
= ((insn
& 0x4000) == 0x4000) ? 0xfff00000 : 0x00000000;
1326 | (((insn
>> 11) & 0xf) << 16)
1327 | (((insn
>> 17) & 0xf) << 12)
1328 | (((insn
>> 16) & 0x1) << 11)
1332 /* The LS field in a sync instruction that accepts 2 operands
1333 Values 2 and 3 are reserved,
1334 must be treated as 0 for future compatibility
1335 Values 0 and 1 can be accepted, if field ESYNC is zero
1336 Otherwise L = complement of ESYNC-bit2 (1<<18) */
1338 static unsigned long
1339 insert_ls (unsigned long insn
,
1341 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1342 const char **errmsg ATTRIBUTE_UNUSED
)
1346 ls
= (insn
>> 21) & 0x03;
1350 return insn
& ~(0x3 << 21);
1353 if ((value
& 0x2) != 0)
1354 return (insn
& ~(0x3 << 21)) | ((value
& 0xf) << 16);
1355 return (insn
& ~(0x3 << 21)) | (0x1 << 21) | ((value
& 0xf) << 16);
1358 /* The MB and ME fields in an M form instruction expressed as a single
1359 operand which is itself a bitmask. The extraction function always
1360 marks it as invalid, since we never want to recognize an
1361 instruction which uses a field of this type. */
1363 static unsigned long
1364 insert_mbe (unsigned long insn
,
1366 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1367 const char **errmsg
)
1369 unsigned long uval
, mask
;
1370 int mb
, me
, mx
, count
, last
;
1376 *errmsg
= _("illegal bitmask");
1382 if ((uval
& 1) != 0)
1388 /* mb: location of last 0->1 transition */
1389 /* me: location of last 1->0 transition */
1390 /* count: # transitions */
1392 for (mx
= 0, mask
= 1L << 31; mx
< 32; ++mx
, mask
>>= 1)
1394 if ((uval
& mask
) && !last
)
1400 else if (!(uval
& mask
) && last
)
1410 if (count
!= 2 && (count
!= 0 || ! last
))
1411 *errmsg
= _("illegal bitmask");
1413 return insn
| (mb
<< 6) | ((me
- 1) << 1);
1417 extract_mbe (unsigned long insn
,
1418 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1427 mb
= (insn
>> 6) & 0x1f;
1428 me
= (insn
>> 1) & 0x1f;
1432 for (i
= mb
; i
<= me
; i
++)
1433 ret
|= 1L << (31 - i
);
1435 else if (mb
== me
+ 1)
1437 else /* (mb > me + 1) */
1440 for (i
= me
+ 1; i
< mb
; i
++)
1441 ret
&= ~(1L << (31 - i
));
1446 /* The MB or ME field in an MD or MDS form instruction. The high bit
1447 is wrapped to the low end. */
1449 static unsigned long
1450 insert_mb6 (unsigned long insn
,
1452 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1453 const char **errmsg ATTRIBUTE_UNUSED
)
1455 return insn
| ((value
& 0x1f) << 6) | (value
& 0x20);
1459 extract_mb6 (unsigned long insn
,
1460 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1461 int *invalid ATTRIBUTE_UNUSED
)
1463 return ((insn
>> 6) & 0x1f) | (insn
& 0x20);
1466 /* The NB field in an X form instruction. The value 32 is stored as
1470 extract_nb (unsigned long insn
,
1471 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1472 int *invalid ATTRIBUTE_UNUSED
)
1476 ret
= (insn
>> 11) & 0x1f;
1482 /* The NB field in an lswi instruction, which has special value
1483 restrictions. The value 32 is stored as 0. */
1485 static unsigned long
1486 insert_nbi (unsigned long insn
,
1488 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1489 const char **errmsg ATTRIBUTE_UNUSED
)
1491 long rtvalue
= (insn
& RT_MASK
) >> 21;
1492 long ravalue
= (insn
& RA_MASK
) >> 16;
1496 if (rtvalue
+ (value
+ 3) / 4 > (rtvalue
> ravalue
? ravalue
+ 32
1498 *errmsg
= _("address register in load range");
1499 return insn
| ((value
& 0x1f) << 11);
1502 /* The NSI field in a D form instruction. This is the same as the SI
1503 field, only negated. The extraction function always marks it as
1504 invalid, since we never want to recognize an instruction which uses
1505 a field of this type. */
1507 static unsigned long
1508 insert_nsi (unsigned long insn
,
1510 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1511 const char **errmsg ATTRIBUTE_UNUSED
)
1513 return insn
| (-value
& 0xffff);
1517 extract_nsi (unsigned long insn
,
1518 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1522 return -(((insn
& 0xffff) ^ 0x8000) - 0x8000);
1525 /* The RA field in a D or X form instruction which is an updating
1526 load, which means that the RA field may not be zero and may not
1527 equal the RT field. */
1529 static unsigned long
1530 insert_ral (unsigned long insn
,
1532 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1533 const char **errmsg
)
1536 || (unsigned long) value
== ((insn
>> 21) & 0x1f))
1537 *errmsg
= "invalid register operand when updating";
1538 return insn
| ((value
& 0x1f) << 16);
1541 /* The RA field in an lmw instruction, which has special value
1544 static unsigned long
1545 insert_ram (unsigned long insn
,
1547 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1548 const char **errmsg
)
1550 if ((unsigned long) value
>= ((insn
>> 21) & 0x1f))
1551 *errmsg
= _("index register in load range");
1552 return insn
| ((value
& 0x1f) << 16);
1555 /* The RA field in the DQ form lq or an lswx instruction, which have special
1556 value restrictions. */
1558 static unsigned long
1559 insert_raq (unsigned long insn
,
1561 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1562 const char **errmsg
)
1564 long rtvalue
= (insn
& RT_MASK
) >> 21;
1566 if (value
== rtvalue
)
1567 *errmsg
= _("source and target register operands must be different");
1568 return insn
| ((value
& 0x1f) << 16);
1571 /* The RA field in a D or X form instruction which is an updating
1572 store or an updating floating point load, which means that the RA
1573 field may not be zero. */
1575 static unsigned long
1576 insert_ras (unsigned long insn
,
1578 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1579 const char **errmsg
)
1582 *errmsg
= _("invalid register operand when updating");
1583 return insn
| ((value
& 0x1f) << 16);
1586 /* The RB field in an X form instruction when it must be the same as
1587 the RS field in the instruction. This is used for extended
1588 mnemonics like mr. This operand is marked FAKE. The insertion
1589 function just copies the BT field into the BA field, and the
1590 extraction function just checks that the fields are the same. */
1592 static unsigned long
1593 insert_rbs (unsigned long insn
,
1594 long value ATTRIBUTE_UNUSED
,
1595 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1596 const char **errmsg ATTRIBUTE_UNUSED
)
1598 return insn
| (((insn
>> 21) & 0x1f) << 11);
1602 extract_rbs (unsigned long insn
,
1603 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1606 if (((insn
>> 21) & 0x1f) != ((insn
>> 11) & 0x1f))
1611 /* The RB field in an lswx instruction, which has special value
1614 static unsigned long
1615 insert_rbx (unsigned long insn
,
1617 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1618 const char **errmsg
)
1620 long rtvalue
= (insn
& RT_MASK
) >> 21;
1622 if (value
== rtvalue
)
1623 *errmsg
= _("source and target register operands must be different");
1624 return insn
| ((value
& 0x1f) << 11);
1627 /* The SCI8 field is made up of SCL and {U,N}I8 fields. */
1628 static unsigned long
1629 insert_sci8 (unsigned long insn
,
1631 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1632 const char **errmsg
)
1635 int scale_factor
= 0;
1638 if ((value
& 0xff000000) == (unsigned int) value
)
1644 else if ((value
& 0xff0000) == (unsigned int) value
)
1650 else if ((value
& 0xff00) == (unsigned int) value
)
1656 else if ((value
& 0xff) == value
)
1662 else if ((value
& 0xffffff00) == 0xffffff00)
1665 ui8
= (value
& 0xff);
1668 else if ((value
& 0xffff00ff) == 0xffff00ff)
1671 ui8
= (value
& 0xff00) >> 8;
1674 else if ((value
& 0xff00ffff) == 0xff00ffff)
1677 ui8
= (value
& 0xff0000) >> 16;
1680 else if ((value
& 0x00ffffff) == 0x00ffffff)
1683 ui8
= (value
& 0xff000000) >> 24;
1687 *errmsg
= _("illegal immediate value");
1689 return insn
| (fill
<< 10) | (scale_factor
<< 8) | (ui8
& 0xff);
1693 extract_sci8 (unsigned long insn
,
1694 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1695 int *invalid ATTRIBUTE_UNUSED
)
1697 int scale_factor
, fill
;
1698 scale_factor
= (insn
& 0x300) >> 8;
1699 fill
= (insn
& 0x00000400) >> 10;
1702 return (insn
& 0xff) << (scale_factor
<< 3);
1705 if (scale_factor
== 0)
1706 return (insn
& 0xff) | 0xffffff00;
1707 else if (scale_factor
== 1)
1708 return 0xffff00ff | ((insn
& 0xff) << (scale_factor
<< 3));
1709 else if (scale_factor
== 2)
1710 return 0xff00ffff | (insn
& 0xff << (scale_factor
<< 3));
1711 else /* scale_factor 3 */
1712 return 0x00ffffff | (insn
& 0xff << (scale_factor
<< 3));
1715 static unsigned long
1716 insert_sci8n (unsigned long insn
,
1718 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1719 const char **errmsg
)
1721 insn
= insert_sci8 (insn
, -(value
& 0xff) & 0xff, 0, errmsg
);
1722 /* Set the F bit. */
1723 return insn
| 0x400;
1727 extract_sci8n (unsigned long insn
,
1728 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1729 int *invalid ATTRIBUTE_UNUSED
)
1732 scale_factor
= (insn
& 0x300) >> 8;
1733 return -(((insn
& 0xff) ^ 0x80) - 0x80) << (scale_factor
<< 3);
1736 static unsigned long
1737 insert_sd4h (unsigned long insn
,
1739 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1740 const char **errmsg ATTRIBUTE_UNUSED
)
1742 return insn
| ((value
& 0x1e) << 7);
1746 extract_sd4h (unsigned long insn
,
1747 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1748 int *invalid ATTRIBUTE_UNUSED
)
1750 return ((insn
>> 8) & 0xf) << 1;
1753 static unsigned long
1754 insert_sd4w (unsigned long insn
,
1756 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1757 const char **errmsg ATTRIBUTE_UNUSED
)
1759 return insn
| ((value
& 0x3c) << 6);
1763 extract_sd4w (unsigned long insn
,
1764 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1765 int *invalid ATTRIBUTE_UNUSED
)
1767 return ((insn
>> 8) & 0xf) << 2;
1770 static unsigned long
1771 insert_oimm (unsigned long insn
,
1773 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1774 const char **errmsg ATTRIBUTE_UNUSED
)
1776 return insn
| (((value
- 1) & 0x1f) << 4);
1780 extract_oimm (unsigned long insn
,
1781 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1782 int *invalid ATTRIBUTE_UNUSED
)
1784 return ((insn
>> 4) & 0x1f) + 1;
1787 /* The SH field in an MD form instruction. This is split. */
1789 static unsigned long
1790 insert_sh6 (unsigned long insn
,
1792 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1793 const char **errmsg ATTRIBUTE_UNUSED
)
1795 return insn
| ((value
& 0x1f) << 11) | ((value
& 0x20) >> 4);
1799 extract_sh6 (unsigned long insn
,
1800 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1801 int *invalid ATTRIBUTE_UNUSED
)
1803 return ((insn
>> 11) & 0x1f) | ((insn
<< 4) & 0x20);
1806 /* The SPR field in an XFX form instruction. This is flipped--the
1807 lower 5 bits are stored in the upper 5 and vice- versa. */
1809 static unsigned long
1810 insert_spr (unsigned long insn
,
1812 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1813 const char **errmsg ATTRIBUTE_UNUSED
)
1815 return insn
| ((value
& 0x1f) << 16) | ((value
& 0x3e0) << 6);
1819 extract_spr (unsigned long insn
,
1820 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1821 int *invalid ATTRIBUTE_UNUSED
)
1823 return ((insn
>> 16) & 0x1f) | ((insn
>> 6) & 0x3e0);
1826 /* Some dialects have 8 SPRG registers instead of the standard 4. */
1827 #define ALLOW8_SPRG (PPC_OPCODE_BOOKE | PPC_OPCODE_405 | PPC_OPCODE_VLE)
1829 static unsigned long
1830 insert_sprg (unsigned long insn
,
1833 const char **errmsg
)
1836 || (value
> 3 && (dialect
& ALLOW8_SPRG
) == 0))
1837 *errmsg
= _("invalid sprg number");
1839 /* If this is mfsprg4..7 then use spr 260..263 which can be read in
1840 user mode. Anything else must use spr 272..279. */
1841 if (value
<= 3 || (insn
& 0x100) != 0)
1844 return insn
| ((value
& 0x17) << 16);
1848 extract_sprg (unsigned long insn
,
1852 unsigned long val
= (insn
>> 16) & 0x1f;
1854 /* mfsprg can use 260..263 and 272..279. mtsprg only uses spr 272..279
1855 If not BOOKE, 405 or VLE, then both use only 272..275. */
1856 if ((val
- 0x10 > 3 && (dialect
& ALLOW8_SPRG
) == 0)
1857 || (val
- 0x10 > 7 && (insn
& 0x100) != 0)
1864 /* The TBR field in an XFX instruction. This is just like SPR, but it
1865 is optional. When TBR is omitted, it must be inserted as 268 (the
1866 magic number of the TB register). These functions treat 0
1867 (indicating an omitted optional operand) as 268. This means that
1868 ``mftb 4,0'' is not handled correctly. This does not matter very
1869 much, since the architecture manual does not define mftb as
1870 accepting any values other than 268 or 269. */
1874 static unsigned long
1875 insert_tbr (unsigned long insn
,
1877 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1878 const char **errmsg ATTRIBUTE_UNUSED
)
1882 return insn
| ((value
& 0x1f) << 16) | ((value
& 0x3e0) << 6);
1886 extract_tbr (unsigned long insn
,
1887 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1888 int *invalid ATTRIBUTE_UNUSED
)
1892 ret
= ((insn
>> 16) & 0x1f) | ((insn
>> 6) & 0x3e0);
1898 /* The XT and XS fields in an XX1 or XX3 form instruction. This is split. */
1900 static unsigned long
1901 insert_xt6 (unsigned long insn
,
1903 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1904 const char **errmsg ATTRIBUTE_UNUSED
)
1906 return insn
| ((value
& 0x1f) << 21) | ((value
& 0x20) >> 5);
1910 extract_xt6 (unsigned long insn
,
1911 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1912 int *invalid ATTRIBUTE_UNUSED
)
1914 return ((insn
<< 5) & 0x20) | ((insn
>> 21) & 0x1f);
1917 /* The XA field in an XX3 form instruction. This is split. */
1919 static unsigned long
1920 insert_xa6 (unsigned long insn
,
1922 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1923 const char **errmsg ATTRIBUTE_UNUSED
)
1925 return insn
| ((value
& 0x1f) << 16) | ((value
& 0x20) >> 3);
1929 extract_xa6 (unsigned long insn
,
1930 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1931 int *invalid ATTRIBUTE_UNUSED
)
1933 return ((insn
<< 3) & 0x20) | ((insn
>> 16) & 0x1f);
1936 /* The XB field in an XX3 form instruction. This is split. */
1938 static unsigned long
1939 insert_xb6 (unsigned long insn
,
1941 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1942 const char **errmsg ATTRIBUTE_UNUSED
)
1944 return insn
| ((value
& 0x1f) << 11) | ((value
& 0x20) >> 4);
1948 extract_xb6 (unsigned long insn
,
1949 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1950 int *invalid ATTRIBUTE_UNUSED
)
1952 return ((insn
<< 4) & 0x20) | ((insn
>> 11) & 0x1f);
1955 /* The XB field in an XX3 form instruction when it must be the same as
1956 the XA field in the instruction. This is used for extended
1957 mnemonics like xvmovdp. This operand is marked FAKE. The insertion
1958 function just copies the XA field into the XB field, and the
1959 extraction function just checks that the fields are the same. */
1961 static unsigned long
1962 insert_xb6s (unsigned long insn
,
1963 long value ATTRIBUTE_UNUSED
,
1964 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1965 const char **errmsg ATTRIBUTE_UNUSED
)
1967 return insn
| (((insn
>> 16) & 0x1f) << 11) | (((insn
>> 2) & 0x1) << 1);
1971 extract_xb6s (unsigned long insn
,
1972 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1975 if ((((insn
>> 16) & 0x1f) != ((insn
>> 11) & 0x1f))
1976 || (((insn
>> 2) & 0x1) != ((insn
>> 1) & 0x1)))
1981 /* The XC field in an XX4 form instruction. This is split. */
1983 static unsigned long
1984 insert_xc6 (unsigned long insn
,
1986 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1987 const char **errmsg ATTRIBUTE_UNUSED
)
1989 return insn
| ((value
& 0x1f) << 6) | ((value
& 0x20) >> 2);
1993 extract_xc6 (unsigned long insn
,
1994 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1995 int *invalid ATTRIBUTE_UNUSED
)
1997 return ((insn
<< 2) & 0x20) | ((insn
>> 6) & 0x1f);
2000 static unsigned long
2001 insert_dm (unsigned long insn
,
2003 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
2004 const char **errmsg
)
2006 if (value
!= 0 && value
!= 1)
2007 *errmsg
= _("invalid constant");
2008 return insn
| (((value
) ? 3 : 0) << 8);
2012 extract_dm (unsigned long insn
,
2013 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
2018 value
= (insn
>> 8) & 3;
2019 if (value
!= 0 && value
!= 3)
2021 return (value
) ? 1 : 0;
2023 /* The VLESIMM field in an I16A form instruction. This is split. */
2025 static unsigned long
2026 insert_vlesi (unsigned long insn
,
2028 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
2029 const char **errmsg ATTRIBUTE_UNUSED
)
2031 return insn
| ((value
& 0xf800) << 10) | (value
& 0x7ff);
2035 extract_vlesi (unsigned long insn
,
2036 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
2037 int *invalid ATTRIBUTE_UNUSED
)
2039 /* RWRW Because I don't know how to make int be 16 and long be 32 */
2040 /* I can't rely on casting an int to long to get sign extension. */
2041 long value
= ((insn
>> 10) & 0xf800) | (insn
& 0x7ff);
2043 value
|= 0xffff0000;
2047 static unsigned long
2048 insert_vlensi (unsigned long insn
,
2050 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
2051 const char **errmsg ATTRIBUTE_UNUSED
)
2054 return insn
| ((value
& 0xf800) << 10) | (value
& 0x7ff);
2057 extract_vlensi (unsigned long insn
,
2058 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
2059 int *invalid ATTRIBUTE_UNUSED
)
2061 long value
= ((insn
>> 10) & 0xf800) | (insn
& 0x7ff);
2063 value
|= 0xffff0000;
2068 /* The VLEUIMM field in an I16A form instruction. This is split. */
2070 static unsigned long
2071 insert_vleui (unsigned long insn
,
2073 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
2074 const char **errmsg ATTRIBUTE_UNUSED
)
2076 return insn
| ((value
& 0xf800) << 10) | (value
& 0x7ff);
2080 extract_vleui (unsigned long insn
,
2081 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
2082 int *invalid ATTRIBUTE_UNUSED
)
2084 return ((insn
>> 10) & 0xf800) | (insn
& 0x7ff);
2087 /* The VLEUIMML field in an I16L form instruction. This is split. */
2089 static unsigned long
2090 insert_vleil (unsigned long insn
,
2092 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
2093 const char **errmsg ATTRIBUTE_UNUSED
)
2095 return insn
| ((value
& 0xf800) << 5) | (value
& 0x7ff);
2099 extract_vleil (unsigned long insn
,
2100 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
2101 int *invalid ATTRIBUTE_UNUSED
)
2103 return ((insn
>> 5) & 0xf800) | (insn
& 0x7ff);
2107 /* Macros used to form opcodes. */
2109 /* The main opcode. */
2110 #define OP(x) ((((unsigned long)(x)) & 0x3f) << 26)
2111 #define OP_MASK OP (0x3f)
2113 /* The main opcode combined with a trap code in the TO field of a D
2114 form instruction. Used for extended mnemonics for the trap
2116 #define OPTO(x,to) (OP (x) | ((((unsigned long)(to)) & 0x1f) << 21))
2117 #define OPTO_MASK (OP_MASK | TO_MASK)
2119 /* The main opcode combined with a comparison size bit in the L field
2120 of a D form or X form instruction. Used for extended mnemonics for
2121 the comparison instructions. */
2122 #define OPL(x,l) (OP (x) | ((((unsigned long)(l)) & 1) << 21))
2123 #define OPL_MASK OPL (0x3f,1)
2125 /* The main opcode combined with an update code in D form instruction.
2126 Used for extended mnemonics for VLE memory instructions. */
2127 #define OPVUP(x,vup) (OP (x) | ((((unsigned long)(vup)) & 0xff) << 8))
2128 #define OPVUP_MASK OPVUP (0x3f, 0xff)
2130 /* An A form instruction. */
2131 #define A(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0x1f) << 1) | (((unsigned long)(rc)) & 1))
2132 #define A_MASK A (0x3f, 0x1f, 1)
2134 /* An A_MASK with the FRB field fixed. */
2135 #define AFRB_MASK (A_MASK | FRB_MASK)
2137 /* An A_MASK with the FRC field fixed. */
2138 #define AFRC_MASK (A_MASK | FRC_MASK)
2140 /* An A_MASK with the FRA and FRC fields fixed. */
2141 #define AFRAFRC_MASK (A_MASK | FRA_MASK | FRC_MASK)
2143 /* An AFRAFRC_MASK, but with L bit clear. */
2144 #define AFRALFRC_MASK (AFRAFRC_MASK & ~((unsigned long) 1 << 16))
2146 /* A B form instruction. */
2147 #define B(op, aa, lk) (OP (op) | ((((unsigned long)(aa)) & 1) << 1) | ((lk) & 1))
2148 #define B_MASK B (0x3f, 1, 1)
2150 /* A BD8 form instruction. This is a 16-bit instruction. */
2151 #define BD8(op, aa, lk) (((((unsigned long)(op)) & 0x3f) << 10) | (((aa) & 1) << 9) | (((lk) & 1) << 8))
2152 #define BD8_MASK BD8 (0x3f, 1, 1)
2154 /* Another BD8 form instruction. This is a 16-bit instruction. */
2155 #define BD8IO(op) ((((unsigned long)(op)) & 0x1f) << 11)
2156 #define BD8IO_MASK BD8IO (0x1f)
2158 /* A BD8 form instruction for simplified mnemonics. */
2159 #define EBD8IO(op, bo, bi) (BD8IO ((op)) | ((bo) << 10) | ((bi) << 8))
2160 /* A mask that excludes BO32 and BI32. */
2161 #define EBD8IO1_MASK 0xf800
2162 /* A mask that includes BO32 and excludes BI32. */
2163 #define EBD8IO2_MASK 0xfc00
2164 /* A mask that include BO32 AND BI32. */
2165 #define EBD8IO3_MASK 0xff00
2167 /* A BD15 form instruction. */
2168 #define BD15(op, aa, lk) (OP (op) | ((((unsigned long)(aa)) & 0xf) << 22) | ((lk) & 1))
2169 #define BD15_MASK BD15 (0x3f, 0xf, 1)
2171 /* A BD15 form instruction for extended conditional branch mnemonics. */
2172 #define EBD15(op, aa, bo, lk) (((op) & 0x3f) << 26) | (((aa) & 0xf) << 22) | (((bo) & 0x3) << 20) | ((lk) & 1)
2173 #define EBD15_MASK 0xfff00001
2175 /* A BD15 form instruction for extended conditional branch mnemonics with BI. */
2176 #define EBD15BI(op, aa, bo, bi, lk) (((op) & 0x3f) << 26) \
2177 | (((aa) & 0xf) << 22) \
2178 | (((bo) & 0x3) << 20) \
2179 | (((bi) & 0x3) << 16) \
2181 #define EBD15BI_MASK 0xfff30001
2183 /* A BD24 form instruction. */
2184 #define BD24(op, aa, lk) (OP (op) | ((((unsigned long)(aa)) & 1) << 25) | ((lk) & 1))
2185 #define BD24_MASK BD24 (0x3f, 1, 1)
2187 /* A B form instruction setting the BO field. */
2188 #define BBO(op, bo, aa, lk) (B ((op), (aa), (lk)) | ((((unsigned long)(bo)) & 0x1f) << 21))
2189 #define BBO_MASK BBO (0x3f, 0x1f, 1, 1)
2191 /* A BBO_MASK with the y bit of the BO field removed. This permits
2192 matching a conditional branch regardless of the setting of the y
2193 bit. Similarly for the 'at' bits used for power4 branch hints. */
2194 #define Y_MASK (((unsigned long) 1) << 21)
2195 #define AT1_MASK (((unsigned long) 3) << 21)
2196 #define AT2_MASK (((unsigned long) 9) << 21)
2197 #define BBOY_MASK (BBO_MASK &~ Y_MASK)
2198 #define BBOAT_MASK (BBO_MASK &~ AT1_MASK)
2200 /* A B form instruction setting the BO field and the condition bits of
2202 #define BBOCB(op, bo, cb, aa, lk) \
2203 (BBO ((op), (bo), (aa), (lk)) | ((((unsigned long)(cb)) & 0x3) << 16))
2204 #define BBOCB_MASK BBOCB (0x3f, 0x1f, 0x3, 1, 1)
2206 /* A BBOCB_MASK with the y bit of the BO field removed. */
2207 #define BBOYCB_MASK (BBOCB_MASK &~ Y_MASK)
2208 #define BBOATCB_MASK (BBOCB_MASK &~ AT1_MASK)
2209 #define BBOAT2CB_MASK (BBOCB_MASK &~ AT2_MASK)
2211 /* A BBOYCB_MASK in which the BI field is fixed. */
2212 #define BBOYBI_MASK (BBOYCB_MASK | BI_MASK)
2213 #define BBOATBI_MASK (BBOAT2CB_MASK | BI_MASK)
2215 /* A VLE C form instruction. */
2216 #define C_LK(x, lk) (((((unsigned long)(x)) & 0x7fff) << 1) | ((lk) & 1))
2217 #define C_LK_MASK C_LK(0x7fff, 1)
2218 #define C(x) ((((unsigned long)(x)) & 0xffff))
2219 #define C_MASK C(0xffff)
2221 /* An Context form instruction. */
2222 #define CTX(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x7))
2223 #define CTX_MASK CTX(0x3f, 0x7)
2225 /* An User Context form instruction. */
2226 #define UCTX(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x1f))
2227 #define UCTX_MASK UCTX(0x3f, 0x1f)
2229 /* The main opcode mask with the RA field clear. */
2230 #define DRA_MASK (OP_MASK | RA_MASK)
2232 /* A DS form instruction. */
2233 #define DSO(op, xop) (OP (op) | ((xop) & 0x3))
2234 #define DS_MASK DSO (0x3f, 3)
2236 /* An EVSEL form instruction. */
2237 #define EVSEL(op, xop) (OP (op) | (((unsigned long)(xop)) & 0xff) << 3)
2238 #define EVSEL_MASK EVSEL(0x3f, 0xff)
2240 /* An IA16 form instruction. */
2241 #define IA16(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x1f) << 11)
2242 #define IA16_MASK IA16(0x3f, 0x1f)
2244 /* An I16A form instruction. */
2245 #define I16A(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x1f) << 11)
2246 #define I16A_MASK I16A(0x3f, 0x1f)
2248 /* An I16L form instruction. */
2249 #define I16L(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x1f) << 11)
2250 #define I16L_MASK I16L(0x3f, 0x1f)
2252 /* An IM7 form instruction. */
2253 #define IM7(op) ((((unsigned long)(op)) & 0x1f) << 11)
2254 #define IM7_MASK IM7(0x1f)
2256 /* An M form instruction. */
2257 #define M(op, rc) (OP (op) | ((rc) & 1))
2258 #define M_MASK M (0x3f, 1)
2260 /* An LI20 form instruction. */
2261 #define LI20(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x1) << 15)
2262 #define LI20_MASK LI20(0x3f, 0x1)
2264 /* An M form instruction with the ME field specified. */
2265 #define MME(op, me, rc) (M ((op), (rc)) | ((((unsigned long)(me)) & 0x1f) << 1))
2267 /* An M_MASK with the MB and ME fields fixed. */
2268 #define MMBME_MASK (M_MASK | MB_MASK | ME_MASK)
2270 /* An M_MASK with the SH and ME fields fixed. */
2271 #define MSHME_MASK (M_MASK | SH_MASK | ME_MASK)
2273 /* An MD form instruction. */
2274 #define MD(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0x7) << 2) | ((rc) & 1))
2275 #define MD_MASK MD (0x3f, 0x7, 1)
2277 /* An MD_MASK with the MB field fixed. */
2278 #define MDMB_MASK (MD_MASK | MB6_MASK)
2280 /* An MD_MASK with the SH field fixed. */
2281 #define MDSH_MASK (MD_MASK | SH6_MASK)
2283 /* An MDS form instruction. */
2284 #define MDS(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0xf) << 1) | ((rc) & 1))
2285 #define MDS_MASK MDS (0x3f, 0xf, 1)
2287 /* An MDS_MASK with the MB field fixed. */
2288 #define MDSMB_MASK (MDS_MASK | MB6_MASK)
2290 /* An SC form instruction. */
2291 #define SC(op, sa, lk) (OP (op) | ((((unsigned long)(sa)) & 1) << 1) | ((lk) & 1))
2292 #define SC_MASK (OP_MASK | (((unsigned long)0x3ff) << 16) | (((unsigned long)1) << 1) | 1)
2294 /* An SCI8 form instruction. */
2295 #define SCI8(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x1f) << 11))
2296 #define SCI8_MASK SCI8(0x3f, 0x1f)
2298 /* An SCI8 form instruction. */
2299 #define SCI8BF(op, fop, xop) (OP (op) | ((((unsigned long)(xop)) & 0x1f) << 11) | (((fop) & 7) << 23))
2300 #define SCI8BF_MASK SCI8BF(0x3f, 7, 0x1f)
2302 /* An SD4 form instruction. This is a 16-bit instruction. */
2303 #define SD4(op) ((((unsigned long)(op)) & 0xf) << 12)
2304 #define SD4_MASK SD4(0xf)
2306 /* An SE_IM5 form instruction. This is a 16-bit instruction. */
2307 #define SE_IM5(op, xop) (((((unsigned long)(op)) & 0x3f) << 10) | (((xop) & 0x1) << 9))
2308 #define SE_IM5_MASK SE_IM5(0x3f, 1)
2310 /* An SE_R form instruction. This is a 16-bit instruction. */
2311 #define SE_R(op, xop) (((((unsigned long)(op)) & 0x3f) << 10) | (((xop) & 0x3f) << 4))
2312 #define SE_R_MASK SE_R(0x3f, 0x3f)
2314 /* An SE_RR form instruction. This is a 16-bit instruction. */
2315 #define SE_RR(op, xop) (((((unsigned long)(op)) & 0x3f) << 10) | (((xop) & 0x3) << 8))
2316 #define SE_RR_MASK SE_RR(0x3f, 3)
2318 /* A VX form instruction. */
2319 #define VX(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x7ff))
2321 /* The mask for an VX form instruction. */
2322 #define VX_MASK VX(0x3f, 0x7ff)
2324 /* A VX_MASK with the VA field fixed. */
2325 #define VXVA_MASK (VX_MASK | (0x1f << 16))
2327 /* A VX_MASK with the VB field fixed. */
2328 #define VXVB_MASK (VX_MASK | (0x1f << 11))
2330 /* A VX_MASK with the VA and VB fields fixed. */
2331 #define VXVAVB_MASK (VX_MASK | (0x1f << 16) | (0x1f << 11))
2333 /* A VX_MASK with the VD and VA fields fixed. */
2334 #define VXVDVA_MASK (VX_MASK | (0x1f << 21) | (0x1f << 16))
2336 /* A VX_MASK with a UIMM4 field. */
2337 #define VXUIMM4_MASK (VX_MASK | (0x1 << 20))
2339 /* A VX_MASK with a UIMM3 field. */
2340 #define VXUIMM3_MASK (VX_MASK | (0x3 << 19))
2342 /* A VX_MASK with a UIMM2 field. */
2343 #define VXUIMM2_MASK (VX_MASK | (0x7 << 18))
2345 /* A VA form instruction. */
2346 #define VXA(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x03f))
2348 /* The mask for an VA form instruction. */
2349 #define VXA_MASK VXA(0x3f, 0x3f)
2351 /* A VXA_MASK with a SHB field. */
2352 #define VXASHB_MASK (VXA_MASK | (1 << 10))
2354 /* A VXR form instruction. */
2355 #define VXR(op, xop, rc) (OP (op) | (((rc) & 1) << 10) | (((unsigned long)(xop)) & 0x3ff))
2357 /* The mask for a VXR form instruction. */
2358 #define VXR_MASK VXR(0x3f, 0x3ff, 1)
2360 /* An X form instruction. */
2361 #define X(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x3ff) << 1))
2363 /* An EX form instruction. */
2364 #define EX(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x7ff))
2366 /* The mask for an EX form instruction. */
2367 #define EX_MASK EX (0x3f, 0x7ff)
2369 /* An XX2 form instruction. */
2370 #define XX2(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x1ff) << 2))
2372 /* An XX3 form instruction. */
2373 #define XX3(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0xff) << 3))
2375 /* An XX3 form instruction with the RC bit specified. */
2376 #define XX3RC(op, xop, rc) (OP (op) | (((rc) & 1) << 10) | ((((unsigned long)(xop)) & 0x7f) << 3))
2378 /* An XX4 form instruction. */
2379 #define XX4(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x3) << 4))
2381 /* A Z form instruction. */
2382 #define Z(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x1ff) << 1))
2384 /* An X form instruction with the RC bit specified. */
2385 #define XRC(op, xop, rc) (X ((op), (xop)) | ((rc) & 1))
2387 /* A Z form instruction with the RC bit specified. */
2388 #define ZRC(op, xop, rc) (Z ((op), (xop)) | ((rc) & 1))
2390 /* The mask for an X form instruction. */
2391 #define X_MASK XRC (0x3f, 0x3ff, 1)
2393 /* An X form wait instruction with everything filled in except the WC field. */
2394 #define XWC_MASK (XRC (0x3f, 0x3ff, 1) | (7 << 23) | RA_MASK | RB_MASK)
2396 /* The mask for an XX1 form instruction. */
2397 #define XX1_MASK X (0x3f, 0x3ff)
2399 /* The mask for an XX2 form instruction. */
2400 #define XX2_MASK (XX2 (0x3f, 0x1ff) | (0x1f << 16))
2402 /* The mask for an XX2 form instruction with the UIM bits specified. */
2403 #define XX2UIM_MASK (XX2 (0x3f, 0x1ff) | (7 << 18))
2405 /* The mask for an XX2 form instruction with the BF bits specified. */
2406 #define XX2BF_MASK (XX2_MASK | (3 << 21) | (1))
2408 /* The mask for an XX3 form instruction. */
2409 #define XX3_MASK XX3 (0x3f, 0xff)
2411 /* The mask for an XX3 form instruction with the BF bits specified. */
2412 #define XX3BF_MASK (XX3 (0x3f, 0xff) | (3 << 21) | (1))
2414 /* The mask for an XX3 form instruction with the DM or SHW bits specified. */
2415 #define XX3DM_MASK (XX3 (0x3f, 0x1f) | (1 << 10))
2416 #define XX3SHW_MASK XX3DM_MASK
2418 /* The mask for an XX4 form instruction. */
2419 #define XX4_MASK XX4 (0x3f, 0x3)
2421 /* An X form wait instruction with everything filled in except the WC field. */
2422 #define XWC_MASK (XRC (0x3f, 0x3ff, 1) | (7 << 23) | RA_MASK | RB_MASK)
2424 /* The mask for a Z form instruction. */
2425 #define Z_MASK ZRC (0x3f, 0x1ff, 1)
2426 #define Z2_MASK ZRC (0x3f, 0xff, 1)
2428 /* An X_MASK with the RA field fixed. */
2429 #define XRA_MASK (X_MASK | RA_MASK)
2431 /* An XRA_MASK with the W field clear. */
2432 #define XWRA_MASK (XRA_MASK & ~((unsigned long) 1 << 16))
2434 /* An X_MASK with the RB field fixed. */
2435 #define XRB_MASK (X_MASK | RB_MASK)
2437 /* An X_MASK with the RT field fixed. */
2438 #define XRT_MASK (X_MASK | RT_MASK)
2440 /* An XRT_MASK mask with the L bits clear. */
2441 #define XLRT_MASK (XRT_MASK & ~((unsigned long) 0x3 << 21))
2443 /* An X_MASK with the RA and RB fields fixed. */
2444 #define XRARB_MASK (X_MASK | RA_MASK | RB_MASK)
2446 /* An XRARB_MASK, but with the L bit clear. */
2447 #define XRLARB_MASK (XRARB_MASK & ~((unsigned long) 1 << 16))
2449 /* An X_MASK with the RT and RA fields fixed. */
2450 #define XRTRA_MASK (X_MASK | RT_MASK | RA_MASK)
2452 /* An XRTRA_MASK, but with L bit clear. */
2453 #define XRTLRA_MASK (XRTRA_MASK & ~((unsigned long) 1 << 21))
2455 /* An X form instruction with the L bit specified. */
2456 #define XOPL(op, xop, l) (X ((op), (xop)) | ((((unsigned long)(l)) & 1) << 21))
2458 /* An X form instruction with the L bits specified. */
2459 #define XOPL2(op, xop, l) (X ((op), (xop)) | ((((unsigned long)(l)) & 3) << 21))
2461 /* An X form instruction with RT fields specified */
2462 #define XRT(op, xop, rt) (X ((op), (xop)) \
2463 | ((((unsigned long)(rt)) & 0x1f) << 21))
2465 /* An X form instruction with RT and RA fields specified */
2466 #define XRTRA(op, xop, rt, ra) (X ((op), (xop)) \
2467 | ((((unsigned long)(rt)) & 0x1f) << 21) \
2468 | ((((unsigned long)(ra)) & 0x1f) << 16))
2470 /* The mask for an X form comparison instruction. */
2471 #define XCMP_MASK (X_MASK | (((unsigned long)1) << 22))
2473 /* The mask for an X form comparison instruction with the L field
2475 #define XCMPL_MASK (XCMP_MASK | (((unsigned long)1) << 21))
2477 /* An X form trap instruction with the TO field specified. */
2478 #define XTO(op, xop, to) (X ((op), (xop)) | ((((unsigned long)(to)) & 0x1f) << 21))
2479 #define XTO_MASK (X_MASK | TO_MASK)
2481 /* An X form tlb instruction with the SH field specified. */
2482 #define XTLB(op, xop, sh) (X ((op), (xop)) | ((((unsigned long)(sh)) & 0x1f) << 11))
2483 #define XTLB_MASK (X_MASK | SH_MASK)
2485 /* An X form sync instruction. */
2486 #define XSYNC(op, xop, l) (X ((op), (xop)) | ((((unsigned long)(l)) & 3) << 21))
2488 /* An X form sync instruction with everything filled in except the LS field. */
2489 #define XSYNC_MASK (0xff9fffff)
2491 /* An X form sync instruction with everything filled in except the L and E fields. */
2492 #define XSYNCLE_MASK (0xff90ffff)
2494 /* An X_MASK, but with the EH bit clear. */
2495 #define XEH_MASK (X_MASK & ~((unsigned long )1))
2497 /* An X form AltiVec dss instruction. */
2498 #define XDSS(op, xop, a) (X ((op), (xop)) | ((((unsigned long)(a)) & 1) << 25))
2499 #define XDSS_MASK XDSS(0x3f, 0x3ff, 1)
2501 /* An XFL form instruction. */
2502 #define XFL(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0x3ff) << 1) | (((unsigned long)(rc)) & 1))
2503 #define XFL_MASK XFL (0x3f, 0x3ff, 1)
2505 /* An X form isel instruction. */
2506 #define XISEL(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x1f) << 1))
2507 #define XISEL_MASK XISEL(0x3f, 0x1f)
2509 /* An XL form instruction with the LK field set to 0. */
2510 #define XL(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x3ff) << 1))
2512 /* An XL form instruction which uses the LK field. */
2513 #define XLLK(op, xop, lk) (XL ((op), (xop)) | ((lk) & 1))
2515 /* The mask for an XL form instruction. */
2516 #define XL_MASK XLLK (0x3f, 0x3ff, 1)
2518 /* An XL form instruction which explicitly sets the BO field. */
2519 #define XLO(op, bo, xop, lk) \
2520 (XLLK ((op), (xop), (lk)) | ((((unsigned long)(bo)) & 0x1f) << 21))
2521 #define XLO_MASK (XL_MASK | BO_MASK)
2523 /* An XL form instruction which explicitly sets the y bit of the BO
2525 #define XLYLK(op, xop, y, lk) (XLLK ((op), (xop), (lk)) | ((((unsigned long)(y)) & 1) << 21))
2526 #define XLYLK_MASK (XL_MASK | Y_MASK)
2528 /* An XL form instruction which sets the BO field and the condition
2529 bits of the BI field. */
2530 #define XLOCB(op, bo, cb, xop, lk) \
2531 (XLO ((op), (bo), (xop), (lk)) | ((((unsigned long)(cb)) & 3) << 16))
2532 #define XLOCB_MASK XLOCB (0x3f, 0x1f, 0x3, 0x3ff, 1)
2534 /* An XL_MASK or XLYLK_MASK or XLOCB_MASK with the BB field fixed. */
2535 #define XLBB_MASK (XL_MASK | BB_MASK)
2536 #define XLYBB_MASK (XLYLK_MASK | BB_MASK)
2537 #define XLBOCBBB_MASK (XLOCB_MASK | BB_MASK)
2539 /* A mask for branch instructions using the BH field. */
2540 #define XLBH_MASK (XL_MASK | (0x1c << 11))
2542 /* An XL_MASK with the BO and BB fields fixed. */
2543 #define XLBOBB_MASK (XL_MASK | BO_MASK | BB_MASK)
2545 /* An XL_MASK with the BO, BI and BB fields fixed. */
2546 #define XLBOBIBB_MASK (XL_MASK | BO_MASK | BI_MASK | BB_MASK)
2548 /* An X form mbar instruction with MO field. */
2549 #define XMBAR(op, xop, mo) (X ((op), (xop)) | ((((unsigned long)(mo)) & 1) << 21))
2551 /* An XO form instruction. */
2552 #define XO(op, xop, oe, rc) \
2553 (OP (op) | ((((unsigned long)(xop)) & 0x1ff) << 1) | ((((unsigned long)(oe)) & 1) << 10) | (((unsigned long)(rc)) & 1))
2554 #define XO_MASK XO (0x3f, 0x1ff, 1, 1)
2556 /* An XO_MASK with the RB field fixed. */
2557 #define XORB_MASK (XO_MASK | RB_MASK)
2559 /* An XOPS form instruction for paired singles. */
2560 #define XOPS(op, xop, rc) \
2561 (OP (op) | ((((unsigned long)(xop)) & 0x3ff) << 1) | (((unsigned long)(rc)) & 1))
2562 #define XOPS_MASK XOPS (0x3f, 0x3ff, 1)
2565 /* An XS form instruction. */
2566 #define XS(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0x1ff) << 2) | (((unsigned long)(rc)) & 1))
2567 #define XS_MASK XS (0x3f, 0x1ff, 1)
2569 /* A mask for the FXM version of an XFX form instruction. */
2570 #define XFXFXM_MASK (X_MASK | (1 << 11) | (1 << 20))
2572 /* An XFX form instruction with the FXM field filled in. */
2573 #define XFXM(op, xop, fxm, p4) \
2574 (X ((op), (xop)) | ((((unsigned long)(fxm)) & 0xff) << 12) \
2575 | ((unsigned long)(p4) << 20))
2577 /* An XFX form instruction with the SPR field filled in. */
2578 #define XSPR(op, xop, spr) \
2579 (X ((op), (xop)) | ((((unsigned long)(spr)) & 0x1f) << 16) | ((((unsigned long)(spr)) & 0x3e0) << 6))
2580 #define XSPR_MASK (X_MASK | SPR_MASK)
2582 /* An XFX form instruction with the SPR field filled in except for the
2584 #define XSPRBAT_MASK (XSPR_MASK &~ SPRBAT_MASK)
2586 /* An XFX form instruction with the SPR field filled in except for the
2588 #define XSPRG_MASK (XSPR_MASK & ~(0x1f << 16))
2590 /* An X form instruction with everything filled in except the E field. */
2591 #define XE_MASK (0xffff7fff)
2593 /* An X form user context instruction. */
2594 #define XUC(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x1f))
2595 #define XUC_MASK XUC(0x3f, 0x1f)
2597 /* An XW form instruction. */
2598 #define XW(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0x3f) << 1) | ((rc) & 1))
2599 /* The mask for a G form instruction. rc not supported at present. */
2600 #define XW_MASK XW (0x3f, 0x3f, 0)
2602 /* An APU form instruction. */
2603 #define APU(op, xop, rc) (OP (op) | (((unsigned long)(xop)) & 0x3ff) << 1 | ((rc) & 1))
2605 /* The mask for an APU form instruction. */
2606 #define APU_MASK APU (0x3f, 0x3ff, 1)
2607 #define APU_RT_MASK (APU_MASK | RT_MASK)
2608 #define APU_RA_MASK (APU_MASK | RA_MASK)
2610 /* The BO encodings used in extended conditional branch mnemonics. */
2611 #define BODNZF (0x0)
2612 #define BODNZFP (0x1)
2614 #define BODZFP (0x3)
2615 #define BODNZT (0x8)
2616 #define BODNZTP (0x9)
2618 #define BODZTP (0xb)
2629 #define BODNZ (0x10)
2630 #define BODNZP (0x11)
2632 #define BODZP (0x13)
2633 #define BODNZM4 (0x18)
2634 #define BODNZP4 (0x19)
2635 #define BODZM4 (0x1a)
2636 #define BODZP4 (0x1b)
2640 /* The BO16 encodings used in extended VLE conditional branch mnemonics. */
2644 /* The BO32 encodings used in extended VLE conditional branch mnemonics. */
2647 #define BO32DNZ (0x2)
2648 #define BO32DZ (0x3)
2650 /* The BI condition bit encodings used in extended conditional branch
2657 /* The TO encodings used in extended trap mnemonics. */
2674 /* Smaller names for the flags so each entry in the opcodes table will
2675 fit on a single line. */
2678 #define PPC PPC_OPCODE_PPC
2679 #define PPCCOM PPC_OPCODE_PPC | PPC_OPCODE_COMMON
2680 #define POWER4 PPC_OPCODE_POWER4
2681 #define POWER5 PPC_OPCODE_POWER5
2682 #define POWER6 PPC_OPCODE_POWER6
2683 #define POWER7 PPC_OPCODE_POWER7
2684 #define CELL PPC_OPCODE_CELL
2685 #define PPC64 PPC_OPCODE_64 | PPC_OPCODE_64_BRIDGE
2686 #define NON32 (PPC_OPCODE_64 | PPC_OPCODE_POWER4 \
2687 | PPC_OPCODE_EFS | PPC_OPCODE_E500MC | PPC_OPCODE_TITAN)
2688 #define PPC403 PPC_OPCODE_403
2689 #define PPC405 PPC_OPCODE_405
2690 #define PPC440 PPC_OPCODE_440
2691 #define PPC464 PPC440
2692 #define PPC476 PPC_OPCODE_476
2696 #define PPCPS PPC_OPCODE_PPCPS
2697 #define PPCVEC PPC_OPCODE_ALTIVEC
2698 #define PPCVEC2 PPC_OPCODE_ALTIVEC2
2699 #define PPCVSX PPC_OPCODE_VSX
2700 #define POWER PPC_OPCODE_POWER
2701 #define POWER2 PPC_OPCODE_POWER | PPC_OPCODE_POWER2
2702 #define PWR2COM PPC_OPCODE_POWER | PPC_OPCODE_POWER2 | PPC_OPCODE_COMMON
2703 #define PPCPWR2 PPC_OPCODE_PPC | PPC_OPCODE_POWER | PPC_OPCODE_POWER2 | PPC_OPCODE_COMMON
2704 #define COM PPC_OPCODE_POWER | PPC_OPCODE_PPC | PPC_OPCODE_COMMON
2705 #define M601 PPC_OPCODE_POWER | PPC_OPCODE_601
2706 #define PWRCOM PPC_OPCODE_POWER | PPC_OPCODE_601 | PPC_OPCODE_COMMON
2707 #define MFDEC1 PPC_OPCODE_POWER
2708 #define MFDEC2 PPC_OPCODE_PPC | PPC_OPCODE_601 | PPC_OPCODE_BOOKE | PPC_OPCODE_TITAN
2709 #define BOOKE PPC_OPCODE_BOOKE
2710 #define NO371 PPC_OPCODE_BOOKE | PPC_OPCODE_PPCPS | PPC_OPCODE_EFS | PPC_OPCODE_VLE
2711 #define PPCE300 PPC_OPCODE_E300
2712 #define PPCSPE PPC_OPCODE_SPE | PPC_OPCODE_VLE
2713 #define PPCISEL PPC_OPCODE_ISEL | PPC_OPCODE_VLE
2714 #define PPCEFS PPC_OPCODE_EFS | PPC_OPCODE_VLE
2715 #define PPCBRLK PPC_OPCODE_BRLOCK
2716 #define PPCPMR PPC_OPCODE_PMR
2717 #define PPCTMR PPC_OPCODE_TMR
2718 #define PPCCHLK PPC_OPCODE_CACHELCK
2719 #define PPCRFMCI PPC_OPCODE_RFMCI
2720 #define E500MC PPC_OPCODE_E500MC
2721 #define PPCA2 PPC_OPCODE_A2
2722 #define TITAN PPC_OPCODE_TITAN
2723 #define MULHW PPC_OPCODE_405 | PPC_OPCODE_440 | TITAN | PPC_OPCODE_VLE
2724 #define E500 PPC_OPCODE_E500
2725 #define E6500 PPC_OPCODE_E6500
2726 #define PPCVLE PPC_OPCODE_VLE
2728 /* The opcode table.
2730 The format of the opcode table is:
2732 NAME OPCODE MASK FLAGS ANTI {OPERANDS}
2734 NAME is the name of the instruction.
2735 OPCODE is the instruction opcode.
2736 MASK is the opcode mask; this is used to tell the disassembler
2737 which bits in the actual opcode must match OPCODE.
2738 FLAGS are flags indicating which processors support the instruction.
2739 ANTI indicates which processors don't support the instruction.
2740 OPERANDS is the list of operands.
2742 The disassembler reads the table in order and prints the first
2743 instruction which matches, so this table is sorted to put more
2744 specific instructions before more general instructions.
2746 This table must be sorted by major opcode. Please try to keep it
2747 vaguely sorted within major opcode too, except of course where
2748 constrained otherwise by disassembler operation. */
2750 const struct powerpc_opcode powerpc_opcodes
[] = {
2751 {"attn", X(0,256), X_MASK
, POWER4
|PPCA2
, PPC476
, {0}},
2752 {"tdlgti", OPTO(2,TOLGT
), OPTO_MASK
, PPC64
, PPCNONE
, {RA
, SI
}},
2753 {"tdllti", OPTO(2,TOLLT
), OPTO_MASK
, PPC64
, PPCNONE
, {RA
, SI
}},
2754 {"tdeqi", OPTO(2,TOEQ
), OPTO_MASK
, PPC64
, PPCNONE
, {RA
, SI
}},
2755 {"tdlgei", OPTO(2,TOLGE
), OPTO_MASK
, PPC64
, PPCNONE
, {RA
, SI
}},
2756 {"tdlnli", OPTO(2,TOLNL
), OPTO_MASK
, PPC64
, PPCNONE
, {RA
, SI
}},
2757 {"tdllei", OPTO(2,TOLLE
), OPTO_MASK
, PPC64
, PPCNONE
, {RA
, SI
}},
2758 {"tdlngi", OPTO(2,TOLNG
), OPTO_MASK
, PPC64
, PPCNONE
, {RA
, SI
}},
2759 {"tdgti", OPTO(2,TOGT
), OPTO_MASK
, PPC64
, PPCNONE
, {RA
, SI
}},
2760 {"tdgei", OPTO(2,TOGE
), OPTO_MASK
, PPC64
, PPCNONE
, {RA
, SI
}},
2761 {"tdnli", OPTO(2,TONL
), OPTO_MASK
, PPC64
, PPCNONE
, {RA
, SI
}},
2762 {"tdlti", OPTO(2,TOLT
), OPTO_MASK
, PPC64
, PPCNONE
, {RA
, SI
}},
2763 {"tdlei", OPTO(2,TOLE
), OPTO_MASK
, PPC64
, PPCNONE
, {RA
, SI
}},
2764 {"tdngi", OPTO(2,TONG
), OPTO_MASK
, PPC64
, PPCNONE
, {RA
, SI
}},
2765 {"tdnei", OPTO(2,TONE
), OPTO_MASK
, PPC64
, PPCNONE
, {RA
, SI
}},
2766 {"tdi", OP(2), OP_MASK
, PPC64
, PPCNONE
, {TO
, RA
, SI
}},
2768 {"twlgti", OPTO(3,TOLGT
), OPTO_MASK
, PPCCOM
, PPCNONE
, {RA
, SI
}},
2769 {"tlgti", OPTO(3,TOLGT
), OPTO_MASK
, PWRCOM
, PPCNONE
, {RA
, SI
}},
2770 {"twllti", OPTO(3,TOLLT
), OPTO_MASK
, PPCCOM
, PPCNONE
, {RA
, SI
}},
2771 {"tllti", OPTO(3,TOLLT
), OPTO_MASK
, PWRCOM
, PPCNONE
, {RA
, SI
}},
2772 {"tweqi", OPTO(3,TOEQ
), OPTO_MASK
, PPCCOM
, PPCNONE
, {RA
, SI
}},
2773 {"teqi", OPTO(3,TOEQ
), OPTO_MASK
, PWRCOM
, PPCNONE
, {RA
, SI
}},
2774 {"twlgei", OPTO(3,TOLGE
), OPTO_MASK
, PPCCOM
, PPCNONE
, {RA
, SI
}},
2775 {"tlgei", OPTO(3,TOLGE
), OPTO_MASK
, PWRCOM
, PPCNONE
, {RA
, SI
}},
2776 {"twlnli", OPTO(3,TOLNL
), OPTO_MASK
, PPCCOM
, PPCNONE
, {RA
, SI
}},
2777 {"tlnli", OPTO(3,TOLNL
), OPTO_MASK
, PWRCOM
, PPCNONE
, {RA
, SI
}},
2778 {"twllei", OPTO(3,TOLLE
), OPTO_MASK
, PPCCOM
, PPCNONE
, {RA
, SI
}},
2779 {"tllei", OPTO(3,TOLLE
), OPTO_MASK
, PWRCOM
, PPCNONE
, {RA
, SI
}},
2780 {"twlngi", OPTO(3,TOLNG
), OPTO_MASK
, PPCCOM
, PPCNONE
, {RA
, SI
}},
2781 {"tlngi", OPTO(3,TOLNG
), OPTO_MASK
, PWRCOM
, PPCNONE
, {RA
, SI
}},
2782 {"twgti", OPTO(3,TOGT
), OPTO_MASK
, PPCCOM
, PPCNONE
, {RA
, SI
}},
2783 {"tgti", OPTO(3,TOGT
), OPTO_MASK
, PWRCOM
, PPCNONE
, {RA
, SI
}},
2784 {"twgei", OPTO(3,TOGE
), OPTO_MASK
, PPCCOM
, PPCNONE
, {RA
, SI
}},
2785 {"tgei", OPTO(3,TOGE
), OPTO_MASK
, PWRCOM
, PPCNONE
, {RA
, SI
}},
2786 {"twnli", OPTO(3,TONL
), OPTO_MASK
, PPCCOM
, PPCNONE
, {RA
, SI
}},
2787 {"tnli", OPTO(3,TONL
), OPTO_MASK
, PWRCOM
, PPCNONE
, {RA
, SI
}},
2788 {"twlti", OPTO(3,TOLT
), OPTO_MASK
, PPCCOM
, PPCNONE
, {RA
, SI
}},
2789 {"tlti", OPTO(3,TOLT
), OPTO_MASK
, PWRCOM
, PPCNONE
, {RA
, SI
}},
2790 {"twlei", OPTO(3,TOLE
), OPTO_MASK
, PPCCOM
, PPCNONE
, {RA
, SI
}},
2791 {"tlei", OPTO(3,TOLE
), OPTO_MASK
, PWRCOM
, PPCNONE
, {RA
, SI
}},
2792 {"twngi", OPTO(3,TONG
), OPTO_MASK
, PPCCOM
, PPCNONE
, {RA
, SI
}},
2793 {"tngi", OPTO(3,TONG
), OPTO_MASK
, PWRCOM
, PPCNONE
, {RA
, SI
}},
2794 {"twnei", OPTO(3,TONE
), OPTO_MASK
, PPCCOM
, PPCNONE
, {RA
, SI
}},
2795 {"tnei", OPTO(3,TONE
), OPTO_MASK
, PWRCOM
, PPCNONE
, {RA
, SI
}},
2796 {"twi", OP(3), OP_MASK
, PPCCOM
, PPCNONE
, {TO
, RA
, SI
}},
2797 {"ti", OP(3), OP_MASK
, PWRCOM
, PPCNONE
, {TO
, RA
, SI
}},
2799 {"ps_cmpu0", X (4, 0), X_MASK
|(3<<21), PPCPS
, PPCNONE
, {BF
, FRA
, FRB
}},
2800 {"vaddubm", VX (4, 0), VX_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
2801 {"vmaxub", VX (4, 2), VX_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
2802 {"vrlb", VX (4, 4), VX_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
2803 {"vcmpequb", VXR(4, 6,0), VXR_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
2804 {"vmuloub", VX (4, 8), VX_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
2805 {"vaddfp", VX (4, 10), VX_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
2806 {"psq_lx", XW (4, 6,0), XW_MASK
, PPCPS
, PPCNONE
, {FRT
,RA
,RB
,PSWM
,PSQM
}},
2807 {"vmrghb", VX (4, 12), VX_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
2808 {"psq_stx", XW (4, 7,0), XW_MASK
, PPCPS
, PPCNONE
, {FRS
,RA
,RB
,PSWM
,PSQM
}},
2809 {"vpkuhum", VX (4, 14), VX_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
2810 {"mulhhwu", XRC(4, 8,0), X_MASK
, MULHW
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
2811 {"mulhhwu.", XRC(4, 8,1), X_MASK
, MULHW
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
2812 {"ps_sum0", A (4, 10,0), A_MASK
, PPCPS
, PPCNONE
, {FRT
, FRA
, FRC
, FRB
}},
2813 {"ps_sum0.", A (4, 10,1), A_MASK
, PPCPS
, PPCNONE
, {FRT
, FRA
, FRC
, FRB
}},
2814 {"ps_sum1", A (4, 11,0), A_MASK
, PPCPS
, PPCNONE
, {FRT
, FRA
, FRC
, FRB
}},
2815 {"ps_sum1.", A (4, 11,1), A_MASK
, PPCPS
, PPCNONE
, {FRT
, FRA
, FRC
, FRB
}},
2816 {"ps_muls0", A (4, 12,0), AFRB_MASK
, PPCPS
, PPCNONE
, {FRT
, FRA
, FRC
}},
2817 {"machhwu", XO (4, 12,0,0),XO_MASK
, MULHW
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
2818 {"ps_muls0.", A (4, 12,1), AFRB_MASK
, PPCPS
, PPCNONE
, {FRT
, FRA
, FRC
}},
2819 {"machhwu.", XO (4, 12,0,1),XO_MASK
, MULHW
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
2820 {"ps_muls1", A (4, 13,0), AFRB_MASK
, PPCPS
, PPCNONE
, {FRT
, FRA
, FRC
}},
2821 {"ps_muls1.", A (4, 13,1), AFRB_MASK
, PPCPS
, PPCNONE
, {FRT
, FRA
, FRC
}},
2822 {"ps_madds0", A (4, 14,0), A_MASK
, PPCPS
, PPCNONE
, {FRT
, FRA
, FRC
, FRB
}},
2823 {"ps_madds0.", A (4, 14,1), A_MASK
, PPCPS
, PPCNONE
, {FRT
, FRA
, FRC
, FRB
}},
2824 {"ps_madds1", A (4, 15,0), A_MASK
, PPCPS
, PPCNONE
, {FRT
, FRA
, FRC
, FRB
}},
2825 {"ps_madds1.", A (4, 15,1), A_MASK
, PPCPS
, PPCNONE
, {FRT
, FRA
, FRC
, FRB
}},
2826 {"vmhaddshs", VXA(4, 32), VXA_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
, VC
}},
2827 {"vmhraddshs", VXA(4, 33), VXA_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
, VC
}},
2828 {"vmladduhm", VXA(4, 34), VXA_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
, VC
}},
2829 {"ps_div", A (4, 18,0), AFRC_MASK
, PPCPS
, PPCNONE
, {FRT
, FRA
, FRB
}},
2830 {"vmsumubm", VXA(4, 36), VXA_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
, VC
}},
2831 {"ps_div.", A (4, 18,1), AFRC_MASK
, PPCPS
, PPCNONE
, {FRT
, FRA
, FRB
}},
2832 {"vmsummbm", VXA(4, 37), VXA_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
, VC
}},
2833 {"vmsumuhm", VXA(4, 38), VXA_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
, VC
}},
2834 {"vmsumuhs", VXA(4, 39), VXA_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
, VC
}},
2835 {"ps_sub", A (4, 20,0), AFRC_MASK
, PPCPS
, PPCNONE
, {FRT
, FRA
, FRB
}},
2836 {"vmsumshm", VXA(4, 40), VXA_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
, VC
}},
2837 {"ps_sub.", A (4, 20,1), AFRC_MASK
, PPCPS
, PPCNONE
, {FRT
, FRA
, FRB
}},
2838 {"vmsumshs", VXA(4, 41), VXA_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
, VC
}},
2839 {"ps_add", A (4, 21,0), AFRC_MASK
, PPCPS
, PPCNONE
, {FRT
, FRA
, FRB
}},
2840 {"vsel", VXA(4, 42), VXA_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
, VC
}},
2841 {"ps_add.", A (4, 21,1), AFRC_MASK
, PPCPS
, PPCNONE
, {FRT
, FRA
, FRB
}},
2842 {"vperm", VXA(4, 43), VXA_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
, VC
}},
2843 {"vsldoi", VXA(4, 44), VXASHB_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
, SHB
}},
2844 {"ps_sel", A (4, 23,0), A_MASK
, PPCPS
, PPCNONE
, {FRT
, FRA
, FRC
, FRB
}},
2845 {"vmaddfp", VXA(4, 46), VXA_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VC
, VB
}},
2846 {"ps_sel.", A (4, 23,1), A_MASK
, PPCPS
, PPCNONE
, {FRT
, FRA
, FRC
, FRB
}},
2847 {"vnmsubfp", VXA(4, 47), VXA_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VC
, VB
}},
2848 {"ps_res", A (4, 24,0), AFRAFRC_MASK
, PPCPS
, PPCNONE
, {FRT
, FRB
}},
2849 {"ps_res.", A (4, 24,1), AFRAFRC_MASK
, PPCPS
, PPCNONE
, {FRT
, FRB
}},
2850 {"ps_mul", A (4, 25,0), AFRB_MASK
, PPCPS
, PPCNONE
, {FRT
, FRA
, FRC
}},
2851 {"ps_mul.", A (4, 25,1), AFRB_MASK
, PPCPS
, PPCNONE
, {FRT
, FRA
, FRC
}},
2852 {"ps_rsqrte", A (4, 26,0), AFRAFRC_MASK
, PPCPS
, PPCNONE
, {FRT
, FRB
}},
2853 {"ps_rsqrte.", A (4, 26,1), AFRAFRC_MASK
, PPCPS
, PPCNONE
, {FRT
, FRB
}},
2854 {"ps_msub", A (4, 28,0), A_MASK
, PPCPS
, PPCNONE
, {FRT
, FRA
, FRC
, FRB
}},
2855 {"ps_msub.", A (4, 28,1), A_MASK
, PPCPS
, PPCNONE
, {FRT
, FRA
, FRC
, FRB
}},
2856 {"ps_madd", A (4, 29,0), A_MASK
, PPCPS
, PPCNONE
, {FRT
, FRA
, FRC
, FRB
}},
2857 {"ps_madd.", A (4, 29,1), A_MASK
, PPCPS
, PPCNONE
, {FRT
, FRA
, FRC
, FRB
}},
2858 {"ps_nmsub", A (4, 30,0), A_MASK
, PPCPS
, PPCNONE
, {FRT
, FRA
, FRC
, FRB
}},
2859 {"ps_nmsub.", A (4, 30,1), A_MASK
, PPCPS
, PPCNONE
, {FRT
, FRA
, FRC
, FRB
}},
2860 {"ps_nmadd", A (4, 31,0), A_MASK
, PPCPS
, PPCNONE
, {FRT
, FRA
, FRC
, FRB
}},
2861 {"ps_nmadd.", A (4, 31,1), A_MASK
, PPCPS
, PPCNONE
, {FRT
, FRA
, FRC
, FRB
}},
2862 {"ps_cmpo0", X (4, 32), X_MASK
|(3<<21), PPCPS
, PPCNONE
, {BF
, FRA
, FRB
}},
2863 {"vadduhm", VX (4, 64), VX_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
2864 {"vmaxuh", VX (4, 66), VX_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
2865 {"vrlh", VX (4, 68), VX_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
2866 {"vcmpequh", VXR(4, 70,0), VXR_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
2867 {"vmulouh", VX (4, 72), VX_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
2868 {"vsubfp", VX (4, 74), VX_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
2869 {"psq_lux", XW (4, 38,0), XW_MASK
, PPCPS
, PPCNONE
, {FRT
,RA
,RB
,PSWM
,PSQM
}},
2870 {"vmrghh", VX (4, 76), VX_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
2871 {"psq_stux", XW (4, 39,0), XW_MASK
, PPCPS
, PPCNONE
, {FRS
,RA
,RB
,PSWM
,PSQM
}},
2872 {"vpkuwum", VX (4, 78), VX_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
2873 {"ps_neg", XRC(4, 40,0), XRA_MASK
, PPCPS
, PPCNONE
, {FRT
, FRB
}},
2874 {"mulhhw", XRC(4, 40,0), X_MASK
, MULHW
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
2875 {"ps_neg.", XRC(4, 40,1), XRA_MASK
, PPCPS
, PPCNONE
, {FRT
, FRB
}},
2876 {"mulhhw.", XRC(4, 40,1), X_MASK
, MULHW
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
2877 {"machhw", XO (4, 44,0,0),XO_MASK
, MULHW
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
2878 {"machhw.", XO (4, 44,0,1),XO_MASK
, MULHW
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
2879 {"nmachhw", XO (4, 46,0,0),XO_MASK
, MULHW
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
2880 {"nmachhw.", XO (4, 46,0,1),XO_MASK
, MULHW
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
2881 {"ps_cmpu1", X (4, 64), X_MASK
|(3<<21), PPCPS
, PPCNONE
, {BF
, FRA
, FRB
}},
2882 {"vadduwm", VX (4, 128), VX_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
2883 {"vmaxuw", VX (4, 130), VX_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
2884 {"vrlw", VX (4, 132), VX_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
2885 {"vcmpequw", VXR(4, 134,0), VXR_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
2886 {"vmrghw", VX (4, 140), VX_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
2887 {"vpkuhus", VX (4, 142), VX_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
2888 {"ps_mr", XRC(4, 72,0), XRA_MASK
, PPCPS
, PPCNONE
, {FRT
, FRB
}},
2889 {"ps_mr.", XRC(4, 72,1), XRA_MASK
, PPCPS
, PPCNONE
, {FRT
, FRB
}},
2890 {"machhwsu", XO (4, 76,0,0),XO_MASK
, MULHW
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
2891 {"machhwsu.", XO (4, 76,0,1),XO_MASK
, MULHW
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
2892 {"ps_cmpo1", X (4, 96), X_MASK
|(3<<21), PPCPS
, PPCNONE
, {BF
, FRA
, FRB
}},
2893 {"vcmpeqfp", VXR(4, 198,0), VXR_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
2894 {"vpkuwus", VX (4, 206), VX_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
2895 {"machhws", XO (4, 108,0,0),XO_MASK
, MULHW
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
2896 {"machhws.", XO (4, 108,0,1),XO_MASK
, MULHW
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
2897 {"nmachhws", XO (4, 110,0,0),XO_MASK
, MULHW
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
2898 {"nmachhws.", XO (4, 110,0,1),XO_MASK
, MULHW
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
2899 {"vmaxsb", VX (4, 258), VX_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
2900 {"vslb", VX (4, 260), VX_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
2901 {"vmulosb", VX (4, 264), VX_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
2902 {"vrefp", VX (4, 266), VXVA_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VB
}},
2903 {"vmrglb", VX (4, 268), VX_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
2904 {"vpkshus", VX (4, 270), VX_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
2905 {"ps_nabs", XRC(4, 136,0), XRA_MASK
, PPCPS
, PPCNONE
, {FRT
, FRB
}},
2906 {"mulchwu", XRC(4, 136,0), X_MASK
, MULHW
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
2907 {"ps_nabs.", XRC(4, 136,1), XRA_MASK
, PPCPS
, PPCNONE
, {FRT
, FRB
}},
2908 {"mulchwu.", XRC(4, 136,1), X_MASK
, MULHW
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
2909 {"macchwu", XO (4, 140,0,0),XO_MASK
, MULHW
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
2910 {"macchwu.", XO (4, 140,0,1),XO_MASK
, MULHW
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
2911 {"vmaxsh", VX (4, 322), VX_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
2912 {"vslh", VX (4, 324), VX_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
2913 {"vmulosh", VX (4, 328), VX_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
2914 {"vrsqrtefp", VX (4, 330), VXVA_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VB
}},
2915 {"vmrglh", VX (4, 332), VX_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
2916 {"vpkswus", VX (4, 334), VX_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
2917 {"mulchw", XRC(4, 168,0), X_MASK
, MULHW
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
2918 {"mulchw.", XRC(4, 168,1), X_MASK
, MULHW
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
2919 {"macchw", XO (4, 172,0,0),XO_MASK
, MULHW
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
2920 {"macchw.", XO (4, 172,0,1),XO_MASK
, MULHW
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
2921 {"nmacchw", XO (4, 174,0,0),XO_MASK
, MULHW
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
2922 {"nmacchw.", XO (4, 174,0,1),XO_MASK
, MULHW
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
2923 {"vaddcuw", VX (4, 384), VX_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
2924 {"vmaxsw", VX (4, 386), VX_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
2925 {"vslw", VX (4, 388), VX_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
2926 {"vexptefp", VX (4, 394), VXVA_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VB
}},
2927 {"vmrglw", VX (4, 396), VX_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
2928 {"vpkshss", VX (4, 398), VX_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
2929 {"macchwsu", XO (4, 204,0,0),XO_MASK
, MULHW
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
2930 {"macchwsu.", XO (4, 204,0,1),XO_MASK
, MULHW
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
2931 {"vsl", VX (4, 452), VX_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
2932 {"vcmpgefp", VXR(4, 454,0), VXR_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
2933 {"vlogefp", VX (4, 458), VXVA_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VB
}},
2934 {"vpkswss", VX (4, 462), VX_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
2935 {"macchws", XO (4, 236,0,0),XO_MASK
, MULHW
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
2936 {"macchws.", XO (4, 236,0,1),XO_MASK
, MULHW
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
2937 {"nmacchws", XO (4, 238,0,0),XO_MASK
, MULHW
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
2938 {"nmacchws.", XO (4, 238,0,1),XO_MASK
, MULHW
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
2939 {"evaddw", VX (4, 512), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
2940 {"vaddubs", VX (4, 512), VX_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
2941 {"evaddiw", VX (4, 514), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RB
, UIMM
}},
2942 {"vminub", VX (4, 514), VX_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
2943 {"evsubfw", VX (4, 516), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
2944 {"evsubw", VX (4, 516), VX_MASK
, PPCSPE
, PPCNONE
, {RS
, RB
, RA
}},
2945 {"vsrb", VX (4, 516), VX_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
2946 {"evsubifw", VX (4, 518), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, UIMM
, RB
}},
2947 {"evsubiw", VX (4, 518), VX_MASK
, PPCSPE
, PPCNONE
, {RS
, RB
, UIMM
}},
2948 {"vcmpgtub", VXR(4, 518,0), VXR_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
2949 {"evabs", VX (4, 520), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
}},
2950 {"vmuleub", VX (4, 520), VX_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
2951 {"evneg", VX (4, 521), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
}},
2952 {"evextsb", VX (4, 522), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
}},
2953 {"vrfin", VX (4, 522), VXVA_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VB
}},
2954 {"evextsh", VX (4, 523), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
}},
2955 {"evrndw", VX (4, 524), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
}},
2956 {"vspltb", VX (4, 524), VXUIMM4_MASK
,PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VB
, UIMM4
}},
2957 {"evcntlzw", VX (4, 525), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
}},
2958 {"evcntlsw", VX (4, 526), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
}},
2959 {"vupkhsb", VX (4, 526), VXVA_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VB
}},
2960 {"brinc", VX (4, 527), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
2961 {"ps_abs", XRC(4, 264,0), XRA_MASK
, PPCPS
, PPCNONE
, {FRT
, FRB
}},
2962 {"ps_abs.", XRC(4, 264,1), XRA_MASK
, PPCPS
, PPCNONE
, {FRT
, FRB
}},
2963 {"evand", VX (4, 529), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
2964 {"evandc", VX (4, 530), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
2965 {"evxor", VX (4, 534), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
2966 {"evmr", VX (4, 535), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, BBA
}},
2967 {"evor", VX (4, 535), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
2968 {"evnor", VX (4, 536), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
2969 {"evnot", VX (4, 536), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, BBA
}},
2970 {"get", APU(4, 268,0), APU_RA_MASK
, PPC405
, PPCNONE
, {RT
, FSL
}},
2971 {"eveqv", VX (4, 537), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
2972 {"evorc", VX (4, 539), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
2973 {"evnand", VX (4, 542), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
2974 {"evsrwu", VX (4, 544), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
2975 {"evsrws", VX (4, 545), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
2976 {"evsrwiu", VX (4, 546), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, EVUIMM
}},
2977 {"evsrwis", VX (4, 547), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, EVUIMM
}},
2978 {"evslw", VX (4, 548), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
2979 {"evslwi", VX (4, 550), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, EVUIMM
}},
2980 {"evrlw", VX (4, 552), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
2981 {"evsplati", VX (4, 553), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, SIMM
}},
2982 {"evrlwi", VX (4, 554), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, EVUIMM
}},
2983 {"evsplatfi", VX (4, 555), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, SIMM
}},
2984 {"evmergehi", VX (4, 556), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
2985 {"evmergelo", VX (4, 557), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
2986 {"evmergehilo", VX (4, 558), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
2987 {"evmergelohi", VX (4, 559), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
2988 {"evcmpgtu", VX (4, 560), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {CRFD
, RA
, RB
}},
2989 {"evcmpgts", VX (4, 561), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {CRFD
, RA
, RB
}},
2990 {"evcmpltu", VX (4, 562), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {CRFD
, RA
, RB
}},
2991 {"evcmplts", VX (4, 563), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {CRFD
, RA
, RB
}},
2992 {"evcmpeq", VX (4, 564), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {CRFD
, RA
, RB
}},
2993 {"cget", APU(4, 284,0), APU_RA_MASK
, PPC405
, PPCNONE
, {RT
, FSL
}},
2994 {"vadduhs", VX (4, 576), VX_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
2995 {"vminuh", VX (4, 578), VX_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
2996 {"vsrh", VX (4, 580), VX_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
2997 {"vcmpgtuh", VXR(4, 582,0), VXR_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
2998 {"vmuleuh", VX (4, 584), VX_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
2999 {"vrfiz", VX (4, 586), VXVA_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VB
}},
3000 {"vsplth", VX (4, 588), VXUIMM3_MASK
,PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VB
, UIMM3
}},
3001 {"vupkhsh", VX (4, 590), VXVA_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VB
}},
3002 {"nget", APU(4, 300,0), APU_RA_MASK
, PPC405
, PPCNONE
, {RT
, FSL
}},
3003 {"evsel", EVSEL(4,79), EVSEL_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
, CRFS
}},
3004 {"ncget", APU(4, 316,0), APU_RA_MASK
, PPC405
, PPCNONE
, {RT
, FSL
}},
3005 {"evfsadd", VX (4, 640), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3006 {"vadduws", VX (4, 640), VX_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
3007 {"evfssub", VX (4, 641), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3008 {"vminuw", VX (4, 642), VX_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
3009 {"evfsabs", VX (4, 644), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
}},
3010 {"vsrw", VX (4, 644), VX_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
3011 {"evfsnabs", VX (4, 645), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
}},
3012 {"evfsneg", VX (4, 646), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
}},
3013 {"vcmpgtuw", VXR(4, 646,0), VXR_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
3014 {"evfsmul", VX (4, 648), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3015 {"evfsdiv", VX (4, 649), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3016 {"vrfip", VX (4, 650), VXVA_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VB
}},
3017 {"evfscmpgt", VX (4, 652), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {CRFD
, RA
, RB
}},
3018 {"vspltw", VX (4, 652), VXUIMM2_MASK
,PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VB
, UIMM2
}},
3019 {"evfscmplt", VX (4, 653), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {CRFD
, RA
, RB
}},
3020 {"evfscmpeq", VX (4, 654), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {CRFD
, RA
, RB
}},
3021 {"vupklsb", VX (4, 654), VXVA_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VB
}},
3022 {"evfscfui", VX (4, 656), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RB
}},
3023 {"evfscfsi", VX (4, 657), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RB
}},
3024 {"evfscfuf", VX (4, 658), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RB
}},
3025 {"evfscfsf", VX (4, 659), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RB
}},
3026 {"evfsctui", VX (4, 660), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RB
}},
3027 {"evfsctsi", VX (4, 661), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RB
}},
3028 {"evfsctuf", VX (4, 662), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RB
}},
3029 {"evfsctsf", VX (4, 663), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RB
}},
3030 {"evfsctuiz", VX (4, 664), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RB
}},
3031 {"put", APU(4, 332,0), APU_RT_MASK
, PPC405
, PPCNONE
, {RA
, FSL
}},
3032 {"evfsctsiz", VX (4, 666), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RB
}},
3033 {"evfststgt", VX (4, 668), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {CRFD
, RA
, RB
}},
3034 {"evfststlt", VX (4, 669), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {CRFD
, RA
, RB
}},
3035 {"evfststeq", VX (4, 670), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {CRFD
, RA
, RB
}},
3036 {"cput", APU(4, 348,0), APU_RT_MASK
, PPC405
, PPCNONE
, {RA
, FSL
}},
3037 {"efsadd", VX (4, 704), VX_MASK
, PPCEFS
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3038 {"efssub", VX (4, 705), VX_MASK
, PPCEFS
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3039 {"efsabs", VX (4, 708), VX_MASK
, PPCEFS
|PPCVLE
, PPCNONE
, {RS
, RA
}},
3040 {"vsr", VX (4, 708), VX_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
3041 {"efsnabs", VX (4, 709), VX_MASK
, PPCEFS
|PPCVLE
, PPCNONE
, {RS
, RA
}},
3042 {"efsneg", VX (4, 710), VX_MASK
, PPCEFS
|PPCVLE
, PPCNONE
, {RS
, RA
}},
3043 {"vcmpgtfp", VXR(4, 710,0), VXR_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
3044 {"efsmul", VX (4, 712), VX_MASK
, PPCEFS
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3045 {"efsdiv", VX (4, 713), VX_MASK
, PPCEFS
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3046 {"vrfim", VX (4, 714), VXVA_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VB
}},
3047 {"efscmpgt", VX (4, 716), VX_MASK
, PPCEFS
|PPCVLE
, PPCNONE
, {CRFD
, RA
, RB
}},
3048 {"efscmplt", VX (4, 717), VX_MASK
, PPCEFS
|PPCVLE
, PPCNONE
, {CRFD
, RA
, RB
}},
3049 {"efscmpeq", VX (4, 718), VX_MASK
, PPCEFS
|PPCVLE
, PPCNONE
, {CRFD
, RA
, RB
}},
3050 {"vupklsh", VX (4, 718), VXVA_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VB
}},
3051 {"efscfd", VX (4, 719), VX_MASK
, PPCEFS
|PPCVLE
, PPCNONE
, {RS
, RB
}},
3052 {"efscfui", VX (4, 720), VX_MASK
, PPCEFS
|PPCVLE
, PPCNONE
, {RS
, RB
}},
3053 {"efscfsi", VX (4, 721), VX_MASK
, PPCEFS
|PPCVLE
, PPCNONE
, {RS
, RB
}},
3054 {"efscfuf", VX (4, 722), VX_MASK
, PPCEFS
|PPCVLE
, PPCNONE
, {RS
, RB
}},
3055 {"efscfsf", VX (4, 723), VX_MASK
, PPCEFS
|PPCVLE
, PPCNONE
, {RS
, RB
}},
3056 {"efsctui", VX (4, 724), VX_MASK
, PPCEFS
|PPCVLE
, PPCNONE
, {RS
, RB
}},
3057 {"efsctsi", VX (4, 725), VX_MASK
, PPCEFS
|PPCVLE
, PPCNONE
, {RS
, RB
}},
3058 {"efsctuf", VX (4, 726), VX_MASK
, PPCEFS
|PPCVLE
, PPCNONE
, {RS
, RB
}},
3059 {"efsctsf", VX (4, 727), VX_MASK
, PPCEFS
|PPCVLE
, PPCNONE
, {RS
, RB
}},
3060 {"efsctuiz", VX (4, 728), VX_MASK
, PPCEFS
|PPCVLE
, PPCNONE
, {RS
, RB
}},
3061 {"nput", APU(4, 364,0), APU_RT_MASK
, PPC405
, PPCNONE
, {RA
, FSL
}},
3062 {"efsctsiz", VX (4, 730), VX_MASK
, PPCEFS
|PPCVLE
, PPCNONE
, {RS
, RB
}},
3063 {"efststgt", VX (4, 732), VX_MASK
, PPCEFS
|PPCVLE
, PPCNONE
, {CRFD
, RA
, RB
}},
3064 {"efststlt", VX (4, 733), VX_MASK
, PPCEFS
|PPCVLE
, PPCNONE
, {CRFD
, RA
, RB
}},
3065 {"efststeq", VX (4, 734), VX_MASK
, PPCEFS
|PPCVLE
, PPCNONE
, {CRFD
, RA
, RB
}},
3066 {"efdadd", VX (4, 736), VX_MASK
, PPCEFS
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3067 {"efdsub", VX (4, 737), VX_MASK
, PPCEFS
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3068 {"efdcfuid", VX (4, 738), VX_MASK
, PPCEFS
|PPCVLE
, PPCNONE
, {RS
, RB
}},
3069 {"efdcfsid", VX (4, 739), VX_MASK
, PPCEFS
|PPCVLE
, PPCNONE
, {RS
, RB
}},
3070 {"efdabs", VX (4, 740), VX_MASK
, PPCEFS
|PPCVLE
, PPCNONE
, {RS
, RA
}},
3071 {"efdnabs", VX (4, 741), VX_MASK
, PPCEFS
|PPCVLE
, PPCNONE
, {RS
, RA
}},
3072 {"efdneg", VX (4, 742), VX_MASK
, PPCEFS
|PPCVLE
, PPCNONE
, {RS
, RA
}},
3073 {"efdmul", VX (4, 744), VX_MASK
, PPCEFS
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3074 {"efddiv", VX (4, 745), VX_MASK
, PPCEFS
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3075 {"efdctuidz", VX (4, 746), VX_MASK
, PPCEFS
|PPCVLE
, PPCNONE
, {RS
, RB
}},
3076 {"efdctsidz", VX (4, 747), VX_MASK
, PPCEFS
|PPCVLE
, PPCNONE
, {RS
, RB
}},
3077 {"efdcmpgt", VX (4, 748), VX_MASK
, PPCEFS
|PPCVLE
, PPCNONE
, {CRFD
, RA
, RB
}},
3078 {"efdcmplt", VX (4, 749), VX_MASK
, PPCEFS
|PPCVLE
, PPCNONE
, {CRFD
, RA
, RB
}},
3079 {"efdcmpeq", VX (4, 750), VX_MASK
, PPCEFS
|PPCVLE
, PPCNONE
, {CRFD
, RA
, RB
}},
3080 {"efdcfs", VX (4, 751), VX_MASK
, PPCEFS
|PPCVLE
, PPCNONE
, {RS
, RB
}},
3081 {"efdcfui", VX (4, 752), VX_MASK
, PPCEFS
|PPCVLE
, PPCNONE
, {RS
, RB
}},
3082 {"efdcfsi", VX (4, 753), VX_MASK
, PPCEFS
|PPCVLE
, PPCNONE
, {RS
, RB
}},
3083 {"efdcfuf", VX (4, 754), VX_MASK
, PPCEFS
|PPCVLE
, PPCNONE
, {RS
, RB
}},
3084 {"efdcfsf", VX (4, 755), VX_MASK
, PPCEFS
|PPCVLE
, PPCNONE
, {RS
, RB
}},
3085 {"efdctui", VX (4, 756), VX_MASK
, PPCEFS
|PPCVLE
, PPCNONE
, {RS
, RB
}},
3086 {"efdctsi", VX (4, 757), VX_MASK
, PPCEFS
|PPCVLE
, PPCNONE
, {RS
, RB
}},
3087 {"efdctuf", VX (4, 758), VX_MASK
, PPCEFS
|PPCVLE
, PPCNONE
, {RS
, RB
}},
3088 {"efdctsf", VX (4, 759), VX_MASK
, PPCEFS
|PPCVLE
, PPCNONE
, {RS
, RB
}},
3089 {"efdctuiz", VX (4, 760), VX_MASK
, PPCEFS
|PPCVLE
, PPCNONE
, {RS
, RB
}},
3090 {"ncput", APU(4, 380,0), APU_RT_MASK
, PPC405
, PPCNONE
, {RA
, FSL
}},
3091 {"efdctsiz", VX (4, 762), VX_MASK
, PPCEFS
|PPCVLE
, PPCNONE
, {RS
, RB
}},
3092 {"efdtstgt", VX (4, 764), VX_MASK
, PPCEFS
|PPCVLE
, PPCNONE
, {CRFD
, RA
, RB
}},
3093 {"efdtstlt", VX (4, 765), VX_MASK
, PPCEFS
|PPCVLE
, PPCNONE
, {CRFD
, RA
, RB
}},
3094 {"efdtsteq", VX (4, 766), VX_MASK
, PPCEFS
|PPCVLE
, PPCNONE
, {CRFD
, RA
, RB
}},
3095 {"evlddx", VX (4, 768), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3096 {"vaddsbs", VX (4, 768), VX_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
3097 {"evldd", VX (4, 769), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, EVUIMM_8
, RA
}},
3098 {"evldwx", VX (4, 770), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3099 {"vminsb", VX (4, 770), VX_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
3100 {"evldw", VX (4, 771), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, EVUIMM_8
, RA
}},
3101 {"evldhx", VX (4, 772), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3102 {"vsrab", VX (4, 772), VX_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
3103 {"evldh", VX (4, 773), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, EVUIMM_8
, RA
}},
3104 {"vcmpgtsb", VXR(4, 774,0), VXR_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
3105 {"evlhhesplatx",VX (4, 776), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3106 {"vmulesb", VX (4, 776), VX_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
3107 {"evlhhesplat", VX (4, 777), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, EVUIMM_2
, RA
}},
3108 {"vcfux", VX (4, 778), VX_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VB
, UIMM
}},
3109 {"evlhhousplatx",VX(4, 780), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3110 {"vspltisb", VX (4, 780), VXVB_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, SIMM
}},
3111 {"evlhhousplat",VX (4, 781), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, EVUIMM_2
, RA
}},
3112 {"evlhhossplatx",VX(4, 782), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3113 {"vpkpx", VX (4, 782), VX_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
3114 {"evlhhossplat",VX (4, 783), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, EVUIMM_2
, RA
}},
3115 {"mullhwu", XRC(4, 392,0), X_MASK
, MULHW
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
3116 {"evlwhex", VX (4, 784), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3117 {"mullhwu.", XRC(4, 392,1), X_MASK
, MULHW
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
3118 {"evlwhe", VX (4, 785), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, EVUIMM_4
, RA
}},
3119 {"evlwhoux", VX (4, 788), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3120 {"evlwhou", VX (4, 789), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, EVUIMM_4
, RA
}},
3121 {"evlwhosx", VX (4, 790), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3122 {"evlwhos", VX (4, 791), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, EVUIMM_4
, RA
}},
3123 {"maclhwu", XO (4, 396,0,0),XO_MASK
, MULHW
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
3124 {"evlwwsplatx", VX (4, 792), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3125 {"maclhwu.", XO (4, 396,0,1),XO_MASK
, MULHW
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
3126 {"evlwwsplat", VX (4, 793), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, EVUIMM_4
, RA
}},
3127 {"evlwhsplatx", VX (4, 796), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3128 {"evlwhsplat", VX (4, 797), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, EVUIMM_4
, RA
}},
3129 {"evstddx", VX (4, 800), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3130 {"evstdd", VX (4, 801), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, EVUIMM_8
, RA
}},
3131 {"evstdwx", VX (4, 802), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3132 {"evstdw", VX (4, 803), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, EVUIMM_8
, RA
}},
3133 {"evstdhx", VX (4, 804), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3134 {"evstdh", VX (4, 805), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, EVUIMM_8
, RA
}},
3135 {"evstwhex", VX (4, 816), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3136 {"evstwhe", VX (4, 817), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, EVUIMM_4
, RA
}},
3137 {"evstwhox", VX (4, 820), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3138 {"evstwho", VX (4, 821), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, EVUIMM_4
, RA
}},
3139 {"evstwwex", VX (4, 824), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3140 {"evstwwe", VX (4, 825), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, EVUIMM_4
, RA
}},
3141 {"evstwwox", VX (4, 828), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3142 {"evstwwo", VX (4, 829), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, EVUIMM_4
, RA
}},
3143 {"vaddshs", VX (4, 832), VX_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
3144 {"vminsh", VX (4, 834), VX_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
3145 {"vsrah", VX (4, 836), VX_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
3146 {"vcmpgtsh", VXR(4, 838,0), VXR_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
3147 {"vmulesh", VX (4, 840), VX_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
3148 {"vcfsx", VX (4, 842), VX_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VB
, UIMM
}},
3149 {"vspltish", VX (4, 844), VXVB_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, SIMM
}},
3150 {"vupkhpx", VX (4, 846), VXVA_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VB
}},
3151 {"mullhw", XRC(4, 424,0), X_MASK
, MULHW
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
3152 {"mullhw.", XRC(4, 424,1), X_MASK
, MULHW
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
3153 {"maclhw", XO (4, 428,0,0),XO_MASK
, MULHW
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
3154 {"maclhw.", XO (4, 428,0,1),XO_MASK
, MULHW
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
3155 {"nmaclhw", XO (4, 430,0,0),XO_MASK
, MULHW
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
3156 {"nmaclhw.", XO (4, 430,0,1),XO_MASK
, MULHW
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
3157 {"vaddsws", VX (4, 896), VX_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
3158 {"vminsw", VX (4, 898), VX_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
3159 {"vsraw", VX (4, 900), VX_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
3160 {"vcmpgtsw", VXR(4, 902,0), VXR_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
3161 {"vctuxs", VX (4, 906), VX_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VB
, UIMM
}},
3162 {"vspltisw", VX (4, 908), VXVB_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, SIMM
}},
3163 {"maclhwsu", XO (4, 460,0,0),XO_MASK
, MULHW
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
3164 {"maclhwsu.", XO (4, 460,0,1),XO_MASK
, MULHW
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
3165 {"vcmpbfp", VXR(4, 966,0), VXR_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
3166 {"vctsxs", VX (4, 970), VX_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VB
, UIMM
}},
3167 {"vupklpx", VX (4, 974), VXVA_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VB
}},
3168 {"maclhws", XO (4, 492,0,0),XO_MASK
, MULHW
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
3169 {"maclhws.", XO (4, 492,0,1),XO_MASK
, MULHW
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
3170 {"nmaclhws", XO (4, 494,0,0),XO_MASK
, MULHW
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
3171 {"nmaclhws.", XO (4, 494,0,1),XO_MASK
, MULHW
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
3172 {"vsububm", VX (4,1024), VX_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
3173 {"vavgub", VX (4,1026), VX_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
3174 {"vabsdub", VX (4,1027), VX_MASK
, PPCVEC2
, PPCNONE
, {VD
, VA
, VB
}},
3175 {"evmhessf", VX (4,1027), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3176 {"vand", VX (4,1028), VX_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
3177 {"vcmpequb.", VXR(4, 6,1), VXR_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
3178 {"udi0fcm.", APU(4, 515,0), APU_MASK
, PPC405
|PPC440
, PPC476
, {URT
, URA
, URB
}},
3179 {"udi0fcm", APU(4, 515,1), APU_MASK
, PPC405
|PPC440
, PPC476
, {URT
, URA
, URB
}},
3180 {"evmhossf", VX (4,1031), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3181 {"evmheumi", VX (4,1032), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3182 {"evmhesmi", VX (4,1033), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3183 {"vmaxfp", VX (4,1034), VX_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
3184 {"evmhesmf", VX (4,1035), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3185 {"evmhoumi", VX (4,1036), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3186 {"vslo", VX (4,1036), VX_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
3187 {"evmhosmi", VX (4,1037), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3188 {"evmhosmf", VX (4,1039), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3189 {"machhwuo", XO (4, 12,1,0),XO_MASK
, MULHW
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
3190 {"machhwuo.", XO (4, 12,1,1),XO_MASK
, MULHW
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
3191 {"ps_merge00", XOPS(4,528,0), XOPS_MASK
, PPCPS
, PPCNONE
, {FRT
, FRA
, FRB
}},
3192 {"ps_merge00.", XOPS(4,528,1), XOPS_MASK
, PPCPS
, PPCNONE
, {FRT
, FRA
, FRB
}},
3193 {"evmhessfa", VX (4,1059), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3194 {"evmhossfa", VX (4,1063), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3195 {"evmheumia", VX (4,1064), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3196 {"evmhesmia", VX (4,1065), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3197 {"evmhesmfa", VX (4,1067), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3198 {"evmhoumia", VX (4,1068), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3199 {"evmhosmia", VX (4,1069), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3200 {"evmhosmfa", VX (4,1071), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3201 {"vsubuhm", VX (4,1088), VX_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
3202 {"vavguh", VX (4,1090), VX_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
3203 {"vabsduh", VX (4,1091), VX_MASK
, PPCVEC2
, PPCNONE
, {VD
, VA
, VB
}},
3204 {"vandc", VX (4,1092), VX_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
3205 {"vcmpequh.", VXR(4, 70,1), VXR_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
3206 {"udi1fcm.", APU(4, 547,0), APU_MASK
, PPC405
|PPC440
, PPC476
, {URT
, URA
, URB
}},
3207 {"udi1fcm", APU(4, 547,1), APU_MASK
, PPC405
|PPC440
, PPC476
, {URT
, URA
, URB
}},
3208 {"evmwhssf", VX (4,1095), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3209 {"evmwlumi", VX (4,1096), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3210 {"vminfp", VX (4,1098), VX_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
3211 {"evmwhumi", VX (4,1100), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3212 {"vsro", VX (4,1100), VX_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
3213 {"evmwhsmi", VX (4,1101), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3214 {"evmwhsmf", VX (4,1103), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3215 {"evmwssf", VX (4,1107), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3216 {"machhwo", XO (4, 44,1,0),XO_MASK
, MULHW
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
3217 {"evmwumi", VX (4,1112), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3218 {"machhwo.", XO (4, 44,1,1),XO_MASK
, MULHW
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
3219 {"evmwsmi", VX (4,1113), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3220 {"evmwsmf", VX (4,1115), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3221 {"nmachhwo", XO (4, 46,1,0),XO_MASK
, MULHW
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
3222 {"nmachhwo.", XO (4, 46,1,1),XO_MASK
, MULHW
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
3223 {"ps_merge01", XOPS(4,560,0), XOPS_MASK
, PPCPS
, PPCNONE
, {FRT
, FRA
, FRB
}},
3224 {"ps_merge01.", XOPS(4,560,1), XOPS_MASK
, PPCPS
, PPCNONE
, {FRT
, FRA
, FRB
}},
3225 {"evmwhssfa", VX (4,1127), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3226 {"evmwlumia", VX (4,1128), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3227 {"evmwhumia", VX (4,1132), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3228 {"evmwhsmia", VX (4,1133), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3229 {"evmwhsmfa", VX (4,1135), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3230 {"evmwssfa", VX (4,1139), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3231 {"evmwumia", VX (4,1144), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3232 {"evmwsmia", VX (4,1145), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3233 {"evmwsmfa", VX (4,1147), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3234 {"vsubuwm", VX (4,1152), VX_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
3235 {"vavguw", VX (4,1154), VX_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
3236 {"vabsduw", VX (4,1155), VX_MASK
, PPCVEC2
, PPCNONE
, {VD
, VA
, VB
}},
3237 {"vor", VX (4,1156), VX_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
3238 {"vcmpequw.", VXR(4, 134,1), VXR_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
3239 {"udi2fcm.", APU(4, 579,0), APU_MASK
, PPC405
|PPC440
, PPC476
, {URT
, URA
, URB
}},
3240 {"udi2fcm", APU(4, 579,1), APU_MASK
, PPC405
|PPC440
, PPC476
, {URT
, URA
, URB
}},
3241 {"machhwsuo", XO (4, 76,1,0),XO_MASK
, MULHW
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
3242 {"machhwsuo.", XO (4, 76,1,1),XO_MASK
, MULHW
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
3243 {"ps_merge10", XOPS(4,592,0), XOPS_MASK
, PPCPS
, PPCNONE
, {FRT
, FRA
, FRB
}},
3244 {"ps_merge10.", XOPS(4,592,1), XOPS_MASK
, PPCPS
, PPCNONE
, {FRT
, FRA
, FRB
}},
3245 {"evaddusiaaw", VX (4,1216), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
}},
3246 {"evaddssiaaw", VX (4,1217), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
}},
3247 {"evsubfusiaaw",VX (4,1218), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
}},
3248 {"evsubfssiaaw",VX (4,1219), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
}},
3249 {"evmra", VX (4,1220), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
}},
3250 {"vxor", VX (4,1220), VX_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
3251 {"evdivws", VX (4,1222), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3252 {"vcmpeqfp.", VXR(4, 198,1), VXR_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
3253 {"udi3fcm.", APU(4, 611,0), APU_MASK
, PPC405
|PPC440
, PPC476
, {URT
, URA
, URB
}},
3254 {"udi3fcm", APU(4, 611,1), APU_MASK
, PPC405
|PPC440
, PPC476
, {URT
, URA
, URB
}},
3255 {"evdivwu", VX (4,1223), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3256 {"evaddumiaaw", VX (4,1224), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
}},
3257 {"evaddsmiaaw", VX (4,1225), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
}},
3258 {"evsubfumiaaw",VX (4,1226), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
}},
3259 {"evsubfsmiaaw",VX (4,1227), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
}},
3260 {"machhwso", XO (4, 108,1,0),XO_MASK
, MULHW
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
3261 {"machhwso.", XO (4, 108,1,1),XO_MASK
, MULHW
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
3262 {"nmachhwso", XO (4, 110,1,0),XO_MASK
, MULHW
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
3263 {"nmachhwso.", XO (4, 110,1,1),XO_MASK
, MULHW
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
3264 {"ps_merge11", XOPS(4,624,0), XOPS_MASK
, PPCPS
, PPCNONE
, {FRT
, FRA
, FRB
}},
3265 {"ps_merge11.", XOPS(4,624,1), XOPS_MASK
, PPCPS
, PPCNONE
, {FRT
, FRA
, FRB
}},
3266 {"evmheusiaaw", VX (4,1280), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3267 {"evmhessiaaw", VX (4,1281), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3268 {"vavgsb", VX (4,1282), VX_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
3269 {"evmhessfaaw", VX (4,1283), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3270 {"evmhousiaaw", VX (4,1284), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3271 {"vnor", VX (4,1284), VX_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
3272 {"evmhossiaaw", VX (4,1285), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3273 {"udi4fcm.", APU(4, 643,0), APU_MASK
, PPC405
|PPC440
, PPC476
, {URT
, URA
, URB
}},
3274 {"udi4fcm", APU(4, 643,1), APU_MASK
, PPC405
|PPC440
, PPC476
, {URT
, URA
, URB
}},
3275 {"evmhossfaaw", VX (4,1287), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3276 {"evmheumiaaw", VX (4,1288), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3277 {"evmhesmiaaw", VX (4,1289), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3278 {"evmhesmfaaw", VX (4,1291), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3279 {"evmhoumiaaw", VX (4,1292), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3280 {"evmhosmiaaw", VX (4,1293), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3281 {"evmhosmfaaw", VX (4,1295), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3282 {"macchwuo", XO (4, 140,1,0),XO_MASK
, MULHW
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
3283 {"macchwuo.", XO (4, 140,1,1),XO_MASK
, MULHW
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
3284 {"evmhegumiaa", VX (4,1320), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3285 {"evmhegsmiaa", VX (4,1321), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3286 {"evmhegsmfaa", VX (4,1323), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3287 {"evmhogumiaa", VX (4,1324), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3288 {"evmhogsmiaa", VX (4,1325), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3289 {"evmhogsmfaa", VX (4,1327), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3290 {"evmwlusiaaw", VX (4,1344), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3291 {"evmwlssiaaw", VX (4,1345), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3292 {"vavgsh", VX (4,1346), VX_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
3293 {"udi5fcm.", APU(4, 675,0), APU_MASK
, PPC405
|PPC440
, PPC476
, {URT
, URA
, URB
}},
3294 {"udi5fcm", APU(4, 675,1), APU_MASK
, PPC405
|PPC440
, PPC476
, {URT
, URA
, URB
}},
3295 {"evmwlumiaaw", VX (4,1352), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3296 {"evmwlsmiaaw", VX (4,1353), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3297 {"evmwssfaa", VX (4,1363), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3298 {"macchwo", XO (4, 172,1,0),XO_MASK
, MULHW
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
3299 {"evmwumiaa", VX (4,1368), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3300 {"macchwo.", XO (4, 172,1,1),XO_MASK
, MULHW
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
3301 {"evmwsmiaa", VX (4,1369), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3302 {"evmwsmfaa", VX (4,1371), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3303 {"nmacchwo", XO (4, 174,1,0),XO_MASK
, MULHW
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
3304 {"nmacchwo.", XO (4, 174,1,1),XO_MASK
, MULHW
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
3305 {"evmheusianw", VX (4,1408), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3306 {"vsubcuw", VX (4,1408), VX_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
3307 {"evmhessianw", VX (4,1409), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3308 {"vavgsw", VX (4,1410), VX_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
3309 {"evmhessfanw", VX (4,1411), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3310 {"evmhousianw", VX (4,1412), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3311 {"evmhossianw", VX (4,1413), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3312 {"udi6fcm.", APU(4, 707,0), APU_MASK
, PPC405
|PPC440
, PPC476
, {URT
, URA
, URB
}},
3313 {"udi6fcm", APU(4, 707,1), APU_MASK
, PPC405
|PPC440
, PPC476
, {URT
, URA
, URB
}},
3314 {"evmhossfanw", VX (4,1415), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3315 {"evmheumianw", VX (4,1416), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3316 {"evmhesmianw", VX (4,1417), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3317 {"evmhesmfanw", VX (4,1419), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3318 {"evmhoumianw", VX (4,1420), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3319 {"evmhosmianw", VX (4,1421), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3320 {"evmhosmfanw", VX (4,1423), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3321 {"macchwsuo", XO (4, 204,1,0),XO_MASK
, MULHW
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
3322 {"macchwsuo.", XO (4, 204,1,1),XO_MASK
, MULHW
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
3323 {"evmhegumian", VX (4,1448), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3324 {"evmhegsmian", VX (4,1449), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3325 {"evmhegsmfan", VX (4,1451), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3326 {"evmhogumian", VX (4,1452), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3327 {"evmhogsmian", VX (4,1453), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3328 {"evmhogsmfan", VX (4,1455), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3329 {"evmwlusianw", VX (4,1472), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3330 {"evmwlssianw", VX (4,1473), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3331 {"vcmpgefp.", VXR(4, 454,1), VXR_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
3332 {"udi7fcm.", APU(4, 739,0), APU_MASK
, PPC405
|PPC440
, PPC476
, {URT
, URA
, URB
}},
3333 {"udi7fcm", APU(4, 739,1), APU_MASK
, PPC405
|PPC440
, PPC476
, {URT
, URA
, URB
}},
3334 {"evmwlumianw", VX (4,1480), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3335 {"evmwlsmianw", VX (4,1481), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3336 {"evmwssfan", VX (4,1491), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3337 {"macchwso", XO (4, 236,1,0),XO_MASK
, MULHW
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
3338 {"evmwumian", VX (4,1496), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3339 {"macchwso.", XO (4, 236,1,1),XO_MASK
, MULHW
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
3340 {"evmwsmian", VX (4,1497), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3341 {"evmwsmfan", VX (4,1499), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3342 {"nmacchwso", XO (4, 238,1,0),XO_MASK
, MULHW
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
3343 {"nmacchwso.", XO (4, 238,1,1),XO_MASK
, MULHW
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
3344 {"vsububs", VX (4,1536), VX_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
3345 {"mfvscr", VX (4,1540), VXVAVB_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
}},
3346 {"vcmpgtub.", VXR(4, 518,1), VXR_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
3347 {"udi8fcm.", APU(4, 771,0), APU_MASK
, PPC440
, PPC476
, {URT
, URA
, URB
}},
3348 {"udi8fcm", APU(4, 771,1), APU_MASK
, PPC440
, PPC476
, {URT
, URA
, URB
}},
3349 {"vsum4ubs", VX (4,1544), VX_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
3350 {"vsubuhs", VX (4,1600), VX_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
3351 {"mtvscr", VX (4,1604), VXVDVA_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VB
}},
3352 {"vcmpgtuh.", VXR(4, 582,1), VXR_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
3353 {"vsum4shs", VX (4,1608), VX_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
3354 {"udi9fcm.", APU(4, 804,0), APU_MASK
, PPC440
, PPC476
, {URT
, URA
, URB
}},
3355 {"udi9fcm", APU(4, 804,1), APU_MASK
, PPC440
, PPC476
, {URT
, URA
, URB
}},
3356 {"vsubuws", VX (4,1664), VX_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
3357 {"vcmpgtuw.", VXR(4, 646,1), VXR_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
3358 {"udi10fcm.", APU(4, 835,0), APU_MASK
, PPC440
, PPC476
, {URT
, URA
, URB
}},
3359 {"udi10fcm", APU(4, 835,1), APU_MASK
, PPC440
, PPC476
, {URT
, URA
, URB
}},
3360 {"vsum2sws", VX (4,1672), VX_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
3361 {"vcmpgtfp.", VXR(4, 710,1), VXR_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
3362 {"udi11fcm.", APU(4, 867,0), APU_MASK
, PPC440
, PPC476
, {URT
, URA
, URB
}},
3363 {"udi11fcm", APU(4, 867,1), APU_MASK
, PPC440
, PPC476
, {URT
, URA
, URB
}},
3364 {"vsubsbs", VX (4,1792), VX_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
3365 {"vcmpgtsb.", VXR(4, 774,1), VXR_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
3366 {"udi12fcm.", APU(4, 899,0), APU_MASK
, PPC440
, PPC476
, {URT
, URA
, URB
}},
3367 {"udi12fcm", APU(4, 899,1), APU_MASK
, PPC440
, PPC476
, {URT
, URA
, URB
}},
3368 {"vsum4sbs", VX (4,1800), VX_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
3369 {"maclhwuo", XO (4, 396,1,0),XO_MASK
, MULHW
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
3370 {"maclhwuo.", XO (4, 396,1,1),XO_MASK
, MULHW
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
3371 {"vsubshs", VX (4,1856), VX_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
3372 {"vcmpgtsh.", VXR(4, 838,1), VXR_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
3373 {"udi13fcm.", APU(4, 931,0), APU_MASK
, PPC440
, PPC476
, {URT
, URA
, URB
}},
3374 {"udi13fcm", APU(4, 931,1), APU_MASK
, PPC440
, PPC476
, {URT
, URA
, URB
}},
3375 {"maclhwo", XO (4, 428,1,0),XO_MASK
, MULHW
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
3376 {"maclhwo.", XO (4, 428,1,1),XO_MASK
, MULHW
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
3377 {"nmaclhwo", XO (4, 430,1,0),XO_MASK
, MULHW
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
3378 {"nmaclhwo.", XO (4, 430,1,1),XO_MASK
, MULHW
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
3379 {"vsubsws", VX (4,1920), VX_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
3380 {"vcmpgtsw.", VXR(4, 902,1), VXR_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
3381 {"udi14fcm.", APU(4, 963,0), APU_MASK
, PPC440
, PPC476
, {URT
, URA
, URB
}},
3382 {"udi14fcm", APU(4, 963,1), APU_MASK
, PPC440
, PPC476
, {URT
, URA
, URB
}},
3383 {"vsumsws", VX (4,1928), VX_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
3384 {"maclhwsuo", XO (4, 460,1,0),XO_MASK
, MULHW
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
3385 {"maclhwsuo.", XO (4, 460,1,1),XO_MASK
, MULHW
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
3386 {"vcmpbfp.", VXR(4, 966,1), VXR_MASK
, PPCVEC
, PPCNONE
, {VD
, VA
, VB
}},
3387 {"udi15fcm.", APU(4, 995,0), APU_MASK
, PPC440
, PPC476
, {URT
, URA
, URB
}},
3388 {"udi15fcm", APU(4, 995,1), APU_MASK
, PPC440
, PPC476
, {URT
, URA
, URB
}},
3389 {"maclhwso", XO (4, 492,1,0),XO_MASK
, MULHW
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
3390 {"maclhwso.", XO (4, 492,1,1),XO_MASK
, MULHW
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
3391 {"nmaclhwso", XO (4, 494,1,0),XO_MASK
, MULHW
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
3392 {"nmaclhwso.", XO (4, 494,1,1),XO_MASK
, MULHW
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
3393 {"dcbz_l", X (4,1014), XRT_MASK
, PPCPS
, PPCNONE
, {RA
, RB
}},
3395 {"mulli", OP(7), OP_MASK
, PPCCOM
, PPCNONE
, {RT
, RA
, SI
}},
3396 {"muli", OP(7), OP_MASK
, PWRCOM
, PPCNONE
, {RT
, RA
, SI
}},
3398 {"subfic", OP(8), OP_MASK
, PPCCOM
, PPCNONE
, {RT
, RA
, SI
}},
3399 {"sfi", OP(8), OP_MASK
, PWRCOM
, PPCNONE
, {RT
, RA
, SI
}},
3401 {"dozi", OP(9), OP_MASK
, M601
, PPCNONE
, {RT
, RA
, SI
}},
3403 {"cmplwi", OPL(10,0), OPL_MASK
, PPCCOM
, PPCNONE
, {OBF
, RA
, UI
}},
3404 {"cmpldi", OPL(10,1), OPL_MASK
, PPC64
, PPCNONE
, {OBF
, RA
, UI
}},
3405 {"cmpli", OP(10), OP_MASK
, PPC
, PPCNONE
, {BF
, L
, RA
, UI
}},
3406 {"cmpli", OP(10), OP_MASK
, PWRCOM
, PPC
, {BF
, RA
, UI
}},
3408 {"cmpwi", OPL(11,0), OPL_MASK
, PPCCOM
, PPCNONE
, {OBF
, RA
, SI
}},
3409 {"cmpdi", OPL(11,1), OPL_MASK
, PPC64
, PPCNONE
, {OBF
, RA
, SI
}},
3410 {"cmpi", OP(11), OP_MASK
, PPC
, PPCNONE
, {BF
, L
, RA
, SI
}},
3411 {"cmpi", OP(11), OP_MASK
, PWRCOM
, PPC
, {BF
, RA
, SI
}},
3413 {"addic", OP(12), OP_MASK
, PPCCOM
, PPCNONE
, {RT
, RA
, SI
}},
3414 {"ai", OP(12), OP_MASK
, PWRCOM
, PPCNONE
, {RT
, RA
, SI
}},
3415 {"subic", OP(12), OP_MASK
, PPCCOM
, PPCNONE
, {RT
, RA
, NSI
}},
3417 {"addic.", OP(13), OP_MASK
, PPCCOM
, PPCNONE
, {RT
, RA
, SI
}},
3418 {"ai.", OP(13), OP_MASK
, PWRCOM
, PPCNONE
, {RT
, RA
, SI
}},
3419 {"subic.", OP(13), OP_MASK
, PPCCOM
, PPCNONE
, {RT
, RA
, NSI
}},
3421 {"li", OP(14), DRA_MASK
, PPCCOM
, PPCNONE
, {RT
, SI
}},
3422 {"lil", OP(14), DRA_MASK
, PWRCOM
, PPCNONE
, {RT
, SI
}},
3423 {"addi", OP(14), OP_MASK
, PPCCOM
, PPCNONE
, {RT
, RA0
, SI
}},
3424 {"cal", OP(14), OP_MASK
, PWRCOM
, PPCNONE
, {RT
, D
, RA0
}},
3425 {"subi", OP(14), OP_MASK
, PPCCOM
, PPCNONE
, {RT
, RA0
, NSI
}},
3426 {"la", OP(14), OP_MASK
, PPCCOM
, PPCNONE
, {RT
, D
, RA0
}},
3428 {"lis", OP(15), DRA_MASK
, PPCCOM
, PPCNONE
, {RT
, SISIGNOPT
}},
3429 {"liu", OP(15), DRA_MASK
, PWRCOM
, PPCNONE
, {RT
, SISIGNOPT
}},
3430 {"addis", OP(15), OP_MASK
, PPCCOM
, PPCNONE
, {RT
, RA0
, SISIGNOPT
}},
3431 {"cau", OP(15), OP_MASK
, PWRCOM
, PPCNONE
, {RT
, RA0
, SISIGNOPT
}},
3432 {"subis", OP(15), OP_MASK
, PPCCOM
, PPCNONE
, {RT
, RA0
, NSI
}},
3434 {"bdnz-", BBO(16,BODNZ
,0,0), BBOATBI_MASK
, PPCCOM
, PPCNONE
, {BDM
}},
3435 {"bdnz+", BBO(16,BODNZ
,0,0), BBOATBI_MASK
, PPCCOM
, PPCNONE
, {BDP
}},
3436 {"bdnz", BBO(16,BODNZ
,0,0), BBOATBI_MASK
, PPCCOM
, PPCNONE
, {BD
}},
3437 {"bdn", BBO(16,BODNZ
,0,0), BBOATBI_MASK
, PWRCOM
, PPCNONE
, {BD
}},
3438 {"bdnzl-", BBO(16,BODNZ
,0,1), BBOATBI_MASK
, PPCCOM
, PPCNONE
, {BDM
}},
3439 {"bdnzl+", BBO(16,BODNZ
,0,1), BBOATBI_MASK
, PPCCOM
, PPCNONE
, {BDP
}},
3440 {"bdnzl", BBO(16,BODNZ
,0,1), BBOATBI_MASK
, PPCCOM
, PPCNONE
, {BD
}},
3441 {"bdnl", BBO(16,BODNZ
,0,1), BBOATBI_MASK
, PWRCOM
, PPCNONE
, {BD
}},
3442 {"bdnza-", BBO(16,BODNZ
,1,0), BBOATBI_MASK
, PPCCOM
, PPCNONE
, {BDMA
}},
3443 {"bdnza+", BBO(16,BODNZ
,1,0), BBOATBI_MASK
, PPCCOM
, PPCNONE
, {BDPA
}},
3444 {"bdnza", BBO(16,BODNZ
,1,0), BBOATBI_MASK
, PPCCOM
, PPCNONE
, {BDA
}},
3445 {"bdna", BBO(16,BODNZ
,1,0), BBOATBI_MASK
, PWRCOM
, PPCNONE
, {BDA
}},
3446 {"bdnzla-", BBO(16,BODNZ
,1,1), BBOATBI_MASK
, PPCCOM
, PPCNONE
, {BDMA
}},
3447 {"bdnzla+", BBO(16,BODNZ
,1,1), BBOATBI_MASK
, PPCCOM
, PPCNONE
, {BDPA
}},
3448 {"bdnzla", BBO(16,BODNZ
,1,1), BBOATBI_MASK
, PPCCOM
, PPCNONE
, {BDA
}},
3449 {"bdnla", BBO(16,BODNZ
,1,1), BBOATBI_MASK
, PWRCOM
, PPCNONE
, {BDA
}},
3450 {"bdz-", BBO(16,BODZ
,0,0), BBOATBI_MASK
, PPCCOM
, PPCNONE
, {BDM
}},
3451 {"bdz+", BBO(16,BODZ
,0,0), BBOATBI_MASK
, PPCCOM
, PPCNONE
, {BDP
}},
3452 {"bdz", BBO(16,BODZ
,0,0), BBOATBI_MASK
, COM
, PPCNONE
, {BD
}},
3453 {"bdzl-", BBO(16,BODZ
,0,1), BBOATBI_MASK
, PPCCOM
, PPCNONE
, {BDM
}},
3454 {"bdzl+", BBO(16,BODZ
,0,1), BBOATBI_MASK
, PPCCOM
, PPCNONE
, {BDP
}},
3455 {"bdzl", BBO(16,BODZ
,0,1), BBOATBI_MASK
, COM
, PPCNONE
, {BD
}},
3456 {"bdza-", BBO(16,BODZ
,1,0), BBOATBI_MASK
, PPCCOM
, PPCNONE
, {BDMA
}},
3457 {"bdza+", BBO(16,BODZ
,1,0), BBOATBI_MASK
, PPCCOM
, PPCNONE
, {BDPA
}},
3458 {"bdza", BBO(16,BODZ
,1,0), BBOATBI_MASK
, COM
, PPCNONE
, {BDA
}},
3459 {"bdzla-", BBO(16,BODZ
,1,1), BBOATBI_MASK
, PPCCOM
, PPCNONE
, {BDMA
}},
3460 {"bdzla+", BBO(16,BODZ
,1,1), BBOATBI_MASK
, PPCCOM
, PPCNONE
, {BDPA
}},
3461 {"bdzla", BBO(16,BODZ
,1,1), BBOATBI_MASK
, COM
, PPCNONE
, {BDA
}},
3463 {"bge-", BBOCB(16,BOF
,CBLT
,0,0), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BDM
}},
3464 {"bge+", BBOCB(16,BOF
,CBLT
,0,0), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BDP
}},
3465 {"bge", BBOCB(16,BOF
,CBLT
,0,0), BBOATCB_MASK
, COM
, PPCNONE
, {CR
, BD
}},
3466 {"bnl-", BBOCB(16,BOF
,CBLT
,0,0), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BDM
}},
3467 {"bnl+", BBOCB(16,BOF
,CBLT
,0,0), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BDP
}},
3468 {"bnl", BBOCB(16,BOF
,CBLT
,0,0), BBOATCB_MASK
, COM
, PPCNONE
, {CR
, BD
}},
3469 {"bgel-", BBOCB(16,BOF
,CBLT
,0,1), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BDM
}},
3470 {"bgel+", BBOCB(16,BOF
,CBLT
,0,1), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BDP
}},
3471 {"bgel", BBOCB(16,BOF
,CBLT
,0,1), BBOATCB_MASK
, COM
, PPCNONE
, {CR
, BD
}},
3472 {"bnll-", BBOCB(16,BOF
,CBLT
,0,1), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BDM
}},
3473 {"bnll+", BBOCB(16,BOF
,CBLT
,0,1), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BDP
}},
3474 {"bnll", BBOCB(16,BOF
,CBLT
,0,1), BBOATCB_MASK
, COM
, PPCNONE
, {CR
, BD
}},
3475 {"bgea-", BBOCB(16,BOF
,CBLT
,1,0), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BDMA
}},
3476 {"bgea+", BBOCB(16,BOF
,CBLT
,1,0), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BDPA
}},
3477 {"bgea", BBOCB(16,BOF
,CBLT
,1,0), BBOATCB_MASK
, COM
, PPCNONE
, {CR
, BDA
}},
3478 {"bnla-", BBOCB(16,BOF
,CBLT
,1,0), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BDMA
}},
3479 {"bnla+", BBOCB(16,BOF
,CBLT
,1,0), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BDPA
}},
3480 {"bnla", BBOCB(16,BOF
,CBLT
,1,0), BBOATCB_MASK
, COM
, PPCNONE
, {CR
, BDA
}},
3481 {"bgela-", BBOCB(16,BOF
,CBLT
,1,1), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BDMA
}},
3482 {"bgela+", BBOCB(16,BOF
,CBLT
,1,1), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BDPA
}},
3483 {"bgela", BBOCB(16,BOF
,CBLT
,1,1), BBOATCB_MASK
, COM
, PPCNONE
, {CR
, BDA
}},
3484 {"bnlla-", BBOCB(16,BOF
,CBLT
,1,1), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BDMA
}},
3485 {"bnlla+", BBOCB(16,BOF
,CBLT
,1,1), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BDPA
}},
3486 {"bnlla", BBOCB(16,BOF
,CBLT
,1,1), BBOATCB_MASK
, COM
, PPCNONE
, {CR
, BDA
}},
3487 {"ble-", BBOCB(16,BOF
,CBGT
,0,0), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BDM
}},
3488 {"ble+", BBOCB(16,BOF
,CBGT
,0,0), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BDP
}},
3489 {"ble", BBOCB(16,BOF
,CBGT
,0,0), BBOATCB_MASK
, COM
, PPCNONE
, {CR
, BD
}},
3490 {"bng-", BBOCB(16,BOF
,CBGT
,0,0), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BDM
}},
3491 {"bng+", BBOCB(16,BOF
,CBGT
,0,0), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BDP
}},
3492 {"bng", BBOCB(16,BOF
,CBGT
,0,0), BBOATCB_MASK
, COM
, PPCNONE
, {CR
, BD
}},
3493 {"blel-", BBOCB(16,BOF
,CBGT
,0,1), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BDM
}},
3494 {"blel+", BBOCB(16,BOF
,CBGT
,0,1), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BDP
}},
3495 {"blel", BBOCB(16,BOF
,CBGT
,0,1), BBOATCB_MASK
, COM
, PPCNONE
, {CR
, BD
}},
3496 {"bngl-", BBOCB(16,BOF
,CBGT
,0,1), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BDM
}},
3497 {"bngl+", BBOCB(16,BOF
,CBGT
,0,1), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BDP
}},
3498 {"bngl", BBOCB(16,BOF
,CBGT
,0,1), BBOATCB_MASK
, COM
, PPCNONE
, {CR
, BD
}},
3499 {"blea-", BBOCB(16,BOF
,CBGT
,1,0), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BDMA
}},
3500 {"blea+", BBOCB(16,BOF
,CBGT
,1,0), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BDPA
}},
3501 {"blea", BBOCB(16,BOF
,CBGT
,1,0), BBOATCB_MASK
, COM
, PPCNONE
, {CR
, BDA
}},
3502 {"bnga-", BBOCB(16,BOF
,CBGT
,1,0), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BDMA
}},
3503 {"bnga+", BBOCB(16,BOF
,CBGT
,1,0), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BDPA
}},
3504 {"bnga", BBOCB(16,BOF
,CBGT
,1,0), BBOATCB_MASK
, COM
, PPCNONE
, {CR
, BDA
}},
3505 {"blela-", BBOCB(16,BOF
,CBGT
,1,1), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BDMA
}},
3506 {"blela+", BBOCB(16,BOF
,CBGT
,1,1), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BDPA
}},
3507 {"blela", BBOCB(16,BOF
,CBGT
,1,1), BBOATCB_MASK
, COM
, PPCNONE
, {CR
, BDA
}},
3508 {"bngla-", BBOCB(16,BOF
,CBGT
,1,1), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BDMA
}},
3509 {"bngla+", BBOCB(16,BOF
,CBGT
,1,1), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BDPA
}},
3510 {"bngla", BBOCB(16,BOF
,CBGT
,1,1), BBOATCB_MASK
, COM
, PPCNONE
, {CR
, BDA
}},
3511 {"bne-", BBOCB(16,BOF
,CBEQ
,0,0), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BDM
}},
3512 {"bne+", BBOCB(16,BOF
,CBEQ
,0,0), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BDP
}},
3513 {"bne", BBOCB(16,BOF
,CBEQ
,0,0), BBOATCB_MASK
, COM
, PPCNONE
, {CR
, BD
}},
3514 {"bnel-", BBOCB(16,BOF
,CBEQ
,0,1), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BDM
}},
3515 {"bnel+", BBOCB(16,BOF
,CBEQ
,0,1), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BDP
}},
3516 {"bnel", BBOCB(16,BOF
,CBEQ
,0,1), BBOATCB_MASK
, COM
, PPCNONE
, {CR
, BD
}},
3517 {"bnea-", BBOCB(16,BOF
,CBEQ
,1,0), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BDMA
}},
3518 {"bnea+", BBOCB(16,BOF
,CBEQ
,1,0), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BDPA
}},
3519 {"bnea", BBOCB(16,BOF
,CBEQ
,1,0), BBOATCB_MASK
, COM
, PPCNONE
, {CR
, BDA
}},
3520 {"bnela-", BBOCB(16,BOF
,CBEQ
,1,1), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BDMA
}},
3521 {"bnela+", BBOCB(16,BOF
,CBEQ
,1,1), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BDPA
}},
3522 {"bnela", BBOCB(16,BOF
,CBEQ
,1,1), BBOATCB_MASK
, COM
, PPCNONE
, {CR
, BDA
}},
3523 {"bns-", BBOCB(16,BOF
,CBSO
,0,0), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BDM
}},
3524 {"bns+", BBOCB(16,BOF
,CBSO
,0,0), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BDP
}},
3525 {"bns", BBOCB(16,BOF
,CBSO
,0,0), BBOATCB_MASK
, COM
, PPCNONE
, {CR
, BD
}},
3526 {"bnu-", BBOCB(16,BOF
,CBSO
,0,0), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BDM
}},
3527 {"bnu+", BBOCB(16,BOF
,CBSO
,0,0), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BDP
}},
3528 {"bnu", BBOCB(16,BOF
,CBSO
,0,0), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BD
}},
3529 {"bnsl-", BBOCB(16,BOF
,CBSO
,0,1), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BDM
}},
3530 {"bnsl+", BBOCB(16,BOF
,CBSO
,0,1), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BDP
}},
3531 {"bnsl", BBOCB(16,BOF
,CBSO
,0,1), BBOATCB_MASK
, COM
, PPCNONE
, {CR
, BD
}},
3532 {"bnul-", BBOCB(16,BOF
,CBSO
,0,1), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BDM
}},
3533 {"bnul+", BBOCB(16,BOF
,CBSO
,0,1), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BDP
}},
3534 {"bnul", BBOCB(16,BOF
,CBSO
,0,1), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BD
}},
3535 {"bnsa-", BBOCB(16,BOF
,CBSO
,1,0), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BDMA
}},
3536 {"bnsa+", BBOCB(16,BOF
,CBSO
,1,0), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BDPA
}},
3537 {"bnsa", BBOCB(16,BOF
,CBSO
,1,0), BBOATCB_MASK
, COM
, PPCNONE
, {CR
, BDA
}},
3538 {"bnua-", BBOCB(16,BOF
,CBSO
,1,0), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BDMA
}},
3539 {"bnua+", BBOCB(16,BOF
,CBSO
,1,0), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BDPA
}},
3540 {"bnua", BBOCB(16,BOF
,CBSO
,1,0), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BDA
}},
3541 {"bnsla-", BBOCB(16,BOF
,CBSO
,1,1), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BDMA
}},
3542 {"bnsla+", BBOCB(16,BOF
,CBSO
,1,1), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BDPA
}},
3543 {"bnsla", BBOCB(16,BOF
,CBSO
,1,1), BBOATCB_MASK
, COM
, PPCNONE
, {CR
, BDA
}},
3544 {"bnula-", BBOCB(16,BOF
,CBSO
,1,1), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BDMA
}},
3545 {"bnula+", BBOCB(16,BOF
,CBSO
,1,1), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BDPA
}},
3546 {"bnula", BBOCB(16,BOF
,CBSO
,1,1), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BDA
}},
3548 {"blt-", BBOCB(16,BOT
,CBLT
,0,0), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BDM
}},
3549 {"blt+", BBOCB(16,BOT
,CBLT
,0,0), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BDP
}},
3550 {"blt", BBOCB(16,BOT
,CBLT
,0,0), BBOATCB_MASK
, COM
, PPCNONE
, {CR
, BD
}},
3551 {"bltl-", BBOCB(16,BOT
,CBLT
,0,1), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BDM
}},
3552 {"bltl+", BBOCB(16,BOT
,CBLT
,0,1), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BDP
}},
3553 {"bltl", BBOCB(16,BOT
,CBLT
,0,1), BBOATCB_MASK
, COM
, PPCNONE
, {CR
, BD
}},
3554 {"blta-", BBOCB(16,BOT
,CBLT
,1,0), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BDMA
}},
3555 {"blta+", BBOCB(16,BOT
,CBLT
,1,0), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BDPA
}},
3556 {"blta", BBOCB(16,BOT
,CBLT
,1,0), BBOATCB_MASK
, COM
, PPCNONE
, {CR
, BDA
}},
3557 {"bltla-", BBOCB(16,BOT
,CBLT
,1,1), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BDMA
}},
3558 {"bltla+", BBOCB(16,BOT
,CBLT
,1,1), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BDPA
}},
3559 {"bltla", BBOCB(16,BOT
,CBLT
,1,1), BBOATCB_MASK
, COM
, PPCNONE
, {CR
, BDA
}},
3560 {"bgt-", BBOCB(16,BOT
,CBGT
,0,0), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BDM
}},
3561 {"bgt+", BBOCB(16,BOT
,CBGT
,0,0), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BDP
}},
3562 {"bgt", BBOCB(16,BOT
,CBGT
,0,0), BBOATCB_MASK
, COM
, PPCNONE
, {CR
, BD
}},
3563 {"bgtl-", BBOCB(16,BOT
,CBGT
,0,1), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BDM
}},
3564 {"bgtl+", BBOCB(16,BOT
,CBGT
,0,1), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BDP
}},
3565 {"bgtl", BBOCB(16,BOT
,CBGT
,0,1), BBOATCB_MASK
, COM
, PPCNONE
, {CR
, BD
}},
3566 {"bgta-", BBOCB(16,BOT
,CBGT
,1,0), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BDMA
}},
3567 {"bgta+", BBOCB(16,BOT
,CBGT
,1,0), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BDPA
}},
3568 {"bgta", BBOCB(16,BOT
,CBGT
,1,0), BBOATCB_MASK
, COM
, PPCNONE
, {CR
, BDA
}},
3569 {"bgtla-", BBOCB(16,BOT
,CBGT
,1,1), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BDMA
}},
3570 {"bgtla+", BBOCB(16,BOT
,CBGT
,1,1), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BDPA
}},
3571 {"bgtla", BBOCB(16,BOT
,CBGT
,1,1), BBOATCB_MASK
, COM
, PPCNONE
, {CR
, BDA
}},
3572 {"beq-", BBOCB(16,BOT
,CBEQ
,0,0), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BDM
}},
3573 {"beq+", BBOCB(16,BOT
,CBEQ
,0,0), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BDP
}},
3574 {"beq", BBOCB(16,BOT
,CBEQ
,0,0), BBOATCB_MASK
, COM
, PPCNONE
, {CR
, BD
}},
3575 {"beql-", BBOCB(16,BOT
,CBEQ
,0,1), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BDM
}},
3576 {"beql+", BBOCB(16,BOT
,CBEQ
,0,1), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BDP
}},
3577 {"beql", BBOCB(16,BOT
,CBEQ
,0,1), BBOATCB_MASK
, COM
, PPCNONE
, {CR
, BD
}},
3578 {"beqa-", BBOCB(16,BOT
,CBEQ
,1,0), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BDMA
}},
3579 {"beqa+", BBOCB(16,BOT
,CBEQ
,1,0), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BDPA
}},
3580 {"beqa", BBOCB(16,BOT
,CBEQ
,1,0), BBOATCB_MASK
, COM
, PPCNONE
, {CR
, BDA
}},
3581 {"beqla-", BBOCB(16,BOT
,CBEQ
,1,1), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BDMA
}},
3582 {"beqla+", BBOCB(16,BOT
,CBEQ
,1,1), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BDPA
}},
3583 {"beqla", BBOCB(16,BOT
,CBEQ
,1,1), BBOATCB_MASK
, COM
, PPCNONE
, {CR
, BDA
}},
3584 {"bso-", BBOCB(16,BOT
,CBSO
,0,0), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BDM
}},
3585 {"bso+", BBOCB(16,BOT
,CBSO
,0,0), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BDP
}},
3586 {"bso", BBOCB(16,BOT
,CBSO
,0,0), BBOATCB_MASK
, COM
, PPCNONE
, {CR
, BD
}},
3587 {"bun-", BBOCB(16,BOT
,CBSO
,0,0), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BDM
}},
3588 {"bun+", BBOCB(16,BOT
,CBSO
,0,0), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BDP
}},
3589 {"bun", BBOCB(16,BOT
,CBSO
,0,0), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BD
}},
3590 {"bsol-", BBOCB(16,BOT
,CBSO
,0,1), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BDM
}},
3591 {"bsol+", BBOCB(16,BOT
,CBSO
,0,1), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BDP
}},
3592 {"bsol", BBOCB(16,BOT
,CBSO
,0,1), BBOATCB_MASK
, COM
, PPCNONE
, {CR
, BD
}},
3593 {"bunl-", BBOCB(16,BOT
,CBSO
,0,1), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BDM
}},
3594 {"bunl+", BBOCB(16,BOT
,CBSO
,0,1), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BDP
}},
3595 {"bunl", BBOCB(16,BOT
,CBSO
,0,1), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BD
}},
3596 {"bsoa-", BBOCB(16,BOT
,CBSO
,1,0), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BDMA
}},
3597 {"bsoa+", BBOCB(16,BOT
,CBSO
,1,0), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BDPA
}},
3598 {"bsoa", BBOCB(16,BOT
,CBSO
,1,0), BBOATCB_MASK
, COM
, PPCNONE
, {CR
, BDA
}},
3599 {"buna-", BBOCB(16,BOT
,CBSO
,1,0), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BDMA
}},
3600 {"buna+", BBOCB(16,BOT
,CBSO
,1,0), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BDPA
}},
3601 {"buna", BBOCB(16,BOT
,CBSO
,1,0), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BDA
}},
3602 {"bsola-", BBOCB(16,BOT
,CBSO
,1,1), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BDMA
}},
3603 {"bsola+", BBOCB(16,BOT
,CBSO
,1,1), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BDPA
}},
3604 {"bsola", BBOCB(16,BOT
,CBSO
,1,1), BBOATCB_MASK
, COM
, PPCNONE
, {CR
, BDA
}},
3605 {"bunla-", BBOCB(16,BOT
,CBSO
,1,1), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BDMA
}},
3606 {"bunla+", BBOCB(16,BOT
,CBSO
,1,1), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BDPA
}},
3607 {"bunla", BBOCB(16,BOT
,CBSO
,1,1), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BDA
}},
3609 {"bdnzf-", BBO(16,BODNZF
,0,0), BBOY_MASK
, PPCCOM
, ISA_V2
, {BI
, BDM
}},
3610 {"bdnzf+", BBO(16,BODNZF
,0,0), BBOY_MASK
, PPCCOM
, ISA_V2
, {BI
, BDP
}},
3611 {"bdnzf", BBO(16,BODNZF
,0,0), BBOY_MASK
, PPCCOM
, PPCNONE
, {BI
, BD
}},
3612 {"bdnzfl-", BBO(16,BODNZF
,0,1), BBOY_MASK
, PPCCOM
, ISA_V2
, {BI
, BDM
}},
3613 {"bdnzfl+", BBO(16,BODNZF
,0,1), BBOY_MASK
, PPCCOM
, ISA_V2
, {BI
, BDP
}},
3614 {"bdnzfl", BBO(16,BODNZF
,0,1), BBOY_MASK
, PPCCOM
, PPCNONE
, {BI
, BD
}},
3615 {"bdnzfa-", BBO(16,BODNZF
,1,0), BBOY_MASK
, PPCCOM
, ISA_V2
, {BI
, BDMA
}},
3616 {"bdnzfa+", BBO(16,BODNZF
,1,0), BBOY_MASK
, PPCCOM
, ISA_V2
, {BI
, BDPA
}},
3617 {"bdnzfa", BBO(16,BODNZF
,1,0), BBOY_MASK
, PPCCOM
, PPCNONE
, {BI
, BDA
}},
3618 {"bdnzfla-", BBO(16,BODNZF
,1,1), BBOY_MASK
, PPCCOM
, ISA_V2
, {BI
, BDMA
}},
3619 {"bdnzfla+", BBO(16,BODNZF
,1,1), BBOY_MASK
, PPCCOM
, ISA_V2
, {BI
, BDPA
}},
3620 {"bdnzfla", BBO(16,BODNZF
,1,1), BBOY_MASK
, PPCCOM
, PPCNONE
, {BI
, BDA
}},
3621 {"bdzf-", BBO(16,BODZF
,0,0), BBOY_MASK
, PPCCOM
, ISA_V2
, {BI
, BDM
}},
3622 {"bdzf+", BBO(16,BODZF
,0,0), BBOY_MASK
, PPCCOM
, ISA_V2
, {BI
, BDP
}},
3623 {"bdzf", BBO(16,BODZF
,0,0), BBOY_MASK
, PPCCOM
, PPCNONE
, {BI
, BD
}},
3624 {"bdzfl-", BBO(16,BODZF
,0,1), BBOY_MASK
, PPCCOM
, ISA_V2
, {BI
, BDM
}},
3625 {"bdzfl+", BBO(16,BODZF
,0,1), BBOY_MASK
, PPCCOM
, ISA_V2
, {BI
, BDP
}},
3626 {"bdzfl", BBO(16,BODZF
,0,1), BBOY_MASK
, PPCCOM
, PPCNONE
, {BI
, BD
}},
3627 {"bdzfa-", BBO(16,BODZF
,1,0), BBOY_MASK
, PPCCOM
, ISA_V2
, {BI
, BDMA
}},
3628 {"bdzfa+", BBO(16,BODZF
,1,0), BBOY_MASK
, PPCCOM
, ISA_V2
, {BI
, BDPA
}},
3629 {"bdzfa", BBO(16,BODZF
,1,0), BBOY_MASK
, PPCCOM
, PPCNONE
, {BI
, BDA
}},
3630 {"bdzfla-", BBO(16,BODZF
,1,1), BBOY_MASK
, PPCCOM
, ISA_V2
, {BI
, BDMA
}},
3631 {"bdzfla+", BBO(16,BODZF
,1,1), BBOY_MASK
, PPCCOM
, ISA_V2
, {BI
, BDPA
}},
3632 {"bdzfla", BBO(16,BODZF
,1,1), BBOY_MASK
, PPCCOM
, PPCNONE
, {BI
, BDA
}},
3634 {"bf-", BBO(16,BOF
,0,0), BBOAT_MASK
, PPCCOM
, PPCNONE
, {BI
, BDM
}},
3635 {"bf+", BBO(16,BOF
,0,0), BBOAT_MASK
, PPCCOM
, PPCNONE
, {BI
, BDP
}},
3636 {"bf", BBO(16,BOF
,0,0), BBOAT_MASK
, PPCCOM
, PPCNONE
, {BI
, BD
}},
3637 {"bbf", BBO(16,BOF
,0,0), BBOAT_MASK
, PWRCOM
, PPCNONE
, {BI
, BD
}},
3638 {"bfl-", BBO(16,BOF
,0,1), BBOAT_MASK
, PPCCOM
, PPCNONE
, {BI
, BDM
}},
3639 {"bfl+", BBO(16,BOF
,0,1), BBOAT_MASK
, PPCCOM
, PPCNONE
, {BI
, BDP
}},
3640 {"bfl", BBO(16,BOF
,0,1), BBOAT_MASK
, PPCCOM
, PPCNONE
, {BI
, BD
}},
3641 {"bbfl", BBO(16,BOF
,0,1), BBOAT_MASK
, PWRCOM
, PPCNONE
, {BI
, BD
}},
3642 {"bfa-", BBO(16,BOF
,1,0), BBOAT_MASK
, PPCCOM
, PPCNONE
, {BI
, BDMA
}},
3643 {"bfa+", BBO(16,BOF
,1,0), BBOAT_MASK
, PPCCOM
, PPCNONE
, {BI
, BDPA
}},
3644 {"bfa", BBO(16,BOF
,1,0), BBOAT_MASK
, PPCCOM
, PPCNONE
, {BI
, BDA
}},
3645 {"bbfa", BBO(16,BOF
,1,0), BBOAT_MASK
, PWRCOM
, PPCNONE
, {BI
, BDA
}},
3646 {"bfla-", BBO(16,BOF
,1,1), BBOAT_MASK
, PPCCOM
, PPCNONE
, {BI
, BDMA
}},
3647 {"bfla+", BBO(16,BOF
,1,1), BBOAT_MASK
, PPCCOM
, PPCNONE
, {BI
, BDPA
}},
3648 {"bfla", BBO(16,BOF
,1,1), BBOAT_MASK
, PPCCOM
, PPCNONE
, {BI
, BDA
}},
3649 {"bbfla", BBO(16,BOF
,1,1), BBOAT_MASK
, PWRCOM
, PPCNONE
, {BI
, BDA
}},
3651 {"bdnzt-", BBO(16,BODNZT
,0,0), BBOY_MASK
, PPCCOM
, ISA_V2
, {BI
, BDM
}},
3652 {"bdnzt+", BBO(16,BODNZT
,0,0), BBOY_MASK
, PPCCOM
, ISA_V2
, {BI
, BDP
}},
3653 {"bdnzt", BBO(16,BODNZT
,0,0), BBOY_MASK
, PPCCOM
, PPCNONE
, {BI
, BD
}},
3654 {"bdnztl-", BBO(16,BODNZT
,0,1), BBOY_MASK
, PPCCOM
, ISA_V2
, {BI
, BDM
}},
3655 {"bdnztl+", BBO(16,BODNZT
,0,1), BBOY_MASK
, PPCCOM
, ISA_V2
, {BI
, BDP
}},
3656 {"bdnztl", BBO(16,BODNZT
,0,1), BBOY_MASK
, PPCCOM
, PPCNONE
, {BI
, BD
}},
3657 {"bdnzta-", BBO(16,BODNZT
,1,0), BBOY_MASK
, PPCCOM
, ISA_V2
, {BI
, BDMA
}},
3658 {"bdnzta+", BBO(16,BODNZT
,1,0), BBOY_MASK
, PPCCOM
, ISA_V2
, {BI
, BDPA
}},
3659 {"bdnzta", BBO(16,BODNZT
,1,0), BBOY_MASK
, PPCCOM
, PPCNONE
, {BI
, BDA
}},
3660 {"bdnztla-", BBO(16,BODNZT
,1,1), BBOY_MASK
, PPCCOM
, ISA_V2
, {BI
, BDMA
}},
3661 {"bdnztla+", BBO(16,BODNZT
,1,1), BBOY_MASK
, PPCCOM
, ISA_V2
, {BI
, BDPA
}},
3662 {"bdnztla", BBO(16,BODNZT
,1,1), BBOY_MASK
, PPCCOM
, PPCNONE
, {BI
, BDA
}},
3663 {"bdzt-", BBO(16,BODZT
,0,0), BBOY_MASK
, PPCCOM
, ISA_V2
, {BI
, BDM
}},
3664 {"bdzt+", BBO(16,BODZT
,0,0), BBOY_MASK
, PPCCOM
, ISA_V2
, {BI
, BDP
}},
3665 {"bdzt", BBO(16,BODZT
,0,0), BBOY_MASK
, PPCCOM
, PPCNONE
, {BI
, BD
}},
3666 {"bdztl-", BBO(16,BODZT
,0,1), BBOY_MASK
, PPCCOM
, ISA_V2
, {BI
, BDM
}},
3667 {"bdztl+", BBO(16,BODZT
,0,1), BBOY_MASK
, PPCCOM
, ISA_V2
, {BI
, BDP
}},
3668 {"bdztl", BBO(16,BODZT
,0,1), BBOY_MASK
, PPCCOM
, PPCNONE
, {BI
, BD
}},
3669 {"bdzta-", BBO(16,BODZT
,1,0), BBOY_MASK
, PPCCOM
, ISA_V2
, {BI
, BDMA
}},
3670 {"bdzta+", BBO(16,BODZT
,1,0), BBOY_MASK
, PPCCOM
, ISA_V2
, {BI
, BDPA
}},
3671 {"bdzta", BBO(16,BODZT
,1,0), BBOY_MASK
, PPCCOM
, PPCNONE
, {BI
, BDA
}},
3672 {"bdztla-", BBO(16,BODZT
,1,1), BBOY_MASK
, PPCCOM
, ISA_V2
, {BI
, BDMA
}},
3673 {"bdztla+", BBO(16,BODZT
,1,1), BBOY_MASK
, PPCCOM
, ISA_V2
, {BI
, BDPA
}},
3674 {"bdztla", BBO(16,BODZT
,1,1), BBOY_MASK
, PPCCOM
, PPCNONE
, {BI
, BDA
}},
3676 {"bt-", BBO(16,BOT
,0,0), BBOAT_MASK
, PPCCOM
, PPCNONE
, {BI
, BDM
}},
3677 {"bt+", BBO(16,BOT
,0,0), BBOAT_MASK
, PPCCOM
, PPCNONE
, {BI
, BDP
}},
3678 {"bt", BBO(16,BOT
,0,0), BBOAT_MASK
, PPCCOM
, PPCNONE
, {BI
, BD
}},
3679 {"bbt", BBO(16,BOT
,0,0), BBOAT_MASK
, PWRCOM
, PPCNONE
, {BI
, BD
}},
3680 {"btl-", BBO(16,BOT
,0,1), BBOAT_MASK
, PPCCOM
, PPCNONE
, {BI
, BDM
}},
3681 {"btl+", BBO(16,BOT
,0,1), BBOAT_MASK
, PPCCOM
, PPCNONE
, {BI
, BDP
}},
3682 {"btl", BBO(16,BOT
,0,1), BBOAT_MASK
, PPCCOM
, PPCNONE
, {BI
, BD
}},
3683 {"bbtl", BBO(16,BOT
,0,1), BBOAT_MASK
, PWRCOM
, PPCNONE
, {BI
, BD
}},
3684 {"bta-", BBO(16,BOT
,1,0), BBOAT_MASK
, PPCCOM
, PPCNONE
, {BI
, BDMA
}},
3685 {"bta+", BBO(16,BOT
,1,0), BBOAT_MASK
, PPCCOM
, PPCNONE
, {BI
, BDPA
}},
3686 {"bta", BBO(16,BOT
,1,0), BBOAT_MASK
, PPCCOM
, PPCNONE
, {BI
, BDA
}},
3687 {"bbta", BBO(16,BOT
,1,0), BBOAT_MASK
, PWRCOM
, PPCNONE
, {BI
, BDA
}},
3688 {"btla-", BBO(16,BOT
,1,1), BBOAT_MASK
, PPCCOM
, PPCNONE
, {BI
, BDMA
}},
3689 {"btla+", BBO(16,BOT
,1,1), BBOAT_MASK
, PPCCOM
, PPCNONE
, {BI
, BDPA
}},
3690 {"btla", BBO(16,BOT
,1,1), BBOAT_MASK
, PPCCOM
, PPCNONE
, {BI
, BDA
}},
3691 {"bbtla", BBO(16,BOT
,1,1), BBOAT_MASK
, PWRCOM
, PPCNONE
, {BI
, BDA
}},
3693 {"bc-", B(16,0,0), B_MASK
, PPCCOM
, PPCNONE
, {BOE
, BI
, BDM
}},
3694 {"bc+", B(16,0,0), B_MASK
, PPCCOM
, PPCNONE
, {BOE
, BI
, BDP
}},
3695 {"bc", B(16,0,0), B_MASK
, COM
, PPCNONE
, {BO
, BI
, BD
}},
3696 {"bcl-", B(16,0,1), B_MASK
, PPCCOM
, PPCNONE
, {BOE
, BI
, BDM
}},
3697 {"bcl+", B(16,0,1), B_MASK
, PPCCOM
, PPCNONE
, {BOE
, BI
, BDP
}},
3698 {"bcl", B(16,0,1), B_MASK
, COM
, PPCNONE
, {BO
, BI
, BD
}},
3699 {"bca-", B(16,1,0), B_MASK
, PPCCOM
, PPCNONE
, {BOE
, BI
, BDMA
}},
3700 {"bca+", B(16,1,0), B_MASK
, PPCCOM
, PPCNONE
, {BOE
, BI
, BDPA
}},
3701 {"bca", B(16,1,0), B_MASK
, COM
, PPCNONE
, {BO
, BI
, BDA
}},
3702 {"bcla-", B(16,1,1), B_MASK
, PPCCOM
, PPCNONE
, {BOE
, BI
, BDMA
}},
3703 {"bcla+", B(16,1,1), B_MASK
, PPCCOM
, PPCNONE
, {BOE
, BI
, BDPA
}},
3704 {"bcla", B(16,1,1), B_MASK
, COM
, PPCNONE
, {BO
, BI
, BDA
}},
3706 {"svc", SC(17,0,0), SC_MASK
, POWER
, PPCNONE
, {SVC_LEV
, FL1
, FL2
}},
3707 {"svcl", SC(17,0,1), SC_MASK
, POWER
, PPCNONE
, {SVC_LEV
, FL1
, FL2
}},
3708 {"sc", SC(17,1,0), SC_MASK
, PPC
, PPCNONE
, {LEV
}},
3709 {"svca", SC(17,1,0), SC_MASK
, PWRCOM
, PPCNONE
, {SV
}},
3710 {"svcla", SC(17,1,1), SC_MASK
, POWER
, PPCNONE
, {SV
}},
3712 {"b", B(18,0,0), B_MASK
, COM
, PPCNONE
, {LI
}},
3713 {"bl", B(18,0,1), B_MASK
, COM
, PPCNONE
, {LI
}},
3714 {"ba", B(18,1,0), B_MASK
, COM
, PPCNONE
, {LIA
}},
3715 {"bla", B(18,1,1), B_MASK
, COM
, PPCNONE
, {LIA
}},
3717 {"mcrf", XL(19,0), XLBB_MASK
|(3<<21)|(3<<16), COM
, PPCNONE
, {BF
, BFA
}},
3719 {"bdnzlr", XLO(19,BODNZ
,16,0), XLBOBIBB_MASK
, PPCCOM
, PPCNONE
, {0}},
3720 {"bdnzlr-", XLO(19,BODNZ
,16,0), XLBOBIBB_MASK
, PPCCOM
, ISA_V2
, {0}},
3721 {"bdnzlrl", XLO(19,BODNZ
,16,1), XLBOBIBB_MASK
, PPCCOM
, PPCNONE
, {0}},
3722 {"bdnzlrl-", XLO(19,BODNZ
,16,1), XLBOBIBB_MASK
, PPCCOM
, ISA_V2
, {0}},
3723 {"bdnzlr+", XLO(19,BODNZP
,16,0), XLBOBIBB_MASK
, PPCCOM
, ISA_V2
, {0}},
3724 {"bdnzlrl+", XLO(19,BODNZP
,16,1), XLBOBIBB_MASK
, PPCCOM
, ISA_V2
, {0}},
3725 {"bdzlr", XLO(19,BODZ
,16,0), XLBOBIBB_MASK
, PPCCOM
, PPCNONE
, {0}},
3726 {"bdzlr-", XLO(19,BODZ
,16,0), XLBOBIBB_MASK
, PPCCOM
, ISA_V2
, {0}},
3727 {"bdzlrl", XLO(19,BODZ
,16,1), XLBOBIBB_MASK
, PPCCOM
, PPCNONE
, {0}},
3728 {"bdzlrl-", XLO(19,BODZ
,16,1), XLBOBIBB_MASK
, PPCCOM
, ISA_V2
, {0}},
3729 {"bdzlr+", XLO(19,BODZP
,16,0), XLBOBIBB_MASK
, PPCCOM
, ISA_V2
, {0}},
3730 {"bdzlrl+", XLO(19,BODZP
,16,1), XLBOBIBB_MASK
, PPCCOM
, ISA_V2
, {0}},
3731 {"blr", XLO(19,BOU
,16,0), XLBOBIBB_MASK
, PPCCOM
, PPCNONE
, {0}},
3732 {"br", XLO(19,BOU
,16,0), XLBOBIBB_MASK
, PWRCOM
, PPCNONE
, {0}},
3733 {"blrl", XLO(19,BOU
,16,1), XLBOBIBB_MASK
, PPCCOM
, PPCNONE
, {0}},
3734 {"brl", XLO(19,BOU
,16,1), XLBOBIBB_MASK
, PWRCOM
, PPCNONE
, {0}},
3735 {"bdnzlr-", XLO(19,BODNZM4
,16,0), XLBOBIBB_MASK
, ISA_V2
, PPCNONE
, {0}},
3736 {"bdnzlrl-", XLO(19,BODNZM4
,16,1), XLBOBIBB_MASK
, ISA_V2
, PPCNONE
, {0}},
3737 {"bdnzlr+", XLO(19,BODNZP4
,16,0), XLBOBIBB_MASK
, ISA_V2
, PPCNONE
, {0}},
3738 {"bdnzlrl+", XLO(19,BODNZP4
,16,1), XLBOBIBB_MASK
, ISA_V2
, PPCNONE
, {0}},
3739 {"bdzlr-", XLO(19,BODZM4
,16,0), XLBOBIBB_MASK
, ISA_V2
, PPCNONE
, {0}},
3740 {"bdzlrl-", XLO(19,BODZM4
,16,1), XLBOBIBB_MASK
, ISA_V2
, PPCNONE
, {0}},
3741 {"bdzlr+", XLO(19,BODZP4
,16,0), XLBOBIBB_MASK
, ISA_V2
, PPCNONE
, {0}},
3742 {"bdzlrl+", XLO(19,BODZP4
,16,1), XLBOBIBB_MASK
, ISA_V2
, PPCNONE
, {0}},
3744 {"bgelr", XLOCB(19,BOF
,CBLT
,16,0), XLBOCBBB_MASK
, PPCCOM
, PPCNONE
, {CR
}},
3745 {"bgelr-", XLOCB(19,BOF
,CBLT
,16,0), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
, {CR
}},
3746 {"bger", XLOCB(19,BOF
,CBLT
,16,0), XLBOCBBB_MASK
, PWRCOM
, PPCNONE
, {CR
}},
3747 {"bnllr", XLOCB(19,BOF
,CBLT
,16,0), XLBOCBBB_MASK
, PPCCOM
, PPCNONE
, {CR
}},
3748 {"bnllr-", XLOCB(19,BOF
,CBLT
,16,0), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
, {CR
}},
3749 {"bnlr", XLOCB(19,BOF
,CBLT
,16,0), XLBOCBBB_MASK
, PWRCOM
, PPCNONE
, {CR
}},
3750 {"bgelrl", XLOCB(19,BOF
,CBLT
,16,1), XLBOCBBB_MASK
, PPCCOM
, PPCNONE
, {CR
}},
3751 {"bgelrl-", XLOCB(19,BOF
,CBLT
,16,1), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
, {CR
}},
3752 {"bgerl", XLOCB(19,BOF
,CBLT
,16,1), XLBOCBBB_MASK
, PWRCOM
, PPCNONE
, {CR
}},
3753 {"bnllrl", XLOCB(19,BOF
,CBLT
,16,1), XLBOCBBB_MASK
, PPCCOM
, PPCNONE
, {CR
}},
3754 {"bnllrl-", XLOCB(19,BOF
,CBLT
,16,1), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
, {CR
}},
3755 {"bnlrl", XLOCB(19,BOF
,CBLT
,16,1), XLBOCBBB_MASK
, PWRCOM
, PPCNONE
, {CR
}},
3756 {"blelr", XLOCB(19,BOF
,CBGT
,16,0), XLBOCBBB_MASK
, PPCCOM
, PPCNONE
, {CR
}},
3757 {"blelr-", XLOCB(19,BOF
,CBGT
,16,0), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
, {CR
}},
3758 {"bler", XLOCB(19,BOF
,CBGT
,16,0), XLBOCBBB_MASK
, PWRCOM
, PPCNONE
, {CR
}},
3759 {"bnglr", XLOCB(19,BOF
,CBGT
,16,0), XLBOCBBB_MASK
, PPCCOM
, PPCNONE
, {CR
}},
3760 {"bnglr-", XLOCB(19,BOF
,CBGT
,16,0), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
, {CR
}},
3761 {"bngr", XLOCB(19,BOF
,CBGT
,16,0), XLBOCBBB_MASK
, PWRCOM
, PPCNONE
, {CR
}},
3762 {"blelrl", XLOCB(19,BOF
,CBGT
,16,1), XLBOCBBB_MASK
, PPCCOM
, PPCNONE
, {CR
}},
3763 {"blelrl-", XLOCB(19,BOF
,CBGT
,16,1), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
, {CR
}},
3764 {"blerl", XLOCB(19,BOF
,CBGT
,16,1), XLBOCBBB_MASK
, PWRCOM
, PPCNONE
, {CR
}},
3765 {"bnglrl", XLOCB(19,BOF
,CBGT
,16,1), XLBOCBBB_MASK
, PPCCOM
, PPCNONE
, {CR
}},
3766 {"bnglrl-", XLOCB(19,BOF
,CBGT
,16,1), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
, {CR
}},
3767 {"bngrl", XLOCB(19,BOF
,CBGT
,16,1), XLBOCBBB_MASK
, PWRCOM
, PPCNONE
, {CR
}},
3768 {"bnelr", XLOCB(19,BOF
,CBEQ
,16,0), XLBOCBBB_MASK
, PPCCOM
, PPCNONE
, {CR
}},
3769 {"bnelr-", XLOCB(19,BOF
,CBEQ
,16,0), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
, {CR
}},
3770 {"bner", XLOCB(19,BOF
,CBEQ
,16,0), XLBOCBBB_MASK
, PWRCOM
, PPCNONE
, {CR
}},
3771 {"bnelrl", XLOCB(19,BOF
,CBEQ
,16,1), XLBOCBBB_MASK
, PPCCOM
, PPCNONE
, {CR
}},
3772 {"bnelrl-", XLOCB(19,BOF
,CBEQ
,16,1), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
, {CR
}},
3773 {"bnerl", XLOCB(19,BOF
,CBEQ
,16,1), XLBOCBBB_MASK
, PWRCOM
, PPCNONE
, {CR
}},
3774 {"bnslr", XLOCB(19,BOF
,CBSO
,16,0), XLBOCBBB_MASK
, PPCCOM
, PPCNONE
, {CR
}},
3775 {"bnslr-", XLOCB(19,BOF
,CBSO
,16,0), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
, {CR
}},
3776 {"bnsr", XLOCB(19,BOF
,CBSO
,16,0), XLBOCBBB_MASK
, PWRCOM
, PPCNONE
, {CR
}},
3777 {"bnulr", XLOCB(19,BOF
,CBSO
,16,0), XLBOCBBB_MASK
, PPCCOM
, PPCNONE
, {CR
}},
3778 {"bnulr-", XLOCB(19,BOF
,CBSO
,16,0), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
, {CR
}},
3779 {"bnslrl", XLOCB(19,BOF
,CBSO
,16,1), XLBOCBBB_MASK
, PPCCOM
, PPCNONE
, {CR
}},
3780 {"bnslrl-", XLOCB(19,BOF
,CBSO
,16,1), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
, {CR
}},
3781 {"bnsrl", XLOCB(19,BOF
,CBSO
,16,1), XLBOCBBB_MASK
, PWRCOM
, PPCNONE
, {CR
}},
3782 {"bnulrl", XLOCB(19,BOF
,CBSO
,16,1), XLBOCBBB_MASK
, PPCCOM
, PPCNONE
, {CR
}},
3783 {"bnulrl-", XLOCB(19,BOF
,CBSO
,16,1), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
, {CR
}},
3784 {"bgelr+", XLOCB(19,BOFP
,CBLT
,16,0), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
, {CR
}},
3785 {"bnllr+", XLOCB(19,BOFP
,CBLT
,16,0), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
, {CR
}},
3786 {"bgelrl+", XLOCB(19,BOFP
,CBLT
,16,1), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
, {CR
}},
3787 {"bnllrl+", XLOCB(19,BOFP
,CBLT
,16,1), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
, {CR
}},
3788 {"blelr+", XLOCB(19,BOFP
,CBGT
,16,0), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
, {CR
}},
3789 {"bnglr+", XLOCB(19,BOFP
,CBGT
,16,0), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
, {CR
}},
3790 {"blelrl+", XLOCB(19,BOFP
,CBGT
,16,1), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
, {CR
}},
3791 {"bnglrl+", XLOCB(19,BOFP
,CBGT
,16,1), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
, {CR
}},
3792 {"bnelr+", XLOCB(19,BOFP
,CBEQ
,16,0), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
, {CR
}},
3793 {"bnelrl+", XLOCB(19,BOFP
,CBEQ
,16,1), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
, {CR
}},
3794 {"bnslr+", XLOCB(19,BOFP
,CBSO
,16,0), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
, {CR
}},
3795 {"bnulr+", XLOCB(19,BOFP
,CBSO
,16,0), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
, {CR
}},
3796 {"bnslrl+", XLOCB(19,BOFP
,CBSO
,16,1), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
, {CR
}},
3797 {"bnulrl+", XLOCB(19,BOFP
,CBSO
,16,1), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
, {CR
}},
3798 {"bgelr-", XLOCB(19,BOFM4
,CBLT
,16,0), XLBOCBBB_MASK
, ISA_V2
, PPCNONE
, {CR
}},
3799 {"bnllr-", XLOCB(19,BOFM4
,CBLT
,16,0), XLBOCBBB_MASK
, ISA_V2
, PPCNONE
, {CR
}},
3800 {"bgelrl-", XLOCB(19,BOFM4
,CBLT
,16,1), XLBOCBBB_MASK
, ISA_V2
, PPCNONE
, {CR
}},
3801 {"bnllrl-", XLOCB(19,BOFM4
,CBLT
,16,1), XLBOCBBB_MASK
, ISA_V2
, PPCNONE
, {CR
}},
3802 {"blelr-", XLOCB(19,BOFM4
,CBGT
,16,0), XLBOCBBB_MASK
, ISA_V2
, PPCNONE
, {CR
}},
3803 {"bnglr-", XLOCB(19,BOFM4
,CBGT
,16,0), XLBOCBBB_MASK
, ISA_V2
, PPCNONE
, {CR
}},
3804 {"blelrl-", XLOCB(19,BOFM4
,CBGT
,16,1), XLBOCBBB_MASK
, ISA_V2
, PPCNONE
, {CR
}},
3805 {"bnglrl-", XLOCB(19,BOFM4
,CBGT
,16,1), XLBOCBBB_MASK
, ISA_V2
, PPCNONE
, {CR
}},
3806 {"bnelr-", XLOCB(19,BOFM4
,CBEQ
,16,0), XLBOCBBB_MASK
, ISA_V2
, PPCNONE
, {CR
}},
3807 {"bnelrl-", XLOCB(19,BOFM4
,CBEQ
,16,1), XLBOCBBB_MASK
, ISA_V2
, PPCNONE
, {CR
}},
3808 {"bnslr-", XLOCB(19,BOFM4
,CBSO
,16,0), XLBOCBBB_MASK
, ISA_V2
, PPCNONE
, {CR
}},
3809 {"bnulr-", XLOCB(19,BOFM4
,CBSO
,16,0), XLBOCBBB_MASK
, ISA_V2
, PPCNONE
, {CR
}},
3810 {"bnslrl-", XLOCB(19,BOFM4
,CBSO
,16,1), XLBOCBBB_MASK
, ISA_V2
, PPCNONE
, {CR
}},
3811 {"bnulrl-", XLOCB(19,BOFM4
,CBSO
,16,1), XLBOCBBB_MASK
, ISA_V2
, PPCNONE
, {CR
}},
3812 {"bgelr+", XLOCB(19,BOFP4
,CBLT
,16,0), XLBOCBBB_MASK
, ISA_V2
, PPCNONE
, {CR
}},
3813 {"bnllr+", XLOCB(19,BOFP4
,CBLT
,16,0), XLBOCBBB_MASK
, ISA_V2
, PPCNONE
, {CR
}},
3814 {"bgelrl+", XLOCB(19,BOFP4
,CBLT
,16,1), XLBOCBBB_MASK
, ISA_V2
, PPCNONE
, {CR
}},
3815 {"bnllrl+", XLOCB(19,BOFP4
,CBLT
,16,1), XLBOCBBB_MASK
, ISA_V2
, PPCNONE
, {CR
}},
3816 {"blelr+", XLOCB(19,BOFP4
,CBGT
,16,0), XLBOCBBB_MASK
, ISA_V2
, PPCNONE
, {CR
}},
3817 {"bnglr+", XLOCB(19,BOFP4
,CBGT
,16,0), XLBOCBBB_MASK
, ISA_V2
, PPCNONE
, {CR
}},
3818 {"blelrl+", XLOCB(19,BOFP4
,CBGT
,16,1), XLBOCBBB_MASK
, ISA_V2
, PPCNONE
, {CR
}},
3819 {"bnglrl+", XLOCB(19,BOFP4
,CBGT
,16,1), XLBOCBBB_MASK
, ISA_V2
, PPCNONE
, {CR
}},
3820 {"bnelr+", XLOCB(19,BOFP4
,CBEQ
,16,0), XLBOCBBB_MASK
, ISA_V2
, PPCNONE
, {CR
}},
3821 {"bnelrl+", XLOCB(19,BOFP4
,CBEQ
,16,1), XLBOCBBB_MASK
, ISA_V2
, PPCNONE
, {CR
}},
3822 {"bnslr+", XLOCB(19,BOFP4
,CBSO
,16,0), XLBOCBBB_MASK
, ISA_V2
, PPCNONE
, {CR
}},
3823 {"bnulr+", XLOCB(19,BOFP4
,CBSO
,16,0), XLBOCBBB_MASK
, ISA_V2
, PPCNONE
, {CR
}},
3824 {"bnslrl+", XLOCB(19,BOFP4
,CBSO
,16,1), XLBOCBBB_MASK
, ISA_V2
, PPCNONE
, {CR
}},
3825 {"bnulrl+", XLOCB(19,BOFP4
,CBSO
,16,1), XLBOCBBB_MASK
, ISA_V2
, PPCNONE
, {CR
}},
3826 {"bltlr", XLOCB(19,BOT
,CBLT
,16,0), XLBOCBBB_MASK
, PPCCOM
, PPCNONE
, {CR
}},
3827 {"bltlr-", XLOCB(19,BOT
,CBLT
,16,0), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
, {CR
}},
3828 {"bltr", XLOCB(19,BOT
,CBLT
,16,0), XLBOCBBB_MASK
, PWRCOM
, PPCNONE
, {CR
}},
3829 {"bltlrl", XLOCB(19,BOT
,CBLT
,16,1), XLBOCBBB_MASK
, PPCCOM
, PPCNONE
, {CR
}},
3830 {"bltlrl-", XLOCB(19,BOT
,CBLT
,16,1), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
, {CR
}},
3831 {"bltrl", XLOCB(19,BOT
,CBLT
,16,1), XLBOCBBB_MASK
, PWRCOM
, PPCNONE
, {CR
}},
3832 {"bgtlr", XLOCB(19,BOT
,CBGT
,16,0), XLBOCBBB_MASK
, PPCCOM
, PPCNONE
, {CR
}},
3833 {"bgtlr-", XLOCB(19,BOT
,CBGT
,16,0), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
, {CR
}},
3834 {"bgtr", XLOCB(19,BOT
,CBGT
,16,0), XLBOCBBB_MASK
, PWRCOM
, PPCNONE
, {CR
}},
3835 {"bgtlrl", XLOCB(19,BOT
,CBGT
,16,1), XLBOCBBB_MASK
, PPCCOM
, PPCNONE
, {CR
}},
3836 {"bgtlrl-", XLOCB(19,BOT
,CBGT
,16,1), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
, {CR
}},
3837 {"bgtrl", XLOCB(19,BOT
,CBGT
,16,1), XLBOCBBB_MASK
, PWRCOM
, PPCNONE
, {CR
}},
3838 {"beqlr", XLOCB(19,BOT
,CBEQ
,16,0), XLBOCBBB_MASK
, PPCCOM
, PPCNONE
, {CR
}},
3839 {"beqlr-", XLOCB(19,BOT
,CBEQ
,16,0), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
, {CR
}},
3840 {"beqr", XLOCB(19,BOT
,CBEQ
,16,0), XLBOCBBB_MASK
, PWRCOM
, PPCNONE
, {CR
}},
3841 {"beqlrl", XLOCB(19,BOT
,CBEQ
,16,1), XLBOCBBB_MASK
, PPCCOM
, PPCNONE
, {CR
}},
3842 {"beqlrl-", XLOCB(19,BOT
,CBEQ
,16,1), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
, {CR
}},
3843 {"beqrl", XLOCB(19,BOT
,CBEQ
,16,1), XLBOCBBB_MASK
, PWRCOM
, PPCNONE
, {CR
}},
3844 {"bsolr", XLOCB(19,BOT
,CBSO
,16,0), XLBOCBBB_MASK
, PPCCOM
, PPCNONE
, {CR
}},
3845 {"bsolr-", XLOCB(19,BOT
,CBSO
,16,0), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
, {CR
}},
3846 {"bsor", XLOCB(19,BOT
,CBSO
,16,0), XLBOCBBB_MASK
, PWRCOM
, PPCNONE
, {CR
}},
3847 {"bunlr", XLOCB(19,BOT
,CBSO
,16,0), XLBOCBBB_MASK
, PPCCOM
, PPCNONE
, {CR
}},
3848 {"bunlr-", XLOCB(19,BOT
,CBSO
,16,0), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
, {CR
}},
3849 {"bsolrl", XLOCB(19,BOT
,CBSO
,16,1), XLBOCBBB_MASK
, PPCCOM
, PPCNONE
, {CR
}},
3850 {"bsolrl-", XLOCB(19,BOT
,CBSO
,16,1), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
, {CR
}},
3851 {"bsorl", XLOCB(19,BOT
,CBSO
,16,1), XLBOCBBB_MASK
, PWRCOM
, PPCNONE
, {CR
}},
3852 {"bunlrl", XLOCB(19,BOT
,CBSO
,16,1), XLBOCBBB_MASK
, PPCCOM
, PPCNONE
, {CR
}},
3853 {"bunlrl-", XLOCB(19,BOT
,CBSO
,16,1), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
, {CR
}},
3854 {"bltlr+", XLOCB(19,BOTP
,CBLT
,16,0), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
, {CR
}},
3855 {"bltlrl+", XLOCB(19,BOTP
,CBLT
,16,1), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
, {CR
}},
3856 {"bgtlr+", XLOCB(19,BOTP
,CBGT
,16,0), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
, {CR
}},
3857 {"bgtlrl+", XLOCB(19,BOTP
,CBGT
,16,1), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
, {CR
}},
3858 {"beqlr+", XLOCB(19,BOTP
,CBEQ
,16,0), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
, {CR
}},
3859 {"beqlrl+", XLOCB(19,BOTP
,CBEQ
,16,1), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
, {CR
}},
3860 {"bsolr+", XLOCB(19,BOTP
,CBSO
,16,0), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
, {CR
}},
3861 {"bunlr+", XLOCB(19,BOTP
,CBSO
,16,0), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
, {CR
}},
3862 {"bsolrl+", XLOCB(19,BOTP
,CBSO
,16,1), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
, {CR
}},
3863 {"bunlrl+", XLOCB(19,BOTP
,CBSO
,16,1), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
, {CR
}},
3864 {"bltlr-", XLOCB(19,BOTM4
,CBLT
,16,0), XLBOCBBB_MASK
, ISA_V2
, PPCNONE
, {CR
}},
3865 {"bltlrl-", XLOCB(19,BOTM4
,CBLT
,16,1), XLBOCBBB_MASK
, ISA_V2
, PPCNONE
, {CR
}},
3866 {"bgtlr-", XLOCB(19,BOTM4
,CBGT
,16,0), XLBOCBBB_MASK
, ISA_V2
, PPCNONE
, {CR
}},
3867 {"bgtlrl-", XLOCB(19,BOTM4
,CBGT
,16,1), XLBOCBBB_MASK
, ISA_V2
, PPCNONE
, {CR
}},
3868 {"beqlr-", XLOCB(19,BOTM4
,CBEQ
,16,0), XLBOCBBB_MASK
, ISA_V2
, PPCNONE
, {CR
}},
3869 {"beqlrl-", XLOCB(19,BOTM4
,CBEQ
,16,1), XLBOCBBB_MASK
, ISA_V2
, PPCNONE
, {CR
}},
3870 {"bsolr-", XLOCB(19,BOTM4
,CBSO
,16,0), XLBOCBBB_MASK
, ISA_V2
, PPCNONE
, {CR
}},
3871 {"bunlr-", XLOCB(19,BOTM4
,CBSO
,16,0), XLBOCBBB_MASK
, ISA_V2
, PPCNONE
, {CR
}},
3872 {"bsolrl-", XLOCB(19,BOTM4
,CBSO
,16,1), XLBOCBBB_MASK
, ISA_V2
, PPCNONE
, {CR
}},
3873 {"bunlrl-", XLOCB(19,BOTM4
,CBSO
,16,1), XLBOCBBB_MASK
, ISA_V2
, PPCNONE
, {CR
}},
3874 {"bltlr+", XLOCB(19,BOTP4
,CBLT
,16,0), XLBOCBBB_MASK
, ISA_V2
, PPCNONE
, {CR
}},
3875 {"bltlrl+", XLOCB(19,BOTP4
,CBLT
,16,1), XLBOCBBB_MASK
, ISA_V2
, PPCNONE
, {CR
}},
3876 {"bgtlr+", XLOCB(19,BOTP4
,CBGT
,16,0), XLBOCBBB_MASK
, ISA_V2
, PPCNONE
, {CR
}},
3877 {"bgtlrl+", XLOCB(19,BOTP4
,CBGT
,16,1), XLBOCBBB_MASK
, ISA_V2
, PPCNONE
, {CR
}},
3878 {"beqlr+", XLOCB(19,BOTP4
,CBEQ
,16,0), XLBOCBBB_MASK
, ISA_V2
, PPCNONE
, {CR
}},
3879 {"beqlrl+", XLOCB(19,BOTP4
,CBEQ
,16,1), XLBOCBBB_MASK
, ISA_V2
, PPCNONE
, {CR
}},
3880 {"bsolr+", XLOCB(19,BOTP4
,CBSO
,16,0), XLBOCBBB_MASK
, ISA_V2
, PPCNONE
, {CR
}},
3881 {"bunlr+", XLOCB(19,BOTP4
,CBSO
,16,0), XLBOCBBB_MASK
, ISA_V2
, PPCNONE
, {CR
}},
3882 {"bsolrl+", XLOCB(19,BOTP4
,CBSO
,16,1), XLBOCBBB_MASK
, ISA_V2
, PPCNONE
, {CR
}},
3883 {"bunlrl+", XLOCB(19,BOTP4
,CBSO
,16,1), XLBOCBBB_MASK
, ISA_V2
, PPCNONE
, {CR
}},
3885 {"bdnzflr", XLO(19,BODNZF
,16,0), XLBOBB_MASK
, PPCCOM
, PPCNONE
, {BI
}},
3886 {"bdnzflr-", XLO(19,BODNZF
,16,0), XLBOBB_MASK
, PPCCOM
, ISA_V2
, {BI
}},
3887 {"bdnzflrl", XLO(19,BODNZF
,16,1), XLBOBB_MASK
, PPCCOM
, PPCNONE
, {BI
}},
3888 {"bdnzflrl-",XLO(19,BODNZF
,16,1), XLBOBB_MASK
, PPCCOM
, ISA_V2
, {BI
}},
3889 {"bdnzflr+", XLO(19,BODNZFP
,16,0), XLBOBB_MASK
, PPCCOM
, ISA_V2
, {BI
}},
3890 {"bdnzflrl+",XLO(19,BODNZFP
,16,1), XLBOBB_MASK
, PPCCOM
, ISA_V2
, {BI
}},
3891 {"bdzflr", XLO(19,BODZF
,16,0), XLBOBB_MASK
, PPCCOM
, PPCNONE
, {BI
}},
3892 {"bdzflr-", XLO(19,BODZF
,16,0), XLBOBB_MASK
, PPCCOM
, ISA_V2
, {BI
}},
3893 {"bdzflrl", XLO(19,BODZF
,16,1), XLBOBB_MASK
, PPCCOM
, PPCNONE
, {BI
}},
3894 {"bdzflrl-", XLO(19,BODZF
,16,1), XLBOBB_MASK
, PPCCOM
, ISA_V2
, {BI
}},
3895 {"bdzflr+", XLO(19,BODZFP
,16,0), XLBOBB_MASK
, PPCCOM
, ISA_V2
, {BI
}},
3896 {"bdzflrl+", XLO(19,BODZFP
,16,1), XLBOBB_MASK
, PPCCOM
, ISA_V2
, {BI
}},
3897 {"bflr", XLO(19,BOF
,16,0), XLBOBB_MASK
, PPCCOM
, PPCNONE
, {BI
}},
3898 {"bflr-", XLO(19,BOF
,16,0), XLBOBB_MASK
, PPCCOM
, ISA_V2
, {BI
}},
3899 {"bbfr", XLO(19,BOF
,16,0), XLBOBB_MASK
, PWRCOM
, PPCNONE
, {BI
}},
3900 {"bflrl", XLO(19,BOF
,16,1), XLBOBB_MASK
, PPCCOM
, PPCNONE
, {BI
}},
3901 {"bflrl-", XLO(19,BOF
,16,1), XLBOBB_MASK
, PPCCOM
, ISA_V2
, {BI
}},
3902 {"bbfrl", XLO(19,BOF
,16,1), XLBOBB_MASK
, PWRCOM
, PPCNONE
, {BI
}},
3903 {"bflr+", XLO(19,BOFP
,16,0), XLBOBB_MASK
, PPCCOM
, ISA_V2
, {BI
}},
3904 {"bflrl+", XLO(19,BOFP
,16,1), XLBOBB_MASK
, PPCCOM
, ISA_V2
, {BI
}},
3905 {"bflr-", XLO(19,BOFM4
,16,0), XLBOBB_MASK
, ISA_V2
, PPCNONE
, {BI
}},
3906 {"bflrl-", XLO(19,BOFM4
,16,1), XLBOBB_MASK
, ISA_V2
, PPCNONE
, {BI
}},
3907 {"bflr+", XLO(19,BOFP4
,16,0), XLBOBB_MASK
, ISA_V2
, PPCNONE
, {BI
}},
3908 {"bflrl+", XLO(19,BOFP4
,16,1), XLBOBB_MASK
, ISA_V2
, PPCNONE
, {BI
}},
3909 {"bdnztlr", XLO(19,BODNZT
,16,0), XLBOBB_MASK
, PPCCOM
, PPCNONE
, {BI
}},
3910 {"bdnztlr-", XLO(19,BODNZT
,16,0), XLBOBB_MASK
, PPCCOM
, ISA_V2
, {BI
}},
3911 {"bdnztlrl", XLO(19,BODNZT
,16,1), XLBOBB_MASK
, PPCCOM
, PPCNONE
, {BI
}},
3912 {"bdnztlrl-",XLO(19,BODNZT
,16,1), XLBOBB_MASK
, PPCCOM
, ISA_V2
, {BI
}},
3913 {"bdnztlr+", XLO(19,BODNZTP
,16,0), XLBOBB_MASK
, PPCCOM
, ISA_V2
, {BI
}},
3914 {"bdnztlrl+",XLO(19,BODNZTP
,16,1), XLBOBB_MASK
, PPCCOM
, ISA_V2
, {BI
}},
3915 {"bdztlr", XLO(19,BODZT
,16,0), XLBOBB_MASK
, PPCCOM
, PPCNONE
, {BI
}},
3916 {"bdztlr-", XLO(19,BODZT
,16,0), XLBOBB_MASK
, PPCCOM
, ISA_V2
, {BI
}},
3917 {"bdztlrl", XLO(19,BODZT
,16,1), XLBOBB_MASK
, PPCCOM
, PPCNONE
, {BI
}},
3918 {"bdztlrl-", XLO(19,BODZT
,16,1), XLBOBB_MASK
, PPCCOM
, ISA_V2
, {BI
}},
3919 {"bdztlr+", XLO(19,BODZTP
,16,0), XLBOBB_MASK
, PPCCOM
, ISA_V2
, {BI
}},
3920 {"bdztlrl+", XLO(19,BODZTP
,16,1), XLBOBB_MASK
, PPCCOM
, ISA_V2
, {BI
}},
3921 {"btlr", XLO(19,BOT
,16,0), XLBOBB_MASK
, PPCCOM
, PPCNONE
, {BI
}},
3922 {"btlr-", XLO(19,BOT
,16,0), XLBOBB_MASK
, PPCCOM
, ISA_V2
, {BI
}},
3923 {"bbtr", XLO(19,BOT
,16,0), XLBOBB_MASK
, PWRCOM
, PPCNONE
, {BI
}},
3924 {"btlrl", XLO(19,BOT
,16,1), XLBOBB_MASK
, PPCCOM
, PPCNONE
, {BI
}},
3925 {"btlrl-", XLO(19,BOT
,16,1), XLBOBB_MASK
, PPCCOM
, ISA_V2
, {BI
}},
3926 {"bbtrl", XLO(19,BOT
,16,1), XLBOBB_MASK
, PWRCOM
, PPCNONE
, {BI
}},
3927 {"btlr+", XLO(19,BOTP
,16,0), XLBOBB_MASK
, PPCCOM
, ISA_V2
, {BI
}},
3928 {"btlrl+", XLO(19,BOTP
,16,1), XLBOBB_MASK
, PPCCOM
, ISA_V2
, {BI
}},
3929 {"btlr-", XLO(19,BOTM4
,16,0), XLBOBB_MASK
, ISA_V2
, PPCNONE
, {BI
}},
3930 {"btlrl-", XLO(19,BOTM4
,16,1), XLBOBB_MASK
, ISA_V2
, PPCNONE
, {BI
}},
3931 {"btlr+", XLO(19,BOTP4
,16,0), XLBOBB_MASK
, ISA_V2
, PPCNONE
, {BI
}},
3932 {"btlrl+", XLO(19,BOTP4
,16,1), XLBOBB_MASK
, ISA_V2
, PPCNONE
, {BI
}},
3934 {"bclr-", XLYLK(19,16,0,0), XLYBB_MASK
, PPCCOM
, PPCNONE
, {BOE
, BI
}},
3935 {"bclrl-", XLYLK(19,16,0,1), XLYBB_MASK
, PPCCOM
, PPCNONE
, {BOE
, BI
}},
3936 {"bclr+", XLYLK(19,16,1,0), XLYBB_MASK
, PPCCOM
, PPCNONE
, {BOE
, BI
}},
3937 {"bclrl+", XLYLK(19,16,1,1), XLYBB_MASK
, PPCCOM
, PPCNONE
, {BOE
, BI
}},
3938 {"bclr", XLLK(19,16,0), XLBH_MASK
, PPCCOM
, PPCNONE
, {BO
, BI
, BH
}},
3939 {"bcr", XLLK(19,16,0), XLBB_MASK
, PWRCOM
, PPCNONE
, {BO
, BI
}},
3940 {"bclrl", XLLK(19,16,1), XLBH_MASK
, PPCCOM
, PPCNONE
, {BO
, BI
, BH
}},
3941 {"bcrl", XLLK(19,16,1), XLBB_MASK
, PWRCOM
, PPCNONE
, {BO
, BI
}},
3943 {"rfid", XL(19,18), 0xffffffff, PPC64
, PPCNONE
, {0}},
3945 {"crnot", XL(19,33), XL_MASK
, PPCCOM
, PPCNONE
, {BT
, BA
, BBA
}},
3946 {"crnor", XL(19,33), XL_MASK
, COM
, PPCNONE
, {BT
, BA
, BB
}},
3947 {"rfmci", X(19,38), 0xffffffff, PPCRFMCI
|PPCA2
|PPC476
, PPCNONE
, {0}},
3949 {"rfdi", XL(19,39), 0xffffffff, E500MC
, PPCNONE
, {0}},
3950 {"rfi", XL(19,50), 0xffffffff, COM
, PPCNONE
, {0}},
3951 {"rfci", XL(19,51), 0xffffffff, PPC403
|BOOKE
|PPCE300
|PPCA2
|PPC476
, PPCNONE
, {0}},
3953 {"rfsvc", XL(19,82), 0xffffffff, POWER
, PPCNONE
, {0}},
3955 {"rfgi", XL(19,102), 0xffffffff, E500MC
|PPCA2
, PPCNONE
, {0}},
3957 {"crandc", XL(19,129), XL_MASK
, COM
, PPCNONE
, {BT
, BA
, BB
}},
3959 {"isync", XL(19,150), 0xffffffff, PPCCOM
, PPCNONE
, {0}},
3960 {"ics", XL(19,150), 0xffffffff, PWRCOM
, PPCNONE
, {0}},
3962 {"crclr", XL(19,193), XL_MASK
, PPCCOM
, PPCNONE
, {BT
, BAT
, BBA
}},
3963 {"crxor", XL(19,193), XL_MASK
, COM
, PPCNONE
, {BT
, BA
, BB
}},
3965 {"dnh", X(19,198), X_MASK
, E500MC
, PPCNONE
, {DUI
, DUIS
}},
3967 {"crnand", XL(19,225), XL_MASK
, COM
, PPCNONE
, {BT
, BA
, BB
}},
3969 {"crand", XL(19,257), XL_MASK
, COM
, PPCNONE
, {BT
, BA
, BB
}},
3971 {"hrfid", XL(19,274), 0xffffffff, POWER5
|CELL
, PPC476
, {0}},
3973 {"crset", XL(19,289), XL_MASK
, PPCCOM
, PPCNONE
, {BT
, BAT
, BBA
}},
3974 {"creqv", XL(19,289), XL_MASK
, COM
, PPCNONE
, {BT
, BA
, BB
}},
3976 {"doze", XL(19,402), 0xffffffff, POWER6
, PPCNONE
, {0}},
3978 {"crorc", XL(19,417), XL_MASK
, COM
, PPCNONE
, {BT
, BA
, BB
}},
3980 {"nap", XL(19,434), 0xffffffff, POWER6
, PPCNONE
, {0}},
3982 {"crmove", XL(19,449), XL_MASK
, PPCCOM
, PPCNONE
, {BT
, BA
, BBA
}},
3983 {"cror", XL(19,449), XL_MASK
, COM
, PPCNONE
, {BT
, BA
, BB
}},
3985 {"sleep", XL(19,466), 0xffffffff, POWER6
, PPCNONE
, {0}},
3986 {"rvwinkle", XL(19,498), 0xffffffff, POWER6
, PPCNONE
, {0}},
3988 {"bctr", XLO(19,BOU
,528,0), XLBOBIBB_MASK
, COM
, PPCNONE
, {0}},
3989 {"bctrl", XLO(19,BOU
,528,1), XLBOBIBB_MASK
, COM
, PPCNONE
, {0}},
3991 {"bgectr", XLOCB(19,BOF
,CBLT
,528,0), XLBOCBBB_MASK
, PPCCOM
, PPCNONE
, {CR
}},
3992 {"bgectr-", XLOCB(19,BOF
,CBLT
,528,0), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
, {CR
}},
3993 {"bnlctr", XLOCB(19,BOF
,CBLT
,528,0), XLBOCBBB_MASK
, PPCCOM
, PPCNONE
, {CR
}},
3994 {"bnlctr-", XLOCB(19,BOF
,CBLT
,528,0), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
, {CR
}},
3995 {"bgectrl", XLOCB(19,BOF
,CBLT
,528,1), XLBOCBBB_MASK
, PPCCOM
, PPCNONE
, {CR
}},
3996 {"bgectrl-",XLOCB(19,BOF
,CBLT
,528,1), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
, {CR
}},
3997 {"bnlctrl", XLOCB(19,BOF
,CBLT
,528,1), XLBOCBBB_MASK
, PPCCOM
, PPCNONE
, {CR
}},
3998 {"bnlctrl-",XLOCB(19,BOF
,CBLT
,528,1), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
, {CR
}},
3999 {"blectr", XLOCB(19,BOF
,CBGT
,528,0), XLBOCBBB_MASK
, PPCCOM
, PPCNONE
, {CR
}},
4000 {"blectr-", XLOCB(19,BOF
,CBGT
,528,0), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
, {CR
}},
4001 {"bngctr", XLOCB(19,BOF
,CBGT
,528,0), XLBOCBBB_MASK
, PPCCOM
, PPCNONE
, {CR
}},
4002 {"bngctr-", XLOCB(19,BOF
,CBGT
,528,0), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
, {CR
}},
4003 {"blectrl", XLOCB(19,BOF
,CBGT
,528,1), XLBOCBBB_MASK
, PPCCOM
, PPCNONE
, {CR
}},
4004 {"blectrl-",XLOCB(19,BOF
,CBGT
,528,1), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
, {CR
}},
4005 {"bngctrl", XLOCB(19,BOF
,CBGT
,528,1), XLBOCBBB_MASK
, PPCCOM
, PPCNONE
, {CR
}},
4006 {"bngctrl-",XLOCB(19,BOF
,CBGT
,528,1), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
, {CR
}},
4007 {"bnectr", XLOCB(19,BOF
,CBEQ
,528,0), XLBOCBBB_MASK
, PPCCOM
, PPCNONE
, {CR
}},
4008 {"bnectr-", XLOCB(19,BOF
,CBEQ
,528,0), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
, {CR
}},
4009 {"bnectrl", XLOCB(19,BOF
,CBEQ
,528,1), XLBOCBBB_MASK
, PPCCOM
, PPCNONE
, {CR
}},
4010 {"bnectrl-",XLOCB(19,BOF
,CBEQ
,528,1), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
, {CR
}},
4011 {"bnsctr", XLOCB(19,BOF
,CBSO
,528,0), XLBOCBBB_MASK
, PPCCOM
, PPCNONE
, {CR
}},
4012 {"bnsctr-", XLOCB(19,BOF
,CBSO
,528,0), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
, {CR
}},
4013 {"bnuctr", XLOCB(19,BOF
,CBSO
,528,0), XLBOCBBB_MASK
, PPCCOM
, PPCNONE
, {CR
}},
4014 {"bnuctr-", XLOCB(19,BOF
,CBSO
,528,0), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
, {CR
}},
4015 {"bnsctrl", XLOCB(19,BOF
,CBSO
,528,1), XLBOCBBB_MASK
, PPCCOM
, PPCNONE
, {CR
}},
4016 {"bnsctrl-",XLOCB(19,BOF
,CBSO
,528,1), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
, {CR
}},
4017 {"bnuctrl", XLOCB(19,BOF
,CBSO
,528,1), XLBOCBBB_MASK
, PPCCOM
, PPCNONE
, {CR
}},
4018 {"bnuctrl-",XLOCB(19,BOF
,CBSO
,528,1), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
, {CR
}},
4019 {"bgectr+", XLOCB(19,BOFP
,CBLT
,528,0), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
, {CR
}},
4020 {"bnlctr+", XLOCB(19,BOFP
,CBLT
,528,0), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
, {CR
}},
4021 {"bgectrl+",XLOCB(19,BOFP
,CBLT
,528,1), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
, {CR
}},
4022 {"bnlctrl+",XLOCB(19,BOFP
,CBLT
,528,1), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
, {CR
}},
4023 {"blectr+", XLOCB(19,BOFP
,CBGT
,528,0), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
, {CR
}},
4024 {"bngctr+", XLOCB(19,BOFP
,CBGT
,528,0), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
, {CR
}},
4025 {"blectrl+",XLOCB(19,BOFP
,CBGT
,528,1), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
, {CR
}},
4026 {"bngctrl+",XLOCB(19,BOFP
,CBGT
,528,1), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
, {CR
}},
4027 {"bnectr+", XLOCB(19,BOFP
,CBEQ
,528,0), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
, {CR
}},
4028 {"bnectrl+",XLOCB(19,BOFP
,CBEQ
,528,1), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
, {CR
}},
4029 {"bnsctr+", XLOCB(19,BOFP
,CBSO
,528,0), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
, {CR
}},
4030 {"bnuctr+", XLOCB(19,BOFP
,CBSO
,528,0), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
, {CR
}},
4031 {"bnsctrl+",XLOCB(19,BOFP
,CBSO
,528,1), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
, {CR
}},
4032 {"bnuctrl+",XLOCB(19,BOFP
,CBSO
,528,1), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
, {CR
}},
4033 {"bgectr-", XLOCB(19,BOFM4
,CBLT
,528,0), XLBOCBBB_MASK
, ISA_V2
, PPCNONE
, {CR
}},
4034 {"bnlctr-", XLOCB(19,BOFM4
,CBLT
,528,0), XLBOCBBB_MASK
, ISA_V2
, PPCNONE
, {CR
}},
4035 {"bgectrl-",XLOCB(19,BOFM4
,CBLT
,528,1), XLBOCBBB_MASK
, ISA_V2
, PPCNONE
, {CR
}},
4036 {"bnlctrl-",XLOCB(19,BOFM4
,CBLT
,528,1), XLBOCBBB_MASK
, ISA_V2
, PPCNONE
, {CR
}},
4037 {"blectr-", XLOCB(19,BOFM4
,CBGT
,528,0), XLBOCBBB_MASK
, ISA_V2
, PPCNONE
, {CR
}},
4038 {"bngctr-", XLOCB(19,BOFM4
,CBGT
,528,0), XLBOCBBB_MASK
, ISA_V2
, PPCNONE
, {CR
}},
4039 {"blectrl-",XLOCB(19,BOFM4
,CBGT
,528,1), XLBOCBBB_MASK
, ISA_V2
, PPCNONE
, {CR
}},
4040 {"bngctrl-",XLOCB(19,BOFM4
,CBGT
,528,1), XLBOCBBB_MASK
, ISA_V2
, PPCNONE
, {CR
}},
4041 {"bnectr-", XLOCB(19,BOFM4
,CBEQ
,528,0), XLBOCBBB_MASK
, ISA_V2
, PPCNONE
, {CR
}},
4042 {"bnectrl-",XLOCB(19,BOFM4
,CBEQ
,528,1), XLBOCBBB_MASK
, ISA_V2
, PPCNONE
, {CR
}},
4043 {"bnsctr-", XLOCB(19,BOFM4
,CBSO
,528,0), XLBOCBBB_MASK
, ISA_V2
, PPCNONE
, {CR
}},
4044 {"bnuctr-", XLOCB(19,BOFM4
,CBSO
,528,0), XLBOCBBB_MASK
, ISA_V2
, PPCNONE
, {CR
}},
4045 {"bnsctrl-",XLOCB(19,BOFM4
,CBSO
,528,1), XLBOCBBB_MASK
, ISA_V2
, PPCNONE
, {CR
}},
4046 {"bnuctrl-",XLOCB(19,BOFM4
,CBSO
,528,1), XLBOCBBB_MASK
, ISA_V2
, PPCNONE
, {CR
}},
4047 {"bgectr+", XLOCB(19,BOFP4
,CBLT
,528,0), XLBOCBBB_MASK
, ISA_V2
, PPCNONE
, {CR
}},
4048 {"bnlctr+", XLOCB(19,BOFP4
,CBLT
,528,0), XLBOCBBB_MASK
, ISA_V2
, PPCNONE
, {CR
}},
4049 {"bgectrl+",XLOCB(19,BOFP4
,CBLT
,528,1), XLBOCBBB_MASK
, ISA_V2
, PPCNONE
, {CR
}},
4050 {"bnlctrl+",XLOCB(19,BOFP4
,CBLT
,528,1), XLBOCBBB_MASK
, ISA_V2
, PPCNONE
, {CR
}},
4051 {"blectr+", XLOCB(19,BOFP4
,CBGT
,528,0), XLBOCBBB_MASK
, ISA_V2
, PPCNONE
, {CR
}},
4052 {"bngctr+", XLOCB(19,BOFP4
,CBGT
,528,0), XLBOCBBB_MASK
, ISA_V2
, PPCNONE
, {CR
}},
4053 {"blectrl+",XLOCB(19,BOFP4
,CBGT
,528,1), XLBOCBBB_MASK
, ISA_V2
, PPCNONE
, {CR
}},
4054 {"bngctrl+",XLOCB(19,BOFP4
,CBGT
,528,1), XLBOCBBB_MASK
, ISA_V2
, PPCNONE
, {CR
}},
4055 {"bnectr+", XLOCB(19,BOFP4
,CBEQ
,528,0), XLBOCBBB_MASK
, ISA_V2
, PPCNONE
, {CR
}},
4056 {"bnectrl+",XLOCB(19,BOFP4
,CBEQ
,528,1), XLBOCBBB_MASK
, ISA_V2
, PPCNONE
, {CR
}},
4057 {"bnsctr+", XLOCB(19,BOFP4
,CBSO
,528,0), XLBOCBBB_MASK
, ISA_V2
, PPCNONE
, {CR
}},
4058 {"bnuctr+", XLOCB(19,BOFP4
,CBSO
,528,0), XLBOCBBB_MASK
, ISA_V2
, PPCNONE
, {CR
}},
4059 {"bnsctrl+",XLOCB(19,BOFP4
,CBSO
,528,1), XLBOCBBB_MASK
, ISA_V2
, PPCNONE
, {CR
}},
4060 {"bnuctrl+",XLOCB(19,BOFP4
,CBSO
,528,1), XLBOCBBB_MASK
, ISA_V2
, PPCNONE
, {CR
}},
4061 {"bltctr", XLOCB(19,BOT
,CBLT
,528,0), XLBOCBBB_MASK
, PPCCOM
, PPCNONE
, {CR
}},
4062 {"bltctr-", XLOCB(19,BOT
,CBLT
,528,0), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
, {CR
}},
4063 {"bltctrl", XLOCB(19,BOT
,CBLT
,528,1), XLBOCBBB_MASK
, PPCCOM
, PPCNONE
, {CR
}},
4064 {"bltctrl-",XLOCB(19,BOT
,CBLT
,528,1), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
, {CR
}},
4065 {"bgtctr", XLOCB(19,BOT
,CBGT
,528,0), XLBOCBBB_MASK
, PPCCOM
, PPCNONE
, {CR
}},
4066 {"bgtctr-", XLOCB(19,BOT
,CBGT
,528,0), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
, {CR
}},
4067 {"bgtctrl", XLOCB(19,BOT
,CBGT
,528,1), XLBOCBBB_MASK
, PPCCOM
, PPCNONE
, {CR
}},
4068 {"bgtctrl-",XLOCB(19,BOT
,CBGT
,528,1), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
, {CR
}},
4069 {"beqctr", XLOCB(19,BOT
,CBEQ
,528,0), XLBOCBBB_MASK
, PPCCOM
, PPCNONE
, {CR
}},
4070 {"beqctr-", XLOCB(19,BOT
,CBEQ
,528,0), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
, {CR
}},
4071 {"beqctrl", XLOCB(19,BOT
,CBEQ
,528,1), XLBOCBBB_MASK
, PPCCOM
, PPCNONE
, {CR
}},
4072 {"beqctrl-",XLOCB(19,BOT
,CBEQ
,528,1), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
, {CR
}},
4073 {"bsoctr", XLOCB(19,BOT
,CBSO
,528,0), XLBOCBBB_MASK
, PPCCOM
, PPCNONE
, {CR
}},
4074 {"bsoctr-", XLOCB(19,BOT
,CBSO
,528,0), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
, {CR
}},
4075 {"bunctr", XLOCB(19,BOT
,CBSO
,528,0), XLBOCBBB_MASK
, PPCCOM
, PPCNONE
, {CR
}},
4076 {"bunctr-", XLOCB(19,BOT
,CBSO
,528,0), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
, {CR
}},
4077 {"bsoctrl", XLOCB(19,BOT
,CBSO
,528,1), XLBOCBBB_MASK
, PPCCOM
, PPCNONE
, {CR
}},
4078 {"bsoctrl-",XLOCB(19,BOT
,CBSO
,528,1), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
, {CR
}},
4079 {"bunctrl", XLOCB(19,BOT
,CBSO
,528,1), XLBOCBBB_MASK
, PPCCOM
, PPCNONE
, {CR
}},
4080 {"bunctrl-",XLOCB(19,BOT
,CBSO
,528,1), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
, {CR
}},
4081 {"bltctr+", XLOCB(19,BOTP
,CBLT
,528,0), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
, {CR
}},
4082 {"bltctrl+",XLOCB(19,BOTP
,CBLT
,528,1), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
, {CR
}},
4083 {"bgtctr+", XLOCB(19,BOTP
,CBGT
,528,0), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
, {CR
}},
4084 {"bgtctrl+",XLOCB(19,BOTP
,CBGT
,528,1), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
, {CR
}},
4085 {"beqctr+", XLOCB(19,BOTP
,CBEQ
,528,0), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
, {CR
}},
4086 {"beqctrl+",XLOCB(19,BOTP
,CBEQ
,528,1), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
, {CR
}},
4087 {"bsoctr+", XLOCB(19,BOTP
,CBSO
,528,0), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
, {CR
}},
4088 {"bunctr+", XLOCB(19,BOTP
,CBSO
,528,0), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
, {CR
}},
4089 {"bsoctrl+",XLOCB(19,BOTP
,CBSO
,528,1), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
, {CR
}},
4090 {"bunctrl+",XLOCB(19,BOTP
,CBSO
,528,1), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
, {CR
}},
4091 {"bltctr-", XLOCB(19,BOTM4
,CBLT
,528,0), XLBOCBBB_MASK
, ISA_V2
, PPCNONE
, {CR
}},
4092 {"bltctrl-",XLOCB(19,BOTM4
,CBLT
,528,1), XLBOCBBB_MASK
, ISA_V2
, PPCNONE
, {CR
}},
4093 {"bgtctr-", XLOCB(19,BOTM4
,CBGT
,528,0), XLBOCBBB_MASK
, ISA_V2
, PPCNONE
, {CR
}},
4094 {"bgtctrl-",XLOCB(19,BOTM4
,CBGT
,528,1), XLBOCBBB_MASK
, ISA_V2
, PPCNONE
, {CR
}},
4095 {"beqctr-", XLOCB(19,BOTM4
,CBEQ
,528,0), XLBOCBBB_MASK
, ISA_V2
, PPCNONE
, {CR
}},
4096 {"beqctrl-",XLOCB(19,BOTM4
,CBEQ
,528,1), XLBOCBBB_MASK
, ISA_V2
, PPCNONE
, {CR
}},
4097 {"bsoctr-", XLOCB(19,BOTM4
,CBSO
,528,0), XLBOCBBB_MASK
, ISA_V2
, PPCNONE
, {CR
}},
4098 {"bunctr-", XLOCB(19,BOTM4
,CBSO
,528,0), XLBOCBBB_MASK
, ISA_V2
, PPCNONE
, {CR
}},
4099 {"bsoctrl-",XLOCB(19,BOTM4
,CBSO
,528,1), XLBOCBBB_MASK
, ISA_V2
, PPCNONE
, {CR
}},
4100 {"bunctrl-",XLOCB(19,BOTM4
,CBSO
,528,1), XLBOCBBB_MASK
, ISA_V2
, PPCNONE
, {CR
}},
4101 {"bltctr+", XLOCB(19,BOTP4
,CBLT
,528,0), XLBOCBBB_MASK
, ISA_V2
, PPCNONE
, {CR
}},
4102 {"bltctrl+",XLOCB(19,BOTP4
,CBLT
,528,1), XLBOCBBB_MASK
, ISA_V2
, PPCNONE
, {CR
}},
4103 {"bgtctr+", XLOCB(19,BOTP4
,CBGT
,528,0), XLBOCBBB_MASK
, ISA_V2
, PPCNONE
, {CR
}},
4104 {"bgtctrl+",XLOCB(19,BOTP4
,CBGT
,528,1), XLBOCBBB_MASK
, ISA_V2
, PPCNONE
, {CR
}},
4105 {"beqctr+", XLOCB(19,BOTP4
,CBEQ
,528,0), XLBOCBBB_MASK
, ISA_V2
, PPCNONE
, {CR
}},
4106 {"beqctrl+",XLOCB(19,BOTP4
,CBEQ
,528,1), XLBOCBBB_MASK
, ISA_V2
, PPCNONE
, {CR
}},
4107 {"bsoctr+", XLOCB(19,BOTP4
,CBSO
,528,0), XLBOCBBB_MASK
, ISA_V2
, PPCNONE
, {CR
}},
4108 {"bunctr+", XLOCB(19,BOTP4
,CBSO
,528,0), XLBOCBBB_MASK
, ISA_V2
, PPCNONE
, {CR
}},
4109 {"bsoctrl+",XLOCB(19,BOTP4
,CBSO
,528,1), XLBOCBBB_MASK
, ISA_V2
, PPCNONE
, {CR
}},
4110 {"bunctrl+",XLOCB(19,BOTP4
,CBSO
,528,1), XLBOCBBB_MASK
, ISA_V2
, PPCNONE
, {CR
}},
4112 {"bfctr", XLO(19,BOF
,528,0), XLBOBB_MASK
, PPCCOM
, PPCNONE
, {BI
}},
4113 {"bfctr-", XLO(19,BOF
,528,0), XLBOBB_MASK
, PPCCOM
, ISA_V2
, {BI
}},
4114 {"bfctrl", XLO(19,BOF
,528,1), XLBOBB_MASK
, PPCCOM
, PPCNONE
, {BI
}},
4115 {"bfctrl-", XLO(19,BOF
,528,1), XLBOBB_MASK
, PPCCOM
, ISA_V2
, {BI
}},
4116 {"bfctr+", XLO(19,BOFP
,528,0), XLBOBB_MASK
, PPCCOM
, ISA_V2
, {BI
}},
4117 {"bfctrl+", XLO(19,BOFP
,528,1), XLBOBB_MASK
, PPCCOM
, ISA_V2
, {BI
}},
4118 {"bfctr-", XLO(19,BOFM4
,528,0), XLBOBB_MASK
, ISA_V2
, PPCNONE
, {BI
}},
4119 {"bfctrl-", XLO(19,BOFM4
,528,1), XLBOBB_MASK
, ISA_V2
, PPCNONE
, {BI
}},
4120 {"bfctr+", XLO(19,BOFP4
,528,0), XLBOBB_MASK
, ISA_V2
, PPCNONE
, {BI
}},
4121 {"bfctrl+", XLO(19,BOFP4
,528,1), XLBOBB_MASK
, ISA_V2
, PPCNONE
, {BI
}},
4122 {"btctr", XLO(19,BOT
,528,0), XLBOBB_MASK
, PPCCOM
, PPCNONE
, {BI
}},
4123 {"btctr-", XLO(19,BOT
,528,0), XLBOBB_MASK
, PPCCOM
, ISA_V2
, {BI
}},
4124 {"btctrl", XLO(19,BOT
,528,1), XLBOBB_MASK
, PPCCOM
, PPCNONE
, {BI
}},
4125 {"btctrl-", XLO(19,BOT
,528,1), XLBOBB_MASK
, PPCCOM
, ISA_V2
, {BI
}},
4126 {"btctr+", XLO(19,BOTP
,528,0), XLBOBB_MASK
, PPCCOM
, ISA_V2
, {BI
}},
4127 {"btctrl+", XLO(19,BOTP
,528,1), XLBOBB_MASK
, PPCCOM
, ISA_V2
, {BI
}},
4128 {"btctr-", XLO(19,BOTM4
,528,0), XLBOBB_MASK
, ISA_V2
, PPCNONE
, {BI
}},
4129 {"btctrl-", XLO(19,BOTM4
,528,1), XLBOBB_MASK
, ISA_V2
, PPCNONE
, {BI
}},
4130 {"btctr+", XLO(19,BOTP4
,528,0), XLBOBB_MASK
, ISA_V2
, PPCNONE
, {BI
}},
4131 {"btctrl+", XLO(19,BOTP4
,528,1), XLBOBB_MASK
, ISA_V2
, PPCNONE
, {BI
}},
4133 {"bcctr-", XLYLK(19,528,0,0), XLYBB_MASK
, PPCCOM
, PPCNONE
, {BOE
, BI
}},
4134 {"bcctrl-", XLYLK(19,528,0,1), XLYBB_MASK
, PPCCOM
, PPCNONE
, {BOE
, BI
}},
4135 {"bcctr+", XLYLK(19,528,1,0), XLYBB_MASK
, PPCCOM
, PPCNONE
, {BOE
, BI
}},
4136 {"bcctrl+", XLYLK(19,528,1,1), XLYBB_MASK
, PPCCOM
, PPCNONE
, {BOE
, BI
}},
4137 {"bcctr", XLLK(19,528,0), XLBH_MASK
, PPCCOM
, PPCNONE
, {BO
, BI
, BH
}},
4138 {"bcc", XLLK(19,528,0), XLBB_MASK
, PWRCOM
, PPCNONE
, {BO
, BI
}},
4139 {"bcctrl", XLLK(19,528,1), XLBH_MASK
, PPCCOM
, PPCNONE
, {BO
, BI
, BH
}},
4140 {"bccl", XLLK(19,528,1), XLBB_MASK
, PWRCOM
, PPCNONE
, {BO
, BI
}},
4142 {"rlwimi", M(20,0), M_MASK
, PPCCOM
, PPCNONE
, {RA
, RS
, SH
, MBE
, ME
}},
4143 {"rlimi", M(20,0), M_MASK
, PWRCOM
, PPCNONE
, {RA
, RS
, SH
, MBE
, ME
}},
4145 {"rlwimi.", M(20,1), M_MASK
, PPCCOM
, PPCNONE
, {RA
, RS
, SH
, MBE
, ME
}},
4146 {"rlimi.", M(20,1), M_MASK
, PWRCOM
, PPCNONE
, {RA
, RS
, SH
, MBE
, ME
}},
4148 {"rotlwi", MME(21,31,0), MMBME_MASK
, PPCCOM
, PPCNONE
, {RA
, RS
, SH
}},
4149 {"clrlwi", MME(21,31,0), MSHME_MASK
, PPCCOM
, PPCNONE
, {RA
, RS
, MB
}},
4150 {"rlwinm", M(21,0), M_MASK
, PPCCOM
, PPCNONE
, {RA
, RS
, SH
, MBE
, ME
}},
4151 {"rlinm", M(21,0), M_MASK
, PWRCOM
, PPCNONE
, {RA
, RS
, SH
, MBE
, ME
}},
4152 {"rotlwi.", MME(21,31,1), MMBME_MASK
, PPCCOM
, PPCNONE
, {RA
, RS
, SH
}},
4153 {"clrlwi.", MME(21,31,1), MSHME_MASK
, PPCCOM
, PPCNONE
, {RA
, RS
, MB
}},
4154 {"rlwinm.", M(21,1), M_MASK
, PPCCOM
, PPCNONE
, {RA
, RS
, SH
, MBE
, ME
}},
4155 {"rlinm.", M(21,1), M_MASK
, PWRCOM
, PPCNONE
, {RA
, RS
, SH
, MBE
, ME
}},
4157 {"rlmi", M(22,0), M_MASK
, M601
, PPCNONE
, {RA
, RS
, RB
, MBE
, ME
}},
4158 {"rlmi.", M(22,1), M_MASK
, M601
, PPCNONE
, {RA
, RS
, RB
, MBE
, ME
}},
4160 {"rotlw", MME(23,31,0), MMBME_MASK
, PPCCOM
, PPCNONE
, {RA
, RS
, RB
}},
4161 {"rlwnm", M(23,0), M_MASK
, PPCCOM
, PPCNONE
, {RA
, RS
, RB
, MBE
, ME
}},
4162 {"rlnm", M(23,0), M_MASK
, PWRCOM
, PPCNONE
, {RA
, RS
, RB
, MBE
, ME
}},
4163 {"rotlw.", MME(23,31,1), MMBME_MASK
, PPCCOM
, PPCNONE
, {RA
, RS
, RB
}},
4164 {"rlwnm.", M(23,1), M_MASK
, PPCCOM
, PPCNONE
, {RA
, RS
, RB
, MBE
, ME
}},
4165 {"rlnm.", M(23,1), M_MASK
, PWRCOM
, PPCNONE
, {RA
, RS
, RB
, MBE
, ME
}},
4167 {"nop", OP(24), 0xffffffff, PPCCOM
, PPCNONE
, {0}},
4168 {"ori", OP(24), OP_MASK
, PPCCOM
, PPCNONE
, {RA
, RS
, UI
}},
4169 {"oril", OP(24), OP_MASK
, PWRCOM
, PPCNONE
, {RA
, RS
, UI
}},
4171 {"oris", OP(25), OP_MASK
, PPCCOM
, PPCNONE
, {RA
, RS
, UI
}},
4172 {"oriu", OP(25), OP_MASK
, PWRCOM
, PPCNONE
, {RA
, RS
, UI
}},
4174 {"xnop", OP(26), 0xffffffff, PPCCOM
, PPCNONE
, {0}},
4175 {"xori", OP(26), OP_MASK
, PPCCOM
, PPCNONE
, {RA
, RS
, UI
}},
4176 {"xoril", OP(26), OP_MASK
, PWRCOM
, PPCNONE
, {RA
, RS
, UI
}},
4178 {"xoris", OP(27), OP_MASK
, PPCCOM
, PPCNONE
, {RA
, RS
, UI
}},
4179 {"xoriu", OP(27), OP_MASK
, PWRCOM
, PPCNONE
, {RA
, RS
, UI
}},
4181 {"andi.", OP(28), OP_MASK
, PPCCOM
, PPCNONE
, {RA
, RS
, UI
}},
4182 {"andil.", OP(28), OP_MASK
, PWRCOM
, PPCNONE
, {RA
, RS
, UI
}},
4184 {"andis.", OP(29), OP_MASK
, PPCCOM
, PPCNONE
, {RA
, RS
, UI
}},
4185 {"andiu.", OP(29), OP_MASK
, PWRCOM
, PPCNONE
, {RA
, RS
, UI
}},
4187 {"rotldi", MD(30,0,0), MDMB_MASK
, PPC64
, PPCNONE
, {RA
, RS
, SH6
}},
4188 {"clrldi", MD(30,0,0), MDSH_MASK
, PPC64
, PPCNONE
, {RA
, RS
, MB6
}},
4189 {"rldicl", MD(30,0,0), MD_MASK
, PPC64
, PPCNONE
, {RA
, RS
, SH6
, MB6
}},
4190 {"rotldi.", MD(30,0,1), MDMB_MASK
, PPC64
, PPCNONE
, {RA
, RS
, SH6
}},
4191 {"clrldi.", MD(30,0,1), MDSH_MASK
, PPC64
, PPCNONE
, {RA
, RS
, MB6
}},
4192 {"rldicl.", MD(30,0,1), MD_MASK
, PPC64
, PPCNONE
, {RA
, RS
, SH6
, MB6
}},
4194 {"rldicr", MD(30,1,0), MD_MASK
, PPC64
, PPCNONE
, {RA
, RS
, SH6
, ME6
}},
4195 {"rldicr.", MD(30,1,1), MD_MASK
, PPC64
, PPCNONE
, {RA
, RS
, SH6
, ME6
}},
4197 {"rldic", MD(30,2,0), MD_MASK
, PPC64
, PPCNONE
, {RA
, RS
, SH6
, MB6
}},
4198 {"rldic.", MD(30,2,1), MD_MASK
, PPC64
, PPCNONE
, {RA
, RS
, SH6
, MB6
}},
4200 {"rldimi", MD(30,3,0), MD_MASK
, PPC64
, PPCNONE
, {RA
, RS
, SH6
, MB6
}},
4201 {"rldimi.", MD(30,3,1), MD_MASK
, PPC64
, PPCNONE
, {RA
, RS
, SH6
, MB6
}},
4203 {"rotld", MDS(30,8,0), MDSMB_MASK
, PPC64
, PPCNONE
, {RA
, RS
, RB
}},
4204 {"rldcl", MDS(30,8,0), MDS_MASK
, PPC64
, PPCNONE
, {RA
, RS
, RB
, MB6
}},
4205 {"rotld.", MDS(30,8,1), MDSMB_MASK
, PPC64
, PPCNONE
, {RA
, RS
, RB
}},
4206 {"rldcl.", MDS(30,8,1), MDS_MASK
, PPC64
, PPCNONE
, {RA
, RS
, RB
, MB6
}},
4208 {"rldcr", MDS(30,9,0), MDS_MASK
, PPC64
, PPCNONE
, {RA
, RS
, RB
, ME6
}},
4209 {"rldcr.", MDS(30,9,1), MDS_MASK
, PPC64
, PPCNONE
, {RA
, RS
, RB
, ME6
}},
4211 {"cmpw", XOPL(31,0,0), XCMPL_MASK
, PPCCOM
, PPCNONE
, {OBF
, RA
, RB
}},
4212 {"cmpd", XOPL(31,0,1), XCMPL_MASK
, PPC64
, PPCNONE
, {OBF
, RA
, RB
}},
4213 {"cmp", X(31,0), XCMP_MASK
, PPC
|PPCVLE
, PPCNONE
, {BF
, L
, RA
, RB
}},
4214 {"cmp", X(31,0), XCMPL_MASK
, PWRCOM
, PPC
, {BF
, RA
, RB
}},
4216 {"twlgt", XTO(31,4,TOLGT
), XTO_MASK
, PPCCOM
|PPCVLE
, PPCNONE
, {RA
, RB
}},
4217 {"tlgt", XTO(31,4,TOLGT
), XTO_MASK
, PWRCOM
, PPCNONE
, {RA
, RB
}},
4218 {"twllt", XTO(31,4,TOLLT
), XTO_MASK
, PPCCOM
|PPCVLE
, PPCNONE
, {RA
, RB
}},
4219 {"tllt", XTO(31,4,TOLLT
), XTO_MASK
, PWRCOM
, PPCNONE
, {RA
, RB
}},
4220 {"tweq", XTO(31,4,TOEQ
), XTO_MASK
, PPCCOM
|PPCVLE
, PPCNONE
, {RA
, RB
}},
4221 {"teq", XTO(31,4,TOEQ
), XTO_MASK
, PWRCOM
, PPCNONE
, {RA
, RB
}},
4222 {"twlge", XTO(31,4,TOLGE
), XTO_MASK
, PPCCOM
|PPCVLE
, PPCNONE
, {RA
, RB
}},
4223 {"tlge", XTO(31,4,TOLGE
), XTO_MASK
, PWRCOM
, PPCNONE
, {RA
, RB
}},
4224 {"twlnl", XTO(31,4,TOLNL
), XTO_MASK
, PPCCOM
|PPCVLE
, PPCNONE
, {RA
, RB
}},
4225 {"tlnl", XTO(31,4,TOLNL
), XTO_MASK
, PWRCOM
, PPCNONE
, {RA
, RB
}},
4226 {"twlle", XTO(31,4,TOLLE
), XTO_MASK
, PPCCOM
|PPCVLE
, PPCNONE
, {RA
, RB
}},
4227 {"tlle", XTO(31,4,TOLLE
), XTO_MASK
, PWRCOM
, PPCNONE
, {RA
, RB
}},
4228 {"twlng", XTO(31,4,TOLNG
), XTO_MASK
, PPCCOM
|PPCVLE
, PPCNONE
, {RA
, RB
}},
4229 {"tlng", XTO(31,4,TOLNG
), XTO_MASK
, PWRCOM
, PPCNONE
, {RA
, RB
}},
4230 {"twgt", XTO(31,4,TOGT
), XTO_MASK
, PPCCOM
|PPCVLE
, PPCNONE
, {RA
, RB
}},
4231 {"tgt", XTO(31,4,TOGT
), XTO_MASK
, PWRCOM
, PPCNONE
, {RA
, RB
}},
4232 {"twge", XTO(31,4,TOGE
), XTO_MASK
, PPCCOM
|PPCVLE
, PPCNONE
, {RA
, RB
}},
4233 {"tge", XTO(31,4,TOGE
), XTO_MASK
, PWRCOM
, PPCNONE
, {RA
, RB
}},
4234 {"twnl", XTO(31,4,TONL
), XTO_MASK
, PPCCOM
|PPCVLE
, PPCNONE
, {RA
, RB
}},
4235 {"tnl", XTO(31,4,TONL
), XTO_MASK
, PWRCOM
, PPCNONE
, {RA
, RB
}},
4236 {"twlt", XTO(31,4,TOLT
), XTO_MASK
, PPCCOM
|PPCVLE
, PPCNONE
, {RA
, RB
}},
4237 {"tlt", XTO(31,4,TOLT
), XTO_MASK
, PWRCOM
, PPCNONE
, {RA
, RB
}},
4238 {"twle", XTO(31,4,TOLE
), XTO_MASK
, PPCCOM
|PPCVLE
, PPCNONE
, {RA
, RB
}},
4239 {"tle", XTO(31,4,TOLE
), XTO_MASK
, PWRCOM
, PPCNONE
, {RA
, RB
}},
4240 {"twng", XTO(31,4,TONG
), XTO_MASK
, PPCCOM
|PPCVLE
, PPCNONE
, {RA
, RB
}},
4241 {"tng", XTO(31,4,TONG
), XTO_MASK
, PWRCOM
, PPCNONE
, {RA
, RB
}},
4242 {"twne", XTO(31,4,TONE
), XTO_MASK
, PPCCOM
|PPCVLE
, PPCNONE
, {RA
, RB
}},
4243 {"tne", XTO(31,4,TONE
), XTO_MASK
, PWRCOM
, PPCNONE
, {RA
, RB
}},
4244 {"trap", XTO(31,4,TOU
), 0xffffffff, PPCCOM
|PPCVLE
, PPCNONE
, {0}},
4245 {"tw", X(31,4), X_MASK
, PPCCOM
|PPCVLE
, PPCNONE
, {TO
, RA
, RB
}},
4246 {"t", X(31,4), X_MASK
, PWRCOM
, PPCNONE
, {TO
, RA
, RB
}},
4248 {"lvsl", X(31,6), X_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, RA0
, RB
}},
4249 {"lvebx", X(31,7), X_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, RA0
, RB
}},
4250 {"lbfcmx", APU(31,7,0), APU_MASK
, PPC405
, PPCNONE
, {FCRT
, RA
, RB
}},
4252 {"subfc", XO(31,8,0,0), XO_MASK
, PPCCOM
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
4253 {"sf", XO(31,8,0,0), XO_MASK
, PWRCOM
, PPCNONE
, {RT
, RA
, RB
}},
4254 {"subc", XO(31,8,0,0), XO_MASK
, PPCCOM
|PPCVLE
, PPCNONE
, {RT
, RB
, RA
}},
4255 {"subfc.", XO(31,8,0,1), XO_MASK
, PPCCOM
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
4256 {"sf.", XO(31,8,0,1), XO_MASK
, PWRCOM
, PPCNONE
, {RT
, RA
, RB
}},
4257 {"subc.", XO(31,8,0,1), XO_MASK
, PPCCOM
|PPCVLE
, PPCNONE
, {RT
, RB
, RA
}},
4259 {"mulhdu", XO(31,9,0,0), XO_MASK
, PPC64
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
4260 {"mulhdu.", XO(31,9,0,1), XO_MASK
, PPC64
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
4262 {"addc", XO(31,10,0,0), XO_MASK
, PPCCOM
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
4263 {"a", XO(31,10,0,0), XO_MASK
, PWRCOM
, PPCNONE
, {RT
, RA
, RB
}},
4264 {"addc.", XO(31,10,0,1), XO_MASK
, PPCCOM
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
4265 {"a.", XO(31,10,0,1), XO_MASK
, PWRCOM
, PPCNONE
, {RT
, RA
, RB
}},
4267 {"mulhwu", XO(31,11,0,0), XO_MASK
, PPC
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
4268 {"mulhwu.", XO(31,11,0,1), XO_MASK
, PPC
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
4270 {"isellt", X(31,15), X_MASK
, PPCISEL
, PPCNONE
, {RT
, RA0
, RB
}},
4272 {"tlbilxlpid", XTO(31,18,0), XTO_MASK
, E500MC
|PPCA2
, PPCNONE
, {0}},
4273 {"tlbilxpid", XTO(31,18,1), XTO_MASK
, E500MC
|PPCA2
, PPCNONE
, {0}},
4274 {"tlbilxva", XTO(31,18,3), XTO_MASK
, E500MC
|PPCA2
, PPCNONE
, {RA0
, RB
}},
4275 {"tlbilx", X(31,18), X_MASK
, E500MC
|PPCA2
, PPCNONE
, {T
, RA0
, RB
}},
4277 {"mfcr", XFXM(31,19,0,0), XFXFXM_MASK
, POWER4
, PPCNONE
, {RT
, FXM4
}},
4278 {"mfcr", XFXM(31,19,0,0), XRARB_MASK
, COM
|PPCVLE
, POWER4
, {RT
}},
4279 {"mfocrf", XFXM(31,19,0,1), XFXFXM_MASK
, COM
|PPCVLE
, PPCNONE
, {RT
, FXM
}},
4281 {"lwarx", X(31,20), XEH_MASK
, PPC
|PPCVLE
, PPCNONE
, {RT
, RA0
, RB
, EH
}},
4283 {"ldx", X(31,21), X_MASK
, PPC64
|PPCVLE
, PPCNONE
, {RT
, RA0
, RB
}},
4285 {"icbt", X(31,22), X_MASK
, BOOKE
|PPCE300
|PPCA2
|PPC476
|PPCVLE
, PPCNONE
, {CT
, RA0
, RB
}},
4287 {"lwzx", X(31,23), X_MASK
, PPCCOM
|PPCVLE
, PPCNONE
, {RT
, RA0
, RB
}},
4288 {"lx", X(31,23), X_MASK
, PWRCOM
, PPCNONE
, {RT
, RA
, RB
}},
4290 {"slw", XRC(31,24,0), X_MASK
, PPCCOM
|PPCVLE
, PPCNONE
, {RA
, RS
, RB
}},
4291 {"sl", XRC(31,24,0), X_MASK
, PWRCOM
, PPCNONE
, {RA
, RS
, RB
}},
4292 {"slw.", XRC(31,24,1), X_MASK
, PPCCOM
|PPCVLE
, PPCNONE
, {RA
, RS
, RB
}},
4293 {"sl.", XRC(31,24,1), X_MASK
, PWRCOM
, PPCNONE
, {RA
, RS
, RB
}},
4295 {"cntlzw", XRC(31,26,0), XRB_MASK
, PPCCOM
|PPCVLE
, PPCNONE
, {RA
, RS
}},
4296 {"cntlz", XRC(31,26,0), XRB_MASK
, PWRCOM
, PPCNONE
, {RA
, RS
}},
4297 {"cntlzw.", XRC(31,26,1), XRB_MASK
, PPCCOM
|PPCVLE
, PPCNONE
, {RA
, RS
}},
4298 {"cntlz.", XRC(31,26,1), XRB_MASK
, PWRCOM
, PPCNONE
, {RA
, RS
}},
4300 {"sld", XRC(31,27,0), X_MASK
, PPC64
, PPCNONE
, {RA
, RS
, RB
}},
4301 {"sld.", XRC(31,27,1), X_MASK
, PPC64
, PPCNONE
, {RA
, RS
, RB
}},
4303 {"and", XRC(31,28,0), X_MASK
, COM
|PPCVLE
, PPCNONE
, {RA
, RS
, RB
}},
4304 {"and.", XRC(31,28,1), X_MASK
, COM
|PPCVLE
, PPCNONE
, {RA
, RS
, RB
}},
4306 {"maskg", XRC(31,29,0), X_MASK
, M601
, PPCA2
, {RA
, RS
, RB
}},
4307 {"maskg.", XRC(31,29,1), X_MASK
, M601
, PPCA2
, {RA
, RS
, RB
}},
4309 {"ldepx", X(31,29), X_MASK
, E500MC
|PPCA2
|PPCVLE
, PPCNONE
, {RT
, RA0
, RB
}},
4310 {"lwepx", X(31,31), X_MASK
, E500MC
|PPCA2
|PPCVLE
, PPCNONE
, {RT
, RA0
, RB
}},
4312 {"cmplw", XOPL(31,32,0), XCMPL_MASK
, PPCCOM
|PPCVLE
, PPCNONE
, {OBF
, RA
, RB
}},
4313 {"cmpld", XOPL(31,32,1), XCMPL_MASK
, PPC64
, PPCNONE
, {OBF
, RA
, RB
}},
4314 {"cmpl", X(31,32), XCMP_MASK
, PPC
|PPCVLE
, PPCNONE
, {BF
, L
, RA
, RB
}},
4315 {"cmpl", X(31,32), XCMPL_MASK
, PWRCOM
, PPC
, {BF
, RA
, RB
}},
4317 {"lvsr", X(31,38), X_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, RA0
, RB
}},
4318 {"lvehx", X(31,39), X_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, RA0
, RB
}},
4319 {"lhfcmx", APU(31,39,0), APU_MASK
, PPC405
, PPCNONE
, {FCRT
, RA
, RB
}},
4321 {"mviwsplt", X(31,46), X_MASK
, PPCVEC2
, PPCNONE
, {VD
, RA
, RB
}},
4323 {"iselgt", X(31,47), X_MASK
, PPCISEL
, PPCNONE
, {RT
, RA0
, RB
}},
4325 {"lvewx", X(31,71), X_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, RA0
, RB
}},
4327 {"addg6s", XO(31,74,0,0), XO_MASK
, POWER6
, PPCNONE
, {RT
, RA
, RB
}},
4329 {"iseleq", X(31,79), X_MASK
, PPCISEL
, PPCNONE
, {RT
, RA0
, RB
}},
4331 {"isel", XISEL(31,15), XISEL_MASK
, PPCISEL
|TITAN
|PPCVLE
, PPCNONE
, {RT
, RA0
, RB
, CRB
}},
4333 {"subf", XO(31,40,0,0), XO_MASK
, PPC
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
4334 {"sub", XO(31,40,0,0), XO_MASK
, PPC
|PPCVLE
, PPCNONE
, {RT
, RB
, RA
}},
4335 {"subf.", XO(31,40,0,1), XO_MASK
, PPC
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
4336 {"sub.", XO(31,40,0,1), XO_MASK
, PPC
|PPCVLE
, PPCNONE
, {RT
, RB
, RA
}},
4338 {"eratilx", X(31,51), X_MASK
, PPCA2
, PPCNONE
, {ERAT_T
, RA
, RB
}},
4340 {"lbarx", X(31,52), XEH_MASK
, POWER7
|PPCVLE
, PPCNONE
, {RT
, RA0
, RB
, EH
}},
4342 {"ldux", X(31,53), X_MASK
, PPC64
|PPCVLE
, PPCNONE
, {RT
, RAL
, RB
}},
4344 {"dcbst", X(31,54), XRT_MASK
, PPC
|PPCVLE
, PPCNONE
, {RA0
, RB
}},
4346 {"lwzux", X(31,55), X_MASK
, PPCCOM
|PPCVLE
, PPCNONE
, {RT
, RAL
, RB
}},
4347 {"lux", X(31,55), X_MASK
, PWRCOM
, PPCNONE
, {RT
, RA
, RB
}},
4349 {"cntlzd", XRC(31,58,0), XRB_MASK
, PPC64
|PPCVLE
, PPCNONE
, {RA
, RS
}},
4350 {"cntlzd.", XRC(31,58,1), XRB_MASK
, PPC64
|PPCVLE
, PPCNONE
, {RA
, RS
}},
4352 {"andc", XRC(31,60,0), X_MASK
, COM
|PPCVLE
, PPCNONE
, {RA
, RS
, RB
}},
4353 {"andc.", XRC(31,60,1), X_MASK
, COM
|PPCVLE
, PPCNONE
, {RA
, RS
, RB
}},
4355 {"waitrsv", X(31,62)|(1<<21), 0xffffffff, POWER7
|E500MC
|PPCA2
, PPCNONE
, {0}},
4356 {"waitimpl", X(31,62)|(2<<21), 0xffffffff, POWER7
|E500MC
|PPCA2
, PPCNONE
, {0}},
4357 {"wait", X(31,62), XWC_MASK
, POWER7
|E500MC
|PPCA2
|PPCVLE
, PPCNONE
, {WC
}},
4359 {"dcbstep", XRT(31,63,0), XRT_MASK
, E500MC
|PPCA2
|PPCVLE
, PPCNONE
, {RA0
, RB
}},
4361 {"tdlgt", XTO(31,68,TOLGT
), XTO_MASK
, PPC64
, PPCNONE
, {RA
, RB
}},
4362 {"tdllt", XTO(31,68,TOLLT
), XTO_MASK
, PPC64
, PPCNONE
, {RA
, RB
}},
4363 {"tdeq", XTO(31,68,TOEQ
), XTO_MASK
, PPC64
, PPCNONE
, {RA
, RB
}},
4364 {"tdlge", XTO(31,68,TOLGE
), XTO_MASK
, PPC64
, PPCNONE
, {RA
, RB
}},
4365 {"tdlnl", XTO(31,68,TOLNL
), XTO_MASK
, PPC64
, PPCNONE
, {RA
, RB
}},
4366 {"tdlle", XTO(31,68,TOLLE
), XTO_MASK
, PPC64
, PPCNONE
, {RA
, RB
}},
4367 {"tdlng", XTO(31,68,TOLNG
), XTO_MASK
, PPC64
, PPCNONE
, {RA
, RB
}},
4368 {"tdgt", XTO(31,68,TOGT
), XTO_MASK
, PPC64
, PPCNONE
, {RA
, RB
}},
4369 {"tdge", XTO(31,68,TOGE
), XTO_MASK
, PPC64
, PPCNONE
, {RA
, RB
}},
4370 {"tdnl", XTO(31,68,TONL
), XTO_MASK
, PPC64
, PPCNONE
, {RA
, RB
}},
4371 {"tdlt", XTO(31,68,TOLT
), XTO_MASK
, PPC64
, PPCNONE
, {RA
, RB
}},
4372 {"tdle", XTO(31,68,TOLE
), XTO_MASK
, PPC64
, PPCNONE
, {RA
, RB
}},
4373 {"tdng", XTO(31,68,TONG
), XTO_MASK
, PPC64
, PPCNONE
, {RA
, RB
}},
4374 {"tdne", XTO(31,68,TONE
), XTO_MASK
, PPC64
, PPCNONE
, {RA
, RB
}},
4375 {"td", X(31,68), X_MASK
, PPC64
|PPCVLE
, PPCNONE
, {TO
, RA
, RB
}},
4377 {"lwfcmx", APU(31,71,0), APU_MASK
, PPC405
, PPCNONE
, {FCRT
, RA
, RB
}},
4378 {"mulhd", XO(31,73,0,0), XO_MASK
, PPC64
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
4379 {"mulhd.", XO(31,73,0,1), XO_MASK
, PPC64
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
4381 {"mulhw", XO(31,75,0,0), XO_MASK
, PPC
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
4382 {"mulhw.", XO(31,75,0,1), XO_MASK
, PPC
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
4384 {"dlmzb", XRC(31,78,0), X_MASK
, PPC403
|PPC440
|TITAN
|PPCVLE
, PPCNONE
, {RA
, RS
, RB
}},
4385 {"dlmzb.", XRC(31,78,1), X_MASK
, PPC403
|PPC440
|TITAN
|PPCVLE
, PPCNONE
, {RA
, RS
, RB
}},
4387 {"mtsrd", X(31,82), XRB_MASK
|(1<<20), PPC64
, PPCNONE
, {SR
, RS
}},
4389 {"mfmsr", X(31,83), XRARB_MASK
, COM
|PPCVLE
, PPCNONE
, {RT
}},
4391 {"ldarx", X(31,84), XEH_MASK
, PPC64
|PPCVLE
, PPCNONE
, {RT
, RA0
, RB
, EH
}},
4393 {"dcbfl", XOPL(31,86,1), XRT_MASK
, POWER5
, PPC476
, {RA0
, RB
}},
4394 {"dcbf", X(31,86), XLRT_MASK
, PPC
|PPCVLE
, PPCNONE
, {RA0
, RB
, L
}},
4396 {"lbzx", X(31,87), X_MASK
, COM
|PPCVLE
, PPCNONE
, {RT
, RA0
, RB
}},
4398 {"lbepx", X(31,95), X_MASK
, E500MC
|PPCA2
|PPCVLE
, PPCNONE
, {RT
, RA0
, RB
}},
4400 {"dni", XRC(31,97,1), XRB_MASK
, E6500
, PPCNONE
, {DUI
, DCTL
}},
4402 {"lvx", X(31,103), X_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, RA0
, RB
}},
4403 {"lqfcmx", APU(31,103,0), APU_MASK
, PPC405
, PPCNONE
, {FCRT
, RA
, RB
}},
4405 {"neg", XO(31,104,0,0), XORB_MASK
, COM
|PPCVLE
, PPCNONE
, {RT
, RA
}},
4406 {"neg.", XO(31,104,0,1), XORB_MASK
, COM
|PPCVLE
, PPCNONE
, {RT
, RA
}},
4408 {"mul", XO(31,107,0,0), XO_MASK
, M601
, PPCNONE
, {RT
, RA
, RB
}},
4409 {"mul.", XO(31,107,0,1), XO_MASK
, M601
, PPCNONE
, {RT
, RA
, RB
}},
4411 {"mvidsplt", X(31,110), X_MASK
, PPCVEC2
, PPCNONE
, {VD
, RA
, RB
}},
4413 {"mtsrdin", X(31,114), XRA_MASK
, PPC64
, PPCNONE
, {RS
, RB
}},
4415 {"lharx", X(31,116), XEH_MASK
, POWER7
|PPCVLE
, PPCNONE
, {RT
, RA0
, RB
, EH
}},
4417 {"clf", X(31,118), XTO_MASK
, POWER
, PPCNONE
, {RA
, RB
}},
4419 {"lbzux", X(31,119), X_MASK
, COM
|PPCVLE
, PPCNONE
, {RT
, RAL
, RB
}},
4421 {"popcntb", X(31,122), XRB_MASK
, POWER5
|PPCVLE
, PPCNONE
, {RA
, RS
}},
4423 {"not", XRC(31,124,0), X_MASK
, COM
, PPCNONE
, {RA
, RS
, RBS
}},
4424 {"nor", XRC(31,124,0), X_MASK
, COM
|PPCVLE
, PPCNONE
, {RA
, RS
, RB
}},
4425 {"not.", XRC(31,124,1), X_MASK
, COM
, PPCNONE
, {RA
, RS
, RBS
}},
4426 {"nor.", XRC(31,124,1), X_MASK
, COM
|PPCVLE
, PPCNONE
, {RA
, RS
, RB
}},
4428 {"dcbfep", XRT(31,127,0), XRT_MASK
, E500MC
|PPCA2
|PPCVLE
, PPCNONE
, {RA0
, RB
}},
4430 {"wrtee", X(31,131), XRARB_MASK
, PPC403
|BOOKE
|PPCA2
|PPC476
|PPCVLE
, PPCNONE
, {RS
}},
4432 {"dcbtstls", X(31,134), X_MASK
, PPCCHLK
|PPC476
|TITAN
|PPCVLE
, PPCNONE
, {CT
, RA0
, RB
}},
4434 {"stvebx", X(31,135), X_MASK
, PPCVEC
, PPCNONE
, {VS
, RA0
, RB
}},
4435 {"stbfcmx", APU(31,135,0), APU_MASK
, PPC405
, PPCNONE
, {FCRT
, RA
, RB
}},
4437 {"subfe", XO(31,136,0,0), XO_MASK
, PPCCOM
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
4438 {"sfe", XO(31,136,0,0), XO_MASK
, PWRCOM
, PPCNONE
, {RT
, RA
, RB
}},
4439 {"subfe.", XO(31,136,0,1), XO_MASK
, PPCCOM
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
4440 {"sfe.", XO(31,136,0,1), XO_MASK
, PWRCOM
, PPCNONE
, {RT
, RA
, RB
}},
4442 {"adde", XO(31,138,0,0), XO_MASK
, PPCCOM
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
4443 {"ae", XO(31,138,0,0), XO_MASK
, PWRCOM
, PPCNONE
, {RT
, RA
, RB
}},
4444 {"adde.", XO(31,138,0,1), XO_MASK
, PPCCOM
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
4445 {"ae.", XO(31,138,0,1), XO_MASK
, PWRCOM
, PPCNONE
, {RT
, RA
, RB
}},
4447 {"dcbtstlse", X(31,142), X_MASK
, PPCCHLK
, E500MC
, {CT
, RA0
, RB
}},
4449 {"mtcr", XFXM(31,144,0xff,0), XRARB_MASK
, COM
, PPCNONE
, {RS
}},
4450 {"mtcrf", XFXM(31,144,0,0), XFXFXM_MASK
, COM
|PPCVLE
, PPCNONE
, {FXM
, RS
}},
4451 {"mtocrf", XFXM(31,144,0,1), XFXFXM_MASK
, COM
|PPCVLE
, PPCNONE
, {FXM
, RS
}},
4453 {"mtmsr", X(31,146), XRLARB_MASK
, COM
|PPCVLE
, PPCNONE
, {RS
, A_L
}},
4455 {"eratsx", XRC(31,147,0), X_MASK
, PPCA2
, PPCNONE
, {RT
, RA0
, RB
}},
4456 {"eratsx.", XRC(31,147,1), X_MASK
, PPCA2
, PPCNONE
, {RT
, RA0
, RB
}},
4458 {"stdx", X(31,149), X_MASK
, PPC64
|PPCVLE
, PPCNONE
, {RS
, RA0
, RB
}},
4460 {"stwcx.", XRC(31,150,1), X_MASK
, PPC
|PPCVLE
, PPCNONE
, {RS
, RA0
, RB
}},
4462 {"stwx", X(31,151), X_MASK
, PPCCOM
|PPCVLE
, PPCNONE
, {RS
, RA0
, RB
}},
4463 {"stx", X(31,151), X_MASK
, PWRCOM
, PPCNONE
, {RS
, RA
, RB
}},
4465 {"slq", XRC(31,152,0), X_MASK
, M601
, PPCNONE
, {RA
, RS
, RB
}},
4466 {"slq.", XRC(31,152,1), X_MASK
, M601
, PPCNONE
, {RA
, RS
, RB
}},
4468 {"sle", XRC(31,153,0), X_MASK
, M601
, PPCNONE
, {RA
, RS
, RB
}},
4469 {"sle.", XRC(31,153,1), X_MASK
, M601
, PPCNONE
, {RA
, RS
, RB
}},
4471 {"prtyw", X(31,154), XRB_MASK
, POWER6
|PPCA2
|PPC476
, PPCNONE
, {RA
, RS
}},
4473 {"stdepx", X(31,157), X_MASK
, E500MC
|PPCA2
|PPCVLE
, PPCNONE
, {RS
, RA0
, RB
}},
4475 {"stwepx", X(31,159), X_MASK
, E500MC
|PPCA2
|PPCVLE
, PPCNONE
, {RS
, RA0
, RB
}},
4477 {"wrteei", X(31,163), XE_MASK
, PPC403
|BOOKE
|PPCA2
|PPC476
|PPCVLE
, PPCNONE
, {E
}},
4479 {"dcbtls", X(31,166), X_MASK
, PPCCHLK
|PPC476
|TITAN
|PPCVLE
, PPCNONE
, {CT
, RA0
, RB
}},
4481 {"stvehx", X(31,167), X_MASK
, PPCVEC
, PPCNONE
, {VS
, RA0
, RB
}},
4482 {"sthfcmx", APU(31,167,0), APU_MASK
, PPC405
, PPCNONE
, {FCRT
, RA
, RB
}},
4484 {"dcbtlse", X(31,174), X_MASK
, PPCCHLK
, E500MC
, {CT
, RA0
, RB
}},
4486 {"mtmsrd", X(31,178), XRLARB_MASK
, PPC64
, PPCNONE
, {RS
, A_L
}},
4488 {"eratre", X(31,179), X_MASK
, PPCA2
, PPCNONE
, {RT
, RA
, WS
}},
4490 {"stdux", X(31,181), X_MASK
, PPC64
|PPCVLE
, PPCNONE
, {RS
, RAS
, RB
}},
4492 {"wchkall", X(31,182), X_MASK
, PPCA2
, PPCNONE
, {OBF
}},
4494 {"stwux", X(31,183), X_MASK
, PPCCOM
|PPCVLE
, PPCNONE
, {RS
, RAS
, RB
}},
4495 {"stux", X(31,183), X_MASK
, PWRCOM
, PPCNONE
, {RS
, RA0
, RB
}},
4497 {"sliq", XRC(31,184,0), X_MASK
, M601
, PPCNONE
, {RA
, RS
, SH
}},
4498 {"sliq.", XRC(31,184,1), X_MASK
, M601
, PPCNONE
, {RA
, RS
, SH
}},
4500 {"prtyd", X(31,186), XRB_MASK
, POWER6
|PPCA2
, PPCNONE
, {RA
, RS
}},
4502 {"icblq.", XRC(31,198,1), X_MASK
, E6500
, PPCNONE
, {CT
, RA0
, RB
}},
4504 {"stvewx", X(31,199), X_MASK
, PPCVEC
, PPCNONE
, {VS
, RA0
, RB
}},
4505 {"stwfcmx", APU(31,199,0), APU_MASK
, PPC405
, PPCNONE
, {FCRT
, RA
, RB
}},
4507 {"subfze", XO(31,200,0,0), XORB_MASK
, PPCCOM
|PPCVLE
, PPCNONE
, {RT
, RA
}},
4508 {"sfze", XO(31,200,0,0), XORB_MASK
, PWRCOM
, PPCNONE
, {RT
, RA
}},
4509 {"subfze.", XO(31,200,0,1), XORB_MASK
, PPCCOM
|PPCVLE
, PPCNONE
, {RT
, RA
}},
4510 {"sfze.", XO(31,200,0,1), XORB_MASK
, PWRCOM
, PPCNONE
, {RT
, RA
}},
4512 {"addze", XO(31,202,0,0), XORB_MASK
, PPCCOM
|PPCVLE
, PPCNONE
, {RT
, RA
}},
4513 {"aze", XO(31,202,0,0), XORB_MASK
, PWRCOM
, PPCNONE
, {RT
, RA
}},
4514 {"addze.", XO(31,202,0,1), XORB_MASK
, PPCCOM
|PPCVLE
, PPCNONE
, {RT
, RA
}},
4515 {"aze.", XO(31,202,0,1), XORB_MASK
, PWRCOM
, PPCNONE
, {RT
, RA
}},
4517 {"msgsnd", XRTRA(31,206,0,0), XRTRA_MASK
, E500MC
|PPCA2
|PPCVLE
, PPCNONE
, {RB
}},
4519 {"mtsr", X(31,210), XRB_MASK
|(1<<20), COM
, NON32
, {SR
, RS
}},
4521 {"eratwe", X(31,211), X_MASK
, PPCA2
, PPCNONE
, {RS
, RA
, WS
}},
4523 {"ldawx.", XRC(31,212,1), X_MASK
, PPCA2
, PPCNONE
, {RT
, RA0
, RB
}},
4525 {"stdcx.", XRC(31,214,1), X_MASK
, PPC64
|PPCVLE
, PPCNONE
, {RS
, RA0
, RB
}},
4527 {"stbx", X(31,215), X_MASK
, COM
|PPCVLE
, PPCNONE
, {RS
, RA0
, RB
}},
4529 {"sllq", XRC(31,216,0), X_MASK
, M601
, PPCNONE
, {RA
, RS
, RB
}},
4530 {"sllq.", XRC(31,216,1), X_MASK
, M601
, PPCNONE
, {RA
, RS
, RB
}},
4532 {"sleq", XRC(31,217,0), X_MASK
, M601
, PPCNONE
, {RA
, RS
, RB
}},
4533 {"sleq.", XRC(31,217,1), X_MASK
, M601
, PPCNONE
, {RA
, RS
, RB
}},
4535 {"stbepx", X(31,223), X_MASK
, E500MC
|PPCA2
|PPCVLE
, PPCNONE
, {RS
, RA0
, RB
}},
4537 {"icblc", X(31,230), X_MASK
, PPCCHLK
|PPC476
|TITAN
|PPCVLE
, PPCNONE
, {CT
, RA0
, RB
}},
4539 {"stvx", X(31,231), X_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VS
, RA0
, RB
}},
4540 {"stqfcmx", APU(31,231,0), APU_MASK
, PPC405
, PPCNONE
, {FCRT
, RA
, RB
}},
4542 {"subfme", XO(31,232,0,0), XORB_MASK
, PPCCOM
|PPCVLE
, PPCNONE
, {RT
, RA
}},
4543 {"sfme", XO(31,232,0,0), XORB_MASK
, PWRCOM
, PPCNONE
, {RT
, RA
}},
4544 {"subfme.", XO(31,232,0,1), XORB_MASK
, PPCCOM
|PPCVLE
, PPCNONE
, {RT
, RA
}},
4545 {"sfme.", XO(31,232,0,1), XORB_MASK
, PWRCOM
, PPCNONE
, {RT
, RA
}},
4547 {"mulld", XO(31,233,0,0), XO_MASK
, PPC64
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
4548 {"mulld.", XO(31,233,0,1), XO_MASK
, PPC64
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
4550 {"addme", XO(31,234,0,0), XORB_MASK
, PPCCOM
|PPCVLE
, PPCNONE
, {RT
, RA
}},
4551 {"ame", XO(31,234,0,0), XORB_MASK
, PWRCOM
, PPCNONE
, {RT
, RA
}},
4552 {"addme.", XO(31,234,0,1), XORB_MASK
, PPCCOM
|PPCVLE
, PPCNONE
, {RT
, RA
}},
4553 {"ame.", XO(31,234,0,1), XORB_MASK
, PWRCOM
, PPCNONE
, {RT
, RA
}},
4555 {"mullw", XO(31,235,0,0), XO_MASK
, PPCCOM
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
4556 {"muls", XO(31,235,0,0), XO_MASK
, PWRCOM
, PPCNONE
, {RT
, RA
, RB
}},
4557 {"mullw.", XO(31,235,0,1), XO_MASK
, PPCCOM
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
4558 {"muls.", XO(31,235,0,1), XO_MASK
, PWRCOM
, PPCNONE
, {RT
, RA
, RB
}},
4560 {"icblce", X(31,238), X_MASK
, PPCCHLK
, E500MC
|PPCA2
, {CT
, RA
, RB
}},
4561 {"msgclr", XRTRA(31,238,0,0),XRTRA_MASK
, E500MC
|PPCA2
|PPCVLE
, PPCNONE
, {RB
}},
4562 {"mtsrin", X(31,242), XRA_MASK
, PPC
, NON32
, {RS
, RB
}},
4563 {"mtsri", X(31,242), XRA_MASK
, POWER
, NON32
, {RS
, RB
}},
4565 {"dcbtstt", XRT(31,246,0x10), XRT_MASK
, POWER7
, PPCNONE
, {RA0
, RB
}},
4566 {"dcbtst", X(31,246), X_MASK
, POWER4
, PPCNONE
, {RA0
, RB
, CT
}},
4567 {"dcbtst", X(31,246), X_MASK
, PPC
|PPCVLE
, POWER4
, {CT
, RA0
, RB
}},
4569 {"stbux", X(31,247), X_MASK
, COM
|PPCVLE
, PPCNONE
, {RS
, RAS
, RB
}},
4571 {"slliq", XRC(31,248,0), X_MASK
, M601
, PPCNONE
, {RA
, RS
, SH
}},
4572 {"slliq.", XRC(31,248,1), X_MASK
, M601
, PPCNONE
, {RA
, RS
, SH
}},
4574 {"bpermd", X(31,252), X_MASK
, POWER7
|PPCA2
, PPCNONE
, {RA
, RS
, RB
}},
4576 {"dcbtstep", XRT(31,255,0), X_MASK
, E500MC
|PPCA2
|PPCVLE
, PPCNONE
, {RT
, RA0
, RB
}},
4578 {"mfdcrx", X(31,259), X_MASK
, BOOKE
|PPCA2
|PPC476
|PPCVLE
, TITAN
, {RS
, RA
}},
4579 {"mfdcrx.", XRC(31,259,1), X_MASK
, PPCA2
, PPCNONE
, {RS
, RA
}},
4581 {"lvexbx", X(31,261), X_MASK
, PPCVEC2
, PPCNONE
, {VD
, RA0
, RB
}},
4583 {"icbt", X(31,262), XRT_MASK
, PPC403
, PPCNONE
, {RA
, RB
}},
4585 {"lvepxl", X(31,263), X_MASK
, PPCVEC2
|PPCVLE
, PPCNONE
, {VD
, RA0
, RB
}},
4587 {"ldfcmx", APU(31,263,0), APU_MASK
, PPC405
, PPCNONE
, {FCRT
, RA
, RB
}},
4588 {"doz", XO(31,264,0,0), XO_MASK
, M601
, PPCNONE
, {RT
, RA
, RB
}},
4589 {"doz.", XO(31,264,0,1), XO_MASK
, M601
, PPCNONE
, {RT
, RA
, RB
}},
4591 {"add", XO(31,266,0,0), XO_MASK
, PPCCOM
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
4592 {"cax", XO(31,266,0,0), XO_MASK
, PWRCOM
, PPCNONE
, {RT
, RA
, RB
}},
4593 {"add.", XO(31,266,0,1), XO_MASK
, PPCCOM
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
4594 {"cax.", XO(31,266,0,1), XO_MASK
, PWRCOM
, PPCNONE
, {RT
, RA
, RB
}},
4596 {"ehpriv", X(31,270), 0xffffffff, E500MC
|PPCA2
|PPCVLE
, PPCNONE
, {0}},
4598 {"tlbiel", X(31,274), XRTLRA_MASK
, POWER4
, PPC476
, {RB
, L
}},
4600 {"mfapidi", X(31,275), X_MASK
, BOOKE
, TITAN
, {RT
, RA
}},
4602 {"lscbx", XRC(31,277,0), X_MASK
, M601
, PPCNONE
, {RT
, RA
, RB
}},
4603 {"lscbx.", XRC(31,277,1), X_MASK
, M601
, PPCNONE
, {RT
, RA
, RB
}},
4605 {"dcbtt", XRT(31,278,0x10), XRT_MASK
, POWER7
, PPCNONE
, {RA0
, RB
}},
4606 {"dcbt", X(31,278), X_MASK
, POWER4
, PPCNONE
, {RA0
, RB
, CT
}},
4607 {"dcbt", X(31,278), X_MASK
, PPC
|PPCVLE
, POWER4
, {CT
, RA0
, RB
}},
4609 {"lhzx", X(31,279), X_MASK
, COM
|PPCVLE
, PPCNONE
, {RT
, RA0
, RB
}},
4611 {"cdtbcd", X(31,282), XRB_MASK
, POWER6
, PPCNONE
, {RA
, RS
}},
4613 {"eqv", XRC(31,284,0), X_MASK
, COM
|PPCVLE
, PPCNONE
, {RA
, RS
, RB
}},
4614 {"eqv.", XRC(31,284,1), X_MASK
, COM
|PPCVLE
, PPCNONE
, {RA
, RS
, RB
}},
4616 {"lhepx", X(31,287), X_MASK
, E500MC
|PPCA2
|PPCVLE
, PPCNONE
, {RT
, RA0
, RB
}},
4618 {"mfdcrux", X(31,291), X_MASK
, PPC464
|PPCVLE
, PPCNONE
, {RS
, RA
}},
4620 {"lvexhx", X(31,293), X_MASK
, PPCVEC2
, PPCNONE
, {VD
, RA0
, RB
}},
4621 {"lvepx", X(31,295), X_MASK
, PPCVEC2
|PPCVLE
, PPCNONE
, {VD
, RA0
, RB
}},
4623 {"tlbie", X(31,306), XRTLRA_MASK
, PPC
, TITAN
, {RB
, L
}},
4624 {"tlbi", X(31,306), XRT_MASK
, POWER
, PPCNONE
, {RA0
, RB
}},
4626 {"eciwx", X(31,310), X_MASK
, PPC
, TITAN
, {RT
, RA0
, RB
}},
4628 {"lhzux", X(31,311), X_MASK
, COM
|PPCVLE
, PPCNONE
, {RT
, RAL
, RB
}},
4630 {"cbcdtd", X(31,314), XRB_MASK
, POWER6
, PPCNONE
, {RA
, RS
}},
4632 {"xor", XRC(31,316,0), X_MASK
, COM
|PPCVLE
, PPCNONE
, {RA
, RS
, RB
}},
4633 {"xor.", XRC(31,316,1), X_MASK
, COM
|PPCVLE
, PPCNONE
, {RA
, RS
, RB
}},
4635 {"dcbtep", XRT(31,319,0), X_MASK
, E500MC
|PPCA2
|PPCVLE
, PPCNONE
, {RT
, RA0
, RB
}},
4637 {"mfexisr", XSPR(31,323, 64), XSPR_MASK
, PPC403
, PPCNONE
, {RT
}},
4638 {"mfexier", XSPR(31,323, 66), XSPR_MASK
, PPC403
, PPCNONE
, {RT
}},
4639 {"mfbr0", XSPR(31,323,128), XSPR_MASK
, PPC403
, PPCNONE
, {RT
}},
4640 {"mfbr1", XSPR(31,323,129), XSPR_MASK
, PPC403
, PPCNONE
, {RT
}},
4641 {"mfbr2", XSPR(31,323,130), XSPR_MASK
, PPC403
, PPCNONE
, {RT
}},
4642 {"mfbr3", XSPR(31,323,131), XSPR_MASK
, PPC403
, PPCNONE
, {RT
}},
4643 {"mfbr4", XSPR(31,323,132), XSPR_MASK
, PPC403
, PPCNONE
, {RT
}},
4644 {"mfbr5", XSPR(31,323,133), XSPR_MASK
, PPC403
, PPCNONE
, {RT
}},
4645 {"mfbr6", XSPR(31,323,134), XSPR_MASK
, PPC403
, PPCNONE
, {RT
}},
4646 {"mfbr7", XSPR(31,323,135), XSPR_MASK
, PPC403
, PPCNONE
, {RT
}},
4647 {"mfbear", XSPR(31,323,144), XSPR_MASK
, PPC403
, PPCNONE
, {RT
}},
4648 {"mfbesr", XSPR(31,323,145), XSPR_MASK
, PPC403
, PPCNONE
, {RT
}},
4649 {"mfiocr", XSPR(31,323,160), XSPR_MASK
, PPC403
, PPCNONE
, {RT
}},
4650 {"mfdmacr0", XSPR(31,323,192), XSPR_MASK
, PPC403
, PPCNONE
, {RT
}},
4651 {"mfdmact0", XSPR(31,323,193), XSPR_MASK
, PPC403
, PPCNONE
, {RT
}},
4652 {"mfdmada0", XSPR(31,323,194), XSPR_MASK
, PPC403
, PPCNONE
, {RT
}},
4653 {"mfdmasa0", XSPR(31,323,195), XSPR_MASK
, PPC403
, PPCNONE
, {RT
}},
4654 {"mfdmacc0", XSPR(31,323,196), XSPR_MASK
, PPC403
, PPCNONE
, {RT
}},
4655 {"mfdmacr1", XSPR(31,323,200), XSPR_MASK
, PPC403
, PPCNONE
, {RT
}},
4656 {"mfdmact1", XSPR(31,323,201), XSPR_MASK
, PPC403
, PPCNONE
, {RT
}},
4657 {"mfdmada1", XSPR(31,323,202), XSPR_MASK
, PPC403
, PPCNONE
, {RT
}},
4658 {"mfdmasa1", XSPR(31,323,203), XSPR_MASK
, PPC403
, PPCNONE
, {RT
}},
4659 {"mfdmacc1", XSPR(31,323,204), XSPR_MASK
, PPC403
, PPCNONE
, {RT
}},
4660 {"mfdmacr2", XSPR(31,323,208), XSPR_MASK
, PPC403
, PPCNONE
, {RT
}},
4661 {"mfdmact2", XSPR(31,323,209), XSPR_MASK
, PPC403
, PPCNONE
, {RT
}},
4662 {"mfdmada2", XSPR(31,323,210), XSPR_MASK
, PPC403
, PPCNONE
, {RT
}},
4663 {"mfdmasa2", XSPR(31,323,211), XSPR_MASK
, PPC403
, PPCNONE
, {RT
}},
4664 {"mfdmacc2", XSPR(31,323,212), XSPR_MASK
, PPC403
, PPCNONE
, {RT
}},
4665 {"mfdmacr3", XSPR(31,323,216), XSPR_MASK
, PPC403
, PPCNONE
, {RT
}},
4666 {"mfdmact3", XSPR(31,323,217), XSPR_MASK
, PPC403
, PPCNONE
, {RT
}},
4667 {"mfdmada3", XSPR(31,323,218), XSPR_MASK
, PPC403
, PPCNONE
, {RT
}},
4668 {"mfdmasa3", XSPR(31,323,219), XSPR_MASK
, PPC403
, PPCNONE
, {RT
}},
4669 {"mfdmacc3", XSPR(31,323,220), XSPR_MASK
, PPC403
, PPCNONE
, {RT
}},
4670 {"mfdmasr", XSPR(31,323,224), XSPR_MASK
, PPC403
, PPCNONE
, {RT
}},
4671 {"mfdcr", X(31,323), X_MASK
, PPC403
|BOOKE
|PPCA2
|PPC476
|PPCVLE
, TITAN
, {RT
, SPR
}},
4672 {"mfdcr.", XRC(31,323,1), X_MASK
, PPCA2
, PPCNONE
, {RT
, SPR
}},
4674 {"lvexwx", X(31,325), X_MASK
, PPCVEC2
, PPCNONE
, {VD
, RA0
, RB
}},
4676 {"dcread", X(31,326), X_MASK
, PPC476
|TITAN
, PPCNONE
, {RT
, RA0
, RB
}},
4678 {"div", XO(31,331,0,0), XO_MASK
, M601
, PPCNONE
, {RT
, RA
, RB
}},
4679 {"div.", XO(31,331,0,1), XO_MASK
, M601
, PPCNONE
, {RT
, RA
, RB
}},
4681 {"lxvdsx", X(31,332), XX1_MASK
, PPCVSX
, PPCNONE
, {XT6
, RA0
, RB
}},
4683 {"mfpmr", X(31,334), X_MASK
, PPCPMR
|PPCE300
|PPCVLE
, PPCNONE
, {RT
, PMR
}},
4684 {"mftmr", X(31,366), X_MASK
, PPCTMR
|E6500
, PPCNONE
, {RT
, TMR
}},
4686 {"mfmq", XSPR(31,339, 0), XSPR_MASK
, M601
, PPCNONE
, {RT
}},
4687 {"mfxer", XSPR(31,339, 1), XSPR_MASK
, COM
|PPCVLE
, PPCNONE
, {RT
}},
4688 {"mfrtcu", XSPR(31,339, 4), XSPR_MASK
, COM
, TITAN
, {RT
}},
4689 {"mfrtcl", XSPR(31,339, 5), XSPR_MASK
, COM
, TITAN
, {RT
}},
4690 {"mfdec", XSPR(31,339, 6), XSPR_MASK
, MFDEC1
, PPCNONE
, {RT
}},
4691 {"mflr", XSPR(31,339, 8), XSPR_MASK
, COM
|PPCVLE
, PPCNONE
, {RT
}},
4692 {"mfctr", XSPR(31,339, 9), XSPR_MASK
, COM
|PPCVLE
, PPCNONE
, {RT
}},
4693 {"mftid", XSPR(31,339, 17), XSPR_MASK
, POWER
, PPCNONE
, {RT
}},
4694 {"mfdsisr", XSPR(31,339, 18), XSPR_MASK
, COM
, TITAN
, {RT
}},
4695 {"mfdar", XSPR(31,339, 19), XSPR_MASK
, COM
, TITAN
, {RT
}},
4696 {"mfdec", XSPR(31,339, 22), XSPR_MASK
, MFDEC2
, MFDEC1
, {RT
}},
4697 {"mfsdr0", XSPR(31,339, 24), XSPR_MASK
, POWER
, PPCNONE
, {RT
}},
4698 {"mfsdr1", XSPR(31,339, 25), XSPR_MASK
, COM
, TITAN
, {RT
}},
4699 {"mfsrr0", XSPR(31,339, 26), XSPR_MASK
, COM
, PPCNONE
, {RT
}},
4700 {"mfsrr1", XSPR(31,339, 27), XSPR_MASK
, COM
, PPCNONE
, {RT
}},
4701 {"mfcfar", XSPR(31,339, 28), XSPR_MASK
, POWER6
, PPCNONE
, {RT
}},
4702 {"mfpid", XSPR(31,339, 48), XSPR_MASK
, BOOKE
|PPCVLE
, PPCNONE
, {RT
}},
4703 {"mfcsrr0", XSPR(31,339, 58), XSPR_MASK
, BOOKE
|PPCVLE
, PPCNONE
, {RT
}},
4704 {"mfcsrr1", XSPR(31,339, 59), XSPR_MASK
, BOOKE
|PPCVLE
, PPCNONE
, {RT
}},
4705 {"mfdear", XSPR(31,339, 61), XSPR_MASK
, BOOKE
|PPCVLE
, PPCNONE
, {RT
}},
4706 {"mfesr", XSPR(31,339, 62), XSPR_MASK
, BOOKE
|PPCVLE
, PPCNONE
, {RT
}},
4707 {"mfivpr", XSPR(31,339, 63), XSPR_MASK
, BOOKE
|PPCVLE
, PPCNONE
, {RT
}},
4708 {"mfcmpa", XSPR(31,339,144), XSPR_MASK
, PPC860
, PPCNONE
, {RT
}},
4709 {"mfcmpb", XSPR(31,339,145), XSPR_MASK
, PPC860
, PPCNONE
, {RT
}},
4710 {"mfcmpc", XSPR(31,339,146), XSPR_MASK
, PPC860
, PPCNONE
, {RT
}},
4711 {"mfcmpd", XSPR(31,339,147), XSPR_MASK
, PPC860
, PPCNONE
, {RT
}},
4712 {"mficr", XSPR(31,339,148), XSPR_MASK
, PPC860
, PPCNONE
, {RT
}},
4713 {"mfder", XSPR(31,339,149), XSPR_MASK
, PPC860
, PPCNONE
, {RT
}},
4714 {"mfcounta", XSPR(31,339,150), XSPR_MASK
, PPC860
, PPCNONE
, {RT
}},
4715 {"mfcountb", XSPR(31,339,151), XSPR_MASK
, PPC860
, PPCNONE
, {RT
}},
4716 {"mfcmpe", XSPR(31,339,152), XSPR_MASK
, PPC860
, PPCNONE
, {RT
}},
4717 {"mfcmpf", XSPR(31,339,153), XSPR_MASK
, PPC860
, PPCNONE
, {RT
}},
4718 {"mfcmpg", XSPR(31,339,154), XSPR_MASK
, PPC860
, PPCNONE
, {RT
}},
4719 {"mfcmph", XSPR(31,339,155), XSPR_MASK
, PPC860
, PPCNONE
, {RT
}},
4720 {"mflctrl1", XSPR(31,339,156), XSPR_MASK
, PPC860
, PPCNONE
, {RT
}},
4721 {"mflctrl2", XSPR(31,339,157), XSPR_MASK
, PPC860
, PPCNONE
, {RT
}},
4722 {"mfictrl", XSPR(31,339,158), XSPR_MASK
, PPC860
, PPCNONE
, {RT
}},
4723 {"mfbar", XSPR(31,339,159), XSPR_MASK
, PPC860
, PPCNONE
, {RT
}},
4724 {"mfvrsave", XSPR(31,339,256), XSPR_MASK
, PPCVEC
, PPCNONE
, {RT
}},
4725 {"mfusprg0", XSPR(31,339,256), XSPR_MASK
, BOOKE
|PPCVLE
, PPCNONE
, {RT
}},
4726 {"mfsprg", XSPR(31,339,256), XSPRG_MASK
, PPC
|PPCVLE
, PPCNONE
, {RT
, SPRG
}},
4727 {"mfsprg4", XSPR(31,339,260), XSPR_MASK
, PPC405
|BOOKE
|PPCVLE
, PPCNONE
, {RT
}},
4728 {"mfsprg5", XSPR(31,339,261), XSPR_MASK
, PPC405
|BOOKE
|PPCVLE
, PPCNONE
, {RT
}},
4729 {"mfsprg6", XSPR(31,339,262), XSPR_MASK
, PPC405
|BOOKE
|PPCVLE
, PPCNONE
, {RT
}},
4730 {"mfsprg7", XSPR(31,339,263), XSPR_MASK
, PPC405
|BOOKE
|PPCVLE
, PPCNONE
, {RT
}},
4731 {"mftb", XSPR(31,339,268), XSPR_MASK
, BOOKE
|PPCVLE
, PPCNONE
, {RT
}},
4732 {"mftbl", XSPR(31,339,268), XSPR_MASK
, BOOKE
|PPCVLE
, PPCNONE
, {RT
}},
4733 {"mftbu", XSPR(31,339,269), XSPR_MASK
, BOOKE
|PPCVLE
, PPCNONE
, {RT
}},
4734 {"mfsprg0", XSPR(31,339,272), XSPR_MASK
, PPC
|PPCVLE
, PPCNONE
, {RT
}},
4735 {"mfsprg1", XSPR(31,339,273), XSPR_MASK
, PPC
|PPCVLE
, PPCNONE
, {RT
}},
4736 {"mfsprg2", XSPR(31,339,274), XSPR_MASK
, PPC
|PPCVLE
, PPCNONE
, {RT
}},
4737 {"mfsprg3", XSPR(31,339,275), XSPR_MASK
, PPC
|PPCVLE
, PPCNONE
, {RT
}},
4738 {"mfasr", XSPR(31,339,280), XSPR_MASK
, PPC64
, PPCNONE
, {RT
}},
4739 {"mfear", XSPR(31,339,282), XSPR_MASK
, PPC
, TITAN
, {RT
}},
4740 {"mfpir", XSPR(31,339,286), XSPR_MASK
, BOOKE
|PPCVLE
, PPCNONE
, {RT
}},
4741 {"mfpvr", XSPR(31,339,287), XSPR_MASK
, PPC
|PPCVLE
, PPCNONE
, {RT
}},
4742 {"mfdbsr", XSPR(31,339,304), XSPR_MASK
, BOOKE
|PPCVLE
, PPCNONE
, {RT
}},
4743 {"mfdbcr0", XSPR(31,339,308), XSPR_MASK
, BOOKE
|PPCVLE
, PPCNONE
, {RT
}},
4744 {"mfdbcr1", XSPR(31,339,309), XSPR_MASK
, BOOKE
|PPCVLE
, PPCNONE
, {RT
}},
4745 {"mfdbcr2", XSPR(31,339,310), XSPR_MASK
, BOOKE
|PPCVLE
, PPCNONE
, {RT
}},
4746 {"mfiac1", XSPR(31,339,312), XSPR_MASK
, BOOKE
|PPCVLE
, PPCNONE
, {RT
}},
4747 {"mfiac2", XSPR(31,339,313), XSPR_MASK
, BOOKE
|PPCVLE
, PPCNONE
, {RT
}},
4748 {"mfiac3", XSPR(31,339,314), XSPR_MASK
, BOOKE
|PPCVLE
, PPCNONE
, {RT
}},
4749 {"mfiac4", XSPR(31,339,315), XSPR_MASK
, BOOKE
|PPCVLE
, PPCNONE
, {RT
}},
4750 {"mfdac1", XSPR(31,339,316), XSPR_MASK
, BOOKE
|PPCVLE
, PPCNONE
, {RT
}},
4751 {"mfdac2", XSPR(31,339,317), XSPR_MASK
, BOOKE
|PPCVLE
, PPCNONE
, {RT
}},
4752 {"mfdvc1", XSPR(31,339,318), XSPR_MASK
, BOOKE
|PPCVLE
, PPCNONE
, {RT
}},
4753 {"mfdvc2", XSPR(31,339,319), XSPR_MASK
, BOOKE
|PPCVLE
, PPCNONE
, {RT
}},
4754 {"mftsr", XSPR(31,339,336), XSPR_MASK
, BOOKE
|PPCVLE
, PPCNONE
, {RT
}},
4755 {"mftcr", XSPR(31,339,340), XSPR_MASK
, BOOKE
|PPCVLE
, PPCNONE
, {RT
}},
4756 {"mfivor0", XSPR(31,339,400), XSPR_MASK
, BOOKE
|PPCVLE
, PPCNONE
, {RT
}},
4757 {"mfivor1", XSPR(31,339,401), XSPR_MASK
, BOOKE
|PPCVLE
, PPCNONE
, {RT
}},
4758 {"mfivor2", XSPR(31,339,402), XSPR_MASK
, BOOKE
|PPCVLE
, PPCNONE
, {RT
}},
4759 {"mfivor3", XSPR(31,339,403), XSPR_MASK
, BOOKE
|PPCVLE
, PPCNONE
, {RT
}},
4760 {"mfivor4", XSPR(31,339,404), XSPR_MASK
, BOOKE
|PPCVLE
, PPCNONE
, {RT
}},
4761 {"mfivor5", XSPR(31,339,405), XSPR_MASK
, BOOKE
|PPCVLE
, PPCNONE
, {RT
}},
4762 {"mfivor6", XSPR(31,339,406), XSPR_MASK
, BOOKE
|PPCVLE
, PPCNONE
, {RT
}},
4763 {"mfivor7", XSPR(31,339,407), XSPR_MASK
, BOOKE
|PPCVLE
, PPCNONE
, {RT
}},
4764 {"mfivor8", XSPR(31,339,408), XSPR_MASK
, BOOKE
|PPCVLE
, PPCNONE
, {RT
}},
4765 {"mfivor9", XSPR(31,339,409), XSPR_MASK
, BOOKE
|PPCVLE
, PPCNONE
, {RT
}},
4766 {"mfivor10", XSPR(31,339,410), XSPR_MASK
, BOOKE
|PPCVLE
, PPCNONE
, {RT
}},
4767 {"mfivor11", XSPR(31,339,411), XSPR_MASK
, BOOKE
|PPCVLE
, PPCNONE
, {RT
}},
4768 {"mfivor12", XSPR(31,339,412), XSPR_MASK
, BOOKE
|PPCVLE
, PPCNONE
, {RT
}},
4769 {"mfivor13", XSPR(31,339,413), XSPR_MASK
, BOOKE
|PPCVLE
, PPCNONE
, {RT
}},
4770 {"mfivor14", XSPR(31,339,414), XSPR_MASK
, BOOKE
|PPCVLE
, PPCNONE
, {RT
}},
4771 {"mfivor15", XSPR(31,339,415), XSPR_MASK
, BOOKE
|PPCVLE
, PPCNONE
, {RT
}},
4772 {"mfspefscr", XSPR(31,339,512), XSPR_MASK
, PPCSPE
, PPCNONE
, {RT
}},
4773 {"mfbbear", XSPR(31,339,513), XSPR_MASK
, PPCBRLK
, PPCNONE
, {RT
}},
4774 {"mfbbtar", XSPR(31,339,514), XSPR_MASK
, PPCBRLK
, PPCNONE
, {RT
}},
4775 {"mfivor32", XSPR(31,339,528), XSPR_MASK
, PPCSPE
, PPCNONE
, {RT
}},
4776 {"mfibatu", XSPR(31,339,528), XSPRBAT_MASK
, PPC
, TITAN
, {RT
, SPRBAT
}},
4777 {"mfivor33", XSPR(31,339,529), XSPR_MASK
, PPCSPE
, PPCNONE
, {RT
}},
4778 {"mfibatl", XSPR(31,339,529), XSPRBAT_MASK
, PPC
, TITAN
, {RT
, SPRBAT
}},
4779 {"mfivor34", XSPR(31,339,530), XSPR_MASK
, PPCSPE
, PPCNONE
, {RT
}},
4780 {"mfivor35", XSPR(31,339,531), XSPR_MASK
, PPCPMR
, PPCNONE
, {RT
}},
4781 {"mfdbatu", XSPR(31,339,536), XSPRBAT_MASK
, PPC
, TITAN
, {RT
, SPRBAT
}},
4782 {"mfdbatl", XSPR(31,339,537), XSPRBAT_MASK
, PPC
, TITAN
, {RT
, SPRBAT
}},
4783 {"mfic_cst", XSPR(31,339,560), XSPR_MASK
, PPC860
, PPCNONE
, {RT
}},
4784 {"mfic_adr", XSPR(31,339,561), XSPR_MASK
, PPC860
, PPCNONE
, {RT
}},
4785 {"mfic_dat", XSPR(31,339,562), XSPR_MASK
, PPC860
, PPCNONE
, {RT
}},
4786 {"mfdc_cst", XSPR(31,339,568), XSPR_MASK
, PPC860
, PPCNONE
, {RT
}},
4787 {"mfdc_adr", XSPR(31,339,569), XSPR_MASK
, PPC860
, PPCNONE
, {RT
}},
4788 {"mfdc_dat", XSPR(31,339,570), XSPR_MASK
, PPC860
, PPCNONE
, {RT
}},
4789 {"mfmcsrr0", XSPR(31,339,570), XSPR_MASK
, PPCRFMCI
, PPCNONE
, {RT
}},
4790 {"mfmcsrr1", XSPR(31,339,571), XSPR_MASK
, PPCRFMCI
, PPCNONE
, {RT
}},
4791 {"mfmcsr", XSPR(31,339,572), XSPR_MASK
, PPCRFMCI
, PPCNONE
, {RT
}},
4792 {"mfmcar", XSPR(31,339,573), XSPR_MASK
, PPCRFMCI
, TITAN
, {RT
}},
4793 {"mfdpdr", XSPR(31,339,630), XSPR_MASK
, PPC860
, PPCNONE
, {RT
}},
4794 {"mfdpir", XSPR(31,339,631), XSPR_MASK
, PPC860
, PPCNONE
, {RT
}},
4795 {"mfimmr", XSPR(31,339,638), XSPR_MASK
, PPC860
, PPCNONE
, {RT
}},
4796 {"mfmi_ctr", XSPR(31,339,784), XSPR_MASK
, PPC860
, PPCNONE
, {RT
}},
4797 {"mfmi_ap", XSPR(31,339,786), XSPR_MASK
, PPC860
, PPCNONE
, {RT
}},
4798 {"mfmi_epn", XSPR(31,339,787), XSPR_MASK
, PPC860
, PPCNONE
, {RT
}},
4799 {"mfmi_twc", XSPR(31,339,789), XSPR_MASK
, PPC860
, PPCNONE
, {RT
}},
4800 {"mfmi_rpn", XSPR(31,339,790), XSPR_MASK
, PPC860
, PPCNONE
, {RT
}},
4801 {"mfmd_ctr", XSPR(31,339,792), XSPR_MASK
, PPC860
, PPCNONE
, {RT
}},
4802 {"mfm_casid", XSPR(31,339,793), XSPR_MASK
, PPC860
, PPCNONE
, {RT
}},
4803 {"mfmd_ap", XSPR(31,339,794), XSPR_MASK
, PPC860
, PPCNONE
, {RT
}},
4804 {"mfmd_epn", XSPR(31,339,795), XSPR_MASK
, PPC860
, PPCNONE
, {RT
}},
4805 {"mfmd_twb", XSPR(31,339,796), XSPR_MASK
, PPC860
, PPCNONE
, {RT
}},
4806 {"mfmd_twc", XSPR(31,339,797), XSPR_MASK
, PPC860
, PPCNONE
, {RT
}},
4807 {"mfmd_rpn", XSPR(31,339,798), XSPR_MASK
, PPC860
, PPCNONE
, {RT
}},
4808 {"mfm_tw", XSPR(31,339,799), XSPR_MASK
, PPC860
, PPCNONE
, {RT
}},
4809 {"mfmi_dbcam", XSPR(31,339,816), XSPR_MASK
, PPC860
, PPCNONE
, {RT
}},
4810 {"mfmi_dbram0", XSPR(31,339,817), XSPR_MASK
, PPC860
, PPCNONE
, {RT
}},
4811 {"mfmi_dbram1", XSPR(31,339,818), XSPR_MASK
, PPC860
, PPCNONE
, {RT
}},
4812 {"mfmd_dbcam", XSPR(31,339,824), XSPR_MASK
, PPC860
, PPCNONE
, {RT
}},
4813 {"mfmd_dbram0", XSPR(31,339,825), XSPR_MASK
, PPC860
, PPCNONE
, {RT
}},
4814 {"mfmd_dbram1", XSPR(31,339,826), XSPR_MASK
, PPC860
, PPCNONE
, {RT
}},
4815 {"mfivndx", XSPR(31,339,880), XSPR_MASK
, TITAN
, PPCNONE
, {RT
}},
4816 {"mfdvndx", XSPR(31,339,881), XSPR_MASK
, TITAN
, PPCNONE
, {RT
}},
4817 {"mfivlim", XSPR(31,339,882), XSPR_MASK
, TITAN
, PPCNONE
, {RT
}},
4818 {"mfdvlim", XSPR(31,339,883), XSPR_MASK
, TITAN
, PPCNONE
, {RT
}},
4819 {"mfclcsr", XSPR(31,339,884), XSPR_MASK
, TITAN
, PPCNONE
, {RT
}},
4820 {"mfccr1", XSPR(31,339,888), XSPR_MASK
, TITAN
, PPCNONE
, {RT
}},
4821 {"mfrstcfg", XSPR(31,339,923), XSPR_MASK
, TITAN
, PPCNONE
, {RT
}},
4822 {"mfdcdbtrl", XSPR(31,339,924), XSPR_MASK
, TITAN
, PPCNONE
, {RT
}},
4823 {"mfdcdbtrh", XSPR(31,339,925), XSPR_MASK
, TITAN
, PPCNONE
, {RT
}},
4824 {"mficdbtr", XSPR(31,339,927), XSPR_MASK
, TITAN
, PPCNONE
, {RT
}},
4825 {"mfummcr0", XSPR(31,339,936), XSPR_MASK
, PPC750
, PPCNONE
, {RT
}},
4826 {"mfupmc1", XSPR(31,339,937), XSPR_MASK
, PPC750
, PPCNONE
, {RT
}},
4827 {"mfupmc2", XSPR(31,339,938), XSPR_MASK
, PPC750
, PPCNONE
, {RT
}},
4828 {"mfusia", XSPR(31,339,939), XSPR_MASK
, PPC750
, PPCNONE
, {RT
}},
4829 {"mfummcr1", XSPR(31,339,940), XSPR_MASK
, PPC750
, PPCNONE
, {RT
}},
4830 {"mfupmc3", XSPR(31,339,941), XSPR_MASK
, PPC750
, PPCNONE
, {RT
}},
4831 {"mfupmc4", XSPR(31,339,942), XSPR_MASK
, PPC750
, PPCNONE
, {RT
}},
4832 {"mfzpr", XSPR(31,339,944), XSPR_MASK
, PPC403
, PPCNONE
, {RT
}},
4833 {"mfpid", XSPR(31,339,945), XSPR_MASK
, PPC403
, PPCNONE
, {RT
}},
4834 {"mfmmucr", XSPR(31,339,946), XSPR_MASK
, TITAN
, PPCNONE
, {RT
}},
4835 {"mfccr0", XSPR(31,339,947), XSPR_MASK
, PPC405
|TITAN
, PPCNONE
, {RT
}},
4836 {"mfiac3", XSPR(31,339,948), XSPR_MASK
, PPC405
, PPCNONE
, {RT
}},
4837 {"mfiac4", XSPR(31,339,949), XSPR_MASK
, PPC405
, PPCNONE
, {RT
}},
4838 {"mfdvc1", XSPR(31,339,950), XSPR_MASK
, PPC405
, PPCNONE
, {RT
}},
4839 {"mfdvc2", XSPR(31,339,951), XSPR_MASK
, PPC405
, PPCNONE
, {RT
}},
4840 {"mfmmcr0", XSPR(31,339,952), XSPR_MASK
, PPC750
, PPCNONE
, {RT
}},
4841 {"mfpmc1", XSPR(31,339,953), XSPR_MASK
, PPC750
, PPCNONE
, {RT
}},
4842 {"mfsgr", XSPR(31,339,953), XSPR_MASK
, PPC403
, PPCNONE
, {RT
}},
4843 {"mfdcwr", XSPR(31,339,954), XSPR_MASK
, PPC403
, PPCNONE
, {RT
}},
4844 {"mfpmc2", XSPR(31,339,954), XSPR_MASK
, PPC750
, PPCNONE
, {RT
}},
4845 {"mfsia", XSPR(31,339,955), XSPR_MASK
, PPC750
, PPCNONE
, {RT
}},
4846 {"mfsler", XSPR(31,339,955), XSPR_MASK
, PPC405
, PPCNONE
, {RT
}},
4847 {"mfmmcr1", XSPR(31,339,956), XSPR_MASK
, PPC750
, PPCNONE
, {RT
}},
4848 {"mfsu0r", XSPR(31,339,956), XSPR_MASK
, PPC405
, PPCNONE
, {RT
}},
4849 {"mfdbcr1", XSPR(31,339,957), XSPR_MASK
, PPC405
, PPCNONE
, {RT
}},
4850 {"mfpmc3", XSPR(31,339,957), XSPR_MASK
, PPC750
, PPCNONE
, {RT
}},
4851 {"mfpmc4", XSPR(31,339,958), XSPR_MASK
, PPC750
, PPCNONE
, {RT
}},
4852 {"mficdbdr", XSPR(31,339,979), XSPR_MASK
, PPC403
|TITAN
, PPCNONE
, {RT
}},
4853 {"mfesr", XSPR(31,339,980), XSPR_MASK
, PPC403
, PPCNONE
, {RT
}},
4854 {"mfdear", XSPR(31,339,981), XSPR_MASK
, PPC403
, PPCNONE
, {RT
}},
4855 {"mfevpr", XSPR(31,339,982), XSPR_MASK
, PPC403
, PPCNONE
, {RT
}},
4856 {"mfcdbcr", XSPR(31,339,983), XSPR_MASK
, PPC403
, PPCNONE
, {RT
}},
4857 {"mftsr", XSPR(31,339,984), XSPR_MASK
, PPC403
, PPCNONE
, {RT
}},
4858 {"mftcr", XSPR(31,339,986), XSPR_MASK
, PPC403
, PPCNONE
, {RT
}},
4859 {"mfpit", XSPR(31,339,987), XSPR_MASK
, PPC403
, PPCNONE
, {RT
}},
4860 {"mftbhi", XSPR(31,339,988), XSPR_MASK
, PPC403
, PPCNONE
, {RT
}},
4861 {"mftblo", XSPR(31,339,989), XSPR_MASK
, PPC403
, PPCNONE
, {RT
}},
4862 {"mfsrr2", XSPR(31,339,990), XSPR_MASK
, PPC403
, PPCNONE
, {RT
}},
4863 {"mfsrr3", XSPR(31,339,991), XSPR_MASK
, PPC403
, PPCNONE
, {RT
}},
4864 {"mfdbsr", XSPR(31,339,1008), XSPR_MASK
, PPC403
, PPCNONE
, {RT
}},
4865 {"mfdbcr0", XSPR(31,339,1010), XSPR_MASK
, PPC405
, PPCNONE
, {RT
}},
4866 {"mfdbdr", XSPR(31,339,1011), XSPR_MASK
, TITAN
, PPCNONE
, {RS
}},
4867 {"mfiac1", XSPR(31,339,1012), XSPR_MASK
, PPC403
, PPCNONE
, {RT
}},
4868 {"mfiac2", XSPR(31,339,1013), XSPR_MASK
, PPC403
, PPCNONE
, {RT
}},
4869 {"mfdac1", XSPR(31,339,1014), XSPR_MASK
, PPC403
, PPCNONE
, {RT
}},
4870 {"mfdac2", XSPR(31,339,1015), XSPR_MASK
, PPC403
, PPCNONE
, {RT
}},
4871 {"mfl2cr", XSPR(31,339,1017), XSPR_MASK
, PPC750
, PPCNONE
, {RT
}},
4872 {"mfdccr", XSPR(31,339,1018), XSPR_MASK
, PPC403
, PPCNONE
, {RT
}},
4873 {"mficcr", XSPR(31,339,1019), XSPR_MASK
, PPC403
, PPCNONE
, {RT
}},
4874 {"mfictc", XSPR(31,339,1019), XSPR_MASK
, PPC750
, PPCNONE
, {RT
}},
4875 {"mfpbl1", XSPR(31,339,1020), XSPR_MASK
, PPC403
, PPCNONE
, {RT
}},
4876 {"mfthrm1", XSPR(31,339,1020), XSPR_MASK
, PPC750
, PPCNONE
, {RT
}},
4877 {"mfpbu1", XSPR(31,339,1021), XSPR_MASK
, PPC403
, PPCNONE
, {RT
}},
4878 {"mfthrm2", XSPR(31,339,1021), XSPR_MASK
, PPC750
, PPCNONE
, {RT
}},
4879 {"mfpbl2", XSPR(31,339,1022), XSPR_MASK
, PPC403
, PPCNONE
, {RT
}},
4880 {"mfthrm3", XSPR(31,339,1022), XSPR_MASK
, PPC750
, PPCNONE
, {RT
}},
4881 {"mfpbu2", XSPR(31,339,1023), XSPR_MASK
, PPC403
, PPCNONE
, {RT
}},
4882 {"mfspr", X(31,339), X_MASK
, COM
|PPCVLE
, PPCNONE
, {RT
, SPR
}},
4884 {"lwax", X(31,341), X_MASK
, PPC64
|PPCVLE
, PPCNONE
, {RT
, RA0
, RB
}},
4886 {"dst", XDSS(31,342,0), XDSS_MASK
, PPCVEC
, PPCNONE
, {RA
, RB
, STRM
}},
4888 {"lhax", X(31,343), X_MASK
, COM
|PPCVLE
, PPCNONE
, {RT
, RA0
, RB
}},
4890 {"lvxl", X(31,359), X_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, RA0
, RB
}},
4892 {"abs", XO(31,360,0,0), XORB_MASK
, M601
, PPCNONE
, {RT
, RA
}},
4893 {"abs.", XO(31,360,0,1), XORB_MASK
, M601
, PPCNONE
, {RT
, RA
}},
4895 {"divs", XO(31,363,0,0), XO_MASK
, M601
, PPCNONE
, {RT
, RA
, RB
}},
4896 {"divs.", XO(31,363,0,1), XO_MASK
, M601
, PPCNONE
, {RT
, RA
, RB
}},
4898 {"tlbia", X(31,370), 0xffffffff, PPC
, TITAN
, {0}},
4900 {"mftbl", XSPR(31,371,268), XSPR_MASK
, PPC
, NO371
, {RT
}},
4901 {"mftbu", XSPR(31,371,269), XSPR_MASK
, PPC
, NO371
, {RT
}},
4902 {"mftb", X(31,371), X_MASK
, PPC
|PPCA2
, NO371
|POWER7
, {RT
, TBR
}},
4904 {"lwaux", X(31,373), X_MASK
, PPC64
|PPCVLE
, PPCNONE
, {RT
, RAL
, RB
}},
4906 {"dstst", XDSS(31,374,0), XDSS_MASK
, PPCVEC
, PPCNONE
, {RA
, RB
, STRM
}},
4908 {"lhaux", X(31,375), X_MASK
, COM
|PPCVLE
, PPCNONE
, {RT
, RAL
, RB
}},
4910 {"popcntw", X(31,378), XRB_MASK
, POWER7
|PPCA2
, PPCNONE
, {RA
, RS
}},
4912 {"mtdcrx", X(31,387), X_MASK
, BOOKE
|PPCA2
|PPC476
|PPCVLE
, TITAN
, {RA
, RS
}},
4913 {"mtdcrx.", XRC(31,387,1), X_MASK
, PPCA2
, PPCNONE
, {RA
, RS
}},
4915 {"stvexbx", X(31,389), X_MASK
, PPCVEC2
, PPCNONE
, {VS
, RA0
, RB
}},
4917 {"dcblc", X(31,390), X_MASK
, PPCCHLK
|PPC476
|TITAN
|PPCVLE
, PPCNONE
, {CT
, RA0
, RB
}},
4918 {"stdfcmx", APU(31,391,0), APU_MASK
, PPC405
, PPCNONE
, {FCRT
, RA
, RB
}},
4920 {"divdeu", XO(31,393,0,0), XO_MASK
, POWER7
|PPCA2
, PPCNONE
, {RT
, RA
, RB
}},
4921 {"divdeu.", XO(31,393,0,1), XO_MASK
, POWER7
|PPCA2
, PPCNONE
, {RT
, RA
, RB
}},
4922 {"divweu", XO(31,395,0,0), XO_MASK
, POWER7
|PPCA2
, PPCNONE
, {RT
, RA
, RB
}},
4923 {"divweu.", XO(31,395,0,1), XO_MASK
, POWER7
|PPCA2
, PPCNONE
, {RT
, RA
, RB
}},
4925 {"dcblce", X(31,398), X_MASK
, PPCCHLK
, E500MC
, {CT
, RA
, RB
}},
4927 {"slbmte", X(31,402), XRA_MASK
, PPC64
, PPCNONE
, {RS
, RB
}},
4929 {"icswx", XRC(31,406,0), X_MASK
, POWER7
|PPCA2
, PPCNONE
, {RS
, RA
, RB
}},
4930 {"icswx.", XRC(31,406,1), X_MASK
, POWER7
|PPCA2
, PPCNONE
, {RS
, RA
, RB
}},
4932 {"sthx", X(31,407), X_MASK
, COM
|PPCVLE
, PPCNONE
, {RS
, RA0
, RB
}},
4934 {"orc", XRC(31,412,0), X_MASK
, COM
|PPCVLE
, PPCNONE
, {RA
, RS
, RB
}},
4935 {"orc.", XRC(31,412,1), X_MASK
, COM
|PPCVLE
, PPCNONE
, {RA
, RS
, RB
}},
4937 {"sthepx", X(31,415), X_MASK
, E500MC
|PPCA2
|PPCVLE
, PPCNONE
, {RS
, RA0
, RB
}},
4939 {"mtdcrux", X(31,419), X_MASK
, PPC464
|PPCVLE
, PPCNONE
, {RA
, RS
}},
4941 {"stvexhx", X(31,421), X_MASK
, PPCVEC2
, PPCNONE
, {VS
, RA0
, RB
}},
4943 {"dcblq.", XRC(31,422,1), X_MASK
, E6500
, PPCNONE
, {CT
, RA0
, RB
}},
4945 {"divde", XO(31,425,0,0), XO_MASK
, POWER7
|PPCA2
, PPCNONE
, {RT
, RA
, RB
}},
4946 {"divde.", XO(31,425,0,1), XO_MASK
, POWER7
|PPCA2
, PPCNONE
, {RT
, RA
, RB
}},
4947 {"divwe", XO(31,427,0,0), XO_MASK
, POWER7
|PPCA2
, PPCNONE
, {RT
, RA
, RB
}},
4948 {"divwe.", XO(31,427,0,1), XO_MASK
, POWER7
|PPCA2
, PPCNONE
, {RT
, RA
, RB
}},
4950 {"slbie", X(31,434), XRTRA_MASK
, PPC64
, PPCNONE
, {RB
}},
4952 {"ecowx", X(31,438), X_MASK
, PPC
, TITAN
, {RT
, RA0
, RB
}},
4954 {"sthux", X(31,439), X_MASK
, COM
|PPCVLE
, PPCNONE
, {RS
, RAS
, RB
}},
4956 {"mdors", 0x7f9ce378, 0xffffffff, E500MC
, PPCNONE
, {0}},
4958 {"miso", 0x7f5ad378, 0xffffffff, E6500
, PPCNONE
, {0}},
4960 /* The "yield", "mdoio" and "mdoom" instructions are extended mnemonics for
4961 "or rX,rX,rX", with rX being r27, r29 and r30 respectively. */
4962 {"yield", 0x7f7bdb78, 0xffffffff, POWER7
, PPCNONE
, {0}},
4963 {"mdoio", 0x7fbdeb78, 0xffffffff, POWER7
, PPCNONE
, {0}},
4964 {"mdoom", 0x7fdef378, 0xffffffff, POWER7
, PPCNONE
, {0}},
4965 {"mr", XRC(31,444,0), X_MASK
, COM
|PPCVLE
, PPCNONE
, {RA
, RS
, RBS
}},
4966 {"or", XRC(31,444,0), X_MASK
, COM
|PPCVLE
, PPCNONE
, {RA
, RS
, RB
}},
4967 {"mr.", XRC(31,444,1), X_MASK
, COM
|PPCVLE
, PPCNONE
, {RA
, RS
, RBS
}},
4968 {"or.", XRC(31,444,1), X_MASK
, COM
|PPCVLE
, PPCNONE
, {RA
, RS
, RB
}},
4970 {"mtexisr", XSPR(31,451, 64), XSPR_MASK
, PPC403
, PPCNONE
, {RS
}},
4971 {"mtexier", XSPR(31,451, 66), XSPR_MASK
, PPC403
, PPCNONE
, {RS
}},
4972 {"mtbr0", XSPR(31,451,128), XSPR_MASK
, PPC403
, PPCNONE
, {RS
}},
4973 {"mtbr1", XSPR(31,451,129), XSPR_MASK
, PPC403
, PPCNONE
, {RS
}},
4974 {"mtbr2", XSPR(31,451,130), XSPR_MASK
, PPC403
, PPCNONE
, {RS
}},
4975 {"mtbr3", XSPR(31,451,131), XSPR_MASK
, PPC403
, PPCNONE
, {RS
}},
4976 {"mtbr4", XSPR(31,451,132), XSPR_MASK
, PPC403
, PPCNONE
, {RS
}},
4977 {"mtbr5", XSPR(31,451,133), XSPR_MASK
, PPC403
, PPCNONE
, {RS
}},
4978 {"mtbr6", XSPR(31,451,134), XSPR_MASK
, PPC403
, PPCNONE
, {RS
}},
4979 {"mtbr7", XSPR(31,451,135), XSPR_MASK
, PPC403
, PPCNONE
, {RS
}},
4980 {"mtbear", XSPR(31,451,144), XSPR_MASK
, PPC403
, PPCNONE
, {RS
}},
4981 {"mtbesr", XSPR(31,451,145), XSPR_MASK
, PPC403
, PPCNONE
, {RS
}},
4982 {"mtiocr", XSPR(31,451,160), XSPR_MASK
, PPC403
, PPCNONE
, {RS
}},
4983 {"mtdmacr0", XSPR(31,451,192), XSPR_MASK
, PPC403
, PPCNONE
, {RS
}},
4984 {"mtdmact0", XSPR(31,451,193), XSPR_MASK
, PPC403
, PPCNONE
, {RS
}},
4985 {"mtdmada0", XSPR(31,451,194), XSPR_MASK
, PPC403
, PPCNONE
, {RS
}},
4986 {"mtdmasa0", XSPR(31,451,195), XSPR_MASK
, PPC403
, PPCNONE
, {RS
}},
4987 {"mtdmacc0", XSPR(31,451,196), XSPR_MASK
, PPC403
, PPCNONE
, {RS
}},
4988 {"mtdmacr1", XSPR(31,451,200), XSPR_MASK
, PPC403
, PPCNONE
, {RS
}},
4989 {"mtdmact1", XSPR(31,451,201), XSPR_MASK
, PPC403
, PPCNONE
, {RS
}},
4990 {"mtdmada1", XSPR(31,451,202), XSPR_MASK
, PPC403
, PPCNONE
, {RS
}},
4991 {"mtdmasa1", XSPR(31,451,203), XSPR_MASK
, PPC403
, PPCNONE
, {RS
}},
4992 {"mtdmacc1", XSPR(31,451,204), XSPR_MASK
, PPC403
, PPCNONE
, {RS
}},
4993 {"mtdmacr2", XSPR(31,451,208), XSPR_MASK
, PPC403
, PPCNONE
, {RS
}},
4994 {"mtdmact2", XSPR(31,451,209), XSPR_MASK
, PPC403
, PPCNONE
, {RS
}},
4995 {"mtdmada2", XSPR(31,451,210), XSPR_MASK
, PPC403
, PPCNONE
, {RS
}},
4996 {"mtdmasa2", XSPR(31,451,211), XSPR_MASK
, PPC403
, PPCNONE
, {RS
}},
4997 {"mtdmacc2", XSPR(31,451,212), XSPR_MASK
, PPC403
, PPCNONE
, {RS
}},
4998 {"mtdmacr3", XSPR(31,451,216), XSPR_MASK
, PPC403
, PPCNONE
, {RS
}},
4999 {"mtdmact3", XSPR(31,451,217), XSPR_MASK
, PPC403
, PPCNONE
, {RS
}},
5000 {"mtdmada3", XSPR(31,451,218), XSPR_MASK
, PPC403
, PPCNONE
, {RS
}},
5001 {"mtdmasa3", XSPR(31,451,219), XSPR_MASK
, PPC403
, PPCNONE
, {RS
}},
5002 {"mtdmacc3", XSPR(31,451,220), XSPR_MASK
, PPC403
, PPCNONE
, {RS
}},
5003 {"mtdmasr", XSPR(31,451,224), XSPR_MASK
, PPC403
, PPCNONE
, {RS
}},
5004 {"mtdcr", X(31,451), X_MASK
, PPC403
|BOOKE
|PPCA2
|PPC476
|PPCVLE
, TITAN
, {SPR
, RS
}},
5005 {"mtdcr.", XRC(31,451,1), X_MASK
, PPCA2
, PPCNONE
, {SPR
, RS
}},
5007 {"stvexwx", X(31,453), X_MASK
, PPCVEC2
, PPCNONE
, {VS
, RA0
, RB
}},
5009 {"dccci", X(31,454), XRT_MASK
, PPC403
|PPC440
|TITAN
|PPCA2
, PPCNONE
, {RAOPT
, RBOPT
}},
5010 {"dci", X(31,454), XRARB_MASK
, PPCA2
|PPC476
|PPCVLE
, PPCNONE
, {CT
}},
5012 {"divdu", XO(31,457,0,0), XO_MASK
, PPC64
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
5013 {"divdu.", XO(31,457,0,1), XO_MASK
, PPC64
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
5015 {"divwu", XO(31,459,0,0), XO_MASK
, PPC
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
5016 {"divwu.", XO(31,459,0,1), XO_MASK
, PPC
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
5018 {"mtpmr", X(31,462), X_MASK
, PPCPMR
|PPCE300
|PPCVLE
, PPCNONE
, {PMR
, RS
}},
5019 {"mttmr", X(31,494), X_MASK
, PPCTMR
|E6500
, PPCNONE
, {TMR
, RS
}},
5021 {"mtmq", XSPR(31,467, 0), XSPR_MASK
, M601
, PPCNONE
, {RS
}},
5022 {"mtxer", XSPR(31,467, 1), XSPR_MASK
, COM
|PPCVLE
, PPCNONE
, {RS
}},
5023 {"mtlr", XSPR(31,467, 8), XSPR_MASK
, COM
|PPCVLE
, PPCNONE
, {RS
}},
5024 {"mtctr", XSPR(31,467, 9), XSPR_MASK
, COM
|PPCVLE
, PPCNONE
, {RS
}},
5025 {"mttid", XSPR(31,467, 17), XSPR_MASK
, POWER
, PPCNONE
, {RS
}},
5026 {"mtdsisr", XSPR(31,467, 18), XSPR_MASK
, COM
, TITAN
, {RS
}},
5027 {"mtdar", XSPR(31,467, 19), XSPR_MASK
, COM
, TITAN
, {RS
}},
5028 {"mtrtcu", XSPR(31,467, 20), XSPR_MASK
, COM
, TITAN
, {RS
}},
5029 {"mtrtcl", XSPR(31,467, 21), XSPR_MASK
, COM
, TITAN
, {RS
}},
5030 {"mtdec", XSPR(31,467, 22), XSPR_MASK
, COM
, PPCNONE
, {RS
}},
5031 {"mtsdr0", XSPR(31,467, 24), XSPR_MASK
, POWER
, PPCNONE
, {RS
}},
5032 {"mtsdr1", XSPR(31,467, 25), XSPR_MASK
, COM
, TITAN
, {RS
}},
5033 {"mtsrr0", XSPR(31,467, 26), XSPR_MASK
, COM
|PPCVLE
, PPCNONE
, {RS
}},
5034 {"mtsrr1", XSPR(31,467, 27), XSPR_MASK
, COM
|PPCVLE
, PPCNONE
, {RS
}},
5035 {"mtcfar", XSPR(31,467, 28), XSPR_MASK
, POWER6
, PPCNONE
, {RS
}},
5036 {"mtpid", XSPR(31,467, 48), XSPR_MASK
, BOOKE
|PPCVLE
, PPCNONE
, {RS
}},
5037 {"mtdecar", XSPR(31,467, 54), XSPR_MASK
, BOOKE
|PPCVLE
, PPCNONE
, {RS
}},
5038 {"mtcsrr0", XSPR(31,467, 58), XSPR_MASK
, BOOKE
|PPCVLE
, PPCNONE
, {RS
}},
5039 {"mtcsrr1", XSPR(31,467, 59), XSPR_MASK
, BOOKE
|PPCVLE
, PPCNONE
, {RS
}},
5040 {"mtdear", XSPR(31,467, 61), XSPR_MASK
, BOOKE
|PPCVLE
, PPCNONE
, {RS
}},
5041 {"mtesr", XSPR(31,467, 62), XSPR_MASK
, BOOKE
|PPCVLE
, PPCNONE
, {RS
}},
5042 {"mtivpr", XSPR(31,467, 63), XSPR_MASK
, BOOKE
|PPCVLE
, PPCNONE
, {RS
}},
5043 {"mtcmpa", XSPR(31,467,144), XSPR_MASK
, PPC860
, PPCNONE
, {RS
}},
5044 {"mtcmpb", XSPR(31,467,145), XSPR_MASK
, PPC860
, PPCNONE
, {RS
}},
5045 {"mtcmpc", XSPR(31,467,146), XSPR_MASK
, PPC860
, PPCNONE
, {RS
}},
5046 {"mtcmpd", XSPR(31,467,147), XSPR_MASK
, PPC860
, PPCNONE
, {RS
}},
5047 {"mticr", XSPR(31,467,148), XSPR_MASK
, PPC860
, PPCNONE
, {RS
}},
5048 {"mtder", XSPR(31,467,149), XSPR_MASK
, PPC860
, PPCNONE
, {RS
}},
5049 {"mtcounta", XSPR(31,467,150), XSPR_MASK
, PPC860
, PPCNONE
, {RS
}},
5050 {"mtcountb", XSPR(31,467,151), XSPR_MASK
, PPC860
, PPCNONE
, {RS
}},
5051 {"mtcmpe", XSPR(31,467,152), XSPR_MASK
, PPC860
, PPCNONE
, {RS
}},
5052 {"mtcmpf", XSPR(31,467,153), XSPR_MASK
, PPC860
, PPCNONE
, {RS
}},
5053 {"mtcmpg", XSPR(31,467,154), XSPR_MASK
, PPC860
, PPCNONE
, {RS
}},
5054 {"mtcmph", XSPR(31,467,155), XSPR_MASK
, PPC860
, PPCNONE
, {RS
}},
5055 {"mtlctrl1", XSPR(31,467,156), XSPR_MASK
, PPC860
, PPCNONE
, {RS
}},
5056 {"mtlctrl2", XSPR(31,467,157), XSPR_MASK
, PPC860
, PPCNONE
, {RS
}},
5057 {"mtictrl", XSPR(31,467,158), XSPR_MASK
, PPC860
, PPCNONE
, {RS
}},
5058 {"mtbar", XSPR(31,467,159), XSPR_MASK
, PPC860
, PPCNONE
, {RS
}},
5059 {"mtvrsave", XSPR(31,467,256), XSPR_MASK
, PPCVEC
, PPCNONE
, {RS
}},
5060 {"mtusprg0", XSPR(31,467,256), XSPR_MASK
, BOOKE
|PPCVLE
, PPCNONE
, {RS
}},
5061 {"mtsprg", XSPR(31,467,256), XSPRG_MASK
, PPC
|PPCVLE
, PPCNONE
, {SPRG
, RS
}},
5062 {"mtsprg0", XSPR(31,467,272), XSPR_MASK
, PPC
|PPCVLE
, PPCNONE
, {RS
}},
5063 {"mtsprg1", XSPR(31,467,273), XSPR_MASK
, PPC
|PPCVLE
, PPCNONE
, {RS
}},
5064 {"mtsprg2", XSPR(31,467,274), XSPR_MASK
, PPC
|PPCVLE
, PPCNONE
, {RS
}},
5065 {"mtsprg3", XSPR(31,467,275), XSPR_MASK
, PPC
|PPCVLE
, PPCNONE
, {RS
}},
5066 {"mtsprg4", XSPR(31,467,276), XSPR_MASK
, PPC405
|BOOKE
|PPCVLE
, PPCNONE
, {RS
}},
5067 {"mtsprg5", XSPR(31,467,277), XSPR_MASK
, PPC405
|BOOKE
|PPCVLE
, PPCNONE
, {RS
}},
5068 {"mtsprg6", XSPR(31,467,278), XSPR_MASK
, PPC405
|BOOKE
|PPCVLE
, PPCNONE
, {RS
}},
5069 {"mtsprg7", XSPR(31,467,279), XSPR_MASK
, PPC405
|BOOKE
|PPCVLE
, PPCNONE
, {RS
}},
5070 {"mtasr", XSPR(31,467,280), XSPR_MASK
, PPC64
, PPCNONE
, {RS
}},
5071 {"mtear", XSPR(31,467,282), XSPR_MASK
, PPC
, TITAN
, {RS
}},
5072 {"mttbl", XSPR(31,467,284), XSPR_MASK
, PPC
, PPCNONE
, {RS
}},
5073 {"mttbu", XSPR(31,467,285), XSPR_MASK
, PPC
, PPCNONE
, {RS
}},
5074 {"mtdbsr", XSPR(31,467,304), XSPR_MASK
, BOOKE
|PPCVLE
, PPCNONE
, {RS
}},
5075 {"mtdbcr0", XSPR(31,467,308), XSPR_MASK
, BOOKE
|PPCVLE
, PPCNONE
, {RS
}},
5076 {"mtdbcr1", XSPR(31,467,309), XSPR_MASK
, BOOKE
|PPCVLE
, PPCNONE
, {RS
}},
5077 {"mtdbcr2", XSPR(31,467,310), XSPR_MASK
, BOOKE
|PPCVLE
, PPCNONE
, {RS
}},
5078 {"mtiac1", XSPR(31,467,312), XSPR_MASK
, BOOKE
|PPCVLE
, PPCNONE
, {RS
}},
5079 {"mtiac2", XSPR(31,467,313), XSPR_MASK
, BOOKE
|PPCVLE
, PPCNONE
, {RS
}},
5080 {"mtiac3", XSPR(31,467,314), XSPR_MASK
, BOOKE
|PPCVLE
, PPCNONE
, {RS
}},
5081 {"mtiac4", XSPR(31,467,315), XSPR_MASK
, BOOKE
|PPCVLE
, PPCNONE
, {RS
}},
5082 {"mtdac1", XSPR(31,467,316), XSPR_MASK
, BOOKE
|PPCVLE
, PPCNONE
, {RS
}},
5083 {"mtdac2", XSPR(31,467,317), XSPR_MASK
, BOOKE
|PPCVLE
, PPCNONE
, {RS
}},
5084 {"mtdvc1", XSPR(31,467,318), XSPR_MASK
, BOOKE
|PPCVLE
, PPCNONE
, {RS
}},
5085 {"mtdvc2", XSPR(31,467,319), XSPR_MASK
, BOOKE
|PPCVLE
, PPCNONE
, {RS
}},
5086 {"mttsr", XSPR(31,467,336), XSPR_MASK
, BOOKE
|PPCVLE
, PPCNONE
, {RS
}},
5087 {"mttcr", XSPR(31,467,340), XSPR_MASK
, BOOKE
|PPCVLE
, PPCNONE
, {RS
}},
5088 {"mtivor0", XSPR(31,467,400), XSPR_MASK
, BOOKE
|PPCVLE
, PPCNONE
, {RS
}},
5089 {"mtivor1", XSPR(31,467,401), XSPR_MASK
, BOOKE
|PPCVLE
, PPCNONE
, {RS
}},
5090 {"mtivor2", XSPR(31,467,402), XSPR_MASK
, BOOKE
|PPCVLE
, PPCNONE
, {RS
}},
5091 {"mtivor3", XSPR(31,467,403), XSPR_MASK
, BOOKE
|PPCVLE
, PPCNONE
, {RS
}},
5092 {"mtivor4", XSPR(31,467,404), XSPR_MASK
, BOOKE
|PPCVLE
, PPCNONE
, {RS
}},
5093 {"mtivor5", XSPR(31,467,405), XSPR_MASK
, BOOKE
|PPCVLE
, PPCNONE
, {RS
}},
5094 {"mtivor6", XSPR(31,467,406), XSPR_MASK
, BOOKE
|PPCVLE
, PPCNONE
, {RS
}},
5095 {"mtivor7", XSPR(31,467,407), XSPR_MASK
, BOOKE
|PPCVLE
, PPCNONE
, {RS
}},
5096 {"mtivor8", XSPR(31,467,408), XSPR_MASK
, BOOKE
|PPCVLE
, PPCNONE
, {RS
}},
5097 {"mtivor9", XSPR(31,467,409), XSPR_MASK
, BOOKE
|PPCVLE
, PPCNONE
, {RS
}},
5098 {"mtivor10", XSPR(31,467,410), XSPR_MASK
, BOOKE
|PPCVLE
, PPCNONE
, {RS
}},
5099 {"mtivor11", XSPR(31,467,411), XSPR_MASK
, BOOKE
|PPCVLE
, PPCNONE
, {RS
}},
5100 {"mtivor12", XSPR(31,467,412), XSPR_MASK
, BOOKE
|PPCVLE
, PPCNONE
, {RS
}},
5101 {"mtivor13", XSPR(31,467,413), XSPR_MASK
, BOOKE
|PPCVLE
, PPCNONE
, {RS
}},
5102 {"mtivor14", XSPR(31,467,414), XSPR_MASK
, BOOKE
|PPCVLE
, PPCNONE
, {RS
}},
5103 {"mtivor15", XSPR(31,467,415), XSPR_MASK
, BOOKE
|PPCVLE
, PPCNONE
, {RS
}},
5104 {"mtspefscr", XSPR(31,467,512), XSPR_MASK
, PPCSPE
, PPCNONE
, {RS
}},
5105 {"mtbbear", XSPR(31,467,513), XSPR_MASK
, PPCBRLK
, PPCNONE
, {RS
}},
5106 {"mtbbtar", XSPR(31,467,514), XSPR_MASK
, PPCBRLK
, PPCNONE
, {RS
}},
5107 {"mtivor32", XSPR(31,467,528), XSPR_MASK
, PPCSPE
, PPCNONE
, {RS
}},
5108 {"mtibatu", XSPR(31,467,528), XSPRBAT_MASK
, PPC
, TITAN
, {SPRBAT
, RS
}},
5109 {"mtivor33", XSPR(31,467,529), XSPR_MASK
, PPCSPE
, PPCNONE
, {RS
}},
5110 {"mtibatl", XSPR(31,467,529), XSPRBAT_MASK
, PPC
, TITAN
, {SPRBAT
, RS
}},
5111 {"mtivor34", XSPR(31,467,530), XSPR_MASK
, PPCSPE
, PPCNONE
, {RS
}},
5112 {"mtivor35", XSPR(31,467,531), XSPR_MASK
, PPCPMR
, PPCNONE
, {RS
}},
5113 {"mtdbatu", XSPR(31,467,536), XSPRBAT_MASK
, PPC
, TITAN
, {SPRBAT
, RS
}},
5114 {"mtdbatl", XSPR(31,467,537), XSPRBAT_MASK
, PPC
, TITAN
, {SPRBAT
, RS
}},
5115 {"mtmcsrr0", XSPR(31,467,570), XSPR_MASK
, PPCRFMCI
|PPCVLE
, PPCNONE
, {RS
}},
5116 {"mtmcsrr1", XSPR(31,467,571), XSPR_MASK
, PPCRFMCI
|PPCVLE
, PPCNONE
, {RS
}},
5117 {"mtmcsr", XSPR(31,467,572), XSPR_MASK
, PPCRFMCI
, PPCNONE
, {RS
}},
5118 {"mtivndx", XSPR(31,467,880), XSPR_MASK
, TITAN
, PPCNONE
, {RS
}},
5119 {"mtdvndx", XSPR(31,467,881), XSPR_MASK
, TITAN
, PPCNONE
, {RS
}},
5120 {"mtivlim", XSPR(31,467,882), XSPR_MASK
, TITAN
, PPCNONE
, {RS
}},
5121 {"mtdvlim", XSPR(31,467,883), XSPR_MASK
, TITAN
, PPCNONE
, {RS
}},
5122 {"mtclcsr", XSPR(31,467,884), XSPR_MASK
, TITAN
, PPCNONE
, {RS
}},
5123 {"mtccr1", XSPR(31,467,888), XSPR_MASK
, TITAN
, PPCNONE
, {RS
}},
5124 {"mtummcr0", XSPR(31,467,936), XSPR_MASK
, PPC750
, PPCNONE
, {RS
}},
5125 {"mtupmc1", XSPR(31,467,937), XSPR_MASK
, PPC750
, PPCNONE
, {RS
}},
5126 {"mtupmc2", XSPR(31,467,938), XSPR_MASK
, PPC750
, PPCNONE
, {RS
}},
5127 {"mtusia", XSPR(31,467,939), XSPR_MASK
, PPC750
, PPCNONE
, {RS
}},
5128 {"mtummcr1", XSPR(31,467,940), XSPR_MASK
, PPC750
, PPCNONE
, {RS
}},
5129 {"mtupmc3", XSPR(31,467,941), XSPR_MASK
, PPC750
, PPCNONE
, {RS
}},
5130 {"mtupmc4", XSPR(31,467,942), XSPR_MASK
, PPC750
, PPCNONE
, {RS
}},
5131 {"mtzpr", XSPR(31,467,944), XSPR_MASK
, PPC403
, PPCNONE
, {RS
}},
5132 {"mtpid", XSPR(31,467,945), XSPR_MASK
, PPC403
, PPCNONE
, {RS
}},
5133 {"mtrmmucr", XSPR(31,467,946), XSPR_MASK
, TITAN
, PPCNONE
, {RS
}},
5134 {"mtccr0", XSPR(31,467,947), XSPR_MASK
, PPC405
|TITAN
, PPCNONE
, {RS
}},
5135 {"mtiac3", XSPR(31,467,948), XSPR_MASK
, PPC405
, PPCNONE
, {RS
}},
5136 {"mtiac4", XSPR(31,467,949), XSPR_MASK
, PPC405
, PPCNONE
, {RS
}},
5137 {"mtdvc1", XSPR(31,467,950), XSPR_MASK
, PPC405
, PPCNONE
, {RS
}},
5138 {"mtdvc2", XSPR(31,467,951), XSPR_MASK
, PPC405
, PPCNONE
, {RS
}},
5139 {"mtmmcr0", XSPR(31,467,952), XSPR_MASK
, PPC750
, PPCNONE
, {RS
}},
5140 {"mtpmc1", XSPR(31,467,953), XSPR_MASK
, PPC750
, PPCNONE
, {RS
}},
5141 {"mtsgr", XSPR(31,467,953), XSPR_MASK
, PPC403
, PPCNONE
, {RS
}},
5142 {"mtdcwr", XSPR(31,467,954), XSPR_MASK
, PPC403
, PPCNONE
, {RS
}},
5143 {"mtpmc2", XSPR(31,467,954), XSPR_MASK
, PPC750
, PPCNONE
, {RS
}},
5144 {"mtsia", XSPR(31,467,955), XSPR_MASK
, PPC750
, PPCNONE
, {RS
}},
5145 {"mtsler", XSPR(31,467,955), XSPR_MASK
, PPC405
, PPCNONE
, {RS
}},
5146 {"mtmmcr1", XSPR(31,467,956), XSPR_MASK
, PPC750
, PPCNONE
, {RS
}},
5147 {"mtsu0r", XSPR(31,467,956), XSPR_MASK
, PPC405
, PPCNONE
, {RS
}},
5148 {"mtdbcr1", XSPR(31,467,957), XSPR_MASK
, PPC405
, PPCNONE
, {RS
}},
5149 {"mtpmc3", XSPR(31,467,957), XSPR_MASK
, PPC750
, PPCNONE
, {RS
}},
5150 {"mtpmc4", XSPR(31,467,958), XSPR_MASK
, PPC750
, PPCNONE
, {RS
}},
5151 {"mticdbdr", XSPR(31,467,979), XSPR_MASK
, PPC403
, PPCNONE
, {RS
}},
5152 {"mtesr", XSPR(31,467,980), XSPR_MASK
, PPC403
, PPCNONE
, {RS
}},
5153 {"mtdear", XSPR(31,467,981), XSPR_MASK
, PPC403
, PPCNONE
, {RS
}},
5154 {"mtevpr", XSPR(31,467,982), XSPR_MASK
, PPC403
, PPCNONE
, {RS
}},
5155 {"mtcdbcr", XSPR(31,467,983), XSPR_MASK
, PPC403
, PPCNONE
, {RS
}},
5156 {"mttsr", XSPR(31,467,984), XSPR_MASK
, PPC403
, PPCNONE
, {RS
}},
5157 {"mttcr", XSPR(31,467,986), XSPR_MASK
, PPC403
, PPCNONE
, {RS
}},
5158 {"mtpit", XSPR(31,467,987), XSPR_MASK
, PPC403
, PPCNONE
, {RS
}},
5159 {"mttbhi", XSPR(31,467,988), XSPR_MASK
, PPC403
, PPCNONE
, {RS
}},
5160 {"mttblo", XSPR(31,467,989), XSPR_MASK
, PPC403
, PPCNONE
, {RS
}},
5161 {"mtsrr2", XSPR(31,467,990), XSPR_MASK
, PPC403
, PPCNONE
, {RS
}},
5162 {"mtsrr3", XSPR(31,467,991), XSPR_MASK
, PPC403
, PPCNONE
, {RS
}},
5163 {"mtdbsr", XSPR(31,467,1008), XSPR_MASK
, PPC403
, PPCNONE
, {RS
}},
5164 {"mtdbdr", XSPR(31,467,1011), XSPR_MASK
, TITAN
, PPCNONE
, {RS
}},
5165 {"mtdbcr0", XSPR(31,467,1010), XSPR_MASK
, PPC405
, PPCNONE
, {RS
}},
5166 {"mtiac1", XSPR(31,467,1012), XSPR_MASK
, PPC403
, PPCNONE
, {RS
}},
5167 {"mtiac2", XSPR(31,467,1013), XSPR_MASK
, PPC403
, PPCNONE
, {RS
}},
5168 {"mtdac1", XSPR(31,467,1014), XSPR_MASK
, PPC403
, PPCNONE
, {RS
}},
5169 {"mtdac2", XSPR(31,467,1015), XSPR_MASK
, PPC403
, PPCNONE
, {RS
}},
5170 {"mtl2cr", XSPR(31,467,1017), XSPR_MASK
, PPC750
, PPCNONE
, {RS
}},
5171 {"mtdccr", XSPR(31,467,1018), XSPR_MASK
, PPC403
, PPCNONE
, {RS
}},
5172 {"mticcr", XSPR(31,467,1019), XSPR_MASK
, PPC403
, PPCNONE
, {RS
}},
5173 {"mtictc", XSPR(31,467,1019), XSPR_MASK
, PPC750
, PPCNONE
, {RS
}},
5174 {"mtpbl1", XSPR(31,467,1020), XSPR_MASK
, PPC403
, PPCNONE
, {RS
}},
5175 {"mtthrm1", XSPR(31,467,1020), XSPR_MASK
, PPC750
, PPCNONE
, {RS
}},
5176 {"mtpbu1", XSPR(31,467,1021), XSPR_MASK
, PPC403
, PPCNONE
, {RS
}},
5177 {"mtthrm2", XSPR(31,467,1021), XSPR_MASK
, PPC750
, PPCNONE
, {RS
}},
5178 {"mtpbl2", XSPR(31,467,1022), XSPR_MASK
, PPC403
, PPCNONE
, {RS
}},
5179 {"mtthrm3", XSPR(31,467,1022), XSPR_MASK
, PPC750
, PPCNONE
, {RS
}},
5180 {"mtpbu2", XSPR(31,467,1023), XSPR_MASK
, PPC403
, PPCNONE
, {RS
}},
5181 {"mtspr", X(31,467), X_MASK
, COM
|PPCVLE
, PPCNONE
, {SPR
, RS
}},
5183 {"dcbi", X(31,470), XRT_MASK
, PPC
|PPCVLE
, PPCNONE
, {RA0
, RB
}},
5185 {"nand", XRC(31,476,0), X_MASK
, COM
|PPCVLE
, PPCNONE
, {RA
, RS
, RB
}},
5186 {"nand.", XRC(31,476,1), X_MASK
, COM
|PPCVLE
, PPCNONE
, {RA
, RS
, RB
}},
5188 {"dsn", X(31,483), XRT_MASK
, E500MC
|PPCVLE
, PPCNONE
, {RA
, RB
}},
5190 {"dcread", X(31,486), X_MASK
, PPC403
|PPC440
|PPCVLE
, PPCA2
|PPC476
, {RT
, RA0
, RB
}},
5192 {"icbtls", X(31,486), X_MASK
, PPCCHLK
|PPC476
|TITAN
|PPCVLE
, PPCNONE
, {CT
, RA0
, RB
}},
5194 {"stvxl", X(31,487), X_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VS
, RA0
, RB
}},
5196 {"nabs", XO(31,488,0,0), XORB_MASK
, M601
, PPCNONE
, {RT
, RA
}},
5197 {"nabs.", XO(31,488,0,1), XORB_MASK
, M601
, PPCNONE
, {RT
, RA
}},
5199 {"divd", XO(31,489,0,0), XO_MASK
, PPC64
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
5200 {"divd.", XO(31,489,0,1), XO_MASK
, PPC64
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
5202 {"divw", XO(31,491,0,0), XO_MASK
, PPC
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
5203 {"divw.", XO(31,491,0,1), XO_MASK
, PPC
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
5205 {"icbtlse", X(31,494), X_MASK
, PPCCHLK
, E500MC
, {CT
, RA
, RB
}},
5207 {"slbia", X(31,498), 0xffffffff, PPC64
, PPCNONE
, {0}},
5209 {"cli", X(31,502), XRB_MASK
, POWER
, PPCNONE
, {RT
, RA
}},
5211 {"popcntd", X(31,506), XRB_MASK
, POWER7
|PPCA2
, PPCNONE
, {RA
, RS
}},
5213 {"cmpb", X(31,508), X_MASK
, POWER6
|PPCA2
|PPC476
, PPCNONE
, {RA
, RS
, RB
}},
5215 {"mcrxr", X(31,512), XRARB_MASK
|(3<<21), COM
|PPCVLE
, POWER7
, {BF
}},
5217 {"lbdx", X(31,515), X_MASK
, E500MC
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
5219 {"bblels", X(31,518), X_MASK
, PPCBRLK
, PPCNONE
, {0}},
5221 {"lvlx", X(31,519), X_MASK
, CELL
, PPCNONE
, {VD
, RA0
, RB
}},
5222 {"lbfcmux", APU(31,519,0), APU_MASK
, PPC405
, PPCNONE
, {FCRT
, RA
, RB
}},
5224 {"subfco", XO(31,8,1,0), XO_MASK
, PPCCOM
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
5225 {"sfo", XO(31,8,1,0), XO_MASK
, PWRCOM
, PPCNONE
, {RT
, RA
, RB
}},
5226 {"subco", XO(31,8,1,0), XO_MASK
, PPCCOM
|PPCVLE
, PPCNONE
, {RT
, RB
, RA
}},
5227 {"subfco.", XO(31,8,1,1), XO_MASK
, PPCCOM
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
5228 {"sfo.", XO(31,8,1,1), XO_MASK
, PWRCOM
, PPCNONE
, {RT
, RA
, RB
}},
5229 {"subco.", XO(31,8,1,1), XO_MASK
, PPCCOM
|PPCVLE
, PPCNONE
, {RT
, RB
, RA
}},
5231 {"addco", XO(31,10,1,0), XO_MASK
, PPCCOM
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
5232 {"ao", XO(31,10,1,0), XO_MASK
, PWRCOM
, PPCNONE
, {RT
, RA
, RB
}},
5233 {"addco.", XO(31,10,1,1), XO_MASK
, PPCCOM
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
5234 {"ao.", XO(31,10,1,1), XO_MASK
, PWRCOM
, PPCNONE
, {RT
, RA
, RB
}},
5236 {"clcs", X(31,531), XRB_MASK
, M601
, PPCNONE
, {RT
, RA
}},
5238 {"ldbrx", X(31,532), X_MASK
, CELL
|POWER7
|PPCA2
, PPCNONE
, {RT
, RA0
, RB
}},
5240 {"lswx", X(31,533), X_MASK
, PPCCOM
|PPCVLE
, E500
|E500MC
, {RT
, RAX
, RBX
}},
5241 {"lsx", X(31,533), X_MASK
, PWRCOM
, PPCNONE
, {RT
, RA
, RB
}},
5243 {"lwbrx", X(31,534), X_MASK
, PPCCOM
|PPCVLE
, PPCNONE
, {RT
, RA0
, RB
}},
5244 {"lbrx", X(31,534), X_MASK
, PWRCOM
, PPCNONE
, {RT
, RA
, RB
}},
5246 {"lfsx", X(31,535), X_MASK
, COM
, PPCEFS
, {FRT
, RA0
, RB
}},
5248 {"srw", XRC(31,536,0), X_MASK
, PPCCOM
|PPCVLE
, PPCNONE
, {RA
, RS
, RB
}},
5249 {"sr", XRC(31,536,0), X_MASK
, PWRCOM
, PPCNONE
, {RA
, RS
, RB
}},
5250 {"srw.", XRC(31,536,1), X_MASK
, PPCCOM
|PPCVLE
, PPCNONE
, {RA
, RS
, RB
}},
5251 {"sr.", XRC(31,536,1), X_MASK
, PWRCOM
, PPCNONE
, {RA
, RS
, RB
}},
5253 {"rrib", XRC(31,537,0), X_MASK
, M601
, PPCNONE
, {RA
, RS
, RB
}},
5254 {"rrib.", XRC(31,537,1), X_MASK
, M601
, PPCNONE
, {RA
, RS
, RB
}},
5256 {"srd", XRC(31,539,0), X_MASK
, PPC64
, PPCNONE
, {RA
, RS
, RB
}},
5257 {"srd.", XRC(31,539,1), X_MASK
, PPC64
, PPCNONE
, {RA
, RS
, RB
}},
5259 {"maskir", XRC(31,541,0), X_MASK
, M601
, PPCNONE
, {RA
, RS
, RB
}},
5260 {"maskir.", XRC(31,541,1), X_MASK
, M601
, PPCNONE
, {RA
, RS
, RB
}},
5262 {"lhdx", X(31,547), X_MASK
, E500MC
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
5264 {"lvtrx", X(31,549), X_MASK
, PPCVEC2
, PPCNONE
, {VD
, RA0
, RB
}},
5266 {"bbelr", X(31,550), X_MASK
, PPCBRLK
, PPCNONE
, {0}},
5268 {"lvrx", X(31,551), X_MASK
, CELL
, PPCNONE
, {VD
, RA0
, RB
}},
5269 {"lhfcmux", APU(31,551,0), APU_MASK
, PPC405
, PPCNONE
, {FCRT
, RA
, RB
}},
5271 {"subfo", XO(31,40,1,0), XO_MASK
, PPC
, PPCNONE
, {RT
, RA
, RB
}},
5272 {"subo", XO(31,40,1,0), XO_MASK
, PPC
, PPCNONE
, {RT
, RB
, RA
}},
5273 {"subfo.", XO(31,40,1,1), XO_MASK
, PPC
, PPCNONE
, {RT
, RA
, RB
}},
5274 {"subo.", XO(31,40,1,1), XO_MASK
, PPC
, PPCNONE
, {RT
, RB
, RA
}},
5276 {"tlbsync", X(31,566), 0xffffffff, PPC
|PPCVLE
, PPCNONE
, {0}},
5278 {"lfsux", X(31,567), X_MASK
, COM
, PPCEFS
, {FRT
, RAS
, RB
}},
5280 {"lwdx", X(31,579), X_MASK
, E500MC
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
5282 {"lvtlx", X(31,581), X_MASK
, PPCVEC2
, PPCNONE
, {VD
, RA0
, RB
}},
5284 {"lwfcmux", APU(31,583,0), APU_MASK
, PPC405
, PPCNONE
, {FCRT
, RA
, RB
}},
5286 {"lxsdx", X(31,588), XX1_MASK
, PPCVSX
, PPCNONE
, {XT6
, RA0
, RB
}},
5288 {"mfsr", X(31,595), XRB_MASK
|(1<<20), COM
, NON32
, {RT
, SR
}},
5290 {"lswi", X(31,597), X_MASK
, PPCCOM
|PPCVLE
, E500
|E500MC
, {RT
, RAX
, NBI
}},
5291 {"lsi", X(31,597), X_MASK
, PWRCOM
, PPCNONE
, {RT
, RA0
, NB
}},
5293 {"lwsync", XSYNC(31,598,1), 0xffffffff, PPC
, E500
, {0}},
5294 {"ptesync", XSYNC(31,598,2), 0xffffffff, PPC64
, PPCNONE
, {0}},
5295 {"sync", X(31,598), XSYNCLE_MASK
,E6500
, PPCNONE
, {LS
, ESYNC
}},
5296 {"sync", X(31,598), XSYNC_MASK
, PPCCOM
|PPCVLE
, BOOKE
|PPC476
, {LS
}},
5297 {"msync", X(31,598), 0xffffffff, BOOKE
|PPCA2
|PPC476
, PPCNONE
, {0}},
5298 {"sync", X(31,598), 0xffffffff, BOOKE
|PPC476
, E6500
, {0}},
5299 {"lwsync", X(31,598), 0xffffffff, E500
, PPCNONE
, {0}},
5300 {"dcs", X(31,598), 0xffffffff, PWRCOM
, PPCNONE
, {0}},
5302 {"lfdx", X(31,599), X_MASK
, COM
, PPCEFS
, {FRT
, RA0
, RB
}},
5304 {"mffgpr", XRC(31,607,0), XRA_MASK
, POWER6
, POWER7
, {FRT
, RB
}},
5305 {"lfdepx", X(31,607), X_MASK
, E500MC
|PPCA2
|PPCVLE
, PPCNONE
, {FRT
, RA0
, RB
}},
5307 {"lddx", X(31,611), X_MASK
, E500MC
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
5309 {"lvswx", X(31,613), X_MASK
, PPCVEC2
, PPCNONE
, {VD
, RA0
, RB
}},
5311 {"lqfcmux", APU(31,615,0), APU_MASK
, PPC405
, PPCNONE
, {FCRT
, RA
, RB
}},
5313 {"nego", XO(31,104,1,0), XORB_MASK
, COM
|PPCVLE
, PPCNONE
, {RT
, RA
}},
5314 {"nego.", XO(31,104,1,1), XORB_MASK
, COM
|PPCVLE
, PPCNONE
, {RT
, RA
}},
5316 {"mulo", XO(31,107,1,0), XO_MASK
, M601
, PPCNONE
, {RT
, RA
, RB
}},
5317 {"mulo.", XO(31,107,1,1), XO_MASK
, M601
, PPCNONE
, {RT
, RA
, RB
}},
5319 {"mfsri", X(31,627), X_MASK
, M601
, PPCNONE
, {RT
, RA
, RB
}},
5321 {"dclst", X(31,630), XRB_MASK
, M601
, PPCNONE
, {RS
, RA
}},
5323 {"lfdux", X(31,631), X_MASK
, COM
, PPCEFS
, {FRT
, RAS
, RB
}},
5325 {"stbdx", X(31,643), X_MASK
, E500MC
, PPCNONE
, {RS
, RA
, RB
}},
5327 {"stvlx", X(31,647), X_MASK
, CELL
, PPCNONE
, {VS
, RA0
, RB
}},
5328 {"stbfcmux", APU(31,647,0), APU_MASK
, PPC405
, PPCNONE
, {FCRT
, RA
, RB
}},
5330 {"subfeo", XO(31,136,1,0), XO_MASK
, PPCCOM
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
5331 {"sfeo", XO(31,136,1,0), XO_MASK
, PWRCOM
, PPCNONE
, {RT
, RA
, RB
}},
5332 {"subfeo.", XO(31,136,1,1), XO_MASK
, PPCCOM
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
5333 {"sfeo.", XO(31,136,1,1), XO_MASK
, PWRCOM
, PPCNONE
, {RT
, RA
, RB
}},
5335 {"addeo", XO(31,138,1,0), XO_MASK
, PPCCOM
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
5336 {"aeo", XO(31,138,1,0), XO_MASK
, PWRCOM
, PPCNONE
, {RT
, RA
, RB
}},
5337 {"addeo.", XO(31,138,1,1), XO_MASK
, PPCCOM
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
5338 {"aeo.", XO(31,138,1,1), XO_MASK
, PWRCOM
, PPCNONE
, {RT
, RA
, RB
}},
5340 {"mfsrin", X(31,659), XRA_MASK
, PPC
, NON32
, {RT
, RB
}},
5342 {"stdbrx", X(31,660), X_MASK
, CELL
|POWER7
|PPCA2
, PPCNONE
, {RS
, RA0
, RB
}},
5344 {"stswx", X(31,661), X_MASK
, PPCCOM
|PPCVLE
, E500
|E500MC
, {RS
, RA0
, RB
}},
5345 {"stsx", X(31,661), X_MASK
, PWRCOM
, PPCNONE
, {RS
, RA0
, RB
}},
5347 {"stwbrx", X(31,662), X_MASK
, PPCCOM
|PPCVLE
, PPCNONE
, {RS
, RA0
, RB
}},
5348 {"stbrx", X(31,662), X_MASK
, PWRCOM
, PPCNONE
, {RS
, RA0
, RB
}},
5350 {"stfsx", X(31,663), X_MASK
, COM
, PPCEFS
, {FRS
, RA0
, RB
}},
5352 {"srq", XRC(31,664,0), X_MASK
, M601
, PPCNONE
, {RA
, RS
, RB
}},
5353 {"srq.", XRC(31,664,1), X_MASK
, M601
, PPCNONE
, {RA
, RS
, RB
}},
5355 {"sre", XRC(31,665,0), X_MASK
, M601
, PPCNONE
, {RA
, RS
, RB
}},
5356 {"sre.", XRC(31,665,1), X_MASK
, M601
, PPCNONE
, {RA
, RS
, RB
}},
5358 {"sthdx", X(31,675), X_MASK
, E500MC
, PPCNONE
, {RS
, RA
, RB
}},
5360 {"stvfrx", X(31,677), X_MASK
, PPCVEC2
, PPCNONE
, {VS
, RA0
, RB
}},
5362 {"stvrx", X(31,679), X_MASK
, CELL
, PPCNONE
, {VS
, RA0
, RB
}},
5363 {"sthfcmux", APU(31,679,0), APU_MASK
, PPC405
, PPCNONE
, {FCRT
, RA
, RB
}},
5365 {"stbcx.", XRC(31,694,1), X_MASK
, POWER7
, PPCNONE
, {RS
, RA0
, RB
}},
5367 {"stfsux", X(31,695), X_MASK
, COM
, PPCEFS
, {FRS
, RAS
, RB
}},
5369 {"sriq", XRC(31,696,0), X_MASK
, M601
, PPCNONE
, {RA
, RS
, SH
}},
5370 {"sriq.", XRC(31,696,1), X_MASK
, M601
, PPCNONE
, {RA
, RS
, SH
}},
5372 {"stwdx", X(31,707), X_MASK
, E500MC
, PPCNONE
, {RS
, RA
, RB
}},
5374 {"stvflx", X(31,709), X_MASK
, PPCVEC2
, PPCNONE
, {VS
, RA0
, RB
}},
5376 {"stwfcmux", APU(31,711,0), APU_MASK
, PPC405
, PPCNONE
, {FCRT
, RA
, RB
}},
5378 {"stxsdx", X(31,716), XX1_MASK
, PPCVSX
, PPCNONE
, {XS6
, RA0
, RB
}},
5380 {"subfzeo", XO(31,200,1,0), XORB_MASK
, PPCCOM
|PPCVLE
, PPCNONE
, {RT
, RA
}},
5381 {"sfzeo", XO(31,200,1,0), XORB_MASK
, PWRCOM
, PPCNONE
, {RT
, RA
}},
5382 {"subfzeo.", XO(31,200,1,1), XORB_MASK
, PPCCOM
|PPCVLE
, PPCNONE
, {RT
, RA
}},
5383 {"sfzeo.", XO(31,200,1,1), XORB_MASK
, PWRCOM
, PPCNONE
, {RT
, RA
}},
5385 {"addzeo", XO(31,202,1,0), XORB_MASK
, PPCCOM
|PPCVLE
, PPCNONE
, {RT
, RA
}},
5386 {"azeo", XO(31,202,1,0), XORB_MASK
, PWRCOM
, PPCNONE
, {RT
, RA
}},
5387 {"addzeo.", XO(31,202,1,1), XORB_MASK
, PPCCOM
|PPCVLE
, PPCNONE
, {RT
, RA
}},
5388 {"azeo.", XO(31,202,1,1), XORB_MASK
, PWRCOM
, PPCNONE
, {RT
, RA
}},
5390 {"stswi", X(31,725), X_MASK
, PPCCOM
|PPCVLE
, E500
|E500MC
, {RS
, RA0
, NB
}},
5391 {"stsi", X(31,725), X_MASK
, PWRCOM
, PPCNONE
, {RS
, RA0
, NB
}},
5393 {"sthcx.", XRC(31,726,1), X_MASK
, POWER7
, PPCNONE
, {RS
, RA0
, RB
}},
5395 {"stfdx", X(31,727), X_MASK
, COM
, PPCEFS
, {FRS
, RA0
, RB
}},
5397 {"srlq", XRC(31,728,0), X_MASK
, M601
, PPCNONE
, {RA
, RS
, RB
}},
5398 {"srlq.", XRC(31,728,1), X_MASK
, M601
, PPCNONE
, {RA
, RS
, RB
}},
5400 {"sreq", XRC(31,729,0), X_MASK
, M601
, PPCNONE
, {RA
, RS
, RB
}},
5401 {"sreq.", XRC(31,729,1), X_MASK
, M601
, PPCNONE
, {RA
, RS
, RB
}},
5403 {"mftgpr", XRC(31,735,0), XRA_MASK
, POWER6
, POWER7
, {RT
, FRB
}},
5404 {"stfdepx", X(31,735), X_MASK
, E500MC
|PPCA2
|PPCVLE
, PPCNONE
, {FRS
, RA0
, RB
}},
5406 {"stddx", X(31,739), X_MASK
, E500MC
, PPCNONE
, {RS
, RA
, RB
}},
5408 {"stvswx", X(31,741), X_MASK
, PPCVEC2
, PPCNONE
, {VS
, RA0
, RB
}},
5410 {"stqfcmux", APU(31,743,0), APU_MASK
, PPC405
, PPCNONE
, {FCRT
, RA
, RB
}},
5412 {"subfmeo", XO(31,232,1,0), XORB_MASK
, PPCCOM
, PPCNONE
, {RT
, RA
}},
5413 {"sfmeo", XO(31,232,1,0), XORB_MASK
, PWRCOM
, PPCNONE
, {RT
, RA
}},
5414 {"subfmeo.", XO(31,232,1,1), XORB_MASK
, PPCCOM
, PPCNONE
, {RT
, RA
}},
5415 {"sfmeo.", XO(31,232,1,1), XORB_MASK
, PWRCOM
, PPCNONE
, {RT
, RA
}},
5417 {"mulldo", XO(31,233,1,0), XO_MASK
, PPC64
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
5418 {"mulldo.", XO(31,233,1,1), XO_MASK
, PPC64
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
5420 {"addmeo", XO(31,234,1,0), XORB_MASK
, PPCCOM
|PPCVLE
, PPCNONE
, {RT
, RA
}},
5421 {"ameo", XO(31,234,1,0), XORB_MASK
, PWRCOM
, PPCNONE
, {RT
, RA
}},
5422 {"addmeo.", XO(31,234,1,1), XORB_MASK
, PPCCOM
|PPCVLE
, PPCNONE
, {RT
, RA
}},
5423 {"ameo.", XO(31,234,1,1), XORB_MASK
, PWRCOM
, PPCNONE
, {RT
, RA
}},
5425 {"mullwo", XO(31,235,1,0), XO_MASK
, PPCCOM
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
5426 {"mulso", XO(31,235,1,0), XO_MASK
, PWRCOM
, PPCNONE
, {RT
, RA
, RB
}},
5427 {"mullwo.", XO(31,235,1,1), XO_MASK
, PPCCOM
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
5428 {"mulso.", XO(31,235,1,1), XO_MASK
, PWRCOM
, PPCNONE
, {RT
, RA
, RB
}},
5430 {"dcba", X(31,758), XRT_MASK
, PPC405
|PPC7450
|BOOKE
|PPCA2
|PPC476
|PPCVLE
, PPCNONE
, {RA0
, RB
}},
5431 {"dcbal", XOPL(31,758,1), XRT_MASK
, E500MC
, PPCNONE
, {RA0
, RB
}},
5433 {"stfdux", X(31,759), X_MASK
, COM
, PPCEFS
, {FRS
, RAS
, RB
}},
5435 {"srliq", XRC(31,760,0), X_MASK
, M601
, PPCNONE
, {RA
, RS
, SH
}},
5436 {"srliq.", XRC(31,760,1), X_MASK
, M601
, PPCNONE
, {RA
, RS
, SH
}},
5438 {"lvsm", X(31,773), X_MASK
, PPCVEC2
, PPCNONE
, {VD
, RA0
, RB
}},
5439 {"stvepxl", X(31,775), X_MASK
, PPCVEC2
, PPCNONE
, {VS
, RA0
, RB
}},
5440 {"lvlxl", X(31,775), X_MASK
, CELL
, PPCNONE
, {VD
, RA0
, RB
}},
5441 {"ldfcmux", APU(31,775,0), APU_MASK
, PPC405
, PPCNONE
, {FCRT
, RA
, RB
}},
5443 {"dozo", XO(31,264,1,0), XO_MASK
, M601
, PPCNONE
, {RT
, RA
, RB
}},
5444 {"dozo.", XO(31,264,1,1), XO_MASK
, M601
, PPCNONE
, {RT
, RA
, RB
}},
5446 {"addo", XO(31,266,1,0), XO_MASK
, PPCCOM
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
5447 {"caxo", XO(31,266,1,0), XO_MASK
, PWRCOM
, PPCNONE
, {RT
, RA
, RB
}},
5448 {"addo.", XO(31,266,1,1), XO_MASK
, PPCCOM
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
5449 {"caxo.", XO(31,266,1,1), XO_MASK
, PWRCOM
, PPCNONE
, {RT
, RA
, RB
}},
5451 {"lxvw4x", X(31,780), XX1_MASK
, PPCVSX
, PPCNONE
, {XT6
, RA0
, RB
}},
5453 {"tlbivax", X(31,786), XRT_MASK
, BOOKE
|PPCA2
|PPC476
|PPCVLE
, PPCNONE
, {RA0
, RB
}},
5455 {"lwzcix", X(31,789), X_MASK
, POWER6
, PPCNONE
, {RT
, RA0
, RB
}},
5457 {"lhbrx", X(31,790), X_MASK
, COM
|PPCVLE
, PPCNONE
, {RT
, RA0
, RB
}},
5459 {"lfdpx", X(31,791), X_MASK
, POWER6
, POWER7
, {FRTp
, RA0
, RB
}},
5460 {"lfqx", X(31,791), X_MASK
, POWER2
, PPCNONE
, {FRT
, RA
, RB
}},
5462 {"sraw", XRC(31,792,0), X_MASK
, PPCCOM
|PPCVLE
, PPCNONE
, {RA
, RS
, RB
}},
5463 {"sra", XRC(31,792,0), X_MASK
, PWRCOM
, PPCNONE
, {RA
, RS
, RB
}},
5464 {"sraw.", XRC(31,792,1), X_MASK
, PPCCOM
|PPCVLE
, PPCNONE
, {RA
, RS
, RB
}},
5465 {"sra.", XRC(31,792,1), X_MASK
, PWRCOM
, PPCNONE
, {RA
, RS
, RB
}},
5467 {"srad", XRC(31,794,0), X_MASK
, PPC64
, PPCNONE
, {RA
, RS
, RB
}},
5468 {"srad.", XRC(31,794,1), X_MASK
, PPC64
, PPCNONE
, {RA
, RS
, RB
}},
5470 {"lfddx", X(31,803), X_MASK
, E500MC
|PPCVLE
, PPCNONE
, {FRT
, RA
, RB
}},
5472 {"lvtrxl", X(31,805), X_MASK
, PPCVEC2
, PPCNONE
, {VD
, RA0
, RB
}},
5473 {"stvepx", X(31,807), X_MASK
, PPCVEC2
, PPCNONE
, {VS
, RA0
, RB
}},
5474 {"lvrxl", X(31,807), X_MASK
, CELL
, PPCNONE
, {VD
, RA0
, RB
}},
5476 {"rac", X(31,818), X_MASK
, M601
, PPCNONE
, {RT
, RA
, RB
}},
5478 {"erativax", X(31,819), X_MASK
, PPCA2
, PPCNONE
, {RS
, RA0
, RB
}},
5480 {"lhzcix", X(31,821), X_MASK
, POWER6
, PPCNONE
, {RT
, RA0
, RB
}},
5482 {"dss", XDSS(31,822,0), XDSS_MASK
, PPCVEC
, PPCNONE
, {STRM
}},
5484 {"lfqux", X(31,823), X_MASK
, POWER2
, PPCNONE
, {FRT
, RA
, RB
}},
5486 {"srawi", XRC(31,824,0), X_MASK
, PPCCOM
|PPCVLE
, PPCNONE
, {RA
, RS
, SH
}},
5487 {"srai", XRC(31,824,0), X_MASK
, PWRCOM
, PPCNONE
, {RA
, RS
, SH
}},
5488 {"srawi.", XRC(31,824,1), X_MASK
, PPCCOM
|PPCVLE
, PPCNONE
, {RA
, RS
, SH
}},
5489 {"srai.", XRC(31,824,1), X_MASK
, PWRCOM
, PPCNONE
, {RA
, RS
, SH
}},
5491 {"sradi", XS(31,413,0), XS_MASK
, PPC64
|PPCVLE
, PPCNONE
, {RA
, RS
, SH6
}},
5492 {"sradi.", XS(31,413,1), XS_MASK
, PPC64
|PPCVLE
, PPCNONE
, {RA
, RS
, SH6
}},
5494 {"lvtlxl", X(31,837), X_MASK
, PPCVEC2
, PPCNONE
, {VD
, RA0
, RB
}},
5496 {"divo", XO(31,331,1,0), XO_MASK
, M601
, PPCNONE
, {RT
, RA
, RB
}},
5497 {"divo.", XO(31,331,1,1), XO_MASK
, M601
, PPCNONE
, {RT
, RA
, RB
}},
5499 {"lxvd2x", X(31,844), XX1_MASK
, PPCVSX
, PPCNONE
, {XT6
, RA0
, RB
}},
5501 {"tlbsrx.", XRC(31,850,1), XRT_MASK
, PPCA2
, PPCNONE
, {RA0
, RB
}},
5503 {"slbmfev", X(31,851), XRA_MASK
, PPC64
, PPCNONE
, {RT
, RB
}},
5505 {"lbzcix", X(31,853), X_MASK
, POWER6
, PPCNONE
, {RT
, RA0
, RB
}},
5507 {"eieio", X(31,854), 0xffffffff, PPC
, BOOKE
|PPCA2
|PPC476
, {0}},
5508 {"mbar", X(31,854), X_MASK
, BOOKE
|PPCA2
|PPC476
|PPCVLE
, PPCNONE
, {MO
}},
5509 {"eieio", XMBAR(31,854,1),0xffffffff, E500
, PPCNONE
, {0}},
5510 {"eieio", X(31,854), 0xffffffff, PPCA2
|PPC476
, PPCNONE
, {0}},
5512 {"lfiwax", X(31,855), X_MASK
, POWER6
|PPCA2
|PPC476
, PPCNONE
, {FRT
, RA0
, RB
}},
5514 {"lvswxl", X(31,869), X_MASK
, PPCVEC2
, PPCNONE
, {VD
, RA0
, RB
}},
5516 {"abso", XO(31,360,1,0), XORB_MASK
, M601
, PPCNONE
, {RT
, RA
}},
5517 {"abso.", XO(31,360,1,1), XORB_MASK
, M601
, PPCNONE
, {RT
, RA
}},
5519 {"divso", XO(31,363,1,0), XO_MASK
, M601
, PPCNONE
, {RT
, RA
, RB
}},
5520 {"divso.", XO(31,363,1,1), XO_MASK
, M601
, PPCNONE
, {RT
, RA
, RB
}},
5522 {"ldcix", X(31,885), X_MASK
, POWER6
, PPCNONE
, {RT
, RA0
, RB
}},
5524 {"lfiwzx", X(31,887), X_MASK
, POWER7
|PPCA2
, PPCNONE
, {FRT
, RA0
, RB
}},
5526 {"stvlxl", X(31,903), X_MASK
, CELL
, PPCNONE
, {VS
, RA0
, RB
}},
5527 {"stdfcmux", APU(31,903,0), APU_MASK
, PPC405
, PPCNONE
, {FCRT
, RA
, RB
}},
5529 {"divdeuo", XO(31,393,1,0), XO_MASK
, POWER7
|PPCA2
, PPCNONE
, {RT
, RA
, RB
}},
5530 {"divdeuo.", XO(31,393,1,1), XO_MASK
, POWER7
|PPCA2
, PPCNONE
, {RT
, RA
, RB
}},
5531 {"divweuo", XO(31,395,1,0), XO_MASK
, POWER7
|PPCA2
, PPCNONE
, {RT
, RA
, RB
}},
5532 {"divweuo.", XO(31,395,1,1), XO_MASK
, POWER7
|PPCA2
, PPCNONE
, {RT
, RA
, RB
}},
5534 {"stxvw4x", X(31,908), XX1_MASK
, PPCVSX
, PPCNONE
, {XS6
, RA0
, RB
}},
5536 {"tlbsx", XRC(31,914,0), X_MASK
, PPC403
|BOOKE
|PPCA2
|PPC476
, PPCNONE
, {RTO
, RA0
, RB
}},
5537 {"tlbsx.", XRC(31,914,1), X_MASK
, PPC403
|BOOKE
|PPCA2
|PPC476
, PPCNONE
, {RTO
, RA0
, RB
}},
5539 {"slbmfee", X(31,915), XRA_MASK
, PPC64
, PPCNONE
, {RT
, RB
}},
5541 {"stwcix", X(31,917), X_MASK
, POWER6
, PPCNONE
, {RS
, RA0
, RB
}},
5543 {"sthbrx", X(31,918), X_MASK
, COM
, PPCNONE
, {RS
, RA0
, RB
}},
5545 {"stfdpx", X(31,919), X_MASK
, POWER6
, POWER7
, {FRSp
, RA0
, RB
}},
5546 {"stfqx", X(31,919), X_MASK
, POWER2
, PPCNONE
, {FRS
, RA0
, RB
}},
5548 {"sraq", XRC(31,920,0), X_MASK
, M601
, PPCNONE
, {RA
, RS
, RB
}},
5549 {"sraq.", XRC(31,920,1), X_MASK
, M601
, PPCNONE
, {RA
, RS
, RB
}},
5551 {"srea", XRC(31,921,0), X_MASK
, M601
, PPCNONE
, {RA
, RS
, RB
}},
5552 {"srea.", XRC(31,921,1), X_MASK
, M601
, PPCNONE
, {RA
, RS
, RB
}},
5554 {"extsh", XRC(31,922,0), XRB_MASK
, PPCCOM
|PPCVLE
, PPCNONE
, {RA
, RS
}},
5555 {"exts", XRC(31,922,0), XRB_MASK
, PWRCOM
, PPCNONE
, {RA
, RS
}},
5556 {"extsh.", XRC(31,922,1), XRB_MASK
, PPCCOM
|PPCVLE
, PPCNONE
, {RA
, RS
}},
5557 {"exts.", XRC(31,922,1), XRB_MASK
, PWRCOM
, PPCNONE
, {RA
, RS
}},
5559 {"stfddx", X(31,931), X_MASK
, E500MC
, PPCNONE
, {FRS
, RA
, RB
}},
5561 {"stvfrxl", X(31,933), X_MASK
, PPCVEC2
, PPCNONE
, {VS
, RA0
, RB
}},
5563 {"wclrone", XOPL2(31,934,2),XRT_MASK
, PPCA2
, PPCNONE
, {RA0
, RB
}},
5564 {"wclrall", X(31,934), XRARB_MASK
, PPCA2
, PPCNONE
, {L
}},
5565 {"wclr", X(31,934), X_MASK
, PPCA2
, PPCNONE
, {L
, RA0
, RB
}},
5567 {"stvrxl", X(31,935), X_MASK
, CELL
, PPCNONE
, {VS
, RA0
, RB
}},
5569 {"divdeo", XO(31,425,1,0), XO_MASK
, POWER7
|PPCA2
, PPCNONE
, {RT
, RA
, RB
}},
5570 {"divdeo.", XO(31,425,1,1), XO_MASK
, POWER7
|PPCA2
, PPCNONE
, {RT
, RA
, RB
}},
5571 {"divweo", XO(31,427,1,0), XO_MASK
, POWER7
|PPCA2
, PPCNONE
, {RT
, RA
, RB
}},
5572 {"divweo.", XO(31,427,1,1), XO_MASK
, POWER7
|PPCA2
, PPCNONE
, {RT
, RA
, RB
}},
5574 {"tlbrehi", XTLB(31,946,0), XTLB_MASK
, PPC403
, PPCA2
, {RT
, RA
}},
5575 {"tlbrelo", XTLB(31,946,1), XTLB_MASK
, PPC403
, PPCA2
, {RT
, RA
}},
5576 {"tlbre", X(31,946), X_MASK
, PPC403
|BOOKE
|PPCA2
|PPC476
, PPCNONE
, {RSO
, RAOPT
, SHO
}},
5578 {"sthcix", X(31,949), X_MASK
, POWER6
, PPCNONE
, {RS
, RA0
, RB
}},
5580 {"icswepx", XRC(31,950,0), X_MASK
, PPCA2
, PPCNONE
, {RS
, RA
, RB
}},
5581 {"icswepx.", XRC(31,950,1), X_MASK
, PPCA2
, PPCNONE
, {RS
, RA
, RB
}},
5583 {"stfqux", X(31,951), X_MASK
, POWER2
, PPCNONE
, {FRS
, RA
, RB
}},
5585 {"sraiq", XRC(31,952,0), X_MASK
, M601
, PPCNONE
, {RA
, RS
, SH
}},
5586 {"sraiq.", XRC(31,952,1), X_MASK
, M601
, PPCNONE
, {RA
, RS
, SH
}},
5588 {"extsb", XRC(31,954,0), XRB_MASK
, PPC
|PPCVLE
, PPCNONE
, {RA
, RS
}},
5589 {"extsb.", XRC(31,954,1), XRB_MASK
, PPC
|PPCVLE
, PPCNONE
, {RA
, RS
}},
5591 {"stvflxl", X(31,965), X_MASK
, PPCVEC2
, PPCNONE
, {VS
, RA0
, RB
}},
5593 {"iccci", X(31,966), XRT_MASK
, PPC403
|PPC440
|TITAN
|PPCA2
, PPCNONE
, {RAOPT
, RBOPT
}},
5594 {"ici", X(31,966), XRARB_MASK
, PPCA2
|PPC476
|PPCVLE
, PPCNONE
, {CT
}},
5596 {"divduo", XO(31,457,1,0), XO_MASK
, PPC64
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
5597 {"divduo.", XO(31,457,1,1), XO_MASK
, PPC64
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
5599 {"divwuo", XO(31,459,1,0), XO_MASK
, PPC
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
5600 {"divwuo.", XO(31,459,1,1), XO_MASK
, PPC
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
5602 {"stxvd2x", X(31,972), XX1_MASK
, PPCVSX
, PPCNONE
, {XS6
, RA0
, RB
}},
5604 {"tlbld", X(31,978), XRTRA_MASK
, PPC
, PPC403
|BOOKE
|PPCA2
|PPC476
, {RB
}},
5605 {"tlbwehi", XTLB(31,978,0), XTLB_MASK
, PPC403
, PPCNONE
, {RT
, RA
}},
5606 {"tlbwelo", XTLB(31,978,1), XTLB_MASK
, PPC403
, PPCNONE
, {RT
, RA
}},
5607 {"tlbwe", X(31,978), X_MASK
, PPC403
|BOOKE
|PPCA2
|PPC476
, PPCNONE
, {RSO
, RAOPT
, SHO
}},
5609 {"stbcix", X(31,981), X_MASK
, POWER6
, PPCNONE
, {RS
, RA0
, RB
}},
5611 {"icbi", X(31,982), XRT_MASK
, PPC
|PPCVLE
, PPCNONE
, {RA0
, RB
}},
5613 {"stfiwx", X(31,983), X_MASK
, PPC
, PPCEFS
, {FRS
, RA0
, RB
}},
5615 {"extsw", XRC(31,986,0), XRB_MASK
, PPC64
|PPCVLE
, PPCNONE
, {RA
, RS
}},
5616 {"extsw.", XRC(31,986,1), XRB_MASK
, PPC64
|PPCVLE
, PPCNONE
, {RA
, RS
}},
5618 {"icbiep", XRT(31,991,0), XRT_MASK
, E500MC
|PPCA2
|PPCVLE
, PPCNONE
, {RA0
, RB
}},
5620 {"stvswxl", X(31,997), X_MASK
, PPCVEC2
, PPCNONE
, {VS
, RA0
, RB
}},
5622 {"icread", X(31,998), XRT_MASK
, PPC403
|PPC440
|PPC476
|TITAN
|PPCVLE
, PPCNONE
, {RA0
, RB
}},
5624 {"nabso", XO(31,488,1,0), XORB_MASK
, M601
, PPCNONE
, {RT
, RA
}},
5625 {"nabso.", XO(31,488,1,1), XORB_MASK
, M601
, PPCNONE
, {RT
, RA
}},
5627 {"divdo", XO(31,489,1,0), XO_MASK
, PPC64
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
5628 {"divdo.", XO(31,489,1,1), XO_MASK
, PPC64
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
5630 {"divwo", XO(31,491,1,0), XO_MASK
, PPC
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
5631 {"divwo.", XO(31,491,1,1), XO_MASK
, PPC
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
5634 {"tlbli", X(31,1010), XRTRA_MASK
, PPC
, TITAN
, {RB
}},
5636 {"stdcix", X(31,1013), X_MASK
, POWER6
, PPCNONE
, {RS
, RA0
, RB
}},
5638 {"dcbz", X(31,1014), XRT_MASK
, PPC
|PPCVLE
, PPCNONE
, {RA0
, RB
}},
5639 {"dclz", X(31,1014), XRT_MASK
, PPC
, PPCNONE
, {RA0
, RB
}},
5641 {"dcbzep", XRT(31,1023,0), XRT_MASK
, E500MC
|PPCA2
|PPCVLE
, PPCNONE
, {RA0
, RB
}},
5643 {"dcbzl", XOPL(31,1014,1), XRT_MASK
, POWER4
|E500MC
, PPC476
, {RA0
, RB
}},
5645 {"cctpl", 0x7c210b78, 0xffffffff, CELL
, PPCNONE
, {0}},
5646 {"cctpm", 0x7c421378, 0xffffffff, CELL
, PPCNONE
, {0}},
5647 {"cctph", 0x7c631b78, 0xffffffff, CELL
, PPCNONE
, {0}},
5649 {"dstt", XDSS(31,342,1), XDSS_MASK
, PPCVEC
, PPCNONE
, {RA
, RB
, STRM
}},
5650 {"dststt", XDSS(31,374,1), XDSS_MASK
, PPCVEC
, PPCNONE
, {RA
, RB
, STRM
}},
5651 {"dssall", XDSS(31,822,1), XDSS_MASK
, PPCVEC
, PPCNONE
, {0}},
5653 {"db8cyc", 0x7f9ce378, 0xffffffff, CELL
, PPCNONE
, {0}},
5654 {"db10cyc", 0x7fbdeb78, 0xffffffff, CELL
, PPCNONE
, {0}},
5655 {"db12cyc", 0x7fdef378, 0xffffffff, CELL
, PPCNONE
, {0}},
5656 {"db16cyc", 0x7ffffb78, 0xffffffff, CELL
, PPCNONE
, {0}},
5658 {"lwz", OP(32), OP_MASK
, PPCCOM
, PPCNONE
, {RT
, D
, RA0
}},
5659 {"l", OP(32), OP_MASK
, PWRCOM
, PPCNONE
, {RT
, D
, RA0
}},
5661 {"lwzu", OP(33), OP_MASK
, PPCCOM
, PPCNONE
, {RT
, D
, RAL
}},
5662 {"lu", OP(33), OP_MASK
, PWRCOM
, PPCNONE
, {RT
, D
, RA0
}},
5664 {"lbz", OP(34), OP_MASK
, COM
, PPCNONE
, {RT
, D
, RA0
}},
5666 {"lbzu", OP(35), OP_MASK
, COM
, PPCNONE
, {RT
, D
, RAL
}},
5668 {"stw", OP(36), OP_MASK
, PPCCOM
, PPCNONE
, {RS
, D
, RA0
}},
5669 {"st", OP(36), OP_MASK
, PWRCOM
, PPCNONE
, {RS
, D
, RA0
}},
5671 {"stwu", OP(37), OP_MASK
, PPCCOM
, PPCNONE
, {RS
, D
, RAS
}},
5672 {"stu", OP(37), OP_MASK
, PWRCOM
, PPCNONE
, {RS
, D
, RA0
}},
5674 {"stb", OP(38), OP_MASK
, COM
, PPCNONE
, {RS
, D
, RA0
}},
5676 {"stbu", OP(39), OP_MASK
, COM
, PPCNONE
, {RS
, D
, RAS
}},
5678 {"lhz", OP(40), OP_MASK
, COM
, PPCNONE
, {RT
, D
, RA0
}},
5680 {"lhzu", OP(41), OP_MASK
, COM
, PPCNONE
, {RT
, D
, RAL
}},
5682 {"lha", OP(42), OP_MASK
, COM
, PPCNONE
, {RT
, D
, RA0
}},
5684 {"lhau", OP(43), OP_MASK
, COM
, PPCNONE
, {RT
, D
, RAL
}},
5686 {"sth", OP(44), OP_MASK
, COM
, PPCNONE
, {RS
, D
, RA0
}},
5688 {"sthu", OP(45), OP_MASK
, COM
, PPCNONE
, {RS
, D
, RAS
}},
5690 {"lmw", OP(46), OP_MASK
, PPCCOM
, PPCNONE
, {RT
, D
, RAM
}},
5691 {"lm", OP(46), OP_MASK
, PWRCOM
, PPCNONE
, {RT
, D
, RA0
}},
5693 {"stmw", OP(47), OP_MASK
, PPCCOM
, PPCNONE
, {RS
, D
, RA0
}},
5694 {"stm", OP(47), OP_MASK
, PWRCOM
, PPCNONE
, {RS
, D
, RA0
}},
5696 {"lfs", OP(48), OP_MASK
, COM
, PPCEFS
, {FRT
, D
, RA0
}},
5698 {"lfsu", OP(49), OP_MASK
, COM
, PPCEFS
, {FRT
, D
, RAS
}},
5700 {"lfd", OP(50), OP_MASK
, COM
, PPCEFS
, {FRT
, D
, RA0
}},
5702 {"lfdu", OP(51), OP_MASK
, COM
, PPCEFS
, {FRT
, D
, RAS
}},
5704 {"stfs", OP(52), OP_MASK
, COM
, PPCEFS
, {FRS
, D
, RA0
}},
5706 {"stfsu", OP(53), OP_MASK
, COM
, PPCEFS
, {FRS
, D
, RAS
}},
5708 {"stfd", OP(54), OP_MASK
, COM
, PPCEFS
, {FRS
, D
, RA0
}},
5710 {"stfdu", OP(55), OP_MASK
, COM
, PPCEFS
, {FRS
, D
, RAS
}},
5712 {"lq", OP(56), OP_MASK
, POWER4
, PPC476
, {RTQ
, DQ
, RAQ
}},
5713 {"psq_l", OP(56), OP_MASK
, PPCPS
, PPCNONE
, {FRT
,PSD
,RA
,PSW
,PSQ
}},
5714 {"lfq", OP(56), OP_MASK
, POWER2
, PPCNONE
, {FRT
, D
, RA0
}},
5716 {"lfdp", OP(57), OP_MASK
, POWER6
, POWER7
, {FRTp
, D
, RA0
}},
5717 {"psq_lu", OP(57), OP_MASK
, PPCPS
, PPCNONE
, {FRT
,PSD
,RA
,PSW
,PSQ
}},
5718 {"lfqu", OP(57), OP_MASK
, POWER2
, PPCNONE
, {FRT
, D
, RA0
}},
5720 {"ld", DSO(58,0), DS_MASK
, PPC64
, PPCNONE
, {RT
, DS
, RA0
}},
5721 {"ldu", DSO(58,1), DS_MASK
, PPC64
, PPCNONE
, {RT
, DS
, RAL
}},
5722 {"lwa", DSO(58,2), DS_MASK
, PPC64
, PPCNONE
, {RT
, DS
, RA0
}},
5724 {"dadd", XRC(59,2,0), X_MASK
, POWER6
, PPCNONE
, {FRT
, FRA
, FRB
}},
5725 {"dadd.", XRC(59,2,1), X_MASK
, POWER6
, PPCNONE
, {FRT
, FRA
, FRB
}},
5727 {"dqua", ZRC(59,3,0), Z2_MASK
, POWER6
, PPCNONE
, {FRT
,FRA
,FRB
,RMC
}},
5728 {"dqua.", ZRC(59,3,1), Z2_MASK
, POWER6
, PPCNONE
, {FRT
,FRA
,FRB
,RMC
}},
5730 {"fdivs", A(59,18,0), AFRC_MASK
, PPC
, PPCEFS
, {FRT
, FRA
, FRB
}},
5731 {"fdivs.", A(59,18,1), AFRC_MASK
, PPC
, PPCEFS
, {FRT
, FRA
, FRB
}},
5733 {"fsubs", A(59,20,0), AFRC_MASK
, PPC
, PPCEFS
, {FRT
, FRA
, FRB
}},
5734 {"fsubs.", A(59,20,1), AFRC_MASK
, PPC
, PPCEFS
, {FRT
, FRA
, FRB
}},
5736 {"fadds", A(59,21,0), AFRC_MASK
, PPC
, PPCEFS
, {FRT
, FRA
, FRB
}},
5737 {"fadds.", A(59,21,1), AFRC_MASK
, PPC
, PPCEFS
, {FRT
, FRA
, FRB
}},
5739 {"fsqrts", A(59,22,0), AFRAFRC_MASK
, PPC
, TITAN
, {FRT
, FRB
}},
5740 {"fsqrts.", A(59,22,1), AFRAFRC_MASK
, PPC
, TITAN
, {FRT
, FRB
}},
5742 {"fres", A(59,24,0), AFRAFRC_MASK
, POWER7
, PPCNONE
, {FRT
, FRB
}},
5743 {"fres", A(59,24,0), AFRALFRC_MASK
, PPC
, POWER7
, {FRT
, FRB
, A_L
}},
5744 {"fres.", A(59,24,1), AFRAFRC_MASK
, POWER7
, PPCNONE
, {FRT
, FRB
}},
5745 {"fres.", A(59,24,1), AFRALFRC_MASK
, PPC
, POWER7
, {FRT
, FRB
, A_L
}},
5747 {"fmuls", A(59,25,0), AFRB_MASK
, PPC
, PPCEFS
, {FRT
, FRA
, FRC
}},
5748 {"fmuls.", A(59,25,1), AFRB_MASK
, PPC
, PPCEFS
, {FRT
, FRA
, FRC
}},
5750 {"frsqrtes", A(59,26,0), AFRAFRC_MASK
, POWER7
, PPCNONE
, {FRT
, FRB
}},
5751 {"frsqrtes", A(59,26,0), AFRALFRC_MASK
, POWER5
, POWER7
, {FRT
, FRB
, A_L
}},
5752 {"frsqrtes.", A(59,26,1), AFRAFRC_MASK
, POWER7
, PPCNONE
, {FRT
, FRB
}},
5753 {"frsqrtes.", A(59,26,1), AFRALFRC_MASK
, POWER5
, POWER7
, {FRT
, FRB
, A_L
}},
5755 {"fmsubs", A(59,28,0), A_MASK
, PPC
, PPCEFS
, {FRT
, FRA
, FRC
, FRB
}},
5756 {"fmsubs.", A(59,28,1), A_MASK
, PPC
, PPCEFS
, {FRT
, FRA
, FRC
, FRB
}},
5758 {"fmadds", A(59,29,0), A_MASK
, PPC
, PPCEFS
, {FRT
, FRA
, FRC
, FRB
}},
5759 {"fmadds.", A(59,29,1), A_MASK
, PPC
, PPCEFS
, {FRT
, FRA
, FRC
, FRB
}},
5761 {"fnmsubs", A(59,30,0), A_MASK
, PPC
, PPCEFS
, {FRT
, FRA
, FRC
, FRB
}},
5762 {"fnmsubs.", A(59,30,1), A_MASK
, PPC
, PPCEFS
, {FRT
, FRA
, FRC
, FRB
}},
5764 {"fnmadds", A(59,31,0), A_MASK
, PPC
, PPCEFS
, {FRT
, FRA
, FRC
, FRB
}},
5765 {"fnmadds.", A(59,31,1), A_MASK
, PPC
, PPCEFS
, {FRT
, FRA
, FRC
, FRB
}},
5767 {"dmul", XRC(59,34,0), X_MASK
, POWER6
, PPCNONE
, {FRT
, FRA
, FRB
}},
5768 {"dmul.", XRC(59,34,1), X_MASK
, POWER6
, PPCNONE
, {FRT
, FRA
, FRB
}},
5770 {"drrnd", ZRC(59,35,0), Z2_MASK
, POWER6
, PPCNONE
, {FRT
, FRA
, FRB
, RMC
}},
5771 {"drrnd.", ZRC(59,35,1), Z2_MASK
, POWER6
, PPCNONE
, {FRT
, FRA
, FRB
, RMC
}},
5773 {"dscli", ZRC(59,66,0), Z_MASK
, POWER6
, PPCNONE
, {FRT
, FRA
, SH16
}},
5774 {"dscli.", ZRC(59,66,1), Z_MASK
, POWER6
, PPCNONE
, {FRT
, FRA
, SH16
}},
5776 {"dquai", ZRC(59,67,0), Z2_MASK
, POWER6
, PPCNONE
, {TE
, FRT
,FRB
,RMC
}},
5777 {"dquai.", ZRC(59,67,1), Z2_MASK
, POWER6
, PPCNONE
, {TE
, FRT
,FRB
,RMC
}},
5779 {"dscri", ZRC(59,98,0), Z_MASK
, POWER6
, PPCNONE
, {FRT
, FRA
, SH16
}},
5780 {"dscri.", ZRC(59,98,1), Z_MASK
, POWER6
, PPCNONE
, {FRT
, FRA
, SH16
}},
5782 {"drintx", ZRC(59,99,0), Z2_MASK
, POWER6
, PPCNONE
, {R
, FRT
, FRB
, RMC
}},
5783 {"drintx.", ZRC(59,99,1), Z2_MASK
, POWER6
, PPCNONE
, {R
, FRT
, FRB
, RMC
}},
5785 {"dcmpo", X(59,130), X_MASK
, POWER6
, PPCNONE
, {BF
, FRA
, FRB
}},
5787 {"dtstex", X(59,162), X_MASK
, POWER6
, PPCNONE
, {BF
, FRA
, FRB
}},
5788 {"dtstdc", Z(59,194), Z_MASK
, POWER6
, PPCNONE
, {BF
, FRA
, DCM
}},
5789 {"dtstdg", Z(59,226), Z_MASK
, POWER6
, PPCNONE
, {BF
, FRA
, DGM
}},
5791 {"drintn", ZRC(59,227,0), Z2_MASK
, POWER6
, PPCNONE
, {R
, FRT
, FRB
, RMC
}},
5792 {"drintn.", ZRC(59,227,1), Z2_MASK
, POWER6
, PPCNONE
, {R
, FRT
, FRB
, RMC
}},
5794 {"dctdp", XRC(59,258,0), X_MASK
, POWER6
, PPCNONE
, {FRT
, FRB
}},
5795 {"dctdp.", XRC(59,258,1), X_MASK
, POWER6
, PPCNONE
, {FRT
, FRB
}},
5797 {"dctfix", XRC(59,290,0), X_MASK
, POWER6
, PPCNONE
, {FRT
, FRB
}},
5798 {"dctfix.", XRC(59,290,1), X_MASK
, POWER6
, PPCNONE
, {FRT
, FRB
}},
5800 {"ddedpd", XRC(59,322,0), X_MASK
, POWER6
, PPCNONE
, {SP
, FRT
, FRB
}},
5801 {"ddedpd.", XRC(59,322,1), X_MASK
, POWER6
, PPCNONE
, {SP
, FRT
, FRB
}},
5803 {"dxex", XRC(59,354,0), X_MASK
, POWER6
, PPCNONE
, {FRT
, FRB
}},
5804 {"dxex.", XRC(59,354,1), X_MASK
, POWER6
, PPCNONE
, {FRT
, FRB
}},
5806 {"dsub", XRC(59,514,0), X_MASK
, POWER6
, PPCNONE
, {FRT
, FRA
, FRB
}},
5807 {"dsub.", XRC(59,514,1), X_MASK
, POWER6
, PPCNONE
, {FRT
, FRA
, FRB
}},
5809 {"ddiv", XRC(59,546,0), X_MASK
, POWER6
, PPCNONE
, {FRT
, FRA
, FRB
}},
5810 {"ddiv.", XRC(59,546,1), X_MASK
, POWER6
, PPCNONE
, {FRT
, FRA
, FRB
}},
5812 {"dcmpu", X(59,642), X_MASK
, POWER6
, PPCNONE
, {BF
, FRA
, FRB
}},
5814 {"dtstsf", X(59,674), X_MASK
, POWER6
, PPCNONE
, {BF
, FRA
, FRB
}},
5816 {"drsp", XRC(59,770,0), X_MASK
, POWER6
, PPCNONE
, {FRT
, FRB
}},
5817 {"drsp.", XRC(59,770,1), X_MASK
, POWER6
, PPCNONE
, {FRT
, FRB
}},
5819 {"dcffix", XRC(59,802,0), X_MASK
|FRA_MASK
, POWER7
, PPCNONE
, {FRT
, FRB
}},
5820 {"dcffix.", XRC(59,802,1), X_MASK
|FRA_MASK
, POWER7
, PPCNONE
, {FRT
, FRB
}},
5822 {"denbcd", XRC(59,834,0), X_MASK
, POWER6
, PPCNONE
, {S
, FRT
, FRB
}},
5823 {"denbcd.", XRC(59,834,1), X_MASK
, POWER6
, PPCNONE
, {S
, FRT
, FRB
}},
5825 {"fcfids", XRC(59,846,0), XRA_MASK
, POWER7
|PPCA2
, PPCNONE
, {FRT
, FRB
}},
5826 {"fcfids.", XRC(59,846,1), XRA_MASK
, POWER7
|PPCA2
, PPCNONE
, {FRT
, FRB
}},
5828 {"diex", XRC(59,866,0), X_MASK
, POWER6
, PPCNONE
, {FRT
, FRA
, FRB
}},
5829 {"diex.", XRC(59,866,1), X_MASK
, POWER6
, PPCNONE
, {FRT
, FRA
, FRB
}},
5831 {"fcfidus", XRC(59,974,0), XRA_MASK
, POWER7
|PPCA2
, PPCNONE
, {FRT
, FRB
}},
5832 {"fcfidus.", XRC(59,974,1), XRA_MASK
, POWER7
|PPCA2
, PPCNONE
, {FRT
, FRB
}},
5834 {"xxsldwi", XX3(60,2), XX3SHW_MASK
, PPCVSX
, PPCNONE
, {XT6
, XA6
, XB6
, SHW
}},
5835 {"xxsel", XX4(60,3), XX4_MASK
, PPCVSX
, PPCNONE
, {XT6
, XA6
, XB6
, XC6
}},
5836 {"xxspltd", XX3(60,10), XX3DM_MASK
, PPCVSX
, PPCNONE
, {XT6
, XA6
, XB6S
, DMEX
}},
5837 {"xxmrghd", XX3(60,10), XX3_MASK
, PPCVSX
, PPCNONE
, {XT6
, XA6
, XB6
}},
5838 {"xxswapd", XX3(60,10)|(2<<8), XX3_MASK
, PPCVSX
, PPCNONE
, {XT6
, XA6
, XB6S
}},
5839 {"xxmrgld", XX3(60,10)|(3<<8), XX3_MASK
, PPCVSX
, PPCNONE
, {XT6
, XA6
, XB6
}},
5840 {"xxpermdi", XX3(60,10), XX3DM_MASK
, PPCVSX
, PPCNONE
, {XT6
, XA6
, XB6
, DM
}},
5841 {"xxmrghw", XX3(60,18), XX3_MASK
, PPCVSX
, PPCNONE
, {XT6
, XA6
, XB6
}},
5842 {"xsadddp", XX3(60,32), XX3_MASK
, PPCVSX
, PPCNONE
, {XT6
, XA6
, XB6
}},
5843 {"xsmaddadp", XX3(60,33), XX3_MASK
, PPCVSX
, PPCNONE
, {XT6
, XA6
, XB6
}},
5844 {"xscmpudp", XX3(60,35), XX3BF_MASK
, PPCVSX
, PPCNONE
, {BF
, XA6
, XB6
}},
5845 {"xssubdp", XX3(60,40), XX3_MASK
, PPCVSX
, PPCNONE
, {XT6
, XA6
, XB6
}},
5846 {"xsmaddmdp", XX3(60,41), XX3_MASK
, PPCVSX
, PPCNONE
, {XT6
, XA6
, XB6
}},
5847 {"xscmpodp", XX3(60,43), XX3BF_MASK
, PPCVSX
, PPCNONE
, {BF
, XA6
, XB6
}},
5848 {"xsmuldp", XX3(60,48), XX3_MASK
, PPCVSX
, PPCNONE
, {XT6
, XA6
, XB6
}},
5849 {"xsmsubadp", XX3(60,49), XX3_MASK
, PPCVSX
, PPCNONE
, {XT6
, XA6
, XB6
}},
5850 {"xxmrglw", XX3(60,50), XX3_MASK
, PPCVSX
, PPCNONE
, {XT6
, XA6
, XB6
}},
5851 {"xsdivdp", XX3(60,56), XX3_MASK
, PPCVSX
, PPCNONE
, {XT6
, XA6
, XB6
}},
5852 {"xsmsubmdp", XX3(60,57), XX3_MASK
, PPCVSX
, PPCNONE
, {XT6
, XA6
, XB6
}},
5853 {"xstdivdp", XX3(60,61), XX3BF_MASK
, PPCVSX
, PPCNONE
, {BF
, XA6
, XB6
}},
5854 {"xvaddsp", XX3(60,64), XX3_MASK
, PPCVSX
, PPCNONE
, {XT6
, XA6
, XB6
}},
5855 {"xvmaddasp", XX3(60,65), XX3_MASK
, PPCVSX
, PPCNONE
, {XT6
, XA6
, XB6
}},
5856 {"xvcmpeqsp", XX3RC(60,67,0), XX3_MASK
, PPCVSX
, PPCNONE
, {XT6
, XA6
, XB6
}},
5857 {"xvcmpeqsp.", XX3RC(60,67,1), XX3_MASK
, PPCVSX
, PPCNONE
, {XT6
, XA6
, XB6
}},
5858 {"xvsubsp", XX3(60,72), XX3_MASK
, PPCVSX
, PPCNONE
, {XT6
, XA6
, XB6
}},
5859 {"xscvdpuxws", XX2(60,72), XX2_MASK
, PPCVSX
, PPCNONE
, {XT6
, XB6
}},
5860 {"xvmaddmsp", XX3(60,73), XX3_MASK
, PPCVSX
, PPCNONE
, {XT6
, XA6
, XB6
}},
5861 {"xsrdpi", XX2(60,73), XX2_MASK
, PPCVSX
, PPCNONE
, {XT6
, XB6
}},
5862 {"xsrsqrtedp", XX2(60,74), XX2_MASK
, PPCVSX
, PPCNONE
, {XT6
, XB6
}},
5863 {"xssqrtdp", XX2(60,75), XX2_MASK
, PPCVSX
, PPCNONE
, {XT6
, XB6
}},
5864 {"xvcmpgtsp", XX3RC(60,75,0), XX3_MASK
, PPCVSX
, PPCNONE
, {XT6
, XA6
, XB6
}},
5865 {"xvcmpgtsp.", XX3RC(60,75,1), XX3_MASK
, PPCVSX
, PPCNONE
, {XT6
, XA6
, XB6
}},
5866 {"xvmulsp", XX3(60,80), XX3_MASK
, PPCVSX
, PPCNONE
, {XT6
, XA6
, XB6
}},
5867 {"xvmsubasp", XX3(60,81), XX3_MASK
, PPCVSX
, PPCNONE
, {XT6
, XA6
, XB6
}},
5868 {"xvcmpgesp", XX3RC(60,83,0), XX3_MASK
, PPCVSX
, PPCNONE
, {XT6
, XA6
, XB6
}},
5869 {"xvcmpgesp.", XX3RC(60,83,1), XX3_MASK
, PPCVSX
, PPCNONE
, {XT6
, XA6
, XB6
}},
5870 {"xvdivsp", XX3(60,88), XX3_MASK
, PPCVSX
, PPCNONE
, {XT6
, XA6
, XB6
}},
5871 {"xscvdpsxws", XX2(60,88), XX2_MASK
, PPCVSX
, PPCNONE
, {XT6
, XB6
}},
5872 {"xvmsubmsp", XX3(60,89), XX3_MASK
, PPCVSX
, PPCNONE
, {XT6
, XA6
, XB6
}},
5873 {"xsrdpiz", XX2(60,89), XX2_MASK
, PPCVSX
, PPCNONE
, {XT6
, XB6
}},
5874 {"xsredp", XX2(60,90), XX2_MASK
, PPCVSX
, PPCNONE
, {XT6
, XB6
}},
5875 {"xvtdivsp", XX3(60,93), XX3BF_MASK
, PPCVSX
, PPCNONE
, {BF
, XA6
, XB6
}},
5876 {"xvadddp", XX3(60,96), XX3_MASK
, PPCVSX
, PPCNONE
, {XT6
, XA6
, XB6
}},
5877 {"xvmaddadp", XX3(60,97), XX3_MASK
, PPCVSX
, PPCNONE
, {XT6
, XA6
, XB6
}},
5878 {"xvcmpeqdp", XX3RC(60,99,0), XX3_MASK
, PPCVSX
, PPCNONE
, {XT6
, XA6
, XB6
}},
5879 {"xvcmpeqdp.", XX3RC(60,99,1), XX3_MASK
, PPCVSX
, PPCNONE
, {XT6
, XA6
, XB6
}},
5880 {"xvsubdp", XX3(60,104), XX3_MASK
, PPCVSX
, PPCNONE
, {XT6
, XA6
, XB6
}},
5881 {"xvmaddmdp", XX3(60,105), XX3_MASK
, PPCVSX
, PPCNONE
, {XT6
, XA6
, XB6
}},
5882 {"xsrdpip", XX2(60,105), XX2_MASK
, PPCVSX
, PPCNONE
, {XT6
, XB6
}},
5883 {"xstsqrtdp", XX2(60,106), XX2BF_MASK
, PPCVSX
, PPCNONE
, {BF
, XB6
}},
5884 {"xsrdpic", XX2(60,107), XX2_MASK
, PPCVSX
, PPCNONE
, {XT6
, XB6
}},
5885 {"xvcmpgtdp", XX3RC(60,107,0), XX3_MASK
, PPCVSX
, PPCNONE
, {XT6
, XA6
, XB6
}},
5886 {"xvcmpgtdp.", XX3RC(60,107,1), XX3_MASK
, PPCVSX
, PPCNONE
, {XT6
, XA6
, XB6
}},
5887 {"xvmuldp", XX3(60,112), XX3_MASK
, PPCVSX
, PPCNONE
, {XT6
, XA6
, XB6
}},
5888 {"xvmsubadp", XX3(60,113), XX3_MASK
, PPCVSX
, PPCNONE
, {XT6
, XA6
, XB6
}},
5889 {"xvcmpgedp", XX3RC(60,115,0), XX3_MASK
, PPCVSX
, PPCNONE
, {XT6
, XA6
, XB6
}},
5890 {"xvcmpgedp.", XX3RC(60,115,1), XX3_MASK
, PPCVSX
, PPCNONE
, {XT6
, XA6
, XB6
}},
5891 {"xvdivdp", XX3(60,120), XX3_MASK
, PPCVSX
, PPCNONE
, {XT6
, XA6
, XB6
}},
5892 {"xvmsubmdp", XX3(60,121), XX3_MASK
, PPCVSX
, PPCNONE
, {XT6
, XA6
, XB6
}},
5893 {"xsrdpim", XX2(60,121), XX2_MASK
, PPCVSX
, PPCNONE
, {XT6
, XB6
}},
5894 {"xvtdivdp", XX3(60,125), XX3BF_MASK
, PPCVSX
, PPCNONE
, {BF
, XA6
, XB6
}},
5895 {"xxland", XX3(60,130), XX3_MASK
, PPCVSX
, PPCNONE
, {XT6
, XA6
, XB6
}},
5896 {"xvcvspuxws", XX2(60,136), XX2_MASK
, PPCVSX
, PPCNONE
, {XT6
, XB6
}},
5897 {"xvrspi", XX2(60,137), XX2_MASK
, PPCVSX
, PPCNONE
, {XT6
, XB6
}},
5898 {"xxlandc", XX3(60,138), XX3_MASK
, PPCVSX
, PPCNONE
, {XT6
, XA6
, XB6
}},
5899 {"xvrsqrtesp", XX2(60,138), XX2_MASK
, PPCVSX
, PPCNONE
, {XT6
, XB6
}},
5900 {"xvsqrtsp", XX2(60,139), XX2_MASK
, PPCVSX
, PPCNONE
, {XT6
, XB6
}},
5901 {"xxlor", XX3(60,146), XX3_MASK
, PPCVSX
, PPCNONE
, {XT6
, XA6
, XB6
}},
5902 {"xvcvspsxws", XX2(60,152), XX2_MASK
, PPCVSX
, PPCNONE
, {XT6
, XB6
}},
5903 {"xvrspiz", XX2(60,153), XX2_MASK
, PPCVSX
, PPCNONE
, {XT6
, XB6
}},
5904 {"xxlxor", XX3(60,154), XX3_MASK
, PPCVSX
, PPCNONE
, {XT6
, XA6
, XB6
}},
5905 {"xvresp", XX2(60,154), XX2_MASK
, PPCVSX
, PPCNONE
, {XT6
, XB6
}},
5906 {"xsmaxdp", XX3(60,160), XX3_MASK
, PPCVSX
, PPCNONE
, {XT6
, XA6
, XB6
}},
5907 {"xsnmaddadp", XX3(60,161), XX3_MASK
, PPCVSX
, PPCNONE
, {XT6
, XA6
, XB6
}},
5908 {"xxlnor", XX3(60,162), XX3_MASK
, PPCVSX
, PPCNONE
, {XT6
, XA6
, XB6
}},
5909 {"xxspltw", XX2(60,164), XX2UIM_MASK
, PPCVSX
, PPCNONE
, {XT6
, XB6
, UIM
}},
5910 {"xsmindp", XX3(60,168), XX3_MASK
, PPCVSX
, PPCNONE
, {XT6
, XA6
, XB6
}},
5911 {"xvcvuxwsp", XX2(60,168), XX2_MASK
, PPCVSX
, PPCNONE
, {XT6
, XB6
}},
5912 {"xsnmaddmdp", XX3(60,169), XX3_MASK
, PPCVSX
, PPCNONE
, {XT6
, XA6
, XB6
}},
5913 {"xvrspip", XX2(60,169), XX2_MASK
, PPCVSX
, PPCNONE
, {XT6
, XB6
}},
5914 {"xvtsqrtsp", XX2(60,170), XX2BF_MASK
, PPCVSX
, PPCNONE
, {BF
, XB6
}},
5915 {"xvrspic", XX2(60,171), XX2_MASK
, PPCVSX
, PPCNONE
, {XT6
, XB6
}},
5916 {"xscpsgndp", XX3(60,176), XX3_MASK
, PPCVSX
, PPCNONE
, {XT6
, XA6
, XB6
}},
5917 {"xsnmsubadp", XX3(60,177), XX3_MASK
, PPCVSX
, PPCNONE
, {XT6
, XA6
, XB6
}},
5918 {"xvcvsxwsp", XX2(60,184), XX2_MASK
, PPCVSX
, PPCNONE
, {XT6
, XB6
}},
5919 {"xsnmsubmdp", XX3(60,185), XX3_MASK
, PPCVSX
, PPCNONE
, {XT6
, XA6
, XB6
}},
5920 {"xvrspim", XX2(60,185), XX2_MASK
, PPCVSX
, PPCNONE
, {XT6
, XB6
}},
5921 {"xvmaxsp", XX3(60,192), XX3_MASK
, PPCVSX
, PPCNONE
, {XT6
, XA6
, XB6
}},
5922 {"xvnmaddasp", XX3(60,193), XX3_MASK
, PPCVSX
, PPCNONE
, {XT6
, XA6
, XB6
}},
5923 {"xvminsp", XX3(60,200), XX3_MASK
, PPCVSX
, PPCNONE
, {XT6
, XA6
, XB6
}},
5924 {"xvcvdpuxws", XX2(60,200), XX2_MASK
, PPCVSX
, PPCNONE
, {XT6
, XB6
}},
5925 {"xvnmaddmsp", XX3(60,201), XX3_MASK
, PPCVSX
, PPCNONE
, {XT6
, XA6
, XB6
}},
5926 {"xvrdpi", XX2(60,201), XX2_MASK
, PPCVSX
, PPCNONE
, {XT6
, XB6
}},
5927 {"xvrsqrtedp", XX2(60,202), XX2_MASK
, PPCVSX
, PPCNONE
, {XT6
, XB6
}},
5928 {"xvsqrtdp", XX2(60,203), XX2_MASK
, PPCVSX
, PPCNONE
, {XT6
, XB6
}},
5929 {"xvmovsp", XX3(60,208), XX3_MASK
, PPCVSX
, PPCNONE
, {XT6
, XA6
, XB6S
}},
5930 {"xvcpsgnsp", XX3(60,208), XX3_MASK
, PPCVSX
, PPCNONE
, {XT6
, XA6
, XB6
}},
5931 {"xvnmsubasp", XX3(60,209), XX3_MASK
, PPCVSX
, PPCNONE
, {XT6
, XA6
, XB6
}},
5932 {"xvcvdpsxws", XX2(60,216), XX2_MASK
, PPCVSX
, PPCNONE
, {XT6
, XB6
}},
5933 {"xvnmsubmsp", XX3(60,217), XX3_MASK
, PPCVSX
, PPCNONE
, {XT6
, XA6
, XB6
}},
5934 {"xvrdpiz", XX2(60,217), XX2_MASK
, PPCVSX
, PPCNONE
, {XT6
, XB6
}},
5935 {"xvredp", XX2(60,218), XX2_MASK
, PPCVSX
, PPCNONE
, {XT6
, XB6
}},
5936 {"xvmaxdp", XX3(60,224), XX3_MASK
, PPCVSX
, PPCNONE
, {XT6
, XA6
, XB6
}},
5937 {"xvnmaddadp", XX3(60,225), XX3_MASK
, PPCVSX
, PPCNONE
, {XT6
, XA6
, XB6
}},
5938 {"xvmindp", XX3(60,232), XX3_MASK
, PPCVSX
, PPCNONE
, {XT6
, XA6
, XB6
}},
5939 {"xvnmaddmdp", XX3(60,233), XX3_MASK
, PPCVSX
, PPCNONE
, {XT6
, XA6
, XB6
}},
5940 {"xvcvuxwdp", XX2(60,232), XX2_MASK
, PPCVSX
, PPCNONE
, {XT6
, XB6
}},
5941 {"xvrdpip", XX2(60,233), XX2_MASK
, PPCVSX
, PPCNONE
, {XT6
, XB6
}},
5942 {"xvtsqrtdp", XX2(60,234), XX2BF_MASK
, PPCVSX
, PPCNONE
, {BF
, XB6
}},
5943 {"xvrdpic", XX2(60,235), XX2_MASK
, PPCVSX
, PPCNONE
, {XT6
, XB6
}},
5944 {"xvmovdp", XX3(60,240), XX3_MASK
, PPCVSX
, PPCNONE
, {XT6
, XA6
, XB6S
}},
5945 {"xvcpsgndp", XX3(60,240), XX3_MASK
, PPCVSX
, PPCNONE
, {XT6
, XA6
, XB6
}},
5946 {"xvnmsubadp", XX3(60,241), XX3_MASK
, PPCVSX
, PPCNONE
, {XT6
, XA6
, XB6
}},
5947 {"xvcvsxwdp", XX2(60,248), XX2_MASK
, PPCVSX
, PPCNONE
, {XT6
, XB6
}},
5948 {"xvnmsubmdp", XX3(60,249), XX3_MASK
, PPCVSX
, PPCNONE
, {XT6
, XA6
, XB6
}},
5949 {"xvrdpim", XX2(60,249), XX2_MASK
, PPCVSX
, PPCNONE
, {XT6
, XB6
}},
5950 {"xscvdpsp", XX2(60,265), XX2_MASK
, PPCVSX
, PPCNONE
, {XT6
, XB6
}},
5951 {"xscvdpuxds", XX2(60,328), XX2_MASK
, PPCVSX
, PPCNONE
, {XT6
, XB6
}},
5952 {"xscvspdp", XX2(60,329), XX2_MASK
, PPCVSX
, PPCNONE
, {XT6
, XB6
}},
5953 {"xscvdpsxds", XX2(60,344), XX2_MASK
, PPCVSX
, PPCNONE
, {XT6
, XB6
}},
5954 {"xsabsdp", XX2(60,345), XX2_MASK
, PPCVSX
, PPCNONE
, {XT6
, XB6
}},
5955 {"xscvuxddp", XX2(60,360), XX2_MASK
, PPCVSX
, PPCNONE
, {XT6
, XB6
}},
5956 {"xsnabsdp", XX2(60,361), XX2_MASK
, PPCVSX
, PPCNONE
, {XT6
, XB6
}},
5957 {"xscvsxddp", XX2(60,376), XX2_MASK
, PPCVSX
, PPCNONE
, {XT6
, XB6
}},
5958 {"xsnegdp", XX2(60,377), XX2_MASK
, PPCVSX
, PPCNONE
, {XT6
, XB6
}},
5959 {"xvcvspuxds", XX2(60,392), XX2_MASK
, PPCVSX
, PPCNONE
, {XT6
, XB6
}},
5960 {"xvcvdpsp", XX2(60,393), XX2_MASK
, PPCVSX
, PPCNONE
, {XT6
, XB6
}},
5961 {"xvcvspsxds", XX2(60,408), XX2_MASK
, PPCVSX
, PPCNONE
, {XT6
, XB6
}},
5962 {"xvabssp", XX2(60,409), XX2_MASK
, PPCVSX
, PPCNONE
, {XT6
, XB6
}},
5963 {"xvcvuxdsp", XX2(60,424), XX2_MASK
, PPCVSX
, PPCNONE
, {XT6
, XB6
}},
5964 {"xvnabssp", XX2(60,425), XX2_MASK
, PPCVSX
, PPCNONE
, {XT6
, XB6
}},
5965 {"xvcvsxdsp", XX2(60,440), XX2_MASK
, PPCVSX
, PPCNONE
, {XT6
, XB6
}},
5966 {"xvnegsp", XX2(60,441), XX2_MASK
, PPCVSX
, PPCNONE
, {XT6
, XB6
}},
5967 {"xvcvdpuxds", XX2(60,456), XX2_MASK
, PPCVSX
, PPCNONE
, {XT6
, XB6
}},
5968 {"xvcvspdp", XX2(60,457), XX2_MASK
, PPCVSX
, PPCNONE
, {XT6
, XB6
}},
5969 {"xvcvdpsxds", XX2(60,472), XX2_MASK
, PPCVSX
, PPCNONE
, {XT6
, XB6
}},
5970 {"xvabsdp", XX2(60,473), XX2_MASK
, PPCVSX
, PPCNONE
, {XT6
, XB6
}},
5971 {"xvcvuxddp", XX2(60,488), XX2_MASK
, PPCVSX
, PPCNONE
, {XT6
, XB6
}},
5972 {"xvnabsdp", XX2(60,489), XX2_MASK
, PPCVSX
, PPCNONE
, {XT6
, XB6
}},
5973 {"xvcvsxddp", XX2(60,504), XX2_MASK
, PPCVSX
, PPCNONE
, {XT6
, XB6
}},
5974 {"xvnegdp", XX2(60,505), XX2_MASK
, PPCVSX
, PPCNONE
, {XT6
, XB6
}},
5976 {"psq_st", OP(60), OP_MASK
, PPCPS
, PPCNONE
, {FRS
,PSD
,RA
,PSW
,PSQ
}},
5977 {"stfq", OP(60), OP_MASK
, POWER2
, PPCNONE
, {FRS
, D
, RA
}},
5979 {"stfdp", OP(61), OP_MASK
, POWER6
, POWER7
, {FRSp
, D
, RA0
}},
5980 {"psq_stu", OP(61), OP_MASK
, PPCPS
, PPCNONE
, {FRS
,PSD
,RA
,PSW
,PSQ
}},
5981 {"stfqu", OP(61), OP_MASK
, POWER2
, PPCNONE
, {FRS
, D
, RA
}},
5983 {"std", DSO(62,0), DS_MASK
, PPC64
, PPCNONE
, {RS
, DS
, RA0
}},
5984 {"stdu", DSO(62,1), DS_MASK
, PPC64
, PPCNONE
, {RS
, DS
, RAS
}},
5985 {"stq", DSO(62,2), DS_MASK
, POWER4
, PPC476
, {RSQ
, DS
, RA0
}},
5987 {"fcmpu", X(63,0), X_MASK
|(3<<21), COM
, PPCEFS
, {BF
, FRA
, FRB
}},
5989 {"daddq", XRC(63,2,0), X_MASK
, POWER6
, PPCNONE
, {FRTp
, FRAp
, FRBp
}},
5990 {"daddq.", XRC(63,2,1), X_MASK
, POWER6
, PPCNONE
, {FRTp
, FRAp
, FRBp
}},
5992 {"dquaq", ZRC(63,3,0), Z2_MASK
, POWER6
, PPCNONE
, {FRTp
, FRAp
, FRBp
, RMC
}},
5993 {"dquaq.", ZRC(63,3,1), Z2_MASK
, POWER6
, PPCNONE
, {FRTp
, FRAp
, FRBp
, RMC
}},
5995 {"fcpsgn", XRC(63,8,0), X_MASK
, POWER6
|PPCA2
|PPC476
, PPCNONE
, {FRT
, FRA
, FRB
}},
5996 {"fcpsgn.", XRC(63,8,1), X_MASK
, POWER6
|PPCA2
|PPC476
, PPCNONE
, {FRT
, FRA
, FRB
}},
5998 {"frsp", XRC(63,12,0), XRA_MASK
, COM
, PPCEFS
, {FRT
, FRB
}},
5999 {"frsp.", XRC(63,12,1), XRA_MASK
, COM
, PPCEFS
, {FRT
, FRB
}},
6001 {"fctiw", XRC(63,14,0), XRA_MASK
, PPCCOM
, PPCEFS
, {FRT
, FRB
}},
6002 {"fcir", XRC(63,14,0), XRA_MASK
, PWR2COM
, PPCNONE
, {FRT
, FRB
}},
6003 {"fctiw.", XRC(63,14,1), XRA_MASK
, PPCCOM
, PPCEFS
, {FRT
, FRB
}},
6004 {"fcir.", XRC(63,14,1), XRA_MASK
, PWR2COM
, PPCNONE
, {FRT
, FRB
}},
6006 {"fctiwz", XRC(63,15,0), XRA_MASK
, PPCCOM
, PPCEFS
, {FRT
, FRB
}},
6007 {"fcirz", XRC(63,15,0), XRA_MASK
, PWR2COM
, PPCNONE
, {FRT
, FRB
}},
6008 {"fctiwz.", XRC(63,15,1), XRA_MASK
, PPCCOM
, PPCEFS
, {FRT
, FRB
}},
6009 {"fcirz.", XRC(63,15,1), XRA_MASK
, PWR2COM
, PPCNONE
, {FRT
, FRB
}},
6011 {"fdiv", A(63,18,0), AFRC_MASK
, PPCCOM
, PPCEFS
, {FRT
, FRA
, FRB
}},
6012 {"fd", A(63,18,0), AFRC_MASK
, PWRCOM
, PPCNONE
, {FRT
, FRA
, FRB
}},
6013 {"fdiv.", A(63,18,1), AFRC_MASK
, PPCCOM
, PPCEFS
, {FRT
, FRA
, FRB
}},
6014 {"fd.", A(63,18,1), AFRC_MASK
, PWRCOM
, PPCNONE
, {FRT
, FRA
, FRB
}},
6016 {"fsub", A(63,20,0), AFRC_MASK
, PPCCOM
, PPCEFS
, {FRT
, FRA
, FRB
}},
6017 {"fs", A(63,20,0), AFRC_MASK
, PWRCOM
, PPCNONE
, {FRT
, FRA
, FRB
}},
6018 {"fsub.", A(63,20,1), AFRC_MASK
, PPCCOM
, PPCEFS
, {FRT
, FRA
, FRB
}},
6019 {"fs.", A(63,20,1), AFRC_MASK
, PWRCOM
, PPCNONE
, {FRT
, FRA
, FRB
}},
6021 {"fadd", A(63,21,0), AFRC_MASK
, PPCCOM
, PPCEFS
, {FRT
, FRA
, FRB
}},
6022 {"fa", A(63,21,0), AFRC_MASK
, PWRCOM
, PPCNONE
, {FRT
, FRA
, FRB
}},
6023 {"fadd.", A(63,21,1), AFRC_MASK
, PPCCOM
, PPCEFS
, {FRT
, FRA
, FRB
}},
6024 {"fa.", A(63,21,1), AFRC_MASK
, PWRCOM
, PPCNONE
, {FRT
, FRA
, FRB
}},
6026 {"fsqrt", A(63,22,0), AFRAFRC_MASK
, PPCPWR2
, TITAN
, {FRT
, FRB
}},
6027 {"fsqrt.", A(63,22,1), AFRAFRC_MASK
, PPCPWR2
, TITAN
, {FRT
, FRB
}},
6029 {"fsel", A(63,23,0), A_MASK
, PPC
, PPCEFS
, {FRT
, FRA
, FRC
, FRB
}},
6030 {"fsel.", A(63,23,1), A_MASK
, PPC
, PPCEFS
, {FRT
, FRA
, FRC
, FRB
}},
6032 {"fre", A(63,24,0), AFRAFRC_MASK
, POWER7
, PPCNONE
, {FRT
, FRB
}},
6033 {"fre", A(63,24,0), AFRALFRC_MASK
, POWER5
, POWER7
, {FRT
, FRB
, A_L
}},
6034 {"fre.", A(63,24,1), AFRAFRC_MASK
, POWER7
, PPCNONE
, {FRT
, FRB
}},
6035 {"fre.", A(63,24,1), AFRALFRC_MASK
, POWER5
, POWER7
, {FRT
, FRB
, A_L
}},
6037 {"fmul", A(63,25,0), AFRB_MASK
, PPCCOM
, PPCEFS
, {FRT
, FRA
, FRC
}},
6038 {"fm", A(63,25,0), AFRB_MASK
, PWRCOM
, PPCNONE
, {FRT
, FRA
, FRC
}},
6039 {"fmul.", A(63,25,1), AFRB_MASK
, PPCCOM
, PPCEFS
, {FRT
, FRA
, FRC
}},
6040 {"fm.", A(63,25,1), AFRB_MASK
, PWRCOM
, PPCNONE
, {FRT
, FRA
, FRC
}},
6042 {"frsqrte", A(63,26,0), AFRAFRC_MASK
, POWER7
, PPCNONE
, {FRT
, FRB
}},
6043 {"frsqrte", A(63,26,0), AFRALFRC_MASK
, PPC
, POWER7
, {FRT
, FRB
, A_L
}},
6044 {"frsqrte.", A(63,26,1), AFRAFRC_MASK
, POWER7
, PPCNONE
, {FRT
, FRB
}},
6045 {"frsqrte.", A(63,26,1), AFRALFRC_MASK
, PPC
, POWER7
, {FRT
, FRB
, A_L
}},
6047 {"fmsub", A(63,28,0), A_MASK
, PPCCOM
, PPCEFS
, {FRT
, FRA
, FRC
, FRB
}},
6048 {"fms", A(63,28,0), A_MASK
, PWRCOM
, PPCNONE
, {FRT
, FRA
, FRC
, FRB
}},
6049 {"fmsub.", A(63,28,1), A_MASK
, PPCCOM
, PPCEFS
, {FRT
, FRA
, FRC
, FRB
}},
6050 {"fms.", A(63,28,1), A_MASK
, PWRCOM
, PPCNONE
, {FRT
, FRA
, FRC
, FRB
}},
6052 {"fmadd", A(63,29,0), A_MASK
, PPCCOM
, PPCEFS
, {FRT
, FRA
, FRC
, FRB
}},
6053 {"fma", A(63,29,0), A_MASK
, PWRCOM
, PPCNONE
, {FRT
, FRA
, FRC
, FRB
}},
6054 {"fmadd.", A(63,29,1), A_MASK
, PPCCOM
, PPCEFS
, {FRT
, FRA
, FRC
, FRB
}},
6055 {"fma.", A(63,29,1), A_MASK
, PWRCOM
, PPCNONE
, {FRT
, FRA
, FRC
, FRB
}},
6057 {"fnmsub", A(63,30,0), A_MASK
, PPCCOM
, PPCEFS
, {FRT
, FRA
, FRC
, FRB
}},
6058 {"fnms", A(63,30,0), A_MASK
, PWRCOM
, PPCNONE
, {FRT
, FRA
, FRC
, FRB
}},
6059 {"fnmsub.", A(63,30,1), A_MASK
, PPCCOM
, PPCEFS
, {FRT
, FRA
, FRC
, FRB
}},
6060 {"fnms.", A(63,30,1), A_MASK
, PWRCOM
, PPCNONE
, {FRT
, FRA
, FRC
, FRB
}},
6062 {"fnmadd", A(63,31,0), A_MASK
, PPCCOM
, PPCEFS
, {FRT
, FRA
, FRC
, FRB
}},
6063 {"fnma", A(63,31,0), A_MASK
, PWRCOM
, PPCNONE
, {FRT
, FRA
, FRC
, FRB
}},
6064 {"fnmadd.", A(63,31,1), A_MASK
, PPCCOM
, PPCEFS
, {FRT
, FRA
, FRC
, FRB
}},
6065 {"fnma.", A(63,31,1), A_MASK
, PWRCOM
, PPCNONE
, {FRT
, FRA
, FRC
, FRB
}},
6067 {"fcmpo", X(63,32), X_MASK
|(3<<21), COM
, PPCEFS
, {BF
, FRA
, FRB
}},
6069 {"dmulq", XRC(63,34,0), X_MASK
, POWER6
, PPCNONE
, {FRTp
, FRAp
, FRBp
}},
6070 {"dmulq.", XRC(63,34,1), X_MASK
, POWER6
, PPCNONE
, {FRTp
, FRAp
, FRBp
}},
6072 {"drrndq", ZRC(63,35,0), Z2_MASK
, POWER6
, PPCNONE
, {FRTp
, FRA
, FRBp
, RMC
}},
6073 {"drrndq.", ZRC(63,35,1), Z2_MASK
, POWER6
, PPCNONE
, {FRTp
, FRA
, FRBp
, RMC
}},
6075 {"mtfsb1", XRC(63,38,0), XRARB_MASK
, COM
, PPCNONE
, {BT
}},
6076 {"mtfsb1.", XRC(63,38,1), XRARB_MASK
, COM
, PPCNONE
, {BT
}},
6078 {"fneg", XRC(63,40,0), XRA_MASK
, COM
, PPCEFS
, {FRT
, FRB
}},
6079 {"fneg.", XRC(63,40,1), XRA_MASK
, COM
, PPCEFS
, {FRT
, FRB
}},
6081 {"mcrfs", X(63,64), XRB_MASK
|(3<<21)|(3<<16), COM
, PPCNONE
, {BF
, BFA
}},
6083 {"dscliq", ZRC(63,66,0), Z_MASK
, POWER6
, PPCNONE
, {FRTp
, FRAp
, SH16
}},
6084 {"dscliq.", ZRC(63,66,1), Z_MASK
, POWER6
, PPCNONE
, {FRTp
, FRAp
, SH16
}},
6086 {"dquaiq", ZRC(63,67,0), Z2_MASK
, POWER6
, PPCNONE
, {TE
, FRTp
, FRBp
, RMC
}},
6087 {"dquaiq.", ZRC(63,67,1), Z2_MASK
, POWER6
, PPCNONE
, {TE
, FRTp
, FRBp
, RMC
}},
6089 {"mtfsb0", XRC(63,70,0), XRARB_MASK
, COM
, PPCNONE
, {BT
}},
6090 {"mtfsb0.", XRC(63,70,1), XRARB_MASK
, COM
, PPCNONE
, {BT
}},
6092 {"fmr", XRC(63,72,0), XRA_MASK
, COM
, PPCEFS
, {FRT
, FRB
}},
6093 {"fmr.", XRC(63,72,1), XRA_MASK
, COM
, PPCEFS
, {FRT
, FRB
}},
6095 {"dscriq", ZRC(63,98,0), Z_MASK
, POWER6
, PPCNONE
, {FRTp
, FRAp
, SH16
}},
6096 {"dscriq.", ZRC(63,98,1), Z_MASK
, POWER6
, PPCNONE
, {FRTp
, FRAp
, SH16
}},
6098 {"drintxq", ZRC(63,99,0), Z2_MASK
, POWER6
, PPCNONE
, {R
, FRTp
, FRBp
, RMC
}},
6099 {"drintxq.", ZRC(63,99,1), Z2_MASK
, POWER6
, PPCNONE
, {R
, FRTp
, FRBp
, RMC
}},
6101 {"ftdiv", X(63,128), X_MASK
|(3<<21), POWER7
, PPCNONE
, {BF
, FRA
, FRB
}},
6103 {"dcmpoq", X(63,130), X_MASK
, POWER6
, PPCNONE
, {BF
, FRAp
, FRBp
}},
6105 {"mtfsfi", XRC(63,134,0), XWRA_MASK
|(3<<21)|(1<<11), POWER6
|PPCA2
|PPC476
, PPCNONE
, {BFF
, U
, W
}},
6106 {"mtfsfi", XRC(63,134,0), XRA_MASK
|(3<<21)|(1<<11), COM
, POWER6
|PPCA2
|PPC476
, {BFF
, U
}},
6107 {"mtfsfi.", XRC(63,134,1), XWRA_MASK
|(3<<21)|(1<<11), POWER6
|PPCA2
|PPC476
, PPCNONE
, {BFF
, U
, W
}},
6108 {"mtfsfi.", XRC(63,134,1), XRA_MASK
|(3<<21)|(1<<11), COM
, POWER6
|PPCA2
|PPC476
, {BFF
, U
}},
6110 {"fnabs", XRC(63,136,0), XRA_MASK
, COM
, PPCEFS
, {FRT
, FRB
}},
6111 {"fnabs.", XRC(63,136,1), XRA_MASK
, COM
, PPCEFS
, {FRT
, FRB
}},
6113 {"fctiwu", XRC(63,142,0), XRA_MASK
, POWER7
, PPCNONE
, {FRT
, FRB
}},
6114 {"fctiwu.", XRC(63,142,1), XRA_MASK
, POWER7
, PPCNONE
, {FRT
, FRB
}},
6115 {"fctiwuz", XRC(63,143,0), XRA_MASK
, POWER7
, PPCNONE
, {FRT
, FRB
}},
6116 {"fctiwuz.", XRC(63,143,1), XRA_MASK
, POWER7
, PPCNONE
, {FRT
, FRB
}},
6118 {"ftsqrt", X(63,160), X_MASK
|(3<<21|FRA_MASK
), POWER7
, PPCNONE
, {BF
, FRB
}},
6120 {"dtstexq", X(63,162), X_MASK
, POWER6
, PPCNONE
, {BF
, FRAp
, FRBp
}},
6121 {"dtstdcq", Z(63,194), Z_MASK
, POWER6
, PPCNONE
, {BF
, FRAp
, DCM
}},
6122 {"dtstdgq", Z(63,226), Z_MASK
, POWER6
, PPCNONE
, {BF
, FRAp
, DGM
}},
6124 {"drintnq", ZRC(63,227,0), Z2_MASK
, POWER6
, PPCNONE
, {R
, FRTp
, FRBp
, RMC
}},
6125 {"drintnq.", ZRC(63,227,1), Z2_MASK
, POWER6
, PPCNONE
, {R
, FRTp
, FRBp
, RMC
}},
6127 {"dctqpq", XRC(63,258,0), X_MASK
, POWER6
, PPCNONE
, {FRTp
, FRB
}},
6128 {"dctqpq.", XRC(63,258,1), X_MASK
, POWER6
, PPCNONE
, {FRTp
, FRB
}},
6130 {"fabs", XRC(63,264,0), XRA_MASK
, COM
, PPCEFS
, {FRT
, FRB
}},
6131 {"fabs.", XRC(63,264,1), XRA_MASK
, COM
, PPCEFS
, {FRT
, FRB
}},
6133 {"dctfixq", XRC(63,290,0), X_MASK
, POWER6
, PPCNONE
, {FRT
, FRBp
}},
6134 {"dctfixq.", XRC(63,290,1), X_MASK
, POWER6
, PPCNONE
, {FRT
, FRBp
}},
6136 {"ddedpdq", XRC(63,322,0), X_MASK
, POWER6
, PPCNONE
, {SP
, FRTp
, FRBp
}},
6137 {"ddedpdq.", XRC(63,322,1), X_MASK
, POWER6
, PPCNONE
, {SP
, FRTp
, FRBp
}},
6139 {"dxexq", XRC(63,354,0), X_MASK
, POWER6
, PPCNONE
, {FRT
, FRBp
}},
6140 {"dxexq.", XRC(63,354,1), X_MASK
, POWER6
, PPCNONE
, {FRT
, FRBp
}},
6142 {"frin", XRC(63,392,0), XRA_MASK
, POWER5
, PPCNONE
, {FRT
, FRB
}},
6143 {"frin.", XRC(63,392,1), XRA_MASK
, POWER5
, PPCNONE
, {FRT
, FRB
}},
6144 {"friz", XRC(63,424,0), XRA_MASK
, POWER5
, PPCNONE
, {FRT
, FRB
}},
6145 {"friz.", XRC(63,424,1), XRA_MASK
, POWER5
, PPCNONE
, {FRT
, FRB
}},
6146 {"frip", XRC(63,456,0), XRA_MASK
, POWER5
, PPCNONE
, {FRT
, FRB
}},
6147 {"frip.", XRC(63,456,1), XRA_MASK
, POWER5
, PPCNONE
, {FRT
, FRB
}},
6148 {"frim", XRC(63,488,0), XRA_MASK
, POWER5
, PPCNONE
, {FRT
, FRB
}},
6149 {"frim.", XRC(63,488,1), XRA_MASK
, POWER5
, PPCNONE
, {FRT
, FRB
}},
6151 {"dsubq", XRC(63,514,0), X_MASK
, POWER6
, PPCNONE
, {FRTp
, FRAp
, FRBp
}},
6152 {"dsubq.", XRC(63,514,1), X_MASK
, POWER6
, PPCNONE
, {FRTp
, FRAp
, FRBp
}},
6154 {"ddivq", XRC(63,546,0), X_MASK
, POWER6
, PPCNONE
, {FRTp
, FRAp
, FRBp
}},
6155 {"ddivq.", XRC(63,546,1), X_MASK
, POWER6
, PPCNONE
, {FRTp
, FRAp
, FRBp
}},
6157 {"mffs", XRC(63,583,0), XRARB_MASK
, COM
, PPCEFS
, {FRT
}},
6158 {"mffs.", XRC(63,583,1), XRARB_MASK
, COM
, PPCEFS
, {FRT
}},
6160 {"dcmpuq", X(63,642), X_MASK
, POWER6
, PPCNONE
, {BF
, FRAp
, FRBp
}},
6162 {"dtstsfq", X(63,674), X_MASK
, POWER6
, PPCNONE
, {BF
, FRA
, FRBp
}},
6164 {"mtfsf", XFL(63,711,0), XFL_MASK
, POWER6
|PPCA2
|PPC476
, PPCNONE
, {FLM
, FRB
, XFL_L
, W
}},
6165 {"mtfsf", XFL(63,711,0), XFL_MASK
, COM
, POWER6
|PPCA2
|PPC476
|PPCEFS
, {FLM
, FRB
}},
6166 {"mtfsf.", XFL(63,711,1), XFL_MASK
, POWER6
|PPCA2
|PPC476
, PPCNONE
, {FLM
, FRB
, XFL_L
, W
}},
6167 {"mtfsf.", XFL(63,711,1), XFL_MASK
, COM
, POWER6
|PPCA2
|PPC476
|PPCEFS
, {FLM
, FRB
}},
6169 {"drdpq", XRC(63,770,0), X_MASK
, POWER6
, PPCNONE
, {FRTp
, FRBp
}},
6170 {"drdpq.", XRC(63,770,1), X_MASK
, POWER6
, PPCNONE
, {FRTp
, FRBp
}},
6172 {"dcffixq", XRC(63,802,0), X_MASK
, POWER6
, PPCNONE
, {FRTp
, FRB
}},
6173 {"dcffixq.", XRC(63,802,1), X_MASK
, POWER6
, PPCNONE
, {FRTp
, FRB
}},
6175 {"fctid", XRC(63,814,0), XRA_MASK
, PPC64
, PPCNONE
, {FRT
, FRB
}},
6176 {"fctid", XRC(63,814,0), XRA_MASK
, PPC476
, PPCNONE
, {FRT
, FRB
}},
6177 {"fctid.", XRC(63,814,1), XRA_MASK
, PPC64
, PPCNONE
, {FRT
, FRB
}},
6178 {"fctid.", XRC(63,814,1), XRA_MASK
, PPC476
, PPCNONE
, {FRT
, FRB
}},
6180 {"fctidz", XRC(63,815,0), XRA_MASK
, PPC64
, PPCNONE
, {FRT
, FRB
}},
6181 {"fctidz", XRC(63,815,0), XRA_MASK
, PPC476
, PPCNONE
, {FRT
, FRB
}},
6182 {"fctidz.", XRC(63,815,1), XRA_MASK
, PPC64
, PPCNONE
, {FRT
, FRB
}},
6183 {"fctidz.", XRC(63,815,1), XRA_MASK
, PPC476
, PPCNONE
, {FRT
, FRB
}},
6185 {"denbcdq", XRC(63,834,0), X_MASK
, POWER6
, PPCNONE
, {S
, FRTp
, FRBp
}},
6186 {"denbcdq.", XRC(63,834,1), X_MASK
, POWER6
, PPCNONE
, {S
, FRTp
, FRBp
}},
6188 {"fcfid", XRC(63,846,0), XRA_MASK
, PPC64
, PPCNONE
, {FRT
, FRB
}},
6189 {"fcfid", XRC(63,846,0), XRA_MASK
, PPC476
, PPCNONE
, {FRT
, FRB
}},
6190 {"fcfid.", XRC(63,846,1), XRA_MASK
, PPC64
, PPCNONE
, {FRT
, FRB
}},
6191 {"fcfid.", XRC(63,846,1), XRA_MASK
, PPC476
, PPCNONE
, {FRT
, FRB
}},
6193 {"diexq", XRC(63,866,0), X_MASK
, POWER6
, PPCNONE
, {FRTp
, FRA
, FRBp
}},
6194 {"diexq.", XRC(63,866,1), X_MASK
, POWER6
, PPCNONE
, {FRTp
, FRA
, FRBp
}},
6196 {"fctidu", XRC(63,942,0), XRA_MASK
, POWER7
|PPCA2
, PPCNONE
, {FRT
, FRB
}},
6197 {"fctidu.", XRC(63,942,1), XRA_MASK
, POWER7
|PPCA2
, PPCNONE
, {FRT
, FRB
}},
6199 {"fctiduz", XRC(63,943,0), XRA_MASK
, POWER7
|PPCA2
, PPCNONE
, {FRT
, FRB
}},
6200 {"fctiduz.", XRC(63,943,1), XRA_MASK
, POWER7
|PPCA2
, PPCNONE
, {FRT
, FRB
}},
6202 {"fcfidu", XRC(63,974,0), XRA_MASK
, POWER7
|PPCA2
, PPCNONE
, {FRT
, FRB
}},
6203 {"fcfidu.", XRC(63,974,1), XRA_MASK
, POWER7
|PPCA2
, PPCNONE
, {FRT
, FRB
}},
6206 const int powerpc_num_opcodes
=
6207 sizeof (powerpc_opcodes
) / sizeof (powerpc_opcodes
[0]);
6209 /* The VLE opcode table.
6211 The format of this opcode table is the same as the main opcode table. */
6213 const struct powerpc_opcode vle_opcodes
[] = {
6215 {"se_illegal", C(0), C_MASK
, PPCVLE
, PPCNONE
, {}},
6216 {"se_isync", C(1), C_MASK
, PPCVLE
, PPCNONE
, {}},
6217 {"se_sc", C(2), C_MASK
, PPCVLE
, PPCNONE
, {}},
6218 {"se_blr", C_LK(2,0), C_LK_MASK
, PPCVLE
, PPCNONE
, {}},
6219 {"se_blrl", C_LK(2,1), C_LK_MASK
, PPCVLE
, PPCNONE
, {}},
6220 {"se_bctr", C_LK(3,0), C_LK_MASK
, PPCVLE
, PPCNONE
, {}},
6221 {"se_bctrl", C_LK(3,1), C_LK_MASK
, PPCVLE
, PPCNONE
, {}},
6222 {"se_rfi", C(8), C_MASK
, PPCVLE
, PPCNONE
, {}},
6223 {"se_rfci", C(9), C_MASK
, PPCVLE
, PPCNONE
, {}},
6224 {"se_rfdi", C(10), C_MASK
, PPCVLE
, PPCNONE
, {}},
6225 {"se_rfmci", C(11), C_MASK
, PPCVLE
, PPCNONE
, {}},
6226 {"se_not", SE_R(0,2), SE_R_MASK
, PPCVLE
, PPCNONE
, {RX
}},
6227 {"se_neg", SE_R(0,3), SE_R_MASK
, PPCVLE
, PPCNONE
, {RX
}},
6228 {"se_mflr", SE_R(0,8), SE_R_MASK
, PPCVLE
, PPCNONE
, {RX
}},
6229 {"se_mtlr", SE_R(0,9), SE_R_MASK
, PPCVLE
, PPCNONE
, {RX
}},
6230 {"se_mfctr", SE_R(0,10), SE_R_MASK
, PPCVLE
, PPCNONE
, {RX
}},
6231 {"se_mtctr", SE_R(0,11), SE_R_MASK
, PPCVLE
, PPCNONE
, {RX
}},
6232 {"se_extzb", SE_R(0,12), SE_R_MASK
, PPCVLE
, PPCNONE
, {RX
}},
6233 {"se_extsb", SE_R(0,13), SE_R_MASK
, PPCVLE
, PPCNONE
, {RX
}},
6234 {"se_extzh", SE_R(0,14), SE_R_MASK
, PPCVLE
, PPCNONE
, {RX
}},
6235 {"se_extsh", SE_R(0,15), SE_R_MASK
, PPCVLE
, PPCNONE
, {RX
}},
6236 {"se_mr", SE_RR(0,1), SE_RR_MASK
, PPCVLE
, PPCNONE
, {RX
, RY
}},
6237 {"se_mtar", SE_RR(0,2), SE_RR_MASK
, PPCVLE
, PPCNONE
, {ARX
, RY
}},
6238 {"se_mfar", SE_RR(0,3), SE_RR_MASK
, PPCVLE
, PPCNONE
, {RX
, ARY
}},
6239 {"se_add", SE_RR(1,0), SE_RR_MASK
, PPCVLE
, PPCNONE
, {RX
, RY
}},
6240 {"se_mullw", SE_RR(1,1), SE_RR_MASK
, PPCVLE
, PPCNONE
, {RX
, RY
}},
6241 {"se_sub", SE_RR(1,2), SE_RR_MASK
, PPCVLE
, PPCNONE
, {RX
, RY
}},
6242 {"se_subf", SE_RR(1,3), SE_RR_MASK
, PPCVLE
, PPCNONE
, {RX
, RY
}},
6243 {"se_cmp", SE_RR(3,0), SE_RR_MASK
, PPCVLE
, PPCNONE
, {RX
, RY
}},
6244 {"se_cmpl", SE_RR(3,1), SE_RR_MASK
, PPCVLE
, PPCNONE
, {RX
, RY
}},
6245 {"se_cmph", SE_RR(3,2), SE_RR_MASK
, PPCVLE
, PPCNONE
, {RX
, RY
}},
6246 {"se_cmphl", SE_RR(3,3), SE_RR_MASK
, PPCVLE
, PPCNONE
, {RX
, RY
}},
6248 {"e_cmpi", SCI8BF(6,0,21), SCI8BF_MASK
, PPCVLE
, PPCNONE
, {CRD32
, RA
, SCLSCI8
}},
6249 {"e_cmpli", SCI8BF(6,1,21), SCI8BF_MASK
, PPCVLE
, PPCNONE
, {CRD32
, RA
, SCLSCI8
}},
6250 {"e_addi", SCI8(6,16), SCI8_MASK
, PPCVLE
, PPCNONE
, {RT
, RA
, SCLSCI8
}},
6251 {"e_subi", SCI8(6,16), SCI8_MASK
, PPCVLE
, PPCNONE
, {RT
, RA
, SCLSCI8N
}},
6252 {"e_addi.", SCI8(6,17), SCI8_MASK
, PPCVLE
, PPCNONE
, {RT
, RA
, SCLSCI8
}},
6253 {"e_addic", SCI8(6,18), SCI8_MASK
, PPCVLE
, PPCNONE
, {RT
, RA
, SCLSCI8
}},
6254 {"e_subic", SCI8(6,18), SCI8_MASK
, PPCVLE
, PPCNONE
, {RT
, RA
, SCLSCI8N
}},
6255 {"e_addic.", SCI8(6,19), SCI8_MASK
, PPCVLE
, PPCNONE
, {RT
, RA
, SCLSCI8
}},
6256 {"e_subic.", SCI8(6,19), SCI8_MASK
, PPCVLE
, PPCNONE
, {RT
, RA
, SCLSCI8N
}},
6257 {"e_mulli", SCI8(6,20), SCI8_MASK
, PPCVLE
, PPCNONE
, {RT
, RA
, SCLSCI8
}},
6258 {"e_subfic", SCI8(6,22), SCI8_MASK
, PPCVLE
, PPCNONE
, {RT
, RA
, SCLSCI8
}},
6259 {"e_subfic.", SCI8(6,23), SCI8_MASK
, PPCVLE
, PPCNONE
, {RT
, RA
, SCLSCI8
}},
6260 {"e_andi", SCI8(6,24), SCI8_MASK
, PPCVLE
, PPCNONE
, {RA
, RS
, SCLSCI8
}},
6261 {"e_andi.", SCI8(6,25), SCI8_MASK
, PPCVLE
, PPCNONE
, {RA
, RS
, SCLSCI8
}},
6262 {"e_nop", SCI8(6,26), 0xffffffff, PPCVLE
, PPCNONE
, {0}},
6263 {"e_ori", SCI8(6,26), SCI8_MASK
, PPCVLE
, PPCNONE
, {RA
, RS
, SCLSCI8
}},
6264 {"e_ori.", SCI8(6,27), SCI8_MASK
, PPCVLE
, PPCNONE
, {RA
, RS
, SCLSCI8
}},
6265 {"e_xori", SCI8(6,28), SCI8_MASK
, PPCVLE
, PPCNONE
, {RA
, RS
, SCLSCI8
}},
6266 {"e_xori.", SCI8(6,29), SCI8_MASK
, PPCVLE
, PPCNONE
, {RA
, RS
, SCLSCI8
}},
6267 {"e_lbzu", OPVUP(6,0), OPVUP_MASK
, PPCVLE
, PPCNONE
, {RT
, D8
, RA0
}},
6268 {"e_lhau", OPVUP(6,3), OPVUP_MASK
, PPCVLE
, PPCNONE
, {RT
, D8
, RA0
}},
6269 {"e_lhzu", OPVUP(6,1), OPVUP_MASK
, PPCVLE
, PPCNONE
, {RT
, D8
, RA0
}},
6270 {"e_lmw", OPVUP(6,8), OPVUP_MASK
, PPCVLE
, PPCNONE
, {RT
, D8
, RA0
}},
6271 {"e_lwzu", OPVUP(6,2), OPVUP_MASK
, PPCVLE
, PPCNONE
, {RT
, D8
, RA0
}},
6272 {"e_stbu", OPVUP(6,4), OPVUP_MASK
, PPCVLE
, PPCNONE
, {RT
, D8
, RA0
}},
6273 {"e_sthu", OPVUP(6,5), OPVUP_MASK
, PPCVLE
, PPCNONE
, {RT
, D8
, RA0
}},
6274 {"e_stwu", OPVUP(6,6), OPVUP_MASK
, PPCVLE
, PPCNONE
, {RT
, D8
, RA0
}},
6275 {"e_stmw", OPVUP(6,9), OPVUP_MASK
, PPCVLE
, PPCNONE
, {RT
, D8
, RA0
}},
6276 {"e_add16i", OP(7), OP_MASK
, PPCVLE
, PPCNONE
, {RT
, RA
, SI
}},
6277 {"e_la", OP(7), OP_MASK
, PPCVLE
, PPCNONE
, {RT
, D
, RA0
}},
6278 {"e_sub16i", OP(7), OP_MASK
, PPCVLE
, PPCNONE
, {RT
, RA
, NSI
}},
6280 {"se_addi", SE_IM5(8,0), SE_IM5_MASK
, PPCVLE
, PPCNONE
, {RX
, OIMM5
}},
6281 {"se_cmpli", SE_IM5(8,1), SE_IM5_MASK
, PPCVLE
, PPCNONE
, {RX
, OIMM5
}},
6282 {"se_subi", SE_IM5(9,0), SE_IM5_MASK
, PPCVLE
, PPCNONE
, {RX
, OIMM5
}},
6283 {"se_subi.", SE_IM5(9,1), SE_IM5_MASK
, PPCVLE
, PPCNONE
, {RX
, OIMM5
}},
6284 {"se_cmpi", SE_IM5(10,1), SE_IM5_MASK
, PPCVLE
, PPCNONE
, {RX
, UI5
}},
6285 {"se_bmaski", SE_IM5(11,0), SE_IM5_MASK
, PPCVLE
, PPCNONE
, {RX
, UI5
}},
6286 {"se_andi", SE_IM5(11,1), SE_IM5_MASK
, PPCVLE
, PPCNONE
, {RX
, UI5
}},
6288 {"e_lbz", OP(12), OP_MASK
, PPCVLE
, PPCNONE
, {RT
, D
, RA0
}},
6289 {"e_stb", OP(13), OP_MASK
, PPCVLE
, PPCNONE
, {RT
, D
, RA0
}},
6290 {"e_lha", OP(14), OP_MASK
, PPCVLE
, PPCNONE
, {RT
, D
, RA0
}},
6292 {"se_srw", SE_RR(16,0), SE_RR_MASK
, PPCVLE
, PPCNONE
, {RX
, RY
}},
6293 {"se_sraw", SE_RR(16,1), SE_RR_MASK
, PPCVLE
, PPCNONE
, {RX
, RY
}},
6294 {"se_slw", SE_RR(16,2), SE_RR_MASK
, PPCVLE
, PPCNONE
, {RX
, RY
}},
6295 {"se_nop", SE_RR(17,0), 0xffff, PPCVLE
, PPCNONE
, {0}},
6296 {"se_or", SE_RR(17,0), SE_RR_MASK
, PPCVLE
, PPCNONE
, {RX
, RY
}},
6297 {"se_andc", SE_RR(17,1), SE_RR_MASK
, PPCVLE
, PPCNONE
, {RX
, RY
}},
6298 {"se_and", SE_RR(17,2), SE_RR_MASK
, PPCVLE
, PPCNONE
, {RX
, RY
}},
6299 {"se_and.", SE_RR(17,3), SE_RR_MASK
, PPCVLE
, PPCNONE
, {RX
, RY
}},
6300 {"se_li", IM7(9), IM7_MASK
, PPCVLE
, PPCNONE
, {RX
, UI7
}},
6302 {"e_lwz", OP(20), OP_MASK
, PPCVLE
, PPCNONE
, {RT
, D
, RA0
}},
6303 {"e_stw", OP(21), OP_MASK
, PPCVLE
, PPCNONE
, {RT
, D
, RA0
}},
6304 {"e_lhz", OP(22), OP_MASK
, PPCVLE
, PPCNONE
, {RT
, D
, RA0
}},
6305 {"e_sth", OP(23), OP_MASK
, PPCVLE
, PPCNONE
, {RT
, D
, RA0
}},
6307 {"se_bclri", SE_IM5(24,0), SE_IM5_MASK
, PPCVLE
, PPCNONE
, {RX
, UI5
}},
6308 {"se_bgeni", SE_IM5(24,1), SE_IM5_MASK
, PPCVLE
, PPCNONE
, {RX
, UI5
}},
6309 {"se_bseti", SE_IM5(25,0), SE_IM5_MASK
, PPCVLE
, PPCNONE
, {RX
, UI5
}},
6310 {"se_btsti", SE_IM5(25,1), SE_IM5_MASK
, PPCVLE
, PPCNONE
, {RX
, UI5
}},
6311 {"se_srwi", SE_IM5(26,0), SE_IM5_MASK
, PPCVLE
, PPCNONE
, {RX
, UI5
}},
6312 {"se_srawi", SE_IM5(26,1), SE_IM5_MASK
, PPCVLE
, PPCNONE
, {RX
, UI5
}},
6313 {"se_slwi", SE_IM5(27,0), SE_IM5_MASK
, PPCVLE
, PPCNONE
, {RX
, UI5
}},
6315 {"e_lis", I16L(28,28), I16L_MASK
, PPCVLE
, PPCNONE
, {RD
, VLEUIMML
}},
6316 {"e_and2is.", I16L(28,29), I16L_MASK
, PPCVLE
, PPCNONE
, {RD
, VLEUIMML
}},
6317 {"e_or2is", I16L(28,26), I16L_MASK
, PPCVLE
, PPCNONE
, {RD
, VLEUIMML
}},
6318 {"e_and2i.", I16L(28,25), I16L_MASK
, PPCVLE
, PPCNONE
, {RD
, VLEUIMML
}},
6319 {"e_or2i", I16L(28,24), I16L_MASK
, PPCVLE
, PPCNONE
, {RD
, VLEUIMML
}},
6320 {"e_cmphl16i", IA16(28,23), IA16_MASK
, PPCVLE
, PPCNONE
, {RA
, VLEUIMM
}},
6321 {"e_cmph16i", IA16(28,22), IA16_MASK
, PPCVLE
, PPCNONE
, {RA
, VLESIMM
}},
6322 {"e_cmpl16i", I16A(28,21), I16A_MASK
, PPCVLE
, PPCNONE
, {RA
, VLEUIMM
}},
6323 {"e_cmplwi", I16A(28,21), I16A_MASK
, PPCVLE
, PPCNONE
, {RA
, VLESIMM
}},
6324 {"e_mull2i", I16A(28,20), I16A_MASK
, PPCVLE
, PPCNONE
, {RA
, VLESIMM
}},
6325 {"e_cmp16i", IA16(28,19), IA16_MASK
, PPCVLE
, PPCNONE
, {RA
, VLESIMM
}},
6326 {"e_cmpwi", IA16(28,19), IA16_MASK
, PPCVLE
, PPCNONE
, {RA
, VLESIMM
}},
6327 {"e_sub2is", I16A(28,18), I16A_MASK
, PPCVLE
, PPCNONE
, {RA
, VLENSIMM
}},
6328 {"e_add2is", I16A(28,18), I16A_MASK
, PPCVLE
, PPCNONE
, {RA
, VLESIMM
}},
6329 {"e_sub2i.", I16A(28,17), I16A_MASK
, PPCVLE
, PPCNONE
, {RA
, VLENSIMM
}},
6330 {"e_add2i.", I16A(28,17), I16A_MASK
, PPCVLE
, PPCNONE
, {RA
, VLESIMM
}},
6331 {"e_li", LI20(28,0), LI20_MASK
, PPCVLE
, PPCNONE
, {RT
, IMM20
}},
6332 {"e_rlwimi", M(29,0), M_MASK
, PPCVLE
, PPCNONE
, {RA
, RS
, SH
, MB
, ME
}},
6333 {"e_rlwinm", M(29,1), M_MASK
, PPCVLE
, PPCNONE
, {RA
, RT
, SH
, MBE
, ME
}},
6334 {"e_b", BD24(30,0,0), BD24_MASK
, PPCVLE
, PPCNONE
, {B24
}},
6335 {"e_bl", BD24(30,0,1), BD24_MASK
, PPCVLE
, PPCNONE
, {B24
}},
6336 {"e_bdnz", EBD15(30,8,BO32DNZ
,0), EBD15_MASK
, PPCVLE
, PPCNONE
, {B15
}},
6337 {"e_bdnzl", EBD15(30,8,BO32DNZ
,1), EBD15_MASK
, PPCVLE
, PPCNONE
, {B15
}},
6338 {"e_bdz", EBD15(30,8,BO32DZ
,0), EBD15_MASK
, PPCVLE
, PPCNONE
, {B15
}},
6339 {"e_bdzl", EBD15(30,8,BO32DZ
,1), EBD15_MASK
, PPCVLE
, PPCNONE
, {B15
}},
6340 {"e_bge", EBD15BI(30,8,BO32F
,CBLT
,0), EBD15BI_MASK
, PPCVLE
, PPCNONE
, {CRS
,B15
}},
6341 {"e_bgel", EBD15BI(30,8,BO32F
,CBLT
,1), EBD15BI_MASK
, PPCVLE
, PPCNONE
, {CRS
,B15
}},
6342 {"e_bnl", EBD15BI(30,8,BO32F
,CBLT
,0), EBD15BI_MASK
, PPCVLE
, PPCNONE
, {CRS
,B15
}},
6343 {"e_bnll", EBD15BI(30,8,BO32F
,CBLT
,1), EBD15BI_MASK
, PPCVLE
, PPCNONE
, {CRS
,B15
}},
6344 {"e_blt", EBD15BI(30,8,BO32T
,CBLT
,0), EBD15BI_MASK
, PPCVLE
, PPCNONE
, {CRS
,B15
}},
6345 {"e_bltl", EBD15BI(30,8,BO32T
,CBLT
,1), EBD15BI_MASK
, PPCVLE
, PPCNONE
, {CRS
,B15
}},
6346 {"e_bgt", EBD15BI(30,8,BO32T
,CBGT
,0), EBD15BI_MASK
, PPCVLE
, PPCNONE
, {CRS
,B15
}},
6347 {"e_bgtl", EBD15BI(30,8,BO32T
,CBGT
,1), EBD15BI_MASK
, PPCVLE
, PPCNONE
, {CRS
,B15
}},
6348 {"e_ble", EBD15BI(30,8,BO32F
,CBGT
,0), EBD15BI_MASK
, PPCVLE
, PPCNONE
, {CRS
,B15
}},
6349 {"e_blel", EBD15BI(30,8,BO32F
,CBGT
,1), EBD15BI_MASK
, PPCVLE
, PPCNONE
, {CRS
,B15
}},
6350 {"e_bng", EBD15BI(30,8,BO32F
,CBGT
,0), EBD15BI_MASK
, PPCVLE
, PPCNONE
, {CRS
,B15
}},
6351 {"e_bngl", EBD15BI(30,8,BO32F
,CBGT
,1), EBD15BI_MASK
, PPCVLE
, PPCNONE
, {CRS
,B15
}},
6352 {"e_bne", EBD15BI(30,8,BO32F
,CBEQ
,0), EBD15BI_MASK
, PPCVLE
, PPCNONE
, {CRS
,B15
}},
6353 {"e_bnel", EBD15BI(30,8,BO32F
,CBEQ
,1), EBD15BI_MASK
, PPCVLE
, PPCNONE
, {CRS
,B15
}},
6354 {"e_beq", EBD15BI(30,8,BO32T
,CBEQ
,0), EBD15BI_MASK
, PPCVLE
, PPCNONE
, {CRS
,B15
}},
6355 {"e_beql", EBD15BI(30,8,BO32T
,CBEQ
,1), EBD15BI_MASK
, PPCVLE
, PPCNONE
, {CRS
,B15
}},
6356 {"e_bso", EBD15BI(30,8,BO32T
,CBSO
,0), EBD15BI_MASK
, PPCVLE
, PPCNONE
, {CRS
,B15
}},
6357 {"e_bsol", EBD15BI(30,8,BO32T
,CBSO
,1), EBD15BI_MASK
, PPCVLE
, PPCNONE
, {CRS
,B15
}},
6358 {"e_bun", EBD15BI(30,8,BO32T
,CBSO
,0), EBD15BI_MASK
, PPCVLE
, PPCNONE
, {CRS
,B15
}},
6359 {"e_bunl", EBD15BI(30,8,BO32T
,CBSO
,1), EBD15BI_MASK
, PPCVLE
, PPCNONE
, {CRS
,B15
}},
6360 {"e_bns", EBD15BI(30,8,BO32F
,CBSO
,0), EBD15BI_MASK
, PPCVLE
, PPCNONE
, {CRS
,B15
}},
6361 {"e_bnsl", EBD15BI(30,8,BO32F
,CBSO
,1), EBD15BI_MASK
, PPCVLE
, PPCNONE
, {CRS
,B15
}},
6362 {"e_bnu", EBD15BI(30,8,BO32F
,CBSO
,0), EBD15BI_MASK
, PPCVLE
, PPCNONE
, {CRS
,B15
}},
6363 {"e_bnul", EBD15BI(30,8,BO32F
,CBSO
,1), EBD15BI_MASK
, PPCVLE
, PPCNONE
, {CRS
,B15
}},
6364 {"e_bc", BD15(30,8,0), BD15_MASK
, PPCVLE
, PPCNONE
, {BO32
, BI32
, B15
}},
6365 {"e_bcl", BD15(30,8,1), BD15_MASK
, PPCVLE
, PPCNONE
, {BO32
, BI32
, B15
}},
6367 {"e_bf", EBD15(30,8,BO32F
,0), EBD15_MASK
, PPCVLE
, PPCNONE
, {BI32
,B15
}},
6368 {"e_bfl", EBD15(30,8,BO32F
,1), EBD15_MASK
, PPCVLE
, PPCNONE
, {BI32
,B15
}},
6369 {"e_bt", EBD15(30,8,BO32T
,0), EBD15_MASK
, PPCVLE
, PPCNONE
, {BI32
,B15
}},
6370 {"e_btl", EBD15(30,8,BO32T
,1), EBD15_MASK
, PPCVLE
, PPCNONE
, {BI32
,B15
}},
6372 {"e_cmph", X(31,14), X_MASK
, PPCVLE
, PPCNONE
, {CRD
, RA
, RB
}},
6373 {"e_cmphl", X(31,46), X_MASK
, PPCVLE
, PPCNONE
, {CRD
, RA
, RB
}},
6374 {"e_crandc", XL(31,129), XL_MASK
, PPCVLE
, PPCNONE
, {BT
, BA
, BB
}},
6375 {"e_crnand", XL(31,225), XL_MASK
, PPCVLE
, PPCNONE
, {BT
, BA
, BB
}},
6376 {"e_crnot", XL(31,33), XL_MASK
, PPCVLE
, PPCNONE
, {BT
, BA
, BBA
}},
6377 {"e_crnor", XL(31,33), XL_MASK
, PPCVLE
, PPCNONE
, {BT
, BA
, BB
}},
6378 {"e_crclr", XL(31,193), XL_MASK
, PPCVLE
, PPCNONE
, {BT
, BAT
, BBA
}},
6379 {"e_crxor", XL(31,193), XL_MASK
, PPCVLE
, PPCNONE
, {BT
, BA
, BB
}},
6380 {"e_mcrf", XL(31,16), XL_MASK
, PPCVLE
, PPCNONE
, {CRD
, CR
}},
6381 {"e_slwi", EX(31,112), EX_MASK
, PPCVLE
, PPCNONE
, {RA
, RS
, SH
}},
6382 {"e_slwi.", EX(31,113), EX_MASK
, PPCVLE
, PPCNONE
, {RA
, RS
, SH
}},
6384 {"e_crand", XL(31,257), XL_MASK
, PPCVLE
, PPCNONE
, {BT
, BA
, BB
}},
6386 {"e_rlw", EX(31,560), EX_MASK
, PPCVLE
, PPCNONE
, {RA
, RS
, RB
}},
6387 {"e_rlw.", EX(31,561), EX_MASK
, PPCVLE
, PPCNONE
, {RA
, RS
, RB
}},
6389 {"e_crset", XL(31,289), XL_MASK
, PPCVLE
, PPCNONE
, {BT
, BAT
, BBA
}},
6390 {"e_creqv", XL(31,289), XL_MASK
, PPCVLE
, PPCNONE
, {BT
, BA
, BB
}},
6392 {"e_rlwi", EX(31,624), EX_MASK
, PPCVLE
, PPCNONE
, {RA
, RS
, SH
}},
6393 {"e_rlwi.", EX(31,625), EX_MASK
, PPCVLE
, PPCNONE
, {RA
, RS
, SH
}},
6395 {"e_crorc", XL(31,417), XL_MASK
, PPCVLE
, PPCNONE
, {BT
, BA
, BB
}},
6397 {"e_crmove", XL(31,449), XL_MASK
, PPCVLE
, PPCNONE
, {BT
, BA
, BBA
}},
6398 {"e_cror", XL(31,449), XL_MASK
, PPCVLE
, PPCNONE
, {BT
, BA
, BB
}},
6400 {"mtmas1", XSPR(31,467,625), XSPR_MASK
, PPCVLE
, PPCNONE
, {RS
}},
6402 {"e_srwi", EX(31,1136), EX_MASK
, PPCVLE
, PPCNONE
, {RA
, RS
, SH
}},
6403 {"e_srwi.", EX(31,1137), EX_MASK
, PPCVLE
, PPCNONE
, {RA
, RS
, SH
}},
6405 {"se_lbz", SD4(8), SD4_MASK
, PPCVLE
, PPCNONE
, {RZ
, SE_SD
, RX
}},
6407 {"se_stb", SD4(9), SD4_MASK
, PPCVLE
, PPCNONE
, {RZ
, SE_SD
, RX
}},
6409 {"se_lhz", SD4(10), SD4_MASK
, PPCVLE
, PPCNONE
, {RZ
, SE_SDH
, RX
}},
6411 {"se_sth", SD4(11), SD4_MASK
, PPCVLE
, PPCNONE
, {RZ
, SE_SDH
, RX
}},
6413 {"se_lwz", SD4(12), SD4_MASK
, PPCVLE
, PPCNONE
, {RZ
, SE_SDW
, RX
}},
6415 {"se_stw", SD4(13), SD4_MASK
, PPCVLE
, PPCNONE
, {RZ
, SE_SDW
, RX
}},
6417 {"se_bge", EBD8IO(28,0,0), EBD8IO3_MASK
, PPCVLE
, PPCNONE
, {B8
}},
6418 {"se_bnl", EBD8IO(28,0,0), EBD8IO3_MASK
, PPCVLE
, PPCNONE
, {B8
}},
6419 {"se_ble", EBD8IO(28,0,1), EBD8IO3_MASK
, PPCVLE
, PPCNONE
, {B8
}},
6420 {"se_bng", EBD8IO(28,0,1), EBD8IO3_MASK
, PPCVLE
, PPCNONE
, {B8
}},
6421 {"se_bne", EBD8IO(28,0,2), EBD8IO3_MASK
, PPCVLE
, PPCNONE
, {B8
}},
6422 {"se_bns", EBD8IO(28,0,3), EBD8IO3_MASK
, PPCVLE
, PPCNONE
, {B8
}},
6423 {"se_bnu", EBD8IO(28,0,3), EBD8IO3_MASK
, PPCVLE
, PPCNONE
, {B8
}},
6424 {"se_bf", EBD8IO(28,0,0), EBD8IO2_MASK
, PPCVLE
, PPCNONE
, {BI16
, B8
}},
6425 {"se_blt", EBD8IO(28,1,0), EBD8IO3_MASK
, PPCVLE
, PPCNONE
, {B8
}},
6426 {"se_bgt", EBD8IO(28,1,1), EBD8IO3_MASK
, PPCVLE
, PPCNONE
, {B8
}},
6427 {"se_beq", EBD8IO(28,1,2), EBD8IO3_MASK
, PPCVLE
, PPCNONE
, {B8
}},
6428 {"se_bso", EBD8IO(28,1,3), EBD8IO3_MASK
, PPCVLE
, PPCNONE
, {B8
}},
6429 {"se_bun", EBD8IO(28,1,3), EBD8IO3_MASK
, PPCVLE
, PPCNONE
, {B8
}},
6430 {"se_bt", EBD8IO(28,1,0), EBD8IO2_MASK
, PPCVLE
, PPCNONE
, {BI16
, B8
}},
6431 {"se_bc", BD8IO(28), BD8IO_MASK
, PPCVLE
, PPCNONE
, {BO16
, BI16
, B8
}},
6432 {"se_b", BD8(58,0,0), BD8_MASK
, PPCVLE
, PPCNONE
, {B8
}},
6433 {"se_bl", BD8(58,0,1), BD8_MASK
, PPCVLE
, PPCNONE
, {B8
}},
6436 const int vle_num_opcodes
=
6437 sizeof (vle_opcodes
) / sizeof (vle_opcodes
[0]);
6439 /* The macro table. This is only used by the assembler. */
6441 /* The expressions of the form (-x ! 31) & (x | 31) have the value 0
6442 when x=0; 32-x when x is between 1 and 31; are negative if x is
6443 negative; and are 32 or more otherwise. This is what you want
6444 when, for instance, you are emulating a right shift by a
6445 rotate-left-and-mask, because the underlying instructions support
6446 shifts of size 0 but not shifts of size 32. By comparison, when
6447 extracting x bits from some word you want to use just 32-x, because
6448 the underlying instructions don't support extracting 0 bits but do
6449 support extracting the whole word (32 bits in this case). */
6451 const struct powerpc_macro powerpc_macros
[] = {
6452 {"extldi", 4, PPC64
, "rldicr %0,%1,%3,(%2)-1"},
6453 {"extldi.", 4, PPC64
, "rldicr. %0,%1,%3,(%2)-1"},
6454 {"extrdi", 4, PPC64
, "rldicl %0,%1,((%2)+(%3))&((%2)+(%3)<>64),64-(%2)"},
6455 {"extrdi.", 4, PPC64
, "rldicl. %0,%1,((%2)+(%3))&((%2)+(%3)<>64),64-(%2)"},
6456 {"insrdi", 4, PPC64
, "rldimi %0,%1,64-((%2)+(%3)),%3"},
6457 {"insrdi.", 4, PPC64
, "rldimi. %0,%1,64-((%2)+(%3)),%3"},
6458 {"rotrdi", 3, PPC64
, "rldicl %0,%1,(-(%2)!63)&((%2)|63),0"},
6459 {"rotrdi.", 3, PPC64
, "rldicl. %0,%1,(-(%2)!63)&((%2)|63),0"},
6460 {"sldi", 3, PPC64
, "rldicr %0,%1,%2,63-(%2)"},
6461 {"sldi.", 3, PPC64
, "rldicr. %0,%1,%2,63-(%2)"},
6462 {"srdi", 3, PPC64
, "rldicl %0,%1,(-(%2)!63)&((%2)|63),%2"},
6463 {"srdi.", 3, PPC64
, "rldicl. %0,%1,(-(%2)!63)&((%2)|63),%2"},
6464 {"clrrdi", 3, PPC64
, "rldicr %0,%1,0,63-(%2)"},
6465 {"clrrdi.", 3, PPC64
, "rldicr. %0,%1,0,63-(%2)"},
6466 {"clrlsldi", 4, PPC64
, "rldic %0,%1,%3,(%2)-(%3)"},
6467 {"clrlsldi.",4, PPC64
, "rldic. %0,%1,%3,(%2)-(%3)"},
6469 {"extlwi", 4, PPCCOM
, "rlwinm %0,%1,%3,0,(%2)-1"},
6470 {"extlwi.", 4, PPCCOM
, "rlwinm. %0,%1,%3,0,(%2)-1"},
6471 {"extrwi", 4, PPCCOM
, "rlwinm %0,%1,((%2)+(%3))&((%2)+(%3)<>32),32-(%2),31"},
6472 {"extrwi.", 4, PPCCOM
, "rlwinm. %0,%1,((%2)+(%3))&((%2)+(%3)<>32),32-(%2),31"},
6473 {"inslwi", 4, PPCCOM
, "rlwimi %0,%1,(-(%3)!31)&((%3)|31),%3,(%2)+(%3)-1"},
6474 {"inslwi.", 4, PPCCOM
, "rlwimi. %0,%1,(-(%3)!31)&((%3)|31),%3,(%2)+(%3)-1"},
6475 {"insrwi", 4, PPCCOM
, "rlwimi %0,%1,32-((%2)+(%3)),%3,(%2)+(%3)-1"},
6476 {"insrwi.", 4, PPCCOM
, "rlwimi. %0,%1,32-((%2)+(%3)),%3,(%2)+(%3)-1"},
6477 {"rotrwi", 3, PPCCOM
, "rlwinm %0,%1,(-(%2)!31)&((%2)|31),0,31"},
6478 {"rotrwi.", 3, PPCCOM
, "rlwinm. %0,%1,(-(%2)!31)&((%2)|31),0,31"},
6479 {"slwi", 3, PPCCOM
, "rlwinm %0,%1,%2,0,31-(%2)"},
6480 {"sli", 3, PWRCOM
, "rlinm %0,%1,%2,0,31-(%2)"},
6481 {"slwi.", 3, PPCCOM
, "rlwinm. %0,%1,%2,0,31-(%2)"},
6482 {"sli.", 3, PWRCOM
, "rlinm. %0,%1,%2,0,31-(%2)"},
6483 {"srwi", 3, PPCCOM
, "rlwinm %0,%1,(-(%2)!31)&((%2)|31),%2,31"},
6484 {"sri", 3, PWRCOM
, "rlinm %0,%1,(-(%2)!31)&((%2)|31),%2,31"},
6485 {"srwi.", 3, PPCCOM
, "rlwinm. %0,%1,(-(%2)!31)&((%2)|31),%2,31"},
6486 {"sri.", 3, PWRCOM
, "rlinm. %0,%1,(-(%2)!31)&((%2)|31),%2,31"},
6487 {"clrrwi", 3, PPCCOM
, "rlwinm %0,%1,0,0,31-(%2)"},
6488 {"clrrwi.", 3, PPCCOM
, "rlwinm. %0,%1,0,0,31-(%2)"},
6489 {"clrlslwi", 4, PPCCOM
, "rlwinm %0,%1,%3,(%2)-(%3),31-(%3)"},
6490 {"clrlslwi.",4, PPCCOM
, "rlwinm. %0,%1,%3,(%2)-(%3),31-(%3)"},
6492 {"e_extlwi", 4, PPCVLE
, "e_rlwinm %0,%1,%3,0,(%2)-1"},
6493 {"e_extrwi", 4, PPCVLE
, "e_rlwinm %0,%1,((%2)+(%3))&((%2)+(%3)<>32),32-(%2),31"},
6494 {"e_inslwi", 4, PPCVLE
, "e_rlwimi %0,%1,(-(%3)!31)&((%3)|31),%3,(%2)+(%3)-1"},
6495 {"e_insrwi", 4, PPCVLE
, "e_rlwimi %0,%1,32-((%2)+(%3)),%3,(%2)+(%3)-1"},
6496 {"e_rotlwi", 3, PPCVLE
, "e_rlwinm %0,%1,%2,0,31"},
6497 {"e_rotrwi", 3, PPCVLE
, "e_rlwinm %0,%1,(-(%2)!31)&((%2)|31),0,31"},
6498 {"e_slwi", 3, PPCVLE
, "e_rlwinm %0,%1,%2,0,31-(%2)"},
6499 {"e_srwi", 3, PPCVLE
, "e_rlwinm %0,%1,(-(%2)!31)&((%2)|31),%2,31"},
6500 {"e_clrlwi", 3, PPCVLE
, "e_rlwinm %0,%1,0,%2,31"},
6501 {"e_clrrwi", 3, PPCVLE
, "e_rlwinm %0,%1,0,0,31-(%2)"},
6502 {"e_clrlslwi",4, PPCVLE
, "e_rlwinm %0,%1,%3,(%2)-(%3),31-(%3)"},
6505 const int powerpc_num_macros
=
6506 sizeof (powerpc_macros
) / sizeof (powerpc_macros
[0]);