1 /* ppc-opc.c -- PowerPC opcode list
2 Copyright (C) 1994-2017 Free Software Foundation, Inc.
3 Written by Ian Lance Taylor, Cygnus Support
5 This file is part of the GNU opcodes library.
7 This library is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3, or (at your option)
12 It is distributed in the hope that it will be useful, but WITHOUT
13 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
14 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
15 License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this file; see the file COPYING. If not, write to the
19 Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston,
20 MA 02110-1301, USA. */
24 #include "opcode/ppc.h"
27 /* This file holds the PowerPC opcode table. The opcode table
28 includes almost all of the extended instruction mnemonics. This
29 permits the disassembler to use them, and simplifies the assembler
30 logic, at the cost of increasing the table size. The table is
31 strictly constant data, so the compiler should be able to put it in
34 This file also holds the operand table. All knowledge about
35 inserting operands into instructions and vice-versa is kept in this
38 /* The functions used to insert and extract complicated operands. */
40 /* The ARX, ARY, RX and RY operands are alternate encodings of GPRs. */
43 insert_arx (uint64_t insn
,
45 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
46 const char **errmsg ATTRIBUTE_UNUSED
)
48 if (value
>= 8 && value
< 24)
49 return insn
| ((value
- 8) & 0xf);
52 *errmsg
= _("invalid register");
58 extract_arx (uint64_t insn
,
59 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
60 int *invalid ATTRIBUTE_UNUSED
)
62 return (insn
& 0xf) + 8;
66 insert_ary (uint64_t insn
,
68 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
69 const char **errmsg ATTRIBUTE_UNUSED
)
71 if (value
>= 8 && value
< 24)
72 return insn
| (((value
- 8) & 0xf) << 4);
75 *errmsg
= _("invalid register");
81 extract_ary (uint64_t insn
,
82 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
83 int *invalid ATTRIBUTE_UNUSED
)
85 return ((insn
>> 4) & 0xf) + 8;
89 insert_rx (uint64_t insn
,
91 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
94 if (value
>= 0 && value
< 8)
96 else if (value
>= 24 && value
<= 31)
97 return insn
| (value
- 16);
100 *errmsg
= _("invalid register");
106 extract_rx (uint64_t insn
,
107 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
108 int *invalid ATTRIBUTE_UNUSED
)
110 int64_t value
= insn
& 0xf;
111 if (value
>= 0 && value
< 8)
118 insert_ry (uint64_t insn
,
120 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
123 if (value
>= 0 && value
< 8)
124 return insn
| (value
<< 4);
125 else if (value
>= 24 && value
<= 31)
126 return insn
| ((value
- 16) << 4);
129 *errmsg
= _("invalid register");
135 extract_ry (uint64_t insn
,
136 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
137 int *invalid ATTRIBUTE_UNUSED
)
139 int64_t value
= (insn
>> 4) & 0xf;
140 if (value
>= 0 && value
< 8)
146 /* The BA field in an XL form instruction when it must be the same as
147 the BT field in the same instruction. This operand is marked FAKE.
148 The insertion function just copies the BT field into the BA field,
149 and the extraction function just checks that the fields are the
153 insert_bat (uint64_t insn
,
154 int64_t value ATTRIBUTE_UNUSED
,
155 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
156 const char **errmsg ATTRIBUTE_UNUSED
)
158 return insn
| (((insn
>> 21) & 0x1f) << 16);
162 extract_bat (uint64_t insn
,
163 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
166 if (((insn
>> 21) & 0x1f) != ((insn
>> 16) & 0x1f))
171 /* The BB field in an XL form instruction when it must be the same as
172 the BA field in the same instruction. This operand is marked FAKE.
173 The insertion function just copies the BA field into the BB field,
174 and the extraction function just checks that the fields are the
178 insert_bba (uint64_t insn
,
179 int64_t value ATTRIBUTE_UNUSED
,
180 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
181 const char **errmsg ATTRIBUTE_UNUSED
)
183 return insn
| (((insn
>> 16) & 0x1f) << 11);
187 extract_bba (uint64_t insn
,
188 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
191 if (((insn
>> 16) & 0x1f) != ((insn
>> 11) & 0x1f))
196 /* The BD field in a B form instruction when the - modifier is used.
197 This modifier means that the branch is not expected to be taken.
198 For chips built to versions of the architecture prior to version 2
199 (ie. not Power4 compatible), we set the y bit of the BO field to 1
200 if the offset is negative. When extracting, we require that the y
201 bit be 1 and that the offset be positive, since if the y bit is 0
202 we just want to print the normal form of the instruction.
203 Power4 compatible targets use two bits, "a", and "t", instead of
204 the "y" bit. "at" == 00 => no hint, "at" == 01 => unpredictable,
205 "at" == 10 => not taken, "at" == 11 => taken. The "t" bit is 00001
206 in BO field, the "a" bit is 00010 for branch on CR(BI) and 01000
207 for branch on CTR. We only handle the taken/not-taken hint here.
208 Note that we don't relax the conditions tested here when
209 disassembling with -Many because insns using extract_bdm and
210 extract_bdp always occur in pairs. One or the other will always
213 #define ISA_V2 (PPC_OPCODE_POWER4 | PPC_OPCODE_E500MC | PPC_OPCODE_TITAN)
216 insert_bdm (uint64_t insn
,
219 const char **errmsg ATTRIBUTE_UNUSED
)
221 if ((dialect
& ISA_V2
) == 0)
223 if ((value
& 0x8000) != 0)
228 if ((insn
& (0x14 << 21)) == (0x04 << 21))
230 else if ((insn
& (0x14 << 21)) == (0x10 << 21))
233 return insn
| (value
& 0xfffc);
237 extract_bdm (uint64_t insn
,
241 if ((dialect
& ISA_V2
) == 0)
243 if (((insn
& (1 << 21)) == 0) != ((insn
& (1 << 15)) == 0))
248 if ((insn
& (0x17 << 21)) != (0x06 << 21)
249 && (insn
& (0x1d << 21)) != (0x18 << 21))
253 return ((insn
& 0xfffc) ^ 0x8000) - 0x8000;
256 /* The BD field in a B form instruction when the + modifier is used.
257 This is like BDM, above, except that the branch is expected to be
261 insert_bdp (uint64_t insn
,
264 const char **errmsg ATTRIBUTE_UNUSED
)
266 if ((dialect
& ISA_V2
) == 0)
268 if ((value
& 0x8000) == 0)
273 if ((insn
& (0x14 << 21)) == (0x04 << 21))
275 else if ((insn
& (0x14 << 21)) == (0x10 << 21))
278 return insn
| (value
& 0xfffc);
282 extract_bdp (uint64_t insn
,
286 if ((dialect
& ISA_V2
) == 0)
288 if (((insn
& (1 << 21)) == 0) == ((insn
& (1 << 15)) == 0))
293 if ((insn
& (0x17 << 21)) != (0x07 << 21)
294 && (insn
& (0x1d << 21)) != (0x19 << 21))
298 return ((insn
& 0xfffc) ^ 0x8000) - 0x8000;
302 valid_bo_pre_v2 (int64_t value
)
304 /* Certain encodings have bits that are required to be zero.
305 These are (z must be zero, y may be anything):
316 if ((value
& 0x14) == 0)
318 else if ((value
& 0x14) == 0x4)
319 return (value
& 0x2) == 0;
320 else if ((value
& 0x14) == 0x10)
321 return (value
& 0x8) == 0;
323 return value
== 0x14;
327 valid_bo_post_v2 (int64_t value
)
329 /* Certain encodings have bits that are required to be zero.
330 These are (z must be zero, a & t may be anything):
341 if ((value
& 0x14) == 0)
342 return (value
& 0x1) == 0;
343 else if ((value
& 0x14) == 0x14)
344 return value
== 0x14;
349 /* Check for legal values of a BO field. */
352 valid_bo (int64_t value
, ppc_cpu_t dialect
, int extract
)
354 int valid_y
= valid_bo_pre_v2 (value
);
355 int valid_at
= valid_bo_post_v2 (value
);
357 /* When disassembling with -Many, accept either encoding on the
358 second pass through opcodes. */
359 if (extract
&& dialect
== ~(ppc_cpu_t
) PPC_OPCODE_ANY
)
360 return valid_y
|| valid_at
;
361 if ((dialect
& ISA_V2
) == 0)
367 /* The BO field in a B form instruction. Warn about attempts to set
368 the field to an illegal value. */
371 insert_bo (uint64_t insn
,
376 if (!valid_bo (value
, dialect
, 0))
377 *errmsg
= _("invalid conditional option");
378 else if (PPC_OP (insn
) == 19 && (insn
& 0x400) && ! (value
& 4))
379 *errmsg
= _("invalid counter access");
380 return insn
| ((value
& 0x1f) << 21);
384 extract_bo (uint64_t insn
,
388 int64_t value
= (insn
>> 21) & 0x1f;
389 if (!valid_bo (value
, dialect
, 1))
394 /* The BO field in a B form instruction when the + or - modifier is
395 used. This is like the BO field, but it must be even. When
396 extracting it, we force it to be even. */
399 insert_boe (uint64_t insn
,
404 if (!valid_bo (value
, dialect
, 0))
405 *errmsg
= _("invalid conditional option");
406 else if (PPC_OP (insn
) == 19 && (insn
& 0x400) && ! (value
& 4))
407 *errmsg
= _("invalid counter access");
408 else if ((value
& 1) != 0)
409 *errmsg
= _("attempt to set y bit when using + or - modifier");
411 return insn
| ((value
& 0x1f) << 21);
415 extract_boe (uint64_t insn
,
419 int64_t value
= (insn
>> 21) & 0x1f;
420 if (!valid_bo (value
, dialect
, 1))
425 /* The DCMX field in a X form instruction when the field is split
426 into separate DC, DM and DX fields. */
429 insert_dcmxs (uint64_t insn
,
431 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
432 const char **errmsg ATTRIBUTE_UNUSED
)
435 | ((value
& 0x1f) << 16)
436 | ((value
& 0x20) >> 3)
441 extract_dcmxs (uint64_t insn
,
442 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
443 int *invalid ATTRIBUTE_UNUSED
)
445 return (insn
& 0x40) | ((insn
<< 3) & 0x20) | ((insn
>> 16) & 0x1f);
448 /* The D field in a DX form instruction when the field is split
449 into separate D0, D1 and D2 fields. */
452 insert_dxd (uint64_t insn
,
454 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
455 const char **errmsg ATTRIBUTE_UNUSED
)
457 return insn
| (value
& 0xffc1) | ((value
& 0x3e) << 15);
461 extract_dxd (uint64_t insn
,
462 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
463 int *invalid ATTRIBUTE_UNUSED
)
465 uint64_t dxd
= (insn
& 0xffc1) | ((insn
>> 15) & 0x3e);
466 return (dxd
^ 0x8000) - 0x8000;
470 insert_dxdn (uint64_t insn
,
472 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
473 const char **errmsg ATTRIBUTE_UNUSED
)
475 return insert_dxd (insn
, -value
, dialect
, errmsg
);
479 extract_dxdn (uint64_t insn
,
480 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
481 int *invalid ATTRIBUTE_UNUSED
)
483 return -extract_dxd (insn
, dialect
, invalid
);
486 /* FXM mask in mfcr and mtcrf instructions. */
489 insert_fxm (uint64_t insn
,
494 /* If we're handling the mfocrf and mtocrf insns ensure that exactly
495 one bit of the mask field is set. */
496 if ((insn
& (1 << 20)) != 0)
498 if (value
== 0 || (value
& -value
) != value
)
500 *errmsg
= _("invalid mask field");
505 /* If only one bit of the FXM field is set, we can use the new form
506 of the instruction, which is faster. Unlike the Power4 branch hint
507 encoding, this is not backward compatible. Do not generate the
508 new form unless -mpower4 has been given, or -many and the two
509 operand form of mfcr was used. */
511 && (value
& -value
) == value
512 && ((dialect
& PPC_OPCODE_POWER4
) != 0
513 || ((dialect
& PPC_OPCODE_ANY
) != 0
514 && (insn
& (0x3ff << 1)) == 19 << 1)))
517 /* Any other value on mfcr is an error. */
518 else if ((insn
& (0x3ff << 1)) == 19 << 1)
520 /* A value of -1 means we used the one operand form of
521 mfcr which is valid. */
523 *errmsg
= _("invalid mfcr mask");
527 return insn
| ((value
& 0xff) << 12);
531 extract_fxm (uint64_t insn
,
532 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
535 int64_t mask
= (insn
>> 12) & 0xff;
537 /* Is this a Power4 insn? */
538 if ((insn
& (1 << 20)) != 0)
540 /* Exactly one bit of MASK should be set. */
541 if (mask
== 0 || (mask
& -mask
) != mask
)
545 /* Check that non-power4 form of mfcr has a zero MASK. */
546 else if ((insn
& (0x3ff << 1)) == 19 << 1)
558 insert_li20 (uint64_t insn
,
560 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
561 const char **errmsg ATTRIBUTE_UNUSED
)
564 | ((value
& 0xf0000) >> 5)
565 | ((value
& 0x0f800) << 5)
570 extract_li20 (uint64_t insn
,
571 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
572 int *invalid ATTRIBUTE_UNUSED
)
574 int64_t ext
= ((insn
& 0x4000) == 0x4000) ? 0xfff00000 : 0x00000000;
577 | (((insn
>> 11) & 0xf) << 16)
578 | (((insn
>> 17) & 0xf) << 12)
579 | (((insn
>> 16) & 0x1) << 11)
583 /* The 2-bit L field in a SYNC or WC field in a WAIT instruction.
584 For SYNC, some L values are reserved:
585 * Value 3 is reserved on newer server cpus.
586 * Values 2 and 3 are reserved on all other cpus. */
589 insert_ls (uint64_t insn
,
594 /* For SYNC, some L values are illegal. */
595 if (((insn
>> 1) & 0x3ff) == 598)
597 int64_t max_lvalue
= (dialect
& PPC_OPCODE_POWER4
) ? 2 : 1;
598 if (value
> max_lvalue
)
600 *errmsg
= _("illegal L operand value");
605 return insn
| ((value
& 0x3) << 21);
609 extract_ls (uint64_t insn
,
613 uint64_t lvalue
= (insn
>> 21) & 3;
615 if (((insn
>> 1) & 0x3ff) == 598)
617 uint64_t max_lvalue
= (dialect
& PPC_OPCODE_POWER4
) ? 2 : 1;
618 if (lvalue
> max_lvalue
)
624 /* The 4-bit E field in a sync instruction that accepts 2 operands.
625 If ESYNC is non-zero, then the L field must be either 0 or 1 and
626 the complement of ESYNC-bit2. */
629 insert_esync (uint64_t insn
,
634 uint64_t ls
= (insn
>> 21) & 0x03;
638 if (((dialect
& PPC_OPCODE_E6500
) != 0 && ls
> 1)
639 || ((dialect
& PPC_OPCODE_POWER9
) != 0 && ls
> 2))
640 *errmsg
= _("illegal L operand value");
645 || (((value
>> 1) & 0x1) ^ ls
) == 0)
646 *errmsg
= _("incompatible L operand value");
648 return insn
| ((value
& 0xf) << 16);
652 extract_esync (uint64_t insn
,
656 uint64_t ls
= (insn
>> 21) & 0x3;
657 uint64_t lvalue
= (insn
>> 16) & 0xf;
661 if (((dialect
& PPC_OPCODE_E6500
) != 0 && ls
> 1)
662 || ((dialect
& PPC_OPCODE_POWER9
) != 0 && ls
> 2))
666 || (((lvalue
>> 1) & 0x1) ^ ls
) == 0)
672 /* The MB and ME fields in an M form instruction expressed as a single
673 operand which is itself a bitmask. The extraction function always
674 marks it as invalid, since we never want to recognize an
675 instruction which uses a field of this type. */
678 insert_mbe (uint64_t insn
,
680 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
684 long mb
, me
, mx
, count
, last
;
690 *errmsg
= _("illegal bitmask");
702 /* mb: location of last 0->1 transition */
703 /* me: location of last 1->0 transition */
704 /* count: # transitions */
706 for (mx
= 0, mask
= (uint64_t) 1 << 31; mx
< 32; ++mx
, mask
>>= 1)
708 if ((uval
& mask
) && !last
)
714 else if (!(uval
& mask
) && last
)
724 if (count
!= 2 && (count
!= 0 || ! last
))
725 *errmsg
= _("illegal bitmask");
727 return insn
| (mb
<< 6) | ((me
- 1) << 1);
731 extract_mbe (uint64_t insn
,
732 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
741 mb
= (insn
>> 6) & 0x1f;
742 me
= (insn
>> 1) & 0x1f;
746 for (i
= mb
; i
<= me
; i
++)
747 ret
|= (uint64_t) 1 << (31 - i
);
749 else if (mb
== me
+ 1)
751 else /* (mb > me + 1) */
754 for (i
= me
+ 1; i
< mb
; i
++)
755 ret
&= ~((uint64_t) 1 << (31 - i
));
760 /* The MB or ME field in an MD or MDS form instruction. The high bit
761 is wrapped to the low end. */
764 insert_mb6 (uint64_t insn
,
766 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
767 const char **errmsg ATTRIBUTE_UNUSED
)
769 return insn
| ((value
& 0x1f) << 6) | (value
& 0x20);
773 extract_mb6 (uint64_t insn
,
774 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
775 int *invalid ATTRIBUTE_UNUSED
)
777 return ((insn
>> 6) & 0x1f) | (insn
& 0x20);
780 /* The NB field in an X form instruction. The value 32 is stored as
784 extract_nb (uint64_t insn
,
785 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
786 int *invalid ATTRIBUTE_UNUSED
)
790 ret
= (insn
>> 11) & 0x1f;
796 /* The NB field in an lswi instruction, which has special value
797 restrictions. The value 32 is stored as 0. */
800 insert_nbi (uint64_t insn
,
802 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
803 const char **errmsg ATTRIBUTE_UNUSED
)
805 int64_t rtvalue
= (insn
>> 21) & 0x1f;
806 int64_t ravalue
= (insn
>> 16) & 0x1f;
810 if (rtvalue
+ (value
+ 3) / 4 > (rtvalue
> ravalue
? ravalue
+ 32
812 *errmsg
= _("address register in load range");
813 return insn
| ((value
& 0x1f) << 11);
816 /* The NSI field in a D form instruction. This is the same as the SI
817 field, only negated. The extraction function always marks it as
818 invalid, since we never want to recognize an instruction which uses
819 a field of this type. */
822 insert_nsi (uint64_t insn
,
824 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
825 const char **errmsg ATTRIBUTE_UNUSED
)
827 return insn
| (-value
& 0xffff);
831 extract_nsi (uint64_t insn
,
832 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
836 return -(((insn
& 0xffff) ^ 0x8000) - 0x8000);
839 /* The RA field in a D or X form instruction which is an updating
840 load, which means that the RA field may not be zero and may not
841 equal the RT field. */
844 insert_ral (uint64_t insn
,
846 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
850 || (uint64_t) value
== ((insn
>> 21) & 0x1f))
851 *errmsg
= "invalid register operand when updating";
852 return insn
| ((value
& 0x1f) << 16);
856 extract_ral (uint64_t insn
,
857 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
860 int64_t rtvalue
= (insn
>> 21) & 0x1f;
861 int64_t ravalue
= (insn
>> 16) & 0x1f;
863 if (rtvalue
== ravalue
|| ravalue
== 0)
868 /* The RA field in an lmw instruction, which has special value
872 insert_ram (uint64_t insn
,
874 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
877 if ((uint64_t) value
>= ((insn
>> 21) & 0x1f))
878 *errmsg
= _("index register in load range");
879 return insn
| ((value
& 0x1f) << 16);
883 extract_ram (uint64_t insn
,
884 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
887 uint64_t rtvalue
= (insn
>> 21) & 0x1f;
888 uint64_t ravalue
= (insn
>> 16) & 0x1f;
890 if (ravalue
>= rtvalue
)
895 /* The RA field in the DQ form lq or an lswx instruction, which have special
896 value restrictions. */
899 insert_raq (uint64_t insn
,
901 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
904 int64_t rtvalue
= (insn
>> 21) & 0x1f;
906 if (value
== rtvalue
)
907 *errmsg
= _("source and target register operands must be different");
908 return insn
| ((value
& 0x1f) << 16);
912 extract_raq (uint64_t insn
,
913 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
916 uint64_t rtvalue
= (insn
>> 21) & 0x1f;
917 uint64_t ravalue
= (insn
>> 16) & 0x1f;
919 if (ravalue
== rtvalue
)
924 /* The RA field in a D or X form instruction which is an updating
925 store or an updating floating point load, which means that the RA
926 field may not be zero. */
929 insert_ras (uint64_t insn
,
931 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
935 *errmsg
= _("invalid register operand when updating");
936 return insn
| ((value
& 0x1f) << 16);
940 extract_ras (uint64_t insn
,
941 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
944 uint64_t ravalue
= (insn
>> 16) & 0x1f;
951 /* The RB field in an X form instruction when it must be the same as
952 the RS field in the instruction. This is used for extended
953 mnemonics like mr. This operand is marked FAKE. The insertion
954 function just copies the BT field into the BA field, and the
955 extraction function just checks that the fields are the same. */
958 insert_rbs (uint64_t insn
,
959 int64_t value ATTRIBUTE_UNUSED
,
960 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
961 const char **errmsg ATTRIBUTE_UNUSED
)
963 return insn
| (((insn
>> 21) & 0x1f) << 11);
967 extract_rbs (uint64_t insn
,
968 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
971 if (((insn
>> 21) & 0x1f) != ((insn
>> 11) & 0x1f))
976 /* The RB field in an lswx instruction, which has special value
980 insert_rbx (uint64_t insn
,
982 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
985 int64_t rtvalue
= (insn
>> 21) & 0x1f;
987 if (value
== rtvalue
)
988 *errmsg
= _("source and target register operands must be different");
989 return insn
| ((value
& 0x1f) << 11);
993 extract_rbx (uint64_t insn
,
994 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
997 uint64_t rtvalue
= (insn
>> 21) & 0x1f;
998 uint64_t rbvalue
= (insn
>> 11) & 0x1f;
1000 if (rbvalue
== rtvalue
)
1005 /* The SCI8 field is made up of SCL and {U,N}I8 fields. */
1007 insert_sci8 (uint64_t insn
,
1009 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1010 const char **errmsg
)
1012 uint64_t fill_scale
= 0;
1013 uint64_t ui8
= value
;
1015 if ((ui8
& 0xffffff00) == 0)
1017 else if ((ui8
& 0xffffff00) == 0xffffff00)
1019 else if ((ui8
& 0xffff00ff) == 0)
1021 fill_scale
= 1 << 8;
1024 else if ((ui8
& 0xffff00ff) == 0xffff00ff)
1026 fill_scale
= 0x400 | (1 << 8);
1029 else if ((ui8
& 0xff00ffff) == 0)
1031 fill_scale
= 2 << 8;
1034 else if ((ui8
& 0xff00ffff) == 0xff00ffff)
1036 fill_scale
= 0x400 | (2 << 8);
1039 else if ((ui8
& 0x00ffffff) == 0)
1041 fill_scale
= 3 << 8;
1044 else if ((ui8
& 0x00ffffff) == 0x00ffffff)
1046 fill_scale
= 0x400 | (3 << 8);
1051 *errmsg
= _("illegal immediate value");
1055 return insn
| fill_scale
| (ui8
& 0xff);
1059 extract_sci8 (uint64_t insn
,
1060 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1061 int *invalid ATTRIBUTE_UNUSED
)
1063 int64_t fill
= insn
& 0x400;
1064 int64_t scale_factor
= (insn
& 0x300) >> 5;
1065 int64_t value
= (insn
& 0xff) << scale_factor
;
1068 value
|= ~((int64_t) 0xff << scale_factor
);
1073 insert_sci8n (uint64_t insn
,
1076 const char **errmsg
)
1078 return insert_sci8 (insn
, -value
, dialect
, errmsg
);
1082 extract_sci8n (uint64_t insn
,
1086 return -extract_sci8 (insn
, dialect
, invalid
);
1090 insert_sd4h (uint64_t insn
,
1092 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1093 const char **errmsg ATTRIBUTE_UNUSED
)
1095 return insn
| ((value
& 0x1e) << 7);
1099 extract_sd4h (uint64_t insn
,
1100 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1101 int *invalid ATTRIBUTE_UNUSED
)
1103 return ((insn
>> 8) & 0xf) << 1;
1107 insert_sd4w (uint64_t insn
,
1109 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1110 const char **errmsg ATTRIBUTE_UNUSED
)
1112 return insn
| ((value
& 0x3c) << 6);
1116 extract_sd4w (uint64_t insn
,
1117 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1118 int *invalid ATTRIBUTE_UNUSED
)
1120 return ((insn
>> 8) & 0xf) << 2;
1124 insert_oimm (uint64_t insn
,
1126 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1127 const char **errmsg ATTRIBUTE_UNUSED
)
1129 return insn
| (((value
- 1) & 0x1f) << 4);
1133 extract_oimm (uint64_t insn
,
1134 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1135 int *invalid ATTRIBUTE_UNUSED
)
1137 return ((insn
>> 4) & 0x1f) + 1;
1140 /* The SH field in an MD form instruction. This is split. */
1143 insert_sh6 (uint64_t insn
,
1145 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1146 const char **errmsg ATTRIBUTE_UNUSED
)
1148 /* SH6 operand in the rldixor instructions. */
1149 if (PPC_OP (insn
) == 4)
1150 return insn
| ((value
& 0x1f) << 6) | ((value
& 0x20) >> 5);
1152 return insn
| ((value
& 0x1f) << 11) | ((value
& 0x20) >> 4);
1156 extract_sh6 (uint64_t insn
,
1157 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1158 int *invalid ATTRIBUTE_UNUSED
)
1160 /* SH6 operand in the rldixor instructions. */
1161 if (PPC_OP (insn
) == 4)
1162 return ((insn
>> 6) & 0x1f) | ((insn
<< 5) & 0x20);
1164 return ((insn
>> 11) & 0x1f) | ((insn
<< 4) & 0x20);
1167 /* The SPR field in an XFX form instruction. This is flipped--the
1168 lower 5 bits are stored in the upper 5 and vice- versa. */
1171 insert_spr (uint64_t insn
,
1173 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1174 const char **errmsg ATTRIBUTE_UNUSED
)
1176 return insn
| ((value
& 0x1f) << 16) | ((value
& 0x3e0) << 6);
1180 extract_spr (uint64_t insn
,
1181 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1182 int *invalid ATTRIBUTE_UNUSED
)
1184 return ((insn
>> 16) & 0x1f) | ((insn
>> 6) & 0x3e0);
1187 /* Some dialects have 8 SPRG registers instead of the standard 4. */
1188 #define ALLOW8_SPRG (PPC_OPCODE_BOOKE | PPC_OPCODE_405)
1191 insert_sprg (uint64_t insn
,
1194 const char **errmsg
)
1197 || (value
> 3 && (dialect
& ALLOW8_SPRG
) == 0))
1198 *errmsg
= _("invalid sprg number");
1200 /* If this is mfsprg4..7 then use spr 260..263 which can be read in
1201 user mode. Anything else must use spr 272..279. */
1202 if (value
<= 3 || (insn
& 0x100) != 0)
1205 return insn
| ((value
& 0x17) << 16);
1209 extract_sprg (uint64_t insn
,
1213 uint64_t val
= (insn
>> 16) & 0x1f;
1215 /* mfsprg can use 260..263 and 272..279. mtsprg only uses spr 272..279
1216 If not BOOKE, 405 or VLE, then both use only 272..275. */
1217 if ((val
- 0x10 > 3 && (dialect
& ALLOW8_SPRG
) == 0)
1218 || (val
- 0x10 > 7 && (insn
& 0x100) != 0)
1225 /* The TBR field in an XFX instruction. This is just like SPR, but it
1229 insert_tbr (uint64_t insn
,
1231 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1232 const char **errmsg
)
1234 if (value
!= 268 && value
!= 269)
1235 *errmsg
= _("invalid tbr number");
1236 return insn
| ((value
& 0x1f) << 16) | ((value
& 0x3e0) << 6);
1240 extract_tbr (uint64_t insn
,
1241 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1244 int64_t ret
= ((insn
>> 16) & 0x1f) | ((insn
>> 6) & 0x3e0);
1245 if (ret
!= 268 && ret
!= 269)
1250 /* The XT and XS fields in an XX1 or XX3 form instruction. This is split. */
1253 insert_xt6 (uint64_t insn
,
1255 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1256 const char **errmsg ATTRIBUTE_UNUSED
)
1258 return insn
| ((value
& 0x1f) << 21) | ((value
& 0x20) >> 5);
1262 extract_xt6 (uint64_t insn
,
1263 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1264 int *invalid ATTRIBUTE_UNUSED
)
1266 return ((insn
<< 5) & 0x20) | ((insn
>> 21) & 0x1f);
1269 /* The XT and XS fields in an DQ form VSX instruction. This is split. */
1271 insert_xtq6 (uint64_t insn
,
1273 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1274 const char **errmsg ATTRIBUTE_UNUSED
)
1276 return insn
| ((value
& 0x1f) << 21) | ((value
& 0x20) >> 2);
1280 extract_xtq6 (uint64_t insn
,
1281 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1282 int *invalid ATTRIBUTE_UNUSED
)
1284 return ((insn
<< 2) & 0x20) | ((insn
>> 21) & 0x1f);
1287 /* The XA field in an XX3 form instruction. This is split. */
1290 insert_xa6 (uint64_t insn
,
1292 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1293 const char **errmsg ATTRIBUTE_UNUSED
)
1295 return insn
| ((value
& 0x1f) << 16) | ((value
& 0x20) >> 3);
1299 extract_xa6 (uint64_t insn
,
1300 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1301 int *invalid ATTRIBUTE_UNUSED
)
1303 return ((insn
<< 3) & 0x20) | ((insn
>> 16) & 0x1f);
1306 /* The XB field in an XX3 form instruction. This is split. */
1309 insert_xb6 (uint64_t insn
,
1311 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1312 const char **errmsg ATTRIBUTE_UNUSED
)
1314 return insn
| ((value
& 0x1f) << 11) | ((value
& 0x20) >> 4);
1318 extract_xb6 (uint64_t insn
,
1319 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1320 int *invalid ATTRIBUTE_UNUSED
)
1322 return ((insn
<< 4) & 0x20) | ((insn
>> 11) & 0x1f);
1325 /* The XB field in an XX3 form instruction when it must be the same as
1326 the XA field in the instruction. This is used for extended
1327 mnemonics like xvmovdp. This operand is marked FAKE. The insertion
1328 function just copies the XA field into the XB field, and the
1329 extraction function just checks that the fields are the same. */
1332 insert_xb6s (uint64_t insn
,
1333 int64_t value ATTRIBUTE_UNUSED
,
1334 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1335 const char **errmsg ATTRIBUTE_UNUSED
)
1337 return insn
| (((insn
>> 16) & 0x1f) << 11) | (((insn
>> 2) & 0x1) << 1);
1341 extract_xb6s (uint64_t insn
,
1342 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1345 if ((((insn
>> 16) & 0x1f) != ((insn
>> 11) & 0x1f))
1346 || (((insn
>> 2) & 0x1) != ((insn
>> 1) & 0x1)))
1351 /* The XC field in an XX4 form instruction. This is split. */
1354 insert_xc6 (uint64_t insn
,
1356 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1357 const char **errmsg ATTRIBUTE_UNUSED
)
1359 return insn
| ((value
& 0x1f) << 6) | ((value
& 0x20) >> 2);
1363 extract_xc6 (uint64_t insn
,
1364 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1365 int *invalid ATTRIBUTE_UNUSED
)
1367 return ((insn
<< 2) & 0x20) | ((insn
>> 6) & 0x1f);
1371 insert_dm (uint64_t insn
,
1373 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1374 const char **errmsg
)
1376 if (value
!= 0 && value
!= 1)
1377 *errmsg
= _("invalid constant");
1378 return insn
| (((value
) ? 3 : 0) << 8);
1382 extract_dm (uint64_t insn
,
1383 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1386 int64_t value
= (insn
>> 8) & 3;
1387 if (value
!= 0 && value
!= 3)
1389 return (value
) ? 1 : 0;
1392 /* The VLESIMM field in an I16A form instruction. This is split. */
1395 insert_vlesi (uint64_t insn
,
1397 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1398 const char **errmsg ATTRIBUTE_UNUSED
)
1400 return insn
| ((value
& 0xf800) << 10) | (value
& 0x7ff);
1404 extract_vlesi (uint64_t insn
,
1405 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1406 int *invalid ATTRIBUTE_UNUSED
)
1408 int64_t value
= ((insn
>> 10) & 0xf800) | (insn
& 0x7ff);
1409 value
= (value
^ 0x8000) - 0x8000;
1414 insert_vlensi (uint64_t insn
,
1416 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1417 const char **errmsg ATTRIBUTE_UNUSED
)
1420 return insn
| ((value
& 0xf800) << 10) | (value
& 0x7ff);
1423 extract_vlensi (uint64_t insn
,
1424 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1425 int *invalid ATTRIBUTE_UNUSED
)
1427 int64_t value
= ((insn
>> 10) & 0xf800) | (insn
& 0x7ff);
1428 value
= (value
^ 0x8000) - 0x8000;
1429 /* Don't use for disassembly. */
1434 /* The VLEUIMM field in an I16A form instruction. This is split. */
1437 insert_vleui (uint64_t insn
,
1439 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1440 const char **errmsg ATTRIBUTE_UNUSED
)
1442 return insn
| ((value
& 0xf800) << 10) | (value
& 0x7ff);
1446 extract_vleui (uint64_t insn
,
1447 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1448 int *invalid ATTRIBUTE_UNUSED
)
1450 return ((insn
>> 10) & 0xf800) | (insn
& 0x7ff);
1453 /* The VLEUIMML field in an I16L form instruction. This is split. */
1456 insert_vleil (uint64_t insn
,
1458 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1459 const char **errmsg ATTRIBUTE_UNUSED
)
1461 return insn
| ((value
& 0xf800) << 5) | (value
& 0x7ff);
1465 extract_vleil (uint64_t insn
,
1466 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1467 int *invalid ATTRIBUTE_UNUSED
)
1469 return ((insn
>> 5) & 0xf800) | (insn
& 0x7ff);
1473 insert_evuimm1_ex0 (uint64_t insn
,
1475 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1476 const char **errmsg
)
1478 if (value
> 0 && value
<= 0x1f)
1479 return insn
| ((value
& 0x1f) << 11);
1482 *errmsg
= _("UIMM = 00000 is illegal");
1488 extract_evuimm1_ex0 (uint64_t insn
,
1489 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1492 int64_t value
= ((insn
>> 11) & 0x1f);
1500 insert_evuimm2_ex0 (uint64_t insn
,
1502 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1503 const char **errmsg
)
1505 if (value
> 0 && value
<= 0x3e)
1506 return insn
| ((value
& 0x3e) << 10);
1509 *errmsg
= _("UIMM = 00000 is illegal");
1515 extract_evuimm2_ex0 (uint64_t insn
,
1516 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1519 int64_t value
= ((insn
>> 10) & 0x3e);
1527 insert_evuimm4_ex0 (uint64_t insn
,
1529 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1530 const char **errmsg
)
1532 if (value
> 0 && value
<= 0x7c)
1533 return insn
| ((value
& 0x7c) << 9);
1536 *errmsg
= _("UIMM = 00000 is illegal");
1542 extract_evuimm4_ex0 (uint64_t insn
,
1543 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1546 int64_t value
= ((insn
>> 9) & 0x7c);
1554 insert_evuimm8_ex0 (uint64_t insn
,
1556 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1557 const char **errmsg
)
1559 if (value
> 0 && value
<= 0xf8)
1560 return insn
| ((value
& 0xf8) << 8);
1563 *errmsg
= _("UIMM = 00000 is illegal");
1569 extract_evuimm8_ex0 (uint64_t insn
,
1570 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1573 int64_t value
= ((insn
>> 8) & 0xf8);
1581 insert_evuimm_lt8 (uint64_t insn
,
1583 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1584 const char **errmsg
)
1586 if (value
>= 0 && value
<= 7)
1587 return insn
| ((value
& 0x7) << 11);
1590 *errmsg
= _("UIMM values >7 are illegal");
1596 extract_evuimm_lt8 (uint64_t insn
,
1597 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1600 int64_t value
= ((insn
>> 11) & 0x1f);
1608 insert_evuimm_lt16 (uint64_t insn
,
1610 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1611 const char **errmsg
)
1613 if (value
>= 0 && value
<= 15)
1614 return insn
| ((value
& 0xf) << 11);
1617 *errmsg
= _("UIMM values >15 are illegal");
1623 extract_evuimm_lt16 (uint64_t insn
,
1624 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1627 int64_t value
= ((insn
>> 11) & 0x1f);
1635 insert_rD_rS_even (uint64_t insn
,
1637 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1638 const char **errmsg
)
1640 if ((value
& 0x1) == 0)
1641 return insn
| ((value
& 0x1e) << 21);
1644 *errmsg
= _("GPR odd is illegal");
1650 extract_rD_rS_even (uint64_t insn
,
1651 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1654 int64_t value
= ((insn
>> 21) & 0x1f);
1655 if ((value
& 0x1) != 0)
1662 insert_off_lsp (uint64_t insn
,
1664 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1665 const char **errmsg
)
1667 if (value
> 0 && value
<= 0x3)
1668 return insn
| (value
& 0x3);
1671 *errmsg
= _("invalid offset");
1677 extract_off_lsp (uint64_t insn
,
1678 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1681 int64_t value
= (insn
& 0x3);
1689 insert_off_spe2 (uint64_t insn
,
1691 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1692 const char **errmsg
)
1694 if (value
> 0 && value
<= 0x7)
1695 return insn
| (value
& 0x7);
1698 *errmsg
= _("invalid offset");
1704 extract_off_spe2 (uint64_t insn
,
1705 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1708 int64_t value
= (insn
& 0x7);
1716 insert_Ddd (uint64_t insn
,
1718 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1719 const char **errmsg
)
1721 if (value
>= 0 && value
<= 0x7)
1722 return insn
| ((value
& 0x3) << 11) | ((value
& 0x4) >> 2);
1725 *errmsg
= _("invalid Ddd value");
1731 extract_Ddd (uint64_t insn
,
1732 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1733 int *invalid ATTRIBUTE_UNUSED
)
1735 return ((insn
>> 11) & 0x3) | ((insn
<< 2) & 0x4);
1738 /* The operands table.
1740 The fields are bitm, shift, insert, extract, flags.
1742 We used to put parens around the various additions, like the one
1743 for BA just below. However, that caused trouble with feeble
1744 compilers with a limit on depth of a parenthesized expression, like
1745 (reportedly) the compiler in Microsoft Developer Studio 5. So we
1746 omit the parens, since the macros are never used in a context where
1747 the addition will be ambiguous. */
1749 const struct powerpc_operand powerpc_operands
[] =
1751 /* The zero index is used to indicate the end of the list of
1754 { 0, 0, NULL
, NULL
, 0 },
1756 /* The BA field in an XL form instruction. */
1757 #define BA UNUSED + 1
1758 /* The BI field in a B form or XL form instruction. */
1760 #define BI_MASK (0x1f << 16)
1761 { 0x1f, 16, NULL
, NULL
, PPC_OPERAND_CR_BIT
},
1763 /* The BA field in an XL form instruction when it must be the same
1764 as the BT field in the same instruction. */
1766 { 0x1f, 16, insert_bat
, extract_bat
, PPC_OPERAND_FAKE
},
1768 /* The BB field in an XL form instruction. */
1770 #define BB_MASK (0x1f << 11)
1771 { 0x1f, 11, NULL
, NULL
, PPC_OPERAND_CR_BIT
},
1773 /* The BB field in an XL form instruction when it must be the same
1774 as the BA field in the same instruction. */
1776 /* The VB field in a VX form instruction when it must be the same
1777 as the VA field in the same instruction. */
1779 { 0x1f, 11, insert_bba
, extract_bba
, PPC_OPERAND_FAKE
},
1781 /* The BD field in a B form instruction. The lower two bits are
1784 { 0xfffc, 0, NULL
, NULL
, PPC_OPERAND_RELATIVE
| PPC_OPERAND_SIGNED
},
1786 /* The BD field in a B form instruction when absolute addressing is
1789 { 0xfffc, 0, NULL
, NULL
, PPC_OPERAND_ABSOLUTE
| PPC_OPERAND_SIGNED
},
1791 /* The BD field in a B form instruction when the - modifier is used.
1792 This sets the y bit of the BO field appropriately. */
1794 { 0xfffc, 0, insert_bdm
, extract_bdm
,
1795 PPC_OPERAND_RELATIVE
| PPC_OPERAND_SIGNED
},
1797 /* The BD field in a B form instruction when the - modifier is used
1798 and absolute address is used. */
1799 #define BDMA BDM + 1
1800 { 0xfffc, 0, insert_bdm
, extract_bdm
,
1801 PPC_OPERAND_ABSOLUTE
| PPC_OPERAND_SIGNED
},
1803 /* The BD field in a B form instruction when the + modifier is used.
1804 This sets the y bit of the BO field appropriately. */
1805 #define BDP BDMA + 1
1806 { 0xfffc, 0, insert_bdp
, extract_bdp
,
1807 PPC_OPERAND_RELATIVE
| PPC_OPERAND_SIGNED
},
1809 /* The BD field in a B form instruction when the + modifier is used
1810 and absolute addressing is used. */
1811 #define BDPA BDP + 1
1812 { 0xfffc, 0, insert_bdp
, extract_bdp
,
1813 PPC_OPERAND_ABSOLUTE
| PPC_OPERAND_SIGNED
},
1815 /* The BF field in an X or XL form instruction. */
1817 /* The CRFD field in an X form instruction. */
1819 /* The CRD field in an XL form instruction. */
1821 { 0x7, 23, NULL
, NULL
, PPC_OPERAND_CR_REG
},
1823 /* The BF field in an X or XL form instruction. */
1825 { 0x7, 23, NULL
, NULL
, 0 },
1827 /* An optional BF field. This is used for comparison instructions,
1828 in which an omitted BF field is taken as zero. */
1830 { 0x7, 23, NULL
, NULL
, PPC_OPERAND_CR_REG
| PPC_OPERAND_OPTIONAL
},
1832 /* The BFA field in an X or XL form instruction. */
1834 { 0x7, 18, NULL
, NULL
, PPC_OPERAND_CR_REG
},
1836 /* The BO field in a B form instruction. Certain values are
1839 #define BO_MASK (0x1f << 21)
1840 { 0x1f, 21, insert_bo
, extract_bo
, 0 },
1842 /* The BO field in a B form instruction when the + or - modifier is
1843 used. This is like the BO field, but it must be even. */
1845 { 0x1e, 21, insert_boe
, extract_boe
, 0 },
1847 /* The RM field in an X form instruction. */
1850 { 0x3, 11, NULL
, NULL
, 0 },
1853 { 0x3, 11, NULL
, NULL
, PPC_OPERAND_OPTIONAL
},
1855 /* The BT field in an X or XL form instruction. */
1857 { 0x1f, 21, NULL
, NULL
, PPC_OPERAND_CR_BIT
},
1859 /* The BI16 field in a BD8 form instruction. */
1861 { 0x3, 8, NULL
, NULL
, PPC_OPERAND_CR_BIT
},
1863 /* The BI32 field in a BD15 form instruction. */
1864 #define BI32 BI16 + 1
1865 { 0xf, 16, NULL
, NULL
, PPC_OPERAND_CR_BIT
},
1867 /* The BO32 field in a BD15 form instruction. */
1868 #define BO32 BI32 + 1
1869 { 0x3, 20, NULL
, NULL
, 0 },
1871 /* The B8 field in a BD8 form instruction. */
1873 { 0x1fe, -1, NULL
, NULL
, PPC_OPERAND_RELATIVE
| PPC_OPERAND_SIGNED
},
1875 /* The B15 field in a BD15 form instruction. The lowest bit is
1878 { 0xfffe, 0, NULL
, NULL
, PPC_OPERAND_RELATIVE
| PPC_OPERAND_SIGNED
},
1880 /* The B24 field in a BD24 form instruction. The lowest bit is
1883 { 0x1fffffe, 0, NULL
, NULL
, PPC_OPERAND_RELATIVE
| PPC_OPERAND_SIGNED
},
1885 /* The condition register number portion of the BI field in a B form
1886 or XL form instruction. This is used for the extended
1887 conditional branch mnemonics, which set the lower two bits of the
1888 BI field. This field is optional. */
1890 { 0x7, 18, NULL
, NULL
, PPC_OPERAND_CR_REG
| PPC_OPERAND_OPTIONAL
},
1892 /* The CRB field in an X form instruction. */
1894 /* The MB field in an M form instruction. */
1896 #define MB_MASK (0x1f << 6)
1897 { 0x1f, 6, NULL
, NULL
, 0 },
1899 /* The CRD32 field in an XL form instruction. */
1900 #define CRD32 CRB + 1
1901 { 0x3, 21, NULL
, NULL
, PPC_OPERAND_CR_REG
},
1903 /* The CRFS field in an X form instruction. */
1904 #define CRFS CRD32 + 1
1905 { 0x7, 0, NULL
, NULL
, PPC_OPERAND_CR_REG
},
1907 #define CRS CRFS + 1
1908 { 0x3, 18, NULL
, NULL
, PPC_OPERAND_CR_REG
| PPC_OPERAND_OPTIONAL
},
1910 /* The CT field in an X form instruction. */
1912 /* The MO field in an mbar instruction. */
1914 { 0x1f, 21, NULL
, NULL
, PPC_OPERAND_OPTIONAL
},
1916 /* The D field in a D form instruction. This is a displacement off
1917 a register, and implies that the next operand is a register in
1920 { 0xffff, 0, NULL
, NULL
, PPC_OPERAND_PARENS
| PPC_OPERAND_SIGNED
},
1922 /* The D8 field in a D form instruction. This is a displacement off
1923 a register, and implies that the next operand is a register in
1926 { 0xff, 0, NULL
, NULL
, PPC_OPERAND_PARENS
| PPC_OPERAND_SIGNED
},
1928 /* The DCMX field in an X form instruction. */
1930 { 0x7f, 16, NULL
, NULL
, 0 },
1932 /* The split DCMX field in an X form instruction. */
1933 #define DCMXS DCMX + 1
1934 { 0x7f, PPC_OPSHIFT_INV
, insert_dcmxs
, extract_dcmxs
, 0 },
1936 /* The DQ field in a DQ form instruction. This is like D, but the
1937 lower four bits are forced to zero. */
1938 #define DQ DCMXS + 1
1939 { 0xfff0, 0, NULL
, NULL
,
1940 PPC_OPERAND_PARENS
| PPC_OPERAND_SIGNED
| PPC_OPERAND_DQ
},
1942 /* The DS field in a DS form instruction. This is like D, but the
1943 lower two bits are forced to zero. */
1945 { 0xfffc, 0, NULL
, NULL
,
1946 PPC_OPERAND_PARENS
| PPC_OPERAND_SIGNED
| PPC_OPERAND_DS
},
1948 /* The DUIS or BHRBE fields in a XFX form instruction, 10 bits
1949 unsigned imediate */
1952 { 0x3ff, 11, NULL
, NULL
, 0 },
1954 /* The split D field in a DX form instruction. */
1955 #define DXD DUIS + 1
1956 { 0xffff, PPC_OPSHIFT_INV
, insert_dxd
, extract_dxd
,
1957 PPC_OPERAND_SIGNED
| PPC_OPERAND_SIGNOPT
},
1959 /* The split ND field in a DX form instruction.
1960 This is the same as the DX field, only negated. */
1961 #define NDXD DXD + 1
1962 { 0xffff, PPC_OPSHIFT_INV
, insert_dxdn
, extract_dxdn
,
1963 PPC_OPERAND_NEGATIVE
| PPC_OPERAND_SIGNED
| PPC_OPERAND_SIGNOPT
},
1965 /* The E field in a wrteei instruction. */
1966 /* And the W bit in the pair singles instructions. */
1967 /* And the ST field in a VX form instruction. */
1971 { 0x1, 15, NULL
, NULL
, 0 },
1973 /* The FL1 field in a POWER SC form instruction. */
1975 /* The U field in an X form instruction. */
1977 { 0xf, 12, NULL
, NULL
, 0 },
1979 /* The FL2 field in a POWER SC form instruction. */
1981 { 0x7, 2, NULL
, NULL
, 0 },
1983 /* The FLM field in an XFL form instruction. */
1985 { 0xff, 17, NULL
, NULL
, 0 },
1987 /* The FRA field in an X or A form instruction. */
1989 #define FRA_MASK (0x1f << 16)
1990 { 0x1f, 16, NULL
, NULL
, PPC_OPERAND_FPR
},
1992 /* The FRAp field of DFP instructions. */
1993 #define FRAp FRA + 1
1994 { 0x1e, 16, NULL
, NULL
, PPC_OPERAND_FPR
},
1996 /* The FRB field in an X or A form instruction. */
1997 #define FRB FRAp + 1
1998 #define FRB_MASK (0x1f << 11)
1999 { 0x1f, 11, NULL
, NULL
, PPC_OPERAND_FPR
},
2001 /* The FRBp field of DFP instructions. */
2002 #define FRBp FRB + 1
2003 { 0x1e, 11, NULL
, NULL
, PPC_OPERAND_FPR
},
2005 /* The FRC field in an A form instruction. */
2006 #define FRC FRBp + 1
2007 #define FRC_MASK (0x1f << 6)
2008 { 0x1f, 6, NULL
, NULL
, PPC_OPERAND_FPR
},
2010 /* The FRS field in an X form instruction or the FRT field in a D, X
2011 or A form instruction. */
2014 { 0x1f, 21, NULL
, NULL
, PPC_OPERAND_FPR
},
2016 /* The FRSp field of stfdp or the FRTp field of lfdp and DFP
2018 #define FRSp FRS + 1
2020 { 0x1e, 21, NULL
, NULL
, PPC_OPERAND_FPR
},
2022 /* The FXM field in an XFX instruction. */
2023 #define FXM FRSp + 1
2024 { 0xff, 12, insert_fxm
, extract_fxm
, 0 },
2026 /* Power4 version for mfcr. */
2027 #define FXM4 FXM + 1
2028 { 0xff, 12, insert_fxm
, extract_fxm
,
2029 PPC_OPERAND_OPTIONAL
| PPC_OPERAND_OPTIONAL_VALUE
},
2030 /* If the FXM4 operand is ommitted, use the sentinel value -1. */
2031 { -1, -1, NULL
, NULL
, 0},
2033 /* The IMM20 field in an LI instruction. */
2034 #define IMM20 FXM4 + 2
2035 { 0xfffff, PPC_OPSHIFT_INV
, insert_li20
, extract_li20
, PPC_OPERAND_SIGNED
},
2037 /* The L field in a D or X form instruction. */
2039 { 0x1, 21, NULL
, NULL
, 0 },
2041 /* The optional L field in tlbie and tlbiel instructions. */
2043 /* The R field in a HTM X form instruction. */
2045 { 0x1, 21, NULL
, NULL
, PPC_OPERAND_OPTIONAL
},
2047 /* The optional (for 32-bit) L field in cmp[l][i] instructions. */
2048 #define L32OPT LOPT + 1
2049 { 0x1, 21, NULL
, NULL
, PPC_OPERAND_OPTIONAL
| PPC_OPERAND_OPTIONAL32
},
2051 /* The L field in dcbf instruction. */
2052 #define L2OPT L32OPT + 1
2053 { 0x3, 21, NULL
, NULL
, PPC_OPERAND_OPTIONAL
},
2055 /* The LEV field in a POWER SVC / POWER9 SCV form instruction. */
2056 #define SVC_LEV L2OPT + 1
2057 { 0x7f, 5, NULL
, NULL
, 0 },
2059 /* The LEV field in an SC form instruction. */
2060 #define LEV SVC_LEV + 1
2061 { 0x7f, 5, NULL
, NULL
, PPC_OPERAND_OPTIONAL
},
2063 /* The LI field in an I form instruction. The lower two bits are
2066 { 0x3fffffc, 0, NULL
, NULL
, PPC_OPERAND_RELATIVE
| PPC_OPERAND_SIGNED
},
2068 /* The LI field in an I form instruction when used as an absolute
2071 { 0x3fffffc, 0, NULL
, NULL
, PPC_OPERAND_ABSOLUTE
| PPC_OPERAND_SIGNED
},
2073 /* The LS or WC field in an X (sync or wait) form instruction. */
2076 { 0x3, 21, insert_ls
, extract_ls
, PPC_OPERAND_OPTIONAL
},
2078 /* The ME field in an M form instruction. */
2080 #define ME_MASK (0x1f << 1)
2081 { 0x1f, 1, NULL
, NULL
, 0 },
2083 /* The MB and ME fields in an M form instruction expressed a single
2084 operand which is a bitmask indicating which bits to select. This
2085 is a two operand form using PPC_OPERAND_NEXT. See the
2086 description in opcode/ppc.h for what this means. */
2088 { 0x1f, 6, NULL
, NULL
, PPC_OPERAND_OPTIONAL
| PPC_OPERAND_NEXT
},
2089 { -1, 0, insert_mbe
, extract_mbe
, 0 },
2091 /* The MB or ME field in an MD or MDS form instruction. The high
2092 bit is wrapped to the low end. */
2095 #define MB6_MASK (0x3f << 5)
2096 { 0x3f, 5, insert_mb6
, extract_mb6
, 0 },
2098 /* The NB field in an X form instruction. The value 32 is stored as
2101 { 0x1f, 11, NULL
, extract_nb
, PPC_OPERAND_PLUS1
},
2103 /* The NBI field in an lswi instruction, which has special value
2104 restrictions. The value 32 is stored as 0. */
2106 { 0x1f, 11, insert_nbi
, extract_nb
, PPC_OPERAND_PLUS1
},
2108 /* The NSI field in a D form instruction. This is the same as the
2109 SI field, only negated. */
2111 { 0xffff, 0, insert_nsi
, extract_nsi
,
2112 PPC_OPERAND_NEGATIVE
| PPC_OPERAND_SIGNED
},
2114 /* The NSI field in a D form instruction when we accept a wide range
2115 of positive values. */
2116 #define NSISIGNOPT NSI + 1
2117 { 0xffff, 0, insert_nsi
, extract_nsi
,
2118 PPC_OPERAND_NEGATIVE
| PPC_OPERAND_SIGNED
| PPC_OPERAND_SIGNOPT
},
2120 /* The RA field in an D, DS, DQ, X, XO, M, or MDS form instruction. */
2121 #define RA NSISIGNOPT + 1
2122 #define RA_MASK (0x1f << 16)
2123 { 0x1f, 16, NULL
, NULL
, PPC_OPERAND_GPR
},
2125 /* As above, but 0 in the RA field means zero, not r0. */
2127 { 0x1f, 16, NULL
, NULL
, PPC_OPERAND_GPR_0
},
2129 /* The RA field in the DQ form lq or an lswx instruction, which have
2130 special value restrictions. */
2133 { 0x1f, 16, insert_raq
, extract_raq
, PPC_OPERAND_GPR_0
},
2135 /* The RA field in a D or X form instruction which is an updating
2136 load, which means that the RA field may not be zero and may not
2137 equal the RT field. */
2139 { 0x1f, 16, insert_ral
, extract_ral
, PPC_OPERAND_GPR_0
},
2141 /* The RA field in an lmw instruction, which has special value
2144 { 0x1f, 16, insert_ram
, extract_ram
, PPC_OPERAND_GPR_0
},
2146 /* The RA field in a D or X form instruction which is an updating
2147 store or an updating floating point load, which means that the RA
2148 field may not be zero. */
2150 { 0x1f, 16, insert_ras
, extract_ras
, PPC_OPERAND_GPR_0
},
2152 /* The RA field of the tlbwe, dccci and iccci instructions,
2153 which are optional. */
2154 #define RAOPT RAS + 1
2155 { 0x1f, 16, NULL
, NULL
, PPC_OPERAND_GPR
| PPC_OPERAND_OPTIONAL
},
2157 /* The RB field in an X, XO, M, or MDS form instruction. */
2158 #define RB RAOPT + 1
2159 #define RB_MASK (0x1f << 11)
2160 { 0x1f, 11, NULL
, NULL
, PPC_OPERAND_GPR
},
2162 /* The RB field in an X form instruction when it must be the same as
2163 the RS field in the instruction. This is used for extended
2164 mnemonics like mr. */
2166 { 0x1f, 11, insert_rbs
, extract_rbs
, PPC_OPERAND_FAKE
},
2168 /* The RB field in an lswx instruction, which has special value
2171 { 0x1f, 11, insert_rbx
, extract_rbx
, PPC_OPERAND_GPR
},
2173 /* The RB field of the dccci and iccci instructions, which are optional. */
2174 #define RBOPT RBX + 1
2175 { 0x1f, 11, NULL
, NULL
, PPC_OPERAND_GPR
| PPC_OPERAND_OPTIONAL
},
2177 /* The RC register field in an maddld, maddhd or maddhdu instruction. */
2178 #define RC RBOPT + 1
2179 { 0x1f, 6, NULL
, NULL
, PPC_OPERAND_GPR
},
2181 /* The RS field in a D, DS, X, XFX, XS, M, MD or MDS form
2182 instruction or the RT field in a D, DS, X, XFX or XO form
2186 #define RT_MASK (0x1f << 21)
2188 { 0x1f, 21, NULL
, NULL
, PPC_OPERAND_GPR
},
2190 #define RD_EVEN RS + 1
2191 #define RS_EVEN RD_EVEN
2192 { 0x1f, 21, insert_rD_rS_even
, extract_rD_rS_even
, PPC_OPERAND_GPR
},
2194 /* The RS and RT fields of the DS form stq and DQ form lq instructions,
2195 which have special value restrictions. */
2196 #define RSQ RS_EVEN + 1
2198 #define Q_MASK (1 << 21)
2199 { 0x1e, 21, NULL
, NULL
, PPC_OPERAND_GPR
},
2201 /* The RS field of the tlbwe instruction, which is optional. */
2204 { 0x1f, 21, NULL
, NULL
, PPC_OPERAND_GPR
| PPC_OPERAND_OPTIONAL
},
2206 /* The RX field of the SE_RR form instruction. */
2208 { 0x1f, PPC_OPSHIFT_INV
, insert_rx
, extract_rx
, PPC_OPERAND_GPR
},
2210 /* The ARX field of the SE_RR form instruction. */
2212 { 0x1f, PPC_OPSHIFT_INV
, insert_arx
, extract_arx
, PPC_OPERAND_GPR
},
2214 /* The RY field of the SE_RR form instruction. */
2217 { 0x1f, PPC_OPSHIFT_INV
, insert_ry
, extract_ry
, PPC_OPERAND_GPR
},
2219 /* The ARY field of the SE_RR form instruction. */
2221 { 0x1f, PPC_OPSHIFT_INV
, insert_ary
, extract_ary
, PPC_OPERAND_GPR
},
2223 /* The SCLSCI8 field in a D form instruction. */
2224 #define SCLSCI8 ARY + 1
2225 { 0xffffffff, PPC_OPSHIFT_INV
, insert_sci8
, extract_sci8
, 0 },
2227 /* The SCLSCI8N field in a D form instruction. This is the same as the
2228 SCLSCI8 field, only negated. */
2229 #define SCLSCI8N SCLSCI8 + 1
2230 { 0xffffffff, PPC_OPSHIFT_INV
, insert_sci8n
, extract_sci8n
,
2231 PPC_OPERAND_NEGATIVE
| PPC_OPERAND_SIGNED
},
2233 /* The SD field of the SD4 form instruction. */
2234 #define SE_SD SCLSCI8N + 1
2235 { 0xf, 8, NULL
, NULL
, PPC_OPERAND_PARENS
},
2237 /* The SD field of the SD4 form instruction, for halfword. */
2238 #define SE_SDH SE_SD + 1
2239 { 0x1e, PPC_OPSHIFT_INV
, insert_sd4h
, extract_sd4h
, PPC_OPERAND_PARENS
},
2241 /* The SD field of the SD4 form instruction, for word. */
2242 #define SE_SDW SE_SDH + 1
2243 { 0x3c, PPC_OPSHIFT_INV
, insert_sd4w
, extract_sd4w
, PPC_OPERAND_PARENS
},
2245 /* The SH field in an X or M form instruction. */
2246 #define SH SE_SDW + 1
2247 #define SH_MASK (0x1f << 11)
2248 /* The other UIMM field in a EVX form instruction. */
2250 /* The FC field in an atomic X form instruction. */
2252 { 0x1f, 11, NULL
, NULL
, 0 },
2254 #define EVUIMM_LT8 SH + 1
2255 { 0x1f, 11, insert_evuimm_lt8
, extract_evuimm_lt8
, 0 },
2257 #define EVUIMM_LT16 EVUIMM_LT8 + 1
2258 { 0x1f, 11, insert_evuimm_lt16
, extract_evuimm_lt16
, 0 },
2260 /* The SI field in a HTM X form instruction. */
2261 #define HTM_SI EVUIMM_LT16 + 1
2262 { 0x1f, 11, NULL
, NULL
, PPC_OPERAND_SIGNED
},
2264 /* The SH field in an MD form instruction. This is split. */
2265 #define SH6 HTM_SI + 1
2266 #define SH6_MASK ((0x1f << 11) | (1 << 1))
2267 { 0x3f, PPC_OPSHIFT_INV
, insert_sh6
, extract_sh6
, 0 },
2269 /* The SH field of some variants of the tlbre and tlbwe
2270 instructions, and the ELEV field of the e_sc instruction. */
2273 { 0x1f, 11, NULL
, NULL
, PPC_OPERAND_OPTIONAL
},
2275 /* The SI field in a D form instruction. */
2277 { 0xffff, 0, NULL
, NULL
, PPC_OPERAND_SIGNED
},
2279 /* The SI field in a D form instruction when we accept a wide range
2280 of positive values. */
2281 #define SISIGNOPT SI + 1
2282 { 0xffff, 0, NULL
, NULL
, PPC_OPERAND_SIGNED
| PPC_OPERAND_SIGNOPT
},
2284 /* The SI8 field in a D form instruction. */
2285 #define SI8 SISIGNOPT + 1
2286 { 0xff, 0, NULL
, NULL
, PPC_OPERAND_SIGNED
},
2288 /* The SPR field in an XFX form instruction. This is flipped--the
2289 lower 5 bits are stored in the upper 5 and vice- versa. */
2293 #define SPR_MASK (0x3ff << 11)
2294 { 0x3ff, 11, insert_spr
, extract_spr
, PPC_OPERAND_SPR
},
2296 /* The BAT index number in an XFX form m[ft]ibat[lu] instruction. */
2297 #define SPRBAT SPR + 1
2298 #define SPRBAT_MASK (0x3 << 17)
2299 { 0x3, 17, NULL
, NULL
, 0 },
2301 /* The SPRG register number in an XFX form m[ft]sprg instruction. */
2302 #define SPRG SPRBAT + 1
2303 { 0x1f, 16, insert_sprg
, extract_sprg
, PPC_OPERAND_SPR
},
2305 /* The SR field in an X form instruction. */
2307 /* The 4-bit UIMM field in a VX form instruction. */
2309 { 0xf, 16, NULL
, NULL
, 0 },
2311 /* The STRM field in an X AltiVec form instruction. */
2313 /* The T field in a tlbilx form instruction. */
2315 /* The L field in wclr instructions. */
2317 { 0x3, 21, NULL
, NULL
, 0 },
2319 /* The ESYNC field in an X (sync) form instruction. */
2320 #define ESYNC STRM + 1
2321 { 0xf, 16, insert_esync
, extract_esync
, PPC_OPERAND_OPTIONAL
},
2323 /* The SV field in a POWER SC form instruction. */
2324 #define SV ESYNC + 1
2325 { 0x3fff, 2, NULL
, NULL
, 0 },
2327 /* The TBR field in an XFX form instruction. This is like the SPR
2328 field, but it is optional. */
2330 { 0x3ff, 11, insert_tbr
, extract_tbr
,
2331 PPC_OPERAND_SPR
| PPC_OPERAND_OPTIONAL
| PPC_OPERAND_OPTIONAL_VALUE
},
2332 /* If the TBR operand is ommitted, use the value 268. */
2333 { -1, 268, NULL
, NULL
, 0},
2335 /* The TO field in a D or X form instruction. */
2338 #define TO_MASK (0x1f << 21)
2339 { 0x1f, 21, NULL
, NULL
, 0 },
2341 /* The UI field in a D form instruction. */
2343 { 0xffff, 0, NULL
, NULL
, 0 },
2345 #define UISIGNOPT UI + 1
2346 { 0xffff, 0, NULL
, NULL
, PPC_OPERAND_SIGNOPT
},
2348 /* The IMM field in an SE_IM5 instruction. */
2349 #define UI5 UISIGNOPT + 1
2350 { 0x1f, 4, NULL
, NULL
, 0 },
2352 /* The OIMM field in an SE_OIM5 instruction. */
2353 #define OIMM5 UI5 + 1
2354 { 0x1f, PPC_OPSHIFT_INV
, insert_oimm
, extract_oimm
, PPC_OPERAND_PLUS1
},
2356 /* The UI7 field in an SE_LI instruction. */
2357 #define UI7 OIMM5 + 1
2358 { 0x7f, 4, NULL
, NULL
, 0 },
2360 /* The VA field in a VA, VX or VXR form instruction. */
2362 { 0x1f, 16, NULL
, NULL
, PPC_OPERAND_VR
},
2364 /* The VB field in a VA, VX or VXR form instruction. */
2366 { 0x1f, 11, NULL
, NULL
, PPC_OPERAND_VR
},
2368 /* The VC field in a VA form instruction. */
2370 { 0x1f, 6, NULL
, NULL
, PPC_OPERAND_VR
},
2372 /* The VD or VS field in a VA, VX, VXR or X form instruction. */
2375 { 0x1f, 21, NULL
, NULL
, PPC_OPERAND_VR
},
2377 /* The SIMM field in a VX form instruction, and TE in Z form. */
2380 { 0x1f, 16, NULL
, NULL
, PPC_OPERAND_SIGNED
},
2382 /* The UIMM field in a VX form instruction. */
2383 #define UIMM SIMM + 1
2385 { 0x1f, 16, NULL
, NULL
, 0 },
2387 /* The 3-bit UIMM field in a VX form instruction. */
2388 #define UIMM3 UIMM + 1
2389 { 0x7, 16, NULL
, NULL
, 0 },
2391 /* The 6-bit UIM field in a X form instruction. */
2392 #define UIM6 UIMM3 + 1
2393 { 0x3f, 16, NULL
, NULL
, 0 },
2395 /* The SIX field in a VX form instruction. */
2396 #define SIX UIM6 + 1
2398 { 0xf, 11, NULL
, NULL
, 0 },
2400 /* The PS field in a VX form instruction. */
2402 { 0x1, 9, NULL
, NULL
, 0 },
2404 /* The SHB field in a VA form instruction. */
2406 { 0xf, 6, NULL
, NULL
, 0 },
2408 /* The other UIMM field in a half word EVX form instruction. */
2409 #define EVUIMM_1 SHB + 1
2410 { 0x1f, 11, NULL
, NULL
, PPC_OPERAND_PARENS
},
2412 #define EVUIMM_1_EX0 EVUIMM_1 + 1
2413 { 0x1f, 11, insert_evuimm1_ex0
, extract_evuimm1_ex0
, PPC_OPERAND_PARENS
},
2415 #define EVUIMM_2 EVUIMM_1_EX0 + 1
2416 { 0x3e, 10, NULL
, NULL
, PPC_OPERAND_PARENS
},
2418 #define EVUIMM_2_EX0 EVUIMM_2 + 1
2419 { 0x3e, 10, insert_evuimm2_ex0
, extract_evuimm2_ex0
, PPC_OPERAND_PARENS
},
2421 /* The other UIMM field in a word EVX form instruction. */
2422 #define EVUIMM_4 EVUIMM_2_EX0 + 1
2423 { 0x7c, 9, NULL
, NULL
, PPC_OPERAND_PARENS
},
2425 #define EVUIMM_4_EX0 EVUIMM_4 + 1
2426 { 0x7c, 9, insert_evuimm4_ex0
, extract_evuimm4_ex0
, PPC_OPERAND_PARENS
},
2428 /* The other UIMM field in a double EVX form instruction. */
2429 #define EVUIMM_8 EVUIMM_4_EX0 + 1
2430 { 0xf8, 8, NULL
, NULL
, PPC_OPERAND_PARENS
},
2432 #define EVUIMM_8_EX0 EVUIMM_8 + 1
2433 { 0xf8, 8, insert_evuimm8_ex0
, extract_evuimm8_ex0
, PPC_OPERAND_PARENS
},
2435 /* The WS or DRM field in an X form instruction. */
2436 #define WS EVUIMM_8_EX0 + 1
2438 /* The NNN field in a VX form instruction for SPE2 */
2440 { 0x7, 11, NULL
, NULL
, 0 },
2442 /* PowerPC paired singles extensions. */
2443 /* W bit in the pair singles instructions for x type instructions. */
2445 /* The BO16 field in a BD8 form instruction. */
2447 { 0x1, 10, 0, 0, 0 },
2449 /* IDX bits for quantization in the pair singles instructions. */
2450 #define PSQ PSWM + 1
2451 { 0x7, 12, 0, 0, PPC_OPERAND_GQR
},
2453 /* IDX bits for quantization in the pair singles x-type instructions. */
2454 #define PSQM PSQ + 1
2455 { 0x7, 7, 0, 0, PPC_OPERAND_GQR
},
2457 /* Smaller D field for quantization in the pair singles instructions. */
2458 #define PSD PSQM + 1
2459 { 0xfff, 0, 0, 0, PPC_OPERAND_PARENS
| PPC_OPERAND_SIGNED
},
2461 /* The L field in an mtmsrd or A form instruction or R or W in an
2466 { 0x1, 16, NULL
, NULL
, PPC_OPERAND_OPTIONAL
},
2468 /* The RMC or CY field in a Z23 form instruction. */
2471 { 0x3, 9, NULL
, NULL
, 0 },
2474 { 0x1, 16, NULL
, NULL
, 0 },
2477 { 0x3, 18, NULL
, NULL
, PPC_OPERAND_OPTIONAL
},
2480 { 0x1, 17, NULL
, NULL
, PPC_OPERAND_OPTIONAL
},
2483 { 0x3, 19, NULL
, NULL
, 0 },
2486 { 0x1, 20, NULL
, NULL
, 0 },
2488 /* The S field in a XL form instruction. */
2490 { 0x1, 11, NULL
, NULL
, PPC_OPERAND_OPTIONAL
| PPC_OPERAND_OPTIONAL_VALUE
},
2491 /* If the SXL operand is ommitted, use the value 1. */
2492 { -1, 1, NULL
, NULL
, 0},
2494 /* SH field starting at bit position 16. */
2495 #define SH16 SXL + 2
2496 /* The DCM and DGM fields in a Z form instruction. */
2499 { 0x3f, 10, NULL
, NULL
, 0 },
2501 /* The EH field in larx instruction. */
2503 { 0x1, 0, NULL
, NULL
, PPC_OPERAND_OPTIONAL
},
2505 /* The L field in an mtfsf or XFL form instruction. */
2506 /* The A field in a HTM X form instruction. */
2507 #define XFL_L EH + 1
2509 { 0x1, 25, NULL
, NULL
, PPC_OPERAND_OPTIONAL
},
2511 /* Xilinx APU related masks and macros */
2512 #define FCRT XFL_L + 1
2513 #define FCRT_MASK (0x1f << 21)
2514 { 0x1f, 21, 0, 0, PPC_OPERAND_FCR
},
2516 /* Xilinx FSL related masks and macros */
2517 #define FSL FCRT + 1
2518 #define FSL_MASK (0x1f << 11)
2519 { 0x1f, 11, 0, 0, PPC_OPERAND_FSL
},
2521 /* Xilinx UDI related masks and macros */
2523 { 0x1f, 21, 0, 0, PPC_OPERAND_UDI
},
2526 { 0x1f, 16, 0, 0, PPC_OPERAND_UDI
},
2529 { 0x1f, 11, 0, 0, PPC_OPERAND_UDI
},
2532 { 0x1f, 6, 0, 0, PPC_OPERAND_UDI
},
2534 /* The VLESIMM field in a D form instruction. */
2535 #define VLESIMM URC + 1
2536 { 0xffff, PPC_OPSHIFT_INV
, insert_vlesi
, extract_vlesi
,
2537 PPC_OPERAND_SIGNED
| PPC_OPERAND_SIGNOPT
},
2539 /* The VLENSIMM field in a D form instruction. */
2540 #define VLENSIMM VLESIMM + 1
2541 { 0xffff, PPC_OPSHIFT_INV
, insert_vlensi
, extract_vlensi
,
2542 PPC_OPERAND_NEGATIVE
| PPC_OPERAND_SIGNED
| PPC_OPERAND_SIGNOPT
},
2544 /* The VLEUIMM field in a D form instruction. */
2545 #define VLEUIMM VLENSIMM + 1
2546 { 0xffff, PPC_OPSHIFT_INV
, insert_vleui
, extract_vleui
, 0 },
2548 /* The VLEUIMML field in a D form instruction. */
2549 #define VLEUIMML VLEUIMM + 1
2550 { 0xffff, PPC_OPSHIFT_INV
, insert_vleil
, extract_vleil
, 0 },
2552 /* The XT and XS fields in an XX1 or XX3 form instruction. This is
2554 #define XS6 VLEUIMML + 1
2556 { 0x3f, PPC_OPSHIFT_INV
, insert_xt6
, extract_xt6
, PPC_OPERAND_VSR
},
2558 /* The XT and XS fields in an DQ form VSX instruction. This is split. */
2559 #define XSQ6 XT6 + 1
2561 { 0x3f, PPC_OPSHIFT_INV
, insert_xtq6
, extract_xtq6
, PPC_OPERAND_VSR
},
2563 /* The XA field in an XX3 form instruction. This is split. */
2564 #define XA6 XTQ6 + 1
2565 { 0x3f, PPC_OPSHIFT_INV
, insert_xa6
, extract_xa6
, PPC_OPERAND_VSR
},
2567 /* The XB field in an XX2 or XX3 form instruction. This is split. */
2569 { 0x3f, PPC_OPSHIFT_INV
, insert_xb6
, extract_xb6
, PPC_OPERAND_VSR
},
2571 /* The XB field in an XX3 form instruction when it must be the same as
2572 the XA field in the instruction. This is used in extended mnemonics
2573 like xvmovdp. This is split. */
2574 #define XB6S XB6 + 1
2575 { 0x3f, PPC_OPSHIFT_INV
, insert_xb6s
, extract_xb6s
, PPC_OPERAND_FAKE
},
2577 /* The XC field in an XX4 form instruction. This is split. */
2578 #define XC6 XB6S + 1
2579 { 0x3f, PPC_OPSHIFT_INV
, insert_xc6
, extract_xc6
, PPC_OPERAND_VSR
},
2581 /* The DM or SHW field in an XX3 form instruction. */
2584 { 0x3, 8, NULL
, NULL
, 0 },
2586 /* The DM field in an extended mnemonic XX3 form instruction. */
2588 { 0x3, 8, insert_dm
, extract_dm
, 0 },
2590 /* The UIM field in an XX2 form instruction. */
2591 #define UIM DMEX + 1
2592 /* The 2-bit UIMM field in a VX form instruction. */
2594 /* The 2-bit L field in a darn instruction. */
2596 { 0x3, 16, NULL
, NULL
, 0 },
2598 #define ERAT_T UIM + 1
2599 { 0x7, 21, NULL
, NULL
, 0 },
2601 #define IH ERAT_T + 1
2602 { 0x7, 21, NULL
, NULL
, PPC_OPERAND_OPTIONAL
},
2604 /* The 8-bit IMM8 field in a XX1 form instruction. */
2606 { 0xff, 11, NULL
, NULL
, PPC_OPERAND_SIGNOPT
},
2608 #define VX_OFF IMM8 + 1
2609 { 0x3, 0, insert_off_lsp
, extract_off_lsp
, 0 },
2611 #define VX_OFF_SPE2 VX_OFF + 1
2612 { 0x7, 0, insert_off_spe2
, extract_off_spe2
, 0 },
2614 #define BBB VX_OFF_SPE2 + 1
2615 { 0x7, 13, NULL
, NULL
, 0 },
2618 #define VX_MASK_DDD (VX_MASK & ~0x1)
2619 { 0x7, PPC_OPSHIFT_INV
, insert_Ddd
, extract_Ddd
, 0 },
2622 { 0x3, 13, NULL
, NULL
, 0 },
2625 const unsigned int num_powerpc_operands
= (sizeof (powerpc_operands
)
2626 / sizeof (powerpc_operands
[0]));
2628 /* Macros used to form opcodes. */
2630 /* The main opcode. */
2631 #define OP(x) ((((uint64_t)(x)) & 0x3f) << 26)
2632 #define OP_MASK OP (0x3f)
2634 /* The main opcode combined with a trap code in the TO field of a D
2635 form instruction. Used for extended mnemonics for the trap
2637 #define OPTO(x,to) (OP (x) | ((((uint64_t)(to)) & 0x1f) << 21))
2638 #define OPTO_MASK (OP_MASK | TO_MASK)
2640 /* The main opcode combined with a comparison size bit in the L field
2641 of a D form or X form instruction. Used for extended mnemonics for
2642 the comparison instructions. */
2643 #define OPL(x,l) (OP (x) | ((((uint64_t)(l)) & 1) << 21))
2644 #define OPL_MASK OPL (0x3f,1)
2646 /* The main opcode combined with an update code in D form instruction.
2647 Used for extended mnemonics for VLE memory instructions. */
2648 #define OPVUP(x,vup) (OP (x) | ((((uint64_t)(vup)) & 0xff) << 8))
2649 #define OPVUP_MASK OPVUP (0x3f, 0xff)
2651 /* The main opcode combined with an update code and the RT fields
2652 specified in D form instruction. Used for VLE volatile context
2653 save/restore instructions. */
2654 #define OPVUPRT(x,vup,rt) \
2656 | ((((uint64_t)(rt)) & 0x1f) << 21))
2657 #define OPVUPRT_MASK OPVUPRT (0x3f, 0xff, 0x1f)
2659 /* An A form instruction. */
2660 #define A(op, xop, rc) \
2662 | ((((uint64_t)(xop)) & 0x1f) << 1) \
2663 | (((uint64_t)(rc)) & 1))
2664 #define A_MASK A (0x3f, 0x1f, 1)
2666 /* An A_MASK with the FRB field fixed. */
2667 #define AFRB_MASK (A_MASK | FRB_MASK)
2669 /* An A_MASK with the FRC field fixed. */
2670 #define AFRC_MASK (A_MASK | FRC_MASK)
2672 /* An A_MASK with the FRA and FRC fields fixed. */
2673 #define AFRAFRC_MASK (A_MASK | FRA_MASK | FRC_MASK)
2675 /* An AFRAFRC_MASK, but with L bit clear. */
2676 #define AFRALFRC_MASK (AFRAFRC_MASK & ~((uint64_t) 1 << 16))
2678 /* A B form instruction. */
2679 #define B(op, aa, lk) \
2681 | ((((uint64_t)(aa)) & 1) << 1) \
2683 #define B_MASK B (0x3f, 1, 1)
2685 /* A BD8 form instruction. This is a 16-bit instruction. */
2686 #define BD8(op, aa, lk) \
2687 (((((uint64_t)(op)) & 0x3f) << 10) \
2688 | (((aa) & 1) << 9) \
2689 | (((lk) & 1) << 8))
2690 #define BD8_MASK BD8 (0x3f, 1, 1)
2692 /* Another BD8 form instruction. This is a 16-bit instruction. */
2693 #define BD8IO(op) ((((uint64_t)(op)) & 0x1f) << 11)
2694 #define BD8IO_MASK BD8IO (0x1f)
2696 /* A BD8 form instruction for simplified mnemonics. */
2697 #define EBD8IO(op, bo, bi) (BD8IO ((op)) | ((bo) << 10) | ((bi) << 8))
2698 /* A mask that excludes BO32 and BI32. */
2699 #define EBD8IO1_MASK 0xf800
2700 /* A mask that includes BO32 and excludes BI32. */
2701 #define EBD8IO2_MASK 0xfc00
2702 /* A mask that include BO32 AND BI32. */
2703 #define EBD8IO3_MASK 0xff00
2705 /* A BD15 form instruction. */
2706 #define BD15(op, aa, lk) \
2708 | ((((uint64_t)(aa)) & 0xf) << 22) \
2710 #define BD15_MASK BD15 (0x3f, 0xf, 1)
2712 /* A BD15 form instruction for extended conditional branch mnemonics. */
2713 #define EBD15(op, aa, bo, lk) \
2714 (((op) & 0x3f) << 26) \
2715 | (((aa) & 0xf) << 22) \
2716 | (((bo) & 0x3) << 20) \
2718 #define EBD15_MASK 0xfff00001
2720 /* A BD15 form instruction for extended conditional branch mnemonics
2722 #define EBD15BI(op, aa, bo, bi, lk) \
2723 ((((op) & 0x3f) << 26) \
2724 | (((aa) & 0xf) << 22) \
2725 | (((bo) & 0x3) << 20) \
2726 | (((bi) & 0x3) << 16) \
2729 #define EBD15BI_MASK 0xfff30001
2731 /* A BD24 form instruction. */
2732 #define BD24(op, aa, lk) \
2734 | ((((uint64_t)(aa)) & 1) << 25) \
2736 #define BD24_MASK BD24 (0x3f, 1, 1)
2738 /* A B form instruction setting the BO field. */
2739 #define BBO(op, bo, aa, lk) \
2740 (B ((op), (aa), (lk)) \
2741 | ((((uint64_t)(bo)) & 0x1f) << 21))
2742 #define BBO_MASK BBO (0x3f, 0x1f, 1, 1)
2744 /* A BBO_MASK with the y bit of the BO field removed. This permits
2745 matching a conditional branch regardless of the setting of the y
2746 bit. Similarly for the 'at' bits used for power4 branch hints. */
2747 #define Y_MASK (((uint64_t) 1) << 21)
2748 #define AT1_MASK (((uint64_t) 3) << 21)
2749 #define AT2_MASK (((uint64_t) 9) << 21)
2750 #define BBOY_MASK (BBO_MASK &~ Y_MASK)
2751 #define BBOAT_MASK (BBO_MASK &~ AT1_MASK)
2753 /* A B form instruction setting the BO field and the condition bits of
2755 #define BBOCB(op, bo, cb, aa, lk) \
2756 (BBO ((op), (bo), (aa), (lk)) | ((((uint64_t)(cb)) & 0x3) << 16))
2757 #define BBOCB_MASK BBOCB (0x3f, 0x1f, 0x3, 1, 1)
2759 /* A BBOCB_MASK with the y bit of the BO field removed. */
2760 #define BBOYCB_MASK (BBOCB_MASK &~ Y_MASK)
2761 #define BBOATCB_MASK (BBOCB_MASK &~ AT1_MASK)
2762 #define BBOAT2CB_MASK (BBOCB_MASK &~ AT2_MASK)
2764 /* A BBOYCB_MASK in which the BI field is fixed. */
2765 #define BBOYBI_MASK (BBOYCB_MASK | BI_MASK)
2766 #define BBOATBI_MASK (BBOAT2CB_MASK | BI_MASK)
2768 /* A VLE C form instruction. */
2769 #define C_LK(x, lk) (((((uint64_t)(x)) & 0x7fff) << 1) | ((lk) & 1))
2770 #define C_LK_MASK C_LK(0x7fff, 1)
2771 #define C(x) ((((uint64_t)(x)) & 0xffff))
2772 #define C_MASK C(0xffff)
2774 /* An Context form instruction. */
2775 #define CTX(op, xop) (OP (op) | (((uint64_t)(xop)) & 0x7))
2776 #define CTX_MASK CTX(0x3f, 0x7)
2778 /* An User Context form instruction. */
2779 #define UCTX(op, xop) (OP (op) | (((uint64_t)(xop)) & 0x1f))
2780 #define UCTX_MASK UCTX(0x3f, 0x1f)
2782 /* The main opcode mask with the RA field clear. */
2783 #define DRA_MASK (OP_MASK | RA_MASK)
2785 /* A DQ form VSX instruction. */
2786 #define DQX(op, xop) (OP (op) | ((xop) & 0x7))
2787 #define DQX_MASK DQX (0x3f, 7)
2789 /* A DS form instruction. */
2790 #define DSO(op, xop) (OP (op) | ((xop) & 0x3))
2791 #define DS_MASK DSO (0x3f, 3)
2793 /* An DX form instruction. */
2794 #define DX(op, xop) (OP (op) | ((((uint64_t)(xop)) & 0x1f) << 1))
2795 #define DX_MASK DX (0x3f, 0x1f)
2796 /* An DX form instruction with the D bits specified. */
2797 #define NODX_MASK (DX_MASK | 0x1fffc1)
2799 /* An EVSEL form instruction. */
2800 #define EVSEL(op, xop) (OP (op) | (((uint64_t)(xop)) & 0xff) << 3)
2801 #define EVSEL_MASK EVSEL(0x3f, 0xff)
2803 /* An IA16 form instruction. */
2804 #define IA16(op, xop) (OP (op) | (((uint64_t)(xop)) & 0x1f) << 11)
2805 #define IA16_MASK IA16(0x3f, 0x1f)
2807 /* An I16A form instruction. */
2808 #define I16A(op, xop) (OP (op) | (((uint64_t)(xop)) & 0x1f) << 11)
2809 #define I16A_MASK I16A(0x3f, 0x1f)
2811 /* An I16L form instruction. */
2812 #define I16L(op, xop) (OP (op) | (((uint64_t)(xop)) & 0x1f) << 11)
2813 #define I16L_MASK I16L(0x3f, 0x1f)
2815 /* An IM7 form instruction. */
2816 #define IM7(op) ((((uint64_t)(op)) & 0x1f) << 11)
2817 #define IM7_MASK IM7(0x1f)
2819 /* An M form instruction. */
2820 #define M(op, rc) (OP (op) | ((rc) & 1))
2821 #define M_MASK M (0x3f, 1)
2823 /* An LI20 form instruction. */
2824 #define LI20(op, xop) (OP (op) | (((uint64_t)(xop)) & 0x1) << 15)
2825 #define LI20_MASK LI20(0x3f, 0x1)
2827 /* An M form instruction with the ME field specified. */
2828 #define MME(op, me, rc) \
2830 | ((((uint64_t)(me)) & 0x1f) << 1))
2832 /* An M_MASK with the MB and ME fields fixed. */
2833 #define MMBME_MASK (M_MASK | MB_MASK | ME_MASK)
2835 /* An M_MASK with the SH and ME fields fixed. */
2836 #define MSHME_MASK (M_MASK | SH_MASK | ME_MASK)
2838 /* An MD form instruction. */
2839 #define MD(op, xop, rc) \
2841 | ((((uint64_t)(xop)) & 0x7) << 2) \
2843 #define MD_MASK MD (0x3f, 0x7, 1)
2845 /* An MD_MASK with the MB field fixed. */
2846 #define MDMB_MASK (MD_MASK | MB6_MASK)
2848 /* An MD_MASK with the SH field fixed. */
2849 #define MDSH_MASK (MD_MASK | SH6_MASK)
2851 /* An MDS form instruction. */
2852 #define MDS(op, xop, rc) \
2854 | ((((uint64_t)(xop)) & 0xf) << 1) \
2856 #define MDS_MASK MDS (0x3f, 0xf, 1)
2858 /* An MDS_MASK with the MB field fixed. */
2859 #define MDSMB_MASK (MDS_MASK | MB6_MASK)
2861 /* An SC form instruction. */
2862 #define SC(op, sa, lk) \
2864 | ((((uint64_t)(sa)) & 1) << 1) \
2868 | (((uint64_t) 0x3ff) << 16) \
2869 | (((uint64_t) 1) << 1) \
2872 /* An SCI8 form instruction. */
2873 #define SCI8(op, xop) (OP (op) | ((((uint64_t)(xop)) & 0x1f) << 11))
2874 #define SCI8_MASK SCI8(0x3f, 0x1f)
2876 /* An SCI8 form instruction. */
2877 #define SCI8BF(op, fop, xop) \
2879 | ((((uint64_t)(xop)) & 0x1f) << 11) \
2880 | (((fop) & 7) << 23))
2881 #define SCI8BF_MASK SCI8BF(0x3f, 7, 0x1f)
2883 /* An SD4 form instruction. This is a 16-bit instruction. */
2884 #define SD4(op) ((((uint64_t)(op)) & 0xf) << 12)
2885 #define SD4_MASK SD4(0xf)
2887 /* An SE_IM5 form instruction. This is a 16-bit instruction. */
2888 #define SE_IM5(op, xop) \
2889 (((((uint64_t)(op)) & 0x3f) << 10) \
2890 | (((xop) & 0x1) << 9))
2891 #define SE_IM5_MASK SE_IM5(0x3f, 1)
2893 /* An SE_R form instruction. This is a 16-bit instruction. */
2894 #define SE_R(op, xop) \
2895 (((((uint64_t)(op)) & 0x3f) << 10) \
2896 | (((xop) & 0x3f) << 4))
2897 #define SE_R_MASK SE_R(0x3f, 0x3f)
2899 /* An SE_RR form instruction. This is a 16-bit instruction. */
2900 #define SE_RR(op, xop) \
2901 (((((uint64_t)(op)) & 0x3f) << 10) \
2902 | (((xop) & 0x3) << 8))
2903 #define SE_RR_MASK SE_RR(0x3f, 3)
2905 /* A VX form instruction. */
2906 #define VX(op, xop) (OP (op) | (((uint64_t)(xop)) & 0x7ff))
2908 /* The mask for an VX form instruction. */
2909 #define VX_MASK VX(0x3f, 0x7ff)
2911 /* A VX LSP form instruction. */
2912 #define VX_LSP(op, xop) (OP (op) | (((uint64_t)(xop)) & 0xffff))
2914 /* The mask for an VX LSP form instruction. */
2915 #define VX_LSP_MASK VX_LSP(0x3f, 0xffff)
2916 #define VX_LSP_OFF_MASK VX_LSP(0x3f, 0x7fc)
2918 /* Additional format of VX SPE2 form instruction. */
2919 #define VX_RA_CONST(op, xop, bits11_15) \
2921 | (((uint64_t)(bits11_15) & 0x1f) << 16) \
2922 | (((uint64_t)(xop)) & 0x7ff))
2923 #define VX_RA_CONST_MASK VX_RA_CONST(0x3f, 0x7ff, 0x1f)
2925 #define VX_RB_CONST(op, xop, bits16_20) \
2927 | (((uint64_t)(bits16_20) & 0x1f) << 11) \
2928 | (((uint64_t)(xop)) & 0x7ff))
2929 #define VX_RB_CONST_MASK VX_RB_CONST(0x3f, 0x7ff, 0x1f)
2931 #define VX_OFF_SPE2_MASK VX(0x3f, 0x7f8)
2933 #define VX_SPE_CRFD(op, xop, bits9_10) \
2935 | (((uint64_t)(bits9_10) & 0x3) << 21) \
2936 | (((uint64_t)(xop)) & 0x7ff))
2937 #define VX_SPE_CRFD_MASK VX_SPE_CRFD(0x3f, 0x7ff, 0x3)
2939 #define VX_SPE2_CLR(op, xop, bit16) \
2941 | (((uint64_t)(bit16) & 0x1) << 15) \
2942 | (((uint64_t)(xop)) & 0x7ff))
2943 #define VX_SPE2_CLR_MASK VX_SPE2_CLR(0x3f, 0x7ff, 0x1)
2945 #define VX_SPE2_SPLATB(op, xop, bits19_20) \
2947 | (((uint64_t)(bits19_20) & 0x3) << 11) \
2948 | (((uint64_t)(xop)) & 0x7ff))
2949 #define VX_SPE2_SPLATB_MASK VX_SPE2_SPLATB(0x3f, 0x7ff, 0x3)
2951 #define VX_SPE2_OCTET(op, xop, bits16_17) \
2953 | (((uint64_t)(bits16_17) & 0x3) << 14) \
2954 | (((uint64_t)(xop)) & 0x7ff))
2955 #define VX_SPE2_OCTET_MASK VX_SPE2_OCTET(0x3f, 0x7ff, 0x7)
2957 #define VX_SPE2_DDHH(op, xop, bit16) \
2959 | (((uint64_t)(bit16) & 0x1) << 15) \
2960 | (((uint64_t)(xop)) & 0x7ff))
2961 #define VX_SPE2_DDHH_MASK VX_SPE2_DDHH(0x3f, 0x7ff, 0x1)
2963 #define VX_SPE2_HH(op, xop, bit16, bits19_20) \
2965 | (((uint64_t)(bit16) & 0x1) << 15) \
2966 | (((uint64_t)(bits19_20) & 0x3) << 11) \
2967 | (((uint64_t)(xop)) & 0x7ff))
2968 #define VX_SPE2_HH_MASK VX_SPE2_HH(0x3f, 0x7ff, 0x1, 0x3)
2970 #define VX_SPE2_EVMAR(op, xop) \
2972 | ((uint64_t)(0x1) << 11) \
2973 | (((uint64_t)(xop)) & 0x7ff))
2974 #define VX_SPE2_EVMAR_MASK \
2975 (VX_SPE2_EVMAR(0x3f, 0x7ff) \
2976 | ((uint64_t)(0x1) << 11))
2978 /* A VX_MASK with the VA field fixed. */
2979 #define VXVA_MASK (VX_MASK | (0x1f << 16))
2981 /* A VX_MASK with the VB field fixed. */
2982 #define VXVB_MASK (VX_MASK | (0x1f << 11))
2984 /* A VX_MASK with the VA and VB fields fixed. */
2985 #define VXVAVB_MASK (VX_MASK | (0x1f << 16) | (0x1f << 11))
2987 /* A VX_MASK with the VD and VA fields fixed. */
2988 #define VXVDVA_MASK (VX_MASK | (0x1f << 21) | (0x1f << 16))
2990 /* A VX_MASK with a UIMM4 field. */
2991 #define VXUIMM4_MASK (VX_MASK | (0x1 << 20))
2993 /* A VX_MASK with a UIMM3 field. */
2994 #define VXUIMM3_MASK (VX_MASK | (0x3 << 19))
2996 /* A VX_MASK with a UIMM2 field. */
2997 #define VXUIMM2_MASK (VX_MASK | (0x7 << 18))
2999 /* A VX_MASK with a PS field. */
3000 #define VXPS_MASK (VX_MASK & ~(0x1 << 9))
3002 /* A VX_MASK with the VA field fixed with a PS field. */
3003 #define VXVAPS_MASK ((VX_MASK | (0x1f << 16)) & ~(0x1 << 9))
3005 /* A VA form instruction. */
3006 #define VXA(op, xop) (OP (op) | (((uint64_t)(xop)) & 0x03f))
3008 /* The mask for an VA form instruction. */
3009 #define VXA_MASK VXA(0x3f, 0x3f)
3011 /* A VXA_MASK with a SHB field. */
3012 #define VXASHB_MASK (VXA_MASK | (1 << 10))
3014 /* A VXR form instruction. */
3015 #define VXR(op, xop, rc) \
3017 | (((uint64_t)(rc) & 1) << 10) \
3018 | (((uint64_t)(xop)) & 0x3ff))
3020 /* The mask for a VXR form instruction. */
3021 #define VXR_MASK VXR(0x3f, 0x3ff, 1)
3023 /* A VX form instruction with a VA tertiary opcode. */
3024 #define VXVA(op, xop, vaop) (VX(op,xop) | (((vaop) & 0x1f) << 16))
3026 #define VXASH(op, xop) (OP (op) | ((((uint64_t)(xop)) & 0x1f) << 1))
3027 #define VXASH_MASK VXASH (0x3f, 0x1f)
3029 /* An X form instruction. */
3030 #define X(op, xop) (OP (op) | ((((uint64_t)(xop)) & 0x3ff) << 1))
3032 /* A X form instruction for Quad-Precision FP Instructions. */
3033 #define XVA(op, xop, vaop) (X(op,xop) | (((vaop) & 0x1f) << 16))
3035 /* An EX form instruction. */
3036 #define EX(op, xop) (OP (op) | (((uint64_t)(xop)) & 0x7ff))
3038 /* The mask for an EX form instruction. */
3039 #define EX_MASK EX (0x3f, 0x7ff)
3041 /* An XX2 form instruction. */
3042 #define XX2(op, xop) (OP (op) | ((((uint64_t)(xop)) & 0x1ff) << 2))
3044 /* A XX2 form instruction with the VA bits specified. */
3045 #define XX2VA(op, xop, vaop) (XX2(op,xop) | (((vaop) & 0x1f) << 16))
3047 /* An XX3 form instruction. */
3048 #define XX3(op, xop) (OP (op) | ((((uint64_t)(xop)) & 0xff) << 3))
3050 /* An XX3 form instruction with the RC bit specified. */
3051 #define XX3RC(op, xop, rc) \
3053 | (((uint64_t)(rc) & 1) << 10) \
3054 | ((((uint64_t)(xop)) & 0x7f) << 3))
3056 /* An XX4 form instruction. */
3057 #define XX4(op, xop) (OP (op) | ((((uint64_t)(xop)) & 0x3) << 4))
3059 /* A Z form instruction. */
3060 #define Z(op, xop) (OP (op) | ((((uint64_t)(xop)) & 0x1ff) << 1))
3062 /* An X form instruction with the RC bit specified. */
3063 #define XRC(op, xop, rc) (X ((op), (xop)) | ((rc) & 1))
3065 /* A X form instruction for Quad-Precision FP Instructions with RC bit. */
3066 #define XVARC(op, xop, vaop, rc) (XVA ((op), (xop), (vaop)) | ((rc) & 1))
3068 /* An X form instruction with the RA bits specified as two ops. */
3069 #define XMMF(op, xop, mop0, mop1) \
3071 | ((mop0) & 3) << 19 \
3072 | ((mop1) & 7) << 16)
3074 /* A Z form instruction with the RC bit specified. */
3075 #define ZRC(op, xop, rc) (Z ((op), (xop)) | ((rc) & 1))
3077 /* The mask for an X form instruction. */
3078 #define X_MASK XRC (0x3f, 0x3ff, 1)
3080 /* The mask for an X form instruction with the BF bits specified. */
3081 #define XBF_MASK (X_MASK | (3 << 21))
3083 /* An X form wait instruction with everything filled in except the WC
3085 #define XWC_MASK (XRC (0x3f, 0x3ff, 1) | (7 << 23) | RA_MASK | RB_MASK)
3087 /* The mask for an XX1 form instruction. */
3088 #define XX1_MASK X (0x3f, 0x3ff)
3090 /* An XX1_MASK with the RB field fixed. */
3091 #define XX1RB_MASK (XX1_MASK | RB_MASK)
3093 /* The mask for an XX2 form instruction. */
3094 #define XX2_MASK (XX2 (0x3f, 0x1ff) | (0x1f << 16))
3096 /* The mask for an XX2 form instruction with the UIM bits specified. */
3097 #define XX2UIM_MASK (XX2 (0x3f, 0x1ff) | (7 << 18))
3099 /* The mask for an XX2 form instruction with the 4 UIM bits specified. */
3100 #define XX2UIM4_MASK (XX2 (0x3f, 0x1ff) | (1 << 20))
3102 /* The mask for an XX2 form instruction with the BF bits specified. */
3103 #define XX2BF_MASK (XX2_MASK | (3 << 21) | (1))
3105 /* The mask for an XX2 form instruction with the BF and DCMX bits
3107 #define XX2BFD_MASK (XX2 (0x3f, 0x1ff) | 1)
3109 /* The mask for an XX2 form instruction with a split DCMX bits
3111 #define XX2DCMXS_MASK XX2 (0x3f, 0x1ee)
3113 /* The mask for an XX3 form instruction. */
3114 #define XX3_MASK XX3 (0x3f, 0xff)
3116 /* The mask for an XX3 form instruction with the BF bits specified. */
3117 #define XX3BF_MASK (XX3 (0x3f, 0xff) | (3 << 21) | (1))
3119 /* The mask for an XX3 form instruction with the DM or SHW bits
3121 #define XX3DM_MASK (XX3 (0x3f, 0x1f) | (1 << 10))
3122 #define XX3SHW_MASK XX3DM_MASK
3124 /* The mask for an XX4 form instruction. */
3125 #define XX4_MASK XX4 (0x3f, 0x3)
3127 /* An X form wait instruction with everything filled in except the WC
3129 #define XWC_MASK (XRC (0x3f, 0x3ff, 1) | (7 << 23) | RA_MASK | RB_MASK)
3131 /* The mask for an XMMF form instruction. */
3132 #define XMMF_MASK (XMMF (0x3f, 0x3ff, 3, 7) | (1))
3134 /* The mask for a Z form instruction. */
3135 #define Z_MASK ZRC (0x3f, 0x1ff, 1)
3136 #define Z2_MASK ZRC (0x3f, 0xff, 1)
3138 /* An X_MASK with the RA/VA field fixed. */
3139 #define XRA_MASK (X_MASK | RA_MASK)
3140 #define XVA_MASK XRA_MASK
3142 /* An XRA_MASK with the A_L/W field clear. */
3143 #define XWRA_MASK (XRA_MASK & ~((uint64_t) 1 << 16))
3144 #define XRLA_MASK XWRA_MASK
3146 /* An X_MASK with the RB field fixed. */
3147 #define XRB_MASK (X_MASK | RB_MASK)
3149 /* An X_MASK with the RT field fixed. */
3150 #define XRT_MASK (X_MASK | RT_MASK)
3152 /* An XRT_MASK mask with the L bits clear. */
3153 #define XLRT_MASK (XRT_MASK & ~((uint64_t) 0x3 << 21))
3155 /* An X_MASK with the RA and RB fields fixed. */
3156 #define XRARB_MASK (X_MASK | RA_MASK | RB_MASK)
3158 /* An XBF_MASK with the RA and RB fields fixed. */
3159 #define XBFRARB_MASK (XBF_MASK | RA_MASK | RB_MASK)
3161 /* An XRARB_MASK, but with the L bit clear. */
3162 #define XRLARB_MASK (XRARB_MASK & ~((uint64_t) 1 << 16))
3164 /* An XRARB_MASK, but with the L bits in a darn instruction clear. */
3165 #define XLRAND_MASK (XRARB_MASK & ~((uint64_t) 3 << 16))
3167 /* An X_MASK with the RT and RA fields fixed. */
3168 #define XRTRA_MASK (X_MASK | RT_MASK | RA_MASK)
3170 /* An X_MASK with the RT and RB fields fixed. */
3171 #define XRTRB_MASK (X_MASK | RT_MASK | RB_MASK)
3173 /* An XRTRA_MASK, but with L bit clear. */
3174 #define XRTLRA_MASK (XRTRA_MASK & ~((uint64_t) 1 << 21))
3176 /* An X_MASK with the RT, RA and RB fields fixed. */
3177 #define XRTRARB_MASK (X_MASK | RT_MASK | RA_MASK | RB_MASK)
3179 /* An XRTRARB_MASK, but with L bit clear. */
3180 #define XRTLRARB_MASK (XRTRARB_MASK & ~((uint64_t) 1 << 21))
3182 /* An XRTRARB_MASK, but with A bit clear. */
3183 #define XRTARARB_MASK (XRTRARB_MASK & ~((uint64_t) 1 << 25))
3185 /* An XRTRARB_MASK, but with BF bits clear. */
3186 #define XRTBFRARB_MASK (XRTRARB_MASK & ~((uint64_t) 7 << 23))
3188 /* An X form instruction with the L bit specified. */
3189 #define XOPL(op, xop, l) \
3191 | ((((uint64_t)(l)) & 1) << 21))
3193 /* An X form instruction with the L bits specified. */
3194 #define XOPL2(op, xop, l) \
3196 | ((((uint64_t)(l)) & 3) << 21))
3198 /* An X form instruction with the L bit and RC bit specified. */
3199 #define XRCL(op, xop, l, rc) \
3200 (XRC ((op), (xop), (rc)) \
3201 | ((((uint64_t)(l)) & 1) << 21))
3203 /* An X form instruction with RT fields specified */
3204 #define XRT(op, xop, rt) \
3206 | ((((uint64_t)(rt)) & 0x1f) << 21))
3208 /* An X form instruction with RT and RA fields specified */
3209 #define XRTRA(op, xop, rt, ra) \
3211 | ((((uint64_t)(rt)) & 0x1f) << 21) \
3212 | ((((uint64_t)(ra)) & 0x1f) << 16))
3214 /* The mask for an X form comparison instruction. */
3215 #define XCMP_MASK (X_MASK | (((uint64_t)1) << 22))
3217 /* The mask for an X form comparison instruction with the L field
3219 #define XCMPL_MASK (XCMP_MASK | (((uint64_t)1) << 21))
3221 /* An X form trap instruction with the TO field specified. */
3222 #define XTO(op, xop, to) \
3224 | ((((uint64_t)(to)) & 0x1f) << 21))
3225 #define XTO_MASK (X_MASK | TO_MASK)
3227 /* An X form tlb instruction with the SH field specified. */
3228 #define XTLB(op, xop, sh) \
3230 | ((((uint64_t)(sh)) & 0x1f) << 11))
3231 #define XTLB_MASK (X_MASK | SH_MASK)
3233 /* An X form sync instruction. */
3234 #define XSYNC(op, xop, l) \
3236 | ((((uint64_t)(l)) & 3) << 21))
3238 /* An X form sync instruction with everything filled in except the LS
3240 #define XSYNC_MASK (0xff9fffff)
3242 /* An X form sync instruction with everything filled in except the L
3244 #define XSYNCLE_MASK (0xff90ffff)
3246 /* An X_MASK, but with the EH bit clear. */
3247 #define XEH_MASK (X_MASK & ~((uint64_t )1))
3249 /* An X form AltiVec dss instruction. */
3250 #define XDSS(op, xop, a) (X ((op), (xop)) | ((((uint64_t)(a)) & 1) << 25))
3251 #define XDSS_MASK XDSS(0x3f, 0x3ff, 1)
3253 /* An XFL form instruction. */
3254 #define XFL(op, xop, rc) \
3256 | ((((uint64_t)(xop)) & 0x3ff) << 1) \
3257 | (((uint64_t)(rc)) & 1))
3258 #define XFL_MASK XFL (0x3f, 0x3ff, 1)
3260 /* An X form isel instruction. */
3261 #define XISEL(op, xop) (OP (op) | ((((uint64_t)(xop)) & 0x1f) << 1))
3262 #define XISEL_MASK XISEL(0x3f, 0x1f)
3264 /* An XL form instruction with the LK field set to 0. */
3265 #define XL(op, xop) (OP (op) | ((((uint64_t)(xop)) & 0x3ff) << 1))
3267 /* An XL form instruction which uses the LK field. */
3268 #define XLLK(op, xop, lk) (XL ((op), (xop)) | ((lk) & 1))
3270 /* The mask for an XL form instruction. */
3271 #define XL_MASK XLLK (0x3f, 0x3ff, 1)
3273 /* An XL_MASK with the RT, RA and RB fields fixed, but S bit clear. */
3274 #define XLS_MASK ((XL_MASK | RT_MASK | RA_MASK | RB_MASK) & ~(1 << 11))
3276 /* An XL form instruction which explicitly sets the BO field. */
3277 #define XLO(op, bo, xop, lk) \
3278 (XLLK ((op), (xop), (lk)) | ((((uint64_t)(bo)) & 0x1f) << 21))
3279 #define XLO_MASK (XL_MASK | BO_MASK)
3281 /* An XL form instruction which explicitly sets the y bit of the BO
3283 #define XLYLK(op, xop, y, lk) \
3284 (XLLK ((op), (xop), (lk)) \
3285 | ((((uint64_t)(y)) & 1) << 21))
3286 #define XLYLK_MASK (XL_MASK | Y_MASK)
3288 /* An XL form instruction which sets the BO field and the condition
3289 bits of the BI field. */
3290 #define XLOCB(op, bo, cb, xop, lk) \
3291 (XLO ((op), (bo), (xop), (lk)) | ((((uint64_t)(cb)) & 3) << 16))
3292 #define XLOCB_MASK XLOCB (0x3f, 0x1f, 0x3, 0x3ff, 1)
3294 /* An XL_MASK or XLYLK_MASK or XLOCB_MASK with the BB field fixed. */
3295 #define XLBB_MASK (XL_MASK | BB_MASK)
3296 #define XLYBB_MASK (XLYLK_MASK | BB_MASK)
3297 #define XLBOCBBB_MASK (XLOCB_MASK | BB_MASK)
3299 /* A mask for branch instructions using the BH field. */
3300 #define XLBH_MASK (XL_MASK | (0x1c << 11))
3302 /* An XL_MASK with the BO and BB fields fixed. */
3303 #define XLBOBB_MASK (XL_MASK | BO_MASK | BB_MASK)
3305 /* An XL_MASK with the BO, BI and BB fields fixed. */
3306 #define XLBOBIBB_MASK (XL_MASK | BO_MASK | BI_MASK | BB_MASK)
3308 /* An X form mbar instruction with MO field. */
3309 #define XMBAR(op, xop, mo) \
3311 | ((((uint64_t)(mo)) & 1) << 21))
3313 /* An XO form instruction. */
3314 #define XO(op, xop, oe, rc) \
3316 | ((((uint64_t)(xop)) & 0x1ff) << 1) \
3317 | ((((uint64_t)(oe)) & 1) << 10) \
3318 | (((unsigned long)(rc)) & 1))
3319 #define XO_MASK XO (0x3f, 0x1ff, 1, 1)
3321 /* An XO_MASK with the RB field fixed. */
3322 #define XORB_MASK (XO_MASK | RB_MASK)
3324 /* An XOPS form instruction for paired singles. */
3325 #define XOPS(op, xop, rc) \
3327 | ((((uint64_t)(xop)) & 0x3ff) << 1) \
3328 | (((uint64_t)(rc)) & 1))
3329 #define XOPS_MASK XOPS (0x3f, 0x3ff, 1)
3332 /* An XS form instruction. */
3333 #define XS(op, xop, rc) \
3335 | ((((uint64_t)(xop)) & 0x1ff) << 2) \
3336 | (((uint64_t)(rc)) & 1))
3337 #define XS_MASK XS (0x3f, 0x1ff, 1)
3339 /* A mask for the FXM version of an XFX form instruction. */
3340 #define XFXFXM_MASK (X_MASK | (1 << 11) | (1 << 20))
3342 /* An XFX form instruction with the FXM field filled in. */
3343 #define XFXM(op, xop, fxm, p4) \
3345 | ((((uint64_t)(fxm)) & 0xff) << 12) \
3346 | ((uint64_t)(p4) << 20))
3348 /* An XFX form instruction with the SPR field filled in. */
3349 #define XSPR(op, xop, spr) \
3351 | ((((uint64_t)(spr)) & 0x1f) << 16) \
3352 | ((((uint64_t)(spr)) & 0x3e0) << 6))
3353 #define XSPR_MASK (X_MASK | SPR_MASK)
3355 /* An XFX form instruction with the SPR field filled in except for the
3357 #define XSPRBAT_MASK (XSPR_MASK &~ SPRBAT_MASK)
3359 /* An XFX form instruction with the SPR field filled in except for the
3361 #define XSPRG_MASK (XSPR_MASK & ~(0x1f << 16))
3363 /* An X form instruction with everything filled in except the E field. */
3364 #define XE_MASK (0xffff7fff)
3366 /* An X form user context instruction. */
3367 #define XUC(op, xop) (OP (op) | (((uint64_t)(xop)) & 0x1f))
3368 #define XUC_MASK XUC(0x3f, 0x1f)
3370 /* An XW form instruction. */
3371 #define XW(op, xop, rc) \
3373 | ((((uint64_t)(xop)) & 0x3f) << 1) \
3375 /* The mask for a G form instruction. rc not supported at present. */
3376 #define XW_MASK XW (0x3f, 0x3f, 0)
3378 /* An APU form instruction. */
3379 #define APU(op, xop, rc) \
3381 | (((uint64_t)(xop)) & 0x3ff) << 1 \
3384 /* The mask for an APU form instruction. */
3385 #define APU_MASK APU (0x3f, 0x3ff, 1)
3386 #define APU_RT_MASK (APU_MASK | RT_MASK)
3387 #define APU_RA_MASK (APU_MASK | RA_MASK)
3389 /* The BO encodings used in extended conditional branch mnemonics. */
3390 #define BODNZF (0x0)
3391 #define BODNZFP (0x1)
3393 #define BODZFP (0x3)
3394 #define BODNZT (0x8)
3395 #define BODNZTP (0x9)
3397 #define BODZTP (0xb)
3408 #define BODNZ (0x10)
3409 #define BODNZP (0x11)
3411 #define BODZP (0x13)
3412 #define BODNZM4 (0x18)
3413 #define BODNZP4 (0x19)
3414 #define BODZM4 (0x1a)
3415 #define BODZP4 (0x1b)
3419 /* The BO16 encodings used in extended VLE conditional branch mnemonics. */
3423 /* The BO32 encodings used in extended VLE conditional branch mnemonics. */
3426 #define BO32DNZ (0x2)
3427 #define BO32DZ (0x3)
3429 /* The BI condition bit encodings used in extended conditional branch
3436 /* The TO encodings used in extended trap mnemonics. */
3453 /* Smaller names for the flags so each entry in the opcodes table will
3454 fit on a single line. */
3456 #define PPC PPC_OPCODE_PPC
3457 #define PPCCOM PPC_OPCODE_PPC | PPC_OPCODE_COMMON
3458 #define POWER4 PPC_OPCODE_POWER4
3459 #define POWER5 PPC_OPCODE_POWER5
3460 #define POWER6 PPC_OPCODE_POWER6
3461 #define POWER7 PPC_OPCODE_POWER7
3462 #define POWER8 PPC_OPCODE_POWER8
3463 #define POWER9 PPC_OPCODE_POWER9
3464 #define CELL PPC_OPCODE_CELL
3465 #define PPC64 PPC_OPCODE_64 | PPC_OPCODE_64_BRIDGE
3466 #define NON32 (PPC_OPCODE_64 | PPC_OPCODE_POWER4 \
3467 | PPC_OPCODE_EFS | PPC_OPCODE_E500MC | PPC_OPCODE_TITAN)
3468 #define PPC403 PPC_OPCODE_403
3469 #define PPC405 PPC_OPCODE_405
3470 #define PPC440 PPC_OPCODE_440
3471 #define PPC464 PPC440
3472 #define PPC476 PPC_OPCODE_476
3473 #define PPC750 PPC_OPCODE_750
3474 #define PPC7450 PPC_OPCODE_7450
3475 #define PPC860 PPC_OPCODE_860
3476 #define PPCPS PPC_OPCODE_PPCPS
3477 #define PPCVEC PPC_OPCODE_ALTIVEC
3478 #define PPCVEC2 (PPC_OPCODE_POWER8 | PPC_OPCODE_E6500)
3479 #define PPCVEC3 PPC_OPCODE_POWER9
3480 #define PPCVSX PPC_OPCODE_VSX
3481 #define PPCVSX2 PPC_OPCODE_POWER8
3482 #define PPCVSX3 PPC_OPCODE_POWER9
3483 #define POWER PPC_OPCODE_POWER
3484 #define POWER2 PPC_OPCODE_POWER | PPC_OPCODE_POWER2
3485 #define PWR2COM PPC_OPCODE_POWER | PPC_OPCODE_POWER2 | PPC_OPCODE_COMMON
3486 #define PPCPWR2 (PPC_OPCODE_PPC | PPC_OPCODE_POWER | PPC_OPCODE_POWER2 \
3487 | PPC_OPCODE_COMMON)
3488 #define COM PPC_OPCODE_POWER | PPC_OPCODE_PPC | PPC_OPCODE_COMMON
3489 #define M601 PPC_OPCODE_POWER | PPC_OPCODE_601
3490 #define PWRCOM PPC_OPCODE_POWER | PPC_OPCODE_601 | PPC_OPCODE_COMMON
3491 #define MFDEC1 PPC_OPCODE_POWER
3492 #define MFDEC2 (PPC_OPCODE_PPC | PPC_OPCODE_601 | PPC_OPCODE_BOOKE \
3494 #define BOOKE PPC_OPCODE_BOOKE
3495 #define NO371 PPC_OPCODE_BOOKE | PPC_OPCODE_PPCPS | PPC_OPCODE_EFS
3496 #define PPCE300 PPC_OPCODE_E300
3497 #define PPCSPE PPC_OPCODE_SPE
3498 #define PPCSPE2 PPC_OPCODE_SPE2
3499 #define PPCISEL PPC_OPCODE_ISEL
3500 #define PPCEFS PPC_OPCODE_EFS
3501 #define PPCEFS2 PPC_OPCODE_EFS2
3502 #define PPCBRLK PPC_OPCODE_BRLOCK
3503 #define PPCPMR PPC_OPCODE_PMR
3504 #define PPCTMR PPC_OPCODE_TMR
3505 #define PPCCHLK PPC_OPCODE_CACHELCK
3506 #define PPCRFMCI PPC_OPCODE_RFMCI
3507 #define E500MC PPC_OPCODE_E500MC
3508 #define PPCA2 PPC_OPCODE_A2
3509 #define TITAN PPC_OPCODE_TITAN
3510 #define MULHW PPC_OPCODE_405 | PPC_OPCODE_440 | PPC_OPCODE_476 | TITAN
3511 #define E500 PPC_OPCODE_E500
3512 #define E6500 PPC_OPCODE_E6500
3513 #define PPCVLE PPC_OPCODE_VLE
3514 #define PPCHTM PPC_OPCODE_POWER8
3515 #define E200Z4 PPC_OPCODE_E200Z4
3516 #define PPCLSP PPC_OPCODE_LSP
3517 /* The list of embedded processors that use the embedded operand ordering
3518 for the 3 operand dcbt and dcbtst instructions. */
3519 #define DCBT_EO (PPC_OPCODE_E500 | PPC_OPCODE_E500MC | PPC_OPCODE_476 \
3524 /* The opcode table.
3526 The format of the opcode table is:
3528 NAME OPCODE MASK FLAGS ANTI {OPERANDS}
3530 NAME is the name of the instruction.
3531 OPCODE is the instruction opcode.
3532 MASK is the opcode mask; this is used to tell the disassembler
3533 which bits in the actual opcode must match OPCODE.
3534 FLAGS are flags indicating which processors support the instruction.
3535 ANTI indicates which processors don't support the instruction.
3536 OPERANDS is the list of operands.
3538 The disassembler reads the table in order and prints the first
3539 instruction which matches, so this table is sorted to put more
3540 specific instructions before more general instructions.
3542 This table must be sorted by major opcode. Please try to keep it
3543 vaguely sorted within major opcode too, except of course where
3544 constrained otherwise by disassembler operation. */
3546 const struct powerpc_opcode powerpc_opcodes
[] = {
3547 {"attn", X(0,256), X_MASK
, POWER4
|PPCA2
, PPC476
|PPCVLE
, {0}},
3548 {"tdlgti", OPTO(2,TOLGT
), OPTO_MASK
, PPC64
, PPCVLE
, {RA
, SI
}},
3549 {"tdllti", OPTO(2,TOLLT
), OPTO_MASK
, PPC64
, PPCVLE
, {RA
, SI
}},
3550 {"tdeqi", OPTO(2,TOEQ
), OPTO_MASK
, PPC64
, PPCVLE
, {RA
, SI
}},
3551 {"tdlgei", OPTO(2,TOLGE
), OPTO_MASK
, PPC64
, PPCVLE
, {RA
, SI
}},
3552 {"tdlnli", OPTO(2,TOLNL
), OPTO_MASK
, PPC64
, PPCVLE
, {RA
, SI
}},
3553 {"tdllei", OPTO(2,TOLLE
), OPTO_MASK
, PPC64
, PPCVLE
, {RA
, SI
}},
3554 {"tdlngi", OPTO(2,TOLNG
), OPTO_MASK
, PPC64
, PPCVLE
, {RA
, SI
}},
3555 {"tdgti", OPTO(2,TOGT
), OPTO_MASK
, PPC64
, PPCVLE
, {RA
, SI
}},
3556 {"tdgei", OPTO(2,TOGE
), OPTO_MASK
, PPC64
, PPCVLE
, {RA
, SI
}},
3557 {"tdnli", OPTO(2,TONL
), OPTO_MASK
, PPC64
, PPCVLE
, {RA
, SI
}},
3558 {"tdlti", OPTO(2,TOLT
), OPTO_MASK
, PPC64
, PPCVLE
, {RA
, SI
}},
3559 {"tdlei", OPTO(2,TOLE
), OPTO_MASK
, PPC64
, PPCVLE
, {RA
, SI
}},
3560 {"tdngi", OPTO(2,TONG
), OPTO_MASK
, PPC64
, PPCVLE
, {RA
, SI
}},
3561 {"tdnei", OPTO(2,TONE
), OPTO_MASK
, PPC64
, PPCVLE
, {RA
, SI
}},
3562 {"tdui", OPTO(2,TOU
), OPTO_MASK
, PPC64
, PPCVLE
, {RA
, SI
}},
3563 {"tdi", OP(2), OP_MASK
, PPC64
, PPCVLE
, {TO
, RA
, SI
}},
3565 {"twlgti", OPTO(3,TOLGT
), OPTO_MASK
, PPCCOM
, PPCVLE
, {RA
, SI
}},
3566 {"tlgti", OPTO(3,TOLGT
), OPTO_MASK
, PWRCOM
, PPCVLE
, {RA
, SI
}},
3567 {"twllti", OPTO(3,TOLLT
), OPTO_MASK
, PPCCOM
, PPCVLE
, {RA
, SI
}},
3568 {"tllti", OPTO(3,TOLLT
), OPTO_MASK
, PWRCOM
, PPCVLE
, {RA
, SI
}},
3569 {"tweqi", OPTO(3,TOEQ
), OPTO_MASK
, PPCCOM
, PPCVLE
, {RA
, SI
}},
3570 {"teqi", OPTO(3,TOEQ
), OPTO_MASK
, PWRCOM
, PPCVLE
, {RA
, SI
}},
3571 {"twlgei", OPTO(3,TOLGE
), OPTO_MASK
, PPCCOM
, PPCVLE
, {RA
, SI
}},
3572 {"tlgei", OPTO(3,TOLGE
), OPTO_MASK
, PWRCOM
, PPCVLE
, {RA
, SI
}},
3573 {"twlnli", OPTO(3,TOLNL
), OPTO_MASK
, PPCCOM
, PPCVLE
, {RA
, SI
}},
3574 {"tlnli", OPTO(3,TOLNL
), OPTO_MASK
, PWRCOM
, PPCVLE
, {RA
, SI
}},
3575 {"twllei", OPTO(3,TOLLE
), OPTO_MASK
, PPCCOM
, PPCVLE
, {RA
, SI
}},
3576 {"tllei", OPTO(3,TOLLE
), OPTO_MASK
, PWRCOM
, PPCVLE
, {RA
, SI
}},
3577 {"twlngi", OPTO(3,TOLNG
), OPTO_MASK
, PPCCOM
, PPCVLE
, {RA
, SI
}},
3578 {"tlngi", OPTO(3,TOLNG
), OPTO_MASK
, PWRCOM
, PPCVLE
, {RA
, SI
}},
3579 {"twgti", OPTO(3,TOGT
), OPTO_MASK
, PPCCOM
, PPCVLE
, {RA
, SI
}},
3580 {"tgti", OPTO(3,TOGT
), OPTO_MASK
, PWRCOM
, PPCVLE
, {RA
, SI
}},
3581 {"twgei", OPTO(3,TOGE
), OPTO_MASK
, PPCCOM
, PPCVLE
, {RA
, SI
}},
3582 {"tgei", OPTO(3,TOGE
), OPTO_MASK
, PWRCOM
, PPCVLE
, {RA
, SI
}},
3583 {"twnli", OPTO(3,TONL
), OPTO_MASK
, PPCCOM
, PPCVLE
, {RA
, SI
}},
3584 {"tnli", OPTO(3,TONL
), OPTO_MASK
, PWRCOM
, PPCVLE
, {RA
, SI
}},
3585 {"twlti", OPTO(3,TOLT
), OPTO_MASK
, PPCCOM
, PPCVLE
, {RA
, SI
}},
3586 {"tlti", OPTO(3,TOLT
), OPTO_MASK
, PWRCOM
, PPCVLE
, {RA
, SI
}},
3587 {"twlei", OPTO(3,TOLE
), OPTO_MASK
, PPCCOM
, PPCVLE
, {RA
, SI
}},
3588 {"tlei", OPTO(3,TOLE
), OPTO_MASK
, PWRCOM
, PPCVLE
, {RA
, SI
}},
3589 {"twngi", OPTO(3,TONG
), OPTO_MASK
, PPCCOM
, PPCVLE
, {RA
, SI
}},
3590 {"tngi", OPTO(3,TONG
), OPTO_MASK
, PWRCOM
, PPCVLE
, {RA
, SI
}},
3591 {"twnei", OPTO(3,TONE
), OPTO_MASK
, PPCCOM
, PPCVLE
, {RA
, SI
}},
3592 {"tnei", OPTO(3,TONE
), OPTO_MASK
, PWRCOM
, PPCVLE
, {RA
, SI
}},
3593 {"twui", OPTO(3,TOU
), OPTO_MASK
, PPCCOM
, PPCVLE
, {RA
, SI
}},
3594 {"tui", OPTO(3,TOU
), OPTO_MASK
, PWRCOM
, PPCVLE
, {RA
, SI
}},
3595 {"twi", OP(3), OP_MASK
, PPCCOM
, PPCVLE
, {TO
, RA
, SI
}},
3596 {"ti", OP(3), OP_MASK
, PWRCOM
, PPCVLE
, {TO
, RA
, SI
}},
3598 {"ps_cmpu0", X (4, 0), XBF_MASK
, PPCPS
, 0, {BF
, FRA
, FRB
}},
3599 {"vaddubm", VX (4, 0), VX_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
3600 {"vmul10cuq", VX (4, 1), VXVB_MASK
, PPCVEC3
, 0, {VD
, VA
}},
3601 {"vmaxub", VX (4, 2), VX_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
3602 {"vrlb", VX (4, 4), VX_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
3603 {"vcmpequb", VXR(4, 6,0), VXR_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
3604 {"vcmpneb", VXR(4, 7,0), VXR_MASK
, PPCVEC3
, 0, {VD
, VA
, VB
}},
3605 {"vmuloub", VX (4, 8), VX_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
3606 {"vaddfp", VX (4, 10), VX_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
3607 {"psq_lx", XW (4, 6,0), XW_MASK
, PPCPS
, 0, {FRT
,RA
,RB
,PSWM
,PSQM
}},
3608 {"vmrghb", VX (4, 12), VX_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
3609 {"psq_stx", XW (4, 7,0), XW_MASK
, PPCPS
, 0, {FRS
,RA
,RB
,PSWM
,PSQM
}},
3610 {"vpkuhum", VX (4, 14), VX_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
3611 {"mulhhwu", XRC(4, 8,0), X_MASK
, MULHW
, 0, {RT
, RA
, RB
}},
3612 {"mulhhwu.", XRC(4, 8,1), X_MASK
, MULHW
, 0, {RT
, RA
, RB
}},
3613 {"ps_sum0", A (4, 10,0), A_MASK
, PPCPS
, 0, {FRT
, FRA
, FRC
, FRB
}},
3614 {"ps_sum0.", A (4, 10,1), A_MASK
, PPCPS
, 0, {FRT
, FRA
, FRC
, FRB
}},
3615 {"ps_sum1", A (4, 11,0), A_MASK
, PPCPS
, 0, {FRT
, FRA
, FRC
, FRB
}},
3616 {"ps_sum1.", A (4, 11,1), A_MASK
, PPCPS
, 0, {FRT
, FRA
, FRC
, FRB
}},
3617 {"ps_muls0", A (4, 12,0), AFRB_MASK
, PPCPS
, 0, {FRT
, FRA
, FRC
}},
3618 {"machhwu", XO (4, 12,0,0), XO_MASK
, MULHW
, 0, {RT
, RA
, RB
}},
3619 {"ps_muls0.", A (4, 12,1), AFRB_MASK
, PPCPS
, 0, {FRT
, FRA
, FRC
}},
3620 {"machhwu.", XO (4, 12,0,1), XO_MASK
, MULHW
, 0, {RT
, RA
, RB
}},
3621 {"ps_muls1", A (4, 13,0), AFRB_MASK
, PPCPS
, 0, {FRT
, FRA
, FRC
}},
3622 {"ps_muls1.", A (4, 13,1), AFRB_MASK
, PPCPS
, 0, {FRT
, FRA
, FRC
}},
3623 {"ps_madds0", A (4, 14,0), A_MASK
, PPCPS
, 0, {FRT
, FRA
, FRC
, FRB
}},
3624 {"ps_madds0.", A (4, 14,1), A_MASK
, PPCPS
, 0, {FRT
, FRA
, FRC
, FRB
}},
3625 {"ps_madds1", A (4, 15,0), A_MASK
, PPCPS
, 0, {FRT
, FRA
, FRC
, FRB
}},
3626 {"ps_madds1.", A (4, 15,1), A_MASK
, PPCPS
, 0, {FRT
, FRA
, FRC
, FRB
}},
3627 {"vmhaddshs", VXA(4, 32), VXA_MASK
, PPCVEC
, 0, {VD
, VA
, VB
, VC
}},
3628 {"vmhraddshs", VXA(4, 33), VXA_MASK
, PPCVEC
, 0, {VD
, VA
, VB
, VC
}},
3629 {"vmladduhm", VXA(4, 34), VXA_MASK
, PPCVEC
, 0, {VD
, VA
, VB
, VC
}},
3630 {"vmsumudm", VXA(4, 35), VXA_MASK
, PPCVEC3
, 0, {VD
, VA
, VB
, VC
}},
3631 {"ps_div", A (4, 18,0), AFRC_MASK
, PPCPS
, 0, {FRT
, FRA
, FRB
}},
3632 {"vmsumubm", VXA(4, 36), VXA_MASK
, PPCVEC
, 0, {VD
, VA
, VB
, VC
}},
3633 {"ps_div.", A (4, 18,1), AFRC_MASK
, PPCPS
, 0, {FRT
, FRA
, FRB
}},
3634 {"vmsummbm", VXA(4, 37), VXA_MASK
, PPCVEC
, 0, {VD
, VA
, VB
, VC
}},
3635 {"vmsumuhm", VXA(4, 38), VXA_MASK
, PPCVEC
, 0, {VD
, VA
, VB
, VC
}},
3636 {"vmsumuhs", VXA(4, 39), VXA_MASK
, PPCVEC
, 0, {VD
, VA
, VB
, VC
}},
3637 {"ps_sub", A (4, 20,0), AFRC_MASK
, PPCPS
, 0, {FRT
, FRA
, FRB
}},
3638 {"vmsumshm", VXA(4, 40), VXA_MASK
, PPCVEC
, 0, {VD
, VA
, VB
, VC
}},
3639 {"ps_sub.", A (4, 20,1), AFRC_MASK
, PPCPS
, 0, {FRT
, FRA
, FRB
}},
3640 {"vmsumshs", VXA(4, 41), VXA_MASK
, PPCVEC
, 0, {VD
, VA
, VB
, VC
}},
3641 {"ps_add", A (4, 21,0), AFRC_MASK
, PPCPS
, 0, {FRT
, FRA
, FRB
}},
3642 {"vsel", VXA(4, 42), VXA_MASK
, PPCVEC
, 0, {VD
, VA
, VB
, VC
}},
3643 {"ps_add.", A (4, 21,1), AFRC_MASK
, PPCPS
, 0, {FRT
, FRA
, FRB
}},
3644 {"vperm", VXA(4, 43), VXA_MASK
, PPCVEC
, 0, {VD
, VA
, VB
, VC
}},
3645 {"vsldoi", VXA(4, 44), VXASHB_MASK
, PPCVEC
, 0, {VD
, VA
, VB
, SHB
}},
3646 {"vpermxor", VXA(4, 45), VXA_MASK
, PPCVEC2
, 0, {VD
, VA
, VB
, VC
}},
3647 {"ps_sel", A (4, 23,0), A_MASK
, PPCPS
, 0, {FRT
, FRA
, FRC
, FRB
}},
3648 {"vmaddfp", VXA(4, 46), VXA_MASK
, PPCVEC
, 0, {VD
, VA
, VC
, VB
}},
3649 {"ps_sel.", A (4, 23,1), A_MASK
, PPCPS
, 0, {FRT
, FRA
, FRC
, FRB
}},
3650 {"vnmsubfp", VXA(4, 47), VXA_MASK
, PPCVEC
, 0, {VD
, VA
, VC
, VB
}},
3651 {"ps_res", A (4, 24,0), AFRAFRC_MASK
, PPCPS
, 0, {FRT
, FRB
}},
3652 {"maddhd", VXA(4, 48), VXA_MASK
, POWER9
, 0, {RT
, RA
, RB
, RC
}},
3653 {"ps_res.", A (4, 24,1), AFRAFRC_MASK
, PPCPS
, 0, {FRT
, FRB
}},
3654 {"maddhdu", VXA(4, 49), VXA_MASK
, POWER9
, 0, {RT
, RA
, RB
, RC
}},
3655 {"ps_mul", A (4, 25,0), AFRB_MASK
, PPCPS
, 0, {FRT
, FRA
, FRC
}},
3656 {"ps_mul.", A (4, 25,1), AFRB_MASK
, PPCPS
, 0, {FRT
, FRA
, FRC
}},
3657 {"maddld", VXA(4, 51), VXA_MASK
, POWER9
, 0, {RT
, RA
, RB
, RC
}},
3658 {"ps_rsqrte", A (4, 26,0), AFRAFRC_MASK
, PPCPS
, 0, {FRT
, FRB
}},
3659 {"ps_rsqrte.", A (4, 26,1), AFRAFRC_MASK
, PPCPS
, 0, {FRT
, FRB
}},
3660 {"ps_msub", A (4, 28,0), A_MASK
, PPCPS
, 0, {FRT
, FRA
, FRC
, FRB
}},
3661 {"ps_msub.", A (4, 28,1), A_MASK
, PPCPS
, 0, {FRT
, FRA
, FRC
, FRB
}},
3662 {"ps_madd", A (4, 29,0), A_MASK
, PPCPS
, 0, {FRT
, FRA
, FRC
, FRB
}},
3663 {"ps_madd.", A (4, 29,1), A_MASK
, PPCPS
, 0, {FRT
, FRA
, FRC
, FRB
}},
3664 {"vpermr", VXA(4, 59), VXA_MASK
, PPCVEC3
, 0, {VD
, VA
, VB
, VC
}},
3665 {"ps_nmsub", A (4, 30,0), A_MASK
, PPCPS
, 0, {FRT
, FRA
, FRC
, FRB
}},
3666 {"vaddeuqm", VXA(4, 60), VXA_MASK
, PPCVEC2
, 0, {VD
, VA
, VB
, VC
}},
3667 {"ps_nmsub.", A (4, 30,1), A_MASK
, PPCPS
, 0, {FRT
, FRA
, FRC
, FRB
}},
3668 {"vaddecuq", VXA(4, 61), VXA_MASK
, PPCVEC2
, 0, {VD
, VA
, VB
, VC
}},
3669 {"ps_nmadd", A (4, 31,0), A_MASK
, PPCPS
, 0, {FRT
, FRA
, FRC
, FRB
}},
3670 {"vsubeuqm", VXA(4, 62), VXA_MASK
, PPCVEC2
, 0, {VD
, VA
, VB
, VC
}},
3671 {"ps_nmadd.", A (4, 31,1), A_MASK
, PPCPS
, 0, {FRT
, FRA
, FRC
, FRB
}},
3672 {"vsubecuq", VXA(4, 63), VXA_MASK
, PPCVEC2
, 0, {VD
, VA
, VB
, VC
}},
3673 {"ps_cmpo0", X (4, 32), XBF_MASK
, PPCPS
, 0, {BF
, FRA
, FRB
}},
3674 {"vadduhm", VX (4, 64), VX_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
3675 {"vmul10ecuq", VX (4, 65), VX_MASK
, PPCVEC3
, 0, {VD
, VA
, VB
}},
3676 {"vmaxuh", VX (4, 66), VX_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
3677 {"vrlh", VX (4, 68), VX_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
3678 {"vcmpequh", VXR(4, 70,0), VXR_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
3679 {"vcmpneh", VXR(4, 71,0), VXR_MASK
, PPCVEC3
, 0, {VD
, VA
, VB
}},
3680 {"vmulouh", VX (4, 72), VX_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
3681 {"vsubfp", VX (4, 74), VX_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
3682 {"psq_lux", XW (4, 38,0), XW_MASK
, PPCPS
, 0, {FRT
,RA
,RB
,PSWM
,PSQM
}},
3683 {"vmrghh", VX (4, 76), VX_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
3684 {"psq_stux", XW (4, 39,0), XW_MASK
, PPCPS
, 0, {FRS
,RA
,RB
,PSWM
,PSQM
}},
3685 {"vpkuwum", VX (4, 78), VX_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
3686 {"ps_neg", XRC(4, 40,0), XRA_MASK
, PPCPS
, 0, {FRT
, FRB
}},
3687 {"mulhhw", XRC(4, 40,0), X_MASK
, MULHW
, 0, {RT
, RA
, RB
}},
3688 {"ps_neg.", XRC(4, 40,1), XRA_MASK
, PPCPS
, 0, {FRT
, FRB
}},
3689 {"mulhhw.", XRC(4, 40,1), X_MASK
, MULHW
, 0, {RT
, RA
, RB
}},
3690 {"machhw", XO (4, 44,0,0), XO_MASK
, MULHW
, 0, {RT
, RA
, RB
}},
3691 {"machhw.", XO (4, 44,0,1), XO_MASK
, MULHW
, 0, {RT
, RA
, RB
}},
3692 {"nmachhw", XO (4, 46,0,0), XO_MASK
, MULHW
, 0, {RT
, RA
, RB
}},
3693 {"nmachhw.", XO (4, 46,0,1), XO_MASK
, MULHW
, 0, {RT
, RA
, RB
}},
3694 {"ps_cmpu1", X (4, 64), XBF_MASK
, PPCPS
, 0, {BF
, FRA
, FRB
}},
3695 {"vadduwm", VX (4, 128), VX_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
3696 {"vmaxuw", VX (4, 130), VX_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
3697 {"vrlw", VX (4, 132), VX_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
3698 {"vrlwmi", VX (4, 133), VX_MASK
, PPCVEC3
, 0, {VD
, VA
, VB
}},
3699 {"vcmpequw", VXR(4, 134,0), VXR_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
3700 {"vcmpnew", VXR(4, 135,0), VXR_MASK
, PPCVEC3
, 0, {VD
, VA
, VB
}},
3701 {"vmulouw", VX (4, 136), VX_MASK
, PPCVEC2
, 0, {VD
, VA
, VB
}},
3702 {"vmuluwm", VX (4, 137), VX_MASK
, PPCVEC2
, 0, {VD
, VA
, VB
}},
3703 {"vmrghw", VX (4, 140), VX_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
3704 {"vpkuhus", VX (4, 142), VX_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
3705 {"ps_mr", XRC(4, 72,0), XRA_MASK
, PPCPS
, 0, {FRT
, FRB
}},
3706 {"ps_mr.", XRC(4, 72,1), XRA_MASK
, PPCPS
, 0, {FRT
, FRB
}},
3707 {"machhwsu", XO (4, 76,0,0), XO_MASK
, MULHW
, 0, {RT
, RA
, RB
}},
3708 {"machhwsu.", XO (4, 76,0,1), XO_MASK
, MULHW
, 0, {RT
, RA
, RB
}},
3709 {"ps_cmpo1", X (4, 96), XBF_MASK
, PPCPS
, 0, {BF
, FRA
, FRB
}},
3710 {"vaddudm", VX (4, 192), VX_MASK
, PPCVEC2
, 0, {VD
, VA
, VB
}},
3711 {"vmaxud", VX (4, 194), VX_MASK
, PPCVEC2
, 0, {VD
, VA
, VB
}},
3712 {"vrld", VX (4, 196), VX_MASK
, PPCVEC2
, 0, {VD
, VA
, VB
}},
3713 {"vrldmi", VX (4, 197), VX_MASK
, PPCVEC3
, 0, {VD
, VA
, VB
}},
3714 {"vcmpeqfp", VXR(4, 198,0), VXR_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
3715 {"vcmpequd", VXR(4, 199,0), VXR_MASK
, PPCVEC2
, 0, {VD
, VA
, VB
}},
3716 {"vpkuwus", VX (4, 206), VX_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
3717 {"machhws", XO (4, 108,0,0), XO_MASK
, MULHW
, 0, {RT
, RA
, RB
}},
3718 {"machhws.", XO (4, 108,0,1), XO_MASK
, MULHW
, 0, {RT
, RA
, RB
}},
3719 {"nmachhws", XO (4, 110,0,0), XO_MASK
, MULHW
, 0, {RT
, RA
, RB
}},
3720 {"nmachhws.", XO (4, 110,0,1), XO_MASK
, MULHW
, 0, {RT
, RA
, RB
}},
3721 {"vadduqm", VX (4, 256), VX_MASK
, PPCVEC2
, 0, {VD
, VA
, VB
}},
3722 {"vmaxsb", VX (4, 258), VX_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
3723 {"vslb", VX (4, 260), VX_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
3724 {"vcmpnezb", VXR(4, 263,0), VXR_MASK
, PPCVEC3
, 0, {VD
, VA
, VB
}},
3725 {"vmulosb", VX (4, 264), VX_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
3726 {"vrefp", VX (4, 266), VXVA_MASK
, PPCVEC
, 0, {VD
, VB
}},
3727 {"vmrglb", VX (4, 268), VX_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
3728 {"vpkshus", VX (4, 270), VX_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
3729 {"ps_nabs", XRC(4, 136,0), XRA_MASK
, PPCPS
, 0, {FRT
, FRB
}},
3730 {"mulchwu", XRC(4, 136,0), X_MASK
, MULHW
, 0, {RT
, RA
, RB
}},
3731 {"ps_nabs.", XRC(4, 136,1), XRA_MASK
, PPCPS
, 0, {FRT
, FRB
}},
3732 {"mulchwu.", XRC(4, 136,1), X_MASK
, MULHW
, 0, {RT
, RA
, RB
}},
3733 {"macchwu", XO (4, 140,0,0), XO_MASK
, MULHW
, 0, {RT
, RA
, RB
}},
3734 {"macchwu.", XO (4, 140,0,1), XO_MASK
, MULHW
, 0, {RT
, RA
, RB
}},
3735 {"vaddcuq", VX (4, 320), VX_MASK
, PPCVEC2
, 0, {VD
, VA
, VB
}},
3736 {"vmaxsh", VX (4, 322), VX_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
3737 {"vslh", VX (4, 324), VX_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
3738 {"vcmpnezh", VXR(4, 327,0), VXR_MASK
, PPCVEC3
, 0, {VD
, VA
, VB
}},
3739 {"vmulosh", VX (4, 328), VX_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
3740 {"vrsqrtefp", VX (4, 330), VXVA_MASK
, PPCVEC
, 0, {VD
, VB
}},
3741 {"vmrglh", VX (4, 332), VX_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
3742 {"vpkswus", VX (4, 334), VX_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
3743 {"mulchw", XRC(4, 168,0), X_MASK
, MULHW
, 0, {RT
, RA
, RB
}},
3744 {"mulchw.", XRC(4, 168,1), X_MASK
, MULHW
, 0, {RT
, RA
, RB
}},
3745 {"macchw", XO (4, 172,0,0), XO_MASK
, MULHW
, 0, {RT
, RA
, RB
}},
3746 {"macchw.", XO (4, 172,0,1), XO_MASK
, MULHW
, 0, {RT
, RA
, RB
}},
3747 {"nmacchw", XO (4, 174,0,0), XO_MASK
, MULHW
, 0, {RT
, RA
, RB
}},
3748 {"nmacchw.", XO (4, 174,0,1), XO_MASK
, MULHW
, 0, {RT
, RA
, RB
}},
3749 {"vaddcuw", VX (4, 384), VX_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
3750 {"vmaxsw", VX (4, 386), VX_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
3751 {"vslw", VX (4, 388), VX_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
3752 {"vrlwnm", VX (4, 389), VX_MASK
, PPCVEC3
, 0, {VD
, VA
, VB
}},
3753 {"vcmpnezw", VXR(4, 391,0), VXR_MASK
, PPCVEC3
, 0, {VD
, VA
, VB
}},
3754 {"vmulosw", VX (4, 392), VX_MASK
, PPCVEC2
, 0, {VD
, VA
, VB
}},
3755 {"vexptefp", VX (4, 394), VXVA_MASK
, PPCVEC
, 0, {VD
, VB
}},
3756 {"vmrglw", VX (4, 396), VX_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
3757 {"vpkshss", VX (4, 398), VX_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
3758 {"macchwsu", XO (4, 204,0,0), XO_MASK
, MULHW
, 0, {RT
, RA
, RB
}},
3759 {"macchwsu.", XO (4, 204,0,1), XO_MASK
, MULHW
, 0, {RT
, RA
, RB
}},
3760 {"vmaxsd", VX (4, 450), VX_MASK
, PPCVEC2
, 0, {VD
, VA
, VB
}},
3761 {"vsl", VX (4, 452), VX_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
3762 {"vrldnm", VX (4, 453), VX_MASK
, PPCVEC3
, 0, {VD
, VA
, VB
}},
3763 {"vcmpgefp", VXR(4, 454,0), VXR_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
3764 {"vlogefp", VX (4, 458), VXVA_MASK
, PPCVEC
, 0, {VD
, VB
}},
3765 {"vpkswss", VX (4, 462), VX_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
3766 {"macchws", XO (4, 236,0,0), XO_MASK
, MULHW
, 0, {RT
, RA
, RB
}},
3767 {"macchws.", XO (4, 236,0,1), XO_MASK
, MULHW
, 0, {RT
, RA
, RB
}},
3768 {"nmacchws", XO (4, 238,0,0), XO_MASK
, MULHW
, 0, {RT
, RA
, RB
}},
3769 {"nmacchws.", XO (4, 238,0,1), XO_MASK
, MULHW
, 0, {RT
, RA
, RB
}},
3770 {"evaddw", VX (4, 512), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
3771 {"vaddubs", VX (4, 512), VX_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
3772 {"vmul10uq", VX (4, 513), VXVB_MASK
, PPCVEC3
, 0, {VD
, VA
}},
3773 {"evaddiw", VX (4, 514), VX_MASK
, PPCSPE
, 0, {RS
, RB
, UIMM
}},
3774 {"vminub", VX (4, 514), VX_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
3775 {"evsubfw", VX (4, 516), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
3776 {"evsubw", VX (4, 516), VX_MASK
, PPCSPE
, 0, {RS
, RB
, RA
}},
3777 {"vsrb", VX (4, 516), VX_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
3778 {"evsubifw", VX (4, 518), VX_MASK
, PPCSPE
, 0, {RS
, UIMM
, RB
}},
3779 {"evsubiw", VX (4, 518), VX_MASK
, PPCSPE
, 0, {RS
, RB
, UIMM
}},
3780 {"vcmpgtub", VXR(4, 518,0), VXR_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
3781 {"evabs", VX (4, 520), VX_MASK
, PPCSPE
, 0, {RS
, RA
}},
3782 {"vmuleub", VX (4, 520), VX_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
3783 {"evneg", VX (4, 521), VX_MASK
, PPCSPE
, 0, {RS
, RA
}},
3784 {"evextsb", VX (4, 522), VX_MASK
, PPCSPE
, 0, {RS
, RA
}},
3785 {"vrfin", VX (4, 522), VXVA_MASK
, PPCVEC
, 0, {VD
, VB
}},
3786 {"evextsh", VX (4, 523), VX_MASK
, PPCSPE
, 0, {RS
, RA
}},
3787 {"evrndw", VX (4, 524), VX_MASK
, PPCSPE
, 0, {RS
, RA
}},
3788 {"vspltb", VX (4, 524), VXUIMM4_MASK
, PPCVEC
, 0, {VD
, VB
, UIMM4
}},
3789 {"vextractub", VX (4, 525), VXUIMM4_MASK
, PPCVEC3
, 0, {VD
, VB
, UIMM4
}},
3790 {"evcntlzw", VX (4, 525), VX_MASK
, PPCSPE
, 0, {RS
, RA
}},
3791 {"evcntlsw", VX (4, 526), VX_MASK
, PPCSPE
, 0, {RS
, RA
}},
3792 {"vupkhsb", VX (4, 526), VXVA_MASK
, PPCVEC
, 0, {VD
, VB
}},
3793 {"brinc", VX (4, 527), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
3794 {"ps_abs", XRC(4, 264,0), XRA_MASK
, PPCPS
, 0, {FRT
, FRB
}},
3795 {"ps_abs.", XRC(4, 264,1), XRA_MASK
, PPCPS
, 0, {FRT
, FRB
}},
3796 {"evand", VX (4, 529), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
3797 {"evandc", VX (4, 530), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
3798 {"evxor", VX (4, 534), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
3799 {"evmr", VX (4, 535), VX_MASK
, PPCSPE
, 0, {RS
, RA
, BBA
}},
3800 {"evor", VX (4, 535), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
3801 {"evnor", VX (4, 536), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
3802 {"evnot", VX (4, 536), VX_MASK
, PPCSPE
, 0, {RS
, RA
, BBA
}},
3803 {"get", APU(4, 268,0), APU_RA_MASK
, PPC405
, 0, {RT
, FSL
}},
3804 {"eveqv", VX (4, 537), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
3805 {"evorc", VX (4, 539), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
3806 {"evnand", VX (4, 542), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
3807 {"evsrwu", VX (4, 544), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
3808 {"evsrws", VX (4, 545), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
3809 {"evsrwiu", VX (4, 546), VX_MASK
, PPCSPE
, 0, {RS
, RA
, EVUIMM
}},
3810 {"evsrwis", VX (4, 547), VX_MASK
, PPCSPE
, 0, {RS
, RA
, EVUIMM
}},
3811 {"evslw", VX (4, 548), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
3812 {"evslwi", VX (4, 550), VX_MASK
, PPCSPE
, 0, {RS
, RA
, EVUIMM
}},
3813 {"evrlw", VX (4, 552), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
3814 {"evsplati", VX (4, 553), VX_MASK
, PPCSPE
, 0, {RS
, SIMM
}},
3815 {"evrlwi", VX (4, 554), VX_MASK
, PPCSPE
, 0, {RS
, RA
, EVUIMM
}},
3816 {"evsplatfi", VX (4, 555), VX_MASK
, PPCSPE
, 0, {RS
, SIMM
}},
3817 {"evmergehi", VX (4, 556), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
3818 {"evmergelo", VX (4, 557), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
3819 {"evmergehilo", VX (4, 558), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
3820 {"evmergelohi", VX (4, 559), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
3821 {"evcmpgtu", VX (4, 560), VX_MASK
, PPCSPE
, 0, {CRFD
, RA
, RB
}},
3822 {"evcmpgts", VX (4, 561), VX_MASK
, PPCSPE
, 0, {CRFD
, RA
, RB
}},
3823 {"evcmpltu", VX (4, 562), VX_MASK
, PPCSPE
, 0, {CRFD
, RA
, RB
}},
3824 {"evcmplts", VX (4, 563), VX_MASK
, PPCSPE
, 0, {CRFD
, RA
, RB
}},
3825 {"evcmpeq", VX (4, 564), VX_MASK
, PPCSPE
, 0, {CRFD
, RA
, RB
}},
3826 {"cget", APU(4, 284,0), APU_RA_MASK
, PPC405
, 0, {RT
, FSL
}},
3827 {"vadduhs", VX (4, 576), VX_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
3828 {"vmul10euq", VX (4, 577), VX_MASK
, PPCVEC3
, 0, {VD
, VA
, VB
}},
3829 {"vminuh", VX (4, 578), VX_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
3830 {"vsrh", VX (4, 580), VX_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
3831 {"vcmpgtuh", VXR(4, 582,0), VXR_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
3832 {"vmuleuh", VX (4, 584), VX_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
3833 {"vrfiz", VX (4, 586), VXVA_MASK
, PPCVEC
, 0, {VD
, VB
}},
3834 {"vsplth", VX (4, 588), VXUIMM3_MASK
, PPCVEC
, 0, {VD
, VB
, UIMM3
}},
3835 {"vextractuh", VX (4, 589), VXUIMM4_MASK
, PPCVEC3
, 0, {VD
, VB
, UIMM4
}},
3836 {"vupkhsh", VX (4, 590), VXVA_MASK
, PPCVEC
, 0, {VD
, VB
}},
3837 {"nget", APU(4, 300,0), APU_RA_MASK
, PPC405
, 0, {RT
, FSL
}},
3838 {"evsel", EVSEL(4,79), EVSEL_MASK
, PPCSPE
, 0, {RS
, RA
, RB
, CRFS
}},
3839 {"ncget", APU(4, 316,0), APU_RA_MASK
, PPC405
, 0, {RT
, FSL
}},
3840 {"evfsadd", VX (4, 640), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
3841 {"vadduws", VX (4, 640), VX_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
3842 {"evfssub", VX (4, 641), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
3843 {"evfsmadd", VX (4, 642), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
3844 {"vminuw", VX (4, 642), VX_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
3845 {"evfsmsub", VX (4, 643), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
3846 {"evfsabs", VX (4, 644), VX_MASK
, PPCSPE
, 0, {RS
, RA
}},
3847 {"vsrw", VX (4, 644), VX_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
3848 {"evfsnabs", VX (4, 645), VX_MASK
, PPCSPE
, 0, {RS
, RA
}},
3849 {"evfsneg", VX (4, 646), VX_MASK
, PPCSPE
, 0, {RS
, RA
}},
3850 {"vcmpgtuw", VXR(4, 646,0), VXR_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
3851 {"evfssqrt", VX_RB_CONST(4, 647, 0), VX_RB_CONST_MASK
, PPCEFS2
, 0, {RD
, RA
}},
3852 {"vmuleuw", VX (4, 648), VX_MASK
, PPCVEC2
, 0, {VD
, VA
, VB
}},
3853 {"evfsmul", VX (4, 648), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
3854 {"evfsdiv", VX (4, 649), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
3855 {"evfsnmadd", VX (4, 650), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
3856 {"vrfip", VX (4, 650), VXVA_MASK
, PPCVEC
, 0, {VD
, VB
}},
3857 {"evfsnmsub", VX (4, 651), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
3858 {"evfscmpgt", VX (4, 652), VX_MASK
, PPCSPE
, 0, {CRFD
, RA
, RB
}},
3859 {"vspltw", VX (4, 652), VXUIMM2_MASK
, PPCVEC
, 0, {VD
, VB
, UIMM2
}},
3860 {"vextractuw", VX (4, 653), VXUIMM4_MASK
, PPCVEC3
, 0, {VD
, VB
, UIMM4
}},
3861 {"evfscmplt", VX (4, 653), VX_MASK
, PPCSPE
, 0, {CRFD
, RA
, RB
}},
3862 {"evfscmpeq", VX (4, 654), VX_MASK
, PPCSPE
, 0, {CRFD
, RA
, RB
}},
3863 {"vupklsb", VX (4, 654), VXVA_MASK
, PPCVEC
, 0, {VD
, VB
}},
3864 {"evfscfui", VX (4, 656), VX_MASK
, PPCSPE
, 0, {RS
, RB
}},
3865 {"evfscfh", VX_RA_CONST(4, 657, 4), VX_RA_CONST_MASK
, PPCEFS2
, 0, {RD
, RB
}},
3866 {"evfscfsi", VX (4, 657), VX_MASK
, PPCSPE
, 0, {RS
, RB
}},
3867 {"evfscfuf", VX (4, 658), VX_MASK
, PPCSPE
, 0, {RS
, RB
}},
3868 {"evfscfsf", VX (4, 659), VX_MASK
, PPCSPE
, 0, {RS
, RB
}},
3869 {"evfsctui", VX (4, 660), VX_MASK
, PPCSPE
, 0, {RS
, RB
}},
3870 {"evfscth", VX_RA_CONST(4, 661, 4), VX_RA_CONST_MASK
, PPCEFS2
, 0, {RD
, RB
}},
3871 {"evfsctsi", VX (4, 661), VX_MASK
, PPCSPE
, 0, {RS
, RB
}},
3872 {"evfsctuf", VX (4, 662), VX_MASK
, PPCSPE
, 0, {RS
, RB
}},
3873 {"evfsctsf", VX (4, 663), VX_MASK
, PPCSPE
, 0, {RS
, RB
}},
3874 {"evfsctuiz", VX (4, 664), VX_MASK
, PPCSPE
, 0, {RS
, RB
}},
3875 {"put", APU(4, 332,0), APU_RT_MASK
, PPC405
, 0, {RA
, FSL
}},
3876 {"evfsctsiz", VX (4, 666), VX_MASK
, PPCSPE
, 0, {RS
, RB
}},
3877 {"evfststgt", VX (4, 668), VX_MASK
, PPCSPE
, 0, {CRFD
, RA
, RB
}},
3878 {"evfststlt", VX (4, 669), VX_MASK
, PPCSPE
, 0, {CRFD
, RA
, RB
}},
3879 {"evfststeq", VX (4, 670), VX_MASK
, PPCSPE
, 0, {CRFD
, RA
, RB
}},
3880 {"evfsmax", VX (4, 672), VX_MASK
, PPCEFS2
, 0, {RD
, RA
, RB
}},
3881 {"evfsmin", VX (4, 673), VX_MASK
, PPCEFS2
, 0, {RD
, RA
, RB
}},
3882 {"evfsaddsub", VX (4, 674), VX_MASK
, PPCEFS2
, 0, {RD
, RA
, RB
}},
3883 {"evfssubadd", VX (4, 675), VX_MASK
, PPCEFS2
, 0, {RD
, RA
, RB
}},
3884 {"evfssum", VX (4, 676), VX_MASK
, PPCEFS2
, 0, {RD
, RA
, RB
}},
3885 {"evfsdiff", VX (4, 677), VX_MASK
, PPCEFS2
, 0, {RD
, RA
, RB
}},
3886 {"evfssumdiff", VX (4, 678), VX_MASK
, PPCEFS2
, 0, {RD
, RA
, RB
}},
3887 {"evfsdiffsum", VX (4, 679), VX_MASK
, PPCEFS2
, 0, {RD
, RA
, RB
}},
3888 {"evfsaddx", VX (4, 680), VX_MASK
, PPCEFS2
, 0, {RD
, RA
, RB
}},
3889 {"evfssubx", VX (4, 681), VX_MASK
, PPCEFS2
, 0, {RD
, RA
, RB
}},
3890 {"evfsaddsubx", VX (4, 682), VX_MASK
, PPCEFS2
, 0, {RD
, RA
, RB
}},
3891 {"evfssubaddx", VX (4, 683), VX_MASK
, PPCEFS2
, 0, {RD
, RA
, RB
}},
3892 {"evfsmulx", VX (4, 684), VX_MASK
, PPCEFS2
, 0, {RD
, RA
, RB
}},
3893 {"evfsmule", VX (4, 686), VX_MASK
, PPCEFS2
, 0, {RD
, RA
, RB
}},
3894 {"evfsmulo", VX (4, 687), VX_MASK
, PPCEFS2
, 0, {RD
, RA
, RB
}},
3895 {"efsmax", VX (4, 688), VX_MASK
, PPCEFS2
, 0, {RD
, RA
, RB
}},
3896 {"efsmin", VX (4, 689), VX_MASK
, PPCEFS2
, 0, {RD
, RA
, RB
}},
3897 {"efdmax", VX (4, 696), VX_MASK
, PPCEFS2
, 0, {RD
, RA
, RB
}},
3898 {"cput", APU(4, 348,0), APU_RT_MASK
, PPC405
, 0, {RA
, FSL
}},
3899 {"efdmin", VX (4, 697), VX_MASK
, PPCEFS2
, 0, {RD
, RA
, RB
}},
3900 {"efsadd", VX (4, 704), VX_MASK
, PPCEFS
, 0, {RS
, RA
, RB
}},
3901 {"efssub", VX (4, 705), VX_MASK
, PPCEFS
, 0, {RS
, RA
, RB
}},
3902 {"efsmadd", VX (4, 706), VX_MASK
, PPCEFS2
, 0, {RS
, RA
, RB
}},
3903 {"vminud", VX (4, 706), VX_MASK
, PPCVEC2
, 0, {VD
, VA
, VB
}},
3904 {"efsmsub", VX (4, 707), VX_MASK
, PPCEFS2
, 0, {RS
, RA
, RB
}},
3905 {"efsabs", VX (4, 708), VX_MASK
, PPCEFS
, 0, {RS
, RA
}},
3906 {"vsr", VX (4, 708), VX_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
3907 {"efsnabs", VX (4, 709), VX_MASK
, PPCEFS
, 0, {RS
, RA
}},
3908 {"efsneg", VX (4, 710), VX_MASK
, PPCEFS
, 0, {RS
, RA
}},
3909 {"vcmpgtfp", VXR(4, 710,0), VXR_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
3910 {"efssqrt", VX_RB_CONST(4, 711, 0), VX_RB_CONST_MASK
,PPCEFS2
, 0, {RD
, RA
}},
3911 {"vcmpgtud", VXR(4, 711,0), VXR_MASK
, PPCVEC2
, 0, {VD
, VA
, VB
}},
3912 {"efsmul", VX (4, 712), VX_MASK
, PPCEFS
, 0, {RS
, RA
, RB
}},
3913 {"efsdiv", VX (4, 713), VX_MASK
, PPCEFS
, 0, {RS
, RA
, RB
}},
3914 {"efsnmadd", VX (4, 714), VX_MASK
, PPCEFS2
, 0, {RS
, RA
, RB
}},
3915 {"vrfim", VX (4, 714), VXVA_MASK
, PPCVEC
, 0, {VD
, VB
}},
3916 {"efsnmsub", VX (4, 715), VX_MASK
, PPCEFS2
, 0, {RS
, RA
, RB
}},
3917 {"efscmpgt", VX (4, 716), VX_MASK
, PPCEFS
, 0, {CRFD
, RA
, RB
}},
3918 {"vextractd", VX (4, 717), VXUIMM4_MASK
, PPCVEC3
, 0, {VD
, VB
, UIMM4
}},
3919 {"efscmplt", VX (4, 717), VX_MASK
, PPCEFS
, 0, {CRFD
, RA
, RB
}},
3920 {"efscmpeq", VX (4, 718), VX_MASK
, PPCEFS
, 0, {CRFD
, RA
, RB
}},
3921 {"vupklsh", VX (4, 718), VXVA_MASK
, PPCVEC
, 0, {VD
, VB
}},
3922 {"efscfd", VX (4, 719), VX_MASK
, PPCEFS
, 0, {RS
, RB
}},
3923 {"efscfui", VX (4, 720), VX_MASK
, PPCEFS
, 0, {RS
, RB
}},
3924 {"efscfh", VX_RA_CONST(4, 721, 4), VX_RA_CONST_MASK
, PPCEFS2
, 0, {RD
, RB
}},
3925 {"efscfsi", VX (4, 721), VX_MASK
, PPCEFS
, 0, {RS
, RB
}},
3926 {"efscfuf", VX (4, 722), VX_MASK
, PPCEFS
, 0, {RS
, RB
}},
3927 {"efscfsf", VX (4, 723), VX_MASK
, PPCEFS
, 0, {RS
, RB
}},
3928 {"efsctui", VX (4, 724), VX_MASK
, PPCEFS
, 0, {RS
, RB
}},
3929 {"efscth", VX_RA_CONST(4, 725, 4), VX_RA_CONST_MASK
, PPCEFS2
, 0, {RD
, RB
}},
3930 {"efsctsi", VX (4, 725), VX_MASK
, PPCEFS
, 0, {RS
, RB
}},
3931 {"efsctuf", VX (4, 726), VX_MASK
, PPCEFS
, 0, {RS
, RB
}},
3932 {"efsctsf", VX (4, 727), VX_MASK
, PPCEFS
, 0, {RS
, RB
}},
3933 {"efsctuiz", VX (4, 728), VX_MASK
, PPCEFS
, 0, {RS
, RB
}},
3934 {"nput", APU(4, 364,0), APU_RT_MASK
, PPC405
, 0, {RA
, FSL
}},
3935 {"efsctsiz", VX (4, 730), VX_MASK
, PPCEFS
, 0, {RS
, RB
}},
3936 {"efststgt", VX (4, 732), VX_MASK
, PPCEFS
, 0, {CRFD
, RA
, RB
}},
3937 {"efststlt", VX (4, 733), VX_MASK
, PPCEFS
, 0, {CRFD
, RA
, RB
}},
3938 {"efststeq", VX (4, 734), VX_MASK
, PPCEFS
, 0, {CRFD
, RA
, RB
}},
3939 {"efdadd", VX (4, 736), VX_MASK
, PPCEFS
, 0, {RS
, RA
, RB
}},
3940 {"efdsub", VX (4, 737), VX_MASK
, PPCEFS
, 0, {RS
, RA
, RB
}},
3941 {"efdmadd", VX (4, 738), VX_MASK
, PPCEFS2
, E500
|E500MC
, {RD
, RA
, RB
}},
3942 {"efdcfuid", VX (4, 738), VX_MASK
, E500
|E500MC
,0, {RS
, RB
}},
3943 {"efdmsub", VX (4, 739), VX_MASK
, PPCEFS2
, E500
|E500MC
, {RD
, RA
, RB
}},
3944 {"efdcfsid", VX (4, 739), VX_MASK
, E500
|E500MC
,0, {RS
, RB
}},
3945 {"efdabs", VX (4, 740), VX_MASK
, PPCEFS
, 0, {RS
, RA
}},
3946 {"efdnabs", VX (4, 741), VX_MASK
, PPCEFS
, 0, {RS
, RA
}},
3947 {"efdneg", VX (4, 742), VX_MASK
, PPCEFS
, 0, {RS
, RA
}},
3948 {"efdsqrt", VX_RB_CONST(4, 743, 0), VX_RB_CONST_MASK
, PPCEFS2
, 0, {RD
, RA
}},
3949 {"efdmul", VX (4, 744), VX_MASK
, PPCEFS
, 0, {RS
, RA
, RB
}},
3950 {"efddiv", VX (4, 745), VX_MASK
, PPCEFS
, 0, {RS
, RA
, RB
}},
3951 {"efdnmadd", VX (4, 746), VX_MASK
, PPCEFS2
, E500
|E500MC
, {RD
, RA
, RB
}},
3952 {"efdctuidz", VX (4, 746), VX_MASK
, E500
|E500MC
,0, {RS
, RB
}},
3953 {"efdnmsub", VX (4, 747), VX_MASK
, PPCEFS2
, E500
|E500MC
, {RD
, RA
, RB
}},
3954 {"efdctsidz", VX (4, 747), VX_MASK
, E500
|E500MC
,0, {RS
, RB
}},
3955 {"efdcmpgt", VX (4, 748), VX_MASK
, PPCEFS
, 0, {CRFD
, RA
, RB
}},
3956 {"efdcmplt", VX (4, 749), VX_MASK
, PPCEFS
, 0, {CRFD
, RA
, RB
}},
3957 {"efdcmpeq", VX (4, 750), VX_MASK
, PPCEFS
, 0, {CRFD
, RA
, RB
}},
3958 {"efdcfs", VX (4, 751), VX_MASK
, PPCEFS
, 0, {RS
, RB
}},
3959 {"efdcfui", VX_RA_CONST(4, 752, 0), VX_RA_CONST_MASK
, PPCEFS
, 0, {RS
, RB
}},
3960 {"efdcfuid", VX_RA_CONST(4, 752, 1), VX_RA_CONST_MASK
, PPCEFS
, E500
|E500MC
, {RS
, RB
}},
3961 {"efdcfsi", VX_RA_CONST(4, 753, 0), VX_RA_CONST_MASK
, PPCEFS
, 0, {RS
, RB
}},
3962 {"efdcfsid", VX_RA_CONST(4, 753, 1), VX_RA_CONST_MASK
, PPCEFS
, E500
|E500MC
, {RS
, RB
}},
3963 {"efdcfh", VX_RA_CONST(4, 753, 4), VX_RA_CONST_MASK
, PPCEFS2
, 0, {RD
, RB
}},
3964 {"efdcfuf", VX (4, 754), VX_MASK
, PPCEFS
, 0, {RS
, RB
}},
3965 {"efdcfsf", VX (4, 755), VX_MASK
, PPCEFS
, 0, {RS
, RB
}},
3966 {"efdctui", VX (4, 756), VX_MASK
, PPCEFS
, 0, {RS
, RB
}},
3967 {"efdcth", VX_RA_CONST(4, 757, 4), VX_RA_CONST_MASK
, PPCEFS2
, 0, {RD
, RB
}},
3968 {"efdctsi", VX (4, 757), VX_MASK
, PPCEFS
, 0, {RS
, RB
}},
3969 {"efdctuf", VX (4, 758), VX_MASK
, PPCEFS
, 0, {RS
, RB
}},
3970 {"efdctsf", VX (4, 759), VX_MASK
, PPCEFS
, 0, {RS
, RB
}},
3971 {"efdctuiz", VX_RA_CONST(4, 760, 0), VX_RA_CONST_MASK
, PPCEFS
, 0, {RS
, RB
}},
3972 {"efdctuidz", VX_RA_CONST(4, 760, 1), VX_RA_CONST_MASK
, PPCEFS
, E500
|E500MC
, {RS
, RB
}},
3973 {"ncput", APU(4, 380,0), APU_RT_MASK
, PPC405
, 0, {RA
, FSL
}},
3974 {"efdctsiz", VX_RA_CONST(4, 762, 0), VX_RA_CONST_MASK
, PPCEFS
, 0, {RS
, RB
}},
3975 {"efdctsidz", VX_RA_CONST(4, 762, 1), VX_RA_CONST_MASK
, PPCEFS
, E500
|E500MC
, {RS
, RB
}},
3976 {"efdtstgt", VX (4, 764), VX_MASK
, PPCEFS
, 0, {CRFD
, RA
, RB
}},
3977 {"efdtstlt", VX (4, 765), VX_MASK
, PPCEFS
, 0, {CRFD
, RA
, RB
}},
3978 {"efdtsteq", VX (4, 766), VX_MASK
, PPCEFS
, 0, {CRFD
, RA
, RB
}},
3979 {"evlddx", VX (4, 768), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
3980 {"vaddsbs", VX (4, 768), VX_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
3981 {"evldd", VX (4, 769), VX_MASK
, PPCSPE
, 0, {RS
, EVUIMM_8
, RA
}},
3982 {"evldwx", VX (4, 770), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
3983 {"vminsb", VX (4, 770), VX_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
3984 {"evldw", VX (4, 771), VX_MASK
, PPCSPE
, 0, {RS
, EVUIMM_8
, RA
}},
3985 {"evldhx", VX (4, 772), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
3986 {"vsrab", VX (4, 772), VX_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
3987 {"evldh", VX (4, 773), VX_MASK
, PPCSPE
, 0, {RS
, EVUIMM_8
, RA
}},
3988 {"vcmpgtsb", VXR(4, 774,0), VXR_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
3989 {"evlhhesplatx",VX (4, 776), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
3990 {"vmulesb", VX (4, 776), VX_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
3991 {"evlhhesplat", VX (4, 777), VX_MASK
, PPCSPE
, 0, {RS
, EVUIMM_2
, RA
}},
3992 {"vcfux", VX (4, 778), VX_MASK
, PPCVEC
, 0, {VD
, VB
, UIMM
}},
3993 {"vcuxwfp", VX (4, 778), VX_MASK
, PPCVEC
, 0, {VD
, VB
, UIMM
}},
3994 {"evlhhousplatx",VX(4, 780), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
3995 {"vspltisb", VX (4, 780), VXVB_MASK
, PPCVEC
, 0, {VD
, SIMM
}},
3996 {"vinsertb", VX (4, 781), VXUIMM4_MASK
, PPCVEC3
, 0, {VD
, VB
, UIMM4
}},
3997 {"evlhhousplat",VX (4, 781), VX_MASK
, PPCSPE
, 0, {RS
, EVUIMM_2
, RA
}},
3998 {"evlhhossplatx",VX(4, 782), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
3999 {"vpkpx", VX (4, 782), VX_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
4000 {"evlhhossplat",VX (4, 783), VX_MASK
, PPCSPE
, 0, {RS
, EVUIMM_2
, RA
}},
4001 {"mullhwu", XRC(4, 392,0), X_MASK
, MULHW
, 0, {RT
, RA
, RB
}},
4002 {"evlwhex", VX (4, 784), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
4003 {"mullhwu.", XRC(4, 392,1), X_MASK
, MULHW
, 0, {RT
, RA
, RB
}},
4004 {"evlwhe", VX (4, 785), VX_MASK
, PPCSPE
, 0, {RS
, EVUIMM_4
, RA
}},
4005 {"evlwhoux", VX (4, 788), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
4006 {"evlwhou", VX (4, 789), VX_MASK
, PPCSPE
, 0, {RS
, EVUIMM_4
, RA
}},
4007 {"evlwhosx", VX (4, 790), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
4008 {"evlwhos", VX (4, 791), VX_MASK
, PPCSPE
, 0, {RS
, EVUIMM_4
, RA
}},
4009 {"maclhwu", XO (4, 396,0,0),XO_MASK
, MULHW
, 0, {RT
, RA
, RB
}},
4010 {"evlwwsplatx", VX (4, 792), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
4011 {"maclhwu.", XO (4, 396,0,1),XO_MASK
, MULHW
, 0, {RT
, RA
, RB
}},
4012 {"evlwwsplat", VX (4, 793), VX_MASK
, PPCSPE
, 0, {RS
, EVUIMM_4
, RA
}},
4013 {"evlwhsplatx", VX (4, 796), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
4014 {"evlwhsplat", VX (4, 797), VX_MASK
, PPCSPE
, 0, {RS
, EVUIMM_4
, RA
}},
4015 {"evstddx", VX (4, 800), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
4016 {"evstdd", VX (4, 801), VX_MASK
, PPCSPE
, 0, {RS
, EVUIMM_8
, RA
}},
4017 {"evstdwx", VX (4, 802), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
4018 {"evstdw", VX (4, 803), VX_MASK
, PPCSPE
, 0, {RS
, EVUIMM_8
, RA
}},
4019 {"evstdhx", VX (4, 804), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
4020 {"evstdh", VX (4, 805), VX_MASK
, PPCSPE
, 0, {RS
, EVUIMM_8
, RA
}},
4021 {"evstwhex", VX (4, 816), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
4022 {"evstwhe", VX (4, 817), VX_MASK
, PPCSPE
, 0, {RS
, EVUIMM_4
, RA
}},
4023 {"evstwhox", VX (4, 820), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
4024 {"evstwho", VX (4, 821), VX_MASK
, PPCSPE
, 0, {RS
, EVUIMM_4
, RA
}},
4025 {"evstwwex", VX (4, 824), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
4026 {"evstwwe", VX (4, 825), VX_MASK
, PPCSPE
, 0, {RS
, EVUIMM_4
, RA
}},
4027 {"evstwwox", VX (4, 828), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
4028 {"evstwwo", VX (4, 829), VX_MASK
, PPCSPE
, 0, {RS
, EVUIMM_4
, RA
}},
4029 {"vaddshs", VX (4, 832), VX_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
4030 {"bcdcpsgn.", VX (4, 833), VX_MASK
, PPCVEC3
, 0, {VD
, VA
, VB
}},
4031 {"vminsh", VX (4, 834), VX_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
4032 {"vsrah", VX (4, 836), VX_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
4033 {"vcmpgtsh", VXR(4, 838,0), VXR_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
4034 {"vmulesh", VX (4, 840), VX_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
4035 {"vcfsx", VX (4, 842), VX_MASK
, PPCVEC
, 0, {VD
, VB
, UIMM
}},
4036 {"vcsxwfp", VX (4, 842), VX_MASK
, PPCVEC
, 0, {VD
, VB
, UIMM
}},
4037 {"vspltish", VX (4, 844), VXVB_MASK
, PPCVEC
, 0, {VD
, SIMM
}},
4038 {"vinserth", VX (4, 845), VXUIMM4_MASK
, PPCVEC3
, 0, {VD
, VB
, UIMM4
}},
4039 {"vupkhpx", VX (4, 846), VXVA_MASK
, PPCVEC
, 0, {VD
, VB
}},
4040 {"mullhw", XRC(4, 424,0), X_MASK
, MULHW
, 0, {RT
, RA
, RB
}},
4041 {"mullhw.", XRC(4, 424,1), X_MASK
, MULHW
, 0, {RT
, RA
, RB
}},
4042 {"maclhw", XO (4, 428,0,0),XO_MASK
, MULHW
, 0, {RT
, RA
, RB
}},
4043 {"maclhw.", XO (4, 428,0,1),XO_MASK
, MULHW
, 0, {RT
, RA
, RB
}},
4044 {"nmaclhw", XO (4, 430,0,0),XO_MASK
, MULHW
, 0, {RT
, RA
, RB
}},
4045 {"nmaclhw.", XO (4, 430,0,1),XO_MASK
, MULHW
, 0, {RT
, RA
, RB
}},
4046 {"vaddsws", VX (4, 896), VX_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
4047 {"vminsw", VX (4, 898), VX_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
4048 {"vsraw", VX (4, 900), VX_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
4049 {"vcmpgtsw", VXR(4, 902,0), VXR_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
4050 {"vmulesw", VX (4, 904), VX_MASK
, PPCVEC2
, 0, {VD
, VA
, VB
}},
4051 {"vctuxs", VX (4, 906), VX_MASK
, PPCVEC
, 0, {VD
, VB
, UIMM
}},
4052 {"vcfpuxws", VX (4, 906), VX_MASK
, PPCVEC
, 0, {VD
, VB
, UIMM
}},
4053 {"vspltisw", VX (4, 908), VXVB_MASK
, PPCVEC
, 0, {VD
, SIMM
}},
4054 {"vinsertw", VX (4, 909), VXUIMM4_MASK
, PPCVEC3
, 0, {VD
, VB
, UIMM4
}},
4055 {"maclhwsu", XO (4, 460,0,0), XO_MASK
, MULHW
, 0, {RT
, RA
, RB
}},
4056 {"maclhwsu.", XO (4, 460,0,1), XO_MASK
, MULHW
, 0, {RT
, RA
, RB
}},
4057 {"vminsd", VX (4, 962), VX_MASK
, PPCVEC2
, 0, {VD
, VA
, VB
}},
4058 {"vsrad", VX (4, 964), VX_MASK
, PPCVEC2
, 0, {VD
, VA
, VB
}},
4059 {"vcmpbfp", VXR(4, 966,0), VXR_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
4060 {"vcmpgtsd", VXR(4, 967,0), VXR_MASK
, PPCVEC2
, 0, {VD
, VA
, VB
}},
4061 {"vctsxs", VX (4, 970), VX_MASK
, PPCVEC
, 0, {VD
, VB
, UIMM
}},
4062 {"vcfpsxws", VX (4, 970), VX_MASK
, PPCVEC
, 0, {VD
, VB
, UIMM
}},
4063 {"vinsertd", VX (4, 973), VXUIMM4_MASK
, PPCVEC3
, 0, {VD
, VB
, UIMM4
}},
4064 {"vupklpx", VX (4, 974), VXVA_MASK
, PPCVEC
, 0, {VD
, VB
}},
4065 {"maclhws", XO (4, 492,0,0), XO_MASK
, MULHW
, 0, {RT
, RA
, RB
}},
4066 {"maclhws.", XO (4, 492,0,1), XO_MASK
, MULHW
, 0, {RT
, RA
, RB
}},
4067 {"nmaclhws", XO (4, 494,0,0), XO_MASK
, MULHW
, 0, {RT
, RA
, RB
}},
4068 {"nmaclhws.", XO (4, 494,0,1), XO_MASK
, MULHW
, 0, {RT
, RA
, RB
}},
4069 {"vsububm", VX (4,1024), VX_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
4070 {"bcdadd.", VX (4,1025), VXPS_MASK
, PPCVEC2
, 0, {VD
, VA
, VB
, PS
}},
4071 {"vavgub", VX (4,1026), VX_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
4072 {"vabsdub", VX (4,1027), VX_MASK
, PPCVEC2
, 0, {VD
, VA
, VB
}},
4073 {"evmhessf", VX (4,1027), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
4074 {"vand", VX (4,1028), VX_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
4075 {"vcmpequb.", VXR(4, 6,1), VXR_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
4076 {"vcmpneb.", VXR(4, 7,1), VXR_MASK
, PPCVEC3
, 0, {VD
, VA
, VB
}},
4077 {"udi0fcm.", APU(4, 515,0), APU_MASK
, PPC405
|PPC440
, 0, {URT
, URA
, URB
}},
4078 {"udi0fcm", APU(4, 515,1), APU_MASK
, PPC405
|PPC440
, 0, {URT
, URA
, URB
}},
4079 {"evmhossf", VX (4,1031), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
4080 {"vpmsumb", VX (4,1032), VX_MASK
, PPCVEC2
, 0, {VD
, VA
, VB
}},
4081 {"evmheumi", VX (4,1032), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
4082 {"evmhesmi", VX (4,1033), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
4083 {"vmaxfp", VX (4,1034), VX_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
4084 {"evmhesmf", VX (4,1035), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
4085 {"evmhoumi", VX (4,1036), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
4086 {"vslo", VX (4,1036), VX_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
4087 {"evmhosmi", VX (4,1037), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
4088 {"evmhosmf", VX (4,1039), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
4089 {"machhwuo", XO (4, 12,1,0), XO_MASK
, MULHW
, 0, {RT
, RA
, RB
}},
4090 {"machhwuo.", XO (4, 12,1,1), XO_MASK
, MULHW
, 0, {RT
, RA
, RB
}},
4091 {"ps_merge00", XOPS(4,528,0), XOPS_MASK
, PPCPS
, 0, {FRT
, FRA
, FRB
}},
4092 {"ps_merge00.", XOPS(4,528,1), XOPS_MASK
, PPCPS
, 0, {FRT
, FRA
, FRB
}},
4093 {"evmhessfa", VX (4,1059), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
4094 {"evmhossfa", VX (4,1063), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
4095 {"evmheumia", VX (4,1064), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
4096 {"evmhesmia", VX (4,1065), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
4097 {"evmhesmfa", VX (4,1067), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
4098 {"evmhoumia", VX (4,1068), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
4099 {"evmhosmia", VX (4,1069), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
4100 {"evmhosmfa", VX (4,1071), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
4101 {"vsubuhm", VX (4,1088), VX_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
4102 {"bcdsub.", VX (4,1089), VXPS_MASK
, PPCVEC2
, 0, {VD
, VA
, VB
, PS
}},
4103 {"vavguh", VX (4,1090), VX_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
4104 {"evmwlssf", VX (4,1091), VX_MASK
, PPCSPE
, 0, {RD
, RA
, RB
}},
4105 {"vabsduh", VX (4,1091), VX_MASK
, PPCVEC2
, 0, {VD
, VA
, VB
}},
4106 {"vandc", VX (4,1092), VX_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
4107 {"vcmpequh.", VXR(4, 70,1), VXR_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
4108 {"udi1fcm.", APU(4, 547,0), APU_MASK
, PPC405
|PPC440
, 0, {URT
, URA
, URB
}},
4109 {"udi1fcm", APU(4, 547,1), APU_MASK
, PPC405
|PPC440
, 0, {URT
, URA
, URB
}},
4110 {"vcmpneh.", VXR(4, 71,1), VXR_MASK
, PPCVEC3
, 0, {VD
, VA
, VB
}},
4111 {"evmwhssf", VX (4,1095), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
4112 {"vpmsumh", VX (4,1096), VX_MASK
, PPCVEC2
, 0, {VD
, VA
, VB
}},
4113 {"evmwlumi", VX (4,1096), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
4114 {"vminfp", VX (4,1098), VX_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
4115 {"evmwlsmf", VX (4,1099), VX_MASK
, PPCSPE
, 0, {RD
, RA
, RB
}},
4116 {"evmwhumi", VX (4,1100), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
4117 {"vsro", VX (4,1100), VX_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
4118 {"evmwhsmi", VX (4,1101), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
4119 {"vpkudum", VX (4,1102), VX_MASK
, PPCVEC2
, 0, {VD
, VA
, VB
}},
4120 {"evmwhsmf", VX (4,1103), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
4121 {"evmwssf", VX (4,1107), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
4122 {"machhwo", XO (4, 44,1,0), XO_MASK
, MULHW
, 0, {RT
, RA
, RB
}},
4123 {"evmwumi", VX (4,1112), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
4124 {"machhwo.", XO (4, 44,1,1), XO_MASK
, MULHW
, 0, {RT
, RA
, RB
}},
4125 {"evmwsmi", VX (4,1113), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
4126 {"evmwsmf", VX (4,1115), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
4127 {"nmachhwo", XO (4, 46,1,0), XO_MASK
, MULHW
, 0, {RT
, RA
, RB
}},
4128 {"nmachhwo.", XO (4, 46,1,1), XO_MASK
, MULHW
, 0, {RT
, RA
, RB
}},
4129 {"ps_merge01", XOPS(4,560,0), XOPS_MASK
, PPCPS
, 0, {FRT
, FRA
, FRB
}},
4130 {"ps_merge01.", XOPS(4,560,1), XOPS_MASK
, PPCPS
, 0, {FRT
, FRA
, FRB
}},
4131 {"evmwlssfa", VX (4,1123), VX_MASK
, PPCSPE
, 0, {RD
, RA
, RB
}},
4132 {"evmwhssfa", VX (4,1127), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
4133 {"evmwlumia", VX (4,1128), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
4134 {"evmwlsmfa", VX (4,1131), VX_MASK
, PPCSPE
, 0, {RD
, RA
, RB
}},
4135 {"evmwhumia", VX (4,1132), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
4136 {"evmwhsmia", VX (4,1133), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
4137 {"evmwhsmfa", VX (4,1135), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
4138 {"evmwssfa", VX (4,1139), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
4139 {"evmwumia", VX (4,1144), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
4140 {"evmwsmia", VX (4,1145), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
4141 {"evmwsmfa", VX (4,1147), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
4142 {"vsubuwm", VX (4,1152), VX_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
4143 {"bcdus.", VX (4,1153), VX_MASK
, PPCVEC3
, 0, {VD
, VA
, VB
}},
4144 {"vavguw", VX (4,1154), VX_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
4145 {"vabsduw", VX (4,1155), VX_MASK
, PPCVEC2
, 0, {VD
, VA
, VB
}},
4146 {"vmr", VX (4,1156), VX_MASK
, PPCVEC
, 0, {VD
, VA
, VBA
}},
4147 {"vor", VX (4,1156), VX_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
4148 {"vcmpnew.", VXR(4, 135,1), VXR_MASK
, PPCVEC3
, 0, {VD
, VA
, VB
}},
4149 {"vpmsumw", VX (4,1160), VX_MASK
, PPCVEC2
, 0, {VD
, VA
, VB
}},
4150 {"vcmpequw.", VXR(4, 134,1), VXR_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
4151 {"udi2fcm.", APU(4, 579,0), APU_MASK
, PPC405
|PPC440
, 0, {URT
, URA
, URB
}},
4152 {"udi2fcm", APU(4, 579,1), APU_MASK
, PPC405
|PPC440
, 0, {URT
, URA
, URB
}},
4153 {"machhwsuo", XO (4, 76,1,0), XO_MASK
, MULHW
, 0, {RT
, RA
, RB
}},
4154 {"machhwsuo.", XO (4, 76,1,1), XO_MASK
, MULHW
, 0, {RT
, RA
, RB
}},
4155 {"ps_merge10", XOPS(4,592,0), XOPS_MASK
, PPCPS
, 0, {FRT
, FRA
, FRB
}},
4156 {"ps_merge10.", XOPS(4,592,1), XOPS_MASK
, PPCPS
, 0, {FRT
, FRA
, FRB
}},
4157 {"vsubudm", VX (4,1216), VX_MASK
, PPCVEC2
, 0, {VD
, VA
, VB
}},
4158 {"evaddusiaaw", VX (4,1216), VX_MASK
, PPCSPE
, 0, {RS
, RA
}},
4159 {"bcds.", VX (4,1217), VXPS_MASK
, PPCVEC3
, 0, {VD
, VA
, VB
, PS
}},
4160 {"evaddssiaaw", VX (4,1217), VX_MASK
, PPCSPE
, 0, {RS
, RA
}},
4161 {"evsubfusiaaw",VX (4,1218), VX_MASK
, PPCSPE
, 0, {RS
, RA
}},
4162 {"evsubfssiaaw",VX (4,1219), VX_MASK
, PPCSPE
, 0, {RS
, RA
}},
4163 {"evmra", VX (4,1220), VX_MASK
, PPCSPE
, 0, {RS
, RA
}},
4164 {"vxor", VX (4,1220), VX_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
4165 {"evdivws", VX (4,1222), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
4166 {"vcmpeqfp.", VXR(4, 198,1), VXR_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
4167 {"udi3fcm.", APU(4, 611,0), APU_MASK
, PPC405
|PPC440
, 0, {URT
, URA
, URB
}},
4168 {"vcmpequd.", VXR(4, 199,1), VXR_MASK
, PPCVEC2
, 0, {VD
, VA
, VB
}},
4169 {"udi3fcm", APU(4, 611,1), APU_MASK
, PPC405
|PPC440
, 0, {URT
, URA
, URB
}},
4170 {"evdivwu", VX (4,1223), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
4171 {"vpmsumd", VX (4,1224), VX_MASK
, PPCVEC2
, 0, {VD
, VA
, VB
}},
4172 {"evaddumiaaw", VX (4,1224), VX_MASK
, PPCSPE
, 0, {RS
, RA
}},
4173 {"evaddsmiaaw", VX (4,1225), VX_MASK
, PPCSPE
, 0, {RS
, RA
}},
4174 {"evsubfumiaaw",VX (4,1226), VX_MASK
, PPCSPE
, 0, {RS
, RA
}},
4175 {"evsubfsmiaaw",VX (4,1227), VX_MASK
, PPCSPE
, 0, {RS
, RA
}},
4176 {"vpkudus", VX (4,1230), VX_MASK
, PPCVEC2
, 0, {VD
, VA
, VB
}},
4177 {"machhwso", XO (4, 108,1,0), XO_MASK
, MULHW
, 0, {RT
, RA
, RB
}},
4178 {"machhwso.", XO (4, 108,1,1), XO_MASK
, MULHW
, 0, {RT
, RA
, RB
}},
4179 {"nmachhwso", XO (4, 110,1,0), XO_MASK
, MULHW
, 0, {RT
, RA
, RB
}},
4180 {"nmachhwso.", XO (4, 110,1,1), XO_MASK
, MULHW
, 0, {RT
, RA
, RB
}},
4181 {"ps_merge11", XOPS(4,624,0), XOPS_MASK
, PPCPS
, 0, {FRT
, FRA
, FRB
}},
4182 {"ps_merge11.", XOPS(4,624,1), XOPS_MASK
, PPCPS
, 0, {FRT
, FRA
, FRB
}},
4183 {"vsubuqm", VX (4,1280), VX_MASK
, PPCVEC2
, 0, {VD
, VA
, VB
}},
4184 {"evmheusiaaw", VX (4,1280), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
4185 {"bcdtrunc.", VX (4,1281), VXPS_MASK
, PPCVEC3
, 0, {VD
, VA
, VB
, PS
}},
4186 {"evmhessiaaw", VX (4,1281), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
4187 {"vavgsb", VX (4,1282), VX_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
4188 {"evmhessfaaw", VX (4,1283), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
4189 {"evmhousiaaw", VX (4,1284), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
4190 {"vnot", VX (4,1284), VX_MASK
, PPCVEC
, 0, {VD
, VA
, VBA
}},
4191 {"vnor", VX (4,1284), VX_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
4192 {"evmhossiaaw", VX (4,1285), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
4193 {"udi4fcm.", APU(4, 643,0), APU_MASK
, PPC405
|PPC440
, 0, {URT
, URA
, URB
}},
4194 {"udi4fcm", APU(4, 643,1), APU_MASK
, PPC405
|PPC440
, 0, {URT
, URA
, URB
}},
4195 {"vcmpnezb.", VXR(4, 263,1), VXR_MASK
, PPCVEC3
, 0, {VD
, VA
, VB
}},
4196 {"evmhossfaaw", VX (4,1287), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
4197 {"evmheumiaaw", VX (4,1288), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
4198 {"vcipher", VX (4,1288), VX_MASK
, PPCVEC2
, 0, {VD
, VA
, VB
}},
4199 {"vcipherlast", VX (4,1289), VX_MASK
, PPCVEC2
, 0, {VD
, VA
, VB
}},
4200 {"evmhesmiaaw", VX (4,1289), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
4201 {"evmhesmfaaw", VX (4,1291), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
4202 {"vgbbd", VX (4,1292), VXVA_MASK
, PPCVEC2
, 0, {VD
, VB
}},
4203 {"evmhoumiaaw", VX (4,1292), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
4204 {"evmhosmiaaw", VX (4,1293), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
4205 {"evmhosmfaaw", VX (4,1295), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
4206 {"macchwuo", XO (4, 140,1,0), XO_MASK
, MULHW
, 0, {RT
, RA
, RB
}},
4207 {"macchwuo.", XO (4, 140,1,1), XO_MASK
, MULHW
, 0, {RT
, RA
, RB
}},
4208 {"evmhegumiaa", VX (4,1320), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
4209 {"evmhegsmiaa", VX (4,1321), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
4210 {"evmhegsmfaa", VX (4,1323), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
4211 {"evmhogumiaa", VX (4,1324), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
4212 {"evmhogsmiaa", VX (4,1325), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
4213 {"evmhogsmfaa", VX (4,1327), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
4214 {"vsubcuq", VX (4,1344), VX_MASK
, PPCVEC2
, 0, {VD
, VA
, VB
}},
4215 {"evmwlusiaaw", VX (4,1344), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
4216 {"bcdutrunc.", VX (4,1345), VX_MASK
, PPCVEC3
, 0, {VD
, VA
, VB
}},
4217 {"evmwlssiaaw", VX (4,1345), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
4218 {"vavgsh", VX (4,1346), VX_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
4219 {"evmwlssfaaw", VX (4,1347), VX_MASK
, PPCSPE
, 0, {RD
, RA
, RB
}},
4220 {"evmwhusiaa", VX (4,1348), VX_MASK
, PPCSPE
, 0, {RD
, RA
, RB
}},
4221 {"vorc", VX (4,1348), VX_MASK
, PPCVEC2
, 0, {VD
, VA
, VB
}},
4222 {"evmwhssmaa", VX (4,1349), VX_MASK
, PPCSPE
, 0, {RD
, RA
, RB
}},
4223 {"udi5fcm.", APU(4, 675,0), APU_MASK
, PPC405
|PPC440
, 0, {URT
, URA
, URB
}},
4224 {"udi5fcm", APU(4, 675,1), APU_MASK
, PPC405
|PPC440
, 0, {URT
, URA
, URB
}},
4225 {"vcmpnezh.", VXR(4, 327,1), VXR_MASK
, PPCVEC3
, 0, {VD
, VA
, VB
}},
4226 {"evmwhssfaa", VX (4,1351), VX_MASK
, PPCSPE
, 0, {RD
, RA
, RB
}},
4227 {"vncipher", VX (4,1352), VX_MASK
, PPCVEC2
, 0, {VD
, VA
, VB
}},
4228 {"evmwlumiaaw", VX (4,1352), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
4229 {"vncipherlast",VX (4,1353), VX_MASK
, PPCVEC2
, 0, {VD
, VA
, VB
}},
4230 {"evmwlsmiaaw", VX (4,1353), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
4231 {"evmwlsmfaaw", VX (4,1355), VX_MASK
, PPCSPE
, 0, {RD
, RA
, RB
}},
4232 {"evmwhumiaa", VX (4,1356), VX_MASK
, PPCSPE
, 0, {RD
, RA
, RB
}},
4233 {"vbpermq", VX (4,1356), VX_MASK
, PPCVEC2
, 0, {VD
, VA
, VB
}},
4234 {"evmwhsmiaa", VX (4,1357), VX_MASK
, PPCSPE
, 0, {RD
, RA
, RB
}},
4235 {"vpksdus", VX (4,1358), VX_MASK
, PPCVEC2
, 0, {VD
, VA
, VB
}},
4236 {"evmwhsmfaa", VX (4,1359), VX_MASK
, PPCSPE
, 0, {RD
, RA
, RB
}},
4237 {"evmwssfaa", VX (4,1363), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
4238 {"macchwo", XO (4, 172,1,0), XO_MASK
, MULHW
, 0, {RT
, RA
, RB
}},
4239 {"evmwumiaa", VX (4,1368), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
4240 {"macchwo.", XO (4, 172,1,1), XO_MASK
, MULHW
, 0, {RT
, RA
, RB
}},
4241 {"evmwsmiaa", VX (4,1369), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
4242 {"evmwsmfaa", VX (4,1371), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
4243 {"nmacchwo", XO (4, 174,1,0), XO_MASK
, MULHW
, 0, {RT
, RA
, RB
}},
4244 {"nmacchwo.", XO (4, 174,1,1), XO_MASK
, MULHW
, 0, {RT
, RA
, RB
}},
4245 {"evmwhgumiaa", VX (4,1380), VX_MASK
, PPCSPE
, 0, {RD
, RA
, RB
}},
4246 {"evmwhgsmiaa", VX (4,1381), VX_MASK
, PPCSPE
, 0, {RD
, RA
, RB
}},
4247 {"evmwhgssfaa", VX (4,1383), VX_MASK
, PPCSPE
, 0, {RD
, RA
, RB
}},
4248 {"evmwhgsmfaa", VX (4,1391), VX_MASK
, PPCSPE
, 0, {RD
, RA
, RB
}},
4249 {"evmheusianw", VX (4,1408), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
4250 {"vsubcuw", VX (4,1408), VX_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
4251 {"evmhessianw", VX (4,1409), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
4252 {"bcdctsq.", VXVA(4,1409,0), VXVA_MASK
, PPCVEC3
, 0, {VD
, VB
}},
4253 {"bcdcfsq.", VXVA(4,1409,2), VXVAPS_MASK
, PPCVEC3
, 0, {VD
, VB
, PS
}},
4254 {"bcdctz.", VXVA(4,1409,4), VXVAPS_MASK
, PPCVEC3
, 0, {VD
, VB
, PS
}},
4255 {"bcdctn.", VXVA(4,1409,5), VXVA_MASK
, PPCVEC3
, 0, {VD
, VB
}},
4256 {"bcdcfz.", VXVA(4,1409,6), VXVAPS_MASK
, PPCVEC3
, 0, {VD
, VB
, PS
}},
4257 {"bcdcfn.", VXVA(4,1409,7), VXVAPS_MASK
, PPCVEC3
, 0, {VD
, VB
, PS
}},
4258 {"bcdsetsgn.", VXVA(4,1409,31), VXVAPS_MASK
, PPCVEC3
, 0, {VD
, VB
, PS
}},
4259 {"vavgsw", VX (4,1410), VX_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
4260 {"evmhessfanw", VX (4,1411), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
4261 {"vnand", VX (4,1412), VX_MASK
, PPCVEC2
, 0, {VD
, VA
, VB
}},
4262 {"evmhousianw", VX (4,1412), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
4263 {"evmhossianw", VX (4,1413), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
4264 {"udi6fcm.", APU(4, 707,0), APU_MASK
, PPC405
|PPC440
, 0, {URT
, URA
, URB
}},
4265 {"udi6fcm", APU(4, 707,1), APU_MASK
, PPC405
|PPC440
, 0, {URT
, URA
, URB
}},
4266 {"vcmpnezw.", VXR(4, 391,1), VXR_MASK
, PPCVEC3
, 0, {VD
, VA
, VB
}},
4267 {"evmhossfanw", VX (4,1415), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
4268 {"evmheumianw", VX (4,1416), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
4269 {"evmhesmianw", VX (4,1417), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
4270 {"evmhesmfanw", VX (4,1419), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
4271 {"evmhoumianw", VX (4,1420), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
4272 {"evmhosmianw", VX (4,1421), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
4273 {"evmhosmfanw", VX (4,1423), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
4274 {"macchwsuo", XO (4, 204,1,0), XO_MASK
, MULHW
, 0, {RT
, RA
, RB
}},
4275 {"macchwsuo.", XO (4, 204,1,1), XO_MASK
, MULHW
, 0, {RT
, RA
, RB
}},
4276 {"evmhegumian", VX (4,1448), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
4277 {"evmhegsmian", VX (4,1449), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
4278 {"evmhegsmfan", VX (4,1451), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
4279 {"evmhogumian", VX (4,1452), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
4280 {"evmhogsmian", VX (4,1453), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
4281 {"evmhogsmfan", VX (4,1455), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
4282 {"evmwlusianw", VX (4,1472), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
4283 {"bcdsr.", VX (4,1473), VXPS_MASK
, PPCVEC3
, 0, {VD
, VA
, VB
, PS
}},
4284 {"evmwlssianw", VX (4,1473), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
4285 {"evmwlssfanw", VX (4,1475), VX_MASK
, PPCSPE
, 0, {RD
, RA
, RB
}},
4286 {"evmwhusian", VX (4,1476), VX_MASK
, PPCSPE
, 0, {RD
, RA
, RB
}},
4287 {"vsld", VX (4,1476), VX_MASK
, PPCVEC2
, 0, {VD
, VA
, VB
}},
4288 {"evmwhssian", VX (4,1477), VX_MASK
, PPCSPE
, 0, {RD
, RA
, RB
}},
4289 {"vcmpgefp.", VXR(4, 454,1), VXR_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
4290 {"udi7fcm.", APU(4, 739,0), APU_MASK
, PPC405
|PPC440
, 0, {URT
, URA
, URB
}},
4291 {"udi7fcm", APU(4, 739,1), APU_MASK
, PPC405
|PPC440
, 0, {URT
, URA
, URB
}},
4292 {"evmwhssfan", VX (4,1479), VX_MASK
, PPCSPE
, 0, {RD
, RA
, RB
}},
4293 {"vsbox", VX (4,1480), VXVB_MASK
, PPCVEC2
, 0, {VD
, VA
}},
4294 {"evmwlumianw", VX (4,1480), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
4295 {"evmwlsmianw", VX (4,1481), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
4296 {"evmwlsmfanw", VX (4,1483), VX_MASK
, PPCSPE
, 0, {RD
, RA
, RB
}},
4297 {"evmwhumian", VX (4,1484), VX_MASK
, PPCSPE
, 0, {RD
, RA
, RB
}},
4298 {"vbpermd", VX (4,1484), VX_MASK
, PPCVEC3
, 0, {VD
, VA
, VB
}},
4299 {"evmwhsmian", VX (4,1485), VX_MASK
, PPCSPE
, 0, {RD
, RA
, RB
}},
4300 {"vpksdss", VX (4,1486), VX_MASK
, PPCVEC2
, 0, {VD
, VA
, VB
}},
4301 {"evmwhsmfan", VX (4,1487), VX_MASK
, PPCSPE
, 0, {RD
, RA
, RB
}},
4302 {"evmwssfan", VX (4,1491), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
4303 {"macchwso", XO (4, 236,1,0), XO_MASK
, MULHW
, 0, {RT
, RA
, RB
}},
4304 {"evmwumian", VX (4,1496), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
4305 {"macchwso.", XO (4, 236,1,1), XO_MASK
, MULHW
, 0, {RT
, RA
, RB
}},
4306 {"evmwsmian", VX (4,1497), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
4307 {"evmwsmfan", VX (4,1499), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
4308 {"evmwhgumian", VX (4,1508), VX_MASK
, PPCSPE
, 0, {RD
, RA
, RB
}},
4309 {"evmwhgsmian", VX (4,1509), VX_MASK
, PPCSPE
, 0, {RD
, RA
, RB
}},
4310 {"evmwhgssfan", VX (4,1511), VX_MASK
, PPCSPE
, 0, {RD
, RA
, RB
}},
4311 {"evmwhgsmfan", VX (4,1519), VX_MASK
, PPCSPE
, 0, {RD
, RA
, RB
}},
4312 {"nmacchwso", XO (4, 238,1,0), XO_MASK
, MULHW
, 0, {RT
, RA
, RB
}},
4313 {"nmacchwso.", XO (4, 238,1,1), XO_MASK
, MULHW
, 0, {RT
, RA
, RB
}},
4314 {"vsububs", VX (4,1536), VX_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
4315 {"vclzlsbb", VXVA(4,1538,0), VXVA_MASK
, PPCVEC3
, 0, {RT
, VB
}},
4316 {"vctzlsbb", VXVA(4,1538,1), VXVA_MASK
, PPCVEC3
, 0, {RT
, VB
}},
4317 {"vnegw", VXVA(4,1538,6), VXVA_MASK
, PPCVEC3
, 0, {VD
, VB
}},
4318 {"vnegd", VXVA(4,1538,7), VXVA_MASK
, PPCVEC3
, 0, {VD
, VB
}},
4319 {"vprtybw", VXVA(4,1538,8), VXVA_MASK
, PPCVEC3
, 0, {VD
, VB
}},
4320 {"vprtybd", VXVA(4,1538,9), VXVA_MASK
, PPCVEC3
, 0, {VD
, VB
}},
4321 {"vprtybq", VXVA(4,1538,10), VXVA_MASK
, PPCVEC3
, 0, {VD
, VB
}},
4322 {"vextsb2w", VXVA(4,1538,16), VXVA_MASK
, PPCVEC3
, 0, {VD
, VB
}},
4323 {"vextsh2w", VXVA(4,1538,17), VXVA_MASK
, PPCVEC3
, 0, {VD
, VB
}},
4324 {"vextsb2d", VXVA(4,1538,24), VXVA_MASK
, PPCVEC3
, 0, {VD
, VB
}},
4325 {"vextsh2d", VXVA(4,1538,25), VXVA_MASK
, PPCVEC3
, 0, {VD
, VB
}},
4326 {"vextsw2d", VXVA(4,1538,26), VXVA_MASK
, PPCVEC3
, 0, {VD
, VB
}},
4327 {"vctzb", VXVA(4,1538,28), VXVA_MASK
, PPCVEC3
, 0, {VD
, VB
}},
4328 {"vctzh", VXVA(4,1538,29), VXVA_MASK
, PPCVEC3
, 0, {VD
, VB
}},
4329 {"vctzw", VXVA(4,1538,30), VXVA_MASK
, PPCVEC3
, 0, {VD
, VB
}},
4330 {"vctzd", VXVA(4,1538,31), VXVA_MASK
, PPCVEC3
, 0, {VD
, VB
}},
4331 {"mfvscr", VX (4,1540), VXVAVB_MASK
, PPCVEC
, 0, {VD
}},
4332 {"vcmpgtub.", VXR(4, 518,1), VXR_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
4333 {"udi8fcm.", APU(4, 771,0), APU_MASK
, PPC440
, 0, {URT
, URA
, URB
}},
4334 {"udi8fcm", APU(4, 771,1), APU_MASK
, PPC440
, 0, {URT
, URA
, URB
}},
4335 {"vsum4ubs", VX (4,1544), VX_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
4336 {"vextublx", VX (4,1549), VX_MASK
, PPCVEC3
, 0, {RT
, RA
, VB
}},
4337 {"vsubuhs", VX (4,1600), VX_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
4338 {"mtvscr", VX (4,1604), VXVDVA_MASK
, PPCVEC
, 0, {VB
}},
4339 {"vcmpgtuh.", VXR(4, 582,1), VXR_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
4340 {"vsum4shs", VX (4,1608), VX_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
4341 {"udi9fcm.", APU(4, 804,0), APU_MASK
, PPC440
, 0, {URT
, URA
, URB
}},
4342 {"udi9fcm", APU(4, 804,1), APU_MASK
, PPC440
, 0, {URT
, URA
, URB
}},
4343 {"vextuhlx", VX (4,1613), VX_MASK
, PPCVEC3
, 0, {RT
, RA
, VB
}},
4344 {"vupkhsw", VX (4,1614), VXVA_MASK
, PPCVEC2
, 0, {VD
, VB
}},
4345 {"vsubuws", VX (4,1664), VX_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
4346 {"vshasigmaw", VX (4,1666), VX_MASK
, PPCVEC2
, 0, {VD
, VA
, ST
, SIX
}},
4347 {"veqv", VX (4,1668), VX_MASK
, PPCVEC2
, 0, {VD
, VA
, VB
}},
4348 {"vcmpgtuw.", VXR(4, 646,1), VXR_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
4349 {"udi10fcm.", APU(4, 835,0), APU_MASK
, PPC440
, 0, {URT
, URA
, URB
}},
4350 {"udi10fcm", APU(4, 835,1), APU_MASK
, PPC440
, 0, {URT
, URA
, URB
}},
4351 {"vsum2sws", VX (4,1672), VX_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
4352 {"vmrgow", VX (4,1676), VX_MASK
, PPCVEC2
, 0, {VD
, VA
, VB
}},
4353 {"vextuwlx", VX (4,1677), VX_MASK
, PPCVEC3
, 0, {RT
, RA
, VB
}},
4354 {"vshasigmad", VX (4,1730), VX_MASK
, PPCVEC2
, 0, {VD
, VA
, ST
, SIX
}},
4355 {"vsrd", VX (4,1732), VX_MASK
, PPCVEC2
, 0, {VD
, VA
, VB
}},
4356 {"vcmpgtfp.", VXR(4, 710,1), VXR_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
4357 {"udi11fcm.", APU(4, 867,0), APU_MASK
, PPC440
, 0, {URT
, URA
, URB
}},
4358 {"vcmpgtud.", VXR(4, 711,1), VXR_MASK
, PPCVEC2
, 0, {VD
, VA
, VB
}},
4359 {"udi11fcm", APU(4, 867,1), APU_MASK
, PPC440
, 0, {URT
, URA
, URB
}},
4360 {"vupklsw", VX (4,1742), VXVA_MASK
, PPCVEC2
, 0, {VD
, VB
}},
4361 {"vsubsbs", VX (4,1792), VX_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
4362 {"vclzb", VX (4,1794), VXVA_MASK
, PPCVEC2
, 0, {VD
, VB
}},
4363 {"vpopcntb", VX (4,1795), VXVA_MASK
, PPCVEC2
, 0, {VD
, VB
}},
4364 {"vsrv", VX (4,1796), VX_MASK
, PPCVEC3
, 0, {VD
, VA
, VB
}},
4365 {"vcmpgtsb.", VXR(4, 774,1), VXR_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
4366 {"udi12fcm.", APU(4, 899,0), APU_MASK
, PPC440
, 0, {URT
, URA
, URB
}},
4367 {"udi12fcm", APU(4, 899,1), APU_MASK
, PPC440
, 0, {URT
, URA
, URB
}},
4368 {"vsum4sbs", VX (4,1800), VX_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
4369 {"vextubrx", VX (4,1805), VX_MASK
, PPCVEC3
, 0, {RT
, RA
, VB
}},
4370 {"maclhwuo", XO (4, 396,1,0), XO_MASK
, MULHW
, 0, {RT
, RA
, RB
}},
4371 {"maclhwuo.", XO (4, 396,1,1), XO_MASK
, MULHW
, 0, {RT
, RA
, RB
}},
4372 {"vsubshs", VX (4,1856), VX_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
4373 {"vclzh", VX (4,1858), VXVA_MASK
, PPCVEC2
, 0, {VD
, VB
}},
4374 {"vpopcnth", VX (4,1859), VXVA_MASK
, PPCVEC2
, 0, {VD
, VB
}},
4375 {"vslv", VX (4,1860), VX_MASK
, PPCVEC3
, 0, {VD
, VA
, VB
}},
4376 {"vcmpgtsh.", VXR(4, 838,1), VXR_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
4377 {"vextuhrx", VX (4,1869), VX_MASK
, PPCVEC3
, 0, {RT
, RA
, VB
}},
4378 {"udi13fcm.", APU(4, 931,0), APU_MASK
, PPC440
, 0, {URT
, URA
, URB
}},
4379 {"udi13fcm", APU(4, 931,1), APU_MASK
, PPC440
, 0, {URT
, URA
, URB
}},
4380 {"maclhwo", XO (4, 428,1,0), XO_MASK
, MULHW
, 0, {RT
, RA
, RB
}},
4381 {"maclhwo.", XO (4, 428,1,1), XO_MASK
, MULHW
, 0, {RT
, RA
, RB
}},
4382 {"nmaclhwo", XO (4, 430,1,0), XO_MASK
, MULHW
, 0, {RT
, RA
, RB
}},
4383 {"nmaclhwo.", XO (4, 430,1,1), XO_MASK
, MULHW
, 0, {RT
, RA
, RB
}},
4384 {"vsubsws", VX (4,1920), VX_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
4385 {"vclzw", VX (4,1922), VXVA_MASK
, PPCVEC2
, 0, {VD
, VB
}},
4386 {"vpopcntw", VX (4,1923), VXVA_MASK
, PPCVEC2
, 0, {VD
, VB
}},
4387 {"vcmpgtsw.", VXR(4, 902,1), VXR_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
4388 {"udi14fcm.", APU(4, 963,0), APU_MASK
, PPC440
, 0, {URT
, URA
, URB
}},
4389 {"udi14fcm", APU(4, 963,1), APU_MASK
, PPC440
, 0, {URT
, URA
, URB
}},
4390 {"vsumsws", VX (4,1928), VX_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
4391 {"vmrgew", VX (4,1932), VX_MASK
, PPCVEC2
, 0, {VD
, VA
, VB
}},
4392 {"vextuwrx", VX (4,1933), VX_MASK
, PPCVEC3
, 0, {RT
, RA
, VB
}},
4393 {"maclhwsuo", XO (4, 460,1,0), XO_MASK
, MULHW
, 0, {RT
, RA
, RB
}},
4394 {"maclhwsuo.", XO (4, 460,1,1), XO_MASK
, MULHW
, 0, {RT
, RA
, RB
}},
4395 {"vclzd", VX (4,1986), VXVA_MASK
, PPCVEC2
, 0, {VD
, VB
}},
4396 {"vpopcntd", VX (4,1987), VXVA_MASK
, PPCVEC2
, 0, {VD
, VB
}},
4397 {"vcmpbfp.", VXR(4, 966,1), VXR_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
4398 {"udi15fcm.", APU(4, 995,0), APU_MASK
, PPC440
, 0, {URT
, URA
, URB
}},
4399 {"vcmpgtsd.", VXR(4, 967,1), VXR_MASK
, PPCVEC2
, 0, {VD
, VA
, VB
}},
4400 {"udi15fcm", APU(4, 995,1), APU_MASK
, PPC440
, 0, {URT
, URA
, URB
}},
4401 {"maclhwso", XO (4, 492,1,0), XO_MASK
, MULHW
, 0, {RT
, RA
, RB
}},
4402 {"maclhwso.", XO (4, 492,1,1), XO_MASK
, MULHW
, 0, {RT
, RA
, RB
}},
4403 {"nmaclhwso", XO (4, 494,1,0), XO_MASK
, MULHW
, 0, {RT
, RA
, RB
}},
4404 {"nmaclhwso.", XO (4, 494,1,1), XO_MASK
, MULHW
, 0, {RT
, RA
, RB
}},
4405 {"dcbz_l", X (4,1014), XRT_MASK
, PPCPS
, 0, {RA
, RB
}},
4407 {"mulli", OP(7), OP_MASK
, PPCCOM
, PPCVLE
, {RT
, RA
, SI
}},
4408 {"muli", OP(7), OP_MASK
, PWRCOM
, PPCVLE
, {RT
, RA
, SI
}},
4410 {"subfic", OP(8), OP_MASK
, PPCCOM
, PPCVLE
, {RT
, RA
, SI
}},
4411 {"sfi", OP(8), OP_MASK
, PWRCOM
, PPCVLE
, {RT
, RA
, SI
}},
4413 {"dozi", OP(9), OP_MASK
, M601
, PPCVLE
, {RT
, RA
, SI
}},
4415 {"cmplwi", OPL(10,0), OPL_MASK
, PPCCOM
, PPCVLE
, {OBF
, RA
, UISIGNOPT
}},
4416 {"cmpldi", OPL(10,1), OPL_MASK
, PPC64
, PPCVLE
, {OBF
, RA
, UISIGNOPT
}},
4417 {"cmpli", OP(10), OP_MASK
, PPC
, PPCVLE
, {BF
, L32OPT
, RA
, UISIGNOPT
}},
4418 {"cmpli", OP(10), OP_MASK
, PWRCOM
, PPC
|PPCVLE
, {BF
, RA
, UISIGNOPT
}},
4420 {"cmpwi", OPL(11,0), OPL_MASK
, PPCCOM
, PPCVLE
, {OBF
, RA
, SI
}},
4421 {"cmpdi", OPL(11,1), OPL_MASK
, PPC64
, PPCVLE
, {OBF
, RA
, SI
}},
4422 {"cmpi", OP(11), OP_MASK
, PPC
, PPCVLE
, {BF
, L32OPT
, RA
, SI
}},
4423 {"cmpi", OP(11), OP_MASK
, PWRCOM
, PPC
|PPCVLE
, {BF
, RA
, SI
}},
4425 {"addic", OP(12), OP_MASK
, PPCCOM
, PPCVLE
, {RT
, RA
, SI
}},
4426 {"ai", OP(12), OP_MASK
, PWRCOM
, PPCVLE
, {RT
, RA
, SI
}},
4427 {"subic", OP(12), OP_MASK
, PPCCOM
, PPCVLE
, {RT
, RA
, NSI
}},
4429 {"addic.", OP(13), OP_MASK
, PPCCOM
, PPCVLE
, {RT
, RA
, SI
}},
4430 {"ai.", OP(13), OP_MASK
, PWRCOM
, PPCVLE
, {RT
, RA
, SI
}},
4431 {"subic.", OP(13), OP_MASK
, PPCCOM
, PPCVLE
, {RT
, RA
, NSI
}},
4433 {"li", OP(14), DRA_MASK
, PPCCOM
, PPCVLE
, {RT
, SI
}},
4434 {"lil", OP(14), DRA_MASK
, PWRCOM
, PPCVLE
, {RT
, SI
}},
4435 {"addi", OP(14), OP_MASK
, PPCCOM
, PPCVLE
, {RT
, RA0
, SI
}},
4436 {"cal", OP(14), OP_MASK
, PWRCOM
, PPCVLE
, {RT
, D
, RA0
}},
4437 {"subi", OP(14), OP_MASK
, PPCCOM
, PPCVLE
, {RT
, RA0
, NSI
}},
4438 {"la", OP(14), OP_MASK
, PPCCOM
, PPCVLE
, {RT
, D
, RA0
}},
4440 {"lis", OP(15), DRA_MASK
, PPCCOM
, PPCVLE
, {RT
, SISIGNOPT
}},
4441 {"liu", OP(15), DRA_MASK
, PWRCOM
, PPCVLE
, {RT
, SISIGNOPT
}},
4442 {"addis", OP(15), OP_MASK
, PPCCOM
, PPCVLE
, {RT
, RA0
, SISIGNOPT
}},
4443 {"cau", OP(15), OP_MASK
, PWRCOM
, PPCVLE
, {RT
, RA0
, SISIGNOPT
}},
4444 {"subis", OP(15), OP_MASK
, PPCCOM
, PPCVLE
, {RT
, RA0
, NSISIGNOPT
}},
4446 {"bdnz-", BBO(16,BODNZ
,0,0), BBOATBI_MASK
, PPCCOM
, PPCVLE
, {BDM
}},
4447 {"bdnz+", BBO(16,BODNZ
,0,0), BBOATBI_MASK
, PPCCOM
, PPCVLE
, {BDP
}},
4448 {"bdnz", BBO(16,BODNZ
,0,0), BBOATBI_MASK
, PPCCOM
, PPCVLE
, {BD
}},
4449 {"bdn", BBO(16,BODNZ
,0,0), BBOATBI_MASK
, PWRCOM
, PPCVLE
, {BD
}},
4450 {"bdnzl-", BBO(16,BODNZ
,0,1), BBOATBI_MASK
, PPCCOM
, PPCVLE
, {BDM
}},
4451 {"bdnzl+", BBO(16,BODNZ
,0,1), BBOATBI_MASK
, PPCCOM
, PPCVLE
, {BDP
}},
4452 {"bdnzl", BBO(16,BODNZ
,0,1), BBOATBI_MASK
, PPCCOM
, PPCVLE
, {BD
}},
4453 {"bdnl", BBO(16,BODNZ
,0,1), BBOATBI_MASK
, PWRCOM
, PPCVLE
, {BD
}},
4454 {"bdnza-", BBO(16,BODNZ
,1,0), BBOATBI_MASK
, PPCCOM
, PPCVLE
, {BDMA
}},
4455 {"bdnza+", BBO(16,BODNZ
,1,0), BBOATBI_MASK
, PPCCOM
, PPCVLE
, {BDPA
}},
4456 {"bdnza", BBO(16,BODNZ
,1,0), BBOATBI_MASK
, PPCCOM
, PPCVLE
, {BDA
}},
4457 {"bdna", BBO(16,BODNZ
,1,0), BBOATBI_MASK
, PWRCOM
, PPCVLE
, {BDA
}},
4458 {"bdnzla-", BBO(16,BODNZ
,1,1), BBOATBI_MASK
, PPCCOM
, PPCVLE
, {BDMA
}},
4459 {"bdnzla+", BBO(16,BODNZ
,1,1), BBOATBI_MASK
, PPCCOM
, PPCVLE
, {BDPA
}},
4460 {"bdnzla", BBO(16,BODNZ
,1,1), BBOATBI_MASK
, PPCCOM
, PPCVLE
, {BDA
}},
4461 {"bdnla", BBO(16,BODNZ
,1,1), BBOATBI_MASK
, PWRCOM
, PPCVLE
, {BDA
}},
4462 {"bdz-", BBO(16,BODZ
,0,0), BBOATBI_MASK
, PPCCOM
, PPCVLE
, {BDM
}},
4463 {"bdz+", BBO(16,BODZ
,0,0), BBOATBI_MASK
, PPCCOM
, PPCVLE
, {BDP
}},
4464 {"bdz", BBO(16,BODZ
,0,0), BBOATBI_MASK
, COM
, PPCVLE
, {BD
}},
4465 {"bdzl-", BBO(16,BODZ
,0,1), BBOATBI_MASK
, PPCCOM
, PPCVLE
, {BDM
}},
4466 {"bdzl+", BBO(16,BODZ
,0,1), BBOATBI_MASK
, PPCCOM
, PPCVLE
, {BDP
}},
4467 {"bdzl", BBO(16,BODZ
,0,1), BBOATBI_MASK
, COM
, PPCVLE
, {BD
}},
4468 {"bdza-", BBO(16,BODZ
,1,0), BBOATBI_MASK
, PPCCOM
, PPCVLE
, {BDMA
}},
4469 {"bdza+", BBO(16,BODZ
,1,0), BBOATBI_MASK
, PPCCOM
, PPCVLE
, {BDPA
}},
4470 {"bdza", BBO(16,BODZ
,1,0), BBOATBI_MASK
, COM
, PPCVLE
, {BDA
}},
4471 {"bdzla-", BBO(16,BODZ
,1,1), BBOATBI_MASK
, PPCCOM
, PPCVLE
, {BDMA
}},
4472 {"bdzla+", BBO(16,BODZ
,1,1), BBOATBI_MASK
, PPCCOM
, PPCVLE
, {BDPA
}},
4473 {"bdzla", BBO(16,BODZ
,1,1), BBOATBI_MASK
, COM
, PPCVLE
, {BDA
}},
4475 {"bge-", BBOCB(16,BOF
,CBLT
,0,0), BBOATCB_MASK
, PPCCOM
, PPCVLE
, {CR
, BDM
}},
4476 {"bge+", BBOCB(16,BOF
,CBLT
,0,0), BBOATCB_MASK
, PPCCOM
, PPCVLE
, {CR
, BDP
}},
4477 {"bge", BBOCB(16,BOF
,CBLT
,0,0), BBOATCB_MASK
, COM
, PPCVLE
, {CR
, BD
}},
4478 {"bnl-", BBOCB(16,BOF
,CBLT
,0,0), BBOATCB_MASK
, PPCCOM
, PPCVLE
, {CR
, BDM
}},
4479 {"bnl+", BBOCB(16,BOF
,CBLT
,0,0), BBOATCB_MASK
, PPCCOM
, PPCVLE
, {CR
, BDP
}},
4480 {"bnl", BBOCB(16,BOF
,CBLT
,0,0), BBOATCB_MASK
, COM
, PPCVLE
, {CR
, BD
}},
4481 {"bgel-", BBOCB(16,BOF
,CBLT
,0,1), BBOATCB_MASK
, PPCCOM
, PPCVLE
, {CR
, BDM
}},
4482 {"bgel+", BBOCB(16,BOF
,CBLT
,0,1), BBOATCB_MASK
, PPCCOM
, PPCVLE
, {CR
, BDP
}},
4483 {"bgel", BBOCB(16,BOF
,CBLT
,0,1), BBOATCB_MASK
, COM
, PPCVLE
, {CR
, BD
}},
4484 {"bnll-", BBOCB(16,BOF
,CBLT
,0,1), BBOATCB_MASK
, PPCCOM
, PPCVLE
, {CR
, BDM
}},
4485 {"bnll+", BBOCB(16,BOF
,CBLT
,0,1), BBOATCB_MASK
, PPCCOM
, PPCVLE
, {CR
, BDP
}},
4486 {"bnll", BBOCB(16,BOF
,CBLT
,0,1), BBOATCB_MASK
, COM
, PPCVLE
, {CR
, BD
}},
4487 {"bgea-", BBOCB(16,BOF
,CBLT
,1,0), BBOATCB_MASK
, PPCCOM
, PPCVLE
, {CR
, BDMA
}},
4488 {"bgea+", BBOCB(16,BOF
,CBLT
,1,0), BBOATCB_MASK
, PPCCOM
, PPCVLE
, {CR
, BDPA
}},
4489 {"bgea", BBOCB(16,BOF
,CBLT
,1,0), BBOATCB_MASK
, COM
, PPCVLE
, {CR
, BDA
}},
4490 {"bnla-", BBOCB(16,BOF
,CBLT
,1,0), BBOATCB_MASK
, PPCCOM
, PPCVLE
, {CR
, BDMA
}},
4491 {"bnla+", BBOCB(16,BOF
,CBLT
,1,0), BBOATCB_MASK
, PPCCOM
, PPCVLE
, {CR
, BDPA
}},
4492 {"bnla", BBOCB(16,BOF
,CBLT
,1,0), BBOATCB_MASK
, COM
, PPCVLE
, {CR
, BDA
}},
4493 {"bgela-", BBOCB(16,BOF
,CBLT
,1,1), BBOATCB_MASK
, PPCCOM
, PPCVLE
, {CR
, BDMA
}},
4494 {"bgela+", BBOCB(16,BOF
,CBLT
,1,1), BBOATCB_MASK
, PPCCOM
, PPCVLE
, {CR
, BDPA
}},
4495 {"bgela", BBOCB(16,BOF
,CBLT
,1,1), BBOATCB_MASK
, COM
, PPCVLE
, {CR
, BDA
}},
4496 {"bnlla-", BBOCB(16,BOF
,CBLT
,1,1), BBOATCB_MASK
, PPCCOM
, PPCVLE
, {CR
, BDMA
}},
4497 {"bnlla+", BBOCB(16,BOF
,CBLT
,1,1), BBOATCB_MASK
, PPCCOM
, PPCVLE
, {CR
, BDPA
}},
4498 {"bnlla", BBOCB(16,BOF
,CBLT
,1,1), BBOATCB_MASK
, COM
, PPCVLE
, {CR
, BDA
}},
4499 {"ble-", BBOCB(16,BOF
,CBGT
,0,0), BBOATCB_MASK
, PPCCOM
, PPCVLE
, {CR
, BDM
}},
4500 {"ble+", BBOCB(16,BOF
,CBGT
,0,0), BBOATCB_MASK
, PPCCOM
, PPCVLE
, {CR
, BDP
}},
4501 {"ble", BBOCB(16,BOF
,CBGT
,0,0), BBOATCB_MASK
, COM
, PPCVLE
, {CR
, BD
}},
4502 {"bng-", BBOCB(16,BOF
,CBGT
,0,0), BBOATCB_MASK
, PPCCOM
, PPCVLE
, {CR
, BDM
}},
4503 {"bng+", BBOCB(16,BOF
,CBGT
,0,0), BBOATCB_MASK
, PPCCOM
, PPCVLE
, {CR
, BDP
}},
4504 {"bng", BBOCB(16,BOF
,CBGT
,0,0), BBOATCB_MASK
, COM
, PPCVLE
, {CR
, BD
}},
4505 {"blel-", BBOCB(16,BOF
,CBGT
,0,1), BBOATCB_MASK
, PPCCOM
, PPCVLE
, {CR
, BDM
}},
4506 {"blel+", BBOCB(16,BOF
,CBGT
,0,1), BBOATCB_MASK
, PPCCOM
, PPCVLE
, {CR
, BDP
}},
4507 {"blel", BBOCB(16,BOF
,CBGT
,0,1), BBOATCB_MASK
, COM
, PPCVLE
, {CR
, BD
}},
4508 {"bngl-", BBOCB(16,BOF
,CBGT
,0,1), BBOATCB_MASK
, PPCCOM
, PPCVLE
, {CR
, BDM
}},
4509 {"bngl+", BBOCB(16,BOF
,CBGT
,0,1), BBOATCB_MASK
, PPCCOM
, PPCVLE
, {CR
, BDP
}},
4510 {"bngl", BBOCB(16,BOF
,CBGT
,0,1), BBOATCB_MASK
, COM
, PPCVLE
, {CR
, BD
}},
4511 {"blea-", BBOCB(16,BOF
,CBGT
,1,0), BBOATCB_MASK
, PPCCOM
, PPCVLE
, {CR
, BDMA
}},
4512 {"blea+", BBOCB(16,BOF
,CBGT
,1,0), BBOATCB_MASK
, PPCCOM
, PPCVLE
, {CR
, BDPA
}},
4513 {"blea", BBOCB(16,BOF
,CBGT
,1,0), BBOATCB_MASK
, COM
, PPCVLE
, {CR
, BDA
}},
4514 {"bnga-", BBOCB(16,BOF
,CBGT
,1,0), BBOATCB_MASK
, PPCCOM
, PPCVLE
, {CR
, BDMA
}},
4515 {"bnga+", BBOCB(16,BOF
,CBGT
,1,0), BBOATCB_MASK
, PPCCOM
, PPCVLE
, {CR
, BDPA
}},
4516 {"bnga", BBOCB(16,BOF
,CBGT
,1,0), BBOATCB_MASK
, COM
, PPCVLE
, {CR
, BDA
}},
4517 {"blela-", BBOCB(16,BOF
,CBGT
,1,1), BBOATCB_MASK
, PPCCOM
, PPCVLE
, {CR
, BDMA
}},
4518 {"blela+", BBOCB(16,BOF
,CBGT
,1,1), BBOATCB_MASK
, PPCCOM
, PPCVLE
, {CR
, BDPA
}},
4519 {"blela", BBOCB(16,BOF
,CBGT
,1,1), BBOATCB_MASK
, COM
, PPCVLE
, {CR
, BDA
}},
4520 {"bngla-", BBOCB(16,BOF
,CBGT
,1,1), BBOATCB_MASK
, PPCCOM
, PPCVLE
, {CR
, BDMA
}},
4521 {"bngla+", BBOCB(16,BOF
,CBGT
,1,1), BBOATCB_MASK
, PPCCOM
, PPCVLE
, {CR
, BDPA
}},
4522 {"bngla", BBOCB(16,BOF
,CBGT
,1,1), BBOATCB_MASK
, COM
, PPCVLE
, {CR
, BDA
}},
4523 {"bne-", BBOCB(16,BOF
,CBEQ
,0,0), BBOATCB_MASK
, PPCCOM
, PPCVLE
, {CR
, BDM
}},
4524 {"bne+", BBOCB(16,BOF
,CBEQ
,0,0), BBOATCB_MASK
, PPCCOM
, PPCVLE
, {CR
, BDP
}},
4525 {"bne", BBOCB(16,BOF
,CBEQ
,0,0), BBOATCB_MASK
, COM
, PPCVLE
, {CR
, BD
}},
4526 {"bnel-", BBOCB(16,BOF
,CBEQ
,0,1), BBOATCB_MASK
, PPCCOM
, PPCVLE
, {CR
, BDM
}},
4527 {"bnel+", BBOCB(16,BOF
,CBEQ
,0,1), BBOATCB_MASK
, PPCCOM
, PPCVLE
, {CR
, BDP
}},
4528 {"bnel", BBOCB(16,BOF
,CBEQ
,0,1), BBOATCB_MASK
, COM
, PPCVLE
, {CR
, BD
}},
4529 {"bnea-", BBOCB(16,BOF
,CBEQ
,1,0), BBOATCB_MASK
, PPCCOM
, PPCVLE
, {CR
, BDMA
}},
4530 {"bnea+", BBOCB(16,BOF
,CBEQ
,1,0), BBOATCB_MASK
, PPCCOM
, PPCVLE
, {CR
, BDPA
}},
4531 {"bnea", BBOCB(16,BOF
,CBEQ
,1,0), BBOATCB_MASK
, COM
, PPCVLE
, {CR
, BDA
}},
4532 {"bnela-", BBOCB(16,BOF
,CBEQ
,1,1), BBOATCB_MASK
, PPCCOM
, PPCVLE
, {CR
, BDMA
}},
4533 {"bnela+", BBOCB(16,BOF
,CBEQ
,1,1), BBOATCB_MASK
, PPCCOM
, PPCVLE
, {CR
, BDPA
}},
4534 {"bnela", BBOCB(16,BOF
,CBEQ
,1,1), BBOATCB_MASK
, COM
, PPCVLE
, {CR
, BDA
}},
4535 {"bns-", BBOCB(16,BOF
,CBSO
,0,0), BBOATCB_MASK
, PPCCOM
, PPCVLE
, {CR
, BDM
}},
4536 {"bns+", BBOCB(16,BOF
,CBSO
,0,0), BBOATCB_MASK
, PPCCOM
, PPCVLE
, {CR
, BDP
}},
4537 {"bns", BBOCB(16,BOF
,CBSO
,0,0), BBOATCB_MASK
, COM
, PPCVLE
, {CR
, BD
}},
4538 {"bnu-", BBOCB(16,BOF
,CBSO
,0,0), BBOATCB_MASK
, PPCCOM
, PPCVLE
, {CR
, BDM
}},
4539 {"bnu+", BBOCB(16,BOF
,CBSO
,0,0), BBOATCB_MASK
, PPCCOM
, PPCVLE
, {CR
, BDP
}},
4540 {"bnu", BBOCB(16,BOF
,CBSO
,0,0), BBOATCB_MASK
, PPCCOM
, PPCVLE
, {CR
, BD
}},
4541 {"bnsl-", BBOCB(16,BOF
,CBSO
,0,1), BBOATCB_MASK
, PPCCOM
, PPCVLE
, {CR
, BDM
}},
4542 {"bnsl+", BBOCB(16,BOF
,CBSO
,0,1), BBOATCB_MASK
, PPCCOM
, PPCVLE
, {CR
, BDP
}},
4543 {"bnsl", BBOCB(16,BOF
,CBSO
,0,1), BBOATCB_MASK
, COM
, PPCVLE
, {CR
, BD
}},
4544 {"bnul-", BBOCB(16,BOF
,CBSO
,0,1), BBOATCB_MASK
, PPCCOM
, PPCVLE
, {CR
, BDM
}},
4545 {"bnul+", BBOCB(16,BOF
,CBSO
,0,1), BBOATCB_MASK
, PPCCOM
, PPCVLE
, {CR
, BDP
}},
4546 {"bnul", BBOCB(16,BOF
,CBSO
,0,1), BBOATCB_MASK
, PPCCOM
, PPCVLE
, {CR
, BD
}},
4547 {"bnsa-", BBOCB(16,BOF
,CBSO
,1,0), BBOATCB_MASK
, PPCCOM
, PPCVLE
, {CR
, BDMA
}},
4548 {"bnsa+", BBOCB(16,BOF
,CBSO
,1,0), BBOATCB_MASK
, PPCCOM
, PPCVLE
, {CR
, BDPA
}},
4549 {"bnsa", BBOCB(16,BOF
,CBSO
,1,0), BBOATCB_MASK
, COM
, PPCVLE
, {CR
, BDA
}},
4550 {"bnua-", BBOCB(16,BOF
,CBSO
,1,0), BBOATCB_MASK
, PPCCOM
, PPCVLE
, {CR
, BDMA
}},
4551 {"bnua+", BBOCB(16,BOF
,CBSO
,1,0), BBOATCB_MASK
, PPCCOM
, PPCVLE
, {CR
, BDPA
}},
4552 {"bnua", BBOCB(16,BOF
,CBSO
,1,0), BBOATCB_MASK
, PPCCOM
, PPCVLE
, {CR
, BDA
}},
4553 {"bnsla-", BBOCB(16,BOF
,CBSO
,1,1), BBOATCB_MASK
, PPCCOM
, PPCVLE
, {CR
, BDMA
}},
4554 {"bnsla+", BBOCB(16,BOF
,CBSO
,1,1), BBOATCB_MASK
, PPCCOM
, PPCVLE
, {CR
, BDPA
}},
4555 {"bnsla", BBOCB(16,BOF
,CBSO
,1,1), BBOATCB_MASK
, COM
, PPCVLE
, {CR
, BDA
}},
4556 {"bnula-", BBOCB(16,BOF
,CBSO
,1,1), BBOATCB_MASK
, PPCCOM
, PPCVLE
, {CR
, BDMA
}},
4557 {"bnula+", BBOCB(16,BOF
,CBSO
,1,1), BBOATCB_MASK
, PPCCOM
, PPCVLE
, {CR
, BDPA
}},
4558 {"bnula", BBOCB(16,BOF
,CBSO
,1,1), BBOATCB_MASK
, PPCCOM
, PPCVLE
, {CR
, BDA
}},
4560 {"blt-", BBOCB(16,BOT
,CBLT
,0,0), BBOATCB_MASK
, PPCCOM
, PPCVLE
, {CR
, BDM
}},
4561 {"blt+", BBOCB(16,BOT
,CBLT
,0,0), BBOATCB_MASK
, PPCCOM
, PPCVLE
, {CR
, BDP
}},
4562 {"blt", BBOCB(16,BOT
,CBLT
,0,0), BBOATCB_MASK
, COM
, PPCVLE
, {CR
, BD
}},
4563 {"bltl-", BBOCB(16,BOT
,CBLT
,0,1), BBOATCB_MASK
, PPCCOM
, PPCVLE
, {CR
, BDM
}},
4564 {"bltl+", BBOCB(16,BOT
,CBLT
,0,1), BBOATCB_MASK
, PPCCOM
, PPCVLE
, {CR
, BDP
}},
4565 {"bltl", BBOCB(16,BOT
,CBLT
,0,1), BBOATCB_MASK
, COM
, PPCVLE
, {CR
, BD
}},
4566 {"blta-", BBOCB(16,BOT
,CBLT
,1,0), BBOATCB_MASK
, PPCCOM
, PPCVLE
, {CR
, BDMA
}},
4567 {"blta+", BBOCB(16,BOT
,CBLT
,1,0), BBOATCB_MASK
, PPCCOM
, PPCVLE
, {CR
, BDPA
}},
4568 {"blta", BBOCB(16,BOT
,CBLT
,1,0), BBOATCB_MASK
, COM
, PPCVLE
, {CR
, BDA
}},
4569 {"bltla-", BBOCB(16,BOT
,CBLT
,1,1), BBOATCB_MASK
, PPCCOM
, PPCVLE
, {CR
, BDMA
}},
4570 {"bltla+", BBOCB(16,BOT
,CBLT
,1,1), BBOATCB_MASK
, PPCCOM
, PPCVLE
, {CR
, BDPA
}},
4571 {"bltla", BBOCB(16,BOT
,CBLT
,1,1), BBOATCB_MASK
, COM
, PPCVLE
, {CR
, BDA
}},
4572 {"bgt-", BBOCB(16,BOT
,CBGT
,0,0), BBOATCB_MASK
, PPCCOM
, PPCVLE
, {CR
, BDM
}},
4573 {"bgt+", BBOCB(16,BOT
,CBGT
,0,0), BBOATCB_MASK
, PPCCOM
, PPCVLE
, {CR
, BDP
}},
4574 {"bgt", BBOCB(16,BOT
,CBGT
,0,0), BBOATCB_MASK
, COM
, PPCVLE
, {CR
, BD
}},
4575 {"bgtl-", BBOCB(16,BOT
,CBGT
,0,1), BBOATCB_MASK
, PPCCOM
, PPCVLE
, {CR
, BDM
}},
4576 {"bgtl+", BBOCB(16,BOT
,CBGT
,0,1), BBOATCB_MASK
, PPCCOM
, PPCVLE
, {CR
, BDP
}},
4577 {"bgtl", BBOCB(16,BOT
,CBGT
,0,1), BBOATCB_MASK
, COM
, PPCVLE
, {CR
, BD
}},
4578 {"bgta-", BBOCB(16,BOT
,CBGT
,1,0), BBOATCB_MASK
, PPCCOM
, PPCVLE
, {CR
, BDMA
}},
4579 {"bgta+", BBOCB(16,BOT
,CBGT
,1,0), BBOATCB_MASK
, PPCCOM
, PPCVLE
, {CR
, BDPA
}},
4580 {"bgta", BBOCB(16,BOT
,CBGT
,1,0), BBOATCB_MASK
, COM
, PPCVLE
, {CR
, BDA
}},
4581 {"bgtla-", BBOCB(16,BOT
,CBGT
,1,1), BBOATCB_MASK
, PPCCOM
, PPCVLE
, {CR
, BDMA
}},
4582 {"bgtla+", BBOCB(16,BOT
,CBGT
,1,1), BBOATCB_MASK
, PPCCOM
, PPCVLE
, {CR
, BDPA
}},
4583 {"bgtla", BBOCB(16,BOT
,CBGT
,1,1), BBOATCB_MASK
, COM
, PPCVLE
, {CR
, BDA
}},
4584 {"beq-", BBOCB(16,BOT
,CBEQ
,0,0), BBOATCB_MASK
, PPCCOM
, PPCVLE
, {CR
, BDM
}},
4585 {"beq+", BBOCB(16,BOT
,CBEQ
,0,0), BBOATCB_MASK
, PPCCOM
, PPCVLE
, {CR
, BDP
}},
4586 {"beq", BBOCB(16,BOT
,CBEQ
,0,0), BBOATCB_MASK
, COM
, PPCVLE
, {CR
, BD
}},
4587 {"beql-", BBOCB(16,BOT
,CBEQ
,0,1), BBOATCB_MASK
, PPCCOM
, PPCVLE
, {CR
, BDM
}},
4588 {"beql+", BBOCB(16,BOT
,CBEQ
,0,1), BBOATCB_MASK
, PPCCOM
, PPCVLE
, {CR
, BDP
}},
4589 {"beql", BBOCB(16,BOT
,CBEQ
,0,1), BBOATCB_MASK
, COM
, PPCVLE
, {CR
, BD
}},
4590 {"beqa-", BBOCB(16,BOT
,CBEQ
,1,0), BBOATCB_MASK
, PPCCOM
, PPCVLE
, {CR
, BDMA
}},
4591 {"beqa+", BBOCB(16,BOT
,CBEQ
,1,0), BBOATCB_MASK
, PPCCOM
, PPCVLE
, {CR
, BDPA
}},
4592 {"beqa", BBOCB(16,BOT
,CBEQ
,1,0), BBOATCB_MASK
, COM
, PPCVLE
, {CR
, BDA
}},
4593 {"beqla-", BBOCB(16,BOT
,CBEQ
,1,1), BBOATCB_MASK
, PPCCOM
, PPCVLE
, {CR
, BDMA
}},
4594 {"beqla+", BBOCB(16,BOT
,CBEQ
,1,1), BBOATCB_MASK
, PPCCOM
, PPCVLE
, {CR
, BDPA
}},
4595 {"beqla", BBOCB(16,BOT
,CBEQ
,1,1), BBOATCB_MASK
, COM
, PPCVLE
, {CR
, BDA
}},
4596 {"bso-", BBOCB(16,BOT
,CBSO
,0,0), BBOATCB_MASK
, PPCCOM
, PPCVLE
, {CR
, BDM
}},
4597 {"bso+", BBOCB(16,BOT
,CBSO
,0,0), BBOATCB_MASK
, PPCCOM
, PPCVLE
, {CR
, BDP
}},
4598 {"bso", BBOCB(16,BOT
,CBSO
,0,0), BBOATCB_MASK
, COM
, PPCVLE
, {CR
, BD
}},
4599 {"bun-", BBOCB(16,BOT
,CBSO
,0,0), BBOATCB_MASK
, PPCCOM
, PPCVLE
, {CR
, BDM
}},
4600 {"bun+", BBOCB(16,BOT
,CBSO
,0,0), BBOATCB_MASK
, PPCCOM
, PPCVLE
, {CR
, BDP
}},
4601 {"bun", BBOCB(16,BOT
,CBSO
,0,0), BBOATCB_MASK
, PPCCOM
, PPCVLE
, {CR
, BD
}},
4602 {"bsol-", BBOCB(16,BOT
,CBSO
,0,1), BBOATCB_MASK
, PPCCOM
, PPCVLE
, {CR
, BDM
}},
4603 {"bsol+", BBOCB(16,BOT
,CBSO
,0,1), BBOATCB_MASK
, PPCCOM
, PPCVLE
, {CR
, BDP
}},
4604 {"bsol", BBOCB(16,BOT
,CBSO
,0,1), BBOATCB_MASK
, COM
, PPCVLE
, {CR
, BD
}},
4605 {"bunl-", BBOCB(16,BOT
,CBSO
,0,1), BBOATCB_MASK
, PPCCOM
, PPCVLE
, {CR
, BDM
}},
4606 {"bunl+", BBOCB(16,BOT
,CBSO
,0,1), BBOATCB_MASK
, PPCCOM
, PPCVLE
, {CR
, BDP
}},
4607 {"bunl", BBOCB(16,BOT
,CBSO
,0,1), BBOATCB_MASK
, PPCCOM
, PPCVLE
, {CR
, BD
}},
4608 {"bsoa-", BBOCB(16,BOT
,CBSO
,1,0), BBOATCB_MASK
, PPCCOM
, PPCVLE
, {CR
, BDMA
}},
4609 {"bsoa+", BBOCB(16,BOT
,CBSO
,1,0), BBOATCB_MASK
, PPCCOM
, PPCVLE
, {CR
, BDPA
}},
4610 {"bsoa", BBOCB(16,BOT
,CBSO
,1,0), BBOATCB_MASK
, COM
, PPCVLE
, {CR
, BDA
}},
4611 {"buna-", BBOCB(16,BOT
,CBSO
,1,0), BBOATCB_MASK
, PPCCOM
, PPCVLE
, {CR
, BDMA
}},
4612 {"buna+", BBOCB(16,BOT
,CBSO
,1,0), BBOATCB_MASK
, PPCCOM
, PPCVLE
, {CR
, BDPA
}},
4613 {"buna", BBOCB(16,BOT
,CBSO
,1,0), BBOATCB_MASK
, PPCCOM
, PPCVLE
, {CR
, BDA
}},
4614 {"bsola-", BBOCB(16,BOT
,CBSO
,1,1), BBOATCB_MASK
, PPCCOM
, PPCVLE
, {CR
, BDMA
}},
4615 {"bsola+", BBOCB(16,BOT
,CBSO
,1,1), BBOATCB_MASK
, PPCCOM
, PPCVLE
, {CR
, BDPA
}},
4616 {"bsola", BBOCB(16,BOT
,CBSO
,1,1), BBOATCB_MASK
, COM
, PPCVLE
, {CR
, BDA
}},
4617 {"bunla-", BBOCB(16,BOT
,CBSO
,1,1), BBOATCB_MASK
, PPCCOM
, PPCVLE
, {CR
, BDMA
}},
4618 {"bunla+", BBOCB(16,BOT
,CBSO
,1,1), BBOATCB_MASK
, PPCCOM
, PPCVLE
, {CR
, BDPA
}},
4619 {"bunla", BBOCB(16,BOT
,CBSO
,1,1), BBOATCB_MASK
, PPCCOM
, PPCVLE
, {CR
, BDA
}},
4621 {"bdnzf-", BBO(16,BODNZF
,0,0), BBOY_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {BI
, BDM
}},
4622 {"bdnzf+", BBO(16,BODNZF
,0,0), BBOY_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {BI
, BDP
}},
4623 {"bdnzf", BBO(16,BODNZF
,0,0), BBOY_MASK
, PPCCOM
, PPCVLE
, {BI
, BD
}},
4624 {"bdnzfl-", BBO(16,BODNZF
,0,1), BBOY_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {BI
, BDM
}},
4625 {"bdnzfl+", BBO(16,BODNZF
,0,1), BBOY_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {BI
, BDP
}},
4626 {"bdnzfl", BBO(16,BODNZF
,0,1), BBOY_MASK
, PPCCOM
, PPCVLE
, {BI
, BD
}},
4627 {"bdnzfa-", BBO(16,BODNZF
,1,0), BBOY_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {BI
, BDMA
}},
4628 {"bdnzfa+", BBO(16,BODNZF
,1,0), BBOY_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {BI
, BDPA
}},
4629 {"bdnzfa", BBO(16,BODNZF
,1,0), BBOY_MASK
, PPCCOM
, PPCVLE
, {BI
, BDA
}},
4630 {"bdnzfla-", BBO(16,BODNZF
,1,1), BBOY_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {BI
, BDMA
}},
4631 {"bdnzfla+", BBO(16,BODNZF
,1,1), BBOY_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {BI
, BDPA
}},
4632 {"bdnzfla", BBO(16,BODNZF
,1,1), BBOY_MASK
, PPCCOM
, PPCVLE
, {BI
, BDA
}},
4633 {"bdzf-", BBO(16,BODZF
,0,0), BBOY_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {BI
, BDM
}},
4634 {"bdzf+", BBO(16,BODZF
,0,0), BBOY_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {BI
, BDP
}},
4635 {"bdzf", BBO(16,BODZF
,0,0), BBOY_MASK
, PPCCOM
, PPCVLE
, {BI
, BD
}},
4636 {"bdzfl-", BBO(16,BODZF
,0,1), BBOY_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {BI
, BDM
}},
4637 {"bdzfl+", BBO(16,BODZF
,0,1), BBOY_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {BI
, BDP
}},
4638 {"bdzfl", BBO(16,BODZF
,0,1), BBOY_MASK
, PPCCOM
, PPCVLE
, {BI
, BD
}},
4639 {"bdzfa-", BBO(16,BODZF
,1,0), BBOY_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {BI
, BDMA
}},
4640 {"bdzfa+", BBO(16,BODZF
,1,0), BBOY_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {BI
, BDPA
}},
4641 {"bdzfa", BBO(16,BODZF
,1,0), BBOY_MASK
, PPCCOM
, PPCVLE
, {BI
, BDA
}},
4642 {"bdzfla-", BBO(16,BODZF
,1,1), BBOY_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {BI
, BDMA
}},
4643 {"bdzfla+", BBO(16,BODZF
,1,1), BBOY_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {BI
, BDPA
}},
4644 {"bdzfla", BBO(16,BODZF
,1,1), BBOY_MASK
, PPCCOM
, PPCVLE
, {BI
, BDA
}},
4646 {"bf-", BBO(16,BOF
,0,0), BBOAT_MASK
, PPCCOM
, PPCVLE
, {BI
, BDM
}},
4647 {"bf+", BBO(16,BOF
,0,0), BBOAT_MASK
, PPCCOM
, PPCVLE
, {BI
, BDP
}},
4648 {"bf", BBO(16,BOF
,0,0), BBOAT_MASK
, PPCCOM
, PPCVLE
, {BI
, BD
}},
4649 {"bbf", BBO(16,BOF
,0,0), BBOAT_MASK
, PWRCOM
, PPCVLE
, {BI
, BD
}},
4650 {"bfl-", BBO(16,BOF
,0,1), BBOAT_MASK
, PPCCOM
, PPCVLE
, {BI
, BDM
}},
4651 {"bfl+", BBO(16,BOF
,0,1), BBOAT_MASK
, PPCCOM
, PPCVLE
, {BI
, BDP
}},
4652 {"bfl", BBO(16,BOF
,0,1), BBOAT_MASK
, PPCCOM
, PPCVLE
, {BI
, BD
}},
4653 {"bbfl", BBO(16,BOF
,0,1), BBOAT_MASK
, PWRCOM
, PPCVLE
, {BI
, BD
}},
4654 {"bfa-", BBO(16,BOF
,1,0), BBOAT_MASK
, PPCCOM
, PPCVLE
, {BI
, BDMA
}},
4655 {"bfa+", BBO(16,BOF
,1,0), BBOAT_MASK
, PPCCOM
, PPCVLE
, {BI
, BDPA
}},
4656 {"bfa", BBO(16,BOF
,1,0), BBOAT_MASK
, PPCCOM
, PPCVLE
, {BI
, BDA
}},
4657 {"bbfa", BBO(16,BOF
,1,0), BBOAT_MASK
, PWRCOM
, PPCVLE
, {BI
, BDA
}},
4658 {"bfla-", BBO(16,BOF
,1,1), BBOAT_MASK
, PPCCOM
, PPCVLE
, {BI
, BDMA
}},
4659 {"bfla+", BBO(16,BOF
,1,1), BBOAT_MASK
, PPCCOM
, PPCVLE
, {BI
, BDPA
}},
4660 {"bfla", BBO(16,BOF
,1,1), BBOAT_MASK
, PPCCOM
, PPCVLE
, {BI
, BDA
}},
4661 {"bbfla", BBO(16,BOF
,1,1), BBOAT_MASK
, PWRCOM
, PPCVLE
, {BI
, BDA
}},
4663 {"bdnzt-", BBO(16,BODNZT
,0,0), BBOY_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {BI
, BDM
}},
4664 {"bdnzt+", BBO(16,BODNZT
,0,0), BBOY_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {BI
, BDP
}},
4665 {"bdnzt", BBO(16,BODNZT
,0,0), BBOY_MASK
, PPCCOM
, PPCVLE
, {BI
, BD
}},
4666 {"bdnztl-", BBO(16,BODNZT
,0,1), BBOY_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {BI
, BDM
}},
4667 {"bdnztl+", BBO(16,BODNZT
,0,1), BBOY_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {BI
, BDP
}},
4668 {"bdnztl", BBO(16,BODNZT
,0,1), BBOY_MASK
, PPCCOM
, PPCVLE
, {BI
, BD
}},
4669 {"bdnzta-", BBO(16,BODNZT
,1,0), BBOY_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {BI
, BDMA
}},
4670 {"bdnzta+", BBO(16,BODNZT
,1,0), BBOY_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {BI
, BDPA
}},
4671 {"bdnzta", BBO(16,BODNZT
,1,0), BBOY_MASK
, PPCCOM
, PPCVLE
, {BI
, BDA
}},
4672 {"bdnztla-", BBO(16,BODNZT
,1,1), BBOY_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {BI
, BDMA
}},
4673 {"bdnztla+", BBO(16,BODNZT
,1,1), BBOY_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {BI
, BDPA
}},
4674 {"bdnztla", BBO(16,BODNZT
,1,1), BBOY_MASK
, PPCCOM
, PPCVLE
, {BI
, BDA
}},
4675 {"bdzt-", BBO(16,BODZT
,0,0), BBOY_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {BI
, BDM
}},
4676 {"bdzt+", BBO(16,BODZT
,0,0), BBOY_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {BI
, BDP
}},
4677 {"bdzt", BBO(16,BODZT
,0,0), BBOY_MASK
, PPCCOM
, PPCVLE
, {BI
, BD
}},
4678 {"bdztl-", BBO(16,BODZT
,0,1), BBOY_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {BI
, BDM
}},
4679 {"bdztl+", BBO(16,BODZT
,0,1), BBOY_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {BI
, BDP
}},
4680 {"bdztl", BBO(16,BODZT
,0,1), BBOY_MASK
, PPCCOM
, PPCVLE
, {BI
, BD
}},
4681 {"bdzta-", BBO(16,BODZT
,1,0), BBOY_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {BI
, BDMA
}},
4682 {"bdzta+", BBO(16,BODZT
,1,0), BBOY_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {BI
, BDPA
}},
4683 {"bdzta", BBO(16,BODZT
,1,0), BBOY_MASK
, PPCCOM
, PPCVLE
, {BI
, BDA
}},
4684 {"bdztla-", BBO(16,BODZT
,1,1), BBOY_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {BI
, BDMA
}},
4685 {"bdztla+", BBO(16,BODZT
,1,1), BBOY_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {BI
, BDPA
}},
4686 {"bdztla", BBO(16,BODZT
,1,1), BBOY_MASK
, PPCCOM
, PPCVLE
, {BI
, BDA
}},
4688 {"bt-", BBO(16,BOT
,0,0), BBOAT_MASK
, PPCCOM
, PPCVLE
, {BI
, BDM
}},
4689 {"bt+", BBO(16,BOT
,0,0), BBOAT_MASK
, PPCCOM
, PPCVLE
, {BI
, BDP
}},
4690 {"bt", BBO(16,BOT
,0,0), BBOAT_MASK
, PPCCOM
, PPCVLE
, {BI
, BD
}},
4691 {"bbt", BBO(16,BOT
,0,0), BBOAT_MASK
, PWRCOM
, PPCVLE
, {BI
, BD
}},
4692 {"btl-", BBO(16,BOT
,0,1), BBOAT_MASK
, PPCCOM
, PPCVLE
, {BI
, BDM
}},
4693 {"btl+", BBO(16,BOT
,0,1), BBOAT_MASK
, PPCCOM
, PPCVLE
, {BI
, BDP
}},
4694 {"btl", BBO(16,BOT
,0,1), BBOAT_MASK
, PPCCOM
, PPCVLE
, {BI
, BD
}},
4695 {"bbtl", BBO(16,BOT
,0,1), BBOAT_MASK
, PWRCOM
, PPCVLE
, {BI
, BD
}},
4696 {"bta-", BBO(16,BOT
,1,0), BBOAT_MASK
, PPCCOM
, PPCVLE
, {BI
, BDMA
}},
4697 {"bta+", BBO(16,BOT
,1,0), BBOAT_MASK
, PPCCOM
, PPCVLE
, {BI
, BDPA
}},
4698 {"bta", BBO(16,BOT
,1,0), BBOAT_MASK
, PPCCOM
, PPCVLE
, {BI
, BDA
}},
4699 {"bbta", BBO(16,BOT
,1,0), BBOAT_MASK
, PWRCOM
, PPCVLE
, {BI
, BDA
}},
4700 {"btla-", BBO(16,BOT
,1,1), BBOAT_MASK
, PPCCOM
, PPCVLE
, {BI
, BDMA
}},
4701 {"btla+", BBO(16,BOT
,1,1), BBOAT_MASK
, PPCCOM
, PPCVLE
, {BI
, BDPA
}},
4702 {"btla", BBO(16,BOT
,1,1), BBOAT_MASK
, PPCCOM
, PPCVLE
, {BI
, BDA
}},
4703 {"bbtla", BBO(16,BOT
,1,1), BBOAT_MASK
, PWRCOM
, PPCVLE
, {BI
, BDA
}},
4705 {"bc-", B(16,0,0), B_MASK
, PPCCOM
, PPCVLE
, {BOE
, BI
, BDM
}},
4706 {"bc+", B(16,0,0), B_MASK
, PPCCOM
, PPCVLE
, {BOE
, BI
, BDP
}},
4707 {"bc", B(16,0,0), B_MASK
, COM
, PPCVLE
, {BO
, BI
, BD
}},
4708 {"bcl-", B(16,0,1), B_MASK
, PPCCOM
, PPCVLE
, {BOE
, BI
, BDM
}},
4709 {"bcl+", B(16,0,1), B_MASK
, PPCCOM
, PPCVLE
, {BOE
, BI
, BDP
}},
4710 {"bcl", B(16,0,1), B_MASK
, COM
, PPCVLE
, {BO
, BI
, BD
}},
4711 {"bca-", B(16,1,0), B_MASK
, PPCCOM
, PPCVLE
, {BOE
, BI
, BDMA
}},
4712 {"bca+", B(16,1,0), B_MASK
, PPCCOM
, PPCVLE
, {BOE
, BI
, BDPA
}},
4713 {"bca", B(16,1,0), B_MASK
, COM
, PPCVLE
, {BO
, BI
, BDA
}},
4714 {"bcla-", B(16,1,1), B_MASK
, PPCCOM
, PPCVLE
, {BOE
, BI
, BDMA
}},
4715 {"bcla+", B(16,1,1), B_MASK
, PPCCOM
, PPCVLE
, {BOE
, BI
, BDPA
}},
4716 {"bcla", B(16,1,1), B_MASK
, COM
, PPCVLE
, {BO
, BI
, BDA
}},
4718 {"svc", SC(17,0,0), SC_MASK
, POWER
, PPCVLE
, {SVC_LEV
, FL1
, FL2
}},
4719 {"scv", SC(17,0,1), SC_MASK
, POWER9
, PPCVLE
, {SVC_LEV
}},
4720 {"svcl", SC(17,0,1), SC_MASK
, POWER
, PPCVLE
, {SVC_LEV
, FL1
, FL2
}},
4721 {"sc", SC(17,1,0), SC_MASK
, PPC
, PPCVLE
, {LEV
}},
4722 {"svca", SC(17,1,0), SC_MASK
, PWRCOM
, PPCVLE
, {SV
}},
4723 {"svcla", SC(17,1,1), SC_MASK
, POWER
, PPCVLE
, {SV
}},
4725 {"b", B(18,0,0), B_MASK
, COM
, PPCVLE
, {LI
}},
4726 {"bl", B(18,0,1), B_MASK
, COM
, PPCVLE
, {LI
}},
4727 {"ba", B(18,1,0), B_MASK
, COM
, PPCVLE
, {LIA
}},
4728 {"bla", B(18,1,1), B_MASK
, COM
, PPCVLE
, {LIA
}},
4730 {"mcrf", XL(19,0), XLBB_MASK
|(3<<21)|(3<<16), COM
, PPCVLE
, {BF
, BFA
}},
4732 {"lnia", DX(19,2), NODX_MASK
, POWER9
, PPCVLE
, {RT
}},
4733 {"addpcis", DX(19,2), DX_MASK
, POWER9
, PPCVLE
, {RT
, DXD
}},
4734 {"subpcis", DX(19,2), DX_MASK
, POWER9
, PPCVLE
, {RT
, NDXD
}},
4736 {"bdnzlr", XLO(19,BODNZ
,16,0), XLBOBIBB_MASK
, PPCCOM
, PPCVLE
, {0}},
4737 {"bdnzlr-", XLO(19,BODNZ
,16,0), XLBOBIBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {0}},
4738 {"bdnzlrl", XLO(19,BODNZ
,16,1), XLBOBIBB_MASK
, PPCCOM
, PPCVLE
, {0}},
4739 {"bdnzlrl-", XLO(19,BODNZ
,16,1), XLBOBIBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {0}},
4740 {"bdnzlr+", XLO(19,BODNZP
,16,0), XLBOBIBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {0}},
4741 {"bdnzlrl+", XLO(19,BODNZP
,16,1), XLBOBIBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {0}},
4742 {"bdzlr", XLO(19,BODZ
,16,0), XLBOBIBB_MASK
, PPCCOM
, PPCVLE
, {0}},
4743 {"bdzlr-", XLO(19,BODZ
,16,0), XLBOBIBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {0}},
4744 {"bdzlrl", XLO(19,BODZ
,16,1), XLBOBIBB_MASK
, PPCCOM
, PPCVLE
, {0}},
4745 {"bdzlrl-", XLO(19,BODZ
,16,1), XLBOBIBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {0}},
4746 {"bdzlr+", XLO(19,BODZP
,16,0), XLBOBIBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {0}},
4747 {"bdzlrl+", XLO(19,BODZP
,16,1), XLBOBIBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {0}},
4748 {"blr", XLO(19,BOU
,16,0), XLBOBIBB_MASK
, PPCCOM
, PPCVLE
, {0}},
4749 {"br", XLO(19,BOU
,16,0), XLBOBIBB_MASK
, PWRCOM
, PPCVLE
, {0}},
4750 {"blrl", XLO(19,BOU
,16,1), XLBOBIBB_MASK
, PPCCOM
, PPCVLE
, {0}},
4751 {"brl", XLO(19,BOU
,16,1), XLBOBIBB_MASK
, PWRCOM
, PPCVLE
, {0}},
4752 {"bdnzlr-", XLO(19,BODNZM4
,16,0), XLBOBIBB_MASK
, ISA_V2
, PPCVLE
, {0}},
4753 {"bdnzlrl-", XLO(19,BODNZM4
,16,1), XLBOBIBB_MASK
, ISA_V2
, PPCVLE
, {0}},
4754 {"bdnzlr+", XLO(19,BODNZP4
,16,0), XLBOBIBB_MASK
, ISA_V2
, PPCVLE
, {0}},
4755 {"bdnzlrl+", XLO(19,BODNZP4
,16,1), XLBOBIBB_MASK
, ISA_V2
, PPCVLE
, {0}},
4756 {"bdzlr-", XLO(19,BODZM4
,16,0), XLBOBIBB_MASK
, ISA_V2
, PPCVLE
, {0}},
4757 {"bdzlrl-", XLO(19,BODZM4
,16,1), XLBOBIBB_MASK
, ISA_V2
, PPCVLE
, {0}},
4758 {"bdzlr+", XLO(19,BODZP4
,16,0), XLBOBIBB_MASK
, ISA_V2
, PPCVLE
, {0}},
4759 {"bdzlrl+", XLO(19,BODZP4
,16,1), XLBOBIBB_MASK
, ISA_V2
, PPCVLE
, {0}},
4761 {"bgelr", XLOCB(19,BOF
,CBLT
,16,0), XLBOCBBB_MASK
, PPCCOM
, PPCVLE
, {CR
}},
4762 {"bgelr-", XLOCB(19,BOF
,CBLT
,16,0), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {CR
}},
4763 {"bger", XLOCB(19,BOF
,CBLT
,16,0), XLBOCBBB_MASK
, PWRCOM
, PPCVLE
, {CR
}},
4764 {"bnllr", XLOCB(19,BOF
,CBLT
,16,0), XLBOCBBB_MASK
, PPCCOM
, PPCVLE
, {CR
}},
4765 {"bnllr-", XLOCB(19,BOF
,CBLT
,16,0), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {CR
}},
4766 {"bnlr", XLOCB(19,BOF
,CBLT
,16,0), XLBOCBBB_MASK
, PWRCOM
, PPCVLE
, {CR
}},
4767 {"bgelrl", XLOCB(19,BOF
,CBLT
,16,1), XLBOCBBB_MASK
, PPCCOM
, PPCVLE
, {CR
}},
4768 {"bgelrl-", XLOCB(19,BOF
,CBLT
,16,1), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {CR
}},
4769 {"bgerl", XLOCB(19,BOF
,CBLT
,16,1), XLBOCBBB_MASK
, PWRCOM
, PPCVLE
, {CR
}},
4770 {"bnllrl", XLOCB(19,BOF
,CBLT
,16,1), XLBOCBBB_MASK
, PPCCOM
, PPCVLE
, {CR
}},
4771 {"bnllrl-", XLOCB(19,BOF
,CBLT
,16,1), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {CR
}},
4772 {"bnlrl", XLOCB(19,BOF
,CBLT
,16,1), XLBOCBBB_MASK
, PWRCOM
, PPCVLE
, {CR
}},
4773 {"blelr", XLOCB(19,BOF
,CBGT
,16,0), XLBOCBBB_MASK
, PPCCOM
, PPCVLE
, {CR
}},
4774 {"blelr-", XLOCB(19,BOF
,CBGT
,16,0), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {CR
}},
4775 {"bler", XLOCB(19,BOF
,CBGT
,16,0), XLBOCBBB_MASK
, PWRCOM
, PPCVLE
, {CR
}},
4776 {"bnglr", XLOCB(19,BOF
,CBGT
,16,0), XLBOCBBB_MASK
, PPCCOM
, PPCVLE
, {CR
}},
4777 {"bnglr-", XLOCB(19,BOF
,CBGT
,16,0), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {CR
}},
4778 {"bngr", XLOCB(19,BOF
,CBGT
,16,0), XLBOCBBB_MASK
, PWRCOM
, PPCVLE
, {CR
}},
4779 {"blelrl", XLOCB(19,BOF
,CBGT
,16,1), XLBOCBBB_MASK
, PPCCOM
, PPCVLE
, {CR
}},
4780 {"blelrl-", XLOCB(19,BOF
,CBGT
,16,1), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {CR
}},
4781 {"blerl", XLOCB(19,BOF
,CBGT
,16,1), XLBOCBBB_MASK
, PWRCOM
, PPCVLE
, {CR
}},
4782 {"bnglrl", XLOCB(19,BOF
,CBGT
,16,1), XLBOCBBB_MASK
, PPCCOM
, PPCVLE
, {CR
}},
4783 {"bnglrl-", XLOCB(19,BOF
,CBGT
,16,1), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {CR
}},
4784 {"bngrl", XLOCB(19,BOF
,CBGT
,16,1), XLBOCBBB_MASK
, PWRCOM
, PPCVLE
, {CR
}},
4785 {"bnelr", XLOCB(19,BOF
,CBEQ
,16,0), XLBOCBBB_MASK
, PPCCOM
, PPCVLE
, {CR
}},
4786 {"bnelr-", XLOCB(19,BOF
,CBEQ
,16,0), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {CR
}},
4787 {"bner", XLOCB(19,BOF
,CBEQ
,16,0), XLBOCBBB_MASK
, PWRCOM
, PPCVLE
, {CR
}},
4788 {"bnelrl", XLOCB(19,BOF
,CBEQ
,16,1), XLBOCBBB_MASK
, PPCCOM
, PPCVLE
, {CR
}},
4789 {"bnelrl-", XLOCB(19,BOF
,CBEQ
,16,1), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {CR
}},
4790 {"bnerl", XLOCB(19,BOF
,CBEQ
,16,1), XLBOCBBB_MASK
, PWRCOM
, PPCVLE
, {CR
}},
4791 {"bnslr", XLOCB(19,BOF
,CBSO
,16,0), XLBOCBBB_MASK
, PPCCOM
, PPCVLE
, {CR
}},
4792 {"bnslr-", XLOCB(19,BOF
,CBSO
,16,0), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {CR
}},
4793 {"bnsr", XLOCB(19,BOF
,CBSO
,16,0), XLBOCBBB_MASK
, PWRCOM
, PPCVLE
, {CR
}},
4794 {"bnulr", XLOCB(19,BOF
,CBSO
,16,0), XLBOCBBB_MASK
, PPCCOM
, PPCVLE
, {CR
}},
4795 {"bnulr-", XLOCB(19,BOF
,CBSO
,16,0), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {CR
}},
4796 {"bnslrl", XLOCB(19,BOF
,CBSO
,16,1), XLBOCBBB_MASK
, PPCCOM
, PPCVLE
, {CR
}},
4797 {"bnslrl-", XLOCB(19,BOF
,CBSO
,16,1), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {CR
}},
4798 {"bnsrl", XLOCB(19,BOF
,CBSO
,16,1), XLBOCBBB_MASK
, PWRCOM
, PPCVLE
, {CR
}},
4799 {"bnulrl", XLOCB(19,BOF
,CBSO
,16,1), XLBOCBBB_MASK
, PPCCOM
, PPCVLE
, {CR
}},
4800 {"bnulrl-", XLOCB(19,BOF
,CBSO
,16,1), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {CR
}},
4801 {"bgelr+", XLOCB(19,BOFP
,CBLT
,16,0), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {CR
}},
4802 {"bnllr+", XLOCB(19,BOFP
,CBLT
,16,0), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {CR
}},
4803 {"bgelrl+", XLOCB(19,BOFP
,CBLT
,16,1), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {CR
}},
4804 {"bnllrl+", XLOCB(19,BOFP
,CBLT
,16,1), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {CR
}},
4805 {"blelr+", XLOCB(19,BOFP
,CBGT
,16,0), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {CR
}},
4806 {"bnglr+", XLOCB(19,BOFP
,CBGT
,16,0), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {CR
}},
4807 {"blelrl+", XLOCB(19,BOFP
,CBGT
,16,1), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {CR
}},
4808 {"bnglrl+", XLOCB(19,BOFP
,CBGT
,16,1), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {CR
}},
4809 {"bnelr+", XLOCB(19,BOFP
,CBEQ
,16,0), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {CR
}},
4810 {"bnelrl+", XLOCB(19,BOFP
,CBEQ
,16,1), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {CR
}},
4811 {"bnslr+", XLOCB(19,BOFP
,CBSO
,16,0), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {CR
}},
4812 {"bnulr+", XLOCB(19,BOFP
,CBSO
,16,0), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {CR
}},
4813 {"bnslrl+", XLOCB(19,BOFP
,CBSO
,16,1), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {CR
}},
4814 {"bnulrl+", XLOCB(19,BOFP
,CBSO
,16,1), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {CR
}},
4815 {"bgelr-", XLOCB(19,BOFM4
,CBLT
,16,0), XLBOCBBB_MASK
, ISA_V2
, PPCVLE
, {CR
}},
4816 {"bnllr-", XLOCB(19,BOFM4
,CBLT
,16,0), XLBOCBBB_MASK
, ISA_V2
, PPCVLE
, {CR
}},
4817 {"bgelrl-", XLOCB(19,BOFM4
,CBLT
,16,1), XLBOCBBB_MASK
, ISA_V2
, PPCVLE
, {CR
}},
4818 {"bnllrl-", XLOCB(19,BOFM4
,CBLT
,16,1), XLBOCBBB_MASK
, ISA_V2
, PPCVLE
, {CR
}},
4819 {"blelr-", XLOCB(19,BOFM4
,CBGT
,16,0), XLBOCBBB_MASK
, ISA_V2
, PPCVLE
, {CR
}},
4820 {"bnglr-", XLOCB(19,BOFM4
,CBGT
,16,0), XLBOCBBB_MASK
, ISA_V2
, PPCVLE
, {CR
}},
4821 {"blelrl-", XLOCB(19,BOFM4
,CBGT
,16,1), XLBOCBBB_MASK
, ISA_V2
, PPCVLE
, {CR
}},
4822 {"bnglrl-", XLOCB(19,BOFM4
,CBGT
,16,1), XLBOCBBB_MASK
, ISA_V2
, PPCVLE
, {CR
}},
4823 {"bnelr-", XLOCB(19,BOFM4
,CBEQ
,16,0), XLBOCBBB_MASK
, ISA_V2
, PPCVLE
, {CR
}},
4824 {"bnelrl-", XLOCB(19,BOFM4
,CBEQ
,16,1), XLBOCBBB_MASK
, ISA_V2
, PPCVLE
, {CR
}},
4825 {"bnslr-", XLOCB(19,BOFM4
,CBSO
,16,0), XLBOCBBB_MASK
, ISA_V2
, PPCVLE
, {CR
}},
4826 {"bnulr-", XLOCB(19,BOFM4
,CBSO
,16,0), XLBOCBBB_MASK
, ISA_V2
, PPCVLE
, {CR
}},
4827 {"bnslrl-", XLOCB(19,BOFM4
,CBSO
,16,1), XLBOCBBB_MASK
, ISA_V2
, PPCVLE
, {CR
}},
4828 {"bnulrl-", XLOCB(19,BOFM4
,CBSO
,16,1), XLBOCBBB_MASK
, ISA_V2
, PPCVLE
, {CR
}},
4829 {"bgelr+", XLOCB(19,BOFP4
,CBLT
,16,0), XLBOCBBB_MASK
, ISA_V2
, PPCVLE
, {CR
}},
4830 {"bnllr+", XLOCB(19,BOFP4
,CBLT
,16,0), XLBOCBBB_MASK
, ISA_V2
, PPCVLE
, {CR
}},
4831 {"bgelrl+", XLOCB(19,BOFP4
,CBLT
,16,1), XLBOCBBB_MASK
, ISA_V2
, PPCVLE
, {CR
}},
4832 {"bnllrl+", XLOCB(19,BOFP4
,CBLT
,16,1), XLBOCBBB_MASK
, ISA_V2
, PPCVLE
, {CR
}},
4833 {"blelr+", XLOCB(19,BOFP4
,CBGT
,16,0), XLBOCBBB_MASK
, ISA_V2
, PPCVLE
, {CR
}},
4834 {"bnglr+", XLOCB(19,BOFP4
,CBGT
,16,0), XLBOCBBB_MASK
, ISA_V2
, PPCVLE
, {CR
}},
4835 {"blelrl+", XLOCB(19,BOFP4
,CBGT
,16,1), XLBOCBBB_MASK
, ISA_V2
, PPCVLE
, {CR
}},
4836 {"bnglrl+", XLOCB(19,BOFP4
,CBGT
,16,1), XLBOCBBB_MASK
, ISA_V2
, PPCVLE
, {CR
}},
4837 {"bnelr+", XLOCB(19,BOFP4
,CBEQ
,16,0), XLBOCBBB_MASK
, ISA_V2
, PPCVLE
, {CR
}},
4838 {"bnelrl+", XLOCB(19,BOFP4
,CBEQ
,16,1), XLBOCBBB_MASK
, ISA_V2
, PPCVLE
, {CR
}},
4839 {"bnslr+", XLOCB(19,BOFP4
,CBSO
,16,0), XLBOCBBB_MASK
, ISA_V2
, PPCVLE
, {CR
}},
4840 {"bnulr+", XLOCB(19,BOFP4
,CBSO
,16,0), XLBOCBBB_MASK
, ISA_V2
, PPCVLE
, {CR
}},
4841 {"bnslrl+", XLOCB(19,BOFP4
,CBSO
,16,1), XLBOCBBB_MASK
, ISA_V2
, PPCVLE
, {CR
}},
4842 {"bnulrl+", XLOCB(19,BOFP4
,CBSO
,16,1), XLBOCBBB_MASK
, ISA_V2
, PPCVLE
, {CR
}},
4843 {"bltlr", XLOCB(19,BOT
,CBLT
,16,0), XLBOCBBB_MASK
, PPCCOM
, PPCVLE
, {CR
}},
4844 {"bltlr-", XLOCB(19,BOT
,CBLT
,16,0), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {CR
}},
4845 {"bltr", XLOCB(19,BOT
,CBLT
,16,0), XLBOCBBB_MASK
, PWRCOM
, PPCVLE
, {CR
}},
4846 {"bltlrl", XLOCB(19,BOT
,CBLT
,16,1), XLBOCBBB_MASK
, PPCCOM
, PPCVLE
, {CR
}},
4847 {"bltlrl-", XLOCB(19,BOT
,CBLT
,16,1), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {CR
}},
4848 {"bltrl", XLOCB(19,BOT
,CBLT
,16,1), XLBOCBBB_MASK
, PWRCOM
, PPCVLE
, {CR
}},
4849 {"bgtlr", XLOCB(19,BOT
,CBGT
,16,0), XLBOCBBB_MASK
, PPCCOM
, PPCVLE
, {CR
}},
4850 {"bgtlr-", XLOCB(19,BOT
,CBGT
,16,0), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {CR
}},
4851 {"bgtr", XLOCB(19,BOT
,CBGT
,16,0), XLBOCBBB_MASK
, PWRCOM
, PPCVLE
, {CR
}},
4852 {"bgtlrl", XLOCB(19,BOT
,CBGT
,16,1), XLBOCBBB_MASK
, PPCCOM
, PPCVLE
, {CR
}},
4853 {"bgtlrl-", XLOCB(19,BOT
,CBGT
,16,1), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {CR
}},
4854 {"bgtrl", XLOCB(19,BOT
,CBGT
,16,1), XLBOCBBB_MASK
, PWRCOM
, PPCVLE
, {CR
}},
4855 {"beqlr", XLOCB(19,BOT
,CBEQ
,16,0), XLBOCBBB_MASK
, PPCCOM
, PPCVLE
, {CR
}},
4856 {"beqlr-", XLOCB(19,BOT
,CBEQ
,16,0), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {CR
}},
4857 {"beqr", XLOCB(19,BOT
,CBEQ
,16,0), XLBOCBBB_MASK
, PWRCOM
, PPCVLE
, {CR
}},
4858 {"beqlrl", XLOCB(19,BOT
,CBEQ
,16,1), XLBOCBBB_MASK
, PPCCOM
, PPCVLE
, {CR
}},
4859 {"beqlrl-", XLOCB(19,BOT
,CBEQ
,16,1), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {CR
}},
4860 {"beqrl", XLOCB(19,BOT
,CBEQ
,16,1), XLBOCBBB_MASK
, PWRCOM
, PPCVLE
, {CR
}},
4861 {"bsolr", XLOCB(19,BOT
,CBSO
,16,0), XLBOCBBB_MASK
, PPCCOM
, PPCVLE
, {CR
}},
4862 {"bsolr-", XLOCB(19,BOT
,CBSO
,16,0), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {CR
}},
4863 {"bsor", XLOCB(19,BOT
,CBSO
,16,0), XLBOCBBB_MASK
, PWRCOM
, PPCVLE
, {CR
}},
4864 {"bunlr", XLOCB(19,BOT
,CBSO
,16,0), XLBOCBBB_MASK
, PPCCOM
, PPCVLE
, {CR
}},
4865 {"bunlr-", XLOCB(19,BOT
,CBSO
,16,0), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {CR
}},
4866 {"bsolrl", XLOCB(19,BOT
,CBSO
,16,1), XLBOCBBB_MASK
, PPCCOM
, PPCVLE
, {CR
}},
4867 {"bsolrl-", XLOCB(19,BOT
,CBSO
,16,1), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {CR
}},
4868 {"bsorl", XLOCB(19,BOT
,CBSO
,16,1), XLBOCBBB_MASK
, PWRCOM
, PPCVLE
, {CR
}},
4869 {"bunlrl", XLOCB(19,BOT
,CBSO
,16,1), XLBOCBBB_MASK
, PPCCOM
, PPCVLE
, {CR
}},
4870 {"bunlrl-", XLOCB(19,BOT
,CBSO
,16,1), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {CR
}},
4871 {"bltlr+", XLOCB(19,BOTP
,CBLT
,16,0), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {CR
}},
4872 {"bltlrl+", XLOCB(19,BOTP
,CBLT
,16,1), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {CR
}},
4873 {"bgtlr+", XLOCB(19,BOTP
,CBGT
,16,0), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {CR
}},
4874 {"bgtlrl+", XLOCB(19,BOTP
,CBGT
,16,1), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {CR
}},
4875 {"beqlr+", XLOCB(19,BOTP
,CBEQ
,16,0), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {CR
}},
4876 {"beqlrl+", XLOCB(19,BOTP
,CBEQ
,16,1), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {CR
}},
4877 {"bsolr+", XLOCB(19,BOTP
,CBSO
,16,0), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {CR
}},
4878 {"bunlr+", XLOCB(19,BOTP
,CBSO
,16,0), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {CR
}},
4879 {"bsolrl+", XLOCB(19,BOTP
,CBSO
,16,1), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {CR
}},
4880 {"bunlrl+", XLOCB(19,BOTP
,CBSO
,16,1), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {CR
}},
4881 {"bltlr-", XLOCB(19,BOTM4
,CBLT
,16,0), XLBOCBBB_MASK
, ISA_V2
, PPCVLE
, {CR
}},
4882 {"bltlrl-", XLOCB(19,BOTM4
,CBLT
,16,1), XLBOCBBB_MASK
, ISA_V2
, PPCVLE
, {CR
}},
4883 {"bgtlr-", XLOCB(19,BOTM4
,CBGT
,16,0), XLBOCBBB_MASK
, ISA_V2
, PPCVLE
, {CR
}},
4884 {"bgtlrl-", XLOCB(19,BOTM4
,CBGT
,16,1), XLBOCBBB_MASK
, ISA_V2
, PPCVLE
, {CR
}},
4885 {"beqlr-", XLOCB(19,BOTM4
,CBEQ
,16,0), XLBOCBBB_MASK
, ISA_V2
, PPCVLE
, {CR
}},
4886 {"beqlrl-", XLOCB(19,BOTM4
,CBEQ
,16,1), XLBOCBBB_MASK
, ISA_V2
, PPCVLE
, {CR
}},
4887 {"bsolr-", XLOCB(19,BOTM4
,CBSO
,16,0), XLBOCBBB_MASK
, ISA_V2
, PPCVLE
, {CR
}},
4888 {"bunlr-", XLOCB(19,BOTM4
,CBSO
,16,0), XLBOCBBB_MASK
, ISA_V2
, PPCVLE
, {CR
}},
4889 {"bsolrl-", XLOCB(19,BOTM4
,CBSO
,16,1), XLBOCBBB_MASK
, ISA_V2
, PPCVLE
, {CR
}},
4890 {"bunlrl-", XLOCB(19,BOTM4
,CBSO
,16,1), XLBOCBBB_MASK
, ISA_V2
, PPCVLE
, {CR
}},
4891 {"bltlr+", XLOCB(19,BOTP4
,CBLT
,16,0), XLBOCBBB_MASK
, ISA_V2
, PPCVLE
, {CR
}},
4892 {"bltlrl+", XLOCB(19,BOTP4
,CBLT
,16,1), XLBOCBBB_MASK
, ISA_V2
, PPCVLE
, {CR
}},
4893 {"bgtlr+", XLOCB(19,BOTP4
,CBGT
,16,0), XLBOCBBB_MASK
, ISA_V2
, PPCVLE
, {CR
}},
4894 {"bgtlrl+", XLOCB(19,BOTP4
,CBGT
,16,1), XLBOCBBB_MASK
, ISA_V2
, PPCVLE
, {CR
}},
4895 {"beqlr+", XLOCB(19,BOTP4
,CBEQ
,16,0), XLBOCBBB_MASK
, ISA_V2
, PPCVLE
, {CR
}},
4896 {"beqlrl+", XLOCB(19,BOTP4
,CBEQ
,16,1), XLBOCBBB_MASK
, ISA_V2
, PPCVLE
, {CR
}},
4897 {"bsolr+", XLOCB(19,BOTP4
,CBSO
,16,0), XLBOCBBB_MASK
, ISA_V2
, PPCVLE
, {CR
}},
4898 {"bunlr+", XLOCB(19,BOTP4
,CBSO
,16,0), XLBOCBBB_MASK
, ISA_V2
, PPCVLE
, {CR
}},
4899 {"bsolrl+", XLOCB(19,BOTP4
,CBSO
,16,1), XLBOCBBB_MASK
, ISA_V2
, PPCVLE
, {CR
}},
4900 {"bunlrl+", XLOCB(19,BOTP4
,CBSO
,16,1), XLBOCBBB_MASK
, ISA_V2
, PPCVLE
, {CR
}},
4902 {"bdnzflr", XLO(19,BODNZF
,16,0), XLBOBB_MASK
, PPCCOM
, PPCVLE
, {BI
}},
4903 {"bdnzflr-", XLO(19,BODNZF
,16,0), XLBOBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {BI
}},
4904 {"bdnzflrl", XLO(19,BODNZF
,16,1), XLBOBB_MASK
, PPCCOM
, PPCVLE
, {BI
}},
4905 {"bdnzflrl-",XLO(19,BODNZF
,16,1), XLBOBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {BI
}},
4906 {"bdnzflr+", XLO(19,BODNZFP
,16,0), XLBOBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {BI
}},
4907 {"bdnzflrl+",XLO(19,BODNZFP
,16,1), XLBOBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {BI
}},
4908 {"bdzflr", XLO(19,BODZF
,16,0), XLBOBB_MASK
, PPCCOM
, PPCVLE
, {BI
}},
4909 {"bdzflr-", XLO(19,BODZF
,16,0), XLBOBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {BI
}},
4910 {"bdzflrl", XLO(19,BODZF
,16,1), XLBOBB_MASK
, PPCCOM
, PPCVLE
, {BI
}},
4911 {"bdzflrl-", XLO(19,BODZF
,16,1), XLBOBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {BI
}},
4912 {"bdzflr+", XLO(19,BODZFP
,16,0), XLBOBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {BI
}},
4913 {"bdzflrl+", XLO(19,BODZFP
,16,1), XLBOBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {BI
}},
4914 {"bflr", XLO(19,BOF
,16,0), XLBOBB_MASK
, PPCCOM
, PPCVLE
, {BI
}},
4915 {"bflr-", XLO(19,BOF
,16,0), XLBOBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {BI
}},
4916 {"bbfr", XLO(19,BOF
,16,0), XLBOBB_MASK
, PWRCOM
, PPCVLE
, {BI
}},
4917 {"bflrl", XLO(19,BOF
,16,1), XLBOBB_MASK
, PPCCOM
, PPCVLE
, {BI
}},
4918 {"bflrl-", XLO(19,BOF
,16,1), XLBOBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {BI
}},
4919 {"bbfrl", XLO(19,BOF
,16,1), XLBOBB_MASK
, PWRCOM
, PPCVLE
, {BI
}},
4920 {"bflr+", XLO(19,BOFP
,16,0), XLBOBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {BI
}},
4921 {"bflrl+", XLO(19,BOFP
,16,1), XLBOBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {BI
}},
4922 {"bflr-", XLO(19,BOFM4
,16,0), XLBOBB_MASK
, ISA_V2
, PPCVLE
, {BI
}},
4923 {"bflrl-", XLO(19,BOFM4
,16,1), XLBOBB_MASK
, ISA_V2
, PPCVLE
, {BI
}},
4924 {"bflr+", XLO(19,BOFP4
,16,0), XLBOBB_MASK
, ISA_V2
, PPCVLE
, {BI
}},
4925 {"bflrl+", XLO(19,BOFP4
,16,1), XLBOBB_MASK
, ISA_V2
, PPCVLE
, {BI
}},
4926 {"bdnztlr", XLO(19,BODNZT
,16,0), XLBOBB_MASK
, PPCCOM
, PPCVLE
, {BI
}},
4927 {"bdnztlr-", XLO(19,BODNZT
,16,0), XLBOBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {BI
}},
4928 {"bdnztlrl", XLO(19,BODNZT
,16,1), XLBOBB_MASK
, PPCCOM
, PPCVLE
, {BI
}},
4929 {"bdnztlrl-", XLO(19,BODNZT
,16,1), XLBOBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {BI
}},
4930 {"bdnztlr+", XLO(19,BODNZTP
,16,0), XLBOBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {BI
}},
4931 {"bdnztlrl+", XLO(19,BODNZTP
,16,1), XLBOBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {BI
}},
4932 {"bdztlr", XLO(19,BODZT
,16,0), XLBOBB_MASK
, PPCCOM
, PPCVLE
, {BI
}},
4933 {"bdztlr-", XLO(19,BODZT
,16,0), XLBOBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {BI
}},
4934 {"bdztlrl", XLO(19,BODZT
,16,1), XLBOBB_MASK
, PPCCOM
, PPCVLE
, {BI
}},
4935 {"bdztlrl-", XLO(19,BODZT
,16,1), XLBOBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {BI
}},
4936 {"bdztlr+", XLO(19,BODZTP
,16,0), XLBOBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {BI
}},
4937 {"bdztlrl+", XLO(19,BODZTP
,16,1), XLBOBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {BI
}},
4938 {"btlr", XLO(19,BOT
,16,0), XLBOBB_MASK
, PPCCOM
, PPCVLE
, {BI
}},
4939 {"btlr-", XLO(19,BOT
,16,0), XLBOBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {BI
}},
4940 {"bbtr", XLO(19,BOT
,16,0), XLBOBB_MASK
, PWRCOM
, PPCVLE
, {BI
}},
4941 {"btlrl", XLO(19,BOT
,16,1), XLBOBB_MASK
, PPCCOM
, PPCVLE
, {BI
}},
4942 {"btlrl-", XLO(19,BOT
,16,1), XLBOBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {BI
}},
4943 {"bbtrl", XLO(19,BOT
,16,1), XLBOBB_MASK
, PWRCOM
, PPCVLE
, {BI
}},
4944 {"btlr+", XLO(19,BOTP
,16,0), XLBOBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {BI
}},
4945 {"btlrl+", XLO(19,BOTP
,16,1), XLBOBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {BI
}},
4946 {"btlr-", XLO(19,BOTM4
,16,0), XLBOBB_MASK
, ISA_V2
, PPCVLE
, {BI
}},
4947 {"btlrl-", XLO(19,BOTM4
,16,1), XLBOBB_MASK
, ISA_V2
, PPCVLE
, {BI
}},
4948 {"btlr+", XLO(19,BOTP4
,16,0), XLBOBB_MASK
, ISA_V2
, PPCVLE
, {BI
}},
4949 {"btlrl+", XLO(19,BOTP4
,16,1), XLBOBB_MASK
, ISA_V2
, PPCVLE
, {BI
}},
4951 {"bclr-", XLYLK(19,16,0,0), XLYBB_MASK
, PPCCOM
, PPCVLE
, {BOE
, BI
}},
4952 {"bclrl-", XLYLK(19,16,0,1), XLYBB_MASK
, PPCCOM
, PPCVLE
, {BOE
, BI
}},
4953 {"bclr+", XLYLK(19,16,1,0), XLYBB_MASK
, PPCCOM
, PPCVLE
, {BOE
, BI
}},
4954 {"bclrl+", XLYLK(19,16,1,1), XLYBB_MASK
, PPCCOM
, PPCVLE
, {BOE
, BI
}},
4955 {"bclr", XLLK(19,16,0), XLBH_MASK
, PPCCOM
, PPCVLE
, {BO
, BI
, BH
}},
4956 {"bcr", XLLK(19,16,0), XLBB_MASK
, PWRCOM
, PPCVLE
, {BO
, BI
}},
4957 {"bclrl", XLLK(19,16,1), XLBH_MASK
, PPCCOM
, PPCVLE
, {BO
, BI
, BH
}},
4958 {"bcrl", XLLK(19,16,1), XLBB_MASK
, PWRCOM
, PPCVLE
, {BO
, BI
}},
4960 {"rfid", XL(19,18), 0xffffffff, PPC64
, PPCVLE
, {0}},
4962 {"crnot", XL(19,33), XL_MASK
, PPCCOM
, PPCVLE
, {BT
, BA
, BBA
}},
4963 {"crnor", XL(19,33), XL_MASK
, COM
, PPCVLE
, {BT
, BA
, BB
}},
4964 {"rfmci", X(19,38), 0xffffffff, PPCRFMCI
|PPCA2
|PPC476
, PPCVLE
, {0}},
4966 {"rfdi", XL(19,39), 0xffffffff, E500MC
, PPCVLE
, {0}},
4967 {"rfi", XL(19,50), 0xffffffff, COM
, PPCVLE
, {0}},
4968 {"rfci", XL(19,51), 0xffffffff, PPC403
|BOOKE
|PPCE300
|PPCA2
|PPC476
, PPCVLE
, {0}},
4970 {"rfscv", XL(19,82), 0xffffffff, POWER9
, PPCVLE
, {0}},
4971 {"rfsvc", XL(19,82), 0xffffffff, POWER
, PPCVLE
, {0}},
4973 {"rfgi", XL(19,102), 0xffffffff, E500MC
|PPCA2
, PPCVLE
, {0}},
4975 {"crandc", XL(19,129), XL_MASK
, COM
, PPCVLE
, {BT
, BA
, BB
}},
4977 {"rfebb", XL(19,146), XLS_MASK
, POWER8
, PPCVLE
, {SXL
}},
4979 {"isync", XL(19,150), 0xffffffff, PPCCOM
, PPCVLE
, {0}},
4980 {"ics", XL(19,150), 0xffffffff, PWRCOM
, PPCVLE
, {0}},
4982 {"crclr", XL(19,193), XL_MASK
, PPCCOM
, PPCVLE
, {BT
, BAT
, BBA
}},
4983 {"crxor", XL(19,193), XL_MASK
, COM
, PPCVLE
, {BT
, BA
, BB
}},
4985 {"dnh", X(19,198), X_MASK
, E500MC
, PPCVLE
, {DUI
, DUIS
}},
4987 {"crnand", XL(19,225), XL_MASK
, COM
, PPCVLE
, {BT
, BA
, BB
}},
4989 {"crand", XL(19,257), XL_MASK
, COM
, PPCVLE
, {BT
, BA
, BB
}},
4991 {"hrfid", XL(19,274), 0xffffffff, POWER5
|CELL
, PPC476
|PPCVLE
, {0}},
4993 {"crset", XL(19,289), XL_MASK
, PPCCOM
, PPCVLE
, {BT
, BAT
, BBA
}},
4994 {"creqv", XL(19,289), XL_MASK
, COM
, PPCVLE
, {BT
, BA
, BB
}},
4996 {"urfid", XL(19,306), 0xffffffff, POWER9
, PPCVLE
, {0}},
4997 {"stop", XL(19,370), 0xffffffff, POWER9
, PPCVLE
, {0}},
4999 {"doze", XL(19,402), 0xffffffff, POWER6
, POWER9
|PPCVLE
, {0}},
5001 {"crorc", XL(19,417), XL_MASK
, COM
, PPCVLE
, {BT
, BA
, BB
}},
5003 {"nap", XL(19,434), 0xffffffff, POWER6
, POWER9
|PPCVLE
, {0}},
5005 {"crmove", XL(19,449), XL_MASK
, PPCCOM
, PPCVLE
, {BT
, BA
, BBA
}},
5006 {"cror", XL(19,449), XL_MASK
, COM
, PPCVLE
, {BT
, BA
, BB
}},
5008 {"sleep", XL(19,466), 0xffffffff, POWER6
, POWER9
|PPCVLE
, {0}},
5009 {"rvwinkle", XL(19,498), 0xffffffff, POWER6
, POWER9
|PPCVLE
, {0}},
5011 {"bctr", XLO(19,BOU
,528,0), XLBOBIBB_MASK
, COM
, PPCVLE
, {0}},
5012 {"bctrl", XLO(19,BOU
,528,1), XLBOBIBB_MASK
, COM
, PPCVLE
, {0}},
5014 {"bgectr", XLOCB(19,BOF
,CBLT
,528,0), XLBOCBBB_MASK
, PPCCOM
, PPCVLE
, {CR
}},
5015 {"bgectr-", XLOCB(19,BOF
,CBLT
,528,0), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {CR
}},
5016 {"bnlctr", XLOCB(19,BOF
,CBLT
,528,0), XLBOCBBB_MASK
, PPCCOM
, PPCVLE
, {CR
}},
5017 {"bnlctr-", XLOCB(19,BOF
,CBLT
,528,0), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {CR
}},
5018 {"bgectrl", XLOCB(19,BOF
,CBLT
,528,1), XLBOCBBB_MASK
, PPCCOM
, PPCVLE
, {CR
}},
5019 {"bgectrl-",XLOCB(19,BOF
,CBLT
,528,1), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {CR
}},
5020 {"bnlctrl", XLOCB(19,BOF
,CBLT
,528,1), XLBOCBBB_MASK
, PPCCOM
, PPCVLE
, {CR
}},
5021 {"bnlctrl-",XLOCB(19,BOF
,CBLT
,528,1), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {CR
}},
5022 {"blectr", XLOCB(19,BOF
,CBGT
,528,0), XLBOCBBB_MASK
, PPCCOM
, PPCVLE
, {CR
}},
5023 {"blectr-", XLOCB(19,BOF
,CBGT
,528,0), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {CR
}},
5024 {"bngctr", XLOCB(19,BOF
,CBGT
,528,0), XLBOCBBB_MASK
, PPCCOM
, PPCVLE
, {CR
}},
5025 {"bngctr-", XLOCB(19,BOF
,CBGT
,528,0), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {CR
}},
5026 {"blectrl", XLOCB(19,BOF
,CBGT
,528,1), XLBOCBBB_MASK
, PPCCOM
, PPCVLE
, {CR
}},
5027 {"blectrl-",XLOCB(19,BOF
,CBGT
,528,1), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {CR
}},
5028 {"bngctrl", XLOCB(19,BOF
,CBGT
,528,1), XLBOCBBB_MASK
, PPCCOM
, PPCVLE
, {CR
}},
5029 {"bngctrl-",XLOCB(19,BOF
,CBGT
,528,1), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {CR
}},
5030 {"bnectr", XLOCB(19,BOF
,CBEQ
,528,0), XLBOCBBB_MASK
, PPCCOM
, PPCVLE
, {CR
}},
5031 {"bnectr-", XLOCB(19,BOF
,CBEQ
,528,0), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {CR
}},
5032 {"bnectrl", XLOCB(19,BOF
,CBEQ
,528,1), XLBOCBBB_MASK
, PPCCOM
, PPCVLE
, {CR
}},
5033 {"bnectrl-",XLOCB(19,BOF
,CBEQ
,528,1), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {CR
}},
5034 {"bnsctr", XLOCB(19,BOF
,CBSO
,528,0), XLBOCBBB_MASK
, PPCCOM
, PPCVLE
, {CR
}},
5035 {"bnsctr-", XLOCB(19,BOF
,CBSO
,528,0), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {CR
}},
5036 {"bnuctr", XLOCB(19,BOF
,CBSO
,528,0), XLBOCBBB_MASK
, PPCCOM
, PPCVLE
, {CR
}},
5037 {"bnuctr-", XLOCB(19,BOF
,CBSO
,528,0), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {CR
}},
5038 {"bnsctrl", XLOCB(19,BOF
,CBSO
,528,1), XLBOCBBB_MASK
, PPCCOM
, PPCVLE
, {CR
}},
5039 {"bnsctrl-",XLOCB(19,BOF
,CBSO
,528,1), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {CR
}},
5040 {"bnuctrl", XLOCB(19,BOF
,CBSO
,528,1), XLBOCBBB_MASK
, PPCCOM
, PPCVLE
, {CR
}},
5041 {"bnuctrl-",XLOCB(19,BOF
,CBSO
,528,1), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {CR
}},
5042 {"bgectr+", XLOCB(19,BOFP
,CBLT
,528,0), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {CR
}},
5043 {"bnlctr+", XLOCB(19,BOFP
,CBLT
,528,0), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {CR
}},
5044 {"bgectrl+",XLOCB(19,BOFP
,CBLT
,528,1), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {CR
}},
5045 {"bnlctrl+",XLOCB(19,BOFP
,CBLT
,528,1), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {CR
}},
5046 {"blectr+", XLOCB(19,BOFP
,CBGT
,528,0), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {CR
}},
5047 {"bngctr+", XLOCB(19,BOFP
,CBGT
,528,0), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {CR
}},
5048 {"blectrl+",XLOCB(19,BOFP
,CBGT
,528,1), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {CR
}},
5049 {"bngctrl+",XLOCB(19,BOFP
,CBGT
,528,1), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {CR
}},
5050 {"bnectr+", XLOCB(19,BOFP
,CBEQ
,528,0), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {CR
}},
5051 {"bnectrl+",XLOCB(19,BOFP
,CBEQ
,528,1), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {CR
}},
5052 {"bnsctr+", XLOCB(19,BOFP
,CBSO
,528,0), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {CR
}},
5053 {"bnuctr+", XLOCB(19,BOFP
,CBSO
,528,0), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {CR
}},
5054 {"bnsctrl+",XLOCB(19,BOFP
,CBSO
,528,1), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {CR
}},
5055 {"bnuctrl+",XLOCB(19,BOFP
,CBSO
,528,1), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {CR
}},
5056 {"bgectr-", XLOCB(19,BOFM4
,CBLT
,528,0), XLBOCBBB_MASK
, ISA_V2
, PPCVLE
, {CR
}},
5057 {"bnlctr-", XLOCB(19,BOFM4
,CBLT
,528,0), XLBOCBBB_MASK
, ISA_V2
, PPCVLE
, {CR
}},
5058 {"bgectrl-",XLOCB(19,BOFM4
,CBLT
,528,1), XLBOCBBB_MASK
, ISA_V2
, PPCVLE
, {CR
}},
5059 {"bnlctrl-",XLOCB(19,BOFM4
,CBLT
,528,1), XLBOCBBB_MASK
, ISA_V2
, PPCVLE
, {CR
}},
5060 {"blectr-", XLOCB(19,BOFM4
,CBGT
,528,0), XLBOCBBB_MASK
, ISA_V2
, PPCVLE
, {CR
}},
5061 {"bngctr-", XLOCB(19,BOFM4
,CBGT
,528,0), XLBOCBBB_MASK
, ISA_V2
, PPCVLE
, {CR
}},
5062 {"blectrl-",XLOCB(19,BOFM4
,CBGT
,528,1), XLBOCBBB_MASK
, ISA_V2
, PPCVLE
, {CR
}},
5063 {"bngctrl-",XLOCB(19,BOFM4
,CBGT
,528,1), XLBOCBBB_MASK
, ISA_V2
, PPCVLE
, {CR
}},
5064 {"bnectr-", XLOCB(19,BOFM4
,CBEQ
,528,0), XLBOCBBB_MASK
, ISA_V2
, PPCVLE
, {CR
}},
5065 {"bnectrl-",XLOCB(19,BOFM4
,CBEQ
,528,1), XLBOCBBB_MASK
, ISA_V2
, PPCVLE
, {CR
}},
5066 {"bnsctr-", XLOCB(19,BOFM4
,CBSO
,528,0), XLBOCBBB_MASK
, ISA_V2
, PPCVLE
, {CR
}},
5067 {"bnuctr-", XLOCB(19,BOFM4
,CBSO
,528,0), XLBOCBBB_MASK
, ISA_V2
, PPCVLE
, {CR
}},
5068 {"bnsctrl-",XLOCB(19,BOFM4
,CBSO
,528,1), XLBOCBBB_MASK
, ISA_V2
, PPCVLE
, {CR
}},
5069 {"bnuctrl-",XLOCB(19,BOFM4
,CBSO
,528,1), XLBOCBBB_MASK
, ISA_V2
, PPCVLE
, {CR
}},
5070 {"bgectr+", XLOCB(19,BOFP4
,CBLT
,528,0), XLBOCBBB_MASK
, ISA_V2
, PPCVLE
, {CR
}},
5071 {"bnlctr+", XLOCB(19,BOFP4
,CBLT
,528,0), XLBOCBBB_MASK
, ISA_V2
, PPCVLE
, {CR
}},
5072 {"bgectrl+",XLOCB(19,BOFP4
,CBLT
,528,1), XLBOCBBB_MASK
, ISA_V2
, PPCVLE
, {CR
}},
5073 {"bnlctrl+",XLOCB(19,BOFP4
,CBLT
,528,1), XLBOCBBB_MASK
, ISA_V2
, PPCVLE
, {CR
}},
5074 {"blectr+", XLOCB(19,BOFP4
,CBGT
,528,0), XLBOCBBB_MASK
, ISA_V2
, PPCVLE
, {CR
}},
5075 {"bngctr+", XLOCB(19,BOFP4
,CBGT
,528,0), XLBOCBBB_MASK
, ISA_V2
, PPCVLE
, {CR
}},
5076 {"blectrl+",XLOCB(19,BOFP4
,CBGT
,528,1), XLBOCBBB_MASK
, ISA_V2
, PPCVLE
, {CR
}},
5077 {"bngctrl+",XLOCB(19,BOFP4
,CBGT
,528,1), XLBOCBBB_MASK
, ISA_V2
, PPCVLE
, {CR
}},
5078 {"bnectr+", XLOCB(19,BOFP4
,CBEQ
,528,0), XLBOCBBB_MASK
, ISA_V2
, PPCVLE
, {CR
}},
5079 {"bnectrl+",XLOCB(19,BOFP4
,CBEQ
,528,1), XLBOCBBB_MASK
, ISA_V2
, PPCVLE
, {CR
}},
5080 {"bnsctr+", XLOCB(19,BOFP4
,CBSO
,528,0), XLBOCBBB_MASK
, ISA_V2
, PPCVLE
, {CR
}},
5081 {"bnuctr+", XLOCB(19,BOFP4
,CBSO
,528,0), XLBOCBBB_MASK
, ISA_V2
, PPCVLE
, {CR
}},
5082 {"bnsctrl+",XLOCB(19,BOFP4
,CBSO
,528,1), XLBOCBBB_MASK
, ISA_V2
, PPCVLE
, {CR
}},
5083 {"bnuctrl+",XLOCB(19,BOFP4
,CBSO
,528,1), XLBOCBBB_MASK
, ISA_V2
, PPCVLE
, {CR
}},
5084 {"bltctr", XLOCB(19,BOT
,CBLT
,528,0), XLBOCBBB_MASK
, PPCCOM
, PPCVLE
, {CR
}},
5085 {"bltctr-", XLOCB(19,BOT
,CBLT
,528,0), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {CR
}},
5086 {"bltctrl", XLOCB(19,BOT
,CBLT
,528,1), XLBOCBBB_MASK
, PPCCOM
, PPCVLE
, {CR
}},
5087 {"bltctrl-",XLOCB(19,BOT
,CBLT
,528,1), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {CR
}},
5088 {"bgtctr", XLOCB(19,BOT
,CBGT
,528,0), XLBOCBBB_MASK
, PPCCOM
, PPCVLE
, {CR
}},
5089 {"bgtctr-", XLOCB(19,BOT
,CBGT
,528,0), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {CR
}},
5090 {"bgtctrl", XLOCB(19,BOT
,CBGT
,528,1), XLBOCBBB_MASK
, PPCCOM
, PPCVLE
, {CR
}},
5091 {"bgtctrl-",XLOCB(19,BOT
,CBGT
,528,1), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {CR
}},
5092 {"beqctr", XLOCB(19,BOT
,CBEQ
,528,0), XLBOCBBB_MASK
, PPCCOM
, PPCVLE
, {CR
}},
5093 {"beqctr-", XLOCB(19,BOT
,CBEQ
,528,0), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {CR
}},
5094 {"beqctrl", XLOCB(19,BOT
,CBEQ
,528,1), XLBOCBBB_MASK
, PPCCOM
, PPCVLE
, {CR
}},
5095 {"beqctrl-",XLOCB(19,BOT
,CBEQ
,528,1), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {CR
}},
5096 {"bsoctr", XLOCB(19,BOT
,CBSO
,528,0), XLBOCBBB_MASK
, PPCCOM
, PPCVLE
, {CR
}},
5097 {"bsoctr-", XLOCB(19,BOT
,CBSO
,528,0), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {CR
}},
5098 {"bunctr", XLOCB(19,BOT
,CBSO
,528,0), XLBOCBBB_MASK
, PPCCOM
, PPCVLE
, {CR
}},
5099 {"bunctr-", XLOCB(19,BOT
,CBSO
,528,0), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {CR
}},
5100 {"bsoctrl", XLOCB(19,BOT
,CBSO
,528,1), XLBOCBBB_MASK
, PPCCOM
, PPCVLE
, {CR
}},
5101 {"bsoctrl-",XLOCB(19,BOT
,CBSO
,528,1), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {CR
}},
5102 {"bunctrl", XLOCB(19,BOT
,CBSO
,528,1), XLBOCBBB_MASK
, PPCCOM
, PPCVLE
, {CR
}},
5103 {"bunctrl-",XLOCB(19,BOT
,CBSO
,528,1), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {CR
}},
5104 {"bltctr+", XLOCB(19,BOTP
,CBLT
,528,0), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {CR
}},
5105 {"bltctrl+",XLOCB(19,BOTP
,CBLT
,528,1), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {CR
}},
5106 {"bgtctr+", XLOCB(19,BOTP
,CBGT
,528,0), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {CR
}},
5107 {"bgtctrl+",XLOCB(19,BOTP
,CBGT
,528,1), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {CR
}},
5108 {"beqctr+", XLOCB(19,BOTP
,CBEQ
,528,0), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {CR
}},
5109 {"beqctrl+",XLOCB(19,BOTP
,CBEQ
,528,1), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {CR
}},
5110 {"bsoctr+", XLOCB(19,BOTP
,CBSO
,528,0), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {CR
}},
5111 {"bunctr+", XLOCB(19,BOTP
,CBSO
,528,0), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {CR
}},
5112 {"bsoctrl+",XLOCB(19,BOTP
,CBSO
,528,1), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {CR
}},
5113 {"bunctrl+",XLOCB(19,BOTP
,CBSO
,528,1), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {CR
}},
5114 {"bltctr-", XLOCB(19,BOTM4
,CBLT
,528,0), XLBOCBBB_MASK
, ISA_V2
, PPCVLE
, {CR
}},
5115 {"bltctrl-",XLOCB(19,BOTM4
,CBLT
,528,1), XLBOCBBB_MASK
, ISA_V2
, PPCVLE
, {CR
}},
5116 {"bgtctr-", XLOCB(19,BOTM4
,CBGT
,528,0), XLBOCBBB_MASK
, ISA_V2
, PPCVLE
, {CR
}},
5117 {"bgtctrl-",XLOCB(19,BOTM4
,CBGT
,528,1), XLBOCBBB_MASK
, ISA_V2
, PPCVLE
, {CR
}},
5118 {"beqctr-", XLOCB(19,BOTM4
,CBEQ
,528,0), XLBOCBBB_MASK
, ISA_V2
, PPCVLE
, {CR
}},
5119 {"beqctrl-",XLOCB(19,BOTM4
,CBEQ
,528,1), XLBOCBBB_MASK
, ISA_V2
, PPCVLE
, {CR
}},
5120 {"bsoctr-", XLOCB(19,BOTM4
,CBSO
,528,0), XLBOCBBB_MASK
, ISA_V2
, PPCVLE
, {CR
}},
5121 {"bunctr-", XLOCB(19,BOTM4
,CBSO
,528,0), XLBOCBBB_MASK
, ISA_V2
, PPCVLE
, {CR
}},
5122 {"bsoctrl-",XLOCB(19,BOTM4
,CBSO
,528,1), XLBOCBBB_MASK
, ISA_V2
, PPCVLE
, {CR
}},
5123 {"bunctrl-",XLOCB(19,BOTM4
,CBSO
,528,1), XLBOCBBB_MASK
, ISA_V2
, PPCVLE
, {CR
}},
5124 {"bltctr+", XLOCB(19,BOTP4
,CBLT
,528,0), XLBOCBBB_MASK
, ISA_V2
, PPCVLE
, {CR
}},
5125 {"bltctrl+",XLOCB(19,BOTP4
,CBLT
,528,1), XLBOCBBB_MASK
, ISA_V2
, PPCVLE
, {CR
}},
5126 {"bgtctr+", XLOCB(19,BOTP4
,CBGT
,528,0), XLBOCBBB_MASK
, ISA_V2
, PPCVLE
, {CR
}},
5127 {"bgtctrl+",XLOCB(19,BOTP4
,CBGT
,528,1), XLBOCBBB_MASK
, ISA_V2
, PPCVLE
, {CR
}},
5128 {"beqctr+", XLOCB(19,BOTP4
,CBEQ
,528,0), XLBOCBBB_MASK
, ISA_V2
, PPCVLE
, {CR
}},
5129 {"beqctrl+",XLOCB(19,BOTP4
,CBEQ
,528,1), XLBOCBBB_MASK
, ISA_V2
, PPCVLE
, {CR
}},
5130 {"bsoctr+", XLOCB(19,BOTP4
,CBSO
,528,0), XLBOCBBB_MASK
, ISA_V2
, PPCVLE
, {CR
}},
5131 {"bunctr+", XLOCB(19,BOTP4
,CBSO
,528,0), XLBOCBBB_MASK
, ISA_V2
, PPCVLE
, {CR
}},
5132 {"bsoctrl+",XLOCB(19,BOTP4
,CBSO
,528,1), XLBOCBBB_MASK
, ISA_V2
, PPCVLE
, {CR
}},
5133 {"bunctrl+",XLOCB(19,BOTP4
,CBSO
,528,1), XLBOCBBB_MASK
, ISA_V2
, PPCVLE
, {CR
}},
5135 {"bfctr", XLO(19,BOF
,528,0), XLBOBB_MASK
, PPCCOM
, PPCVLE
, {BI
}},
5136 {"bfctr-", XLO(19,BOF
,528,0), XLBOBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {BI
}},
5137 {"bfctrl", XLO(19,BOF
,528,1), XLBOBB_MASK
, PPCCOM
, PPCVLE
, {BI
}},
5138 {"bfctrl-", XLO(19,BOF
,528,1), XLBOBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {BI
}},
5139 {"bfctr+", XLO(19,BOFP
,528,0), XLBOBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {BI
}},
5140 {"bfctrl+", XLO(19,BOFP
,528,1), XLBOBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {BI
}},
5141 {"bfctr-", XLO(19,BOFM4
,528,0), XLBOBB_MASK
, ISA_V2
, PPCVLE
, {BI
}},
5142 {"bfctrl-", XLO(19,BOFM4
,528,1), XLBOBB_MASK
, ISA_V2
, PPCVLE
, {BI
}},
5143 {"bfctr+", XLO(19,BOFP4
,528,0), XLBOBB_MASK
, ISA_V2
, PPCVLE
, {BI
}},
5144 {"bfctrl+", XLO(19,BOFP4
,528,1), XLBOBB_MASK
, ISA_V2
, PPCVLE
, {BI
}},
5145 {"btctr", XLO(19,BOT
,528,0), XLBOBB_MASK
, PPCCOM
, PPCVLE
, {BI
}},
5146 {"btctr-", XLO(19,BOT
,528,0), XLBOBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {BI
}},
5147 {"btctrl", XLO(19,BOT
,528,1), XLBOBB_MASK
, PPCCOM
, PPCVLE
, {BI
}},
5148 {"btctrl-", XLO(19,BOT
,528,1), XLBOBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {BI
}},
5149 {"btctr+", XLO(19,BOTP
,528,0), XLBOBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {BI
}},
5150 {"btctrl+", XLO(19,BOTP
,528,1), XLBOBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
, {BI
}},
5151 {"btctr-", XLO(19,BOTM4
,528,0), XLBOBB_MASK
, ISA_V2
, PPCVLE
, {BI
}},
5152 {"btctrl-", XLO(19,BOTM4
,528,1), XLBOBB_MASK
, ISA_V2
, PPCVLE
, {BI
}},
5153 {"btctr+", XLO(19,BOTP4
,528,0), XLBOBB_MASK
, ISA_V2
, PPCVLE
, {BI
}},
5154 {"btctrl+", XLO(19,BOTP4
,528,1), XLBOBB_MASK
, ISA_V2
, PPCVLE
, {BI
}},
5156 {"bcctr-", XLYLK(19,528,0,0), XLYBB_MASK
, PPCCOM
, PPCVLE
, {BOE
, BI
}},
5157 {"bcctrl-", XLYLK(19,528,0,1), XLYBB_MASK
, PPCCOM
, PPCVLE
, {BOE
, BI
}},
5158 {"bcctr+", XLYLK(19,528,1,0), XLYBB_MASK
, PPCCOM
, PPCVLE
, {BOE
, BI
}},
5159 {"bcctrl+", XLYLK(19,528,1,1), XLYBB_MASK
, PPCCOM
, PPCVLE
, {BOE
, BI
}},
5160 {"bcctr", XLLK(19,528,0), XLBH_MASK
, PPCCOM
, PPCVLE
, {BO
, BI
, BH
}},
5161 {"bcc", XLLK(19,528,0), XLBB_MASK
, PWRCOM
, PPCVLE
, {BO
, BI
}},
5162 {"bcctrl", XLLK(19,528,1), XLBH_MASK
, PPCCOM
, PPCVLE
, {BO
, BI
, BH
}},
5163 {"bccl", XLLK(19,528,1), XLBB_MASK
, PWRCOM
, PPCVLE
, {BO
, BI
}},
5165 {"bctar-", XLYLK(19,560,0,0), XLYBB_MASK
, POWER8
, PPCVLE
, {BOE
, BI
}},
5166 {"bctarl-", XLYLK(19,560,0,1), XLYBB_MASK
, POWER8
, PPCVLE
, {BOE
, BI
}},
5167 {"bctar+", XLYLK(19,560,1,0), XLYBB_MASK
, POWER8
, PPCVLE
, {BOE
, BI
}},
5168 {"bctarl+", XLYLK(19,560,1,1), XLYBB_MASK
, POWER8
, PPCVLE
, {BOE
, BI
}},
5169 {"bctar", XLLK(19,560,0), XLBH_MASK
, POWER8
, PPCVLE
, {BO
, BI
, BH
}},
5170 {"bctarl", XLLK(19,560,1), XLBH_MASK
, POWER8
, PPCVLE
, {BO
, BI
, BH
}},
5172 {"rlwimi", M(20,0), M_MASK
, PPCCOM
, PPCVLE
, {RA
, RS
, SH
, MBE
, ME
}},
5173 {"rlimi", M(20,0), M_MASK
, PWRCOM
, PPCVLE
, {RA
, RS
, SH
, MBE
, ME
}},
5175 {"rlwimi.", M(20,1), M_MASK
, PPCCOM
, PPCVLE
, {RA
, RS
, SH
, MBE
, ME
}},
5176 {"rlimi.", M(20,1), M_MASK
, PWRCOM
, PPCVLE
, {RA
, RS
, SH
, MBE
, ME
}},
5178 {"rotlwi", MME(21,31,0), MMBME_MASK
, PPCCOM
, PPCVLE
, {RA
, RS
, SH
}},
5179 {"clrlwi", MME(21,31,0), MSHME_MASK
, PPCCOM
, PPCVLE
, {RA
, RS
, MB
}},
5180 {"rlwinm", M(21,0), M_MASK
, PPCCOM
, PPCVLE
, {RA
, RS
, SH
, MBE
, ME
}},
5181 {"rlinm", M(21,0), M_MASK
, PWRCOM
, PPCVLE
, {RA
, RS
, SH
, MBE
, ME
}},
5182 {"rotlwi.", MME(21,31,1), MMBME_MASK
, PPCCOM
, PPCVLE
, {RA
, RS
, SH
}},
5183 {"clrlwi.", MME(21,31,1), MSHME_MASK
, PPCCOM
, PPCVLE
, {RA
, RS
, MB
}},
5184 {"rlwinm.", M(21,1), M_MASK
, PPCCOM
, PPCVLE
, {RA
, RS
, SH
, MBE
, ME
}},
5185 {"rlinm.", M(21,1), M_MASK
, PWRCOM
, PPCVLE
, {RA
, RS
, SH
, MBE
, ME
}},
5187 {"rlmi", M(22,0), M_MASK
, M601
, PPCVLE
, {RA
, RS
, RB
, MBE
, ME
}},
5188 {"rlmi.", M(22,1), M_MASK
, M601
, PPCVLE
, {RA
, RS
, RB
, MBE
, ME
}},
5190 {"rotlw", MME(23,31,0), MMBME_MASK
, PPCCOM
, PPCVLE
, {RA
, RS
, RB
}},
5191 {"rlwnm", M(23,0), M_MASK
, PPCCOM
, PPCVLE
, {RA
, RS
, RB
, MBE
, ME
}},
5192 {"rlnm", M(23,0), M_MASK
, PWRCOM
, PPCVLE
, {RA
, RS
, RB
, MBE
, ME
}},
5193 {"rotlw.", MME(23,31,1), MMBME_MASK
, PPCCOM
, PPCVLE
, {RA
, RS
, RB
}},
5194 {"rlwnm.", M(23,1), M_MASK
, PPCCOM
, PPCVLE
, {RA
, RS
, RB
, MBE
, ME
}},
5195 {"rlnm.", M(23,1), M_MASK
, PWRCOM
, PPCVLE
, {RA
, RS
, RB
, MBE
, ME
}},
5197 {"nop", OP(24), 0xffffffff, PPCCOM
, PPCVLE
, {0}},
5198 {"ori", OP(24), OP_MASK
, PPCCOM
, PPCVLE
, {RA
, RS
, UI
}},
5199 {"oril", OP(24), OP_MASK
, PWRCOM
, PPCVLE
, {RA
, RS
, UI
}},
5201 {"oris", OP(25), OP_MASK
, PPCCOM
, PPCVLE
, {RA
, RS
, UI
}},
5202 {"oriu", OP(25), OP_MASK
, PWRCOM
, PPCVLE
, {RA
, RS
, UI
}},
5204 {"xnop", OP(26), 0xffffffff, PPCCOM
, PPCVLE
, {0}},
5205 {"xori", OP(26), OP_MASK
, PPCCOM
, PPCVLE
, {RA
, RS
, UI
}},
5206 {"xoril", OP(26), OP_MASK
, PWRCOM
, PPCVLE
, {RA
, RS
, UI
}},
5208 {"xoris", OP(27), OP_MASK
, PPCCOM
, PPCVLE
, {RA
, RS
, UI
}},
5209 {"xoriu", OP(27), OP_MASK
, PWRCOM
, PPCVLE
, {RA
, RS
, UI
}},
5211 {"andi.", OP(28), OP_MASK
, PPCCOM
, PPCVLE
, {RA
, RS
, UI
}},
5212 {"andil.", OP(28), OP_MASK
, PWRCOM
, PPCVLE
, {RA
, RS
, UI
}},
5214 {"andis.", OP(29), OP_MASK
, PPCCOM
, PPCVLE
, {RA
, RS
, UI
}},
5215 {"andiu.", OP(29), OP_MASK
, PWRCOM
, PPCVLE
, {RA
, RS
, UI
}},
5217 {"rotldi", MD(30,0,0), MDMB_MASK
, PPC64
, PPCVLE
, {RA
, RS
, SH6
}},
5218 {"clrldi", MD(30,0,0), MDSH_MASK
, PPC64
, PPCVLE
, {RA
, RS
, MB6
}},
5219 {"rldicl", MD(30,0,0), MD_MASK
, PPC64
, PPCVLE
, {RA
, RS
, SH6
, MB6
}},
5220 {"rotldi.", MD(30,0,1), MDMB_MASK
, PPC64
, PPCVLE
, {RA
, RS
, SH6
}},
5221 {"clrldi.", MD(30,0,1), MDSH_MASK
, PPC64
, PPCVLE
, {RA
, RS
, MB6
}},
5222 {"rldicl.", MD(30,0,1), MD_MASK
, PPC64
, PPCVLE
, {RA
, RS
, SH6
, MB6
}},
5224 {"rldicr", MD(30,1,0), MD_MASK
, PPC64
, PPCVLE
, {RA
, RS
, SH6
, ME6
}},
5225 {"rldicr.", MD(30,1,1), MD_MASK
, PPC64
, PPCVLE
, {RA
, RS
, SH6
, ME6
}},
5227 {"rldic", MD(30,2,0), MD_MASK
, PPC64
, PPCVLE
, {RA
, RS
, SH6
, MB6
}},
5228 {"rldic.", MD(30,2,1), MD_MASK
, PPC64
, PPCVLE
, {RA
, RS
, SH6
, MB6
}},
5230 {"rldimi", MD(30,3,0), MD_MASK
, PPC64
, PPCVLE
, {RA
, RS
, SH6
, MB6
}},
5231 {"rldimi.", MD(30,3,1), MD_MASK
, PPC64
, PPCVLE
, {RA
, RS
, SH6
, MB6
}},
5233 {"rotld", MDS(30,8,0), MDSMB_MASK
, PPC64
, PPCVLE
, {RA
, RS
, RB
}},
5234 {"rldcl", MDS(30,8,0), MDS_MASK
, PPC64
, PPCVLE
, {RA
, RS
, RB
, MB6
}},
5235 {"rotld.", MDS(30,8,1), MDSMB_MASK
, PPC64
, PPCVLE
, {RA
, RS
, RB
}},
5236 {"rldcl.", MDS(30,8,1), MDS_MASK
, PPC64
, PPCVLE
, {RA
, RS
, RB
, MB6
}},
5238 {"rldcr", MDS(30,9,0), MDS_MASK
, PPC64
, PPCVLE
, {RA
, RS
, RB
, ME6
}},
5239 {"rldcr.", MDS(30,9,1), MDS_MASK
, PPC64
, PPCVLE
, {RA
, RS
, RB
, ME6
}},
5241 {"cmpw", XOPL(31,0,0), XCMPL_MASK
, PPCCOM
, 0, {OBF
, RA
, RB
}},
5242 {"cmpd", XOPL(31,0,1), XCMPL_MASK
, PPC64
, 0, {OBF
, RA
, RB
}},
5243 {"cmp", X(31,0), XCMP_MASK
, PPC
, 0, {BF
, L32OPT
, RA
, RB
}},
5244 {"cmp", X(31,0), XCMPL_MASK
, PWRCOM
, PPC
, {BF
, RA
, RB
}},
5246 {"twlgt", XTO(31,4,TOLGT
), XTO_MASK
, PPCCOM
, 0, {RA
, RB
}},
5247 {"tlgt", XTO(31,4,TOLGT
), XTO_MASK
, PWRCOM
, 0, {RA
, RB
}},
5248 {"twllt", XTO(31,4,TOLLT
), XTO_MASK
, PPCCOM
, 0, {RA
, RB
}},
5249 {"tllt", XTO(31,4,TOLLT
), XTO_MASK
, PWRCOM
, 0, {RA
, RB
}},
5250 {"tweq", XTO(31,4,TOEQ
), XTO_MASK
, PPCCOM
, 0, {RA
, RB
}},
5251 {"teq", XTO(31,4,TOEQ
), XTO_MASK
, PWRCOM
, 0, {RA
, RB
}},
5252 {"twlge", XTO(31,4,TOLGE
), XTO_MASK
, PPCCOM
, 0, {RA
, RB
}},
5253 {"tlge", XTO(31,4,TOLGE
), XTO_MASK
, PWRCOM
, 0, {RA
, RB
}},
5254 {"twlnl", XTO(31,4,TOLNL
), XTO_MASK
, PPCCOM
, 0, {RA
, RB
}},
5255 {"tlnl", XTO(31,4,TOLNL
), XTO_MASK
, PWRCOM
, 0, {RA
, RB
}},
5256 {"twlle", XTO(31,4,TOLLE
), XTO_MASK
, PPCCOM
, 0, {RA
, RB
}},
5257 {"tlle", XTO(31,4,TOLLE
), XTO_MASK
, PWRCOM
, 0, {RA
, RB
}},
5258 {"twlng", XTO(31,4,TOLNG
), XTO_MASK
, PPCCOM
, 0, {RA
, RB
}},
5259 {"tlng", XTO(31,4,TOLNG
), XTO_MASK
, PWRCOM
, 0, {RA
, RB
}},
5260 {"twgt", XTO(31,4,TOGT
), XTO_MASK
, PPCCOM
, 0, {RA
, RB
}},
5261 {"tgt", XTO(31,4,TOGT
), XTO_MASK
, PWRCOM
, 0, {RA
, RB
}},
5262 {"twge", XTO(31,4,TOGE
), XTO_MASK
, PPCCOM
, 0, {RA
, RB
}},
5263 {"tge", XTO(31,4,TOGE
), XTO_MASK
, PWRCOM
, 0, {RA
, RB
}},
5264 {"twnl", XTO(31,4,TONL
), XTO_MASK
, PPCCOM
, 0, {RA
, RB
}},
5265 {"tnl", XTO(31,4,TONL
), XTO_MASK
, PWRCOM
, 0, {RA
, RB
}},
5266 {"twlt", XTO(31,4,TOLT
), XTO_MASK
, PPCCOM
, 0, {RA
, RB
}},
5267 {"tlt", XTO(31,4,TOLT
), XTO_MASK
, PWRCOM
, 0, {RA
, RB
}},
5268 {"twle", XTO(31,4,TOLE
), XTO_MASK
, PPCCOM
, 0, {RA
, RB
}},
5269 {"tle", XTO(31,4,TOLE
), XTO_MASK
, PWRCOM
, 0, {RA
, RB
}},
5270 {"twng", XTO(31,4,TONG
), XTO_MASK
, PPCCOM
, 0, {RA
, RB
}},
5271 {"tng", XTO(31,4,TONG
), XTO_MASK
, PWRCOM
, 0, {RA
, RB
}},
5272 {"twne", XTO(31,4,TONE
), XTO_MASK
, PPCCOM
, 0, {RA
, RB
}},
5273 {"tne", XTO(31,4,TONE
), XTO_MASK
, PWRCOM
, 0, {RA
, RB
}},
5274 {"trap", XTO(31,4,TOU
), 0xffffffff, PPCCOM
, 0, {0}},
5275 {"twu", XTO(31,4,TOU
), XTO_MASK
, PPCCOM
, 0, {RA
, RB
}},
5276 {"tu", XTO(31,4,TOU
), XTO_MASK
, PWRCOM
, 0, {RA
, RB
}},
5277 {"tw", X(31,4), X_MASK
, PPCCOM
, 0, {TO
, RA
, RB
}},
5278 {"t", X(31,4), X_MASK
, PWRCOM
, 0, {TO
, RA
, RB
}},
5280 {"lvsl", X(31,6), X_MASK
, PPCVEC
, 0, {VD
, RA0
, RB
}},
5281 {"lvebx", X(31,7), X_MASK
, PPCVEC
, 0, {VD
, RA0
, RB
}},
5282 {"lbfcmx", APU(31,7,0), APU_MASK
, PPC405
, 0, {FCRT
, RA
, RB
}},
5284 {"subfc", XO(31,8,0,0), XO_MASK
, PPCCOM
, 0, {RT
, RA
, RB
}},
5285 {"sf", XO(31,8,0,0), XO_MASK
, PWRCOM
, 0, {RT
, RA
, RB
}},
5286 {"subc", XO(31,8,0,0), XO_MASK
, PPCCOM
, 0, {RT
, RB
, RA
}},
5287 {"subfc.", XO(31,8,0,1), XO_MASK
, PPCCOM
, 0, {RT
, RA
, RB
}},
5288 {"sf.", XO(31,8,0,1), XO_MASK
, PWRCOM
, 0, {RT
, RA
, RB
}},
5289 {"subc.", XO(31,8,0,1), XO_MASK
, PPCCOM
, 0, {RT
, RB
, RA
}},
5291 {"mulhdu", XO(31,9,0,0), XO_MASK
, PPC64
, 0, {RT
, RA
, RB
}},
5292 {"mulhdu.", XO(31,9,0,1), XO_MASK
, PPC64
, 0, {RT
, RA
, RB
}},
5294 {"addc", XO(31,10,0,0), XO_MASK
, PPCCOM
, 0, {RT
, RA
, RB
}},
5295 {"a", XO(31,10,0,0), XO_MASK
, PWRCOM
, 0, {RT
, RA
, RB
}},
5296 {"addc.", XO(31,10,0,1), XO_MASK
, PPCCOM
, 0, {RT
, RA
, RB
}},
5297 {"a.", XO(31,10,0,1), XO_MASK
, PWRCOM
, 0, {RT
, RA
, RB
}},
5299 {"mulhwu", XO(31,11,0,0), XO_MASK
, PPC
, 0, {RT
, RA
, RB
}},
5300 {"mulhwu.", XO(31,11,0,1), XO_MASK
, PPC
, 0, {RT
, RA
, RB
}},
5302 {"lxsiwzx", X(31,12), XX1_MASK
, PPCVSX2
, 0, {XT6
, RA0
, RB
}},
5304 {"isellt", X(31,15), X_MASK
, PPCISEL
, 0, {RT
, RA0
, RB
}},
5306 {"tlbilxlpid", XTO(31,18,0), XTO_MASK
, E500MC
|PPCA2
, 0, {0}},
5307 {"tlbilxpid", XTO(31,18,1), XTO_MASK
, E500MC
|PPCA2
, 0, {0}},
5308 {"tlbilxva", XTO(31,18,3), XTO_MASK
, E500MC
|PPCA2
, 0, {RA0
, RB
}},
5309 {"tlbilx", X(31,18), X_MASK
, E500MC
|PPCA2
, 0, {T
, RA0
, RB
}},
5311 {"mfcr", XFXM(31,19,0,0), XFXFXM_MASK
, COM
, 0, {RT
, FXM4
}},
5312 {"mfocrf", XFXM(31,19,0,1), XFXFXM_MASK
, COM
, 0, {RT
, FXM
}},
5314 {"lwarx", X(31,20), XEH_MASK
, PPC
, 0, {RT
, RA0
, RB
, EH
}},
5316 {"ldx", X(31,21), X_MASK
, PPC64
, 0, {RT
, RA0
, RB
}},
5318 {"icbt", X(31,22), X_MASK
, BOOKE
|PPCE300
|PPCA2
|PPC476
, 0, {CT
, RA0
, RB
}},
5320 {"lwzx", X(31,23), X_MASK
, PPCCOM
, 0, {RT
, RA0
, RB
}},
5321 {"lx", X(31,23), X_MASK
, PWRCOM
, 0, {RT
, RA
, RB
}},
5323 {"slw", XRC(31,24,0), X_MASK
, PPCCOM
, 0, {RA
, RS
, RB
}},
5324 {"sl", XRC(31,24,0), X_MASK
, PWRCOM
, 0, {RA
, RS
, RB
}},
5325 {"slw.", XRC(31,24,1), X_MASK
, PPCCOM
, 0, {RA
, RS
, RB
}},
5326 {"sl.", XRC(31,24,1), X_MASK
, PWRCOM
, 0, {RA
, RS
, RB
}},
5328 {"cntlzw", XRC(31,26,0), XRB_MASK
, PPCCOM
, 0, {RA
, RS
}},
5329 {"cntlz", XRC(31,26,0), XRB_MASK
, PWRCOM
, 0, {RA
, RS
}},
5330 {"cntlzw.", XRC(31,26,1), XRB_MASK
, PPCCOM
, 0, {RA
, RS
}},
5331 {"cntlz.", XRC(31,26,1), XRB_MASK
, PWRCOM
, 0, {RA
, RS
}},
5333 {"sld", XRC(31,27,0), X_MASK
, PPC64
, 0, {RA
, RS
, RB
}},
5334 {"sld.", XRC(31,27,1), X_MASK
, PPC64
, 0, {RA
, RS
, RB
}},
5336 {"and", XRC(31,28,0), X_MASK
, COM
, 0, {RA
, RS
, RB
}},
5337 {"and.", XRC(31,28,1), X_MASK
, COM
, 0, {RA
, RS
, RB
}},
5339 {"maskg", XRC(31,29,0), X_MASK
, M601
, PPCA2
, {RA
, RS
, RB
}},
5340 {"maskg.", XRC(31,29,1), X_MASK
, M601
, PPCA2
, {RA
, RS
, RB
}},
5342 {"ldepx", X(31,29), X_MASK
, E500MC
|PPCA2
, 0, {RT
, RA0
, RB
}},
5344 {"waitasec", X(31,30), XRTRARB_MASK
, POWER8
, POWER9
, {0}},
5345 {"wait", X(31,30), XWC_MASK
, POWER9
, 0, {WC
}},
5347 {"lwepx", X(31,31), X_MASK
, E500MC
|PPCA2
, 0, {RT
, RA0
, RB
}},
5349 {"cmplw", XOPL(31,32,0), XCMPL_MASK
, PPCCOM
, 0, {OBF
, RA
, RB
}},
5350 {"cmpld", XOPL(31,32,1), XCMPL_MASK
, PPC64
, 0, {OBF
, RA
, RB
}},
5351 {"cmpl", X(31,32), XCMP_MASK
, PPC
, 0, {BF
, L32OPT
, RA
, RB
}},
5352 {"cmpl", X(31,32), XCMPL_MASK
, PWRCOM
, PPC
, {BF
, RA
, RB
}},
5354 {"lvsr", X(31,38), X_MASK
, PPCVEC
, 0, {VD
, RA0
, RB
}},
5355 {"lvehx", X(31,39), X_MASK
, PPCVEC
, 0, {VD
, RA0
, RB
}},
5356 {"lhfcmx", APU(31,39,0), APU_MASK
, PPC405
, 0, {FCRT
, RA
, RB
}},
5358 {"mviwsplt", X(31,46), X_MASK
, E6500
, 0, {VD
, RA
, RB
}},
5360 {"iselgt", X(31,47), X_MASK
, PPCISEL
, 0, {RT
, RA0
, RB
}},
5362 {"lvewx", X(31,71), X_MASK
, PPCVEC
, 0, {VD
, RA0
, RB
}},
5364 {"addg6s", XO(31,74,0,0), XO_MASK
, POWER6
, 0, {RT
, RA
, RB
}},
5366 {"lxsiwax", X(31,76), XX1_MASK
, PPCVSX2
, 0, {XT6
, RA0
, RB
}},
5368 {"iseleq", X(31,79), X_MASK
, PPCISEL
, 0, {RT
, RA0
, RB
}},
5370 {"isel", XISEL(31,15), XISEL_MASK
, PPCISEL
|TITAN
, 0, {RT
, RA0
, RB
, CRB
}},
5372 {"subf", XO(31,40,0,0), XO_MASK
, PPC
, 0, {RT
, RA
, RB
}},
5373 {"sub", XO(31,40,0,0), XO_MASK
, PPC
, 0, {RT
, RB
, RA
}},
5374 {"subf.", XO(31,40,0,1), XO_MASK
, PPC
, 0, {RT
, RA
, RB
}},
5375 {"sub.", XO(31,40,0,1), XO_MASK
, PPC
, 0, {RT
, RB
, RA
}},
5377 {"mfvsrd", X(31,51), XX1RB_MASK
, PPCVSX2
, 0, {RA
, XS6
}},
5378 {"mffprd", X(31,51), XX1RB_MASK
|1, PPCVSX2
, 0, {RA
, FRS
}},
5379 {"mfvrd", X(31,51)|1, XX1RB_MASK
|1, PPCVSX2
, 0, {RA
, VS
}},
5380 {"eratilx", X(31,51), X_MASK
, PPCA2
, 0, {ERAT_T
, RA
, RB
}},
5382 {"lbarx", X(31,52), XEH_MASK
, POWER8
|E6500
, 0, {RT
, RA0
, RB
, EH
}},
5384 {"ldux", X(31,53), X_MASK
, PPC64
, 0, {RT
, RAL
, RB
}},
5386 {"dcbst", X(31,54), XRT_MASK
, PPC
, 0, {RA0
, RB
}},
5388 {"lwzux", X(31,55), X_MASK
, PPCCOM
, 0, {RT
, RAL
, RB
}},
5389 {"lux", X(31,55), X_MASK
, PWRCOM
, 0, {RT
, RA
, RB
}},
5391 {"cntlzd", XRC(31,58,0), XRB_MASK
, PPC64
, 0, {RA
, RS
}},
5392 {"cntlzd.", XRC(31,58,1), XRB_MASK
, PPC64
, 0, {RA
, RS
}},
5394 {"andc", XRC(31,60,0), X_MASK
, COM
, 0, {RA
, RS
, RB
}},
5395 {"andc.", XRC(31,60,1), X_MASK
, COM
, 0, {RA
, RS
, RB
}},
5397 {"waitrsv", X(31,62)|(1<<21), 0xffffffff, E500MC
|PPCA2
, 0, {0}},
5398 {"waitimpl", X(31,62)|(2<<21), 0xffffffff, E500MC
|PPCA2
, 0, {0}},
5399 {"wait", X(31,62), XWC_MASK
, E500MC
|PPCA2
, 0, {WC
}},
5401 {"dcbstep", XRT(31,63,0), XRT_MASK
, E500MC
|PPCA2
, 0, {RA0
, RB
}},
5403 {"tdlgt", XTO(31,68,TOLGT
), XTO_MASK
, PPC64
, 0, {RA
, RB
}},
5404 {"tdllt", XTO(31,68,TOLLT
), XTO_MASK
, PPC64
, 0, {RA
, RB
}},
5405 {"tdeq", XTO(31,68,TOEQ
), XTO_MASK
, PPC64
, 0, {RA
, RB
}},
5406 {"tdlge", XTO(31,68,TOLGE
), XTO_MASK
, PPC64
, 0, {RA
, RB
}},
5407 {"tdlnl", XTO(31,68,TOLNL
), XTO_MASK
, PPC64
, 0, {RA
, RB
}},
5408 {"tdlle", XTO(31,68,TOLLE
), XTO_MASK
, PPC64
, 0, {RA
, RB
}},
5409 {"tdlng", XTO(31,68,TOLNG
), XTO_MASK
, PPC64
, 0, {RA
, RB
}},
5410 {"tdgt", XTO(31,68,TOGT
), XTO_MASK
, PPC64
, 0, {RA
, RB
}},
5411 {"tdge", XTO(31,68,TOGE
), XTO_MASK
, PPC64
, 0, {RA
, RB
}},
5412 {"tdnl", XTO(31,68,TONL
), XTO_MASK
, PPC64
, 0, {RA
, RB
}},
5413 {"tdlt", XTO(31,68,TOLT
), XTO_MASK
, PPC64
, 0, {RA
, RB
}},
5414 {"tdle", XTO(31,68,TOLE
), XTO_MASK
, PPC64
, 0, {RA
, RB
}},
5415 {"tdng", XTO(31,68,TONG
), XTO_MASK
, PPC64
, 0, {RA
, RB
}},
5416 {"tdne", XTO(31,68,TONE
), XTO_MASK
, PPC64
, 0, {RA
, RB
}},
5417 {"tdu", XTO(31,68,TOU
), XTO_MASK
, PPC64
, 0, {RA
, RB
}},
5418 {"td", X(31,68), X_MASK
, PPC64
, 0, {TO
, RA
, RB
}},
5420 {"lwfcmx", APU(31,71,0), APU_MASK
, PPC405
, 0, {FCRT
, RA
, RB
}},
5421 {"mulhd", XO(31,73,0,0), XO_MASK
, PPC64
, 0, {RT
, RA
, RB
}},
5422 {"mulhd.", XO(31,73,0,1), XO_MASK
, PPC64
, 0, {RT
, RA
, RB
}},
5424 {"mulhw", XO(31,75,0,0), XO_MASK
, PPC
, 0, {RT
, RA
, RB
}},
5425 {"mulhw.", XO(31,75,0,1), XO_MASK
, PPC
, 0, {RT
, RA
, RB
}},
5427 {"dlmzb", XRC(31,78,0), X_MASK
, PPC403
|PPC440
|PPC476
|TITAN
, 0, {RA
, RS
, RB
}},
5428 {"dlmzb.", XRC(31,78,1), X_MASK
, PPC403
|PPC440
|PPC476
|TITAN
, 0, {RA
, RS
, RB
}},
5430 {"mtsrd", X(31,82), XRB_MASK
|(1<<20), PPC64
, 0, {SR
, RS
}},
5432 {"mfmsr", X(31,83), XRARB_MASK
, COM
, 0, {RT
}},
5434 {"ldarx", X(31,84), XEH_MASK
, PPC64
, 0, {RT
, RA0
, RB
, EH
}},
5436 {"dcbfl", XOPL(31,86,1), XRT_MASK
, POWER5
, PPC476
, {RA0
, RB
}},
5437 {"dcbf", X(31,86), XLRT_MASK
, PPC
, 0, {RA0
, RB
, L2OPT
}},
5439 {"lbzx", X(31,87), X_MASK
, COM
, 0, {RT
, RA0
, RB
}},
5441 {"lbepx", X(31,95), X_MASK
, E500MC
|PPCA2
, 0, {RT
, RA0
, RB
}},
5443 {"dni", XRC(31,97,1), XRB_MASK
, E6500
, 0, {DUI
, DCTL
}},
5445 {"lvx", X(31,103), X_MASK
, PPCVEC
, 0, {VD
, RA0
, RB
}},
5446 {"lqfcmx", APU(31,103,0), APU_MASK
, PPC405
, 0, {FCRT
, RA
, RB
}},
5448 {"neg", XO(31,104,0,0), XORB_MASK
, COM
, 0, {RT
, RA
}},
5449 {"neg.", XO(31,104,0,1), XORB_MASK
, COM
, 0, {RT
, RA
}},
5451 {"mul", XO(31,107,0,0), XO_MASK
, M601
, 0, {RT
, RA
, RB
}},
5452 {"mul.", XO(31,107,0,1), XO_MASK
, M601
, 0, {RT
, RA
, RB
}},
5454 {"mvidsplt", X(31,110), X_MASK
, E6500
, 0, {VD
, RA
, RB
}},
5456 {"mtsrdin", X(31,114), XRA_MASK
, PPC64
, 0, {RS
, RB
}},
5458 {"mffprwz", X(31,115), XX1RB_MASK
|1, PPCVSX2
, 0, {RA
, FRS
}},
5459 {"mfvrwz", X(31,115)|1, XX1RB_MASK
|1, PPCVSX2
, 0, {RA
, VS
}},
5460 {"mfvsrwz", X(31,115), XX1RB_MASK
, PPCVSX2
, 0, {RA
, XS6
}},
5462 {"lharx", X(31,116), XEH_MASK
, POWER8
|E6500
, 0, {RT
, RA0
, RB
, EH
}},
5464 {"clf", X(31,118), XTO_MASK
, POWER
, 0, {RA
, RB
}},
5466 {"lbzux", X(31,119), X_MASK
, COM
, 0, {RT
, RAL
, RB
}},
5468 {"popcntb", X(31,122), XRB_MASK
, POWER5
, 0, {RA
, RS
}},
5470 {"not", XRC(31,124,0), X_MASK
, COM
, 0, {RA
, RS
, RBS
}},
5471 {"nor", XRC(31,124,0), X_MASK
, COM
, 0, {RA
, RS
, RB
}},
5472 {"not.", XRC(31,124,1), X_MASK
, COM
, 0, {RA
, RS
, RBS
}},
5473 {"nor.", XRC(31,124,1), X_MASK
, COM
, 0, {RA
, RS
, RB
}},
5475 {"dcbfep", XRT(31,127,0), XRT_MASK
, E500MC
|PPCA2
, 0, {RA0
, RB
}},
5477 {"setb", X(31,128), XRB_MASK
|(3<<16), POWER9
, 0, {RT
, BFA
}},
5479 {"wrtee", X(31,131), XRARB_MASK
, PPC403
|BOOKE
|PPCA2
|PPC476
, 0, {RS
}},
5481 {"dcbtstls", X(31,134), X_MASK
, PPCCHLK
|PPC476
|TITAN
, 0, {CT
, RA0
, RB
}},
5483 {"stvebx", X(31,135), X_MASK
, PPCVEC
, 0, {VS
, RA0
, RB
}},
5484 {"stbfcmx", APU(31,135,0), APU_MASK
, PPC405
, 0, {FCRT
, RA
, RB
}},
5486 {"subfe", XO(31,136,0,0), XO_MASK
, PPCCOM
, 0, {RT
, RA
, RB
}},
5487 {"sfe", XO(31,136,0,0), XO_MASK
, PWRCOM
, 0, {RT
, RA
, RB
}},
5488 {"subfe.", XO(31,136,0,1), XO_MASK
, PPCCOM
, 0, {RT
, RA
, RB
}},
5489 {"sfe.", XO(31,136,0,1), XO_MASK
, PWRCOM
, 0, {RT
, RA
, RB
}},
5491 {"adde", XO(31,138,0,0), XO_MASK
, PPCCOM
, 0, {RT
, RA
, RB
}},
5492 {"ae", XO(31,138,0,0), XO_MASK
, PWRCOM
, 0, {RT
, RA
, RB
}},
5493 {"adde.", XO(31,138,0,1), XO_MASK
, PPCCOM
, 0, {RT
, RA
, RB
}},
5494 {"ae.", XO(31,138,0,1), XO_MASK
, PWRCOM
, 0, {RT
, RA
, RB
}},
5496 {"stxsiwx", X(31,140), XX1_MASK
, PPCVSX2
, 0, {XS6
, RA0
, RB
}},
5498 {"msgsndp", XRTRA(31,142,0,0), XRTRA_MASK
, POWER8
, 0, {RB
}},
5499 {"dcbtstlse", X(31,142), X_MASK
, PPCCHLK
, E500MC
, {CT
, RA0
, RB
}},
5501 {"mtcr", XFXM(31,144,0xff,0), XRARB_MASK
, COM
, 0, {RS
}},
5502 {"mtcrf", XFXM(31,144,0,0), XFXFXM_MASK
, COM
, 0, {FXM
, RS
}},
5503 {"mtocrf", XFXM(31,144,0,1), XFXFXM_MASK
, COM
, 0, {FXM
, RS
}},
5505 {"mtmsr", X(31,146), XRLARB_MASK
, COM
, 0, {RS
, A_L
}},
5507 {"mtsle", X(31,147), XRTLRARB_MASK
, POWER8
, 0, {L
}},
5509 {"eratsx", XRC(31,147,0), X_MASK
, PPCA2
, 0, {RT
, RA0
, RB
}},
5510 {"eratsx.", XRC(31,147,1), X_MASK
, PPCA2
, 0, {RT
, RA0
, RB
}},
5512 {"stdx", X(31,149), X_MASK
, PPC64
, 0, {RS
, RA0
, RB
}},
5514 {"stwcx.", XRC(31,150,1), X_MASK
, PPC
, 0, {RS
, RA0
, RB
}},
5516 {"stwx", X(31,151), X_MASK
, PPCCOM
, 0, {RS
, RA0
, RB
}},
5517 {"stx", X(31,151), X_MASK
, PWRCOM
, 0, {RS
, RA
, RB
}},
5519 {"slq", XRC(31,152,0), X_MASK
, M601
, 0, {RA
, RS
, RB
}},
5520 {"slq.", XRC(31,152,1), X_MASK
, M601
, 0, {RA
, RS
, RB
}},
5522 {"sle", XRC(31,153,0), X_MASK
, M601
, 0, {RA
, RS
, RB
}},
5523 {"sle.", XRC(31,153,1), X_MASK
, M601
, 0, {RA
, RS
, RB
}},
5525 {"prtyw", X(31,154), XRB_MASK
, POWER6
|PPCA2
|PPC476
, 0, {RA
, RS
}},
5527 {"stdepx", X(31,157), X_MASK
, E500MC
|PPCA2
, 0, {RS
, RA0
, RB
}},
5529 {"stwepx", X(31,159), X_MASK
, E500MC
|PPCA2
, 0, {RS
, RA0
, RB
}},
5531 {"wrteei", X(31,163), XE_MASK
, PPC403
|BOOKE
|PPCA2
|PPC476
, 0, {E
}},
5533 {"dcbtls", X(31,166), X_MASK
, PPCCHLK
|PPC476
|TITAN
, 0, {CT
, RA0
, RB
}},
5535 {"stvehx", X(31,167), X_MASK
, PPCVEC
, 0, {VS
, RA0
, RB
}},
5536 {"sthfcmx", APU(31,167,0), APU_MASK
, PPC405
, 0, {FCRT
, RA
, RB
}},
5538 {"addex", ZRC(31,170,0), Z2_MASK
, POWER9
, 0, {RT
, RA
, RB
, CY
}},
5540 {"msgclrp", XRTRA(31,174,0,0), XRTRA_MASK
, POWER8
, 0, {RB
}},
5541 {"dcbtlse", X(31,174), X_MASK
, PPCCHLK
, E500MC
, {CT
, RA0
, RB
}},
5543 {"mtmsrd", X(31,178), XRLARB_MASK
, PPC64
, 0, {RS
, A_L
}},
5545 {"mtvsrd", X(31,179), XX1RB_MASK
, PPCVSX2
, 0, {XT6
, RA
}},
5546 {"mtfprd", X(31,179), XX1RB_MASK
|1, PPCVSX2
, 0, {FRT
, RA
}},
5547 {"mtvrd", X(31,179)|1, XX1RB_MASK
|1, PPCVSX2
, 0, {VD
, RA
}},
5548 {"eratre", X(31,179), X_MASK
, PPCA2
, 0, {RT
, RA
, WS
}},
5550 {"stdux", X(31,181), X_MASK
, PPC64
, 0, {RS
, RAS
, RB
}},
5552 {"stqcx.", XRC(31,182,1), X_MASK
|Q_MASK
, POWER8
, 0, {RSQ
, RA0
, RB
}},
5553 {"wchkall", X(31,182), X_MASK
, PPCA2
, 0, {OBF
}},
5555 {"stwux", X(31,183), X_MASK
, PPCCOM
, 0, {RS
, RAS
, RB
}},
5556 {"stux", X(31,183), X_MASK
, PWRCOM
, 0, {RS
, RA0
, RB
}},
5558 {"sliq", XRC(31,184,0), X_MASK
, M601
, 0, {RA
, RS
, SH
}},
5559 {"sliq.", XRC(31,184,1), X_MASK
, M601
, 0, {RA
, RS
, SH
}},
5561 {"prtyd", X(31,186), XRB_MASK
, POWER6
|PPCA2
, 0, {RA
, RS
}},
5563 {"cmprb", X(31,192), XCMP_MASK
, POWER9
, 0, {BF
, L
, RA
, RB
}},
5565 {"icblq.", XRC(31,198,1), X_MASK
, E6500
, 0, {CT
, RA0
, RB
}},
5567 {"stvewx", X(31,199), X_MASK
, PPCVEC
, 0, {VS
, RA0
, RB
}},
5568 {"stwfcmx", APU(31,199,0), APU_MASK
, PPC405
, 0, {FCRT
, RA
, RB
}},
5570 {"subfze", XO(31,200,0,0), XORB_MASK
, PPCCOM
, 0, {RT
, RA
}},
5571 {"sfze", XO(31,200,0,0), XORB_MASK
, PWRCOM
, 0, {RT
, RA
}},
5572 {"subfze.", XO(31,200,0,1), XORB_MASK
, PPCCOM
, 0, {RT
, RA
}},
5573 {"sfze.", XO(31,200,0,1), XORB_MASK
, PWRCOM
, 0, {RT
, RA
}},
5575 {"addze", XO(31,202,0,0), XORB_MASK
, PPCCOM
, 0, {RT
, RA
}},
5576 {"aze", XO(31,202,0,0), XORB_MASK
, PWRCOM
, 0, {RT
, RA
}},
5577 {"addze.", XO(31,202,0,1), XORB_MASK
, PPCCOM
, 0, {RT
, RA
}},
5578 {"aze.", XO(31,202,0,1), XORB_MASK
, PWRCOM
, 0, {RT
, RA
}},
5580 {"msgsnd", XRTRA(31,206,0,0), XRTRA_MASK
, E500MC
|PPCA2
|POWER8
, 0, {RB
}},
5582 {"mtsr", X(31,210), XRB_MASK
|(1<<20), COM
, NON32
, {SR
, RS
}},
5584 {"mtfprwa", X(31,211), XX1RB_MASK
|1, PPCVSX2
, 0, {FRT
, RA
}},
5585 {"mtvrwa", X(31,211)|1, XX1RB_MASK
|1, PPCVSX2
, 0, {VD
, RA
}},
5586 {"mtvsrwa", X(31,211), XX1RB_MASK
, PPCVSX2
, 0, {XT6
, RA
}},
5587 {"eratwe", X(31,211), X_MASK
, PPCA2
, 0, {RS
, RA
, WS
}},
5589 {"ldawx.", XRC(31,212,1), X_MASK
, PPCA2
, 0, {RT
, RA0
, RB
}},
5591 {"stdcx.", XRC(31,214,1), X_MASK
, PPC64
, 0, {RS
, RA0
, RB
}},
5593 {"stbx", X(31,215), X_MASK
, COM
, 0, {RS
, RA0
, RB
}},
5595 {"sllq", XRC(31,216,0), X_MASK
, M601
, 0, {RA
, RS
, RB
}},
5596 {"sllq.", XRC(31,216,1), X_MASK
, M601
, 0, {RA
, RS
, RB
}},
5598 {"sleq", XRC(31,217,0), X_MASK
, M601
, 0, {RA
, RS
, RB
}},
5599 {"sleq.", XRC(31,217,1), X_MASK
, M601
, 0, {RA
, RS
, RB
}},
5601 {"stbepx", X(31,223), X_MASK
, E500MC
|PPCA2
, 0, {RS
, RA0
, RB
}},
5603 {"cmpeqb", X(31,224), XCMPL_MASK
, POWER9
, 0, {BF
, RA
, RB
}},
5605 {"icblc", X(31,230), X_MASK
, PPCCHLK
|PPC476
|TITAN
, 0, {CT
, RA0
, RB
}},
5607 {"stvx", X(31,231), X_MASK
, PPCVEC
, 0, {VS
, RA0
, RB
}},
5608 {"stqfcmx", APU(31,231,0), APU_MASK
, PPC405
, 0, {FCRT
, RA
, RB
}},
5610 {"subfme", XO(31,232,0,0), XORB_MASK
, PPCCOM
, 0, {RT
, RA
}},
5611 {"sfme", XO(31,232,0,0), XORB_MASK
, PWRCOM
, 0, {RT
, RA
}},
5612 {"subfme.", XO(31,232,0,1), XORB_MASK
, PPCCOM
, 0, {RT
, RA
}},
5613 {"sfme.", XO(31,232,0,1), XORB_MASK
, PWRCOM
, 0, {RT
, RA
}},
5615 {"mulld", XO(31,233,0,0), XO_MASK
, PPC64
, 0, {RT
, RA
, RB
}},
5616 {"mulld.", XO(31,233,0,1), XO_MASK
, PPC64
, 0, {RT
, RA
, RB
}},
5618 {"addme", XO(31,234,0,0), XORB_MASK
, PPCCOM
, 0, {RT
, RA
}},
5619 {"ame", XO(31,234,0,0), XORB_MASK
, PWRCOM
, 0, {RT
, RA
}},
5620 {"addme.", XO(31,234,0,1), XORB_MASK
, PPCCOM
, 0, {RT
, RA
}},
5621 {"ame.", XO(31,234,0,1), XORB_MASK
, PWRCOM
, 0, {RT
, RA
}},
5623 {"mullw", XO(31,235,0,0), XO_MASK
, PPCCOM
, 0, {RT
, RA
, RB
}},
5624 {"muls", XO(31,235,0,0), XO_MASK
, PWRCOM
, 0, {RT
, RA
, RB
}},
5625 {"mullw.", XO(31,235,0,1), XO_MASK
, PPCCOM
, 0, {RT
, RA
, RB
}},
5626 {"muls.", XO(31,235,0,1), XO_MASK
, PWRCOM
, 0, {RT
, RA
, RB
}},
5628 {"icblce", X(31,238), X_MASK
, PPCCHLK
, E500MC
|PPCA2
, {CT
, RA
, RB
}},
5629 {"msgclr", XRTRA(31,238,0,0), XRTRA_MASK
, E500MC
|PPCA2
|POWER8
, 0, {RB
}},
5630 {"mtsrin", X(31,242), XRA_MASK
, PPC
, NON32
, {RS
, RB
}},
5631 {"mtsri", X(31,242), XRA_MASK
, POWER
, NON32
, {RS
, RB
}},
5633 {"mtfprwz", X(31,243), XX1RB_MASK
|1, PPCVSX2
, 0, {FRT
, RA
}},
5634 {"mtvrwz", X(31,243)|1, XX1RB_MASK
|1, PPCVSX2
, 0, {VD
, RA
}},
5635 {"mtvsrwz", X(31,243), XX1RB_MASK
, PPCVSX2
, 0, {XT6
, RA
}},
5637 {"dcbtstt", XRT(31,246,0x10), XRT_MASK
, POWER7
, 0, {RA0
, RB
}},
5638 {"dcbtst", X(31,246), X_MASK
, POWER4
, DCBT_EO
, {RA0
, RB
, CT
}},
5639 {"dcbtst", X(31,246), X_MASK
, DCBT_EO
, 0, {CT
, RA0
, RB
}},
5640 {"dcbtst", X(31,246), X_MASK
, PPC
, POWER4
|DCBT_EO
, {RA0
, RB
}},
5642 {"stbux", X(31,247), X_MASK
, COM
, 0, {RS
, RAS
, RB
}},
5644 {"slliq", XRC(31,248,0), X_MASK
, M601
, 0, {RA
, RS
, SH
}},
5645 {"slliq.", XRC(31,248,1), X_MASK
, M601
, 0, {RA
, RS
, SH
}},
5647 {"bpermd", X(31,252), X_MASK
, POWER7
|PPCA2
, 0, {RA
, RS
, RB
}},
5649 {"dcbtstep", XRT(31,255,0), X_MASK
, E500MC
|PPCA2
, 0, {RT
, RA0
, RB
}},
5651 {"mfdcrx", X(31,259), X_MASK
, BOOKE
|PPCA2
|PPC476
, TITAN
, {RS
, RA
}},
5652 {"mfdcrx.", XRC(31,259,1), X_MASK
, PPCA2
, 0, {RS
, RA
}},
5654 {"lvexbx", X(31,261), X_MASK
, E6500
, 0, {VD
, RA0
, RB
}},
5656 {"icbt", X(31,262), XRT_MASK
, PPC403
, 0, {RA
, RB
}},
5658 {"lvepxl", X(31,263), X_MASK
, E6500
, 0, {VD
, RA0
, RB
}},
5660 {"ldfcmx", APU(31,263,0), APU_MASK
, PPC405
, 0, {FCRT
, RA
, RB
}},
5661 {"doz", XO(31,264,0,0), XO_MASK
, M601
, 0, {RT
, RA
, RB
}},
5662 {"doz.", XO(31,264,0,1), XO_MASK
, M601
, 0, {RT
, RA
, RB
}},
5664 {"modud", X(31,265), X_MASK
, POWER9
, 0, {RT
, RA
, RB
}},
5666 {"add", XO(31,266,0,0), XO_MASK
, PPCCOM
, 0, {RT
, RA
, RB
}},
5667 {"cax", XO(31,266,0,0), XO_MASK
, PWRCOM
, 0, {RT
, RA
, RB
}},
5668 {"add.", XO(31,266,0,1), XO_MASK
, PPCCOM
, 0, {RT
, RA
, RB
}},
5669 {"cax.", XO(31,266,0,1), XO_MASK
, PWRCOM
, 0, {RT
, RA
, RB
}},
5671 {"moduw", X(31,267), X_MASK
, POWER9
, 0, {RT
, RA
, RB
}},
5673 {"lxvx", X(31,268), XX1_MASK
|1<<6, PPCVSX3
, 0, {XT6
, RA0
, RB
}},
5674 {"lxvl", X(31,269), XX1_MASK
, PPCVSX3
, 0, {XT6
, RA0
, RB
}},
5676 {"ehpriv", X(31,270), 0xffffffff, E500MC
|PPCA2
, 0, {0}},
5678 {"tlbiel", X(31,274), X_MASK
|1<<20,POWER9
, 0, {RB
, RSO
, RIC
, PRS
, X_R
}},
5679 {"tlbiel", X(31,274), XRTLRA_MASK
, POWER4
, POWER9
|PPC476
, {RB
, LOPT
}},
5681 {"mfapidi", X(31,275), X_MASK
, BOOKE
, E500
|TITAN
, {RT
, RA
}},
5683 {"lqarx", X(31,276), XEH_MASK
|Q_MASK
, POWER8
, 0, {RTQ
, RAX
, RBX
, EH
}},
5685 {"lscbx", XRC(31,277,0), X_MASK
, M601
, 0, {RT
, RA
, RB
}},
5686 {"lscbx.", XRC(31,277,1), X_MASK
, M601
, 0, {RT
, RA
, RB
}},
5688 {"dcbtt", XRT(31,278,0x10), XRT_MASK
, POWER7
, 0, {RA0
, RB
}},
5689 {"dcbt", X(31,278), X_MASK
, POWER4
, DCBT_EO
, {RA0
, RB
, CT
}},
5690 {"dcbt", X(31,278), X_MASK
, DCBT_EO
, 0, {CT
, RA0
, RB
}},
5691 {"dcbt", X(31,278), X_MASK
, PPC
, POWER4
|DCBT_EO
, {RA0
, RB
}},
5693 {"lhzx", X(31,279), X_MASK
, COM
, 0, {RT
, RA0
, RB
}},
5695 {"cdtbcd", X(31,282), XRB_MASK
, POWER6
, 0, {RA
, RS
}},
5697 {"eqv", XRC(31,284,0), X_MASK
, COM
, 0, {RA
, RS
, RB
}},
5698 {"eqv.", XRC(31,284,1), X_MASK
, COM
, 0, {RA
, RS
, RB
}},
5700 {"lhepx", X(31,287), X_MASK
, E500MC
|PPCA2
, 0, {RT
, RA0
, RB
}},
5702 {"mfdcrux", X(31,291), X_MASK
, PPC464
|PPC476
, 0, {RS
, RA
}},
5704 {"lvexhx", X(31,293), X_MASK
, E6500
, 0, {VD
, RA0
, RB
}},
5705 {"lvepx", X(31,295), X_MASK
, E6500
, 0, {VD
, RA0
, RB
}},
5707 {"lxvll", X(31,301), XX1_MASK
, PPCVSX3
, 0, {XT6
, RA0
, RB
}},
5709 {"mfbhrbe", X(31,302), X_MASK
, POWER8
, 0, {RT
, BHRBE
}},
5711 {"tlbie", X(31,306), X_MASK
|1<<20,POWER9
, TITAN
, {RB
, RS
, RIC
, PRS
, X_R
}},
5712 {"tlbie", X(31,306), XRA_MASK
, POWER7
, POWER9
|TITAN
, {RB
, RS
}},
5713 {"tlbie", X(31,306), XRTLRA_MASK
, PPC
, E500
|POWER7
|TITAN
, {RB
, LOPT
}},
5714 {"tlbi", X(31,306), XRT_MASK
, POWER
, 0, {RA0
, RB
}},
5716 {"mfvsrld", X(31,307), XX1RB_MASK
, PPCVSX3
, 0, {RA
, XS6
}},
5718 {"ldmx", X(31,309), X_MASK
, POWER9
, 0, {RT
, RA0
, RB
}},
5720 {"eciwx", X(31,310), X_MASK
, PPC
, E500
|TITAN
, {RT
, RA0
, RB
}},
5722 {"lhzux", X(31,311), X_MASK
, COM
, 0, {RT
, RAL
, RB
}},
5724 {"cbcdtd", X(31,314), XRB_MASK
, POWER6
, 0, {RA
, RS
}},
5726 {"xor", XRC(31,316,0), X_MASK
, COM
, 0, {RA
, RS
, RB
}},
5727 {"xor.", XRC(31,316,1), X_MASK
, COM
, 0, {RA
, RS
, RB
}},
5729 {"dcbtep", XRT(31,319,0), X_MASK
, E500MC
|PPCA2
, 0, {RT
, RA0
, RB
}},
5731 {"mfexisr", XSPR(31,323, 64), XSPR_MASK
, PPC403
, 0, {RT
}},
5732 {"mfexier", XSPR(31,323, 66), XSPR_MASK
, PPC403
, 0, {RT
}},
5733 {"mfbr0", XSPR(31,323,128), XSPR_MASK
, PPC403
, 0, {RT
}},
5734 {"mfbr1", XSPR(31,323,129), XSPR_MASK
, PPC403
, 0, {RT
}},
5735 {"mfbr2", XSPR(31,323,130), XSPR_MASK
, PPC403
, 0, {RT
}},
5736 {"mfbr3", XSPR(31,323,131), XSPR_MASK
, PPC403
, 0, {RT
}},
5737 {"mfbr4", XSPR(31,323,132), XSPR_MASK
, PPC403
, 0, {RT
}},
5738 {"mfbr5", XSPR(31,323,133), XSPR_MASK
, PPC403
, 0, {RT
}},
5739 {"mfbr6", XSPR(31,323,134), XSPR_MASK
, PPC403
, 0, {RT
}},
5740 {"mfbr7", XSPR(31,323,135), XSPR_MASK
, PPC403
, 0, {RT
}},
5741 {"mfbear", XSPR(31,323,144), XSPR_MASK
, PPC403
, 0, {RT
}},
5742 {"mfbesr", XSPR(31,323,145), XSPR_MASK
, PPC403
, 0, {RT
}},
5743 {"mfiocr", XSPR(31,323,160), XSPR_MASK
, PPC403
, 0, {RT
}},
5744 {"mfdmacr0", XSPR(31,323,192), XSPR_MASK
, PPC403
, 0, {RT
}},
5745 {"mfdmact0", XSPR(31,323,193), XSPR_MASK
, PPC403
, 0, {RT
}},
5746 {"mfdmada0", XSPR(31,323,194), XSPR_MASK
, PPC403
, 0, {RT
}},
5747 {"mfdmasa0", XSPR(31,323,195), XSPR_MASK
, PPC403
, 0, {RT
}},
5748 {"mfdmacc0", XSPR(31,323,196), XSPR_MASK
, PPC403
, 0, {RT
}},
5749 {"mfdmacr1", XSPR(31,323,200), XSPR_MASK
, PPC403
, 0, {RT
}},
5750 {"mfdmact1", XSPR(31,323,201), XSPR_MASK
, PPC403
, 0, {RT
}},
5751 {"mfdmada1", XSPR(31,323,202), XSPR_MASK
, PPC403
, 0, {RT
}},
5752 {"mfdmasa1", XSPR(31,323,203), XSPR_MASK
, PPC403
, 0, {RT
}},
5753 {"mfdmacc1", XSPR(31,323,204), XSPR_MASK
, PPC403
, 0, {RT
}},
5754 {"mfdmacr2", XSPR(31,323,208), XSPR_MASK
, PPC403
, 0, {RT
}},
5755 {"mfdmact2", XSPR(31,323,209), XSPR_MASK
, PPC403
, 0, {RT
}},
5756 {"mfdmada2", XSPR(31,323,210), XSPR_MASK
, PPC403
, 0, {RT
}},
5757 {"mfdmasa2", XSPR(31,323,211), XSPR_MASK
, PPC403
, 0, {RT
}},
5758 {"mfdmacc2", XSPR(31,323,212), XSPR_MASK
, PPC403
, 0, {RT
}},
5759 {"mfdmacr3", XSPR(31,323,216), XSPR_MASK
, PPC403
, 0, {RT
}},
5760 {"mfdmact3", XSPR(31,323,217), XSPR_MASK
, PPC403
, 0, {RT
}},
5761 {"mfdmada3", XSPR(31,323,218), XSPR_MASK
, PPC403
, 0, {RT
}},
5762 {"mfdmasa3", XSPR(31,323,219), XSPR_MASK
, PPC403
, 0, {RT
}},
5763 {"mfdmacc3", XSPR(31,323,220), XSPR_MASK
, PPC403
, 0, {RT
}},
5764 {"mfdmasr", XSPR(31,323,224), XSPR_MASK
, PPC403
, 0, {RT
}},
5765 {"mfdcr", X(31,323), X_MASK
, PPC403
|BOOKE
|PPCA2
|PPC476
, E500
|TITAN
, {RT
, SPR
}},
5766 {"mfdcr.", XRC(31,323,1), X_MASK
, PPCA2
, 0, {RT
, SPR
}},
5768 {"lvexwx", X(31,325), X_MASK
, E6500
, 0, {VD
, RA0
, RB
}},
5770 {"dcread", X(31,326), X_MASK
, PPC476
|TITAN
, 0, {RT
, RA0
, RB
}},
5772 {"div", XO(31,331,0,0), XO_MASK
, M601
, 0, {RT
, RA
, RB
}},
5773 {"div.", XO(31,331,0,1), XO_MASK
, M601
, 0, {RT
, RA
, RB
}},
5775 {"lxvdsx", X(31,332), XX1_MASK
, PPCVSX
, 0, {XT6
, RA0
, RB
}},
5777 {"mfpmr", X(31,334), X_MASK
, PPCPMR
|PPCE300
, 0, {RT
, PMR
}},
5778 {"mftmr", X(31,366), X_MASK
, PPCTMR
, 0, {RT
, TMR
}},
5780 {"slbsync", X(31,338), 0xffffffff, POWER9
, 0, {0}},
5782 {"mfmq", XSPR(31,339, 0), XSPR_MASK
, M601
, 0, {RT
}},
5783 {"mfxer", XSPR(31,339, 1), XSPR_MASK
, COM
, 0, {RT
}},
5784 {"mfrtcu", XSPR(31,339, 4), XSPR_MASK
, COM
, TITAN
, {RT
}},
5785 {"mfrtcl", XSPR(31,339, 5), XSPR_MASK
, COM
, TITAN
, {RT
}},
5786 {"mfdec", XSPR(31,339, 6), XSPR_MASK
, MFDEC1
, 0, {RT
}},
5787 {"mflr", XSPR(31,339, 8), XSPR_MASK
, COM
, 0, {RT
}},
5788 {"mfctr", XSPR(31,339, 9), XSPR_MASK
, COM
, 0, {RT
}},
5789 {"mfdscr", XSPR(31,339, 17), XSPR_MASK
, POWER6
, 0, {RT
}},
5790 {"mftid", XSPR(31,339, 17), XSPR_MASK
, POWER
, 0, {RT
}},
5791 {"mfdsisr", XSPR(31,339, 18), XSPR_MASK
, COM
, TITAN
, {RT
}},
5792 {"mfdar", XSPR(31,339, 19), XSPR_MASK
, COM
, TITAN
, {RT
}},
5793 {"mfdec", XSPR(31,339, 22), XSPR_MASK
, MFDEC2
, MFDEC1
, {RT
}},
5794 {"mfsdr0", XSPR(31,339, 24), XSPR_MASK
, POWER
, 0, {RT
}},
5795 {"mfsdr1", XSPR(31,339, 25), XSPR_MASK
, COM
, TITAN
, {RT
}},
5796 {"mfsrr0", XSPR(31,339, 26), XSPR_MASK
, COM
, 0, {RT
}},
5797 {"mfsrr1", XSPR(31,339, 27), XSPR_MASK
, COM
, 0, {RT
}},
5798 {"mfcfar", XSPR(31,339, 28), XSPR_MASK
, POWER6
, 0, {RT
}},
5799 {"mfpid", XSPR(31,339, 48), XSPR_MASK
, BOOKE
, 0, {RT
}},
5800 {"mfcsrr0", XSPR(31,339, 58), XSPR_MASK
, BOOKE
, 0, {RT
}},
5801 {"mfcsrr1", XSPR(31,339, 59), XSPR_MASK
, BOOKE
, 0, {RT
}},
5802 {"mfdear", XSPR(31,339, 61), XSPR_MASK
, BOOKE
, 0, {RT
}},
5803 {"mfesr", XSPR(31,339, 62), XSPR_MASK
, BOOKE
, 0, {RT
}},
5804 {"mfivpr", XSPR(31,339, 63), XSPR_MASK
, BOOKE
, 0, {RT
}},
5805 {"mfctrl", XSPR(31,339,136), XSPR_MASK
, POWER4
, 0, {RT
}},
5806 {"mfcmpa", XSPR(31,339,144), XSPR_MASK
, PPC860
, 0, {RT
}},
5807 {"mfcmpb", XSPR(31,339,145), XSPR_MASK
, PPC860
, 0, {RT
}},
5808 {"mfcmpc", XSPR(31,339,146), XSPR_MASK
, PPC860
, 0, {RT
}},
5809 {"mfcmpd", XSPR(31,339,147), XSPR_MASK
, PPC860
, 0, {RT
}},
5810 {"mficr", XSPR(31,339,148), XSPR_MASK
, PPC860
, 0, {RT
}},
5811 {"mfder", XSPR(31,339,149), XSPR_MASK
, PPC860
, 0, {RT
}},
5812 {"mfcounta", XSPR(31,339,150), XSPR_MASK
, PPC860
, 0, {RT
}},
5813 {"mfcountb", XSPR(31,339,151), XSPR_MASK
, PPC860
, 0, {RT
}},
5814 {"mfcmpe", XSPR(31,339,152), XSPR_MASK
, PPC860
, 0, {RT
}},
5815 {"mfcmpf", XSPR(31,339,153), XSPR_MASK
, PPC860
, 0, {RT
}},
5816 {"mfcmpg", XSPR(31,339,154), XSPR_MASK
, PPC860
, 0, {RT
}},
5817 {"mfcmph", XSPR(31,339,155), XSPR_MASK
, PPC860
, 0, {RT
}},
5818 {"mflctrl1", XSPR(31,339,156), XSPR_MASK
, PPC860
, 0, {RT
}},
5819 {"mflctrl2", XSPR(31,339,157), XSPR_MASK
, PPC860
, 0, {RT
}},
5820 {"mfictrl", XSPR(31,339,158), XSPR_MASK
, PPC860
, 0, {RT
}},
5821 {"mfbar", XSPR(31,339,159), XSPR_MASK
, PPC860
, 0, {RT
}},
5822 {"mfvrsave", XSPR(31,339,256), XSPR_MASK
, PPCVEC
, 0, {RT
}},
5823 {"mfusprg0", XSPR(31,339,256), XSPR_MASK
, BOOKE
, 0, {RT
}},
5824 {"mfsprg", XSPR(31,339,256), XSPRG_MASK
, PPC
, 0, {RT
, SPRG
}},
5825 {"mfsprg4", XSPR(31,339,260), XSPR_MASK
, PPC405
|BOOKE
, 0, {RT
}},
5826 {"mfsprg5", XSPR(31,339,261), XSPR_MASK
, PPC405
|BOOKE
, 0, {RT
}},
5827 {"mfsprg6", XSPR(31,339,262), XSPR_MASK
, PPC405
|BOOKE
, 0, {RT
}},
5828 {"mfsprg7", XSPR(31,339,263), XSPR_MASK
, PPC405
|BOOKE
, 0, {RT
}},
5829 {"mftbu", XSPR(31,339,269), XSPR_MASK
, POWER4
|BOOKE
, 0, {RT
}},
5830 {"mftb", X(31,339), X_MASK
, POWER4
|BOOKE
, 0, {RT
, TBR
}},
5831 {"mftbl", XSPR(31,339,268), XSPR_MASK
, POWER4
|BOOKE
, 0, {RT
}},
5832 {"mfsprg0", XSPR(31,339,272), XSPR_MASK
, PPC
, 0, {RT
}},
5833 {"mfsprg1", XSPR(31,339,273), XSPR_MASK
, PPC
, 0, {RT
}},
5834 {"mfsprg2", XSPR(31,339,274), XSPR_MASK
, PPC
, 0, {RT
}},
5835 {"mfsprg3", XSPR(31,339,275), XSPR_MASK
, PPC
, 0, {RT
}},
5836 {"mfasr", XSPR(31,339,280), XSPR_MASK
, PPC64
, 0, {RT
}},
5837 {"mfear", XSPR(31,339,282), XSPR_MASK
, PPC
, TITAN
, {RT
}},
5838 {"mfpir", XSPR(31,339,286), XSPR_MASK
, BOOKE
, 0, {RT
}},
5839 {"mfpvr", XSPR(31,339,287), XSPR_MASK
, PPC
, 0, {RT
}},
5840 {"mfdbsr", XSPR(31,339,304), XSPR_MASK
, BOOKE
, 0, {RT
}},
5841 {"mfdbcr0", XSPR(31,339,308), XSPR_MASK
, BOOKE
, 0, {RT
}},
5842 {"mfdbcr1", XSPR(31,339,309), XSPR_MASK
, BOOKE
, 0, {RT
}},
5843 {"mfdbcr2", XSPR(31,339,310), XSPR_MASK
, BOOKE
, 0, {RT
}},
5844 {"mfiac1", XSPR(31,339,312), XSPR_MASK
, BOOKE
, 0, {RT
}},
5845 {"mfiac2", XSPR(31,339,313), XSPR_MASK
, BOOKE
, 0, {RT
}},
5846 {"mfiac3", XSPR(31,339,314), XSPR_MASK
, BOOKE
, 0, {RT
}},
5847 {"mfiac4", XSPR(31,339,315), XSPR_MASK
, BOOKE
, 0, {RT
}},
5848 {"mfdac1", XSPR(31,339,316), XSPR_MASK
, BOOKE
, 0, {RT
}},
5849 {"mfdac2", XSPR(31,339,317), XSPR_MASK
, BOOKE
, 0, {RT
}},
5850 {"mfdvc1", XSPR(31,339,318), XSPR_MASK
, BOOKE
, 0, {RT
}},
5851 {"mfdvc2", XSPR(31,339,319), XSPR_MASK
, BOOKE
, 0, {RT
}},
5852 {"mftsr", XSPR(31,339,336), XSPR_MASK
, BOOKE
, 0, {RT
}},
5853 {"mftcr", XSPR(31,339,340), XSPR_MASK
, BOOKE
, 0, {RT
}},
5854 {"mfivor0", XSPR(31,339,400), XSPR_MASK
, BOOKE
, 0, {RT
}},
5855 {"mfivor1", XSPR(31,339,401), XSPR_MASK
, BOOKE
, 0, {RT
}},
5856 {"mfivor2", XSPR(31,339,402), XSPR_MASK
, BOOKE
, 0, {RT
}},
5857 {"mfivor3", XSPR(31,339,403), XSPR_MASK
, BOOKE
, 0, {RT
}},
5858 {"mfivor4", XSPR(31,339,404), XSPR_MASK
, BOOKE
, 0, {RT
}},
5859 {"mfivor5", XSPR(31,339,405), XSPR_MASK
, BOOKE
, 0, {RT
}},
5860 {"mfivor6", XSPR(31,339,406), XSPR_MASK
, BOOKE
, 0, {RT
}},
5861 {"mfivor7", XSPR(31,339,407), XSPR_MASK
, BOOKE
, 0, {RT
}},
5862 {"mfivor8", XSPR(31,339,408), XSPR_MASK
, BOOKE
, 0, {RT
}},
5863 {"mfivor9", XSPR(31,339,409), XSPR_MASK
, BOOKE
, 0, {RT
}},
5864 {"mfivor10", XSPR(31,339,410), XSPR_MASK
, BOOKE
, 0, {RT
}},
5865 {"mfivor11", XSPR(31,339,411), XSPR_MASK
, BOOKE
, 0, {RT
}},
5866 {"mfivor12", XSPR(31,339,412), XSPR_MASK
, BOOKE
, 0, {RT
}},
5867 {"mfivor13", XSPR(31,339,413), XSPR_MASK
, BOOKE
, 0, {RT
}},
5868 {"mfivor14", XSPR(31,339,414), XSPR_MASK
, BOOKE
, 0, {RT
}},
5869 {"mfivor15", XSPR(31,339,415), XSPR_MASK
, BOOKE
, 0, {RT
}},
5870 {"mfspefscr", XSPR(31,339,512), XSPR_MASK
, PPCSPE
, 0, {RT
}},
5871 {"mfbbear", XSPR(31,339,513), XSPR_MASK
, PPCBRLK
, 0, {RT
}},
5872 {"mfbbtar", XSPR(31,339,514), XSPR_MASK
, PPCBRLK
, 0, {RT
}},
5873 {"mfivor32", XSPR(31,339,528), XSPR_MASK
, PPCSPE
|E6500
, 0, {RT
}},
5874 {"mfivor33", XSPR(31,339,529), XSPR_MASK
, PPCSPE
|E6500
, 0, {RT
}},
5875 {"mfivor34", XSPR(31,339,530), XSPR_MASK
, PPCSPE
, 0, {RT
}},
5876 {"mfivor35", XSPR(31,339,531), XSPR_MASK
, PPCPMR
, 0, {RT
}},
5877 {"mfibatu", XSPR(31,339,528), XSPRBAT_MASK
, PPC
, TITAN
, {RT
, SPRBAT
}},
5878 {"mfibatl", XSPR(31,339,529), XSPRBAT_MASK
, PPC
, TITAN
, {RT
, SPRBAT
}},
5879 {"mfdbatu", XSPR(31,339,536), XSPRBAT_MASK
, PPC
, TITAN
, {RT
, SPRBAT
}},
5880 {"mfdbatl", XSPR(31,339,537), XSPRBAT_MASK
, PPC
, TITAN
, {RT
, SPRBAT
}},
5881 {"mfic_cst", XSPR(31,339,560), XSPR_MASK
, PPC860
, 0, {RT
}},
5882 {"mfic_adr", XSPR(31,339,561), XSPR_MASK
, PPC860
, 0, {RT
}},
5883 {"mfic_dat", XSPR(31,339,562), XSPR_MASK
, PPC860
, 0, {RT
}},
5884 {"mfdc_cst", XSPR(31,339,568), XSPR_MASK
, PPC860
, 0, {RT
}},
5885 {"mfdc_adr", XSPR(31,339,569), XSPR_MASK
, PPC860
, 0, {RT
}},
5886 {"mfdc_dat", XSPR(31,339,570), XSPR_MASK
, PPC860
, 0, {RT
}},
5887 {"mfmcsrr0", XSPR(31,339,570), XSPR_MASK
, PPCRFMCI
, 0, {RT
}},
5888 {"mfmcsrr1", XSPR(31,339,571), XSPR_MASK
, PPCRFMCI
, 0, {RT
}},
5889 {"mfmcsr", XSPR(31,339,572), XSPR_MASK
, PPCRFMCI
, 0, {RT
}},
5890 {"mfmcar", XSPR(31,339,573), XSPR_MASK
, PPCRFMCI
, TITAN
, {RT
}},
5891 {"mfdpdr", XSPR(31,339,630), XSPR_MASK
, PPC860
, 0, {RT
}},
5892 {"mfdpir", XSPR(31,339,631), XSPR_MASK
, PPC860
, 0, {RT
}},
5893 {"mfimmr", XSPR(31,339,638), XSPR_MASK
, PPC860
, 0, {RT
}},
5894 {"mfmi_ctr", XSPR(31,339,784), XSPR_MASK
, PPC860
, 0, {RT
}},
5895 {"mfmi_ap", XSPR(31,339,786), XSPR_MASK
, PPC860
, 0, {RT
}},
5896 {"mfmi_epn", XSPR(31,339,787), XSPR_MASK
, PPC860
, 0, {RT
}},
5897 {"mfmi_twc", XSPR(31,339,789), XSPR_MASK
, PPC860
, 0, {RT
}},
5898 {"mfmi_rpn", XSPR(31,339,790), XSPR_MASK
, PPC860
, 0, {RT
}},
5899 {"mfmd_ctr", XSPR(31,339,792), XSPR_MASK
, PPC860
, 0, {RT
}},
5900 {"mfm_casid", XSPR(31,339,793), XSPR_MASK
, PPC860
, 0, {RT
}},
5901 {"mfmd_ap", XSPR(31,339,794), XSPR_MASK
, PPC860
, 0, {RT
}},
5902 {"mfmd_epn", XSPR(31,339,795), XSPR_MASK
, PPC860
, 0, {RT
}},
5903 {"mfmd_twb", XSPR(31,339,796), XSPR_MASK
, PPC860
, 0, {RT
}},
5904 {"mfmd_twc", XSPR(31,339,797), XSPR_MASK
, PPC860
, 0, {RT
}},
5905 {"mfmd_rpn", XSPR(31,339,798), XSPR_MASK
, PPC860
, 0, {RT
}},
5906 {"mfm_tw", XSPR(31,339,799), XSPR_MASK
, PPC860
, 0, {RT
}},
5907 {"mfmi_dbcam", XSPR(31,339,816), XSPR_MASK
, PPC860
, 0, {RT
}},
5908 {"mfmi_dbram0", XSPR(31,339,817), XSPR_MASK
, PPC860
, 0, {RT
}},
5909 {"mfmi_dbram1", XSPR(31,339,818), XSPR_MASK
, PPC860
, 0, {RT
}},
5910 {"mfmd_dbcam", XSPR(31,339,824), XSPR_MASK
, PPC860
, 0, {RT
}},
5911 {"mfmd_dbram0", XSPR(31,339,825), XSPR_MASK
, PPC860
, 0, {RT
}},
5912 {"mfmd_dbram1", XSPR(31,339,826), XSPR_MASK
, PPC860
, 0, {RT
}},
5913 {"mfivndx", XSPR(31,339,880), XSPR_MASK
, TITAN
, 0, {RT
}},
5914 {"mfdvndx", XSPR(31,339,881), XSPR_MASK
, TITAN
, 0, {RT
}},
5915 {"mfivlim", XSPR(31,339,882), XSPR_MASK
, TITAN
, 0, {RT
}},
5916 {"mfdvlim", XSPR(31,339,883), XSPR_MASK
, TITAN
, 0, {RT
}},
5917 {"mfclcsr", XSPR(31,339,884), XSPR_MASK
, TITAN
, 0, {RT
}},
5918 {"mfccr1", XSPR(31,339,888), XSPR_MASK
, TITAN
, 0, {RT
}},
5919 {"mfppr", XSPR(31,339,896), XSPR_MASK
, POWER7
, 0, {RT
}},
5920 {"mfppr32", XSPR(31,339,898), XSPR_MASK
, POWER7
, 0, {RT
}},
5921 {"mfrstcfg", XSPR(31,339,923), XSPR_MASK
, TITAN
, 0, {RT
}},
5922 {"mfdcdbtrl", XSPR(31,339,924), XSPR_MASK
, TITAN
, 0, {RT
}},
5923 {"mfdcdbtrh", XSPR(31,339,925), XSPR_MASK
, TITAN
, 0, {RT
}},
5924 {"mficdbtr", XSPR(31,339,927), XSPR_MASK
, TITAN
, 0, {RT
}},
5925 {"mfummcr0", XSPR(31,339,936), XSPR_MASK
, PPC750
, 0, {RT
}},
5926 {"mfupmc1", XSPR(31,339,937), XSPR_MASK
, PPC750
, 0, {RT
}},
5927 {"mfupmc2", XSPR(31,339,938), XSPR_MASK
, PPC750
, 0, {RT
}},
5928 {"mfusia", XSPR(31,339,939), XSPR_MASK
, PPC750
, 0, {RT
}},
5929 {"mfummcr1", XSPR(31,339,940), XSPR_MASK
, PPC750
, 0, {RT
}},
5930 {"mfupmc3", XSPR(31,339,941), XSPR_MASK
, PPC750
, 0, {RT
}},
5931 {"mfupmc4", XSPR(31,339,942), XSPR_MASK
, PPC750
, 0, {RT
}},
5932 {"mfzpr", XSPR(31,339,944), XSPR_MASK
, PPC403
, 0, {RT
}},
5933 {"mfpid", XSPR(31,339,945), XSPR_MASK
, PPC403
, 0, {RT
}},
5934 {"mfmmucr", XSPR(31,339,946), XSPR_MASK
, TITAN
, 0, {RT
}},
5935 {"mfccr0", XSPR(31,339,947), XSPR_MASK
, PPC405
|TITAN
, 0, {RT
}},
5936 {"mfiac3", XSPR(31,339,948), XSPR_MASK
, PPC405
, 0, {RT
}},
5937 {"mfiac4", XSPR(31,339,949), XSPR_MASK
, PPC405
, 0, {RT
}},
5938 {"mfdvc1", XSPR(31,339,950), XSPR_MASK
, PPC405
, 0, {RT
}},
5939 {"mfdvc2", XSPR(31,339,951), XSPR_MASK
, PPC405
, 0, {RT
}},
5940 {"mfmmcr0", XSPR(31,339,952), XSPR_MASK
, PPC750
, 0, {RT
}},
5941 {"mfpmc1", XSPR(31,339,953), XSPR_MASK
, PPC750
, 0, {RT
}},
5942 {"mfsgr", XSPR(31,339,953), XSPR_MASK
, PPC403
, 0, {RT
}},
5943 {"mfdcwr", XSPR(31,339,954), XSPR_MASK
, PPC403
, 0, {RT
}},
5944 {"mfpmc2", XSPR(31,339,954), XSPR_MASK
, PPC750
, 0, {RT
}},
5945 {"mfsia", XSPR(31,339,955), XSPR_MASK
, PPC750
, 0, {RT
}},
5946 {"mfsler", XSPR(31,339,955), XSPR_MASK
, PPC405
, 0, {RT
}},
5947 {"mfmmcr1", XSPR(31,339,956), XSPR_MASK
, PPC750
, 0, {RT
}},
5948 {"mfsu0r", XSPR(31,339,956), XSPR_MASK
, PPC405
, 0, {RT
}},
5949 {"mfdbcr1", XSPR(31,339,957), XSPR_MASK
, PPC405
, 0, {RT
}},
5950 {"mfpmc3", XSPR(31,339,957), XSPR_MASK
, PPC750
, 0, {RT
}},
5951 {"mfpmc4", XSPR(31,339,958), XSPR_MASK
, PPC750
, 0, {RT
}},
5952 {"mficdbdr", XSPR(31,339,979), XSPR_MASK
, PPC403
|TITAN
, 0, {RT
}},
5953 {"mfesr", XSPR(31,339,980), XSPR_MASK
, PPC403
, 0, {RT
}},
5954 {"mfdear", XSPR(31,339,981), XSPR_MASK
, PPC403
, 0, {RT
}},
5955 {"mfevpr", XSPR(31,339,982), XSPR_MASK
, PPC403
, 0, {RT
}},
5956 {"mfcdbcr", XSPR(31,339,983), XSPR_MASK
, PPC403
, 0, {RT
}},
5957 {"mftsr", XSPR(31,339,984), XSPR_MASK
, PPC403
, 0, {RT
}},
5958 {"mftcr", XSPR(31,339,986), XSPR_MASK
, PPC403
, 0, {RT
}},
5959 {"mfpit", XSPR(31,339,987), XSPR_MASK
, PPC403
, 0, {RT
}},
5960 {"mftbhi", XSPR(31,339,988), XSPR_MASK
, PPC403
, 0, {RT
}},
5961 {"mftblo", XSPR(31,339,989), XSPR_MASK
, PPC403
, 0, {RT
}},
5962 {"mfsrr2", XSPR(31,339,990), XSPR_MASK
, PPC403
, 0, {RT
}},
5963 {"mfsrr3", XSPR(31,339,991), XSPR_MASK
, PPC403
, 0, {RT
}},
5964 {"mfdbsr", XSPR(31,339,1008), XSPR_MASK
, PPC403
, 0, {RT
}},
5965 {"mfdbcr0", XSPR(31,339,1010), XSPR_MASK
, PPC405
, 0, {RT
}},
5966 {"mfdbdr", XSPR(31,339,1011), XSPR_MASK
, TITAN
, 0, {RS
}},
5967 {"mfiac1", XSPR(31,339,1012), XSPR_MASK
, PPC403
, 0, {RT
}},
5968 {"mfiac2", XSPR(31,339,1013), XSPR_MASK
, PPC403
, 0, {RT
}},
5969 {"mfdac1", XSPR(31,339,1014), XSPR_MASK
, PPC403
, 0, {RT
}},
5970 {"mfdac2", XSPR(31,339,1015), XSPR_MASK
, PPC403
, 0, {RT
}},
5971 {"mfl2cr", XSPR(31,339,1017), XSPR_MASK
, PPC750
, 0, {RT
}},
5972 {"mfdccr", XSPR(31,339,1018), XSPR_MASK
, PPC403
, 0, {RT
}},
5973 {"mficcr", XSPR(31,339,1019), XSPR_MASK
, PPC403
, 0, {RT
}},
5974 {"mfictc", XSPR(31,339,1019), XSPR_MASK
, PPC750
, 0, {RT
}},
5975 {"mfpbl1", XSPR(31,339,1020), XSPR_MASK
, PPC403
, 0, {RT
}},
5976 {"mfthrm1", XSPR(31,339,1020), XSPR_MASK
, PPC750
, 0, {RT
}},
5977 {"mfpbu1", XSPR(31,339,1021), XSPR_MASK
, PPC403
, 0, {RT
}},
5978 {"mfthrm2", XSPR(31,339,1021), XSPR_MASK
, PPC750
, 0, {RT
}},
5979 {"mfpbl2", XSPR(31,339,1022), XSPR_MASK
, PPC403
, 0, {RT
}},
5980 {"mfthrm3", XSPR(31,339,1022), XSPR_MASK
, PPC750
, 0, {RT
}},
5981 {"mfpbu2", XSPR(31,339,1023), XSPR_MASK
, PPC403
, 0, {RT
}},
5982 {"mfspr", X(31,339), X_MASK
, COM
, 0, {RT
, SPR
}},
5984 {"lwax", X(31,341), X_MASK
, PPC64
, 0, {RT
, RA0
, RB
}},
5986 {"dst", XDSS(31,342,0), XDSS_MASK
, PPCVEC
, 0, {RA
, RB
, STRM
}},
5988 {"lhax", X(31,343), X_MASK
, COM
, 0, {RT
, RA0
, RB
}},
5990 {"lvxl", X(31,359), X_MASK
, PPCVEC
, 0, {VD
, RA0
, RB
}},
5992 {"abs", XO(31,360,0,0), XORB_MASK
, M601
, 0, {RT
, RA
}},
5993 {"abs.", XO(31,360,0,1), XORB_MASK
, M601
, 0, {RT
, RA
}},
5995 {"divs", XO(31,363,0,0), XO_MASK
, M601
, 0, {RT
, RA
, RB
}},
5996 {"divs.", XO(31,363,0,1), XO_MASK
, M601
, 0, {RT
, RA
, RB
}},
5998 {"lxvwsx", X(31,364), XX1_MASK
, PPCVSX3
, 0, {XT6
, RA0
, RB
}},
6000 {"tlbia", X(31,370), 0xffffffff, PPC
, E500
|TITAN
, {0}},
6002 {"mftbu", XSPR(31,371,269), XSPR_MASK
, PPC
, NO371
|POWER4
, {RT
}},
6003 {"mftb", X(31,371), X_MASK
, PPC
, NO371
|POWER4
, {RT
, TBR
}},
6004 {"mftbl", XSPR(31,371,268), XSPR_MASK
, PPC
, NO371
|POWER4
, {RT
}},
6006 {"lwaux", X(31,373), X_MASK
, PPC64
, 0, {RT
, RAL
, RB
}},
6008 {"dstst", XDSS(31,374,0), XDSS_MASK
, PPCVEC
, 0, {RA
, RB
, STRM
}},
6010 {"lhaux", X(31,375), X_MASK
, COM
, 0, {RT
, RAL
, RB
}},
6012 {"popcntw", X(31,378), XRB_MASK
, POWER7
|PPCA2
, 0, {RA
, RS
}},
6014 {"mtdcrx", X(31,387), X_MASK
, BOOKE
|PPCA2
|PPC476
, TITAN
, {RA
, RS
}},
6015 {"mtdcrx.", XRC(31,387,1), X_MASK
, PPCA2
, 0, {RA
, RS
}},
6017 {"stvexbx", X(31,389), X_MASK
, E6500
, 0, {VS
, RA0
, RB
}},
6019 {"dcblc", X(31,390), X_MASK
, PPCCHLK
|PPC476
|TITAN
, 0, {CT
, RA0
, RB
}},
6020 {"stdfcmx", APU(31,391,0), APU_MASK
, PPC405
, 0, {FCRT
, RA
, RB
}},
6022 {"divdeu", XO(31,393,0,0), XO_MASK
, POWER7
|PPCA2
, 0, {RT
, RA
, RB
}},
6023 {"divdeu.", XO(31,393,0,1), XO_MASK
, POWER7
|PPCA2
, 0, {RT
, RA
, RB
}},
6024 {"divweu", XO(31,395,0,0), XO_MASK
, POWER7
|PPCA2
, 0, {RT
, RA
, RB
}},
6025 {"divweu.", XO(31,395,0,1), XO_MASK
, POWER7
|PPCA2
, 0, {RT
, RA
, RB
}},
6027 {"stxvx", X(31,396), XX1_MASK
, PPCVSX3
, 0, {XS6
, RA0
, RB
}},
6028 {"stxvl", X(31,397), XX1_MASK
, PPCVSX3
, 0, {XS6
, RA0
, RB
}},
6030 {"dcblce", X(31,398), X_MASK
, PPCCHLK
, E500MC
, {CT
, RA
, RB
}},
6032 {"slbmte", X(31,402), XRA_MASK
, PPC64
, 0, {RS
, RB
}},
6034 {"mtvsrws", X(31,403), XX1RB_MASK
, PPCVSX3
, 0, {XT6
, RA
}},
6036 {"pbt.", XRC(31,404,1), X_MASK
, POWER8
, 0, {RS
, RA0
, RB
}},
6038 {"icswx", XRC(31,406,0), X_MASK
, POWER7
|PPCA2
, 0, {RS
, RA
, RB
}},
6039 {"icswx.", XRC(31,406,1), X_MASK
, POWER7
|PPCA2
, 0, {RS
, RA
, RB
}},
6041 {"sthx", X(31,407), X_MASK
, COM
, 0, {RS
, RA0
, RB
}},
6043 {"orc", XRC(31,412,0), X_MASK
, COM
, 0, {RA
, RS
, RB
}},
6044 {"orc.", XRC(31,412,1), X_MASK
, COM
, 0, {RA
, RS
, RB
}},
6046 {"sthepx", X(31,415), X_MASK
, E500MC
|PPCA2
, 0, {RS
, RA0
, RB
}},
6048 {"mtdcrux", X(31,419), X_MASK
, PPC464
|PPC476
, 0, {RA
, RS
}},
6050 {"stvexhx", X(31,421), X_MASK
, E6500
, 0, {VS
, RA0
, RB
}},
6052 {"dcblq.", XRC(31,422,1), X_MASK
, E6500
, 0, {CT
, RA0
, RB
}},
6054 {"divde", XO(31,425,0,0), XO_MASK
, POWER7
|PPCA2
, 0, {RT
, RA
, RB
}},
6055 {"divde.", XO(31,425,0,1), XO_MASK
, POWER7
|PPCA2
, 0, {RT
, RA
, RB
}},
6056 {"divwe", XO(31,427,0,0), XO_MASK
, POWER7
|PPCA2
, 0, {RT
, RA
, RB
}},
6057 {"divwe.", XO(31,427,0,1), XO_MASK
, POWER7
|PPCA2
, 0, {RT
, RA
, RB
}},
6059 {"stxvll", X(31,429), XX1_MASK
, PPCVSX3
, 0, {XS6
, RA0
, RB
}},
6061 {"clrbhrb", X(31,430), 0xffffffff, POWER8
, 0, {0}},
6063 {"slbie", X(31,434), XRTRA_MASK
, PPC64
, 0, {RB
}},
6065 {"mtvsrdd", X(31,435), XX1_MASK
, PPCVSX3
, 0, {XT6
, RA0
, RB
}},
6067 {"ecowx", X(31,438), X_MASK
, PPC
, E500
|TITAN
, {RT
, RA0
, RB
}},
6069 {"sthux", X(31,439), X_MASK
, COM
, 0, {RS
, RAS
, RB
}},
6071 {"mdors", 0x7f9ce378, 0xffffffff, E500MC
, 0, {0}},
6073 {"miso", 0x7f5ad378, 0xffffffff, E6500
, 0, {0}},
6075 /* The "yield", "mdoio" and "mdoom" instructions are extended mnemonics for
6076 "or rX,rX,rX", with rX being r27, r29 and r30 respectively. */
6077 {"yield", 0x7f7bdb78, 0xffffffff, POWER7
, 0, {0}},
6078 {"mdoio", 0x7fbdeb78, 0xffffffff, POWER7
, 0, {0}},
6079 {"mdoom", 0x7fdef378, 0xffffffff, POWER7
, 0, {0}},
6080 {"mr", XRC(31,444,0), X_MASK
, COM
, 0, {RA
, RS
, RBS
}},
6081 {"or", XRC(31,444,0), X_MASK
, COM
, 0, {RA
, RS
, RB
}},
6082 {"mr.", XRC(31,444,1), X_MASK
, COM
, 0, {RA
, RS
, RBS
}},
6083 {"or.", XRC(31,444,1), X_MASK
, COM
, 0, {RA
, RS
, RB
}},
6085 {"mtexisr", XSPR(31,451, 64), XSPR_MASK
, PPC403
, 0, {RS
}},
6086 {"mtexier", XSPR(31,451, 66), XSPR_MASK
, PPC403
, 0, {RS
}},
6087 {"mtbr0", XSPR(31,451,128), XSPR_MASK
, PPC403
, 0, {RS
}},
6088 {"mtbr1", XSPR(31,451,129), XSPR_MASK
, PPC403
, 0, {RS
}},
6089 {"mtbr2", XSPR(31,451,130), XSPR_MASK
, PPC403
, 0, {RS
}},
6090 {"mtbr3", XSPR(31,451,131), XSPR_MASK
, PPC403
, 0, {RS
}},
6091 {"mtbr4", XSPR(31,451,132), XSPR_MASK
, PPC403
, 0, {RS
}},
6092 {"mtbr5", XSPR(31,451,133), XSPR_MASK
, PPC403
, 0, {RS
}},
6093 {"mtbr6", XSPR(31,451,134), XSPR_MASK
, PPC403
, 0, {RS
}},
6094 {"mtbr7", XSPR(31,451,135), XSPR_MASK
, PPC403
, 0, {RS
}},
6095 {"mtbear", XSPR(31,451,144), XSPR_MASK
, PPC403
, 0, {RS
}},
6096 {"mtbesr", XSPR(31,451,145), XSPR_MASK
, PPC403
, 0, {RS
}},
6097 {"mtiocr", XSPR(31,451,160), XSPR_MASK
, PPC403
, 0, {RS
}},
6098 {"mtdmacr0", XSPR(31,451,192), XSPR_MASK
, PPC403
, 0, {RS
}},
6099 {"mtdmact0", XSPR(31,451,193), XSPR_MASK
, PPC403
, 0, {RS
}},
6100 {"mtdmada0", XSPR(31,451,194), XSPR_MASK
, PPC403
, 0, {RS
}},
6101 {"mtdmasa0", XSPR(31,451,195), XSPR_MASK
, PPC403
, 0, {RS
}},
6102 {"mtdmacc0", XSPR(31,451,196), XSPR_MASK
, PPC403
, 0, {RS
}},
6103 {"mtdmacr1", XSPR(31,451,200), XSPR_MASK
, PPC403
, 0, {RS
}},
6104 {"mtdmact1", XSPR(31,451,201), XSPR_MASK
, PPC403
, 0, {RS
}},
6105 {"mtdmada1", XSPR(31,451,202), XSPR_MASK
, PPC403
, 0, {RS
}},
6106 {"mtdmasa1", XSPR(31,451,203), XSPR_MASK
, PPC403
, 0, {RS
}},
6107 {"mtdmacc1", XSPR(31,451,204), XSPR_MASK
, PPC403
, 0, {RS
}},
6108 {"mtdmacr2", XSPR(31,451,208), XSPR_MASK
, PPC403
, 0, {RS
}},
6109 {"mtdmact2", XSPR(31,451,209), XSPR_MASK
, PPC403
, 0, {RS
}},
6110 {"mtdmada2", XSPR(31,451,210), XSPR_MASK
, PPC403
, 0, {RS
}},
6111 {"mtdmasa2", XSPR(31,451,211), XSPR_MASK
, PPC403
, 0, {RS
}},
6112 {"mtdmacc2", XSPR(31,451,212), XSPR_MASK
, PPC403
, 0, {RS
}},
6113 {"mtdmacr3", XSPR(31,451,216), XSPR_MASK
, PPC403
, 0, {RS
}},
6114 {"mtdmact3", XSPR(31,451,217), XSPR_MASK
, PPC403
, 0, {RS
}},
6115 {"mtdmada3", XSPR(31,451,218), XSPR_MASK
, PPC403
, 0, {RS
}},
6116 {"mtdmasa3", XSPR(31,451,219), XSPR_MASK
, PPC403
, 0, {RS
}},
6117 {"mtdmacc3", XSPR(31,451,220), XSPR_MASK
, PPC403
, 0, {RS
}},
6118 {"mtdmasr", XSPR(31,451,224), XSPR_MASK
, PPC403
, 0, {RS
}},
6119 {"mtdcr", X(31,451), X_MASK
, PPC403
|BOOKE
|PPCA2
|PPC476
, E500
|TITAN
, {SPR
, RS
}},
6120 {"mtdcr.", XRC(31,451,1), X_MASK
, PPCA2
, 0, {SPR
, RS
}},
6122 {"stvexwx", X(31,453), X_MASK
, E6500
, 0, {VS
, RA0
, RB
}},
6124 {"dccci", X(31,454), XRT_MASK
, PPC403
|PPC440
|PPC476
|TITAN
|PPCA2
, 0, {RAOPT
, RBOPT
}},
6125 {"dci", X(31,454), XRARB_MASK
, PPCA2
|PPC476
, 0, {CT
}},
6127 {"divdu", XO(31,457,0,0), XO_MASK
, PPC64
, 0, {RT
, RA
, RB
}},
6128 {"divdu.", XO(31,457,0,1), XO_MASK
, PPC64
, 0, {RT
, RA
, RB
}},
6130 {"divwu", XO(31,459,0,0), XO_MASK
, PPC
, 0, {RT
, RA
, RB
}},
6131 {"divwu.", XO(31,459,0,1), XO_MASK
, PPC
, 0, {RT
, RA
, RB
}},
6133 {"mtpmr", X(31,462), X_MASK
, PPCPMR
|PPCE300
, 0, {PMR
, RS
}},
6134 {"mttmr", X(31,494), X_MASK
, PPCTMR
, 0, {TMR
, RS
}},
6136 {"slbieg", X(31,466), XRA_MASK
, POWER9
, 0, {RS
, RB
}},
6138 {"mtmq", XSPR(31,467, 0), XSPR_MASK
, M601
, 0, {RS
}},
6139 {"mtxer", XSPR(31,467, 1), XSPR_MASK
, COM
, 0, {RS
}},
6140 {"mtlr", XSPR(31,467, 8), XSPR_MASK
, COM
, 0, {RS
}},
6141 {"mtctr", XSPR(31,467, 9), XSPR_MASK
, COM
, 0, {RS
}},
6142 {"mtdscr", XSPR(31,467, 17), XSPR_MASK
, POWER6
, 0, {RS
}},
6143 {"mttid", XSPR(31,467, 17), XSPR_MASK
, POWER
, 0, {RS
}},
6144 {"mtdsisr", XSPR(31,467, 18), XSPR_MASK
, COM
, TITAN
, {RS
}},
6145 {"mtdar", XSPR(31,467, 19), XSPR_MASK
, COM
, TITAN
, {RS
}},
6146 {"mtrtcu", XSPR(31,467, 20), XSPR_MASK
, COM
, TITAN
, {RS
}},
6147 {"mtrtcl", XSPR(31,467, 21), XSPR_MASK
, COM
, TITAN
, {RS
}},
6148 {"mtdec", XSPR(31,467, 22), XSPR_MASK
, COM
, 0, {RS
}},
6149 {"mtsdr0", XSPR(31,467, 24), XSPR_MASK
, POWER
, 0, {RS
}},
6150 {"mtsdr1", XSPR(31,467, 25), XSPR_MASK
, COM
, TITAN
, {RS
}},
6151 {"mtsrr0", XSPR(31,467, 26), XSPR_MASK
, COM
, 0, {RS
}},
6152 {"mtsrr1", XSPR(31,467, 27), XSPR_MASK
, COM
, 0, {RS
}},
6153 {"mtcfar", XSPR(31,467, 28), XSPR_MASK
, POWER6
, 0, {RS
}},
6154 {"mtpid", XSPR(31,467, 48), XSPR_MASK
, BOOKE
, 0, {RS
}},
6155 {"mtdecar", XSPR(31,467, 54), XSPR_MASK
, BOOKE
, 0, {RS
}},
6156 {"mtcsrr0", XSPR(31,467, 58), XSPR_MASK
, BOOKE
, 0, {RS
}},
6157 {"mtcsrr1", XSPR(31,467, 59), XSPR_MASK
, BOOKE
, 0, {RS
}},
6158 {"mtdear", XSPR(31,467, 61), XSPR_MASK
, BOOKE
, 0, {RS
}},
6159 {"mtesr", XSPR(31,467, 62), XSPR_MASK
, BOOKE
, 0, {RS
}},
6160 {"mtivpr", XSPR(31,467, 63), XSPR_MASK
, BOOKE
, 0, {RS
}},
6161 {"mtcmpa", XSPR(31,467,144), XSPR_MASK
, PPC860
, 0, {RS
}},
6162 {"mtcmpb", XSPR(31,467,145), XSPR_MASK
, PPC860
, 0, {RS
}},
6163 {"mtcmpc", XSPR(31,467,146), XSPR_MASK
, PPC860
, 0, {RS
}},
6164 {"mtcmpd", XSPR(31,467,147), XSPR_MASK
, PPC860
, 0, {RS
}},
6165 {"mticr", XSPR(31,467,148), XSPR_MASK
, PPC860
, 0, {RS
}},
6166 {"mtder", XSPR(31,467,149), XSPR_MASK
, PPC860
, 0, {RS
}},
6167 {"mtcounta", XSPR(31,467,150), XSPR_MASK
, PPC860
, 0, {RS
}},
6168 {"mtcountb", XSPR(31,467,151), XSPR_MASK
, PPC860
, 0, {RS
}},
6169 {"mtctrl", XSPR(31,467,152), XSPR_MASK
, POWER4
, 0, {RS
}},
6170 {"mtcmpe", XSPR(31,467,152), XSPR_MASK
, PPC860
, 0, {RS
}},
6171 {"mtcmpf", XSPR(31,467,153), XSPR_MASK
, PPC860
, 0, {RS
}},
6172 {"mtcmpg", XSPR(31,467,154), XSPR_MASK
, PPC860
, 0, {RS
}},
6173 {"mtcmph", XSPR(31,467,155), XSPR_MASK
, PPC860
, 0, {RS
}},
6174 {"mtlctrl1", XSPR(31,467,156), XSPR_MASK
, PPC860
, 0, {RS
}},
6175 {"mtlctrl2", XSPR(31,467,157), XSPR_MASK
, PPC860
, 0, {RS
}},
6176 {"mtictrl", XSPR(31,467,158), XSPR_MASK
, PPC860
, 0, {RS
}},
6177 {"mtbar", XSPR(31,467,159), XSPR_MASK
, PPC860
, 0, {RS
}},
6178 {"mtvrsave", XSPR(31,467,256), XSPR_MASK
, PPCVEC
, 0, {RS
}},
6179 {"mtusprg0", XSPR(31,467,256), XSPR_MASK
, BOOKE
, 0, {RS
}},
6180 {"mtsprg", XSPR(31,467,256), XSPRG_MASK
, PPC
, 0, {SPRG
, RS
}},
6181 {"mtsprg0", XSPR(31,467,272), XSPR_MASK
, PPC
, 0, {RS
}},
6182 {"mtsprg1", XSPR(31,467,273), XSPR_MASK
, PPC
, 0, {RS
}},
6183 {"mtsprg2", XSPR(31,467,274), XSPR_MASK
, PPC
, 0, {RS
}},
6184 {"mtsprg3", XSPR(31,467,275), XSPR_MASK
, PPC
, 0, {RS
}},
6185 {"mtsprg4", XSPR(31,467,276), XSPR_MASK
, PPC405
|BOOKE
, 0, {RS
}},
6186 {"mtsprg5", XSPR(31,467,277), XSPR_MASK
, PPC405
|BOOKE
, 0, {RS
}},
6187 {"mtsprg6", XSPR(31,467,278), XSPR_MASK
, PPC405
|BOOKE
, 0, {RS
}},
6188 {"mtsprg7", XSPR(31,467,279), XSPR_MASK
, PPC405
|BOOKE
, 0, {RS
}},
6189 {"mtasr", XSPR(31,467,280), XSPR_MASK
, PPC64
, 0, {RS
}},
6190 {"mtear", XSPR(31,467,282), XSPR_MASK
, PPC
, TITAN
, {RS
}},
6191 {"mttbl", XSPR(31,467,284), XSPR_MASK
, PPC
, 0, {RS
}},
6192 {"mttbu", XSPR(31,467,285), XSPR_MASK
, PPC
, 0, {RS
}},
6193 {"mtdbsr", XSPR(31,467,304), XSPR_MASK
, BOOKE
, 0, {RS
}},
6194 {"mtdbcr0", XSPR(31,467,308), XSPR_MASK
, BOOKE
, 0, {RS
}},
6195 {"mtdbcr1", XSPR(31,467,309), XSPR_MASK
, BOOKE
, 0, {RS
}},
6196 {"mtdbcr2", XSPR(31,467,310), XSPR_MASK
, BOOKE
, 0, {RS
}},
6197 {"mtiac1", XSPR(31,467,312), XSPR_MASK
, BOOKE
, 0, {RS
}},
6198 {"mtiac2", XSPR(31,467,313), XSPR_MASK
, BOOKE
, 0, {RS
}},
6199 {"mtiac3", XSPR(31,467,314), XSPR_MASK
, BOOKE
, 0, {RS
}},
6200 {"mtiac4", XSPR(31,467,315), XSPR_MASK
, BOOKE
, 0, {RS
}},
6201 {"mtdac1", XSPR(31,467,316), XSPR_MASK
, BOOKE
, 0, {RS
}},
6202 {"mtdac2", XSPR(31,467,317), XSPR_MASK
, BOOKE
, 0, {RS
}},
6203 {"mtdvc1", XSPR(31,467,318), XSPR_MASK
, BOOKE
, 0, {RS
}},
6204 {"mtdvc2", XSPR(31,467,319), XSPR_MASK
, BOOKE
, 0, {RS
}},
6205 {"mttsr", XSPR(31,467,336), XSPR_MASK
, BOOKE
, 0, {RS
}},
6206 {"mttcr", XSPR(31,467,340), XSPR_MASK
, BOOKE
, 0, {RS
}},
6207 {"mtivor0", XSPR(31,467,400), XSPR_MASK
, BOOKE
, 0, {RS
}},
6208 {"mtivor1", XSPR(31,467,401), XSPR_MASK
, BOOKE
, 0, {RS
}},
6209 {"mtivor2", XSPR(31,467,402), XSPR_MASK
, BOOKE
, 0, {RS
}},
6210 {"mtivor3", XSPR(31,467,403), XSPR_MASK
, BOOKE
, 0, {RS
}},
6211 {"mtivor4", XSPR(31,467,404), XSPR_MASK
, BOOKE
, 0, {RS
}},
6212 {"mtivor5", XSPR(31,467,405), XSPR_MASK
, BOOKE
, 0, {RS
}},
6213 {"mtivor6", XSPR(31,467,406), XSPR_MASK
, BOOKE
, 0, {RS
}},
6214 {"mtivor7", XSPR(31,467,407), XSPR_MASK
, BOOKE
, 0, {RS
}},
6215 {"mtivor8", XSPR(31,467,408), XSPR_MASK
, BOOKE
, 0, {RS
}},
6216 {"mtivor9", XSPR(31,467,409), XSPR_MASK
, BOOKE
, 0, {RS
}},
6217 {"mtivor10", XSPR(31,467,410), XSPR_MASK
, BOOKE
, 0, {RS
}},
6218 {"mtivor11", XSPR(31,467,411), XSPR_MASK
, BOOKE
, 0, {RS
}},
6219 {"mtivor12", XSPR(31,467,412), XSPR_MASK
, BOOKE
, 0, {RS
}},
6220 {"mtivor13", XSPR(31,467,413), XSPR_MASK
, BOOKE
, 0, {RS
}},
6221 {"mtivor14", XSPR(31,467,414), XSPR_MASK
, BOOKE
, 0, {RS
}},
6222 {"mtivor15", XSPR(31,467,415), XSPR_MASK
, BOOKE
, 0, {RS
}},
6223 {"mtspefscr", XSPR(31,467,512), XSPR_MASK
, PPCSPE
, 0, {RS
}},
6224 {"mtbbear", XSPR(31,467,513), XSPR_MASK
, PPCBRLK
, 0, {RS
}},
6225 {"mtbbtar", XSPR(31,467,514), XSPR_MASK
, PPCBRLK
, 0, {RS
}},
6226 {"mtivor32", XSPR(31,467,528), XSPR_MASK
, PPCSPE
|E6500
, 0, {RS
}},
6227 {"mtivor33", XSPR(31,467,529), XSPR_MASK
, PPCSPE
|E6500
, 0, {RS
}},
6228 {"mtivor34", XSPR(31,467,530), XSPR_MASK
, PPCSPE
, 0, {RS
}},
6229 {"mtivor35", XSPR(31,467,531), XSPR_MASK
, PPCPMR
, 0, {RS
}},
6230 {"mtibatu", XSPR(31,467,528), XSPRBAT_MASK
, PPC
, TITAN
, {SPRBAT
, RS
}},
6231 {"mtibatl", XSPR(31,467,529), XSPRBAT_MASK
, PPC
, TITAN
, {SPRBAT
, RS
}},
6232 {"mtdbatu", XSPR(31,467,536), XSPRBAT_MASK
, PPC
, TITAN
, {SPRBAT
, RS
}},
6233 {"mtdbatl", XSPR(31,467,537), XSPRBAT_MASK
, PPC
, TITAN
, {SPRBAT
, RS
}},
6234 {"mtmcsrr0", XSPR(31,467,570), XSPR_MASK
, PPCRFMCI
, 0, {RS
}},
6235 {"mtmcsrr1", XSPR(31,467,571), XSPR_MASK
, PPCRFMCI
, 0, {RS
}},
6236 {"mtmcsr", XSPR(31,467,572), XSPR_MASK
, PPCRFMCI
, 0, {RS
}},
6237 {"mtivndx", XSPR(31,467,880), XSPR_MASK
, TITAN
, 0, {RS
}},
6238 {"mtdvndx", XSPR(31,467,881), XSPR_MASK
, TITAN
, 0, {RS
}},
6239 {"mtivlim", XSPR(31,467,882), XSPR_MASK
, TITAN
, 0, {RS
}},
6240 {"mtdvlim", XSPR(31,467,883), XSPR_MASK
, TITAN
, 0, {RS
}},
6241 {"mtclcsr", XSPR(31,467,884), XSPR_MASK
, TITAN
, 0, {RS
}},
6242 {"mtccr1", XSPR(31,467,888), XSPR_MASK
, TITAN
, 0, {RS
}},
6243 {"mtppr", XSPR(31,467,896), XSPR_MASK
, POWER7
, 0, {RS
}},
6244 {"mtppr32", XSPR(31,467,898), XSPR_MASK
, POWER7
, 0, {RS
}},
6245 {"mtummcr0", XSPR(31,467,936), XSPR_MASK
, PPC750
, 0, {RS
}},
6246 {"mtupmc1", XSPR(31,467,937), XSPR_MASK
, PPC750
, 0, {RS
}},
6247 {"mtupmc2", XSPR(31,467,938), XSPR_MASK
, PPC750
, 0, {RS
}},
6248 {"mtusia", XSPR(31,467,939), XSPR_MASK
, PPC750
, 0, {RS
}},
6249 {"mtummcr1", XSPR(31,467,940), XSPR_MASK
, PPC750
, 0, {RS
}},
6250 {"mtupmc3", XSPR(31,467,941), XSPR_MASK
, PPC750
, 0, {RS
}},
6251 {"mtupmc4", XSPR(31,467,942), XSPR_MASK
, PPC750
, 0, {RS
}},
6252 {"mtzpr", XSPR(31,467,944), XSPR_MASK
, PPC403
, 0, {RS
}},
6253 {"mtpid", XSPR(31,467,945), XSPR_MASK
, PPC403
, 0, {RS
}},
6254 {"mtrmmucr", XSPR(31,467,946), XSPR_MASK
, TITAN
, 0, {RS
}},
6255 {"mtccr0", XSPR(31,467,947), XSPR_MASK
, PPC405
|TITAN
, 0, {RS
}},
6256 {"mtiac3", XSPR(31,467,948), XSPR_MASK
, PPC405
, 0, {RS
}},
6257 {"mtiac4", XSPR(31,467,949), XSPR_MASK
, PPC405
, 0, {RS
}},
6258 {"mtdvc1", XSPR(31,467,950), XSPR_MASK
, PPC405
, 0, {RS
}},
6259 {"mtdvc2", XSPR(31,467,951), XSPR_MASK
, PPC405
, 0, {RS
}},
6260 {"mtmmcr0", XSPR(31,467,952), XSPR_MASK
, PPC750
, 0, {RS
}},
6261 {"mtpmc1", XSPR(31,467,953), XSPR_MASK
, PPC750
, 0, {RS
}},
6262 {"mtsgr", XSPR(31,467,953), XSPR_MASK
, PPC403
, 0, {RS
}},
6263 {"mtdcwr", XSPR(31,467,954), XSPR_MASK
, PPC403
, 0, {RS
}},
6264 {"mtpmc2", XSPR(31,467,954), XSPR_MASK
, PPC750
, 0, {RS
}},
6265 {"mtsia", XSPR(31,467,955), XSPR_MASK
, PPC750
, 0, {RS
}},
6266 {"mtsler", XSPR(31,467,955), XSPR_MASK
, PPC405
, 0, {RS
}},
6267 {"mtmmcr1", XSPR(31,467,956), XSPR_MASK
, PPC750
, 0, {RS
}},
6268 {"mtsu0r", XSPR(31,467,956), XSPR_MASK
, PPC405
, 0, {RS
}},
6269 {"mtdbcr1", XSPR(31,467,957), XSPR_MASK
, PPC405
, 0, {RS
}},
6270 {"mtpmc3", XSPR(31,467,957), XSPR_MASK
, PPC750
, 0, {RS
}},
6271 {"mtpmc4", XSPR(31,467,958), XSPR_MASK
, PPC750
, 0, {RS
}},
6272 {"mticdbdr", XSPR(31,467,979), XSPR_MASK
, PPC403
, 0, {RS
}},
6273 {"mtesr", XSPR(31,467,980), XSPR_MASK
, PPC403
, 0, {RS
}},
6274 {"mtdear", XSPR(31,467,981), XSPR_MASK
, PPC403
, 0, {RS
}},
6275 {"mtevpr", XSPR(31,467,982), XSPR_MASK
, PPC403
, 0, {RS
}},
6276 {"mtcdbcr", XSPR(31,467,983), XSPR_MASK
, PPC403
, 0, {RS
}},
6277 {"mttsr", XSPR(31,467,984), XSPR_MASK
, PPC403
, 0, {RS
}},
6278 {"mttcr", XSPR(31,467,986), XSPR_MASK
, PPC403
, 0, {RS
}},
6279 {"mtpit", XSPR(31,467,987), XSPR_MASK
, PPC403
, 0, {RS
}},
6280 {"mttbhi", XSPR(31,467,988), XSPR_MASK
, PPC403
, 0, {RS
}},
6281 {"mttblo", XSPR(31,467,989), XSPR_MASK
, PPC403
, 0, {RS
}},
6282 {"mtsrr2", XSPR(31,467,990), XSPR_MASK
, PPC403
, 0, {RS
}},
6283 {"mtsrr3", XSPR(31,467,991), XSPR_MASK
, PPC403
, 0, {RS
}},
6284 {"mtdbsr", XSPR(31,467,1008), XSPR_MASK
, PPC403
, 0, {RS
}},
6285 {"mtdbdr", XSPR(31,467,1011), XSPR_MASK
, TITAN
, 0, {RS
}},
6286 {"mtdbcr0", XSPR(31,467,1010), XSPR_MASK
, PPC405
, 0, {RS
}},
6287 {"mtiac1", XSPR(31,467,1012), XSPR_MASK
, PPC403
, 0, {RS
}},
6288 {"mtiac2", XSPR(31,467,1013), XSPR_MASK
, PPC403
, 0, {RS
}},
6289 {"mtdac1", XSPR(31,467,1014), XSPR_MASK
, PPC403
, 0, {RS
}},
6290 {"mtdac2", XSPR(31,467,1015), XSPR_MASK
, PPC403
, 0, {RS
}},
6291 {"mtl2cr", XSPR(31,467,1017), XSPR_MASK
, PPC750
, 0, {RS
}},
6292 {"mtdccr", XSPR(31,467,1018), XSPR_MASK
, PPC403
, 0, {RS
}},
6293 {"mticcr", XSPR(31,467,1019), XSPR_MASK
, PPC403
, 0, {RS
}},
6294 {"mtictc", XSPR(31,467,1019), XSPR_MASK
, PPC750
, 0, {RS
}},
6295 {"mtpbl1", XSPR(31,467,1020), XSPR_MASK
, PPC403
, 0, {RS
}},
6296 {"mtthrm1", XSPR(31,467,1020), XSPR_MASK
, PPC750
, 0, {RS
}},
6297 {"mtpbu1", XSPR(31,467,1021), XSPR_MASK
, PPC403
, 0, {RS
}},
6298 {"mtthrm2", XSPR(31,467,1021), XSPR_MASK
, PPC750
, 0, {RS
}},
6299 {"mtpbl2", XSPR(31,467,1022), XSPR_MASK
, PPC403
, 0, {RS
}},
6300 {"mtthrm3", XSPR(31,467,1022), XSPR_MASK
, PPC750
, 0, {RS
}},
6301 {"mtpbu2", XSPR(31,467,1023), XSPR_MASK
, PPC403
, 0, {RS
}},
6302 {"mtspr", X(31,467), X_MASK
, COM
, 0, {SPR
, RS
}},
6304 {"dcbi", X(31,470), XRT_MASK
, PPC
, 0, {RA0
, RB
}},
6306 {"nand", XRC(31,476,0), X_MASK
, COM
, 0, {RA
, RS
, RB
}},
6307 {"nand.", XRC(31,476,1), X_MASK
, COM
, 0, {RA
, RS
, RB
}},
6309 {"dsn", X(31,483), XRT_MASK
, E500MC
, 0, {RA
, RB
}},
6311 {"dcread", X(31,486), X_MASK
, PPC403
|PPC440
, PPCA2
, {RT
, RA0
, RB
}},
6313 {"icbtls", X(31,486), X_MASK
, PPCCHLK
|PPC476
|TITAN
, 0, {CT
, RA0
, RB
}},
6315 {"stvxl", X(31,487), X_MASK
, PPCVEC
, 0, {VS
, RA0
, RB
}},
6317 {"nabs", XO(31,488,0,0), XORB_MASK
, M601
, 0, {RT
, RA
}},
6318 {"nabs.", XO(31,488,0,1), XORB_MASK
, M601
, 0, {RT
, RA
}},
6320 {"divd", XO(31,489,0,0), XO_MASK
, PPC64
, 0, {RT
, RA
, RB
}},
6321 {"divd.", XO(31,489,0,1), XO_MASK
, PPC64
, 0, {RT
, RA
, RB
}},
6323 {"divw", XO(31,491,0,0), XO_MASK
, PPC
, 0, {RT
, RA
, RB
}},
6324 {"divw.", XO(31,491,0,1), XO_MASK
, PPC
, 0, {RT
, RA
, RB
}},
6326 {"icbtlse", X(31,494), X_MASK
, PPCCHLK
, E500MC
, {CT
, RA
, RB
}},
6328 {"slbia", X(31,498), 0xff1fffff, POWER6
, 0, {IH
}},
6329 {"slbia", X(31,498), 0xffffffff, PPC64
, POWER6
, {0}},
6331 {"cli", X(31,502), XRB_MASK
, POWER
, 0, {RT
, RA
}},
6333 {"popcntd", X(31,506), XRB_MASK
, POWER7
|PPCA2
, 0, {RA
, RS
}},
6335 {"cmpb", X(31,508), X_MASK
, POWER6
|PPCA2
|PPC476
, 0, {RA
, RS
, RB
}},
6337 {"mcrxr", X(31,512), XBFRARB_MASK
, COM
, POWER7
, {BF
}},
6339 {"lbdcbx", X(31,514), X_MASK
, E200Z4
, 0, {RT
, RA
, RB
}},
6340 {"lbdx", X(31,515), X_MASK
, E500MC
|E200Z4
, 0, {RT
, RA
, RB
}},
6342 {"bblels", X(31,518), X_MASK
, PPCBRLK
, 0, {0}},
6344 {"lvlx", X(31,519), X_MASK
, CELL
, 0, {VD
, RA0
, RB
}},
6345 {"lbfcmux", APU(31,519,0), APU_MASK
, PPC405
, 0, {FCRT
, RA
, RB
}},
6347 {"subfco", XO(31,8,1,0), XO_MASK
, PPCCOM
, 0, {RT
, RA
, RB
}},
6348 {"sfo", XO(31,8,1,0), XO_MASK
, PWRCOM
, 0, {RT
, RA
, RB
}},
6349 {"subco", XO(31,8,1,0), XO_MASK
, PPCCOM
, 0, {RT
, RB
, RA
}},
6350 {"subfco.", XO(31,8,1,1), XO_MASK
, PPCCOM
, 0, {RT
, RA
, RB
}},
6351 {"sfo.", XO(31,8,1,1), XO_MASK
, PWRCOM
, 0, {RT
, RA
, RB
}},
6352 {"subco.", XO(31,8,1,1), XO_MASK
, PPCCOM
, 0, {RT
, RB
, RA
}},
6354 {"addco", XO(31,10,1,0), XO_MASK
, PPCCOM
, 0, {RT
, RA
, RB
}},
6355 {"ao", XO(31,10,1,0), XO_MASK
, PWRCOM
, 0, {RT
, RA
, RB
}},
6356 {"addco.", XO(31,10,1,1), XO_MASK
, PPCCOM
, 0, {RT
, RA
, RB
}},
6357 {"ao.", XO(31,10,1,1), XO_MASK
, PWRCOM
, 0, {RT
, RA
, RB
}},
6359 {"lxsspx", X(31,524), XX1_MASK
, PPCVSX2
, 0, {XT6
, RA0
, RB
}},
6361 {"clcs", X(31,531), XRB_MASK
, M601
, 0, {RT
, RA
}},
6363 {"ldbrx", X(31,532), X_MASK
, CELL
|POWER7
|PPCA2
, 0, {RT
, RA0
, RB
}},
6365 {"lswx", X(31,533), X_MASK
, PPCCOM
, E500
|E500MC
, {RT
, RAX
, RBX
}},
6366 {"lsx", X(31,533), X_MASK
, PWRCOM
, 0, {RT
, RA
, RB
}},
6368 {"lwbrx", X(31,534), X_MASK
, PPCCOM
, 0, {RT
, RA0
, RB
}},
6369 {"lbrx", X(31,534), X_MASK
, PWRCOM
, 0, {RT
, RA
, RB
}},
6371 {"lfsx", X(31,535), X_MASK
, COM
, PPCEFS
, {FRT
, RA0
, RB
}},
6373 {"srw", XRC(31,536,0), X_MASK
, PPCCOM
, 0, {RA
, RS
, RB
}},
6374 {"sr", XRC(31,536,0), X_MASK
, PWRCOM
, 0, {RA
, RS
, RB
}},
6375 {"srw.", XRC(31,536,1), X_MASK
, PPCCOM
, 0, {RA
, RS
, RB
}},
6376 {"sr.", XRC(31,536,1), X_MASK
, PWRCOM
, 0, {RA
, RS
, RB
}},
6378 {"rrib", XRC(31,537,0), X_MASK
, M601
, 0, {RA
, RS
, RB
}},
6379 {"rrib.", XRC(31,537,1), X_MASK
, M601
, 0, {RA
, RS
, RB
}},
6381 {"cnttzw", XRC(31,538,0), XRB_MASK
, POWER9
, 0, {RA
, RS
}},
6382 {"cnttzw.", XRC(31,538,1), XRB_MASK
, POWER9
, 0, {RA
, RS
}},
6384 {"srd", XRC(31,539,0), X_MASK
, PPC64
, 0, {RA
, RS
, RB
}},
6385 {"srd.", XRC(31,539,1), X_MASK
, PPC64
, 0, {RA
, RS
, RB
}},
6387 {"maskir", XRC(31,541,0), X_MASK
, M601
, 0, {RA
, RS
, RB
}},
6388 {"maskir.", XRC(31,541,1), X_MASK
, M601
, 0, {RA
, RS
, RB
}},
6390 {"lhdcbx", X(31,546), X_MASK
, E200Z4
, 0, {RT
, RA
, RB
}},
6391 {"lhdx", X(31,547), X_MASK
, E500MC
|E200Z4
, 0, {RT
, RA
, RB
}},
6393 {"lvtrx", X(31,549), X_MASK
, E6500
, 0, {VD
, RA0
, RB
}},
6395 {"bbelr", X(31,550), X_MASK
, PPCBRLK
, 0, {0}},
6397 {"lvrx", X(31,551), X_MASK
, CELL
, 0, {VD
, RA0
, RB
}},
6398 {"lhfcmux", APU(31,551,0), APU_MASK
, PPC405
, 0, {FCRT
, RA
, RB
}},
6400 {"subfo", XO(31,40,1,0), XO_MASK
, PPC
, 0, {RT
, RA
, RB
}},
6401 {"subo", XO(31,40,1,0), XO_MASK
, PPC
, 0, {RT
, RB
, RA
}},
6402 {"subfo.", XO(31,40,1,1), XO_MASK
, PPC
, 0, {RT
, RA
, RB
}},
6403 {"subo.", XO(31,40,1,1), XO_MASK
, PPC
, 0, {RT
, RB
, RA
}},
6405 {"tlbsync", X(31,566), 0xffffffff, PPC
, 0, {0}},
6407 {"lfsux", X(31,567), X_MASK
, COM
, PPCEFS
, {FRT
, RAS
, RB
}},
6409 {"cnttzd", XRC(31,570,0), XRB_MASK
, POWER9
, 0, {RA
, RS
}},
6410 {"cnttzd.", XRC(31,570,1), XRB_MASK
, POWER9
, 0, {RA
, RS
}},
6412 {"mcrxrx", X(31,576), XBFRARB_MASK
, POWER9
, 0, {BF
}},
6414 {"lwdcbx", X(31,578), X_MASK
, E200Z4
, 0, {RT
, RA
, RB
}},
6415 {"lwdx", X(31,579), X_MASK
, E500MC
|E200Z4
, 0, {RT
, RA
, RB
}},
6417 {"lvtlx", X(31,581), X_MASK
, E6500
, 0, {VD
, RA0
, RB
}},
6419 {"lwat", X(31,582), X_MASK
, POWER9
, 0, {RT
, RA0
, FC
}},
6421 {"lwfcmux", APU(31,583,0), APU_MASK
, PPC405
, 0, {FCRT
, RA
, RB
}},
6423 {"lxsdx", X(31,588), XX1_MASK
, PPCVSX
, 0, {XT6
, RA0
, RB
}},
6425 {"mfsr", X(31,595), XRB_MASK
|(1<<20), COM
, NON32
, {RT
, SR
}},
6427 {"lswi", X(31,597), X_MASK
, PPCCOM
, E500
|E500MC
, {RT
, RAX
, NBI
}},
6428 {"lsi", X(31,597), X_MASK
, PWRCOM
, 0, {RT
, RA0
, NB
}},
6430 {"hwsync", XSYNC(31,598,0), 0xffffffff, POWER4
, BOOKE
|PPC476
, {0}},
6431 {"lwsync", XSYNC(31,598,1), 0xffffffff, PPC
, E500
, {0}},
6432 {"ptesync", XSYNC(31,598,2), 0xffffffff, PPC64
, 0, {0}},
6433 {"sync", X(31,598), XSYNCLE_MASK
, E6500
, 0, {LS
, ESYNC
}},
6434 {"sync", X(31,598), XSYNC_MASK
, PPCCOM
, BOOKE
|PPC476
, {LS
}},
6435 {"msync", X(31,598), 0xffffffff, BOOKE
|PPCA2
|PPC476
, 0, {0}},
6436 {"sync", X(31,598), 0xffffffff, BOOKE
|PPC476
, E6500
, {0}},
6437 {"lwsync", X(31,598), 0xffffffff, E500
, 0, {0}},
6438 {"dcs", X(31,598), 0xffffffff, PWRCOM
, 0, {0}},
6440 {"lfdx", X(31,599), X_MASK
, COM
, PPCEFS
, {FRT
, RA0
, RB
}},
6442 {"mffgpr", XRC(31,607,0), XRA_MASK
, POWER6
, POWER7
, {FRT
, RB
}},
6443 {"lfdepx", X(31,607), X_MASK
, E500MC
|PPCA2
, 0, {FRT
, RA0
, RB
}},
6445 {"lddx", X(31,611), X_MASK
, E500MC
, 0, {RT
, RA
, RB
}},
6447 {"lvswx", X(31,613), X_MASK
, E6500
, 0, {VD
, RA0
, RB
}},
6449 {"ldat", X(31,614), X_MASK
, POWER9
, 0, {RT
, RA0
, FC
}},
6451 {"lqfcmux", APU(31,615,0), APU_MASK
, PPC405
, 0, {FCRT
, RA
, RB
}},
6453 {"nego", XO(31,104,1,0), XORB_MASK
, COM
, 0, {RT
, RA
}},
6454 {"nego.", XO(31,104,1,1), XORB_MASK
, COM
, 0, {RT
, RA
}},
6456 {"mulo", XO(31,107,1,0), XO_MASK
, M601
, 0, {RT
, RA
, RB
}},
6457 {"mulo.", XO(31,107,1,1), XO_MASK
, M601
, 0, {RT
, RA
, RB
}},
6459 {"mfsri", X(31,627), X_MASK
, M601
, 0, {RT
, RA
, RB
}},
6461 {"dclst", X(31,630), XRB_MASK
, M601
, 0, {RS
, RA
}},
6463 {"lfdux", X(31,631), X_MASK
, COM
, PPCEFS
, {FRT
, RAS
, RB
}},
6465 {"stbdcbx", X(31,642), X_MASK
, E200Z4
, 0, {RS
, RA
, RB
}},
6466 {"stbdx", X(31,643), X_MASK
, E500MC
|E200Z4
, 0, {RS
, RA
, RB
}},
6468 {"stvlx", X(31,647), X_MASK
, CELL
, 0, {VS
, RA0
, RB
}},
6469 {"stbfcmux", APU(31,647,0), APU_MASK
, PPC405
, 0, {FCRT
, RA
, RB
}},
6471 {"stxsspx", X(31,652), XX1_MASK
, PPCVSX2
, 0, {XS6
, RA0
, RB
}},
6473 {"tbegin.", XRC(31,654,1), XRTLRARB_MASK
, PPCHTM
, 0, {HTM_R
}},
6475 {"subfeo", XO(31,136,1,0), XO_MASK
, PPCCOM
, 0, {RT
, RA
, RB
}},
6476 {"sfeo", XO(31,136,1,0), XO_MASK
, PWRCOM
, 0, {RT
, RA
, RB
}},
6477 {"subfeo.", XO(31,136,1,1), XO_MASK
, PPCCOM
, 0, {RT
, RA
, RB
}},
6478 {"sfeo.", XO(31,136,1,1), XO_MASK
, PWRCOM
, 0, {RT
, RA
, RB
}},
6480 {"addeo", XO(31,138,1,0), XO_MASK
, PPCCOM
, 0, {RT
, RA
, RB
}},
6481 {"aeo", XO(31,138,1,0), XO_MASK
, PWRCOM
, 0, {RT
, RA
, RB
}},
6482 {"addeo.", XO(31,138,1,1), XO_MASK
, PPCCOM
, 0, {RT
, RA
, RB
}},
6483 {"aeo.", XO(31,138,1,1), XO_MASK
, PWRCOM
, 0, {RT
, RA
, RB
}},
6485 {"mfsrin", X(31,659), XRA_MASK
, PPC
, NON32
, {RT
, RB
}},
6487 {"stdbrx", X(31,660), X_MASK
, CELL
|POWER7
|PPCA2
, 0, {RS
, RA0
, RB
}},
6489 {"stswx", X(31,661), X_MASK
, PPCCOM
, E500
|E500MC
, {RS
, RA0
, RB
}},
6490 {"stsx", X(31,661), X_MASK
, PWRCOM
, 0, {RS
, RA0
, RB
}},
6492 {"stwbrx", X(31,662), X_MASK
, PPCCOM
, 0, {RS
, RA0
, RB
}},
6493 {"stbrx", X(31,662), X_MASK
, PWRCOM
, 0, {RS
, RA0
, RB
}},
6495 {"stfsx", X(31,663), X_MASK
, COM
, PPCEFS
, {FRS
, RA0
, RB
}},
6497 {"srq", XRC(31,664,0), X_MASK
, M601
, 0, {RA
, RS
, RB
}},
6498 {"srq.", XRC(31,664,1), X_MASK
, M601
, 0, {RA
, RS
, RB
}},
6500 {"sre", XRC(31,665,0), X_MASK
, M601
, 0, {RA
, RS
, RB
}},
6501 {"sre.", XRC(31,665,1), X_MASK
, M601
, 0, {RA
, RS
, RB
}},
6503 {"sthdcbx", X(31,674), X_MASK
, E200Z4
, 0, {RS
, RA
, RB
}},
6504 {"sthdx", X(31,675), X_MASK
, E500MC
|E200Z4
, 0, {RS
, RA
, RB
}},
6506 {"stvfrx", X(31,677), X_MASK
, E6500
, 0, {VS
, RA0
, RB
}},
6508 {"stvrx", X(31,679), X_MASK
, CELL
, 0, {VS
, RA0
, RB
}},
6509 {"sthfcmux", APU(31,679,0), APU_MASK
, PPC405
, 0, {FCRT
, RA
, RB
}},
6511 {"tendall.", XRC(31,686,1)|(1<<25), XRTRARB_MASK
, PPCHTM
, 0, {0}},
6512 {"tend.", XRC(31,686,1), XRTARARB_MASK
, PPCHTM
, 0, {HTM_A
}},
6514 {"stbcx.", XRC(31,694,1), X_MASK
, POWER8
|E6500
, 0, {RS
, RA0
, RB
}},
6516 {"stfsux", X(31,695), X_MASK
, COM
, PPCEFS
, {FRS
, RAS
, RB
}},
6518 {"sriq", XRC(31,696,0), X_MASK
, M601
, 0, {RA
, RS
, SH
}},
6519 {"sriq.", XRC(31,696,1), X_MASK
, M601
, 0, {RA
, RS
, SH
}},
6521 {"stwdcbx", X(31,706), X_MASK
, E200Z4
, 0, {RS
, RA
, RB
}},
6522 {"stwdx", X(31,707), X_MASK
, E500MC
|E200Z4
, 0, {RS
, RA
, RB
}},
6524 {"stvflx", X(31,709), X_MASK
, E6500
, 0, {VS
, RA0
, RB
}},
6526 {"stwat", X(31,710), X_MASK
, POWER9
, 0, {RS
, RA0
, FC
}},
6528 {"stwfcmux", APU(31,711,0), APU_MASK
, PPC405
, 0, {FCRT
, RA
, RB
}},
6530 {"stxsdx", X(31,716), XX1_MASK
, PPCVSX
, 0, {XS6
, RA0
, RB
}},
6532 {"tcheck", X(31,718), XRTBFRARB_MASK
, PPCHTM
, 0, {BF
}},
6534 {"subfzeo", XO(31,200,1,0), XORB_MASK
, PPCCOM
, 0, {RT
, RA
}},
6535 {"sfzeo", XO(31,200,1,0), XORB_MASK
, PWRCOM
, 0, {RT
, RA
}},
6536 {"subfzeo.", XO(31,200,1,1), XORB_MASK
, PPCCOM
, 0, {RT
, RA
}},
6537 {"sfzeo.", XO(31,200,1,1), XORB_MASK
, PWRCOM
, 0, {RT
, RA
}},
6539 {"addzeo", XO(31,202,1,0), XORB_MASK
, PPCCOM
, 0, {RT
, RA
}},
6540 {"azeo", XO(31,202,1,0), XORB_MASK
, PWRCOM
, 0, {RT
, RA
}},
6541 {"addzeo.", XO(31,202,1,1), XORB_MASK
, PPCCOM
, 0, {RT
, RA
}},
6542 {"azeo.", XO(31,202,1,1), XORB_MASK
, PWRCOM
, 0, {RT
, RA
}},
6544 {"stswi", X(31,725), X_MASK
, PPCCOM
, E500
|E500MC
, {RS
, RA0
, NB
}},
6545 {"stsi", X(31,725), X_MASK
, PWRCOM
, 0, {RS
, RA0
, NB
}},
6547 {"sthcx.", XRC(31,726,1), X_MASK
, POWER8
|E6500
, 0, {RS
, RA0
, RB
}},
6549 {"stfdx", X(31,727), X_MASK
, COM
, PPCEFS
, {FRS
, RA0
, RB
}},
6551 {"srlq", XRC(31,728,0), X_MASK
, M601
, 0, {RA
, RS
, RB
}},
6552 {"srlq.", XRC(31,728,1), X_MASK
, M601
, 0, {RA
, RS
, RB
}},
6554 {"sreq", XRC(31,729,0), X_MASK
, M601
, 0, {RA
, RS
, RB
}},
6555 {"sreq.", XRC(31,729,1), X_MASK
, M601
, 0, {RA
, RS
, RB
}},
6557 {"mftgpr", XRC(31,735,0), XRA_MASK
, POWER6
, POWER7
, {RT
, FRB
}},
6558 {"stfdepx", X(31,735), X_MASK
, E500MC
|PPCA2
, 0, {FRS
, RA0
, RB
}},
6560 {"stddx", X(31,739), X_MASK
, E500MC
, 0, {RS
, RA
, RB
}},
6562 {"stvswx", X(31,741), X_MASK
, E6500
, 0, {VS
, RA0
, RB
}},
6564 {"stdat", X(31,742), X_MASK
, POWER9
, 0, {RS
, RA0
, FC
}},
6566 {"stqfcmux", APU(31,743,0), APU_MASK
, PPC405
, 0, {FCRT
, RA
, RB
}},
6568 {"subfmeo", XO(31,232,1,0), XORB_MASK
, PPCCOM
, 0, {RT
, RA
}},
6569 {"sfmeo", XO(31,232,1,0), XORB_MASK
, PWRCOM
, 0, {RT
, RA
}},
6570 {"subfmeo.", XO(31,232,1,1), XORB_MASK
, PPCCOM
, 0, {RT
, RA
}},
6571 {"sfmeo.", XO(31,232,1,1), XORB_MASK
, PWRCOM
, 0, {RT
, RA
}},
6573 {"mulldo", XO(31,233,1,0), XO_MASK
, PPC64
, 0, {RT
, RA
, RB
}},
6574 {"mulldo.", XO(31,233,1,1), XO_MASK
, PPC64
, 0, {RT
, RA
, RB
}},
6576 {"addmeo", XO(31,234,1,0), XORB_MASK
, PPCCOM
, 0, {RT
, RA
}},
6577 {"ameo", XO(31,234,1,0), XORB_MASK
, PWRCOM
, 0, {RT
, RA
}},
6578 {"addmeo.", XO(31,234,1,1), XORB_MASK
, PPCCOM
, 0, {RT
, RA
}},
6579 {"ameo.", XO(31,234,1,1), XORB_MASK
, PWRCOM
, 0, {RT
, RA
}},
6581 {"mullwo", XO(31,235,1,0), XO_MASK
, PPCCOM
, 0, {RT
, RA
, RB
}},
6582 {"mulso", XO(31,235,1,0), XO_MASK
, PWRCOM
, 0, {RT
, RA
, RB
}},
6583 {"mullwo.", XO(31,235,1,1), XO_MASK
, PPCCOM
, 0, {RT
, RA
, RB
}},
6584 {"mulso.", XO(31,235,1,1), XO_MASK
, PWRCOM
, 0, {RT
, RA
, RB
}},
6586 {"tsuspend.", XRCL(31,750,0,1), XRTRARB_MASK
,PPCHTM
, 0, {0}},
6587 {"tresume.", XRCL(31,750,1,1), XRTRARB_MASK
,PPCHTM
, 0, {0}},
6588 {"tsr.", XRC(31,750,1), XRTLRARB_MASK
,PPCHTM
, 0, {L
}},
6590 {"darn", X(31,755), XLRAND_MASK
, POWER9
, 0, {RT
, LRAND
}},
6592 {"dcba", X(31,758), XRT_MASK
, PPC405
|PPC7450
|BOOKE
|PPCA2
|PPC476
, 0, {RA0
, RB
}},
6593 {"dcbal", XOPL(31,758,1), XRT_MASK
, E500MC
, 0, {RA0
, RB
}},
6595 {"stfdux", X(31,759), X_MASK
, COM
, PPCEFS
, {FRS
, RAS
, RB
}},
6597 {"srliq", XRC(31,760,0), X_MASK
, M601
, 0, {RA
, RS
, SH
}},
6598 {"srliq.", XRC(31,760,1), X_MASK
, M601
, 0, {RA
, RS
, SH
}},
6600 {"lvsm", X(31,773), X_MASK
, E6500
, 0, {VD
, RA0
, RB
}},
6602 {"copy", XOPL(31,774,1), XRT_MASK
, POWER9
, 0, {RA0
, RB
}},
6604 {"stvepxl", X(31,775), X_MASK
, E6500
, 0, {VS
, RA0
, RB
}},
6605 {"lvlxl", X(31,775), X_MASK
, CELL
, 0, {VD
, RA0
, RB
}},
6606 {"ldfcmux", APU(31,775,0), APU_MASK
, PPC405
, 0, {FCRT
, RA
, RB
}},
6608 {"dozo", XO(31,264,1,0), XO_MASK
, M601
, 0, {RT
, RA
, RB
}},
6609 {"dozo.", XO(31,264,1,1), XO_MASK
, M601
, 0, {RT
, RA
, RB
}},
6611 {"addo", XO(31,266,1,0), XO_MASK
, PPCCOM
, 0, {RT
, RA
, RB
}},
6612 {"caxo", XO(31,266,1,0), XO_MASK
, PWRCOM
, 0, {RT
, RA
, RB
}},
6613 {"addo.", XO(31,266,1,1), XO_MASK
, PPCCOM
, 0, {RT
, RA
, RB
}},
6614 {"caxo.", XO(31,266,1,1), XO_MASK
, PWRCOM
, 0, {RT
, RA
, RB
}},
6616 {"modsd", X(31,777), X_MASK
, POWER9
, 0, {RT
, RA
, RB
}},
6617 {"modsw", X(31,779), X_MASK
, POWER9
, 0, {RT
, RA
, RB
}},
6619 {"lxvw4x", X(31,780), XX1_MASK
, PPCVSX
, 0, {XT6
, RA0
, RB
}},
6620 {"lxsibzx", X(31,781), XX1_MASK
, PPCVSX3
, 0, {XT6
, RA0
, RB
}},
6622 {"tabortwc.", XRC(31,782,1), X_MASK
, PPCHTM
, 0, {TO
, RA
, RB
}},
6624 {"tlbivax", X(31,786), XRT_MASK
, BOOKE
|PPCA2
|PPC476
, 0, {RA0
, RB
}},
6626 {"lwzcix", X(31,789), X_MASK
, POWER6
, 0, {RT
, RA0
, RB
}},
6628 {"lhbrx", X(31,790), X_MASK
, COM
, 0, {RT
, RA0
, RB
}},
6630 {"lfdpx", X(31,791), X_MASK
|Q_MASK
, POWER6
, POWER7
, {FRTp
, RA0
, RB
}},
6631 {"lfqx", X(31,791), X_MASK
, POWER2
, 0, {FRT
, RA
, RB
}},
6633 {"sraw", XRC(31,792,0), X_MASK
, PPCCOM
, 0, {RA
, RS
, RB
}},
6634 {"sra", XRC(31,792,0), X_MASK
, PWRCOM
, 0, {RA
, RS
, RB
}},
6635 {"sraw.", XRC(31,792,1), X_MASK
, PPCCOM
, 0, {RA
, RS
, RB
}},
6636 {"sra.", XRC(31,792,1), X_MASK
, PWRCOM
, 0, {RA
, RS
, RB
}},
6638 {"srad", XRC(31,794,0), X_MASK
, PPC64
, 0, {RA
, RS
, RB
}},
6639 {"srad.", XRC(31,794,1), X_MASK
, PPC64
, 0, {RA
, RS
, RB
}},
6641 {"evlddepx", VX (31, 1598), VX_MASK
, PPCSPE
, 0, {RT
, RA
, RB
}},
6642 {"lfddx", X(31,803), X_MASK
, E500MC
, 0, {FRT
, RA
, RB
}},
6644 {"lvtrxl", X(31,805), X_MASK
, E6500
, 0, {VD
, RA0
, RB
}},
6645 {"stvepx", X(31,807), X_MASK
, E6500
, 0, {VS
, RA0
, RB
}},
6646 {"lvrxl", X(31,807), X_MASK
, CELL
, 0, {VD
, RA0
, RB
}},
6648 {"lxvh8x", X(31,812), XX1_MASK
, PPCVSX3
, 0, {XT6
, RA0
, RB
}},
6649 {"lxsihzx", X(31,813), XX1_MASK
, PPCVSX3
, 0, {XT6
, RA0
, RB
}},
6651 {"tabortdc.", XRC(31,814,1), X_MASK
, PPCHTM
, 0, {TO
, RA
, RB
}},
6653 {"rac", X(31,818), X_MASK
, M601
, 0, {RT
, RA
, RB
}},
6655 {"erativax", X(31,819), X_MASK
, PPCA2
, 0, {RS
, RA0
, RB
}},
6657 {"lhzcix", X(31,821), X_MASK
, POWER6
, 0, {RT
, RA0
, RB
}},
6659 {"dss", XDSS(31,822,0), XDSS_MASK
, PPCVEC
, 0, {STRM
}},
6661 {"lfqux", X(31,823), X_MASK
, POWER2
, 0, {FRT
, RA
, RB
}},
6663 {"srawi", XRC(31,824,0), X_MASK
, PPCCOM
, 0, {RA
, RS
, SH
}},
6664 {"srai", XRC(31,824,0), X_MASK
, PWRCOM
, 0, {RA
, RS
, SH
}},
6665 {"srawi.", XRC(31,824,1), X_MASK
, PPCCOM
, 0, {RA
, RS
, SH
}},
6666 {"srai.", XRC(31,824,1), X_MASK
, PWRCOM
, 0, {RA
, RS
, SH
}},
6668 {"sradi", XS(31,413,0), XS_MASK
, PPC64
, 0, {RA
, RS
, SH6
}},
6669 {"sradi.", XS(31,413,1), XS_MASK
, PPC64
, 0, {RA
, RS
, SH6
}},
6671 {"lvtlxl", X(31,837), X_MASK
, E6500
, 0, {VD
, RA0
, RB
}},
6673 {"cpabort", X(31,838), XRTRARB_MASK
,POWER9
, 0, {0}},
6675 {"divo", XO(31,331,1,0), XO_MASK
, M601
, 0, {RT
, RA
, RB
}},
6676 {"divo.", XO(31,331,1,1), XO_MASK
, M601
, 0, {RT
, RA
, RB
}},
6678 {"lxvd2x", X(31,844), XX1_MASK
, PPCVSX
, 0, {XT6
, RA0
, RB
}},
6679 {"lxvx", X(31,844), XX1_MASK
, POWER8
, POWER9
|PPCVSX3
, {XT6
, RA0
, RB
}},
6681 {"tabortwci.", XRC(31,846,1), X_MASK
, PPCHTM
, 0, {TO
, RA
, HTM_SI
}},
6683 {"tlbsrx.", XRC(31,850,1), XRT_MASK
, PPCA2
, 0, {RA0
, RB
}},
6685 {"slbiag", X(31,850), XRARB_MASK
, POWER9
, 0, {RS
}},
6686 {"slbmfev", X(31,851), XRLA_MASK
, POWER9
, 0, {RT
, RB
, A_L
}},
6687 {"slbmfev", X(31,851), XRA_MASK
, PPC64
, POWER9
, {RT
, RB
}},
6689 {"lbzcix", X(31,853), X_MASK
, POWER6
, 0, {RT
, RA0
, RB
}},
6691 {"eieio", X(31,854), 0xffffffff, PPC
, BOOKE
|PPCA2
|PPC476
, {0}},
6692 {"mbar", X(31,854), X_MASK
, BOOKE
|PPCA2
|PPC476
, 0, {MO
}},
6693 {"eieio", XMBAR(31,854,1),0xffffffff, E500
, 0, {0}},
6694 {"eieio", X(31,854), 0xffffffff, PPCA2
|PPC476
, 0, {0}},
6696 {"lfiwax", X(31,855), X_MASK
, POWER6
|PPCA2
|PPC476
, 0, {FRT
, RA0
, RB
}},
6698 {"lvswxl", X(31,869), X_MASK
, E6500
, 0, {VD
, RA0
, RB
}},
6700 {"abso", XO(31,360,1,0), XORB_MASK
, M601
, 0, {RT
, RA
}},
6701 {"abso.", XO(31,360,1,1), XORB_MASK
, M601
, 0, {RT
, RA
}},
6703 {"divso", XO(31,363,1,0), XO_MASK
, M601
, 0, {RT
, RA
, RB
}},
6704 {"divso.", XO(31,363,1,1), XO_MASK
, M601
, 0, {RT
, RA
, RB
}},
6706 {"lxvb16x", X(31,876), XX1_MASK
, PPCVSX3
, 0, {XT6
, RA0
, RB
}},
6708 {"tabortdci.", XRC(31,878,1), X_MASK
, PPCHTM
, 0, {TO
, RA
, HTM_SI
}},
6710 {"rmieg", X(31,882), XRTRA_MASK
, POWER9
, 0, {RB
}},
6712 {"ldcix", X(31,885), X_MASK
, POWER6
, 0, {RT
, RA0
, RB
}},
6714 {"msgsync", X(31,886), 0xffffffff, POWER9
, 0, {0}},
6716 {"lfiwzx", X(31,887), X_MASK
, POWER7
|PPCA2
, 0, {FRT
, RA0
, RB
}},
6718 {"extswsli", XS(31,445,0), XS_MASK
, POWER9
, 0, {RA
, RS
, SH6
}},
6719 {"extswsli.", XS(31,445,1), XS_MASK
, POWER9
, 0, {RA
, RS
, SH6
}},
6721 {"paste.", XRCL(31,902,1,1),XRT_MASK
, POWER9
, 0, {RA0
, RB
}},
6723 {"stvlxl", X(31,903), X_MASK
, CELL
, 0, {VS
, RA0
, RB
}},
6724 {"stdfcmux", APU(31,903,0), APU_MASK
, PPC405
, 0, {FCRT
, RA
, RB
}},
6726 {"divdeuo", XO(31,393,1,0), XO_MASK
, POWER7
|PPCA2
, 0, {RT
, RA
, RB
}},
6727 {"divdeuo.", XO(31,393,1,1), XO_MASK
, POWER7
|PPCA2
, 0, {RT
, RA
, RB
}},
6728 {"divweuo", XO(31,395,1,0), XO_MASK
, POWER7
|PPCA2
, 0, {RT
, RA
, RB
}},
6729 {"divweuo.", XO(31,395,1,1), XO_MASK
, POWER7
|PPCA2
, 0, {RT
, RA
, RB
}},
6731 {"stxvw4x", X(31,908), XX1_MASK
, PPCVSX
, 0, {XS6
, RA0
, RB
}},
6732 {"stxsibx", X(31,909), XX1_MASK
, PPCVSX3
, 0, {XS6
, RA0
, RB
}},
6734 {"tabort.", XRC(31,910,1), XRTRB_MASK
, PPCHTM
, 0, {RA
}},
6736 {"tlbsx", XRC(31,914,0), X_MASK
, PPC403
|BOOKE
|PPCA2
|PPC476
, 0, {RTO
, RA0
, RB
}},
6737 {"tlbsx.", XRC(31,914,1), X_MASK
, PPC403
|BOOKE
|PPCA2
|PPC476
, 0, {RTO
, RA0
, RB
}},
6739 {"slbmfee", X(31,915), XRLA_MASK
, POWER9
, 0, {RT
, RB
, A_L
}},
6740 {"slbmfee", X(31,915), XRA_MASK
, PPC64
, POWER9
, {RT
, RB
}},
6742 {"stwcix", X(31,917), X_MASK
, POWER6
, 0, {RS
, RA0
, RB
}},
6744 {"sthbrx", X(31,918), X_MASK
, COM
, 0, {RS
, RA0
, RB
}},
6746 {"stfdpx", X(31,919), X_MASK
|Q_MASK
, POWER6
, POWER7
, {FRSp
, RA0
, RB
}},
6747 {"stfqx", X(31,919), X_MASK
, POWER2
, 0, {FRS
, RA0
, RB
}},
6749 {"sraq", XRC(31,920,0), X_MASK
, M601
, 0, {RA
, RS
, RB
}},
6750 {"sraq.", XRC(31,920,1), X_MASK
, M601
, 0, {RA
, RS
, RB
}},
6752 {"srea", XRC(31,921,0), X_MASK
, M601
, 0, {RA
, RS
, RB
}},
6753 {"srea.", XRC(31,921,1), X_MASK
, M601
, 0, {RA
, RS
, RB
}},
6755 {"extsh", XRC(31,922,0), XRB_MASK
, PPCCOM
, 0, {RA
, RS
}},
6756 {"exts", XRC(31,922,0), XRB_MASK
, PWRCOM
, 0, {RA
, RS
}},
6757 {"extsh.", XRC(31,922,1), XRB_MASK
, PPCCOM
, 0, {RA
, RS
}},
6758 {"exts.", XRC(31,922,1), XRB_MASK
, PWRCOM
, 0, {RA
, RS
}},
6760 {"evstddepx", VX (31, 1854), VX_MASK
, PPCSPE
, 0, {RT
, RA
, RB
}},
6761 {"stfddx", X(31,931), X_MASK
, E500MC
, 0, {FRS
, RA
, RB
}},
6763 {"stvfrxl", X(31,933), X_MASK
, E6500
, 0, {VS
, RA0
, RB
}},
6765 {"wclrone", XOPL2(31,934,2),XRT_MASK
, PPCA2
, 0, {RA0
, RB
}},
6766 {"wclrall", X(31,934), XRARB_MASK
, PPCA2
, 0, {L2
}},
6767 {"wclr", X(31,934), X_MASK
, PPCA2
, 0, {L2
, RA0
, RB
}},
6769 {"stvrxl", X(31,935), X_MASK
, CELL
, 0, {VS
, RA0
, RB
}},
6771 {"divdeo", XO(31,425,1,0), XO_MASK
, POWER7
|PPCA2
, 0, {RT
, RA
, RB
}},
6772 {"divdeo.", XO(31,425,1,1), XO_MASK
, POWER7
|PPCA2
, 0, {RT
, RA
, RB
}},
6773 {"divweo", XO(31,427,1,0), XO_MASK
, POWER7
|PPCA2
, 0, {RT
, RA
, RB
}},
6774 {"divweo.", XO(31,427,1,1), XO_MASK
, POWER7
|PPCA2
, 0, {RT
, RA
, RB
}},
6776 {"stxvh8x", X(31,940), XX1_MASK
, PPCVSX3
, 0, {XS6
, RA0
, RB
}},
6777 {"stxsihx", X(31,941), XX1_MASK
, PPCVSX3
, 0, {XS6
, RA0
, RB
}},
6779 {"treclaim.", XRC(31,942,1), XRTRB_MASK
, PPCHTM
, 0, {RA
}},
6781 {"tlbrehi", XTLB(31,946,0), XTLB_MASK
, PPC403
, PPCA2
, {RT
, RA
}},
6782 {"tlbrelo", XTLB(31,946,1), XTLB_MASK
, PPC403
, PPCA2
, {RT
, RA
}},
6783 {"tlbre", X(31,946), X_MASK
, PPC403
|BOOKE
|PPCA2
|PPC476
, 0, {RSO
, RAOPT
, SHO
}},
6785 {"sthcix", X(31,949), X_MASK
, POWER6
, 0, {RS
, RA0
, RB
}},
6787 {"icswepx", XRC(31,950,0), X_MASK
, PPCA2
, 0, {RS
, RA
, RB
}},
6788 {"icswepx.", XRC(31,950,1), X_MASK
, PPCA2
, 0, {RS
, RA
, RB
}},
6790 {"stfqux", X(31,951), X_MASK
, POWER2
, 0, {FRS
, RA
, RB
}},
6792 {"sraiq", XRC(31,952,0), X_MASK
, M601
, 0, {RA
, RS
, SH
}},
6793 {"sraiq.", XRC(31,952,1), X_MASK
, M601
, 0, {RA
, RS
, SH
}},
6795 {"extsb", XRC(31,954,0), XRB_MASK
, PPC
, 0, {RA
, RS
}},
6796 {"extsb.", XRC(31,954,1), XRB_MASK
, PPC
, 0, {RA
, RS
}},
6798 {"stvflxl", X(31,965), X_MASK
, E6500
, 0, {VS
, RA0
, RB
}},
6800 {"iccci", X(31,966), XRT_MASK
, PPC403
|PPC440
|PPC476
|TITAN
|PPCA2
, 0, {RAOPT
, RBOPT
}},
6801 {"ici", X(31,966), XRARB_MASK
, PPCA2
|PPC476
, 0, {CT
}},
6803 {"divduo", XO(31,457,1,0), XO_MASK
, PPC64
, 0, {RT
, RA
, RB
}},
6804 {"divduo.", XO(31,457,1,1), XO_MASK
, PPC64
, 0, {RT
, RA
, RB
}},
6806 {"divwuo", XO(31,459,1,0), XO_MASK
, PPC
, 0, {RT
, RA
, RB
}},
6807 {"divwuo.", XO(31,459,1,1), XO_MASK
, PPC
, 0, {RT
, RA
, RB
}},
6809 {"stxvd2x", X(31,972), XX1_MASK
, PPCVSX
, 0, {XS6
, RA0
, RB
}},
6810 {"stxvx", X(31,972), XX1_MASK
, POWER8
, POWER9
|PPCVSX3
, {XS6
, RA0
, RB
}},
6812 {"tlbld", X(31,978), XRTRA_MASK
, PPC
, PPC403
|BOOKE
|PPCA2
|PPC476
, {RB
}},
6813 {"tlbwehi", XTLB(31,978,0), XTLB_MASK
, PPC403
, 0, {RT
, RA
}},
6814 {"tlbwelo", XTLB(31,978,1), XTLB_MASK
, PPC403
, 0, {RT
, RA
}},
6815 {"tlbwe", X(31,978), X_MASK
, PPC403
|BOOKE
|PPCA2
|PPC476
, 0, {RSO
, RAOPT
, SHO
}},
6817 {"slbfee.", XRC(31,979,1), XRA_MASK
, POWER6
, 0, {RT
, RB
}},
6819 {"stbcix", X(31,981), X_MASK
, POWER6
, 0, {RS
, RA0
, RB
}},
6821 {"icbi", X(31,982), XRT_MASK
, PPC
, 0, {RA0
, RB
}},
6823 {"stfiwx", X(31,983), X_MASK
, PPC
, PPCEFS
, {FRS
, RA0
, RB
}},
6825 {"extsw", XRC(31,986,0), XRB_MASK
, PPC64
, 0, {RA
, RS
}},
6826 {"extsw.", XRC(31,986,1), XRB_MASK
, PPC64
, 0, {RA
, RS
}},
6828 {"icbiep", XRT(31,991,0), XRT_MASK
, E500MC
|PPCA2
, 0, {RA0
, RB
}},
6830 {"stvswxl", X(31,997), X_MASK
, E6500
, 0, {VS
, RA0
, RB
}},
6832 {"icread", X(31,998), XRT_MASK
, PPC403
|PPC440
|PPC476
|TITAN
, 0, {RA0
, RB
}},
6834 {"nabso", XO(31,488,1,0), XORB_MASK
, M601
, 0, {RT
, RA
}},
6835 {"nabso.", XO(31,488,1,1), XORB_MASK
, M601
, 0, {RT
, RA
}},
6837 {"divdo", XO(31,489,1,0), XO_MASK
, PPC64
, 0, {RT
, RA
, RB
}},
6838 {"divdo.", XO(31,489,1,1), XO_MASK
, PPC64
, 0, {RT
, RA
, RB
}},
6840 {"divwo", XO(31,491,1,0), XO_MASK
, PPC
, 0, {RT
, RA
, RB
}},
6841 {"divwo.", XO(31,491,1,1), XO_MASK
, PPC
, 0, {RT
, RA
, RB
}},
6843 {"stxvb16x", X(31,1004), XX1_MASK
, PPCVSX3
, 0, {XS6
, RA0
, RB
}},
6845 {"trechkpt.", XRC(31,1006,1), XRTRARB_MASK
,PPCHTM
, 0, {0}},
6847 {"tlbli", X(31,1010), XRTRA_MASK
, PPC
, TITAN
, {RB
}},
6849 {"stdcix", X(31,1013), X_MASK
, POWER6
, 0, {RS
, RA0
, RB
}},
6851 {"dcbz", X(31,1014), XRT_MASK
, PPC
, 0, {RA0
, RB
}},
6852 {"dclz", X(31,1014), XRT_MASK
, PPC
, 0, {RA0
, RB
}},
6854 {"dcbzep", XRT(31,1023,0), XRT_MASK
, E500MC
|PPCA2
, 0, {RA0
, RB
}},
6856 {"dcbzl", XOPL(31,1014,1), XRT_MASK
, POWER4
|E500MC
, PPC476
, {RA0
, RB
}},
6858 {"cctpl", 0x7c210b78, 0xffffffff, CELL
, 0, {0}},
6859 {"cctpm", 0x7c421378, 0xffffffff, CELL
, 0, {0}},
6860 {"cctph", 0x7c631b78, 0xffffffff, CELL
, 0, {0}},
6862 {"dstt", XDSS(31,342,1), XDSS_MASK
, PPCVEC
, 0, {RA
, RB
, STRM
}},
6863 {"dststt", XDSS(31,374,1), XDSS_MASK
, PPCVEC
, 0, {RA
, RB
, STRM
}},
6864 {"dssall", XDSS(31,822,1), XDSS_MASK
, PPCVEC
, 0, {0}},
6866 {"db8cyc", 0x7f9ce378, 0xffffffff, CELL
, 0, {0}},
6867 {"db10cyc", 0x7fbdeb78, 0xffffffff, CELL
, 0, {0}},
6868 {"db12cyc", 0x7fdef378, 0xffffffff, CELL
, 0, {0}},
6869 {"db16cyc", 0x7ffffb78, 0xffffffff, CELL
, 0, {0}},
6871 {"lwz", OP(32), OP_MASK
, PPCCOM
, PPCVLE
, {RT
, D
, RA0
}},
6872 {"l", OP(32), OP_MASK
, PWRCOM
, PPCVLE
, {RT
, D
, RA0
}},
6874 {"lwzu", OP(33), OP_MASK
, PPCCOM
, PPCVLE
, {RT
, D
, RAL
}},
6875 {"lu", OP(33), OP_MASK
, PWRCOM
, PPCVLE
, {RT
, D
, RA0
}},
6877 {"lbz", OP(34), OP_MASK
, COM
, PPCVLE
, {RT
, D
, RA0
}},
6879 {"lbzu", OP(35), OP_MASK
, COM
, PPCVLE
, {RT
, D
, RAL
}},
6881 {"stw", OP(36), OP_MASK
, PPCCOM
, PPCVLE
, {RS
, D
, RA0
}},
6882 {"st", OP(36), OP_MASK
, PWRCOM
, PPCVLE
, {RS
, D
, RA0
}},
6884 {"stwu", OP(37), OP_MASK
, PPCCOM
, PPCVLE
, {RS
, D
, RAS
}},
6885 {"stu", OP(37), OP_MASK
, PWRCOM
, PPCVLE
, {RS
, D
, RA0
}},
6887 {"stb", OP(38), OP_MASK
, COM
, PPCVLE
, {RS
, D
, RA0
}},
6889 {"stbu", OP(39), OP_MASK
, COM
, PPCVLE
, {RS
, D
, RAS
}},
6891 {"lhz", OP(40), OP_MASK
, COM
, PPCVLE
, {RT
, D
, RA0
}},
6893 {"lhzu", OP(41), OP_MASK
, COM
, PPCVLE
, {RT
, D
, RAL
}},
6895 {"lha", OP(42), OP_MASK
, COM
, PPCVLE
, {RT
, D
, RA0
}},
6897 {"lhau", OP(43), OP_MASK
, COM
, PPCVLE
, {RT
, D
, RAL
}},
6899 {"sth", OP(44), OP_MASK
, COM
, PPCVLE
, {RS
, D
, RA0
}},
6901 {"sthu", OP(45), OP_MASK
, COM
, PPCVLE
, {RS
, D
, RAS
}},
6903 {"lmw", OP(46), OP_MASK
, PPCCOM
, PPCVLE
, {RT
, D
, RAM
}},
6904 {"lm", OP(46), OP_MASK
, PWRCOM
, PPCVLE
, {RT
, D
, RA0
}},
6906 {"stmw", OP(47), OP_MASK
, PPCCOM
, PPCVLE
, {RS
, D
, RA0
}},
6907 {"stm", OP(47), OP_MASK
, PWRCOM
, PPCVLE
, {RS
, D
, RA0
}},
6909 {"lfs", OP(48), OP_MASK
, COM
, PPCEFS
|PPCVLE
, {FRT
, D
, RA0
}},
6911 {"lfsu", OP(49), OP_MASK
, COM
, PPCEFS
|PPCVLE
, {FRT
, D
, RAS
}},
6913 {"lfd", OP(50), OP_MASK
, COM
, PPCEFS
|PPCVLE
, {FRT
, D
, RA0
}},
6915 {"lfdu", OP(51), OP_MASK
, COM
, PPCEFS
|PPCVLE
, {FRT
, D
, RAS
}},
6917 {"stfs", OP(52), OP_MASK
, COM
, PPCEFS
|PPCVLE
, {FRS
, D
, RA0
}},
6919 {"stfsu", OP(53), OP_MASK
, COM
, PPCEFS
|PPCVLE
, {FRS
, D
, RAS
}},
6921 {"stfd", OP(54), OP_MASK
, COM
, PPCEFS
|PPCVLE
, {FRS
, D
, RA0
}},
6923 {"stfdu", OP(55), OP_MASK
, COM
, PPCEFS
|PPCVLE
, {FRS
, D
, RAS
}},
6925 {"lq", OP(56), OP_MASK
|Q_MASK
, POWER4
, PPC476
|PPCVLE
, {RTQ
, DQ
, RAQ
}},
6926 {"psq_l", OP(56), OP_MASK
, PPCPS
, PPCVLE
, {FRT
,PSD
,RA
,PSW
,PSQ
}},
6927 {"lfq", OP(56), OP_MASK
, POWER2
, PPCVLE
, {FRT
, D
, RA0
}},
6929 {"lxsd", DSO(57,2), DS_MASK
, PPCVSX3
, PPCVLE
, {VD
, DS
, RA0
}},
6930 {"lxssp", DSO(57,3), DS_MASK
, PPCVSX3
, PPCVLE
, {VD
, DS
, RA0
}},
6931 {"lfdp", OP(57), OP_MASK
|Q_MASK
, POWER6
, POWER7
|PPCVLE
, {FRTp
, DS
, RA0
}},
6932 {"psq_lu", OP(57), OP_MASK
, PPCPS
, PPCVLE
, {FRT
,PSD
,RA
,PSW
,PSQ
}},
6933 {"lfqu", OP(57), OP_MASK
, POWER2
, PPCVLE
, {FRT
, D
, RA0
}},
6935 {"ld", DSO(58,0), DS_MASK
, PPC64
, PPCVLE
, {RT
, DS
, RA0
}},
6936 {"ldu", DSO(58,1), DS_MASK
, PPC64
, PPCVLE
, {RT
, DS
, RAL
}},
6937 {"lwa", DSO(58,2), DS_MASK
, PPC64
, PPCVLE
, {RT
, DS
, RA0
}},
6939 {"dadd", XRC(59,2,0), X_MASK
, POWER6
, PPCVLE
, {FRT
, FRA
, FRB
}},
6940 {"dadd.", XRC(59,2,1), X_MASK
, POWER6
, PPCVLE
, {FRT
, FRA
, FRB
}},
6942 {"dqua", ZRC(59,3,0), Z2_MASK
, POWER6
, PPCVLE
, {FRT
,FRA
,FRB
,RMC
}},
6943 {"dqua.", ZRC(59,3,1), Z2_MASK
, POWER6
, PPCVLE
, {FRT
,FRA
,FRB
,RMC
}},
6945 {"fdivs", A(59,18,0), AFRC_MASK
, PPC
, PPCEFS
|PPCVLE
, {FRT
, FRA
, FRB
}},
6946 {"fdivs.", A(59,18,1), AFRC_MASK
, PPC
, PPCEFS
|PPCVLE
, {FRT
, FRA
, FRB
}},
6948 {"fsubs", A(59,20,0), AFRC_MASK
, PPC
, PPCEFS
|PPCVLE
, {FRT
, FRA
, FRB
}},
6949 {"fsubs.", A(59,20,1), AFRC_MASK
, PPC
, PPCEFS
|PPCVLE
, {FRT
, FRA
, FRB
}},
6951 {"fadds", A(59,21,0), AFRC_MASK
, PPC
, PPCEFS
|PPCVLE
, {FRT
, FRA
, FRB
}},
6952 {"fadds.", A(59,21,1), AFRC_MASK
, PPC
, PPCEFS
|PPCVLE
, {FRT
, FRA
, FRB
}},
6954 {"fsqrts", A(59,22,0), AFRAFRC_MASK
, PPC
, TITAN
|PPCVLE
, {FRT
, FRB
}},
6955 {"fsqrts.", A(59,22,1), AFRAFRC_MASK
, PPC
, TITAN
|PPCVLE
, {FRT
, FRB
}},
6957 {"fres", A(59,24,0), AFRAFRC_MASK
, POWER7
, PPCVLE
, {FRT
, FRB
}},
6958 {"fres", A(59,24,0), AFRALFRC_MASK
, PPC
, POWER7
|PPCVLE
, {FRT
, FRB
, A_L
}},
6959 {"fres.", A(59,24,1), AFRAFRC_MASK
, POWER7
, PPCVLE
, {FRT
, FRB
}},
6960 {"fres.", A(59,24,1), AFRALFRC_MASK
, PPC
, POWER7
|PPCVLE
, {FRT
, FRB
, A_L
}},
6962 {"fmuls", A(59,25,0), AFRB_MASK
, PPC
, PPCEFS
|PPCVLE
, {FRT
, FRA
, FRC
}},
6963 {"fmuls.", A(59,25,1), AFRB_MASK
, PPC
, PPCEFS
|PPCVLE
, {FRT
, FRA
, FRC
}},
6965 {"frsqrtes", A(59,26,0), AFRAFRC_MASK
, POWER7
, PPCVLE
, {FRT
, FRB
}},
6966 {"frsqrtes", A(59,26,0), AFRALFRC_MASK
, POWER5
, POWER7
|PPCVLE
, {FRT
, FRB
, A_L
}},
6967 {"frsqrtes.", A(59,26,1), AFRAFRC_MASK
, POWER7
, PPCVLE
, {FRT
, FRB
}},
6968 {"frsqrtes.", A(59,26,1), AFRALFRC_MASK
, POWER5
, POWER7
|PPCVLE
, {FRT
, FRB
, A_L
}},
6970 {"fmsubs", A(59,28,0), A_MASK
, PPC
, PPCEFS
|PPCVLE
, {FRT
, FRA
, FRC
, FRB
}},
6971 {"fmsubs.", A(59,28,1), A_MASK
, PPC
, PPCEFS
|PPCVLE
, {FRT
, FRA
, FRC
, FRB
}},
6973 {"fmadds", A(59,29,0), A_MASK
, PPC
, PPCEFS
|PPCVLE
, {FRT
, FRA
, FRC
, FRB
}},
6974 {"fmadds.", A(59,29,1), A_MASK
, PPC
, PPCEFS
|PPCVLE
, {FRT
, FRA
, FRC
, FRB
}},
6976 {"fnmsubs", A(59,30,0), A_MASK
, PPC
, PPCEFS
|PPCVLE
, {FRT
, FRA
, FRC
, FRB
}},
6977 {"fnmsubs.", A(59,30,1), A_MASK
, PPC
, PPCEFS
|PPCVLE
, {FRT
, FRA
, FRC
, FRB
}},
6979 {"fnmadds", A(59,31,0), A_MASK
, PPC
, PPCEFS
|PPCVLE
, {FRT
, FRA
, FRC
, FRB
}},
6980 {"fnmadds.", A(59,31,1), A_MASK
, PPC
, PPCEFS
|PPCVLE
, {FRT
, FRA
, FRC
, FRB
}},
6982 {"dmul", XRC(59,34,0), X_MASK
, POWER6
, PPCVLE
, {FRT
, FRA
, FRB
}},
6983 {"dmul.", XRC(59,34,1), X_MASK
, POWER6
, PPCVLE
, {FRT
, FRA
, FRB
}},
6985 {"drrnd", ZRC(59,35,0), Z2_MASK
, POWER6
, PPCVLE
, {FRT
, FRA
, FRB
, RMC
}},
6986 {"drrnd.", ZRC(59,35,1), Z2_MASK
, POWER6
, PPCVLE
, {FRT
, FRA
, FRB
, RMC
}},
6988 {"dscli", ZRC(59,66,0), Z_MASK
, POWER6
, PPCVLE
, {FRT
, FRA
, SH16
}},
6989 {"dscli.", ZRC(59,66,1), Z_MASK
, POWER6
, PPCVLE
, {FRT
, FRA
, SH16
}},
6991 {"dquai", ZRC(59,67,0), Z2_MASK
, POWER6
, PPCVLE
, {TE
, FRT
,FRB
,RMC
}},
6992 {"dquai.", ZRC(59,67,1), Z2_MASK
, POWER6
, PPCVLE
, {TE
, FRT
,FRB
,RMC
}},
6994 {"dscri", ZRC(59,98,0), Z_MASK
, POWER6
, PPCVLE
, {FRT
, FRA
, SH16
}},
6995 {"dscri.", ZRC(59,98,1), Z_MASK
, POWER6
, PPCVLE
, {FRT
, FRA
, SH16
}},
6997 {"drintx", ZRC(59,99,0), Z2_MASK
, POWER6
, PPCVLE
, {R
, FRT
, FRB
, RMC
}},
6998 {"drintx.", ZRC(59,99,1), Z2_MASK
, POWER6
, PPCVLE
, {R
, FRT
, FRB
, RMC
}},
7000 {"dcmpo", X(59,130), X_MASK
, POWER6
, PPCVLE
, {BF
, FRA
, FRB
}},
7002 {"dtstex", X(59,162), X_MASK
, POWER6
, PPCVLE
, {BF
, FRA
, FRB
}},
7003 {"dtstdc", Z(59,194), Z_MASK
, POWER6
, PPCVLE
, {BF
, FRA
, DCM
}},
7004 {"dtstdg", Z(59,226), Z_MASK
, POWER6
, PPCVLE
, {BF
, FRA
, DGM
}},
7006 {"drintn", ZRC(59,227,0), Z2_MASK
, POWER6
, PPCVLE
, {R
, FRT
, FRB
, RMC
}},
7007 {"drintn.", ZRC(59,227,1), Z2_MASK
, POWER6
, PPCVLE
, {R
, FRT
, FRB
, RMC
}},
7009 {"dctdp", XRC(59,258,0), X_MASK
, POWER6
, PPCVLE
, {FRT
, FRB
}},
7010 {"dctdp.", XRC(59,258,1), X_MASK
, POWER6
, PPCVLE
, {FRT
, FRB
}},
7012 {"dctfix", XRC(59,290,0), X_MASK
, POWER6
, PPCVLE
, {FRT
, FRB
}},
7013 {"dctfix.", XRC(59,290,1), X_MASK
, POWER6
, PPCVLE
, {FRT
, FRB
}},
7015 {"ddedpd", XRC(59,322,0), X_MASK
, POWER6
, PPCVLE
, {SP
, FRT
, FRB
}},
7016 {"ddedpd.", XRC(59,322,1), X_MASK
, POWER6
, PPCVLE
, {SP
, FRT
, FRB
}},
7018 {"dxex", XRC(59,354,0), X_MASK
, POWER6
, PPCVLE
, {FRT
, FRB
}},
7019 {"dxex.", XRC(59,354,1), X_MASK
, POWER6
, PPCVLE
, {FRT
, FRB
}},
7021 {"dsub", XRC(59,514,0), X_MASK
, POWER6
, PPCVLE
, {FRT
, FRA
, FRB
}},
7022 {"dsub.", XRC(59,514,1), X_MASK
, POWER6
, PPCVLE
, {FRT
, FRA
, FRB
}},
7024 {"ddiv", XRC(59,546,0), X_MASK
, POWER6
, PPCVLE
, {FRT
, FRA
, FRB
}},
7025 {"ddiv.", XRC(59,546,1), X_MASK
, POWER6
, PPCVLE
, {FRT
, FRA
, FRB
}},
7027 {"dcmpu", X(59,642), X_MASK
, POWER6
, PPCVLE
, {BF
, FRA
, FRB
}},
7029 {"dtstsf", X(59,674), X_MASK
, POWER6
, PPCVLE
, {BF
, FRA
, FRB
}},
7030 {"dtstsfi", X(59,675), X_MASK
|1<<22,POWER9
, PPCVLE
, {BF
, UIM6
, FRB
}},
7032 {"drsp", XRC(59,770,0), X_MASK
, POWER6
, PPCVLE
, {FRT
, FRB
}},
7033 {"drsp.", XRC(59,770,1), X_MASK
, POWER6
, PPCVLE
, {FRT
, FRB
}},
7035 {"dcffix", XRC(59,802,0), X_MASK
|FRA_MASK
, POWER7
, PPCVLE
, {FRT
, FRB
}},
7036 {"dcffix.", XRC(59,802,1), X_MASK
|FRA_MASK
, POWER7
, PPCVLE
, {FRT
, FRB
}},
7038 {"denbcd", XRC(59,834,0), X_MASK
, POWER6
, PPCVLE
, {S
, FRT
, FRB
}},
7039 {"denbcd.", XRC(59,834,1), X_MASK
, POWER6
, PPCVLE
, {S
, FRT
, FRB
}},
7041 {"fcfids", XRC(59,846,0), XRA_MASK
, POWER7
|PPCA2
, PPCVLE
, {FRT
, FRB
}},
7042 {"fcfids.", XRC(59,846,1), XRA_MASK
, POWER7
|PPCA2
, PPCVLE
, {FRT
, FRB
}},
7044 {"diex", XRC(59,866,0), X_MASK
, POWER6
, PPCVLE
, {FRT
, FRA
, FRB
}},
7045 {"diex.", XRC(59,866,1), X_MASK
, POWER6
, PPCVLE
, {FRT
, FRA
, FRB
}},
7047 {"fcfidus", XRC(59,974,0), XRA_MASK
, POWER7
|PPCA2
, PPCVLE
, {FRT
, FRB
}},
7048 {"fcfidus.", XRC(59,974,1), XRA_MASK
, POWER7
|PPCA2
, PPCVLE
, {FRT
, FRB
}},
7050 {"xsaddsp", XX3(60,0), XX3_MASK
, PPCVSX2
, PPCVLE
, {XT6
, XA6
, XB6
}},
7051 {"xsmaddasp", XX3(60,1), XX3_MASK
, PPCVSX2
, PPCVLE
, {XT6
, XA6
, XB6
}},
7052 {"xxsldwi", XX3(60,2), XX3SHW_MASK
, PPCVSX
, PPCVLE
, {XT6
, XA6
, XB6
, SHW
}},
7053 {"xscmpeqdp", XX3(60,3), XX3_MASK
, PPCVSX3
, PPCVLE
, {XT6
, XA6
, XB6
}},
7054 {"xsrsqrtesp", XX2(60,10), XX2_MASK
, PPCVSX2
, PPCVLE
, {XT6
, XB6
}},
7055 {"xssqrtsp", XX2(60,11), XX2_MASK
, PPCVSX2
, PPCVLE
, {XT6
, XB6
}},
7056 {"xxsel", XX4(60,3), XX4_MASK
, PPCVSX
, PPCVLE
, {XT6
, XA6
, XB6
, XC6
}},
7057 {"xssubsp", XX3(60,8), XX3_MASK
, PPCVSX2
, PPCVLE
, {XT6
, XA6
, XB6
}},
7058 {"xsmaddmsp", XX3(60,9), XX3_MASK
, PPCVSX2
, PPCVLE
, {XT6
, XA6
, XB6
}},
7059 {"xxspltd", XX3(60,10), XX3DM_MASK
, PPCVSX
, PPCVLE
, {XT6
, XA6
, XB6S
, DMEX
}},
7060 {"xxmrghd", XX3(60,10), XX3_MASK
, PPCVSX
, PPCVLE
, {XT6
, XA6
, XB6
}},
7061 {"xxswapd", XX3(60,10)|(2<<8), XX3_MASK
, PPCVSX
, PPCVLE
, {XT6
, XA6
, XB6S
}},
7062 {"xxmrgld", XX3(60,10)|(3<<8), XX3_MASK
, PPCVSX
, PPCVLE
, {XT6
, XA6
, XB6
}},
7063 {"xxpermdi", XX3(60,10), XX3DM_MASK
, PPCVSX
, PPCVLE
, {XT6
, XA6
, XB6
, DM
}},
7064 {"xscmpgtdp", XX3(60,11), XX3_MASK
, PPCVSX3
, PPCVLE
, {XT6
, XA6
, XB6
}},
7065 {"xsresp", XX2(60,26), XX2_MASK
, PPCVSX2
, PPCVLE
, {XT6
, XB6
}},
7066 {"xsmulsp", XX3(60,16), XX3_MASK
, PPCVSX2
, PPCVLE
, {XT6
, XA6
, XB6
}},
7067 {"xsmsubasp", XX3(60,17), XX3_MASK
, PPCVSX2
, PPCVLE
, {XT6
, XA6
, XB6
}},
7068 {"xxmrghw", XX3(60,18), XX3_MASK
, PPCVSX
, PPCVLE
, {XT6
, XA6
, XB6
}},
7069 {"xscmpgedp", XX3(60,19), XX3_MASK
, PPCVSX3
, PPCVLE
, {XT6
, XA6
, XB6
}},
7070 {"xsdivsp", XX3(60,24), XX3_MASK
, PPCVSX2
, PPCVLE
, {XT6
, XA6
, XB6
}},
7071 {"xsmsubmsp", XX3(60,25), XX3_MASK
, PPCVSX2
, PPCVLE
, {XT6
, XA6
, XB6
}},
7072 {"xxperm", XX3(60,26), XX3_MASK
, PPCVSX3
, PPCVLE
, {XT6
, XA6
, XB6
}},
7073 {"xsadddp", XX3(60,32), XX3_MASK
, PPCVSX
, PPCVLE
, {XT6
, XA6
, XB6
}},
7074 {"xsmaddadp", XX3(60,33), XX3_MASK
, PPCVSX
, PPCVLE
, {XT6
, XA6
, XB6
}},
7075 {"xscmpudp", XX3(60,35), XX3BF_MASK
, PPCVSX
, PPCVLE
, {BF
, XA6
, XB6
}},
7076 {"xscvdpuxws", XX2(60,72), XX2_MASK
, PPCVSX
, PPCVLE
, {XT6
, XB6
}},
7077 {"xsrdpi", XX2(60,73), XX2_MASK
, PPCVSX
, PPCVLE
, {XT6
, XB6
}},
7078 {"xsrsqrtedp", XX2(60,74), XX2_MASK
, PPCVSX
, PPCVLE
, {XT6
, XB6
}},
7079 {"xssqrtdp", XX2(60,75), XX2_MASK
, PPCVSX
, PPCVLE
, {XT6
, XB6
}},
7080 {"xssubdp", XX3(60,40), XX3_MASK
, PPCVSX
, PPCVLE
, {XT6
, XA6
, XB6
}},
7081 {"xsmaddmdp", XX3(60,41), XX3_MASK
, PPCVSX
, PPCVLE
, {XT6
, XA6
, XB6
}},
7082 {"xscmpodp", XX3(60,43), XX3BF_MASK
, PPCVSX
, PPCVLE
, {BF
, XA6
, XB6
}},
7083 {"xscvdpsxws", XX2(60,88), XX2_MASK
, PPCVSX
, PPCVLE
, {XT6
, XB6
}},
7084 {"xsrdpiz", XX2(60,89), XX2_MASK
, PPCVSX
, PPCVLE
, {XT6
, XB6
}},
7085 {"xsredp", XX2(60,90), XX2_MASK
, PPCVSX
, PPCVLE
, {XT6
, XB6
}},
7086 {"xsmuldp", XX3(60,48), XX3_MASK
, PPCVSX
, PPCVLE
, {XT6
, XA6
, XB6
}},
7087 {"xsmsubadp", XX3(60,49), XX3_MASK
, PPCVSX
, PPCVLE
, {XT6
, XA6
, XB6
}},
7088 {"xxmrglw", XX3(60,50), XX3_MASK
, PPCVSX
, PPCVLE
, {XT6
, XA6
, XB6
}},
7089 {"xsrdpip", XX2(60,105), XX2_MASK
, PPCVSX
, PPCVLE
, {XT6
, XB6
}},
7090 {"xstsqrtdp", XX2(60,106), XX2BF_MASK
, PPCVSX
, PPCVLE
, {BF
, XB6
}},
7091 {"xsrdpic", XX2(60,107), XX2_MASK
, PPCVSX
, PPCVLE
, {XT6
, XB6
}},
7092 {"xsdivdp", XX3(60,56), XX3_MASK
, PPCVSX
, PPCVLE
, {XT6
, XA6
, XB6
}},
7093 {"xsmsubmdp", XX3(60,57), XX3_MASK
, PPCVSX
, PPCVLE
, {XT6
, XA6
, XB6
}},
7094 {"xxpermr", XX3(60,58), XX3_MASK
, PPCVSX3
, PPCVLE
, {XT6
, XA6
, XB6
}},
7095 {"xscmpexpdp", XX3(60,59), XX3BF_MASK
, PPCVSX3
, PPCVLE
, {BF
, XA6
, XB6
}},
7096 {"xsrdpim", XX2(60,121), XX2_MASK
, PPCVSX
, PPCVLE
, {XT6
, XB6
}},
7097 {"xstdivdp", XX3(60,61), XX3BF_MASK
, PPCVSX
, PPCVLE
, {BF
, XA6
, XB6
}},
7098 {"xvaddsp", XX3(60,64), XX3_MASK
, PPCVSX
, PPCVLE
, {XT6
, XA6
, XB6
}},
7099 {"xvmaddasp", XX3(60,65), XX3_MASK
, PPCVSX
, PPCVLE
, {XT6
, XA6
, XB6
}},
7100 {"xvcmpeqsp", XX3RC(60,67,0), XX3_MASK
, PPCVSX
, PPCVLE
, {XT6
, XA6
, XB6
}},
7101 {"xvcmpeqsp.", XX3RC(60,67,1), XX3_MASK
, PPCVSX
, PPCVLE
, {XT6
, XA6
, XB6
}},
7102 {"xvcvspuxws", XX2(60,136), XX2_MASK
, PPCVSX
, PPCVLE
, {XT6
, XB6
}},
7103 {"xvrspi", XX2(60,137), XX2_MASK
, PPCVSX
, PPCVLE
, {XT6
, XB6
}},
7104 {"xvrsqrtesp", XX2(60,138), XX2_MASK
, PPCVSX
, PPCVLE
, {XT6
, XB6
}},
7105 {"xvsqrtsp", XX2(60,139), XX2_MASK
, PPCVSX
, PPCVLE
, {XT6
, XB6
}},
7106 {"xvsubsp", XX3(60,72), XX3_MASK
, PPCVSX
, PPCVLE
, {XT6
, XA6
, XB6
}},
7107 {"xvmaddmsp", XX3(60,73), XX3_MASK
, PPCVSX
, PPCVLE
, {XT6
, XA6
, XB6
}},
7108 {"xvcmpgtsp", XX3RC(60,75,0), XX3_MASK
, PPCVSX
, PPCVLE
, {XT6
, XA6
, XB6
}},
7109 {"xvcmpgtsp.", XX3RC(60,75,1), XX3_MASK
, PPCVSX
, PPCVLE
, {XT6
, XA6
, XB6
}},
7110 {"xvcvspsxws", XX2(60,152), XX2_MASK
, PPCVSX
, PPCVLE
, {XT6
, XB6
}},
7111 {"xvrspiz", XX2(60,153), XX2_MASK
, PPCVSX
, PPCVLE
, {XT6
, XB6
}},
7112 {"xvresp", XX2(60,154), XX2_MASK
, PPCVSX
, PPCVLE
, {XT6
, XB6
}},
7113 {"xvmulsp", XX3(60,80), XX3_MASK
, PPCVSX
, PPCVLE
, {XT6
, XA6
, XB6
}},
7114 {"xvmsubasp", XX3(60,81), XX3_MASK
, PPCVSX
, PPCVLE
, {XT6
, XA6
, XB6
}},
7115 {"xxspltw", XX2(60,164), XX2UIM_MASK
, PPCVSX
, PPCVLE
, {XT6
, XB6
, UIM
}},
7116 {"xxextractuw", XX2(60,165), XX2UIM4_MASK
, PPCVSX3
, PPCVLE
, {XT6
, XB6
, UIMM4
}},
7117 {"xvcmpgesp", XX3RC(60,83,0), XX3_MASK
, PPCVSX
, PPCVLE
, {XT6
, XA6
, XB6
}},
7118 {"xvcmpgesp.", XX3RC(60,83,1), XX3_MASK
, PPCVSX
, PPCVLE
, {XT6
, XA6
, XB6
}},
7119 {"xvcvuxwsp", XX2(60,168), XX2_MASK
, PPCVSX
, PPCVLE
, {XT6
, XB6
}},
7120 {"xvrspip", XX2(60,169), XX2_MASK
, PPCVSX
, PPCVLE
, {XT6
, XB6
}},
7121 {"xvtsqrtsp", XX2(60,170), XX2BF_MASK
, PPCVSX
, PPCVLE
, {BF
, XB6
}},
7122 {"xvrspic", XX2(60,171), XX2_MASK
, PPCVSX
, PPCVLE
, {XT6
, XB6
}},
7123 {"xvdivsp", XX3(60,88), XX3_MASK
, PPCVSX
, PPCVLE
, {XT6
, XA6
, XB6
}},
7124 {"xvmsubmsp", XX3(60,89), XX3_MASK
, PPCVSX
, PPCVLE
, {XT6
, XA6
, XB6
}},
7125 {"xxspltib", X(60,360), XX1_MASK
|3<<19, PPCVSX3
, PPCVLE
, {XT6
, IMM8
}},
7126 {"xxinsertw", XX2(60,181), XX2UIM4_MASK
, PPCVSX3
, PPCVLE
, {XT6
, XB6
, UIMM4
}},
7127 {"xvcvsxwsp", XX2(60,184), XX2_MASK
, PPCVSX
, PPCVLE
, {XT6
, XB6
}},
7128 {"xvrspim", XX2(60,185), XX2_MASK
, PPCVSX
, PPCVLE
, {XT6
, XB6
}},
7129 {"xvtdivsp", XX3(60,93), XX3BF_MASK
, PPCVSX
, PPCVLE
, {BF
, XA6
, XB6
}},
7130 {"xvadddp", XX3(60,96), XX3_MASK
, PPCVSX
, PPCVLE
, {XT6
, XA6
, XB6
}},
7131 {"xvmaddadp", XX3(60,97), XX3_MASK
, PPCVSX
, PPCVLE
, {XT6
, XA6
, XB6
}},
7132 {"xvcmpeqdp", XX3RC(60,99,0), XX3_MASK
, PPCVSX
, PPCVLE
, {XT6
, XA6
, XB6
}},
7133 {"xvcmpeqdp.", XX3RC(60,99,1), XX3_MASK
, PPCVSX
, PPCVLE
, {XT6
, XA6
, XB6
}},
7134 {"xvcvdpuxws", XX2(60,200), XX2_MASK
, PPCVSX
, PPCVLE
, {XT6
, XB6
}},
7135 {"xvrdpi", XX2(60,201), XX2_MASK
, PPCVSX
, PPCVLE
, {XT6
, XB6
}},
7136 {"xvrsqrtedp", XX2(60,202), XX2_MASK
, PPCVSX
, PPCVLE
, {XT6
, XB6
}},
7137 {"xvsqrtdp", XX2(60,203), XX2_MASK
, PPCVSX
, PPCVLE
, {XT6
, XB6
}},
7138 {"xvsubdp", XX3(60,104), XX3_MASK
, PPCVSX
, PPCVLE
, {XT6
, XA6
, XB6
}},
7139 {"xvmaddmdp", XX3(60,105), XX3_MASK
, PPCVSX
, PPCVLE
, {XT6
, XA6
, XB6
}},
7140 {"xvcmpgtdp", XX3RC(60,107,0), XX3_MASK
, PPCVSX
, PPCVLE
, {XT6
, XA6
, XB6
}},
7141 {"xvcmpgtdp.", XX3RC(60,107,1), XX3_MASK
, PPCVSX
, PPCVLE
, {XT6
, XA6
, XB6
}},
7142 {"xvcvdpsxws", XX2(60,216), XX2_MASK
, PPCVSX
, PPCVLE
, {XT6
, XB6
}},
7143 {"xvrdpiz", XX2(60,217), XX2_MASK
, PPCVSX
, PPCVLE
, {XT6
, XB6
}},
7144 {"xvredp", XX2(60,218), XX2_MASK
, PPCVSX
, PPCVLE
, {XT6
, XB6
}},
7145 {"xvmuldp", XX3(60,112), XX3_MASK
, PPCVSX
, PPCVLE
, {XT6
, XA6
, XB6
}},
7146 {"xvmsubadp", XX3(60,113), XX3_MASK
, PPCVSX
, PPCVLE
, {XT6
, XA6
, XB6
}},
7147 {"xvcmpgedp", XX3RC(60,115,0), XX3_MASK
, PPCVSX
, PPCVLE
, {XT6
, XA6
, XB6
}},
7148 {"xvcmpgedp.", XX3RC(60,115,1), XX3_MASK
, PPCVSX
, PPCVLE
, {XT6
, XA6
, XB6
}},
7149 {"xvcvuxwdp", XX2(60,232), XX2_MASK
, PPCVSX
, PPCVLE
, {XT6
, XB6
}},
7150 {"xvrdpip", XX2(60,233), XX2_MASK
, PPCVSX
, PPCVLE
, {XT6
, XB6
}},
7151 {"xvtsqrtdp", XX2(60,234), XX2BF_MASK
, PPCVSX
, PPCVLE
, {BF
, XB6
}},
7152 {"xvrdpic", XX2(60,235), XX2_MASK
, PPCVSX
, PPCVLE
, {XT6
, XB6
}},
7153 {"xvdivdp", XX3(60,120), XX3_MASK
, PPCVSX
, PPCVLE
, {XT6
, XA6
, XB6
}},
7154 {"xvmsubmdp", XX3(60,121), XX3_MASK
, PPCVSX
, PPCVLE
, {XT6
, XA6
, XB6
}},
7155 {"xvcvsxwdp", XX2(60,248), XX2_MASK
, PPCVSX
, PPCVLE
, {XT6
, XB6
}},
7156 {"xvrdpim", XX2(60,249), XX2_MASK
, PPCVSX
, PPCVLE
, {XT6
, XB6
}},
7157 {"xvtdivdp", XX3(60,125), XX3BF_MASK
, PPCVSX
, PPCVLE
, {BF
, XA6
, XB6
}},
7158 {"xsmaxcdp", XX3(60,128), XX3_MASK
, PPCVSX3
, PPCVLE
, {XT6
, XA6
, XB6
}},
7159 {"xsnmaddasp", XX3(60,129), XX3_MASK
, PPCVSX2
, PPCVLE
, {XT6
, XA6
, XB6
}},
7160 {"xxland", XX3(60,130), XX3_MASK
, PPCVSX
, PPCVLE
, {XT6
, XA6
, XB6
}},
7161 {"xscvdpsp", XX2(60,265), XX2_MASK
, PPCVSX
, PPCVLE
, {XT6
, XB6
}},
7162 {"xscvdpspn", XX2(60,267), XX2_MASK
, PPCVSX2
, PPCVLE
, {XT6
, XB6
}},
7163 {"xsmincdp", XX3(60,136), XX3_MASK
, PPCVSX3
, PPCVLE
, {XT6
, XA6
, XB6
}},
7164 {"xsnmaddmsp", XX3(60,137), XX3_MASK
, PPCVSX2
, PPCVLE
, {XT6
, XA6
, XB6
}},
7165 {"xxlandc", XX3(60,138), XX3_MASK
, PPCVSX
, PPCVLE
, {XT6
, XA6
, XB6
}},
7166 {"xsrsp", XX2(60,281), XX2_MASK
, PPCVSX2
, PPCVLE
, {XT6
, XB6
}},
7167 {"xsmaxjdp", XX3(60,144), XX3_MASK
, PPCVSX3
, PPCVLE
, {XT6
, XA6
, XB6
}},
7168 {"xsnmsubasp", XX3(60,145), XX3_MASK
, PPCVSX2
, PPCVLE
, {XT6
, XA6
, XB6
}},
7169 {"xxlor", XX3(60,146), XX3_MASK
, PPCVSX
, PPCVLE
, {XT6
, XA6
, XB6
}},
7170 {"xscvuxdsp", XX2(60,296), XX2_MASK
, PPCVSX2
, PPCVLE
, {XT6
, XB6
}},
7171 {"xststdcsp", XX2(60,298), XX2BFD_MASK
, PPCVSX3
, PPCVLE
, {BF
, XB6
, DCMX
}},
7172 {"xsminjdp", XX3(60,152), XX3_MASK
, PPCVSX3
, PPCVLE
, {XT6
, XA6
, XB6
}},
7173 {"xsnmsubmsp", XX3(60,153), XX3_MASK
, PPCVSX2
, PPCVLE
, {XT6
, XA6
, XB6
}},
7174 {"xxlxor", XX3(60,154), XX3_MASK
, PPCVSX
, PPCVLE
, {XT6
, XA6
, XB6
}},
7175 {"xscvsxdsp", XX2(60,312), XX2_MASK
, PPCVSX2
, PPCVLE
, {XT6
, XB6
}},
7176 {"xsmaxdp", XX3(60,160), XX3_MASK
, PPCVSX
, PPCVLE
, {XT6
, XA6
, XB6
}},
7177 {"xsnmaddadp", XX3(60,161), XX3_MASK
, PPCVSX
, PPCVLE
, {XT6
, XA6
, XB6
}},
7178 {"xxlnor", XX3(60,162), XX3_MASK
, PPCVSX
, PPCVLE
, {XT6
, XA6
, XB6
}},
7179 {"xscvdpuxds", XX2(60,328), XX2_MASK
, PPCVSX
, PPCVLE
, {XT6
, XB6
}},
7180 {"xscvspdp", XX2(60,329), XX2_MASK
, PPCVSX
, PPCVLE
, {XT6
, XB6
}},
7181 {"xscvspdpn", XX2(60,331), XX2_MASK
, PPCVSX2
, PPCVLE
, {XT6
, XB6
}},
7182 {"xsmindp", XX3(60,168), XX3_MASK
, PPCVSX
, PPCVLE
, {XT6
, XA6
, XB6
}},
7183 {"xsnmaddmdp", XX3(60,169), XX3_MASK
, PPCVSX
, PPCVLE
, {XT6
, XA6
, XB6
}},
7184 {"xxlorc", XX3(60,170), XX3_MASK
, PPCVSX2
, PPCVLE
, {XT6
, XA6
, XB6
}},
7185 {"xscvdpsxds", XX2(60,344), XX2_MASK
, PPCVSX
, PPCVLE
, {XT6
, XB6
}},
7186 {"xsabsdp", XX2(60,345), XX2_MASK
, PPCVSX
, PPCVLE
, {XT6
, XB6
}},
7187 {"xsxexpdp", XX2VA(60,347,0),XX2_MASK
|1, PPCVSX3
, PPCVLE
, {RT
, XB6
}},
7188 {"xsxsigdp", XX2VA(60,347,1),XX2_MASK
|1, PPCVSX3
, PPCVLE
, {RT
, XB6
}},
7189 {"xscvhpdp", XX2VA(60,347,16),XX2_MASK
, PPCVSX3
, PPCVLE
, {XT6
, XB6
}},
7190 {"xscvdphp", XX2VA(60,347,17),XX2_MASK
, PPCVSX3
, PPCVLE
, {XT6
, XB6
}},
7191 {"xscpsgndp", XX3(60,176), XX3_MASK
, PPCVSX
, PPCVLE
, {XT6
, XA6
, XB6
}},
7192 {"xsnmsubadp", XX3(60,177), XX3_MASK
, PPCVSX
, PPCVLE
, {XT6
, XA6
, XB6
}},
7193 {"xxlnand", XX3(60,178), XX3_MASK
, PPCVSX2
, PPCVLE
, {XT6
, XA6
, XB6
}},
7194 {"xscvuxddp", XX2(60,360), XX2_MASK
, PPCVSX
, PPCVLE
, {XT6
, XB6
}},
7195 {"xsnabsdp", XX2(60,361), XX2_MASK
, PPCVSX
, PPCVLE
, {XT6
, XB6
}},
7196 {"xststdcdp", XX2(60,362), XX2BFD_MASK
, PPCVSX3
, PPCVLE
, {BF
, XB6
, DCMX
}},
7197 {"xsnmsubmdp", XX3(60,185), XX3_MASK
, PPCVSX
, PPCVLE
, {XT6
, XA6
, XB6
}},
7198 {"xxleqv", XX3(60,186), XX3_MASK
, PPCVSX2
, PPCVLE
, {XT6
, XA6
, XB6
}},
7199 {"xscvsxddp", XX2(60,376), XX2_MASK
, PPCVSX
, PPCVLE
, {XT6
, XB6
}},
7200 {"xsnegdp", XX2(60,377), XX2_MASK
, PPCVSX
, PPCVLE
, {XT6
, XB6
}},
7201 {"xvmaxsp", XX3(60,192), XX3_MASK
, PPCVSX
, PPCVLE
, {XT6
, XA6
, XB6
}},
7202 {"xvnmaddasp", XX3(60,193), XX3_MASK
, PPCVSX
, PPCVLE
, {XT6
, XA6
, XB6
}},
7203 {"xvcvspuxds", XX2(60,392), XX2_MASK
, PPCVSX
, PPCVLE
, {XT6
, XB6
}},
7204 {"xvcvdpsp", XX2(60,393), XX2_MASK
, PPCVSX
, PPCVLE
, {XT6
, XB6
}},
7205 {"xvminsp", XX3(60,200), XX3_MASK
, PPCVSX
, PPCVLE
, {XT6
, XA6
, XB6
}},
7206 {"xvnmaddmsp", XX3(60,201), XX3_MASK
, PPCVSX
, PPCVLE
, {XT6
, XA6
, XB6
}},
7207 {"xvcvspsxds", XX2(60,408), XX2_MASK
, PPCVSX
, PPCVLE
, {XT6
, XB6
}},
7208 {"xvabssp", XX2(60,409), XX2_MASK
, PPCVSX
, PPCVLE
, {XT6
, XB6
}},
7209 {"xvmovsp", XX3(60,208), XX3_MASK
, PPCVSX
, PPCVLE
, {XT6
, XA6
, XB6S
}},
7210 {"xvcpsgnsp", XX3(60,208), XX3_MASK
, PPCVSX
, PPCVLE
, {XT6
, XA6
, XB6
}},
7211 {"xvnmsubasp", XX3(60,209), XX3_MASK
, PPCVSX
, PPCVLE
, {XT6
, XA6
, XB6
}},
7212 {"xvcvuxdsp", XX2(60,424), XX2_MASK
, PPCVSX
, PPCVLE
, {XT6
, XB6
}},
7213 {"xvnabssp", XX2(60,425), XX2_MASK
, PPCVSX
, PPCVLE
, {XT6
, XB6
}},
7214 {"xvtstdcsp", XX2(60,426), XX2DCMXS_MASK
, PPCVSX3
, PPCVLE
, {XT6
, XB6
, DCMXS
}},
7215 {"xviexpsp", XX3(60,216), XX3_MASK
, PPCVSX3
, PPCVLE
, {XT6
, XA6
, XB6
}},
7216 {"xvnmsubmsp", XX3(60,217), XX3_MASK
, PPCVSX
, PPCVLE
, {XT6
, XA6
, XB6
}},
7217 {"xvcvsxdsp", XX2(60,440), XX2_MASK
, PPCVSX
, PPCVLE
, {XT6
, XB6
}},
7218 {"xvnegsp", XX2(60,441), XX2_MASK
, PPCVSX
, PPCVLE
, {XT6
, XB6
}},
7219 {"xvmaxdp", XX3(60,224), XX3_MASK
, PPCVSX
, PPCVLE
, {XT6
, XA6
, XB6
}},
7220 {"xvnmaddadp", XX3(60,225), XX3_MASK
, PPCVSX
, PPCVLE
, {XT6
, XA6
, XB6
}},
7221 {"xvcvdpuxds", XX2(60,456), XX2_MASK
, PPCVSX
, PPCVLE
, {XT6
, XB6
}},
7222 {"xvcvspdp", XX2(60,457), XX2_MASK
, PPCVSX
, PPCVLE
, {XT6
, XB6
}},
7223 {"xsiexpdp", X(60,918), XX1_MASK
, PPCVSX3
, PPCVLE
, {XT6
, RA
, RB
}},
7224 {"xvmindp", XX3(60,232), XX3_MASK
, PPCVSX
, PPCVLE
, {XT6
, XA6
, XB6
}},
7225 {"xvnmaddmdp", XX3(60,233), XX3_MASK
, PPCVSX
, PPCVLE
, {XT6
, XA6
, XB6
}},
7226 {"xvcvdpsxds", XX2(60,472), XX2_MASK
, PPCVSX
, PPCVLE
, {XT6
, XB6
}},
7227 {"xvabsdp", XX2(60,473), XX2_MASK
, PPCVSX
, PPCVLE
, {XT6
, XB6
}},
7228 {"xvxexpdp", XX2VA(60,475,0),XX2_MASK
, PPCVSX3
, PPCVLE
, {XT6
, XB6
}},
7229 {"xvxsigdp", XX2VA(60,475,1),XX2_MASK
, PPCVSX3
, PPCVLE
, {XT6
, XB6
}},
7230 {"xxbrh", XX2VA(60,475,7),XX2_MASK
, PPCVSX3
, PPCVLE
, {XT6
, XB6
}},
7231 {"xvxexpsp", XX2VA(60,475,8),XX2_MASK
, PPCVSX3
, PPCVLE
, {XT6
, XB6
}},
7232 {"xvxsigsp", XX2VA(60,475,9),XX2_MASK
, PPCVSX3
, PPCVLE
, {XT6
, XB6
}},
7233 {"xxbrw", XX2VA(60,475,15),XX2_MASK
, PPCVSX3
, PPCVLE
, {XT6
, XB6
}},
7234 {"xxbrd", XX2VA(60,475,23),XX2_MASK
, PPCVSX3
, PPCVLE
, {XT6
, XB6
}},
7235 {"xvcvhpsp", XX2VA(60,475,24),XX2_MASK
, PPCVSX3
, PPCVLE
, {XT6
, XB6
}},
7236 {"xvcvsphp", XX2VA(60,475,25),XX2_MASK
, PPCVSX3
, PPCVLE
, {XT6
, XB6
}},
7237 {"xxbrq", XX2VA(60,475,31),XX2_MASK
, PPCVSX3
, PPCVLE
, {XT6
, XB6
}},
7238 {"xvmovdp", XX3(60,240), XX3_MASK
, PPCVSX
, PPCVLE
, {XT6
, XA6
, XB6S
}},
7239 {"xvcpsgndp", XX3(60,240), XX3_MASK
, PPCVSX
, PPCVLE
, {XT6
, XA6
, XB6
}},
7240 {"xvnmsubadp", XX3(60,241), XX3_MASK
, PPCVSX
, PPCVLE
, {XT6
, XA6
, XB6
}},
7241 {"xvcvuxddp", XX2(60,488), XX2_MASK
, PPCVSX
, PPCVLE
, {XT6
, XB6
}},
7242 {"xvnabsdp", XX2(60,489), XX2_MASK
, PPCVSX
, PPCVLE
, {XT6
, XB6
}},
7243 {"xvtstdcdp", XX2(60,490), XX2DCMXS_MASK
, PPCVSX3
, PPCVLE
, {XT6
, XB6
, DCMXS
}},
7244 {"xviexpdp", XX3(60,248), XX3_MASK
, PPCVSX3
, PPCVLE
, {XT6
, XA6
, XB6
}},
7245 {"xvnmsubmdp", XX3(60,249), XX3_MASK
, PPCVSX
, PPCVLE
, {XT6
, XA6
, XB6
}},
7246 {"xvcvsxddp", XX2(60,504), XX2_MASK
, PPCVSX
, PPCVLE
, {XT6
, XB6
}},
7247 {"xvnegdp", XX2(60,505), XX2_MASK
, PPCVSX
, PPCVLE
, {XT6
, XB6
}},
7249 {"psq_st", OP(60), OP_MASK
, PPCPS
, PPCVLE
, {FRS
,PSD
,RA
,PSW
,PSQ
}},
7250 {"stfq", OP(60), OP_MASK
, POWER2
, PPCVLE
, {FRS
, D
, RA
}},
7252 {"lxv", DQX(61,1), DQX_MASK
, PPCVSX3
, PPCVLE
, {XTQ6
, DQ
, RA0
}},
7253 {"stxv", DQX(61,5), DQX_MASK
, PPCVSX3
, PPCVLE
, {XSQ6
, DQ
, RA0
}},
7254 {"stxsd", DSO(61,2), DS_MASK
, PPCVSX3
, PPCVLE
, {VS
, DS
, RA0
}},
7255 {"stxssp", DSO(61,3), DS_MASK
, PPCVSX3
, PPCVLE
, {VS
, DS
, RA0
}},
7256 {"stfdp", OP(61), OP_MASK
|Q_MASK
, POWER6
, POWER7
|PPCVLE
, {FRSp
, DS
, RA0
}},
7257 {"psq_stu", OP(61), OP_MASK
, PPCPS
, PPCVLE
, {FRS
,PSD
,RA
,PSW
,PSQ
}},
7258 {"stfqu", OP(61), OP_MASK
, POWER2
, PPCVLE
, {FRS
, D
, RA
}},
7260 {"std", DSO(62,0), DS_MASK
, PPC64
, PPCVLE
, {RS
, DS
, RA0
}},
7261 {"stdu", DSO(62,1), DS_MASK
, PPC64
, PPCVLE
, {RS
, DS
, RAS
}},
7262 {"stq", DSO(62,2), DS_MASK
|Q_MASK
, POWER4
, PPC476
|PPCVLE
, {RSQ
, DS
, RA0
}},
7264 {"fcmpu", X(63,0), XBF_MASK
, COM
, PPCEFS
|PPCVLE
, {BF
, FRA
, FRB
}},
7266 {"daddq", XRC(63,2,0), X_MASK
|Q_MASK
, POWER6
, PPCVLE
, {FRTp
, FRAp
, FRBp
}},
7267 {"daddq.", XRC(63,2,1), X_MASK
|Q_MASK
, POWER6
, PPCVLE
, {FRTp
, FRAp
, FRBp
}},
7269 {"dquaq", ZRC(63,3,0), Z2_MASK
|Q_MASK
, POWER6
, PPCVLE
, {FRTp
, FRAp
, FRBp
, RMC
}},
7270 {"dquaq.", ZRC(63,3,1), Z2_MASK
|Q_MASK
, POWER6
, PPCVLE
, {FRTp
, FRAp
, FRBp
, RMC
}},
7272 {"xsaddqp", XRC(63,4,0), X_MASK
, PPCVSX3
, PPCVLE
, {VD
, VA
, VB
}},
7273 {"xsaddqpo", XRC(63,4,1), X_MASK
, PPCVSX3
, PPCVLE
, {VD
, VA
, VB
}},
7275 {"xsrqpi", ZRC(63,5,0), Z2_MASK
, PPCVSX3
, PPCVLE
, {R
, VD
, VB
, RMC
}},
7276 {"xsrqpix", ZRC(63,5,1), Z2_MASK
, PPCVSX3
, PPCVLE
, {R
, VD
, VB
, RMC
}},
7278 {"fcpsgn", XRC(63,8,0), X_MASK
, POWER6
|PPCA2
|PPC476
, PPCVLE
, {FRT
, FRA
, FRB
}},
7279 {"fcpsgn.", XRC(63,8,1), X_MASK
, POWER6
|PPCA2
|PPC476
, PPCVLE
, {FRT
, FRA
, FRB
}},
7281 {"frsp", XRC(63,12,0), XRA_MASK
, COM
, PPCEFS
|PPCVLE
, {FRT
, FRB
}},
7282 {"frsp.", XRC(63,12,1), XRA_MASK
, COM
, PPCEFS
|PPCVLE
, {FRT
, FRB
}},
7284 {"fctiw", XRC(63,14,0), XRA_MASK
, PPCCOM
, PPCEFS
|PPCVLE
, {FRT
, FRB
}},
7285 {"fcir", XRC(63,14,0), XRA_MASK
, PWR2COM
, PPCVLE
, {FRT
, FRB
}},
7286 {"fctiw.", XRC(63,14,1), XRA_MASK
, PPCCOM
, PPCEFS
|PPCVLE
, {FRT
, FRB
}},
7287 {"fcir.", XRC(63,14,1), XRA_MASK
, PWR2COM
, PPCVLE
, {FRT
, FRB
}},
7289 {"fctiwz", XRC(63,15,0), XRA_MASK
, PPCCOM
, PPCEFS
|PPCVLE
, {FRT
, FRB
}},
7290 {"fcirz", XRC(63,15,0), XRA_MASK
, PWR2COM
, PPCVLE
, {FRT
, FRB
}},
7291 {"fctiwz.", XRC(63,15,1), XRA_MASK
, PPCCOM
, PPCEFS
|PPCVLE
, {FRT
, FRB
}},
7292 {"fcirz.", XRC(63,15,1), XRA_MASK
, PWR2COM
, PPCVLE
, {FRT
, FRB
}},
7294 {"fdiv", A(63,18,0), AFRC_MASK
, PPCCOM
, PPCEFS
|PPCVLE
, {FRT
, FRA
, FRB
}},
7295 {"fd", A(63,18,0), AFRC_MASK
, PWRCOM
, PPCVLE
, {FRT
, FRA
, FRB
}},
7296 {"fdiv.", A(63,18,1), AFRC_MASK
, PPCCOM
, PPCEFS
|PPCVLE
, {FRT
, FRA
, FRB
}},
7297 {"fd.", A(63,18,1), AFRC_MASK
, PWRCOM
, PPCVLE
, {FRT
, FRA
, FRB
}},
7299 {"fsub", A(63,20,0), AFRC_MASK
, PPCCOM
, PPCEFS
|PPCVLE
, {FRT
, FRA
, FRB
}},
7300 {"fs", A(63,20,0), AFRC_MASK
, PWRCOM
, PPCVLE
, {FRT
, FRA
, FRB
}},
7301 {"fsub.", A(63,20,1), AFRC_MASK
, PPCCOM
, PPCEFS
|PPCVLE
, {FRT
, FRA
, FRB
}},
7302 {"fs.", A(63,20,1), AFRC_MASK
, PWRCOM
, PPCVLE
, {FRT
, FRA
, FRB
}},
7304 {"fadd", A(63,21,0), AFRC_MASK
, PPCCOM
, PPCEFS
|PPCVLE
, {FRT
, FRA
, FRB
}},
7305 {"fa", A(63,21,0), AFRC_MASK
, PWRCOM
, PPCVLE
, {FRT
, FRA
, FRB
}},
7306 {"fadd.", A(63,21,1), AFRC_MASK
, PPCCOM
, PPCEFS
|PPCVLE
, {FRT
, FRA
, FRB
}},
7307 {"fa.", A(63,21,1), AFRC_MASK
, PWRCOM
, PPCVLE
, {FRT
, FRA
, FRB
}},
7309 {"fsqrt", A(63,22,0), AFRAFRC_MASK
, PPCPWR2
, TITAN
|PPCVLE
, {FRT
, FRB
}},
7310 {"fsqrt.", A(63,22,1), AFRAFRC_MASK
, PPCPWR2
, TITAN
|PPCVLE
, {FRT
, FRB
}},
7312 {"fsel", A(63,23,0), A_MASK
, PPC
, PPCEFS
|PPCVLE
, {FRT
, FRA
, FRC
, FRB
}},
7313 {"fsel.", A(63,23,1), A_MASK
, PPC
, PPCEFS
|PPCVLE
, {FRT
, FRA
, FRC
, FRB
}},
7315 {"fre", A(63,24,0), AFRAFRC_MASK
, POWER7
, PPCVLE
, {FRT
, FRB
}},
7316 {"fre", A(63,24,0), AFRALFRC_MASK
, POWER5
, POWER7
|PPCVLE
, {FRT
, FRB
, A_L
}},
7317 {"fre.", A(63,24,1), AFRAFRC_MASK
, POWER7
, PPCVLE
, {FRT
, FRB
}},
7318 {"fre.", A(63,24,1), AFRALFRC_MASK
, POWER5
, POWER7
|PPCVLE
, {FRT
, FRB
, A_L
}},
7320 {"fmul", A(63,25,0), AFRB_MASK
, PPCCOM
, PPCEFS
|PPCVLE
, {FRT
, FRA
, FRC
}},
7321 {"fm", A(63,25,0), AFRB_MASK
, PWRCOM
, PPCVLE
|PPCVLE
, {FRT
, FRA
, FRC
}},
7322 {"fmul.", A(63,25,1), AFRB_MASK
, PPCCOM
, PPCEFS
|PPCVLE
, {FRT
, FRA
, FRC
}},
7323 {"fm.", A(63,25,1), AFRB_MASK
, PWRCOM
, PPCVLE
|PPCVLE
, {FRT
, FRA
, FRC
}},
7325 {"frsqrte", A(63,26,0), AFRAFRC_MASK
, POWER7
, PPCVLE
, {FRT
, FRB
}},
7326 {"frsqrte", A(63,26,0), AFRALFRC_MASK
, PPC
, POWER7
|PPCVLE
, {FRT
, FRB
, A_L
}},
7327 {"frsqrte.", A(63,26,1), AFRAFRC_MASK
, POWER7
, PPCVLE
, {FRT
, FRB
}},
7328 {"frsqrte.", A(63,26,1), AFRALFRC_MASK
, PPC
, POWER7
|PPCVLE
, {FRT
, FRB
, A_L
}},
7330 {"fmsub", A(63,28,0), A_MASK
, PPCCOM
, PPCEFS
|PPCVLE
, {FRT
, FRA
, FRC
, FRB
}},
7331 {"fms", A(63,28,0), A_MASK
, PWRCOM
, PPCVLE
, {FRT
, FRA
, FRC
, FRB
}},
7332 {"fmsub.", A(63,28,1), A_MASK
, PPCCOM
, PPCEFS
|PPCVLE
, {FRT
, FRA
, FRC
, FRB
}},
7333 {"fms.", A(63,28,1), A_MASK
, PWRCOM
, PPCVLE
, {FRT
, FRA
, FRC
, FRB
}},
7335 {"fmadd", A(63,29,0), A_MASK
, PPCCOM
, PPCEFS
|PPCVLE
, {FRT
, FRA
, FRC
, FRB
}},
7336 {"fma", A(63,29,0), A_MASK
, PWRCOM
, PPCVLE
, {FRT
, FRA
, FRC
, FRB
}},
7337 {"fmadd.", A(63,29,1), A_MASK
, PPCCOM
, PPCEFS
|PPCVLE
, {FRT
, FRA
, FRC
, FRB
}},
7338 {"fma.", A(63,29,1), A_MASK
, PWRCOM
, PPCVLE
, {FRT
, FRA
, FRC
, FRB
}},
7340 {"fnmsub", A(63,30,0), A_MASK
, PPCCOM
, PPCEFS
|PPCVLE
, {FRT
, FRA
, FRC
, FRB
}},
7341 {"fnms", A(63,30,0), A_MASK
, PWRCOM
, PPCVLE
, {FRT
, FRA
, FRC
, FRB
}},
7342 {"fnmsub.", A(63,30,1), A_MASK
, PPCCOM
, PPCEFS
|PPCVLE
, {FRT
, FRA
, FRC
, FRB
}},
7343 {"fnms.", A(63,30,1), A_MASK
, PWRCOM
, PPCVLE
, {FRT
, FRA
, FRC
, FRB
}},
7345 {"fnmadd", A(63,31,0), A_MASK
, PPCCOM
, PPCEFS
|PPCVLE
, {FRT
, FRA
, FRC
, FRB
}},
7346 {"fnma", A(63,31,0), A_MASK
, PWRCOM
, PPCVLE
, {FRT
, FRA
, FRC
, FRB
}},
7347 {"fnmadd.", A(63,31,1), A_MASK
, PPCCOM
, PPCEFS
|PPCVLE
, {FRT
, FRA
, FRC
, FRB
}},
7348 {"fnma.", A(63,31,1), A_MASK
, PWRCOM
, PPCVLE
, {FRT
, FRA
, FRC
, FRB
}},
7350 {"fcmpo", X(63,32), XBF_MASK
, COM
, PPCEFS
|PPCVLE
, {BF
, FRA
, FRB
}},
7352 {"dmulq", XRC(63,34,0), X_MASK
|Q_MASK
, POWER6
, PPCVLE
, {FRTp
, FRAp
, FRBp
}},
7353 {"dmulq.", XRC(63,34,1), X_MASK
|Q_MASK
, POWER6
, PPCVLE
, {FRTp
, FRAp
, FRBp
}},
7355 {"drrndq", ZRC(63,35,0), Z2_MASK
|Q_MASK
, POWER6
, PPCVLE
, {FRTp
, FRA
, FRBp
, RMC
}},
7356 {"drrndq.", ZRC(63,35,1), Z2_MASK
|Q_MASK
, POWER6
, PPCVLE
, {FRTp
, FRA
, FRBp
, RMC
}},
7358 {"xsmulqp", XRC(63,36,0), X_MASK
, PPCVSX3
, PPCVLE
, {VD
, VA
, VB
}},
7359 {"xsmulqpo", XRC(63,36,1), X_MASK
, PPCVSX3
, PPCVLE
, {VD
, VA
, VB
}},
7361 {"xsrqpxp", Z(63,37), Z2_MASK
, PPCVSX3
, PPCVLE
, {R
, VD
, VB
, RMC
}},
7363 {"mtfsb1", XRC(63,38,0), XRARB_MASK
, COM
, PPCVLE
, {BT
}},
7364 {"mtfsb1.", XRC(63,38,1), XRARB_MASK
, COM
, PPCVLE
, {BT
}},
7366 {"fneg", XRC(63,40,0), XRA_MASK
, COM
, PPCEFS
|PPCVLE
, {FRT
, FRB
}},
7367 {"fneg.", XRC(63,40,1), XRA_MASK
, COM
, PPCEFS
|PPCVLE
, {FRT
, FRB
}},
7369 {"mcrfs", X(63,64), XRB_MASK
|(3<<21)|(3<<16), COM
, PPCVLE
, {BF
, BFA
}},
7371 {"dscliq", ZRC(63,66,0), Z_MASK
|Q_MASK
, POWER6
, PPCVLE
, {FRTp
, FRAp
, SH16
}},
7372 {"dscliq.", ZRC(63,66,1), Z_MASK
|Q_MASK
, POWER6
, PPCVLE
, {FRTp
, FRAp
, SH16
}},
7374 {"dquaiq", ZRC(63,67,0), Z2_MASK
|Q_MASK
, POWER6
, PPCVLE
, {TE
, FRTp
, FRBp
, RMC
}},
7375 {"dquaiq.", ZRC(63,67,1), Z2_MASK
|Q_MASK
, POWER6
, PPCVLE
, {TE
, FRTp
, FRBp
, RMC
}},
7377 {"mtfsb0", XRC(63,70,0), XRARB_MASK
, COM
, PPCVLE
, {BT
}},
7378 {"mtfsb0.", XRC(63,70,1), XRARB_MASK
, COM
, PPCVLE
, {BT
}},
7380 {"fmr", XRC(63,72,0), XRA_MASK
, COM
, PPCEFS
|PPCVLE
, {FRT
, FRB
}},
7381 {"fmr.", XRC(63,72,1), XRA_MASK
, COM
, PPCEFS
|PPCVLE
, {FRT
, FRB
}},
7383 {"dscriq", ZRC(63,98,0), Z_MASK
|Q_MASK
, POWER6
, PPCVLE
, {FRTp
, FRAp
, SH16
}},
7384 {"dscriq.", ZRC(63,98,1), Z_MASK
|Q_MASK
, POWER6
, PPCVLE
, {FRTp
, FRAp
, SH16
}},
7386 {"drintxq", ZRC(63,99,0), Z2_MASK
|Q_MASK
, POWER6
, PPCVLE
, {R
, FRTp
, FRBp
, RMC
}},
7387 {"drintxq.", ZRC(63,99,1), Z2_MASK
|Q_MASK
, POWER6
, PPCVLE
, {R
, FRTp
, FRBp
, RMC
}},
7389 {"xscpsgnqp", X(63,100), X_MASK
, PPCVSX3
, PPCVLE
, {VD
, VA
, VB
}},
7391 {"ftdiv", X(63,128), XBF_MASK
, POWER7
, PPCVLE
, {BF
, FRA
, FRB
}},
7393 {"dcmpoq", X(63,130), X_MASK
, POWER6
, PPCVLE
, {BF
, FRAp
, FRBp
}},
7395 {"xscmpoqp", X(63,132), XBF_MASK
, PPCVSX3
, PPCVLE
, {BF
, VA
, VB
}},
7397 {"mtfsfi", XRC(63,134,0), XWRA_MASK
|(3<<21)|(1<<11), POWER6
|PPCA2
|PPC476
, PPCVLE
, {BFF
, U
, W
}},
7398 {"mtfsfi", XRC(63,134,0), XRA_MASK
|(3<<21)|(1<<11), COM
, POWER6
|PPCA2
|PPC476
|PPCVLE
, {BFF
, U
}},
7399 {"mtfsfi.", XRC(63,134,1), XWRA_MASK
|(3<<21)|(1<<11), POWER6
|PPCA2
|PPC476
, PPCVLE
, {BFF
, U
, W
}},
7400 {"mtfsfi.", XRC(63,134,1), XRA_MASK
|(3<<21)|(1<<11), COM
, POWER6
|PPCA2
|PPC476
|PPCVLE
, {BFF
, U
}},
7402 {"fnabs", XRC(63,136,0), XRA_MASK
, COM
, PPCEFS
|PPCVLE
, {FRT
, FRB
}},
7403 {"fnabs.", XRC(63,136,1), XRA_MASK
, COM
, PPCEFS
|PPCVLE
, {FRT
, FRB
}},
7405 {"fctiwu", XRC(63,142,0), XRA_MASK
, POWER7
, PPCVLE
, {FRT
, FRB
}},
7406 {"fctiwu.", XRC(63,142,1), XRA_MASK
, POWER7
, PPCVLE
, {FRT
, FRB
}},
7407 {"fctiwuz", XRC(63,143,0), XRA_MASK
, POWER7
, PPCVLE
, {FRT
, FRB
}},
7408 {"fctiwuz.", XRC(63,143,1), XRA_MASK
, POWER7
, PPCVLE
, {FRT
, FRB
}},
7410 {"ftsqrt", X(63,160), XBF_MASK
|FRA_MASK
, POWER7
, PPCVLE
, {BF
, FRB
}},
7412 {"dtstexq", X(63,162), X_MASK
, POWER6
, PPCVLE
, {BF
, FRAp
, FRBp
}},
7414 {"xscmpexpqp", X(63,164), XBF_MASK
, PPCVSX3
, PPCVLE
, {BF
, VA
, VB
}},
7416 {"dtstdcq", Z(63,194), Z_MASK
, POWER6
, PPCVLE
, {BF
, FRAp
, DCM
}},
7417 {"dtstdgq", Z(63,226), Z_MASK
, POWER6
, PPCVLE
, {BF
, FRAp
, DGM
}},
7419 {"drintnq", ZRC(63,227,0), Z2_MASK
|Q_MASK
, POWER6
, PPCVLE
, {R
, FRTp
, FRBp
, RMC
}},
7420 {"drintnq.", ZRC(63,227,1), Z2_MASK
|Q_MASK
, POWER6
, PPCVLE
, {R
, FRTp
, FRBp
, RMC
}},
7422 {"dctqpq", XRC(63,258,0), X_MASK
|Q_MASK
, POWER6
, PPCVLE
, {FRTp
, FRB
}},
7423 {"dctqpq.", XRC(63,258,1), X_MASK
|Q_MASK
, POWER6
, PPCVLE
, {FRTp
, FRB
}},
7425 {"fabs", XRC(63,264,0), XRA_MASK
, COM
, PPCEFS
|PPCVLE
, {FRT
, FRB
}},
7426 {"fabs.", XRC(63,264,1), XRA_MASK
, COM
, PPCEFS
|PPCVLE
, {FRT
, FRB
}},
7428 {"dctfixq", XRC(63,290,0), X_MASK
, POWER6
, PPCVLE
, {FRT
, FRBp
}},
7429 {"dctfixq.", XRC(63,290,1), X_MASK
, POWER6
, PPCVLE
, {FRT
, FRBp
}},
7431 {"ddedpdq", XRC(63,322,0), X_MASK
|Q_MASK
, POWER6
, PPCVLE
, {SP
, FRTp
, FRBp
}},
7432 {"ddedpdq.", XRC(63,322,1), X_MASK
|Q_MASK
, POWER6
, PPCVLE
, {SP
, FRTp
, FRBp
}},
7434 {"dxexq", XRC(63,354,0), X_MASK
, POWER6
, PPCVLE
, {FRT
, FRBp
}},
7435 {"dxexq.", XRC(63,354,1), X_MASK
, POWER6
, PPCVLE
, {FRT
, FRBp
}},
7437 {"xsmaddqp", XRC(63,388,0), X_MASK
, PPCVSX3
, PPCVLE
, {VD
, VA
, VB
}},
7438 {"xsmaddqpo", XRC(63,388,1), X_MASK
, PPCVSX3
, PPCVLE
, {VD
, VA
, VB
}},
7440 {"frin", XRC(63,392,0), XRA_MASK
, POWER5
, PPCVLE
, {FRT
, FRB
}},
7441 {"frin.", XRC(63,392,1), XRA_MASK
, POWER5
, PPCVLE
, {FRT
, FRB
}},
7443 {"xsmsubqp", XRC(63,420,0), X_MASK
, PPCVSX3
, PPCVLE
, {VD
, VA
, VB
}},
7444 {"xsmsubqpo", XRC(63,420,1), X_MASK
, PPCVSX3
, PPCVLE
, {VD
, VA
, VB
}},
7446 {"friz", XRC(63,424,0), XRA_MASK
, POWER5
, PPCVLE
, {FRT
, FRB
}},
7447 {"friz.", XRC(63,424,1), XRA_MASK
, POWER5
, PPCVLE
, {FRT
, FRB
}},
7449 {"xsnmaddqp", XRC(63,452,0), X_MASK
, PPCVSX3
, PPCVLE
, {VD
, VA
, VB
}},
7450 {"xsnmaddqpo", XRC(63,452,1), X_MASK
, PPCVSX3
, PPCVLE
, {VD
, VA
, VB
}},
7452 {"frip", XRC(63,456,0), XRA_MASK
, POWER5
, PPCVLE
, {FRT
, FRB
}},
7453 {"frip.", XRC(63,456,1), XRA_MASK
, POWER5
, PPCVLE
, {FRT
, FRB
}},
7455 {"xsnmsubqp", XRC(63,484,0), X_MASK
, PPCVSX3
, PPCVLE
, {VD
, VA
, VB
}},
7456 {"xsnmsubqpo", XRC(63,484,1), X_MASK
, PPCVSX3
, PPCVLE
, {VD
, VA
, VB
}},
7458 {"frim", XRC(63,488,0), XRA_MASK
, POWER5
, PPCVLE
, {FRT
, FRB
}},
7459 {"frim.", XRC(63,488,1), XRA_MASK
, POWER5
, PPCVLE
, {FRT
, FRB
}},
7461 {"dsubq", XRC(63,514,0), X_MASK
|Q_MASK
, POWER6
, PPCVLE
, {FRTp
, FRAp
, FRBp
}},
7462 {"dsubq.", XRC(63,514,1), X_MASK
|Q_MASK
, POWER6
, PPCVLE
, {FRTp
, FRAp
, FRBp
}},
7464 {"xssubqp", XRC(63,516,0), X_MASK
, PPCVSX3
, PPCVLE
, {VD
, VA
, VB
}},
7465 {"xssubqpo", XRC(63,516,1), X_MASK
, PPCVSX3
, PPCVLE
, {VD
, VA
, VB
}},
7467 {"ddivq", XRC(63,546,0), X_MASK
|Q_MASK
, POWER6
, PPCVLE
, {FRTp
, FRAp
, FRBp
}},
7468 {"ddivq.", XRC(63,546,1), X_MASK
|Q_MASK
, POWER6
, PPCVLE
, {FRTp
, FRAp
, FRBp
}},
7470 {"xsdivqp", XRC(63,548,0), X_MASK
, PPCVSX3
, PPCVLE
, {VD
, VA
, VB
}},
7471 {"xsdivqpo", XRC(63,548,1), X_MASK
, PPCVSX3
, PPCVLE
, {VD
, VA
, VB
}},
7473 {"mffs", XRC(63,583,0), XRARB_MASK
, COM
, PPCEFS
|PPCVLE
, {FRT
}},
7474 {"mffs.", XRC(63,583,1), XRARB_MASK
, COM
, PPCEFS
|PPCVLE
, {FRT
}},
7476 {"mffsce", XMMF(63,583,0,1), XMMF_MASK
|RB_MASK
, POWER9
, PPCVLE
, {FRT
}},
7477 {"mffscdrn", XMMF(63,583,2,4), XMMF_MASK
, POWER9
, PPCVLE
, {FRT
, FRB
}},
7478 {"mffscdrni", XMMF(63,583,2,5), XMMF_MASK
|(3<<14), POWER9
, PPCVLE
, {FRT
, DRM
}},
7479 {"mffscrn", XMMF(63,583,2,6), XMMF_MASK
, POWER9
, PPCVLE
, {FRT
, FRB
}},
7480 {"mffscrni", XMMF(63,583,2,7), XMMF_MASK
|(7<<13), POWER9
, PPCVLE
, {FRT
, RM
}},
7481 {"mffsl", XMMF(63,583,3,0), XMMF_MASK
|RB_MASK
, POWER9
, PPCVLE
, {FRT
}},
7483 {"dcmpuq", X(63,642), X_MASK
, POWER6
, PPCVLE
, {BF
, FRAp
, FRBp
}},
7485 {"xscmpuqp", X(63,644), XBF_MASK
, PPCVSX3
, PPCVLE
, {BF
, VA
, VB
}},
7487 {"dtstsfq", X(63,674), X_MASK
, POWER6
, PPCVLE
, {BF
, FRA
, FRBp
}},
7488 {"dtstsfiq", X(63,675), X_MASK
|1<<22,POWER9
, PPCVLE
, {BF
, UIM6
, FRBp
}},
7490 {"xststdcqp", X(63,708), X_MASK
, PPCVSX3
, PPCVLE
, {BF
, VB
, DCMX
}},
7492 {"mtfsf", XFL(63,711,0), XFL_MASK
, POWER6
|PPCA2
|PPC476
, PPCVLE
, {FLM
, FRB
, XFL_L
, W
}},
7493 {"mtfsf", XFL(63,711,0), XFL_MASK
, COM
, POWER6
|PPCA2
|PPC476
|PPCEFS
|PPCVLE
, {FLM
, FRB
}},
7494 {"mtfsf.", XFL(63,711,1), XFL_MASK
, POWER6
|PPCA2
|PPC476
, PPCVLE
, {FLM
, FRB
, XFL_L
, W
}},
7495 {"mtfsf.", XFL(63,711,1), XFL_MASK
, COM
, POWER6
|PPCA2
|PPC476
|PPCEFS
|PPCVLE
, {FLM
, FRB
}},
7497 {"drdpq", XRC(63,770,0), X_MASK
|Q_MASK
, POWER6
, PPCVLE
, {FRTp
, FRBp
}},
7498 {"drdpq.", XRC(63,770,1), X_MASK
|Q_MASK
, POWER6
, PPCVLE
, {FRTp
, FRBp
}},
7500 {"dcffixq", XRC(63,802,0), X_MASK
|Q_MASK
, POWER6
, PPCVLE
, {FRTp
, FRB
}},
7501 {"dcffixq.", XRC(63,802,1), X_MASK
|Q_MASK
, POWER6
, PPCVLE
, {FRTp
, FRB
}},
7503 {"xsabsqp", XVA(63,804,0), XVA_MASK
, PPCVSX3
, PPCVLE
, {VD
, VB
}},
7504 {"xsxexpqp", XVA(63,804,2), XVA_MASK
, PPCVSX3
, PPCVLE
, {VD
, VB
}},
7505 {"xsnabsqp", XVA(63,804,8), XVA_MASK
, PPCVSX3
, PPCVLE
, {VD
, VB
}},
7506 {"xsnegqp", XVA(63,804,16), XVA_MASK
, PPCVSX3
, PPCVLE
, {VD
, VB
}},
7507 {"xsxsigqp", XVA(63,804,18), XVA_MASK
, PPCVSX3
, PPCVLE
, {VD
, VB
}},
7508 {"xssqrtqp", XVARC(63,804,27,0), XVA_MASK
, PPCVSX3
, PPCVLE
, {VD
, VB
}},
7509 {"xssqrtqpo", XVARC(63,804,27,1), XVA_MASK
, PPCVSX3
, PPCVLE
, {VD
, VB
}},
7511 {"fctid", XRC(63,814,0), XRA_MASK
, PPC64
, PPCVLE
, {FRT
, FRB
}},
7512 {"fctid", XRC(63,814,0), XRA_MASK
, PPC476
, PPCVLE
, {FRT
, FRB
}},
7513 {"fctid.", XRC(63,814,1), XRA_MASK
, PPC64
, PPCVLE
, {FRT
, FRB
}},
7514 {"fctid.", XRC(63,814,1), XRA_MASK
, PPC476
, PPCVLE
, {FRT
, FRB
}},
7516 {"fctidz", XRC(63,815,0), XRA_MASK
, PPC64
, PPCVLE
, {FRT
, FRB
}},
7517 {"fctidz", XRC(63,815,0), XRA_MASK
, PPC476
, PPCVLE
, {FRT
, FRB
}},
7518 {"fctidz.", XRC(63,815,1), XRA_MASK
, PPC64
, PPCVLE
, {FRT
, FRB
}},
7519 {"fctidz.", XRC(63,815,1), XRA_MASK
, PPC476
, PPCVLE
, {FRT
, FRB
}},
7521 {"denbcdq", XRC(63,834,0), X_MASK
|Q_MASK
, POWER6
, PPCVLE
, {S
, FRTp
, FRBp
}},
7522 {"denbcdq.", XRC(63,834,1), X_MASK
|Q_MASK
, POWER6
, PPCVLE
, {S
, FRTp
, FRBp
}},
7524 {"xscvqpuwz", XVA(63,836,1), XVA_MASK
, PPCVSX3
, PPCVLE
, {VD
, VB
}},
7525 {"xscvudqp", XVA(63,836,2), XVA_MASK
, PPCVSX3
, PPCVLE
, {VD
, VB
}},
7526 {"xscvqpswz", XVA(63,836,9), XVA_MASK
, PPCVSX3
, PPCVLE
, {VD
, VB
}},
7527 {"xscvsdqp", XVA(63,836,10), XVA_MASK
, PPCVSX3
, PPCVLE
, {VD
, VB
}},
7528 {"xscvqpudz", XVA(63,836,17), XVA_MASK
, PPCVSX3
, PPCVLE
, {VD
, VB
}},
7529 {"xscvqpdp", XVARC(63,836,20,0), XVA_MASK
, PPCVSX3
, PPCVLE
, {VD
, VB
}},
7530 {"xscvqpdpo", XVARC(63,836,20,1), XVA_MASK
, PPCVSX3
, PPCVLE
, {VD
, VB
}},
7531 {"xscvdpqp", XVA(63,836,22), XVA_MASK
, PPCVSX3
, PPCVLE
, {VD
, VB
}},
7532 {"xscvqpsdz", XVA(63,836,25), XVA_MASK
, PPCVSX3
, PPCVLE
, {VD
, VB
}},
7534 {"fmrgow", X(63,838), X_MASK
, PPCVSX2
, PPCVLE
, {FRT
, FRA
, FRB
}},
7536 {"fcfid", XRC(63,846,0), XRA_MASK
, PPC64
, PPCVLE
, {FRT
, FRB
}},
7537 {"fcfid", XRC(63,846,0), XRA_MASK
, PPC476
, PPCVLE
, {FRT
, FRB
}},
7538 {"fcfid.", XRC(63,846,1), XRA_MASK
, PPC64
, PPCVLE
, {FRT
, FRB
}},
7539 {"fcfid.", XRC(63,846,1), XRA_MASK
, PPC476
, PPCVLE
, {FRT
, FRB
}},
7541 {"diexq", XRC(63,866,0), X_MASK
|Q_MASK
, POWER6
, PPCVLE
, {FRTp
, FRA
, FRBp
}},
7542 {"diexq.", XRC(63,866,1), X_MASK
|Q_MASK
, POWER6
, PPCVLE
, {FRTp
, FRA
, FRBp
}},
7544 {"xsiexpqp", X(63,868), X_MASK
, PPCVSX3
, PPCVLE
, {VD
, VA
, VB
}},
7546 {"fctidu", XRC(63,942,0), XRA_MASK
, POWER7
|PPCA2
, PPCVLE
, {FRT
, FRB
}},
7547 {"fctidu.", XRC(63,942,1), XRA_MASK
, POWER7
|PPCA2
, PPCVLE
, {FRT
, FRB
}},
7549 {"fctiduz", XRC(63,943,0), XRA_MASK
, POWER7
|PPCA2
, PPCVLE
, {FRT
, FRB
}},
7550 {"fctiduz.", XRC(63,943,1), XRA_MASK
, POWER7
|PPCA2
, PPCVLE
, {FRT
, FRB
}},
7552 {"fmrgew", X(63,966), X_MASK
, PPCVSX2
, PPCVLE
, {FRT
, FRA
, FRB
}},
7554 {"fcfidu", XRC(63,974,0), XRA_MASK
, POWER7
|PPCA2
, PPCVLE
, {FRT
, FRB
}},
7555 {"fcfidu.", XRC(63,974,1), XRA_MASK
, POWER7
|PPCA2
, PPCVLE
, {FRT
, FRB
}},
7558 const int powerpc_num_opcodes
=
7559 sizeof (powerpc_opcodes
) / sizeof (powerpc_opcodes
[0]);
7561 /* The VLE opcode table.
7563 The format of this opcode table is the same as the main opcode table. */
7565 const struct powerpc_opcode vle_opcodes
[] = {
7566 {"se_illegal", C(0), C_MASK
, PPCVLE
, 0, {}},
7567 {"se_isync", C(1), C_MASK
, PPCVLE
, 0, {}},
7568 {"se_sc", C(2), C_MASK
, PPCVLE
, 0, {}},
7569 {"se_blr", C_LK(2,0), C_LK_MASK
, PPCVLE
, 0, {}},
7570 {"se_blrl", C_LK(2,1), C_LK_MASK
, PPCVLE
, 0, {}},
7571 {"se_bctr", C_LK(3,0), C_LK_MASK
, PPCVLE
, 0, {}},
7572 {"se_bctrl", C_LK(3,1), C_LK_MASK
, PPCVLE
, 0, {}},
7573 {"se_rfi", C(8), C_MASK
, PPCVLE
, 0, {}},
7574 {"se_rfci", C(9), C_MASK
, PPCVLE
, 0, {}},
7575 {"se_rfdi", C(10), C_MASK
, PPCVLE
, 0, {}},
7576 {"se_rfmci", C(11), C_MASK
, PPCRFMCI
|PPCVLE
, 0, {}},
7577 {"se_rfgi", C(12), C_MASK
, PPCVLE
, 0, {}},
7578 {"se_not", SE_R(0,2), SE_R_MASK
, PPCVLE
, 0, {RX
}},
7579 {"se_neg", SE_R(0,3), SE_R_MASK
, PPCVLE
, 0, {RX
}},
7580 {"se_mflr", SE_R(0,8), SE_R_MASK
, PPCVLE
, 0, {RX
}},
7581 {"se_mtlr", SE_R(0,9), SE_R_MASK
, PPCVLE
, 0, {RX
}},
7582 {"se_mfctr", SE_R(0,10), SE_R_MASK
, PPCVLE
, 0, {RX
}},
7583 {"se_mtctr", SE_R(0,11), SE_R_MASK
, PPCVLE
, 0, {RX
}},
7584 {"se_extzb", SE_R(0,12), SE_R_MASK
, PPCVLE
, 0, {RX
}},
7585 {"se_extsb", SE_R(0,13), SE_R_MASK
, PPCVLE
, 0, {RX
}},
7586 {"se_extzh", SE_R(0,14), SE_R_MASK
, PPCVLE
, 0, {RX
}},
7587 {"se_extsh", SE_R(0,15), SE_R_MASK
, PPCVLE
, 0, {RX
}},
7588 {"se_mr", SE_RR(0,1), SE_RR_MASK
, PPCVLE
, 0, {RX
, RY
}},
7589 {"se_mtar", SE_RR(0,2), SE_RR_MASK
, PPCVLE
, 0, {ARX
, RY
}},
7590 {"se_mfar", SE_RR(0,3), SE_RR_MASK
, PPCVLE
, 0, {RX
, ARY
}},
7591 {"se_add", SE_RR(1,0), SE_RR_MASK
, PPCVLE
, 0, {RX
, RY
}},
7592 {"se_mullw", SE_RR(1,1), SE_RR_MASK
, PPCVLE
, 0, {RX
, RY
}},
7593 {"se_sub", SE_RR(1,2), SE_RR_MASK
, PPCVLE
, 0, {RX
, RY
}},
7594 {"se_subf", SE_RR(1,3), SE_RR_MASK
, PPCVLE
, 0, {RX
, RY
}},
7595 {"se_cmp", SE_RR(3,0), SE_RR_MASK
, PPCVLE
, 0, {RX
, RY
}},
7596 {"se_cmpl", SE_RR(3,1), SE_RR_MASK
, PPCVLE
, 0, {RX
, RY
}},
7597 {"se_cmph", SE_RR(3,2), SE_RR_MASK
, PPCVLE
, 0, {RX
, RY
}},
7598 {"se_cmphl", SE_RR(3,3), SE_RR_MASK
, PPCVLE
, 0, {RX
, RY
}},
7600 /* by major opcode */
7601 {"zvaddih", VX(4, 0x200), VX_MASK
, PPCLSP
, 0, {RD
, RA
, EVUIMM
}},
7602 {"zvsubifh", VX(4, 0x201), VX_MASK
, PPCLSP
, 0, {RD
, RA
, EVUIMM
}},
7603 {"zvaddh", VX(4, 0x204), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
7604 {"zvsubfh", VX(4, 0x205), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
7605 {"zvaddsubfh", VX(4, 0x206), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
7606 {"zvsubfaddh", VX(4, 0x207), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
7607 {"zvaddhx", VX(4, 0x20C), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
7608 {"zvsubfhx", VX(4, 0x20D), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
7609 {"zvaddsubfhx", VX(4, 0x20E), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
7610 {"zvsubfaddhx", VX(4, 0x20F), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
7611 {"zaddwus", VX(4, 0x210), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
7612 {"zsubfwus", VX(4, 0x211), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
7613 {"zaddwss", VX(4, 0x212), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
7614 {"zsubfwss", VX(4, 0x213), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
7615 {"zvaddhus", VX(4, 0x214), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
7616 {"zvsubfhus", VX(4, 0x215), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
7617 {"zvaddhss", VX(4, 0x216), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
7618 {"zvsubfhss", VX(4, 0x217), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
7619 {"zvaddsubfhss", VX(4, 0x21A), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
7620 {"zvsubfaddhss", VX(4, 0x21B), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
7621 {"zvaddhxss", VX(4, 0x21C), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
7622 {"zvsubfhxss", VX(4, 0x21D), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
7623 {"zvaddsubfhxss", VX(4, 0x21E), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
7624 {"zvsubfaddhxss", VX(4, 0x21F), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
7625 {"zaddheuw", VX(4, 0x220), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
7626 {"zsubfheuw", VX(4, 0x221), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
7627 {"zaddhesw", VX(4, 0x222), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
7628 {"zsubfhesw", VX(4, 0x223), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
7629 {"zaddhouw", VX(4, 0x224), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
7630 {"zsubfhouw", VX(4, 0x225), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
7631 {"zaddhosw", VX(4, 0x226), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
7632 {"zsubfhosw", VX(4, 0x227), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
7633 {"zvmergehih", VX(4, 0x22C), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
7634 {"zvmergeloh", VX(4, 0x22D), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
7635 {"zvmergehiloh", VX(4, 0x22E), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
7636 {"zvmergelohih", VX(4, 0x22F), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
7637 {"zvcmpgthu", VX(4, 0x230), VX_MASK
, PPCLSP
, 0, {CRFD
, RA
, RB
}},
7638 {"zvcmpgths", VX(4, 0x230), VX_MASK
, PPCLSP
, 0, {CRFD
, RA
, RB
}},
7639 {"zvcmplthu", VX(4, 0x231), VX_MASK
, PPCLSP
, 0, {CRFD
, RA
, RB
}},
7640 {"zvcmplths", VX(4, 0x231), VX_MASK
, PPCLSP
, 0, {CRFD
, RA
, RB
}},
7641 {"zvcmpeqh", VX(4, 0x232), VX_MASK
, PPCLSP
, 0, {CRFD
, RA
, RB
}},
7642 {"zpkswgshfrs", VX(4, 0x238), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
7643 {"zpkswgswfrs", VX(4, 0x239), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
7644 {"zvpkshgwshfrs", VX(4, 0x23A), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
7645 {"zvpkswshfrs", VX(4, 0x23B), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
7646 {"zvpkswuhs", VX(4, 0x23C), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
7647 {"zvpkswshs", VX(4, 0x23D), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
7648 {"zvpkuwuhs", VX(4, 0x23E), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
7649 {"zvsplatih", VX_LSP(4, 0x23F), VX_LSP_MASK
, PPCLSP
, 0, {RD
, SIMM
}},
7650 {"zvsplatfih", VX_LSP(4, 0xA3F), VX_LSP_MASK
, PPCLSP
, 0, {RD
, SIMM
}},
7651 {"zcntlsw", VX_LSP(4, 0x2A3F), VX_LSP_MASK
, PPCLSP
, 0, {RD
, RA
}},
7652 {"zvcntlzh", VX_LSP(4, 0x323F), VX_LSP_MASK
, PPCLSP
, 0, {RD
, RA
}},
7653 {"zvcntlsh", VX_LSP(4, 0x3A3F), VX_LSP_MASK
, PPCLSP
, 0, {RD
, RA
}},
7654 {"znegws", VX_LSP(4, 0x4A3F), VX_LSP_MASK
, PPCLSP
, 0, {RD
, RA
}},
7655 {"zvnegh", VX_LSP(4, 0x523F), VX_LSP_MASK
, PPCLSP
, 0, {RD
, RA
}},
7656 {"zvneghs", VX_LSP(4, 0x5A3F), VX_LSP_MASK
, PPCLSP
, 0, {RD
, RA
}},
7657 {"zvnegho", VX_LSP(4, 0x623F), VX_LSP_MASK
, PPCLSP
, 0, {RD
, RA
}},
7658 {"zvneghos", VX_LSP(4, 0x6A3F), VX_LSP_MASK
, PPCLSP
, 0, {RD
, RA
}},
7659 {"zrndwh", VX_LSP(4, 0x823F), VX_LSP_MASK
, PPCLSP
, 0, {RD
, RA
}},
7660 {"zrndwhss", VX_LSP(4, 0x8A3F), VX_LSP_MASK
, PPCLSP
, 0, {RD
, RA
}},
7661 {"zvabsh", VX_LSP(4, 0xA23F), VX_LSP_MASK
, PPCLSP
, 0, {RD
, RA
}},
7662 {"zvabshs", VX_LSP(4, 0xAA3F), VX_LSP_MASK
, PPCLSP
, 0, {RD
, RA
}},
7663 {"zabsw", VX_LSP(4, 0xB23F), VX_LSP_MASK
, PPCLSP
, 0, {RD
, RA
}},
7664 {"zabsws", VX_LSP(4, 0xBA3F), VX_LSP_MASK
, PPCLSP
, 0, {RD
, RA
}},
7665 {"zsatswuw", VX_LSP(4, 0xC23F), VX_LSP_MASK
, PPCLSP
, 0, {RD
, RA
}},
7666 {"zsatuwsw", VX_LSP(4, 0xCA3F), VX_LSP_MASK
, PPCLSP
, 0, {RD
, RA
}},
7667 {"zsatswuh", VX_LSP(4, 0xD23F), VX_LSP_MASK
, PPCLSP
, 0, {RD
, RA
}},
7668 {"zsatswsh", VX_LSP(4, 0xDA3F), VX_LSP_MASK
, PPCLSP
, 0, {RD
, RA
}},
7669 {"zvsatshuh", VX_LSP(4, 0xE23F), VX_LSP_MASK
, PPCLSP
, 0, {RD
, RA
}},
7670 {"zvsatuhsh", VX_LSP(4, 0xEA3F), VX_LSP_MASK
, PPCLSP
, 0, {RD
, RA
}},
7671 {"zsatuwuh", VX_LSP(4, 0xF23F), VX_LSP_MASK
, PPCLSP
, 0, {RD
, RA
}},
7672 {"zsatuwsh", VX_LSP(4, 0xFA3F), VX_LSP_MASK
, PPCLSP
, 0, {RD
, RA
}},
7673 {"zsatsduw", VX(4, 0x260), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
7674 {"zsatsdsw", VX(4, 0x261), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
7675 {"zsatuduw", VX(4, 0x262), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
7676 {"zvselh", VX(4, 0x264), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
7677 {"zxtrw", VX(4, 0x264), VX_LSP_OFF_MASK
, PPCLSP
, 0, {RD
, RA
, RB
, VX_OFF
}},
7678 {"zbrminc", VX(4, 0x268), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
7679 {"zcircinc", VX(4, 0x269), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
7680 {"zdivwsf", VX(4, 0x26B), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
7681 {"zvsrhu", VX(4, 0x270), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
7682 {"zvsrhs", VX(4, 0x271), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
7683 {"zvsrhiu", VX(4, 0x272), VX_MASK
, PPCLSP
, 0, {RD
, RA
, EVUIMM_LT16
}},
7684 {"zvsrhis", VX(4, 0x273), VX_MASK
, PPCLSP
, 0, {RD
, RA
, EVUIMM_LT16
}},
7685 {"zvslh", VX(4, 0x274), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
7686 {"zvrlh", VX(4, 0x275), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
7687 {"zvslhi", VX(4, 0x276), VX_MASK
, PPCLSP
, 0, {RD
, RA
, EVUIMM_LT16
}},
7688 {"zvrlhi", VX(4, 0x277), VX_MASK
, PPCLSP
, 0, {RD
, RA
, EVUIMM_LT16
}},
7689 {"zvslhus", VX(4, 0x278), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
7690 {"zvslhss", VX(4, 0x279), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
7691 {"zvslhius", VX(4, 0x27A), VX_MASK
, PPCLSP
, 0, {RD
, RA
, EVUIMM_LT16
}},
7692 {"zvslhiss", VX(4, 0x27B), VX_MASK
, PPCLSP
, 0, {RD
, RA
, EVUIMM_LT16
}},
7693 {"zslwus", VX(4, 0x27C), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
7694 {"zslwss", VX(4, 0x27D), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
7695 {"zslwius", VX(4, 0x27E), VX_MASK
, PPCLSP
, 0, {RD
, RA
, EVUIMM
}},
7696 {"zslwiss", VX(4, 0x27F), VX_MASK
, PPCLSP
, 0, {RD
, RA
, EVUIMM
}},
7697 {"zaddwgui", VX(4, 0x460), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7698 {"zsubfwgui", VX(4, 0x461), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7699 {"zaddd", VX(4, 0x462), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7700 {"zsubfd", VX(4, 0x463), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7701 {"zvaddsubfw", VX(4, 0x464), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7702 {"zvsubfaddw", VX(4, 0x465), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7703 {"zvaddw", VX(4, 0x466), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7704 {"zvsubfw", VX(4, 0x467), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7705 {"zaddwgsi", VX(4, 0x468), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7706 {"zsubfwgsi", VX(4, 0x469), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7707 {"zadddss", VX(4, 0x46A), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7708 {"zsubfdss", VX(4, 0x46B), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7709 {"zvaddsubfwss", VX(4, 0x46C), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7710 {"zvsubfaddwss", VX(4, 0x46D), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7711 {"zvaddwss", VX(4, 0x46E), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
7712 {"zvsubfwss", VX(4, 0x46F), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7713 {"zaddwgsf", VX(4, 0x470), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7714 {"zsubfwgsf", VX(4, 0x471), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7715 {"zadddus", VX(4, 0x472), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7716 {"zsubfdus", VX(4, 0x473), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7717 {"zvaddwus", VX(4, 0x476), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7718 {"zvsubfwus", VX(4, 0x477), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7719 {"zvunpkhgwsf", VX_LSP(4, 0x478), VX_LSP_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
}},
7720 {"zvunpkhsf", VX_LSP(4, 0xC78), VX_LSP_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
}},
7721 {"zvunpkhui", VX_LSP(4, 0x1478), VX_LSP_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
}},
7722 {"zvunpkhsi", VX_LSP(4, 0x1C78), VX_LSP_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
}},
7723 {"zunpkwgsf", VX_LSP(4, 0x2478), VX_LSP_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
}},
7724 {"zvdotphgwasmf", VX(4, 0x488), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
7725 {"zvdotphgwasmfr", VX(4, 0x489), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
7726 {"zvdotphgwasmfaa", VX(4, 0x48A), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
7727 {"zvdotphgwasmfraa", VX(4, 0x48B), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
7728 {"zvdotphgwasmfan", VX(4, 0x48C), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
7729 {"zvdotphgwasmfran", VX(4, 0x48D), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
7730 {"zvmhulgwsmf", VX(4, 0x490), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7731 {"zvmhulgwsmfr", VX(4, 0x491), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7732 {"zvmhulgwsmfaa", VX(4, 0x492), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7733 {"zvmhulgwsmfraa", VX(4, 0x493), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7734 {"zvmhulgwsmfan", VX(4, 0x494), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7735 {"zvmhulgwsmfran", VX(4, 0x495), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7736 {"zvmhulgwsmfanp", VX(4, 0x496), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7737 {"zvmhulgwsmfranp", VX(4, 0x497), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7738 {"zmhegwsmf", VX(4, 0x498), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
7739 {"zmhegwsmfr", VX(4, 0x499), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
7740 {"zmhegwsmfaa", VX(4, 0x49A), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
7741 {"zmhegwsmfraa", VX(4, 0x49B), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
7742 {"zmhegwsmfan", VX(4, 0x49C), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
7743 {"zmhegwsmfran", VX(4, 0x49D), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
7744 {"zvdotphxgwasmf", VX(4, 0x4A8), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
7745 {"zvdotphxgwasmfr", VX(4, 0x4A9), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
7746 {"zvdotphxgwasmfaa", VX(4, 0x4AA), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
7747 {"zvdotphxgwasmfraa", VX(4, 0x4AB), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
7748 {"zvdotphxgwasmfan", VX(4, 0x4AC), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
7749 {"zvdotphxgwasmfran", VX(4, 0x4AD), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
7750 {"zvmhllgwsmf", VX(4, 0x4B0), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7751 {"zvmhllgwsmfr", VX(4, 0x4B1), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7752 {"zvmhllgwsmfaa", VX(4, 0x4B2), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7753 {"zvmhllgwsmfraa", VX(4, 0x4B3), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7754 {"zvmhllgwsmfan", VX(4, 0x4B4), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7755 {"zvmhllgwsmfran", VX(4, 0x4B5), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7756 {"zvmhllgwsmfanp", VX(4, 0x4B6), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7757 {"zvmhllgwsmfranp", VX(4, 0x4B7), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7758 {"zmheogwsmf", VX(4, 0x4B8), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
7759 {"zmheogwsmfr", VX(4, 0x4B9), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
7760 {"zmheogwsmfaa", VX(4, 0x4BA), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
7761 {"zmheogwsmfraa", VX(4, 0x4BB), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
7762 {"zmheogwsmfan", VX(4, 0x4BC), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
7763 {"zmheogwsmfran", VX(4, 0x4BD), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
7764 {"zvdotphgwssmf", VX(4, 0x4C8), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
7765 {"zvdotphgwssmfr", VX(4, 0x4C9), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
7766 {"zvdotphgwssmfaa", VX(4, 0x4CA), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
7767 {"zvdotphgwssmfraa", VX(4, 0x4CB), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
7768 {"zvdotphgwssmfan", VX(4, 0x4CC), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
7769 {"zvdotphgwssmfran", VX(4, 0x4CD), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
7770 {"zvmhuugwsmf", VX(4, 0x4D0), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7771 {"zvmhuugwsmfr", VX(4, 0x4D1), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7772 {"zvmhuugwsmfaa", VX(4, 0x4D2), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7773 {"zvmhuugwsmfraa", VX(4, 0x4D3), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7774 {"zvmhuugwsmfan", VX(4, 0x4D4), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7775 {"zvmhuugwsmfran", VX(4, 0x4D5), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7776 {"zvmhuugwsmfanp", VX(4, 0x4D6), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7777 {"zvmhuugwsmfranp", VX(4, 0x4D7), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7778 {"zmhogwsmf", VX(4, 0x4D8), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
7779 {"zmhogwsmfr", VX(4, 0x4D9), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
7780 {"zmhogwsmfaa", VX(4, 0x4DA), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
7781 {"zmhogwsmfraa", VX(4, 0x4DB), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
7782 {"zmhogwsmfan", VX(4, 0x4DC), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
7783 {"zmhogwsmfran", VX(4, 0x4DD), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
7784 {"zvmhxlgwsmf", VX(4, 0x4F0), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7785 {"zvmhxlgwsmfr", VX(4, 0x4F1), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7786 {"zvmhxlgwsmfaa", VX(4, 0x4F2), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7787 {"zvmhxlgwsmfraa", VX(4, 0x4F3), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7788 {"zvmhxlgwsmfan", VX(4, 0x4F4), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7789 {"zvmhxlgwsmfran", VX(4, 0x4F5), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7790 {"zvmhxlgwsmfanp", VX(4, 0x4F6), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7791 {"zvmhxlgwsmfranp", VX(4, 0x4F7), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7792 {"zmhegui", VX(4, 0x500), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7793 {"zvdotphgaui", VX(4, 0x501), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7794 {"zmheguiaa", VX(4, 0x502), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7795 {"zvdotphgauiaa", VX(4, 0x503), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7796 {"zmheguian", VX(4, 0x504), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7797 {"zvdotphgauian", VX(4, 0x505), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7798 {"zmhegsi", VX(4, 0x508), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7799 {"zvdotphgasi", VX(4, 0x509), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7800 {"zmhegsiaa", VX(4, 0x50A), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7801 {"zvdotphgasiaa", VX(4, 0x50B), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7802 {"zmhegsian", VX(4, 0x50C), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7803 {"zvdotphgasian", VX(4, 0x50D), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7804 {"zmhegsui", VX(4, 0x510), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7805 {"zvdotphgasui", VX(4, 0x511), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7806 {"zmhegsuiaa", VX(4, 0x512), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7807 {"zvdotphgasuiaa", VX(4, 0x513), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7808 {"zmhegsuian", VX(4, 0x514), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7809 {"zvdotphgasuian", VX(4, 0x515), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7810 {"zmhegsmf", VX(4, 0x518), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7811 {"zvdotphgasmf", VX(4, 0x519), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7812 {"zmhegsmfaa", VX(4, 0x51A), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7813 {"zvdotphgasmfaa", VX(4, 0x51B), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7814 {"zmhegsmfan", VX(4, 0x51C), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7815 {"zvdotphgasmfan", VX(4, 0x51D), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7816 {"zmheogui", VX(4, 0x520), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7817 {"zvdotphxgaui", VX(4, 0x521), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7818 {"zmheoguiaa", VX(4, 0x522), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7819 {"zvdotphxgauiaa", VX(4, 0x523), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7820 {"zmheoguian", VX(4, 0x524), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7821 {"zvdotphxgauian", VX(4, 0x525), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7822 {"zmheogsi", VX(4, 0x528), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7823 {"zvdotphxgasi", VX(4, 0x529), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7824 {"zmheogsiaa", VX(4, 0x52A), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7825 {"zvdotphxgasiaa", VX(4, 0x52B), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7826 {"zmheogsian", VX(4, 0x52C), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7827 {"zvdotphxgasian", VX(4, 0x52D), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7828 {"zmheogsui", VX(4, 0x530), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7829 {"zvdotphxgasui", VX(4, 0x531), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7830 {"zmheogsuiaa", VX(4, 0x532), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7831 {"zvdotphxgasuiaa", VX(4, 0x533), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7832 {"zmheogsuian", VX(4, 0x534), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7833 {"zvdotphxgasuian", VX(4, 0x535), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7834 {"zmheogsmf", VX(4, 0x538), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7835 {"zvdotphxgasmf", VX(4, 0x539), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7836 {"zmheogsmfaa", VX(4, 0x53A), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7837 {"zvdotphxgasmfaa", VX(4, 0x53B), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7838 {"zmheogsmfan", VX(4, 0x53C), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7839 {"zvdotphxgasmfan", VX(4, 0x53D), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7840 {"zmhogui", VX(4, 0x540), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7841 {"zvdotphgsui", VX(4, 0x541), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7842 {"zmhoguiaa", VX(4, 0x542), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7843 {"zvdotphgsuiaa", VX(4, 0x543), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7844 {"zmhoguian", VX(4, 0x544), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7845 {"zvdotphgsuian", VX(4, 0x545), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7846 {"zmhogsi", VX(4, 0x548), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7847 {"zvdotphgssi", VX(4, 0x549), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7848 {"zmhogsiaa", VX(4, 0x54A), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7849 {"zvdotphgssiaa", VX(4, 0x54B), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7850 {"zmhogsian", VX(4, 0x54C), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7851 {"zvdotphgssian", VX(4, 0x54D), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7852 {"zmhogsui", VX(4, 0x550), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7853 {"zvdotphgssui", VX(4, 0x551), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7854 {"zmhogsuiaa", VX(4, 0x552), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7855 {"zvdotphgssuiaa", VX(4, 0x553), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7856 {"zmhogsuian", VX(4, 0x554), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7857 {"zvdotphgssuian", VX(4, 0x555), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7858 {"zmhogsmf", VX(4, 0x558), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7859 {"zvdotphgssmf", VX(4, 0x559), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7860 {"zmhogsmfaa", VX(4, 0x55A), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7861 {"zvdotphgssmfaa", VX(4, 0x55B), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7862 {"zmhogsmfan", VX(4, 0x55C), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7863 {"zvdotphgssmfan", VX(4, 0x55D), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7864 {"zmwgui", VX(4, 0x560), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7865 {"zmwguiaa", VX(4, 0x562), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7866 {"zmwguiaas", VX(4, 0x563), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7867 {"zmwguian", VX(4, 0x564), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7868 {"zmwguians", VX(4, 0x565), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7869 {"zmwgsi", VX(4, 0x568), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7870 {"zmwgsiaa", VX(4, 0x56A), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7871 {"zmwgsiaas", VX(4, 0x56B), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7872 {"zmwgsian", VX(4, 0x56C), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7873 {"zmwgsians", VX(4, 0x56D), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7874 {"zmwgsui", VX(4, 0x570), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7875 {"zmwgsuiaa", VX(4, 0x572), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7876 {"zmwgsuiaas", VX(4, 0x573), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7877 {"zmwgsuian", VX(4, 0x574), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7878 {"zmwgsuians", VX(4, 0x575), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7879 {"zmwgsmf", VX(4, 0x578), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7880 {"zmwgsmfr", VX(4, 0x579), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7881 {"zmwgsmfaa", VX(4, 0x57A), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7882 {"zmwgsmfraa", VX(4, 0x57B), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7883 {"zmwgsmfan", VX(4, 0x57C), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7884 {"zmwgsmfran", VX(4, 0x57D), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7885 {"zvmhului", VX(4, 0x580), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7886 {"zvmhuluiaa", VX(4, 0x582), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7887 {"zvmhuluiaas", VX(4, 0x583), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7888 {"zvmhuluian", VX(4, 0x584), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7889 {"zvmhuluians", VX(4, 0x585), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7890 {"zvmhuluianp", VX(4, 0x586), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7891 {"zvmhuluianps", VX(4, 0x587), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7892 {"zvmhulsi", VX(4, 0x588), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7893 {"zvmhulsiaa", VX(4, 0x58A), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7894 {"zvmhulsiaas", VX(4, 0x58B), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7895 {"zvmhulsian", VX(4, 0x58C), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7896 {"zvmhulsians", VX(4, 0x58D), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7897 {"zvmhulsianp", VX(4, 0x58E), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7898 {"zvmhulsianps", VX(4, 0x58F), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7899 {"zvmhulsui", VX(4, 0x590), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7900 {"zvmhulsuiaa", VX(4, 0x592), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7901 {"zvmhulsuiaas", VX(4, 0x593), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7902 {"zvmhulsuian", VX(4, 0x594), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7903 {"zvmhulsuians", VX(4, 0x595), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7904 {"zvmhulsuianp", VX(4, 0x596), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7905 {"zvmhulsuianps", VX(4, 0x597), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7906 {"zvmhulsf", VX(4, 0x598), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7907 {"zvmhulsfr", VX(4, 0x599), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7908 {"zvmhulsfaas", VX(4, 0x59A), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7909 {"zvmhulsfraas", VX(4, 0x59B), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7910 {"zvmhulsfans", VX(4, 0x59C), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7911 {"zvmhulsfrans", VX(4, 0x59D), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7912 {"zvmhulsfanps", VX(4, 0x59E), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7913 {"zvmhulsfranps", VX(4, 0x59F), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7914 {"zvmhllui", VX(4, 0x5A0), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7915 {"zvmhlluiaa", VX(4, 0x5A2), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7916 {"zvmhlluiaas", VX(4, 0x5A3), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7917 {"zvmhlluian", VX(4, 0x5A4), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7918 {"zvmhlluians", VX(4, 0x5A5), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7919 {"zvmhlluianp", VX(4, 0x5A6), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7920 {"zvmhlluianps", VX(4, 0x5A7), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7921 {"zvmhllsi", VX(4, 0x5A8), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7922 {"zvmhllsiaa", VX(4, 0x5AA), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7923 {"zvmhllsiaas", VX(4, 0x5AB), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7924 {"zvmhllsian", VX(4, 0x5AC), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7925 {"zvmhllsians", VX(4, 0x5AD), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7926 {"zvmhllsianp", VX(4, 0x5AE), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7927 {"zvmhllsianps", VX(4, 0x5AF), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7928 {"zvmhllsui", VX(4, 0x5B0), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7929 {"zvmhllsuiaa", VX(4, 0x5B2), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7930 {"zvmhllsuiaas", VX(4, 0x5B3), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7931 {"zvmhllsuian", VX(4, 0x5B4), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7932 {"zvmhllsuians", VX(4, 0x5B5), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7933 {"zvmhllsuianp", VX(4, 0x5B6), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7934 {"zvmhllsuianps", VX(4, 0x5B7), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7935 {"zvmhllsf", VX(4, 0x5B8), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7936 {"zvmhllsfr", VX(4, 0x5B9), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7937 {"zvmhllsfaas", VX(4, 0x5BA), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7938 {"zvmhllsfraas", VX(4, 0x5BB), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7939 {"zvmhllsfans", VX(4, 0x5BC), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7940 {"zvmhllsfrans", VX(4, 0x5BD), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7941 {"zvmhllsfanps", VX(4, 0x5BE), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7942 {"zvmhllsfranps", VX(4, 0x5BF), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7943 {"zvmhuuui", VX(4, 0x5C0), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7944 {"zvmhuuuiaa", VX(4, 0x5C2), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7945 {"zvmhuuuiaas", VX(4, 0x5C3), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7946 {"zvmhuuuian", VX(4, 0x5C4), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7947 {"zvmhuuuians", VX(4, 0x5C5), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7948 {"zvmhuuuianp", VX(4, 0x5C6), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7949 {"zvmhuuuianps", VX(4, 0x5C7), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7950 {"zvmhuusi", VX(4, 0x5C8), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7951 {"zvmhuusiaa", VX(4, 0x5CA), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7952 {"zvmhuusiaas", VX(4, 0x5CB), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7953 {"zvmhuusian", VX(4, 0x5CC), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7954 {"zvmhuusians", VX(4, 0x5CD), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7955 {"zvmhuusianp", VX(4, 0x5CE), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7956 {"zvmhuusianps", VX(4, 0x5CF), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7957 {"zvmhuusui", VX(4, 0x5D0), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7958 {"zvmhuusuiaa", VX(4, 0x5D2), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7959 {"zvmhuusuiaas", VX(4, 0x5D3), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7960 {"zvmhuusuian", VX(4, 0x5D4), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7961 {"zvmhuusuians", VX(4, 0x5D5), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7962 {"zvmhuusuianp", VX(4, 0x5D6), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7963 {"zvmhuusuianps", VX(4, 0x5D7), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7964 {"zvmhuusf", VX(4, 0x5D8), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7965 {"zvmhuusfr", VX(4, 0x5D9), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7966 {"zvmhuusfaas", VX(4, 0x5DA), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7967 {"zvmhuusfraas", VX(4, 0x5DB), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7968 {"zvmhuusfans", VX(4, 0x5DC), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7969 {"zvmhuusfrans", VX(4, 0x5DD), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7970 {"zvmhuusfanps", VX(4, 0x5DE), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7971 {"zvmhuusfranps", VX(4, 0x5DF), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7972 {"zvmhxlui", VX(4, 0x5E0), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7973 {"zvmhxluiaa", VX(4, 0x5E2), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7974 {"zvmhxluiaas", VX(4, 0x5E3), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7975 {"zvmhxluian", VX(4, 0x5E4), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7976 {"zvmhxluians", VX(4, 0x5E5), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7977 {"zvmhxluianp", VX(4, 0x5E6), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7978 {"zvmhxluianps", VX(4, 0x5E7), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7979 {"zvmhxlsi", VX(4, 0x5E8), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7980 {"zvmhxlsiaa", VX(4, 0x5EA), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7981 {"zvmhxlsiaas", VX(4, 0x5EB), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7982 {"zvmhxlsian", VX(4, 0x5EC), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7983 {"zvmhxlsians", VX(4, 0x5ED), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7984 {"zvmhxlsianp", VX(4, 0x5EE), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7985 {"zvmhxlsianps", VX(4, 0x5EF), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7986 {"zvmhxlsui", VX(4, 0x5F0), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7987 {"zvmhxlsuiaa", VX(4, 0x5F2), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7988 {"zvmhxlsuiaas", VX(4, 0x5F3), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7989 {"zvmhxlsuian", VX(4, 0x5F4), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7990 {"zvmhxlsuians", VX(4, 0x5F5), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7991 {"zvmhxlsuianp", VX(4, 0x5F6), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7992 {"zvmhxlsuianps", VX(4, 0x5F7), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7993 {"zvmhxlsf", VX(4, 0x5F8), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7994 {"zvmhxlsfr", VX(4, 0x5F9), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7995 {"zvmhxlsfaas", VX(4, 0x5FA), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7996 {"zvmhxlsfraas", VX(4, 0x5FB), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7997 {"zvmhxlsfans", VX(4, 0x5FC), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7998 {"zvmhxlsfrans", VX(4, 0x5FD), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
7999 {"zvmhxlsfanps", VX(4, 0x5FE), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
8000 {"zvmhxlsfranps", VX(4, 0x5FF), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
8001 {"zmheui", VX(4, 0x600), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8002 {"zmheuiaa", VX(4, 0x602), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8003 {"zmheuiaas", VX(4, 0x603), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8004 {"zmheuian", VX(4, 0x604), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8005 {"zmheuians", VX(4, 0x605), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8006 {"zmhesi", VX(4, 0x608), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8007 {"zmhesiaa", VX(4, 0x60A), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8008 {"zmhesiaas", VX(4, 0x60B), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8009 {"zmhesian", VX(4, 0x60C), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8010 {"zmhesians", VX(4, 0x60D), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8011 {"zmhesui", VX(4, 0x610), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8012 {"zmhesuiaa", VX(4, 0x612), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8013 {"zmhesuiaas", VX(4, 0x613), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8014 {"zmhesuian", VX(4, 0x614), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8015 {"zmhesuians", VX(4, 0x615), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8016 {"zmhesf", VX(4, 0x618), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8017 {"zmhesfr", VX(4, 0x619), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8018 {"zmhesfaas", VX(4, 0x61A), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8019 {"zmhesfraas", VX(4, 0x61B), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8020 {"zmhesfans", VX(4, 0x61C), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8021 {"zmhesfrans", VX(4, 0x61D), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8022 {"zmheoui", VX(4, 0x620), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8023 {"zmheouiaa", VX(4, 0x622), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8024 {"zmheouiaas", VX(4, 0x623), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8025 {"zmheouian", VX(4, 0x624), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8026 {"zmheouians", VX(4, 0x625), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8027 {"zmheosi", VX(4, 0x628), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8028 {"zmheosiaa", VX(4, 0x62A), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8029 {"zmheosiaas", VX(4, 0x62B), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8030 {"zmheosian", VX(4, 0x62C), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8031 {"zmheosians", VX(4, 0x62D), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8032 {"zmheosui", VX(4, 0x630), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8033 {"zmheosuiaa", VX(4, 0x632), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8034 {"zmheosuiaas", VX(4, 0x633), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8035 {"zmheosuian", VX(4, 0x634), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8036 {"zmheosuians", VX(4, 0x635), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8037 {"zmheosf", VX(4, 0x638), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8038 {"zmheosfr", VX(4, 0x639), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8039 {"zmheosfaas", VX(4, 0x63A), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8040 {"zmheosfraas", VX(4, 0x63B), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8041 {"zmheosfans", VX(4, 0x63C), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8042 {"zmheosfrans", VX(4, 0x63D), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8043 {"zmhoui", VX(4, 0x640), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8044 {"zmhouiaa", VX(4, 0x642), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8045 {"zmhouiaas", VX(4, 0x643), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8046 {"zmhouian", VX(4, 0x644), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8047 {"zmhouians", VX(4, 0x645), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8048 {"zmhosi", VX(4, 0x648), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8049 {"zmhosiaa", VX(4, 0x64A), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8050 {"zmhosiaas", VX(4, 0x64B), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8051 {"zmhosian", VX(4, 0x64C), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8052 {"zmhosians", VX(4, 0x64D), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8053 {"zmhosui", VX(4, 0x650), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8054 {"zmhosuiaa", VX(4, 0x652), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8055 {"zmhosuiaas", VX(4, 0x653), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8056 {"zmhosuian", VX(4, 0x654), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8057 {"zmhosuians", VX(4, 0x655), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8058 {"zmhosf", VX(4, 0x658), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8059 {"zmhosfr", VX(4, 0x659), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8060 {"zmhosfaas", VX(4, 0x65A), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8061 {"zmhosfraas", VX(4, 0x65B), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8062 {"zmhosfans", VX(4, 0x65C), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8063 {"zmhosfrans", VX(4, 0x65D), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8064 {"zvmhuih", VX(4, 0x660), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8065 {"zvmhuihs", VX(4, 0x661), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8066 {"zvmhuiaah", VX(4, 0x662), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8067 {"zvmhuiaahs", VX(4, 0x663), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8068 {"zvmhuianh", VX(4, 0x664), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8069 {"zvmhuianhs", VX(4, 0x665), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8070 {"zvmhsihs", VX(4, 0x669), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8071 {"zvmhsiaahs", VX(4, 0x66B), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8072 {"zvmhsianhs", VX(4, 0x66D), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8073 {"zvmhsuihs", VX(4, 0x671), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8074 {"zvmhsuiaahs", VX(4, 0x673), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8075 {"zvmhsuianhs", VX(4, 0x675), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8076 {"zvmhsfh", VX(4, 0x678), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8077 {"zvmhsfrh", VX(4, 0x679), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8078 {"zvmhsfaahs", VX(4, 0x67A), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8079 {"zvmhsfraahs", VX(4, 0x67B), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8080 {"zvmhsfanhs", VX(4, 0x67C), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8081 {"zvmhsfranhs", VX(4, 0x67D), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8082 {"zvdotphaui", VX(4, 0x680), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8083 {"zvdotphauis", VX(4, 0x681), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8084 {"zvdotphauiaa", VX(4, 0x682), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8085 {"zvdotphauiaas", VX(4, 0x683), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8086 {"zvdotphauian", VX(4, 0x684), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8087 {"zvdotphauians", VX(4, 0x685), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8088 {"zvdotphasi", VX(4, 0x688), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8089 {"zvdotphasis", VX(4, 0x689), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8090 {"zvdotphasiaa", VX(4, 0x68A), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8091 {"zvdotphasiaas", VX(4, 0x68B), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8092 {"zvdotphasian", VX(4, 0x68C), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8093 {"zvdotphasians", VX(4, 0x68D), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8094 {"zvdotphasui", VX(4, 0x690), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8095 {"zvdotphasuis", VX(4, 0x691), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8096 {"zvdotphasuiaa", VX(4, 0x692), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8097 {"zvdotphasuiaas", VX(4, 0x693), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8098 {"zvdotphasuian", VX(4, 0x694), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8099 {"zvdotphasuians", VX(4, 0x695), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8100 {"zvdotphasfs", VX(4, 0x698), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8101 {"zvdotphasfrs", VX(4, 0x699), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8102 {"zvdotphasfaas", VX(4, 0x69A), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8103 {"zvdotphasfraas", VX(4, 0x69B), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8104 {"zvdotphasfans", VX(4, 0x69C), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8105 {"zvdotphasfrans", VX(4, 0x69D), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8106 {"zvdotphxaui", VX(4, 0x6A0), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8107 {"zvdotphxauis", VX(4, 0x6A1), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8108 {"zvdotphxauiaa", VX(4, 0x6A2), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8109 {"zvdotphxauiaas", VX(4, 0x6A3), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8110 {"zvdotphxauian", VX(4, 0x6A4), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8111 {"zvdotphxauians", VX(4, 0x6A5), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8112 {"zvdotphxasi", VX(4, 0x6A8), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8113 {"zvdotphxasis", VX(4, 0x6A9), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8114 {"zvdotphxasiaa", VX(4, 0x6AA), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8115 {"zvdotphxasiaas", VX(4, 0x6AB), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8116 {"zvdotphxasian", VX(4, 0x6AC), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8117 {"zvdotphxasians", VX(4, 0x6AD), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8118 {"zvdotphxasui", VX(4, 0x6B0), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8119 {"zvdotphxasuis", VX(4, 0x6B1), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8120 {"zvdotphxasuiaa", VX(4, 0x6B2), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8121 {"zvdotphxasuiaas", VX(4, 0x6B3), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8122 {"zvdotphxasuian", VX(4, 0x6B4), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8123 {"zvdotphxasuians", VX(4, 0x6B5), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8124 {"zvdotphxasfs", VX(4, 0x6B8), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8125 {"zvdotphxasfrs", VX(4, 0x6B9), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8126 {"zvdotphxasfaas", VX(4, 0x6BA), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8127 {"zvdotphxasfraas", VX(4, 0x6BB), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8128 {"zvdotphxasfans", VX(4, 0x6BC), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8129 {"zvdotphxasfrans", VX(4, 0x6BD), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8130 {"zvdotphsui", VX(4, 0x6C0), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8131 {"zvdotphsuis", VX(4, 0x6C1), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8132 {"zvdotphsuiaa", VX(4, 0x6C2), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8133 {"zvdotphsuiaas", VX(4, 0x6C3), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8134 {"zvdotphsuian", VX(4, 0x6C4), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8135 {"zvdotphsuians", VX(4, 0x6C5), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8136 {"zvdotphssi", VX(4, 0x6C8), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8137 {"zvdotphssis", VX(4, 0x6C9), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8138 {"zvdotphssiaa", VX(4, 0x6CA), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8139 {"zvdotphssiaas", VX(4, 0x6CB), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8140 {"zvdotphssian", VX(4, 0x6CC), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8141 {"zvdotphssians", VX(4, 0x6CD), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8142 {"zvdotphssui", VX(4, 0x6D0), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8143 {"zvdotphssuis", VX(4, 0x6D1), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8144 {"zvdotphssuiaa", VX(4, 0x6D2), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8145 {"zvdotphssuiaas", VX(4, 0x6D3), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8146 {"zvdotphssuian", VX(4, 0x6D4), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8147 {"zvdotphssuians", VX(4, 0x6D5), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8148 {"zvdotphssfs", VX(4, 0x6D8), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8149 {"zvdotphssfrs", VX(4, 0x6D9), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8150 {"zvdotphssfaas", VX(4, 0x6DA), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8151 {"zvdotphssfraas", VX(4, 0x6DB), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8152 {"zvdotphssfans", VX(4, 0x6DC), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8153 {"zvdotphssfrans", VX(4, 0x6DD), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8154 {"zmwluis", VX(4, 0x6E1), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8155 {"zmwluiaa", VX(4, 0x6E2), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8156 {"zmwluiaas", VX(4, 0x6E3), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8157 {"zmwluian", VX(4, 0x6E4), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8158 {"zmwluians", VX(4, 0x6E5), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8159 {"zmwlsis", VX(4, 0x6E9), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8160 {"zmwlsiaas", VX(4, 0x6EB), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8161 {"zmwlsians", VX(4, 0x6ED), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8162 {"zmwlsuis", VX(4, 0x6F1), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8163 {"zmwlsuiaas", VX(4, 0x6F3), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8164 {"zmwlsuians", VX(4, 0x6F5), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8165 {"zmwsf", VX(4, 0x6F8), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8166 {"zmwsfr", VX(4, 0x6F9), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8167 {"zmwsfaas", VX(4, 0x6FA), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8168 {"zmwsfraas", VX(4, 0x6FB), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8169 {"zmwsfans", VX(4, 0x6FC), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8170 {"zmwsfrans", VX(4, 0x6FD), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8171 {"zlddx", VX(4, 0x300), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
8172 {"zldd", VX(4, 0x301), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, EVUIMM_8
, RA
}},
8173 {"zldwx", VX(4, 0x302), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
8174 {"zldw", VX(4, 0x303), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, EVUIMM_8
, RA
}},
8175 {"zldhx", VX(4, 0x304), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
8176 {"zldh", VX(4, 0x305), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, EVUIMM_8
, RA
}},
8177 {"zlwgsfdx", VX(4, 0x308), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
8178 {"zlwgsfd", VX(4, 0x309), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, EVUIMM_4
, RA
}},
8179 {"zlwwosdx", VX(4, 0x30A), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
8180 {"zlwwosd", VX(4, 0x30B), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, EVUIMM_4
, RA
}},
8181 {"zlwhsplatwdx", VX(4, 0x30C), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
8182 {"zlwhsplatwd", VX(4, 0x30D), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, EVUIMM_4
, RA
}},
8183 {"zlwhsplatdx", VX(4, 0x30E), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
8184 {"zlwhsplatd", VX(4, 0x30F), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, EVUIMM_4
, RA
}},
8185 {"zlwhgwsfdx", VX(4, 0x310), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
8186 {"zlwhgwsfd", VX(4, 0x311), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, EVUIMM_4
, RA
}},
8187 {"zlwhedx", VX(4, 0x312), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
8188 {"zlwhed", VX(4, 0x313), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, EVUIMM_4
, RA
}},
8189 {"zlwhosdx", VX(4, 0x314), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
8190 {"zlwhosd", VX(4, 0x315), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, EVUIMM_4
, RA
}},
8191 {"zlwhoudx", VX(4, 0x316), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
8192 {"zlwhoud", VX(4, 0x317), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, EVUIMM_4
, RA
}},
8193 {"zlwhx", VX(4, 0x318), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8194 {"zlwh", VX(4, 0x319), VX_MASK
, PPCLSP
, 0, {RD
, EVUIMM_4
, RA
}},
8195 {"zlwwx", VX(4, 0x31A), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8196 {"zlww", VX(4, 0x31B), VX_MASK
, PPCLSP
, 0, {RD
, EVUIMM_4
, RA
}},
8197 {"zlhgwsfx", VX(4, 0x31C), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8198 {"zlhgwsf", VX(4, 0x31D), VX_MASK
, PPCLSP
, 0, {RD
, EVUIMM_2
, RA
}},
8199 {"zlhhsplatx", VX(4, 0x31E), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8200 {"zlhhsplat", VX(4, 0x31F), VX_MASK
, PPCLSP
, 0, {RD
, EVUIMM_2
, RA
}},
8201 {"zstddx", VX(4, 0x320), VX_MASK
, PPCLSP
, 0, {RS_EVEN
, RA
, RB
}},
8202 {"zstdd", VX(4, 0x321), VX_MASK
, PPCLSP
, 0, {RS_EVEN
, EVUIMM_8
, RA
}},
8203 {"zstdwx", VX(4, 0x322), VX_MASK
, PPCLSP
, 0, {RS_EVEN
, RA
, RB
}},
8204 {"zstdw", VX(4, 0x323), VX_MASK
, PPCLSP
, 0, {RS_EVEN
, EVUIMM_8
, RA
}},
8205 {"zstdhx", VX(4, 0x324), VX_MASK
, PPCLSP
, 0, {RS_EVEN
, RA
, RB
}},
8206 {"zstdh", VX(4, 0x325), VX_MASK
, PPCLSP
, 0, {RS_EVEN
, EVUIMM_8
, RA
}},
8207 {"zstwhedx", VX(4, 0x328), VX_MASK
, PPCLSP
, 0, {RS_EVEN
, RA
, RB
}},
8208 {"zstwhed", VX(4, 0x329), VX_MASK
, PPCLSP
, 0, {RS_EVEN
, EVUIMM_4
, RA
}},
8209 {"zstwhodx", VX(4, 0x32A), VX_MASK
, PPCLSP
, 0, {RS_EVEN
, RA
, RB
}},
8210 {"zstwhod", VX(4, 0x32B), VX_MASK
, PPCLSP
, 0, {RS_EVEN
, EVUIMM_4
, RA
}},
8211 {"zlhhex", VX(4, 0x330), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8212 {"zlhhe", VX(4, 0x331), VX_MASK
, PPCLSP
, 0, {RD
, EVUIMM_2
, RA
}},
8213 {"zlhhosx", VX(4, 0x332), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8214 {"zlhhos", VX(4, 0x333), VX_MASK
, PPCLSP
, 0, {RD
, EVUIMM_2
, RA
}},
8215 {"zlhhoux", VX(4, 0x334), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8216 {"zlhhou", VX(4, 0x335), VX_MASK
, PPCLSP
, 0, {RD
, EVUIMM_2
, RA
}},
8217 {"zsthex", VX(4, 0x338), VX_MASK
, PPCLSP
, 0, {RS
, RA
, RB
}},
8218 {"zsthe", VX(4, 0x339), VX_MASK
, PPCLSP
, 0, {RS
, EVUIMM_2
, RA
}},
8219 {"zsthox", VX(4, 0x33A), VX_MASK
, PPCLSP
, 0, {RS
, RA
, RB
}},
8220 {"zstho", VX(4, 0x33B), VX_MASK
, PPCLSP
, 0, {RS
, EVUIMM_2
, RA
}},
8221 {"zstwhx", VX(4, 0x33C), VX_MASK
, PPCLSP
, 0, {RS
, RA
, RB
}},
8222 {"zstwh", VX(4, 0x33D), VX_MASK
, PPCLSP
, 0, {RS
, EVUIMM_4
, RA
}},
8223 {"zstwwx", VX(4, 0x33E), VX_MASK
, PPCLSP
, 0, {RS
, RA
, RB
}},
8224 {"zstww", VX(4, 0x33F), VX_MASK
, PPCLSP
, 0, {RS
, EVUIMM_4
, RA
}},
8225 {"zlddmx", VX(4, 0x340), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
8226 {"zlddu", VX(4, 0x341), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, EVUIMM_8_EX0
, RA
}},
8227 {"zldwmx", VX(4, 0x342), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
8228 {"zldwu", VX(4, 0x343), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, EVUIMM_8_EX0
, RA
}},
8229 {"zldhmx", VX(4, 0x344), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
8230 {"zldhu", VX(4, 0x345), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, EVUIMM_8_EX0
, RA
}},
8231 {"zlwgsfdmx", VX(4, 0x348), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
8232 {"zlwgsfdu", VX(4, 0x349), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, EVUIMM_4_EX0
, RA
}},
8233 {"zlwwosdmx", VX(4, 0x34A), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
8234 {"zlwwosdu", VX(4, 0x34B), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, EVUIMM_4_EX0
, RA
}},
8235 {"zlwhsplatwdmx", VX(4, 0x34C), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
8236 {"zlwhsplatwdu", VX(4, 0x34D), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, EVUIMM_4_EX0
, RA
}},
8237 {"zlwhsplatdmx", VX(4, 0x34E), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
8238 {"zlwhsplatdu", VX(4, 0x34F), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, EVUIMM_4_EX0
, RA
}},
8239 {"zlwhgwsfdmx", VX(4, 0x350), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
8240 {"zlwhgwsfdu", VX(4, 0x351), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, EVUIMM_4_EX0
, RA
}},
8241 {"zlwhedmx", VX(4, 0x352), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
8242 {"zlwhedu", VX(4, 0x353), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, EVUIMM_4_EX0
, RA
}},
8243 {"zlwhosdmx", VX(4, 0x354), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
8244 {"zlwhosdu", VX(4, 0x355), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, EVUIMM_4_EX0
, RA
}},
8245 {"zlwhoudmx", VX(4, 0x356), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
8246 {"zlwhoudu", VX(4, 0x357), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, EVUIMM_4_EX0
, RA
}},
8247 {"zlwhmx", VX(4, 0x358), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8248 {"zlwhu", VX(4, 0x359), VX_MASK
, PPCLSP
, 0, {RD
, EVUIMM_4_EX0
, RA
}},
8249 {"zlwwmx", VX(4, 0x35A), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8250 {"zlwwu", VX(4, 0x35B), VX_MASK
, PPCLSP
, 0, {RD
, EVUIMM_4_EX0
, RA
}},
8251 {"zlhgwsfmx", VX(4, 0x35C), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8252 {"zlhgwsfu", VX(4, 0x35D), VX_MASK
, PPCLSP
, 0, {RD
, EVUIMM_2_EX0
, RA
}},
8253 {"zlhhsplatmx", VX(4, 0x35E), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8254 {"zlhhsplatu", VX(4, 0x35F), VX_MASK
, PPCLSP
, 0, {RD
, EVUIMM_2_EX0
, RA
}},
8255 {"zstddmx", VX(4, 0x360), VX_MASK
, PPCLSP
, 0, {RS_EVEN
, RA
, RB
}},
8256 {"zstddu", VX(4, 0x361), VX_MASK
, PPCLSP
, 0, {RS
, EVUIMM_8_EX0
, RA
}},
8257 {"zstdwmx", VX(4, 0x362), VX_MASK
, PPCLSP
, 0, {RS_EVEN
, RA
, RB
}},
8258 {"zstdwu", VX(4, 0x363), VX_MASK
, PPCLSP
, 0, {RS_EVEN
, EVUIMM_8_EX0
, RA
}},
8259 {"zstdhmx", VX(4, 0x364), VX_MASK
, PPCLSP
, 0, {RS_EVEN
, RA
, RB
}},
8260 {"zstdhu", VX(4, 0x365), VX_MASK
, PPCLSP
, 0, {RS_EVEN
, EVUIMM_8_EX0
, RA
}},
8261 {"zstwhedmx", VX(4, 0x368), VX_MASK
, PPCLSP
, 0, {RS_EVEN
, RA
, RB
}},
8262 {"zstwhedu", VX(4, 0x369), VX_MASK
, PPCLSP
, 0, {RS_EVEN
, EVUIMM_4_EX0
, RA
}},
8263 {"zstwhodmx", VX(4, 0x36A), VX_MASK
, PPCLSP
, 0, {RS_EVEN
, RA
, RB
}},
8264 {"zstwhodu", VX(4, 0x36B), VX_MASK
, PPCLSP
, 0, {RS_EVEN
, EVUIMM_4_EX0
, RA
}},
8265 {"zlhhemx", VX(4, 0x370), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8266 {"zlhheu", VX(4, 0x371), VX_MASK
, PPCLSP
, 0, {RD
, EVUIMM_2_EX0
, RA
}},
8267 {"zlhhosmx", VX(4, 0x372), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8268 {"zlhhosu", VX(4, 0x373), VX_MASK
, PPCLSP
, 0, {RD
, EVUIMM_2_EX0
, RA
}},
8269 {"zlhhoumx", VX(4, 0x374), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
8270 {"zlhhouu", VX(4, 0x375), VX_MASK
, PPCLSP
, 0, {RD
, EVUIMM_2_EX0
, RA
}},
8271 {"zsthemx", VX(4, 0x378), VX_MASK
, PPCLSP
, 0, {RS
, RA
, RB
}},
8272 {"zstheu", VX(4, 0x379), VX_MASK
, PPCLSP
, 0, {RS
, EVUIMM_2_EX0
, RA
}},
8273 {"zsthomx", VX(4, 0x37A), VX_MASK
, PPCLSP
, 0, {RS
, RA
, RB
}},
8274 {"zsthou", VX(4, 0x37B), VX_MASK
, PPCLSP
, 0, {RS
, EVUIMM_2_EX0
, RA
}},
8275 {"zstwhmx", VX(4, 0x37C), VX_MASK
, PPCLSP
, 0, {RS
, RA
, RB
}},
8276 {"zstwhu", VX(4, 0x37D), VX_MASK
, PPCLSP
, 0, {RS
, EVUIMM_4_EX0
, RA
}},
8277 {"zstwwmx", VX(4, 0x37E), VX_MASK
, PPCLSP
, 0, {RS
, RA
, RB
}},
8278 {"zstwwu", VX(4, 0x37F), VX_MASK
, PPCLSP
, 0, {RS
, EVUIMM_4_EX0
, RA
}},
8280 {"e_cmpi", SCI8BF(6,0,21), SCI8BF_MASK
, PPCVLE
, 0, {CRD32
, RA
, SCLSCI8
}},
8281 {"e_cmpwi", SCI8BF(6,0,21), SCI8BF_MASK
, PPCVLE
, 0, {CRD32
, RA
, SCLSCI8
}},
8282 {"e_cmpli", SCI8BF(6,1,21), SCI8BF_MASK
, PPCVLE
, 0, {CRD32
, RA
, SCLSCI8
}},
8283 {"e_cmplwi", SCI8BF(6,1,21), SCI8BF_MASK
, PPCVLE
, 0, {CRD32
, RA
, SCLSCI8
}},
8284 {"e_addi", SCI8(6,16), SCI8_MASK
, PPCVLE
, 0, {RT
, RA
, SCLSCI8
}},
8285 {"e_subi", SCI8(6,16), SCI8_MASK
, PPCVLE
, 0, {RT
, RA
, SCLSCI8N
}},
8286 {"e_addi.", SCI8(6,17), SCI8_MASK
, PPCVLE
, 0, {RT
, RA
, SCLSCI8
}},
8287 {"e_addic", SCI8(6,18), SCI8_MASK
, PPCVLE
, 0, {RT
, RA
, SCLSCI8
}},
8288 {"e_subic", SCI8(6,18), SCI8_MASK
, PPCVLE
, 0, {RT
, RA
, SCLSCI8N
}},
8289 {"e_addic.", SCI8(6,19), SCI8_MASK
, PPCVLE
, 0, {RT
, RA
, SCLSCI8
}},
8290 {"e_subic.", SCI8(6,19), SCI8_MASK
, PPCVLE
, 0, {RT
, RA
, SCLSCI8N
}},
8291 {"e_mulli", SCI8(6,20), SCI8_MASK
, PPCVLE
, 0, {RT
, RA
, SCLSCI8
}},
8292 {"e_subfic", SCI8(6,22), SCI8_MASK
, PPCVLE
, 0, {RT
, RA
, SCLSCI8
}},
8293 {"e_subfic.", SCI8(6,23), SCI8_MASK
, PPCVLE
, 0, {RT
, RA
, SCLSCI8
}},
8294 {"e_andi", SCI8(6,24), SCI8_MASK
, PPCVLE
, 0, {RA
, RS
, SCLSCI8
}},
8295 {"e_andi.", SCI8(6,25), SCI8_MASK
, PPCVLE
, 0, {RA
, RS
, SCLSCI8
}},
8296 {"e_nop", SCI8(6,26), 0xffffffff, PPCVLE
, 0, {0}},
8297 {"e_ori", SCI8(6,26), SCI8_MASK
, PPCVLE
, 0, {RA
, RS
, SCLSCI8
}},
8298 {"e_ori.", SCI8(6,27), SCI8_MASK
, PPCVLE
, 0, {RA
, RS
, SCLSCI8
}},
8299 {"e_xori", SCI8(6,28), SCI8_MASK
, PPCVLE
, 0, {RA
, RS
, SCLSCI8
}},
8300 {"e_xori.", SCI8(6,29), SCI8_MASK
, PPCVLE
, 0, {RA
, RS
, SCLSCI8
}},
8301 {"e_lbzu", OPVUP(6,0), OPVUP_MASK
, PPCVLE
, 0, {RT
, D8
, RA0
}},
8302 {"e_lhau", OPVUP(6,3), OPVUP_MASK
, PPCVLE
, 0, {RT
, D8
, RA0
}},
8303 {"e_lhzu", OPVUP(6,1), OPVUP_MASK
, PPCVLE
, 0, {RT
, D8
, RA0
}},
8304 {"e_lmw", OPVUP(6,8), OPVUP_MASK
, PPCVLE
, 0, {RT
, D8
, RA0
}},
8305 {"e_lwzu", OPVUP(6,2), OPVUP_MASK
, PPCVLE
, 0, {RT
, D8
, RA0
}},
8306 {"e_stbu", OPVUP(6,4), OPVUP_MASK
, PPCVLE
, 0, {RT
, D8
, RA0
}},
8307 {"e_sthu", OPVUP(6,5), OPVUP_MASK
, PPCVLE
, 0, {RT
, D8
, RA0
}},
8308 {"e_stwu", OPVUP(6,6), OPVUP_MASK
, PPCVLE
, 0, {RT
, D8
, RA0
}},
8309 {"e_stmw", OPVUP(6,9), OPVUP_MASK
, PPCVLE
, 0, {RT
, D8
, RA0
}},
8310 {"e_lmvgprw", OPVUPRT(6,16,0),OPVUPRT_MASK
, PPCVLE
, 0, {D8
, RA0
}},
8311 {"e_ldmvgprw", OPVUPRT(6,16,0),OPVUPRT_MASK
, PPCVLE
, 0, {D8
, RA0
}},
8312 {"e_stmvgprw", OPVUPRT(6,17,0),OPVUPRT_MASK
, PPCVLE
, 0, {D8
, RA0
}},
8313 {"e_lmvsprw", OPVUPRT(6,16,1),OPVUPRT_MASK
, PPCVLE
, 0, {D8
, RA0
}},
8314 {"e_ldmvsprw", OPVUPRT(6,16,1),OPVUPRT_MASK
, PPCVLE
, 0, {D8
, RA0
}},
8315 {"e_stmvsprw", OPVUPRT(6,17,1),OPVUPRT_MASK
, PPCVLE
, 0, {D8
, RA0
}},
8316 {"e_lmvsrrw", OPVUPRT(6,16,4),OPVUPRT_MASK
, PPCVLE
, 0, {D8
, RA0
}},
8317 {"e_ldmvsrrw", OPVUPRT(6,16,4),OPVUPRT_MASK
, PPCVLE
, 0, {D8
, RA0
}},
8318 {"e_stmvsrrw", OPVUPRT(6,17,4),OPVUPRT_MASK
, PPCVLE
, 0, {D8
, RA0
}},
8319 {"e_lmvcsrrw", OPVUPRT(6,16,5),OPVUPRT_MASK
, PPCVLE
, 0, {D8
, RA0
}},
8320 {"e_ldmvcsrrw", OPVUPRT(6,16,5),OPVUPRT_MASK
, PPCVLE
, 0, {D8
, RA0
}},
8321 {"e_stmvcsrrw", OPVUPRT(6,17,5),OPVUPRT_MASK
, PPCVLE
, 0, {D8
, RA0
}},
8322 {"e_lmvdsrrw", OPVUPRT(6,16,6),OPVUPRT_MASK
, PPCVLE
, 0, {D8
, RA0
}},
8323 {"e_ldmvdsrrw", OPVUPRT(6,16,6),OPVUPRT_MASK
, PPCVLE
, 0, {D8
, RA0
}},
8324 {"e_stmvdsrrw", OPVUPRT(6,17,6),OPVUPRT_MASK
, PPCVLE
, 0, {D8
, RA0
}},
8325 {"e_lmvmcsrrw", OPVUPRT(6,16,7),OPVUPRT_MASK
, PPCVLE
, 0, {D8
, RA0
}},
8326 {"e_stmvmcsrrw", OPVUPRT(6,17,7),OPVUPRT_MASK
, PPCVLE
, 0, {D8
, RA0
}},
8327 {"e_add16i", OP(7), OP_MASK
, PPCVLE
, 0, {RT
, RA
, SI
}},
8328 {"e_la", OP(7), OP_MASK
, PPCVLE
, 0, {RT
, D
, RA0
}},
8329 {"e_sub16i", OP(7), OP_MASK
, PPCVLE
, 0, {RT
, RA
, NSI
}},
8331 {"se_addi", SE_IM5(8,0), SE_IM5_MASK
, PPCVLE
, 0, {RX
, OIMM5
}},
8332 {"se_cmpli", SE_IM5(8,1), SE_IM5_MASK
, PPCVLE
, 0, {RX
, OIMM5
}},
8333 {"se_subi", SE_IM5(9,0), SE_IM5_MASK
, PPCVLE
, 0, {RX
, OIMM5
}},
8334 {"se_subi.", SE_IM5(9,1), SE_IM5_MASK
, PPCVLE
, 0, {RX
, OIMM5
}},
8335 {"se_cmpi", SE_IM5(10,1), SE_IM5_MASK
, PPCVLE
, 0, {RX
, UI5
}},
8336 {"se_bmaski", SE_IM5(11,0), SE_IM5_MASK
, PPCVLE
, 0, {RX
, UI5
}},
8337 {"se_andi", SE_IM5(11,1), SE_IM5_MASK
, PPCVLE
, 0, {RX
, UI5
}},
8339 {"e_lbz", OP(12), OP_MASK
, PPCVLE
, 0, {RT
, D
, RA0
}},
8340 {"e_stb", OP(13), OP_MASK
, PPCVLE
, 0, {RT
, D
, RA0
}},
8341 {"e_lha", OP(14), OP_MASK
, PPCVLE
, 0, {RT
, D
, RA0
}},
8343 {"se_srw", SE_RR(16,0), SE_RR_MASK
, PPCVLE
, 0, {RX
, RY
}},
8344 {"se_sraw", SE_RR(16,1), SE_RR_MASK
, PPCVLE
, 0, {RX
, RY
}},
8345 {"se_slw", SE_RR(16,2), SE_RR_MASK
, PPCVLE
, 0, {RX
, RY
}},
8346 {"se_nop", SE_RR(17,0), 0xffff, PPCVLE
, 0, {0}},
8347 {"se_or", SE_RR(17,0), SE_RR_MASK
, PPCVLE
, 0, {RX
, RY
}},
8348 {"se_andc", SE_RR(17,1), SE_RR_MASK
, PPCVLE
, 0, {RX
, RY
}},
8349 {"se_and", SE_RR(17,2), SE_RR_MASK
, PPCVLE
, 0, {RX
, RY
}},
8350 {"se_and.", SE_RR(17,3), SE_RR_MASK
, PPCVLE
, 0, {RX
, RY
}},
8351 {"se_li", IM7(9), IM7_MASK
, PPCVLE
, 0, {RX
, UI7
}},
8353 {"e_lwz", OP(20), OP_MASK
, PPCVLE
, 0, {RT
, D
, RA0
}},
8354 {"e_stw", OP(21), OP_MASK
, PPCVLE
, 0, {RT
, D
, RA0
}},
8355 {"e_lhz", OP(22), OP_MASK
, PPCVLE
, 0, {RT
, D
, RA0
}},
8356 {"e_sth", OP(23), OP_MASK
, PPCVLE
, 0, {RT
, D
, RA0
}},
8358 {"se_bclri", SE_IM5(24,0), SE_IM5_MASK
, PPCVLE
, 0, {RX
, UI5
}},
8359 {"se_bgeni", SE_IM5(24,1), SE_IM5_MASK
, PPCVLE
, 0, {RX
, UI5
}},
8360 {"se_bseti", SE_IM5(25,0), SE_IM5_MASK
, PPCVLE
, 0, {RX
, UI5
}},
8361 {"se_btsti", SE_IM5(25,1), SE_IM5_MASK
, PPCVLE
, 0, {RX
, UI5
}},
8362 {"se_srwi", SE_IM5(26,0), SE_IM5_MASK
, PPCVLE
, 0, {RX
, UI5
}},
8363 {"se_srawi", SE_IM5(26,1), SE_IM5_MASK
, PPCVLE
, 0, {RX
, UI5
}},
8364 {"se_slwi", SE_IM5(27,0), SE_IM5_MASK
, PPCVLE
, 0, {RX
, UI5
}},
8366 {"e_lis", I16L(28,28), I16L_MASK
, PPCVLE
, 0, {RD
, VLEUIMML
}},
8367 {"e_and2is.", I16L(28,29), I16L_MASK
, PPCVLE
, 0, {RD
, VLEUIMML
}},
8368 {"e_or2is", I16L(28,26), I16L_MASK
, PPCVLE
, 0, {RD
, VLEUIMML
}},
8369 {"e_and2i.", I16L(28,25), I16L_MASK
, PPCVLE
, 0, {RD
, VLEUIMML
}},
8370 {"e_or2i", I16L(28,24), I16L_MASK
, PPCVLE
, 0, {RD
, VLEUIMML
}},
8371 {"e_cmphl16i", IA16(28,23), IA16_MASK
, PPCVLE
, 0, {RA
, VLEUIMM
}},
8372 {"e_cmph16i", IA16(28,22), IA16_MASK
, PPCVLE
, 0, {RA
, VLESIMM
}},
8373 {"e_cmpl16i", I16A(28,21), I16A_MASK
, PPCVLE
, 0, {RA
, VLEUIMM
}},
8374 {"e_mull2i", I16A(28,20), I16A_MASK
, PPCVLE
, 0, {RA
, VLESIMM
}},
8375 {"e_cmp16i", IA16(28,19), IA16_MASK
, PPCVLE
, 0, {RA
, VLESIMM
}},
8376 {"e_sub2is", I16A(28,18), I16A_MASK
, PPCVLE
, 0, {RA
, VLENSIMM
}},
8377 {"e_add2is", I16A(28,18), I16A_MASK
, PPCVLE
, 0, {RA
, VLESIMM
}},
8378 {"e_sub2i.", I16A(28,17), I16A_MASK
, PPCVLE
, 0, {RA
, VLENSIMM
}},
8379 {"e_add2i.", I16A(28,17), I16A_MASK
, PPCVLE
, 0, {RA
, VLESIMM
}},
8380 {"e_li", LI20(28,0), LI20_MASK
, PPCVLE
, 0, {RT
, IMM20
}},
8381 {"e_rlwimi", M(29,0), M_MASK
, PPCVLE
, 0, {RA
, RS
, SH
, MB
, ME
}},
8382 {"e_rlwinm", M(29,1), M_MASK
, PPCVLE
, 0, {RA
, RT
, SH
, MBE
, ME
}},
8383 {"e_b", BD24(30,0,0), BD24_MASK
, PPCVLE
, 0, {B24
}},
8384 {"e_bl", BD24(30,0,1), BD24_MASK
, PPCVLE
, 0, {B24
}},
8385 {"e_bdnz", EBD15(30,8,BO32DNZ
,0), EBD15_MASK
, PPCVLE
, 0, {B15
}},
8386 {"e_bdnzl", EBD15(30,8,BO32DNZ
,1), EBD15_MASK
, PPCVLE
, 0, {B15
}},
8387 {"e_bdz", EBD15(30,8,BO32DZ
,0), EBD15_MASK
, PPCVLE
, 0, {B15
}},
8388 {"e_bdzl", EBD15(30,8,BO32DZ
,1), EBD15_MASK
, PPCVLE
, 0, {B15
}},
8389 {"e_bge", EBD15BI(30,8,BO32F
,CBLT
,0), EBD15BI_MASK
, PPCVLE
, 0, {CRS
,B15
}},
8390 {"e_bgel", EBD15BI(30,8,BO32F
,CBLT
,1), EBD15BI_MASK
, PPCVLE
, 0, {CRS
,B15
}},
8391 {"e_bnl", EBD15BI(30,8,BO32F
,CBLT
,0), EBD15BI_MASK
, PPCVLE
, 0, {CRS
,B15
}},
8392 {"e_bnll", EBD15BI(30,8,BO32F
,CBLT
,1), EBD15BI_MASK
, PPCVLE
, 0, {CRS
,B15
}},
8393 {"e_blt", EBD15BI(30,8,BO32T
,CBLT
,0), EBD15BI_MASK
, PPCVLE
, 0, {CRS
,B15
}},
8394 {"e_bltl", EBD15BI(30,8,BO32T
,CBLT
,1), EBD15BI_MASK
, PPCVLE
, 0, {CRS
,B15
}},
8395 {"e_bgt", EBD15BI(30,8,BO32T
,CBGT
,0), EBD15BI_MASK
, PPCVLE
, 0, {CRS
,B15
}},
8396 {"e_bgtl", EBD15BI(30,8,BO32T
,CBGT
,1), EBD15BI_MASK
, PPCVLE
, 0, {CRS
,B15
}},
8397 {"e_ble", EBD15BI(30,8,BO32F
,CBGT
,0), EBD15BI_MASK
, PPCVLE
, 0, {CRS
,B15
}},
8398 {"e_blel", EBD15BI(30,8,BO32F
,CBGT
,1), EBD15BI_MASK
, PPCVLE
, 0, {CRS
,B15
}},
8399 {"e_bng", EBD15BI(30,8,BO32F
,CBGT
,0), EBD15BI_MASK
, PPCVLE
, 0, {CRS
,B15
}},
8400 {"e_bngl", EBD15BI(30,8,BO32F
,CBGT
,1), EBD15BI_MASK
, PPCVLE
, 0, {CRS
,B15
}},
8401 {"e_bne", EBD15BI(30,8,BO32F
,CBEQ
,0), EBD15BI_MASK
, PPCVLE
, 0, {CRS
,B15
}},
8402 {"e_bnel", EBD15BI(30,8,BO32F
,CBEQ
,1), EBD15BI_MASK
, PPCVLE
, 0, {CRS
,B15
}},
8403 {"e_beq", EBD15BI(30,8,BO32T
,CBEQ
,0), EBD15BI_MASK
, PPCVLE
, 0, {CRS
,B15
}},
8404 {"e_beql", EBD15BI(30,8,BO32T
,CBEQ
,1), EBD15BI_MASK
, PPCVLE
, 0, {CRS
,B15
}},
8405 {"e_bso", EBD15BI(30,8,BO32T
,CBSO
,0), EBD15BI_MASK
, PPCVLE
, 0, {CRS
,B15
}},
8406 {"e_bsol", EBD15BI(30,8,BO32T
,CBSO
,1), EBD15BI_MASK
, PPCVLE
, 0, {CRS
,B15
}},
8407 {"e_bun", EBD15BI(30,8,BO32T
,CBSO
,0), EBD15BI_MASK
, PPCVLE
, 0, {CRS
,B15
}},
8408 {"e_bunl", EBD15BI(30,8,BO32T
,CBSO
,1), EBD15BI_MASK
, PPCVLE
, 0, {CRS
,B15
}},
8409 {"e_bns", EBD15BI(30,8,BO32F
,CBSO
,0), EBD15BI_MASK
, PPCVLE
, 0, {CRS
,B15
}},
8410 {"e_bnsl", EBD15BI(30,8,BO32F
,CBSO
,1), EBD15BI_MASK
, PPCVLE
, 0, {CRS
,B15
}},
8411 {"e_bnu", EBD15BI(30,8,BO32F
,CBSO
,0), EBD15BI_MASK
, PPCVLE
, 0, {CRS
,B15
}},
8412 {"e_bnul", EBD15BI(30,8,BO32F
,CBSO
,1), EBD15BI_MASK
, PPCVLE
, 0, {CRS
,B15
}},
8413 {"e_bc", BD15(30,8,0), BD15_MASK
, PPCVLE
, 0, {BO32
, BI32
, B15
}},
8414 {"e_bcl", BD15(30,8,1), BD15_MASK
, PPCVLE
, 0, {BO32
, BI32
, B15
}},
8416 {"e_bf", EBD15(30,8,BO32F
,0), EBD15_MASK
, PPCVLE
, 0, {BI32
,B15
}},
8417 {"e_bfl", EBD15(30,8,BO32F
,1), EBD15_MASK
, PPCVLE
, 0, {BI32
,B15
}},
8418 {"e_bt", EBD15(30,8,BO32T
,0), EBD15_MASK
, PPCVLE
, 0, {BI32
,B15
}},
8419 {"e_btl", EBD15(30,8,BO32T
,1), EBD15_MASK
, PPCVLE
, 0, {BI32
,B15
}},
8421 {"e_cmph", X(31,14), X_MASK
, PPCVLE
, 0, {CRD
, RA
, RB
}},
8422 {"e_sc", X(31,36), XRTRA_MASK
, PPCVLE
, 0, {ELEV
}},
8423 {"e_cmphl", X(31,46), X_MASK
, PPCVLE
, 0, {CRD
, RA
, RB
}},
8424 {"e_crandc", XL(31,129), XL_MASK
, PPCVLE
, 0, {BT
, BA
, BB
}},
8425 {"e_crnand", XL(31,225), XL_MASK
, PPCVLE
, 0, {BT
, BA
, BB
}},
8426 {"e_crnot", XL(31,33), XL_MASK
, PPCVLE
, 0, {BT
, BA
, BBA
}},
8427 {"e_crnor", XL(31,33), XL_MASK
, PPCVLE
, 0, {BT
, BA
, BB
}},
8428 {"e_crclr", XL(31,193), XL_MASK
, PPCVLE
, 0, {BT
, BAT
, BBA
}},
8429 {"e_crxor", XL(31,193), XL_MASK
, PPCVLE
, 0, {BT
, BA
, BB
}},
8430 {"e_mcrf", XL(31,16), XL_MASK
, PPCVLE
, 0, {CRD
, CR
}},
8431 {"e_slwi", EX(31,112), EX_MASK
, PPCVLE
, 0, {RA
, RS
, SH
}},
8432 {"e_slwi.", EX(31,113), EX_MASK
, PPCVLE
, 0, {RA
, RS
, SH
}},
8434 {"e_crand", XL(31,257), XL_MASK
, PPCVLE
, 0, {BT
, BA
, BB
}},
8436 {"e_rlw", EX(31,560), EX_MASK
, PPCVLE
, 0, {RA
, RS
, RB
}},
8437 {"e_rlw.", EX(31,561), EX_MASK
, PPCVLE
, 0, {RA
, RS
, RB
}},
8439 {"e_crset", XL(31,289), XL_MASK
, PPCVLE
, 0, {BT
, BAT
, BBA
}},
8440 {"e_creqv", XL(31,289), XL_MASK
, PPCVLE
, 0, {BT
, BA
, BB
}},
8442 {"e_rlwi", EX(31,624), EX_MASK
, PPCVLE
, 0, {RA
, RS
, SH
}},
8443 {"e_rlwi.", EX(31,625), EX_MASK
, PPCVLE
, 0, {RA
, RS
, SH
}},
8445 {"e_crorc", XL(31,417), XL_MASK
, PPCVLE
, 0, {BT
, BA
, BB
}},
8447 {"e_crmove", XL(31,449), XL_MASK
, PPCVLE
, 0, {BT
, BA
, BBA
}},
8448 {"e_cror", XL(31,449), XL_MASK
, PPCVLE
, 0, {BT
, BA
, BB
}},
8450 {"mtmas1", XSPR(31,467,625), XSPR_MASK
, PPCVLE
, 0, {RS
}},
8452 {"e_srwi", EX(31,1136), EX_MASK
, PPCVLE
, 0, {RA
, RS
, SH
}},
8453 {"e_srwi.", EX(31,1137), EX_MASK
, PPCVLE
, 0, {RA
, RS
, SH
}},
8455 {"se_lbz", SD4(8), SD4_MASK
, PPCVLE
, 0, {RZ
, SE_SD
, RX
}},
8457 {"se_stb", SD4(9), SD4_MASK
, PPCVLE
, 0, {RZ
, SE_SD
, RX
}},
8459 {"se_lhz", SD4(10), SD4_MASK
, PPCVLE
, 0, {RZ
, SE_SDH
, RX
}},
8461 {"se_sth", SD4(11), SD4_MASK
, PPCVLE
, 0, {RZ
, SE_SDH
, RX
}},
8463 {"se_lwz", SD4(12), SD4_MASK
, PPCVLE
, 0, {RZ
, SE_SDW
, RX
}},
8465 {"se_stw", SD4(13), SD4_MASK
, PPCVLE
, 0, {RZ
, SE_SDW
, RX
}},
8467 {"se_bge", EBD8IO(28,0,0), EBD8IO3_MASK
, PPCVLE
, 0, {B8
}},
8468 {"se_bnl", EBD8IO(28,0,0), EBD8IO3_MASK
, PPCVLE
, 0, {B8
}},
8469 {"se_ble", EBD8IO(28,0,1), EBD8IO3_MASK
, PPCVLE
, 0, {B8
}},
8470 {"se_bng", EBD8IO(28,0,1), EBD8IO3_MASK
, PPCVLE
, 0, {B8
}},
8471 {"se_bne", EBD8IO(28,0,2), EBD8IO3_MASK
, PPCVLE
, 0, {B8
}},
8472 {"se_bns", EBD8IO(28,0,3), EBD8IO3_MASK
, PPCVLE
, 0, {B8
}},
8473 {"se_bnu", EBD8IO(28,0,3), EBD8IO3_MASK
, PPCVLE
, 0, {B8
}},
8474 {"se_bf", EBD8IO(28,0,0), EBD8IO2_MASK
, PPCVLE
, 0, {BI16
, B8
}},
8475 {"se_blt", EBD8IO(28,1,0), EBD8IO3_MASK
, PPCVLE
, 0, {B8
}},
8476 {"se_bgt", EBD8IO(28,1,1), EBD8IO3_MASK
, PPCVLE
, 0, {B8
}},
8477 {"se_beq", EBD8IO(28,1,2), EBD8IO3_MASK
, PPCVLE
, 0, {B8
}},
8478 {"se_bso", EBD8IO(28,1,3), EBD8IO3_MASK
, PPCVLE
, 0, {B8
}},
8479 {"se_bun", EBD8IO(28,1,3), EBD8IO3_MASK
, PPCVLE
, 0, {B8
}},
8480 {"se_bt", EBD8IO(28,1,0), EBD8IO2_MASK
, PPCVLE
, 0, {BI16
, B8
}},
8481 {"se_bc", BD8IO(28), BD8IO_MASK
, PPCVLE
, 0, {BO16
, BI16
, B8
}},
8482 {"se_b", BD8(58,0,0), BD8_MASK
, PPCVLE
, 0, {B8
}},
8483 {"se_bl", BD8(58,0,1), BD8_MASK
, PPCVLE
, 0, {B8
}},
8486 const int vle_num_opcodes
=
8487 sizeof (vle_opcodes
) / sizeof (vle_opcodes
[0]);
8489 /* The macro table. This is only used by the assembler. */
8491 /* The expressions of the form (-x ! 31) & (x | 31) have the value 0
8492 when x=0; 32-x when x is between 1 and 31; are negative if x is
8493 negative; and are 32 or more otherwise. This is what you want
8494 when, for instance, you are emulating a right shift by a
8495 rotate-left-and-mask, because the underlying instructions support
8496 shifts of size 0 but not shifts of size 32. By comparison, when
8497 extracting x bits from some word you want to use just 32-x, because
8498 the underlying instructions don't support extracting 0 bits but do
8499 support extracting the whole word (32 bits in this case). */
8501 const struct powerpc_macro powerpc_macros
[] = {
8502 {"extldi", 4, PPC64
, "rldicr %0,%1,%3,(%2)-1"},
8503 {"extldi.", 4, PPC64
, "rldicr. %0,%1,%3,(%2)-1"},
8504 {"extrdi", 4, PPC64
, "rldicl %0,%1,((%2)+(%3))&((%2)+(%3)<>64),64-(%2)"},
8505 {"extrdi.", 4, PPC64
, "rldicl. %0,%1,((%2)+(%3))&((%2)+(%3)<>64),64-(%2)"},
8506 {"insrdi", 4, PPC64
, "rldimi %0,%1,64-((%2)+(%3)),%3"},
8507 {"insrdi.", 4, PPC64
, "rldimi. %0,%1,64-((%2)+(%3)),%3"},
8508 {"rotrdi", 3, PPC64
, "rldicl %0,%1,(-(%2)!63)&((%2)|63),0"},
8509 {"rotrdi.", 3, PPC64
, "rldicl. %0,%1,(-(%2)!63)&((%2)|63),0"},
8510 {"sldi", 3, PPC64
, "rldicr %0,%1,%2,63-(%2)"},
8511 {"sldi.", 3, PPC64
, "rldicr. %0,%1,%2,63-(%2)"},
8512 {"srdi", 3, PPC64
, "rldicl %0,%1,(-(%2)!63)&((%2)|63),%2"},
8513 {"srdi.", 3, PPC64
, "rldicl. %0,%1,(-(%2)!63)&((%2)|63),%2"},
8514 {"clrrdi", 3, PPC64
, "rldicr %0,%1,0,63-(%2)"},
8515 {"clrrdi.", 3, PPC64
, "rldicr. %0,%1,0,63-(%2)"},
8516 {"clrlsldi", 4, PPC64
, "rldic %0,%1,%3,(%2)-(%3)"},
8517 {"clrlsldi.",4, PPC64
, "rldic. %0,%1,%3,(%2)-(%3)"},
8519 {"extlwi", 4, PPCCOM
, "rlwinm %0,%1,%3,0,(%2)-1"},
8520 {"extlwi.", 4, PPCCOM
, "rlwinm. %0,%1,%3,0,(%2)-1"},
8521 {"extrwi", 4, PPCCOM
, "rlwinm %0,%1,((%2)+(%3))&((%2)+(%3)<>32),32-(%2),31"},
8522 {"extrwi.", 4, PPCCOM
, "rlwinm. %0,%1,((%2)+(%3))&((%2)+(%3)<>32),32-(%2),31"},
8523 {"inslwi", 4, PPCCOM
, "rlwimi %0,%1,(-(%3)!31)&((%3)|31),%3,(%2)+(%3)-1"},
8524 {"inslwi.", 4, PPCCOM
, "rlwimi. %0,%1,(-(%3)!31)&((%3)|31),%3,(%2)+(%3)-1"},
8525 {"insrwi", 4, PPCCOM
, "rlwimi %0,%1,32-((%2)+(%3)),%3,(%2)+(%3)-1"},
8526 {"insrwi.", 4, PPCCOM
, "rlwimi. %0,%1,32-((%2)+(%3)),%3,(%2)+(%3)-1"},
8527 {"rotrwi", 3, PPCCOM
, "rlwinm %0,%1,(-(%2)!31)&((%2)|31),0,31"},
8528 {"rotrwi.", 3, PPCCOM
, "rlwinm. %0,%1,(-(%2)!31)&((%2)|31),0,31"},
8529 {"slwi", 3, PPCCOM
, "rlwinm %0,%1,%2,0,31-(%2)"},
8530 {"sli", 3, PWRCOM
, "rlinm %0,%1,%2,0,31-(%2)"},
8531 {"slwi.", 3, PPCCOM
, "rlwinm. %0,%1,%2,0,31-(%2)"},
8532 {"sli.", 3, PWRCOM
, "rlinm. %0,%1,%2,0,31-(%2)"},
8533 {"srwi", 3, PPCCOM
, "rlwinm %0,%1,(-(%2)!31)&((%2)|31),%2,31"},
8534 {"sri", 3, PWRCOM
, "rlinm %0,%1,(-(%2)!31)&((%2)|31),%2,31"},
8535 {"srwi.", 3, PPCCOM
, "rlwinm. %0,%1,(-(%2)!31)&((%2)|31),%2,31"},
8536 {"sri.", 3, PWRCOM
, "rlinm. %0,%1,(-(%2)!31)&((%2)|31),%2,31"},
8537 {"clrrwi", 3, PPCCOM
, "rlwinm %0,%1,0,0,31-(%2)"},
8538 {"clrrwi.", 3, PPCCOM
, "rlwinm. %0,%1,0,0,31-(%2)"},
8539 {"clrlslwi", 4, PPCCOM
, "rlwinm %0,%1,%3,(%2)-(%3),31-(%3)"},
8540 {"clrlslwi.",4, PPCCOM
, "rlwinm. %0,%1,%3,(%2)-(%3),31-(%3)"},
8542 {"e_extlwi", 4, PPCVLE
, "e_rlwinm %0,%1,%3,0,(%2)-1"},
8543 {"e_extrwi", 4, PPCVLE
, "e_rlwinm %0,%1,((%2)+(%3))&((%2)+(%3)<>32),32-(%2),31"},
8544 {"e_inslwi", 4, PPCVLE
, "e_rlwimi %0,%1,(-(%3)!31)&((%3)|31),%3,(%2)+(%3)-1"},
8545 {"e_insrwi", 4, PPCVLE
, "e_rlwimi %0,%1,32-((%2)+(%3)),%3,(%2)+(%3)-1"},
8546 {"e_rotlwi", 3, PPCVLE
, "e_rlwinm %0,%1,%2,0,31"},
8547 {"e_rotrwi", 3, PPCVLE
, "e_rlwinm %0,%1,(-(%2)!31)&((%2)|31),0,31"},
8548 {"e_slwi", 3, PPCVLE
, "e_rlwinm %0,%1,%2,0,31-(%2)"},
8549 {"e_srwi", 3, PPCVLE
, "e_rlwinm %0,%1,(-(%2)!31)&((%2)|31),%2,31"},
8550 {"e_clrlwi", 3, PPCVLE
, "e_rlwinm %0,%1,0,%2,31"},
8551 {"e_clrrwi", 3, PPCVLE
, "e_rlwinm %0,%1,0,0,31-(%2)"},
8552 {"e_clrlslwi",4, PPCVLE
, "e_rlwinm %0,%1,%3,(%2)-(%3),31-(%3)"},
8554 /* old SPE instructions have new names with the same opcodes */
8555 {"evsadd", 3, PPCSPE
|PPCVLE
, "efsadd %0,%1,%2"},
8556 {"evssub", 3, PPCSPE
|PPCVLE
, "efssub %0,%1,%2"},
8557 {"evsabs", 2, PPCSPE
|PPCVLE
, "efsabs %0,%1"},
8558 {"evsnabs", 2, PPCSPE
|PPCVLE
, "efsnabs %0,%1"},
8559 {"evsneg", 2, PPCSPE
|PPCVLE
, "efsneg %0,%1"},
8560 {"evsmul", 3, PPCSPE
|PPCVLE
, "efsmul %0,%1,%2"},
8561 {"evsdiv", 3, PPCSPE
|PPCVLE
, "efsdiv %0,%1,%2"},
8562 {"evscmpgt", 3, PPCSPE
|PPCVLE
, "efscmpgt %0,%1,%2"},
8563 {"evsgmplt", 3, PPCSPE
|PPCVLE
, "efscmplt %0,%1,%2"},
8564 {"evsgmpeq", 3, PPCSPE
|PPCVLE
, "efscmpeq %0,%1,%2"},
8565 {"evscfui", 2, PPCSPE
|PPCVLE
, "efscfui %0,%1"},
8566 {"evscfsi", 2, PPCSPE
|PPCVLE
, "efscfsi %0,%1"},
8567 {"evscfuf", 2, PPCSPE
|PPCVLE
, "efscfuf %0,%1"},
8568 {"evscfsf", 2, PPCSPE
|PPCVLE
, "efscfsf %0,%1"},
8569 {"evsctui", 2, PPCSPE
|PPCVLE
, "efsctui %0,%1"},
8570 {"evsctsi", 2, PPCSPE
|PPCVLE
, "efsctsi %0,%1"},
8571 {"evsctuf", 2, PPCSPE
|PPCVLE
, "efsctuf %0,%1"},
8572 {"evsctsf", 2, PPCSPE
|PPCVLE
, "efsctsf %0,%1"},
8573 {"evsctuiz", 2, PPCSPE
|PPCVLE
, "efsctuiz %0,%1"},
8574 {"evsctsiz", 2, PPCSPE
|PPCVLE
, "efsctsiz %0,%1"},
8575 {"evststgt", 3, PPCSPE
|PPCVLE
, "efststgt %0,%1,%2"},
8576 {"evststlt", 3, PPCSPE
|PPCVLE
, "efststlt %0,%1,%2"},
8577 {"evststeq", 3, PPCSPE
|PPCVLE
, "efststeq %0,%1,%2"},
8579 /* SPE2 instructions which just are mapped to SPE2 */
8580 {"evdotphsssi", 3, PPCSPE2
, "evdotphssmi %0,%1,%2"},
8581 {"evdotphsssia", 3, PPCSPE2
, "evdotphssmia %0,%1,%2"},
8582 {"evdotpwsssi", 3, PPCSPE2
, "evdotpwssmi %0,%1,%2"},
8583 {"evdotpwsssia", 3, PPCSPE2
, "evdotpwssmia %0,%1,%2"}
8586 const int powerpc_num_macros
=
8587 sizeof (powerpc_macros
) / sizeof (powerpc_macros
[0]);
8589 /* SPE v2 instruction set from SPE2PIM Rev. 2 08/2011 */
8590 const struct powerpc_opcode spe2_opcodes
[] = {
8591 {"evdotpwcssi", VX (4, 128), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
8592 {"evdotpwcsmi", VX (4, 129), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
8593 {"evdotpwcssfr", VX (4, 130), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
8594 {"evdotpwcssf", VX (4, 131), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
8595 {"evdotpwgasmf", VX (4, 136), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
8596 {"evdotpwxgasmf", VX (4, 137), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
8597 {"evdotpwgasmfr", VX (4, 138), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
8598 {"evdotpwxgasmfr", VX (4, 139), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
8599 {"evdotpwgssmf", VX (4, 140), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
8600 {"evdotpwxgssmf", VX (4, 141), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
8601 {"evdotpwgssmfr", VX (4, 142), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
8602 {"evdotpwxgssmfr", VX (4, 143), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
8603 {"evdotpwcssiaaw3", VX (4, 144), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
8604 {"evdotpwcsmiaaw3", VX (4, 145), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
8605 {"evdotpwcssfraaw3", VX (4, 146), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
8606 {"evdotpwcssfaaw3", VX (4, 147), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
8607 {"evdotpwgasmfaa3", VX (4, 152), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
8608 {"evdotpwxgasmfaa3", VX (4, 153), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
8609 {"evdotpwgasmfraa3", VX (4, 154), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
8610 {"evdotpwxgasmfraa3", VX (4, 155), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
8611 {"evdotpwgssmfaa3", VX (4, 156), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
8612 {"evdotpwxgssmfaa3", VX (4, 157), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
8613 {"evdotpwgssmfraa3", VX (4, 158), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
8614 {"evdotpwxgssmfraa3", VX (4, 159), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
8615 {"evdotpwcssia", VX (4, 160), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
8616 {"evdotpwcsmia", VX (4, 161), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
8617 {"evdotpwcssfra", VX (4, 162), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
8618 {"evdotpwcssfa", VX (4, 163), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
8619 {"evdotpwgasmfa", VX (4, 168), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
8620 {"evdotpwxgasmfa", VX (4, 169), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
8621 {"evdotpwgasmfra", VX (4, 170), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
8622 {"evdotpwxgasmfra", VX (4, 171), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
8623 {"evdotpwgssmfa", VX (4, 172), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
8624 {"evdotpwxgssmfa", VX (4, 173), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
8625 {"evdotpwgssmfra", VX (4, 174), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
8626 {"evdotpwxgssmfra", VX (4, 175), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
8627 {"evdotpwcssiaaw", VX (4, 176), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
8628 {"evdotpwcsmiaaw", VX (4, 177), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
8629 {"evdotpwcssfraaw", VX (4, 178), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
8630 {"evdotpwcssfaaw", VX (4, 179), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
8631 {"evdotpwgasmfaa", VX (4, 184), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
8632 {"evdotpwxgasmfaa", VX (4, 185), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
8633 {"evdotpwgasmfraa", VX (4, 186), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
8634 {"evdotpwxgasmfraa", VX (4, 187), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
8635 {"evdotpwgssmfaa", VX (4, 188), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
8636 {"evdotpwxgssmfaa", VX (4, 189), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
8637 {"evdotpwgssmfraa", VX (4, 190), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
8638 {"evdotpwxgssmfraa", VX (4, 191), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
8639 {"evdotphihcssi", VX (4, 256), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
8640 {"evdotplohcssi", VX (4, 257), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
8641 {"evdotphihcssf", VX (4, 258), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
8642 {"evdotplohcssf", VX (4, 259), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
8643 {"evdotphihcsmi", VX (4, 264), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
8644 {"evdotplohcsmi", VX (4, 265), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
8645 {"evdotphihcssfr", VX (4, 266), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
8646 {"evdotplohcssfr", VX (4, 267), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
8647 {"evdotphihcssiaaw3", VX (4, 272), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
8648 {"evdotplohcssiaaw3", VX (4, 273), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
8649 {"evdotphihcssfaaw3", VX (4, 274), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
8650 {"evdotplohcssfaaw3", VX (4, 275), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
8651 {"evdotphihcsmiaaw3", VX (4, 280), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
8652 {"evdotplohcsmiaaw3", VX (4, 281), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
8653 {"evdotphihcssfraaw3", VX (4, 282), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
8654 {"evdotplohcssfraaw3", VX (4, 283), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
8655 {"evdotphihcssia", VX (4, 288), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
8656 {"evdotplohcssia", VX (4, 289), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
8657 {"evdotphihcssfa", VX (4, 290), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
8658 {"evdotplohcssfa", VX (4, 291), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
8659 {"evdotphihcsmia", VX (4, 296), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
8660 {"evdotplohcsmia", VX (4, 297), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
8661 {"evdotphihcssfra", VX (4, 298), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
8662 {"evdotplohcssfra", VX (4, 299), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
8663 {"evdotphihcssiaaw", VX (4, 304), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
8664 {"evdotplohcssiaaw", VX (4, 305), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
8665 {"evdotphihcssfaaw", VX (4, 306), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
8666 {"evdotplohcssfaaw", VX (4, 307), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
8667 {"evdotphihcsmiaaw", VX (4, 312), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
8668 {"evdotplohcsmiaaw", VX (4, 313), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
8669 {"evdotphihcssfraaw", VX (4, 314), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
8670 {"evdotplohcssfraaw", VX (4, 315), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
8671 {"evdotphausi", VX (4, 320), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
8672 {"evdotphassi", VX (4, 321), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
8673 {"evdotphasusi", VX (4, 322), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
8674 {"evdotphassf", VX (4, 323), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
8675 {"evdotphsssf", VX (4, 327), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
8676 {"evdotphaumi", VX (4, 328), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
8677 {"evdotphasmi", VX (4, 329), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
8678 {"evdotphasumi", VX (4, 330), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
8679 {"evdotphassfr", VX (4, 331), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
8680 {"evdotphssmi", VX (4, 333), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
8681 {"evdotphsssfr", VX (4, 335), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
8682 {"evdotphausiaaw3", VX (4, 336), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
8683 {"evdotphassiaaw3", VX (4, 337), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
8684 {"evdotphasusiaaw3", VX (4, 338), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
8685 {"evdotphassfaaw3", VX (4, 339), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
8686 {"evdotphsssiaaw3", VX (4, 341), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
8687 {"evdotphsssfaaw3", VX (4, 343), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
8688 {"evdotphaumiaaw3", VX (4, 344), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
8689 {"evdotphasmiaaw3", VX (4, 345), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
8690 {"evdotphasumiaaw3", VX (4, 346), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
8691 {"evdotphassfraaw3", VX (4, 347), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
8692 {"evdotphssmiaaw3", VX (4, 349), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
8693 {"evdotphsssfraaw3", VX (4, 351), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
8694 {"evdotphausia", VX (4, 352), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
8695 {"evdotphassia", VX (4, 353), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
8696 {"evdotphasusia", VX (4, 354), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
8697 {"evdotphassfa", VX (4, 355), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
8698 {"evdotphsssfa", VX (4, 359), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
8699 {"evdotphaumia", VX (4, 360), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
8700 {"evdotphasmia", VX (4, 361), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
8701 {"evdotphasumia", VX (4, 362), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
8702 {"evdotphassfra", VX (4, 363), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
8703 {"evdotphssmia", VX (4, 365), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
8704 {"evdotphsssfra", VX (4, 367), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
8705 {"evdotphausiaaw", VX (4, 368), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
8706 {"evdotphassiaaw", VX (4, 369), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
8707 {"evdotphasusiaaw", VX (4, 370), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
8708 {"evdotphassfaaw", VX (4, 371), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
8709 {"evdotphsssiaaw", VX (4, 373), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
8710 {"evdotphsssfaaw", VX (4, 375), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
8711 {"evdotphaumiaaw", VX (4, 376), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
8712 {"evdotphasmiaaw", VX (4, 377), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
8713 {"evdotphasumiaaw", VX (4, 378), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
8714 {"evdotphassfraaw", VX (4, 379), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
8715 {"evdotphssmiaaw", VX (4, 381), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
8716 {"evdotphsssfraaw", VX (4, 383), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
8717 {"evdotp4hgaumi", VX (4, 384), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
8718 {"evdotp4hgasmi", VX (4, 385), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
8719 {"evdotp4hgasumi", VX (4, 386), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
8720 {"evdotp4hgasmf", VX (4, 387), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
8721 {"evdotp4hgssmi", VX (4, 388), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
8722 {"evdotp4hgssmf", VX (4, 389), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
8723 {"evdotp4hxgasmi", VX (4, 390), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
8724 {"evdotp4hxgasmf", VX (4, 391), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
8725 {"evdotpbaumi", VX (4, 392), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
8726 {"evdotpbasmi", VX (4, 393), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
8727 {"evdotpbasumi", VX (4, 394), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
8728 {"evdotp4hxgssmi", VX (4, 398), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
8729 {"evdotp4hxgssmf", VX (4, 399), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
8730 {"evdotp4hgaumiaa3", VX (4, 400), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
8731 {"evdotp4hgasmiaa3", VX (4, 401), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
8732 {"evdotp4hgasumiaa3", VX (4, 402), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
8733 {"evdotp4hgasmfaa3", VX (4, 403), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
8734 {"evdotp4hgssmiaa3", VX (4, 404), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
8735 {"evdotp4hgssmfaa3", VX (4, 405), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
8736 {"evdotp4hxgasmiaa3", VX (4, 406), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
8737 {"evdotp4hxgasmfaa3", VX (4, 407), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
8738 {"evdotpbaumiaaw3", VX (4, 408), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
8739 {"evdotpbasmiaaw3", VX (4, 409), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
8740 {"evdotpbasumiaaw3", VX (4, 410), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
8741 {"evdotp4hxgssmiaa3", VX (4, 414), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
8742 {"evdotp4hxgssmfaa3", VX (4, 415), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
8743 {"evdotp4hgaumia", VX (4, 416), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
8744 {"evdotp4hgasmia", VX (4, 417), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
8745 {"evdotp4hgasumia", VX (4, 418), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
8746 {"evdotp4hgasmfa", VX (4, 419), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
8747 {"evdotp4hgssmia", VX (4, 420), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
8748 {"evdotp4hgssmfa", VX (4, 421), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
8749 {"evdotp4hxgasmia", VX (4, 422), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
8750 {"evdotp4hxgasmfa", VX (4, 423), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
8751 {"evdotpbaumia", VX (4, 424), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
8752 {"evdotpbasmia", VX (4, 425), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
8753 {"evdotpbasumia", VX (4, 426), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
8754 {"evdotp4hxgssmia", VX (4, 430), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
8755 {"evdotp4hxgssmfa", VX (4, 431), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
8756 {"evdotp4hgaumiaa", VX (4, 432), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
8757 {"evdotp4hgasmiaa", VX (4, 433), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
8758 {"evdotp4hgasumiaa", VX (4, 434), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
8759 {"evdotp4hgasmfaa", VX (4, 435), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
8760 {"evdotp4hgssmiaa", VX (4, 436), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
8761 {"evdotp4hgssmfaa", VX (4, 437), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
8762 {"evdotp4hxgasmiaa", VX (4, 438), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
8763 {"evdotp4hxgasmfaa", VX (4, 439), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
8764 {"evdotpbaumiaaw", VX (4, 440), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
8765 {"evdotpbasmiaaw", VX (4, 441), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
8766 {"evdotpbasumiaaw", VX (4, 442), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
8767 {"evdotp4hxgssmiaa", VX (4, 446), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
8768 {"evdotp4hxgssmfaa", VX (4, 447), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
8769 {"evdotpwausi", VX (4, 448), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
8770 {"evdotpwassi", VX (4, 449), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
8771 {"evdotpwasusi", VX (4, 450), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
8772 {"evdotpwaumi", VX (4, 456), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
8773 {"evdotpwasmi", VX (4, 457), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
8774 {"evdotpwasumi", VX (4, 458), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
8775 {"evdotpwssmi", VX (4, 461), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
8776 {"evdotpwausiaa3", VX (4, 464), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
8777 {"evdotpwassiaa3", VX (4, 465), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
8778 {"evdotpwasusiaa3", VX (4, 466), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
8779 {"evdotpwsssiaa3", VX (4, 469), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
8780 {"evdotpwaumiaa3", VX (4, 472), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
8781 {"evdotpwasmiaa3", VX (4, 473), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
8782 {"evdotpwasumiaa3", VX (4, 474), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
8783 {"evdotpwssmiaa3", VX (4, 477), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
8784 {"evdotpwausia", VX (4, 480), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
8785 {"evdotpwassia", VX (4, 481), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
8786 {"evdotpwasusia", VX (4, 482), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
8787 {"evdotpwaumia", VX (4, 488), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
8788 {"evdotpwasmia", VX (4, 489), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
8789 {"evdotpwasumia", VX (4, 490), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
8790 {"evdotpwssmia", VX (4, 493), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
8791 {"evdotpwausiaa", VX (4, 496), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
8792 {"evdotpwassiaa", VX (4, 497), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
8793 {"evdotpwasusiaa", VX (4, 498), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
8794 {"evdotpwsssiaa", VX (4, 501), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
8795 {"evdotpwaumiaa", VX (4, 504), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
8796 {"evdotpwasmiaa", VX (4, 505), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
8797 {"evdotpwasumiaa", VX (4, 506), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
8798 {"evdotpwssmiaa", VX (4, 509), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
8799 {"evaddib", VX (4, 515), VX_MASK
, PPCSPE2
, 0, {RD
, RB
, UIMM
}},
8800 {"evaddih", VX (4, 513), VX_MASK
, PPCSPE2
, 0, {RD
, RB
, UIMM
}},
8801 {"evsubifh", VX (4, 517), VX_MASK
, PPCSPE2
, 0, {RD
, UIMM
, RB
}},
8802 {"evsubifb", VX (4, 519), VX_MASK
, PPCSPE2
, 0, {RD
, UIMM
, RB
}},
8803 {"evabsb", VX_RB_CONST(4, 520, 2), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, RA
}},
8804 {"evabsh", VX_RB_CONST(4, 520, 4), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, RA
}},
8805 {"evabsd", VX_RB_CONST(4, 520, 6), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, RA
}},
8806 {"evabss", VX_RB_CONST(4, 520, 8), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, RA
}},
8807 {"evabsbs", VX_RB_CONST(4, 520, 10), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, RA
}},
8808 {"evabshs", VX_RB_CONST(4, 520, 12), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, RA
}},
8809 {"evabsds", VX_RB_CONST(4, 520, 14), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, RA
}},
8810 {"evnegwo", VX_RB_CONST(4, 521, 1), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, RA
}},
8811 {"evnegb", VX_RB_CONST(4, 521, 2), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, RA
}},
8812 {"evnegbo", VX_RB_CONST(4, 521, 3), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, RA
}},
8813 {"evnegh", VX_RB_CONST(4, 521, 4), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, RA
}},
8814 {"evnegho", VX_RB_CONST(4, 521, 5), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, RA
}},
8815 {"evnegd", VX_RB_CONST(4, 521, 6), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, RA
}},
8816 {"evnegs", VX_RB_CONST(4, 521, 8), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, RA
}},
8817 {"evnegwos", VX_RB_CONST(4, 521, 9), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, RA
}},
8818 {"evnegbs", VX_RB_CONST(4, 521, 10), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, RA
}},
8819 {"evnegbos", VX_RB_CONST(4, 521, 11), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, RA
}},
8820 {"evneghs", VX_RB_CONST(4, 521, 12), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, RA
}},
8821 {"evneghos", VX_RB_CONST(4, 521, 13), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, RA
}},
8822 {"evnegds", VX_RB_CONST(4, 521, 14), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, RA
}},
8823 {"evextzb", VX_RB_CONST(4, 522, 1), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, RA
}},
8824 {"evextsbh", VX_RB_CONST(4, 522, 4), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, RA
}},
8825 {"evextsw", VX_RB_CONST(4, 523, 6), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, RA
}},
8826 {"evrndwh", VX_RB_CONST(4, 524, 0), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, RA
}},
8827 {"evrndhb", VX_RB_CONST(4, 524, 4), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, RA
}},
8828 {"evrnddw", VX_RB_CONST(4, 524, 6), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, RA
}},
8829 {"evrndwhus", VX_RB_CONST(4, 524, 8), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, RA
}},
8830 {"evrndwhss", VX_RB_CONST(4, 524, 9), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, RA
}},
8831 {"evrndhbus", VX_RB_CONST(4, 524, 12), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, RA
}},
8832 {"evrndhbss", VX_RB_CONST(4, 524, 13), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, RA
}},
8833 {"evrnddwus", VX_RB_CONST(4, 524, 14), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, RA
}},
8834 {"evrnddwss", VX_RB_CONST(4, 524, 15), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, RA
}},
8835 {"evrndwnh", VX_RB_CONST(4, 524, 16), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, RA
}},
8836 {"evrndhnb", VX_RB_CONST(4, 524, 20), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, RA
}},
8837 {"evrnddnw", VX_RB_CONST(4, 524, 22), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, RA
}},
8838 {"evrndwnhus", VX_RB_CONST(4, 524, 24), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, RA
}},
8839 {"evrndwnhss", VX_RB_CONST(4, 524, 25), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, RA
}},
8840 {"evrndhnbus", VX_RB_CONST(4, 524, 28), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, RA
}},
8841 {"evrndhnbss", VX_RB_CONST(4, 524, 29), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, RA
}},
8842 {"evrnddnwus", VX_RB_CONST(4, 524, 30), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, RA
}},
8843 {"evrnddnwss", VX_RB_CONST(4, 524, 31), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, RA
}},
8844 {"evcntlzh", VX_RB_CONST(4, 525, 4), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, RA
}},
8845 {"evcntlsh", VX_RB_CONST(4, 526, 4), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, RA
}},
8846 {"evpopcntb", VX_RB_CONST(4, 526, 26), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, RA
}},
8847 {"circinc", VX (4, 528), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
8848 {"evunpkhibui", VX_RB_CONST(4, 540, 0), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, RA
}},
8849 {"evunpkhibsi", VX_RB_CONST(4, 540, 1), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, RA
}},
8850 {"evunpkhihui", VX_RB_CONST(4, 540, 2), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, RA
}},
8851 {"evunpkhihsi", VX_RB_CONST(4, 540, 3), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, RA
}},
8852 {"evunpklobui", VX_RB_CONST(4, 540, 4), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, RA
}},
8853 {"evunpklobsi", VX_RB_CONST(4, 540, 5), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, RA
}},
8854 {"evunpklohui", VX_RB_CONST(4, 540, 6), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, RA
}},
8855 {"evunpklohsi", VX_RB_CONST(4, 540, 7), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, RA
}},
8856 {"evunpklohf", VX_RB_CONST(4, 540, 8), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, RA
}},
8857 {"evunpkhihf", VX_RB_CONST(4, 540, 9), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, RA
}},
8858 {"evunpklowgsf", VX_RB_CONST(4, 540, 12), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, RA
}},
8859 {"evunpkhiwgsf", VX_RB_CONST(4, 540, 13), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, RA
}},
8860 {"evsatsduw", VX_RB_CONST(4, 540, 16), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, RA
}},
8861 {"evsatsdsw", VX_RB_CONST(4, 540, 17), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, RA
}},
8862 {"evsatshub", VX_RB_CONST(4, 540, 18), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, RA
}},
8863 {"evsatshsb", VX_RB_CONST(4, 540, 19), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, RA
}},
8864 {"evsatuwuh", VX_RB_CONST(4, 540, 20), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, RA
}},
8865 {"evsatswsh", VX_RB_CONST(4, 540, 21), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, RA
}},
8866 {"evsatswuh", VX_RB_CONST(4, 540, 22), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, RA
}},
8867 {"evsatuhub", VX_RB_CONST(4, 540, 23), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, RA
}},
8868 {"evsatuduw", VX_RB_CONST(4, 540, 24), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, RA
}},
8869 {"evsatuwsw", VX_RB_CONST(4, 540, 25), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, RA
}},
8870 {"evsatshuh", VX_RB_CONST(4, 540, 26), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, RA
}},
8871 {"evsatuhsh", VX_RB_CONST(4, 540, 27), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, RA
}},
8872 {"evsatswuw", VX_RB_CONST(4, 540, 28), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, RA
}},
8873 {"evsatswgsdf", VX_RB_CONST(4, 540, 29), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, RA
}},
8874 {"evsatsbub", VX_RB_CONST(4, 540, 30), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, RA
}},
8875 {"evsatubsb", VX_RB_CONST(4, 540, 31), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, RA
}},
8876 {"evmaxhpuw", VX_RB_CONST(4, 541, 0), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, RA
}},
8877 {"evmaxhpsw", VX_RB_CONST(4, 541, 1), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, RA
}},
8878 {"evmaxbpuh", VX_RB_CONST(4, 541, 4), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, RA
}},
8879 {"evmaxbpsh", VX_RB_CONST(4, 541, 5), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, RA
}},
8880 {"evmaxwpud", VX_RB_CONST(4, 541, 6), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, RA
}},
8881 {"evmaxwpsd", VX_RB_CONST(4, 541, 7), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, RA
}},
8882 {"evminhpuw", VX_RB_CONST(4, 541, 8), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, RA
}},
8883 {"evminhpsw", VX_RB_CONST(4, 541, 9), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, RA
}},
8884 {"evminbpuh", VX_RB_CONST(4, 541, 12), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, RA
}},
8885 {"evminbpsh", VX_RB_CONST(4, 541, 13), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, RA
}},
8886 {"evminwpud", VX_RB_CONST(4, 541, 14), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, RA
}},
8887 {"evminwpsd", VX_RB_CONST(4, 541, 15), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, RA
}},
8888 {"evmaxmagws", VX (4, 543), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
8889 {"evsl", VX (4, 549), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
8890 {"evsli", VX (4, 551), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, EVUIMM
}},
8891 {"evsplatie", VX_RB_CONST (4, 553, 1), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, SIMM
}},
8892 {"evsplatib", VX_RB_CONST (4, 553, 2), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, SIMM
}},
8893 {"evsplatibe", VX_RB_CONST (4, 553, 3), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, SIMM
}},
8894 {"evsplatih", VX_RB_CONST (4, 553, 4), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, SIMM
}},
8895 {"evsplatihe", VX_RB_CONST (4, 553, 5), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, SIMM
}},
8896 {"evsplatid", VX_RB_CONST (4, 553, 6), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, SIMM
}},
8897 {"evsplatia", VX_RB_CONST (4, 553, 16), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, SIMM
}},
8898 {"evsplatiea", VX_RB_CONST (4, 553, 17), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, SIMM
}},
8899 {"evsplatiba", VX_RB_CONST (4, 553, 18), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, SIMM
}},
8900 {"evsplatibea", VX_RB_CONST (4, 553, 19), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, SIMM
}},
8901 {"evsplatiha", VX_RB_CONST (4, 553, 20), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, SIMM
}},
8902 {"evsplatihea", VX_RB_CONST (4, 553, 21), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, SIMM
}},
8903 {"evsplatida", VX_RB_CONST (4, 553, 22), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, SIMM
}},
8904 {"evsplatfio", VX_RB_CONST (4, 555, 1), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, SIMM
}},
8905 {"evsplatfib", VX_RB_CONST (4, 555, 2), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, SIMM
}},
8906 {"evsplatfibo", VX_RB_CONST (4, 555, 3), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, SIMM
}},
8907 {"evsplatfih", VX_RB_CONST (4, 555, 4), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, SIMM
}},
8908 {"evsplatfiho", VX_RB_CONST (4, 555, 5), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, SIMM
}},
8909 {"evsplatfid", VX_RB_CONST (4, 555, 6), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, SIMM
}},
8910 {"evsplatfia", VX_RB_CONST (4, 555, 16), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, SIMM
}},
8911 {"evsplatfioa", VX_RB_CONST (4, 555, 17), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, SIMM
}},
8912 {"evsplatfiba", VX_RB_CONST (4, 555, 18), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, SIMM
}},
8913 {"evsplatfiboa", VX_RB_CONST (4, 555, 19), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, SIMM
}},
8914 {"evsplatfiha", VX_RB_CONST (4, 555, 20), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, SIMM
}},
8915 {"evsplatfihoa", VX_RB_CONST (4, 555, 21), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, SIMM
}},
8916 {"evsplatfida", VX_RB_CONST (4, 555, 22), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, SIMM
}},
8917 {"evcmpgtdu", VX_SPE_CRFD (4, 560, 1), VX_SPE_CRFD_MASK
, PPCSPE2
, 0, {CRFD
, RA
, RB
}},
8918 {"evcmpgtds", VX_SPE_CRFD (4, 561, 1), VX_SPE_CRFD_MASK
, PPCSPE2
, 0, {CRFD
, RA
, RB
}},
8919 {"evcmpltdu", VX_SPE_CRFD (4, 562, 1), VX_SPE_CRFD_MASK
, PPCSPE2
, 0, {CRFD
, RA
, RB
}},
8920 {"evcmpltds", VX_SPE_CRFD (4, 563, 1), VX_SPE_CRFD_MASK
, PPCSPE2
, 0, {CRFD
, RA
, RB
}},
8921 {"evcmpeqd", VX_SPE_CRFD (4, 564, 1), VX_SPE_CRFD_MASK
, PPCSPE2
, 0, {CRFD
, RA
, RB
}},
8922 {"evswapbhilo", VX (4, 568), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
8923 {"evswapblohi", VX (4, 569), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
8924 {"evswaphhilo", VX (4, 570), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
8925 {"evswaphlohi", VX (4, 571), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
8926 {"evswaphe", VX (4, 572), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
8927 {"evswaphhi", VX (4, 573), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
8928 {"evswaphlo", VX (4, 574), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
8929 {"evswapho", VX (4, 575), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
8930 {"evinsb", VX (4, 584), VX_MASK_DDD
, PPCSPE2
, 0, {RD
, RA
, DDD
, BBB
}},
8931 {"evxtrb", VX (4, 586), VX_MASK_DDD
, PPCSPE2
, 0, {RD
, RA
, DDD
, BBB
}},
8932 {"evsplath", VX_SPE2_HH (4, 588, 0, 0), VX_SPE2_HH_MASK
, PPCSPE2
, 0, {RD
, RA
, HH
}},
8933 {"evsplatb", VX_SPE2_SPLATB (4, 588, 2), VX_SPE2_SPLATB_MASK
, PPCSPE2
, 0, {RD
, RA
, BBB
}},
8934 {"evinsh", VX_SPE2_DDHH (4, 589, 0), VX_SPE2_DDHH_MASK
, PPCSPE2
, 0, {RD
, RA
, DD
, HH
}},
8935 {"evclrbe", VX_SPE2_CLR (4, 590, 0), VX_SPE2_CLR_MASK
, PPCSPE2
, 0, {RD
, RA
, MMMM
}},
8936 {"evclrbo", VX_SPE2_CLR (4, 590, 1), VX_SPE2_CLR_MASK
, PPCSPE2
, 0, {RD
, RA
, MMMM
}},
8937 {"evclrh", VX_SPE2_CLR (4, 591, 1), VX_SPE2_CLR_MASK
, PPCSPE2
, 0, {RD
, RA
, MMMM
}},
8938 {"evxtrh", VX_SPE2_DDHH (4, 591, 0), VX_SPE2_DDHH_MASK
, PPCSPE2
, 0, {RD
, RA
, DD
, HH
}},
8939 {"evselbitm0", VX (4, 592), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
8940 {"evselbitm1", VX (4, 593), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
8941 {"evselbit", VX (4, 594), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
8942 {"evperm", VX (4, 596), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
8943 {"evperm2", VX (4, 597), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
8944 {"evperm3", VX (4, 598), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
8945 {"evxtrd", VX (4, 600), VX_OFF_SPE2_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
, VX_OFF_SPE2
}},
8946 {"evsrbu", VX (4, 608), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
8947 {"evsrbs", VX (4, 609), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
8948 {"evsrbiu", VX (4, 610), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, EVUIMM_LT8
}},
8949 {"evsrbis", VX (4, 611), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, EVUIMM_LT8
}},
8950 {"evslb", VX (4, 612), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
8951 {"evrlb", VX (4, 613), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
8952 {"evslbi", VX (4, 614), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, EVUIMM_LT8
}},
8953 {"evrlbi", VX (4, 615), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, EVUIMM_LT8
}},
8954 {"evsrhu", VX (4, 616), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
8955 {"evsrhs", VX (4, 617), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
8956 {"evsrhiu", VX (4, 618), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, EVUIMM_LT16
}},
8957 {"evsrhis", VX (4, 619), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, EVUIMM_LT16
}},
8958 {"evslh", VX (4, 620), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
8959 {"evrlh", VX (4, 621), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
8960 {"evslhi", VX (4, 622), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, EVUIMM_LT16
}},
8961 {"evrlhi", VX (4, 623), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, EVUIMM_LT16
}},
8962 {"evsru", VX (4, 624), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
8963 {"evsrs", VX (4, 625), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
8964 {"evsriu", VX (4, 626), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, EVUIMM
}},
8965 {"evsris", VX (4, 627), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, EVUIMM
}},
8966 {"evlvsl", VX (4, 628), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
8967 {"evlvsr", VX (4, 629), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
8968 {"evsroiu", VX_SPE2_OCTET (4, 631, 0), VX_SPE2_OCTET_MASK
, PPCSPE2
, 0, {RD
, RA
, NNN
}},
8969 {"evsrois", VX_SPE2_OCTET (4, 631, 1), VX_SPE2_OCTET_MASK
, PPCSPE2
, 0, {RD
, RA
, NNN
}},
8970 {"evsloi", VX_SPE2_OCTET (4, 631, 2), VX_SPE2_OCTET_MASK
, PPCSPE2
, 0, {RD
, RA
, NNN
}},
8971 {"evldbx", VX (4, 774), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
8972 {"evldb", VX (4, 775), VX_MASK
, PPCSPE2
, 0, {RD
, EVUIMM_8
, RA
}},
8973 {"evlhhsplathx", VX (4, 778), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
8974 {"evlhhsplath", VX (4, 779), VX_MASK
, PPCSPE2
, 0, {RD
, EVUIMM_2
, RA
}},
8975 {"evlwbsplatwx", VX (4, 786), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
8976 {"evlwbsplatw", VX (4, 787), VX_MASK
, PPCSPE2
, 0, {RD
, EVUIMM_4
, RA
}},
8977 {"evlwhsplatwx", VX (4, 794), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
8978 {"evlwhsplatw", VX (4, 795), VX_MASK
, PPCSPE2
, 0, {RD
, EVUIMM_4
, RA
}},
8979 {"evlbbsplatbx", VX (4, 798), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
8980 {"evlbbsplatb", VX (4, 799), VX_MASK
, PPCSPE2
, 0, {RD
, EVUIMM_1
, RA
}},
8981 {"evstdbx", VX (4, 806), VX_MASK
, PPCSPE2
, 0, {RS
, RA
, RB
}},
8982 {"evstdb", VX (4, 807), VX_MASK
, PPCSPE2
, 0, {RS
, EVUIMM_8
, RA
}},
8983 {"evlwbex", VX (4, 810), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
8984 {"evlwbe", VX (4, 811), VX_MASK
, PPCSPE2
, 0, {RD
, EVUIMM_4
, RA
}},
8985 {"evlwboux", VX (4, 812), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
8986 {"evlwbou", VX (4, 813), VX_MASK
, PPCSPE2
, 0, {RD
, EVUIMM_4
, RA
}},
8987 {"evlwbosx", VX (4, 814), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
8988 {"evlwbos", VX (4, 815), VX_MASK
, PPCSPE2
, 0, {RD
, EVUIMM_4
, RA
}},
8989 {"evstwbex", VX (4, 818), VX_MASK
, PPCSPE2
, 0, {RS
, RA
, RB
}},
8990 {"evstwbe", VX (4, 819), VX_MASK
, PPCSPE2
, 0, {RS
, EVUIMM_4
, RA
}},
8991 {"evstwbox", VX (4, 822), VX_MASK
, PPCSPE2
, 0, {RS
, RA
, RB
}},
8992 {"evstwbo", VX (4, 823), VX_MASK
, PPCSPE2
, 0, {RS
, EVUIMM_4
, RA
}},
8993 {"evstwbx", VX (4, 826), VX_MASK
, PPCSPE2
, 0, {RS
, RA
, RB
}},
8994 {"evstwb", VX (4, 827), VX_MASK
, PPCSPE2
, 0, {RS
, EVUIMM_4
, RA
}},
8995 {"evsthbx", VX (4, 830), VX_MASK
, PPCSPE2
, 0, {RS
, RA
, RB
}},
8996 {"evsthb", VX (4, 831), VX_MASK
, PPCSPE2
, 0, {RS
, EVUIMM_2
, RA
}},
8997 {"evlddmx", VX (4, 832), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
8998 {"evlddu", VX (4, 833), VX_MASK
, PPCSPE2
, 0, {RD
, EVUIMM_8_EX0
, RA
}},
8999 {"evldwmx", VX (4, 834), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9000 {"evldwu", VX (4, 835), VX_MASK
, PPCSPE2
, 0, {RD
, EVUIMM_8_EX0
, RA
}},
9001 {"evldhmx", VX (4, 836), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9002 {"evldhu", VX (4, 837), VX_MASK
, PPCSPE2
, 0, {RD
, EVUIMM_8_EX0
, RA
}},
9003 {"evldbmx", VX (4, 838), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9004 {"evldbu", VX (4, 839), VX_MASK
, PPCSPE2
, 0, {RD
, EVUIMM_8_EX0
, RA
}},
9005 {"evlhhesplatmx", VX (4, 840), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9006 {"evlhhesplatu", VX (4, 841), VX_MASK
, PPCSPE2
, 0, {RD
, EVUIMM_2_EX0
, RA
}},
9007 {"evlhhsplathmx", VX (4, 842), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9008 {"evlhhsplathu", VX (4, 843), VX_MASK
, PPCSPE2
, 0, {RD
, EVUIMM_2_EX0
, RA
}},
9009 {"evlhhousplatmx", VX (4, 844), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9010 {"evlhhousplatu", VX (4, 845), VX_MASK
, PPCSPE2
, 0, {RD
, EVUIMM_2_EX0
, RA
}},
9011 {"evlhhossplatmx", VX (4, 846), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9012 {"evlhhossplatu", VX (4, 847), VX_MASK
, PPCSPE2
, 0, {RD
, EVUIMM_2_EX0
, RA
}},
9013 {"evlwhemx", VX (4, 848), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9014 {"evlwheu", VX (4, 849), VX_MASK
, PPCSPE2
, 0, {RD
, EVUIMM_4_EX0
, RA
}},
9015 {"evlwbsplatwmx", VX (4, 850), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9016 {"evlwbsplatwu", VX (4, 851), VX_MASK
, PPCSPE2
, 0, {RD
, EVUIMM_4_EX0
, RA
}},
9017 {"evlwhoumx", VX (4, 852), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9018 {"evlwhouu", VX (4, 853), VX_MASK
, PPCSPE2
, 0, {RD
, EVUIMM_4_EX0
, RA
}},
9019 {"evlwhosmx", VX (4, 854), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9020 {"evlwhosu", VX (4, 855), VX_MASK
, PPCSPE2
, 0, {RD
, EVUIMM_4_EX0
, RA
}},
9021 {"evlwwsplatmx", VX (4, 856), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9022 {"evlwwsplatu", VX (4, 857), VX_MASK
, PPCSPE2
, 0, {RD
, EVUIMM_4_EX0
, RA
}},
9023 {"evlwhsplatwmx", VX (4, 858), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9024 {"evlwhsplatwu", VX (4, 859), VX_MASK
, PPCSPE2
, 0, {RD
, EVUIMM_4_EX0
, RA
}},
9025 {"evlwhsplatmx", VX (4, 860), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9026 {"evlwhsplatu", VX (4, 861), VX_MASK
, PPCSPE2
, 0, {RD
, EVUIMM_4_EX0
, RA
}},
9027 {"evlbbsplatbmx", VX (4, 862), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9028 {"evlbbsplatbu", VX (4, 863), VX_MASK
, PPCSPE2
, 0, {RD
, EVUIMM_1_EX0
, RA
}},
9029 {"evstddmx", VX (4, 864), VX_MASK
, PPCSPE2
, 0, {RS
, RA
, RB
}},
9030 {"evstddu", VX (4, 865), VX_MASK
, PPCSPE2
, 0, {RS
, EVUIMM_8_EX0
, RA
}},
9031 {"evstdwmx", VX (4, 866), VX_MASK
, PPCSPE2
, 0, {RS
, RA
, RB
}},
9032 {"evstdwu", VX (4, 867), VX_MASK
, PPCSPE2
, 0, {RS
, EVUIMM_8_EX0
, RA
}},
9033 {"evstdhmx", VX (4, 868), VX_MASK
, PPCSPE2
, 0, {RS
, RA
, RB
}},
9034 {"evstdhu", VX (4, 869), VX_MASK
, PPCSPE2
, 0, {RS
, EVUIMM_8_EX0
, RA
}},
9035 {"evstdbmx", VX (4, 870), VX_MASK
, PPCSPE2
, 0, {RS
, RA
, RB
}},
9036 {"evstdbu", VX (4, 871), VX_MASK
, PPCSPE2
, 0, {RS
, EVUIMM_8_EX0
, RA
}},
9037 {"evlwbemx", VX (4, 874), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9038 {"evlwbeu", VX (4, 875), VX_MASK
, PPCSPE2
, 0, {RD
, EVUIMM_4_EX0
, RA
}},
9039 {"evlwboumx", VX (4, 876), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9040 {"evlwbouu", VX (4, 877), VX_MASK
, PPCSPE2
, 0, {RD
, EVUIMM_4_EX0
, RA
}},
9041 {"evlwbosmx", VX (4, 878), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9042 {"evlwbosu", VX (4, 879), VX_MASK
, PPCSPE2
, 0, {RD
, EVUIMM_4_EX0
, RA
}},
9043 {"evstwhemx", VX (4, 880), VX_MASK
, PPCSPE2
, 0, {RS
, RA
, RB
}},
9044 {"evstwheu", VX (4, 881), VX_MASK
, PPCSPE2
, 0, {RS
, EVUIMM_4_EX0
, RA
}},
9045 {"evstwbemx", VX (4, 882), VX_MASK
, PPCSPE2
, 0, {RS
, RA
, RB
}},
9046 {"evstwbeu", VX (4, 883), VX_MASK
, PPCSPE2
, 0, {RS
, EVUIMM_4_EX0
, RA
}},
9047 {"evstwhomx", VX (4, 884), VX_MASK
, PPCSPE2
, 0, {RS
, RA
, RB
}},
9048 {"evstwhou", VX (4, 885), VX_MASK
, PPCSPE2
, 0, {RS
, EVUIMM_4_EX0
, RA
}},
9049 {"evstwbomx", VX (4, 886), VX_MASK
, PPCSPE2
, 0, {RS
, RA
, RB
}},
9050 {"evstwbou", VX (4, 887), VX_MASK
, PPCSPE2
, 0, {RS
, EVUIMM_4_EX0
, RA
}},
9051 {"evstwwemx", VX (4, 888), VX_MASK
, PPCSPE2
, 0, {RS
, RA
, RB
}},
9052 {"evstwweu", VX (4, 889), VX_MASK
, PPCSPE2
, 0, {RS
, EVUIMM_4_EX0
, RA
}},
9053 {"evstwbmx", VX (4, 890), VX_MASK
, PPCSPE2
, 0, {RS
, RA
, RB
}},
9054 {"evstwbu", VX (4, 891), VX_MASK
, PPCSPE2
, 0, {RS
, EVUIMM_4_EX0
, RA
}},
9055 {"evstwwomx", VX (4, 892), VX_MASK
, PPCSPE2
, 0, {RS
, RA
, RB
}},
9056 {"evstwwou", VX (4, 893), VX_MASK
, PPCSPE2
, 0, {RS
, EVUIMM_4_EX0
, RA
}},
9057 {"evsthbmx", VX (4, 894), VX_MASK
, PPCSPE2
, 0, {RS
, RA
, RB
}},
9058 {"evsthbu", VX (4, 895), VX_MASK
, PPCSPE2
, 0, {RS
, EVUIMM_2_EX0
, RA
}},
9059 {"evmhusi", VX (4, 1024), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9060 {"evmhssi", VX (4, 1025), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9061 {"evmhsusi", VX (4, 1026), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9062 {"evmhssf", VX (4, 1028), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9063 {"evmhumi", VX (4, 1029), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9064 {"evmhssfr", VX (4, 1030), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9065 {"evmhesumi", VX (4, 1034), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9066 {"evmhosumi", VX (4, 1038), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9067 {"evmbeumi", VX (4, 1048), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9068 {"evmbesmi", VX (4, 1049), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9069 {"evmbesumi", VX (4, 1050), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9070 {"evmboumi", VX (4, 1052), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9071 {"evmbosmi", VX (4, 1053), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9072 {"evmbosumi", VX (4, 1054), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9073 {"evmhesumia", VX (4, 1066), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9074 {"evmhosumia", VX (4, 1070), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9075 {"evmbeumia", VX (4, 1080), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9076 {"evmbesmia", VX (4, 1081), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9077 {"evmbesumia", VX (4, 1082), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9078 {"evmboumia", VX (4, 1084), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9079 {"evmbosmia", VX (4, 1085), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9080 {"evmbosumia", VX (4, 1086), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9081 {"evmwusiw", VX (4, 1088), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9082 {"evmwssiw", VX (4, 1089), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9083 {"evmwhssfr", VX (4, 1094), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9084 {"evmwehgsmfr", VX (4, 1110), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9085 {"evmwehgsmf", VX (4, 1111), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9086 {"evmwohgsmfr", VX (4, 1118), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9087 {"evmwohgsmf", VX (4, 1119), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9088 {"evmwhssfra", VX (4, 1126), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9089 {"evmwehgsmfra", VX (4, 1142), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9090 {"evmwehgsmfa", VX (4, 1143), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9091 {"evmwohgsmfra", VX (4, 1150), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9092 {"evmwohgsmfa", VX (4, 1151), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9093 {"evaddusiaa", VX_RB_CONST(4, 1152, 0), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, RA
}},
9094 {"evaddssiaa", VX_RB_CONST(4, 1153, 0), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, RA
}},
9095 {"evsubfusiaa", VX_RB_CONST(4, 1154, 0), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, RA
}},
9096 {"evsubfssiaa", VX_RB_CONST(4, 1155, 0), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, RA
}},
9097 {"evaddsmiaa", VX_RB_CONST(4, 1156, 0), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, RA
}},
9098 {"evsubfsmiaa", VX_RB_CONST(4, 1158, 0), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, RA
}},
9099 {"evaddh", VX (4, 1160), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9100 {"evaddhss", VX (4, 1161), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9101 {"evsubfh", VX (4, 1162), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9102 {"evsubfhss", VX (4, 1163), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9103 {"evaddhx", VX (4, 1164), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9104 {"evaddhxss", VX (4, 1165), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9105 {"evsubfhx", VX (4, 1166), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9106 {"evsubfhxss", VX (4, 1167), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9107 {"evaddd", VX (4, 1168), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9108 {"evadddss", VX (4, 1169), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9109 {"evsubfd", VX (4, 1170), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9110 {"evsubfdss", VX (4, 1171), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9111 {"evaddb", VX (4, 1172), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9112 {"evaddbss", VX (4, 1173), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9113 {"evsubfb", VX (4, 1174), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9114 {"evsubfbss", VX (4, 1175), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9115 {"evaddsubfh", VX (4, 1176), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9116 {"evaddsubfhss", VX (4, 1177), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9117 {"evsubfaddh", VX (4, 1178), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9118 {"evsubfaddhss", VX (4, 1179), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9119 {"evaddsubfhx", VX (4, 1180), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9120 {"evaddsubfhxss", VX (4, 1181), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9121 {"evsubfaddhx", VX (4, 1182), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9122 {"evsubfaddhxss", VX (4, 1183), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9123 {"evadddus", VX (4, 1184), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9124 {"evaddbus", VX (4, 1185), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9125 {"evsubfdus", VX (4, 1186), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9126 {"evsubfbus", VX (4, 1187), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9127 {"evaddwus", VX (4, 1188), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9128 {"evaddwxus", VX (4, 1189), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9129 {"evsubfwus", VX (4, 1190), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9130 {"evsubfwxus", VX (4, 1191), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9131 {"evadd2subf2h", VX (4, 1192), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9132 {"evadd2subf2hss", VX (4, 1193), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9133 {"evsubf2add2h", VX (4, 1194), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9134 {"evsubf2add2hss", VX (4, 1195), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9135 {"evaddhus", VX (4, 1196), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9136 {"evaddhxus", VX (4, 1197), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9137 {"evsubfhus", VX (4, 1198), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9138 {"evsubfhxus", VX (4, 1199), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9139 {"evaddwss", VX (4, 1201), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9140 {"evsubfwss", VX (4, 1203), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9141 {"evaddwx", VX (4, 1204), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9142 {"evaddwxss", VX (4, 1205), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9143 {"evsubfwx", VX (4, 1206), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9144 {"evsubfwxss", VX (4, 1207), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9145 {"evaddsubfw", VX (4, 1208), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9146 {"evaddsubfwss", VX (4, 1209), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9147 {"evsubfaddw", VX (4, 1210), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9148 {"evsubfaddwss", VX (4, 1211), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9149 {"evaddsubfwx", VX (4, 1212), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9150 {"evaddsubfwxss", VX (4, 1213), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9151 {"evsubfaddwx", VX (4, 1214), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9152 {"evsubfaddwxss", VX (4, 1215), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9153 {"evmar", VX_SPE2_EVMAR (4, 1220), VX_SPE2_EVMAR_MASK
, PPCSPE2
, 0, {RD
}},
9154 {"evsumwu", VX_RB_CONST(4, 1221, 0), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, RA
}},
9155 {"evsumws", VX_RB_CONST(4, 1221, 1), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, RA
}},
9156 {"evsum4bu", VX_RB_CONST(4, 1221, 2), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, RA
}},
9157 {"evsum4bs", VX_RB_CONST(4, 1221, 3), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, RA
}},
9158 {"evsum2hu", VX_RB_CONST(4, 1221, 4), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, RA
}},
9159 {"evsum2hs", VX_RB_CONST(4, 1221, 5), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, RA
}},
9160 {"evdiff2his", VX_RB_CONST(4, 1221, 6), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, RA
}},
9161 {"evsum2his", VX_RB_CONST(4, 1221, 7), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, RA
}},
9162 {"evsumwua", VX_RB_CONST(4, 1221, 16), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, RA
}},
9163 {"evsumwsa", VX_RB_CONST(4, 1221, 17), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, RA
}},
9164 {"evsum4bua", VX_RB_CONST(4, 1221, 18), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, RA
}},
9165 {"evsum4bsa", VX_RB_CONST(4, 1221, 19), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, RA
}},
9166 {"evsum2hua", VX_RB_CONST(4, 1221, 20), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, RA
}},
9167 {"evsum2hsa", VX_RB_CONST(4, 1221, 21), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, RA
}},
9168 {"evdiff2hisa", VX_RB_CONST(4, 1221, 22), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, RA
}},
9169 {"evsum2hisa", VX_RB_CONST(4, 1221, 23), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, RA
}},
9170 {"evsumwuaa", VX_RB_CONST(4, 1221, 24), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, RA
}},
9171 {"evsumwsaa", VX_RB_CONST(4, 1221, 25), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, RA
}},
9172 {"evsum4buaaw", VX_RB_CONST(4, 1221, 26), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, RA
}},
9173 {"evsum4bsaaw", VX_RB_CONST(4, 1221, 27), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, RA
}},
9174 {"evsum2huaaw", VX_RB_CONST(4, 1221, 28), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, RA
}},
9175 {"evsum2hsaaw", VX_RB_CONST(4, 1221, 29), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, RA
}},
9176 {"evdiff2hisaaw", VX_RB_CONST(4, 1221, 30), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, RA
}},
9177 {"evsum2hisaaw", VX_RB_CONST(4, 1221, 31), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, RA
}},
9178 {"evdivwsf", VX (4, 1228), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9179 {"evdivwuf", VX (4, 1229), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9180 {"evdivs", VX (4, 1230), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9181 {"evdivu", VX (4, 1231), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9182 {"evaddwegsi", VX (4, 1232), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9183 {"evaddwegsf", VX (4, 1233), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9184 {"evsubfwegsi", VX (4, 1234), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9185 {"evsubfwegsf", VX (4, 1235), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9186 {"evaddwogsi", VX (4, 1236), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9187 {"evaddwogsf", VX (4, 1237), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9188 {"evsubfwogsi", VX (4, 1238), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9189 {"evsubfwogsf", VX (4, 1239), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9190 {"evaddhhiuw", VX (4, 1240), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9191 {"evaddhhisw", VX (4, 1241), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9192 {"evsubfhhiuw", VX (4, 1242), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9193 {"evsubfhhisw", VX (4, 1243), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9194 {"evaddhlouw", VX (4, 1244), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9195 {"evaddhlosw", VX (4, 1245), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9196 {"evsubfhlouw", VX (4, 1246), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9197 {"evsubfhlosw", VX (4, 1247), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9198 {"evmhesusiaaw", VX (4, 1282), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9199 {"evmhosusiaaw", VX (4, 1286), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9200 {"evmhesumiaaw", VX (4, 1290), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9201 {"evmhosumiaaw", VX (4, 1294), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9202 {"evmbeusiaah", VX (4, 1296), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9203 {"evmbessiaah", VX (4, 1297), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9204 {"evmbesusiaah", VX (4, 1298), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9205 {"evmbousiaah", VX (4, 1300), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9206 {"evmbossiaah", VX (4, 1301), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9207 {"evmbosusiaah", VX (4, 1302), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9208 {"evmbeumiaah", VX (4, 1304), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9209 {"evmbesmiaah", VX (4, 1305), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9210 {"evmbesumiaah", VX (4, 1306), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9211 {"evmboumiaah", VX (4, 1308), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9212 {"evmbosmiaah", VX (4, 1309), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9213 {"evmbosumiaah", VX (4, 1310), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9214 {"evmwlusiaaw3", VX (4, 1346), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9215 {"evmwlssiaaw3", VX (4, 1347), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9216 {"evmwhssfraaw3", VX (4, 1348), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9217 {"evmwhssfaaw3", VX (4, 1349), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9218 {"evmwhssfraaw", VX (4, 1350), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9219 {"evmwhssfaaw", VX (4, 1351), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9220 {"evmwlumiaaw3", VX (4, 1354), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9221 {"evmwlsmiaaw3", VX (4, 1355), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9222 {"evmwusiaa", VX (4, 1360), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9223 {"evmwssiaa", VX (4, 1361), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9224 {"evmwehgsmfraa", VX (4, 1366), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9225 {"evmwehgsmfaa", VX (4, 1367), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9226 {"evmwohgsmfraa", VX (4, 1374), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9227 {"evmwohgsmfaa", VX (4, 1375), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9228 {"evmhesusianw", VX (4, 1410), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9229 {"evmhosusianw", VX (4, 1414), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9230 {"evmhesumianw", VX (4, 1418), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9231 {"evmhosumianw", VX (4, 1422), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9232 {"evmbeusianh", VX (4, 1424), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9233 {"evmbessianh", VX (4, 1425), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9234 {"evmbesusianh", VX (4, 1426), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9235 {"evmbousianh", VX (4, 1428), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9236 {"evmbossianh", VX (4, 1429), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9237 {"evmbosusianh", VX (4, 1430), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9238 {"evmbeumianh", VX (4, 1432), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9239 {"evmbesmianh", VX (4, 1433), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9240 {"evmbesumianh", VX (4, 1434), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9241 {"evmboumianh", VX (4, 1436), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9242 {"evmbosmianh", VX (4, 1437), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9243 {"evmbosumianh", VX (4, 1438), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9244 {"evmwlusianw3", VX (4, 1474), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9245 {"evmwlssianw3", VX (4, 1475), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9246 {"evmwhssfranw3", VX (4, 1476), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9247 {"evmwhssfanw3", VX (4, 1477), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9248 {"evmwhssfranw", VX (4, 1478), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9249 {"evmwhssfanw", VX (4, 1479), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9250 {"evmwlumianw3", VX (4, 1482), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9251 {"evmwlsmianw3", VX (4, 1483), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9252 {"evmwusian", VX (4, 1488), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9253 {"evmwssian", VX (4, 1489), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9254 {"evmwehgsmfran", VX (4, 1494), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9255 {"evmwehgsmfan", VX (4, 1495), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9256 {"evmwohgsmfran", VX (4, 1502), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9257 {"evmwohgsmfan", VX (4, 1503), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9258 {"evseteqb", VX (4, 1536), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9259 {"evseteqb.", VX (4, 1537), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9260 {"evseteqh", VX (4, 1538), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9261 {"evseteqh.", VX (4, 1539), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9262 {"evseteqw", VX (4, 1540), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9263 {"evseteqw.", VX (4, 1541), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9264 {"evsetgthu", VX (4, 1544), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9265 {"evsetgthu.", VX (4, 1545), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9266 {"evsetgths", VX (4, 1546), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9267 {"evsetgths.", VX (4, 1547), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9268 {"evsetgtwu", VX (4, 1548), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9269 {"evsetgtwu.", VX (4, 1549), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9270 {"evsetgtws", VX (4, 1550), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9271 {"evsetgtws.", VX (4, 1551), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9272 {"evsetgtbu", VX (4, 1552), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9273 {"evsetgtbu.", VX (4, 1553), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9274 {"evsetgtbs", VX (4, 1554), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9275 {"evsetgtbs.", VX (4, 1555), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9276 {"evsetltbu", VX (4, 1556), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9277 {"evsetltbu.", VX (4, 1557), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9278 {"evsetltbs", VX (4, 1558), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9279 {"evsetltbs.", VX (4, 1559), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9280 {"evsetlthu", VX (4, 1560), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9281 {"evsetlthu.", VX (4, 1561), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9282 {"evsetlths", VX (4, 1562), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9283 {"evsetlths.", VX (4, 1563), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9284 {"evsetltwu", VX (4, 1564), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9285 {"evsetltwu.", VX (4, 1565), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9286 {"evsetltws", VX (4, 1566), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9287 {"evsetltws.", VX (4, 1567), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9288 {"evsaduw", VX (4, 1568), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9289 {"evsadsw", VX (4, 1569), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9290 {"evsad4ub", VX (4, 1570), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9291 {"evsad4sb", VX (4, 1571), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9292 {"evsad2uh", VX (4, 1572), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9293 {"evsad2sh", VX (4, 1573), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9294 {"evsaduwa", VX (4, 1576), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9295 {"evsadswa", VX (4, 1577), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9296 {"evsad4uba", VX (4, 1578), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9297 {"evsad4sba", VX (4, 1579), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9298 {"evsad2uha", VX (4, 1580), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9299 {"evsad2sha", VX (4, 1581), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9300 {"evabsdifuw", VX (4, 1584), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9301 {"evabsdifsw", VX (4, 1585), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9302 {"evabsdifub", VX (4, 1586), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9303 {"evabsdifsb", VX (4, 1587), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9304 {"evabsdifuh", VX (4, 1588), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9305 {"evabsdifsh", VX (4, 1589), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9306 {"evsaduwaa", VX (4, 1592), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9307 {"evsadswaa", VX (4, 1593), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9308 {"evsad4ubaaw", VX (4, 1594), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9309 {"evsad4sbaaw", VX (4, 1595), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9310 {"evsad2uhaaw", VX (4, 1596), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9311 {"evsad2shaaw", VX (4, 1597), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9312 {"evpkshubs", VX (4, 1600), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9313 {"evpkshsbs", VX (4, 1601), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9314 {"evpkswuhs", VX (4, 1602), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9315 {"evpkswshs", VX (4, 1603), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9316 {"evpkuhubs", VX (4, 1604), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9317 {"evpkuwuhs", VX (4, 1605), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9318 {"evpkswshilvs", VX (4, 1606), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9319 {"evpkswgshefrs", VX (4, 1607), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9320 {"evpkswshfrs", VX (4, 1608), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9321 {"evpkswshilvfrs", VX (4, 1609), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9322 {"evpksdswfrs", VX (4, 1610), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9323 {"evpksdshefrs", VX (4, 1611), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9324 {"evpkuduws", VX (4, 1612), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9325 {"evpksdsws", VX (4, 1613), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9326 {"evpkswgswfrs", VX (4, 1614), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9327 {"evilveh", VX (4, 1616), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9328 {"evilveoh", VX (4, 1617), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9329 {"evilvhih", VX (4, 1618), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9330 {"evilvhiloh", VX (4, 1619), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9331 {"evilvloh", VX (4, 1620), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9332 {"evilvlohih", VX (4, 1621), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9333 {"evilvoeh", VX (4, 1622), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9334 {"evilvoh", VX (4, 1623), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9335 {"evdlveb", VX (4, 1624), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9336 {"evdlveh", VX (4, 1625), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9337 {"evdlveob", VX (4, 1626), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9338 {"evdlveoh", VX (4, 1627), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9339 {"evdlvob", VX (4, 1628), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9340 {"evdlvoh", VX (4, 1629), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9341 {"evdlvoeb", VX (4, 1630), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9342 {"evdlvoeh", VX (4, 1631), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9343 {"evmaxbu", VX (4, 1632), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9344 {"evmaxbs", VX (4, 1633), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9345 {"evmaxhu", VX (4, 1634), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9346 {"evmaxhs", VX (4, 1635), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9347 {"evmaxwu", VX (4, 1636), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9348 {"evmaxws", VX (4, 1637), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9349 {"evmaxdu", VX (4, 1638), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9350 {"evmaxds", VX (4, 1639), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9351 {"evminbu", VX (4, 1640), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9352 {"evminbs", VX (4, 1641), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9353 {"evminhu", VX (4, 1642), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9354 {"evminhs", VX (4, 1643), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9355 {"evminwu", VX (4, 1644), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9356 {"evminws", VX (4, 1645), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9357 {"evmindu", VX (4, 1646), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9358 {"evminds", VX (4, 1647), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9359 {"evavgwu", VX (4, 1648), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9360 {"evavgws", VX (4, 1649), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9361 {"evavgbu", VX (4, 1650), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9362 {"evavgbs", VX (4, 1651), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9363 {"evavghu", VX (4, 1652), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9364 {"evavghs", VX (4, 1653), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9365 {"evavgdu", VX (4, 1654), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9366 {"evavgds", VX (4, 1655), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9367 {"evavgwur", VX (4, 1656), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9368 {"evavgwsr", VX (4, 1657), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9369 {"evavgbur", VX (4, 1658), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9370 {"evavgbsr", VX (4, 1659), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9371 {"evavghur", VX (4, 1660), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9372 {"evavghsr", VX (4, 1661), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9373 {"evavgdur", VX (4, 1662), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9374 {"evavgdsr", VX (4, 1663), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
9377 const int spe2_num_opcodes
=
9378 sizeof (spe2_opcodes
) / sizeof (spe2_opcodes
[0]);