1 /* ppc-opc.c -- PowerPC opcode list
2 Copyright 1994, 1995, 1996, 1997, 1998, 2000, 2001, 2002, 2003, 2004,
3 2005, 2006, 2007, 2008, 2009, 2010, 2011, 2012
4 Free Software Foundation, Inc.
5 Written by Ian Lance Taylor, Cygnus Support
7 This file is part of the GNU opcodes library.
9 This library is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 3, or (at your option)
14 It is distributed in the hope that it will be useful, but WITHOUT
15 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
16 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
17 License for more details.
19 You should have received a copy of the GNU General Public License
20 along with this file; see the file COPYING. If not, write to the
21 Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston,
22 MA 02110-1301, USA. */
26 #include "opcode/ppc.h"
29 /* This file holds the PowerPC opcode table. The opcode table
30 includes almost all of the extended instruction mnemonics. This
31 permits the disassembler to use them, and simplifies the assembler
32 logic, at the cost of increasing the table size. The table is
33 strictly constant data, so the compiler should be able to put it in
36 This file also holds the operand table. All knowledge about
37 inserting operands into instructions and vice-versa is kept in this
40 /* Local insertion and extraction functions. */
42 static unsigned long insert_arx (unsigned long, long, ppc_cpu_t
, const char **);
43 static long extract_arx (unsigned long, ppc_cpu_t
, int *);
44 static unsigned long insert_ary (unsigned long, long, ppc_cpu_t
, const char **);
45 static long extract_ary (unsigned long, ppc_cpu_t
, int *);
46 static unsigned long insert_bat (unsigned long, long, ppc_cpu_t
, const char **);
47 static long extract_bat (unsigned long, ppc_cpu_t
, int *);
48 static unsigned long insert_bba (unsigned long, long, ppc_cpu_t
, const char **);
49 static long extract_bba (unsigned long, ppc_cpu_t
, int *);
50 static unsigned long insert_bdm (unsigned long, long, ppc_cpu_t
, const char **);
51 static long extract_bdm (unsigned long, ppc_cpu_t
, int *);
52 static unsigned long insert_bdp (unsigned long, long, ppc_cpu_t
, const char **);
53 static long extract_bdp (unsigned long, ppc_cpu_t
, int *);
54 static unsigned long insert_bo (unsigned long, long, ppc_cpu_t
, const char **);
55 static long extract_bo (unsigned long, ppc_cpu_t
, int *);
56 static unsigned long insert_boe (unsigned long, long, ppc_cpu_t
, const char **);
57 static long extract_boe (unsigned long, ppc_cpu_t
, int *);
58 static unsigned long insert_fxm (unsigned long, long, ppc_cpu_t
, const char **);
59 static long extract_fxm (unsigned long, ppc_cpu_t
, int *);
60 static unsigned long insert_li20 (unsigned long, long, ppc_cpu_t
, const char **);
61 static long extract_li20 (unsigned long, ppc_cpu_t
, int *);
62 static unsigned long insert_ls (unsigned long, long, ppc_cpu_t
, const char **);
63 static unsigned long insert_mbe (unsigned long, long, ppc_cpu_t
, const char **);
64 static long extract_mbe (unsigned long, ppc_cpu_t
, int *);
65 static unsigned long insert_mb6 (unsigned long, long, ppc_cpu_t
, const char **);
66 static long extract_mb6 (unsigned long, ppc_cpu_t
, int *);
67 static long extract_nb (unsigned long, ppc_cpu_t
, int *);
68 static unsigned long insert_nbi (unsigned long, long, ppc_cpu_t
, const char **);
69 static unsigned long insert_nsi (unsigned long, long, ppc_cpu_t
, const char **);
70 static long extract_nsi (unsigned long, ppc_cpu_t
, int *);
71 static unsigned long insert_oimm (unsigned long, long, ppc_cpu_t
, const char **);
72 static long extract_oimm (unsigned long, ppc_cpu_t
, int *);
73 static unsigned long insert_ral (unsigned long, long, ppc_cpu_t
, const char **);
74 static unsigned long insert_ram (unsigned long, long, ppc_cpu_t
, const char **);
75 static unsigned long insert_raq (unsigned long, long, ppc_cpu_t
, const char **);
76 static unsigned long insert_ras (unsigned long, long, ppc_cpu_t
, const char **);
77 static unsigned long insert_rbs (unsigned long, long, ppc_cpu_t
, const char **);
78 static long extract_rbs (unsigned long, ppc_cpu_t
, int *);
79 static unsigned long insert_rbx (unsigned long, long, ppc_cpu_t
, const char **);
80 static unsigned long insert_rx (unsigned long, long, ppc_cpu_t
, const char **);
81 static long extract_rx (unsigned long, ppc_cpu_t
, int *);
82 static unsigned long insert_ry (unsigned long, long, ppc_cpu_t
, const char **);
83 static long extract_ry (unsigned long, ppc_cpu_t
, int *);
84 static unsigned long insert_sh6 (unsigned long, long, ppc_cpu_t
, const char **);
85 static long extract_sh6 (unsigned long, ppc_cpu_t
, int *);
86 static unsigned long insert_sci8 (unsigned long, long, ppc_cpu_t
, const char **);
87 static long extract_sci8 (unsigned long, ppc_cpu_t
, int *);
88 static unsigned long insert_sci8n (unsigned long, long, ppc_cpu_t
, const char **);
89 static long extract_sci8n (unsigned long, ppc_cpu_t
, int *);
90 static unsigned long insert_sd4h (unsigned long, long, ppc_cpu_t
, const char **);
91 static long extract_sd4h (unsigned long, ppc_cpu_t
, int *);
92 static unsigned long insert_sd4w (unsigned long, long, ppc_cpu_t
, const char **);
93 static long extract_sd4w (unsigned long, ppc_cpu_t
, int *);
94 static unsigned long insert_spr (unsigned long, long, ppc_cpu_t
, const char **);
95 static long extract_spr (unsigned long, ppc_cpu_t
, int *);
96 static unsigned long insert_sprg (unsigned long, long, ppc_cpu_t
, const char **);
97 static long extract_sprg (unsigned long, ppc_cpu_t
, int *);
98 static unsigned long insert_tbr (unsigned long, long, ppc_cpu_t
, const char **);
99 static long extract_tbr (unsigned long, ppc_cpu_t
, int *);
100 static unsigned long insert_xt6 (unsigned long, long, ppc_cpu_t
, const char **);
101 static long extract_xt6 (unsigned long, ppc_cpu_t
, int *);
102 static unsigned long insert_xa6 (unsigned long, long, ppc_cpu_t
, const char **);
103 static long extract_xa6 (unsigned long, ppc_cpu_t
, int *);
104 static unsigned long insert_xb6 (unsigned long, long, ppc_cpu_t
, const char **);
105 static long extract_xb6 (unsigned long, ppc_cpu_t
, int *);
106 static unsigned long insert_xb6s (unsigned long, long, ppc_cpu_t
, const char **);
107 static long extract_xb6s (unsigned long, ppc_cpu_t
, int *);
108 static unsigned long insert_xc6 (unsigned long, long, ppc_cpu_t
, const char **);
109 static long extract_xc6 (unsigned long, ppc_cpu_t
, int *);
110 static unsigned long insert_dm (unsigned long, long, ppc_cpu_t
, const char **);
111 static long extract_dm (unsigned long, ppc_cpu_t
, int *);
112 static unsigned long insert_vlesi (unsigned long, long, ppc_cpu_t
, const char **);
113 static long extract_vlesi (unsigned long, ppc_cpu_t
, int *);
114 static unsigned long insert_vlensi (unsigned long, long, ppc_cpu_t
, const char **);
115 static long extract_vlensi (unsigned long, ppc_cpu_t
, int *);
116 static unsigned long insert_vleui (unsigned long, long, ppc_cpu_t
, const char **);
117 static long extract_vleui (unsigned long, ppc_cpu_t
, int *);
118 static unsigned long insert_vleil (unsigned long, long, ppc_cpu_t
, const char **);
119 static long extract_vleil (unsigned long, ppc_cpu_t
, int *);
121 /* The operands table.
123 The fields are bitm, shift, insert, extract, flags.
125 We used to put parens around the various additions, like the one
126 for BA just below. However, that caused trouble with feeble
127 compilers with a limit on depth of a parenthesized expression, like
128 (reportedly) the compiler in Microsoft Developer Studio 5. So we
129 omit the parens, since the macros are never used in a context where
130 the addition will be ambiguous. */
132 const struct powerpc_operand powerpc_operands
[] =
134 /* The zero index is used to indicate the end of the list of
137 { 0, 0, NULL
, NULL
, 0 },
139 /* The BA field in an XL form instruction. */
140 #define BA UNUSED + 1
141 /* The BI field in a B form or XL form instruction. */
143 #define BI_MASK (0x1f << 16)
144 { 0x1f, 16, NULL
, NULL
, PPC_OPERAND_CR_BIT
},
146 /* The BA field in an XL form instruction when it must be the same
147 as the BT field in the same instruction. */
149 { 0x1f, 16, insert_bat
, extract_bat
, PPC_OPERAND_FAKE
},
151 /* The BB field in an XL form instruction. */
153 #define BB_MASK (0x1f << 11)
154 { 0x1f, 11, NULL
, NULL
, PPC_OPERAND_CR_BIT
},
156 /* The BB field in an XL form instruction when it must be the same
157 as the BA field in the same instruction. */
159 /* The VB field in a VX form instruction when it must be the same
160 as the VA field in the same instruction. */
162 { 0x1f, 11, insert_bba
, extract_bba
, PPC_OPERAND_FAKE
},
164 /* The BD field in a B form instruction. The lower two bits are
167 { 0xfffc, 0, NULL
, NULL
, PPC_OPERAND_RELATIVE
| PPC_OPERAND_SIGNED
},
169 /* The BD field in a B form instruction when absolute addressing is
172 { 0xfffc, 0, NULL
, NULL
, PPC_OPERAND_ABSOLUTE
| PPC_OPERAND_SIGNED
},
174 /* The BD field in a B form instruction when the - modifier is used.
175 This sets the y bit of the BO field appropriately. */
177 { 0xfffc, 0, insert_bdm
, extract_bdm
,
178 PPC_OPERAND_RELATIVE
| PPC_OPERAND_SIGNED
},
180 /* The BD field in a B form instruction when the - modifier is used
181 and absolute address is used. */
183 { 0xfffc, 0, insert_bdm
, extract_bdm
,
184 PPC_OPERAND_ABSOLUTE
| PPC_OPERAND_SIGNED
},
186 /* The BD field in a B form instruction when the + modifier is used.
187 This sets the y bit of the BO field appropriately. */
189 { 0xfffc, 0, insert_bdp
, extract_bdp
,
190 PPC_OPERAND_RELATIVE
| PPC_OPERAND_SIGNED
},
192 /* The BD field in a B form instruction when the + modifier is used
193 and absolute addressing is used. */
195 { 0xfffc, 0, insert_bdp
, extract_bdp
,
196 PPC_OPERAND_ABSOLUTE
| PPC_OPERAND_SIGNED
},
198 /* The BF field in an X or XL form instruction. */
200 /* The CRFD field in an X form instruction. */
202 /* The CRD field in an XL form instruction. */
204 { 0x7, 23, NULL
, NULL
, PPC_OPERAND_CR_REG
},
206 /* The BF field in an X or XL form instruction. */
208 { 0x7, 23, NULL
, NULL
, 0 },
210 /* An optional BF field. This is used for comparison instructions,
211 in which an omitted BF field is taken as zero. */
213 { 0x7, 23, NULL
, NULL
, PPC_OPERAND_CR_REG
| PPC_OPERAND_OPTIONAL
},
215 /* The BFA field in an X or XL form instruction. */
217 { 0x7, 18, NULL
, NULL
, PPC_OPERAND_CR_REG
},
219 /* The BO field in a B form instruction. Certain values are
222 #define BO_MASK (0x1f << 21)
223 { 0x1f, 21, insert_bo
, extract_bo
, 0 },
225 /* The BO field in a B form instruction when the + or - modifier is
226 used. This is like the BO field, but it must be even. */
228 { 0x1e, 21, insert_boe
, extract_boe
, 0 },
231 { 0x3, 11, NULL
, NULL
, PPC_OPERAND_OPTIONAL
},
233 /* The BT field in an X or XL form instruction. */
235 { 0x1f, 21, NULL
, NULL
, PPC_OPERAND_CR_BIT
},
237 /* The BI16 field in a BD8 form instruction. */
239 { 0x3, 8, NULL
, NULL
, PPC_OPERAND_CR_BIT
},
241 /* The BI32 field in a BD15 form instruction. */
242 #define BI32 BI16 + 1
243 { 0xf, 16, NULL
, NULL
, PPC_OPERAND_CR_BIT
},
245 /* The BO32 field in a BD15 form instruction. */
246 #define BO32 BI32 + 1
247 { 0x3, 20, NULL
, NULL
, 0 },
249 /* The B8 field in a BD8 form instruction. */
251 { 0x1fe, -1, NULL
, NULL
, PPC_OPERAND_RELATIVE
| PPC_OPERAND_SIGNED
},
253 /* The B15 field in a BD15 form instruction. The lowest bit is
256 { 0xfffe, 0, NULL
, NULL
, PPC_OPERAND_RELATIVE
| PPC_OPERAND_SIGNED
},
258 /* The B24 field in a BD24 form instruction. The lowest bit is
261 { 0x1fffffe, 0, NULL
, NULL
, PPC_OPERAND_RELATIVE
| PPC_OPERAND_SIGNED
},
263 /* The condition register number portion of the BI field in a B form
264 or XL form instruction. This is used for the extended
265 conditional branch mnemonics, which set the lower two bits of the
266 BI field. This field is optional. */
268 { 0x7, 18, NULL
, NULL
, PPC_OPERAND_CR_REG
| PPC_OPERAND_OPTIONAL
},
270 /* The CRB field in an X form instruction. */
272 /* The MB field in an M form instruction. */
274 #define MB_MASK (0x1f << 6)
275 { 0x1f, 6, NULL
, NULL
, 0 },
277 /* The CRD32 field in an XL form instruction. */
278 #define CRD32 CRB + 1
279 { 0x3, 21, NULL
, NULL
, PPC_OPERAND_CR_REG
},
281 /* The CRFS field in an X form instruction. */
282 #define CRFS CRD32 + 1
283 { 0x7, 0, NULL
, NULL
, PPC_OPERAND_CR_REG
},
286 { 0x3, 18, NULL
, NULL
, PPC_OPERAND_CR_REG
| PPC_OPERAND_OPTIONAL
},
288 /* The CT field in an X form instruction. */
290 /* The MO field in an mbar instruction. */
292 { 0x1f, 21, NULL
, NULL
, PPC_OPERAND_OPTIONAL
},
294 /* The D field in a D form instruction. This is a displacement off
295 a register, and implies that the next operand is a register in
298 { 0xffff, 0, NULL
, NULL
, PPC_OPERAND_PARENS
| PPC_OPERAND_SIGNED
},
300 /* The D8 field in a D form instruction. This is a displacement off
301 a register, and implies that the next operand is a register in
304 { 0xff, 0, NULL
, NULL
, PPC_OPERAND_PARENS
| PPC_OPERAND_SIGNED
},
306 /* The DQ field in a DQ form instruction. This is like D, but the
307 lower four bits are forced to zero. */
309 { 0xfff0, 0, NULL
, NULL
,
310 PPC_OPERAND_PARENS
| PPC_OPERAND_SIGNED
| PPC_OPERAND_DQ
},
312 /* The DS field in a DS form instruction. This is like D, but the
313 lower two bits are forced to zero. */
315 { 0xfffc, 0, NULL
, NULL
,
316 PPC_OPERAND_PARENS
| PPC_OPERAND_SIGNED
| PPC_OPERAND_DS
},
318 /* The DUIS or BHRBE fields in a XFX form instruction, 10 bits
322 { 0x3ff, 11, NULL
, NULL
, 0 },
324 /* The E field in a wrteei instruction. */
325 /* And the W bit in the pair singles instructions. */
326 /* And the ST field in a VX form instruction. */
330 { 0x1, 15, NULL
, NULL
, 0 },
332 /* The FL1 field in a POWER SC form instruction. */
334 /* The U field in an X form instruction. */
336 { 0xf, 12, NULL
, NULL
, 0 },
338 /* The FL2 field in a POWER SC form instruction. */
340 { 0x7, 2, NULL
, NULL
, 0 },
342 /* The FLM field in an XFL form instruction. */
344 { 0xff, 17, NULL
, NULL
, 0 },
346 /* The FRA field in an X or A form instruction. */
348 #define FRA_MASK (0x1f << 16)
349 { 0x1f, 16, NULL
, NULL
, PPC_OPERAND_FPR
},
351 /* The FRAp field of DFP instructions. */
353 { 0x1e, 16, NULL
, NULL
, PPC_OPERAND_FPR
},
355 /* The FRB field in an X or A form instruction. */
357 #define FRB_MASK (0x1f << 11)
358 { 0x1f, 11, NULL
, NULL
, PPC_OPERAND_FPR
},
360 /* The FRBp field of DFP instructions. */
362 { 0x1e, 11, NULL
, NULL
, PPC_OPERAND_FPR
},
364 /* The FRC field in an A form instruction. */
366 #define FRC_MASK (0x1f << 6)
367 { 0x1f, 6, NULL
, NULL
, PPC_OPERAND_FPR
},
369 /* The FRS field in an X form instruction or the FRT field in a D, X
370 or A form instruction. */
373 { 0x1f, 21, NULL
, NULL
, PPC_OPERAND_FPR
},
375 /* The FRSp field of stfdp or the FRTp field of lfdp and DFP
379 { 0x1e, 21, NULL
, NULL
, PPC_OPERAND_FPR
},
381 /* The FXM field in an XFX instruction. */
383 { 0xff, 12, insert_fxm
, extract_fxm
, 0 },
385 /* Power4 version for mfcr. */
387 { 0xff, 12, insert_fxm
, extract_fxm
, PPC_OPERAND_OPTIONAL
},
389 /* The IMM20 field in an LI instruction. */
390 #define IMM20 FXM4 + 1
391 { 0xfffff, PPC_OPSHIFT_INV
, insert_li20
, extract_li20
, PPC_OPERAND_SIGNED
},
393 /* The L field in a D or X form instruction. */
395 /* The R field in a HTM X form instruction. */
397 { 0x1, 21, NULL
, NULL
, PPC_OPERAND_OPTIONAL
},
399 /* The LEV field in a POWER SVC form instruction. */
400 #define SVC_LEV L + 1
401 { 0x7f, 5, NULL
, NULL
, 0 },
403 /* The LEV field in an SC form instruction. */
404 #define LEV SVC_LEV + 1
405 { 0x7f, 5, NULL
, NULL
, PPC_OPERAND_OPTIONAL
},
407 /* The LI field in an I form instruction. The lower two bits are
410 { 0x3fffffc, 0, NULL
, NULL
, PPC_OPERAND_RELATIVE
| PPC_OPERAND_SIGNED
},
412 /* The LI field in an I form instruction when used as an absolute
415 { 0x3fffffc, 0, NULL
, NULL
, PPC_OPERAND_ABSOLUTE
| PPC_OPERAND_SIGNED
},
417 /* The LS or WC field in an X (sync or wait) form instruction. */
420 { 0x3, 21, NULL
, NULL
, PPC_OPERAND_OPTIONAL
},
422 /* The ME field in an M form instruction. */
424 #define ME_MASK (0x1f << 1)
425 { 0x1f, 1, NULL
, NULL
, 0 },
427 /* The MB and ME fields in an M form instruction expressed a single
428 operand which is a bitmask indicating which bits to select. This
429 is a two operand form using PPC_OPERAND_NEXT. See the
430 description in opcode/ppc.h for what this means. */
432 { 0x1f, 6, NULL
, NULL
, PPC_OPERAND_OPTIONAL
| PPC_OPERAND_NEXT
},
433 { -1, 0, insert_mbe
, extract_mbe
, 0 },
435 /* The MB or ME field in an MD or MDS form instruction. The high
436 bit is wrapped to the low end. */
439 #define MB6_MASK (0x3f << 5)
440 { 0x3f, 5, insert_mb6
, extract_mb6
, 0 },
442 /* The NB field in an X form instruction. The value 32 is stored as
445 { 0x1f, 11, NULL
, extract_nb
, PPC_OPERAND_PLUS1
},
447 /* The NBI field in an lswi instruction, which has special value
448 restrictions. The value 32 is stored as 0. */
450 { 0x1f, 11, insert_nbi
, extract_nb
, PPC_OPERAND_PLUS1
},
452 /* The NSI field in a D form instruction. This is the same as the
453 SI field, only negated. */
455 { 0xffff, 0, insert_nsi
, extract_nsi
,
456 PPC_OPERAND_NEGATIVE
| PPC_OPERAND_SIGNED
},
458 /* The RA field in an D, DS, DQ, X, XO, M, or MDS form instruction. */
460 #define RA_MASK (0x1f << 16)
461 { 0x1f, 16, NULL
, NULL
, PPC_OPERAND_GPR
},
463 /* As above, but 0 in the RA field means zero, not r0. */
465 { 0x1f, 16, NULL
, NULL
, PPC_OPERAND_GPR_0
},
467 /* The RA field in the DQ form lq or an lswx instruction, which have special
468 value restrictions. */
471 { 0x1f, 16, insert_raq
, NULL
, PPC_OPERAND_GPR_0
},
473 /* The RA field in a D or X form instruction which is an updating
474 load, which means that the RA field may not be zero and may not
475 equal the RT field. */
477 { 0x1f, 16, insert_ral
, NULL
, PPC_OPERAND_GPR_0
},
479 /* The RA field in an lmw instruction, which has special value
482 { 0x1f, 16, insert_ram
, NULL
, PPC_OPERAND_GPR_0
},
484 /* The RA field in a D or X form instruction which is an updating
485 store or an updating floating point load, which means that the RA
486 field may not be zero. */
488 { 0x1f, 16, insert_ras
, NULL
, PPC_OPERAND_GPR_0
},
490 /* The RA field of the tlbwe, dccci and iccci instructions,
491 which are optional. */
492 #define RAOPT RAS + 1
493 { 0x1f, 16, NULL
, NULL
, PPC_OPERAND_GPR
| PPC_OPERAND_OPTIONAL
},
495 /* The RB field in an X, XO, M, or MDS form instruction. */
497 #define RB_MASK (0x1f << 11)
498 { 0x1f, 11, NULL
, NULL
, PPC_OPERAND_GPR
},
500 /* The RB field in an X form instruction when it must be the same as
501 the RS field in the instruction. This is used for extended
502 mnemonics like mr. */
504 { 0x1f, 11, insert_rbs
, extract_rbs
, PPC_OPERAND_FAKE
},
506 /* The RB field in an lswx instruction, which has special value
509 { 0x1f, 11, insert_rbx
, NULL
, PPC_OPERAND_GPR
},
511 /* The RB field of the dccci and iccci instructions, which are optional. */
512 #define RBOPT RBX + 1
513 { 0x1f, 11, NULL
, NULL
, PPC_OPERAND_GPR
| PPC_OPERAND_OPTIONAL
},
515 /* The RS field in a D, DS, X, XFX, XS, M, MD or MDS form
516 instruction or the RT field in a D, DS, X, XFX or XO form
520 #define RT_MASK (0x1f << 21)
522 { 0x1f, 21, NULL
, NULL
, PPC_OPERAND_GPR
},
524 /* The RS and RT fields of the DS form stq and DQ form lq instructions,
525 which have special value restrictions. */
528 { 0x1e, 21, NULL
, NULL
, PPC_OPERAND_GPR
},
530 /* The RS field of the tlbwe instruction, which is optional. */
533 { 0x1f, 21, NULL
, NULL
, PPC_OPERAND_GPR
| PPC_OPERAND_OPTIONAL
},
535 /* The RX field of the SE_RR form instruction. */
537 { 0x1f, PPC_OPSHIFT_INV
, insert_rx
, extract_rx
, PPC_OPERAND_GPR
},
539 /* The ARX field of the SE_RR form instruction. */
541 { 0x1f, PPC_OPSHIFT_INV
, insert_arx
, extract_arx
, PPC_OPERAND_GPR
},
543 /* The RY field of the SE_RR form instruction. */
546 { 0x1f, PPC_OPSHIFT_INV
, insert_ry
, extract_ry
, PPC_OPERAND_GPR
},
548 /* The ARY field of the SE_RR form instruction. */
550 { 0x1f, PPC_OPSHIFT_INV
, insert_ary
, extract_ary
, PPC_OPERAND_GPR
},
552 /* The SCLSCI8 field in a D form instruction. */
553 #define SCLSCI8 ARY + 1
554 { 0xffffffff, PPC_OPSHIFT_INV
, insert_sci8
, extract_sci8
, 0 },
556 /* The SCLSCI8N field in a D form instruction. This is the same as the
557 SCLSCI8 field, only negated. */
558 #define SCLSCI8N SCLSCI8 + 1
559 { 0xffffffff, PPC_OPSHIFT_INV
, insert_sci8n
, extract_sci8n
,
560 PPC_OPERAND_NEGATIVE
| PPC_OPERAND_SIGNED
},
562 /* The SD field of the SD4 form instruction. */
563 #define SE_SD SCLSCI8N + 1
564 { 0xf, 8, NULL
, NULL
, PPC_OPERAND_PARENS
},
566 /* The SD field of the SD4 form instruction, for halfword. */
567 #define SE_SDH SE_SD + 1
568 { 0x1e, PPC_OPSHIFT_INV
, insert_sd4h
, extract_sd4h
, PPC_OPERAND_PARENS
},
570 /* The SD field of the SD4 form instruction, for word. */
571 #define SE_SDW SE_SDH + 1
572 { 0x3c, PPC_OPSHIFT_INV
, insert_sd4w
, extract_sd4w
, PPC_OPERAND_PARENS
},
574 /* The SH field in an X or M form instruction. */
575 #define SH SE_SDW + 1
576 #define SH_MASK (0x1f << 11)
577 /* The other UIMM field in a EVX form instruction. */
579 { 0x1f, 11, NULL
, NULL
, 0 },
581 /* The SI field in a HTM X form instruction. */
582 #define HTM_SI SH + 1
583 { 0x1f, 11, NULL
, NULL
, PPC_OPERAND_SIGNED
},
585 /* The SH field in an MD form instruction. This is split. */
586 #define SH6 HTM_SI + 1
587 #define SH6_MASK ((0x1f << 11) | (1 << 1))
588 { 0x3f, PPC_OPSHIFT_INV
, insert_sh6
, extract_sh6
, 0 },
590 /* The SH field of the tlbwe instruction, which is optional. */
592 { 0x1f, 11, NULL
, NULL
, PPC_OPERAND_OPTIONAL
},
594 /* The SI field in a D form instruction. */
596 { 0xffff, 0, NULL
, NULL
, PPC_OPERAND_SIGNED
},
598 /* The SI field in a D form instruction when we accept a wide range
599 of positive values. */
600 #define SISIGNOPT SI + 1
601 { 0xffff, 0, NULL
, NULL
, PPC_OPERAND_SIGNED
| PPC_OPERAND_SIGNOPT
},
603 /* The SI8 field in a D form instruction. */
604 #define SI8 SISIGNOPT + 1
605 { 0xff, 0, NULL
, NULL
, PPC_OPERAND_SIGNED
},
607 /* The SPR field in an XFX form instruction. This is flipped--the
608 lower 5 bits are stored in the upper 5 and vice- versa. */
612 #define SPR_MASK (0x3ff << 11)
613 { 0x3ff, 11, insert_spr
, extract_spr
, 0 },
615 /* The BAT index number in an XFX form m[ft]ibat[lu] instruction. */
616 #define SPRBAT SPR + 1
617 #define SPRBAT_MASK (0x3 << 17)
618 { 0x3, 17, NULL
, NULL
, 0 },
620 /* The SPRG register number in an XFX form m[ft]sprg instruction. */
621 #define SPRG SPRBAT + 1
622 { 0x1f, 16, insert_sprg
, extract_sprg
, 0 },
624 /* The SR field in an X form instruction. */
626 /* The 4-bit UIMM field in a VX form instruction. */
628 { 0xf, 16, NULL
, NULL
, 0 },
630 /* The STRM field in an X AltiVec form instruction. */
632 /* The T field in a tlbilx form instruction. */
634 { 0x3, 21, NULL
, NULL
, 0 },
636 /* The ESYNC field in an X (sync) form instruction. */
637 #define ESYNC STRM + 1
638 { 0xf, 16, insert_ls
, NULL
, PPC_OPERAND_OPTIONAL
},
640 /* The SV field in a POWER SC form instruction. */
642 { 0x3fff, 2, NULL
, NULL
, 0 },
644 /* The TBR field in an XFX form instruction. This is like the SPR
645 field, but it is optional. */
647 { 0x3ff, 11, insert_tbr
, extract_tbr
, PPC_OPERAND_OPTIONAL
},
649 /* The TO field in a D or X form instruction. */
652 #define TO_MASK (0x1f << 21)
653 { 0x1f, 21, NULL
, NULL
, 0 },
655 /* The UI field in a D form instruction. */
657 { 0xffff, 0, NULL
, NULL
, 0 },
659 /* The IMM field in an SE_IM5 instruction. */
661 { 0x1f, 4, NULL
, NULL
, 0 },
663 /* The OIMM field in an SE_OIM5 instruction. */
664 #define OIMM5 UI5 + 1
665 { 0x1f, PPC_OPSHIFT_INV
, insert_oimm
, extract_oimm
, PPC_OPERAND_PLUS1
},
667 /* The UI7 field in an SE_LI instruction. */
668 #define UI7 OIMM5 + 1
669 { 0x7f, 4, NULL
, NULL
, 0 },
671 /* The VA field in a VA, VX or VXR form instruction. */
673 { 0x1f, 16, NULL
, NULL
, PPC_OPERAND_VR
},
675 /* The VB field in a VA, VX or VXR form instruction. */
677 { 0x1f, 11, NULL
, NULL
, PPC_OPERAND_VR
},
679 /* The VC field in a VA form instruction. */
681 { 0x1f, 6, NULL
, NULL
, PPC_OPERAND_VR
},
683 /* The VD or VS field in a VA, VX, VXR or X form instruction. */
686 { 0x1f, 21, NULL
, NULL
, PPC_OPERAND_VR
},
688 /* The SIMM field in a VX form instruction, and TE in Z form. */
691 { 0x1f, 16, NULL
, NULL
, PPC_OPERAND_SIGNED
},
693 /* The UIMM field in a VX form instruction. */
694 #define UIMM SIMM + 1
696 { 0x1f, 16, NULL
, NULL
, 0 },
698 /* The 3-bit UIMM field in a VX form instruction. */
699 #define UIMM3 UIMM + 1
700 { 0x7, 16, NULL
, NULL
, 0 },
702 /* The SIX field in a VX form instruction. */
703 #define SIX UIMM3 + 1
704 { 0xf, 11, NULL
, NULL
, 0 },
706 /* The PS field in a VX form instruction. */
708 { 0x1, 9, NULL
, NULL
, 0 },
710 /* The SHB field in a VA form instruction. */
712 { 0xf, 6, NULL
, NULL
, 0 },
714 /* The other UIMM field in a half word EVX form instruction. */
715 #define EVUIMM_2 SHB + 1
716 { 0x3e, 10, NULL
, NULL
, PPC_OPERAND_PARENS
},
718 /* The other UIMM field in a word EVX form instruction. */
719 #define EVUIMM_4 EVUIMM_2 + 1
720 { 0x7c, 9, NULL
, NULL
, PPC_OPERAND_PARENS
},
722 /* The other UIMM field in a double EVX form instruction. */
723 #define EVUIMM_8 EVUIMM_4 + 1
724 { 0xf8, 8, NULL
, NULL
, PPC_OPERAND_PARENS
},
727 #define WS EVUIMM_8 + 1
728 { 0x7, 11, NULL
, NULL
, 0 },
730 /* PowerPC paired singles extensions. */
731 /* W bit in the pair singles instructions for x type instructions. */
733 /* The BO16 field in a BD8 form instruction. */
735 { 0x1, 10, 0, 0, 0 },
737 /* IDX bits for quantization in the pair singles instructions. */
739 { 0x7, 12, 0, 0, 0 },
741 /* IDX bits for quantization in the pair singles x-type instructions. */
745 /* Smaller D field for quantization in the pair singles instructions. */
747 { 0xfff, 0, 0, 0, PPC_OPERAND_PARENS
| PPC_OPERAND_SIGNED
},
752 { 0x1, 16, NULL
, NULL
, PPC_OPERAND_OPTIONAL
},
754 #define RMC MTMSRD_L + 1
755 { 0x3, 9, NULL
, NULL
, 0 },
758 { 0x1, 16, NULL
, NULL
, 0 },
761 { 0x3, 19, NULL
, NULL
, 0 },
764 { 0x1, 20, NULL
, NULL
, 0 },
766 /* The S field in a XL form instruction. */
768 { 0x1, 11, NULL
, NULL
, PPC_OPERAND_OPTIONAL
},
770 /* SH field starting at bit position 16. */
772 /* The DCM and DGM fields in a Z form instruction. */
775 { 0x3f, 10, NULL
, NULL
, 0 },
777 /* The EH field in larx instruction. */
779 { 0x1, 0, NULL
, NULL
, PPC_OPERAND_OPTIONAL
},
781 /* The L field in an mtfsf or XFL form instruction. */
782 /* The A field in a HTM X form instruction. */
785 { 0x1, 25, NULL
, NULL
, PPC_OPERAND_OPTIONAL
},
787 /* Xilinx APU related masks and macros */
788 #define FCRT XFL_L + 1
789 #define FCRT_MASK (0x1f << 21)
790 { 0x1f, 21, 0, 0, PPC_OPERAND_FCR
},
792 /* Xilinx FSL related masks and macros */
794 #define FSL_MASK (0x1f << 11)
795 { 0x1f, 11, 0, 0, PPC_OPERAND_FSL
},
797 /* Xilinx UDI related masks and macros */
799 { 0x1f, 21, 0, 0, PPC_OPERAND_UDI
},
802 { 0x1f, 16, 0, 0, PPC_OPERAND_UDI
},
805 { 0x1f, 11, 0, 0, PPC_OPERAND_UDI
},
808 { 0x1f, 6, 0, 0, PPC_OPERAND_UDI
},
810 /* The VLESIMM field in a D form instruction. */
811 #define VLESIMM URC + 1
812 { 0xffff, PPC_OPSHIFT_INV
, insert_vlesi
, extract_vlesi
,
813 PPC_OPERAND_SIGNED
| PPC_OPERAND_SIGNOPT
},
815 /* The VLENSIMM field in a D form instruction. */
816 #define VLENSIMM VLESIMM + 1
817 { 0xffff, PPC_OPSHIFT_INV
, insert_vlensi
, extract_vlensi
,
818 PPC_OPERAND_NEGATIVE
| PPC_OPERAND_SIGNED
| PPC_OPERAND_SIGNOPT
},
820 /* The VLEUIMM field in a D form instruction. */
821 #define VLEUIMM VLENSIMM + 1
822 { 0xffff, PPC_OPSHIFT_INV
, insert_vleui
, extract_vleui
, 0 },
824 /* The VLEUIMML field in a D form instruction. */
825 #define VLEUIMML VLEUIMM + 1
826 { 0xffff, PPC_OPSHIFT_INV
, insert_vleil
, extract_vleil
, 0 },
828 /* The XT and XS fields in an XX1 or XX3 form instruction. This is split. */
829 #define XS6 VLEUIMML + 1
831 { 0x3f, PPC_OPSHIFT_INV
, insert_xt6
, extract_xt6
, PPC_OPERAND_VSR
},
833 /* The XA field in an XX3 form instruction. This is split. */
835 { 0x3f, PPC_OPSHIFT_INV
, insert_xa6
, extract_xa6
, PPC_OPERAND_VSR
},
837 /* The XB field in an XX2 or XX3 form instruction. This is split. */
839 { 0x3f, PPC_OPSHIFT_INV
, insert_xb6
, extract_xb6
, PPC_OPERAND_VSR
},
841 /* The XB field in an XX3 form instruction when it must be the same as
842 the XA field in the instruction. This is used in extended mnemonics
843 like xvmovdp. This is split. */
845 { 0x3f, PPC_OPSHIFT_INV
, insert_xb6s
, extract_xb6s
, PPC_OPERAND_FAKE
},
847 /* The XC field in an XX4 form instruction. This is split. */
849 { 0x3f, PPC_OPSHIFT_INV
, insert_xc6
, extract_xc6
, PPC_OPERAND_VSR
},
851 /* The DM or SHW field in an XX3 form instruction. */
854 { 0x3, 8, NULL
, NULL
, 0 },
856 /* The DM field in an extended mnemonic XX3 form instruction. */
858 { 0x3, 8, insert_dm
, extract_dm
, 0 },
860 /* The UIM field in an XX2 form instruction. */
862 /* The 2-bit UIMM field in a VX form instruction. */
864 { 0x3, 16, NULL
, NULL
, 0 },
866 #define ERAT_T UIM + 1
867 { 0x7, 21, NULL
, NULL
, 0 },
870 const unsigned int num_powerpc_operands
= (sizeof (powerpc_operands
)
871 / sizeof (powerpc_operands
[0]));
873 /* The functions used to insert and extract complicated operands. */
875 /* The ARX, ARY, RX and RY operands are alternate encodings of GPRs. */
878 insert_arx (unsigned long insn
,
880 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
881 const char **errmsg ATTRIBUTE_UNUSED
)
883 if (value
>= 8 && value
< 24)
884 return insn
| ((value
- 8) & 0xf);
887 *errmsg
= _("invalid register");
893 extract_arx (unsigned long insn
,
894 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
895 int *invalid ATTRIBUTE_UNUSED
)
897 return (insn
& 0xf) + 8;
901 insert_ary (unsigned long insn
,
903 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
904 const char **errmsg ATTRIBUTE_UNUSED
)
906 if (value
>= 8 && value
< 24)
907 return insn
| (((value
- 8) & 0xf) << 4);
910 *errmsg
= _("invalid register");
916 extract_ary (unsigned long insn
,
917 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
918 int *invalid ATTRIBUTE_UNUSED
)
920 return ((insn
>> 4) & 0xf) + 8;
924 insert_rx (unsigned long insn
,
926 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
929 if (value
>= 0 && value
< 8)
931 else if (value
>= 24 && value
<= 31)
932 return insn
| (value
- 16);
935 *errmsg
= _("invalid register");
941 extract_rx (unsigned long insn
,
942 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
943 int *invalid ATTRIBUTE_UNUSED
)
945 int value
= insn
& 0xf;
946 if (value
>= 0 && value
< 8)
953 insert_ry (unsigned long insn
,
955 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
958 if (value
>= 0 && value
< 8)
959 return insn
| (value
<< 4);
960 else if (value
>= 24 && value
<= 31)
961 return insn
| ((value
- 16) << 4);
964 *errmsg
= _("invalid register");
970 extract_ry (unsigned long insn
,
971 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
972 int *invalid ATTRIBUTE_UNUSED
)
974 int value
= (insn
>> 4) & 0xf;
975 if (value
>= 0 && value
< 8)
981 /* The BA field in an XL form instruction when it must be the same as
982 the BT field in the same instruction. This operand is marked FAKE.
983 The insertion function just copies the BT field into the BA field,
984 and the extraction function just checks that the fields are the
988 insert_bat (unsigned long insn
,
989 long value ATTRIBUTE_UNUSED
,
990 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
991 const char **errmsg ATTRIBUTE_UNUSED
)
993 return insn
| (((insn
>> 21) & 0x1f) << 16);
997 extract_bat (unsigned long insn
,
998 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1001 if (((insn
>> 21) & 0x1f) != ((insn
>> 16) & 0x1f))
1006 /* The BB field in an XL form instruction when it must be the same as
1007 the BA field in the same instruction. This operand is marked FAKE.
1008 The insertion function just copies the BA field into the BB field,
1009 and the extraction function just checks that the fields are the
1012 static unsigned long
1013 insert_bba (unsigned long insn
,
1014 long value ATTRIBUTE_UNUSED
,
1015 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1016 const char **errmsg ATTRIBUTE_UNUSED
)
1018 return insn
| (((insn
>> 16) & 0x1f) << 11);
1022 extract_bba (unsigned long insn
,
1023 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1026 if (((insn
>> 16) & 0x1f) != ((insn
>> 11) & 0x1f))
1031 /* The BD field in a B form instruction when the - modifier is used.
1032 This modifier means that the branch is not expected to be taken.
1033 For chips built to versions of the architecture prior to version 2
1034 (ie. not Power4 compatible), we set the y bit of the BO field to 1
1035 if the offset is negative. When extracting, we require that the y
1036 bit be 1 and that the offset be positive, since if the y bit is 0
1037 we just want to print the normal form of the instruction.
1038 Power4 compatible targets use two bits, "a", and "t", instead of
1039 the "y" bit. "at" == 00 => no hint, "at" == 01 => unpredictable,
1040 "at" == 10 => not taken, "at" == 11 => taken. The "t" bit is 00001
1041 in BO field, the "a" bit is 00010 for branch on CR(BI) and 01000
1042 for branch on CTR. We only handle the taken/not-taken hint here.
1043 Note that we don't relax the conditions tested here when
1044 disassembling with -Many because insns using extract_bdm and
1045 extract_bdp always occur in pairs. One or the other will always
1048 #define ISA_V2 (PPC_OPCODE_POWER4 | PPC_OPCODE_E500MC | PPC_OPCODE_TITAN)
1050 static unsigned long
1051 insert_bdm (unsigned long insn
,
1054 const char **errmsg ATTRIBUTE_UNUSED
)
1056 if ((dialect
& ISA_V2
) == 0)
1058 if ((value
& 0x8000) != 0)
1063 if ((insn
& (0x14 << 21)) == (0x04 << 21))
1065 else if ((insn
& (0x14 << 21)) == (0x10 << 21))
1068 return insn
| (value
& 0xfffc);
1072 extract_bdm (unsigned long insn
,
1076 if ((dialect
& ISA_V2
) == 0)
1078 if (((insn
& (1 << 21)) == 0) != ((insn
& (1 << 15)) == 0))
1083 if ((insn
& (0x17 << 21)) != (0x06 << 21)
1084 && (insn
& (0x1d << 21)) != (0x18 << 21))
1088 return ((insn
& 0xfffc) ^ 0x8000) - 0x8000;
1091 /* The BD field in a B form instruction when the + modifier is used.
1092 This is like BDM, above, except that the branch is expected to be
1095 static unsigned long
1096 insert_bdp (unsigned long insn
,
1099 const char **errmsg ATTRIBUTE_UNUSED
)
1101 if ((dialect
& ISA_V2
) == 0)
1103 if ((value
& 0x8000) == 0)
1108 if ((insn
& (0x14 << 21)) == (0x04 << 21))
1110 else if ((insn
& (0x14 << 21)) == (0x10 << 21))
1113 return insn
| (value
& 0xfffc);
1117 extract_bdp (unsigned long insn
,
1121 if ((dialect
& ISA_V2
) == 0)
1123 if (((insn
& (1 << 21)) == 0) == ((insn
& (1 << 15)) == 0))
1128 if ((insn
& (0x17 << 21)) != (0x07 << 21)
1129 && (insn
& (0x1d << 21)) != (0x19 << 21))
1133 return ((insn
& 0xfffc) ^ 0x8000) - 0x8000;
1137 valid_bo_pre_v2 (long value
)
1139 /* Certain encodings have bits that are required to be zero.
1140 These are (z must be zero, y may be anything):
1151 if ((value
& 0x14) == 0)
1153 else if ((value
& 0x14) == 0x4)
1154 return (value
& 0x2) == 0;
1155 else if ((value
& 0x14) == 0x10)
1156 return (value
& 0x8) == 0;
1158 return value
== 0x14;
1162 valid_bo_post_v2 (long value
)
1164 /* Certain encodings have bits that are required to be zero.
1165 These are (z must be zero, a & t may be anything):
1176 if ((value
& 0x14) == 0)
1177 return (value
& 0x1) == 0;
1178 else if ((value
& 0x14) == 0x14)
1179 return value
== 0x14;
1184 /* Check for legal values of a BO field. */
1187 valid_bo (long value
, ppc_cpu_t dialect
, int extract
)
1189 int valid_y
= valid_bo_pre_v2 (value
);
1190 int valid_at
= valid_bo_post_v2 (value
);
1192 /* When disassembling with -Many, accept either encoding on the
1193 second pass through opcodes. */
1194 if (extract
&& dialect
== ~(ppc_cpu_t
) PPC_OPCODE_ANY
)
1195 return valid_y
|| valid_at
;
1196 if ((dialect
& ISA_V2
) == 0)
1202 /* The BO field in a B form instruction. Warn about attempts to set
1203 the field to an illegal value. */
1205 static unsigned long
1206 insert_bo (unsigned long insn
,
1209 const char **errmsg
)
1211 if (!valid_bo (value
, dialect
, 0))
1212 *errmsg
= _("invalid conditional option");
1213 else if (PPC_OP (insn
) == 19 && (insn
& 0x400) && ! (value
& 4))
1214 *errmsg
= _("invalid counter access");
1215 return insn
| ((value
& 0x1f) << 21);
1219 extract_bo (unsigned long insn
,
1225 value
= (insn
>> 21) & 0x1f;
1226 if (!valid_bo (value
, dialect
, 1))
1231 /* The BO field in a B form instruction when the + or - modifier is
1232 used. This is like the BO field, but it must be even. When
1233 extracting it, we force it to be even. */
1235 static unsigned long
1236 insert_boe (unsigned long insn
,
1239 const char **errmsg
)
1241 if (!valid_bo (value
, dialect
, 0))
1242 *errmsg
= _("invalid conditional option");
1243 else if (PPC_OP (insn
) == 19 && (insn
& 0x400) && ! (value
& 4))
1244 *errmsg
= _("invalid counter access");
1245 else if ((value
& 1) != 0)
1246 *errmsg
= _("attempt to set y bit when using + or - modifier");
1248 return insn
| ((value
& 0x1f) << 21);
1252 extract_boe (unsigned long insn
,
1258 value
= (insn
>> 21) & 0x1f;
1259 if (!valid_bo (value
, dialect
, 1))
1261 return value
& 0x1e;
1264 /* FXM mask in mfcr and mtcrf instructions. */
1266 static unsigned long
1267 insert_fxm (unsigned long insn
,
1270 const char **errmsg
)
1272 /* If we're handling the mfocrf and mtocrf insns ensure that exactly
1273 one bit of the mask field is set. */
1274 if ((insn
& (1 << 20)) != 0)
1276 if (value
== 0 || (value
& -value
) != value
)
1278 *errmsg
= _("invalid mask field");
1283 /* If the optional field on mfcr is missing that means we want to use
1284 the old form of the instruction that moves the whole cr. In that
1285 case we'll have VALUE zero. There doesn't seem to be a way to
1286 distinguish this from the case where someone writes mfcr %r3,0. */
1287 else if (value
== 0)
1290 /* If only one bit of the FXM field is set, we can use the new form
1291 of the instruction, which is faster. Unlike the Power4 branch hint
1292 encoding, this is not backward compatible. Do not generate the
1293 new form unless -mpower4 has been given, or -many and the two
1294 operand form of mfcr was used. */
1295 else if ((value
& -value
) == value
1296 && ((dialect
& PPC_OPCODE_POWER4
) != 0
1297 || ((dialect
& PPC_OPCODE_ANY
) != 0
1298 && (insn
& (0x3ff << 1)) == 19 << 1)))
1301 /* Any other value on mfcr is an error. */
1302 else if ((insn
& (0x3ff << 1)) == 19 << 1)
1304 *errmsg
= _("ignoring invalid mfcr mask");
1308 return insn
| ((value
& 0xff) << 12);
1312 extract_fxm (unsigned long insn
,
1313 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1316 long mask
= (insn
>> 12) & 0xff;
1318 /* Is this a Power4 insn? */
1319 if ((insn
& (1 << 20)) != 0)
1321 /* Exactly one bit of MASK should be set. */
1322 if (mask
== 0 || (mask
& -mask
) != mask
)
1326 /* Check that non-power4 form of mfcr has a zero MASK. */
1327 else if ((insn
& (0x3ff << 1)) == 19 << 1)
1336 static unsigned long
1337 insert_li20 (unsigned long insn
,
1339 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1340 const char **errmsg ATTRIBUTE_UNUSED
)
1342 return insn
| ((value
& 0xf0000) >> 5) | ((value
& 0x0f800) << 5) | (value
& 0x7ff);
1346 extract_li20 (unsigned long insn
,
1347 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1348 int *invalid ATTRIBUTE_UNUSED
)
1350 long ext
= ((insn
& 0x4000) == 0x4000) ? 0xfff00000 : 0x00000000;
1353 | (((insn
>> 11) & 0xf) << 16)
1354 | (((insn
>> 17) & 0xf) << 12)
1355 | (((insn
>> 16) & 0x1) << 11)
1359 /* The LS field in a sync instruction that accepts 2 operands
1360 Values 2 and 3 are reserved,
1361 must be treated as 0 for future compatibility
1362 Values 0 and 1 can be accepted, if field ESYNC is zero
1363 Otherwise L = complement of ESYNC-bit2 (1<<18) */
1365 static unsigned long
1366 insert_ls (unsigned long insn
,
1368 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1369 const char **errmsg ATTRIBUTE_UNUSED
)
1373 ls
= (insn
>> 21) & 0x03;
1377 return insn
& ~(0x3 << 21);
1380 if ((value
& 0x2) != 0)
1381 return (insn
& ~(0x3 << 21)) | ((value
& 0xf) << 16);
1382 return (insn
& ~(0x3 << 21)) | (0x1 << 21) | ((value
& 0xf) << 16);
1385 /* The MB and ME fields in an M form instruction expressed as a single
1386 operand which is itself a bitmask. The extraction function always
1387 marks it as invalid, since we never want to recognize an
1388 instruction which uses a field of this type. */
1390 static unsigned long
1391 insert_mbe (unsigned long insn
,
1393 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1394 const char **errmsg
)
1396 unsigned long uval
, mask
;
1397 int mb
, me
, mx
, count
, last
;
1403 *errmsg
= _("illegal bitmask");
1409 if ((uval
& 1) != 0)
1415 /* mb: location of last 0->1 transition */
1416 /* me: location of last 1->0 transition */
1417 /* count: # transitions */
1419 for (mx
= 0, mask
= 1L << 31; mx
< 32; ++mx
, mask
>>= 1)
1421 if ((uval
& mask
) && !last
)
1427 else if (!(uval
& mask
) && last
)
1437 if (count
!= 2 && (count
!= 0 || ! last
))
1438 *errmsg
= _("illegal bitmask");
1440 return insn
| (mb
<< 6) | ((me
- 1) << 1);
1444 extract_mbe (unsigned long insn
,
1445 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1454 mb
= (insn
>> 6) & 0x1f;
1455 me
= (insn
>> 1) & 0x1f;
1459 for (i
= mb
; i
<= me
; i
++)
1460 ret
|= 1L << (31 - i
);
1462 else if (mb
== me
+ 1)
1464 else /* (mb > me + 1) */
1467 for (i
= me
+ 1; i
< mb
; i
++)
1468 ret
&= ~(1L << (31 - i
));
1473 /* The MB or ME field in an MD or MDS form instruction. The high bit
1474 is wrapped to the low end. */
1476 static unsigned long
1477 insert_mb6 (unsigned long insn
,
1479 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1480 const char **errmsg ATTRIBUTE_UNUSED
)
1482 return insn
| ((value
& 0x1f) << 6) | (value
& 0x20);
1486 extract_mb6 (unsigned long insn
,
1487 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1488 int *invalid ATTRIBUTE_UNUSED
)
1490 return ((insn
>> 6) & 0x1f) | (insn
& 0x20);
1493 /* The NB field in an X form instruction. The value 32 is stored as
1497 extract_nb (unsigned long insn
,
1498 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1499 int *invalid ATTRIBUTE_UNUSED
)
1503 ret
= (insn
>> 11) & 0x1f;
1509 /* The NB field in an lswi instruction, which has special value
1510 restrictions. The value 32 is stored as 0. */
1512 static unsigned long
1513 insert_nbi (unsigned long insn
,
1515 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1516 const char **errmsg ATTRIBUTE_UNUSED
)
1518 long rtvalue
= (insn
& RT_MASK
) >> 21;
1519 long ravalue
= (insn
& RA_MASK
) >> 16;
1523 if (rtvalue
+ (value
+ 3) / 4 > (rtvalue
> ravalue
? ravalue
+ 32
1525 *errmsg
= _("address register in load range");
1526 return insn
| ((value
& 0x1f) << 11);
1529 /* The NSI field in a D form instruction. This is the same as the SI
1530 field, only negated. The extraction function always marks it as
1531 invalid, since we never want to recognize an instruction which uses
1532 a field of this type. */
1534 static unsigned long
1535 insert_nsi (unsigned long insn
,
1537 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1538 const char **errmsg ATTRIBUTE_UNUSED
)
1540 return insn
| (-value
& 0xffff);
1544 extract_nsi (unsigned long insn
,
1545 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1549 return -(((insn
& 0xffff) ^ 0x8000) - 0x8000);
1552 /* The RA field in a D or X form instruction which is an updating
1553 load, which means that the RA field may not be zero and may not
1554 equal the RT field. */
1556 static unsigned long
1557 insert_ral (unsigned long insn
,
1559 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1560 const char **errmsg
)
1563 || (unsigned long) value
== ((insn
>> 21) & 0x1f))
1564 *errmsg
= "invalid register operand when updating";
1565 return insn
| ((value
& 0x1f) << 16);
1568 /* The RA field in an lmw instruction, which has special value
1571 static unsigned long
1572 insert_ram (unsigned long insn
,
1574 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1575 const char **errmsg
)
1577 if ((unsigned long) value
>= ((insn
>> 21) & 0x1f))
1578 *errmsg
= _("index register in load range");
1579 return insn
| ((value
& 0x1f) << 16);
1582 /* The RA field in the DQ form lq or an lswx instruction, which have special
1583 value restrictions. */
1585 static unsigned long
1586 insert_raq (unsigned long insn
,
1588 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1589 const char **errmsg
)
1591 long rtvalue
= (insn
& RT_MASK
) >> 21;
1593 if (value
== rtvalue
)
1594 *errmsg
= _("source and target register operands must be different");
1595 return insn
| ((value
& 0x1f) << 16);
1598 /* The RA field in a D or X form instruction which is an updating
1599 store or an updating floating point load, which means that the RA
1600 field may not be zero. */
1602 static unsigned long
1603 insert_ras (unsigned long insn
,
1605 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1606 const char **errmsg
)
1609 *errmsg
= _("invalid register operand when updating");
1610 return insn
| ((value
& 0x1f) << 16);
1613 /* The RB field in an X form instruction when it must be the same as
1614 the RS field in the instruction. This is used for extended
1615 mnemonics like mr. This operand is marked FAKE. The insertion
1616 function just copies the BT field into the BA field, and the
1617 extraction function just checks that the fields are the same. */
1619 static unsigned long
1620 insert_rbs (unsigned long insn
,
1621 long value ATTRIBUTE_UNUSED
,
1622 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1623 const char **errmsg ATTRIBUTE_UNUSED
)
1625 return insn
| (((insn
>> 21) & 0x1f) << 11);
1629 extract_rbs (unsigned long insn
,
1630 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1633 if (((insn
>> 21) & 0x1f) != ((insn
>> 11) & 0x1f))
1638 /* The RB field in an lswx instruction, which has special value
1641 static unsigned long
1642 insert_rbx (unsigned long insn
,
1644 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1645 const char **errmsg
)
1647 long rtvalue
= (insn
& RT_MASK
) >> 21;
1649 if (value
== rtvalue
)
1650 *errmsg
= _("source and target register operands must be different");
1651 return insn
| ((value
& 0x1f) << 11);
1654 /* The SCI8 field is made up of SCL and {U,N}I8 fields. */
1655 static unsigned long
1656 insert_sci8 (unsigned long insn
,
1658 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1659 const char **errmsg
)
1661 unsigned int fill_scale
= 0;
1662 unsigned long ui8
= value
;
1664 if ((ui8
& 0xffffff00) == 0)
1666 else if ((ui8
& 0xffffff00) == 0xffffff00)
1668 else if ((ui8
& 0xffff00ff) == 0)
1670 fill_scale
= 1 << 8;
1673 else if ((ui8
& 0xffff00ff) == 0xffff00ff)
1675 fill_scale
= 0x400 | (1 << 8);
1678 else if ((ui8
& 0xff00ffff) == 0)
1680 fill_scale
= 2 << 8;
1683 else if ((ui8
& 0xff00ffff) == 0xff00ffff)
1685 fill_scale
= 0x400 | (2 << 8);
1688 else if ((ui8
& 0x00ffffff) == 0)
1690 fill_scale
= 3 << 8;
1693 else if ((ui8
& 0x00ffffff) == 0x00ffffff)
1695 fill_scale
= 0x400 | (3 << 8);
1700 *errmsg
= _("illegal immediate value");
1704 return insn
| fill_scale
| (ui8
& 0xff);
1708 extract_sci8 (unsigned long insn
,
1709 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1710 int *invalid ATTRIBUTE_UNUSED
)
1712 int fill
= insn
& 0x400;
1713 int scale_factor
= (insn
& 0x300) >> 5;
1714 long value
= (insn
& 0xff) << scale_factor
;
1717 value
|= ~((long) 0xff << scale_factor
);
1721 static unsigned long
1722 insert_sci8n (unsigned long insn
,
1725 const char **errmsg
)
1727 return insert_sci8 (insn
, -value
, dialect
, errmsg
);
1731 extract_sci8n (unsigned long insn
,
1735 return -extract_sci8 (insn
, dialect
, invalid
);
1738 static unsigned long
1739 insert_sd4h (unsigned long insn
,
1741 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1742 const char **errmsg ATTRIBUTE_UNUSED
)
1744 return insn
| ((value
& 0x1e) << 7);
1748 extract_sd4h (unsigned long insn
,
1749 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1750 int *invalid ATTRIBUTE_UNUSED
)
1752 return ((insn
>> 8) & 0xf) << 1;
1755 static unsigned long
1756 insert_sd4w (unsigned long insn
,
1758 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1759 const char **errmsg ATTRIBUTE_UNUSED
)
1761 return insn
| ((value
& 0x3c) << 6);
1765 extract_sd4w (unsigned long insn
,
1766 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1767 int *invalid ATTRIBUTE_UNUSED
)
1769 return ((insn
>> 8) & 0xf) << 2;
1772 static unsigned long
1773 insert_oimm (unsigned long insn
,
1775 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1776 const char **errmsg ATTRIBUTE_UNUSED
)
1778 return insn
| (((value
- 1) & 0x1f) << 4);
1782 extract_oimm (unsigned long insn
,
1783 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1784 int *invalid ATTRIBUTE_UNUSED
)
1786 return ((insn
>> 4) & 0x1f) + 1;
1789 /* The SH field in an MD form instruction. This is split. */
1791 static unsigned long
1792 insert_sh6 (unsigned long insn
,
1794 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1795 const char **errmsg ATTRIBUTE_UNUSED
)
1797 return insn
| ((value
& 0x1f) << 11) | ((value
& 0x20) >> 4);
1801 extract_sh6 (unsigned long insn
,
1802 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1803 int *invalid ATTRIBUTE_UNUSED
)
1805 return ((insn
>> 11) & 0x1f) | ((insn
<< 4) & 0x20);
1808 /* The SPR field in an XFX form instruction. This is flipped--the
1809 lower 5 bits are stored in the upper 5 and vice- versa. */
1811 static unsigned long
1812 insert_spr (unsigned long insn
,
1814 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1815 const char **errmsg ATTRIBUTE_UNUSED
)
1817 return insn
| ((value
& 0x1f) << 16) | ((value
& 0x3e0) << 6);
1821 extract_spr (unsigned long insn
,
1822 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1823 int *invalid ATTRIBUTE_UNUSED
)
1825 return ((insn
>> 16) & 0x1f) | ((insn
>> 6) & 0x3e0);
1828 /* Some dialects have 8 SPRG registers instead of the standard 4. */
1829 #define ALLOW8_SPRG (PPC_OPCODE_BOOKE | PPC_OPCODE_405 | PPC_OPCODE_VLE)
1831 static unsigned long
1832 insert_sprg (unsigned long insn
,
1835 const char **errmsg
)
1838 || (value
> 3 && (dialect
& ALLOW8_SPRG
) == 0))
1839 *errmsg
= _("invalid sprg number");
1841 /* If this is mfsprg4..7 then use spr 260..263 which can be read in
1842 user mode. Anything else must use spr 272..279. */
1843 if (value
<= 3 || (insn
& 0x100) != 0)
1846 return insn
| ((value
& 0x17) << 16);
1850 extract_sprg (unsigned long insn
,
1854 unsigned long val
= (insn
>> 16) & 0x1f;
1856 /* mfsprg can use 260..263 and 272..279. mtsprg only uses spr 272..279
1857 If not BOOKE, 405 or VLE, then both use only 272..275. */
1858 if ((val
- 0x10 > 3 && (dialect
& ALLOW8_SPRG
) == 0)
1859 || (val
- 0x10 > 7 && (insn
& 0x100) != 0)
1866 /* The TBR field in an XFX instruction. This is just like SPR, but it
1867 is optional. When TBR is omitted, it must be inserted as 268 (the
1868 magic number of the TB register). These functions treat 0
1869 (indicating an omitted optional operand) as 268. This means that
1870 ``mftb 4,0'' is not handled correctly. This does not matter very
1871 much, since the architecture manual does not define mftb as
1872 accepting any values other than 268 or 269. */
1876 static unsigned long
1877 insert_tbr (unsigned long insn
,
1879 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1880 const char **errmsg ATTRIBUTE_UNUSED
)
1884 return insn
| ((value
& 0x1f) << 16) | ((value
& 0x3e0) << 6);
1888 extract_tbr (unsigned long insn
,
1889 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1890 int *invalid ATTRIBUTE_UNUSED
)
1894 ret
= ((insn
>> 16) & 0x1f) | ((insn
>> 6) & 0x3e0);
1900 /* The XT and XS fields in an XX1 or XX3 form instruction. This is split. */
1902 static unsigned long
1903 insert_xt6 (unsigned long insn
,
1905 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1906 const char **errmsg ATTRIBUTE_UNUSED
)
1908 return insn
| ((value
& 0x1f) << 21) | ((value
& 0x20) >> 5);
1912 extract_xt6 (unsigned long insn
,
1913 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1914 int *invalid ATTRIBUTE_UNUSED
)
1916 return ((insn
<< 5) & 0x20) | ((insn
>> 21) & 0x1f);
1919 /* The XA field in an XX3 form instruction. This is split. */
1921 static unsigned long
1922 insert_xa6 (unsigned long insn
,
1924 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1925 const char **errmsg ATTRIBUTE_UNUSED
)
1927 return insn
| ((value
& 0x1f) << 16) | ((value
& 0x20) >> 3);
1931 extract_xa6 (unsigned long insn
,
1932 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1933 int *invalid ATTRIBUTE_UNUSED
)
1935 return ((insn
<< 3) & 0x20) | ((insn
>> 16) & 0x1f);
1938 /* The XB field in an XX3 form instruction. This is split. */
1940 static unsigned long
1941 insert_xb6 (unsigned long insn
,
1943 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1944 const char **errmsg ATTRIBUTE_UNUSED
)
1946 return insn
| ((value
& 0x1f) << 11) | ((value
& 0x20) >> 4);
1950 extract_xb6 (unsigned long insn
,
1951 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1952 int *invalid ATTRIBUTE_UNUSED
)
1954 return ((insn
<< 4) & 0x20) | ((insn
>> 11) & 0x1f);
1957 /* The XB field in an XX3 form instruction when it must be the same as
1958 the XA field in the instruction. This is used for extended
1959 mnemonics like xvmovdp. This operand is marked FAKE. The insertion
1960 function just copies the XA field into the XB field, and the
1961 extraction function just checks that the fields are the same. */
1963 static unsigned long
1964 insert_xb6s (unsigned long insn
,
1965 long value ATTRIBUTE_UNUSED
,
1966 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1967 const char **errmsg ATTRIBUTE_UNUSED
)
1969 return insn
| (((insn
>> 16) & 0x1f) << 11) | (((insn
>> 2) & 0x1) << 1);
1973 extract_xb6s (unsigned long insn
,
1974 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1977 if ((((insn
>> 16) & 0x1f) != ((insn
>> 11) & 0x1f))
1978 || (((insn
>> 2) & 0x1) != ((insn
>> 1) & 0x1)))
1983 /* The XC field in an XX4 form instruction. This is split. */
1985 static unsigned long
1986 insert_xc6 (unsigned long insn
,
1988 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1989 const char **errmsg ATTRIBUTE_UNUSED
)
1991 return insn
| ((value
& 0x1f) << 6) | ((value
& 0x20) >> 2);
1995 extract_xc6 (unsigned long insn
,
1996 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1997 int *invalid ATTRIBUTE_UNUSED
)
1999 return ((insn
<< 2) & 0x20) | ((insn
>> 6) & 0x1f);
2002 static unsigned long
2003 insert_dm (unsigned long insn
,
2005 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
2006 const char **errmsg
)
2008 if (value
!= 0 && value
!= 1)
2009 *errmsg
= _("invalid constant");
2010 return insn
| (((value
) ? 3 : 0) << 8);
2014 extract_dm (unsigned long insn
,
2015 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
2020 value
= (insn
>> 8) & 3;
2021 if (value
!= 0 && value
!= 3)
2023 return (value
) ? 1 : 0;
2025 /* The VLESIMM field in an I16A form instruction. This is split. */
2027 static unsigned long
2028 insert_vlesi (unsigned long insn
,
2030 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
2031 const char **errmsg ATTRIBUTE_UNUSED
)
2033 return insn
| ((value
& 0xf800) << 10) | (value
& 0x7ff);
2037 extract_vlesi (unsigned long insn
,
2038 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
2039 int *invalid ATTRIBUTE_UNUSED
)
2041 long value
= ((insn
>> 10) & 0xf800) | (insn
& 0x7ff);
2042 value
= (value
^ 0x8000) - 0x8000;
2046 static unsigned long
2047 insert_vlensi (unsigned long insn
,
2049 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
2050 const char **errmsg ATTRIBUTE_UNUSED
)
2053 return insn
| ((value
& 0xf800) << 10) | (value
& 0x7ff);
2056 extract_vlensi (unsigned long insn
,
2057 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
2058 int *invalid ATTRIBUTE_UNUSED
)
2060 long value
= ((insn
>> 10) & 0xf800) | (insn
& 0x7ff);
2061 value
= (value
^ 0x8000) - 0x8000;
2062 /* Don't use for disassembly. */
2067 /* The VLEUIMM field in an I16A form instruction. This is split. */
2069 static unsigned long
2070 insert_vleui (unsigned long insn
,
2072 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
2073 const char **errmsg ATTRIBUTE_UNUSED
)
2075 return insn
| ((value
& 0xf800) << 10) | (value
& 0x7ff);
2079 extract_vleui (unsigned long insn
,
2080 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
2081 int *invalid ATTRIBUTE_UNUSED
)
2083 return ((insn
>> 10) & 0xf800) | (insn
& 0x7ff);
2086 /* The VLEUIMML field in an I16L form instruction. This is split. */
2088 static unsigned long
2089 insert_vleil (unsigned long insn
,
2091 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
2092 const char **errmsg ATTRIBUTE_UNUSED
)
2094 return insn
| ((value
& 0xf800) << 5) | (value
& 0x7ff);
2098 extract_vleil (unsigned long insn
,
2099 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
2100 int *invalid ATTRIBUTE_UNUSED
)
2102 return ((insn
>> 5) & 0xf800) | (insn
& 0x7ff);
2106 /* Macros used to form opcodes. */
2108 /* The main opcode. */
2109 #define OP(x) ((((unsigned long)(x)) & 0x3f) << 26)
2110 #define OP_MASK OP (0x3f)
2112 /* The main opcode combined with a trap code in the TO field of a D
2113 form instruction. Used for extended mnemonics for the trap
2115 #define OPTO(x,to) (OP (x) | ((((unsigned long)(to)) & 0x1f) << 21))
2116 #define OPTO_MASK (OP_MASK | TO_MASK)
2118 /* The main opcode combined with a comparison size bit in the L field
2119 of a D form or X form instruction. Used for extended mnemonics for
2120 the comparison instructions. */
2121 #define OPL(x,l) (OP (x) | ((((unsigned long)(l)) & 1) << 21))
2122 #define OPL_MASK OPL (0x3f,1)
2124 /* The main opcode combined with an update code in D form instruction.
2125 Used for extended mnemonics for VLE memory instructions. */
2126 #define OPVUP(x,vup) (OP (x) | ((((unsigned long)(vup)) & 0xff) << 8))
2127 #define OPVUP_MASK OPVUP (0x3f, 0xff)
2129 /* An A form instruction. */
2130 #define A(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0x1f) << 1) | (((unsigned long)(rc)) & 1))
2131 #define A_MASK A (0x3f, 0x1f, 1)
2133 /* An A_MASK with the FRB field fixed. */
2134 #define AFRB_MASK (A_MASK | FRB_MASK)
2136 /* An A_MASK with the FRC field fixed. */
2137 #define AFRC_MASK (A_MASK | FRC_MASK)
2139 /* An A_MASK with the FRA and FRC fields fixed. */
2140 #define AFRAFRC_MASK (A_MASK | FRA_MASK | FRC_MASK)
2142 /* An AFRAFRC_MASK, but with L bit clear. */
2143 #define AFRALFRC_MASK (AFRAFRC_MASK & ~((unsigned long) 1 << 16))
2145 /* A B form instruction. */
2146 #define B(op, aa, lk) (OP (op) | ((((unsigned long)(aa)) & 1) << 1) | ((lk) & 1))
2147 #define B_MASK B (0x3f, 1, 1)
2149 /* A BD8 form instruction. This is a 16-bit instruction. */
2150 #define BD8(op, aa, lk) (((((unsigned long)(op)) & 0x3f) << 10) | (((aa) & 1) << 9) | (((lk) & 1) << 8))
2151 #define BD8_MASK BD8 (0x3f, 1, 1)
2153 /* Another BD8 form instruction. This is a 16-bit instruction. */
2154 #define BD8IO(op) ((((unsigned long)(op)) & 0x1f) << 11)
2155 #define BD8IO_MASK BD8IO (0x1f)
2157 /* A BD8 form instruction for simplified mnemonics. */
2158 #define EBD8IO(op, bo, bi) (BD8IO ((op)) | ((bo) << 10) | ((bi) << 8))
2159 /* A mask that excludes BO32 and BI32. */
2160 #define EBD8IO1_MASK 0xf800
2161 /* A mask that includes BO32 and excludes BI32. */
2162 #define EBD8IO2_MASK 0xfc00
2163 /* A mask that include BO32 AND BI32. */
2164 #define EBD8IO3_MASK 0xff00
2166 /* A BD15 form instruction. */
2167 #define BD15(op, aa, lk) (OP (op) | ((((unsigned long)(aa)) & 0xf) << 22) | ((lk) & 1))
2168 #define BD15_MASK BD15 (0x3f, 0xf, 1)
2170 /* A BD15 form instruction for extended conditional branch mnemonics. */
2171 #define EBD15(op, aa, bo, lk) (((op) & 0x3f) << 26) | (((aa) & 0xf) << 22) | (((bo) & 0x3) << 20) | ((lk) & 1)
2172 #define EBD15_MASK 0xfff00001
2174 /* A BD15 form instruction for extended conditional branch mnemonics with BI. */
2175 #define EBD15BI(op, aa, bo, bi, lk) (((op) & 0x3f) << 26) \
2176 | (((aa) & 0xf) << 22) \
2177 | (((bo) & 0x3) << 20) \
2178 | (((bi) & 0x3) << 16) \
2180 #define EBD15BI_MASK 0xfff30001
2182 /* A BD24 form instruction. */
2183 #define BD24(op, aa, lk) (OP (op) | ((((unsigned long)(aa)) & 1) << 25) | ((lk) & 1))
2184 #define BD24_MASK BD24 (0x3f, 1, 1)
2186 /* A B form instruction setting the BO field. */
2187 #define BBO(op, bo, aa, lk) (B ((op), (aa), (lk)) | ((((unsigned long)(bo)) & 0x1f) << 21))
2188 #define BBO_MASK BBO (0x3f, 0x1f, 1, 1)
2190 /* A BBO_MASK with the y bit of the BO field removed. This permits
2191 matching a conditional branch regardless of the setting of the y
2192 bit. Similarly for the 'at' bits used for power4 branch hints. */
2193 #define Y_MASK (((unsigned long) 1) << 21)
2194 #define AT1_MASK (((unsigned long) 3) << 21)
2195 #define AT2_MASK (((unsigned long) 9) << 21)
2196 #define BBOY_MASK (BBO_MASK &~ Y_MASK)
2197 #define BBOAT_MASK (BBO_MASK &~ AT1_MASK)
2199 /* A B form instruction setting the BO field and the condition bits of
2201 #define BBOCB(op, bo, cb, aa, lk) \
2202 (BBO ((op), (bo), (aa), (lk)) | ((((unsigned long)(cb)) & 0x3) << 16))
2203 #define BBOCB_MASK BBOCB (0x3f, 0x1f, 0x3, 1, 1)
2205 /* A BBOCB_MASK with the y bit of the BO field removed. */
2206 #define BBOYCB_MASK (BBOCB_MASK &~ Y_MASK)
2207 #define BBOATCB_MASK (BBOCB_MASK &~ AT1_MASK)
2208 #define BBOAT2CB_MASK (BBOCB_MASK &~ AT2_MASK)
2210 /* A BBOYCB_MASK in which the BI field is fixed. */
2211 #define BBOYBI_MASK (BBOYCB_MASK | BI_MASK)
2212 #define BBOATBI_MASK (BBOAT2CB_MASK | BI_MASK)
2214 /* A VLE C form instruction. */
2215 #define C_LK(x, lk) (((((unsigned long)(x)) & 0x7fff) << 1) | ((lk) & 1))
2216 #define C_LK_MASK C_LK(0x7fff, 1)
2217 #define C(x) ((((unsigned long)(x)) & 0xffff))
2218 #define C_MASK C(0xffff)
2220 /* An Context form instruction. */
2221 #define CTX(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x7))
2222 #define CTX_MASK CTX(0x3f, 0x7)
2224 /* An User Context form instruction. */
2225 #define UCTX(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x1f))
2226 #define UCTX_MASK UCTX(0x3f, 0x1f)
2228 /* The main opcode mask with the RA field clear. */
2229 #define DRA_MASK (OP_MASK | RA_MASK)
2231 /* A DS form instruction. */
2232 #define DSO(op, xop) (OP (op) | ((xop) & 0x3))
2233 #define DS_MASK DSO (0x3f, 3)
2235 /* An EVSEL form instruction. */
2236 #define EVSEL(op, xop) (OP (op) | (((unsigned long)(xop)) & 0xff) << 3)
2237 #define EVSEL_MASK EVSEL(0x3f, 0xff)
2239 /* An IA16 form instruction. */
2240 #define IA16(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x1f) << 11)
2241 #define IA16_MASK IA16(0x3f, 0x1f)
2243 /* An I16A form instruction. */
2244 #define I16A(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x1f) << 11)
2245 #define I16A_MASK I16A(0x3f, 0x1f)
2247 /* An I16L form instruction. */
2248 #define I16L(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x1f) << 11)
2249 #define I16L_MASK I16L(0x3f, 0x1f)
2251 /* An IM7 form instruction. */
2252 #define IM7(op) ((((unsigned long)(op)) & 0x1f) << 11)
2253 #define IM7_MASK IM7(0x1f)
2255 /* An M form instruction. */
2256 #define M(op, rc) (OP (op) | ((rc) & 1))
2257 #define M_MASK M (0x3f, 1)
2259 /* An LI20 form instruction. */
2260 #define LI20(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x1) << 15)
2261 #define LI20_MASK LI20(0x3f, 0x1)
2263 /* An M form instruction with the ME field specified. */
2264 #define MME(op, me, rc) (M ((op), (rc)) | ((((unsigned long)(me)) & 0x1f) << 1))
2266 /* An M_MASK with the MB and ME fields fixed. */
2267 #define MMBME_MASK (M_MASK | MB_MASK | ME_MASK)
2269 /* An M_MASK with the SH and ME fields fixed. */
2270 #define MSHME_MASK (M_MASK | SH_MASK | ME_MASK)
2272 /* An MD form instruction. */
2273 #define MD(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0x7) << 2) | ((rc) & 1))
2274 #define MD_MASK MD (0x3f, 0x7, 1)
2276 /* An MD_MASK with the MB field fixed. */
2277 #define MDMB_MASK (MD_MASK | MB6_MASK)
2279 /* An MD_MASK with the SH field fixed. */
2280 #define MDSH_MASK (MD_MASK | SH6_MASK)
2282 /* An MDS form instruction. */
2283 #define MDS(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0xf) << 1) | ((rc) & 1))
2284 #define MDS_MASK MDS (0x3f, 0xf, 1)
2286 /* An MDS_MASK with the MB field fixed. */
2287 #define MDSMB_MASK (MDS_MASK | MB6_MASK)
2289 /* An SC form instruction. */
2290 #define SC(op, sa, lk) (OP (op) | ((((unsigned long)(sa)) & 1) << 1) | ((lk) & 1))
2291 #define SC_MASK (OP_MASK | (((unsigned long)0x3ff) << 16) | (((unsigned long)1) << 1) | 1)
2293 /* An SCI8 form instruction. */
2294 #define SCI8(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x1f) << 11))
2295 #define SCI8_MASK SCI8(0x3f, 0x1f)
2297 /* An SCI8 form instruction. */
2298 #define SCI8BF(op, fop, xop) (OP (op) | ((((unsigned long)(xop)) & 0x1f) << 11) | (((fop) & 7) << 23))
2299 #define SCI8BF_MASK SCI8BF(0x3f, 7, 0x1f)
2301 /* An SD4 form instruction. This is a 16-bit instruction. */
2302 #define SD4(op) ((((unsigned long)(op)) & 0xf) << 12)
2303 #define SD4_MASK SD4(0xf)
2305 /* An SE_IM5 form instruction. This is a 16-bit instruction. */
2306 #define SE_IM5(op, xop) (((((unsigned long)(op)) & 0x3f) << 10) | (((xop) & 0x1) << 9))
2307 #define SE_IM5_MASK SE_IM5(0x3f, 1)
2309 /* An SE_R form instruction. This is a 16-bit instruction. */
2310 #define SE_R(op, xop) (((((unsigned long)(op)) & 0x3f) << 10) | (((xop) & 0x3f) << 4))
2311 #define SE_R_MASK SE_R(0x3f, 0x3f)
2313 /* An SE_RR form instruction. This is a 16-bit instruction. */
2314 #define SE_RR(op, xop) (((((unsigned long)(op)) & 0x3f) << 10) | (((xop) & 0x3) << 8))
2315 #define SE_RR_MASK SE_RR(0x3f, 3)
2317 /* A VX form instruction. */
2318 #define VX(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x7ff))
2320 /* The mask for an VX form instruction. */
2321 #define VX_MASK VX(0x3f, 0x7ff)
2323 /* A VX_MASK with the VA field fixed. */
2324 #define VXVA_MASK (VX_MASK | (0x1f << 16))
2326 /* A VX_MASK with the VB field fixed. */
2327 #define VXVB_MASK (VX_MASK | (0x1f << 11))
2329 /* A VX_MASK with the VA and VB fields fixed. */
2330 #define VXVAVB_MASK (VX_MASK | (0x1f << 16) | (0x1f << 11))
2332 /* A VX_MASK with the VD and VA fields fixed. */
2333 #define VXVDVA_MASK (VX_MASK | (0x1f << 21) | (0x1f << 16))
2335 /* A VX_MASK with a UIMM4 field. */
2336 #define VXUIMM4_MASK (VX_MASK | (0x1 << 20))
2338 /* A VX_MASK with a UIMM3 field. */
2339 #define VXUIMM3_MASK (VX_MASK | (0x3 << 19))
2341 /* A VX_MASK with a UIMM2 field. */
2342 #define VXUIMM2_MASK (VX_MASK | (0x7 << 18))
2344 /* A VX_MASK with a PS field. */
2345 #define VXPS_MASK (VX_MASK & ~(0x1 << 9))
2347 /* A VA form instruction. */
2348 #define VXA(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x03f))
2350 /* The mask for an VA form instruction. */
2351 #define VXA_MASK VXA(0x3f, 0x3f)
2353 /* A VXA_MASK with a SHB field. */
2354 #define VXASHB_MASK (VXA_MASK | (1 << 10))
2356 /* A VXR form instruction. */
2357 #define VXR(op, xop, rc) (OP (op) | (((rc) & 1) << 10) | (((unsigned long)(xop)) & 0x3ff))
2359 /* The mask for a VXR form instruction. */
2360 #define VXR_MASK VXR(0x3f, 0x3ff, 1)
2362 /* An X form instruction. */
2363 #define X(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x3ff) << 1))
2365 /* An EX form instruction. */
2366 #define EX(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x7ff))
2368 /* The mask for an EX form instruction. */
2369 #define EX_MASK EX (0x3f, 0x7ff)
2371 /* An XX2 form instruction. */
2372 #define XX2(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x1ff) << 2))
2374 /* An XX3 form instruction. */
2375 #define XX3(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0xff) << 3))
2377 /* An XX3 form instruction with the RC bit specified. */
2378 #define XX3RC(op, xop, rc) (OP (op) | (((rc) & 1) << 10) | ((((unsigned long)(xop)) & 0x7f) << 3))
2380 /* An XX4 form instruction. */
2381 #define XX4(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x3) << 4))
2383 /* A Z form instruction. */
2384 #define Z(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x1ff) << 1))
2386 /* An X form instruction with the RC bit specified. */
2387 #define XRC(op, xop, rc) (X ((op), (xop)) | ((rc) & 1))
2389 /* A Z form instruction with the RC bit specified. */
2390 #define ZRC(op, xop, rc) (Z ((op), (xop)) | ((rc) & 1))
2392 /* The mask for an X form instruction. */
2393 #define X_MASK XRC (0x3f, 0x3ff, 1)
2395 /* An X form wait instruction with everything filled in except the WC field. */
2396 #define XWC_MASK (XRC (0x3f, 0x3ff, 1) | (7 << 23) | RA_MASK | RB_MASK)
2398 /* The mask for an XX1 form instruction. */
2399 #define XX1_MASK X (0x3f, 0x3ff)
2401 /* An XX1_MASK with the RB field fixed. */
2402 #define XX1RB_MASK (XX1_MASK | RB_MASK)
2404 /* The mask for an XX2 form instruction. */
2405 #define XX2_MASK (XX2 (0x3f, 0x1ff) | (0x1f << 16))
2407 /* The mask for an XX2 form instruction with the UIM bits specified. */
2408 #define XX2UIM_MASK (XX2 (0x3f, 0x1ff) | (7 << 18))
2410 /* The mask for an XX2 form instruction with the BF bits specified. */
2411 #define XX2BF_MASK (XX2_MASK | (3 << 21) | (1))
2413 /* The mask for an XX3 form instruction. */
2414 #define XX3_MASK XX3 (0x3f, 0xff)
2416 /* The mask for an XX3 form instruction with the BF bits specified. */
2417 #define XX3BF_MASK (XX3 (0x3f, 0xff) | (3 << 21) | (1))
2419 /* The mask for an XX3 form instruction with the DM or SHW bits specified. */
2420 #define XX3DM_MASK (XX3 (0x3f, 0x1f) | (1 << 10))
2421 #define XX3SHW_MASK XX3DM_MASK
2423 /* The mask for an XX4 form instruction. */
2424 #define XX4_MASK XX4 (0x3f, 0x3)
2426 /* An X form wait instruction with everything filled in except the WC field. */
2427 #define XWC_MASK (XRC (0x3f, 0x3ff, 1) | (7 << 23) | RA_MASK | RB_MASK)
2429 /* The mask for a Z form instruction. */
2430 #define Z_MASK ZRC (0x3f, 0x1ff, 1)
2431 #define Z2_MASK ZRC (0x3f, 0xff, 1)
2433 /* An X_MASK with the RA field fixed. */
2434 #define XRA_MASK (X_MASK | RA_MASK)
2436 /* An XRA_MASK with the W field clear. */
2437 #define XWRA_MASK (XRA_MASK & ~((unsigned long) 1 << 16))
2439 /* An X_MASK with the RB field fixed. */
2440 #define XRB_MASK (X_MASK | RB_MASK)
2442 /* An X_MASK with the RT field fixed. */
2443 #define XRT_MASK (X_MASK | RT_MASK)
2445 /* An XRT_MASK mask with the L bits clear. */
2446 #define XLRT_MASK (XRT_MASK & ~((unsigned long) 0x3 << 21))
2448 /* An X_MASK with the RA and RB fields fixed. */
2449 #define XRARB_MASK (X_MASK | RA_MASK | RB_MASK)
2451 /* An XRARB_MASK, but with the L bit clear. */
2452 #define XRLARB_MASK (XRARB_MASK & ~((unsigned long) 1 << 16))
2454 /* An X_MASK with the RT and RA fields fixed. */
2455 #define XRTRA_MASK (X_MASK | RT_MASK | RA_MASK)
2457 /* An X_MASK with the RT and RB fields fixed. */
2458 #define XRTRB_MASK (X_MASK | RT_MASK | RB_MASK)
2460 /* An XRTRA_MASK, but with L bit clear. */
2461 #define XRTLRA_MASK (XRTRA_MASK & ~((unsigned long) 1 << 21))
2463 /* An X_MASK with the RT, RA and RB fields fixed. */
2464 #define XRTRARB_MASK (X_MASK | RT_MASK | RA_MASK | RB_MASK)
2466 /* An XRTRARB_MASK, but with L bit clear. */
2467 #define XRTLRARB_MASK (XRTRARB_MASK & ~((unsigned long) 1 << 21))
2469 /* An XRTRARB_MASK, but with A bit clear. */
2470 #define XRTARARB_MASK (XRTRARB_MASK & ~((unsigned long) 1 << 25))
2472 /* An XRTRARB_MASK, but with BF bits clear. */
2473 #define XRTBFRARB_MASK (XRTRARB_MASK & ~((unsigned long) 7 << 23))
2475 /* An X form instruction with the L bit specified. */
2476 #define XOPL(op, xop, l) (X ((op), (xop)) | ((((unsigned long)(l)) & 1) << 21))
2478 /* An X form instruction with the L bits specified. */
2479 #define XOPL2(op, xop, l) (X ((op), (xop)) | ((((unsigned long)(l)) & 3) << 21))
2481 /* An X form instruction with the L bit and RC bit specified. */
2482 #define XRCL(op, xop, l, rc) (XRC ((op), (xop), (rc)) | ((((unsigned long)(l)) & 1) << 21))
2484 /* An X form instruction with RT fields specified */
2485 #define XRT(op, xop, rt) (X ((op), (xop)) \
2486 | ((((unsigned long)(rt)) & 0x1f) << 21))
2488 /* An X form instruction with RT and RA fields specified */
2489 #define XRTRA(op, xop, rt, ra) (X ((op), (xop)) \
2490 | ((((unsigned long)(rt)) & 0x1f) << 21) \
2491 | ((((unsigned long)(ra)) & 0x1f) << 16))
2493 /* The mask for an X form comparison instruction. */
2494 #define XCMP_MASK (X_MASK | (((unsigned long)1) << 22))
2496 /* The mask for an X form comparison instruction with the L field
2498 #define XCMPL_MASK (XCMP_MASK | (((unsigned long)1) << 21))
2500 /* An X form trap instruction with the TO field specified. */
2501 #define XTO(op, xop, to) (X ((op), (xop)) | ((((unsigned long)(to)) & 0x1f) << 21))
2502 #define XTO_MASK (X_MASK | TO_MASK)
2504 /* An X form tlb instruction with the SH field specified. */
2505 #define XTLB(op, xop, sh) (X ((op), (xop)) | ((((unsigned long)(sh)) & 0x1f) << 11))
2506 #define XTLB_MASK (X_MASK | SH_MASK)
2508 /* An X form sync instruction. */
2509 #define XSYNC(op, xop, l) (X ((op), (xop)) | ((((unsigned long)(l)) & 3) << 21))
2511 /* An X form sync instruction with everything filled in except the LS field. */
2512 #define XSYNC_MASK (0xff9fffff)
2514 /* An X form sync instruction with everything filled in except the L and E fields. */
2515 #define XSYNCLE_MASK (0xff90ffff)
2517 /* An X_MASK, but with the EH bit clear. */
2518 #define XEH_MASK (X_MASK & ~((unsigned long )1))
2520 /* An X form AltiVec dss instruction. */
2521 #define XDSS(op, xop, a) (X ((op), (xop)) | ((((unsigned long)(a)) & 1) << 25))
2522 #define XDSS_MASK XDSS(0x3f, 0x3ff, 1)
2524 /* An XFL form instruction. */
2525 #define XFL(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0x3ff) << 1) | (((unsigned long)(rc)) & 1))
2526 #define XFL_MASK XFL (0x3f, 0x3ff, 1)
2528 /* An X form isel instruction. */
2529 #define XISEL(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x1f) << 1))
2530 #define XISEL_MASK XISEL(0x3f, 0x1f)
2532 /* An XL form instruction with the LK field set to 0. */
2533 #define XL(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x3ff) << 1))
2535 /* An XL form instruction which uses the LK field. */
2536 #define XLLK(op, xop, lk) (XL ((op), (xop)) | ((lk) & 1))
2538 /* The mask for an XL form instruction. */
2539 #define XL_MASK XLLK (0x3f, 0x3ff, 1)
2541 /* An XL_MASK with the RT, RA and RB fields fixed, but S bit clear. */
2542 #define XLS_MASK ((XL_MASK | RT_MASK | RA_MASK | RB_MASK) & ~(1 << 11))
2544 /* An XL form instruction which explicitly sets the BO field. */
2545 #define XLO(op, bo, xop, lk) \
2546 (XLLK ((op), (xop), (lk)) | ((((unsigned long)(bo)) & 0x1f) << 21))
2547 #define XLO_MASK (XL_MASK | BO_MASK)
2549 /* An XL form instruction which explicitly sets the y bit of the BO
2551 #define XLYLK(op, xop, y, lk) (XLLK ((op), (xop), (lk)) | ((((unsigned long)(y)) & 1) << 21))
2552 #define XLYLK_MASK (XL_MASK | Y_MASK)
2554 /* An XL form instruction which sets the BO field and the condition
2555 bits of the BI field. */
2556 #define XLOCB(op, bo, cb, xop, lk) \
2557 (XLO ((op), (bo), (xop), (lk)) | ((((unsigned long)(cb)) & 3) << 16))
2558 #define XLOCB_MASK XLOCB (0x3f, 0x1f, 0x3, 0x3ff, 1)
2560 /* An XL_MASK or XLYLK_MASK or XLOCB_MASK with the BB field fixed. */
2561 #define XLBB_MASK (XL_MASK | BB_MASK)
2562 #define XLYBB_MASK (XLYLK_MASK | BB_MASK)
2563 #define XLBOCBBB_MASK (XLOCB_MASK | BB_MASK)
2565 /* A mask for branch instructions using the BH field. */
2566 #define XLBH_MASK (XL_MASK | (0x1c << 11))
2568 /* An XL_MASK with the BO and BB fields fixed. */
2569 #define XLBOBB_MASK (XL_MASK | BO_MASK | BB_MASK)
2571 /* An XL_MASK with the BO, BI and BB fields fixed. */
2572 #define XLBOBIBB_MASK (XL_MASK | BO_MASK | BI_MASK | BB_MASK)
2574 /* An X form mbar instruction with MO field. */
2575 #define XMBAR(op, xop, mo) (X ((op), (xop)) | ((((unsigned long)(mo)) & 1) << 21))
2577 /* An XO form instruction. */
2578 #define XO(op, xop, oe, rc) \
2579 (OP (op) | ((((unsigned long)(xop)) & 0x1ff) << 1) | ((((unsigned long)(oe)) & 1) << 10) | (((unsigned long)(rc)) & 1))
2580 #define XO_MASK XO (0x3f, 0x1ff, 1, 1)
2582 /* An XO_MASK with the RB field fixed. */
2583 #define XORB_MASK (XO_MASK | RB_MASK)
2585 /* An XOPS form instruction for paired singles. */
2586 #define XOPS(op, xop, rc) \
2587 (OP (op) | ((((unsigned long)(xop)) & 0x3ff) << 1) | (((unsigned long)(rc)) & 1))
2588 #define XOPS_MASK XOPS (0x3f, 0x3ff, 1)
2591 /* An XS form instruction. */
2592 #define XS(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0x1ff) << 2) | (((unsigned long)(rc)) & 1))
2593 #define XS_MASK XS (0x3f, 0x1ff, 1)
2595 /* A mask for the FXM version of an XFX form instruction. */
2596 #define XFXFXM_MASK (X_MASK | (1 << 11) | (1 << 20))
2598 /* An XFX form instruction with the FXM field filled in. */
2599 #define XFXM(op, xop, fxm, p4) \
2600 (X ((op), (xop)) | ((((unsigned long)(fxm)) & 0xff) << 12) \
2601 | ((unsigned long)(p4) << 20))
2603 /* An XFX form instruction with the SPR field filled in. */
2604 #define XSPR(op, xop, spr) \
2605 (X ((op), (xop)) | ((((unsigned long)(spr)) & 0x1f) << 16) | ((((unsigned long)(spr)) & 0x3e0) << 6))
2606 #define XSPR_MASK (X_MASK | SPR_MASK)
2608 /* An XFX form instruction with the SPR field filled in except for the
2610 #define XSPRBAT_MASK (XSPR_MASK &~ SPRBAT_MASK)
2612 /* An XFX form instruction with the SPR field filled in except for the
2614 #define XSPRG_MASK (XSPR_MASK & ~(0x1f << 16))
2616 /* An X form instruction with everything filled in except the E field. */
2617 #define XE_MASK (0xffff7fff)
2619 /* An X form user context instruction. */
2620 #define XUC(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x1f))
2621 #define XUC_MASK XUC(0x3f, 0x1f)
2623 /* An XW form instruction. */
2624 #define XW(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0x3f) << 1) | ((rc) & 1))
2625 /* The mask for a G form instruction. rc not supported at present. */
2626 #define XW_MASK XW (0x3f, 0x3f, 0)
2628 /* An APU form instruction. */
2629 #define APU(op, xop, rc) (OP (op) | (((unsigned long)(xop)) & 0x3ff) << 1 | ((rc) & 1))
2631 /* The mask for an APU form instruction. */
2632 #define APU_MASK APU (0x3f, 0x3ff, 1)
2633 #define APU_RT_MASK (APU_MASK | RT_MASK)
2634 #define APU_RA_MASK (APU_MASK | RA_MASK)
2636 /* The BO encodings used in extended conditional branch mnemonics. */
2637 #define BODNZF (0x0)
2638 #define BODNZFP (0x1)
2640 #define BODZFP (0x3)
2641 #define BODNZT (0x8)
2642 #define BODNZTP (0x9)
2644 #define BODZTP (0xb)
2655 #define BODNZ (0x10)
2656 #define BODNZP (0x11)
2658 #define BODZP (0x13)
2659 #define BODNZM4 (0x18)
2660 #define BODNZP4 (0x19)
2661 #define BODZM4 (0x1a)
2662 #define BODZP4 (0x1b)
2666 /* The BO16 encodings used in extended VLE conditional branch mnemonics. */
2670 /* The BO32 encodings used in extended VLE conditional branch mnemonics. */
2673 #define BO32DNZ (0x2)
2674 #define BO32DZ (0x3)
2676 /* The BI condition bit encodings used in extended conditional branch
2683 /* The TO encodings used in extended trap mnemonics. */
2700 /* Smaller names for the flags so each entry in the opcodes table will
2701 fit on a single line. */
2704 #define PPC PPC_OPCODE_PPC
2705 #define PPCCOM PPC_OPCODE_PPC | PPC_OPCODE_COMMON
2706 #define POWER4 PPC_OPCODE_POWER4
2707 #define POWER5 PPC_OPCODE_POWER5
2708 #define POWER6 PPC_OPCODE_POWER6
2709 #define POWER7 PPC_OPCODE_POWER7
2710 #define POWER8 PPC_OPCODE_POWER8
2711 #define CELL PPC_OPCODE_CELL
2712 #define PPC64 PPC_OPCODE_64 | PPC_OPCODE_64_BRIDGE
2713 #define NON32 (PPC_OPCODE_64 | PPC_OPCODE_POWER4 \
2714 | PPC_OPCODE_EFS | PPC_OPCODE_E500MC | PPC_OPCODE_TITAN)
2715 #define PPC403 PPC_OPCODE_403
2716 #define PPC405 PPC_OPCODE_405
2717 #define PPC440 PPC_OPCODE_440
2718 #define PPC464 PPC440
2719 #define PPC476 PPC_OPCODE_476
2723 #define PPCPS PPC_OPCODE_PPCPS
2724 #define PPCVEC PPC_OPCODE_ALTIVEC
2725 #define PPCVEC2 PPC_OPCODE_ALTIVEC2
2726 #define PPCVSX PPC_OPCODE_VSX
2727 #define PPCVSX2 PPC_OPCODE_VSX
2728 #define POWER PPC_OPCODE_POWER
2729 #define POWER2 PPC_OPCODE_POWER | PPC_OPCODE_POWER2
2730 #define PWR2COM PPC_OPCODE_POWER | PPC_OPCODE_POWER2 | PPC_OPCODE_COMMON
2731 #define PPCPWR2 PPC_OPCODE_PPC | PPC_OPCODE_POWER | PPC_OPCODE_POWER2 | PPC_OPCODE_COMMON
2732 #define COM PPC_OPCODE_POWER | PPC_OPCODE_PPC | PPC_OPCODE_COMMON
2733 #define M601 PPC_OPCODE_POWER | PPC_OPCODE_601
2734 #define PWRCOM PPC_OPCODE_POWER | PPC_OPCODE_601 | PPC_OPCODE_COMMON
2735 #define MFDEC1 PPC_OPCODE_POWER
2736 #define MFDEC2 PPC_OPCODE_PPC | PPC_OPCODE_601 | PPC_OPCODE_BOOKE | PPC_OPCODE_TITAN
2737 #define BOOKE PPC_OPCODE_BOOKE
2738 #define NO371 PPC_OPCODE_BOOKE | PPC_OPCODE_PPCPS | PPC_OPCODE_EFS | PPC_OPCODE_VLE
2739 #define PPCE300 PPC_OPCODE_E300
2740 #define PPCSPE PPC_OPCODE_SPE | PPC_OPCODE_VLE
2741 #define PPCISEL PPC_OPCODE_ISEL | PPC_OPCODE_VLE
2742 #define PPCEFS PPC_OPCODE_EFS | PPC_OPCODE_VLE
2743 #define PPCBRLK PPC_OPCODE_BRLOCK
2744 #define PPCPMR PPC_OPCODE_PMR
2745 #define PPCTMR PPC_OPCODE_TMR
2746 #define PPCCHLK PPC_OPCODE_CACHELCK
2747 #define PPCRFMCI PPC_OPCODE_RFMCI
2748 #define E500MC PPC_OPCODE_E500MC
2749 #define PPCA2 PPC_OPCODE_A2
2750 #define TITAN PPC_OPCODE_TITAN
2751 #define MULHW PPC_OPCODE_405 | PPC_OPCODE_440 | TITAN | PPC_OPCODE_VLE
2752 #define E500 PPC_OPCODE_E500
2753 #define E6500 PPC_OPCODE_E6500
2754 #define PPCVLE PPC_OPCODE_VLE
2755 #define PPCHTM PPC_OPCODE_HTM
2757 /* The opcode table.
2759 The format of the opcode table is:
2761 NAME OPCODE MASK FLAGS ANTI {OPERANDS}
2763 NAME is the name of the instruction.
2764 OPCODE is the instruction opcode.
2765 MASK is the opcode mask; this is used to tell the disassembler
2766 which bits in the actual opcode must match OPCODE.
2767 FLAGS are flags indicating which processors support the instruction.
2768 ANTI indicates which processors don't support the instruction.
2769 OPERANDS is the list of operands.
2771 The disassembler reads the table in order and prints the first
2772 instruction which matches, so this table is sorted to put more
2773 specific instructions before more general instructions.
2775 This table must be sorted by major opcode. Please try to keep it
2776 vaguely sorted within major opcode too, except of course where
2777 constrained otherwise by disassembler operation. */
2779 const struct powerpc_opcode powerpc_opcodes
[] = {
2780 {"attn", X(0,256), X_MASK
, POWER4
|PPCA2
, PPC476
, {0}},
2781 {"tdlgti", OPTO(2,TOLGT
), OPTO_MASK
, PPC64
, PPCNONE
, {RA
, SI
}},
2782 {"tdllti", OPTO(2,TOLLT
), OPTO_MASK
, PPC64
, PPCNONE
, {RA
, SI
}},
2783 {"tdeqi", OPTO(2,TOEQ
), OPTO_MASK
, PPC64
, PPCNONE
, {RA
, SI
}},
2784 {"tdlgei", OPTO(2,TOLGE
), OPTO_MASK
, PPC64
, PPCNONE
, {RA
, SI
}},
2785 {"tdlnli", OPTO(2,TOLNL
), OPTO_MASK
, PPC64
, PPCNONE
, {RA
, SI
}},
2786 {"tdllei", OPTO(2,TOLLE
), OPTO_MASK
, PPC64
, PPCNONE
, {RA
, SI
}},
2787 {"tdlngi", OPTO(2,TOLNG
), OPTO_MASK
, PPC64
, PPCNONE
, {RA
, SI
}},
2788 {"tdgti", OPTO(2,TOGT
), OPTO_MASK
, PPC64
, PPCNONE
, {RA
, SI
}},
2789 {"tdgei", OPTO(2,TOGE
), OPTO_MASK
, PPC64
, PPCNONE
, {RA
, SI
}},
2790 {"tdnli", OPTO(2,TONL
), OPTO_MASK
, PPC64
, PPCNONE
, {RA
, SI
}},
2791 {"tdlti", OPTO(2,TOLT
), OPTO_MASK
, PPC64
, PPCNONE
, {RA
, SI
}},
2792 {"tdlei", OPTO(2,TOLE
), OPTO_MASK
, PPC64
, PPCNONE
, {RA
, SI
}},
2793 {"tdngi", OPTO(2,TONG
), OPTO_MASK
, PPC64
, PPCNONE
, {RA
, SI
}},
2794 {"tdnei", OPTO(2,TONE
), OPTO_MASK
, PPC64
, PPCNONE
, {RA
, SI
}},
2795 {"tdui", OPTO(2,TOU
), OPTO_MASK
, PPC64
, PPCNONE
, {RA
, SI
}},
2796 {"tdi", OP(2), OP_MASK
, PPC64
, PPCNONE
, {TO
, RA
, SI
}},
2798 {"twlgti", OPTO(3,TOLGT
), OPTO_MASK
, PPCCOM
, PPCNONE
, {RA
, SI
}},
2799 {"tlgti", OPTO(3,TOLGT
), OPTO_MASK
, PWRCOM
, PPCNONE
, {RA
, SI
}},
2800 {"twllti", OPTO(3,TOLLT
), OPTO_MASK
, PPCCOM
, PPCNONE
, {RA
, SI
}},
2801 {"tllti", OPTO(3,TOLLT
), OPTO_MASK
, PWRCOM
, PPCNONE
, {RA
, SI
}},
2802 {"tweqi", OPTO(3,TOEQ
), OPTO_MASK
, PPCCOM
, PPCNONE
, {RA
, SI
}},
2803 {"teqi", OPTO(3,TOEQ
), OPTO_MASK
, PWRCOM
, PPCNONE
, {RA
, SI
}},
2804 {"twlgei", OPTO(3,TOLGE
), OPTO_MASK
, PPCCOM
, PPCNONE
, {RA
, SI
}},
2805 {"tlgei", OPTO(3,TOLGE
), OPTO_MASK
, PWRCOM
, PPCNONE
, {RA
, SI
}},
2806 {"twlnli", OPTO(3,TOLNL
), OPTO_MASK
, PPCCOM
, PPCNONE
, {RA
, SI
}},
2807 {"tlnli", OPTO(3,TOLNL
), OPTO_MASK
, PWRCOM
, PPCNONE
, {RA
, SI
}},
2808 {"twllei", OPTO(3,TOLLE
), OPTO_MASK
, PPCCOM
, PPCNONE
, {RA
, SI
}},
2809 {"tllei", OPTO(3,TOLLE
), OPTO_MASK
, PWRCOM
, PPCNONE
, {RA
, SI
}},
2810 {"twlngi", OPTO(3,TOLNG
), OPTO_MASK
, PPCCOM
, PPCNONE
, {RA
, SI
}},
2811 {"tlngi", OPTO(3,TOLNG
), OPTO_MASK
, PWRCOM
, PPCNONE
, {RA
, SI
}},
2812 {"twgti", OPTO(3,TOGT
), OPTO_MASK
, PPCCOM
, PPCNONE
, {RA
, SI
}},
2813 {"tgti", OPTO(3,TOGT
), OPTO_MASK
, PWRCOM
, PPCNONE
, {RA
, SI
}},
2814 {"twgei", OPTO(3,TOGE
), OPTO_MASK
, PPCCOM
, PPCNONE
, {RA
, SI
}},
2815 {"tgei", OPTO(3,TOGE
), OPTO_MASK
, PWRCOM
, PPCNONE
, {RA
, SI
}},
2816 {"twnli", OPTO(3,TONL
), OPTO_MASK
, PPCCOM
, PPCNONE
, {RA
, SI
}},
2817 {"tnli", OPTO(3,TONL
), OPTO_MASK
, PWRCOM
, PPCNONE
, {RA
, SI
}},
2818 {"twlti", OPTO(3,TOLT
), OPTO_MASK
, PPCCOM
, PPCNONE
, {RA
, SI
}},
2819 {"tlti", OPTO(3,TOLT
), OPTO_MASK
, PWRCOM
, PPCNONE
, {RA
, SI
}},
2820 {"twlei", OPTO(3,TOLE
), OPTO_MASK
, PPCCOM
, PPCNONE
, {RA
, SI
}},
2821 {"tlei", OPTO(3,TOLE
), OPTO_MASK
, PWRCOM
, PPCNONE
, {RA
, SI
}},
2822 {"twngi", OPTO(3,TONG
), OPTO_MASK
, PPCCOM
, PPCNONE
, {RA
, SI
}},
2823 {"tngi", OPTO(3,TONG
), OPTO_MASK
, PWRCOM
, PPCNONE
, {RA
, SI
}},
2824 {"twnei", OPTO(3,TONE
), OPTO_MASK
, PPCCOM
, PPCNONE
, {RA
, SI
}},
2825 {"tnei", OPTO(3,TONE
), OPTO_MASK
, PWRCOM
, PPCNONE
, {RA
, SI
}},
2826 {"twui", OPTO(3,TOU
), OPTO_MASK
, PPCCOM
, PPCNONE
, {RA
, SI
}},
2827 {"tui", OPTO(3,TOU
), OPTO_MASK
, PWRCOM
, PPCNONE
, {RA
, SI
}},
2828 {"twi", OP(3), OP_MASK
, PPCCOM
, PPCNONE
, {TO
, RA
, SI
}},
2829 {"ti", OP(3), OP_MASK
, PWRCOM
, PPCNONE
, {TO
, RA
, SI
}},
2831 {"ps_cmpu0", X (4, 0), X_MASK
|(3<<21), PPCPS
, PPCNONE
, {BF
, FRA
, FRB
}},
2832 {"vaddubm", VX (4, 0), VX_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
2833 {"vmaxub", VX (4, 2), VX_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
2834 {"vrlb", VX (4, 4), VX_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
2835 {"vcmpequb", VXR(4, 6,0), VXR_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
2836 {"vmuloub", VX (4, 8), VX_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
2837 {"vaddfp", VX (4, 10), VX_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
2838 {"psq_lx", XW (4, 6,0), XW_MASK
, PPCPS
, PPCNONE
, {FRT
,RA
,RB
,PSWM
,PSQM
}},
2839 {"vmrghb", VX (4, 12), VX_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
2840 {"psq_stx", XW (4, 7,0), XW_MASK
, PPCPS
, PPCNONE
, {FRS
,RA
,RB
,PSWM
,PSQM
}},
2841 {"vpkuhum", VX (4, 14), VX_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
2842 {"mulhhwu", XRC(4, 8,0), X_MASK
, MULHW
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
2843 {"mulhhwu.", XRC(4, 8,1), X_MASK
, MULHW
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
2844 {"ps_sum0", A (4, 10,0), A_MASK
, PPCPS
, PPCNONE
, {FRT
, FRA
, FRC
, FRB
}},
2845 {"ps_sum0.", A (4, 10,1), A_MASK
, PPCPS
, PPCNONE
, {FRT
, FRA
, FRC
, FRB
}},
2846 {"ps_sum1", A (4, 11,0), A_MASK
, PPCPS
, PPCNONE
, {FRT
, FRA
, FRC
, FRB
}},
2847 {"ps_sum1.", A (4, 11,1), A_MASK
, PPCPS
, PPCNONE
, {FRT
, FRA
, FRC
, FRB
}},
2848 {"ps_muls0", A (4, 12,0), AFRB_MASK
, PPCPS
, PPCNONE
, {FRT
, FRA
, FRC
}},
2849 {"machhwu", XO (4, 12,0,0),XO_MASK
, MULHW
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
2850 {"ps_muls0.", A (4, 12,1), AFRB_MASK
, PPCPS
, PPCNONE
, {FRT
, FRA
, FRC
}},
2851 {"machhwu.", XO (4, 12,0,1),XO_MASK
, MULHW
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
2852 {"ps_muls1", A (4, 13,0), AFRB_MASK
, PPCPS
, PPCNONE
, {FRT
, FRA
, FRC
}},
2853 {"ps_muls1.", A (4, 13,1), AFRB_MASK
, PPCPS
, PPCNONE
, {FRT
, FRA
, FRC
}},
2854 {"ps_madds0", A (4, 14,0), A_MASK
, PPCPS
, PPCNONE
, {FRT
, FRA
, FRC
, FRB
}},
2855 {"ps_madds0.", A (4, 14,1), A_MASK
, PPCPS
, PPCNONE
, {FRT
, FRA
, FRC
, FRB
}},
2856 {"ps_madds1", A (4, 15,0), A_MASK
, PPCPS
, PPCNONE
, {FRT
, FRA
, FRC
, FRB
}},
2857 {"ps_madds1.", A (4, 15,1), A_MASK
, PPCPS
, PPCNONE
, {FRT
, FRA
, FRC
, FRB
}},
2858 {"vmhaddshs", VXA(4, 32), VXA_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
, VC
}},
2859 {"vmhraddshs", VXA(4, 33), VXA_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
, VC
}},
2860 {"vmladduhm", VXA(4, 34), VXA_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
, VC
}},
2861 {"ps_div", A (4, 18,0), AFRC_MASK
, PPCPS
, PPCNONE
, {FRT
, FRA
, FRB
}},
2862 {"vmsumubm", VXA(4, 36), VXA_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
, VC
}},
2863 {"ps_div.", A (4, 18,1), AFRC_MASK
, PPCPS
, PPCNONE
, {FRT
, FRA
, FRB
}},
2864 {"vmsummbm", VXA(4, 37), VXA_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
, VC
}},
2865 {"vmsumuhm", VXA(4, 38), VXA_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
, VC
}},
2866 {"vmsumuhs", VXA(4, 39), VXA_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
, VC
}},
2867 {"ps_sub", A (4, 20,0), AFRC_MASK
, PPCPS
, PPCNONE
, {FRT
, FRA
, FRB
}},
2868 {"vmsumshm", VXA(4, 40), VXA_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
, VC
}},
2869 {"ps_sub.", A (4, 20,1), AFRC_MASK
, PPCPS
, PPCNONE
, {FRT
, FRA
, FRB
}},
2870 {"vmsumshs", VXA(4, 41), VXA_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
, VC
}},
2871 {"ps_add", A (4, 21,0), AFRC_MASK
, PPCPS
, PPCNONE
, {FRT
, FRA
, FRB
}},
2872 {"vsel", VXA(4, 42), VXA_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
, VC
}},
2873 {"ps_add.", A (4, 21,1), AFRC_MASK
, PPCPS
, PPCNONE
, {FRT
, FRA
, FRB
}},
2874 {"vperm", VXA(4, 43), VXA_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
, VC
}},
2875 {"vsldoi", VXA(4, 44), VXASHB_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
, SHB
}},
2876 {"ps_sel", A (4, 23,0), A_MASK
, PPCPS
, PPCNONE
, {FRT
, FRA
, FRC
, FRB
}},
2877 {"vpermxor", VXA(4, 45), VXA_MASK
, PPCVEC2
, PPCNONE
, {VD
, VA
, VB
, VC
}},
2878 {"vmaddfp", VXA(4, 46), VXA_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VC
, VB
}},
2879 {"ps_sel.", A (4, 23,1), A_MASK
, PPCPS
, PPCNONE
, {FRT
, FRA
, FRC
, FRB
}},
2880 {"vnmsubfp", VXA(4, 47), VXA_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VC
, VB
}},
2881 {"ps_res", A (4, 24,0), AFRAFRC_MASK
, PPCPS
, PPCNONE
, {FRT
, FRB
}},
2882 {"ps_res.", A (4, 24,1), AFRAFRC_MASK
, PPCPS
, PPCNONE
, {FRT
, FRB
}},
2883 {"ps_mul", A (4, 25,0), AFRB_MASK
, PPCPS
, PPCNONE
, {FRT
, FRA
, FRC
}},
2884 {"ps_mul.", A (4, 25,1), AFRB_MASK
, PPCPS
, PPCNONE
, {FRT
, FRA
, FRC
}},
2885 {"ps_rsqrte", A (4, 26,0), AFRAFRC_MASK
, PPCPS
, PPCNONE
, {FRT
, FRB
}},
2886 {"ps_rsqrte.", A (4, 26,1), AFRAFRC_MASK
, PPCPS
, PPCNONE
, {FRT
, FRB
}},
2887 {"ps_msub", A (4, 28,0), A_MASK
, PPCPS
, PPCNONE
, {FRT
, FRA
, FRC
, FRB
}},
2888 {"ps_msub.", A (4, 28,1), A_MASK
, PPCPS
, PPCNONE
, {FRT
, FRA
, FRC
, FRB
}},
2889 {"ps_madd", A (4, 29,0), A_MASK
, PPCPS
, PPCNONE
, {FRT
, FRA
, FRC
, FRB
}},
2890 {"ps_madd.", A (4, 29,1), A_MASK
, PPCPS
, PPCNONE
, {FRT
, FRA
, FRC
, FRB
}},
2891 {"ps_nmsub", A (4, 30,0), A_MASK
, PPCPS
, PPCNONE
, {FRT
, FRA
, FRC
, FRB
}},
2892 {"ps_nmsub.", A (4, 30,1), A_MASK
, PPCPS
, PPCNONE
, {FRT
, FRA
, FRC
, FRB
}},
2893 {"ps_nmadd", A (4, 31,0), A_MASK
, PPCPS
, PPCNONE
, {FRT
, FRA
, FRC
, FRB
}},
2894 {"ps_nmadd.", A (4, 31,1), A_MASK
, PPCPS
, PPCNONE
, {FRT
, FRA
, FRC
, FRB
}},
2895 {"ps_cmpo0", X (4, 32), X_MASK
|(3<<21), PPCPS
, PPCNONE
, {BF
, FRA
, FRB
}},
2896 {"vaddeuqm", VXA(4, 60), VXA_MASK
, PPCVEC2
, PPCNONE
, {VD
, VA
, VB
, VC
}},
2897 {"vaddecuq", VXA(4, 61), VXA_MASK
, PPCVEC2
, PPCNONE
, {VD
, VA
, VB
, VC
}},
2898 {"vsubeuqm", VXA(4, 62), VXA_MASK
, PPCVEC2
, PPCNONE
, {VD
, VA
, VB
, VC
}},
2899 {"vsubecuq", VXA(4, 63), VXA_MASK
, PPCVEC2
, PPCNONE
, {VD
, VA
, VB
, VC
}},
2900 {"vadduhm", VX (4, 64), VX_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
2901 {"vmaxuh", VX (4, 66), VX_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
2902 {"vrlh", VX (4, 68), VX_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
2903 {"vcmpequh", VXR(4, 70,0), VXR_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
2904 {"vmulouh", VX (4, 72), VX_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
2905 {"vsubfp", VX (4, 74), VX_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
2906 {"psq_lux", XW (4, 38,0), XW_MASK
, PPCPS
, PPCNONE
, {FRT
,RA
,RB
,PSWM
,PSQM
}},
2907 {"vmrghh", VX (4, 76), VX_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
2908 {"psq_stux", XW (4, 39,0), XW_MASK
, PPCPS
, PPCNONE
, {FRS
,RA
,RB
,PSWM
,PSQM
}},
2909 {"vpkuwum", VX (4, 78), VX_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
2910 {"ps_neg", XRC(4, 40,0), XRA_MASK
, PPCPS
, PPCNONE
, {FRT
, FRB
}},
2911 {"mulhhw", XRC(4, 40,0), X_MASK
, MULHW
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
2912 {"ps_neg.", XRC(4, 40,1), XRA_MASK
, PPCPS
, PPCNONE
, {FRT
, FRB
}},
2913 {"mulhhw.", XRC(4, 40,1), X_MASK
, MULHW
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
2914 {"machhw", XO (4, 44,0,0),XO_MASK
, MULHW
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
2915 {"machhw.", XO (4, 44,0,1),XO_MASK
, MULHW
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
2916 {"nmachhw", XO (4, 46,0,0),XO_MASK
, MULHW
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
2917 {"nmachhw.", XO (4, 46,0,1),XO_MASK
, MULHW
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
2918 {"ps_cmpu1", X (4, 64), X_MASK
|(3<<21), PPCPS
, PPCNONE
, {BF
, FRA
, FRB
}},
2919 {"vadduwm", VX (4, 128), VX_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
2920 {"vmaxuw", VX (4, 130), VX_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
2921 {"vrlw", VX (4, 132), VX_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
2922 {"vcmpequw", VXR(4, 134,0), VXR_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
2923 {"vmulouw", VX (4, 136), VX_MASK
, PPCVEC2
, PPCNONE
, {VD
, VA
, VB
}},
2924 {"vmuluwm", VX (4, 137), VX_MASK
, PPCVEC2
, PPCNONE
, {VD
, VA
, VB
}},
2925 {"vmrghw", VX (4, 140), VX_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
2926 {"vpkuhus", VX (4, 142), VX_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
2927 {"ps_mr", XRC(4, 72,0), XRA_MASK
, PPCPS
, PPCNONE
, {FRT
, FRB
}},
2928 {"ps_mr.", XRC(4, 72,1), XRA_MASK
, PPCPS
, PPCNONE
, {FRT
, FRB
}},
2929 {"machhwsu", XO (4, 76,0,0),XO_MASK
, MULHW
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
2930 {"machhwsu.", XO (4, 76,0,1),XO_MASK
, MULHW
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
2931 {"ps_cmpo1", X (4, 96), X_MASK
|(3<<21), PPCPS
, PPCNONE
, {BF
, FRA
, FRB
}},
2932 {"vaddudm", VX (4, 192), VX_MASK
, PPCVEC2
, PPCNONE
, {VD
, VA
, VB
}},
2933 {"vmaxud", VX (4, 194), VX_MASK
, PPCVEC2
, PPCNONE
, {VD
, VA
, VB
}},
2934 {"vrld", VX (4, 196), VX_MASK
, PPCVEC2
, PPCNONE
, {VD
, VA
, VB
}},
2935 {"vcmpeqfp", VXR(4, 198,0), VXR_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
2936 {"vcmpequd", VXR(4, 199,0), VXR_MASK
, PPCVEC2
, PPCNONE
, {VD
, VA
, VB
}},
2937 {"vpkuwus", VX (4, 206), VX_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
2938 {"machhws", XO (4, 108,0,0),XO_MASK
, MULHW
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
2939 {"machhws.", XO (4, 108,0,1),XO_MASK
, MULHW
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
2940 {"nmachhws", XO (4, 110,0,0),XO_MASK
, MULHW
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
2941 {"nmachhws.", XO (4, 110,0,1),XO_MASK
, MULHW
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
2942 {"vadduqm", VX (4, 256), VX_MASK
, PPCVEC2
, PPCNONE
, {VD
, VA
, VB
}},
2943 {"vmaxsb", VX (4, 258), VX_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
2944 {"vslb", VX (4, 260), VX_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
2945 {"vmulosb", VX (4, 264), VX_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
2946 {"vrefp", VX (4, 266), VXVA_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VB
}},
2947 {"vmrglb", VX (4, 268), VX_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
2948 {"vpkshus", VX (4, 270), VX_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
2949 {"ps_nabs", XRC(4, 136,0), XRA_MASK
, PPCPS
, PPCNONE
, {FRT
, FRB
}},
2950 {"mulchwu", XRC(4, 136,0), X_MASK
, MULHW
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
2951 {"ps_nabs.", XRC(4, 136,1), XRA_MASK
, PPCPS
, PPCNONE
, {FRT
, FRB
}},
2952 {"mulchwu.", XRC(4, 136,1), X_MASK
, MULHW
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
2953 {"macchwu", XO (4, 140,0,0),XO_MASK
, MULHW
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
2954 {"macchwu.", XO (4, 140,0,1),XO_MASK
, MULHW
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
2955 {"vaddcuq", VX (4, 320), VX_MASK
, PPCVEC2
, PPCNONE
, {VD
, VA
, VB
}},
2956 {"vmaxsh", VX (4, 322), VX_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
2957 {"vslh", VX (4, 324), VX_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
2958 {"vmulosh", VX (4, 328), VX_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
2959 {"vrsqrtefp", VX (4, 330), VXVA_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VB
}},
2960 {"vmrglh", VX (4, 332), VX_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
2961 {"vpkswus", VX (4, 334), VX_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
2962 {"mulchw", XRC(4, 168,0), X_MASK
, MULHW
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
2963 {"mulchw.", XRC(4, 168,1), X_MASK
, MULHW
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
2964 {"macchw", XO (4, 172,0,0),XO_MASK
, MULHW
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
2965 {"macchw.", XO (4, 172,0,1),XO_MASK
, MULHW
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
2966 {"nmacchw", XO (4, 174,0,0),XO_MASK
, MULHW
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
2967 {"nmacchw.", XO (4, 174,0,1),XO_MASK
, MULHW
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
2968 {"vaddcuw", VX (4, 384), VX_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
2969 {"vmaxsw", VX (4, 386), VX_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
2970 {"vslw", VX (4, 388), VX_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
2971 {"vmulosw", VX (4, 392), VX_MASK
, PPCVEC2
, PPCNONE
, {VD
, VA
, VB
}},
2972 {"vexptefp", VX (4, 394), VXVA_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VB
}},
2973 {"vmrglw", VX (4, 396), VX_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
2974 {"vpkshss", VX (4, 398), VX_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
2975 {"macchwsu", XO (4, 204,0,0),XO_MASK
, MULHW
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
2976 {"macchwsu.", XO (4, 204,0,1),XO_MASK
, MULHW
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
2977 {"vmaxsd", VX (4, 450), VX_MASK
, PPCVEC2
, PPCNONE
, {VD
, VA
, VB
}},
2978 {"vsl", VX (4, 452), VX_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
2979 {"vcmpgefp", VXR(4, 454,0), VXR_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
2980 {"vlogefp", VX (4, 458), VXVA_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VB
}},
2981 {"vpkswss", VX (4, 462), VX_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
2982 {"macchws", XO (4, 236,0,0),XO_MASK
, MULHW
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
2983 {"macchws.", XO (4, 236,0,1),XO_MASK
, MULHW
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
2984 {"nmacchws", XO (4, 238,0,0),XO_MASK
, MULHW
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
2985 {"nmacchws.", XO (4, 238,0,1),XO_MASK
, MULHW
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
2986 {"evaddw", VX (4, 512), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
2987 {"vaddubs", VX (4, 512), VX_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
2988 {"evaddiw", VX (4, 514), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RB
, UIMM
}},
2989 {"vminub", VX (4, 514), VX_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
2990 {"evsubfw", VX (4, 516), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
2991 {"evsubw", VX (4, 516), VX_MASK
, PPCSPE
, PPCNONE
, {RS
, RB
, RA
}},
2992 {"vsrb", VX (4, 516), VX_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
2993 {"evsubifw", VX (4, 518), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, UIMM
, RB
}},
2994 {"evsubiw", VX (4, 518), VX_MASK
, PPCSPE
, PPCNONE
, {RS
, RB
, UIMM
}},
2995 {"vcmpgtub", VXR(4, 518,0), VXR_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
2996 {"evabs", VX (4, 520), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
}},
2997 {"vmuleub", VX (4, 520), VX_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
2998 {"evneg", VX (4, 521), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
}},
2999 {"evextsb", VX (4, 522), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
}},
3000 {"vrfin", VX (4, 522), VXVA_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VB
}},
3001 {"evextsh", VX (4, 523), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
}},
3002 {"evrndw", VX (4, 524), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
}},
3003 {"vspltb", VX (4, 524), VXUIMM4_MASK
,PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VB
, UIMM4
}},
3004 {"evcntlzw", VX (4, 525), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
}},
3005 {"evcntlsw", VX (4, 526), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
}},
3006 {"vupkhsb", VX (4, 526), VXVA_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VB
}},
3007 {"brinc", VX (4, 527), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3008 {"ps_abs", XRC(4, 264,0), XRA_MASK
, PPCPS
, PPCNONE
, {FRT
, FRB
}},
3009 {"ps_abs.", XRC(4, 264,1), XRA_MASK
, PPCPS
, PPCNONE
, {FRT
, FRB
}},
3010 {"evand", VX (4, 529), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3011 {"evandc", VX (4, 530), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3012 {"evxor", VX (4, 534), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3013 {"evmr", VX (4, 535), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, BBA
}},
3014 {"evor", VX (4, 535), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3015 {"evnor", VX (4, 536), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3016 {"evnot", VX (4, 536), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, BBA
}},
3017 {"get", APU(4, 268,0), APU_RA_MASK
, PPC405
, PPCNONE
, {RT
, FSL
}},
3018 {"eveqv", VX (4, 537), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3019 {"evorc", VX (4, 539), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3020 {"evnand", VX (4, 542), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3021 {"evsrwu", VX (4, 544), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3022 {"evsrws", VX (4, 545), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3023 {"evsrwiu", VX (4, 546), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, EVUIMM
}},
3024 {"evsrwis", VX (4, 547), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, EVUIMM
}},
3025 {"evslw", VX (4, 548), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3026 {"evslwi", VX (4, 550), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, EVUIMM
}},
3027 {"evrlw", VX (4, 552), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3028 {"evsplati", VX (4, 553), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, SIMM
}},
3029 {"evrlwi", VX (4, 554), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, EVUIMM
}},
3030 {"evsplatfi", VX (4, 555), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, SIMM
}},
3031 {"evmergehi", VX (4, 556), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3032 {"evmergelo", VX (4, 557), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3033 {"evmergehilo", VX (4, 558), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3034 {"evmergelohi", VX (4, 559), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3035 {"evcmpgtu", VX (4, 560), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {CRFD
, RA
, RB
}},
3036 {"evcmpgts", VX (4, 561), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {CRFD
, RA
, RB
}},
3037 {"evcmpltu", VX (4, 562), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {CRFD
, RA
, RB
}},
3038 {"evcmplts", VX (4, 563), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {CRFD
, RA
, RB
}},
3039 {"evcmpeq", VX (4, 564), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {CRFD
, RA
, RB
}},
3040 {"cget", APU(4, 284,0), APU_RA_MASK
, PPC405
, PPCNONE
, {RT
, FSL
}},
3041 {"vadduhs", VX (4, 576), VX_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
3042 {"vminuh", VX (4, 578), VX_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
3043 {"vsrh", VX (4, 580), VX_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
3044 {"vcmpgtuh", VXR(4, 582,0), VXR_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
3045 {"vmuleuh", VX (4, 584), VX_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
3046 {"vrfiz", VX (4, 586), VXVA_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VB
}},
3047 {"vsplth", VX (4, 588), VXUIMM3_MASK
,PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VB
, UIMM3
}},
3048 {"vupkhsh", VX (4, 590), VXVA_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VB
}},
3049 {"nget", APU(4, 300,0), APU_RA_MASK
, PPC405
, PPCNONE
, {RT
, FSL
}},
3050 {"evsel", EVSEL(4,79), EVSEL_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
, CRFS
}},
3051 {"ncget", APU(4, 316,0), APU_RA_MASK
, PPC405
, PPCNONE
, {RT
, FSL
}},
3052 {"evfsadd", VX (4, 640), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3053 {"vadduws", VX (4, 640), VX_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
3054 {"evfssub", VX (4, 641), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3055 {"vminuw", VX (4, 642), VX_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
3056 {"evfsabs", VX (4, 644), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
}},
3057 {"vsrw", VX (4, 644), VX_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
3058 {"evfsnabs", VX (4, 645), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
}},
3059 {"evfsneg", VX (4, 646), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
}},
3060 {"vcmpgtuw", VXR(4, 646,0), VXR_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
3061 {"vmuleuw", VX (4, 648), VX_MASK
, PPCVEC2
, PPCNONE
, {VD
, VA
, VB
}},
3062 {"evfsmul", VX (4, 648), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3063 {"evfsdiv", VX (4, 649), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3064 {"vrfip", VX (4, 650), VXVA_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VB
}},
3065 {"evfscmpgt", VX (4, 652), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {CRFD
, RA
, RB
}},
3066 {"vspltw", VX (4, 652), VXUIMM2_MASK
,PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VB
, UIMM2
}},
3067 {"evfscmplt", VX (4, 653), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {CRFD
, RA
, RB
}},
3068 {"evfscmpeq", VX (4, 654), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {CRFD
, RA
, RB
}},
3069 {"vupklsb", VX (4, 654), VXVA_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VB
}},
3070 {"evfscfui", VX (4, 656), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RB
}},
3071 {"evfscfsi", VX (4, 657), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RB
}},
3072 {"evfscfuf", VX (4, 658), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RB
}},
3073 {"evfscfsf", VX (4, 659), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RB
}},
3074 {"evfsctui", VX (4, 660), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RB
}},
3075 {"evfsctsi", VX (4, 661), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RB
}},
3076 {"evfsctuf", VX (4, 662), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RB
}},
3077 {"evfsctsf", VX (4, 663), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RB
}},
3078 {"evfsctuiz", VX (4, 664), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RB
}},
3079 {"put", APU(4, 332,0), APU_RT_MASK
, PPC405
, PPCNONE
, {RA
, FSL
}},
3080 {"evfsctsiz", VX (4, 666), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RB
}},
3081 {"evfststgt", VX (4, 668), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {CRFD
, RA
, RB
}},
3082 {"evfststlt", VX (4, 669), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {CRFD
, RA
, RB
}},
3083 {"evfststeq", VX (4, 670), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {CRFD
, RA
, RB
}},
3084 {"cput", APU(4, 348,0), APU_RT_MASK
, PPC405
, PPCNONE
, {RA
, FSL
}},
3085 {"efsadd", VX (4, 704), VX_MASK
, PPCEFS
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3086 {"efssub", VX (4, 705), VX_MASK
, PPCEFS
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3087 {"vminud", VX (4, 706), VX_MASK
, PPCVEC2
, PPCNONE
, {VD
, VA
, VB
}},
3088 {"efsabs", VX (4, 708), VX_MASK
, PPCEFS
|PPCVLE
, PPCNONE
, {RS
, RA
}},
3089 {"vsr", VX (4, 708), VX_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
3090 {"efsnabs", VX (4, 709), VX_MASK
, PPCEFS
|PPCVLE
, PPCNONE
, {RS
, RA
}},
3091 {"efsneg", VX (4, 710), VX_MASK
, PPCEFS
|PPCVLE
, PPCNONE
, {RS
, RA
}},
3092 {"vcmpgtfp", VXR(4, 710,0), VXR_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
3093 {"vcmpgtud", VXR(4, 711,0), VXR_MASK
, PPCVEC2
, PPCNONE
, {VD
, VA
, VB
}},
3094 {"efsmul", VX (4, 712), VX_MASK
, PPCEFS
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3095 {"efsdiv", VX (4, 713), VX_MASK
, PPCEFS
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3096 {"vrfim", VX (4, 714), VXVA_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VB
}},
3097 {"efscmpgt", VX (4, 716), VX_MASK
, PPCEFS
|PPCVLE
, PPCNONE
, {CRFD
, RA
, RB
}},
3098 {"efscmplt", VX (4, 717), VX_MASK
, PPCEFS
|PPCVLE
, PPCNONE
, {CRFD
, RA
, RB
}},
3099 {"efscmpeq", VX (4, 718), VX_MASK
, PPCEFS
|PPCVLE
, PPCNONE
, {CRFD
, RA
, RB
}},
3100 {"vupklsh", VX (4, 718), VXVA_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VB
}},
3101 {"efscfd", VX (4, 719), VX_MASK
, PPCEFS
|PPCVLE
, PPCNONE
, {RS
, RB
}},
3102 {"efscfui", VX (4, 720), VX_MASK
, PPCEFS
|PPCVLE
, PPCNONE
, {RS
, RB
}},
3103 {"efscfsi", VX (4, 721), VX_MASK
, PPCEFS
|PPCVLE
, PPCNONE
, {RS
, RB
}},
3104 {"efscfuf", VX (4, 722), VX_MASK
, PPCEFS
|PPCVLE
, PPCNONE
, {RS
, RB
}},
3105 {"efscfsf", VX (4, 723), VX_MASK
, PPCEFS
|PPCVLE
, PPCNONE
, {RS
, RB
}},
3106 {"efsctui", VX (4, 724), VX_MASK
, PPCEFS
|PPCVLE
, PPCNONE
, {RS
, RB
}},
3107 {"efsctsi", VX (4, 725), VX_MASK
, PPCEFS
|PPCVLE
, PPCNONE
, {RS
, RB
}},
3108 {"efsctuf", VX (4, 726), VX_MASK
, PPCEFS
|PPCVLE
, PPCNONE
, {RS
, RB
}},
3109 {"efsctsf", VX (4, 727), VX_MASK
, PPCEFS
|PPCVLE
, PPCNONE
, {RS
, RB
}},
3110 {"efsctuiz", VX (4, 728), VX_MASK
, PPCEFS
|PPCVLE
, PPCNONE
, {RS
, RB
}},
3111 {"nput", APU(4, 364,0), APU_RT_MASK
, PPC405
, PPCNONE
, {RA
, FSL
}},
3112 {"efsctsiz", VX (4, 730), VX_MASK
, PPCEFS
|PPCVLE
, PPCNONE
, {RS
, RB
}},
3113 {"efststgt", VX (4, 732), VX_MASK
, PPCEFS
|PPCVLE
, PPCNONE
, {CRFD
, RA
, RB
}},
3114 {"efststlt", VX (4, 733), VX_MASK
, PPCEFS
|PPCVLE
, PPCNONE
, {CRFD
, RA
, RB
}},
3115 {"efststeq", VX (4, 734), VX_MASK
, PPCEFS
|PPCVLE
, PPCNONE
, {CRFD
, RA
, RB
}},
3116 {"efdadd", VX (4, 736), VX_MASK
, PPCEFS
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3117 {"efdsub", VX (4, 737), VX_MASK
, PPCEFS
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3118 {"efdcfuid", VX (4, 738), VX_MASK
, PPCEFS
|PPCVLE
, PPCNONE
, {RS
, RB
}},
3119 {"efdcfsid", VX (4, 739), VX_MASK
, PPCEFS
|PPCVLE
, PPCNONE
, {RS
, RB
}},
3120 {"efdabs", VX (4, 740), VX_MASK
, PPCEFS
|PPCVLE
, PPCNONE
, {RS
, RA
}},
3121 {"efdnabs", VX (4, 741), VX_MASK
, PPCEFS
|PPCVLE
, PPCNONE
, {RS
, RA
}},
3122 {"efdneg", VX (4, 742), VX_MASK
, PPCEFS
|PPCVLE
, PPCNONE
, {RS
, RA
}},
3123 {"efdmul", VX (4, 744), VX_MASK
, PPCEFS
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3124 {"efddiv", VX (4, 745), VX_MASK
, PPCEFS
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3125 {"efdctuidz", VX (4, 746), VX_MASK
, PPCEFS
|PPCVLE
, PPCNONE
, {RS
, RB
}},
3126 {"efdctsidz", VX (4, 747), VX_MASK
, PPCEFS
|PPCVLE
, PPCNONE
, {RS
, RB
}},
3127 {"efdcmpgt", VX (4, 748), VX_MASK
, PPCEFS
|PPCVLE
, PPCNONE
, {CRFD
, RA
, RB
}},
3128 {"efdcmplt", VX (4, 749), VX_MASK
, PPCEFS
|PPCVLE
, PPCNONE
, {CRFD
, RA
, RB
}},
3129 {"efdcmpeq", VX (4, 750), VX_MASK
, PPCEFS
|PPCVLE
, PPCNONE
, {CRFD
, RA
, RB
}},
3130 {"efdcfs", VX (4, 751), VX_MASK
, PPCEFS
|PPCVLE
, PPCNONE
, {RS
, RB
}},
3131 {"efdcfui", VX (4, 752), VX_MASK
, PPCEFS
|PPCVLE
, PPCNONE
, {RS
, RB
}},
3132 {"efdcfsi", VX (4, 753), VX_MASK
, PPCEFS
|PPCVLE
, PPCNONE
, {RS
, RB
}},
3133 {"efdcfuf", VX (4, 754), VX_MASK
, PPCEFS
|PPCVLE
, PPCNONE
, {RS
, RB
}},
3134 {"efdcfsf", VX (4, 755), VX_MASK
, PPCEFS
|PPCVLE
, PPCNONE
, {RS
, RB
}},
3135 {"efdctui", VX (4, 756), VX_MASK
, PPCEFS
|PPCVLE
, PPCNONE
, {RS
, RB
}},
3136 {"efdctsi", VX (4, 757), VX_MASK
, PPCEFS
|PPCVLE
, PPCNONE
, {RS
, RB
}},
3137 {"efdctuf", VX (4, 758), VX_MASK
, PPCEFS
|PPCVLE
, PPCNONE
, {RS
, RB
}},
3138 {"efdctsf", VX (4, 759), VX_MASK
, PPCEFS
|PPCVLE
, PPCNONE
, {RS
, RB
}},
3139 {"efdctuiz", VX (4, 760), VX_MASK
, PPCEFS
|PPCVLE
, PPCNONE
, {RS
, RB
}},
3140 {"ncput", APU(4, 380,0), APU_RT_MASK
, PPC405
, PPCNONE
, {RA
, FSL
}},
3141 {"efdctsiz", VX (4, 762), VX_MASK
, PPCEFS
|PPCVLE
, PPCNONE
, {RS
, RB
}},
3142 {"efdtstgt", VX (4, 764), VX_MASK
, PPCEFS
|PPCVLE
, PPCNONE
, {CRFD
, RA
, RB
}},
3143 {"efdtstlt", VX (4, 765), VX_MASK
, PPCEFS
|PPCVLE
, PPCNONE
, {CRFD
, RA
, RB
}},
3144 {"efdtsteq", VX (4, 766), VX_MASK
, PPCEFS
|PPCVLE
, PPCNONE
, {CRFD
, RA
, RB
}},
3145 {"evlddx", VX (4, 768), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3146 {"vaddsbs", VX (4, 768), VX_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
3147 {"evldd", VX (4, 769), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, EVUIMM_8
, RA
}},
3148 {"evldwx", VX (4, 770), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3149 {"vminsb", VX (4, 770), VX_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
3150 {"evldw", VX (4, 771), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, EVUIMM_8
, RA
}},
3151 {"evldhx", VX (4, 772), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3152 {"vsrab", VX (4, 772), VX_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
3153 {"evldh", VX (4, 773), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, EVUIMM_8
, RA
}},
3154 {"vcmpgtsb", VXR(4, 774,0), VXR_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
3155 {"evlhhesplatx",VX (4, 776), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3156 {"vmulesb", VX (4, 776), VX_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
3157 {"evlhhesplat", VX (4, 777), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, EVUIMM_2
, RA
}},
3158 {"vcfux", VX (4, 778), VX_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VB
, UIMM
}},
3159 {"vcuxwfp", VX (4, 778), VX_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VB
, UIMM
}},
3160 {"evlhhousplatx",VX(4, 780), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3161 {"vspltisb", VX (4, 780), VXVB_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, SIMM
}},
3162 {"evlhhousplat",VX (4, 781), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, EVUIMM_2
, RA
}},
3163 {"evlhhossplatx",VX(4, 782), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3164 {"vpkpx", VX (4, 782), VX_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
3165 {"evlhhossplat",VX (4, 783), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, EVUIMM_2
, RA
}},
3166 {"mullhwu", XRC(4, 392,0), X_MASK
, MULHW
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
3167 {"evlwhex", VX (4, 784), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3168 {"mullhwu.", XRC(4, 392,1), X_MASK
, MULHW
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
3169 {"evlwhe", VX (4, 785), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, EVUIMM_4
, RA
}},
3170 {"evlwhoux", VX (4, 788), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3171 {"evlwhou", VX (4, 789), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, EVUIMM_4
, RA
}},
3172 {"evlwhosx", VX (4, 790), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3173 {"evlwhos", VX (4, 791), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, EVUIMM_4
, RA
}},
3174 {"maclhwu", XO (4, 396,0,0),XO_MASK
, MULHW
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
3175 {"evlwwsplatx", VX (4, 792), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3176 {"maclhwu.", XO (4, 396,0,1),XO_MASK
, MULHW
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
3177 {"evlwwsplat", VX (4, 793), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, EVUIMM_4
, RA
}},
3178 {"evlwhsplatx", VX (4, 796), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3179 {"evlwhsplat", VX (4, 797), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, EVUIMM_4
, RA
}},
3180 {"evstddx", VX (4, 800), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3181 {"evstdd", VX (4, 801), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, EVUIMM_8
, RA
}},
3182 {"evstdwx", VX (4, 802), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3183 {"evstdw", VX (4, 803), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, EVUIMM_8
, RA
}},
3184 {"evstdhx", VX (4, 804), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3185 {"evstdh", VX (4, 805), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, EVUIMM_8
, RA
}},
3186 {"evstwhex", VX (4, 816), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3187 {"evstwhe", VX (4, 817), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, EVUIMM_4
, RA
}},
3188 {"evstwhox", VX (4, 820), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3189 {"evstwho", VX (4, 821), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, EVUIMM_4
, RA
}},
3190 {"evstwwex", VX (4, 824), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3191 {"evstwwe", VX (4, 825), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, EVUIMM_4
, RA
}},
3192 {"evstwwox", VX (4, 828), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3193 {"evstwwo", VX (4, 829), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, EVUIMM_4
, RA
}},
3194 {"vaddshs", VX (4, 832), VX_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
3195 {"vminsh", VX (4, 834), VX_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
3196 {"vsrah", VX (4, 836), VX_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
3197 {"vcmpgtsh", VXR(4, 838,0), VXR_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
3198 {"vmulesh", VX (4, 840), VX_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
3199 {"vcfsx", VX (4, 842), VX_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VB
, UIMM
}},
3200 {"vcsxwfp", VX (4, 842), VX_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VB
, UIMM
}},
3201 {"vspltish", VX (4, 844), VXVB_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, SIMM
}},
3202 {"vupkhpx", VX (4, 846), VXVA_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VB
}},
3203 {"mullhw", XRC(4, 424,0), X_MASK
, MULHW
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
3204 {"mullhw.", XRC(4, 424,1), X_MASK
, MULHW
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
3205 {"maclhw", XO (4, 428,0,0),XO_MASK
, MULHW
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
3206 {"maclhw.", XO (4, 428,0,1),XO_MASK
, MULHW
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
3207 {"nmaclhw", XO (4, 430,0,0),XO_MASK
, MULHW
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
3208 {"nmaclhw.", XO (4, 430,0,1),XO_MASK
, MULHW
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
3209 {"vaddsws", VX (4, 896), VX_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
3210 {"vminsw", VX (4, 898), VX_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
3211 {"vsraw", VX (4, 900), VX_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
3212 {"vcmpgtsw", VXR(4, 902,0), VXR_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
3213 {"vmulesw", VX (4, 904), VX_MASK
, PPCVEC2
, PPCNONE
, {VD
, VA
, VB
}},
3214 {"vctuxs", VX (4, 906), VX_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VB
, UIMM
}},
3215 {"vcfpuxws", VX (4, 906), VX_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VB
, UIMM
}},
3216 {"vspltisw", VX (4, 908), VXVB_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, SIMM
}},
3217 {"maclhwsu", XO (4, 460,0,0),XO_MASK
, MULHW
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
3218 {"maclhwsu.", XO (4, 460,0,1),XO_MASK
, MULHW
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
3219 {"vminsd", VX (4, 962), VX_MASK
, PPCVEC2
, PPCNONE
, {VD
, VA
, VB
}},
3220 {"vsrad", VX (4, 964), VX_MASK
, PPCVEC2
, PPCNONE
, {VD
, VA
, VB
}},
3221 {"vcmpbfp", VXR(4, 966,0), VXR_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
3222 {"vcmpgtsd", VXR(4, 967,0), VXR_MASK
, PPCVEC2
, PPCNONE
, {VD
, VA
, VB
}},
3223 {"vctsxs", VX (4, 970), VX_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VB
, UIMM
}},
3224 {"vcfpsxws", VX (4, 970), VX_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VB
, UIMM
}},
3225 {"vupklpx", VX (4, 974), VXVA_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VB
}},
3226 {"maclhws", XO (4, 492,0,0),XO_MASK
, MULHW
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
3227 {"maclhws.", XO (4, 492,0,1),XO_MASK
, MULHW
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
3228 {"nmaclhws", XO (4, 494,0,0),XO_MASK
, MULHW
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
3229 {"nmaclhws.", XO (4, 494,0,1),XO_MASK
, MULHW
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
3230 {"vsububm", VX (4,1024), VX_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
3231 {"bcdadd.", VX (4,1025), VXPS_MASK
, PPCVEC2
, PPCNONE
, {VD
, VA
, VB
, PS
}},
3232 {"vavgub", VX (4,1026), VX_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
3233 {"vabsdub", VX (4,1027), VX_MASK
, PPCVEC2
, PPCNONE
, {VD
, VA
, VB
}},
3234 {"evmhessf", VX (4,1027), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3235 {"vand", VX (4,1028), VX_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
3236 {"vcmpequb.", VXR(4, 6,1), VXR_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
3237 {"udi0fcm.", APU(4, 515,0), APU_MASK
, PPC405
|PPC440
, PPC476
, {URT
, URA
, URB
}},
3238 {"udi0fcm", APU(4, 515,1), APU_MASK
, PPC405
|PPC440
, PPC476
, {URT
, URA
, URB
}},
3239 {"evmhossf", VX (4,1031), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3240 {"vpmsumb", VX (4,1032), VX_MASK
, PPCVEC2
, PPCNONE
, {VD
, VA
, VB
}},
3241 {"evmheumi", VX (4,1032), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3242 {"evmhesmi", VX (4,1033), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3243 {"vmaxfp", VX (4,1034), VX_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
3244 {"evmhesmf", VX (4,1035), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3245 {"evmhoumi", VX (4,1036), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3246 {"vslo", VX (4,1036), VX_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
3247 {"evmhosmi", VX (4,1037), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3248 {"evmhosmf", VX (4,1039), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3249 {"machhwuo", XO (4, 12,1,0),XO_MASK
, MULHW
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
3250 {"machhwuo.", XO (4, 12,1,1),XO_MASK
, MULHW
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
3251 {"ps_merge00", XOPS(4,528,0), XOPS_MASK
, PPCPS
, PPCNONE
, {FRT
, FRA
, FRB
}},
3252 {"ps_merge00.", XOPS(4,528,1), XOPS_MASK
, PPCPS
, PPCNONE
, {FRT
, FRA
, FRB
}},
3253 {"evmhessfa", VX (4,1059), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3254 {"evmhossfa", VX (4,1063), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3255 {"evmheumia", VX (4,1064), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3256 {"evmhesmia", VX (4,1065), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3257 {"evmhesmfa", VX (4,1067), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3258 {"evmhoumia", VX (4,1068), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3259 {"evmhosmia", VX (4,1069), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3260 {"evmhosmfa", VX (4,1071), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3261 {"vsubuhm", VX (4,1088), VX_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
3262 {"bcdsub.", VX (4,1089), VXPS_MASK
, PPCVEC2
, PPCNONE
, {VD
, VA
, VB
, PS
}},
3263 {"vavguh", VX (4,1090), VX_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
3264 {"vabsduh", VX (4,1091), VX_MASK
, PPCVEC2
, PPCNONE
, {VD
, VA
, VB
}},
3265 {"vandc", VX (4,1092), VX_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
3266 {"vcmpequh.", VXR(4, 70,1), VXR_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
3267 {"udi1fcm.", APU(4, 547,0), APU_MASK
, PPC405
|PPC440
, PPC476
, {URT
, URA
, URB
}},
3268 {"udi1fcm", APU(4, 547,1), APU_MASK
, PPC405
|PPC440
, PPC476
, {URT
, URA
, URB
}},
3269 {"evmwhssf", VX (4,1095), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3270 {"vpmsumh", VX (4,1096), VX_MASK
, PPCVEC2
, PPCNONE
, {VD
, VA
, VB
}},
3271 {"evmwlumi", VX (4,1096), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3272 {"vminfp", VX (4,1098), VX_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
3273 {"evmwhumi", VX (4,1100), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3274 {"vsro", VX (4,1100), VX_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
3275 {"evmwhsmi", VX (4,1101), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3276 {"vpkudum", VX (4,1102), VX_MASK
, PPCVEC2
, PPCNONE
, {VD
, VA
, VB
}},
3277 {"evmwhsmf", VX (4,1103), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3278 {"evmwssf", VX (4,1107), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3279 {"machhwo", XO (4, 44,1,0),XO_MASK
, MULHW
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
3280 {"evmwumi", VX (4,1112), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3281 {"machhwo.", XO (4, 44,1,1),XO_MASK
, MULHW
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
3282 {"evmwsmi", VX (4,1113), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3283 {"evmwsmf", VX (4,1115), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3284 {"nmachhwo", XO (4, 46,1,0),XO_MASK
, MULHW
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
3285 {"nmachhwo.", XO (4, 46,1,1),XO_MASK
, MULHW
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
3286 {"ps_merge01", XOPS(4,560,0), XOPS_MASK
, PPCPS
, PPCNONE
, {FRT
, FRA
, FRB
}},
3287 {"ps_merge01.", XOPS(4,560,1), XOPS_MASK
, PPCPS
, PPCNONE
, {FRT
, FRA
, FRB
}},
3288 {"evmwhssfa", VX (4,1127), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3289 {"evmwlumia", VX (4,1128), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3290 {"evmwhumia", VX (4,1132), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3291 {"evmwhsmia", VX (4,1133), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3292 {"evmwhsmfa", VX (4,1135), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3293 {"evmwssfa", VX (4,1139), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3294 {"evmwumia", VX (4,1144), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3295 {"evmwsmia", VX (4,1145), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3296 {"evmwsmfa", VX (4,1147), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3297 {"vsubuwm", VX (4,1152), VX_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
3298 {"vavguw", VX (4,1154), VX_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
3299 {"vabsduw", VX (4,1155), VX_MASK
, PPCVEC2
, PPCNONE
, {VD
, VA
, VB
}},
3300 {"vmr", VX (4,1156), VX_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VBA
}},
3301 {"vor", VX (4,1156), VX_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
3302 {"vpmsumw", VX (4,1160), VX_MASK
, PPCVEC2
, PPCNONE
, {VD
, VA
, VB
}},
3303 {"vcmpequw.", VXR(4, 134,1), VXR_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
3304 {"udi2fcm.", APU(4, 579,0), APU_MASK
, PPC405
|PPC440
, PPC476
, {URT
, URA
, URB
}},
3305 {"udi2fcm", APU(4, 579,1), APU_MASK
, PPC405
|PPC440
, PPC476
, {URT
, URA
, URB
}},
3306 {"machhwsuo", XO (4, 76,1,0),XO_MASK
, MULHW
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
3307 {"machhwsuo.", XO (4, 76,1,1),XO_MASK
, MULHW
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
3308 {"ps_merge10", XOPS(4,592,0), XOPS_MASK
, PPCPS
, PPCNONE
, {FRT
, FRA
, FRB
}},
3309 {"ps_merge10.", XOPS(4,592,1), XOPS_MASK
, PPCPS
, PPCNONE
, {FRT
, FRA
, FRB
}},
3310 {"vsubudm", VX (4,1216), VX_MASK
, PPCVEC2
, PPCNONE
, {VD
, VA
, VB
}},
3311 {"evaddusiaaw", VX (4,1216), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
}},
3312 {"evaddssiaaw", VX (4,1217), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
}},
3313 {"evsubfusiaaw",VX (4,1218), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
}},
3314 {"evsubfssiaaw",VX (4,1219), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
}},
3315 {"evmra", VX (4,1220), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
}},
3316 {"vxor", VX (4,1220), VX_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
3317 {"evdivws", VX (4,1222), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3318 {"vcmpeqfp.", VXR(4, 198,1), VXR_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
3319 {"udi3fcm.", APU(4, 611,0), APU_MASK
, PPC405
|PPC440
, PPC476
, {URT
, URA
, URB
}},
3320 {"vcmpequd.", VXR(4, 199,1), VXR_MASK
, PPCVEC2
, PPCNONE
, {VD
, VA
, VB
}},
3321 {"udi3fcm", APU(4, 611,1), APU_MASK
, PPC405
|PPC440
, PPC476
, {URT
, URA
, URB
}},
3322 {"evdivwu", VX (4,1223), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3323 {"vpmsumd", VX (4,1224), VX_MASK
, PPCVEC2
, PPCNONE
, {VD
, VA
, VB
}},
3324 {"evaddumiaaw", VX (4,1224), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
}},
3325 {"evaddsmiaaw", VX (4,1225), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
}},
3326 {"evsubfumiaaw",VX (4,1226), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
}},
3327 {"evsubfsmiaaw",VX (4,1227), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
}},
3328 {"vpkudus", VX (4,1230), VX_MASK
, PPCVEC2
, PPCNONE
, {VD
, VA
, VB
}},
3329 {"machhwso", XO (4, 108,1,0),XO_MASK
, MULHW
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
3330 {"machhwso.", XO (4, 108,1,1),XO_MASK
, MULHW
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
3331 {"nmachhwso", XO (4, 110,1,0),XO_MASK
, MULHW
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
3332 {"nmachhwso.", XO (4, 110,1,1),XO_MASK
, MULHW
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
3333 {"ps_merge11", XOPS(4,624,0), XOPS_MASK
, PPCPS
, PPCNONE
, {FRT
, FRA
, FRB
}},
3334 {"ps_merge11.", XOPS(4,624,1), XOPS_MASK
, PPCPS
, PPCNONE
, {FRT
, FRA
, FRB
}},
3335 {"vsubuqm", VX (4,1280), VX_MASK
, PPCVEC2
, PPCNONE
, {VD
, VA
, VB
}},
3336 {"evmheusiaaw", VX (4,1280), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3337 {"evmhessiaaw", VX (4,1281), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3338 {"vavgsb", VX (4,1282), VX_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
3339 {"evmhessfaaw", VX (4,1283), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3340 {"evmhousiaaw", VX (4,1284), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3341 {"vnot", VX (4,1284), VX_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VBA
}},
3342 {"vnor", VX (4,1284), VX_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
3343 {"evmhossiaaw", VX (4,1285), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3344 {"udi4fcm.", APU(4, 643,0), APU_MASK
, PPC405
|PPC440
, PPC476
, {URT
, URA
, URB
}},
3345 {"udi4fcm", APU(4, 643,1), APU_MASK
, PPC405
|PPC440
, PPC476
, {URT
, URA
, URB
}},
3346 {"evmhossfaaw", VX (4,1287), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3347 {"evmheumiaaw", VX (4,1288), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3348 {"vcipher", VX (4,1288), VX_MASK
, PPCVEC2
, PPCNONE
, {VD
, VA
, VB
}},
3349 {"vcipherlast", VX (4,1289), VX_MASK
, PPCVEC2
, PPCNONE
, {VD
, VA
, VB
}},
3350 {"evmhesmiaaw", VX (4,1289), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3351 {"evmhesmfaaw", VX (4,1291), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3352 {"vgbbd", VX (4,1292), VXVA_MASK
, PPCVEC2
, PPCNONE
, {VD
, VB
}},
3353 {"evmhoumiaaw", VX (4,1292), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3354 {"evmhosmiaaw", VX (4,1293), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3355 {"evmhosmfaaw", VX (4,1295), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3356 {"macchwuo", XO (4, 140,1,0),XO_MASK
, MULHW
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
3357 {"macchwuo.", XO (4, 140,1,1),XO_MASK
, MULHW
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
3358 {"evmhegumiaa", VX (4,1320), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3359 {"evmhegsmiaa", VX (4,1321), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3360 {"evmhegsmfaa", VX (4,1323), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3361 {"evmhogumiaa", VX (4,1324), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3362 {"evmhogsmiaa", VX (4,1325), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3363 {"evmhogsmfaa", VX (4,1327), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3364 {"vsubcuq", VX (4,1344), VX_MASK
, PPCVEC2
, PPCNONE
, {VD
, VA
, VB
}},
3365 {"evmwlusiaaw", VX (4,1344), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3366 {"evmwlssiaaw", VX (4,1345), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3367 {"vavgsh", VX (4,1346), VX_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
3368 {"vorc", VX (4,1348), VX_MASK
, PPCVEC2
, PPCNONE
, {VD
, VA
, VB
}},
3369 {"udi5fcm.", APU(4, 675,0), APU_MASK
, PPC405
|PPC440
, PPC476
, {URT
, URA
, URB
}},
3370 {"udi5fcm", APU(4, 675,1), APU_MASK
, PPC405
|PPC440
, PPC476
, {URT
, URA
, URB
}},
3371 {"vncipher", VX (4,1352), VX_MASK
, PPCVEC2
, PPCNONE
, {VD
, VA
, VB
}},
3372 {"evmwlumiaaw", VX (4,1352), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3373 {"vncipherlast",VX (4,1353), VX_MASK
, PPCVEC2
, PPCNONE
, {VD
, VA
, VB
}},
3374 {"evmwlsmiaaw", VX (4,1353), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3375 {"vbpermq", VX (4,1356), VX_MASK
, PPCVEC2
, PPCNONE
, {VD
, VA
, VB
}},
3376 {"vpksdus", VX (4,1358), VX_MASK
, PPCVEC2
, PPCNONE
, {VD
, VA
, VB
}},
3377 {"evmwssfaa", VX (4,1363), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3378 {"macchwo", XO (4, 172,1,0),XO_MASK
, MULHW
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
3379 {"evmwumiaa", VX (4,1368), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3380 {"macchwo.", XO (4, 172,1,1),XO_MASK
, MULHW
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
3381 {"evmwsmiaa", VX (4,1369), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3382 {"evmwsmfaa", VX (4,1371), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3383 {"nmacchwo", XO (4, 174,1,0),XO_MASK
, MULHW
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
3384 {"nmacchwo.", XO (4, 174,1,1),XO_MASK
, MULHW
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
3385 {"evmheusianw", VX (4,1408), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3386 {"vsubcuw", VX (4,1408), VX_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
3387 {"evmhessianw", VX (4,1409), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3388 {"vavgsw", VX (4,1410), VX_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
3389 {"evmhessfanw", VX (4,1411), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3390 {"vnand", VX (4,1412), VX_MASK
, PPCVEC2
, PPCNONE
, {VD
, VA
, VB
}},
3391 {"evmhousianw", VX (4,1412), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3392 {"evmhossianw", VX (4,1413), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3393 {"udi6fcm.", APU(4, 707,0), APU_MASK
, PPC405
|PPC440
, PPC476
, {URT
, URA
, URB
}},
3394 {"udi6fcm", APU(4, 707,1), APU_MASK
, PPC405
|PPC440
, PPC476
, {URT
, URA
, URB
}},
3395 {"evmhossfanw", VX (4,1415), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3396 {"evmheumianw", VX (4,1416), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3397 {"evmhesmianw", VX (4,1417), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3398 {"evmhesmfanw", VX (4,1419), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3399 {"evmhoumianw", VX (4,1420), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3400 {"evmhosmianw", VX (4,1421), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3401 {"evmhosmfanw", VX (4,1423), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3402 {"macchwsuo", XO (4, 204,1,0),XO_MASK
, MULHW
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
3403 {"macchwsuo.", XO (4, 204,1,1),XO_MASK
, MULHW
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
3404 {"evmhegumian", VX (4,1448), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3405 {"evmhegsmian", VX (4,1449), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3406 {"evmhegsmfan", VX (4,1451), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3407 {"evmhogumian", VX (4,1452), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3408 {"evmhogsmian", VX (4,1453), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3409 {"evmhogsmfan", VX (4,1455), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3410 {"evmwlusianw", VX (4,1472), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3411 {"evmwlssianw", VX (4,1473), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3412 {"vsld", VX (4,1476), VX_MASK
, PPCVEC2
, PPCNONE
, {VD
, VA
, VB
}},
3413 {"vcmpgefp.", VXR(4, 454,1), VXR_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
3414 {"udi7fcm.", APU(4, 739,0), APU_MASK
, PPC405
|PPC440
, PPC476
, {URT
, URA
, URB
}},
3415 {"udi7fcm", APU(4, 739,1), APU_MASK
, PPC405
|PPC440
, PPC476
, {URT
, URA
, URB
}},
3416 {"vsbox", VX (4,1480), VXVB_MASK
, PPCVEC2
, PPCNONE
, {VD
, VA
}},
3417 {"evmwlumianw", VX (4,1480), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3418 {"evmwlsmianw", VX (4,1481), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3419 {"vpksdss", VX (4,1486), VX_MASK
, PPCVEC2
, PPCNONE
, {VD
, VA
, VB
}},
3420 {"evmwssfan", VX (4,1491), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3421 {"macchwso", XO (4, 236,1,0),XO_MASK
, MULHW
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
3422 {"evmwumian", VX (4,1496), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3423 {"macchwso.", XO (4, 236,1,1),XO_MASK
, MULHW
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
3424 {"evmwsmian", VX (4,1497), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3425 {"evmwsmfan", VX (4,1499), VX_MASK
, PPCSPE
|PPCVLE
, PPCNONE
, {RS
, RA
, RB
}},
3426 {"nmacchwso", XO (4, 238,1,0),XO_MASK
, MULHW
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
3427 {"nmacchwso.", XO (4, 238,1,1),XO_MASK
, MULHW
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
3428 {"vsububs", VX (4,1536), VX_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
3429 {"mfvscr", VX (4,1540), VXVAVB_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
}},
3430 {"vcmpgtub.", VXR(4, 518,1), VXR_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
3431 {"udi8fcm.", APU(4, 771,0), APU_MASK
, PPC440
, PPC476
, {URT
, URA
, URB
}},
3432 {"udi8fcm", APU(4, 771,1), APU_MASK
, PPC440
, PPC476
, {URT
, URA
, URB
}},
3433 {"vsum4ubs", VX (4,1544), VX_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
3434 {"vsubuhs", VX (4,1600), VX_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
3435 {"mtvscr", VX (4,1604), VXVDVA_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VB
}},
3436 {"vcmpgtuh.", VXR(4, 582,1), VXR_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
3437 {"vsum4shs", VX (4,1608), VX_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
3438 {"udi9fcm.", APU(4, 804,0), APU_MASK
, PPC440
, PPC476
, {URT
, URA
, URB
}},
3439 {"udi9fcm", APU(4, 804,1), APU_MASK
, PPC440
, PPC476
, {URT
, URA
, URB
}},
3440 {"vupkhsw", VX (4,1614), VXVA_MASK
, PPCVEC2
, PPCNONE
, {VD
, VB
}},
3441 {"vsubuws", VX (4,1664), VX_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
3442 {"vshasigmaw", VX (4,1666), VX_MASK
, PPCVEC2
, PPCNONE
, {VD
, VA
, ST
, SIX
}},
3443 {"veqv", VX (4,1668), VX_MASK
, PPCVEC2
, PPCNONE
, {VD
, VA
, VB
}},
3444 {"vcmpgtuw.", VXR(4, 646,1), VXR_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
3445 {"udi10fcm.", APU(4, 835,0), APU_MASK
, PPC440
, PPC476
, {URT
, URA
, URB
}},
3446 {"udi10fcm", APU(4, 835,1), APU_MASK
, PPC440
, PPC476
, {URT
, URA
, URB
}},
3447 {"vsum2sws", VX (4,1672), VX_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
3448 {"vmrgow", VX (4,1676), VX_MASK
, PPCVEC2
, PPCNONE
, {VD
, VA
, VB
}},
3449 {"vshasigmad", VX (4,1730), VX_MASK
, PPCVEC2
, PPCNONE
, {VD
, VA
, ST
, SIX
}},
3450 {"vsrd", VX (4,1732), VX_MASK
, PPCVEC2
, PPCNONE
, {VD
, VA
, VB
}},
3451 {"vcmpgtfp.", VXR(4, 710,1), VXR_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
3452 {"udi11fcm.", APU(4, 867,0), APU_MASK
, PPC440
, PPC476
, {URT
, URA
, URB
}},
3453 {"vcmpgtud.", VXR(4, 711,1), VXR_MASK
, PPCVEC2
, PPCNONE
, {VD
, VA
, VB
}},
3454 {"udi11fcm", APU(4, 867,1), APU_MASK
, PPC440
, PPC476
, {URT
, URA
, URB
}},
3455 {"vupklsw", VX (4,1742), VXVA_MASK
, PPCVEC2
, PPCNONE
, {VD
, VB
}},
3456 {"vsubsbs", VX (4,1792), VX_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
3457 {"vclzb", VX (4,1794), VXVA_MASK
, PPCVEC2
, PPCNONE
, {VD
, VB
}},
3458 {"vpopcntb", VX (4,1795), VXVA_MASK
, PPCVEC2
, PPCNONE
, {VD
, VB
}},
3459 {"vcmpgtsb.", VXR(4, 774,1), VXR_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
3460 {"udi12fcm.", APU(4, 899,0), APU_MASK
, PPC440
, PPC476
, {URT
, URA
, URB
}},
3461 {"udi12fcm", APU(4, 899,1), APU_MASK
, PPC440
, PPC476
, {URT
, URA
, URB
}},
3462 {"vsum4sbs", VX (4,1800), VX_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
3463 {"maclhwuo", XO (4, 396,1,0),XO_MASK
, MULHW
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
3464 {"maclhwuo.", XO (4, 396,1,1),XO_MASK
, MULHW
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
3465 {"vsubshs", VX (4,1856), VX_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
3466 {"vclzh", VX (4,1858), VXVA_MASK
, PPCVEC2
, PPCNONE
, {VD
, VB
}},
3467 {"vpopcnth", VX (4,1859), VXVA_MASK
, PPCVEC2
, PPCNONE
, {VD
, VB
}},
3468 {"vcmpgtsh.", VXR(4, 838,1), VXR_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
3469 {"udi13fcm.", APU(4, 931,0), APU_MASK
, PPC440
, PPC476
, {URT
, URA
, URB
}},
3470 {"udi13fcm", APU(4, 931,1), APU_MASK
, PPC440
, PPC476
, {URT
, URA
, URB
}},
3471 {"maclhwo", XO (4, 428,1,0),XO_MASK
, MULHW
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
3472 {"maclhwo.", XO (4, 428,1,1),XO_MASK
, MULHW
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
3473 {"nmaclhwo", XO (4, 430,1,0),XO_MASK
, MULHW
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
3474 {"nmaclhwo.", XO (4, 430,1,1),XO_MASK
, MULHW
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
3475 {"vsubsws", VX (4,1920), VX_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
3476 {"vclzw", VX (4,1922), VXVA_MASK
, PPCVEC2
, PPCNONE
, {VD
, VB
}},
3477 {"vpopcntw", VX (4,1923), VXVA_MASK
, PPCVEC2
, PPCNONE
, {VD
, VB
}},
3478 {"vcmpgtsw.", VXR(4, 902,1), VXR_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
3479 {"udi14fcm.", APU(4, 963,0), APU_MASK
, PPC440
, PPC476
, {URT
, URA
, URB
}},
3480 {"udi14fcm", APU(4, 963,1), APU_MASK
, PPC440
, PPC476
, {URT
, URA
, URB
}},
3481 {"vsumsws", VX (4,1928), VX_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, VA
, VB
}},
3482 {"vmrgew", VX (4,1932), VX_MASK
, PPCVEC2
, PPCNONE
, {VD
, VA
, VB
}},
3483 {"maclhwsuo", XO (4, 460,1,0),XO_MASK
, MULHW
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
3484 {"maclhwsuo.", XO (4, 460,1,1),XO_MASK
, MULHW
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
3485 {"vclzd", VX (4,1986), VXVA_MASK
, PPCVEC2
, PPCNONE
, {VD
, VB
}},
3486 {"vpopcntd", VX (4,1987), VXVA_MASK
, PPCVEC2
, PPCNONE
, {VD
, VB
}},
3487 {"vcmpbfp.", VXR(4, 966,1), VXR_MASK
, PPCVEC
, PPCNONE
, {VD
, VA
, VB
}},
3488 {"udi15fcm.", APU(4, 995,0), APU_MASK
, PPC440
, PPC476
, {URT
, URA
, URB
}},
3489 {"vcmpgtsd.", VXR(4, 967,1), VXR_MASK
, PPCVEC2
, PPCNONE
, {VD
, VA
, VB
}},
3490 {"udi15fcm", APU(4, 995,1), APU_MASK
, PPC440
, PPC476
, {URT
, URA
, URB
}},
3491 {"maclhwso", XO (4, 492,1,0),XO_MASK
, MULHW
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
3492 {"maclhwso.", XO (4, 492,1,1),XO_MASK
, MULHW
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
3493 {"nmaclhwso", XO (4, 494,1,0),XO_MASK
, MULHW
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
3494 {"nmaclhwso.", XO (4, 494,1,1),XO_MASK
, MULHW
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
3495 {"dcbz_l", X (4,1014), XRT_MASK
, PPCPS
, PPCNONE
, {RA
, RB
}},
3497 {"mulli", OP(7), OP_MASK
, PPCCOM
, PPCNONE
, {RT
, RA
, SI
}},
3498 {"muli", OP(7), OP_MASK
, PWRCOM
, PPCNONE
, {RT
, RA
, SI
}},
3500 {"subfic", OP(8), OP_MASK
, PPCCOM
, PPCNONE
, {RT
, RA
, SI
}},
3501 {"sfi", OP(8), OP_MASK
, PWRCOM
, PPCNONE
, {RT
, RA
, SI
}},
3503 {"dozi", OP(9), OP_MASK
, M601
, PPCNONE
, {RT
, RA
, SI
}},
3505 {"cmplwi", OPL(10,0), OPL_MASK
, PPCCOM
, PPCNONE
, {OBF
, RA
, UI
}},
3506 {"cmpldi", OPL(10,1), OPL_MASK
, PPC64
, PPCNONE
, {OBF
, RA
, UI
}},
3507 {"cmpli", OP(10), OP_MASK
, PPC
, PPCNONE
, {BF
, L
, RA
, UI
}},
3508 {"cmpli", OP(10), OP_MASK
, PWRCOM
, PPC
, {BF
, RA
, UI
}},
3510 {"cmpwi", OPL(11,0), OPL_MASK
, PPCCOM
, PPCNONE
, {OBF
, RA
, SI
}},
3511 {"cmpdi", OPL(11,1), OPL_MASK
, PPC64
, PPCNONE
, {OBF
, RA
, SI
}},
3512 {"cmpi", OP(11), OP_MASK
, PPC
, PPCNONE
, {BF
, L
, RA
, SI
}},
3513 {"cmpi", OP(11), OP_MASK
, PWRCOM
, PPC
, {BF
, RA
, SI
}},
3515 {"addic", OP(12), OP_MASK
, PPCCOM
, PPCNONE
, {RT
, RA
, SI
}},
3516 {"ai", OP(12), OP_MASK
, PWRCOM
, PPCNONE
, {RT
, RA
, SI
}},
3517 {"subic", OP(12), OP_MASK
, PPCCOM
, PPCNONE
, {RT
, RA
, NSI
}},
3519 {"addic.", OP(13), OP_MASK
, PPCCOM
, PPCNONE
, {RT
, RA
, SI
}},
3520 {"ai.", OP(13), OP_MASK
, PWRCOM
, PPCNONE
, {RT
, RA
, SI
}},
3521 {"subic.", OP(13), OP_MASK
, PPCCOM
, PPCNONE
, {RT
, RA
, NSI
}},
3523 {"li", OP(14), DRA_MASK
, PPCCOM
, PPCNONE
, {RT
, SI
}},
3524 {"lil", OP(14), DRA_MASK
, PWRCOM
, PPCNONE
, {RT
, SI
}},
3525 {"addi", OP(14), OP_MASK
, PPCCOM
, PPCNONE
, {RT
, RA0
, SI
}},
3526 {"cal", OP(14), OP_MASK
, PWRCOM
, PPCNONE
, {RT
, D
, RA0
}},
3527 {"subi", OP(14), OP_MASK
, PPCCOM
, PPCNONE
, {RT
, RA0
, NSI
}},
3528 {"la", OP(14), OP_MASK
, PPCCOM
, PPCNONE
, {RT
, D
, RA0
}},
3530 {"lis", OP(15), DRA_MASK
, PPCCOM
, PPCNONE
, {RT
, SISIGNOPT
}},
3531 {"liu", OP(15), DRA_MASK
, PWRCOM
, PPCNONE
, {RT
, SISIGNOPT
}},
3532 {"addis", OP(15), OP_MASK
, PPCCOM
, PPCNONE
, {RT
, RA0
, SISIGNOPT
}},
3533 {"cau", OP(15), OP_MASK
, PWRCOM
, PPCNONE
, {RT
, RA0
, SISIGNOPT
}},
3534 {"subis", OP(15), OP_MASK
, PPCCOM
, PPCNONE
, {RT
, RA0
, NSI
}},
3536 {"bdnz-", BBO(16,BODNZ
,0,0), BBOATBI_MASK
, PPCCOM
, PPCNONE
, {BDM
}},
3537 {"bdnz+", BBO(16,BODNZ
,0,0), BBOATBI_MASK
, PPCCOM
, PPCNONE
, {BDP
}},
3538 {"bdnz", BBO(16,BODNZ
,0,0), BBOATBI_MASK
, PPCCOM
, PPCNONE
, {BD
}},
3539 {"bdn", BBO(16,BODNZ
,0,0), BBOATBI_MASK
, PWRCOM
, PPCNONE
, {BD
}},
3540 {"bdnzl-", BBO(16,BODNZ
,0,1), BBOATBI_MASK
, PPCCOM
, PPCNONE
, {BDM
}},
3541 {"bdnzl+", BBO(16,BODNZ
,0,1), BBOATBI_MASK
, PPCCOM
, PPCNONE
, {BDP
}},
3542 {"bdnzl", BBO(16,BODNZ
,0,1), BBOATBI_MASK
, PPCCOM
, PPCNONE
, {BD
}},
3543 {"bdnl", BBO(16,BODNZ
,0,1), BBOATBI_MASK
, PWRCOM
, PPCNONE
, {BD
}},
3544 {"bdnza-", BBO(16,BODNZ
,1,0), BBOATBI_MASK
, PPCCOM
, PPCNONE
, {BDMA
}},
3545 {"bdnza+", BBO(16,BODNZ
,1,0), BBOATBI_MASK
, PPCCOM
, PPCNONE
, {BDPA
}},
3546 {"bdnza", BBO(16,BODNZ
,1,0), BBOATBI_MASK
, PPCCOM
, PPCNONE
, {BDA
}},
3547 {"bdna", BBO(16,BODNZ
,1,0), BBOATBI_MASK
, PWRCOM
, PPCNONE
, {BDA
}},
3548 {"bdnzla-", BBO(16,BODNZ
,1,1), BBOATBI_MASK
, PPCCOM
, PPCNONE
, {BDMA
}},
3549 {"bdnzla+", BBO(16,BODNZ
,1,1), BBOATBI_MASK
, PPCCOM
, PPCNONE
, {BDPA
}},
3550 {"bdnzla", BBO(16,BODNZ
,1,1), BBOATBI_MASK
, PPCCOM
, PPCNONE
, {BDA
}},
3551 {"bdnla", BBO(16,BODNZ
,1,1), BBOATBI_MASK
, PWRCOM
, PPCNONE
, {BDA
}},
3552 {"bdz-", BBO(16,BODZ
,0,0), BBOATBI_MASK
, PPCCOM
, PPCNONE
, {BDM
}},
3553 {"bdz+", BBO(16,BODZ
,0,0), BBOATBI_MASK
, PPCCOM
, PPCNONE
, {BDP
}},
3554 {"bdz", BBO(16,BODZ
,0,0), BBOATBI_MASK
, COM
, PPCNONE
, {BD
}},
3555 {"bdzl-", BBO(16,BODZ
,0,1), BBOATBI_MASK
, PPCCOM
, PPCNONE
, {BDM
}},
3556 {"bdzl+", BBO(16,BODZ
,0,1), BBOATBI_MASK
, PPCCOM
, PPCNONE
, {BDP
}},
3557 {"bdzl", BBO(16,BODZ
,0,1), BBOATBI_MASK
, COM
, PPCNONE
, {BD
}},
3558 {"bdza-", BBO(16,BODZ
,1,0), BBOATBI_MASK
, PPCCOM
, PPCNONE
, {BDMA
}},
3559 {"bdza+", BBO(16,BODZ
,1,0), BBOATBI_MASK
, PPCCOM
, PPCNONE
, {BDPA
}},
3560 {"bdza", BBO(16,BODZ
,1,0), BBOATBI_MASK
, COM
, PPCNONE
, {BDA
}},
3561 {"bdzla-", BBO(16,BODZ
,1,1), BBOATBI_MASK
, PPCCOM
, PPCNONE
, {BDMA
}},
3562 {"bdzla+", BBO(16,BODZ
,1,1), BBOATBI_MASK
, PPCCOM
, PPCNONE
, {BDPA
}},
3563 {"bdzla", BBO(16,BODZ
,1,1), BBOATBI_MASK
, COM
, PPCNONE
, {BDA
}},
3565 {"bge-", BBOCB(16,BOF
,CBLT
,0,0), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BDM
}},
3566 {"bge+", BBOCB(16,BOF
,CBLT
,0,0), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BDP
}},
3567 {"bge", BBOCB(16,BOF
,CBLT
,0,0), BBOATCB_MASK
, COM
, PPCNONE
, {CR
, BD
}},
3568 {"bnl-", BBOCB(16,BOF
,CBLT
,0,0), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BDM
}},
3569 {"bnl+", BBOCB(16,BOF
,CBLT
,0,0), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BDP
}},
3570 {"bnl", BBOCB(16,BOF
,CBLT
,0,0), BBOATCB_MASK
, COM
, PPCNONE
, {CR
, BD
}},
3571 {"bgel-", BBOCB(16,BOF
,CBLT
,0,1), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BDM
}},
3572 {"bgel+", BBOCB(16,BOF
,CBLT
,0,1), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BDP
}},
3573 {"bgel", BBOCB(16,BOF
,CBLT
,0,1), BBOATCB_MASK
, COM
, PPCNONE
, {CR
, BD
}},
3574 {"bnll-", BBOCB(16,BOF
,CBLT
,0,1), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BDM
}},
3575 {"bnll+", BBOCB(16,BOF
,CBLT
,0,1), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BDP
}},
3576 {"bnll", BBOCB(16,BOF
,CBLT
,0,1), BBOATCB_MASK
, COM
, PPCNONE
, {CR
, BD
}},
3577 {"bgea-", BBOCB(16,BOF
,CBLT
,1,0), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BDMA
}},
3578 {"bgea+", BBOCB(16,BOF
,CBLT
,1,0), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BDPA
}},
3579 {"bgea", BBOCB(16,BOF
,CBLT
,1,0), BBOATCB_MASK
, COM
, PPCNONE
, {CR
, BDA
}},
3580 {"bnla-", BBOCB(16,BOF
,CBLT
,1,0), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BDMA
}},
3581 {"bnla+", BBOCB(16,BOF
,CBLT
,1,0), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BDPA
}},
3582 {"bnla", BBOCB(16,BOF
,CBLT
,1,0), BBOATCB_MASK
, COM
, PPCNONE
, {CR
, BDA
}},
3583 {"bgela-", BBOCB(16,BOF
,CBLT
,1,1), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BDMA
}},
3584 {"bgela+", BBOCB(16,BOF
,CBLT
,1,1), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BDPA
}},
3585 {"bgela", BBOCB(16,BOF
,CBLT
,1,1), BBOATCB_MASK
, COM
, PPCNONE
, {CR
, BDA
}},
3586 {"bnlla-", BBOCB(16,BOF
,CBLT
,1,1), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BDMA
}},
3587 {"bnlla+", BBOCB(16,BOF
,CBLT
,1,1), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BDPA
}},
3588 {"bnlla", BBOCB(16,BOF
,CBLT
,1,1), BBOATCB_MASK
, COM
, PPCNONE
, {CR
, BDA
}},
3589 {"ble-", BBOCB(16,BOF
,CBGT
,0,0), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BDM
}},
3590 {"ble+", BBOCB(16,BOF
,CBGT
,0,0), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BDP
}},
3591 {"ble", BBOCB(16,BOF
,CBGT
,0,0), BBOATCB_MASK
, COM
, PPCNONE
, {CR
, BD
}},
3592 {"bng-", BBOCB(16,BOF
,CBGT
,0,0), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BDM
}},
3593 {"bng+", BBOCB(16,BOF
,CBGT
,0,0), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BDP
}},
3594 {"bng", BBOCB(16,BOF
,CBGT
,0,0), BBOATCB_MASK
, COM
, PPCNONE
, {CR
, BD
}},
3595 {"blel-", BBOCB(16,BOF
,CBGT
,0,1), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BDM
}},
3596 {"blel+", BBOCB(16,BOF
,CBGT
,0,1), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BDP
}},
3597 {"blel", BBOCB(16,BOF
,CBGT
,0,1), BBOATCB_MASK
, COM
, PPCNONE
, {CR
, BD
}},
3598 {"bngl-", BBOCB(16,BOF
,CBGT
,0,1), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BDM
}},
3599 {"bngl+", BBOCB(16,BOF
,CBGT
,0,1), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BDP
}},
3600 {"bngl", BBOCB(16,BOF
,CBGT
,0,1), BBOATCB_MASK
, COM
, PPCNONE
, {CR
, BD
}},
3601 {"blea-", BBOCB(16,BOF
,CBGT
,1,0), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BDMA
}},
3602 {"blea+", BBOCB(16,BOF
,CBGT
,1,0), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BDPA
}},
3603 {"blea", BBOCB(16,BOF
,CBGT
,1,0), BBOATCB_MASK
, COM
, PPCNONE
, {CR
, BDA
}},
3604 {"bnga-", BBOCB(16,BOF
,CBGT
,1,0), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BDMA
}},
3605 {"bnga+", BBOCB(16,BOF
,CBGT
,1,0), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BDPA
}},
3606 {"bnga", BBOCB(16,BOF
,CBGT
,1,0), BBOATCB_MASK
, COM
, PPCNONE
, {CR
, BDA
}},
3607 {"blela-", BBOCB(16,BOF
,CBGT
,1,1), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BDMA
}},
3608 {"blela+", BBOCB(16,BOF
,CBGT
,1,1), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BDPA
}},
3609 {"blela", BBOCB(16,BOF
,CBGT
,1,1), BBOATCB_MASK
, COM
, PPCNONE
, {CR
, BDA
}},
3610 {"bngla-", BBOCB(16,BOF
,CBGT
,1,1), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BDMA
}},
3611 {"bngla+", BBOCB(16,BOF
,CBGT
,1,1), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BDPA
}},
3612 {"bngla", BBOCB(16,BOF
,CBGT
,1,1), BBOATCB_MASK
, COM
, PPCNONE
, {CR
, BDA
}},
3613 {"bne-", BBOCB(16,BOF
,CBEQ
,0,0), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BDM
}},
3614 {"bne+", BBOCB(16,BOF
,CBEQ
,0,0), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BDP
}},
3615 {"bne", BBOCB(16,BOF
,CBEQ
,0,0), BBOATCB_MASK
, COM
, PPCNONE
, {CR
, BD
}},
3616 {"bnel-", BBOCB(16,BOF
,CBEQ
,0,1), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BDM
}},
3617 {"bnel+", BBOCB(16,BOF
,CBEQ
,0,1), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BDP
}},
3618 {"bnel", BBOCB(16,BOF
,CBEQ
,0,1), BBOATCB_MASK
, COM
, PPCNONE
, {CR
, BD
}},
3619 {"bnea-", BBOCB(16,BOF
,CBEQ
,1,0), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BDMA
}},
3620 {"bnea+", BBOCB(16,BOF
,CBEQ
,1,0), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BDPA
}},
3621 {"bnea", BBOCB(16,BOF
,CBEQ
,1,0), BBOATCB_MASK
, COM
, PPCNONE
, {CR
, BDA
}},
3622 {"bnela-", BBOCB(16,BOF
,CBEQ
,1,1), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BDMA
}},
3623 {"bnela+", BBOCB(16,BOF
,CBEQ
,1,1), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BDPA
}},
3624 {"bnela", BBOCB(16,BOF
,CBEQ
,1,1), BBOATCB_MASK
, COM
, PPCNONE
, {CR
, BDA
}},
3625 {"bns-", BBOCB(16,BOF
,CBSO
,0,0), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BDM
}},
3626 {"bns+", BBOCB(16,BOF
,CBSO
,0,0), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BDP
}},
3627 {"bns", BBOCB(16,BOF
,CBSO
,0,0), BBOATCB_MASK
, COM
, PPCNONE
, {CR
, BD
}},
3628 {"bnu-", BBOCB(16,BOF
,CBSO
,0,0), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BDM
}},
3629 {"bnu+", BBOCB(16,BOF
,CBSO
,0,0), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BDP
}},
3630 {"bnu", BBOCB(16,BOF
,CBSO
,0,0), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BD
}},
3631 {"bnsl-", BBOCB(16,BOF
,CBSO
,0,1), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BDM
}},
3632 {"bnsl+", BBOCB(16,BOF
,CBSO
,0,1), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BDP
}},
3633 {"bnsl", BBOCB(16,BOF
,CBSO
,0,1), BBOATCB_MASK
, COM
, PPCNONE
, {CR
, BD
}},
3634 {"bnul-", BBOCB(16,BOF
,CBSO
,0,1), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BDM
}},
3635 {"bnul+", BBOCB(16,BOF
,CBSO
,0,1), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BDP
}},
3636 {"bnul", BBOCB(16,BOF
,CBSO
,0,1), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BD
}},
3637 {"bnsa-", BBOCB(16,BOF
,CBSO
,1,0), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BDMA
}},
3638 {"bnsa+", BBOCB(16,BOF
,CBSO
,1,0), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BDPA
}},
3639 {"bnsa", BBOCB(16,BOF
,CBSO
,1,0), BBOATCB_MASK
, COM
, PPCNONE
, {CR
, BDA
}},
3640 {"bnua-", BBOCB(16,BOF
,CBSO
,1,0), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BDMA
}},
3641 {"bnua+", BBOCB(16,BOF
,CBSO
,1,0), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BDPA
}},
3642 {"bnua", BBOCB(16,BOF
,CBSO
,1,0), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BDA
}},
3643 {"bnsla-", BBOCB(16,BOF
,CBSO
,1,1), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BDMA
}},
3644 {"bnsla+", BBOCB(16,BOF
,CBSO
,1,1), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BDPA
}},
3645 {"bnsla", BBOCB(16,BOF
,CBSO
,1,1), BBOATCB_MASK
, COM
, PPCNONE
, {CR
, BDA
}},
3646 {"bnula-", BBOCB(16,BOF
,CBSO
,1,1), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BDMA
}},
3647 {"bnula+", BBOCB(16,BOF
,CBSO
,1,1), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BDPA
}},
3648 {"bnula", BBOCB(16,BOF
,CBSO
,1,1), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BDA
}},
3650 {"blt-", BBOCB(16,BOT
,CBLT
,0,0), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BDM
}},
3651 {"blt+", BBOCB(16,BOT
,CBLT
,0,0), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BDP
}},
3652 {"blt", BBOCB(16,BOT
,CBLT
,0,0), BBOATCB_MASK
, COM
, PPCNONE
, {CR
, BD
}},
3653 {"bltl-", BBOCB(16,BOT
,CBLT
,0,1), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BDM
}},
3654 {"bltl+", BBOCB(16,BOT
,CBLT
,0,1), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BDP
}},
3655 {"bltl", BBOCB(16,BOT
,CBLT
,0,1), BBOATCB_MASK
, COM
, PPCNONE
, {CR
, BD
}},
3656 {"blta-", BBOCB(16,BOT
,CBLT
,1,0), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BDMA
}},
3657 {"blta+", BBOCB(16,BOT
,CBLT
,1,0), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BDPA
}},
3658 {"blta", BBOCB(16,BOT
,CBLT
,1,0), BBOATCB_MASK
, COM
, PPCNONE
, {CR
, BDA
}},
3659 {"bltla-", BBOCB(16,BOT
,CBLT
,1,1), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BDMA
}},
3660 {"bltla+", BBOCB(16,BOT
,CBLT
,1,1), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BDPA
}},
3661 {"bltla", BBOCB(16,BOT
,CBLT
,1,1), BBOATCB_MASK
, COM
, PPCNONE
, {CR
, BDA
}},
3662 {"bgt-", BBOCB(16,BOT
,CBGT
,0,0), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BDM
}},
3663 {"bgt+", BBOCB(16,BOT
,CBGT
,0,0), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BDP
}},
3664 {"bgt", BBOCB(16,BOT
,CBGT
,0,0), BBOATCB_MASK
, COM
, PPCNONE
, {CR
, BD
}},
3665 {"bgtl-", BBOCB(16,BOT
,CBGT
,0,1), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BDM
}},
3666 {"bgtl+", BBOCB(16,BOT
,CBGT
,0,1), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BDP
}},
3667 {"bgtl", BBOCB(16,BOT
,CBGT
,0,1), BBOATCB_MASK
, COM
, PPCNONE
, {CR
, BD
}},
3668 {"bgta-", BBOCB(16,BOT
,CBGT
,1,0), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BDMA
}},
3669 {"bgta+", BBOCB(16,BOT
,CBGT
,1,0), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BDPA
}},
3670 {"bgta", BBOCB(16,BOT
,CBGT
,1,0), BBOATCB_MASK
, COM
, PPCNONE
, {CR
, BDA
}},
3671 {"bgtla-", BBOCB(16,BOT
,CBGT
,1,1), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BDMA
}},
3672 {"bgtla+", BBOCB(16,BOT
,CBGT
,1,1), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BDPA
}},
3673 {"bgtla", BBOCB(16,BOT
,CBGT
,1,1), BBOATCB_MASK
, COM
, PPCNONE
, {CR
, BDA
}},
3674 {"beq-", BBOCB(16,BOT
,CBEQ
,0,0), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BDM
}},
3675 {"beq+", BBOCB(16,BOT
,CBEQ
,0,0), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BDP
}},
3676 {"beq", BBOCB(16,BOT
,CBEQ
,0,0), BBOATCB_MASK
, COM
, PPCNONE
, {CR
, BD
}},
3677 {"beql-", BBOCB(16,BOT
,CBEQ
,0,1), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BDM
}},
3678 {"beql+", BBOCB(16,BOT
,CBEQ
,0,1), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BDP
}},
3679 {"beql", BBOCB(16,BOT
,CBEQ
,0,1), BBOATCB_MASK
, COM
, PPCNONE
, {CR
, BD
}},
3680 {"beqa-", BBOCB(16,BOT
,CBEQ
,1,0), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BDMA
}},
3681 {"beqa+", BBOCB(16,BOT
,CBEQ
,1,0), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BDPA
}},
3682 {"beqa", BBOCB(16,BOT
,CBEQ
,1,0), BBOATCB_MASK
, COM
, PPCNONE
, {CR
, BDA
}},
3683 {"beqla-", BBOCB(16,BOT
,CBEQ
,1,1), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BDMA
}},
3684 {"beqla+", BBOCB(16,BOT
,CBEQ
,1,1), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BDPA
}},
3685 {"beqla", BBOCB(16,BOT
,CBEQ
,1,1), BBOATCB_MASK
, COM
, PPCNONE
, {CR
, BDA
}},
3686 {"bso-", BBOCB(16,BOT
,CBSO
,0,0), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BDM
}},
3687 {"bso+", BBOCB(16,BOT
,CBSO
,0,0), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BDP
}},
3688 {"bso", BBOCB(16,BOT
,CBSO
,0,0), BBOATCB_MASK
, COM
, PPCNONE
, {CR
, BD
}},
3689 {"bun-", BBOCB(16,BOT
,CBSO
,0,0), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BDM
}},
3690 {"bun+", BBOCB(16,BOT
,CBSO
,0,0), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BDP
}},
3691 {"bun", BBOCB(16,BOT
,CBSO
,0,0), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BD
}},
3692 {"bsol-", BBOCB(16,BOT
,CBSO
,0,1), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BDM
}},
3693 {"bsol+", BBOCB(16,BOT
,CBSO
,0,1), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BDP
}},
3694 {"bsol", BBOCB(16,BOT
,CBSO
,0,1), BBOATCB_MASK
, COM
, PPCNONE
, {CR
, BD
}},
3695 {"bunl-", BBOCB(16,BOT
,CBSO
,0,1), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BDM
}},
3696 {"bunl+", BBOCB(16,BOT
,CBSO
,0,1), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BDP
}},
3697 {"bunl", BBOCB(16,BOT
,CBSO
,0,1), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BD
}},
3698 {"bsoa-", BBOCB(16,BOT
,CBSO
,1,0), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BDMA
}},
3699 {"bsoa+", BBOCB(16,BOT
,CBSO
,1,0), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BDPA
}},
3700 {"bsoa", BBOCB(16,BOT
,CBSO
,1,0), BBOATCB_MASK
, COM
, PPCNONE
, {CR
, BDA
}},
3701 {"buna-", BBOCB(16,BOT
,CBSO
,1,0), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BDMA
}},
3702 {"buna+", BBOCB(16,BOT
,CBSO
,1,0), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BDPA
}},
3703 {"buna", BBOCB(16,BOT
,CBSO
,1,0), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BDA
}},
3704 {"bsola-", BBOCB(16,BOT
,CBSO
,1,1), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BDMA
}},
3705 {"bsola+", BBOCB(16,BOT
,CBSO
,1,1), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BDPA
}},
3706 {"bsola", BBOCB(16,BOT
,CBSO
,1,1), BBOATCB_MASK
, COM
, PPCNONE
, {CR
, BDA
}},
3707 {"bunla-", BBOCB(16,BOT
,CBSO
,1,1), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BDMA
}},
3708 {"bunla+", BBOCB(16,BOT
,CBSO
,1,1), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BDPA
}},
3709 {"bunla", BBOCB(16,BOT
,CBSO
,1,1), BBOATCB_MASK
, PPCCOM
, PPCNONE
, {CR
, BDA
}},
3711 {"bdnzf-", BBO(16,BODNZF
,0,0), BBOY_MASK
, PPCCOM
, ISA_V2
, {BI
, BDM
}},
3712 {"bdnzf+", BBO(16,BODNZF
,0,0), BBOY_MASK
, PPCCOM
, ISA_V2
, {BI
, BDP
}},
3713 {"bdnzf", BBO(16,BODNZF
,0,0), BBOY_MASK
, PPCCOM
, PPCNONE
, {BI
, BD
}},
3714 {"bdnzfl-", BBO(16,BODNZF
,0,1), BBOY_MASK
, PPCCOM
, ISA_V2
, {BI
, BDM
}},
3715 {"bdnzfl+", BBO(16,BODNZF
,0,1), BBOY_MASK
, PPCCOM
, ISA_V2
, {BI
, BDP
}},
3716 {"bdnzfl", BBO(16,BODNZF
,0,1), BBOY_MASK
, PPCCOM
, PPCNONE
, {BI
, BD
}},
3717 {"bdnzfa-", BBO(16,BODNZF
,1,0), BBOY_MASK
, PPCCOM
, ISA_V2
, {BI
, BDMA
}},
3718 {"bdnzfa+", BBO(16,BODNZF
,1,0), BBOY_MASK
, PPCCOM
, ISA_V2
, {BI
, BDPA
}},
3719 {"bdnzfa", BBO(16,BODNZF
,1,0), BBOY_MASK
, PPCCOM
, PPCNONE
, {BI
, BDA
}},
3720 {"bdnzfla-", BBO(16,BODNZF
,1,1), BBOY_MASK
, PPCCOM
, ISA_V2
, {BI
, BDMA
}},
3721 {"bdnzfla+", BBO(16,BODNZF
,1,1), BBOY_MASK
, PPCCOM
, ISA_V2
, {BI
, BDPA
}},
3722 {"bdnzfla", BBO(16,BODNZF
,1,1), BBOY_MASK
, PPCCOM
, PPCNONE
, {BI
, BDA
}},
3723 {"bdzf-", BBO(16,BODZF
,0,0), BBOY_MASK
, PPCCOM
, ISA_V2
, {BI
, BDM
}},
3724 {"bdzf+", BBO(16,BODZF
,0,0), BBOY_MASK
, PPCCOM
, ISA_V2
, {BI
, BDP
}},
3725 {"bdzf", BBO(16,BODZF
,0,0), BBOY_MASK
, PPCCOM
, PPCNONE
, {BI
, BD
}},
3726 {"bdzfl-", BBO(16,BODZF
,0,1), BBOY_MASK
, PPCCOM
, ISA_V2
, {BI
, BDM
}},
3727 {"bdzfl+", BBO(16,BODZF
,0,1), BBOY_MASK
, PPCCOM
, ISA_V2
, {BI
, BDP
}},
3728 {"bdzfl", BBO(16,BODZF
,0,1), BBOY_MASK
, PPCCOM
, PPCNONE
, {BI
, BD
}},
3729 {"bdzfa-", BBO(16,BODZF
,1,0), BBOY_MASK
, PPCCOM
, ISA_V2
, {BI
, BDMA
}},
3730 {"bdzfa+", BBO(16,BODZF
,1,0), BBOY_MASK
, PPCCOM
, ISA_V2
, {BI
, BDPA
}},
3731 {"bdzfa", BBO(16,BODZF
,1,0), BBOY_MASK
, PPCCOM
, PPCNONE
, {BI
, BDA
}},
3732 {"bdzfla-", BBO(16,BODZF
,1,1), BBOY_MASK
, PPCCOM
, ISA_V2
, {BI
, BDMA
}},
3733 {"bdzfla+", BBO(16,BODZF
,1,1), BBOY_MASK
, PPCCOM
, ISA_V2
, {BI
, BDPA
}},
3734 {"bdzfla", BBO(16,BODZF
,1,1), BBOY_MASK
, PPCCOM
, PPCNONE
, {BI
, BDA
}},
3736 {"bf-", BBO(16,BOF
,0,0), BBOAT_MASK
, PPCCOM
, PPCNONE
, {BI
, BDM
}},
3737 {"bf+", BBO(16,BOF
,0,0), BBOAT_MASK
, PPCCOM
, PPCNONE
, {BI
, BDP
}},
3738 {"bf", BBO(16,BOF
,0,0), BBOAT_MASK
, PPCCOM
, PPCNONE
, {BI
, BD
}},
3739 {"bbf", BBO(16,BOF
,0,0), BBOAT_MASK
, PWRCOM
, PPCNONE
, {BI
, BD
}},
3740 {"bfl-", BBO(16,BOF
,0,1), BBOAT_MASK
, PPCCOM
, PPCNONE
, {BI
, BDM
}},
3741 {"bfl+", BBO(16,BOF
,0,1), BBOAT_MASK
, PPCCOM
, PPCNONE
, {BI
, BDP
}},
3742 {"bfl", BBO(16,BOF
,0,1), BBOAT_MASK
, PPCCOM
, PPCNONE
, {BI
, BD
}},
3743 {"bbfl", BBO(16,BOF
,0,1), BBOAT_MASK
, PWRCOM
, PPCNONE
, {BI
, BD
}},
3744 {"bfa-", BBO(16,BOF
,1,0), BBOAT_MASK
, PPCCOM
, PPCNONE
, {BI
, BDMA
}},
3745 {"bfa+", BBO(16,BOF
,1,0), BBOAT_MASK
, PPCCOM
, PPCNONE
, {BI
, BDPA
}},
3746 {"bfa", BBO(16,BOF
,1,0), BBOAT_MASK
, PPCCOM
, PPCNONE
, {BI
, BDA
}},
3747 {"bbfa", BBO(16,BOF
,1,0), BBOAT_MASK
, PWRCOM
, PPCNONE
, {BI
, BDA
}},
3748 {"bfla-", BBO(16,BOF
,1,1), BBOAT_MASK
, PPCCOM
, PPCNONE
, {BI
, BDMA
}},
3749 {"bfla+", BBO(16,BOF
,1,1), BBOAT_MASK
, PPCCOM
, PPCNONE
, {BI
, BDPA
}},
3750 {"bfla", BBO(16,BOF
,1,1), BBOAT_MASK
, PPCCOM
, PPCNONE
, {BI
, BDA
}},
3751 {"bbfla", BBO(16,BOF
,1,1), BBOAT_MASK
, PWRCOM
, PPCNONE
, {BI
, BDA
}},
3753 {"bdnzt-", BBO(16,BODNZT
,0,0), BBOY_MASK
, PPCCOM
, ISA_V2
, {BI
, BDM
}},
3754 {"bdnzt+", BBO(16,BODNZT
,0,0), BBOY_MASK
, PPCCOM
, ISA_V2
, {BI
, BDP
}},
3755 {"bdnzt", BBO(16,BODNZT
,0,0), BBOY_MASK
, PPCCOM
, PPCNONE
, {BI
, BD
}},
3756 {"bdnztl-", BBO(16,BODNZT
,0,1), BBOY_MASK
, PPCCOM
, ISA_V2
, {BI
, BDM
}},
3757 {"bdnztl+", BBO(16,BODNZT
,0,1), BBOY_MASK
, PPCCOM
, ISA_V2
, {BI
, BDP
}},
3758 {"bdnztl", BBO(16,BODNZT
,0,1), BBOY_MASK
, PPCCOM
, PPCNONE
, {BI
, BD
}},
3759 {"bdnzta-", BBO(16,BODNZT
,1,0), BBOY_MASK
, PPCCOM
, ISA_V2
, {BI
, BDMA
}},
3760 {"bdnzta+", BBO(16,BODNZT
,1,0), BBOY_MASK
, PPCCOM
, ISA_V2
, {BI
, BDPA
}},
3761 {"bdnzta", BBO(16,BODNZT
,1,0), BBOY_MASK
, PPCCOM
, PPCNONE
, {BI
, BDA
}},
3762 {"bdnztla-", BBO(16,BODNZT
,1,1), BBOY_MASK
, PPCCOM
, ISA_V2
, {BI
, BDMA
}},
3763 {"bdnztla+", BBO(16,BODNZT
,1,1), BBOY_MASK
, PPCCOM
, ISA_V2
, {BI
, BDPA
}},
3764 {"bdnztla", BBO(16,BODNZT
,1,1), BBOY_MASK
, PPCCOM
, PPCNONE
, {BI
, BDA
}},
3765 {"bdzt-", BBO(16,BODZT
,0,0), BBOY_MASK
, PPCCOM
, ISA_V2
, {BI
, BDM
}},
3766 {"bdzt+", BBO(16,BODZT
,0,0), BBOY_MASK
, PPCCOM
, ISA_V2
, {BI
, BDP
}},
3767 {"bdzt", BBO(16,BODZT
,0,0), BBOY_MASK
, PPCCOM
, PPCNONE
, {BI
, BD
}},
3768 {"bdztl-", BBO(16,BODZT
,0,1), BBOY_MASK
, PPCCOM
, ISA_V2
, {BI
, BDM
}},
3769 {"bdztl+", BBO(16,BODZT
,0,1), BBOY_MASK
, PPCCOM
, ISA_V2
, {BI
, BDP
}},
3770 {"bdztl", BBO(16,BODZT
,0,1), BBOY_MASK
, PPCCOM
, PPCNONE
, {BI
, BD
}},
3771 {"bdzta-", BBO(16,BODZT
,1,0), BBOY_MASK
, PPCCOM
, ISA_V2
, {BI
, BDMA
}},
3772 {"bdzta+", BBO(16,BODZT
,1,0), BBOY_MASK
, PPCCOM
, ISA_V2
, {BI
, BDPA
}},
3773 {"bdzta", BBO(16,BODZT
,1,0), BBOY_MASK
, PPCCOM
, PPCNONE
, {BI
, BDA
}},
3774 {"bdztla-", BBO(16,BODZT
,1,1), BBOY_MASK
, PPCCOM
, ISA_V2
, {BI
, BDMA
}},
3775 {"bdztla+", BBO(16,BODZT
,1,1), BBOY_MASK
, PPCCOM
, ISA_V2
, {BI
, BDPA
}},
3776 {"bdztla", BBO(16,BODZT
,1,1), BBOY_MASK
, PPCCOM
, PPCNONE
, {BI
, BDA
}},
3778 {"bt-", BBO(16,BOT
,0,0), BBOAT_MASK
, PPCCOM
, PPCNONE
, {BI
, BDM
}},
3779 {"bt+", BBO(16,BOT
,0,0), BBOAT_MASK
, PPCCOM
, PPCNONE
, {BI
, BDP
}},
3780 {"bt", BBO(16,BOT
,0,0), BBOAT_MASK
, PPCCOM
, PPCNONE
, {BI
, BD
}},
3781 {"bbt", BBO(16,BOT
,0,0), BBOAT_MASK
, PWRCOM
, PPCNONE
, {BI
, BD
}},
3782 {"btl-", BBO(16,BOT
,0,1), BBOAT_MASK
, PPCCOM
, PPCNONE
, {BI
, BDM
}},
3783 {"btl+", BBO(16,BOT
,0,1), BBOAT_MASK
, PPCCOM
, PPCNONE
, {BI
, BDP
}},
3784 {"btl", BBO(16,BOT
,0,1), BBOAT_MASK
, PPCCOM
, PPCNONE
, {BI
, BD
}},
3785 {"bbtl", BBO(16,BOT
,0,1), BBOAT_MASK
, PWRCOM
, PPCNONE
, {BI
, BD
}},
3786 {"bta-", BBO(16,BOT
,1,0), BBOAT_MASK
, PPCCOM
, PPCNONE
, {BI
, BDMA
}},
3787 {"bta+", BBO(16,BOT
,1,0), BBOAT_MASK
, PPCCOM
, PPCNONE
, {BI
, BDPA
}},
3788 {"bta", BBO(16,BOT
,1,0), BBOAT_MASK
, PPCCOM
, PPCNONE
, {BI
, BDA
}},
3789 {"bbta", BBO(16,BOT
,1,0), BBOAT_MASK
, PWRCOM
, PPCNONE
, {BI
, BDA
}},
3790 {"btla-", BBO(16,BOT
,1,1), BBOAT_MASK
, PPCCOM
, PPCNONE
, {BI
, BDMA
}},
3791 {"btla+", BBO(16,BOT
,1,1), BBOAT_MASK
, PPCCOM
, PPCNONE
, {BI
, BDPA
}},
3792 {"btla", BBO(16,BOT
,1,1), BBOAT_MASK
, PPCCOM
, PPCNONE
, {BI
, BDA
}},
3793 {"bbtla", BBO(16,BOT
,1,1), BBOAT_MASK
, PWRCOM
, PPCNONE
, {BI
, BDA
}},
3795 {"bc-", B(16,0,0), B_MASK
, PPCCOM
, PPCNONE
, {BOE
, BI
, BDM
}},
3796 {"bc+", B(16,0,0), B_MASK
, PPCCOM
, PPCNONE
, {BOE
, BI
, BDP
}},
3797 {"bc", B(16,0,0), B_MASK
, COM
, PPCNONE
, {BO
, BI
, BD
}},
3798 {"bcl-", B(16,0,1), B_MASK
, PPCCOM
, PPCNONE
, {BOE
, BI
, BDM
}},
3799 {"bcl+", B(16,0,1), B_MASK
, PPCCOM
, PPCNONE
, {BOE
, BI
, BDP
}},
3800 {"bcl", B(16,0,1), B_MASK
, COM
, PPCNONE
, {BO
, BI
, BD
}},
3801 {"bca-", B(16,1,0), B_MASK
, PPCCOM
, PPCNONE
, {BOE
, BI
, BDMA
}},
3802 {"bca+", B(16,1,0), B_MASK
, PPCCOM
, PPCNONE
, {BOE
, BI
, BDPA
}},
3803 {"bca", B(16,1,0), B_MASK
, COM
, PPCNONE
, {BO
, BI
, BDA
}},
3804 {"bcla-", B(16,1,1), B_MASK
, PPCCOM
, PPCNONE
, {BOE
, BI
, BDMA
}},
3805 {"bcla+", B(16,1,1), B_MASK
, PPCCOM
, PPCNONE
, {BOE
, BI
, BDPA
}},
3806 {"bcla", B(16,1,1), B_MASK
, COM
, PPCNONE
, {BO
, BI
, BDA
}},
3808 {"svc", SC(17,0,0), SC_MASK
, POWER
, PPCNONE
, {SVC_LEV
, FL1
, FL2
}},
3809 {"svcl", SC(17,0,1), SC_MASK
, POWER
, PPCNONE
, {SVC_LEV
, FL1
, FL2
}},
3810 {"sc", SC(17,1,0), SC_MASK
, PPC
, PPCNONE
, {LEV
}},
3811 {"svca", SC(17,1,0), SC_MASK
, PWRCOM
, PPCNONE
, {SV
}},
3812 {"svcla", SC(17,1,1), SC_MASK
, POWER
, PPCNONE
, {SV
}},
3814 {"b", B(18,0,0), B_MASK
, COM
, PPCNONE
, {LI
}},
3815 {"bl", B(18,0,1), B_MASK
, COM
, PPCNONE
, {LI
}},
3816 {"ba", B(18,1,0), B_MASK
, COM
, PPCNONE
, {LIA
}},
3817 {"bla", B(18,1,1), B_MASK
, COM
, PPCNONE
, {LIA
}},
3819 {"mcrf", XL(19,0), XLBB_MASK
|(3<<21)|(3<<16), COM
, PPCNONE
, {BF
, BFA
}},
3821 {"bdnzlr", XLO(19,BODNZ
,16,0), XLBOBIBB_MASK
, PPCCOM
, PPCNONE
, {0}},
3822 {"bdnzlr-", XLO(19,BODNZ
,16,0), XLBOBIBB_MASK
, PPCCOM
, ISA_V2
, {0}},
3823 {"bdnzlrl", XLO(19,BODNZ
,16,1), XLBOBIBB_MASK
, PPCCOM
, PPCNONE
, {0}},
3824 {"bdnzlrl-", XLO(19,BODNZ
,16,1), XLBOBIBB_MASK
, PPCCOM
, ISA_V2
, {0}},
3825 {"bdnzlr+", XLO(19,BODNZP
,16,0), XLBOBIBB_MASK
, PPCCOM
, ISA_V2
, {0}},
3826 {"bdnzlrl+", XLO(19,BODNZP
,16,1), XLBOBIBB_MASK
, PPCCOM
, ISA_V2
, {0}},
3827 {"bdzlr", XLO(19,BODZ
,16,0), XLBOBIBB_MASK
, PPCCOM
, PPCNONE
, {0}},
3828 {"bdzlr-", XLO(19,BODZ
,16,0), XLBOBIBB_MASK
, PPCCOM
, ISA_V2
, {0}},
3829 {"bdzlrl", XLO(19,BODZ
,16,1), XLBOBIBB_MASK
, PPCCOM
, PPCNONE
, {0}},
3830 {"bdzlrl-", XLO(19,BODZ
,16,1), XLBOBIBB_MASK
, PPCCOM
, ISA_V2
, {0}},
3831 {"bdzlr+", XLO(19,BODZP
,16,0), XLBOBIBB_MASK
, PPCCOM
, ISA_V2
, {0}},
3832 {"bdzlrl+", XLO(19,BODZP
,16,1), XLBOBIBB_MASK
, PPCCOM
, ISA_V2
, {0}},
3833 {"blr", XLO(19,BOU
,16,0), XLBOBIBB_MASK
, PPCCOM
, PPCNONE
, {0}},
3834 {"br", XLO(19,BOU
,16,0), XLBOBIBB_MASK
, PWRCOM
, PPCNONE
, {0}},
3835 {"blrl", XLO(19,BOU
,16,1), XLBOBIBB_MASK
, PPCCOM
, PPCNONE
, {0}},
3836 {"brl", XLO(19,BOU
,16,1), XLBOBIBB_MASK
, PWRCOM
, PPCNONE
, {0}},
3837 {"bdnzlr-", XLO(19,BODNZM4
,16,0), XLBOBIBB_MASK
, ISA_V2
, PPCNONE
, {0}},
3838 {"bdnzlrl-", XLO(19,BODNZM4
,16,1), XLBOBIBB_MASK
, ISA_V2
, PPCNONE
, {0}},
3839 {"bdnzlr+", XLO(19,BODNZP4
,16,0), XLBOBIBB_MASK
, ISA_V2
, PPCNONE
, {0}},
3840 {"bdnzlrl+", XLO(19,BODNZP4
,16,1), XLBOBIBB_MASK
, ISA_V2
, PPCNONE
, {0}},
3841 {"bdzlr-", XLO(19,BODZM4
,16,0), XLBOBIBB_MASK
, ISA_V2
, PPCNONE
, {0}},
3842 {"bdzlrl-", XLO(19,BODZM4
,16,1), XLBOBIBB_MASK
, ISA_V2
, PPCNONE
, {0}},
3843 {"bdzlr+", XLO(19,BODZP4
,16,0), XLBOBIBB_MASK
, ISA_V2
, PPCNONE
, {0}},
3844 {"bdzlrl+", XLO(19,BODZP4
,16,1), XLBOBIBB_MASK
, ISA_V2
, PPCNONE
, {0}},
3846 {"bgelr", XLOCB(19,BOF
,CBLT
,16,0), XLBOCBBB_MASK
, PPCCOM
, PPCNONE
, {CR
}},
3847 {"bgelr-", XLOCB(19,BOF
,CBLT
,16,0), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
, {CR
}},
3848 {"bger", XLOCB(19,BOF
,CBLT
,16,0), XLBOCBBB_MASK
, PWRCOM
, PPCNONE
, {CR
}},
3849 {"bnllr", XLOCB(19,BOF
,CBLT
,16,0), XLBOCBBB_MASK
, PPCCOM
, PPCNONE
, {CR
}},
3850 {"bnllr-", XLOCB(19,BOF
,CBLT
,16,0), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
, {CR
}},
3851 {"bnlr", XLOCB(19,BOF
,CBLT
,16,0), XLBOCBBB_MASK
, PWRCOM
, PPCNONE
, {CR
}},
3852 {"bgelrl", XLOCB(19,BOF
,CBLT
,16,1), XLBOCBBB_MASK
, PPCCOM
, PPCNONE
, {CR
}},
3853 {"bgelrl-", XLOCB(19,BOF
,CBLT
,16,1), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
, {CR
}},
3854 {"bgerl", XLOCB(19,BOF
,CBLT
,16,1), XLBOCBBB_MASK
, PWRCOM
, PPCNONE
, {CR
}},
3855 {"bnllrl", XLOCB(19,BOF
,CBLT
,16,1), XLBOCBBB_MASK
, PPCCOM
, PPCNONE
, {CR
}},
3856 {"bnllrl-", XLOCB(19,BOF
,CBLT
,16,1), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
, {CR
}},
3857 {"bnlrl", XLOCB(19,BOF
,CBLT
,16,1), XLBOCBBB_MASK
, PWRCOM
, PPCNONE
, {CR
}},
3858 {"blelr", XLOCB(19,BOF
,CBGT
,16,0), XLBOCBBB_MASK
, PPCCOM
, PPCNONE
, {CR
}},
3859 {"blelr-", XLOCB(19,BOF
,CBGT
,16,0), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
, {CR
}},
3860 {"bler", XLOCB(19,BOF
,CBGT
,16,0), XLBOCBBB_MASK
, PWRCOM
, PPCNONE
, {CR
}},
3861 {"bnglr", XLOCB(19,BOF
,CBGT
,16,0), XLBOCBBB_MASK
, PPCCOM
, PPCNONE
, {CR
}},
3862 {"bnglr-", XLOCB(19,BOF
,CBGT
,16,0), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
, {CR
}},
3863 {"bngr", XLOCB(19,BOF
,CBGT
,16,0), XLBOCBBB_MASK
, PWRCOM
, PPCNONE
, {CR
}},
3864 {"blelrl", XLOCB(19,BOF
,CBGT
,16,1), XLBOCBBB_MASK
, PPCCOM
, PPCNONE
, {CR
}},
3865 {"blelrl-", XLOCB(19,BOF
,CBGT
,16,1), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
, {CR
}},
3866 {"blerl", XLOCB(19,BOF
,CBGT
,16,1), XLBOCBBB_MASK
, PWRCOM
, PPCNONE
, {CR
}},
3867 {"bnglrl", XLOCB(19,BOF
,CBGT
,16,1), XLBOCBBB_MASK
, PPCCOM
, PPCNONE
, {CR
}},
3868 {"bnglrl-", XLOCB(19,BOF
,CBGT
,16,1), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
, {CR
}},
3869 {"bngrl", XLOCB(19,BOF
,CBGT
,16,1), XLBOCBBB_MASK
, PWRCOM
, PPCNONE
, {CR
}},
3870 {"bnelr", XLOCB(19,BOF
,CBEQ
,16,0), XLBOCBBB_MASK
, PPCCOM
, PPCNONE
, {CR
}},
3871 {"bnelr-", XLOCB(19,BOF
,CBEQ
,16,0), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
, {CR
}},
3872 {"bner", XLOCB(19,BOF
,CBEQ
,16,0), XLBOCBBB_MASK
, PWRCOM
, PPCNONE
, {CR
}},
3873 {"bnelrl", XLOCB(19,BOF
,CBEQ
,16,1), XLBOCBBB_MASK
, PPCCOM
, PPCNONE
, {CR
}},
3874 {"bnelrl-", XLOCB(19,BOF
,CBEQ
,16,1), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
, {CR
}},
3875 {"bnerl", XLOCB(19,BOF
,CBEQ
,16,1), XLBOCBBB_MASK
, PWRCOM
, PPCNONE
, {CR
}},
3876 {"bnslr", XLOCB(19,BOF
,CBSO
,16,0), XLBOCBBB_MASK
, PPCCOM
, PPCNONE
, {CR
}},
3877 {"bnslr-", XLOCB(19,BOF
,CBSO
,16,0), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
, {CR
}},
3878 {"bnsr", XLOCB(19,BOF
,CBSO
,16,0), XLBOCBBB_MASK
, PWRCOM
, PPCNONE
, {CR
}},
3879 {"bnulr", XLOCB(19,BOF
,CBSO
,16,0), XLBOCBBB_MASK
, PPCCOM
, PPCNONE
, {CR
}},
3880 {"bnulr-", XLOCB(19,BOF
,CBSO
,16,0), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
, {CR
}},
3881 {"bnslrl", XLOCB(19,BOF
,CBSO
,16,1), XLBOCBBB_MASK
, PPCCOM
, PPCNONE
, {CR
}},
3882 {"bnslrl-", XLOCB(19,BOF
,CBSO
,16,1), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
, {CR
}},
3883 {"bnsrl", XLOCB(19,BOF
,CBSO
,16,1), XLBOCBBB_MASK
, PWRCOM
, PPCNONE
, {CR
}},
3884 {"bnulrl", XLOCB(19,BOF
,CBSO
,16,1), XLBOCBBB_MASK
, PPCCOM
, PPCNONE
, {CR
}},
3885 {"bnulrl-", XLOCB(19,BOF
,CBSO
,16,1), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
, {CR
}},
3886 {"bgelr+", XLOCB(19,BOFP
,CBLT
,16,0), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
, {CR
}},
3887 {"bnllr+", XLOCB(19,BOFP
,CBLT
,16,0), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
, {CR
}},
3888 {"bgelrl+", XLOCB(19,BOFP
,CBLT
,16,1), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
, {CR
}},
3889 {"bnllrl+", XLOCB(19,BOFP
,CBLT
,16,1), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
, {CR
}},
3890 {"blelr+", XLOCB(19,BOFP
,CBGT
,16,0), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
, {CR
}},
3891 {"bnglr+", XLOCB(19,BOFP
,CBGT
,16,0), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
, {CR
}},
3892 {"blelrl+", XLOCB(19,BOFP
,CBGT
,16,1), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
, {CR
}},
3893 {"bnglrl+", XLOCB(19,BOFP
,CBGT
,16,1), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
, {CR
}},
3894 {"bnelr+", XLOCB(19,BOFP
,CBEQ
,16,0), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
, {CR
}},
3895 {"bnelrl+", XLOCB(19,BOFP
,CBEQ
,16,1), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
, {CR
}},
3896 {"bnslr+", XLOCB(19,BOFP
,CBSO
,16,0), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
, {CR
}},
3897 {"bnulr+", XLOCB(19,BOFP
,CBSO
,16,0), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
, {CR
}},
3898 {"bnslrl+", XLOCB(19,BOFP
,CBSO
,16,1), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
, {CR
}},
3899 {"bnulrl+", XLOCB(19,BOFP
,CBSO
,16,1), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
, {CR
}},
3900 {"bgelr-", XLOCB(19,BOFM4
,CBLT
,16,0), XLBOCBBB_MASK
, ISA_V2
, PPCNONE
, {CR
}},
3901 {"bnllr-", XLOCB(19,BOFM4
,CBLT
,16,0), XLBOCBBB_MASK
, ISA_V2
, PPCNONE
, {CR
}},
3902 {"bgelrl-", XLOCB(19,BOFM4
,CBLT
,16,1), XLBOCBBB_MASK
, ISA_V2
, PPCNONE
, {CR
}},
3903 {"bnllrl-", XLOCB(19,BOFM4
,CBLT
,16,1), XLBOCBBB_MASK
, ISA_V2
, PPCNONE
, {CR
}},
3904 {"blelr-", XLOCB(19,BOFM4
,CBGT
,16,0), XLBOCBBB_MASK
, ISA_V2
, PPCNONE
, {CR
}},
3905 {"bnglr-", XLOCB(19,BOFM4
,CBGT
,16,0), XLBOCBBB_MASK
, ISA_V2
, PPCNONE
, {CR
}},
3906 {"blelrl-", XLOCB(19,BOFM4
,CBGT
,16,1), XLBOCBBB_MASK
, ISA_V2
, PPCNONE
, {CR
}},
3907 {"bnglrl-", XLOCB(19,BOFM4
,CBGT
,16,1), XLBOCBBB_MASK
, ISA_V2
, PPCNONE
, {CR
}},
3908 {"bnelr-", XLOCB(19,BOFM4
,CBEQ
,16,0), XLBOCBBB_MASK
, ISA_V2
, PPCNONE
, {CR
}},
3909 {"bnelrl-", XLOCB(19,BOFM4
,CBEQ
,16,1), XLBOCBBB_MASK
, ISA_V2
, PPCNONE
, {CR
}},
3910 {"bnslr-", XLOCB(19,BOFM4
,CBSO
,16,0), XLBOCBBB_MASK
, ISA_V2
, PPCNONE
, {CR
}},
3911 {"bnulr-", XLOCB(19,BOFM4
,CBSO
,16,0), XLBOCBBB_MASK
, ISA_V2
, PPCNONE
, {CR
}},
3912 {"bnslrl-", XLOCB(19,BOFM4
,CBSO
,16,1), XLBOCBBB_MASK
, ISA_V2
, PPCNONE
, {CR
}},
3913 {"bnulrl-", XLOCB(19,BOFM4
,CBSO
,16,1), XLBOCBBB_MASK
, ISA_V2
, PPCNONE
, {CR
}},
3914 {"bgelr+", XLOCB(19,BOFP4
,CBLT
,16,0), XLBOCBBB_MASK
, ISA_V2
, PPCNONE
, {CR
}},
3915 {"bnllr+", XLOCB(19,BOFP4
,CBLT
,16,0), XLBOCBBB_MASK
, ISA_V2
, PPCNONE
, {CR
}},
3916 {"bgelrl+", XLOCB(19,BOFP4
,CBLT
,16,1), XLBOCBBB_MASK
, ISA_V2
, PPCNONE
, {CR
}},
3917 {"bnllrl+", XLOCB(19,BOFP4
,CBLT
,16,1), XLBOCBBB_MASK
, ISA_V2
, PPCNONE
, {CR
}},
3918 {"blelr+", XLOCB(19,BOFP4
,CBGT
,16,0), XLBOCBBB_MASK
, ISA_V2
, PPCNONE
, {CR
}},
3919 {"bnglr+", XLOCB(19,BOFP4
,CBGT
,16,0), XLBOCBBB_MASK
, ISA_V2
, PPCNONE
, {CR
}},
3920 {"blelrl+", XLOCB(19,BOFP4
,CBGT
,16,1), XLBOCBBB_MASK
, ISA_V2
, PPCNONE
, {CR
}},
3921 {"bnglrl+", XLOCB(19,BOFP4
,CBGT
,16,1), XLBOCBBB_MASK
, ISA_V2
, PPCNONE
, {CR
}},
3922 {"bnelr+", XLOCB(19,BOFP4
,CBEQ
,16,0), XLBOCBBB_MASK
, ISA_V2
, PPCNONE
, {CR
}},
3923 {"bnelrl+", XLOCB(19,BOFP4
,CBEQ
,16,1), XLBOCBBB_MASK
, ISA_V2
, PPCNONE
, {CR
}},
3924 {"bnslr+", XLOCB(19,BOFP4
,CBSO
,16,0), XLBOCBBB_MASK
, ISA_V2
, PPCNONE
, {CR
}},
3925 {"bnulr+", XLOCB(19,BOFP4
,CBSO
,16,0), XLBOCBBB_MASK
, ISA_V2
, PPCNONE
, {CR
}},
3926 {"bnslrl+", XLOCB(19,BOFP4
,CBSO
,16,1), XLBOCBBB_MASK
, ISA_V2
, PPCNONE
, {CR
}},
3927 {"bnulrl+", XLOCB(19,BOFP4
,CBSO
,16,1), XLBOCBBB_MASK
, ISA_V2
, PPCNONE
, {CR
}},
3928 {"bltlr", XLOCB(19,BOT
,CBLT
,16,0), XLBOCBBB_MASK
, PPCCOM
, PPCNONE
, {CR
}},
3929 {"bltlr-", XLOCB(19,BOT
,CBLT
,16,0), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
, {CR
}},
3930 {"bltr", XLOCB(19,BOT
,CBLT
,16,0), XLBOCBBB_MASK
, PWRCOM
, PPCNONE
, {CR
}},
3931 {"bltlrl", XLOCB(19,BOT
,CBLT
,16,1), XLBOCBBB_MASK
, PPCCOM
, PPCNONE
, {CR
}},
3932 {"bltlrl-", XLOCB(19,BOT
,CBLT
,16,1), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
, {CR
}},
3933 {"bltrl", XLOCB(19,BOT
,CBLT
,16,1), XLBOCBBB_MASK
, PWRCOM
, PPCNONE
, {CR
}},
3934 {"bgtlr", XLOCB(19,BOT
,CBGT
,16,0), XLBOCBBB_MASK
, PPCCOM
, PPCNONE
, {CR
}},
3935 {"bgtlr-", XLOCB(19,BOT
,CBGT
,16,0), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
, {CR
}},
3936 {"bgtr", XLOCB(19,BOT
,CBGT
,16,0), XLBOCBBB_MASK
, PWRCOM
, PPCNONE
, {CR
}},
3937 {"bgtlrl", XLOCB(19,BOT
,CBGT
,16,1), XLBOCBBB_MASK
, PPCCOM
, PPCNONE
, {CR
}},
3938 {"bgtlrl-", XLOCB(19,BOT
,CBGT
,16,1), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
, {CR
}},
3939 {"bgtrl", XLOCB(19,BOT
,CBGT
,16,1), XLBOCBBB_MASK
, PWRCOM
, PPCNONE
, {CR
}},
3940 {"beqlr", XLOCB(19,BOT
,CBEQ
,16,0), XLBOCBBB_MASK
, PPCCOM
, PPCNONE
, {CR
}},
3941 {"beqlr-", XLOCB(19,BOT
,CBEQ
,16,0), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
, {CR
}},
3942 {"beqr", XLOCB(19,BOT
,CBEQ
,16,0), XLBOCBBB_MASK
, PWRCOM
, PPCNONE
, {CR
}},
3943 {"beqlrl", XLOCB(19,BOT
,CBEQ
,16,1), XLBOCBBB_MASK
, PPCCOM
, PPCNONE
, {CR
}},
3944 {"beqlrl-", XLOCB(19,BOT
,CBEQ
,16,1), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
, {CR
}},
3945 {"beqrl", XLOCB(19,BOT
,CBEQ
,16,1), XLBOCBBB_MASK
, PWRCOM
, PPCNONE
, {CR
}},
3946 {"bsolr", XLOCB(19,BOT
,CBSO
,16,0), XLBOCBBB_MASK
, PPCCOM
, PPCNONE
, {CR
}},
3947 {"bsolr-", XLOCB(19,BOT
,CBSO
,16,0), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
, {CR
}},
3948 {"bsor", XLOCB(19,BOT
,CBSO
,16,0), XLBOCBBB_MASK
, PWRCOM
, PPCNONE
, {CR
}},
3949 {"bunlr", XLOCB(19,BOT
,CBSO
,16,0), XLBOCBBB_MASK
, PPCCOM
, PPCNONE
, {CR
}},
3950 {"bunlr-", XLOCB(19,BOT
,CBSO
,16,0), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
, {CR
}},
3951 {"bsolrl", XLOCB(19,BOT
,CBSO
,16,1), XLBOCBBB_MASK
, PPCCOM
, PPCNONE
, {CR
}},
3952 {"bsolrl-", XLOCB(19,BOT
,CBSO
,16,1), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
, {CR
}},
3953 {"bsorl", XLOCB(19,BOT
,CBSO
,16,1), XLBOCBBB_MASK
, PWRCOM
, PPCNONE
, {CR
}},
3954 {"bunlrl", XLOCB(19,BOT
,CBSO
,16,1), XLBOCBBB_MASK
, PPCCOM
, PPCNONE
, {CR
}},
3955 {"bunlrl-", XLOCB(19,BOT
,CBSO
,16,1), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
, {CR
}},
3956 {"bltlr+", XLOCB(19,BOTP
,CBLT
,16,0), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
, {CR
}},
3957 {"bltlrl+", XLOCB(19,BOTP
,CBLT
,16,1), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
, {CR
}},
3958 {"bgtlr+", XLOCB(19,BOTP
,CBGT
,16,0), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
, {CR
}},
3959 {"bgtlrl+", XLOCB(19,BOTP
,CBGT
,16,1), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
, {CR
}},
3960 {"beqlr+", XLOCB(19,BOTP
,CBEQ
,16,0), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
, {CR
}},
3961 {"beqlrl+", XLOCB(19,BOTP
,CBEQ
,16,1), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
, {CR
}},
3962 {"bsolr+", XLOCB(19,BOTP
,CBSO
,16,0), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
, {CR
}},
3963 {"bunlr+", XLOCB(19,BOTP
,CBSO
,16,0), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
, {CR
}},
3964 {"bsolrl+", XLOCB(19,BOTP
,CBSO
,16,1), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
, {CR
}},
3965 {"bunlrl+", XLOCB(19,BOTP
,CBSO
,16,1), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
, {CR
}},
3966 {"bltlr-", XLOCB(19,BOTM4
,CBLT
,16,0), XLBOCBBB_MASK
, ISA_V2
, PPCNONE
, {CR
}},
3967 {"bltlrl-", XLOCB(19,BOTM4
,CBLT
,16,1), XLBOCBBB_MASK
, ISA_V2
, PPCNONE
, {CR
}},
3968 {"bgtlr-", XLOCB(19,BOTM4
,CBGT
,16,0), XLBOCBBB_MASK
, ISA_V2
, PPCNONE
, {CR
}},
3969 {"bgtlrl-", XLOCB(19,BOTM4
,CBGT
,16,1), XLBOCBBB_MASK
, ISA_V2
, PPCNONE
, {CR
}},
3970 {"beqlr-", XLOCB(19,BOTM4
,CBEQ
,16,0), XLBOCBBB_MASK
, ISA_V2
, PPCNONE
, {CR
}},
3971 {"beqlrl-", XLOCB(19,BOTM4
,CBEQ
,16,1), XLBOCBBB_MASK
, ISA_V2
, PPCNONE
, {CR
}},
3972 {"bsolr-", XLOCB(19,BOTM4
,CBSO
,16,0), XLBOCBBB_MASK
, ISA_V2
, PPCNONE
, {CR
}},
3973 {"bunlr-", XLOCB(19,BOTM4
,CBSO
,16,0), XLBOCBBB_MASK
, ISA_V2
, PPCNONE
, {CR
}},
3974 {"bsolrl-", XLOCB(19,BOTM4
,CBSO
,16,1), XLBOCBBB_MASK
, ISA_V2
, PPCNONE
, {CR
}},
3975 {"bunlrl-", XLOCB(19,BOTM4
,CBSO
,16,1), XLBOCBBB_MASK
, ISA_V2
, PPCNONE
, {CR
}},
3976 {"bltlr+", XLOCB(19,BOTP4
,CBLT
,16,0), XLBOCBBB_MASK
, ISA_V2
, PPCNONE
, {CR
}},
3977 {"bltlrl+", XLOCB(19,BOTP4
,CBLT
,16,1), XLBOCBBB_MASK
, ISA_V2
, PPCNONE
, {CR
}},
3978 {"bgtlr+", XLOCB(19,BOTP4
,CBGT
,16,0), XLBOCBBB_MASK
, ISA_V2
, PPCNONE
, {CR
}},
3979 {"bgtlrl+", XLOCB(19,BOTP4
,CBGT
,16,1), XLBOCBBB_MASK
, ISA_V2
, PPCNONE
, {CR
}},
3980 {"beqlr+", XLOCB(19,BOTP4
,CBEQ
,16,0), XLBOCBBB_MASK
, ISA_V2
, PPCNONE
, {CR
}},
3981 {"beqlrl+", XLOCB(19,BOTP4
,CBEQ
,16,1), XLBOCBBB_MASK
, ISA_V2
, PPCNONE
, {CR
}},
3982 {"bsolr+", XLOCB(19,BOTP4
,CBSO
,16,0), XLBOCBBB_MASK
, ISA_V2
, PPCNONE
, {CR
}},
3983 {"bunlr+", XLOCB(19,BOTP4
,CBSO
,16,0), XLBOCBBB_MASK
, ISA_V2
, PPCNONE
, {CR
}},
3984 {"bsolrl+", XLOCB(19,BOTP4
,CBSO
,16,1), XLBOCBBB_MASK
, ISA_V2
, PPCNONE
, {CR
}},
3985 {"bunlrl+", XLOCB(19,BOTP4
,CBSO
,16,1), XLBOCBBB_MASK
, ISA_V2
, PPCNONE
, {CR
}},
3987 {"bdnzflr", XLO(19,BODNZF
,16,0), XLBOBB_MASK
, PPCCOM
, PPCNONE
, {BI
}},
3988 {"bdnzflr-", XLO(19,BODNZF
,16,0), XLBOBB_MASK
, PPCCOM
, ISA_V2
, {BI
}},
3989 {"bdnzflrl", XLO(19,BODNZF
,16,1), XLBOBB_MASK
, PPCCOM
, PPCNONE
, {BI
}},
3990 {"bdnzflrl-",XLO(19,BODNZF
,16,1), XLBOBB_MASK
, PPCCOM
, ISA_V2
, {BI
}},
3991 {"bdnzflr+", XLO(19,BODNZFP
,16,0), XLBOBB_MASK
, PPCCOM
, ISA_V2
, {BI
}},
3992 {"bdnzflrl+",XLO(19,BODNZFP
,16,1), XLBOBB_MASK
, PPCCOM
, ISA_V2
, {BI
}},
3993 {"bdzflr", XLO(19,BODZF
,16,0), XLBOBB_MASK
, PPCCOM
, PPCNONE
, {BI
}},
3994 {"bdzflr-", XLO(19,BODZF
,16,0), XLBOBB_MASK
, PPCCOM
, ISA_V2
, {BI
}},
3995 {"bdzflrl", XLO(19,BODZF
,16,1), XLBOBB_MASK
, PPCCOM
, PPCNONE
, {BI
}},
3996 {"bdzflrl-", XLO(19,BODZF
,16,1), XLBOBB_MASK
, PPCCOM
, ISA_V2
, {BI
}},
3997 {"bdzflr+", XLO(19,BODZFP
,16,0), XLBOBB_MASK
, PPCCOM
, ISA_V2
, {BI
}},
3998 {"bdzflrl+", XLO(19,BODZFP
,16,1), XLBOBB_MASK
, PPCCOM
, ISA_V2
, {BI
}},
3999 {"bflr", XLO(19,BOF
,16,0), XLBOBB_MASK
, PPCCOM
, PPCNONE
, {BI
}},
4000 {"bflr-", XLO(19,BOF
,16,0), XLBOBB_MASK
, PPCCOM
, ISA_V2
, {BI
}},
4001 {"bbfr", XLO(19,BOF
,16,0), XLBOBB_MASK
, PWRCOM
, PPCNONE
, {BI
}},
4002 {"bflrl", XLO(19,BOF
,16,1), XLBOBB_MASK
, PPCCOM
, PPCNONE
, {BI
}},
4003 {"bflrl-", XLO(19,BOF
,16,1), XLBOBB_MASK
, PPCCOM
, ISA_V2
, {BI
}},
4004 {"bbfrl", XLO(19,BOF
,16,1), XLBOBB_MASK
, PWRCOM
, PPCNONE
, {BI
}},
4005 {"bflr+", XLO(19,BOFP
,16,0), XLBOBB_MASK
, PPCCOM
, ISA_V2
, {BI
}},
4006 {"bflrl+", XLO(19,BOFP
,16,1), XLBOBB_MASK
, PPCCOM
, ISA_V2
, {BI
}},
4007 {"bflr-", XLO(19,BOFM4
,16,0), XLBOBB_MASK
, ISA_V2
, PPCNONE
, {BI
}},
4008 {"bflrl-", XLO(19,BOFM4
,16,1), XLBOBB_MASK
, ISA_V2
, PPCNONE
, {BI
}},
4009 {"bflr+", XLO(19,BOFP4
,16,0), XLBOBB_MASK
, ISA_V2
, PPCNONE
, {BI
}},
4010 {"bflrl+", XLO(19,BOFP4
,16,1), XLBOBB_MASK
, ISA_V2
, PPCNONE
, {BI
}},
4011 {"bdnztlr", XLO(19,BODNZT
,16,0), XLBOBB_MASK
, PPCCOM
, PPCNONE
, {BI
}},
4012 {"bdnztlr-", XLO(19,BODNZT
,16,0), XLBOBB_MASK
, PPCCOM
, ISA_V2
, {BI
}},
4013 {"bdnztlrl", XLO(19,BODNZT
,16,1), XLBOBB_MASK
, PPCCOM
, PPCNONE
, {BI
}},
4014 {"bdnztlrl-",XLO(19,BODNZT
,16,1), XLBOBB_MASK
, PPCCOM
, ISA_V2
, {BI
}},
4015 {"bdnztlr+", XLO(19,BODNZTP
,16,0), XLBOBB_MASK
, PPCCOM
, ISA_V2
, {BI
}},
4016 {"bdnztlrl+",XLO(19,BODNZTP
,16,1), XLBOBB_MASK
, PPCCOM
, ISA_V2
, {BI
}},
4017 {"bdztlr", XLO(19,BODZT
,16,0), XLBOBB_MASK
, PPCCOM
, PPCNONE
, {BI
}},
4018 {"bdztlr-", XLO(19,BODZT
,16,0), XLBOBB_MASK
, PPCCOM
, ISA_V2
, {BI
}},
4019 {"bdztlrl", XLO(19,BODZT
,16,1), XLBOBB_MASK
, PPCCOM
, PPCNONE
, {BI
}},
4020 {"bdztlrl-", XLO(19,BODZT
,16,1), XLBOBB_MASK
, PPCCOM
, ISA_V2
, {BI
}},
4021 {"bdztlr+", XLO(19,BODZTP
,16,0), XLBOBB_MASK
, PPCCOM
, ISA_V2
, {BI
}},
4022 {"bdztlrl+", XLO(19,BODZTP
,16,1), XLBOBB_MASK
, PPCCOM
, ISA_V2
, {BI
}},
4023 {"btlr", XLO(19,BOT
,16,0), XLBOBB_MASK
, PPCCOM
, PPCNONE
, {BI
}},
4024 {"btlr-", XLO(19,BOT
,16,0), XLBOBB_MASK
, PPCCOM
, ISA_V2
, {BI
}},
4025 {"bbtr", XLO(19,BOT
,16,0), XLBOBB_MASK
, PWRCOM
, PPCNONE
, {BI
}},
4026 {"btlrl", XLO(19,BOT
,16,1), XLBOBB_MASK
, PPCCOM
, PPCNONE
, {BI
}},
4027 {"btlrl-", XLO(19,BOT
,16,1), XLBOBB_MASK
, PPCCOM
, ISA_V2
, {BI
}},
4028 {"bbtrl", XLO(19,BOT
,16,1), XLBOBB_MASK
, PWRCOM
, PPCNONE
, {BI
}},
4029 {"btlr+", XLO(19,BOTP
,16,0), XLBOBB_MASK
, PPCCOM
, ISA_V2
, {BI
}},
4030 {"btlrl+", XLO(19,BOTP
,16,1), XLBOBB_MASK
, PPCCOM
, ISA_V2
, {BI
}},
4031 {"btlr-", XLO(19,BOTM4
,16,0), XLBOBB_MASK
, ISA_V2
, PPCNONE
, {BI
}},
4032 {"btlrl-", XLO(19,BOTM4
,16,1), XLBOBB_MASK
, ISA_V2
, PPCNONE
, {BI
}},
4033 {"btlr+", XLO(19,BOTP4
,16,0), XLBOBB_MASK
, ISA_V2
, PPCNONE
, {BI
}},
4034 {"btlrl+", XLO(19,BOTP4
,16,1), XLBOBB_MASK
, ISA_V2
, PPCNONE
, {BI
}},
4036 {"bclr-", XLYLK(19,16,0,0), XLYBB_MASK
, PPCCOM
, PPCNONE
, {BOE
, BI
}},
4037 {"bclrl-", XLYLK(19,16,0,1), XLYBB_MASK
, PPCCOM
, PPCNONE
, {BOE
, BI
}},
4038 {"bclr+", XLYLK(19,16,1,0), XLYBB_MASK
, PPCCOM
, PPCNONE
, {BOE
, BI
}},
4039 {"bclrl+", XLYLK(19,16,1,1), XLYBB_MASK
, PPCCOM
, PPCNONE
, {BOE
, BI
}},
4040 {"bclr", XLLK(19,16,0), XLBH_MASK
, PPCCOM
, PPCNONE
, {BO
, BI
, BH
}},
4041 {"bcr", XLLK(19,16,0), XLBB_MASK
, PWRCOM
, PPCNONE
, {BO
, BI
}},
4042 {"bclrl", XLLK(19,16,1), XLBH_MASK
, PPCCOM
, PPCNONE
, {BO
, BI
, BH
}},
4043 {"bcrl", XLLK(19,16,1), XLBB_MASK
, PWRCOM
, PPCNONE
, {BO
, BI
}},
4045 {"rfid", XL(19,18), 0xffffffff, PPC64
, PPCNONE
, {0}},
4047 {"crnot", XL(19,33), XL_MASK
, PPCCOM
, PPCNONE
, {BT
, BA
, BBA
}},
4048 {"crnor", XL(19,33), XL_MASK
, COM
, PPCNONE
, {BT
, BA
, BB
}},
4049 {"rfmci", X(19,38), 0xffffffff, PPCRFMCI
|PPCA2
|PPC476
, PPCNONE
, {0}},
4051 {"rfdi", XL(19,39), 0xffffffff, E500MC
, PPCNONE
, {0}},
4052 {"rfi", XL(19,50), 0xffffffff, COM
, PPCNONE
, {0}},
4053 {"rfci", XL(19,51), 0xffffffff, PPC403
|BOOKE
|PPCE300
|PPCA2
|PPC476
, PPCNONE
, {0}},
4055 {"rfsvc", XL(19,82), 0xffffffff, POWER
, PPCNONE
, {0}},
4057 {"rfgi", XL(19,102), 0xffffffff, E500MC
|PPCA2
, PPCNONE
, {0}},
4059 {"crandc", XL(19,129), XL_MASK
, COM
, PPCNONE
, {BT
, BA
, BB
}},
4061 {"rfebb", XL(19,146), XLS_MASK
, POWER8
, PPCNONE
, {SXL
}},
4063 {"isync", XL(19,150), 0xffffffff, PPCCOM
, PPCNONE
, {0}},
4064 {"ics", XL(19,150), 0xffffffff, PWRCOM
, PPCNONE
, {0}},
4066 {"crclr", XL(19,193), XL_MASK
, PPCCOM
, PPCNONE
, {BT
, BAT
, BBA
}},
4067 {"crxor", XL(19,193), XL_MASK
, COM
, PPCNONE
, {BT
, BA
, BB
}},
4069 {"dnh", X(19,198), X_MASK
, E500MC
, PPCNONE
, {DUI
, DUIS
}},
4071 {"crnand", XL(19,225), XL_MASK
, COM
, PPCNONE
, {BT
, BA
, BB
}},
4073 {"crand", XL(19,257), XL_MASK
, COM
, PPCNONE
, {BT
, BA
, BB
}},
4075 {"hrfid", XL(19,274), 0xffffffff, POWER5
|CELL
, PPC476
, {0}},
4077 {"crset", XL(19,289), XL_MASK
, PPCCOM
, PPCNONE
, {BT
, BAT
, BBA
}},
4078 {"creqv", XL(19,289), XL_MASK
, COM
, PPCNONE
, {BT
, BA
, BB
}},
4080 {"doze", XL(19,402), 0xffffffff, POWER6
, PPCNONE
, {0}},
4082 {"crorc", XL(19,417), XL_MASK
, COM
, PPCNONE
, {BT
, BA
, BB
}},
4084 {"nap", XL(19,434), 0xffffffff, POWER6
, PPCNONE
, {0}},
4086 {"crmove", XL(19,449), XL_MASK
, PPCCOM
, PPCNONE
, {BT
, BA
, BBA
}},
4087 {"cror", XL(19,449), XL_MASK
, COM
, PPCNONE
, {BT
, BA
, BB
}},
4089 {"sleep", XL(19,466), 0xffffffff, POWER6
, PPCNONE
, {0}},
4090 {"rvwinkle", XL(19,498), 0xffffffff, POWER6
, PPCNONE
, {0}},
4092 {"bctr", XLO(19,BOU
,528,0), XLBOBIBB_MASK
, COM
, PPCNONE
, {0}},
4093 {"bctrl", XLO(19,BOU
,528,1), XLBOBIBB_MASK
, COM
, PPCNONE
, {0}},
4095 {"bgectr", XLOCB(19,BOF
,CBLT
,528,0), XLBOCBBB_MASK
, PPCCOM
, PPCNONE
, {CR
}},
4096 {"bgectr-", XLOCB(19,BOF
,CBLT
,528,0), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
, {CR
}},
4097 {"bnlctr", XLOCB(19,BOF
,CBLT
,528,0), XLBOCBBB_MASK
, PPCCOM
, PPCNONE
, {CR
}},
4098 {"bnlctr-", XLOCB(19,BOF
,CBLT
,528,0), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
, {CR
}},
4099 {"bgectrl", XLOCB(19,BOF
,CBLT
,528,1), XLBOCBBB_MASK
, PPCCOM
, PPCNONE
, {CR
}},
4100 {"bgectrl-",XLOCB(19,BOF
,CBLT
,528,1), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
, {CR
}},
4101 {"bnlctrl", XLOCB(19,BOF
,CBLT
,528,1), XLBOCBBB_MASK
, PPCCOM
, PPCNONE
, {CR
}},
4102 {"bnlctrl-",XLOCB(19,BOF
,CBLT
,528,1), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
, {CR
}},
4103 {"blectr", XLOCB(19,BOF
,CBGT
,528,0), XLBOCBBB_MASK
, PPCCOM
, PPCNONE
, {CR
}},
4104 {"blectr-", XLOCB(19,BOF
,CBGT
,528,0), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
, {CR
}},
4105 {"bngctr", XLOCB(19,BOF
,CBGT
,528,0), XLBOCBBB_MASK
, PPCCOM
, PPCNONE
, {CR
}},
4106 {"bngctr-", XLOCB(19,BOF
,CBGT
,528,0), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
, {CR
}},
4107 {"blectrl", XLOCB(19,BOF
,CBGT
,528,1), XLBOCBBB_MASK
, PPCCOM
, PPCNONE
, {CR
}},
4108 {"blectrl-",XLOCB(19,BOF
,CBGT
,528,1), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
, {CR
}},
4109 {"bngctrl", XLOCB(19,BOF
,CBGT
,528,1), XLBOCBBB_MASK
, PPCCOM
, PPCNONE
, {CR
}},
4110 {"bngctrl-",XLOCB(19,BOF
,CBGT
,528,1), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
, {CR
}},
4111 {"bnectr", XLOCB(19,BOF
,CBEQ
,528,0), XLBOCBBB_MASK
, PPCCOM
, PPCNONE
, {CR
}},
4112 {"bnectr-", XLOCB(19,BOF
,CBEQ
,528,0), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
, {CR
}},
4113 {"bnectrl", XLOCB(19,BOF
,CBEQ
,528,1), XLBOCBBB_MASK
, PPCCOM
, PPCNONE
, {CR
}},
4114 {"bnectrl-",XLOCB(19,BOF
,CBEQ
,528,1), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
, {CR
}},
4115 {"bnsctr", XLOCB(19,BOF
,CBSO
,528,0), XLBOCBBB_MASK
, PPCCOM
, PPCNONE
, {CR
}},
4116 {"bnsctr-", XLOCB(19,BOF
,CBSO
,528,0), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
, {CR
}},
4117 {"bnuctr", XLOCB(19,BOF
,CBSO
,528,0), XLBOCBBB_MASK
, PPCCOM
, PPCNONE
, {CR
}},
4118 {"bnuctr-", XLOCB(19,BOF
,CBSO
,528,0), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
, {CR
}},
4119 {"bnsctrl", XLOCB(19,BOF
,CBSO
,528,1), XLBOCBBB_MASK
, PPCCOM
, PPCNONE
, {CR
}},
4120 {"bnsctrl-",XLOCB(19,BOF
,CBSO
,528,1), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
, {CR
}},
4121 {"bnuctrl", XLOCB(19,BOF
,CBSO
,528,1), XLBOCBBB_MASK
, PPCCOM
, PPCNONE
, {CR
}},
4122 {"bnuctrl-",XLOCB(19,BOF
,CBSO
,528,1), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
, {CR
}},
4123 {"bgectr+", XLOCB(19,BOFP
,CBLT
,528,0), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
, {CR
}},
4124 {"bnlctr+", XLOCB(19,BOFP
,CBLT
,528,0), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
, {CR
}},
4125 {"bgectrl+",XLOCB(19,BOFP
,CBLT
,528,1), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
, {CR
}},
4126 {"bnlctrl+",XLOCB(19,BOFP
,CBLT
,528,1), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
, {CR
}},
4127 {"blectr+", XLOCB(19,BOFP
,CBGT
,528,0), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
, {CR
}},
4128 {"bngctr+", XLOCB(19,BOFP
,CBGT
,528,0), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
, {CR
}},
4129 {"blectrl+",XLOCB(19,BOFP
,CBGT
,528,1), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
, {CR
}},
4130 {"bngctrl+",XLOCB(19,BOFP
,CBGT
,528,1), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
, {CR
}},
4131 {"bnectr+", XLOCB(19,BOFP
,CBEQ
,528,0), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
, {CR
}},
4132 {"bnectrl+",XLOCB(19,BOFP
,CBEQ
,528,1), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
, {CR
}},
4133 {"bnsctr+", XLOCB(19,BOFP
,CBSO
,528,0), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
, {CR
}},
4134 {"bnuctr+", XLOCB(19,BOFP
,CBSO
,528,0), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
, {CR
}},
4135 {"bnsctrl+",XLOCB(19,BOFP
,CBSO
,528,1), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
, {CR
}},
4136 {"bnuctrl+",XLOCB(19,BOFP
,CBSO
,528,1), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
, {CR
}},
4137 {"bgectr-", XLOCB(19,BOFM4
,CBLT
,528,0), XLBOCBBB_MASK
, ISA_V2
, PPCNONE
, {CR
}},
4138 {"bnlctr-", XLOCB(19,BOFM4
,CBLT
,528,0), XLBOCBBB_MASK
, ISA_V2
, PPCNONE
, {CR
}},
4139 {"bgectrl-",XLOCB(19,BOFM4
,CBLT
,528,1), XLBOCBBB_MASK
, ISA_V2
, PPCNONE
, {CR
}},
4140 {"bnlctrl-",XLOCB(19,BOFM4
,CBLT
,528,1), XLBOCBBB_MASK
, ISA_V2
, PPCNONE
, {CR
}},
4141 {"blectr-", XLOCB(19,BOFM4
,CBGT
,528,0), XLBOCBBB_MASK
, ISA_V2
, PPCNONE
, {CR
}},
4142 {"bngctr-", XLOCB(19,BOFM4
,CBGT
,528,0), XLBOCBBB_MASK
, ISA_V2
, PPCNONE
, {CR
}},
4143 {"blectrl-",XLOCB(19,BOFM4
,CBGT
,528,1), XLBOCBBB_MASK
, ISA_V2
, PPCNONE
, {CR
}},
4144 {"bngctrl-",XLOCB(19,BOFM4
,CBGT
,528,1), XLBOCBBB_MASK
, ISA_V2
, PPCNONE
, {CR
}},
4145 {"bnectr-", XLOCB(19,BOFM4
,CBEQ
,528,0), XLBOCBBB_MASK
, ISA_V2
, PPCNONE
, {CR
}},
4146 {"bnectrl-",XLOCB(19,BOFM4
,CBEQ
,528,1), XLBOCBBB_MASK
, ISA_V2
, PPCNONE
, {CR
}},
4147 {"bnsctr-", XLOCB(19,BOFM4
,CBSO
,528,0), XLBOCBBB_MASK
, ISA_V2
, PPCNONE
, {CR
}},
4148 {"bnuctr-", XLOCB(19,BOFM4
,CBSO
,528,0), XLBOCBBB_MASK
, ISA_V2
, PPCNONE
, {CR
}},
4149 {"bnsctrl-",XLOCB(19,BOFM4
,CBSO
,528,1), XLBOCBBB_MASK
, ISA_V2
, PPCNONE
, {CR
}},
4150 {"bnuctrl-",XLOCB(19,BOFM4
,CBSO
,528,1), XLBOCBBB_MASK
, ISA_V2
, PPCNONE
, {CR
}},
4151 {"bgectr+", XLOCB(19,BOFP4
,CBLT
,528,0), XLBOCBBB_MASK
, ISA_V2
, PPCNONE
, {CR
}},
4152 {"bnlctr+", XLOCB(19,BOFP4
,CBLT
,528,0), XLBOCBBB_MASK
, ISA_V2
, PPCNONE
, {CR
}},
4153 {"bgectrl+",XLOCB(19,BOFP4
,CBLT
,528,1), XLBOCBBB_MASK
, ISA_V2
, PPCNONE
, {CR
}},
4154 {"bnlctrl+",XLOCB(19,BOFP4
,CBLT
,528,1), XLBOCBBB_MASK
, ISA_V2
, PPCNONE
, {CR
}},
4155 {"blectr+", XLOCB(19,BOFP4
,CBGT
,528,0), XLBOCBBB_MASK
, ISA_V2
, PPCNONE
, {CR
}},
4156 {"bngctr+", XLOCB(19,BOFP4
,CBGT
,528,0), XLBOCBBB_MASK
, ISA_V2
, PPCNONE
, {CR
}},
4157 {"blectrl+",XLOCB(19,BOFP4
,CBGT
,528,1), XLBOCBBB_MASK
, ISA_V2
, PPCNONE
, {CR
}},
4158 {"bngctrl+",XLOCB(19,BOFP4
,CBGT
,528,1), XLBOCBBB_MASK
, ISA_V2
, PPCNONE
, {CR
}},
4159 {"bnectr+", XLOCB(19,BOFP4
,CBEQ
,528,0), XLBOCBBB_MASK
, ISA_V2
, PPCNONE
, {CR
}},
4160 {"bnectrl+",XLOCB(19,BOFP4
,CBEQ
,528,1), XLBOCBBB_MASK
, ISA_V2
, PPCNONE
, {CR
}},
4161 {"bnsctr+", XLOCB(19,BOFP4
,CBSO
,528,0), XLBOCBBB_MASK
, ISA_V2
, PPCNONE
, {CR
}},
4162 {"bnuctr+", XLOCB(19,BOFP4
,CBSO
,528,0), XLBOCBBB_MASK
, ISA_V2
, PPCNONE
, {CR
}},
4163 {"bnsctrl+",XLOCB(19,BOFP4
,CBSO
,528,1), XLBOCBBB_MASK
, ISA_V2
, PPCNONE
, {CR
}},
4164 {"bnuctrl+",XLOCB(19,BOFP4
,CBSO
,528,1), XLBOCBBB_MASK
, ISA_V2
, PPCNONE
, {CR
}},
4165 {"bltctr", XLOCB(19,BOT
,CBLT
,528,0), XLBOCBBB_MASK
, PPCCOM
, PPCNONE
, {CR
}},
4166 {"bltctr-", XLOCB(19,BOT
,CBLT
,528,0), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
, {CR
}},
4167 {"bltctrl", XLOCB(19,BOT
,CBLT
,528,1), XLBOCBBB_MASK
, PPCCOM
, PPCNONE
, {CR
}},
4168 {"bltctrl-",XLOCB(19,BOT
,CBLT
,528,1), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
, {CR
}},
4169 {"bgtctr", XLOCB(19,BOT
,CBGT
,528,0), XLBOCBBB_MASK
, PPCCOM
, PPCNONE
, {CR
}},
4170 {"bgtctr-", XLOCB(19,BOT
,CBGT
,528,0), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
, {CR
}},
4171 {"bgtctrl", XLOCB(19,BOT
,CBGT
,528,1), XLBOCBBB_MASK
, PPCCOM
, PPCNONE
, {CR
}},
4172 {"bgtctrl-",XLOCB(19,BOT
,CBGT
,528,1), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
, {CR
}},
4173 {"beqctr", XLOCB(19,BOT
,CBEQ
,528,0), XLBOCBBB_MASK
, PPCCOM
, PPCNONE
, {CR
}},
4174 {"beqctr-", XLOCB(19,BOT
,CBEQ
,528,0), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
, {CR
}},
4175 {"beqctrl", XLOCB(19,BOT
,CBEQ
,528,1), XLBOCBBB_MASK
, PPCCOM
, PPCNONE
, {CR
}},
4176 {"beqctrl-",XLOCB(19,BOT
,CBEQ
,528,1), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
, {CR
}},
4177 {"bsoctr", XLOCB(19,BOT
,CBSO
,528,0), XLBOCBBB_MASK
, PPCCOM
, PPCNONE
, {CR
}},
4178 {"bsoctr-", XLOCB(19,BOT
,CBSO
,528,0), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
, {CR
}},
4179 {"bunctr", XLOCB(19,BOT
,CBSO
,528,0), XLBOCBBB_MASK
, PPCCOM
, PPCNONE
, {CR
}},
4180 {"bunctr-", XLOCB(19,BOT
,CBSO
,528,0), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
, {CR
}},
4181 {"bsoctrl", XLOCB(19,BOT
,CBSO
,528,1), XLBOCBBB_MASK
, PPCCOM
, PPCNONE
, {CR
}},
4182 {"bsoctrl-",XLOCB(19,BOT
,CBSO
,528,1), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
, {CR
}},
4183 {"bunctrl", XLOCB(19,BOT
,CBSO
,528,1), XLBOCBBB_MASK
, PPCCOM
, PPCNONE
, {CR
}},
4184 {"bunctrl-",XLOCB(19,BOT
,CBSO
,528,1), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
, {CR
}},
4185 {"bltctr+", XLOCB(19,BOTP
,CBLT
,528,0), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
, {CR
}},
4186 {"bltctrl+",XLOCB(19,BOTP
,CBLT
,528,1), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
, {CR
}},
4187 {"bgtctr+", XLOCB(19,BOTP
,CBGT
,528,0), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
, {CR
}},
4188 {"bgtctrl+",XLOCB(19,BOTP
,CBGT
,528,1), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
, {CR
}},
4189 {"beqctr+", XLOCB(19,BOTP
,CBEQ
,528,0), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
, {CR
}},
4190 {"beqctrl+",XLOCB(19,BOTP
,CBEQ
,528,1), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
, {CR
}},
4191 {"bsoctr+", XLOCB(19,BOTP
,CBSO
,528,0), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
, {CR
}},
4192 {"bunctr+", XLOCB(19,BOTP
,CBSO
,528,0), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
, {CR
}},
4193 {"bsoctrl+",XLOCB(19,BOTP
,CBSO
,528,1), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
, {CR
}},
4194 {"bunctrl+",XLOCB(19,BOTP
,CBSO
,528,1), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
, {CR
}},
4195 {"bltctr-", XLOCB(19,BOTM4
,CBLT
,528,0), XLBOCBBB_MASK
, ISA_V2
, PPCNONE
, {CR
}},
4196 {"bltctrl-",XLOCB(19,BOTM4
,CBLT
,528,1), XLBOCBBB_MASK
, ISA_V2
, PPCNONE
, {CR
}},
4197 {"bgtctr-", XLOCB(19,BOTM4
,CBGT
,528,0), XLBOCBBB_MASK
, ISA_V2
, PPCNONE
, {CR
}},
4198 {"bgtctrl-",XLOCB(19,BOTM4
,CBGT
,528,1), XLBOCBBB_MASK
, ISA_V2
, PPCNONE
, {CR
}},
4199 {"beqctr-", XLOCB(19,BOTM4
,CBEQ
,528,0), XLBOCBBB_MASK
, ISA_V2
, PPCNONE
, {CR
}},
4200 {"beqctrl-",XLOCB(19,BOTM4
,CBEQ
,528,1), XLBOCBBB_MASK
, ISA_V2
, PPCNONE
, {CR
}},
4201 {"bsoctr-", XLOCB(19,BOTM4
,CBSO
,528,0), XLBOCBBB_MASK
, ISA_V2
, PPCNONE
, {CR
}},
4202 {"bunctr-", XLOCB(19,BOTM4
,CBSO
,528,0), XLBOCBBB_MASK
, ISA_V2
, PPCNONE
, {CR
}},
4203 {"bsoctrl-",XLOCB(19,BOTM4
,CBSO
,528,1), XLBOCBBB_MASK
, ISA_V2
, PPCNONE
, {CR
}},
4204 {"bunctrl-",XLOCB(19,BOTM4
,CBSO
,528,1), XLBOCBBB_MASK
, ISA_V2
, PPCNONE
, {CR
}},
4205 {"bltctr+", XLOCB(19,BOTP4
,CBLT
,528,0), XLBOCBBB_MASK
, ISA_V2
, PPCNONE
, {CR
}},
4206 {"bltctrl+",XLOCB(19,BOTP4
,CBLT
,528,1), XLBOCBBB_MASK
, ISA_V2
, PPCNONE
, {CR
}},
4207 {"bgtctr+", XLOCB(19,BOTP4
,CBGT
,528,0), XLBOCBBB_MASK
, ISA_V2
, PPCNONE
, {CR
}},
4208 {"bgtctrl+",XLOCB(19,BOTP4
,CBGT
,528,1), XLBOCBBB_MASK
, ISA_V2
, PPCNONE
, {CR
}},
4209 {"beqctr+", XLOCB(19,BOTP4
,CBEQ
,528,0), XLBOCBBB_MASK
, ISA_V2
, PPCNONE
, {CR
}},
4210 {"beqctrl+",XLOCB(19,BOTP4
,CBEQ
,528,1), XLBOCBBB_MASK
, ISA_V2
, PPCNONE
, {CR
}},
4211 {"bsoctr+", XLOCB(19,BOTP4
,CBSO
,528,0), XLBOCBBB_MASK
, ISA_V2
, PPCNONE
, {CR
}},
4212 {"bunctr+", XLOCB(19,BOTP4
,CBSO
,528,0), XLBOCBBB_MASK
, ISA_V2
, PPCNONE
, {CR
}},
4213 {"bsoctrl+",XLOCB(19,BOTP4
,CBSO
,528,1), XLBOCBBB_MASK
, ISA_V2
, PPCNONE
, {CR
}},
4214 {"bunctrl+",XLOCB(19,BOTP4
,CBSO
,528,1), XLBOCBBB_MASK
, ISA_V2
, PPCNONE
, {CR
}},
4216 {"bfctr", XLO(19,BOF
,528,0), XLBOBB_MASK
, PPCCOM
, PPCNONE
, {BI
}},
4217 {"bfctr-", XLO(19,BOF
,528,0), XLBOBB_MASK
, PPCCOM
, ISA_V2
, {BI
}},
4218 {"bfctrl", XLO(19,BOF
,528,1), XLBOBB_MASK
, PPCCOM
, PPCNONE
, {BI
}},
4219 {"bfctrl-", XLO(19,BOF
,528,1), XLBOBB_MASK
, PPCCOM
, ISA_V2
, {BI
}},
4220 {"bfctr+", XLO(19,BOFP
,528,0), XLBOBB_MASK
, PPCCOM
, ISA_V2
, {BI
}},
4221 {"bfctrl+", XLO(19,BOFP
,528,1), XLBOBB_MASK
, PPCCOM
, ISA_V2
, {BI
}},
4222 {"bfctr-", XLO(19,BOFM4
,528,0), XLBOBB_MASK
, ISA_V2
, PPCNONE
, {BI
}},
4223 {"bfctrl-", XLO(19,BOFM4
,528,1), XLBOBB_MASK
, ISA_V2
, PPCNONE
, {BI
}},
4224 {"bfctr+", XLO(19,BOFP4
,528,0), XLBOBB_MASK
, ISA_V2
, PPCNONE
, {BI
}},
4225 {"bfctrl+", XLO(19,BOFP4
,528,1), XLBOBB_MASK
, ISA_V2
, PPCNONE
, {BI
}},
4226 {"btctr", XLO(19,BOT
,528,0), XLBOBB_MASK
, PPCCOM
, PPCNONE
, {BI
}},
4227 {"btctr-", XLO(19,BOT
,528,0), XLBOBB_MASK
, PPCCOM
, ISA_V2
, {BI
}},
4228 {"btctrl", XLO(19,BOT
,528,1), XLBOBB_MASK
, PPCCOM
, PPCNONE
, {BI
}},
4229 {"btctrl-", XLO(19,BOT
,528,1), XLBOBB_MASK
, PPCCOM
, ISA_V2
, {BI
}},
4230 {"btctr+", XLO(19,BOTP
,528,0), XLBOBB_MASK
, PPCCOM
, ISA_V2
, {BI
}},
4231 {"btctrl+", XLO(19,BOTP
,528,1), XLBOBB_MASK
, PPCCOM
, ISA_V2
, {BI
}},
4232 {"btctr-", XLO(19,BOTM4
,528,0), XLBOBB_MASK
, ISA_V2
, PPCNONE
, {BI
}},
4233 {"btctrl-", XLO(19,BOTM4
,528,1), XLBOBB_MASK
, ISA_V2
, PPCNONE
, {BI
}},
4234 {"btctr+", XLO(19,BOTP4
,528,0), XLBOBB_MASK
, ISA_V2
, PPCNONE
, {BI
}},
4235 {"btctrl+", XLO(19,BOTP4
,528,1), XLBOBB_MASK
, ISA_V2
, PPCNONE
, {BI
}},
4237 {"bcctr-", XLYLK(19,528,0,0), XLYBB_MASK
, PPCCOM
, PPCNONE
, {BOE
, BI
}},
4238 {"bcctrl-", XLYLK(19,528,0,1), XLYBB_MASK
, PPCCOM
, PPCNONE
, {BOE
, BI
}},
4239 {"bcctr+", XLYLK(19,528,1,0), XLYBB_MASK
, PPCCOM
, PPCNONE
, {BOE
, BI
}},
4240 {"bcctrl+", XLYLK(19,528,1,1), XLYBB_MASK
, PPCCOM
, PPCNONE
, {BOE
, BI
}},
4241 {"bcctr", XLLK(19,528,0), XLBH_MASK
, PPCCOM
, PPCNONE
, {BO
, BI
, BH
}},
4242 {"bcc", XLLK(19,528,0), XLBB_MASK
, PWRCOM
, PPCNONE
, {BO
, BI
}},
4243 {"bcctrl", XLLK(19,528,1), XLBH_MASK
, PPCCOM
, PPCNONE
, {BO
, BI
, BH
}},
4244 {"bccl", XLLK(19,528,1), XLBB_MASK
, PWRCOM
, PPCNONE
, {BO
, BI
}},
4246 {"bctar-", XLYLK(19,560,0,0), XLYBB_MASK
, POWER8
, PPCNONE
, {BOE
, BI
}},
4247 {"bctarl-", XLYLK(19,560,0,1), XLYBB_MASK
, POWER8
, PPCNONE
, {BOE
, BI
}},
4248 {"bctar+", XLYLK(19,560,1,0), XLYBB_MASK
, POWER8
, PPCNONE
, {BOE
, BI
}},
4249 {"bctarl+", XLYLK(19,560,1,1), XLYBB_MASK
, POWER8
, PPCNONE
, {BOE
, BI
}},
4250 {"bctar", XLLK(19,560,0), XLBH_MASK
, POWER8
, PPCNONE
, {BO
, BI
, BH
}},
4251 {"bctarl", XLLK(19,560,1), XLBH_MASK
, POWER8
, PPCNONE
, {BO
, BI
, BH
}},
4253 {"rlwimi", M(20,0), M_MASK
, PPCCOM
, PPCNONE
, {RA
, RS
, SH
, MBE
, ME
}},
4254 {"rlimi", M(20,0), M_MASK
, PWRCOM
, PPCNONE
, {RA
, RS
, SH
, MBE
, ME
}},
4256 {"rlwimi.", M(20,1), M_MASK
, PPCCOM
, PPCNONE
, {RA
, RS
, SH
, MBE
, ME
}},
4257 {"rlimi.", M(20,1), M_MASK
, PWRCOM
, PPCNONE
, {RA
, RS
, SH
, MBE
, ME
}},
4259 {"rotlwi", MME(21,31,0), MMBME_MASK
, PPCCOM
, PPCNONE
, {RA
, RS
, SH
}},
4260 {"clrlwi", MME(21,31,0), MSHME_MASK
, PPCCOM
, PPCNONE
, {RA
, RS
, MB
}},
4261 {"rlwinm", M(21,0), M_MASK
, PPCCOM
, PPCNONE
, {RA
, RS
, SH
, MBE
, ME
}},
4262 {"rlinm", M(21,0), M_MASK
, PWRCOM
, PPCNONE
, {RA
, RS
, SH
, MBE
, ME
}},
4263 {"rotlwi.", MME(21,31,1), MMBME_MASK
, PPCCOM
, PPCNONE
, {RA
, RS
, SH
}},
4264 {"clrlwi.", MME(21,31,1), MSHME_MASK
, PPCCOM
, PPCNONE
, {RA
, RS
, MB
}},
4265 {"rlwinm.", M(21,1), M_MASK
, PPCCOM
, PPCNONE
, {RA
, RS
, SH
, MBE
, ME
}},
4266 {"rlinm.", M(21,1), M_MASK
, PWRCOM
, PPCNONE
, {RA
, RS
, SH
, MBE
, ME
}},
4268 {"rlmi", M(22,0), M_MASK
, M601
, PPCNONE
, {RA
, RS
, RB
, MBE
, ME
}},
4269 {"rlmi.", M(22,1), M_MASK
, M601
, PPCNONE
, {RA
, RS
, RB
, MBE
, ME
}},
4271 {"rotlw", MME(23,31,0), MMBME_MASK
, PPCCOM
, PPCNONE
, {RA
, RS
, RB
}},
4272 {"rlwnm", M(23,0), M_MASK
, PPCCOM
, PPCNONE
, {RA
, RS
, RB
, MBE
, ME
}},
4273 {"rlnm", M(23,0), M_MASK
, PWRCOM
, PPCNONE
, {RA
, RS
, RB
, MBE
, ME
}},
4274 {"rotlw.", MME(23,31,1), MMBME_MASK
, PPCCOM
, PPCNONE
, {RA
, RS
, RB
}},
4275 {"rlwnm.", M(23,1), M_MASK
, PPCCOM
, PPCNONE
, {RA
, RS
, RB
, MBE
, ME
}},
4276 {"rlnm.", M(23,1), M_MASK
, PWRCOM
, PPCNONE
, {RA
, RS
, RB
, MBE
, ME
}},
4278 {"nop", OP(24), 0xffffffff, PPCCOM
, PPCNONE
, {0}},
4279 {"ori", OP(24), OP_MASK
, PPCCOM
, PPCNONE
, {RA
, RS
, UI
}},
4280 {"oril", OP(24), OP_MASK
, PWRCOM
, PPCNONE
, {RA
, RS
, UI
}},
4282 {"oris", OP(25), OP_MASK
, PPCCOM
, PPCNONE
, {RA
, RS
, UI
}},
4283 {"oriu", OP(25), OP_MASK
, PWRCOM
, PPCNONE
, {RA
, RS
, UI
}},
4285 {"xnop", OP(26), 0xffffffff, PPCCOM
, PPCNONE
, {0}},
4286 {"xori", OP(26), OP_MASK
, PPCCOM
, PPCNONE
, {RA
, RS
, UI
}},
4287 {"xoril", OP(26), OP_MASK
, PWRCOM
, PPCNONE
, {RA
, RS
, UI
}},
4289 {"xoris", OP(27), OP_MASK
, PPCCOM
, PPCNONE
, {RA
, RS
, UI
}},
4290 {"xoriu", OP(27), OP_MASK
, PWRCOM
, PPCNONE
, {RA
, RS
, UI
}},
4292 {"andi.", OP(28), OP_MASK
, PPCCOM
, PPCNONE
, {RA
, RS
, UI
}},
4293 {"andil.", OP(28), OP_MASK
, PWRCOM
, PPCNONE
, {RA
, RS
, UI
}},
4295 {"andis.", OP(29), OP_MASK
, PPCCOM
, PPCNONE
, {RA
, RS
, UI
}},
4296 {"andiu.", OP(29), OP_MASK
, PWRCOM
, PPCNONE
, {RA
, RS
, UI
}},
4298 {"rotldi", MD(30,0,0), MDMB_MASK
, PPC64
, PPCNONE
, {RA
, RS
, SH6
}},
4299 {"clrldi", MD(30,0,0), MDSH_MASK
, PPC64
, PPCNONE
, {RA
, RS
, MB6
}},
4300 {"rldicl", MD(30,0,0), MD_MASK
, PPC64
, PPCNONE
, {RA
, RS
, SH6
, MB6
}},
4301 {"rotldi.", MD(30,0,1), MDMB_MASK
, PPC64
, PPCNONE
, {RA
, RS
, SH6
}},
4302 {"clrldi.", MD(30,0,1), MDSH_MASK
, PPC64
, PPCNONE
, {RA
, RS
, MB6
}},
4303 {"rldicl.", MD(30,0,1), MD_MASK
, PPC64
, PPCNONE
, {RA
, RS
, SH6
, MB6
}},
4305 {"rldicr", MD(30,1,0), MD_MASK
, PPC64
, PPCNONE
, {RA
, RS
, SH6
, ME6
}},
4306 {"rldicr.", MD(30,1,1), MD_MASK
, PPC64
, PPCNONE
, {RA
, RS
, SH6
, ME6
}},
4308 {"rldic", MD(30,2,0), MD_MASK
, PPC64
, PPCNONE
, {RA
, RS
, SH6
, MB6
}},
4309 {"rldic.", MD(30,2,1), MD_MASK
, PPC64
, PPCNONE
, {RA
, RS
, SH6
, MB6
}},
4311 {"rldimi", MD(30,3,0), MD_MASK
, PPC64
, PPCNONE
, {RA
, RS
, SH6
, MB6
}},
4312 {"rldimi.", MD(30,3,1), MD_MASK
, PPC64
, PPCNONE
, {RA
, RS
, SH6
, MB6
}},
4314 {"rotld", MDS(30,8,0), MDSMB_MASK
, PPC64
, PPCNONE
, {RA
, RS
, RB
}},
4315 {"rldcl", MDS(30,8,0), MDS_MASK
, PPC64
, PPCNONE
, {RA
, RS
, RB
, MB6
}},
4316 {"rotld.", MDS(30,8,1), MDSMB_MASK
, PPC64
, PPCNONE
, {RA
, RS
, RB
}},
4317 {"rldcl.", MDS(30,8,1), MDS_MASK
, PPC64
, PPCNONE
, {RA
, RS
, RB
, MB6
}},
4319 {"rldcr", MDS(30,9,0), MDS_MASK
, PPC64
, PPCNONE
, {RA
, RS
, RB
, ME6
}},
4320 {"rldcr.", MDS(30,9,1), MDS_MASK
, PPC64
, PPCNONE
, {RA
, RS
, RB
, ME6
}},
4322 {"cmpw", XOPL(31,0,0), XCMPL_MASK
, PPCCOM
, PPCNONE
, {OBF
, RA
, RB
}},
4323 {"cmpd", XOPL(31,0,1), XCMPL_MASK
, PPC64
, PPCNONE
, {OBF
, RA
, RB
}},
4324 {"cmp", X(31,0), XCMP_MASK
, PPC
|PPCVLE
, PPCNONE
, {BF
, L
, RA
, RB
}},
4325 {"cmp", X(31,0), XCMPL_MASK
, PWRCOM
, PPC
, {BF
, RA
, RB
}},
4327 {"twlgt", XTO(31,4,TOLGT
), XTO_MASK
, PPCCOM
|PPCVLE
, PPCNONE
, {RA
, RB
}},
4328 {"tlgt", XTO(31,4,TOLGT
), XTO_MASK
, PWRCOM
, PPCNONE
, {RA
, RB
}},
4329 {"twllt", XTO(31,4,TOLLT
), XTO_MASK
, PPCCOM
|PPCVLE
, PPCNONE
, {RA
, RB
}},
4330 {"tllt", XTO(31,4,TOLLT
), XTO_MASK
, PWRCOM
, PPCNONE
, {RA
, RB
}},
4331 {"tweq", XTO(31,4,TOEQ
), XTO_MASK
, PPCCOM
|PPCVLE
, PPCNONE
, {RA
, RB
}},
4332 {"teq", XTO(31,4,TOEQ
), XTO_MASK
, PWRCOM
, PPCNONE
, {RA
, RB
}},
4333 {"twlge", XTO(31,4,TOLGE
), XTO_MASK
, PPCCOM
|PPCVLE
, PPCNONE
, {RA
, RB
}},
4334 {"tlge", XTO(31,4,TOLGE
), XTO_MASK
, PWRCOM
, PPCNONE
, {RA
, RB
}},
4335 {"twlnl", XTO(31,4,TOLNL
), XTO_MASK
, PPCCOM
|PPCVLE
, PPCNONE
, {RA
, RB
}},
4336 {"tlnl", XTO(31,4,TOLNL
), XTO_MASK
, PWRCOM
, PPCNONE
, {RA
, RB
}},
4337 {"twlle", XTO(31,4,TOLLE
), XTO_MASK
, PPCCOM
|PPCVLE
, PPCNONE
, {RA
, RB
}},
4338 {"tlle", XTO(31,4,TOLLE
), XTO_MASK
, PWRCOM
, PPCNONE
, {RA
, RB
}},
4339 {"twlng", XTO(31,4,TOLNG
), XTO_MASK
, PPCCOM
|PPCVLE
, PPCNONE
, {RA
, RB
}},
4340 {"tlng", XTO(31,4,TOLNG
), XTO_MASK
, PWRCOM
, PPCNONE
, {RA
, RB
}},
4341 {"twgt", XTO(31,4,TOGT
), XTO_MASK
, PPCCOM
|PPCVLE
, PPCNONE
, {RA
, RB
}},
4342 {"tgt", XTO(31,4,TOGT
), XTO_MASK
, PWRCOM
, PPCNONE
, {RA
, RB
}},
4343 {"twge", XTO(31,4,TOGE
), XTO_MASK
, PPCCOM
|PPCVLE
, PPCNONE
, {RA
, RB
}},
4344 {"tge", XTO(31,4,TOGE
), XTO_MASK
, PWRCOM
, PPCNONE
, {RA
, RB
}},
4345 {"twnl", XTO(31,4,TONL
), XTO_MASK
, PPCCOM
|PPCVLE
, PPCNONE
, {RA
, RB
}},
4346 {"tnl", XTO(31,4,TONL
), XTO_MASK
, PWRCOM
, PPCNONE
, {RA
, RB
}},
4347 {"twlt", XTO(31,4,TOLT
), XTO_MASK
, PPCCOM
|PPCVLE
, PPCNONE
, {RA
, RB
}},
4348 {"tlt", XTO(31,4,TOLT
), XTO_MASK
, PWRCOM
, PPCNONE
, {RA
, RB
}},
4349 {"twle", XTO(31,4,TOLE
), XTO_MASK
, PPCCOM
|PPCVLE
, PPCNONE
, {RA
, RB
}},
4350 {"tle", XTO(31,4,TOLE
), XTO_MASK
, PWRCOM
, PPCNONE
, {RA
, RB
}},
4351 {"twng", XTO(31,4,TONG
), XTO_MASK
, PPCCOM
|PPCVLE
, PPCNONE
, {RA
, RB
}},
4352 {"tng", XTO(31,4,TONG
), XTO_MASK
, PWRCOM
, PPCNONE
, {RA
, RB
}},
4353 {"twne", XTO(31,4,TONE
), XTO_MASK
, PPCCOM
|PPCVLE
, PPCNONE
, {RA
, RB
}},
4354 {"tne", XTO(31,4,TONE
), XTO_MASK
, PWRCOM
, PPCNONE
, {RA
, RB
}},
4355 {"trap", XTO(31,4,TOU
), 0xffffffff, PPCCOM
|PPCVLE
, PPCNONE
, {0}},
4356 {"twu", XTO(31,4,TOU
), XTO_MASK
, PPCCOM
|PPCVLE
, PPCNONE
, {RA
, RB
}},
4357 {"tu", XTO(31,4,TOU
), XTO_MASK
, PWRCOM
, PPCNONE
, {RA
, RB
}},
4358 {"tw", X(31,4), X_MASK
, PPCCOM
|PPCVLE
, PPCNONE
, {TO
, RA
, RB
}},
4359 {"t", X(31,4), X_MASK
, PWRCOM
, PPCNONE
, {TO
, RA
, RB
}},
4361 {"lvsl", X(31,6), X_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, RA0
, RB
}},
4362 {"lvebx", X(31,7), X_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, RA0
, RB
}},
4363 {"lbfcmx", APU(31,7,0), APU_MASK
, PPC405
, PPCNONE
, {FCRT
, RA
, RB
}},
4365 {"subfc", XO(31,8,0,0), XO_MASK
, PPCCOM
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
4366 {"sf", XO(31,8,0,0), XO_MASK
, PWRCOM
, PPCNONE
, {RT
, RA
, RB
}},
4367 {"subc", XO(31,8,0,0), XO_MASK
, PPCCOM
|PPCVLE
, PPCNONE
, {RT
, RB
, RA
}},
4368 {"subfc.", XO(31,8,0,1), XO_MASK
, PPCCOM
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
4369 {"sf.", XO(31,8,0,1), XO_MASK
, PWRCOM
, PPCNONE
, {RT
, RA
, RB
}},
4370 {"subc.", XO(31,8,0,1), XO_MASK
, PPCCOM
|PPCVLE
, PPCNONE
, {RT
, RB
, RA
}},
4372 {"mulhdu", XO(31,9,0,0), XO_MASK
, PPC64
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
4373 {"mulhdu.", XO(31,9,0,1), XO_MASK
, PPC64
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
4375 {"addc", XO(31,10,0,0), XO_MASK
, PPCCOM
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
4376 {"a", XO(31,10,0,0), XO_MASK
, PWRCOM
, PPCNONE
, {RT
, RA
, RB
}},
4377 {"addc.", XO(31,10,0,1), XO_MASK
, PPCCOM
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
4378 {"a.", XO(31,10,0,1), XO_MASK
, PWRCOM
, PPCNONE
, {RT
, RA
, RB
}},
4380 {"mulhwu", XO(31,11,0,0), XO_MASK
, PPC
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
4381 {"mulhwu.", XO(31,11,0,1), XO_MASK
, PPC
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
4383 {"lxsiwzx", X(31,12), XX1_MASK
, PPCVSX2
, PPCNONE
, {XT6
, RA0
, RB
}},
4385 {"isellt", X(31,15), X_MASK
, PPCISEL
, PPCNONE
, {RT
, RA0
, RB
}},
4387 {"tlbilxlpid", XTO(31,18,0), XTO_MASK
, E500MC
|PPCA2
, PPCNONE
, {0}},
4388 {"tlbilxpid", XTO(31,18,1), XTO_MASK
, E500MC
|PPCA2
, PPCNONE
, {0}},
4389 {"tlbilxva", XTO(31,18,3), XTO_MASK
, E500MC
|PPCA2
, PPCNONE
, {RA0
, RB
}},
4390 {"tlbilx", X(31,18), X_MASK
, E500MC
|PPCA2
, PPCNONE
, {T
, RA0
, RB
}},
4392 {"mfcr", XFXM(31,19,0,0), XFXFXM_MASK
, POWER4
, PPCNONE
, {RT
, FXM4
}},
4393 {"mfcr", XFXM(31,19,0,0), XRARB_MASK
, COM
|PPCVLE
, POWER4
, {RT
}},
4394 {"mfocrf", XFXM(31,19,0,1), XFXFXM_MASK
, COM
|PPCVLE
, PPCNONE
, {RT
, FXM
}},
4396 {"lwarx", X(31,20), XEH_MASK
, PPC
|PPCVLE
, PPCNONE
, {RT
, RA0
, RB
, EH
}},
4398 {"ldx", X(31,21), X_MASK
, PPC64
|PPCVLE
, PPCNONE
, {RT
, RA0
, RB
}},
4400 {"icbt", X(31,22), X_MASK
, BOOKE
|PPCE300
|PPCA2
|PPC476
|PPCVLE
, PPCNONE
, {CT
, RA0
, RB
}},
4402 {"lwzx", X(31,23), X_MASK
, PPCCOM
|PPCVLE
, PPCNONE
, {RT
, RA0
, RB
}},
4403 {"lx", X(31,23), X_MASK
, PWRCOM
, PPCNONE
, {RT
, RA
, RB
}},
4405 {"slw", XRC(31,24,0), X_MASK
, PPCCOM
|PPCVLE
, PPCNONE
, {RA
, RS
, RB
}},
4406 {"sl", XRC(31,24,0), X_MASK
, PWRCOM
, PPCNONE
, {RA
, RS
, RB
}},
4407 {"slw.", XRC(31,24,1), X_MASK
, PPCCOM
|PPCVLE
, PPCNONE
, {RA
, RS
, RB
}},
4408 {"sl.", XRC(31,24,1), X_MASK
, PWRCOM
, PPCNONE
, {RA
, RS
, RB
}},
4410 {"cntlzw", XRC(31,26,0), XRB_MASK
, PPCCOM
|PPCVLE
, PPCNONE
, {RA
, RS
}},
4411 {"cntlz", XRC(31,26,0), XRB_MASK
, PWRCOM
, PPCNONE
, {RA
, RS
}},
4412 {"cntlzw.", XRC(31,26,1), XRB_MASK
, PPCCOM
|PPCVLE
, PPCNONE
, {RA
, RS
}},
4413 {"cntlz.", XRC(31,26,1), XRB_MASK
, PWRCOM
, PPCNONE
, {RA
, RS
}},
4415 {"sld", XRC(31,27,0), X_MASK
, PPC64
, PPCNONE
, {RA
, RS
, RB
}},
4416 {"sld.", XRC(31,27,1), X_MASK
, PPC64
, PPCNONE
, {RA
, RS
, RB
}},
4418 {"and", XRC(31,28,0), X_MASK
, COM
|PPCVLE
, PPCNONE
, {RA
, RS
, RB
}},
4419 {"and.", XRC(31,28,1), X_MASK
, COM
|PPCVLE
, PPCNONE
, {RA
, RS
, RB
}},
4421 {"maskg", XRC(31,29,0), X_MASK
, M601
, PPCA2
, {RA
, RS
, RB
}},
4422 {"maskg.", XRC(31,29,1), X_MASK
, M601
, PPCA2
, {RA
, RS
, RB
}},
4424 {"ldepx", X(31,29), X_MASK
, E500MC
|PPCA2
|PPCVLE
, PPCNONE
, {RT
, RA0
, RB
}},
4426 {"waitasec", X(31,30), XRTRARB_MASK
,POWER8
, PPCNONE
, {0}},
4428 {"lwepx", X(31,31), X_MASK
, E500MC
|PPCA2
|PPCVLE
, PPCNONE
, {RT
, RA0
, RB
}},
4430 {"cmplw", XOPL(31,32,0), XCMPL_MASK
, PPCCOM
|PPCVLE
, PPCNONE
, {OBF
, RA
, RB
}},
4431 {"cmpld", XOPL(31,32,1), XCMPL_MASK
, PPC64
, PPCNONE
, {OBF
, RA
, RB
}},
4432 {"cmpl", X(31,32), XCMP_MASK
, PPC
|PPCVLE
, PPCNONE
, {BF
, L
, RA
, RB
}},
4433 {"cmpl", X(31,32), XCMPL_MASK
, PWRCOM
, PPC
, {BF
, RA
, RB
}},
4435 {"lvsr", X(31,38), X_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, RA0
, RB
}},
4436 {"lvehx", X(31,39), X_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, RA0
, RB
}},
4437 {"lhfcmx", APU(31,39,0), APU_MASK
, PPC405
, PPCNONE
, {FCRT
, RA
, RB
}},
4439 {"mviwsplt", X(31,46), X_MASK
, PPCVEC2
, PPCNONE
, {VD
, RA
, RB
}},
4441 {"iselgt", X(31,47), X_MASK
, PPCISEL
, PPCNONE
, {RT
, RA0
, RB
}},
4443 {"lvewx", X(31,71), X_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, RA0
, RB
}},
4445 {"addg6s", XO(31,74,0,0), XO_MASK
, POWER6
, PPCNONE
, {RT
, RA
, RB
}},
4447 {"lxsiwax", X(31,76), XX1_MASK
, PPCVSX2
, PPCNONE
, {XT6
, RA0
, RB
}},
4449 {"iseleq", X(31,79), X_MASK
, PPCISEL
, PPCNONE
, {RT
, RA0
, RB
}},
4451 {"isel", XISEL(31,15), XISEL_MASK
, PPCISEL
|TITAN
|PPCVLE
, PPCNONE
, {RT
, RA0
, RB
, CRB
}},
4453 {"subf", XO(31,40,0,0), XO_MASK
, PPC
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
4454 {"sub", XO(31,40,0,0), XO_MASK
, PPC
|PPCVLE
, PPCNONE
, {RT
, RB
, RA
}},
4455 {"subf.", XO(31,40,0,1), XO_MASK
, PPC
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
4456 {"sub.", XO(31,40,0,1), XO_MASK
, PPC
|PPCVLE
, PPCNONE
, {RT
, RB
, RA
}},
4458 {"mfvsrd", X(31,51), XX1RB_MASK
, PPCVSX2
, PPCNONE
, {RA
, XS6
}},
4459 {"mffprd", X(31,51), XX1RB_MASK
|1, PPCVSX2
, PPCNONE
, {RA
, FRS
}},
4460 {"mfvrd", X(31,51)|1, XX1RB_MASK
|1, PPCVSX2
, PPCNONE
, {RA
, VS
}},
4461 {"eratilx", X(31,51), X_MASK
, PPCA2
, PPCNONE
, {ERAT_T
, RA
, RB
}},
4463 {"lbarx", X(31,52), XEH_MASK
, POWER7
|PPCVLE
, PPCNONE
, {RT
, RA0
, RB
, EH
}},
4465 {"ldux", X(31,53), X_MASK
, PPC64
|PPCVLE
, PPCNONE
, {RT
, RAL
, RB
}},
4467 {"dcbst", X(31,54), XRT_MASK
, PPC
|PPCVLE
, PPCNONE
, {RA0
, RB
}},
4469 {"lwzux", X(31,55), X_MASK
, PPCCOM
|PPCVLE
, PPCNONE
, {RT
, RAL
, RB
}},
4470 {"lux", X(31,55), X_MASK
, PWRCOM
, PPCNONE
, {RT
, RA
, RB
}},
4472 {"cntlzd", XRC(31,58,0), XRB_MASK
, PPC64
|PPCVLE
, PPCNONE
, {RA
, RS
}},
4473 {"cntlzd.", XRC(31,58,1), XRB_MASK
, PPC64
|PPCVLE
, PPCNONE
, {RA
, RS
}},
4475 {"andc", XRC(31,60,0), X_MASK
, COM
|PPCVLE
, PPCNONE
, {RA
, RS
, RB
}},
4476 {"andc.", XRC(31,60,1), X_MASK
, COM
|PPCVLE
, PPCNONE
, {RA
, RS
, RB
}},
4478 {"waitrsv", X(31,62)|(1<<21), 0xffffffff, POWER7
|E500MC
|PPCA2
, PPCNONE
, {0}},
4479 {"waitimpl", X(31,62)|(2<<21), 0xffffffff, POWER7
|E500MC
|PPCA2
, PPCNONE
, {0}},
4480 {"wait", X(31,62), XWC_MASK
, POWER7
|E500MC
|PPCA2
|PPCVLE
, PPCNONE
, {WC
}},
4482 {"dcbstep", XRT(31,63,0), XRT_MASK
, E500MC
|PPCA2
|PPCVLE
, PPCNONE
, {RA0
, RB
}},
4484 {"tdlgt", XTO(31,68,TOLGT
), XTO_MASK
, PPC64
, PPCNONE
, {RA
, RB
}},
4485 {"tdllt", XTO(31,68,TOLLT
), XTO_MASK
, PPC64
, PPCNONE
, {RA
, RB
}},
4486 {"tdeq", XTO(31,68,TOEQ
), XTO_MASK
, PPC64
, PPCNONE
, {RA
, RB
}},
4487 {"tdlge", XTO(31,68,TOLGE
), XTO_MASK
, PPC64
, PPCNONE
, {RA
, RB
}},
4488 {"tdlnl", XTO(31,68,TOLNL
), XTO_MASK
, PPC64
, PPCNONE
, {RA
, RB
}},
4489 {"tdlle", XTO(31,68,TOLLE
), XTO_MASK
, PPC64
, PPCNONE
, {RA
, RB
}},
4490 {"tdlng", XTO(31,68,TOLNG
), XTO_MASK
, PPC64
, PPCNONE
, {RA
, RB
}},
4491 {"tdgt", XTO(31,68,TOGT
), XTO_MASK
, PPC64
, PPCNONE
, {RA
, RB
}},
4492 {"tdge", XTO(31,68,TOGE
), XTO_MASK
, PPC64
, PPCNONE
, {RA
, RB
}},
4493 {"tdnl", XTO(31,68,TONL
), XTO_MASK
, PPC64
, PPCNONE
, {RA
, RB
}},
4494 {"tdlt", XTO(31,68,TOLT
), XTO_MASK
, PPC64
, PPCNONE
, {RA
, RB
}},
4495 {"tdle", XTO(31,68,TOLE
), XTO_MASK
, PPC64
, PPCNONE
, {RA
, RB
}},
4496 {"tdng", XTO(31,68,TONG
), XTO_MASK
, PPC64
, PPCNONE
, {RA
, RB
}},
4497 {"tdne", XTO(31,68,TONE
), XTO_MASK
, PPC64
, PPCNONE
, {RA
, RB
}},
4498 {"tdu", XTO(31,68,TOU
), XTO_MASK
, PPC64
, PPCNONE
, {RA
, RB
}},
4499 {"td", X(31,68), X_MASK
, PPC64
|PPCVLE
, PPCNONE
, {TO
, RA
, RB
}},
4501 {"lwfcmx", APU(31,71,0), APU_MASK
, PPC405
, PPCNONE
, {FCRT
, RA
, RB
}},
4502 {"mulhd", XO(31,73,0,0), XO_MASK
, PPC64
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
4503 {"mulhd.", XO(31,73,0,1), XO_MASK
, PPC64
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
4505 {"mulhw", XO(31,75,0,0), XO_MASK
, PPC
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
4506 {"mulhw.", XO(31,75,0,1), XO_MASK
, PPC
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
4508 {"dlmzb", XRC(31,78,0), X_MASK
, PPC403
|PPC440
|TITAN
|PPCVLE
, PPCNONE
, {RA
, RS
, RB
}},
4509 {"dlmzb.", XRC(31,78,1), X_MASK
, PPC403
|PPC440
|TITAN
|PPCVLE
, PPCNONE
, {RA
, RS
, RB
}},
4511 {"mtsrd", X(31,82), XRB_MASK
|(1<<20), PPC64
, PPCNONE
, {SR
, RS
}},
4513 {"mfmsr", X(31,83), XRARB_MASK
, COM
|PPCVLE
, PPCNONE
, {RT
}},
4515 {"ldarx", X(31,84), XEH_MASK
, PPC64
|PPCVLE
, PPCNONE
, {RT
, RA0
, RB
, EH
}},
4517 {"dcbfl", XOPL(31,86,1), XRT_MASK
, POWER5
, PPC476
, {RA0
, RB
}},
4518 {"dcbf", X(31,86), XLRT_MASK
, PPC
|PPCVLE
, PPCNONE
, {RA0
, RB
, L
}},
4520 {"lbzx", X(31,87), X_MASK
, COM
|PPCVLE
, PPCNONE
, {RT
, RA0
, RB
}},
4522 {"lbepx", X(31,95), X_MASK
, E500MC
|PPCA2
|PPCVLE
, PPCNONE
, {RT
, RA0
, RB
}},
4524 {"dni", XRC(31,97,1), XRB_MASK
, E6500
, PPCNONE
, {DUI
, DCTL
}},
4526 {"lvx", X(31,103), X_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, RA0
, RB
}},
4527 {"lqfcmx", APU(31,103,0), APU_MASK
, PPC405
, PPCNONE
, {FCRT
, RA
, RB
}},
4529 {"neg", XO(31,104,0,0), XORB_MASK
, COM
|PPCVLE
, PPCNONE
, {RT
, RA
}},
4530 {"neg.", XO(31,104,0,1), XORB_MASK
, COM
|PPCVLE
, PPCNONE
, {RT
, RA
}},
4532 {"mul", XO(31,107,0,0), XO_MASK
, M601
, PPCNONE
, {RT
, RA
, RB
}},
4533 {"mul.", XO(31,107,0,1), XO_MASK
, M601
, PPCNONE
, {RT
, RA
, RB
}},
4535 {"mvidsplt", X(31,110), X_MASK
, PPCVEC2
, PPCNONE
, {VD
, RA
, RB
}},
4537 {"mtsrdin", X(31,114), XRA_MASK
, PPC64
, PPCNONE
, {RS
, RB
}},
4539 {"mffprwz", X(31,115), XX1RB_MASK
|1, PPCVSX2
, PPCNONE
, {RA
, FRS
}},
4540 {"mfvrwz", X(31,115)|1, XX1RB_MASK
|1, PPCVSX2
, PPCNONE
, {RA
, VS
}},
4541 {"mfvsrwz", X(31,115), XX1RB_MASK
, PPCVSX2
, PPCNONE
, {RA
, XS6
}},
4543 {"lharx", X(31,116), XEH_MASK
, POWER7
|PPCVLE
, PPCNONE
, {RT
, RA0
, RB
, EH
}},
4545 {"clf", X(31,118), XTO_MASK
, POWER
, PPCNONE
, {RA
, RB
}},
4547 {"lbzux", X(31,119), X_MASK
, COM
|PPCVLE
, PPCNONE
, {RT
, RAL
, RB
}},
4549 {"popcntb", X(31,122), XRB_MASK
, POWER5
|PPCVLE
, PPCNONE
, {RA
, RS
}},
4551 {"not", XRC(31,124,0), X_MASK
, COM
, PPCNONE
, {RA
, RS
, RBS
}},
4552 {"nor", XRC(31,124,0), X_MASK
, COM
|PPCVLE
, PPCNONE
, {RA
, RS
, RB
}},
4553 {"not.", XRC(31,124,1), X_MASK
, COM
, PPCNONE
, {RA
, RS
, RBS
}},
4554 {"nor.", XRC(31,124,1), X_MASK
, COM
|PPCVLE
, PPCNONE
, {RA
, RS
, RB
}},
4556 {"dcbfep", XRT(31,127,0), XRT_MASK
, E500MC
|PPCA2
|PPCVLE
, PPCNONE
, {RA0
, RB
}},
4558 {"wrtee", X(31,131), XRARB_MASK
, PPC403
|BOOKE
|PPCA2
|PPC476
|PPCVLE
, PPCNONE
, {RS
}},
4560 {"dcbtstls", X(31,134), X_MASK
, PPCCHLK
|PPC476
|TITAN
|PPCVLE
, PPCNONE
, {CT
, RA0
, RB
}},
4562 {"stvebx", X(31,135), X_MASK
, PPCVEC
, PPCNONE
, {VS
, RA0
, RB
}},
4563 {"stbfcmx", APU(31,135,0), APU_MASK
, PPC405
, PPCNONE
, {FCRT
, RA
, RB
}},
4565 {"subfe", XO(31,136,0,0), XO_MASK
, PPCCOM
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
4566 {"sfe", XO(31,136,0,0), XO_MASK
, PWRCOM
, PPCNONE
, {RT
, RA
, RB
}},
4567 {"subfe.", XO(31,136,0,1), XO_MASK
, PPCCOM
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
4568 {"sfe.", XO(31,136,0,1), XO_MASK
, PWRCOM
, PPCNONE
, {RT
, RA
, RB
}},
4570 {"adde", XO(31,138,0,0), XO_MASK
, PPCCOM
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
4571 {"ae", XO(31,138,0,0), XO_MASK
, PWRCOM
, PPCNONE
, {RT
, RA
, RB
}},
4572 {"adde.", XO(31,138,0,1), XO_MASK
, PPCCOM
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
4573 {"ae.", XO(31,138,0,1), XO_MASK
, PWRCOM
, PPCNONE
, {RT
, RA
, RB
}},
4575 {"stxsiwx", X(31,140), XX1_MASK
, PPCVSX2
, PPCNONE
, {XS6
, RA0
, RB
}},
4577 {"msgsndp", XRTRA(31,142,0,0), XRTRA_MASK
, POWER8
, PPCNONE
, {RB
}},
4578 {"dcbtstlse", X(31,142), X_MASK
, PPCCHLK
, E500MC
, {CT
, RA0
, RB
}},
4580 {"mtcr", XFXM(31,144,0xff,0), XRARB_MASK
, COM
, PPCNONE
, {RS
}},
4581 {"mtcrf", XFXM(31,144,0,0), XFXFXM_MASK
, COM
|PPCVLE
, PPCNONE
, {FXM
, RS
}},
4582 {"mtocrf", XFXM(31,144,0,1), XFXFXM_MASK
, COM
|PPCVLE
, PPCNONE
, {FXM
, RS
}},
4584 {"mtmsr", X(31,146), XRLARB_MASK
, COM
|PPCVLE
, PPCNONE
, {RS
, A_L
}},
4586 {"mtsle", X(31,147), XRTLRARB_MASK
, POWER8
, PPCNONE
, {L
}},
4588 {"eratsx", XRC(31,147,0), X_MASK
, PPCA2
, PPCNONE
, {RT
, RA0
, RB
}},
4589 {"eratsx.", XRC(31,147,1), X_MASK
, PPCA2
, PPCNONE
, {RT
, RA0
, RB
}},
4591 {"stdx", X(31,149), X_MASK
, PPC64
|PPCVLE
, PPCNONE
, {RS
, RA0
, RB
}},
4593 {"stwcx.", XRC(31,150,1), X_MASK
, PPC
|PPCVLE
, PPCNONE
, {RS
, RA0
, RB
}},
4595 {"stwx", X(31,151), X_MASK
, PPCCOM
|PPCVLE
, PPCNONE
, {RS
, RA0
, RB
}},
4596 {"stx", X(31,151), X_MASK
, PWRCOM
, PPCNONE
, {RS
, RA
, RB
}},
4598 {"slq", XRC(31,152,0), X_MASK
, M601
, PPCNONE
, {RA
, RS
, RB
}},
4599 {"slq.", XRC(31,152,1), X_MASK
, M601
, PPCNONE
, {RA
, RS
, RB
}},
4601 {"sle", XRC(31,153,0), X_MASK
, M601
, PPCNONE
, {RA
, RS
, RB
}},
4602 {"sle.", XRC(31,153,1), X_MASK
, M601
, PPCNONE
, {RA
, RS
, RB
}},
4604 {"prtyw", X(31,154), XRB_MASK
, POWER6
|PPCA2
|PPC476
, PPCNONE
, {RA
, RS
}},
4606 {"stdepx", X(31,157), X_MASK
, E500MC
|PPCA2
|PPCVLE
, PPCNONE
, {RS
, RA0
, RB
}},
4608 {"stwepx", X(31,159), X_MASK
, E500MC
|PPCA2
|PPCVLE
, PPCNONE
, {RS
, RA0
, RB
}},
4610 {"wrteei", X(31,163), XE_MASK
, PPC403
|BOOKE
|PPCA2
|PPC476
|PPCVLE
, PPCNONE
, {E
}},
4612 {"dcbtls", X(31,166), X_MASK
, PPCCHLK
|PPC476
|TITAN
|PPCVLE
, PPCNONE
, {CT
, RA0
, RB
}},
4614 {"stvehx", X(31,167), X_MASK
, PPCVEC
, PPCNONE
, {VS
, RA0
, RB
}},
4615 {"sthfcmx", APU(31,167,0), APU_MASK
, PPC405
, PPCNONE
, {FCRT
, RA
, RB
}},
4617 {"msgclrp", XRTRA(31,174,0,0), XRTRA_MASK
, POWER8
, PPCNONE
, {RB
}},
4618 {"dcbtlse", X(31,174), X_MASK
, PPCCHLK
, E500MC
, {CT
, RA0
, RB
}},
4620 {"mtmsrd", X(31,178), XRLARB_MASK
, PPC64
, PPCNONE
, {RS
, A_L
}},
4622 {"mtvsrd", X(31,179), XX1RB_MASK
, PPCVSX2
, PPCNONE
, {XT6
, RA
}},
4623 {"mtfprd", X(31,179), XX1RB_MASK
|1, PPCVSX2
, PPCNONE
, {FRT
, RA
}},
4624 {"mtvrd", X(31,179)|1, XX1RB_MASK
|1, PPCVSX2
, PPCNONE
, {VD
, RA
}},
4625 {"eratre", X(31,179), X_MASK
, PPCA2
, PPCNONE
, {RT
, RA
, WS
}},
4627 {"stdux", X(31,181), X_MASK
, PPC64
|PPCVLE
, PPCNONE
, {RS
, RAS
, RB
}},
4629 {"stqcx.", XRC(31,182,1), X_MASK
, POWER8
, PPCNONE
, {RSQ
, RA0
, RB
}},
4630 {"wchkall", X(31,182), X_MASK
, PPCA2
, PPCNONE
, {OBF
}},
4632 {"stwux", X(31,183), X_MASK
, PPCCOM
|PPCVLE
, PPCNONE
, {RS
, RAS
, RB
}},
4633 {"stux", X(31,183), X_MASK
, PWRCOM
, PPCNONE
, {RS
, RA0
, RB
}},
4635 {"sliq", XRC(31,184,0), X_MASK
, M601
, PPCNONE
, {RA
, RS
, SH
}},
4636 {"sliq.", XRC(31,184,1), X_MASK
, M601
, PPCNONE
, {RA
, RS
, SH
}},
4638 {"prtyd", X(31,186), XRB_MASK
, POWER6
|PPCA2
, PPCNONE
, {RA
, RS
}},
4640 {"icblq.", XRC(31,198,1), X_MASK
, E6500
, PPCNONE
, {CT
, RA0
, RB
}},
4642 {"stvewx", X(31,199), X_MASK
, PPCVEC
, PPCNONE
, {VS
, RA0
, RB
}},
4643 {"stwfcmx", APU(31,199,0), APU_MASK
, PPC405
, PPCNONE
, {FCRT
, RA
, RB
}},
4645 {"subfze", XO(31,200,0,0), XORB_MASK
, PPCCOM
|PPCVLE
, PPCNONE
, {RT
, RA
}},
4646 {"sfze", XO(31,200,0,0), XORB_MASK
, PWRCOM
, PPCNONE
, {RT
, RA
}},
4647 {"subfze.", XO(31,200,0,1), XORB_MASK
, PPCCOM
|PPCVLE
, PPCNONE
, {RT
, RA
}},
4648 {"sfze.", XO(31,200,0,1), XORB_MASK
, PWRCOM
, PPCNONE
, {RT
, RA
}},
4650 {"addze", XO(31,202,0,0), XORB_MASK
, PPCCOM
|PPCVLE
, PPCNONE
, {RT
, RA
}},
4651 {"aze", XO(31,202,0,0), XORB_MASK
, PWRCOM
, PPCNONE
, {RT
, RA
}},
4652 {"addze.", XO(31,202,0,1), XORB_MASK
, PPCCOM
|PPCVLE
, PPCNONE
, {RT
, RA
}},
4653 {"aze.", XO(31,202,0,1), XORB_MASK
, PWRCOM
, PPCNONE
, {RT
, RA
}},
4655 {"msgsnd", XRTRA(31,206,0,0), XRTRA_MASK
, E500MC
|PPCA2
|PPCVLE
, PPCNONE
, {RB
}},
4657 {"mtsr", X(31,210), XRB_MASK
|(1<<20), COM
, NON32
, {SR
, RS
}},
4659 {"mtfprwa", X(31,211), XX1RB_MASK
|1, PPCVSX2
, PPCNONE
, {FRT
, RA
}},
4660 {"mtvrwa", X(31,211)|1, XX1RB_MASK
|1, PPCVSX2
, PPCNONE
, {VD
, RA
}},
4661 {"mtvsrwa", X(31,211), XX1RB_MASK
, PPCVSX2
, PPCNONE
, {XT6
, RA
}},
4662 {"eratwe", X(31,211), X_MASK
, PPCA2
, PPCNONE
, {RS
, RA
, WS
}},
4664 {"ldawx.", XRC(31,212,1), X_MASK
, PPCA2
, PPCNONE
, {RT
, RA0
, RB
}},
4666 {"stdcx.", XRC(31,214,1), X_MASK
, PPC64
|PPCVLE
, PPCNONE
, {RS
, RA0
, RB
}},
4668 {"stbx", X(31,215), X_MASK
, COM
|PPCVLE
, PPCNONE
, {RS
, RA0
, RB
}},
4670 {"sllq", XRC(31,216,0), X_MASK
, M601
, PPCNONE
, {RA
, RS
, RB
}},
4671 {"sllq.", XRC(31,216,1), X_MASK
, M601
, PPCNONE
, {RA
, RS
, RB
}},
4673 {"sleq", XRC(31,217,0), X_MASK
, M601
, PPCNONE
, {RA
, RS
, RB
}},
4674 {"sleq.", XRC(31,217,1), X_MASK
, M601
, PPCNONE
, {RA
, RS
, RB
}},
4676 {"stbepx", X(31,223), X_MASK
, E500MC
|PPCA2
|PPCVLE
, PPCNONE
, {RS
, RA0
, RB
}},
4678 {"icblc", X(31,230), X_MASK
, PPCCHLK
|PPC476
|TITAN
|PPCVLE
, PPCNONE
, {CT
, RA0
, RB
}},
4680 {"stvx", X(31,231), X_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VS
, RA0
, RB
}},
4681 {"stqfcmx", APU(31,231,0), APU_MASK
, PPC405
, PPCNONE
, {FCRT
, RA
, RB
}},
4683 {"subfme", XO(31,232,0,0), XORB_MASK
, PPCCOM
|PPCVLE
, PPCNONE
, {RT
, RA
}},
4684 {"sfme", XO(31,232,0,0), XORB_MASK
, PWRCOM
, PPCNONE
, {RT
, RA
}},
4685 {"subfme.", XO(31,232,0,1), XORB_MASK
, PPCCOM
|PPCVLE
, PPCNONE
, {RT
, RA
}},
4686 {"sfme.", XO(31,232,0,1), XORB_MASK
, PWRCOM
, PPCNONE
, {RT
, RA
}},
4688 {"mulld", XO(31,233,0,0), XO_MASK
, PPC64
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
4689 {"mulld.", XO(31,233,0,1), XO_MASK
, PPC64
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
4691 {"addme", XO(31,234,0,0), XORB_MASK
, PPCCOM
|PPCVLE
, PPCNONE
, {RT
, RA
}},
4692 {"ame", XO(31,234,0,0), XORB_MASK
, PWRCOM
, PPCNONE
, {RT
, RA
}},
4693 {"addme.", XO(31,234,0,1), XORB_MASK
, PPCCOM
|PPCVLE
, PPCNONE
, {RT
, RA
}},
4694 {"ame.", XO(31,234,0,1), XORB_MASK
, PWRCOM
, PPCNONE
, {RT
, RA
}},
4696 {"mullw", XO(31,235,0,0), XO_MASK
, PPCCOM
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
4697 {"muls", XO(31,235,0,0), XO_MASK
, PWRCOM
, PPCNONE
, {RT
, RA
, RB
}},
4698 {"mullw.", XO(31,235,0,1), XO_MASK
, PPCCOM
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
4699 {"muls.", XO(31,235,0,1), XO_MASK
, PWRCOM
, PPCNONE
, {RT
, RA
, RB
}},
4701 {"icblce", X(31,238), X_MASK
, PPCCHLK
, E500MC
|PPCA2
, {CT
, RA
, RB
}},
4702 {"msgclr", XRTRA(31,238,0,0),XRTRA_MASK
, E500MC
|PPCA2
|PPCVLE
, PPCNONE
, {RB
}},
4703 {"mtsrin", X(31,242), XRA_MASK
, PPC
, NON32
, {RS
, RB
}},
4704 {"mtsri", X(31,242), XRA_MASK
, POWER
, NON32
, {RS
, RB
}},
4706 {"mtfprwz", X(31,243), XX1RB_MASK
|1, PPCVSX2
, PPCNONE
, {FRT
, RA
}},
4707 {"mtvrwz", X(31,243)|1, XX1RB_MASK
|1, PPCVSX2
, PPCNONE
, {VD
, RA
}},
4708 {"mtvsrwz", X(31,243), XX1RB_MASK
, PPCVSX2
, PPCNONE
, {XT6
, RA
}},
4710 {"dcbtstt", XRT(31,246,0x10), XRT_MASK
, POWER7
, PPCNONE
, {RA0
, RB
}},
4711 {"dcbtst", X(31,246), X_MASK
, POWER4
, PPCNONE
, {RA0
, RB
, CT
}},
4712 {"dcbtst", X(31,246), X_MASK
, PPC
|PPCVLE
, POWER4
, {CT
, RA0
, RB
}},
4714 {"stbux", X(31,247), X_MASK
, COM
|PPCVLE
, PPCNONE
, {RS
, RAS
, RB
}},
4716 {"slliq", XRC(31,248,0), X_MASK
, M601
, PPCNONE
, {RA
, RS
, SH
}},
4717 {"slliq.", XRC(31,248,1), X_MASK
, M601
, PPCNONE
, {RA
, RS
, SH
}},
4719 {"bpermd", X(31,252), X_MASK
, POWER7
|PPCA2
, PPCNONE
, {RA
, RS
, RB
}},
4721 {"dcbtstep", XRT(31,255,0), X_MASK
, E500MC
|PPCA2
|PPCVLE
, PPCNONE
, {RT
, RA0
, RB
}},
4723 {"mfdcrx", X(31,259), X_MASK
, BOOKE
|PPCA2
|PPC476
|PPCVLE
, TITAN
, {RS
, RA
}},
4724 {"mfdcrx.", XRC(31,259,1), X_MASK
, PPCA2
, PPCNONE
, {RS
, RA
}},
4726 {"lvexbx", X(31,261), X_MASK
, PPCVEC2
, PPCNONE
, {VD
, RA0
, RB
}},
4728 {"icbt", X(31,262), XRT_MASK
, PPC403
, PPCNONE
, {RA
, RB
}},
4730 {"lvepxl", X(31,263), X_MASK
, PPCVEC2
|PPCVLE
, PPCNONE
, {VD
, RA0
, RB
}},
4732 {"ldfcmx", APU(31,263,0), APU_MASK
, PPC405
, PPCNONE
, {FCRT
, RA
, RB
}},
4733 {"doz", XO(31,264,0,0), XO_MASK
, M601
, PPCNONE
, {RT
, RA
, RB
}},
4734 {"doz.", XO(31,264,0,1), XO_MASK
, M601
, PPCNONE
, {RT
, RA
, RB
}},
4736 {"add", XO(31,266,0,0), XO_MASK
, PPCCOM
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
4737 {"cax", XO(31,266,0,0), XO_MASK
, PWRCOM
, PPCNONE
, {RT
, RA
, RB
}},
4738 {"add.", XO(31,266,0,1), XO_MASK
, PPCCOM
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
4739 {"cax.", XO(31,266,0,1), XO_MASK
, PWRCOM
, PPCNONE
, {RT
, RA
, RB
}},
4741 {"ehpriv", X(31,270), 0xffffffff, E500MC
|PPCA2
|PPCVLE
, PPCNONE
, {0}},
4743 {"tlbiel", X(31,274), XRTLRA_MASK
, POWER4
, PPC476
, {RB
, L
}},
4745 {"mfapidi", X(31,275), X_MASK
, BOOKE
, TITAN
, {RT
, RA
}},
4747 {"lqarx", X(31,276), XEH_MASK
, POWER8
, PPCNONE
, {RTQ
, RAX
, RBX
, EH
}},
4749 {"lscbx", XRC(31,277,0), X_MASK
, M601
, PPCNONE
, {RT
, RA
, RB
}},
4750 {"lscbx.", XRC(31,277,1), X_MASK
, M601
, PPCNONE
, {RT
, RA
, RB
}},
4752 {"dcbtt", XRT(31,278,0x10), XRT_MASK
, POWER7
, PPCNONE
, {RA0
, RB
}},
4753 {"dcbt", X(31,278), X_MASK
, POWER4
, PPCNONE
, {RA0
, RB
, CT
}},
4754 {"dcbt", X(31,278), X_MASK
, PPC
|PPCVLE
, POWER4
, {CT
, RA0
, RB
}},
4756 {"lhzx", X(31,279), X_MASK
, COM
|PPCVLE
, PPCNONE
, {RT
, RA0
, RB
}},
4758 {"cdtbcd", X(31,282), XRB_MASK
, POWER6
, PPCNONE
, {RA
, RS
}},
4760 {"eqv", XRC(31,284,0), X_MASK
, COM
|PPCVLE
, PPCNONE
, {RA
, RS
, RB
}},
4761 {"eqv.", XRC(31,284,1), X_MASK
, COM
|PPCVLE
, PPCNONE
, {RA
, RS
, RB
}},
4763 {"lhepx", X(31,287), X_MASK
, E500MC
|PPCA2
|PPCVLE
, PPCNONE
, {RT
, RA0
, RB
}},
4765 {"mfdcrux", X(31,291), X_MASK
, PPC464
|PPCVLE
, PPCNONE
, {RS
, RA
}},
4767 {"lvexhx", X(31,293), X_MASK
, PPCVEC2
, PPCNONE
, {VD
, RA0
, RB
}},
4768 {"lvepx", X(31,295), X_MASK
, PPCVEC2
|PPCVLE
, PPCNONE
, {VD
, RA0
, RB
}},
4770 {"mfbhrbe", X(31,302), X_MASK
, POWER8
, PPCNONE
, {RT
, BHRBE
}},
4772 {"tlbie", X(31,306), XRTLRA_MASK
, PPC
, TITAN
, {RB
, L
}},
4773 {"tlbi", X(31,306), XRT_MASK
, POWER
, PPCNONE
, {RA0
, RB
}},
4775 {"eciwx", X(31,310), X_MASK
, PPC
, TITAN
, {RT
, RA0
, RB
}},
4777 {"lhzux", X(31,311), X_MASK
, COM
|PPCVLE
, PPCNONE
, {RT
, RAL
, RB
}},
4779 {"cbcdtd", X(31,314), XRB_MASK
, POWER6
, PPCNONE
, {RA
, RS
}},
4781 {"xor", XRC(31,316,0), X_MASK
, COM
|PPCVLE
, PPCNONE
, {RA
, RS
, RB
}},
4782 {"xor.", XRC(31,316,1), X_MASK
, COM
|PPCVLE
, PPCNONE
, {RA
, RS
, RB
}},
4784 {"dcbtep", XRT(31,319,0), X_MASK
, E500MC
|PPCA2
|PPCVLE
, PPCNONE
, {RT
, RA0
, RB
}},
4786 {"mfexisr", XSPR(31,323, 64), XSPR_MASK
, PPC403
, PPCNONE
, {RT
}},
4787 {"mfexier", XSPR(31,323, 66), XSPR_MASK
, PPC403
, PPCNONE
, {RT
}},
4788 {"mfbr0", XSPR(31,323,128), XSPR_MASK
, PPC403
, PPCNONE
, {RT
}},
4789 {"mfbr1", XSPR(31,323,129), XSPR_MASK
, PPC403
, PPCNONE
, {RT
}},
4790 {"mfbr2", XSPR(31,323,130), XSPR_MASK
, PPC403
, PPCNONE
, {RT
}},
4791 {"mfbr3", XSPR(31,323,131), XSPR_MASK
, PPC403
, PPCNONE
, {RT
}},
4792 {"mfbr4", XSPR(31,323,132), XSPR_MASK
, PPC403
, PPCNONE
, {RT
}},
4793 {"mfbr5", XSPR(31,323,133), XSPR_MASK
, PPC403
, PPCNONE
, {RT
}},
4794 {"mfbr6", XSPR(31,323,134), XSPR_MASK
, PPC403
, PPCNONE
, {RT
}},
4795 {"mfbr7", XSPR(31,323,135), XSPR_MASK
, PPC403
, PPCNONE
, {RT
}},
4796 {"mfbear", XSPR(31,323,144), XSPR_MASK
, PPC403
, PPCNONE
, {RT
}},
4797 {"mfbesr", XSPR(31,323,145), XSPR_MASK
, PPC403
, PPCNONE
, {RT
}},
4798 {"mfiocr", XSPR(31,323,160), XSPR_MASK
, PPC403
, PPCNONE
, {RT
}},
4799 {"mfdmacr0", XSPR(31,323,192), XSPR_MASK
, PPC403
, PPCNONE
, {RT
}},
4800 {"mfdmact0", XSPR(31,323,193), XSPR_MASK
, PPC403
, PPCNONE
, {RT
}},
4801 {"mfdmada0", XSPR(31,323,194), XSPR_MASK
, PPC403
, PPCNONE
, {RT
}},
4802 {"mfdmasa0", XSPR(31,323,195), XSPR_MASK
, PPC403
, PPCNONE
, {RT
}},
4803 {"mfdmacc0", XSPR(31,323,196), XSPR_MASK
, PPC403
, PPCNONE
, {RT
}},
4804 {"mfdmacr1", XSPR(31,323,200), XSPR_MASK
, PPC403
, PPCNONE
, {RT
}},
4805 {"mfdmact1", XSPR(31,323,201), XSPR_MASK
, PPC403
, PPCNONE
, {RT
}},
4806 {"mfdmada1", XSPR(31,323,202), XSPR_MASK
, PPC403
, PPCNONE
, {RT
}},
4807 {"mfdmasa1", XSPR(31,323,203), XSPR_MASK
, PPC403
, PPCNONE
, {RT
}},
4808 {"mfdmacc1", XSPR(31,323,204), XSPR_MASK
, PPC403
, PPCNONE
, {RT
}},
4809 {"mfdmacr2", XSPR(31,323,208), XSPR_MASK
, PPC403
, PPCNONE
, {RT
}},
4810 {"mfdmact2", XSPR(31,323,209), XSPR_MASK
, PPC403
, PPCNONE
, {RT
}},
4811 {"mfdmada2", XSPR(31,323,210), XSPR_MASK
, PPC403
, PPCNONE
, {RT
}},
4812 {"mfdmasa2", XSPR(31,323,211), XSPR_MASK
, PPC403
, PPCNONE
, {RT
}},
4813 {"mfdmacc2", XSPR(31,323,212), XSPR_MASK
, PPC403
, PPCNONE
, {RT
}},
4814 {"mfdmacr3", XSPR(31,323,216), XSPR_MASK
, PPC403
, PPCNONE
, {RT
}},
4815 {"mfdmact3", XSPR(31,323,217), XSPR_MASK
, PPC403
, PPCNONE
, {RT
}},
4816 {"mfdmada3", XSPR(31,323,218), XSPR_MASK
, PPC403
, PPCNONE
, {RT
}},
4817 {"mfdmasa3", XSPR(31,323,219), XSPR_MASK
, PPC403
, PPCNONE
, {RT
}},
4818 {"mfdmacc3", XSPR(31,323,220), XSPR_MASK
, PPC403
, PPCNONE
, {RT
}},
4819 {"mfdmasr", XSPR(31,323,224), XSPR_MASK
, PPC403
, PPCNONE
, {RT
}},
4820 {"mfdcr", X(31,323), X_MASK
, PPC403
|BOOKE
|PPCA2
|PPC476
|PPCVLE
, TITAN
, {RT
, SPR
}},
4821 {"mfdcr.", XRC(31,323,1), X_MASK
, PPCA2
, PPCNONE
, {RT
, SPR
}},
4823 {"lvexwx", X(31,325), X_MASK
, PPCVEC2
, PPCNONE
, {VD
, RA0
, RB
}},
4825 {"dcread", X(31,326), X_MASK
, PPC476
|TITAN
, PPCNONE
, {RT
, RA0
, RB
}},
4827 {"div", XO(31,331,0,0), XO_MASK
, M601
, PPCNONE
, {RT
, RA
, RB
}},
4828 {"div.", XO(31,331,0,1), XO_MASK
, M601
, PPCNONE
, {RT
, RA
, RB
}},
4830 {"lxvdsx", X(31,332), XX1_MASK
, PPCVSX
, PPCNONE
, {XT6
, RA0
, RB
}},
4832 {"mfpmr", X(31,334), X_MASK
, PPCPMR
|PPCE300
|PPCVLE
, PPCNONE
, {RT
, PMR
}},
4833 {"mftmr", X(31,366), X_MASK
, PPCTMR
|E6500
, PPCNONE
, {RT
, TMR
}},
4835 {"mfmq", XSPR(31,339, 0), XSPR_MASK
, M601
, PPCNONE
, {RT
}},
4836 {"mfxer", XSPR(31,339, 1), XSPR_MASK
, COM
|PPCVLE
, PPCNONE
, {RT
}},
4837 {"mfrtcu", XSPR(31,339, 4), XSPR_MASK
, COM
, TITAN
, {RT
}},
4838 {"mfrtcl", XSPR(31,339, 5), XSPR_MASK
, COM
, TITAN
, {RT
}},
4839 {"mfdec", XSPR(31,339, 6), XSPR_MASK
, MFDEC1
, PPCNONE
, {RT
}},
4840 {"mflr", XSPR(31,339, 8), XSPR_MASK
, COM
|PPCVLE
, PPCNONE
, {RT
}},
4841 {"mfctr", XSPR(31,339, 9), XSPR_MASK
, COM
|PPCVLE
, PPCNONE
, {RT
}},
4842 {"mftid", XSPR(31,339, 17), XSPR_MASK
, POWER
, PPCNONE
, {RT
}},
4843 {"mfdsisr", XSPR(31,339, 18), XSPR_MASK
, COM
, TITAN
, {RT
}},
4844 {"mfdar", XSPR(31,339, 19), XSPR_MASK
, COM
, TITAN
, {RT
}},
4845 {"mfdec", XSPR(31,339, 22), XSPR_MASK
, MFDEC2
, MFDEC1
, {RT
}},
4846 {"mfsdr0", XSPR(31,339, 24), XSPR_MASK
, POWER
, PPCNONE
, {RT
}},
4847 {"mfsdr1", XSPR(31,339, 25), XSPR_MASK
, COM
, TITAN
, {RT
}},
4848 {"mfsrr0", XSPR(31,339, 26), XSPR_MASK
, COM
, PPCNONE
, {RT
}},
4849 {"mfsrr1", XSPR(31,339, 27), XSPR_MASK
, COM
, PPCNONE
, {RT
}},
4850 {"mfcfar", XSPR(31,339, 28), XSPR_MASK
, POWER6
, PPCNONE
, {RT
}},
4851 {"mfpid", XSPR(31,339, 48), XSPR_MASK
, BOOKE
|PPCVLE
, PPCNONE
, {RT
}},
4852 {"mfcsrr0", XSPR(31,339, 58), XSPR_MASK
, BOOKE
|PPCVLE
, PPCNONE
, {RT
}},
4853 {"mfcsrr1", XSPR(31,339, 59), XSPR_MASK
, BOOKE
|PPCVLE
, PPCNONE
, {RT
}},
4854 {"mfdear", XSPR(31,339, 61), XSPR_MASK
, BOOKE
|PPCVLE
, PPCNONE
, {RT
}},
4855 {"mfesr", XSPR(31,339, 62), XSPR_MASK
, BOOKE
|PPCVLE
, PPCNONE
, {RT
}},
4856 {"mfivpr", XSPR(31,339, 63), XSPR_MASK
, BOOKE
|PPCVLE
, PPCNONE
, {RT
}},
4857 {"mfcmpa", XSPR(31,339,144), XSPR_MASK
, PPC860
, PPCNONE
, {RT
}},
4858 {"mfcmpb", XSPR(31,339,145), XSPR_MASK
, PPC860
, PPCNONE
, {RT
}},
4859 {"mfcmpc", XSPR(31,339,146), XSPR_MASK
, PPC860
, PPCNONE
, {RT
}},
4860 {"mfcmpd", XSPR(31,339,147), XSPR_MASK
, PPC860
, PPCNONE
, {RT
}},
4861 {"mficr", XSPR(31,339,148), XSPR_MASK
, PPC860
, PPCNONE
, {RT
}},
4862 {"mfder", XSPR(31,339,149), XSPR_MASK
, PPC860
, PPCNONE
, {RT
}},
4863 {"mfcounta", XSPR(31,339,150), XSPR_MASK
, PPC860
, PPCNONE
, {RT
}},
4864 {"mfcountb", XSPR(31,339,151), XSPR_MASK
, PPC860
, PPCNONE
, {RT
}},
4865 {"mfcmpe", XSPR(31,339,152), XSPR_MASK
, PPC860
, PPCNONE
, {RT
}},
4866 {"mfcmpf", XSPR(31,339,153), XSPR_MASK
, PPC860
, PPCNONE
, {RT
}},
4867 {"mfcmpg", XSPR(31,339,154), XSPR_MASK
, PPC860
, PPCNONE
, {RT
}},
4868 {"mfcmph", XSPR(31,339,155), XSPR_MASK
, PPC860
, PPCNONE
, {RT
}},
4869 {"mflctrl1", XSPR(31,339,156), XSPR_MASK
, PPC860
, PPCNONE
, {RT
}},
4870 {"mflctrl2", XSPR(31,339,157), XSPR_MASK
, PPC860
, PPCNONE
, {RT
}},
4871 {"mfictrl", XSPR(31,339,158), XSPR_MASK
, PPC860
, PPCNONE
, {RT
}},
4872 {"mfbar", XSPR(31,339,159), XSPR_MASK
, PPC860
, PPCNONE
, {RT
}},
4873 {"mfvrsave", XSPR(31,339,256), XSPR_MASK
, PPCVEC
, PPCNONE
, {RT
}},
4874 {"mfusprg0", XSPR(31,339,256), XSPR_MASK
, BOOKE
|PPCVLE
, PPCNONE
, {RT
}},
4875 {"mfsprg", XSPR(31,339,256), XSPRG_MASK
, PPC
|PPCVLE
, PPCNONE
, {RT
, SPRG
}},
4876 {"mfsprg4", XSPR(31,339,260), XSPR_MASK
, PPC405
|BOOKE
|PPCVLE
, PPCNONE
, {RT
}},
4877 {"mfsprg5", XSPR(31,339,261), XSPR_MASK
, PPC405
|BOOKE
|PPCVLE
, PPCNONE
, {RT
}},
4878 {"mfsprg6", XSPR(31,339,262), XSPR_MASK
, PPC405
|BOOKE
|PPCVLE
, PPCNONE
, {RT
}},
4879 {"mfsprg7", XSPR(31,339,263), XSPR_MASK
, PPC405
|BOOKE
|PPCVLE
, PPCNONE
, {RT
}},
4880 {"mftb", XSPR(31,339,268), XSPR_MASK
, BOOKE
|PPCVLE
, PPCNONE
, {RT
}},
4881 {"mftbl", XSPR(31,339,268), XSPR_MASK
, BOOKE
|PPCVLE
, PPCNONE
, {RT
}},
4882 {"mftbu", XSPR(31,339,269), XSPR_MASK
, BOOKE
|PPCVLE
, PPCNONE
, {RT
}},
4883 {"mfsprg0", XSPR(31,339,272), XSPR_MASK
, PPC
|PPCVLE
, PPCNONE
, {RT
}},
4884 {"mfsprg1", XSPR(31,339,273), XSPR_MASK
, PPC
|PPCVLE
, PPCNONE
, {RT
}},
4885 {"mfsprg2", XSPR(31,339,274), XSPR_MASK
, PPC
|PPCVLE
, PPCNONE
, {RT
}},
4886 {"mfsprg3", XSPR(31,339,275), XSPR_MASK
, PPC
|PPCVLE
, PPCNONE
, {RT
}},
4887 {"mfasr", XSPR(31,339,280), XSPR_MASK
, PPC64
, PPCNONE
, {RT
}},
4888 {"mfear", XSPR(31,339,282), XSPR_MASK
, PPC
, TITAN
, {RT
}},
4889 {"mfpir", XSPR(31,339,286), XSPR_MASK
, BOOKE
|PPCVLE
, PPCNONE
, {RT
}},
4890 {"mfpvr", XSPR(31,339,287), XSPR_MASK
, PPC
|PPCVLE
, PPCNONE
, {RT
}},
4891 {"mfdbsr", XSPR(31,339,304), XSPR_MASK
, BOOKE
|PPCVLE
, PPCNONE
, {RT
}},
4892 {"mfdbcr0", XSPR(31,339,308), XSPR_MASK
, BOOKE
|PPCVLE
, PPCNONE
, {RT
}},
4893 {"mfdbcr1", XSPR(31,339,309), XSPR_MASK
, BOOKE
|PPCVLE
, PPCNONE
, {RT
}},
4894 {"mfdbcr2", XSPR(31,339,310), XSPR_MASK
, BOOKE
|PPCVLE
, PPCNONE
, {RT
}},
4895 {"mfiac1", XSPR(31,339,312), XSPR_MASK
, BOOKE
|PPCVLE
, PPCNONE
, {RT
}},
4896 {"mfiac2", XSPR(31,339,313), XSPR_MASK
, BOOKE
|PPCVLE
, PPCNONE
, {RT
}},
4897 {"mfiac3", XSPR(31,339,314), XSPR_MASK
, BOOKE
|PPCVLE
, PPCNONE
, {RT
}},
4898 {"mfiac4", XSPR(31,339,315), XSPR_MASK
, BOOKE
|PPCVLE
, PPCNONE
, {RT
}},
4899 {"mfdac1", XSPR(31,339,316), XSPR_MASK
, BOOKE
|PPCVLE
, PPCNONE
, {RT
}},
4900 {"mfdac2", XSPR(31,339,317), XSPR_MASK
, BOOKE
|PPCVLE
, PPCNONE
, {RT
}},
4901 {"mfdvc1", XSPR(31,339,318), XSPR_MASK
, BOOKE
|PPCVLE
, PPCNONE
, {RT
}},
4902 {"mfdvc2", XSPR(31,339,319), XSPR_MASK
, BOOKE
|PPCVLE
, PPCNONE
, {RT
}},
4903 {"mftsr", XSPR(31,339,336), XSPR_MASK
, BOOKE
|PPCVLE
, PPCNONE
, {RT
}},
4904 {"mftcr", XSPR(31,339,340), XSPR_MASK
, BOOKE
|PPCVLE
, PPCNONE
, {RT
}},
4905 {"mfivor0", XSPR(31,339,400), XSPR_MASK
, BOOKE
|PPCVLE
, PPCNONE
, {RT
}},
4906 {"mfivor1", XSPR(31,339,401), XSPR_MASK
, BOOKE
|PPCVLE
, PPCNONE
, {RT
}},
4907 {"mfivor2", XSPR(31,339,402), XSPR_MASK
, BOOKE
|PPCVLE
, PPCNONE
, {RT
}},
4908 {"mfivor3", XSPR(31,339,403), XSPR_MASK
, BOOKE
|PPCVLE
, PPCNONE
, {RT
}},
4909 {"mfivor4", XSPR(31,339,404), XSPR_MASK
, BOOKE
|PPCVLE
, PPCNONE
, {RT
}},
4910 {"mfivor5", XSPR(31,339,405), XSPR_MASK
, BOOKE
|PPCVLE
, PPCNONE
, {RT
}},
4911 {"mfivor6", XSPR(31,339,406), XSPR_MASK
, BOOKE
|PPCVLE
, PPCNONE
, {RT
}},
4912 {"mfivor7", XSPR(31,339,407), XSPR_MASK
, BOOKE
|PPCVLE
, PPCNONE
, {RT
}},
4913 {"mfivor8", XSPR(31,339,408), XSPR_MASK
, BOOKE
|PPCVLE
, PPCNONE
, {RT
}},
4914 {"mfivor9", XSPR(31,339,409), XSPR_MASK
, BOOKE
|PPCVLE
, PPCNONE
, {RT
}},
4915 {"mfivor10", XSPR(31,339,410), XSPR_MASK
, BOOKE
|PPCVLE
, PPCNONE
, {RT
}},
4916 {"mfivor11", XSPR(31,339,411), XSPR_MASK
, BOOKE
|PPCVLE
, PPCNONE
, {RT
}},
4917 {"mfivor12", XSPR(31,339,412), XSPR_MASK
, BOOKE
|PPCVLE
, PPCNONE
, {RT
}},
4918 {"mfivor13", XSPR(31,339,413), XSPR_MASK
, BOOKE
|PPCVLE
, PPCNONE
, {RT
}},
4919 {"mfivor14", XSPR(31,339,414), XSPR_MASK
, BOOKE
|PPCVLE
, PPCNONE
, {RT
}},
4920 {"mfivor15", XSPR(31,339,415), XSPR_MASK
, BOOKE
|PPCVLE
, PPCNONE
, {RT
}},
4921 {"mfspefscr", XSPR(31,339,512), XSPR_MASK
, PPCSPE
, PPCNONE
, {RT
}},
4922 {"mfbbear", XSPR(31,339,513), XSPR_MASK
, PPCBRLK
, PPCNONE
, {RT
}},
4923 {"mfbbtar", XSPR(31,339,514), XSPR_MASK
, PPCBRLK
, PPCNONE
, {RT
}},
4924 {"mfivor32", XSPR(31,339,528), XSPR_MASK
, PPCSPE
, PPCNONE
, {RT
}},
4925 {"mfibatu", XSPR(31,339,528), XSPRBAT_MASK
, PPC
, TITAN
, {RT
, SPRBAT
}},
4926 {"mfivor33", XSPR(31,339,529), XSPR_MASK
, PPCSPE
, PPCNONE
, {RT
}},
4927 {"mfibatl", XSPR(31,339,529), XSPRBAT_MASK
, PPC
, TITAN
, {RT
, SPRBAT
}},
4928 {"mfivor34", XSPR(31,339,530), XSPR_MASK
, PPCSPE
, PPCNONE
, {RT
}},
4929 {"mfivor35", XSPR(31,339,531), XSPR_MASK
, PPCPMR
, PPCNONE
, {RT
}},
4930 {"mfdbatu", XSPR(31,339,536), XSPRBAT_MASK
, PPC
, TITAN
, {RT
, SPRBAT
}},
4931 {"mfdbatl", XSPR(31,339,537), XSPRBAT_MASK
, PPC
, TITAN
, {RT
, SPRBAT
}},
4932 {"mfic_cst", XSPR(31,339,560), XSPR_MASK
, PPC860
, PPCNONE
, {RT
}},
4933 {"mfic_adr", XSPR(31,339,561), XSPR_MASK
, PPC860
, PPCNONE
, {RT
}},
4934 {"mfic_dat", XSPR(31,339,562), XSPR_MASK
, PPC860
, PPCNONE
, {RT
}},
4935 {"mfdc_cst", XSPR(31,339,568), XSPR_MASK
, PPC860
, PPCNONE
, {RT
}},
4936 {"mfdc_adr", XSPR(31,339,569), XSPR_MASK
, PPC860
, PPCNONE
, {RT
}},
4937 {"mfdc_dat", XSPR(31,339,570), XSPR_MASK
, PPC860
, PPCNONE
, {RT
}},
4938 {"mfmcsrr0", XSPR(31,339,570), XSPR_MASK
, PPCRFMCI
, PPCNONE
, {RT
}},
4939 {"mfmcsrr1", XSPR(31,339,571), XSPR_MASK
, PPCRFMCI
, PPCNONE
, {RT
}},
4940 {"mfmcsr", XSPR(31,339,572), XSPR_MASK
, PPCRFMCI
, PPCNONE
, {RT
}},
4941 {"mfmcar", XSPR(31,339,573), XSPR_MASK
, PPCRFMCI
, TITAN
, {RT
}},
4942 {"mfdpdr", XSPR(31,339,630), XSPR_MASK
, PPC860
, PPCNONE
, {RT
}},
4943 {"mfdpir", XSPR(31,339,631), XSPR_MASK
, PPC860
, PPCNONE
, {RT
}},
4944 {"mfimmr", XSPR(31,339,638), XSPR_MASK
, PPC860
, PPCNONE
, {RT
}},
4945 {"mfmi_ctr", XSPR(31,339,784), XSPR_MASK
, PPC860
, PPCNONE
, {RT
}},
4946 {"mfmi_ap", XSPR(31,339,786), XSPR_MASK
, PPC860
, PPCNONE
, {RT
}},
4947 {"mfmi_epn", XSPR(31,339,787), XSPR_MASK
, PPC860
, PPCNONE
, {RT
}},
4948 {"mfmi_twc", XSPR(31,339,789), XSPR_MASK
, PPC860
, PPCNONE
, {RT
}},
4949 {"mfmi_rpn", XSPR(31,339,790), XSPR_MASK
, PPC860
, PPCNONE
, {RT
}},
4950 {"mfmd_ctr", XSPR(31,339,792), XSPR_MASK
, PPC860
, PPCNONE
, {RT
}},
4951 {"mfm_casid", XSPR(31,339,793), XSPR_MASK
, PPC860
, PPCNONE
, {RT
}},
4952 {"mfmd_ap", XSPR(31,339,794), XSPR_MASK
, PPC860
, PPCNONE
, {RT
}},
4953 {"mfmd_epn", XSPR(31,339,795), XSPR_MASK
, PPC860
, PPCNONE
, {RT
}},
4954 {"mfmd_twb", XSPR(31,339,796), XSPR_MASK
, PPC860
, PPCNONE
, {RT
}},
4955 {"mfmd_twc", XSPR(31,339,797), XSPR_MASK
, PPC860
, PPCNONE
, {RT
}},
4956 {"mfmd_rpn", XSPR(31,339,798), XSPR_MASK
, PPC860
, PPCNONE
, {RT
}},
4957 {"mfm_tw", XSPR(31,339,799), XSPR_MASK
, PPC860
, PPCNONE
, {RT
}},
4958 {"mfmi_dbcam", XSPR(31,339,816), XSPR_MASK
, PPC860
, PPCNONE
, {RT
}},
4959 {"mfmi_dbram0", XSPR(31,339,817), XSPR_MASK
, PPC860
, PPCNONE
, {RT
}},
4960 {"mfmi_dbram1", XSPR(31,339,818), XSPR_MASK
, PPC860
, PPCNONE
, {RT
}},
4961 {"mfmd_dbcam", XSPR(31,339,824), XSPR_MASK
, PPC860
, PPCNONE
, {RT
}},
4962 {"mfmd_dbram0", XSPR(31,339,825), XSPR_MASK
, PPC860
, PPCNONE
, {RT
}},
4963 {"mfmd_dbram1", XSPR(31,339,826), XSPR_MASK
, PPC860
, PPCNONE
, {RT
}},
4964 {"mfivndx", XSPR(31,339,880), XSPR_MASK
, TITAN
, PPCNONE
, {RT
}},
4965 {"mfdvndx", XSPR(31,339,881), XSPR_MASK
, TITAN
, PPCNONE
, {RT
}},
4966 {"mfivlim", XSPR(31,339,882), XSPR_MASK
, TITAN
, PPCNONE
, {RT
}},
4967 {"mfdvlim", XSPR(31,339,883), XSPR_MASK
, TITAN
, PPCNONE
, {RT
}},
4968 {"mfclcsr", XSPR(31,339,884), XSPR_MASK
, TITAN
, PPCNONE
, {RT
}},
4969 {"mfccr1", XSPR(31,339,888), XSPR_MASK
, TITAN
, PPCNONE
, {RT
}},
4970 {"mfppr", XSPR(31,339,896), XSPR_MASK
, POWER7
, PPCNONE
, {RT
}},
4971 {"mfppr32", XSPR(31,339,898), XSPR_MASK
, POWER7
, PPCNONE
, {RT
}},
4972 {"mfrstcfg", XSPR(31,339,923), XSPR_MASK
, TITAN
, PPCNONE
, {RT
}},
4973 {"mfdcdbtrl", XSPR(31,339,924), XSPR_MASK
, TITAN
, PPCNONE
, {RT
}},
4974 {"mfdcdbtrh", XSPR(31,339,925), XSPR_MASK
, TITAN
, PPCNONE
, {RT
}},
4975 {"mficdbtr", XSPR(31,339,927), XSPR_MASK
, TITAN
, PPCNONE
, {RT
}},
4976 {"mfummcr0", XSPR(31,339,936), XSPR_MASK
, PPC750
, PPCNONE
, {RT
}},
4977 {"mfupmc1", XSPR(31,339,937), XSPR_MASK
, PPC750
, PPCNONE
, {RT
}},
4978 {"mfupmc2", XSPR(31,339,938), XSPR_MASK
, PPC750
, PPCNONE
, {RT
}},
4979 {"mfusia", XSPR(31,339,939), XSPR_MASK
, PPC750
, PPCNONE
, {RT
}},
4980 {"mfummcr1", XSPR(31,339,940), XSPR_MASK
, PPC750
, PPCNONE
, {RT
}},
4981 {"mfupmc3", XSPR(31,339,941), XSPR_MASK
, PPC750
, PPCNONE
, {RT
}},
4982 {"mfupmc4", XSPR(31,339,942), XSPR_MASK
, PPC750
, PPCNONE
, {RT
}},
4983 {"mfzpr", XSPR(31,339,944), XSPR_MASK
, PPC403
, PPCNONE
, {RT
}},
4984 {"mfpid", XSPR(31,339,945), XSPR_MASK
, PPC403
, PPCNONE
, {RT
}},
4985 {"mfmmucr", XSPR(31,339,946), XSPR_MASK
, TITAN
, PPCNONE
, {RT
}},
4986 {"mfccr0", XSPR(31,339,947), XSPR_MASK
, PPC405
|TITAN
, PPCNONE
, {RT
}},
4987 {"mfiac3", XSPR(31,339,948), XSPR_MASK
, PPC405
, PPCNONE
, {RT
}},
4988 {"mfiac4", XSPR(31,339,949), XSPR_MASK
, PPC405
, PPCNONE
, {RT
}},
4989 {"mfdvc1", XSPR(31,339,950), XSPR_MASK
, PPC405
, PPCNONE
, {RT
}},
4990 {"mfdvc2", XSPR(31,339,951), XSPR_MASK
, PPC405
, PPCNONE
, {RT
}},
4991 {"mfmmcr0", XSPR(31,339,952), XSPR_MASK
, PPC750
, PPCNONE
, {RT
}},
4992 {"mfpmc1", XSPR(31,339,953), XSPR_MASK
, PPC750
, PPCNONE
, {RT
}},
4993 {"mfsgr", XSPR(31,339,953), XSPR_MASK
, PPC403
, PPCNONE
, {RT
}},
4994 {"mfdcwr", XSPR(31,339,954), XSPR_MASK
, PPC403
, PPCNONE
, {RT
}},
4995 {"mfpmc2", XSPR(31,339,954), XSPR_MASK
, PPC750
, PPCNONE
, {RT
}},
4996 {"mfsia", XSPR(31,339,955), XSPR_MASK
, PPC750
, PPCNONE
, {RT
}},
4997 {"mfsler", XSPR(31,339,955), XSPR_MASK
, PPC405
, PPCNONE
, {RT
}},
4998 {"mfmmcr1", XSPR(31,339,956), XSPR_MASK
, PPC750
, PPCNONE
, {RT
}},
4999 {"mfsu0r", XSPR(31,339,956), XSPR_MASK
, PPC405
, PPCNONE
, {RT
}},
5000 {"mfdbcr1", XSPR(31,339,957), XSPR_MASK
, PPC405
, PPCNONE
, {RT
}},
5001 {"mfpmc3", XSPR(31,339,957), XSPR_MASK
, PPC750
, PPCNONE
, {RT
}},
5002 {"mfpmc4", XSPR(31,339,958), XSPR_MASK
, PPC750
, PPCNONE
, {RT
}},
5003 {"mficdbdr", XSPR(31,339,979), XSPR_MASK
, PPC403
|TITAN
, PPCNONE
, {RT
}},
5004 {"mfesr", XSPR(31,339,980), XSPR_MASK
, PPC403
, PPCNONE
, {RT
}},
5005 {"mfdear", XSPR(31,339,981), XSPR_MASK
, PPC403
, PPCNONE
, {RT
}},
5006 {"mfevpr", XSPR(31,339,982), XSPR_MASK
, PPC403
, PPCNONE
, {RT
}},
5007 {"mfcdbcr", XSPR(31,339,983), XSPR_MASK
, PPC403
, PPCNONE
, {RT
}},
5008 {"mftsr", XSPR(31,339,984), XSPR_MASK
, PPC403
, PPCNONE
, {RT
}},
5009 {"mftcr", XSPR(31,339,986), XSPR_MASK
, PPC403
, PPCNONE
, {RT
}},
5010 {"mfpit", XSPR(31,339,987), XSPR_MASK
, PPC403
, PPCNONE
, {RT
}},
5011 {"mftbhi", XSPR(31,339,988), XSPR_MASK
, PPC403
, PPCNONE
, {RT
}},
5012 {"mftblo", XSPR(31,339,989), XSPR_MASK
, PPC403
, PPCNONE
, {RT
}},
5013 {"mfsrr2", XSPR(31,339,990), XSPR_MASK
, PPC403
, PPCNONE
, {RT
}},
5014 {"mfsrr3", XSPR(31,339,991), XSPR_MASK
, PPC403
, PPCNONE
, {RT
}},
5015 {"mfdbsr", XSPR(31,339,1008), XSPR_MASK
, PPC403
, PPCNONE
, {RT
}},
5016 {"mfdbcr0", XSPR(31,339,1010), XSPR_MASK
, PPC405
, PPCNONE
, {RT
}},
5017 {"mfdbdr", XSPR(31,339,1011), XSPR_MASK
, TITAN
, PPCNONE
, {RS
}},
5018 {"mfiac1", XSPR(31,339,1012), XSPR_MASK
, PPC403
, PPCNONE
, {RT
}},
5019 {"mfiac2", XSPR(31,339,1013), XSPR_MASK
, PPC403
, PPCNONE
, {RT
}},
5020 {"mfdac1", XSPR(31,339,1014), XSPR_MASK
, PPC403
, PPCNONE
, {RT
}},
5021 {"mfdac2", XSPR(31,339,1015), XSPR_MASK
, PPC403
, PPCNONE
, {RT
}},
5022 {"mfl2cr", XSPR(31,339,1017), XSPR_MASK
, PPC750
, PPCNONE
, {RT
}},
5023 {"mfdccr", XSPR(31,339,1018), XSPR_MASK
, PPC403
, PPCNONE
, {RT
}},
5024 {"mficcr", XSPR(31,339,1019), XSPR_MASK
, PPC403
, PPCNONE
, {RT
}},
5025 {"mfictc", XSPR(31,339,1019), XSPR_MASK
, PPC750
, PPCNONE
, {RT
}},
5026 {"mfpbl1", XSPR(31,339,1020), XSPR_MASK
, PPC403
, PPCNONE
, {RT
}},
5027 {"mfthrm1", XSPR(31,339,1020), XSPR_MASK
, PPC750
, PPCNONE
, {RT
}},
5028 {"mfpbu1", XSPR(31,339,1021), XSPR_MASK
, PPC403
, PPCNONE
, {RT
}},
5029 {"mfthrm2", XSPR(31,339,1021), XSPR_MASK
, PPC750
, PPCNONE
, {RT
}},
5030 {"mfpbl2", XSPR(31,339,1022), XSPR_MASK
, PPC403
, PPCNONE
, {RT
}},
5031 {"mfthrm3", XSPR(31,339,1022), XSPR_MASK
, PPC750
, PPCNONE
, {RT
}},
5032 {"mfpbu2", XSPR(31,339,1023), XSPR_MASK
, PPC403
, PPCNONE
, {RT
}},
5033 {"mfspr", X(31,339), X_MASK
, COM
|PPCVLE
, PPCNONE
, {RT
, SPR
}},
5035 {"lwax", X(31,341), X_MASK
, PPC64
|PPCVLE
, PPCNONE
, {RT
, RA0
, RB
}},
5037 {"dst", XDSS(31,342,0), XDSS_MASK
, PPCVEC
, PPCNONE
, {RA
, RB
, STRM
}},
5039 {"lhax", X(31,343), X_MASK
, COM
|PPCVLE
, PPCNONE
, {RT
, RA0
, RB
}},
5041 {"lvxl", X(31,359), X_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VD
, RA0
, RB
}},
5043 {"abs", XO(31,360,0,0), XORB_MASK
, M601
, PPCNONE
, {RT
, RA
}},
5044 {"abs.", XO(31,360,0,1), XORB_MASK
, M601
, PPCNONE
, {RT
, RA
}},
5046 {"divs", XO(31,363,0,0), XO_MASK
, M601
, PPCNONE
, {RT
, RA
, RB
}},
5047 {"divs.", XO(31,363,0,1), XO_MASK
, M601
, PPCNONE
, {RT
, RA
, RB
}},
5049 {"tlbia", X(31,370), 0xffffffff, PPC
, TITAN
, {0}},
5051 {"mftbl", XSPR(31,371,268), XSPR_MASK
, PPC
, NO371
, {RT
}},
5052 {"mftbu", XSPR(31,371,269), XSPR_MASK
, PPC
, NO371
, {RT
}},
5053 {"mftb", X(31,371), X_MASK
, PPC
|PPCA2
, NO371
|POWER7
, {RT
, TBR
}},
5055 {"lwaux", X(31,373), X_MASK
, PPC64
|PPCVLE
, PPCNONE
, {RT
, RAL
, RB
}},
5057 {"dstst", XDSS(31,374,0), XDSS_MASK
, PPCVEC
, PPCNONE
, {RA
, RB
, STRM
}},
5059 {"lhaux", X(31,375), X_MASK
, COM
|PPCVLE
, PPCNONE
, {RT
, RAL
, RB
}},
5061 {"popcntw", X(31,378), XRB_MASK
, POWER7
|PPCA2
, PPCNONE
, {RA
, RS
}},
5063 {"mtdcrx", X(31,387), X_MASK
, BOOKE
|PPCA2
|PPC476
|PPCVLE
, TITAN
, {RA
, RS
}},
5064 {"mtdcrx.", XRC(31,387,1), X_MASK
, PPCA2
, PPCNONE
, {RA
, RS
}},
5066 {"stvexbx", X(31,389), X_MASK
, PPCVEC2
, PPCNONE
, {VS
, RA0
, RB
}},
5068 {"dcblc", X(31,390), X_MASK
, PPCCHLK
|PPC476
|TITAN
|PPCVLE
, PPCNONE
, {CT
, RA0
, RB
}},
5069 {"stdfcmx", APU(31,391,0), APU_MASK
, PPC405
, PPCNONE
, {FCRT
, RA
, RB
}},
5071 {"divdeu", XO(31,393,0,0), XO_MASK
, POWER7
|PPCA2
, PPCNONE
, {RT
, RA
, RB
}},
5072 {"divdeu.", XO(31,393,0,1), XO_MASK
, POWER7
|PPCA2
, PPCNONE
, {RT
, RA
, RB
}},
5073 {"divweu", XO(31,395,0,0), XO_MASK
, POWER7
|PPCA2
, PPCNONE
, {RT
, RA
, RB
}},
5074 {"divweu.", XO(31,395,0,1), XO_MASK
, POWER7
|PPCA2
, PPCNONE
, {RT
, RA
, RB
}},
5076 {"dcblce", X(31,398), X_MASK
, PPCCHLK
, E500MC
, {CT
, RA
, RB
}},
5078 {"slbmte", X(31,402), XRA_MASK
, PPC64
, PPCNONE
, {RS
, RB
}},
5080 {"pbt.", XRC(31,404,1), X_MASK
, POWER8
, PPCNONE
, {RS
, RA0
, RB
}},
5082 {"icswx", XRC(31,406,0), X_MASK
, POWER7
|PPCA2
, PPCNONE
, {RS
, RA
, RB
}},
5083 {"icswx.", XRC(31,406,1), X_MASK
, POWER7
|PPCA2
, PPCNONE
, {RS
, RA
, RB
}},
5085 {"sthx", X(31,407), X_MASK
, COM
|PPCVLE
, PPCNONE
, {RS
, RA0
, RB
}},
5087 {"orc", XRC(31,412,0), X_MASK
, COM
|PPCVLE
, PPCNONE
, {RA
, RS
, RB
}},
5088 {"orc.", XRC(31,412,1), X_MASK
, COM
|PPCVLE
, PPCNONE
, {RA
, RS
, RB
}},
5090 {"sthepx", X(31,415), X_MASK
, E500MC
|PPCA2
|PPCVLE
, PPCNONE
, {RS
, RA0
, RB
}},
5092 {"mtdcrux", X(31,419), X_MASK
, PPC464
|PPCVLE
, PPCNONE
, {RA
, RS
}},
5094 {"stvexhx", X(31,421), X_MASK
, PPCVEC2
, PPCNONE
, {VS
, RA0
, RB
}},
5096 {"dcblq.", XRC(31,422,1), X_MASK
, E6500
, PPCNONE
, {CT
, RA0
, RB
}},
5098 {"divde", XO(31,425,0,0), XO_MASK
, POWER7
|PPCA2
, PPCNONE
, {RT
, RA
, RB
}},
5099 {"divde.", XO(31,425,0,1), XO_MASK
, POWER7
|PPCA2
, PPCNONE
, {RT
, RA
, RB
}},
5100 {"divwe", XO(31,427,0,0), XO_MASK
, POWER7
|PPCA2
, PPCNONE
, {RT
, RA
, RB
}},
5101 {"divwe.", XO(31,427,0,1), XO_MASK
, POWER7
|PPCA2
, PPCNONE
, {RT
, RA
, RB
}},
5103 {"clrbhrb", X(31,430), 0xffffffff, POWER8
, PPCNONE
, {0}},
5105 {"slbie", X(31,434), XRTRA_MASK
, PPC64
, PPCNONE
, {RB
}},
5107 {"ecowx", X(31,438), X_MASK
, PPC
, TITAN
, {RT
, RA0
, RB
}},
5109 {"sthux", X(31,439), X_MASK
, COM
|PPCVLE
, PPCNONE
, {RS
, RAS
, RB
}},
5111 {"mdors", 0x7f9ce378, 0xffffffff, E500MC
, PPCNONE
, {0}},
5113 {"miso", 0x7f5ad378, 0xffffffff, E6500
, PPCNONE
, {0}},
5115 /* The "yield", "mdoio" and "mdoom" instructions are extended mnemonics for
5116 "or rX,rX,rX", with rX being r27, r29 and r30 respectively. */
5117 {"yield", 0x7f7bdb78, 0xffffffff, POWER7
, PPCNONE
, {0}},
5118 {"mdoio", 0x7fbdeb78, 0xffffffff, POWER7
, PPCNONE
, {0}},
5119 {"mdoom", 0x7fdef378, 0xffffffff, POWER7
, PPCNONE
, {0}},
5120 {"mr", XRC(31,444,0), X_MASK
, COM
|PPCVLE
, PPCNONE
, {RA
, RS
, RBS
}},
5121 {"or", XRC(31,444,0), X_MASK
, COM
|PPCVLE
, PPCNONE
, {RA
, RS
, RB
}},
5122 {"mr.", XRC(31,444,1), X_MASK
, COM
|PPCVLE
, PPCNONE
, {RA
, RS
, RBS
}},
5123 {"or.", XRC(31,444,1), X_MASK
, COM
|PPCVLE
, PPCNONE
, {RA
, RS
, RB
}},
5125 {"mtexisr", XSPR(31,451, 64), XSPR_MASK
, PPC403
, PPCNONE
, {RS
}},
5126 {"mtexier", XSPR(31,451, 66), XSPR_MASK
, PPC403
, PPCNONE
, {RS
}},
5127 {"mtbr0", XSPR(31,451,128), XSPR_MASK
, PPC403
, PPCNONE
, {RS
}},
5128 {"mtbr1", XSPR(31,451,129), XSPR_MASK
, PPC403
, PPCNONE
, {RS
}},
5129 {"mtbr2", XSPR(31,451,130), XSPR_MASK
, PPC403
, PPCNONE
, {RS
}},
5130 {"mtbr3", XSPR(31,451,131), XSPR_MASK
, PPC403
, PPCNONE
, {RS
}},
5131 {"mtbr4", XSPR(31,451,132), XSPR_MASK
, PPC403
, PPCNONE
, {RS
}},
5132 {"mtbr5", XSPR(31,451,133), XSPR_MASK
, PPC403
, PPCNONE
, {RS
}},
5133 {"mtbr6", XSPR(31,451,134), XSPR_MASK
, PPC403
, PPCNONE
, {RS
}},
5134 {"mtbr7", XSPR(31,451,135), XSPR_MASK
, PPC403
, PPCNONE
, {RS
}},
5135 {"mtbear", XSPR(31,451,144), XSPR_MASK
, PPC403
, PPCNONE
, {RS
}},
5136 {"mtbesr", XSPR(31,451,145), XSPR_MASK
, PPC403
, PPCNONE
, {RS
}},
5137 {"mtiocr", XSPR(31,451,160), XSPR_MASK
, PPC403
, PPCNONE
, {RS
}},
5138 {"mtdmacr0", XSPR(31,451,192), XSPR_MASK
, PPC403
, PPCNONE
, {RS
}},
5139 {"mtdmact0", XSPR(31,451,193), XSPR_MASK
, PPC403
, PPCNONE
, {RS
}},
5140 {"mtdmada0", XSPR(31,451,194), XSPR_MASK
, PPC403
, PPCNONE
, {RS
}},
5141 {"mtdmasa0", XSPR(31,451,195), XSPR_MASK
, PPC403
, PPCNONE
, {RS
}},
5142 {"mtdmacc0", XSPR(31,451,196), XSPR_MASK
, PPC403
, PPCNONE
, {RS
}},
5143 {"mtdmacr1", XSPR(31,451,200), XSPR_MASK
, PPC403
, PPCNONE
, {RS
}},
5144 {"mtdmact1", XSPR(31,451,201), XSPR_MASK
, PPC403
, PPCNONE
, {RS
}},
5145 {"mtdmada1", XSPR(31,451,202), XSPR_MASK
, PPC403
, PPCNONE
, {RS
}},
5146 {"mtdmasa1", XSPR(31,451,203), XSPR_MASK
, PPC403
, PPCNONE
, {RS
}},
5147 {"mtdmacc1", XSPR(31,451,204), XSPR_MASK
, PPC403
, PPCNONE
, {RS
}},
5148 {"mtdmacr2", XSPR(31,451,208), XSPR_MASK
, PPC403
, PPCNONE
, {RS
}},
5149 {"mtdmact2", XSPR(31,451,209), XSPR_MASK
, PPC403
, PPCNONE
, {RS
}},
5150 {"mtdmada2", XSPR(31,451,210), XSPR_MASK
, PPC403
, PPCNONE
, {RS
}},
5151 {"mtdmasa2", XSPR(31,451,211), XSPR_MASK
, PPC403
, PPCNONE
, {RS
}},
5152 {"mtdmacc2", XSPR(31,451,212), XSPR_MASK
, PPC403
, PPCNONE
, {RS
}},
5153 {"mtdmacr3", XSPR(31,451,216), XSPR_MASK
, PPC403
, PPCNONE
, {RS
}},
5154 {"mtdmact3", XSPR(31,451,217), XSPR_MASK
, PPC403
, PPCNONE
, {RS
}},
5155 {"mtdmada3", XSPR(31,451,218), XSPR_MASK
, PPC403
, PPCNONE
, {RS
}},
5156 {"mtdmasa3", XSPR(31,451,219), XSPR_MASK
, PPC403
, PPCNONE
, {RS
}},
5157 {"mtdmacc3", XSPR(31,451,220), XSPR_MASK
, PPC403
, PPCNONE
, {RS
}},
5158 {"mtdmasr", XSPR(31,451,224), XSPR_MASK
, PPC403
, PPCNONE
, {RS
}},
5159 {"mtdcr", X(31,451), X_MASK
, PPC403
|BOOKE
|PPCA2
|PPC476
|PPCVLE
, TITAN
, {SPR
, RS
}},
5160 {"mtdcr.", XRC(31,451,1), X_MASK
, PPCA2
, PPCNONE
, {SPR
, RS
}},
5162 {"stvexwx", X(31,453), X_MASK
, PPCVEC2
, PPCNONE
, {VS
, RA0
, RB
}},
5164 {"dccci", X(31,454), XRT_MASK
, PPC403
|PPC440
|TITAN
|PPCA2
, PPCNONE
, {RAOPT
, RBOPT
}},
5165 {"dci", X(31,454), XRARB_MASK
, PPCA2
|PPC476
|PPCVLE
, PPCNONE
, {CT
}},
5167 {"divdu", XO(31,457,0,0), XO_MASK
, PPC64
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
5168 {"divdu.", XO(31,457,0,1), XO_MASK
, PPC64
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
5170 {"divwu", XO(31,459,0,0), XO_MASK
, PPC
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
5171 {"divwu.", XO(31,459,0,1), XO_MASK
, PPC
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
5173 {"mtpmr", X(31,462), X_MASK
, PPCPMR
|PPCE300
|PPCVLE
, PPCNONE
, {PMR
, RS
}},
5174 {"mttmr", X(31,494), X_MASK
, PPCTMR
|E6500
, PPCNONE
, {TMR
, RS
}},
5176 {"mtmq", XSPR(31,467, 0), XSPR_MASK
, M601
, PPCNONE
, {RS
}},
5177 {"mtxer", XSPR(31,467, 1), XSPR_MASK
, COM
|PPCVLE
, PPCNONE
, {RS
}},
5178 {"mtlr", XSPR(31,467, 8), XSPR_MASK
, COM
|PPCVLE
, PPCNONE
, {RS
}},
5179 {"mtctr", XSPR(31,467, 9), XSPR_MASK
, COM
|PPCVLE
, PPCNONE
, {RS
}},
5180 {"mttid", XSPR(31,467, 17), XSPR_MASK
, POWER
, PPCNONE
, {RS
}},
5181 {"mtdsisr", XSPR(31,467, 18), XSPR_MASK
, COM
, TITAN
, {RS
}},
5182 {"mtdar", XSPR(31,467, 19), XSPR_MASK
, COM
, TITAN
, {RS
}},
5183 {"mtrtcu", XSPR(31,467, 20), XSPR_MASK
, COM
, TITAN
, {RS
}},
5184 {"mtrtcl", XSPR(31,467, 21), XSPR_MASK
, COM
, TITAN
, {RS
}},
5185 {"mtdec", XSPR(31,467, 22), XSPR_MASK
, COM
, PPCNONE
, {RS
}},
5186 {"mtsdr0", XSPR(31,467, 24), XSPR_MASK
, POWER
, PPCNONE
, {RS
}},
5187 {"mtsdr1", XSPR(31,467, 25), XSPR_MASK
, COM
, TITAN
, {RS
}},
5188 {"mtsrr0", XSPR(31,467, 26), XSPR_MASK
, COM
|PPCVLE
, PPCNONE
, {RS
}},
5189 {"mtsrr1", XSPR(31,467, 27), XSPR_MASK
, COM
|PPCVLE
, PPCNONE
, {RS
}},
5190 {"mtcfar", XSPR(31,467, 28), XSPR_MASK
, POWER6
, PPCNONE
, {RS
}},
5191 {"mtpid", XSPR(31,467, 48), XSPR_MASK
, BOOKE
|PPCVLE
, PPCNONE
, {RS
}},
5192 {"mtdecar", XSPR(31,467, 54), XSPR_MASK
, BOOKE
|PPCVLE
, PPCNONE
, {RS
}},
5193 {"mtcsrr0", XSPR(31,467, 58), XSPR_MASK
, BOOKE
|PPCVLE
, PPCNONE
, {RS
}},
5194 {"mtcsrr1", XSPR(31,467, 59), XSPR_MASK
, BOOKE
|PPCVLE
, PPCNONE
, {RS
}},
5195 {"mtdear", XSPR(31,467, 61), XSPR_MASK
, BOOKE
|PPCVLE
, PPCNONE
, {RS
}},
5196 {"mtesr", XSPR(31,467, 62), XSPR_MASK
, BOOKE
|PPCVLE
, PPCNONE
, {RS
}},
5197 {"mtivpr", XSPR(31,467, 63), XSPR_MASK
, BOOKE
|PPCVLE
, PPCNONE
, {RS
}},
5198 {"mtcmpa", XSPR(31,467,144), XSPR_MASK
, PPC860
, PPCNONE
, {RS
}},
5199 {"mtcmpb", XSPR(31,467,145), XSPR_MASK
, PPC860
, PPCNONE
, {RS
}},
5200 {"mtcmpc", XSPR(31,467,146), XSPR_MASK
, PPC860
, PPCNONE
, {RS
}},
5201 {"mtcmpd", XSPR(31,467,147), XSPR_MASK
, PPC860
, PPCNONE
, {RS
}},
5202 {"mticr", XSPR(31,467,148), XSPR_MASK
, PPC860
, PPCNONE
, {RS
}},
5203 {"mtder", XSPR(31,467,149), XSPR_MASK
, PPC860
, PPCNONE
, {RS
}},
5204 {"mtcounta", XSPR(31,467,150), XSPR_MASK
, PPC860
, PPCNONE
, {RS
}},
5205 {"mtcountb", XSPR(31,467,151), XSPR_MASK
, PPC860
, PPCNONE
, {RS
}},
5206 {"mtcmpe", XSPR(31,467,152), XSPR_MASK
, PPC860
, PPCNONE
, {RS
}},
5207 {"mtcmpf", XSPR(31,467,153), XSPR_MASK
, PPC860
, PPCNONE
, {RS
}},
5208 {"mtcmpg", XSPR(31,467,154), XSPR_MASK
, PPC860
, PPCNONE
, {RS
}},
5209 {"mtcmph", XSPR(31,467,155), XSPR_MASK
, PPC860
, PPCNONE
, {RS
}},
5210 {"mtlctrl1", XSPR(31,467,156), XSPR_MASK
, PPC860
, PPCNONE
, {RS
}},
5211 {"mtlctrl2", XSPR(31,467,157), XSPR_MASK
, PPC860
, PPCNONE
, {RS
}},
5212 {"mtictrl", XSPR(31,467,158), XSPR_MASK
, PPC860
, PPCNONE
, {RS
}},
5213 {"mtbar", XSPR(31,467,159), XSPR_MASK
, PPC860
, PPCNONE
, {RS
}},
5214 {"mtvrsave", XSPR(31,467,256), XSPR_MASK
, PPCVEC
, PPCNONE
, {RS
}},
5215 {"mtusprg0", XSPR(31,467,256), XSPR_MASK
, BOOKE
|PPCVLE
, PPCNONE
, {RS
}},
5216 {"mtsprg", XSPR(31,467,256), XSPRG_MASK
, PPC
|PPCVLE
, PPCNONE
, {SPRG
, RS
}},
5217 {"mtsprg0", XSPR(31,467,272), XSPR_MASK
, PPC
|PPCVLE
, PPCNONE
, {RS
}},
5218 {"mtsprg1", XSPR(31,467,273), XSPR_MASK
, PPC
|PPCVLE
, PPCNONE
, {RS
}},
5219 {"mtsprg2", XSPR(31,467,274), XSPR_MASK
, PPC
|PPCVLE
, PPCNONE
, {RS
}},
5220 {"mtsprg3", XSPR(31,467,275), XSPR_MASK
, PPC
|PPCVLE
, PPCNONE
, {RS
}},
5221 {"mtsprg4", XSPR(31,467,276), XSPR_MASK
, PPC405
|BOOKE
|PPCVLE
, PPCNONE
, {RS
}},
5222 {"mtsprg5", XSPR(31,467,277), XSPR_MASK
, PPC405
|BOOKE
|PPCVLE
, PPCNONE
, {RS
}},
5223 {"mtsprg6", XSPR(31,467,278), XSPR_MASK
, PPC405
|BOOKE
|PPCVLE
, PPCNONE
, {RS
}},
5224 {"mtsprg7", XSPR(31,467,279), XSPR_MASK
, PPC405
|BOOKE
|PPCVLE
, PPCNONE
, {RS
}},
5225 {"mtasr", XSPR(31,467,280), XSPR_MASK
, PPC64
, PPCNONE
, {RS
}},
5226 {"mtear", XSPR(31,467,282), XSPR_MASK
, PPC
, TITAN
, {RS
}},
5227 {"mttbl", XSPR(31,467,284), XSPR_MASK
, PPC
, PPCNONE
, {RS
}},
5228 {"mttbu", XSPR(31,467,285), XSPR_MASK
, PPC
, PPCNONE
, {RS
}},
5229 {"mtdbsr", XSPR(31,467,304), XSPR_MASK
, BOOKE
|PPCVLE
, PPCNONE
, {RS
}},
5230 {"mtdbcr0", XSPR(31,467,308), XSPR_MASK
, BOOKE
|PPCVLE
, PPCNONE
, {RS
}},
5231 {"mtdbcr1", XSPR(31,467,309), XSPR_MASK
, BOOKE
|PPCVLE
, PPCNONE
, {RS
}},
5232 {"mtdbcr2", XSPR(31,467,310), XSPR_MASK
, BOOKE
|PPCVLE
, PPCNONE
, {RS
}},
5233 {"mtiac1", XSPR(31,467,312), XSPR_MASK
, BOOKE
|PPCVLE
, PPCNONE
, {RS
}},
5234 {"mtiac2", XSPR(31,467,313), XSPR_MASK
, BOOKE
|PPCVLE
, PPCNONE
, {RS
}},
5235 {"mtiac3", XSPR(31,467,314), XSPR_MASK
, BOOKE
|PPCVLE
, PPCNONE
, {RS
}},
5236 {"mtiac4", XSPR(31,467,315), XSPR_MASK
, BOOKE
|PPCVLE
, PPCNONE
, {RS
}},
5237 {"mtdac1", XSPR(31,467,316), XSPR_MASK
, BOOKE
|PPCVLE
, PPCNONE
, {RS
}},
5238 {"mtdac2", XSPR(31,467,317), XSPR_MASK
, BOOKE
|PPCVLE
, PPCNONE
, {RS
}},
5239 {"mtdvc1", XSPR(31,467,318), XSPR_MASK
, BOOKE
|PPCVLE
, PPCNONE
, {RS
}},
5240 {"mtdvc2", XSPR(31,467,319), XSPR_MASK
, BOOKE
|PPCVLE
, PPCNONE
, {RS
}},
5241 {"mttsr", XSPR(31,467,336), XSPR_MASK
, BOOKE
|PPCVLE
, PPCNONE
, {RS
}},
5242 {"mttcr", XSPR(31,467,340), XSPR_MASK
, BOOKE
|PPCVLE
, PPCNONE
, {RS
}},
5243 {"mtivor0", XSPR(31,467,400), XSPR_MASK
, BOOKE
|PPCVLE
, PPCNONE
, {RS
}},
5244 {"mtivor1", XSPR(31,467,401), XSPR_MASK
, BOOKE
|PPCVLE
, PPCNONE
, {RS
}},
5245 {"mtivor2", XSPR(31,467,402), XSPR_MASK
, BOOKE
|PPCVLE
, PPCNONE
, {RS
}},
5246 {"mtivor3", XSPR(31,467,403), XSPR_MASK
, BOOKE
|PPCVLE
, PPCNONE
, {RS
}},
5247 {"mtivor4", XSPR(31,467,404), XSPR_MASK
, BOOKE
|PPCVLE
, PPCNONE
, {RS
}},
5248 {"mtivor5", XSPR(31,467,405), XSPR_MASK
, BOOKE
|PPCVLE
, PPCNONE
, {RS
}},
5249 {"mtivor6", XSPR(31,467,406), XSPR_MASK
, BOOKE
|PPCVLE
, PPCNONE
, {RS
}},
5250 {"mtivor7", XSPR(31,467,407), XSPR_MASK
, BOOKE
|PPCVLE
, PPCNONE
, {RS
}},
5251 {"mtivor8", XSPR(31,467,408), XSPR_MASK
, BOOKE
|PPCVLE
, PPCNONE
, {RS
}},
5252 {"mtivor9", XSPR(31,467,409), XSPR_MASK
, BOOKE
|PPCVLE
, PPCNONE
, {RS
}},
5253 {"mtivor10", XSPR(31,467,410), XSPR_MASK
, BOOKE
|PPCVLE
, PPCNONE
, {RS
}},
5254 {"mtivor11", XSPR(31,467,411), XSPR_MASK
, BOOKE
|PPCVLE
, PPCNONE
, {RS
}},
5255 {"mtivor12", XSPR(31,467,412), XSPR_MASK
, BOOKE
|PPCVLE
, PPCNONE
, {RS
}},
5256 {"mtivor13", XSPR(31,467,413), XSPR_MASK
, BOOKE
|PPCVLE
, PPCNONE
, {RS
}},
5257 {"mtivor14", XSPR(31,467,414), XSPR_MASK
, BOOKE
|PPCVLE
, PPCNONE
, {RS
}},
5258 {"mtivor15", XSPR(31,467,415), XSPR_MASK
, BOOKE
|PPCVLE
, PPCNONE
, {RS
}},
5259 {"mtspefscr", XSPR(31,467,512), XSPR_MASK
, PPCSPE
, PPCNONE
, {RS
}},
5260 {"mtbbear", XSPR(31,467,513), XSPR_MASK
, PPCBRLK
, PPCNONE
, {RS
}},
5261 {"mtbbtar", XSPR(31,467,514), XSPR_MASK
, PPCBRLK
, PPCNONE
, {RS
}},
5262 {"mtivor32", XSPR(31,467,528), XSPR_MASK
, PPCSPE
, PPCNONE
, {RS
}},
5263 {"mtibatu", XSPR(31,467,528), XSPRBAT_MASK
, PPC
, TITAN
, {SPRBAT
, RS
}},
5264 {"mtivor33", XSPR(31,467,529), XSPR_MASK
, PPCSPE
, PPCNONE
, {RS
}},
5265 {"mtibatl", XSPR(31,467,529), XSPRBAT_MASK
, PPC
, TITAN
, {SPRBAT
, RS
}},
5266 {"mtivor34", XSPR(31,467,530), XSPR_MASK
, PPCSPE
, PPCNONE
, {RS
}},
5267 {"mtivor35", XSPR(31,467,531), XSPR_MASK
, PPCPMR
, PPCNONE
, {RS
}},
5268 {"mtdbatu", XSPR(31,467,536), XSPRBAT_MASK
, PPC
, TITAN
, {SPRBAT
, RS
}},
5269 {"mtdbatl", XSPR(31,467,537), XSPRBAT_MASK
, PPC
, TITAN
, {SPRBAT
, RS
}},
5270 {"mtmcsrr0", XSPR(31,467,570), XSPR_MASK
, PPCRFMCI
|PPCVLE
, PPCNONE
, {RS
}},
5271 {"mtmcsrr1", XSPR(31,467,571), XSPR_MASK
, PPCRFMCI
|PPCVLE
, PPCNONE
, {RS
}},
5272 {"mtmcsr", XSPR(31,467,572), XSPR_MASK
, PPCRFMCI
, PPCNONE
, {RS
}},
5273 {"mtivndx", XSPR(31,467,880), XSPR_MASK
, TITAN
, PPCNONE
, {RS
}},
5274 {"mtdvndx", XSPR(31,467,881), XSPR_MASK
, TITAN
, PPCNONE
, {RS
}},
5275 {"mtivlim", XSPR(31,467,882), XSPR_MASK
, TITAN
, PPCNONE
, {RS
}},
5276 {"mtdvlim", XSPR(31,467,883), XSPR_MASK
, TITAN
, PPCNONE
, {RS
}},
5277 {"mtclcsr", XSPR(31,467,884), XSPR_MASK
, TITAN
, PPCNONE
, {RS
}},
5278 {"mtccr1", XSPR(31,467,888), XSPR_MASK
, TITAN
, PPCNONE
, {RS
}},
5279 {"mtppr", XSPR(31,467,896), XSPR_MASK
, POWER7
, PPCNONE
, {RS
}},
5280 {"mtppr32", XSPR(31,467,898), XSPR_MASK
, POWER7
, PPCNONE
, {RS
}},
5281 {"mtummcr0", XSPR(31,467,936), XSPR_MASK
, PPC750
, PPCNONE
, {RS
}},
5282 {"mtupmc1", XSPR(31,467,937), XSPR_MASK
, PPC750
, PPCNONE
, {RS
}},
5283 {"mtupmc2", XSPR(31,467,938), XSPR_MASK
, PPC750
, PPCNONE
, {RS
}},
5284 {"mtusia", XSPR(31,467,939), XSPR_MASK
, PPC750
, PPCNONE
, {RS
}},
5285 {"mtummcr1", XSPR(31,467,940), XSPR_MASK
, PPC750
, PPCNONE
, {RS
}},
5286 {"mtupmc3", XSPR(31,467,941), XSPR_MASK
, PPC750
, PPCNONE
, {RS
}},
5287 {"mtupmc4", XSPR(31,467,942), XSPR_MASK
, PPC750
, PPCNONE
, {RS
}},
5288 {"mtzpr", XSPR(31,467,944), XSPR_MASK
, PPC403
, PPCNONE
, {RS
}},
5289 {"mtpid", XSPR(31,467,945), XSPR_MASK
, PPC403
, PPCNONE
, {RS
}},
5290 {"mtrmmucr", XSPR(31,467,946), XSPR_MASK
, TITAN
, PPCNONE
, {RS
}},
5291 {"mtccr0", XSPR(31,467,947), XSPR_MASK
, PPC405
|TITAN
, PPCNONE
, {RS
}},
5292 {"mtiac3", XSPR(31,467,948), XSPR_MASK
, PPC405
, PPCNONE
, {RS
}},
5293 {"mtiac4", XSPR(31,467,949), XSPR_MASK
, PPC405
, PPCNONE
, {RS
}},
5294 {"mtdvc1", XSPR(31,467,950), XSPR_MASK
, PPC405
, PPCNONE
, {RS
}},
5295 {"mtdvc2", XSPR(31,467,951), XSPR_MASK
, PPC405
, PPCNONE
, {RS
}},
5296 {"mtmmcr0", XSPR(31,467,952), XSPR_MASK
, PPC750
, PPCNONE
, {RS
}},
5297 {"mtpmc1", XSPR(31,467,953), XSPR_MASK
, PPC750
, PPCNONE
, {RS
}},
5298 {"mtsgr", XSPR(31,467,953), XSPR_MASK
, PPC403
, PPCNONE
, {RS
}},
5299 {"mtdcwr", XSPR(31,467,954), XSPR_MASK
, PPC403
, PPCNONE
, {RS
}},
5300 {"mtpmc2", XSPR(31,467,954), XSPR_MASK
, PPC750
, PPCNONE
, {RS
}},
5301 {"mtsia", XSPR(31,467,955), XSPR_MASK
, PPC750
, PPCNONE
, {RS
}},
5302 {"mtsler", XSPR(31,467,955), XSPR_MASK
, PPC405
, PPCNONE
, {RS
}},
5303 {"mtmmcr1", XSPR(31,467,956), XSPR_MASK
, PPC750
, PPCNONE
, {RS
}},
5304 {"mtsu0r", XSPR(31,467,956), XSPR_MASK
, PPC405
, PPCNONE
, {RS
}},
5305 {"mtdbcr1", XSPR(31,467,957), XSPR_MASK
, PPC405
, PPCNONE
, {RS
}},
5306 {"mtpmc3", XSPR(31,467,957), XSPR_MASK
, PPC750
, PPCNONE
, {RS
}},
5307 {"mtpmc4", XSPR(31,467,958), XSPR_MASK
, PPC750
, PPCNONE
, {RS
}},
5308 {"mticdbdr", XSPR(31,467,979), XSPR_MASK
, PPC403
, PPCNONE
, {RS
}},
5309 {"mtesr", XSPR(31,467,980), XSPR_MASK
, PPC403
, PPCNONE
, {RS
}},
5310 {"mtdear", XSPR(31,467,981), XSPR_MASK
, PPC403
, PPCNONE
, {RS
}},
5311 {"mtevpr", XSPR(31,467,982), XSPR_MASK
, PPC403
, PPCNONE
, {RS
}},
5312 {"mtcdbcr", XSPR(31,467,983), XSPR_MASK
, PPC403
, PPCNONE
, {RS
}},
5313 {"mttsr", XSPR(31,467,984), XSPR_MASK
, PPC403
, PPCNONE
, {RS
}},
5314 {"mttcr", XSPR(31,467,986), XSPR_MASK
, PPC403
, PPCNONE
, {RS
}},
5315 {"mtpit", XSPR(31,467,987), XSPR_MASK
, PPC403
, PPCNONE
, {RS
}},
5316 {"mttbhi", XSPR(31,467,988), XSPR_MASK
, PPC403
, PPCNONE
, {RS
}},
5317 {"mttblo", XSPR(31,467,989), XSPR_MASK
, PPC403
, PPCNONE
, {RS
}},
5318 {"mtsrr2", XSPR(31,467,990), XSPR_MASK
, PPC403
, PPCNONE
, {RS
}},
5319 {"mtsrr3", XSPR(31,467,991), XSPR_MASK
, PPC403
, PPCNONE
, {RS
}},
5320 {"mtdbsr", XSPR(31,467,1008), XSPR_MASK
, PPC403
, PPCNONE
, {RS
}},
5321 {"mtdbdr", XSPR(31,467,1011), XSPR_MASK
, TITAN
, PPCNONE
, {RS
}},
5322 {"mtdbcr0", XSPR(31,467,1010), XSPR_MASK
, PPC405
, PPCNONE
, {RS
}},
5323 {"mtiac1", XSPR(31,467,1012), XSPR_MASK
, PPC403
, PPCNONE
, {RS
}},
5324 {"mtiac2", XSPR(31,467,1013), XSPR_MASK
, PPC403
, PPCNONE
, {RS
}},
5325 {"mtdac1", XSPR(31,467,1014), XSPR_MASK
, PPC403
, PPCNONE
, {RS
}},
5326 {"mtdac2", XSPR(31,467,1015), XSPR_MASK
, PPC403
, PPCNONE
, {RS
}},
5327 {"mtl2cr", XSPR(31,467,1017), XSPR_MASK
, PPC750
, PPCNONE
, {RS
}},
5328 {"mtdccr", XSPR(31,467,1018), XSPR_MASK
, PPC403
, PPCNONE
, {RS
}},
5329 {"mticcr", XSPR(31,467,1019), XSPR_MASK
, PPC403
, PPCNONE
, {RS
}},
5330 {"mtictc", XSPR(31,467,1019), XSPR_MASK
, PPC750
, PPCNONE
, {RS
}},
5331 {"mtpbl1", XSPR(31,467,1020), XSPR_MASK
, PPC403
, PPCNONE
, {RS
}},
5332 {"mtthrm1", XSPR(31,467,1020), XSPR_MASK
, PPC750
, PPCNONE
, {RS
}},
5333 {"mtpbu1", XSPR(31,467,1021), XSPR_MASK
, PPC403
, PPCNONE
, {RS
}},
5334 {"mtthrm2", XSPR(31,467,1021), XSPR_MASK
, PPC750
, PPCNONE
, {RS
}},
5335 {"mtpbl2", XSPR(31,467,1022), XSPR_MASK
, PPC403
, PPCNONE
, {RS
}},
5336 {"mtthrm3", XSPR(31,467,1022), XSPR_MASK
, PPC750
, PPCNONE
, {RS
}},
5337 {"mtpbu2", XSPR(31,467,1023), XSPR_MASK
, PPC403
, PPCNONE
, {RS
}},
5338 {"mtspr", X(31,467), X_MASK
, COM
|PPCVLE
, PPCNONE
, {SPR
, RS
}},
5340 {"dcbi", X(31,470), XRT_MASK
, PPC
|PPCVLE
, PPCNONE
, {RA0
, RB
}},
5342 {"nand", XRC(31,476,0), X_MASK
, COM
|PPCVLE
, PPCNONE
, {RA
, RS
, RB
}},
5343 {"nand.", XRC(31,476,1), X_MASK
, COM
|PPCVLE
, PPCNONE
, {RA
, RS
, RB
}},
5345 {"dsn", X(31,483), XRT_MASK
, E500MC
|PPCVLE
, PPCNONE
, {RA
, RB
}},
5347 {"dcread", X(31,486), X_MASK
, PPC403
|PPC440
|PPCVLE
, PPCA2
|PPC476
, {RT
, RA0
, RB
}},
5349 {"icbtls", X(31,486), X_MASK
, PPCCHLK
|PPC476
|TITAN
|PPCVLE
, PPCNONE
, {CT
, RA0
, RB
}},
5351 {"stvxl", X(31,487), X_MASK
, PPCVEC
|PPCVLE
, PPCNONE
, {VS
, RA0
, RB
}},
5353 {"nabs", XO(31,488,0,0), XORB_MASK
, M601
, PPCNONE
, {RT
, RA
}},
5354 {"nabs.", XO(31,488,0,1), XORB_MASK
, M601
, PPCNONE
, {RT
, RA
}},
5356 {"divd", XO(31,489,0,0), XO_MASK
, PPC64
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
5357 {"divd.", XO(31,489,0,1), XO_MASK
, PPC64
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
5359 {"divw", XO(31,491,0,0), XO_MASK
, PPC
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
5360 {"divw.", XO(31,491,0,1), XO_MASK
, PPC
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
5362 {"icbtlse", X(31,494), X_MASK
, PPCCHLK
, E500MC
, {CT
, RA
, RB
}},
5364 {"slbia", X(31,498), 0xffffffff, PPC64
, PPCNONE
, {0}},
5366 {"cli", X(31,502), XRB_MASK
, POWER
, PPCNONE
, {RT
, RA
}},
5368 {"popcntd", X(31,506), XRB_MASK
, POWER7
|PPCA2
, PPCNONE
, {RA
, RS
}},
5370 {"cmpb", X(31,508), X_MASK
, POWER6
|PPCA2
|PPC476
, PPCNONE
, {RA
, RS
, RB
}},
5372 {"mcrxr", X(31,512), XRARB_MASK
|(3<<21), COM
|PPCVLE
, POWER7
, {BF
}},
5374 {"lbdx", X(31,515), X_MASK
, E500MC
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
5376 {"bblels", X(31,518), X_MASK
, PPCBRLK
, PPCNONE
, {0}},
5378 {"lvlx", X(31,519), X_MASK
, CELL
, PPCNONE
, {VD
, RA0
, RB
}},
5379 {"lbfcmux", APU(31,519,0), APU_MASK
, PPC405
, PPCNONE
, {FCRT
, RA
, RB
}},
5381 {"subfco", XO(31,8,1,0), XO_MASK
, PPCCOM
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
5382 {"sfo", XO(31,8,1,0), XO_MASK
, PWRCOM
, PPCNONE
, {RT
, RA
, RB
}},
5383 {"subco", XO(31,8,1,0), XO_MASK
, PPCCOM
|PPCVLE
, PPCNONE
, {RT
, RB
, RA
}},
5384 {"subfco.", XO(31,8,1,1), XO_MASK
, PPCCOM
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
5385 {"sfo.", XO(31,8,1,1), XO_MASK
, PWRCOM
, PPCNONE
, {RT
, RA
, RB
}},
5386 {"subco.", XO(31,8,1,1), XO_MASK
, PPCCOM
|PPCVLE
, PPCNONE
, {RT
, RB
, RA
}},
5388 {"addco", XO(31,10,1,0), XO_MASK
, PPCCOM
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
5389 {"ao", XO(31,10,1,0), XO_MASK
, PWRCOM
, PPCNONE
, {RT
, RA
, RB
}},
5390 {"addco.", XO(31,10,1,1), XO_MASK
, PPCCOM
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
5391 {"ao.", XO(31,10,1,1), XO_MASK
, PWRCOM
, PPCNONE
, {RT
, RA
, RB
}},
5393 {"lxsspx", X(31,524), XX1_MASK
, PPCVSX2
, PPCNONE
, {XT6
, RA0
, RB
}},
5395 {"clcs", X(31,531), XRB_MASK
, M601
, PPCNONE
, {RT
, RA
}},
5397 {"ldbrx", X(31,532), X_MASK
, CELL
|POWER7
|PPCA2
, PPCNONE
, {RT
, RA0
, RB
}},
5399 {"lswx", X(31,533), X_MASK
, PPCCOM
|PPCVLE
, E500
|E500MC
, {RT
, RAX
, RBX
}},
5400 {"lsx", X(31,533), X_MASK
, PWRCOM
, PPCNONE
, {RT
, RA
, RB
}},
5402 {"lwbrx", X(31,534), X_MASK
, PPCCOM
|PPCVLE
, PPCNONE
, {RT
, RA0
, RB
}},
5403 {"lbrx", X(31,534), X_MASK
, PWRCOM
, PPCNONE
, {RT
, RA
, RB
}},
5405 {"lfsx", X(31,535), X_MASK
, COM
, PPCEFS
, {FRT
, RA0
, RB
}},
5407 {"srw", XRC(31,536,0), X_MASK
, PPCCOM
|PPCVLE
, PPCNONE
, {RA
, RS
, RB
}},
5408 {"sr", XRC(31,536,0), X_MASK
, PWRCOM
, PPCNONE
, {RA
, RS
, RB
}},
5409 {"srw.", XRC(31,536,1), X_MASK
, PPCCOM
|PPCVLE
, PPCNONE
, {RA
, RS
, RB
}},
5410 {"sr.", XRC(31,536,1), X_MASK
, PWRCOM
, PPCNONE
, {RA
, RS
, RB
}},
5412 {"rrib", XRC(31,537,0), X_MASK
, M601
, PPCNONE
, {RA
, RS
, RB
}},
5413 {"rrib.", XRC(31,537,1), X_MASK
, M601
, PPCNONE
, {RA
, RS
, RB
}},
5415 {"srd", XRC(31,539,0), X_MASK
, PPC64
, PPCNONE
, {RA
, RS
, RB
}},
5416 {"srd.", XRC(31,539,1), X_MASK
, PPC64
, PPCNONE
, {RA
, RS
, RB
}},
5418 {"maskir", XRC(31,541,0), X_MASK
, M601
, PPCNONE
, {RA
, RS
, RB
}},
5419 {"maskir.", XRC(31,541,1), X_MASK
, M601
, PPCNONE
, {RA
, RS
, RB
}},
5421 {"lhdx", X(31,547), X_MASK
, E500MC
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
5423 {"lvtrx", X(31,549), X_MASK
, PPCVEC2
, PPCNONE
, {VD
, RA0
, RB
}},
5425 {"bbelr", X(31,550), X_MASK
, PPCBRLK
, PPCNONE
, {0}},
5427 {"lvrx", X(31,551), X_MASK
, CELL
, PPCNONE
, {VD
, RA0
, RB
}},
5428 {"lhfcmux", APU(31,551,0), APU_MASK
, PPC405
, PPCNONE
, {FCRT
, RA
, RB
}},
5430 {"subfo", XO(31,40,1,0), XO_MASK
, PPC
, PPCNONE
, {RT
, RA
, RB
}},
5431 {"subo", XO(31,40,1,0), XO_MASK
, PPC
, PPCNONE
, {RT
, RB
, RA
}},
5432 {"subfo.", XO(31,40,1,1), XO_MASK
, PPC
, PPCNONE
, {RT
, RA
, RB
}},
5433 {"subo.", XO(31,40,1,1), XO_MASK
, PPC
, PPCNONE
, {RT
, RB
, RA
}},
5435 {"tlbsync", X(31,566), 0xffffffff, PPC
|PPCVLE
, PPCNONE
, {0}},
5437 {"lfsux", X(31,567), X_MASK
, COM
, PPCEFS
, {FRT
, RAS
, RB
}},
5439 {"lwdx", X(31,579), X_MASK
, E500MC
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
5441 {"lvtlx", X(31,581), X_MASK
, PPCVEC2
, PPCNONE
, {VD
, RA0
, RB
}},
5443 {"lwfcmux", APU(31,583,0), APU_MASK
, PPC405
, PPCNONE
, {FCRT
, RA
, RB
}},
5445 {"lxsdx", X(31,588), XX1_MASK
, PPCVSX
, PPCNONE
, {XT6
, RA0
, RB
}},
5447 {"mfsr", X(31,595), XRB_MASK
|(1<<20), COM
, NON32
, {RT
, SR
}},
5449 {"lswi", X(31,597), X_MASK
, PPCCOM
|PPCVLE
, E500
|E500MC
, {RT
, RAX
, NBI
}},
5450 {"lsi", X(31,597), X_MASK
, PWRCOM
, PPCNONE
, {RT
, RA0
, NB
}},
5452 {"lwsync", XSYNC(31,598,1), 0xffffffff, PPC
, E500
, {0}},
5453 {"ptesync", XSYNC(31,598,2), 0xffffffff, PPC64
, PPCNONE
, {0}},
5454 {"sync", X(31,598), XSYNCLE_MASK
,E6500
, PPCNONE
, {LS
, ESYNC
}},
5455 {"sync", X(31,598), XSYNC_MASK
, PPCCOM
|PPCVLE
, BOOKE
|PPC476
, {LS
}},
5456 {"msync", X(31,598), 0xffffffff, BOOKE
|PPCA2
|PPC476
, PPCNONE
, {0}},
5457 {"sync", X(31,598), 0xffffffff, BOOKE
|PPC476
, E6500
, {0}},
5458 {"lwsync", X(31,598), 0xffffffff, E500
, PPCNONE
, {0}},
5459 {"dcs", X(31,598), 0xffffffff, PWRCOM
, PPCNONE
, {0}},
5461 {"lfdx", X(31,599), X_MASK
, COM
, PPCEFS
, {FRT
, RA0
, RB
}},
5463 {"mffgpr", XRC(31,607,0), XRA_MASK
, POWER6
, POWER7
, {FRT
, RB
}},
5464 {"lfdepx", X(31,607), X_MASK
, E500MC
|PPCA2
|PPCVLE
, PPCNONE
, {FRT
, RA0
, RB
}},
5466 {"lddx", X(31,611), X_MASK
, E500MC
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
5468 {"lvswx", X(31,613), X_MASK
, PPCVEC2
, PPCNONE
, {VD
, RA0
, RB
}},
5470 {"lqfcmux", APU(31,615,0), APU_MASK
, PPC405
, PPCNONE
, {FCRT
, RA
, RB
}},
5472 {"nego", XO(31,104,1,0), XORB_MASK
, COM
|PPCVLE
, PPCNONE
, {RT
, RA
}},
5473 {"nego.", XO(31,104,1,1), XORB_MASK
, COM
|PPCVLE
, PPCNONE
, {RT
, RA
}},
5475 {"mulo", XO(31,107,1,0), XO_MASK
, M601
, PPCNONE
, {RT
, RA
, RB
}},
5476 {"mulo.", XO(31,107,1,1), XO_MASK
, M601
, PPCNONE
, {RT
, RA
, RB
}},
5478 {"mfsri", X(31,627), X_MASK
, M601
, PPCNONE
, {RT
, RA
, RB
}},
5480 {"dclst", X(31,630), XRB_MASK
, M601
, PPCNONE
, {RS
, RA
}},
5482 {"lfdux", X(31,631), X_MASK
, COM
, PPCEFS
, {FRT
, RAS
, RB
}},
5484 {"stbdx", X(31,643), X_MASK
, E500MC
, PPCNONE
, {RS
, RA
, RB
}},
5486 {"stvlx", X(31,647), X_MASK
, CELL
, PPCNONE
, {VS
, RA0
, RB
}},
5487 {"stbfcmux", APU(31,647,0), APU_MASK
, PPC405
, PPCNONE
, {FCRT
, RA
, RB
}},
5489 {"stxsspx", X(31,652), XX1_MASK
, PPCVSX2
, PPCNONE
, {XS6
, RA0
, RB
}},
5491 {"tbegin.", XRC(31,654,1), XRTLRARB_MASK
,PPCHTM
, PPCNONE
, {HTM_R
}},
5493 {"subfeo", XO(31,136,1,0), XO_MASK
, PPCCOM
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
5494 {"sfeo", XO(31,136,1,0), XO_MASK
, PWRCOM
, PPCNONE
, {RT
, RA
, RB
}},
5495 {"subfeo.", XO(31,136,1,1), XO_MASK
, PPCCOM
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
5496 {"sfeo.", XO(31,136,1,1), XO_MASK
, PWRCOM
, PPCNONE
, {RT
, RA
, RB
}},
5498 {"addeo", XO(31,138,1,0), XO_MASK
, PPCCOM
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
5499 {"aeo", XO(31,138,1,0), XO_MASK
, PWRCOM
, PPCNONE
, {RT
, RA
, RB
}},
5500 {"addeo.", XO(31,138,1,1), XO_MASK
, PPCCOM
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
5501 {"aeo.", XO(31,138,1,1), XO_MASK
, PWRCOM
, PPCNONE
, {RT
, RA
, RB
}},
5503 {"mfsrin", X(31,659), XRA_MASK
, PPC
, NON32
, {RT
, RB
}},
5505 {"stdbrx", X(31,660), X_MASK
, CELL
|POWER7
|PPCA2
, PPCNONE
, {RS
, RA0
, RB
}},
5507 {"stswx", X(31,661), X_MASK
, PPCCOM
|PPCVLE
, E500
|E500MC
, {RS
, RA0
, RB
}},
5508 {"stsx", X(31,661), X_MASK
, PWRCOM
, PPCNONE
, {RS
, RA0
, RB
}},
5510 {"stwbrx", X(31,662), X_MASK
, PPCCOM
|PPCVLE
, PPCNONE
, {RS
, RA0
, RB
}},
5511 {"stbrx", X(31,662), X_MASK
, PWRCOM
, PPCNONE
, {RS
, RA0
, RB
}},
5513 {"stfsx", X(31,663), X_MASK
, COM
, PPCEFS
, {FRS
, RA0
, RB
}},
5515 {"srq", XRC(31,664,0), X_MASK
, M601
, PPCNONE
, {RA
, RS
, RB
}},
5516 {"srq.", XRC(31,664,1), X_MASK
, M601
, PPCNONE
, {RA
, RS
, RB
}},
5518 {"sre", XRC(31,665,0), X_MASK
, M601
, PPCNONE
, {RA
, RS
, RB
}},
5519 {"sre.", XRC(31,665,1), X_MASK
, M601
, PPCNONE
, {RA
, RS
, RB
}},
5521 {"sthdx", X(31,675), X_MASK
, E500MC
, PPCNONE
, {RS
, RA
, RB
}},
5523 {"stvfrx", X(31,677), X_MASK
, PPCVEC2
, PPCNONE
, {VS
, RA0
, RB
}},
5525 {"stvrx", X(31,679), X_MASK
, CELL
, PPCNONE
, {VS
, RA0
, RB
}},
5526 {"sthfcmux", APU(31,679,0), APU_MASK
, PPC405
, PPCNONE
, {FCRT
, RA
, RB
}},
5528 {"tendall.", XRC(31,686,1)|(1<<25), XRTRARB_MASK
, PPCHTM
, PPCNONE
, {0}},
5529 {"tend.", XRC(31,686,1), XRTARARB_MASK
, PPCHTM
, PPCNONE
, {HTM_A
}},
5531 {"stbcx.", XRC(31,694,1), X_MASK
, POWER7
, PPCNONE
, {RS
, RA0
, RB
}},
5533 {"stfsux", X(31,695), X_MASK
, COM
, PPCEFS
, {FRS
, RAS
, RB
}},
5535 {"sriq", XRC(31,696,0), X_MASK
, M601
, PPCNONE
, {RA
, RS
, SH
}},
5536 {"sriq.", XRC(31,696,1), X_MASK
, M601
, PPCNONE
, {RA
, RS
, SH
}},
5538 {"stwdx", X(31,707), X_MASK
, E500MC
, PPCNONE
, {RS
, RA
, RB
}},
5540 {"stvflx", X(31,709), X_MASK
, PPCVEC2
, PPCNONE
, {VS
, RA0
, RB
}},
5542 {"stwfcmux", APU(31,711,0), APU_MASK
, PPC405
, PPCNONE
, {FCRT
, RA
, RB
}},
5544 {"stxsdx", X(31,716), XX1_MASK
, PPCVSX
, PPCNONE
, {XS6
, RA0
, RB
}},
5546 {"tcheck", X(31,718), XRTBFRARB_MASK
, PPCHTM
, PPCNONE
, {BF
}},
5548 {"subfzeo", XO(31,200,1,0), XORB_MASK
, PPCCOM
|PPCVLE
, PPCNONE
, {RT
, RA
}},
5549 {"sfzeo", XO(31,200,1,0), XORB_MASK
, PWRCOM
, PPCNONE
, {RT
, RA
}},
5550 {"subfzeo.", XO(31,200,1,1), XORB_MASK
, PPCCOM
|PPCVLE
, PPCNONE
, {RT
, RA
}},
5551 {"sfzeo.", XO(31,200,1,1), XORB_MASK
, PWRCOM
, PPCNONE
, {RT
, RA
}},
5553 {"addzeo", XO(31,202,1,0), XORB_MASK
, PPCCOM
|PPCVLE
, PPCNONE
, {RT
, RA
}},
5554 {"azeo", XO(31,202,1,0), XORB_MASK
, PWRCOM
, PPCNONE
, {RT
, RA
}},
5555 {"addzeo.", XO(31,202,1,1), XORB_MASK
, PPCCOM
|PPCVLE
, PPCNONE
, {RT
, RA
}},
5556 {"azeo.", XO(31,202,1,1), XORB_MASK
, PWRCOM
, PPCNONE
, {RT
, RA
}},
5558 {"stswi", X(31,725), X_MASK
, PPCCOM
|PPCVLE
, E500
|E500MC
, {RS
, RA0
, NB
}},
5559 {"stsi", X(31,725), X_MASK
, PWRCOM
, PPCNONE
, {RS
, RA0
, NB
}},
5561 {"sthcx.", XRC(31,726,1), X_MASK
, POWER7
, PPCNONE
, {RS
, RA0
, RB
}},
5563 {"stfdx", X(31,727), X_MASK
, COM
, PPCEFS
, {FRS
, RA0
, RB
}},
5565 {"srlq", XRC(31,728,0), X_MASK
, M601
, PPCNONE
, {RA
, RS
, RB
}},
5566 {"srlq.", XRC(31,728,1), X_MASK
, M601
, PPCNONE
, {RA
, RS
, RB
}},
5568 {"sreq", XRC(31,729,0), X_MASK
, M601
, PPCNONE
, {RA
, RS
, RB
}},
5569 {"sreq.", XRC(31,729,1), X_MASK
, M601
, PPCNONE
, {RA
, RS
, RB
}},
5571 {"mftgpr", XRC(31,735,0), XRA_MASK
, POWER6
, POWER7
, {RT
, FRB
}},
5572 {"stfdepx", X(31,735), X_MASK
, E500MC
|PPCA2
|PPCVLE
, PPCNONE
, {FRS
, RA0
, RB
}},
5574 {"stddx", X(31,739), X_MASK
, E500MC
, PPCNONE
, {RS
, RA
, RB
}},
5576 {"stvswx", X(31,741), X_MASK
, PPCVEC2
, PPCNONE
, {VS
, RA0
, RB
}},
5578 {"stqfcmux", APU(31,743,0), APU_MASK
, PPC405
, PPCNONE
, {FCRT
, RA
, RB
}},
5580 {"subfmeo", XO(31,232,1,0), XORB_MASK
, PPCCOM
, PPCNONE
, {RT
, RA
}},
5581 {"sfmeo", XO(31,232,1,0), XORB_MASK
, PWRCOM
, PPCNONE
, {RT
, RA
}},
5582 {"subfmeo.", XO(31,232,1,1), XORB_MASK
, PPCCOM
, PPCNONE
, {RT
, RA
}},
5583 {"sfmeo.", XO(31,232,1,1), XORB_MASK
, PWRCOM
, PPCNONE
, {RT
, RA
}},
5585 {"mulldo", XO(31,233,1,0), XO_MASK
, PPC64
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
5586 {"mulldo.", XO(31,233,1,1), XO_MASK
, PPC64
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
5588 {"addmeo", XO(31,234,1,0), XORB_MASK
, PPCCOM
|PPCVLE
, PPCNONE
, {RT
, RA
}},
5589 {"ameo", XO(31,234,1,0), XORB_MASK
, PWRCOM
, PPCNONE
, {RT
, RA
}},
5590 {"addmeo.", XO(31,234,1,1), XORB_MASK
, PPCCOM
|PPCVLE
, PPCNONE
, {RT
, RA
}},
5591 {"ameo.", XO(31,234,1,1), XORB_MASK
, PWRCOM
, PPCNONE
, {RT
, RA
}},
5593 {"mullwo", XO(31,235,1,0), XO_MASK
, PPCCOM
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
5594 {"mulso", XO(31,235,1,0), XO_MASK
, PWRCOM
, PPCNONE
, {RT
, RA
, RB
}},
5595 {"mullwo.", XO(31,235,1,1), XO_MASK
, PPCCOM
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
5596 {"mulso.", XO(31,235,1,1), XO_MASK
, PWRCOM
, PPCNONE
, {RT
, RA
, RB
}},
5598 {"tsuspend.", XRCL(31,750,0,1), XRTRARB_MASK
,PPCHTM
, PPCNONE
, {0}},
5599 {"tresume.", XRCL(31,750,1,1), XRTRARB_MASK
,PPCHTM
, PPCNONE
, {0}},
5600 {"tsr.", XRC(31,750,1), XRTLRARB_MASK
,PPCHTM
, PPCNONE
, {L
}},
5602 {"dcba", X(31,758), XRT_MASK
, PPC405
|PPC7450
|BOOKE
|PPCA2
|PPC476
|PPCVLE
, PPCNONE
, {RA0
, RB
}},
5603 {"dcbal", XOPL(31,758,1), XRT_MASK
, E500MC
, PPCNONE
, {RA0
, RB
}},
5605 {"stfdux", X(31,759), X_MASK
, COM
, PPCEFS
, {FRS
, RAS
, RB
}},
5607 {"srliq", XRC(31,760,0), X_MASK
, M601
, PPCNONE
, {RA
, RS
, SH
}},
5608 {"srliq.", XRC(31,760,1), X_MASK
, M601
, PPCNONE
, {RA
, RS
, SH
}},
5610 {"lvsm", X(31,773), X_MASK
, PPCVEC2
, PPCNONE
, {VD
, RA0
, RB
}},
5611 {"stvepxl", X(31,775), X_MASK
, PPCVEC2
, PPCNONE
, {VS
, RA0
, RB
}},
5612 {"lvlxl", X(31,775), X_MASK
, CELL
, PPCNONE
, {VD
, RA0
, RB
}},
5613 {"ldfcmux", APU(31,775,0), APU_MASK
, PPC405
, PPCNONE
, {FCRT
, RA
, RB
}},
5615 {"dozo", XO(31,264,1,0), XO_MASK
, M601
, PPCNONE
, {RT
, RA
, RB
}},
5616 {"dozo.", XO(31,264,1,1), XO_MASK
, M601
, PPCNONE
, {RT
, RA
, RB
}},
5618 {"addo", XO(31,266,1,0), XO_MASK
, PPCCOM
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
5619 {"caxo", XO(31,266,1,0), XO_MASK
, PWRCOM
, PPCNONE
, {RT
, RA
, RB
}},
5620 {"addo.", XO(31,266,1,1), XO_MASK
, PPCCOM
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
5621 {"caxo.", XO(31,266,1,1), XO_MASK
, PWRCOM
, PPCNONE
, {RT
, RA
, RB
}},
5623 {"lxvw4x", X(31,780), XX1_MASK
, PPCVSX
, PPCNONE
, {XT6
, RA0
, RB
}},
5625 {"tabortwc.", XRC(31,782,1), X_MASK
, PPCHTM
, PPCNONE
, {TO
, RA
, RB
}},
5627 {"tlbivax", X(31,786), XRT_MASK
, BOOKE
|PPCA2
|PPC476
|PPCVLE
, PPCNONE
, {RA0
, RB
}},
5629 {"lwzcix", X(31,789), X_MASK
, POWER6
, PPCNONE
, {RT
, RA0
, RB
}},
5631 {"lhbrx", X(31,790), X_MASK
, COM
|PPCVLE
, PPCNONE
, {RT
, RA0
, RB
}},
5633 {"lfdpx", X(31,791), X_MASK
, POWER6
, POWER7
, {FRTp
, RA0
, RB
}},
5634 {"lfqx", X(31,791), X_MASK
, POWER2
, PPCNONE
, {FRT
, RA
, RB
}},
5636 {"sraw", XRC(31,792,0), X_MASK
, PPCCOM
|PPCVLE
, PPCNONE
, {RA
, RS
, RB
}},
5637 {"sra", XRC(31,792,0), X_MASK
, PWRCOM
, PPCNONE
, {RA
, RS
, RB
}},
5638 {"sraw.", XRC(31,792,1), X_MASK
, PPCCOM
|PPCVLE
, PPCNONE
, {RA
, RS
, RB
}},
5639 {"sra.", XRC(31,792,1), X_MASK
, PWRCOM
, PPCNONE
, {RA
, RS
, RB
}},
5641 {"srad", XRC(31,794,0), X_MASK
, PPC64
, PPCNONE
, {RA
, RS
, RB
}},
5642 {"srad.", XRC(31,794,1), X_MASK
, PPC64
, PPCNONE
, {RA
, RS
, RB
}},
5644 {"lfddx", X(31,803), X_MASK
, E500MC
|PPCVLE
, PPCNONE
, {FRT
, RA
, RB
}},
5646 {"lvtrxl", X(31,805), X_MASK
, PPCVEC2
, PPCNONE
, {VD
, RA0
, RB
}},
5647 {"stvepx", X(31,807), X_MASK
, PPCVEC2
, PPCNONE
, {VS
, RA0
, RB
}},
5648 {"lvrxl", X(31,807), X_MASK
, CELL
, PPCNONE
, {VD
, RA0
, RB
}},
5650 {"tabortdc.", XRC(31,814,1), X_MASK
, PPCHTM
, PPCNONE
, {TO
, RA
, RB
}},
5652 {"rac", X(31,818), X_MASK
, M601
, PPCNONE
, {RT
, RA
, RB
}},
5654 {"erativax", X(31,819), X_MASK
, PPCA2
, PPCNONE
, {RS
, RA0
, RB
}},
5656 {"lhzcix", X(31,821), X_MASK
, POWER6
, PPCNONE
, {RT
, RA0
, RB
}},
5658 {"dss", XDSS(31,822,0), XDSS_MASK
, PPCVEC
, PPCNONE
, {STRM
}},
5660 {"lfqux", X(31,823), X_MASK
, POWER2
, PPCNONE
, {FRT
, RA
, RB
}},
5662 {"srawi", XRC(31,824,0), X_MASK
, PPCCOM
|PPCVLE
, PPCNONE
, {RA
, RS
, SH
}},
5663 {"srai", XRC(31,824,0), X_MASK
, PWRCOM
, PPCNONE
, {RA
, RS
, SH
}},
5664 {"srawi.", XRC(31,824,1), X_MASK
, PPCCOM
|PPCVLE
, PPCNONE
, {RA
, RS
, SH
}},
5665 {"srai.", XRC(31,824,1), X_MASK
, PWRCOM
, PPCNONE
, {RA
, RS
, SH
}},
5667 {"sradi", XS(31,413,0), XS_MASK
, PPC64
|PPCVLE
, PPCNONE
, {RA
, RS
, SH6
}},
5668 {"sradi.", XS(31,413,1), XS_MASK
, PPC64
|PPCVLE
, PPCNONE
, {RA
, RS
, SH6
}},
5670 {"lvtlxl", X(31,837), X_MASK
, PPCVEC2
, PPCNONE
, {VD
, RA0
, RB
}},
5672 {"divo", XO(31,331,1,0), XO_MASK
, M601
, PPCNONE
, {RT
, RA
, RB
}},
5673 {"divo.", XO(31,331,1,1), XO_MASK
, M601
, PPCNONE
, {RT
, RA
, RB
}},
5675 {"lxvd2x", X(31,844), XX1_MASK
, PPCVSX
, PPCNONE
, {XT6
, RA0
, RB
}},
5676 {"lxvx", X(31,844), XX1_MASK
, PPCVSX
, PPCNONE
, {XT6
, RA0
, RB
}},
5678 {"tabortwci.", XRC(31,846,1), X_MASK
, PPCHTM
, PPCNONE
, {TO
, RA
, HTM_SI
}},
5680 {"tlbsrx.", XRC(31,850,1), XRT_MASK
, PPCA2
, PPCNONE
, {RA0
, RB
}},
5682 {"slbmfev", X(31,851), XRA_MASK
, PPC64
, PPCNONE
, {RT
, RB
}},
5684 {"lbzcix", X(31,853), X_MASK
, POWER6
, PPCNONE
, {RT
, RA0
, RB
}},
5686 {"eieio", X(31,854), 0xffffffff, PPC
, BOOKE
|PPCA2
|PPC476
, {0}},
5687 {"mbar", X(31,854), X_MASK
, BOOKE
|PPCA2
|PPC476
|PPCVLE
, PPCNONE
, {MO
}},
5688 {"eieio", XMBAR(31,854,1),0xffffffff, E500
, PPCNONE
, {0}},
5689 {"eieio", X(31,854), 0xffffffff, PPCA2
|PPC476
, PPCNONE
, {0}},
5691 {"lfiwax", X(31,855), X_MASK
, POWER6
|PPCA2
|PPC476
, PPCNONE
, {FRT
, RA0
, RB
}},
5693 {"lvswxl", X(31,869), X_MASK
, PPCVEC2
, PPCNONE
, {VD
, RA0
, RB
}},
5695 {"abso", XO(31,360,1,0), XORB_MASK
, M601
, PPCNONE
, {RT
, RA
}},
5696 {"abso.", XO(31,360,1,1), XORB_MASK
, M601
, PPCNONE
, {RT
, RA
}},
5698 {"divso", XO(31,363,1,0), XO_MASK
, M601
, PPCNONE
, {RT
, RA
, RB
}},
5699 {"divso.", XO(31,363,1,1), XO_MASK
, M601
, PPCNONE
, {RT
, RA
, RB
}},
5701 {"tabortdci.", XRC(31,878,1), X_MASK
, PPCHTM
, PPCNONE
, {TO
, RA
, HTM_SI
}},
5703 {"ldcix", X(31,885), X_MASK
, POWER6
, PPCNONE
, {RT
, RA0
, RB
}},
5705 {"lfiwzx", X(31,887), X_MASK
, POWER7
|PPCA2
, PPCNONE
, {FRT
, RA0
, RB
}},
5707 {"stvlxl", X(31,903), X_MASK
, CELL
, PPCNONE
, {VS
, RA0
, RB
}},
5708 {"stdfcmux", APU(31,903,0), APU_MASK
, PPC405
, PPCNONE
, {FCRT
, RA
, RB
}},
5710 {"divdeuo", XO(31,393,1,0), XO_MASK
, POWER7
|PPCA2
, PPCNONE
, {RT
, RA
, RB
}},
5711 {"divdeuo.", XO(31,393,1,1), XO_MASK
, POWER7
|PPCA2
, PPCNONE
, {RT
, RA
, RB
}},
5712 {"divweuo", XO(31,395,1,0), XO_MASK
, POWER7
|PPCA2
, PPCNONE
, {RT
, RA
, RB
}},
5713 {"divweuo.", XO(31,395,1,1), XO_MASK
, POWER7
|PPCA2
, PPCNONE
, {RT
, RA
, RB
}},
5715 {"stxvw4x", X(31,908), XX1_MASK
, PPCVSX
, PPCNONE
, {XS6
, RA0
, RB
}},
5717 {"tabort.", XRC(31,910,1), XRTRB_MASK
, PPCHTM
, PPCNONE
, {RA
}},
5719 {"tlbsx", XRC(31,914,0), X_MASK
, PPC403
|BOOKE
|PPCA2
|PPC476
, PPCNONE
, {RTO
, RA0
, RB
}},
5720 {"tlbsx.", XRC(31,914,1), X_MASK
, PPC403
|BOOKE
|PPCA2
|PPC476
, PPCNONE
, {RTO
, RA0
, RB
}},
5722 {"slbmfee", X(31,915), XRA_MASK
, PPC64
, PPCNONE
, {RT
, RB
}},
5724 {"stwcix", X(31,917), X_MASK
, POWER6
, PPCNONE
, {RS
, RA0
, RB
}},
5726 {"sthbrx", X(31,918), X_MASK
, COM
, PPCNONE
, {RS
, RA0
, RB
}},
5728 {"stfdpx", X(31,919), X_MASK
, POWER6
, POWER7
, {FRSp
, RA0
, RB
}},
5729 {"stfqx", X(31,919), X_MASK
, POWER2
, PPCNONE
, {FRS
, RA0
, RB
}},
5731 {"sraq", XRC(31,920,0), X_MASK
, M601
, PPCNONE
, {RA
, RS
, RB
}},
5732 {"sraq.", XRC(31,920,1), X_MASK
, M601
, PPCNONE
, {RA
, RS
, RB
}},
5734 {"srea", XRC(31,921,0), X_MASK
, M601
, PPCNONE
, {RA
, RS
, RB
}},
5735 {"srea.", XRC(31,921,1), X_MASK
, M601
, PPCNONE
, {RA
, RS
, RB
}},
5737 {"extsh", XRC(31,922,0), XRB_MASK
, PPCCOM
|PPCVLE
, PPCNONE
, {RA
, RS
}},
5738 {"exts", XRC(31,922,0), XRB_MASK
, PWRCOM
, PPCNONE
, {RA
, RS
}},
5739 {"extsh.", XRC(31,922,1), XRB_MASK
, PPCCOM
|PPCVLE
, PPCNONE
, {RA
, RS
}},
5740 {"exts.", XRC(31,922,1), XRB_MASK
, PWRCOM
, PPCNONE
, {RA
, RS
}},
5742 {"stfddx", X(31,931), X_MASK
, E500MC
, PPCNONE
, {FRS
, RA
, RB
}},
5744 {"stvfrxl", X(31,933), X_MASK
, PPCVEC2
, PPCNONE
, {VS
, RA0
, RB
}},
5746 {"wclrone", XOPL2(31,934,2),XRT_MASK
, PPCA2
, PPCNONE
, {RA0
, RB
}},
5747 {"wclrall", X(31,934), XRARB_MASK
, PPCA2
, PPCNONE
, {L
}},
5748 {"wclr", X(31,934), X_MASK
, PPCA2
, PPCNONE
, {L
, RA0
, RB
}},
5750 {"stvrxl", X(31,935), X_MASK
, CELL
, PPCNONE
, {VS
, RA0
, RB
}},
5752 {"divdeo", XO(31,425,1,0), XO_MASK
, POWER7
|PPCA2
, PPCNONE
, {RT
, RA
, RB
}},
5753 {"divdeo.", XO(31,425,1,1), XO_MASK
, POWER7
|PPCA2
, PPCNONE
, {RT
, RA
, RB
}},
5754 {"divweo", XO(31,427,1,0), XO_MASK
, POWER7
|PPCA2
, PPCNONE
, {RT
, RA
, RB
}},
5755 {"divweo.", XO(31,427,1,1), XO_MASK
, POWER7
|PPCA2
, PPCNONE
, {RT
, RA
, RB
}},
5757 {"treclaim.", XRC(31,942,1), XRTRB_MASK
, PPCHTM
, PPCNONE
, {RA
}},
5759 {"tlbrehi", XTLB(31,946,0), XTLB_MASK
, PPC403
, PPCA2
, {RT
, RA
}},
5760 {"tlbrelo", XTLB(31,946,1), XTLB_MASK
, PPC403
, PPCA2
, {RT
, RA
}},
5761 {"tlbre", X(31,946), X_MASK
, PPC403
|BOOKE
|PPCA2
|PPC476
, PPCNONE
, {RSO
, RAOPT
, SHO
}},
5763 {"sthcix", X(31,949), X_MASK
, POWER6
, PPCNONE
, {RS
, RA0
, RB
}},
5765 {"icswepx", XRC(31,950,0), X_MASK
, PPCA2
, PPCNONE
, {RS
, RA
, RB
}},
5766 {"icswepx.", XRC(31,950,1), X_MASK
, PPCA2
, PPCNONE
, {RS
, RA
, RB
}},
5768 {"stfqux", X(31,951), X_MASK
, POWER2
, PPCNONE
, {FRS
, RA
, RB
}},
5770 {"sraiq", XRC(31,952,0), X_MASK
, M601
, PPCNONE
, {RA
, RS
, SH
}},
5771 {"sraiq.", XRC(31,952,1), X_MASK
, M601
, PPCNONE
, {RA
, RS
, SH
}},
5773 {"extsb", XRC(31,954,0), XRB_MASK
, PPC
|PPCVLE
, PPCNONE
, {RA
, RS
}},
5774 {"extsb.", XRC(31,954,1), XRB_MASK
, PPC
|PPCVLE
, PPCNONE
, {RA
, RS
}},
5776 {"stvflxl", X(31,965), X_MASK
, PPCVEC2
, PPCNONE
, {VS
, RA0
, RB
}},
5778 {"iccci", X(31,966), XRT_MASK
, PPC403
|PPC440
|TITAN
|PPCA2
, PPCNONE
, {RAOPT
, RBOPT
}},
5779 {"ici", X(31,966), XRARB_MASK
, PPCA2
|PPC476
|PPCVLE
, PPCNONE
, {CT
}},
5781 {"divduo", XO(31,457,1,0), XO_MASK
, PPC64
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
5782 {"divduo.", XO(31,457,1,1), XO_MASK
, PPC64
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
5784 {"divwuo", XO(31,459,1,0), XO_MASK
, PPC
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
5785 {"divwuo.", XO(31,459,1,1), XO_MASK
, PPC
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
5787 {"stxvd2x", X(31,972), XX1_MASK
, PPCVSX
, PPCNONE
, {XS6
, RA0
, RB
}},
5788 {"stxvx", X(31,972), XX1_MASK
, PPCVSX
, PPCNONE
, {XS6
, RA0
, RB
}},
5790 {"tlbld", X(31,978), XRTRA_MASK
, PPC
, PPC403
|BOOKE
|PPCA2
|PPC476
, {RB
}},
5791 {"tlbwehi", XTLB(31,978,0), XTLB_MASK
, PPC403
, PPCNONE
, {RT
, RA
}},
5792 {"tlbwelo", XTLB(31,978,1), XTLB_MASK
, PPC403
, PPCNONE
, {RT
, RA
}},
5793 {"tlbwe", X(31,978), X_MASK
, PPC403
|BOOKE
|PPCA2
|PPC476
, PPCNONE
, {RSO
, RAOPT
, SHO
}},
5795 {"stbcix", X(31,981), X_MASK
, POWER6
, PPCNONE
, {RS
, RA0
, RB
}},
5797 {"icbi", X(31,982), XRT_MASK
, PPC
|PPCVLE
, PPCNONE
, {RA0
, RB
}},
5799 {"stfiwx", X(31,983), X_MASK
, PPC
, PPCEFS
, {FRS
, RA0
, RB
}},
5801 {"extsw", XRC(31,986,0), XRB_MASK
, PPC64
|PPCVLE
, PPCNONE
, {RA
, RS
}},
5802 {"extsw.", XRC(31,986,1), XRB_MASK
, PPC64
|PPCVLE
, PPCNONE
, {RA
, RS
}},
5804 {"icbiep", XRT(31,991,0), XRT_MASK
, E500MC
|PPCA2
|PPCVLE
, PPCNONE
, {RA0
, RB
}},
5806 {"stvswxl", X(31,997), X_MASK
, PPCVEC2
, PPCNONE
, {VS
, RA0
, RB
}},
5808 {"icread", X(31,998), XRT_MASK
, PPC403
|PPC440
|PPC476
|TITAN
|PPCVLE
, PPCNONE
, {RA0
, RB
}},
5810 {"nabso", XO(31,488,1,0), XORB_MASK
, M601
, PPCNONE
, {RT
, RA
}},
5811 {"nabso.", XO(31,488,1,1), XORB_MASK
, M601
, PPCNONE
, {RT
, RA
}},
5813 {"divdo", XO(31,489,1,0), XO_MASK
, PPC64
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
5814 {"divdo.", XO(31,489,1,1), XO_MASK
, PPC64
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
5816 {"divwo", XO(31,491,1,0), XO_MASK
, PPC
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
5817 {"divwo.", XO(31,491,1,1), XO_MASK
, PPC
|PPCVLE
, PPCNONE
, {RT
, RA
, RB
}},
5819 {"trechkpt.", XRC(31,1006,1), XRTRARB_MASK
,PPCHTM
, PPCNONE
, {0}},
5821 {"tlbli", X(31,1010), XRTRA_MASK
, PPC
, TITAN
, {RB
}},
5823 {"stdcix", X(31,1013), X_MASK
, POWER6
, PPCNONE
, {RS
, RA0
, RB
}},
5825 {"dcbz", X(31,1014), XRT_MASK
, PPC
|PPCVLE
, PPCNONE
, {RA0
, RB
}},
5826 {"dclz", X(31,1014), XRT_MASK
, PPC
, PPCNONE
, {RA0
, RB
}},
5828 {"dcbzep", XRT(31,1023,0), XRT_MASK
, E500MC
|PPCA2
|PPCVLE
, PPCNONE
, {RA0
, RB
}},
5830 {"dcbzl", XOPL(31,1014,1), XRT_MASK
, POWER4
|E500MC
, PPC476
, {RA0
, RB
}},
5832 {"cctpl", 0x7c210b78, 0xffffffff, CELL
, PPCNONE
, {0}},
5833 {"cctpm", 0x7c421378, 0xffffffff, CELL
, PPCNONE
, {0}},
5834 {"cctph", 0x7c631b78, 0xffffffff, CELL
, PPCNONE
, {0}},
5836 {"dstt", XDSS(31,342,1), XDSS_MASK
, PPCVEC
, PPCNONE
, {RA
, RB
, STRM
}},
5837 {"dststt", XDSS(31,374,1), XDSS_MASK
, PPCVEC
, PPCNONE
, {RA
, RB
, STRM
}},
5838 {"dssall", XDSS(31,822,1), XDSS_MASK
, PPCVEC
, PPCNONE
, {0}},
5840 {"db8cyc", 0x7f9ce378, 0xffffffff, CELL
, PPCNONE
, {0}},
5841 {"db10cyc", 0x7fbdeb78, 0xffffffff, CELL
, PPCNONE
, {0}},
5842 {"db12cyc", 0x7fdef378, 0xffffffff, CELL
, PPCNONE
, {0}},
5843 {"db16cyc", 0x7ffffb78, 0xffffffff, CELL
, PPCNONE
, {0}},
5845 {"lwz", OP(32), OP_MASK
, PPCCOM
, PPCNONE
, {RT
, D
, RA0
}},
5846 {"l", OP(32), OP_MASK
, PWRCOM
, PPCNONE
, {RT
, D
, RA0
}},
5848 {"lwzu", OP(33), OP_MASK
, PPCCOM
, PPCNONE
, {RT
, D
, RAL
}},
5849 {"lu", OP(33), OP_MASK
, PWRCOM
, PPCNONE
, {RT
, D
, RA0
}},
5851 {"lbz", OP(34), OP_MASK
, COM
, PPCNONE
, {RT
, D
, RA0
}},
5853 {"lbzu", OP(35), OP_MASK
, COM
, PPCNONE
, {RT
, D
, RAL
}},
5855 {"stw", OP(36), OP_MASK
, PPCCOM
, PPCNONE
, {RS
, D
, RA0
}},
5856 {"st", OP(36), OP_MASK
, PWRCOM
, PPCNONE
, {RS
, D
, RA0
}},
5858 {"stwu", OP(37), OP_MASK
, PPCCOM
, PPCNONE
, {RS
, D
, RAS
}},
5859 {"stu", OP(37), OP_MASK
, PWRCOM
, PPCNONE
, {RS
, D
, RA0
}},
5861 {"stb", OP(38), OP_MASK
, COM
, PPCNONE
, {RS
, D
, RA0
}},
5863 {"stbu", OP(39), OP_MASK
, COM
, PPCNONE
, {RS
, D
, RAS
}},
5865 {"lhz", OP(40), OP_MASK
, COM
, PPCNONE
, {RT
, D
, RA0
}},
5867 {"lhzu", OP(41), OP_MASK
, COM
, PPCNONE
, {RT
, D
, RAL
}},
5869 {"lha", OP(42), OP_MASK
, COM
, PPCNONE
, {RT
, D
, RA0
}},
5871 {"lhau", OP(43), OP_MASK
, COM
, PPCNONE
, {RT
, D
, RAL
}},
5873 {"sth", OP(44), OP_MASK
, COM
, PPCNONE
, {RS
, D
, RA0
}},
5875 {"sthu", OP(45), OP_MASK
, COM
, PPCNONE
, {RS
, D
, RAS
}},
5877 {"lmw", OP(46), OP_MASK
, PPCCOM
, PPCNONE
, {RT
, D
, RAM
}},
5878 {"lm", OP(46), OP_MASK
, PWRCOM
, PPCNONE
, {RT
, D
, RA0
}},
5880 {"stmw", OP(47), OP_MASK
, PPCCOM
, PPCNONE
, {RS
, D
, RA0
}},
5881 {"stm", OP(47), OP_MASK
, PWRCOM
, PPCNONE
, {RS
, D
, RA0
}},
5883 {"lfs", OP(48), OP_MASK
, COM
, PPCEFS
, {FRT
, D
, RA0
}},
5885 {"lfsu", OP(49), OP_MASK
, COM
, PPCEFS
, {FRT
, D
, RAS
}},
5887 {"lfd", OP(50), OP_MASK
, COM
, PPCEFS
, {FRT
, D
, RA0
}},
5889 {"lfdu", OP(51), OP_MASK
, COM
, PPCEFS
, {FRT
, D
, RAS
}},
5891 {"stfs", OP(52), OP_MASK
, COM
, PPCEFS
, {FRS
, D
, RA0
}},
5893 {"stfsu", OP(53), OP_MASK
, COM
, PPCEFS
, {FRS
, D
, RAS
}},
5895 {"stfd", OP(54), OP_MASK
, COM
, PPCEFS
, {FRS
, D
, RA0
}},
5897 {"stfdu", OP(55), OP_MASK
, COM
, PPCEFS
, {FRS
, D
, RAS
}},
5899 {"lq", OP(56), OP_MASK
, POWER4
, PPC476
, {RTQ
, DQ
, RAQ
}},
5900 {"psq_l", OP(56), OP_MASK
, PPCPS
, PPCNONE
, {FRT
,PSD
,RA
,PSW
,PSQ
}},
5901 {"lfq", OP(56), OP_MASK
, POWER2
, PPCNONE
, {FRT
, D
, RA0
}},
5903 {"lfdp", OP(57), OP_MASK
, POWER6
, POWER7
, {FRTp
, DS
, RA0
}},
5904 {"psq_lu", OP(57), OP_MASK
, PPCPS
, PPCNONE
, {FRT
,PSD
,RA
,PSW
,PSQ
}},
5905 {"lfqu", OP(57), OP_MASK
, POWER2
, PPCNONE
, {FRT
, D
, RA0
}},
5907 {"ld", DSO(58,0), DS_MASK
, PPC64
, PPCNONE
, {RT
, DS
, RA0
}},
5908 {"ldu", DSO(58,1), DS_MASK
, PPC64
, PPCNONE
, {RT
, DS
, RAL
}},
5909 {"lwa", DSO(58,2), DS_MASK
, PPC64
, PPCNONE
, {RT
, DS
, RA0
}},
5911 {"dadd", XRC(59,2,0), X_MASK
, POWER6
, PPCNONE
, {FRT
, FRA
, FRB
}},
5912 {"dadd.", XRC(59,2,1), X_MASK
, POWER6
, PPCNONE
, {FRT
, FRA
, FRB
}},
5914 {"dqua", ZRC(59,3,0), Z2_MASK
, POWER6
, PPCNONE
, {FRT
,FRA
,FRB
,RMC
}},
5915 {"dqua.", ZRC(59,3,1), Z2_MASK
, POWER6
, PPCNONE
, {FRT
,FRA
,FRB
,RMC
}},
5917 {"fdivs", A(59,18,0), AFRC_MASK
, PPC
, PPCEFS
, {FRT
, FRA
, FRB
}},
5918 {"fdivs.", A(59,18,1), AFRC_MASK
, PPC
, PPCEFS
, {FRT
, FRA
, FRB
}},
5920 {"fsubs", A(59,20,0), AFRC_MASK
, PPC
, PPCEFS
, {FRT
, FRA
, FRB
}},
5921 {"fsubs.", A(59,20,1), AFRC_MASK
, PPC
, PPCEFS
, {FRT
, FRA
, FRB
}},
5923 {"fadds", A(59,21,0), AFRC_MASK
, PPC
, PPCEFS
, {FRT
, FRA
, FRB
}},
5924 {"fadds.", A(59,21,1), AFRC_MASK
, PPC
, PPCEFS
, {FRT
, FRA
, FRB
}},
5926 {"fsqrts", A(59,22,0), AFRAFRC_MASK
, PPC
, TITAN
, {FRT
, FRB
}},
5927 {"fsqrts.", A(59,22,1), AFRAFRC_MASK
, PPC
, TITAN
, {FRT
, FRB
}},
5929 {"fres", A(59,24,0), AFRAFRC_MASK
, POWER7
, PPCNONE
, {FRT
, FRB
}},
5930 {"fres", A(59,24,0), AFRALFRC_MASK
, PPC
, POWER7
, {FRT
, FRB
, A_L
}},
5931 {"fres.", A(59,24,1), AFRAFRC_MASK
, POWER7
, PPCNONE
, {FRT
, FRB
}},
5932 {"fres.", A(59,24,1), AFRALFRC_MASK
, PPC
, POWER7
, {FRT
, FRB
, A_L
}},
5934 {"fmuls", A(59,25,0), AFRB_MASK
, PPC
, PPCEFS
, {FRT
, FRA
, FRC
}},
5935 {"fmuls.", A(59,25,1), AFRB_MASK
, PPC
, PPCEFS
, {FRT
, FRA
, FRC
}},
5937 {"frsqrtes", A(59,26,0), AFRAFRC_MASK
, POWER7
, PPCNONE
, {FRT
, FRB
}},
5938 {"frsqrtes", A(59,26,0), AFRALFRC_MASK
, POWER5
, POWER7
, {FRT
, FRB
, A_L
}},
5939 {"frsqrtes.", A(59,26,1), AFRAFRC_MASK
, POWER7
, PPCNONE
, {FRT
, FRB
}},
5940 {"frsqrtes.", A(59,26,1), AFRALFRC_MASK
, POWER5
, POWER7
, {FRT
, FRB
, A_L
}},
5942 {"fmsubs", A(59,28,0), A_MASK
, PPC
, PPCEFS
, {FRT
, FRA
, FRC
, FRB
}},
5943 {"fmsubs.", A(59,28,1), A_MASK
, PPC
, PPCEFS
, {FRT
, FRA
, FRC
, FRB
}},
5945 {"fmadds", A(59,29,0), A_MASK
, PPC
, PPCEFS
, {FRT
, FRA
, FRC
, FRB
}},
5946 {"fmadds.", A(59,29,1), A_MASK
, PPC
, PPCEFS
, {FRT
, FRA
, FRC
, FRB
}},
5948 {"fnmsubs", A(59,30,0), A_MASK
, PPC
, PPCEFS
, {FRT
, FRA
, FRC
, FRB
}},
5949 {"fnmsubs.", A(59,30,1), A_MASK
, PPC
, PPCEFS
, {FRT
, FRA
, FRC
, FRB
}},
5951 {"fnmadds", A(59,31,0), A_MASK
, PPC
, PPCEFS
, {FRT
, FRA
, FRC
, FRB
}},
5952 {"fnmadds.", A(59,31,1), A_MASK
, PPC
, PPCEFS
, {FRT
, FRA
, FRC
, FRB
}},
5954 {"dmul", XRC(59,34,0), X_MASK
, POWER6
, PPCNONE
, {FRT
, FRA
, FRB
}},
5955 {"dmul.", XRC(59,34,1), X_MASK
, POWER6
, PPCNONE
, {FRT
, FRA
, FRB
}},
5957 {"drrnd", ZRC(59,35,0), Z2_MASK
, POWER6
, PPCNONE
, {FRT
, FRA
, FRB
, RMC
}},
5958 {"drrnd.", ZRC(59,35,1), Z2_MASK
, POWER6
, PPCNONE
, {FRT
, FRA
, FRB
, RMC
}},
5960 {"dscli", ZRC(59,66,0), Z_MASK
, POWER6
, PPCNONE
, {FRT
, FRA
, SH16
}},
5961 {"dscli.", ZRC(59,66,1), Z_MASK
, POWER6
, PPCNONE
, {FRT
, FRA
, SH16
}},
5963 {"dquai", ZRC(59,67,0), Z2_MASK
, POWER6
, PPCNONE
, {TE
, FRT
,FRB
,RMC
}},
5964 {"dquai.", ZRC(59,67,1), Z2_MASK
, POWER6
, PPCNONE
, {TE
, FRT
,FRB
,RMC
}},
5966 {"dscri", ZRC(59,98,0), Z_MASK
, POWER6
, PPCNONE
, {FRT
, FRA
, SH16
}},
5967 {"dscri.", ZRC(59,98,1), Z_MASK
, POWER6
, PPCNONE
, {FRT
, FRA
, SH16
}},
5969 {"drintx", ZRC(59,99,0), Z2_MASK
, POWER6
, PPCNONE
, {R
, FRT
, FRB
, RMC
}},
5970 {"drintx.", ZRC(59,99,1), Z2_MASK
, POWER6
, PPCNONE
, {R
, FRT
, FRB
, RMC
}},
5972 {"dcmpo", X(59,130), X_MASK
, POWER6
, PPCNONE
, {BF
, FRA
, FRB
}},
5974 {"dtstex", X(59,162), X_MASK
, POWER6
, PPCNONE
, {BF
, FRA
, FRB
}},
5975 {"dtstdc", Z(59,194), Z_MASK
, POWER6
, PPCNONE
, {BF
, FRA
, DCM
}},
5976 {"dtstdg", Z(59,226), Z_MASK
, POWER6
, PPCNONE
, {BF
, FRA
, DGM
}},
5978 {"drintn", ZRC(59,227,0), Z2_MASK
, POWER6
, PPCNONE
, {R
, FRT
, FRB
, RMC
}},
5979 {"drintn.", ZRC(59,227,1), Z2_MASK
, POWER6
, PPCNONE
, {R
, FRT
, FRB
, RMC
}},
5981 {"dctdp", XRC(59,258,0), X_MASK
, POWER6
, PPCNONE
, {FRT
, FRB
}},
5982 {"dctdp.", XRC(59,258,1), X_MASK
, POWER6
, PPCNONE
, {FRT
, FRB
}},
5984 {"dctfix", XRC(59,290,0), X_MASK
, POWER6
, PPCNONE
, {FRT
, FRB
}},
5985 {"dctfix.", XRC(59,290,1), X_MASK
, POWER6
, PPCNONE
, {FRT
, FRB
}},
5987 {"ddedpd", XRC(59,322,0), X_MASK
, POWER6
, PPCNONE
, {SP
, FRT
, FRB
}},
5988 {"ddedpd.", XRC(59,322,1), X_MASK
, POWER6
, PPCNONE
, {SP
, FRT
, FRB
}},
5990 {"dxex", XRC(59,354,0), X_MASK
, POWER6
, PPCNONE
, {FRT
, FRB
}},
5991 {"dxex.", XRC(59,354,1), X_MASK
, POWER6
, PPCNONE
, {FRT
, FRB
}},
5993 {"dsub", XRC(59,514,0), X_MASK
, POWER6
, PPCNONE
, {FRT
, FRA
, FRB
}},
5994 {"dsub.", XRC(59,514,1), X_MASK
, POWER6
, PPCNONE
, {FRT
, FRA
, FRB
}},
5996 {"ddiv", XRC(59,546,0), X_MASK
, POWER6
, PPCNONE
, {FRT
, FRA
, FRB
}},
5997 {"ddiv.", XRC(59,546,1), X_MASK
, POWER6
, PPCNONE
, {FRT
, FRA
, FRB
}},
5999 {"dcmpu", X(59,642), X_MASK
, POWER6
, PPCNONE
, {BF
, FRA
, FRB
}},
6001 {"dtstsf", X(59,674), X_MASK
, POWER6
, PPCNONE
, {BF
, FRA
, FRB
}},
6003 {"drsp", XRC(59,770,0), X_MASK
, POWER6
, PPCNONE
, {FRT
, FRB
}},
6004 {"drsp.", XRC(59,770,1), X_MASK
, POWER6
, PPCNONE
, {FRT
, FRB
}},
6006 {"dcffix", XRC(59,802,0), X_MASK
|FRA_MASK
, POWER7
, PPCNONE
, {FRT
, FRB
}},
6007 {"dcffix.", XRC(59,802,1), X_MASK
|FRA_MASK
, POWER7
, PPCNONE
, {FRT
, FRB
}},
6009 {"denbcd", XRC(59,834,0), X_MASK
, POWER6
, PPCNONE
, {S
, FRT
, FRB
}},
6010 {"denbcd.", XRC(59,834,1), X_MASK
, POWER6
, PPCNONE
, {S
, FRT
, FRB
}},
6012 {"fcfids", XRC(59,846,0), XRA_MASK
, POWER7
|PPCA2
, PPCNONE
, {FRT
, FRB
}},
6013 {"fcfids.", XRC(59,846,1), XRA_MASK
, POWER7
|PPCA2
, PPCNONE
, {FRT
, FRB
}},
6015 {"diex", XRC(59,866,0), X_MASK
, POWER6
, PPCNONE
, {FRT
, FRA
, FRB
}},
6016 {"diex.", XRC(59,866,1), X_MASK
, POWER6
, PPCNONE
, {FRT
, FRA
, FRB
}},
6018 {"fcfidus", XRC(59,974,0), XRA_MASK
, POWER7
|PPCA2
, PPCNONE
, {FRT
, FRB
}},
6019 {"fcfidus.", XRC(59,974,1), XRA_MASK
, POWER7
|PPCA2
, PPCNONE
, {FRT
, FRB
}},
6021 {"xsaddsp", XX3(60,0), XX3_MASK
, PPCVSX2
, PPCNONE
, {XT6
, XA6
, XB6
}},
6022 {"xsmaddasp", XX3(60,1), XX3_MASK
, PPCVSX2
, PPCNONE
, {XT6
, XA6
, XB6
}},
6023 {"xxsldwi", XX3(60,2), XX3SHW_MASK
, PPCVSX
, PPCNONE
, {XT6
, XA6
, XB6
, SHW
}},
6024 {"xxsel", XX4(60,3), XX4_MASK
, PPCVSX
, PPCNONE
, {XT6
, XA6
, XB6
, XC6
}},
6025 {"xssubsp", XX3(60,8), XX3_MASK
, PPCVSX2
, PPCNONE
, {XT6
, XA6
, XB6
}},
6026 {"xsmaddmsp", XX3(60,9), XX3_MASK
, PPCVSX2
, PPCNONE
, {XT6
, XA6
, XB6
}},
6027 {"xxspltd", XX3(60,10), XX3DM_MASK
, PPCVSX
, PPCNONE
, {XT6
, XA6
, XB6S
, DMEX
}},
6028 {"xxmrghd", XX3(60,10), XX3_MASK
, PPCVSX
, PPCNONE
, {XT6
, XA6
, XB6
}},
6029 {"xxswapd", XX3(60,10)|(2<<8), XX3_MASK
, PPCVSX
, PPCNONE
, {XT6
, XA6
, XB6S
}},
6030 {"xxmrgld", XX3(60,10)|(3<<8), XX3_MASK
, PPCVSX
, PPCNONE
, {XT6
, XA6
, XB6
}},
6031 {"xxpermdi", XX3(60,10), XX3DM_MASK
, PPCVSX
, PPCNONE
, {XT6
, XA6
, XB6
, DM
}},
6032 {"xsrsqrtesp", XX2(60,10), XX2_MASK
, PPCVSX2
, PPCNONE
, {XT6
, XB6
}},
6033 {"xssqrtsp", XX2(60,11), XX2_MASK
, PPCVSX2
, PPCNONE
, {XT6
, XB6
}},
6034 {"xsmulsp", XX3(60,16), XX3_MASK
, PPCVSX2
, PPCNONE
, {XT6
, XA6
, XB6
}},
6035 {"xsmsubasp", XX3(60,17), XX3_MASK
, PPCVSX2
, PPCNONE
, {XT6
, XA6
, XB6
}},
6036 {"xxmrghw", XX3(60,18), XX3_MASK
, PPCVSX
, PPCNONE
, {XT6
, XA6
, XB6
}},
6037 {"xsdivsp", XX3(60,24), XX3_MASK
, PPCVSX2
, PPCNONE
, {XT6
, XA6
, XB6
}},
6038 {"xsmsubmsp", XX3(60,25), XX3_MASK
, PPCVSX2
, PPCNONE
, {XT6
, XA6
, XB6
}},
6039 {"xsresp", XX2(60,26), XX2_MASK
, PPCVSX2
, PPCNONE
, {XT6
, XB6
}},
6040 {"xsadddp", XX3(60,32), XX3_MASK
, PPCVSX
, PPCNONE
, {XT6
, XA6
, XB6
}},
6041 {"xsmaddadp", XX3(60,33), XX3_MASK
, PPCVSX
, PPCNONE
, {XT6
, XA6
, XB6
}},
6042 {"xscmpudp", XX3(60,35), XX3BF_MASK
, PPCVSX
, PPCNONE
, {BF
, XA6
, XB6
}},
6043 {"xssubdp", XX3(60,40), XX3_MASK
, PPCVSX
, PPCNONE
, {XT6
, XA6
, XB6
}},
6044 {"xsmaddmdp", XX3(60,41), XX3_MASK
, PPCVSX
, PPCNONE
, {XT6
, XA6
, XB6
}},
6045 {"xscmpodp", XX3(60,43), XX3BF_MASK
, PPCVSX
, PPCNONE
, {BF
, XA6
, XB6
}},
6046 {"xsmuldp", XX3(60,48), XX3_MASK
, PPCVSX
, PPCNONE
, {XT6
, XA6
, XB6
}},
6047 {"xsmsubadp", XX3(60,49), XX3_MASK
, PPCVSX
, PPCNONE
, {XT6
, XA6
, XB6
}},
6048 {"xxmrglw", XX3(60,50), XX3_MASK
, PPCVSX
, PPCNONE
, {XT6
, XA6
, XB6
}},
6049 {"xsdivdp", XX3(60,56), XX3_MASK
, PPCVSX
, PPCNONE
, {XT6
, XA6
, XB6
}},
6050 {"xsmsubmdp", XX3(60,57), XX3_MASK
, PPCVSX
, PPCNONE
, {XT6
, XA6
, XB6
}},
6051 {"xstdivdp", XX3(60,61), XX3BF_MASK
, PPCVSX
, PPCNONE
, {BF
, XA6
, XB6
}},
6052 {"xvaddsp", XX3(60,64), XX3_MASK
, PPCVSX
, PPCNONE
, {XT6
, XA6
, XB6
}},
6053 {"xvmaddasp", XX3(60,65), XX3_MASK
, PPCVSX
, PPCNONE
, {XT6
, XA6
, XB6
}},
6054 {"xvcmpeqsp", XX3RC(60,67,0), XX3_MASK
, PPCVSX
, PPCNONE
, {XT6
, XA6
, XB6
}},
6055 {"xvcmpeqsp.", XX3RC(60,67,1), XX3_MASK
, PPCVSX
, PPCNONE
, {XT6
, XA6
, XB6
}},
6056 {"xvsubsp", XX3(60,72), XX3_MASK
, PPCVSX
, PPCNONE
, {XT6
, XA6
, XB6
}},
6057 {"xscvdpuxws", XX2(60,72), XX2_MASK
, PPCVSX
, PPCNONE
, {XT6
, XB6
}},
6058 {"xvmaddmsp", XX3(60,73), XX3_MASK
, PPCVSX
, PPCNONE
, {XT6
, XA6
, XB6
}},
6059 {"xsrdpi", XX2(60,73), XX2_MASK
, PPCVSX
, PPCNONE
, {XT6
, XB6
}},
6060 {"xsrsqrtedp", XX2(60,74), XX2_MASK
, PPCVSX
, PPCNONE
, {XT6
, XB6
}},
6061 {"xssqrtdp", XX2(60,75), XX2_MASK
, PPCVSX
, PPCNONE
, {XT6
, XB6
}},
6062 {"xvcmpgtsp", XX3RC(60,75,0), XX3_MASK
, PPCVSX
, PPCNONE
, {XT6
, XA6
, XB6
}},
6063 {"xvcmpgtsp.", XX3RC(60,75,1), XX3_MASK
, PPCVSX
, PPCNONE
, {XT6
, XA6
, XB6
}},
6064 {"xvmulsp", XX3(60,80), XX3_MASK
, PPCVSX
, PPCNONE
, {XT6
, XA6
, XB6
}},
6065 {"xvmsubasp", XX3(60,81), XX3_MASK
, PPCVSX
, PPCNONE
, {XT6
, XA6
, XB6
}},
6066 {"xvcmpgesp", XX3RC(60,83,0), XX3_MASK
, PPCVSX
, PPCNONE
, {XT6
, XA6
, XB6
}},
6067 {"xvcmpgesp.", XX3RC(60,83,1), XX3_MASK
, PPCVSX
, PPCNONE
, {XT6
, XA6
, XB6
}},
6068 {"xvdivsp", XX3(60,88), XX3_MASK
, PPCVSX
, PPCNONE
, {XT6
, XA6
, XB6
}},
6069 {"xscvdpsxws", XX2(60,88), XX2_MASK
, PPCVSX
, PPCNONE
, {XT6
, XB6
}},
6070 {"xvmsubmsp", XX3(60,89), XX3_MASK
, PPCVSX
, PPCNONE
, {XT6
, XA6
, XB6
}},
6071 {"xsrdpiz", XX2(60,89), XX2_MASK
, PPCVSX
, PPCNONE
, {XT6
, XB6
}},
6072 {"xsredp", XX2(60,90), XX2_MASK
, PPCVSX
, PPCNONE
, {XT6
, XB6
}},
6073 {"xvtdivsp", XX3(60,93), XX3BF_MASK
, PPCVSX
, PPCNONE
, {BF
, XA6
, XB6
}},
6074 {"xvadddp", XX3(60,96), XX3_MASK
, PPCVSX
, PPCNONE
, {XT6
, XA6
, XB6
}},
6075 {"xvmaddadp", XX3(60,97), XX3_MASK
, PPCVSX
, PPCNONE
, {XT6
, XA6
, XB6
}},
6076 {"xvcmpeqdp", XX3RC(60,99,0), XX3_MASK
, PPCVSX
, PPCNONE
, {XT6
, XA6
, XB6
}},
6077 {"xvcmpeqdp.", XX3RC(60,99,1), XX3_MASK
, PPCVSX
, PPCNONE
, {XT6
, XA6
, XB6
}},
6078 {"xvsubdp", XX3(60,104), XX3_MASK
, PPCVSX
, PPCNONE
, {XT6
, XA6
, XB6
}},
6079 {"xvmaddmdp", XX3(60,105), XX3_MASK
, PPCVSX
, PPCNONE
, {XT6
, XA6
, XB6
}},
6080 {"xsrdpip", XX2(60,105), XX2_MASK
, PPCVSX
, PPCNONE
, {XT6
, XB6
}},
6081 {"xstsqrtdp", XX2(60,106), XX2BF_MASK
, PPCVSX
, PPCNONE
, {BF
, XB6
}},
6082 {"xsrdpic", XX2(60,107), XX2_MASK
, PPCVSX
, PPCNONE
, {XT6
, XB6
}},
6083 {"xvcmpgtdp", XX3RC(60,107,0), XX3_MASK
, PPCVSX
, PPCNONE
, {XT6
, XA6
, XB6
}},
6084 {"xvcmpgtdp.", XX3RC(60,107,1), XX3_MASK
, PPCVSX
, PPCNONE
, {XT6
, XA6
, XB6
}},
6085 {"xvmuldp", XX3(60,112), XX3_MASK
, PPCVSX
, PPCNONE
, {XT6
, XA6
, XB6
}},
6086 {"xvmsubadp", XX3(60,113), XX3_MASK
, PPCVSX
, PPCNONE
, {XT6
, XA6
, XB6
}},
6087 {"xvcmpgedp", XX3RC(60,115,0), XX3_MASK
, PPCVSX
, PPCNONE
, {XT6
, XA6
, XB6
}},
6088 {"xvcmpgedp.", XX3RC(60,115,1), XX3_MASK
, PPCVSX
, PPCNONE
, {XT6
, XA6
, XB6
}},
6089 {"xvdivdp", XX3(60,120), XX3_MASK
, PPCVSX
, PPCNONE
, {XT6
, XA6
, XB6
}},
6090 {"xvmsubmdp", XX3(60,121), XX3_MASK
, PPCVSX
, PPCNONE
, {XT6
, XA6
, XB6
}},
6091 {"xsrdpim", XX2(60,121), XX2_MASK
, PPCVSX
, PPCNONE
, {XT6
, XB6
}},
6092 {"xvtdivdp", XX3(60,125), XX3BF_MASK
, PPCVSX
, PPCNONE
, {BF
, XA6
, XB6
}},
6093 {"xsnmaddasp", XX3(60,129), XX3_MASK
, PPCVSX2
, PPCNONE
, {XT6
, XA6
, XB6
}},
6094 {"xxland", XX3(60,130), XX3_MASK
, PPCVSX
, PPCNONE
, {XT6
, XA6
, XB6
}},
6095 {"xvcvspuxws", XX2(60,136), XX2_MASK
, PPCVSX
, PPCNONE
, {XT6
, XB6
}},
6096 {"xsnmaddmsp", XX3(60,137), XX3_MASK
, PPCVSX2
, PPCNONE
, {XT6
, XA6
, XB6
}},
6097 {"xvrspi", XX2(60,137), XX2_MASK
, PPCVSX
, PPCNONE
, {XT6
, XB6
}},
6098 {"xxlandc", XX3(60,138), XX3_MASK
, PPCVSX
, PPCNONE
, {XT6
, XA6
, XB6
}},
6099 {"xvrsqrtesp", XX2(60,138), XX2_MASK
, PPCVSX
, PPCNONE
, {XT6
, XB6
}},
6100 {"xvsqrtsp", XX2(60,139), XX2_MASK
, PPCVSX
, PPCNONE
, {XT6
, XB6
}},
6101 {"xsnmsubasp", XX3(60,145), XX3_MASK
, PPCVSX2
, PPCNONE
, {XT6
, XA6
, XB6
}},
6102 {"xxlor", XX3(60,146), XX3_MASK
, PPCVSX
, PPCNONE
, {XT6
, XA6
, XB6
}},
6103 {"xvcvspsxws", XX2(60,152), XX2_MASK
, PPCVSX
, PPCNONE
, {XT6
, XB6
}},
6104 {"xsnmsubmsp", XX3(60,153), XX3_MASK
, PPCVSX2
, PPCNONE
, {XT6
, XA6
, XB6
}},
6105 {"xvrspiz", XX2(60,153), XX2_MASK
, PPCVSX
, PPCNONE
, {XT6
, XB6
}},
6106 {"xxlxor", XX3(60,154), XX3_MASK
, PPCVSX
, PPCNONE
, {XT6
, XA6
, XB6
}},
6107 {"xvresp", XX2(60,154), XX2_MASK
, PPCVSX
, PPCNONE
, {XT6
, XB6
}},
6108 {"xsmaxdp", XX3(60,160), XX3_MASK
, PPCVSX
, PPCNONE
, {XT6
, XA6
, XB6
}},
6109 {"xsnmaddadp", XX3(60,161), XX3_MASK
, PPCVSX
, PPCNONE
, {XT6
, XA6
, XB6
}},
6110 {"xxlnor", XX3(60,162), XX3_MASK
, PPCVSX
, PPCNONE
, {XT6
, XA6
, XB6
}},
6111 {"xxspltw", XX2(60,164), XX2UIM_MASK
, PPCVSX
, PPCNONE
, {XT6
, XB6
, UIM
}},
6112 {"xsmindp", XX3(60,168), XX3_MASK
, PPCVSX
, PPCNONE
, {XT6
, XA6
, XB6
}},
6113 {"xvcvuxwsp", XX2(60,168), XX2_MASK
, PPCVSX
, PPCNONE
, {XT6
, XB6
}},
6114 {"xsnmaddmdp", XX3(60,169), XX3_MASK
, PPCVSX
, PPCNONE
, {XT6
, XA6
, XB6
}},
6115 {"xvrspip", XX2(60,169), XX2_MASK
, PPCVSX
, PPCNONE
, {XT6
, XB6
}},
6116 {"xvtsqrtsp", XX2(60,170), XX2BF_MASK
, PPCVSX
, PPCNONE
, {BF
, XB6
}},
6117 {"xxlorc", XX3(60,170), XX3_MASK
, PPCVSX2
, PPCNONE
, {XT6
, XA6
, XB6
}},
6118 {"xvrspic", XX2(60,171), XX2_MASK
, PPCVSX
, PPCNONE
, {XT6
, XB6
}},
6119 {"xscpsgndp", XX3(60,176), XX3_MASK
, PPCVSX
, PPCNONE
, {XT6
, XA6
, XB6
}},
6120 {"xsnmsubadp", XX3(60,177), XX3_MASK
, PPCVSX
, PPCNONE
, {XT6
, XA6
, XB6
}},
6121 {"xxlnand", XX3(60,178), XX3_MASK
, PPCVSX2
, PPCNONE
, {XT6
, XA6
, XB6
}},
6122 {"xvcvsxwsp", XX2(60,184), XX2_MASK
, PPCVSX
, PPCNONE
, {XT6
, XB6
}},
6123 {"xsnmsubmdp", XX3(60,185), XX3_MASK
, PPCVSX
, PPCNONE
, {XT6
, XA6
, XB6
}},
6124 {"xvrspim", XX2(60,185), XX2_MASK
, PPCVSX
, PPCNONE
, {XT6
, XB6
}},
6125 {"xxleqv", XX3(60,186), XX3_MASK
, PPCVSX2
, PPCNONE
, {XT6
, XA6
, XB6
}},
6126 {"xvmaxsp", XX3(60,192), XX3_MASK
, PPCVSX
, PPCNONE
, {XT6
, XA6
, XB6
}},
6127 {"xvnmaddasp", XX3(60,193), XX3_MASK
, PPCVSX
, PPCNONE
, {XT6
, XA6
, XB6
}},
6128 {"xvminsp", XX3(60,200), XX3_MASK
, PPCVSX
, PPCNONE
, {XT6
, XA6
, XB6
}},
6129 {"xvcvdpuxws", XX2(60,200), XX2_MASK
, PPCVSX
, PPCNONE
, {XT6
, XB6
}},
6130 {"xvnmaddmsp", XX3(60,201), XX3_MASK
, PPCVSX
, PPCNONE
, {XT6
, XA6
, XB6
}},
6131 {"xvrdpi", XX2(60,201), XX2_MASK
, PPCVSX
, PPCNONE
, {XT6
, XB6
}},
6132 {"xvrsqrtedp", XX2(60,202), XX2_MASK
, PPCVSX
, PPCNONE
, {XT6
, XB6
}},
6133 {"xvsqrtdp", XX2(60,203), XX2_MASK
, PPCVSX
, PPCNONE
, {XT6
, XB6
}},
6134 {"xvmovsp", XX3(60,208), XX3_MASK
, PPCVSX
, PPCNONE
, {XT6
, XA6
, XB6S
}},
6135 {"xvcpsgnsp", XX3(60,208), XX3_MASK
, PPCVSX
, PPCNONE
, {XT6
, XA6
, XB6
}},
6136 {"xvnmsubasp", XX3(60,209), XX3_MASK
, PPCVSX
, PPCNONE
, {XT6
, XA6
, XB6
}},
6137 {"xvcvdpsxws", XX2(60,216), XX2_MASK
, PPCVSX
, PPCNONE
, {XT6
, XB6
}},
6138 {"xvnmsubmsp", XX3(60,217), XX3_MASK
, PPCVSX
, PPCNONE
, {XT6
, XA6
, XB6
}},
6139 {"xvrdpiz", XX2(60,217), XX2_MASK
, PPCVSX
, PPCNONE
, {XT6
, XB6
}},
6140 {"xvredp", XX2(60,218), XX2_MASK
, PPCVSX
, PPCNONE
, {XT6
, XB6
}},
6141 {"xvmaxdp", XX3(60,224), XX3_MASK
, PPCVSX
, PPCNONE
, {XT6
, XA6
, XB6
}},
6142 {"xvnmaddadp", XX3(60,225), XX3_MASK
, PPCVSX
, PPCNONE
, {XT6
, XA6
, XB6
}},
6143 {"xvmindp", XX3(60,232), XX3_MASK
, PPCVSX
, PPCNONE
, {XT6
, XA6
, XB6
}},
6144 {"xvnmaddmdp", XX3(60,233), XX3_MASK
, PPCVSX
, PPCNONE
, {XT6
, XA6
, XB6
}},
6145 {"xvcvuxwdp", XX2(60,232), XX2_MASK
, PPCVSX
, PPCNONE
, {XT6
, XB6
}},
6146 {"xvrdpip", XX2(60,233), XX2_MASK
, PPCVSX
, PPCNONE
, {XT6
, XB6
}},
6147 {"xvtsqrtdp", XX2(60,234), XX2BF_MASK
, PPCVSX
, PPCNONE
, {BF
, XB6
}},
6148 {"xvrdpic", XX2(60,235), XX2_MASK
, PPCVSX
, PPCNONE
, {XT6
, XB6
}},
6149 {"xvmovdp", XX3(60,240), XX3_MASK
, PPCVSX
, PPCNONE
, {XT6
, XA6
, XB6S
}},
6150 {"xvcpsgndp", XX3(60,240), XX3_MASK
, PPCVSX
, PPCNONE
, {XT6
, XA6
, XB6
}},
6151 {"xvnmsubadp", XX3(60,241), XX3_MASK
, PPCVSX
, PPCNONE
, {XT6
, XA6
, XB6
}},
6152 {"xvcvsxwdp", XX2(60,248), XX2_MASK
, PPCVSX
, PPCNONE
, {XT6
, XB6
}},
6153 {"xvnmsubmdp", XX3(60,249), XX3_MASK
, PPCVSX
, PPCNONE
, {XT6
, XA6
, XB6
}},
6154 {"xvrdpim", XX2(60,249), XX2_MASK
, PPCVSX
, PPCNONE
, {XT6
, XB6
}},
6155 {"xscvdpsp", XX2(60,265), XX2_MASK
, PPCVSX
, PPCNONE
, {XT6
, XB6
}},
6156 {"xscvdpspn", XX2(60,267), XX2_MASK
, PPCVSX2
, PPCNONE
, {XT6
, XB6
}},
6157 {"xsrsp", XX2(60,281), XX2_MASK
, PPCVSX2
, PPCNONE
, {XT6
, XB6
}},
6158 {"xscvuxdsp", XX2(60,296), XX2_MASK
, PPCVSX2
, PPCNONE
, {XT6
, XB6
}},
6159 {"xscvsxdsp", XX2(60,312), XX2_MASK
, PPCVSX2
, PPCNONE
, {XT6
, XB6
}},
6160 {"xscvdpuxds", XX2(60,328), XX2_MASK
, PPCVSX
, PPCNONE
, {XT6
, XB6
}},
6161 {"xscvspdp", XX2(60,329), XX2_MASK
, PPCVSX
, PPCNONE
, {XT6
, XB6
}},
6162 {"xscvspdpn", XX2(60,331), XX2_MASK
, PPCVSX2
, PPCNONE
, {XT6
, XB6
}},
6163 {"xscvdpsxds", XX2(60,344), XX2_MASK
, PPCVSX
, PPCNONE
, {XT6
, XB6
}},
6164 {"xsabsdp", XX2(60,345), XX2_MASK
, PPCVSX
, PPCNONE
, {XT6
, XB6
}},
6165 {"xscvuxddp", XX2(60,360), XX2_MASK
, PPCVSX
, PPCNONE
, {XT6
, XB6
}},
6166 {"xsnabsdp", XX2(60,361), XX2_MASK
, PPCVSX
, PPCNONE
, {XT6
, XB6
}},
6167 {"xscvsxddp", XX2(60,376), XX2_MASK
, PPCVSX
, PPCNONE
, {XT6
, XB6
}},
6168 {"xsnegdp", XX2(60,377), XX2_MASK
, PPCVSX
, PPCNONE
, {XT6
, XB6
}},
6169 {"xvcvspuxds", XX2(60,392), XX2_MASK
, PPCVSX
, PPCNONE
, {XT6
, XB6
}},
6170 {"xvcvdpsp", XX2(60,393), XX2_MASK
, PPCVSX
, PPCNONE
, {XT6
, XB6
}},
6171 {"xvcvspsxds", XX2(60,408), XX2_MASK
, PPCVSX
, PPCNONE
, {XT6
, XB6
}},
6172 {"xvabssp", XX2(60,409), XX2_MASK
, PPCVSX
, PPCNONE
, {XT6
, XB6
}},
6173 {"xvcvuxdsp", XX2(60,424), XX2_MASK
, PPCVSX
, PPCNONE
, {XT6
, XB6
}},
6174 {"xvnabssp", XX2(60,425), XX2_MASK
, PPCVSX
, PPCNONE
, {XT6
, XB6
}},
6175 {"xvcvsxdsp", XX2(60,440), XX2_MASK
, PPCVSX
, PPCNONE
, {XT6
, XB6
}},
6176 {"xvnegsp", XX2(60,441), XX2_MASK
, PPCVSX
, PPCNONE
, {XT6
, XB6
}},
6177 {"xvcvdpuxds", XX2(60,456), XX2_MASK
, PPCVSX
, PPCNONE
, {XT6
, XB6
}},
6178 {"xvcvspdp", XX2(60,457), XX2_MASK
, PPCVSX
, PPCNONE
, {XT6
, XB6
}},
6179 {"xvcvdpsxds", XX2(60,472), XX2_MASK
, PPCVSX
, PPCNONE
, {XT6
, XB6
}},
6180 {"xvabsdp", XX2(60,473), XX2_MASK
, PPCVSX
, PPCNONE
, {XT6
, XB6
}},
6181 {"xvcvuxddp", XX2(60,488), XX2_MASK
, PPCVSX
, PPCNONE
, {XT6
, XB6
}},
6182 {"xvnabsdp", XX2(60,489), XX2_MASK
, PPCVSX
, PPCNONE
, {XT6
, XB6
}},
6183 {"xvcvsxddp", XX2(60,504), XX2_MASK
, PPCVSX
, PPCNONE
, {XT6
, XB6
}},
6184 {"xvnegdp", XX2(60,505), XX2_MASK
, PPCVSX
, PPCNONE
, {XT6
, XB6
}},
6186 {"psq_st", OP(60), OP_MASK
, PPCPS
, PPCNONE
, {FRS
,PSD
,RA
,PSW
,PSQ
}},
6187 {"stfq", OP(60), OP_MASK
, POWER2
, PPCNONE
, {FRS
, D
, RA
}},
6189 {"stfdp", OP(61), OP_MASK
, POWER6
, POWER7
, {FRSp
, DS
, RA0
}},
6190 {"psq_stu", OP(61), OP_MASK
, PPCPS
, PPCNONE
, {FRS
,PSD
,RA
,PSW
,PSQ
}},
6191 {"stfqu", OP(61), OP_MASK
, POWER2
, PPCNONE
, {FRS
, D
, RA
}},
6193 {"std", DSO(62,0), DS_MASK
, PPC64
, PPCNONE
, {RS
, DS
, RA0
}},
6194 {"stdu", DSO(62,1), DS_MASK
, PPC64
, PPCNONE
, {RS
, DS
, RAS
}},
6195 {"stq", DSO(62,2), DS_MASK
, POWER4
, PPC476
, {RSQ
, DS
, RA0
}},
6197 {"fcmpu", X(63,0), X_MASK
|(3<<21), COM
, PPCEFS
, {BF
, FRA
, FRB
}},
6199 {"daddq", XRC(63,2,0), X_MASK
, POWER6
, PPCNONE
, {FRTp
, FRAp
, FRBp
}},
6200 {"daddq.", XRC(63,2,1), X_MASK
, POWER6
, PPCNONE
, {FRTp
, FRAp
, FRBp
}},
6202 {"dquaq", ZRC(63,3,0), Z2_MASK
, POWER6
, PPCNONE
, {FRTp
, FRAp
, FRBp
, RMC
}},
6203 {"dquaq.", ZRC(63,3,1), Z2_MASK
, POWER6
, PPCNONE
, {FRTp
, FRAp
, FRBp
, RMC
}},
6205 {"fcpsgn", XRC(63,8,0), X_MASK
, POWER6
|PPCA2
|PPC476
, PPCNONE
, {FRT
, FRA
, FRB
}},
6206 {"fcpsgn.", XRC(63,8,1), X_MASK
, POWER6
|PPCA2
|PPC476
, PPCNONE
, {FRT
, FRA
, FRB
}},
6208 {"frsp", XRC(63,12,0), XRA_MASK
, COM
, PPCEFS
, {FRT
, FRB
}},
6209 {"frsp.", XRC(63,12,1), XRA_MASK
, COM
, PPCEFS
, {FRT
, FRB
}},
6211 {"fctiw", XRC(63,14,0), XRA_MASK
, PPCCOM
, PPCEFS
, {FRT
, FRB
}},
6212 {"fcir", XRC(63,14,0), XRA_MASK
, PWR2COM
, PPCNONE
, {FRT
, FRB
}},
6213 {"fctiw.", XRC(63,14,1), XRA_MASK
, PPCCOM
, PPCEFS
, {FRT
, FRB
}},
6214 {"fcir.", XRC(63,14,1), XRA_MASK
, PWR2COM
, PPCNONE
, {FRT
, FRB
}},
6216 {"fctiwz", XRC(63,15,0), XRA_MASK
, PPCCOM
, PPCEFS
, {FRT
, FRB
}},
6217 {"fcirz", XRC(63,15,0), XRA_MASK
, PWR2COM
, PPCNONE
, {FRT
, FRB
}},
6218 {"fctiwz.", XRC(63,15,1), XRA_MASK
, PPCCOM
, PPCEFS
, {FRT
, FRB
}},
6219 {"fcirz.", XRC(63,15,1), XRA_MASK
, PWR2COM
, PPCNONE
, {FRT
, FRB
}},
6221 {"fdiv", A(63,18,0), AFRC_MASK
, PPCCOM
, PPCEFS
, {FRT
, FRA
, FRB
}},
6222 {"fd", A(63,18,0), AFRC_MASK
, PWRCOM
, PPCNONE
, {FRT
, FRA
, FRB
}},
6223 {"fdiv.", A(63,18,1), AFRC_MASK
, PPCCOM
, PPCEFS
, {FRT
, FRA
, FRB
}},
6224 {"fd.", A(63,18,1), AFRC_MASK
, PWRCOM
, PPCNONE
, {FRT
, FRA
, FRB
}},
6226 {"fsub", A(63,20,0), AFRC_MASK
, PPCCOM
, PPCEFS
, {FRT
, FRA
, FRB
}},
6227 {"fs", A(63,20,0), AFRC_MASK
, PWRCOM
, PPCNONE
, {FRT
, FRA
, FRB
}},
6228 {"fsub.", A(63,20,1), AFRC_MASK
, PPCCOM
, PPCEFS
, {FRT
, FRA
, FRB
}},
6229 {"fs.", A(63,20,1), AFRC_MASK
, PWRCOM
, PPCNONE
, {FRT
, FRA
, FRB
}},
6231 {"fadd", A(63,21,0), AFRC_MASK
, PPCCOM
, PPCEFS
, {FRT
, FRA
, FRB
}},
6232 {"fa", A(63,21,0), AFRC_MASK
, PWRCOM
, PPCNONE
, {FRT
, FRA
, FRB
}},
6233 {"fadd.", A(63,21,1), AFRC_MASK
, PPCCOM
, PPCEFS
, {FRT
, FRA
, FRB
}},
6234 {"fa.", A(63,21,1), AFRC_MASK
, PWRCOM
, PPCNONE
, {FRT
, FRA
, FRB
}},
6236 {"fsqrt", A(63,22,0), AFRAFRC_MASK
, PPCPWR2
, TITAN
, {FRT
, FRB
}},
6237 {"fsqrt.", A(63,22,1), AFRAFRC_MASK
, PPCPWR2
, TITAN
, {FRT
, FRB
}},
6239 {"fsel", A(63,23,0), A_MASK
, PPC
, PPCEFS
, {FRT
, FRA
, FRC
, FRB
}},
6240 {"fsel.", A(63,23,1), A_MASK
, PPC
, PPCEFS
, {FRT
, FRA
, FRC
, FRB
}},
6242 {"fre", A(63,24,0), AFRAFRC_MASK
, POWER7
, PPCNONE
, {FRT
, FRB
}},
6243 {"fre", A(63,24,0), AFRALFRC_MASK
, POWER5
, POWER7
, {FRT
, FRB
, A_L
}},
6244 {"fre.", A(63,24,1), AFRAFRC_MASK
, POWER7
, PPCNONE
, {FRT
, FRB
}},
6245 {"fre.", A(63,24,1), AFRALFRC_MASK
, POWER5
, POWER7
, {FRT
, FRB
, A_L
}},
6247 {"fmul", A(63,25,0), AFRB_MASK
, PPCCOM
, PPCEFS
, {FRT
, FRA
, FRC
}},
6248 {"fm", A(63,25,0), AFRB_MASK
, PWRCOM
, PPCNONE
, {FRT
, FRA
, FRC
}},
6249 {"fmul.", A(63,25,1), AFRB_MASK
, PPCCOM
, PPCEFS
, {FRT
, FRA
, FRC
}},
6250 {"fm.", A(63,25,1), AFRB_MASK
, PWRCOM
, PPCNONE
, {FRT
, FRA
, FRC
}},
6252 {"frsqrte", A(63,26,0), AFRAFRC_MASK
, POWER7
, PPCNONE
, {FRT
, FRB
}},
6253 {"frsqrte", A(63,26,0), AFRALFRC_MASK
, PPC
, POWER7
, {FRT
, FRB
, A_L
}},
6254 {"frsqrte.", A(63,26,1), AFRAFRC_MASK
, POWER7
, PPCNONE
, {FRT
, FRB
}},
6255 {"frsqrte.", A(63,26,1), AFRALFRC_MASK
, PPC
, POWER7
, {FRT
, FRB
, A_L
}},
6257 {"fmsub", A(63,28,0), A_MASK
, PPCCOM
, PPCEFS
, {FRT
, FRA
, FRC
, FRB
}},
6258 {"fms", A(63,28,0), A_MASK
, PWRCOM
, PPCNONE
, {FRT
, FRA
, FRC
, FRB
}},
6259 {"fmsub.", A(63,28,1), A_MASK
, PPCCOM
, PPCEFS
, {FRT
, FRA
, FRC
, FRB
}},
6260 {"fms.", A(63,28,1), A_MASK
, PWRCOM
, PPCNONE
, {FRT
, FRA
, FRC
, FRB
}},
6262 {"fmadd", A(63,29,0), A_MASK
, PPCCOM
, PPCEFS
, {FRT
, FRA
, FRC
, FRB
}},
6263 {"fma", A(63,29,0), A_MASK
, PWRCOM
, PPCNONE
, {FRT
, FRA
, FRC
, FRB
}},
6264 {"fmadd.", A(63,29,1), A_MASK
, PPCCOM
, PPCEFS
, {FRT
, FRA
, FRC
, FRB
}},
6265 {"fma.", A(63,29,1), A_MASK
, PWRCOM
, PPCNONE
, {FRT
, FRA
, FRC
, FRB
}},
6267 {"fnmsub", A(63,30,0), A_MASK
, PPCCOM
, PPCEFS
, {FRT
, FRA
, FRC
, FRB
}},
6268 {"fnms", A(63,30,0), A_MASK
, PWRCOM
, PPCNONE
, {FRT
, FRA
, FRC
, FRB
}},
6269 {"fnmsub.", A(63,30,1), A_MASK
, PPCCOM
, PPCEFS
, {FRT
, FRA
, FRC
, FRB
}},
6270 {"fnms.", A(63,30,1), A_MASK
, PWRCOM
, PPCNONE
, {FRT
, FRA
, FRC
, FRB
}},
6272 {"fnmadd", A(63,31,0), A_MASK
, PPCCOM
, PPCEFS
, {FRT
, FRA
, FRC
, FRB
}},
6273 {"fnma", A(63,31,0), A_MASK
, PWRCOM
, PPCNONE
, {FRT
, FRA
, FRC
, FRB
}},
6274 {"fnmadd.", A(63,31,1), A_MASK
, PPCCOM
, PPCEFS
, {FRT
, FRA
, FRC
, FRB
}},
6275 {"fnma.", A(63,31,1), A_MASK
, PWRCOM
, PPCNONE
, {FRT
, FRA
, FRC
, FRB
}},
6277 {"fcmpo", X(63,32), X_MASK
|(3<<21), COM
, PPCEFS
, {BF
, FRA
, FRB
}},
6279 {"dmulq", XRC(63,34,0), X_MASK
, POWER6
, PPCNONE
, {FRTp
, FRAp
, FRBp
}},
6280 {"dmulq.", XRC(63,34,1), X_MASK
, POWER6
, PPCNONE
, {FRTp
, FRAp
, FRBp
}},
6282 {"drrndq", ZRC(63,35,0), Z2_MASK
, POWER6
, PPCNONE
, {FRTp
, FRA
, FRBp
, RMC
}},
6283 {"drrndq.", ZRC(63,35,1), Z2_MASK
, POWER6
, PPCNONE
, {FRTp
, FRA
, FRBp
, RMC
}},
6285 {"mtfsb1", XRC(63,38,0), XRARB_MASK
, COM
, PPCNONE
, {BT
}},
6286 {"mtfsb1.", XRC(63,38,1), XRARB_MASK
, COM
, PPCNONE
, {BT
}},
6288 {"fneg", XRC(63,40,0), XRA_MASK
, COM
, PPCEFS
, {FRT
, FRB
}},
6289 {"fneg.", XRC(63,40,1), XRA_MASK
, COM
, PPCEFS
, {FRT
, FRB
}},
6291 {"mcrfs", X(63,64), XRB_MASK
|(3<<21)|(3<<16), COM
, PPCNONE
, {BF
, BFA
}},
6293 {"dscliq", ZRC(63,66,0), Z_MASK
, POWER6
, PPCNONE
, {FRTp
, FRAp
, SH16
}},
6294 {"dscliq.", ZRC(63,66,1), Z_MASK
, POWER6
, PPCNONE
, {FRTp
, FRAp
, SH16
}},
6296 {"dquaiq", ZRC(63,67,0), Z2_MASK
, POWER6
, PPCNONE
, {TE
, FRTp
, FRBp
, RMC
}},
6297 {"dquaiq.", ZRC(63,67,1), Z2_MASK
, POWER6
, PPCNONE
, {TE
, FRTp
, FRBp
, RMC
}},
6299 {"mtfsb0", XRC(63,70,0), XRARB_MASK
, COM
, PPCNONE
, {BT
}},
6300 {"mtfsb0.", XRC(63,70,1), XRARB_MASK
, COM
, PPCNONE
, {BT
}},
6302 {"fmr", XRC(63,72,0), XRA_MASK
, COM
, PPCEFS
, {FRT
, FRB
}},
6303 {"fmr.", XRC(63,72,1), XRA_MASK
, COM
, PPCEFS
, {FRT
, FRB
}},
6305 {"dscriq", ZRC(63,98,0), Z_MASK
, POWER6
, PPCNONE
, {FRTp
, FRAp
, SH16
}},
6306 {"dscriq.", ZRC(63,98,1), Z_MASK
, POWER6
, PPCNONE
, {FRTp
, FRAp
, SH16
}},
6308 {"drintxq", ZRC(63,99,0), Z2_MASK
, POWER6
, PPCNONE
, {R
, FRTp
, FRBp
, RMC
}},
6309 {"drintxq.", ZRC(63,99,1), Z2_MASK
, POWER6
, PPCNONE
, {R
, FRTp
, FRBp
, RMC
}},
6311 {"ftdiv", X(63,128), X_MASK
|(3<<21), POWER7
, PPCNONE
, {BF
, FRA
, FRB
}},
6313 {"dcmpoq", X(63,130), X_MASK
, POWER6
, PPCNONE
, {BF
, FRAp
, FRBp
}},
6315 {"mtfsfi", XRC(63,134,0), XWRA_MASK
|(3<<21)|(1<<11), POWER6
|PPCA2
|PPC476
, PPCNONE
, {BFF
, U
, W
}},
6316 {"mtfsfi", XRC(63,134,0), XRA_MASK
|(3<<21)|(1<<11), COM
, POWER6
|PPCA2
|PPC476
, {BFF
, U
}},
6317 {"mtfsfi.", XRC(63,134,1), XWRA_MASK
|(3<<21)|(1<<11), POWER6
|PPCA2
|PPC476
, PPCNONE
, {BFF
, U
, W
}},
6318 {"mtfsfi.", XRC(63,134,1), XRA_MASK
|(3<<21)|(1<<11), COM
, POWER6
|PPCA2
|PPC476
, {BFF
, U
}},
6320 {"fnabs", XRC(63,136,0), XRA_MASK
, COM
, PPCEFS
, {FRT
, FRB
}},
6321 {"fnabs.", XRC(63,136,1), XRA_MASK
, COM
, PPCEFS
, {FRT
, FRB
}},
6323 {"fctiwu", XRC(63,142,0), XRA_MASK
, POWER7
, PPCNONE
, {FRT
, FRB
}},
6324 {"fctiwu.", XRC(63,142,1), XRA_MASK
, POWER7
, PPCNONE
, {FRT
, FRB
}},
6325 {"fctiwuz", XRC(63,143,0), XRA_MASK
, POWER7
, PPCNONE
, {FRT
, FRB
}},
6326 {"fctiwuz.", XRC(63,143,1), XRA_MASK
, POWER7
, PPCNONE
, {FRT
, FRB
}},
6328 {"ftsqrt", X(63,160), X_MASK
|(3<<21|FRA_MASK
), POWER7
, PPCNONE
, {BF
, FRB
}},
6330 {"dtstexq", X(63,162), X_MASK
, POWER6
, PPCNONE
, {BF
, FRAp
, FRBp
}},
6331 {"dtstdcq", Z(63,194), Z_MASK
, POWER6
, PPCNONE
, {BF
, FRAp
, DCM
}},
6332 {"dtstdgq", Z(63,226), Z_MASK
, POWER6
, PPCNONE
, {BF
, FRAp
, DGM
}},
6334 {"drintnq", ZRC(63,227,0), Z2_MASK
, POWER6
, PPCNONE
, {R
, FRTp
, FRBp
, RMC
}},
6335 {"drintnq.", ZRC(63,227,1), Z2_MASK
, POWER6
, PPCNONE
, {R
, FRTp
, FRBp
, RMC
}},
6337 {"dctqpq", XRC(63,258,0), X_MASK
, POWER6
, PPCNONE
, {FRTp
, FRB
}},
6338 {"dctqpq.", XRC(63,258,1), X_MASK
, POWER6
, PPCNONE
, {FRTp
, FRB
}},
6340 {"fabs", XRC(63,264,0), XRA_MASK
, COM
, PPCEFS
, {FRT
, FRB
}},
6341 {"fabs.", XRC(63,264,1), XRA_MASK
, COM
, PPCEFS
, {FRT
, FRB
}},
6343 {"dctfixq", XRC(63,290,0), X_MASK
, POWER6
, PPCNONE
, {FRT
, FRBp
}},
6344 {"dctfixq.", XRC(63,290,1), X_MASK
, POWER6
, PPCNONE
, {FRT
, FRBp
}},
6346 {"ddedpdq", XRC(63,322,0), X_MASK
, POWER6
, PPCNONE
, {SP
, FRTp
, FRBp
}},
6347 {"ddedpdq.", XRC(63,322,1), X_MASK
, POWER6
, PPCNONE
, {SP
, FRTp
, FRBp
}},
6349 {"dxexq", XRC(63,354,0), X_MASK
, POWER6
, PPCNONE
, {FRT
, FRBp
}},
6350 {"dxexq.", XRC(63,354,1), X_MASK
, POWER6
, PPCNONE
, {FRT
, FRBp
}},
6352 {"frin", XRC(63,392,0), XRA_MASK
, POWER5
, PPCNONE
, {FRT
, FRB
}},
6353 {"frin.", XRC(63,392,1), XRA_MASK
, POWER5
, PPCNONE
, {FRT
, FRB
}},
6354 {"friz", XRC(63,424,0), XRA_MASK
, POWER5
, PPCNONE
, {FRT
, FRB
}},
6355 {"friz.", XRC(63,424,1), XRA_MASK
, POWER5
, PPCNONE
, {FRT
, FRB
}},
6356 {"frip", XRC(63,456,0), XRA_MASK
, POWER5
, PPCNONE
, {FRT
, FRB
}},
6357 {"frip.", XRC(63,456,1), XRA_MASK
, POWER5
, PPCNONE
, {FRT
, FRB
}},
6358 {"frim", XRC(63,488,0), XRA_MASK
, POWER5
, PPCNONE
, {FRT
, FRB
}},
6359 {"frim.", XRC(63,488,1), XRA_MASK
, POWER5
, PPCNONE
, {FRT
, FRB
}},
6361 {"dsubq", XRC(63,514,0), X_MASK
, POWER6
, PPCNONE
, {FRTp
, FRAp
, FRBp
}},
6362 {"dsubq.", XRC(63,514,1), X_MASK
, POWER6
, PPCNONE
, {FRTp
, FRAp
, FRBp
}},
6364 {"ddivq", XRC(63,546,0), X_MASK
, POWER6
, PPCNONE
, {FRTp
, FRAp
, FRBp
}},
6365 {"ddivq.", XRC(63,546,1), X_MASK
, POWER6
, PPCNONE
, {FRTp
, FRAp
, FRBp
}},
6367 {"mffs", XRC(63,583,0), XRARB_MASK
, COM
, PPCEFS
, {FRT
}},
6368 {"mffs.", XRC(63,583,1), XRARB_MASK
, COM
, PPCEFS
, {FRT
}},
6370 {"dcmpuq", X(63,642), X_MASK
, POWER6
, PPCNONE
, {BF
, FRAp
, FRBp
}},
6372 {"dtstsfq", X(63,674), X_MASK
, POWER6
, PPCNONE
, {BF
, FRA
, FRBp
}},
6374 {"mtfsf", XFL(63,711,0), XFL_MASK
, POWER6
|PPCA2
|PPC476
, PPCNONE
, {FLM
, FRB
, XFL_L
, W
}},
6375 {"mtfsf", XFL(63,711,0), XFL_MASK
, COM
, POWER6
|PPCA2
|PPC476
|PPCEFS
, {FLM
, FRB
}},
6376 {"mtfsf.", XFL(63,711,1), XFL_MASK
, POWER6
|PPCA2
|PPC476
, PPCNONE
, {FLM
, FRB
, XFL_L
, W
}},
6377 {"mtfsf.", XFL(63,711,1), XFL_MASK
, COM
, POWER6
|PPCA2
|PPC476
|PPCEFS
, {FLM
, FRB
}},
6379 {"drdpq", XRC(63,770,0), X_MASK
, POWER6
, PPCNONE
, {FRTp
, FRBp
}},
6380 {"drdpq.", XRC(63,770,1), X_MASK
, POWER6
, PPCNONE
, {FRTp
, FRBp
}},
6382 {"dcffixq", XRC(63,802,0), X_MASK
, POWER6
, PPCNONE
, {FRTp
, FRB
}},
6383 {"dcffixq.", XRC(63,802,1), X_MASK
, POWER6
, PPCNONE
, {FRTp
, FRB
}},
6385 {"fctid", XRC(63,814,0), XRA_MASK
, PPC64
, PPCNONE
, {FRT
, FRB
}},
6386 {"fctid", XRC(63,814,0), XRA_MASK
, PPC476
, PPCNONE
, {FRT
, FRB
}},
6387 {"fctid.", XRC(63,814,1), XRA_MASK
, PPC64
, PPCNONE
, {FRT
, FRB
}},
6388 {"fctid.", XRC(63,814,1), XRA_MASK
, PPC476
, PPCNONE
, {FRT
, FRB
}},
6390 {"fctidz", XRC(63,815,0), XRA_MASK
, PPC64
, PPCNONE
, {FRT
, FRB
}},
6391 {"fctidz", XRC(63,815,0), XRA_MASK
, PPC476
, PPCNONE
, {FRT
, FRB
}},
6392 {"fctidz.", XRC(63,815,1), XRA_MASK
, PPC64
, PPCNONE
, {FRT
, FRB
}},
6393 {"fctidz.", XRC(63,815,1), XRA_MASK
, PPC476
, PPCNONE
, {FRT
, FRB
}},
6395 {"denbcdq", XRC(63,834,0), X_MASK
, POWER6
, PPCNONE
, {S
, FRTp
, FRBp
}},
6396 {"denbcdq.", XRC(63,834,1), X_MASK
, POWER6
, PPCNONE
, {S
, FRTp
, FRBp
}},
6398 {"fmrgow", X(63,838), X_MASK
, PPCVSX2
, PPCNONE
, {FRT
, FRA
, FRB
}},
6400 {"fcfid", XRC(63,846,0), XRA_MASK
, PPC64
, PPCNONE
, {FRT
, FRB
}},
6401 {"fcfid", XRC(63,846,0), XRA_MASK
, PPC476
, PPCNONE
, {FRT
, FRB
}},
6402 {"fcfid.", XRC(63,846,1), XRA_MASK
, PPC64
, PPCNONE
, {FRT
, FRB
}},
6403 {"fcfid.", XRC(63,846,1), XRA_MASK
, PPC476
, PPCNONE
, {FRT
, FRB
}},
6405 {"diexq", XRC(63,866,0), X_MASK
, POWER6
, PPCNONE
, {FRTp
, FRA
, FRBp
}},
6406 {"diexq.", XRC(63,866,1), X_MASK
, POWER6
, PPCNONE
, {FRTp
, FRA
, FRBp
}},
6408 {"fctidu", XRC(63,942,0), XRA_MASK
, POWER7
|PPCA2
, PPCNONE
, {FRT
, FRB
}},
6409 {"fctidu.", XRC(63,942,1), XRA_MASK
, POWER7
|PPCA2
, PPCNONE
, {FRT
, FRB
}},
6411 {"fctiduz", XRC(63,943,0), XRA_MASK
, POWER7
|PPCA2
, PPCNONE
, {FRT
, FRB
}},
6412 {"fctiduz.", XRC(63,943,1), XRA_MASK
, POWER7
|PPCA2
, PPCNONE
, {FRT
, FRB
}},
6414 {"fmrgew", X(63,966), X_MASK
, PPCVSX2
, PPCNONE
, {FRT
, FRA
, FRB
}},
6416 {"fcfidu", XRC(63,974,0), XRA_MASK
, POWER7
|PPCA2
, PPCNONE
, {FRT
, FRB
}},
6417 {"fcfidu.", XRC(63,974,1), XRA_MASK
, POWER7
|PPCA2
, PPCNONE
, {FRT
, FRB
}},
6420 const int powerpc_num_opcodes
=
6421 sizeof (powerpc_opcodes
) / sizeof (powerpc_opcodes
[0]);
6423 /* The VLE opcode table.
6425 The format of this opcode table is the same as the main opcode table. */
6427 const struct powerpc_opcode vle_opcodes
[] = {
6429 {"se_illegal", C(0), C_MASK
, PPCVLE
, PPCNONE
, {}},
6430 {"se_isync", C(1), C_MASK
, PPCVLE
, PPCNONE
, {}},
6431 {"se_sc", C(2), C_MASK
, PPCVLE
, PPCNONE
, {}},
6432 {"se_blr", C_LK(2,0), C_LK_MASK
, PPCVLE
, PPCNONE
, {}},
6433 {"se_blrl", C_LK(2,1), C_LK_MASK
, PPCVLE
, PPCNONE
, {}},
6434 {"se_bctr", C_LK(3,0), C_LK_MASK
, PPCVLE
, PPCNONE
, {}},
6435 {"se_bctrl", C_LK(3,1), C_LK_MASK
, PPCVLE
, PPCNONE
, {}},
6436 {"se_rfi", C(8), C_MASK
, PPCVLE
, PPCNONE
, {}},
6437 {"se_rfci", C(9), C_MASK
, PPCVLE
, PPCNONE
, {}},
6438 {"se_rfdi", C(10), C_MASK
, PPCVLE
, PPCNONE
, {}},
6439 {"se_rfmci", C(11), C_MASK
, PPCVLE
, PPCNONE
, {}},
6440 {"se_not", SE_R(0,2), SE_R_MASK
, PPCVLE
, PPCNONE
, {RX
}},
6441 {"se_neg", SE_R(0,3), SE_R_MASK
, PPCVLE
, PPCNONE
, {RX
}},
6442 {"se_mflr", SE_R(0,8), SE_R_MASK
, PPCVLE
, PPCNONE
, {RX
}},
6443 {"se_mtlr", SE_R(0,9), SE_R_MASK
, PPCVLE
, PPCNONE
, {RX
}},
6444 {"se_mfctr", SE_R(0,10), SE_R_MASK
, PPCVLE
, PPCNONE
, {RX
}},
6445 {"se_mtctr", SE_R(0,11), SE_R_MASK
, PPCVLE
, PPCNONE
, {RX
}},
6446 {"se_extzb", SE_R(0,12), SE_R_MASK
, PPCVLE
, PPCNONE
, {RX
}},
6447 {"se_extsb", SE_R(0,13), SE_R_MASK
, PPCVLE
, PPCNONE
, {RX
}},
6448 {"se_extzh", SE_R(0,14), SE_R_MASK
, PPCVLE
, PPCNONE
, {RX
}},
6449 {"se_extsh", SE_R(0,15), SE_R_MASK
, PPCVLE
, PPCNONE
, {RX
}},
6450 {"se_mr", SE_RR(0,1), SE_RR_MASK
, PPCVLE
, PPCNONE
, {RX
, RY
}},
6451 {"se_mtar", SE_RR(0,2), SE_RR_MASK
, PPCVLE
, PPCNONE
, {ARX
, RY
}},
6452 {"se_mfar", SE_RR(0,3), SE_RR_MASK
, PPCVLE
, PPCNONE
, {RX
, ARY
}},
6453 {"se_add", SE_RR(1,0), SE_RR_MASK
, PPCVLE
, PPCNONE
, {RX
, RY
}},
6454 {"se_mullw", SE_RR(1,1), SE_RR_MASK
, PPCVLE
, PPCNONE
, {RX
, RY
}},
6455 {"se_sub", SE_RR(1,2), SE_RR_MASK
, PPCVLE
, PPCNONE
, {RX
, RY
}},
6456 {"se_subf", SE_RR(1,3), SE_RR_MASK
, PPCVLE
, PPCNONE
, {RX
, RY
}},
6457 {"se_cmp", SE_RR(3,0), SE_RR_MASK
, PPCVLE
, PPCNONE
, {RX
, RY
}},
6458 {"se_cmpl", SE_RR(3,1), SE_RR_MASK
, PPCVLE
, PPCNONE
, {RX
, RY
}},
6459 {"se_cmph", SE_RR(3,2), SE_RR_MASK
, PPCVLE
, PPCNONE
, {RX
, RY
}},
6460 {"se_cmphl", SE_RR(3,3), SE_RR_MASK
, PPCVLE
, PPCNONE
, {RX
, RY
}},
6462 {"e_cmpi", SCI8BF(6,0,21), SCI8BF_MASK
, PPCVLE
, PPCNONE
, {CRD32
, RA
, SCLSCI8
}},
6463 {"e_cmpli", SCI8BF(6,1,21), SCI8BF_MASK
, PPCVLE
, PPCNONE
, {CRD32
, RA
, SCLSCI8
}},
6464 {"e_addi", SCI8(6,16), SCI8_MASK
, PPCVLE
, PPCNONE
, {RT
, RA
, SCLSCI8
}},
6465 {"e_subi", SCI8(6,16), SCI8_MASK
, PPCVLE
, PPCNONE
, {RT
, RA
, SCLSCI8N
}},
6466 {"e_addi.", SCI8(6,17), SCI8_MASK
, PPCVLE
, PPCNONE
, {RT
, RA
, SCLSCI8
}},
6467 {"e_addic", SCI8(6,18), SCI8_MASK
, PPCVLE
, PPCNONE
, {RT
, RA
, SCLSCI8
}},
6468 {"e_subic", SCI8(6,18), SCI8_MASK
, PPCVLE
, PPCNONE
, {RT
, RA
, SCLSCI8N
}},
6469 {"e_addic.", SCI8(6,19), SCI8_MASK
, PPCVLE
, PPCNONE
, {RT
, RA
, SCLSCI8
}},
6470 {"e_subic.", SCI8(6,19), SCI8_MASK
, PPCVLE
, PPCNONE
, {RT
, RA
, SCLSCI8N
}},
6471 {"e_mulli", SCI8(6,20), SCI8_MASK
, PPCVLE
, PPCNONE
, {RT
, RA
, SCLSCI8
}},
6472 {"e_subfic", SCI8(6,22), SCI8_MASK
, PPCVLE
, PPCNONE
, {RT
, RA
, SCLSCI8
}},
6473 {"e_subfic.", SCI8(6,23), SCI8_MASK
, PPCVLE
, PPCNONE
, {RT
, RA
, SCLSCI8
}},
6474 {"e_andi", SCI8(6,24), SCI8_MASK
, PPCVLE
, PPCNONE
, {RA
, RS
, SCLSCI8
}},
6475 {"e_andi.", SCI8(6,25), SCI8_MASK
, PPCVLE
, PPCNONE
, {RA
, RS
, SCLSCI8
}},
6476 {"e_nop", SCI8(6,26), 0xffffffff, PPCVLE
, PPCNONE
, {0}},
6477 {"e_ori", SCI8(6,26), SCI8_MASK
, PPCVLE
, PPCNONE
, {RA
, RS
, SCLSCI8
}},
6478 {"e_ori.", SCI8(6,27), SCI8_MASK
, PPCVLE
, PPCNONE
, {RA
, RS
, SCLSCI8
}},
6479 {"e_xori", SCI8(6,28), SCI8_MASK
, PPCVLE
, PPCNONE
, {RA
, RS
, SCLSCI8
}},
6480 {"e_xori.", SCI8(6,29), SCI8_MASK
, PPCVLE
, PPCNONE
, {RA
, RS
, SCLSCI8
}},
6481 {"e_lbzu", OPVUP(6,0), OPVUP_MASK
, PPCVLE
, PPCNONE
, {RT
, D8
, RA0
}},
6482 {"e_lhau", OPVUP(6,3), OPVUP_MASK
, PPCVLE
, PPCNONE
, {RT
, D8
, RA0
}},
6483 {"e_lhzu", OPVUP(6,1), OPVUP_MASK
, PPCVLE
, PPCNONE
, {RT
, D8
, RA0
}},
6484 {"e_lmw", OPVUP(6,8), OPVUP_MASK
, PPCVLE
, PPCNONE
, {RT
, D8
, RA0
}},
6485 {"e_lwzu", OPVUP(6,2), OPVUP_MASK
, PPCVLE
, PPCNONE
, {RT
, D8
, RA0
}},
6486 {"e_stbu", OPVUP(6,4), OPVUP_MASK
, PPCVLE
, PPCNONE
, {RT
, D8
, RA0
}},
6487 {"e_sthu", OPVUP(6,5), OPVUP_MASK
, PPCVLE
, PPCNONE
, {RT
, D8
, RA0
}},
6488 {"e_stwu", OPVUP(6,6), OPVUP_MASK
, PPCVLE
, PPCNONE
, {RT
, D8
, RA0
}},
6489 {"e_stmw", OPVUP(6,9), OPVUP_MASK
, PPCVLE
, PPCNONE
, {RT
, D8
, RA0
}},
6490 {"e_add16i", OP(7), OP_MASK
, PPCVLE
, PPCNONE
, {RT
, RA
, SI
}},
6491 {"e_la", OP(7), OP_MASK
, PPCVLE
, PPCNONE
, {RT
, D
, RA0
}},
6492 {"e_sub16i", OP(7), OP_MASK
, PPCVLE
, PPCNONE
, {RT
, RA
, NSI
}},
6494 {"se_addi", SE_IM5(8,0), SE_IM5_MASK
, PPCVLE
, PPCNONE
, {RX
, OIMM5
}},
6495 {"se_cmpli", SE_IM5(8,1), SE_IM5_MASK
, PPCVLE
, PPCNONE
, {RX
, OIMM5
}},
6496 {"se_subi", SE_IM5(9,0), SE_IM5_MASK
, PPCVLE
, PPCNONE
, {RX
, OIMM5
}},
6497 {"se_subi.", SE_IM5(9,1), SE_IM5_MASK
, PPCVLE
, PPCNONE
, {RX
, OIMM5
}},
6498 {"se_cmpi", SE_IM5(10,1), SE_IM5_MASK
, PPCVLE
, PPCNONE
, {RX
, UI5
}},
6499 {"se_bmaski", SE_IM5(11,0), SE_IM5_MASK
, PPCVLE
, PPCNONE
, {RX
, UI5
}},
6500 {"se_andi", SE_IM5(11,1), SE_IM5_MASK
, PPCVLE
, PPCNONE
, {RX
, UI5
}},
6502 {"e_lbz", OP(12), OP_MASK
, PPCVLE
, PPCNONE
, {RT
, D
, RA0
}},
6503 {"e_stb", OP(13), OP_MASK
, PPCVLE
, PPCNONE
, {RT
, D
, RA0
}},
6504 {"e_lha", OP(14), OP_MASK
, PPCVLE
, PPCNONE
, {RT
, D
, RA0
}},
6506 {"se_srw", SE_RR(16,0), SE_RR_MASK
, PPCVLE
, PPCNONE
, {RX
, RY
}},
6507 {"se_sraw", SE_RR(16,1), SE_RR_MASK
, PPCVLE
, PPCNONE
, {RX
, RY
}},
6508 {"se_slw", SE_RR(16,2), SE_RR_MASK
, PPCVLE
, PPCNONE
, {RX
, RY
}},
6509 {"se_nop", SE_RR(17,0), 0xffff, PPCVLE
, PPCNONE
, {0}},
6510 {"se_or", SE_RR(17,0), SE_RR_MASK
, PPCVLE
, PPCNONE
, {RX
, RY
}},
6511 {"se_andc", SE_RR(17,1), SE_RR_MASK
, PPCVLE
, PPCNONE
, {RX
, RY
}},
6512 {"se_and", SE_RR(17,2), SE_RR_MASK
, PPCVLE
, PPCNONE
, {RX
, RY
}},
6513 {"se_and.", SE_RR(17,3), SE_RR_MASK
, PPCVLE
, PPCNONE
, {RX
, RY
}},
6514 {"se_li", IM7(9), IM7_MASK
, PPCVLE
, PPCNONE
, {RX
, UI7
}},
6516 {"e_lwz", OP(20), OP_MASK
, PPCVLE
, PPCNONE
, {RT
, D
, RA0
}},
6517 {"e_stw", OP(21), OP_MASK
, PPCVLE
, PPCNONE
, {RT
, D
, RA0
}},
6518 {"e_lhz", OP(22), OP_MASK
, PPCVLE
, PPCNONE
, {RT
, D
, RA0
}},
6519 {"e_sth", OP(23), OP_MASK
, PPCVLE
, PPCNONE
, {RT
, D
, RA0
}},
6521 {"se_bclri", SE_IM5(24,0), SE_IM5_MASK
, PPCVLE
, PPCNONE
, {RX
, UI5
}},
6522 {"se_bgeni", SE_IM5(24,1), SE_IM5_MASK
, PPCVLE
, PPCNONE
, {RX
, UI5
}},
6523 {"se_bseti", SE_IM5(25,0), SE_IM5_MASK
, PPCVLE
, PPCNONE
, {RX
, UI5
}},
6524 {"se_btsti", SE_IM5(25,1), SE_IM5_MASK
, PPCVLE
, PPCNONE
, {RX
, UI5
}},
6525 {"se_srwi", SE_IM5(26,0), SE_IM5_MASK
, PPCVLE
, PPCNONE
, {RX
, UI5
}},
6526 {"se_srawi", SE_IM5(26,1), SE_IM5_MASK
, PPCVLE
, PPCNONE
, {RX
, UI5
}},
6527 {"se_slwi", SE_IM5(27,0), SE_IM5_MASK
, PPCVLE
, PPCNONE
, {RX
, UI5
}},
6529 {"e_lis", I16L(28,28), I16L_MASK
, PPCVLE
, PPCNONE
, {RD
, VLEUIMML
}},
6530 {"e_and2is.", I16L(28,29), I16L_MASK
, PPCVLE
, PPCNONE
, {RD
, VLEUIMML
}},
6531 {"e_or2is", I16L(28,26), I16L_MASK
, PPCVLE
, PPCNONE
, {RD
, VLEUIMML
}},
6532 {"e_and2i.", I16L(28,25), I16L_MASK
, PPCVLE
, PPCNONE
, {RD
, VLEUIMML
}},
6533 {"e_or2i", I16L(28,24), I16L_MASK
, PPCVLE
, PPCNONE
, {RD
, VLEUIMML
}},
6534 {"e_cmphl16i", IA16(28,23), IA16_MASK
, PPCVLE
, PPCNONE
, {RA
, VLEUIMM
}},
6535 {"e_cmph16i", IA16(28,22), IA16_MASK
, PPCVLE
, PPCNONE
, {RA
, VLESIMM
}},
6536 {"e_cmpl16i", I16A(28,21), I16A_MASK
, PPCVLE
, PPCNONE
, {RA
, VLEUIMM
}},
6537 {"e_cmplwi", I16A(28,21), I16A_MASK
, PPCVLE
, PPCNONE
, {RA
, VLESIMM
}},
6538 {"e_mull2i", I16A(28,20), I16A_MASK
, PPCVLE
, PPCNONE
, {RA
, VLESIMM
}},
6539 {"e_cmp16i", IA16(28,19), IA16_MASK
, PPCVLE
, PPCNONE
, {RA
, VLESIMM
}},
6540 {"e_cmpwi", IA16(28,19), IA16_MASK
, PPCVLE
, PPCNONE
, {RA
, VLESIMM
}},
6541 {"e_sub2is", I16A(28,18), I16A_MASK
, PPCVLE
, PPCNONE
, {RA
, VLENSIMM
}},
6542 {"e_add2is", I16A(28,18), I16A_MASK
, PPCVLE
, PPCNONE
, {RA
, VLESIMM
}},
6543 {"e_sub2i.", I16A(28,17), I16A_MASK
, PPCVLE
, PPCNONE
, {RA
, VLENSIMM
}},
6544 {"e_add2i.", I16A(28,17), I16A_MASK
, PPCVLE
, PPCNONE
, {RA
, VLESIMM
}},
6545 {"e_li", LI20(28,0), LI20_MASK
, PPCVLE
, PPCNONE
, {RT
, IMM20
}},
6546 {"e_rlwimi", M(29,0), M_MASK
, PPCVLE
, PPCNONE
, {RA
, RS
, SH
, MB
, ME
}},
6547 {"e_rlwinm", M(29,1), M_MASK
, PPCVLE
, PPCNONE
, {RA
, RT
, SH
, MBE
, ME
}},
6548 {"e_b", BD24(30,0,0), BD24_MASK
, PPCVLE
, PPCNONE
, {B24
}},
6549 {"e_bl", BD24(30,0,1), BD24_MASK
, PPCVLE
, PPCNONE
, {B24
}},
6550 {"e_bdnz", EBD15(30,8,BO32DNZ
,0), EBD15_MASK
, PPCVLE
, PPCNONE
, {B15
}},
6551 {"e_bdnzl", EBD15(30,8,BO32DNZ
,1), EBD15_MASK
, PPCVLE
, PPCNONE
, {B15
}},
6552 {"e_bdz", EBD15(30,8,BO32DZ
,0), EBD15_MASK
, PPCVLE
, PPCNONE
, {B15
}},
6553 {"e_bdzl", EBD15(30,8,BO32DZ
,1), EBD15_MASK
, PPCVLE
, PPCNONE
, {B15
}},
6554 {"e_bge", EBD15BI(30,8,BO32F
,CBLT
,0), EBD15BI_MASK
, PPCVLE
, PPCNONE
, {CRS
,B15
}},
6555 {"e_bgel", EBD15BI(30,8,BO32F
,CBLT
,1), EBD15BI_MASK
, PPCVLE
, PPCNONE
, {CRS
,B15
}},
6556 {"e_bnl", EBD15BI(30,8,BO32F
,CBLT
,0), EBD15BI_MASK
, PPCVLE
, PPCNONE
, {CRS
,B15
}},
6557 {"e_bnll", EBD15BI(30,8,BO32F
,CBLT
,1), EBD15BI_MASK
, PPCVLE
, PPCNONE
, {CRS
,B15
}},
6558 {"e_blt", EBD15BI(30,8,BO32T
,CBLT
,0), EBD15BI_MASK
, PPCVLE
, PPCNONE
, {CRS
,B15
}},
6559 {"e_bltl", EBD15BI(30,8,BO32T
,CBLT
,1), EBD15BI_MASK
, PPCVLE
, PPCNONE
, {CRS
,B15
}},
6560 {"e_bgt", EBD15BI(30,8,BO32T
,CBGT
,0), EBD15BI_MASK
, PPCVLE
, PPCNONE
, {CRS
,B15
}},
6561 {"e_bgtl", EBD15BI(30,8,BO32T
,CBGT
,1), EBD15BI_MASK
, PPCVLE
, PPCNONE
, {CRS
,B15
}},
6562 {"e_ble", EBD15BI(30,8,BO32F
,CBGT
,0), EBD15BI_MASK
, PPCVLE
, PPCNONE
, {CRS
,B15
}},
6563 {"e_blel", EBD15BI(30,8,BO32F
,CBGT
,1), EBD15BI_MASK
, PPCVLE
, PPCNONE
, {CRS
,B15
}},
6564 {"e_bng", EBD15BI(30,8,BO32F
,CBGT
,0), EBD15BI_MASK
, PPCVLE
, PPCNONE
, {CRS
,B15
}},
6565 {"e_bngl", EBD15BI(30,8,BO32F
,CBGT
,1), EBD15BI_MASK
, PPCVLE
, PPCNONE
, {CRS
,B15
}},
6566 {"e_bne", EBD15BI(30,8,BO32F
,CBEQ
,0), EBD15BI_MASK
, PPCVLE
, PPCNONE
, {CRS
,B15
}},
6567 {"e_bnel", EBD15BI(30,8,BO32F
,CBEQ
,1), EBD15BI_MASK
, PPCVLE
, PPCNONE
, {CRS
,B15
}},
6568 {"e_beq", EBD15BI(30,8,BO32T
,CBEQ
,0), EBD15BI_MASK
, PPCVLE
, PPCNONE
, {CRS
,B15
}},
6569 {"e_beql", EBD15BI(30,8,BO32T
,CBEQ
,1), EBD15BI_MASK
, PPCVLE
, PPCNONE
, {CRS
,B15
}},
6570 {"e_bso", EBD15BI(30,8,BO32T
,CBSO
,0), EBD15BI_MASK
, PPCVLE
, PPCNONE
, {CRS
,B15
}},
6571 {"e_bsol", EBD15BI(30,8,BO32T
,CBSO
,1), EBD15BI_MASK
, PPCVLE
, PPCNONE
, {CRS
,B15
}},
6572 {"e_bun", EBD15BI(30,8,BO32T
,CBSO
,0), EBD15BI_MASK
, PPCVLE
, PPCNONE
, {CRS
,B15
}},
6573 {"e_bunl", EBD15BI(30,8,BO32T
,CBSO
,1), EBD15BI_MASK
, PPCVLE
, PPCNONE
, {CRS
,B15
}},
6574 {"e_bns", EBD15BI(30,8,BO32F
,CBSO
,0), EBD15BI_MASK
, PPCVLE
, PPCNONE
, {CRS
,B15
}},
6575 {"e_bnsl", EBD15BI(30,8,BO32F
,CBSO
,1), EBD15BI_MASK
, PPCVLE
, PPCNONE
, {CRS
,B15
}},
6576 {"e_bnu", EBD15BI(30,8,BO32F
,CBSO
,0), EBD15BI_MASK
, PPCVLE
, PPCNONE
, {CRS
,B15
}},
6577 {"e_bnul", EBD15BI(30,8,BO32F
,CBSO
,1), EBD15BI_MASK
, PPCVLE
, PPCNONE
, {CRS
,B15
}},
6578 {"e_bc", BD15(30,8,0), BD15_MASK
, PPCVLE
, PPCNONE
, {BO32
, BI32
, B15
}},
6579 {"e_bcl", BD15(30,8,1), BD15_MASK
, PPCVLE
, PPCNONE
, {BO32
, BI32
, B15
}},
6581 {"e_bf", EBD15(30,8,BO32F
,0), EBD15_MASK
, PPCVLE
, PPCNONE
, {BI32
,B15
}},
6582 {"e_bfl", EBD15(30,8,BO32F
,1), EBD15_MASK
, PPCVLE
, PPCNONE
, {BI32
,B15
}},
6583 {"e_bt", EBD15(30,8,BO32T
,0), EBD15_MASK
, PPCVLE
, PPCNONE
, {BI32
,B15
}},
6584 {"e_btl", EBD15(30,8,BO32T
,1), EBD15_MASK
, PPCVLE
, PPCNONE
, {BI32
,B15
}},
6586 {"e_cmph", X(31,14), X_MASK
, PPCVLE
, PPCNONE
, {CRD
, RA
, RB
}},
6587 {"e_cmphl", X(31,46), X_MASK
, PPCVLE
, PPCNONE
, {CRD
, RA
, RB
}},
6588 {"e_crandc", XL(31,129), XL_MASK
, PPCVLE
, PPCNONE
, {BT
, BA
, BB
}},
6589 {"e_crnand", XL(31,225), XL_MASK
, PPCVLE
, PPCNONE
, {BT
, BA
, BB
}},
6590 {"e_crnot", XL(31,33), XL_MASK
, PPCVLE
, PPCNONE
, {BT
, BA
, BBA
}},
6591 {"e_crnor", XL(31,33), XL_MASK
, PPCVLE
, PPCNONE
, {BT
, BA
, BB
}},
6592 {"e_crclr", XL(31,193), XL_MASK
, PPCVLE
, PPCNONE
, {BT
, BAT
, BBA
}},
6593 {"e_crxor", XL(31,193), XL_MASK
, PPCVLE
, PPCNONE
, {BT
, BA
, BB
}},
6594 {"e_mcrf", XL(31,16), XL_MASK
, PPCVLE
, PPCNONE
, {CRD
, CR
}},
6595 {"e_slwi", EX(31,112), EX_MASK
, PPCVLE
, PPCNONE
, {RA
, RS
, SH
}},
6596 {"e_slwi.", EX(31,113), EX_MASK
, PPCVLE
, PPCNONE
, {RA
, RS
, SH
}},
6598 {"e_crand", XL(31,257), XL_MASK
, PPCVLE
, PPCNONE
, {BT
, BA
, BB
}},
6600 {"e_rlw", EX(31,560), EX_MASK
, PPCVLE
, PPCNONE
, {RA
, RS
, RB
}},
6601 {"e_rlw.", EX(31,561), EX_MASK
, PPCVLE
, PPCNONE
, {RA
, RS
, RB
}},
6603 {"e_crset", XL(31,289), XL_MASK
, PPCVLE
, PPCNONE
, {BT
, BAT
, BBA
}},
6604 {"e_creqv", XL(31,289), XL_MASK
, PPCVLE
, PPCNONE
, {BT
, BA
, BB
}},
6606 {"e_rlwi", EX(31,624), EX_MASK
, PPCVLE
, PPCNONE
, {RA
, RS
, SH
}},
6607 {"e_rlwi.", EX(31,625), EX_MASK
, PPCVLE
, PPCNONE
, {RA
, RS
, SH
}},
6609 {"e_crorc", XL(31,417), XL_MASK
, PPCVLE
, PPCNONE
, {BT
, BA
, BB
}},
6611 {"e_crmove", XL(31,449), XL_MASK
, PPCVLE
, PPCNONE
, {BT
, BA
, BBA
}},
6612 {"e_cror", XL(31,449), XL_MASK
, PPCVLE
, PPCNONE
, {BT
, BA
, BB
}},
6614 {"mtmas1", XSPR(31,467,625), XSPR_MASK
, PPCVLE
, PPCNONE
, {RS
}},
6616 {"e_srwi", EX(31,1136), EX_MASK
, PPCVLE
, PPCNONE
, {RA
, RS
, SH
}},
6617 {"e_srwi.", EX(31,1137), EX_MASK
, PPCVLE
, PPCNONE
, {RA
, RS
, SH
}},
6619 {"se_lbz", SD4(8), SD4_MASK
, PPCVLE
, PPCNONE
, {RZ
, SE_SD
, RX
}},
6621 {"se_stb", SD4(9), SD4_MASK
, PPCVLE
, PPCNONE
, {RZ
, SE_SD
, RX
}},
6623 {"se_lhz", SD4(10), SD4_MASK
, PPCVLE
, PPCNONE
, {RZ
, SE_SDH
, RX
}},
6625 {"se_sth", SD4(11), SD4_MASK
, PPCVLE
, PPCNONE
, {RZ
, SE_SDH
, RX
}},
6627 {"se_lwz", SD4(12), SD4_MASK
, PPCVLE
, PPCNONE
, {RZ
, SE_SDW
, RX
}},
6629 {"se_stw", SD4(13), SD4_MASK
, PPCVLE
, PPCNONE
, {RZ
, SE_SDW
, RX
}},
6631 {"se_bge", EBD8IO(28,0,0), EBD8IO3_MASK
, PPCVLE
, PPCNONE
, {B8
}},
6632 {"se_bnl", EBD8IO(28,0,0), EBD8IO3_MASK
, PPCVLE
, PPCNONE
, {B8
}},
6633 {"se_ble", EBD8IO(28,0,1), EBD8IO3_MASK
, PPCVLE
, PPCNONE
, {B8
}},
6634 {"se_bng", EBD8IO(28,0,1), EBD8IO3_MASK
, PPCVLE
, PPCNONE
, {B8
}},
6635 {"se_bne", EBD8IO(28,0,2), EBD8IO3_MASK
, PPCVLE
, PPCNONE
, {B8
}},
6636 {"se_bns", EBD8IO(28,0,3), EBD8IO3_MASK
, PPCVLE
, PPCNONE
, {B8
}},
6637 {"se_bnu", EBD8IO(28,0,3), EBD8IO3_MASK
, PPCVLE
, PPCNONE
, {B8
}},
6638 {"se_bf", EBD8IO(28,0,0), EBD8IO2_MASK
, PPCVLE
, PPCNONE
, {BI16
, B8
}},
6639 {"se_blt", EBD8IO(28,1,0), EBD8IO3_MASK
, PPCVLE
, PPCNONE
, {B8
}},
6640 {"se_bgt", EBD8IO(28,1,1), EBD8IO3_MASK
, PPCVLE
, PPCNONE
, {B8
}},
6641 {"se_beq", EBD8IO(28,1,2), EBD8IO3_MASK
, PPCVLE
, PPCNONE
, {B8
}},
6642 {"se_bso", EBD8IO(28,1,3), EBD8IO3_MASK
, PPCVLE
, PPCNONE
, {B8
}},
6643 {"se_bun", EBD8IO(28,1,3), EBD8IO3_MASK
, PPCVLE
, PPCNONE
, {B8
}},
6644 {"se_bt", EBD8IO(28,1,0), EBD8IO2_MASK
, PPCVLE
, PPCNONE
, {BI16
, B8
}},
6645 {"se_bc", BD8IO(28), BD8IO_MASK
, PPCVLE
, PPCNONE
, {BO16
, BI16
, B8
}},
6646 {"se_b", BD8(58,0,0), BD8_MASK
, PPCVLE
, PPCNONE
, {B8
}},
6647 {"se_bl", BD8(58,0,1), BD8_MASK
, PPCVLE
, PPCNONE
, {B8
}},
6650 const int vle_num_opcodes
=
6651 sizeof (vle_opcodes
) / sizeof (vle_opcodes
[0]);
6653 /* The macro table. This is only used by the assembler. */
6655 /* The expressions of the form (-x ! 31) & (x | 31) have the value 0
6656 when x=0; 32-x when x is between 1 and 31; are negative if x is
6657 negative; and are 32 or more otherwise. This is what you want
6658 when, for instance, you are emulating a right shift by a
6659 rotate-left-and-mask, because the underlying instructions support
6660 shifts of size 0 but not shifts of size 32. By comparison, when
6661 extracting x bits from some word you want to use just 32-x, because
6662 the underlying instructions don't support extracting 0 bits but do
6663 support extracting the whole word (32 bits in this case). */
6665 const struct powerpc_macro powerpc_macros
[] = {
6666 {"extldi", 4, PPC64
, "rldicr %0,%1,%3,(%2)-1"},
6667 {"extldi.", 4, PPC64
, "rldicr. %0,%1,%3,(%2)-1"},
6668 {"extrdi", 4, PPC64
, "rldicl %0,%1,((%2)+(%3))&((%2)+(%3)<>64),64-(%2)"},
6669 {"extrdi.", 4, PPC64
, "rldicl. %0,%1,((%2)+(%3))&((%2)+(%3)<>64),64-(%2)"},
6670 {"insrdi", 4, PPC64
, "rldimi %0,%1,64-((%2)+(%3)),%3"},
6671 {"insrdi.", 4, PPC64
, "rldimi. %0,%1,64-((%2)+(%3)),%3"},
6672 {"rotrdi", 3, PPC64
, "rldicl %0,%1,(-(%2)!63)&((%2)|63),0"},
6673 {"rotrdi.", 3, PPC64
, "rldicl. %0,%1,(-(%2)!63)&((%2)|63),0"},
6674 {"sldi", 3, PPC64
, "rldicr %0,%1,%2,63-(%2)"},
6675 {"sldi.", 3, PPC64
, "rldicr. %0,%1,%2,63-(%2)"},
6676 {"srdi", 3, PPC64
, "rldicl %0,%1,(-(%2)!63)&((%2)|63),%2"},
6677 {"srdi.", 3, PPC64
, "rldicl. %0,%1,(-(%2)!63)&((%2)|63),%2"},
6678 {"clrrdi", 3, PPC64
, "rldicr %0,%1,0,63-(%2)"},
6679 {"clrrdi.", 3, PPC64
, "rldicr. %0,%1,0,63-(%2)"},
6680 {"clrlsldi", 4, PPC64
, "rldic %0,%1,%3,(%2)-(%3)"},
6681 {"clrlsldi.",4, PPC64
, "rldic. %0,%1,%3,(%2)-(%3)"},
6683 {"extlwi", 4, PPCCOM
, "rlwinm %0,%1,%3,0,(%2)-1"},
6684 {"extlwi.", 4, PPCCOM
, "rlwinm. %0,%1,%3,0,(%2)-1"},
6685 {"extrwi", 4, PPCCOM
, "rlwinm %0,%1,((%2)+(%3))&((%2)+(%3)<>32),32-(%2),31"},
6686 {"extrwi.", 4, PPCCOM
, "rlwinm. %0,%1,((%2)+(%3))&((%2)+(%3)<>32),32-(%2),31"},
6687 {"inslwi", 4, PPCCOM
, "rlwimi %0,%1,(-(%3)!31)&((%3)|31),%3,(%2)+(%3)-1"},
6688 {"inslwi.", 4, PPCCOM
, "rlwimi. %0,%1,(-(%3)!31)&((%3)|31),%3,(%2)+(%3)-1"},
6689 {"insrwi", 4, PPCCOM
, "rlwimi %0,%1,32-((%2)+(%3)),%3,(%2)+(%3)-1"},
6690 {"insrwi.", 4, PPCCOM
, "rlwimi. %0,%1,32-((%2)+(%3)),%3,(%2)+(%3)-1"},
6691 {"rotrwi", 3, PPCCOM
, "rlwinm %0,%1,(-(%2)!31)&((%2)|31),0,31"},
6692 {"rotrwi.", 3, PPCCOM
, "rlwinm. %0,%1,(-(%2)!31)&((%2)|31),0,31"},
6693 {"slwi", 3, PPCCOM
, "rlwinm %0,%1,%2,0,31-(%2)"},
6694 {"sli", 3, PWRCOM
, "rlinm %0,%1,%2,0,31-(%2)"},
6695 {"slwi.", 3, PPCCOM
, "rlwinm. %0,%1,%2,0,31-(%2)"},
6696 {"sli.", 3, PWRCOM
, "rlinm. %0,%1,%2,0,31-(%2)"},
6697 {"srwi", 3, PPCCOM
, "rlwinm %0,%1,(-(%2)!31)&((%2)|31),%2,31"},
6698 {"sri", 3, PWRCOM
, "rlinm %0,%1,(-(%2)!31)&((%2)|31),%2,31"},
6699 {"srwi.", 3, PPCCOM
, "rlwinm. %0,%1,(-(%2)!31)&((%2)|31),%2,31"},
6700 {"sri.", 3, PWRCOM
, "rlinm. %0,%1,(-(%2)!31)&((%2)|31),%2,31"},
6701 {"clrrwi", 3, PPCCOM
, "rlwinm %0,%1,0,0,31-(%2)"},
6702 {"clrrwi.", 3, PPCCOM
, "rlwinm. %0,%1,0,0,31-(%2)"},
6703 {"clrlslwi", 4, PPCCOM
, "rlwinm %0,%1,%3,(%2)-(%3),31-(%3)"},
6704 {"clrlslwi.",4, PPCCOM
, "rlwinm. %0,%1,%3,(%2)-(%3),31-(%3)"},
6706 {"e_extlwi", 4, PPCVLE
, "e_rlwinm %0,%1,%3,0,(%2)-1"},
6707 {"e_extrwi", 4, PPCVLE
, "e_rlwinm %0,%1,((%2)+(%3))&((%2)+(%3)<>32),32-(%2),31"},
6708 {"e_inslwi", 4, PPCVLE
, "e_rlwimi %0,%1,(-(%3)!31)&((%3)|31),%3,(%2)+(%3)-1"},
6709 {"e_insrwi", 4, PPCVLE
, "e_rlwimi %0,%1,32-((%2)+(%3)),%3,(%2)+(%3)-1"},
6710 {"e_rotlwi", 3, PPCVLE
, "e_rlwinm %0,%1,%2,0,31"},
6711 {"e_rotrwi", 3, PPCVLE
, "e_rlwinm %0,%1,(-(%2)!31)&((%2)|31),0,31"},
6712 {"e_slwi", 3, PPCVLE
, "e_rlwinm %0,%1,%2,0,31-(%2)"},
6713 {"e_srwi", 3, PPCVLE
, "e_rlwinm %0,%1,(-(%2)!31)&((%2)|31),%2,31"},
6714 {"e_clrlwi", 3, PPCVLE
, "e_rlwinm %0,%1,0,%2,31"},
6715 {"e_clrrwi", 3, PPCVLE
, "e_rlwinm %0,%1,0,0,31-(%2)"},
6716 {"e_clrlslwi",4, PPCVLE
, "e_rlwinm %0,%1,%3,(%2)-(%3),31-(%3)"},
6719 const int powerpc_num_macros
=
6720 sizeof (powerpc_macros
) / sizeof (powerpc_macros
[0]);